Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 21
1 01:23:21.903460 lava-dispatcher, installed at version: 2023.06
2 01:23:21.903668 start: 0 validate
3 01:23:21.903805 Start time: 2023-08-28 01:23:21.903795+00:00 (UTC)
4 01:23:21.903942 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:23:21.904114 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 01:23:22.172412 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:23:22.172605 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:23:22.437688 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:23:22.437863 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:23:42.397922 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:23:42.398091 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:23:42.927300 validate duration: 21.02
14 01:23:42.927705 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:23:42.927868 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:23:42.928023 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:23:42.928206 Not decompressing ramdisk as can be used compressed.
18 01:23:42.928351 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 01:23:42.928470 saving as /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/ramdisk/rootfs.cpio.gz
20 01:23:42.928589 total size: 34390042 (32 MB)
21 01:23:46.888140 progress 0 % (0 MB)
22 01:23:46.897063 progress 5 % (1 MB)
23 01:23:46.905747 progress 10 % (3 MB)
24 01:23:46.914824 progress 15 % (4 MB)
25 01:23:46.923489 progress 20 % (6 MB)
26 01:23:46.932379 progress 25 % (8 MB)
27 01:23:46.941063 progress 30 % (9 MB)
28 01:23:46.950016 progress 35 % (11 MB)
29 01:23:46.958654 progress 40 % (13 MB)
30 01:23:46.967384 progress 45 % (14 MB)
31 01:23:46.975967 progress 50 % (16 MB)
32 01:23:46.984801 progress 55 % (18 MB)
33 01:23:46.993453 progress 60 % (19 MB)
34 01:23:47.002253 progress 65 % (21 MB)
35 01:23:47.010915 progress 70 % (22 MB)
36 01:23:47.019830 progress 75 % (24 MB)
37 01:23:47.028478 progress 80 % (26 MB)
38 01:23:47.037360 progress 85 % (27 MB)
39 01:23:47.045929 progress 90 % (29 MB)
40 01:23:47.054606 progress 95 % (31 MB)
41 01:23:47.063126 progress 100 % (32 MB)
42 01:23:47.063310 32 MB downloaded in 4.13 s (7.93 MB/s)
43 01:23:47.063474 end: 1.1.1 http-download (duration 00:00:04) [common]
45 01:23:47.063723 end: 1.1 download-retry (duration 00:00:04) [common]
46 01:23:47.063812 start: 1.2 download-retry (timeout 00:09:56) [common]
47 01:23:47.063899 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 01:23:47.064039 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:23:47.064110 saving as /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/kernel/Image
50 01:23:47.064173 total size: 49220096 (46 MB)
51 01:23:47.064236 No compression specified
52 01:23:47.065367 progress 0 % (0 MB)
53 01:23:47.077741 progress 5 % (2 MB)
54 01:23:47.090065 progress 10 % (4 MB)
55 01:23:47.102472 progress 15 % (7 MB)
56 01:23:47.114924 progress 20 % (9 MB)
57 01:23:47.127412 progress 25 % (11 MB)
58 01:23:47.140007 progress 30 % (14 MB)
59 01:23:47.152549 progress 35 % (16 MB)
60 01:23:47.165427 progress 40 % (18 MB)
61 01:23:47.177870 progress 45 % (21 MB)
62 01:23:47.190537 progress 50 % (23 MB)
63 01:23:47.202972 progress 55 % (25 MB)
64 01:23:47.215397 progress 60 % (28 MB)
65 01:23:47.227782 progress 65 % (30 MB)
66 01:23:47.240352 progress 70 % (32 MB)
67 01:23:47.252839 progress 75 % (35 MB)
68 01:23:47.265180 progress 80 % (37 MB)
69 01:23:47.277532 progress 85 % (39 MB)
70 01:23:47.289964 progress 90 % (42 MB)
71 01:23:47.302173 progress 95 % (44 MB)
72 01:23:47.314475 progress 100 % (46 MB)
73 01:23:47.314614 46 MB downloaded in 0.25 s (187.43 MB/s)
74 01:23:47.314783 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:23:47.315048 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:23:47.315152 start: 1.3 download-retry (timeout 00:09:56) [common]
78 01:23:47.315260 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 01:23:47.315414 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:23:47.315515 saving as /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/dtb/mt8192-asurada-spherion-r0.dtb
81 01:23:47.315617 total size: 47278 (0 MB)
82 01:23:47.315719 No compression specified
83 01:23:47.317353 progress 69 % (0 MB)
84 01:23:47.317654 progress 100 % (0 MB)
85 01:23:47.317825 0 MB downloaded in 0.00 s (20.44 MB/s)
86 01:23:47.317967 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:23:47.318223 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:23:47.318327 start: 1.4 download-retry (timeout 00:09:56) [common]
90 01:23:47.318428 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 01:23:47.318556 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:23:47.318655 saving as /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/modules/modules.tar
93 01:23:47.318756 total size: 8616896 (8 MB)
94 01:23:47.318857 Using unxz to decompress xz
95 01:23:47.322800 progress 0 % (0 MB)
96 01:23:47.343817 progress 5 % (0 MB)
97 01:23:47.367484 progress 10 % (0 MB)
98 01:23:47.396579 progress 15 % (1 MB)
99 01:23:47.424214 progress 20 % (1 MB)
100 01:23:47.447537 progress 25 % (2 MB)
101 01:23:47.471723 progress 30 % (2 MB)
102 01:23:47.498115 progress 35 % (2 MB)
103 01:23:47.522216 progress 40 % (3 MB)
104 01:23:47.547747 progress 45 % (3 MB)
105 01:23:47.573082 progress 50 % (4 MB)
106 01:23:47.597854 progress 55 % (4 MB)
107 01:23:47.622184 progress 60 % (4 MB)
108 01:23:47.645858 progress 65 % (5 MB)
109 01:23:47.670915 progress 70 % (5 MB)
110 01:23:47.696312 progress 75 % (6 MB)
111 01:23:47.719761 progress 80 % (6 MB)
112 01:23:47.744512 progress 85 % (7 MB)
113 01:23:47.768611 progress 90 % (7 MB)
114 01:23:47.792723 progress 95 % (7 MB)
115 01:23:47.818827 progress 100 % (8 MB)
116 01:23:47.825051 8 MB downloaded in 0.51 s (16.23 MB/s)
117 01:23:47.825385 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:23:47.825842 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:23:47.825995 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 01:23:47.826158 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 01:23:47.826298 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:23:47.826450 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 01:23:47.826778 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3
125 01:23:47.826987 makedir: /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin
126 01:23:47.827156 makedir: /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/tests
127 01:23:47.827318 makedir: /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/results
128 01:23:47.827500 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-add-keys
129 01:23:47.827720 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-add-sources
130 01:23:47.827925 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-background-process-start
131 01:23:47.828130 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-background-process-stop
132 01:23:47.828330 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-common-functions
133 01:23:47.828529 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-echo-ipv4
134 01:23:47.828733 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-install-packages
135 01:23:47.828932 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-installed-packages
136 01:23:47.829130 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-os-build
137 01:23:47.829335 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-probe-channel
138 01:23:47.829535 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-probe-ip
139 01:23:47.829734 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-target-ip
140 01:23:47.829933 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-target-mac
141 01:23:47.830130 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-target-storage
142 01:23:47.830334 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-case
143 01:23:47.830537 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-event
144 01:23:47.830730 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-feedback
145 01:23:47.830932 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-raise
146 01:23:47.831133 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-reference
147 01:23:47.831328 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-runner
148 01:23:47.831530 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-set
149 01:23:47.831735 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-test-shell
150 01:23:47.831946 Updating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-install-packages (oe)
151 01:23:47.832176 Updating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/bin/lava-installed-packages (oe)
152 01:23:47.832376 Creating /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/environment
153 01:23:47.832540 LAVA metadata
154 01:23:47.832662 - LAVA_JOB_ID=11368530
155 01:23:47.832795 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:23:47.832968 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 01:23:47.833089 skipped lava-vland-overlay
158 01:23:47.833222 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:23:47.833368 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 01:23:47.833487 skipped lava-multinode-overlay
161 01:23:47.833625 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:23:47.833775 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 01:23:47.833909 Loading test definitions
164 01:23:47.834073 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 01:23:47.834208 Using /lava-11368530 at stage 0
166 01:23:47.834693 uuid=11368530_1.5.2.3.1 testdef=None
167 01:23:47.834842 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:23:47.834989 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 01:23:47.835827 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:23:47.836231 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 01:23:47.837308 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:23:47.837723 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 01:23:47.838714 runner path: /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/0/tests/0_cros-ec test_uuid 11368530_1.5.2.3.1
176 01:23:47.838944 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:23:47.839329 Creating lava-test-runner.conf files
179 01:23:47.839444 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11368530/lava-overlay-1jj0rgp3/lava-11368530/0 for stage 0
180 01:23:47.839590 - 0_cros-ec
181 01:23:47.839750 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:23:47.839891 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 01:23:47.849963 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:23:47.850125 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 01:23:47.850271 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:23:47.850416 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:23:47.850561 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 01:23:48.767942 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:23:48.768319 start: 1.5.4 extract-modules (timeout 00:09:54) [common]
190 01:23:48.768444 extracting modules file /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11368530/extract-overlay-ramdisk-cslckvub/ramdisk
191 01:23:48.981215 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:23:48.981394 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
193 01:23:48.981496 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368530/compress-overlay-oduv1exw/overlay-1.5.2.4.tar.gz to ramdisk
194 01:23:48.981571 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368530/compress-overlay-oduv1exw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11368530/extract-overlay-ramdisk-cslckvub/ramdisk
195 01:23:48.988094 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:23:48.988209 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
197 01:23:48.988302 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:23:48.988401 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
199 01:23:48.988477 Building ramdisk /var/lib/lava/dispatcher/tmp/11368530/extract-overlay-ramdisk-cslckvub/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11368530/extract-overlay-ramdisk-cslckvub/ramdisk
200 01:23:49.689904 >> 270888 blocks
201 01:23:54.359182 rename /var/lib/lava/dispatcher/tmp/11368530/extract-overlay-ramdisk-cslckvub/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/ramdisk/ramdisk.cpio.gz
202 01:23:54.359622 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 01:23:54.359753 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 01:23:54.359856 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 01:23:54.359960 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/kernel/Image'
206 01:24:06.395635 Returned 0 in 12 seconds
207 01:24:06.496224 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/kernel/image.itb
208 01:24:07.172677 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:24:07.173075 output: Created: Mon Aug 28 02:24:07 2023
210 01:24:07.173157 output: Image 0 (kernel-1)
211 01:24:07.173226 output: Description:
212 01:24:07.173293 output: Created: Mon Aug 28 02:24:07 2023
213 01:24:07.173359 output: Type: Kernel Image
214 01:24:07.173423 output: Compression: lzma compressed
215 01:24:07.173483 output: Data Size: 11038667 Bytes = 10779.95 KiB = 10.53 MiB
216 01:24:07.173544 output: Architecture: AArch64
217 01:24:07.173603 output: OS: Linux
218 01:24:07.173664 output: Load Address: 0x00000000
219 01:24:07.173720 output: Entry Point: 0x00000000
220 01:24:07.173776 output: Hash algo: crc32
221 01:24:07.173832 output: Hash value: 3affb6e1
222 01:24:07.173888 output: Image 1 (fdt-1)
223 01:24:07.173944 output: Description: mt8192-asurada-spherion-r0
224 01:24:07.173999 output: Created: Mon Aug 28 02:24:07 2023
225 01:24:07.174056 output: Type: Flat Device Tree
226 01:24:07.174111 output: Compression: uncompressed
227 01:24:07.174166 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 01:24:07.174223 output: Architecture: AArch64
229 01:24:07.174278 output: Hash algo: crc32
230 01:24:07.174333 output: Hash value: cc4352de
231 01:24:07.174388 output: Image 2 (ramdisk-1)
232 01:24:07.174443 output: Description: unavailable
233 01:24:07.174499 output: Created: Mon Aug 28 02:24:07 2023
234 01:24:07.174555 output: Type: RAMDisk Image
235 01:24:07.174610 output: Compression: Unknown Compression
236 01:24:07.174666 output: Data Size: 47512644 Bytes = 46399.07 KiB = 45.31 MiB
237 01:24:07.174721 output: Architecture: AArch64
238 01:24:07.174776 output: OS: Linux
239 01:24:07.174832 output: Load Address: unavailable
240 01:24:07.174887 output: Entry Point: unavailable
241 01:24:07.174942 output: Hash algo: crc32
242 01:24:07.174996 output: Hash value: f78aaa11
243 01:24:07.175051 output: Default Configuration: 'conf-1'
244 01:24:07.175106 output: Configuration 0 (conf-1)
245 01:24:07.175161 output: Description: mt8192-asurada-spherion-r0
246 01:24:07.175216 output: Kernel: kernel-1
247 01:24:07.175272 output: Init Ramdisk: ramdisk-1
248 01:24:07.175327 output: FDT: fdt-1
249 01:24:07.175382 output: Loadables: kernel-1
250 01:24:07.175438 output:
251 01:24:07.175630 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 01:24:07.175728 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 01:24:07.175836 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 01:24:07.175935 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 01:24:07.176015 No LXC device requested
256 01:24:07.176097 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:24:07.176186 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 01:24:07.176266 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:24:07.176338 Checking files for TFTP limit of 4294967296 bytes.
260 01:24:07.176859 end: 1 tftp-deploy (duration 00:00:24) [common]
261 01:24:07.176969 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:24:07.177063 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:24:07.177186 substitutions:
264 01:24:07.177257 - {DTB}: 11368530/tftp-deploy-8rmbjqvi/dtb/mt8192-asurada-spherion-r0.dtb
265 01:24:07.177324 - {INITRD}: 11368530/tftp-deploy-8rmbjqvi/ramdisk/ramdisk.cpio.gz
266 01:24:07.177387 - {KERNEL}: 11368530/tftp-deploy-8rmbjqvi/kernel/Image
267 01:24:07.177447 - {LAVA_MAC}: None
268 01:24:07.177507 - {PRESEED_CONFIG}: None
269 01:24:07.177566 - {PRESEED_LOCAL}: None
270 01:24:07.177625 - {RAMDISK}: 11368530/tftp-deploy-8rmbjqvi/ramdisk/ramdisk.cpio.gz
271 01:24:07.177684 - {ROOT_PART}: None
272 01:24:07.177741 - {ROOT}: None
273 01:24:07.177799 - {SERVER_IP}: 192.168.201.1
274 01:24:07.177855 - {TEE}: None
275 01:24:07.177928 Parsed boot commands:
276 01:24:07.177998 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:24:07.178173 Parsed boot commands: tftpboot 192.168.201.1 11368530/tftp-deploy-8rmbjqvi/kernel/image.itb 11368530/tftp-deploy-8rmbjqvi/kernel/cmdline
278 01:24:07.178264 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:24:07.178353 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:24:07.178446 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:24:07.178537 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:24:07.178609 Not connected, no need to disconnect.
283 01:24:07.178686 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:24:07.178769 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:24:07.178841 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 01:24:07.182314 Setting prompt string to ['lava-test: # ']
287 01:24:07.182638 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:24:07.182748 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:24:07.182849 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:24:07.182975 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:24:07.183168 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 01:24:12.321937 >> Command sent successfully.
293 01:24:12.324314 Returned 0 in 5 seconds
294 01:24:12.424729 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:24:12.425259 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:24:12.425423 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:24:12.425562 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:24:12.425689 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:24:12.425813 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:24:12.426214 [Enter `^Ec?' for help]
302 01:24:12.601232
303 01:24:12.601411
304 01:24:12.601529 F0: 102B 0000
305 01:24:12.601642
306 01:24:12.601755 F3: 1001 0000 [0200]
307 01:24:12.601870
308 01:24:12.604890 F3: 1001 0000
309 01:24:12.605010
310 01:24:12.605125 F7: 102D 0000
311 01:24:12.605229
312 01:24:12.605339 F1: 0000 0000
313 01:24:12.608612
314 01:24:12.608734 V0: 0000 0000 [0001]
315 01:24:12.608847
316 01:24:12.608960 00: 0007 8000
317 01:24:12.609072
318 01:24:12.612626 01: 0000 0000
319 01:24:12.612745
320 01:24:12.612891 BP: 0C00 0209 [0000]
321 01:24:12.613008
322 01:24:12.616227 G0: 1182 0000
323 01:24:12.616350
324 01:24:12.616465 EC: 0000 0021 [4000]
325 01:24:12.616579
326 01:24:12.620156 S7: 0000 0000 [0000]
327 01:24:12.620280
328 01:24:12.620394 CC: 0000 0000 [0001]
329 01:24:12.620505
330 01:24:12.623244 T0: 0000 0040 [010F]
331 01:24:12.623373
332 01:24:12.623489 Jump to BL
333 01:24:12.623599
334 01:24:12.648198
335 01:24:12.648325
336 01:24:12.648437
337 01:24:12.655310 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:24:12.659364 ARM64: Exception handlers installed.
339 01:24:12.663111 ARM64: Testing exception
340 01:24:12.666518 ARM64: Done test exception
341 01:24:12.673670 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:24:12.681354 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:24:12.688120 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:24:12.699158 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:24:12.705724 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:24:12.716219 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:24:12.726804 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:24:12.733290 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:24:12.751245 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:24:12.754345 WDT: Last reset was cold boot
351 01:24:12.757525 SPI1(PAD0) initialized at 2873684 Hz
352 01:24:12.760939 SPI5(PAD0) initialized at 992727 Hz
353 01:24:12.764461 VBOOT: Loading verstage.
354 01:24:12.770889 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:24:12.774695 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:24:12.777453 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:24:12.780995 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:24:12.788312 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:24:12.794808 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:24:12.805750 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 01:24:12.805881
362 01:24:12.805997
363 01:24:12.815779 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:24:12.819294 ARM64: Exception handlers installed.
365 01:24:12.822750 ARM64: Testing exception
366 01:24:12.822875 ARM64: Done test exception
367 01:24:12.829296 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:24:12.832451 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:24:12.846924 Probing TPM: . done!
370 01:24:12.847049 TPM ready after 0 ms
371 01:24:12.853816 Connected to device vid:did:rid of 1ae0:0028:00
372 01:24:12.861735 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 01:24:12.917957 Initialized TPM device CR50 revision 0
374 01:24:12.929786 tlcl_send_startup: Startup return code is 0
375 01:24:12.929924 TPM: setup succeeded
376 01:24:12.941392 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:24:12.950200 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:24:12.960053 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:24:12.970139 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:24:12.972983 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:24:12.978679 in-header: 03 07 00 00 08 00 00 00
382 01:24:12.983068 in-data: aa e4 47 04 13 02 00 00
383 01:24:12.986364 Chrome EC: UHEPI supported
384 01:24:12.993181 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:24:12.997743 in-header: 03 ad 00 00 08 00 00 00
386 01:24:13.000823 in-data: 00 20 20 08 00 00 00 00
387 01:24:13.000948 Phase 1
388 01:24:13.005168 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:24:13.012371 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:24:13.015843 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:24:13.020207 Recovery requested (1009000e)
392 01:24:13.028477 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:24:13.034147 tlcl_extend: response is 0
394 01:24:13.042928 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:24:13.048672 tlcl_extend: response is 0
396 01:24:13.055977 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:24:13.076219 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 01:24:13.083142 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:24:13.083268
400 01:24:13.083382
401 01:24:13.092823 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:24:13.096185 ARM64: Exception handlers installed.
403 01:24:13.096313 ARM64: Testing exception
404 01:24:13.099732 ARM64: Done test exception
405 01:24:13.121457 pmic_efuse_setting: Set efuses in 11 msecs
406 01:24:13.125072 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:24:13.131753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:24:13.135674 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:24:13.138717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:24:13.145427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:24:13.148834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:24:13.156638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:24:13.160163 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:24:13.164232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:24:13.167964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:24:13.175171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:24:13.178486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:24:13.182139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:24:13.185434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:24:13.192569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:24:13.199677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:24:13.206335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:24:13.209890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:24:13.217051 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:24:13.220706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:24:13.227395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:24:13.234786 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:24:13.237827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:24:13.244573 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:24:13.247775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:24:13.254457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:24:13.261195 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:24:13.264705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:24:13.271730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:24:13.274458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:24:13.281444 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:24:13.285133 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:24:13.291433 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:24:13.294788 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:24:13.301440 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:24:13.304847 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:24:13.311412 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:24:13.314762 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:24:13.321716 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:24:13.325569 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:24:13.328234 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:24:13.331560 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:24:13.338151 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:24:13.342659 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:24:13.346222 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:24:13.349547 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:24:13.356633 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:24:13.359569 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:24:13.362689 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:24:13.369340 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:24:13.372935 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:24:13.376176 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:24:13.382824 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:24:13.392861 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:24:13.396453 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:24:13.406053 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:24:13.412883 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:24:13.419530 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:24:13.422973 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:24:13.426084 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:24:13.433908 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x9
467 01:24:13.441156 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:24:13.444275 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 01:24:13.447171 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:24:13.458646 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 01:24:13.467794 [RTC]rtc_get_frequency_meter,154: input=23, output=956
472 01:24:13.477434 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 01:24:13.487083 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 01:24:13.496795 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 01:24:13.499959 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 01:24:13.506657 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 01:24:13.509764 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 01:24:13.513114 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 01:24:13.516628 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 01:24:13.520125 ADC[4]: Raw value=902876 ID=7
481 01:24:13.523476 ADC[3]: Raw value=213179 ID=1
482 01:24:13.523561 RAM Code: 0x71
483 01:24:13.530045 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 01:24:13.533339 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 01:24:13.544443 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 01:24:13.548725 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 01:24:13.551545 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 01:24:13.555875 in-header: 03 07 00 00 08 00 00 00
489 01:24:13.559392 in-data: aa e4 47 04 13 02 00 00
490 01:24:13.563415 Chrome EC: UHEPI supported
491 01:24:13.570682 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 01:24:13.574093 in-header: 03 ed 00 00 08 00 00 00
493 01:24:13.574223 in-data: 80 20 60 08 00 00 00 00
494 01:24:13.578029 MRC: failed to locate region type 0.
495 01:24:13.585447 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 01:24:13.590130 DRAM-K: Running full calibration
497 01:24:13.596529 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 01:24:13.596657 header.status = 0x0
499 01:24:13.600586 header.version = 0x6 (expected: 0x6)
500 01:24:13.603422 header.size = 0xd00 (expected: 0xd00)
501 01:24:13.603553 header.flags = 0x0
502 01:24:13.610030 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 01:24:13.628669 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 01:24:13.635312 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 01:24:13.638642 dram_init: ddr_geometry: 2
506 01:24:13.638768 [EMI] MDL number = 2
507 01:24:13.642012 [EMI] Get MDL freq = 0
508 01:24:13.645239 dram_init: ddr_type: 0
509 01:24:13.645363 is_discrete_lpddr4: 1
510 01:24:13.648996 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 01:24:13.649120
512 01:24:13.649233
513 01:24:13.652083 [Bian_co] ETT version 0.0.0.1
514 01:24:13.655812 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 01:24:13.655942
516 01:24:13.663437 dramc_set_vcore_voltage set vcore to 650000
517 01:24:13.663565 Read voltage for 800, 4
518 01:24:13.663683 Vio18 = 0
519 01:24:13.666838 Vcore = 650000
520 01:24:13.666964 Vdram = 0
521 01:24:13.667085 Vddq = 0
522 01:24:13.670784 Vmddr = 0
523 01:24:13.670912 dram_init: config_dvfs: 1
524 01:24:13.674495 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 01:24:13.681704 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 01:24:13.685285 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 01:24:13.688446 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 01:24:13.691661 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 01:24:13.695163 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 01:24:13.698223 MEM_TYPE=3, freq_sel=18
531 01:24:13.701693 sv_algorithm_assistance_LP4_1600
532 01:24:13.704885 ============ PULL DRAM RESETB DOWN ============
533 01:24:13.711661 ========== PULL DRAM RESETB DOWN end =========
534 01:24:13.714942 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 01:24:13.718376 ===================================
536 01:24:13.721974 LPDDR4 DRAM CONFIGURATION
537 01:24:13.725362 ===================================
538 01:24:13.725484 EX_ROW_EN[0] = 0x0
539 01:24:13.728301 EX_ROW_EN[1] = 0x0
540 01:24:13.728423 LP4Y_EN = 0x0
541 01:24:13.732126 WORK_FSP = 0x0
542 01:24:13.732251 WL = 0x2
543 01:24:13.735127 RL = 0x2
544 01:24:13.735253 BL = 0x2
545 01:24:13.739015 RPST = 0x0
546 01:24:13.739142 RD_PRE = 0x0
547 01:24:13.741651 WR_PRE = 0x1
548 01:24:13.741777 WR_PST = 0x0
549 01:24:13.745291 DBI_WR = 0x0
550 01:24:13.745415 DBI_RD = 0x0
551 01:24:13.748284 OTF = 0x1
552 01:24:13.752086 ===================================
553 01:24:13.755067 ===================================
554 01:24:13.755194 ANA top config
555 01:24:13.759006 ===================================
556 01:24:13.761860 DLL_ASYNC_EN = 0
557 01:24:13.765689 ALL_SLAVE_EN = 1
558 01:24:13.768433 NEW_RANK_MODE = 1
559 01:24:13.768562 DLL_IDLE_MODE = 1
560 01:24:13.771959 LP45_APHY_COMB_EN = 1
561 01:24:13.775216 TX_ODT_DIS = 1
562 01:24:13.778564 NEW_8X_MODE = 1
563 01:24:13.782127 ===================================
564 01:24:13.785229 ===================================
565 01:24:13.788672 data_rate = 1600
566 01:24:13.788836 CKR = 1
567 01:24:13.791930 DQ_P2S_RATIO = 8
568 01:24:13.795264 ===================================
569 01:24:13.798785 CA_P2S_RATIO = 8
570 01:24:13.801862 DQ_CA_OPEN = 0
571 01:24:13.805655 DQ_SEMI_OPEN = 0
572 01:24:13.808660 CA_SEMI_OPEN = 0
573 01:24:13.808790 CA_FULL_RATE = 0
574 01:24:13.812169 DQ_CKDIV4_EN = 1
575 01:24:13.815405 CA_CKDIV4_EN = 1
576 01:24:13.819312 CA_PREDIV_EN = 0
577 01:24:13.822310 PH8_DLY = 0
578 01:24:13.822397 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 01:24:13.825433 DQ_AAMCK_DIV = 4
580 01:24:13.828713 CA_AAMCK_DIV = 4
581 01:24:13.832291 CA_ADMCK_DIV = 4
582 01:24:13.835403 DQ_TRACK_CA_EN = 0
583 01:24:13.838753 CA_PICK = 800
584 01:24:13.838882 CA_MCKIO = 800
585 01:24:13.842395 MCKIO_SEMI = 0
586 01:24:13.845721 PLL_FREQ = 3068
587 01:24:13.849078 DQ_UI_PI_RATIO = 32
588 01:24:13.852185 CA_UI_PI_RATIO = 0
589 01:24:13.855523 ===================================
590 01:24:13.858867 ===================================
591 01:24:13.862304 memory_type:LPDDR4
592 01:24:13.862390 GP_NUM : 10
593 01:24:13.865436 SRAM_EN : 1
594 01:24:13.865522 MD32_EN : 0
595 01:24:13.869567 ===================================
596 01:24:13.872392 [ANA_INIT] >>>>>>>>>>>>>>
597 01:24:13.876287 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 01:24:13.880520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 01:24:13.883771 ===================================
600 01:24:13.883859 data_rate = 1600,PCW = 0X7600
601 01:24:13.887488 ===================================
602 01:24:13.891432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 01:24:13.895720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 01:24:13.902959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 01:24:13.906878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 01:24:13.909901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 01:24:13.913839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 01:24:13.916456 [ANA_INIT] flow start
609 01:24:13.919766 [ANA_INIT] PLL >>>>>>>>
610 01:24:13.919852 [ANA_INIT] PLL <<<<<<<<
611 01:24:13.923088 [ANA_INIT] MIDPI >>>>>>>>
612 01:24:13.926421 [ANA_INIT] MIDPI <<<<<<<<
613 01:24:13.926507 [ANA_INIT] DLL >>>>>>>>
614 01:24:13.929808 [ANA_INIT] flow end
615 01:24:13.933395 ============ LP4 DIFF to SE enter ============
616 01:24:13.936862 ============ LP4 DIFF to SE exit ============
617 01:24:13.939722 [ANA_INIT] <<<<<<<<<<<<<
618 01:24:13.943340 [Flow] Enable top DCM control >>>>>
619 01:24:13.946311 [Flow] Enable top DCM control <<<<<
620 01:24:13.949767 Enable DLL master slave shuffle
621 01:24:13.956299 ==============================================================
622 01:24:13.956385 Gating Mode config
623 01:24:13.963182 ==============================================================
624 01:24:13.963268 Config description:
625 01:24:13.973154 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 01:24:13.979835 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 01:24:13.986350 SELPH_MODE 0: By rank 1: By Phase
628 01:24:13.990102 ==============================================================
629 01:24:13.993402 GAT_TRACK_EN = 1
630 01:24:13.996557 RX_GATING_MODE = 2
631 01:24:13.999929 RX_GATING_TRACK_MODE = 2
632 01:24:14.003517 SELPH_MODE = 1
633 01:24:14.006785 PICG_EARLY_EN = 1
634 01:24:14.009808 VALID_LAT_VALUE = 1
635 01:24:14.013254 ==============================================================
636 01:24:14.016758 Enter into Gating configuration >>>>
637 01:24:14.019969 Exit from Gating configuration <<<<
638 01:24:14.023297 Enter into DVFS_PRE_config >>>>>
639 01:24:14.037044 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 01:24:14.040474 Exit from DVFS_PRE_config <<<<<
641 01:24:14.040579 Enter into PICG configuration >>>>
642 01:24:14.043634 Exit from PICG configuration <<<<
643 01:24:14.046664 [RX_INPUT] configuration >>>>>
644 01:24:14.050350 [RX_INPUT] configuration <<<<<
645 01:24:14.057052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 01:24:14.060732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 01:24:14.066959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 01:24:14.073709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 01:24:14.081093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 01:24:14.086754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 01:24:14.090280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 01:24:14.093678 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 01:24:14.097021 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 01:24:14.100546 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 01:24:14.107636 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 01:24:14.111423 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 01:24:14.114761 ===================================
658 01:24:14.117939 LPDDR4 DRAM CONFIGURATION
659 01:24:14.121581 ===================================
660 01:24:14.121665 EX_ROW_EN[0] = 0x0
661 01:24:14.124695 EX_ROW_EN[1] = 0x0
662 01:24:14.124819 LP4Y_EN = 0x0
663 01:24:14.127878 WORK_FSP = 0x0
664 01:24:14.127963 WL = 0x2
665 01:24:14.131072 RL = 0x2
666 01:24:14.131157 BL = 0x2
667 01:24:14.134557 RPST = 0x0
668 01:24:14.134641 RD_PRE = 0x0
669 01:24:14.137791 WR_PRE = 0x1
670 01:24:14.137876 WR_PST = 0x0
671 01:24:14.141430 DBI_WR = 0x0
672 01:24:14.141514 DBI_RD = 0x0
673 01:24:14.144470 OTF = 0x1
674 01:24:14.147761 ===================================
675 01:24:14.151083 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 01:24:14.154614 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 01:24:14.160969 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 01:24:14.164714 ===================================
679 01:24:14.164836 LPDDR4 DRAM CONFIGURATION
680 01:24:14.168002 ===================================
681 01:24:14.171148 EX_ROW_EN[0] = 0x10
682 01:24:14.174472 EX_ROW_EN[1] = 0x0
683 01:24:14.174600 LP4Y_EN = 0x0
684 01:24:14.177766 WORK_FSP = 0x0
685 01:24:14.177891 WL = 0x2
686 01:24:14.181465 RL = 0x2
687 01:24:14.181590 BL = 0x2
688 01:24:14.185443 RPST = 0x0
689 01:24:14.185567 RD_PRE = 0x0
690 01:24:14.188719 WR_PRE = 0x1
691 01:24:14.188865 WR_PST = 0x0
692 01:24:14.188982 DBI_WR = 0x0
693 01:24:14.192413 DBI_RD = 0x0
694 01:24:14.192534 OTF = 0x1
695 01:24:14.196012 ===================================
696 01:24:14.203277 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 01:24:14.207615 nWR fixed to 40
698 01:24:14.211287 [ModeRegInit_LP4] CH0 RK0
699 01:24:14.211411 [ModeRegInit_LP4] CH0 RK1
700 01:24:14.214475 [ModeRegInit_LP4] CH1 RK0
701 01:24:14.214598 [ModeRegInit_LP4] CH1 RK1
702 01:24:14.217889 match AC timing 13
703 01:24:14.221444 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 01:24:14.224772 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 01:24:14.231984 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 01:24:14.235642 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 01:24:14.239379 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 01:24:14.243231 [EMI DOE] emi_dcm 0
709 01:24:14.247132 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 01:24:14.247219 ==
711 01:24:14.250719 Dram Type= 6, Freq= 0, CH_0, rank 0
712 01:24:14.254039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 01:24:14.254126 ==
714 01:24:14.257984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 01:24:14.264982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 01:24:14.275424 [CA 0] Center 38 (7~69) winsize 63
717 01:24:14.279710 [CA 1] Center 38 (7~69) winsize 63
718 01:24:14.283542 [CA 2] Center 35 (5~66) winsize 62
719 01:24:14.286795 [CA 3] Center 35 (5~66) winsize 62
720 01:24:14.290681 [CA 4] Center 34 (4~65) winsize 62
721 01:24:14.290814 [CA 5] Center 33 (3~64) winsize 62
722 01:24:14.290883
723 01:24:14.294466 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 01:24:14.294552
725 01:24:14.298293 [CATrainingPosCal] consider 1 rank data
726 01:24:14.301938 u2DelayCellTimex100 = 270/100 ps
727 01:24:14.305082 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 01:24:14.309336 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 01:24:14.312760 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 01:24:14.316139 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 01:24:14.319959 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 01:24:14.324096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 01:24:14.324182
734 01:24:14.327333 CA PerBit enable=1, Macro0, CA PI delay=33
735 01:24:14.327420
736 01:24:14.330825 [CBTSetCACLKResult] CA Dly = 33
737 01:24:14.334434 CS Dly: 6 (0~37)
738 01:24:14.334519 ==
739 01:24:14.338341 Dram Type= 6, Freq= 0, CH_0, rank 1
740 01:24:14.341834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 01:24:14.341947 ==
742 01:24:14.345501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 01:24:14.352687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 01:24:14.361699 [CA 0] Center 38 (7~69) winsize 63
745 01:24:14.365184 [CA 1] Center 38 (8~69) winsize 62
746 01:24:14.368949 [CA 2] Center 36 (5~67) winsize 63
747 01:24:14.372404 [CA 3] Center 36 (5~67) winsize 63
748 01:24:14.376281 [CA 4] Center 35 (4~66) winsize 63
749 01:24:14.380069 [CA 5] Center 34 (4~65) winsize 62
750 01:24:14.380195
751 01:24:14.383686 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 01:24:14.383813
753 01:24:14.387632 [CATrainingPosCal] consider 2 rank data
754 01:24:14.387759 u2DelayCellTimex100 = 270/100 ps
755 01:24:14.391410 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 01:24:14.395245 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 01:24:14.398651 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 01:24:14.402496 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 01:24:14.406186 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 01:24:14.409846 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 01:24:14.409971
762 01:24:14.413675 CA PerBit enable=1, Macro0, CA PI delay=34
763 01:24:14.413800
764 01:24:14.417506 [CBTSetCACLKResult] CA Dly = 34
765 01:24:14.417631 CS Dly: 6 (0~38)
766 01:24:14.421082
767 01:24:14.421202 ----->DramcWriteLeveling(PI) begin...
768 01:24:14.421312 ==
769 01:24:14.424997 Dram Type= 6, Freq= 0, CH_0, rank 0
770 01:24:14.429170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 01:24:14.429295 ==
772 01:24:14.433182 Write leveling (Byte 0): 31 => 31
773 01:24:14.436682 Write leveling (Byte 1): 31 => 31
774 01:24:14.440357 DramcWriteLeveling(PI) end<-----
775 01:24:14.440482
776 01:24:14.440600 ==
777 01:24:14.444484 Dram Type= 6, Freq= 0, CH_0, rank 0
778 01:24:14.448382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 01:24:14.448505 ==
780 01:24:14.452640 [Gating] SW mode calibration
781 01:24:14.459555 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 01:24:14.463686 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 01:24:14.467362 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 01:24:14.470964 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
785 01:24:14.474568 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 01:24:14.481951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 01:24:14.486045 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 01:24:14.489940 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 01:24:14.493614 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:24:14.497029 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:24:14.500710 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:24:14.508267 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:24:14.511566 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:24:14.514746 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:24:14.518075 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:24:14.524536 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:24:14.528014 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:24:14.531439 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:24:14.537831 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 01:24:14.541474 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
801 01:24:14.544500 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
802 01:24:14.551169 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:24:14.554639 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 01:24:14.558017 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 01:24:14.564772 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:24:14.568211 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:24:14.571196 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:24:14.578010 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
809 01:24:14.581370 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
810 01:24:14.584542 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
811 01:24:14.591741 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 01:24:14.594704 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 01:24:14.597951 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 01:24:14.604729 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 01:24:14.608322 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
816 01:24:14.611501 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
817 01:24:14.614738 0 10 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
818 01:24:14.621981 0 10 12 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
819 01:24:14.624677 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 01:24:14.628565 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 01:24:14.635153 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 01:24:14.638078 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:24:14.641428 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:24:14.648034 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
825 01:24:14.651355 0 11 8 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
826 01:24:14.655155 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
827 01:24:14.661510 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 01:24:14.665307 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 01:24:14.668549 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 01:24:14.674826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 01:24:14.678220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 01:24:14.681690 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 01:24:14.684880 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 01:24:14.691526 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 01:24:14.695299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 01:24:14.698348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 01:24:14.704887 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:24:14.708183 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:24:14.711888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:24:14.718146 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:24:14.721635 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:24:14.725035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:24:14.731993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:24:14.735105 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:24:14.738340 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:24:14.745170 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:24:14.748405 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:24:14.752100 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 01:24:14.755323 Total UI for P1: 0, mck2ui 16
850 01:24:14.758316 best dqsien dly found for B0: ( 0, 14, 2)
851 01:24:14.761788 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 01:24:14.765296 Total UI for P1: 0, mck2ui 16
853 01:24:14.768563 best dqsien dly found for B1: ( 0, 14, 4)
854 01:24:14.772036 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 01:24:14.778786 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
856 01:24:14.778874
857 01:24:14.782209 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 01:24:14.785269 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 01:24:14.788356 [Gating] SW calibration Done
860 01:24:14.788444 ==
861 01:24:14.791877 Dram Type= 6, Freq= 0, CH_0, rank 0
862 01:24:14.795586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 01:24:14.795675 ==
864 01:24:14.795763 RX Vref Scan: 0
865 01:24:14.795846
866 01:24:14.798514 RX Vref 0 -> 0, step: 1
867 01:24:14.798602
868 01:24:14.801976 RX Delay -130 -> 252, step: 16
869 01:24:14.805111 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 01:24:14.808783 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 01:24:14.815084 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 01:24:14.818430 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 01:24:14.822273 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
874 01:24:14.825469 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 01:24:14.828659 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
876 01:24:14.832014 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
877 01:24:14.838701 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 01:24:14.842031 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 01:24:14.845346 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 01:24:14.848591 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 01:24:14.855249 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 01:24:14.858837 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 01:24:14.861962 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 01:24:14.865213 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
885 01:24:14.865298 ==
886 01:24:14.868598 Dram Type= 6, Freq= 0, CH_0, rank 0
887 01:24:14.871960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 01:24:14.875778 ==
889 01:24:14.875863 DQS Delay:
890 01:24:14.875930 DQS0 = 0, DQS1 = 0
891 01:24:14.878871 DQM Delay:
892 01:24:14.878956 DQM0 = 91, DQM1 = 78
893 01:24:14.882126 DQ Delay:
894 01:24:14.882220 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
895 01:24:14.885312 DQ4 =85, DQ5 =77, DQ6 =109, DQ7 =109
896 01:24:14.889193 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 01:24:14.892202 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
898 01:24:14.892288
899 01:24:14.895456
900 01:24:14.895541 ==
901 01:24:14.898869 Dram Type= 6, Freq= 0, CH_0, rank 0
902 01:24:14.902097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 01:24:14.902205 ==
904 01:24:14.902302
905 01:24:14.902393
906 01:24:14.905756 TX Vref Scan disable
907 01:24:14.905855 == TX Byte 0 ==
908 01:24:14.908893 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 01:24:14.915772 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 01:24:14.915857 == TX Byte 1 ==
911 01:24:14.918960 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 01:24:14.925940 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 01:24:14.926026 ==
914 01:24:14.929117 Dram Type= 6, Freq= 0, CH_0, rank 0
915 01:24:14.932358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 01:24:14.932443 ==
917 01:24:14.945106 TX Vref=22, minBit 1, minWin=27, winSum=438
918 01:24:14.948512 TX Vref=24, minBit 6, minWin=27, winSum=440
919 01:24:14.952132 TX Vref=26, minBit 7, minWin=27, winSum=447
920 01:24:14.955426 TX Vref=28, minBit 8, minWin=27, winSum=452
921 01:24:14.958609 TX Vref=30, minBit 8, minWin=27, winSum=454
922 01:24:14.962423 TX Vref=32, minBit 10, minWin=27, winSum=452
923 01:24:14.969012 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 30
924 01:24:14.969099
925 01:24:14.972108 Final TX Range 1 Vref 30
926 01:24:14.972210
927 01:24:14.972311 ==
928 01:24:14.975373 Dram Type= 6, Freq= 0, CH_0, rank 0
929 01:24:14.978850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 01:24:14.978937 ==
931 01:24:14.979005
932 01:24:14.982157
933 01:24:14.982243 TX Vref Scan disable
934 01:24:14.985565 == TX Byte 0 ==
935 01:24:14.988504 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 01:24:14.992130 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 01:24:14.995479 == TX Byte 1 ==
938 01:24:14.998787 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 01:24:15.002167 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 01:24:15.005194
941 01:24:15.005280 [DATLAT]
942 01:24:15.005348 Freq=800, CH0 RK0
943 01:24:15.005469
944 01:24:15.008746 DATLAT Default: 0xa
945 01:24:15.008885 0, 0xFFFF, sum = 0
946 01:24:15.011738 1, 0xFFFF, sum = 0
947 01:24:15.011841 2, 0xFFFF, sum = 0
948 01:24:15.015452 3, 0xFFFF, sum = 0
949 01:24:15.015589 4, 0xFFFF, sum = 0
950 01:24:15.018597 5, 0xFFFF, sum = 0
951 01:24:15.018684 6, 0xFFFF, sum = 0
952 01:24:15.021926 7, 0xFFFF, sum = 0
953 01:24:15.022012 8, 0xFFFF, sum = 0
954 01:24:15.025343 9, 0x0, sum = 1
955 01:24:15.025433 10, 0x0, sum = 2
956 01:24:15.028713 11, 0x0, sum = 3
957 01:24:15.028837 12, 0x0, sum = 4
958 01:24:15.032109 best_step = 10
959 01:24:15.032194
960 01:24:15.032262 ==
961 01:24:15.035791 Dram Type= 6, Freq= 0, CH_0, rank 0
962 01:24:15.039276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 01:24:15.039361 ==
964 01:24:15.042131 RX Vref Scan: 1
965 01:24:15.042254
966 01:24:15.042369 Set Vref Range= 32 -> 127
967 01:24:15.042483
968 01:24:15.045483 RX Vref 32 -> 127, step: 1
969 01:24:15.045607
970 01:24:15.048978 RX Delay -95 -> 252, step: 8
971 01:24:15.049101
972 01:24:15.052145 Set Vref, RX VrefLevel [Byte0]: 32
973 01:24:15.055498 [Byte1]: 32
974 01:24:15.055622
975 01:24:15.059172 Set Vref, RX VrefLevel [Byte0]: 33
976 01:24:15.062214 [Byte1]: 33
977 01:24:15.065696
978 01:24:15.065819 Set Vref, RX VrefLevel [Byte0]: 34
979 01:24:15.068950 [Byte1]: 34
980 01:24:15.073068
981 01:24:15.073191 Set Vref, RX VrefLevel [Byte0]: 35
982 01:24:15.076277 [Byte1]: 35
983 01:24:15.080759
984 01:24:15.080880 Set Vref, RX VrefLevel [Byte0]: 36
985 01:24:15.084009 [Byte1]: 36
986 01:24:15.088372
987 01:24:15.088495 Set Vref, RX VrefLevel [Byte0]: 37
988 01:24:15.091756 [Byte1]: 37
989 01:24:15.095975
990 01:24:15.096101 Set Vref, RX VrefLevel [Byte0]: 38
991 01:24:15.099292 [Byte1]: 38
992 01:24:15.104169
993 01:24:15.104294 Set Vref, RX VrefLevel [Byte0]: 39
994 01:24:15.107452 [Byte1]: 39
995 01:24:15.111470
996 01:24:15.111596 Set Vref, RX VrefLevel [Byte0]: 40
997 01:24:15.114432 [Byte1]: 40
998 01:24:15.118871
999 01:24:15.118995 Set Vref, RX VrefLevel [Byte0]: 41
1000 01:24:15.122279 [Byte1]: 41
1001 01:24:15.126664
1002 01:24:15.126788 Set Vref, RX VrefLevel [Byte0]: 42
1003 01:24:15.130055 [Byte1]: 42
1004 01:24:15.134755
1005 01:24:15.134880 Set Vref, RX VrefLevel [Byte0]: 43
1006 01:24:15.137973 [Byte1]: 43
1007 01:24:15.142360
1008 01:24:15.142485 Set Vref, RX VrefLevel [Byte0]: 44
1009 01:24:15.145899 [Byte1]: 44
1010 01:24:15.149455
1011 01:24:15.149580 Set Vref, RX VrefLevel [Byte0]: 45
1012 01:24:15.152845 [Byte1]: 45
1013 01:24:15.157345
1014 01:24:15.157466 Set Vref, RX VrefLevel [Byte0]: 46
1015 01:24:15.160571 [Byte1]: 46
1016 01:24:15.164446
1017 01:24:15.164571 Set Vref, RX VrefLevel [Byte0]: 47
1018 01:24:15.167830 [Byte1]: 47
1019 01:24:15.172106
1020 01:24:15.172230 Set Vref, RX VrefLevel [Byte0]: 48
1021 01:24:15.175326 [Byte1]: 48
1022 01:24:15.180031
1023 01:24:15.180154 Set Vref, RX VrefLevel [Byte0]: 49
1024 01:24:15.183103 [Byte1]: 49
1025 01:24:15.187437
1026 01:24:15.187561 Set Vref, RX VrefLevel [Byte0]: 50
1027 01:24:15.190432 [Byte1]: 50
1028 01:24:15.195207
1029 01:24:15.195329 Set Vref, RX VrefLevel [Byte0]: 51
1030 01:24:15.198173 [Byte1]: 51
1031 01:24:15.202557
1032 01:24:15.202684 Set Vref, RX VrefLevel [Byte0]: 52
1033 01:24:15.205716 [Byte1]: 52
1034 01:24:15.210096
1035 01:24:15.210219 Set Vref, RX VrefLevel [Byte0]: 53
1036 01:24:15.213245 [Byte1]: 53
1037 01:24:15.217705
1038 01:24:15.217829 Set Vref, RX VrefLevel [Byte0]: 54
1039 01:24:15.221078 [Byte1]: 54
1040 01:24:15.225060
1041 01:24:15.225185 Set Vref, RX VrefLevel [Byte0]: 55
1042 01:24:15.228274 [Byte1]: 55
1043 01:24:15.232741
1044 01:24:15.232899 Set Vref, RX VrefLevel [Byte0]: 56
1045 01:24:15.235958 [Byte1]: 56
1046 01:24:15.240183
1047 01:24:15.240306 Set Vref, RX VrefLevel [Byte0]: 57
1048 01:24:15.243461 [Byte1]: 57
1049 01:24:15.247779
1050 01:24:15.247900 Set Vref, RX VrefLevel [Byte0]: 58
1051 01:24:15.251562 [Byte1]: 58
1052 01:24:15.255486
1053 01:24:15.255614 Set Vref, RX VrefLevel [Byte0]: 59
1054 01:24:15.258875 [Byte1]: 59
1055 01:24:15.263105
1056 01:24:15.263229 Set Vref, RX VrefLevel [Byte0]: 60
1057 01:24:15.266509 [Byte1]: 60
1058 01:24:15.270779
1059 01:24:15.270902 Set Vref, RX VrefLevel [Byte0]: 61
1060 01:24:15.274264 [Byte1]: 61
1061 01:24:15.278395
1062 01:24:15.278519 Set Vref, RX VrefLevel [Byte0]: 62
1063 01:24:15.281506 [Byte1]: 62
1064 01:24:15.285829
1065 01:24:15.285953 Set Vref, RX VrefLevel [Byte0]: 63
1066 01:24:15.289466 [Byte1]: 63
1067 01:24:15.293358
1068 01:24:15.293478 Set Vref, RX VrefLevel [Byte0]: 64
1069 01:24:15.296623 [Byte1]: 64
1070 01:24:15.301005
1071 01:24:15.301089 Set Vref, RX VrefLevel [Byte0]: 65
1072 01:24:15.304637 [Byte1]: 65
1073 01:24:15.308923
1074 01:24:15.309007 Set Vref, RX VrefLevel [Byte0]: 66
1075 01:24:15.312171 [Byte1]: 66
1076 01:24:15.316459
1077 01:24:15.316543 Set Vref, RX VrefLevel [Byte0]: 67
1078 01:24:15.319545 [Byte1]: 67
1079 01:24:15.324300
1080 01:24:15.324429 Set Vref, RX VrefLevel [Byte0]: 68
1081 01:24:15.327139 [Byte1]: 68
1082 01:24:15.331600
1083 01:24:15.331725 Set Vref, RX VrefLevel [Byte0]: 69
1084 01:24:15.334837 [Byte1]: 69
1085 01:24:15.338969
1086 01:24:15.339090 Set Vref, RX VrefLevel [Byte0]: 70
1087 01:24:15.342314 [Byte1]: 70
1088 01:24:15.346767
1089 01:24:15.346891 Set Vref, RX VrefLevel [Byte0]: 71
1090 01:24:15.350006 [Byte1]: 71
1091 01:24:15.354295
1092 01:24:15.354418 Set Vref, RX VrefLevel [Byte0]: 72
1093 01:24:15.357884 [Byte1]: 72
1094 01:24:15.361782
1095 01:24:15.361906 Set Vref, RX VrefLevel [Byte0]: 73
1096 01:24:15.365490 [Byte1]: 73
1097 01:24:15.369568
1098 01:24:15.369694 Set Vref, RX VrefLevel [Byte0]: 74
1099 01:24:15.372826 [Byte1]: 74
1100 01:24:15.377071
1101 01:24:15.377193 Set Vref, RX VrefLevel [Byte0]: 75
1102 01:24:15.380320 [Byte1]: 75
1103 01:24:15.384504
1104 01:24:15.384628 Set Vref, RX VrefLevel [Byte0]: 76
1105 01:24:15.388218 [Byte1]: 76
1106 01:24:15.392589
1107 01:24:15.392713 Set Vref, RX VrefLevel [Byte0]: 77
1108 01:24:15.395786 [Byte1]: 77
1109 01:24:15.399724
1110 01:24:15.399849 Final RX Vref Byte 0 = 63 to rank0
1111 01:24:15.403415 Final RX Vref Byte 1 = 61 to rank0
1112 01:24:15.406518 Final RX Vref Byte 0 = 63 to rank1
1113 01:24:15.409791 Final RX Vref Byte 1 = 61 to rank1==
1114 01:24:15.413101 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 01:24:15.419856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 01:24:15.419987 ==
1117 01:24:15.420106 DQS Delay:
1118 01:24:15.420221 DQS0 = 0, DQS1 = 0
1119 01:24:15.423289 DQM Delay:
1120 01:24:15.423414 DQM0 = 93, DQM1 = 82
1121 01:24:15.426510 DQ Delay:
1122 01:24:15.429925 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1123 01:24:15.430051 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1124 01:24:15.433267 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1125 01:24:15.436672 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =92
1126 01:24:15.440007
1127 01:24:15.440130
1128 01:24:15.446536 [DQSOSCAuto] RK0, (LSB)MR18= 0x3833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1129 01:24:15.450138 CH0 RK0: MR19=606, MR18=3833
1130 01:24:15.456560 CH0_RK0: MR19=0x606, MR18=0x3833, DQSOSC=395, MR23=63, INC=94, DEC=63
1131 01:24:15.456684
1132 01:24:15.460061 ----->DramcWriteLeveling(PI) begin...
1133 01:24:15.460199 ==
1134 01:24:15.463491 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 01:24:15.466805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 01:24:15.466929 ==
1137 01:24:15.469910 Write leveling (Byte 0): 30 => 30
1138 01:24:15.473573 Write leveling (Byte 1): 29 => 29
1139 01:24:15.476956 DramcWriteLeveling(PI) end<-----
1140 01:24:15.477082
1141 01:24:15.477200 ==
1142 01:24:15.479974 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 01:24:15.483458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 01:24:15.483576 ==
1145 01:24:15.486915 [Gating] SW mode calibration
1146 01:24:15.494130 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 01:24:15.500245 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 01:24:15.503390 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 01:24:15.507710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1150 01:24:15.513560 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 01:24:15.516851 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 01:24:15.520217 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:24:15.526753 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:24:15.571727 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:24:15.572173 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:24:15.572297 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:24:15.572602 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:24:15.572757 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:24:15.572902 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:24:15.573016 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:24:15.573328 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:24:15.573633 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:24:15.573996 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:24:15.615059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:24:15.615187 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1166 01:24:15.615497 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1167 01:24:15.615633 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:24:15.616158 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:24:15.616601 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:24:15.616736 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:24:15.617060 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:24:15.617380 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:24:15.617676 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:24:15.644700 0 9 8 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 1)
1175 01:24:15.644807 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 01:24:15.645073 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 01:24:15.645363 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 01:24:15.645615 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 01:24:15.645958 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 01:24:15.646043 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:24:15.648980 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
1182 01:24:15.652322 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1183 01:24:15.655583 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 01:24:15.662271 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 01:24:15.665463 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 01:24:15.669321 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 01:24:15.675691 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:24:15.679026 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:24:15.682218 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1190 01:24:15.688952 0 11 8 | B1->B0 | 3b3b 4443 | 0 1 | (0 0) (0 0)
1191 01:24:15.692664 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 01:24:15.695564 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 01:24:15.702689 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 01:24:15.706336 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 01:24:15.710008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:24:15.713577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:24:15.717359 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 01:24:15.724290 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 01:24:15.727512 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 01:24:15.731610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:24:15.735314 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:24:15.741788 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:24:15.744760 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:24:15.748646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:24:15.755348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:24:15.758968 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:24:15.761535 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:24:15.768263 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:24:15.771679 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:24:15.774921 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:24:15.781566 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:24:15.784968 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:24:15.788298 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 01:24:15.795125 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 01:24:15.795251 Total UI for P1: 0, mck2ui 16
1216 01:24:15.798541 best dqsien dly found for B0: ( 0, 14, 4)
1217 01:24:15.801598 Total UI for P1: 0, mck2ui 16
1218 01:24:15.805337 best dqsien dly found for B1: ( 0, 14, 6)
1219 01:24:15.808432 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1220 01:24:15.811635 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1221 01:24:15.815153
1222 01:24:15.818552 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1223 01:24:15.821952 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 01:24:15.825110 [Gating] SW calibration Done
1225 01:24:15.825193 ==
1226 01:24:15.828415 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 01:24:15.831881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 01:24:15.831965 ==
1229 01:24:15.832032 RX Vref Scan: 0
1230 01:24:15.832093
1231 01:24:15.835213 RX Vref 0 -> 0, step: 1
1232 01:24:15.835296
1233 01:24:15.838717 RX Delay -130 -> 252, step: 16
1234 01:24:15.841886 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1235 01:24:15.845111 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1236 01:24:15.851917 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1237 01:24:15.855068 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1238 01:24:15.858669 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1239 01:24:15.861891 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1240 01:24:15.865478 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1241 01:24:15.871986 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1242 01:24:15.875297 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1243 01:24:15.878533 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1244 01:24:15.881992 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1245 01:24:15.885433 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1246 01:24:15.891922 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1247 01:24:15.895447 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1248 01:24:15.898765 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1249 01:24:15.902114 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1250 01:24:15.902197 ==
1251 01:24:15.905344 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 01:24:15.908667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 01:24:15.911994 ==
1254 01:24:15.912099 DQS Delay:
1255 01:24:15.912192 DQS0 = 0, DQS1 = 0
1256 01:24:15.915594 DQM Delay:
1257 01:24:15.915676 DQM0 = 92, DQM1 = 84
1258 01:24:15.918681 DQ Delay:
1259 01:24:15.918789 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1260 01:24:15.922111 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1261 01:24:15.925591 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =85
1262 01:24:15.928908 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1263 01:24:15.928991
1264 01:24:15.932481
1265 01:24:15.932563 ==
1266 01:24:15.935814 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 01:24:15.938757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 01:24:15.938841 ==
1269 01:24:15.938906
1270 01:24:15.938966
1271 01:24:15.942402 TX Vref Scan disable
1272 01:24:15.942509 == TX Byte 0 ==
1273 01:24:15.945498 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1274 01:24:15.952346 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1275 01:24:15.952431 == TX Byte 1 ==
1276 01:24:15.955769 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1277 01:24:15.962272 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1278 01:24:15.962357 ==
1279 01:24:15.965642 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 01:24:15.968781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 01:24:15.968866 ==
1282 01:24:15.982484 TX Vref=22, minBit 3, minWin=27, winSum=443
1283 01:24:15.986031 TX Vref=24, minBit 8, minWin=27, winSum=443
1284 01:24:15.989226 TX Vref=26, minBit 8, minWin=27, winSum=449
1285 01:24:15.992473 TX Vref=28, minBit 8, minWin=27, winSum=447
1286 01:24:15.995661 TX Vref=30, minBit 10, minWin=27, winSum=453
1287 01:24:15.999148 TX Vref=32, minBit 8, minWin=27, winSum=451
1288 01:24:16.006000 [TxChooseVref] Worse bit 10, Min win 27, Win sum 453, Final Vref 30
1289 01:24:16.006129
1290 01:24:16.009712 Final TX Range 1 Vref 30
1291 01:24:16.009838
1292 01:24:16.009952 ==
1293 01:24:16.012788 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 01:24:16.016096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 01:24:16.016219 ==
1296 01:24:16.016334
1297 01:24:16.016443
1298 01:24:16.019075 TX Vref Scan disable
1299 01:24:16.022753 == TX Byte 0 ==
1300 01:24:16.025893 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1301 01:24:16.029270 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1302 01:24:16.032740 == TX Byte 1 ==
1303 01:24:16.035801 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1304 01:24:16.039221 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1305 01:24:16.039304
1306 01:24:16.042624 [DATLAT]
1307 01:24:16.042706 Freq=800, CH0 RK1
1308 01:24:16.042772
1309 01:24:16.045940 DATLAT Default: 0xa
1310 01:24:16.046022 0, 0xFFFF, sum = 0
1311 01:24:16.049568 1, 0xFFFF, sum = 0
1312 01:24:16.049653 2, 0xFFFF, sum = 0
1313 01:24:16.052705 3, 0xFFFF, sum = 0
1314 01:24:16.052812 4, 0xFFFF, sum = 0
1315 01:24:16.055999 5, 0xFFFF, sum = 0
1316 01:24:16.056084 6, 0xFFFF, sum = 0
1317 01:24:16.059352 7, 0xFFFF, sum = 0
1318 01:24:16.059437 8, 0xFFFF, sum = 0
1319 01:24:16.062555 9, 0x0, sum = 1
1320 01:24:16.062639 10, 0x0, sum = 2
1321 01:24:16.065825 11, 0x0, sum = 3
1322 01:24:16.065909 12, 0x0, sum = 4
1323 01:24:16.069690 best_step = 10
1324 01:24:16.069773
1325 01:24:16.069839 ==
1326 01:24:16.072453 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 01:24:16.075846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 01:24:16.075930 ==
1329 01:24:16.079306 RX Vref Scan: 0
1330 01:24:16.079387
1331 01:24:16.079453 RX Vref 0 -> 0, step: 1
1332 01:24:16.079515
1333 01:24:16.082815 RX Delay -79 -> 252, step: 8
1334 01:24:16.089287 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1335 01:24:16.092549 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1336 01:24:16.095898 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1337 01:24:16.099127 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1338 01:24:16.102393 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1339 01:24:16.105995 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1340 01:24:16.112487 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1341 01:24:16.116011 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1342 01:24:16.119113 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1343 01:24:16.122698 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1344 01:24:16.125935 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1345 01:24:16.132502 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1346 01:24:16.135896 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1347 01:24:16.139408 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1348 01:24:16.143193 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1349 01:24:16.149262 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1350 01:24:16.149344 ==
1351 01:24:16.152675 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 01:24:16.155923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 01:24:16.156006 ==
1354 01:24:16.156071 DQS Delay:
1355 01:24:16.159729 DQS0 = 0, DQS1 = 0
1356 01:24:16.159812 DQM Delay:
1357 01:24:16.162777 DQM0 = 91, DQM1 = 82
1358 01:24:16.162860 DQ Delay:
1359 01:24:16.165938 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1360 01:24:16.169167 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1361 01:24:16.172498 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1362 01:24:16.175931 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1363 01:24:16.176013
1364 01:24:16.176079
1365 01:24:16.183134 [DQSOSCAuto] RK1, (LSB)MR18= 0x4620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1366 01:24:16.186130 CH0 RK1: MR19=606, MR18=4620
1367 01:24:16.192776 CH0_RK1: MR19=0x606, MR18=0x4620, DQSOSC=392, MR23=63, INC=96, DEC=64
1368 01:24:16.196150 [RxdqsGatingPostProcess] freq 800
1369 01:24:16.200094 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1370 01:24:16.202769 Pre-setting of DQS Precalculation
1371 01:24:16.209703 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1372 01:24:16.209786 ==
1373 01:24:16.212719 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 01:24:16.216353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 01:24:16.216436 ==
1376 01:24:16.223031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1377 01:24:16.229669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1378 01:24:16.237748 [CA 0] Center 36 (6~67) winsize 62
1379 01:24:16.241058 [CA 1] Center 36 (6~67) winsize 62
1380 01:24:16.243953 [CA 2] Center 35 (5~65) winsize 61
1381 01:24:16.247365 [CA 3] Center 34 (3~65) winsize 63
1382 01:24:16.250933 [CA 4] Center 34 (4~65) winsize 62
1383 01:24:16.253970 [CA 5] Center 34 (3~65) winsize 63
1384 01:24:16.254052
1385 01:24:16.257331 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1386 01:24:16.257414
1387 01:24:16.260528 [CATrainingPosCal] consider 1 rank data
1388 01:24:16.264095 u2DelayCellTimex100 = 270/100 ps
1389 01:24:16.267674 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1390 01:24:16.271024 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1391 01:24:16.274395 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1392 01:24:16.280666 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1393 01:24:16.284160 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1394 01:24:16.287603 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1395 01:24:16.287688
1396 01:24:16.290662 CA PerBit enable=1, Macro0, CA PI delay=34
1397 01:24:16.290747
1398 01:24:16.293877 [CBTSetCACLKResult] CA Dly = 34
1399 01:24:16.293961 CS Dly: 4 (0~35)
1400 01:24:16.294029 ==
1401 01:24:16.297196 Dram Type= 6, Freq= 0, CH_1, rank 1
1402 01:24:16.304013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 01:24:16.304099 ==
1404 01:24:16.307902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 01:24:16.313793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 01:24:16.323577 [CA 0] Center 37 (6~68) winsize 63
1407 01:24:16.326634 [CA 1] Center 37 (6~68) winsize 63
1408 01:24:16.330043 [CA 2] Center 35 (5~66) winsize 62
1409 01:24:16.333804 [CA 3] Center 34 (4~65) winsize 62
1410 01:24:16.337199 [CA 4] Center 34 (4~65) winsize 62
1411 01:24:16.340236 [CA 5] Center 34 (4~64) winsize 61
1412 01:24:16.340357
1413 01:24:16.343545 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1414 01:24:16.343665
1415 01:24:16.347191 [CATrainingPosCal] consider 2 rank data
1416 01:24:16.350302 u2DelayCellTimex100 = 270/100 ps
1417 01:24:16.353742 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 01:24:16.356772 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 01:24:16.363852 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1420 01:24:16.366744 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 01:24:16.370473 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 01:24:16.374058 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 01:24:16.374142
1424 01:24:16.377785 CA PerBit enable=1, Macro0, CA PI delay=34
1425 01:24:16.377869
1426 01:24:16.381243 [CBTSetCACLKResult] CA Dly = 34
1427 01:24:16.381326 CS Dly: 5 (0~38)
1428 01:24:16.381399
1429 01:24:16.385296 ----->DramcWriteLeveling(PI) begin...
1430 01:24:16.385381 ==
1431 01:24:16.389225 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 01:24:16.392763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 01:24:16.392863 ==
1434 01:24:16.396307 Write leveling (Byte 0): 27 => 27
1435 01:24:16.400222 Write leveling (Byte 1): 28 => 28
1436 01:24:16.400310 DramcWriteLeveling(PI) end<-----
1437 01:24:16.404146
1438 01:24:16.404229 ==
1439 01:24:16.407390 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 01:24:16.410872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 01:24:16.410960 ==
1442 01:24:16.414048 [Gating] SW mode calibration
1443 01:24:16.420739 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1444 01:24:16.424122 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1445 01:24:16.431329 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1446 01:24:16.434661 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1447 01:24:16.437658 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 01:24:16.440971 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 01:24:16.447745 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 01:24:16.450830 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 01:24:16.454386 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 01:24:16.461135 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:24:16.464218 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:24:16.467853 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:24:16.474465 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:24:16.477622 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:24:16.480943 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:24:16.487816 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:24:16.491418 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:24:16.494370 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:24:16.500994 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1462 01:24:16.504700 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1463 01:24:16.507825 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1464 01:24:16.511890 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 01:24:16.517743 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 01:24:16.521031 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:24:16.524926 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:24:16.531283 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:24:16.534803 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:24:16.537910 0 9 4 | B1->B0 | 2424 2726 | 0 1 | (0 0) (0 0)
1471 01:24:16.544646 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 01:24:16.548021 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 01:24:16.551733 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 01:24:16.558077 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 01:24:16.561801 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 01:24:16.565183 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 01:24:16.568200 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1478 01:24:16.574717 0 10 4 | B1->B0 | 2c2c 2b2b | 0 1 | (0 0) (1 0)
1479 01:24:16.578287 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1480 01:24:16.581830 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 01:24:16.588171 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 01:24:16.591424 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 01:24:16.595120 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 01:24:16.601656 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 01:24:16.604933 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:24:16.608232 0 11 4 | B1->B0 | 3434 3939 | 1 0 | (0 0) (0 0)
1487 01:24:16.614901 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 01:24:16.618547 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 01:24:16.621694 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 01:24:16.628905 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 01:24:16.632034 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 01:24:16.634939 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 01:24:16.641779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:24:16.645136 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1495 01:24:16.648213 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 01:24:16.651564 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 01:24:16.658307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 01:24:16.661676 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:24:16.664934 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:24:16.671815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:24:16.675057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:24:16.678788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:24:16.685139 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:24:16.688312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:24:16.692055 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:24:16.698369 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:24:16.702535 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:24:16.705142 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:24:16.712096 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1510 01:24:16.715026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1511 01:24:16.718684 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 01:24:16.721851 Total UI for P1: 0, mck2ui 16
1513 01:24:16.725201 best dqsien dly found for B0: ( 0, 14, 2)
1514 01:24:16.728558 Total UI for P1: 0, mck2ui 16
1515 01:24:16.732140 best dqsien dly found for B1: ( 0, 14, 2)
1516 01:24:16.735449 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1517 01:24:16.738898 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1518 01:24:16.738983
1519 01:24:16.741958 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1520 01:24:16.745354 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1521 01:24:16.748841 [Gating] SW calibration Done
1522 01:24:16.748925 ==
1523 01:24:16.751896 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 01:24:16.758458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 01:24:16.758545 ==
1526 01:24:16.758613 RX Vref Scan: 0
1527 01:24:16.758678
1528 01:24:16.761860 RX Vref 0 -> 0, step: 1
1529 01:24:16.761945
1530 01:24:16.765341 RX Delay -130 -> 252, step: 16
1531 01:24:16.768622 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1532 01:24:16.772141 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1533 01:24:16.775447 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1534 01:24:16.778605 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1535 01:24:16.785245 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1536 01:24:16.788609 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1537 01:24:16.792022 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1538 01:24:16.795485 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1539 01:24:16.798721 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1540 01:24:16.802905 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1541 01:24:16.809050 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1542 01:24:16.812185 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1543 01:24:16.815463 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1544 01:24:16.818878 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1545 01:24:16.825646 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1546 01:24:16.828993 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1547 01:24:16.829078 ==
1548 01:24:16.832222 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 01:24:16.836082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 01:24:16.836172 ==
1551 01:24:16.838857 DQS Delay:
1552 01:24:16.838941 DQS0 = 0, DQS1 = 0
1553 01:24:16.839009 DQM Delay:
1554 01:24:16.842277 DQM0 = 87, DQM1 = 80
1555 01:24:16.842362 DQ Delay:
1556 01:24:16.845662 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1557 01:24:16.848889 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1558 01:24:16.852179 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1559 01:24:16.855574 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1560 01:24:16.855658
1561 01:24:16.855726
1562 01:24:16.855788 ==
1563 01:24:16.858817 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 01:24:16.862442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 01:24:16.865556 ==
1566 01:24:16.865640
1567 01:24:16.865708
1568 01:24:16.865772 TX Vref Scan disable
1569 01:24:16.869094 == TX Byte 0 ==
1570 01:24:16.872200 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1571 01:24:16.875619 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1572 01:24:16.879037 == TX Byte 1 ==
1573 01:24:16.882190 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 01:24:16.885736 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 01:24:16.888950 ==
1576 01:24:16.889035 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 01:24:16.895927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 01:24:16.896011 ==
1579 01:24:16.907654 TX Vref=22, minBit 10, minWin=27, winSum=448
1580 01:24:16.910942 TX Vref=24, minBit 8, minWin=27, winSum=450
1581 01:24:16.914473 TX Vref=26, minBit 8, minWin=27, winSum=456
1582 01:24:16.917567 TX Vref=28, minBit 15, minWin=27, winSum=456
1583 01:24:16.921168 TX Vref=30, minBit 14, minWin=27, winSum=458
1584 01:24:16.928220 TX Vref=32, minBit 14, minWin=27, winSum=459
1585 01:24:16.931161 [TxChooseVref] Worse bit 14, Min win 27, Win sum 459, Final Vref 32
1586 01:24:16.931246
1587 01:24:16.934911 Final TX Range 1 Vref 32
1588 01:24:16.935017
1589 01:24:16.935104 ==
1590 01:24:16.937793 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 01:24:16.941784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 01:24:16.941870 ==
1593 01:24:16.944983
1594 01:24:16.945067
1595 01:24:16.945134 TX Vref Scan disable
1596 01:24:16.948196 == TX Byte 0 ==
1597 01:24:16.951128 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1598 01:24:16.954870 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1599 01:24:16.958752 == TX Byte 1 ==
1600 01:24:16.962117 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 01:24:16.965651 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 01:24:16.965735
1603 01:24:16.968770 [DATLAT]
1604 01:24:16.968867 Freq=800, CH1 RK0
1605 01:24:16.968935
1606 01:24:16.971939 DATLAT Default: 0xa
1607 01:24:16.972023 0, 0xFFFF, sum = 0
1608 01:24:16.975769 1, 0xFFFF, sum = 0
1609 01:24:16.975856 2, 0xFFFF, sum = 0
1610 01:24:16.978818 3, 0xFFFF, sum = 0
1611 01:24:16.978904 4, 0xFFFF, sum = 0
1612 01:24:16.982123 5, 0xFFFF, sum = 0
1613 01:24:16.982209 6, 0xFFFF, sum = 0
1614 01:24:16.985517 7, 0xFFFF, sum = 0
1615 01:24:16.985603 8, 0xFFFF, sum = 0
1616 01:24:16.988690 9, 0x0, sum = 1
1617 01:24:16.988822 10, 0x0, sum = 2
1618 01:24:16.992221 11, 0x0, sum = 3
1619 01:24:16.992306 12, 0x0, sum = 4
1620 01:24:16.995534 best_step = 10
1621 01:24:16.995619
1622 01:24:16.995686 ==
1623 01:24:16.999301 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 01:24:17.001968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 01:24:17.002055 ==
1626 01:24:17.002123 RX Vref Scan: 1
1627 01:24:17.005641
1628 01:24:17.005726 Set Vref Range= 32 -> 127
1629 01:24:17.005794
1630 01:24:17.008643 RX Vref 32 -> 127, step: 1
1631 01:24:17.008728
1632 01:24:17.012270 RX Delay -95 -> 252, step: 8
1633 01:24:17.012354
1634 01:24:17.015321 Set Vref, RX VrefLevel [Byte0]: 32
1635 01:24:17.018935 [Byte1]: 32
1636 01:24:17.019019
1637 01:24:17.022191 Set Vref, RX VrefLevel [Byte0]: 33
1638 01:24:17.025569 [Byte1]: 33
1639 01:24:17.025654
1640 01:24:17.028951 Set Vref, RX VrefLevel [Byte0]: 34
1641 01:24:17.032255 [Byte1]: 34
1642 01:24:17.035992
1643 01:24:17.036076 Set Vref, RX VrefLevel [Byte0]: 35
1644 01:24:17.039066 [Byte1]: 35
1645 01:24:17.043735
1646 01:24:17.043819 Set Vref, RX VrefLevel [Byte0]: 36
1647 01:24:17.047050 [Byte1]: 36
1648 01:24:17.051114
1649 01:24:17.051198 Set Vref, RX VrefLevel [Byte0]: 37
1650 01:24:17.054413 [Byte1]: 37
1651 01:24:17.059260
1652 01:24:17.059345 Set Vref, RX VrefLevel [Byte0]: 38
1653 01:24:17.062192 [Byte1]: 38
1654 01:24:17.066305
1655 01:24:17.066389 Set Vref, RX VrefLevel [Byte0]: 39
1656 01:24:17.069673 [Byte1]: 39
1657 01:24:17.073867
1658 01:24:17.073951 Set Vref, RX VrefLevel [Byte0]: 40
1659 01:24:17.077508 [Byte1]: 40
1660 01:24:17.081315
1661 01:24:17.081424 Set Vref, RX VrefLevel [Byte0]: 41
1662 01:24:17.084772 [Byte1]: 41
1663 01:24:17.089217
1664 01:24:17.089301 Set Vref, RX VrefLevel [Byte0]: 42
1665 01:24:17.092619 [Byte1]: 42
1666 01:24:17.096557
1667 01:24:17.096641 Set Vref, RX VrefLevel [Byte0]: 43
1668 01:24:17.100208 [Byte1]: 43
1669 01:24:17.104261
1670 01:24:17.104345 Set Vref, RX VrefLevel [Byte0]: 44
1671 01:24:17.108051 [Byte1]: 44
1672 01:24:17.111767
1673 01:24:17.111851 Set Vref, RX VrefLevel [Byte0]: 45
1674 01:24:17.115111 [Byte1]: 45
1675 01:24:17.119375
1676 01:24:17.119459 Set Vref, RX VrefLevel [Byte0]: 46
1677 01:24:17.122883 [Byte1]: 46
1678 01:24:17.127040
1679 01:24:17.127123 Set Vref, RX VrefLevel [Byte0]: 47
1680 01:24:17.130310 [Byte1]: 47
1681 01:24:17.134736
1682 01:24:17.134820 Set Vref, RX VrefLevel [Byte0]: 48
1683 01:24:17.137768 [Byte1]: 48
1684 01:24:17.142110
1685 01:24:17.142193 Set Vref, RX VrefLevel [Byte0]: 49
1686 01:24:17.145676 [Byte1]: 49
1687 01:24:17.150363
1688 01:24:17.150446 Set Vref, RX VrefLevel [Byte0]: 50
1689 01:24:17.153033 [Byte1]: 50
1690 01:24:17.157406
1691 01:24:17.157489 Set Vref, RX VrefLevel [Byte0]: 51
1692 01:24:17.160695 [Byte1]: 51
1693 01:24:17.165013
1694 01:24:17.165097 Set Vref, RX VrefLevel [Byte0]: 52
1695 01:24:17.168178 [Byte1]: 52
1696 01:24:17.172712
1697 01:24:17.172807 Set Vref, RX VrefLevel [Byte0]: 53
1698 01:24:17.175948 [Byte1]: 53
1699 01:24:17.180118
1700 01:24:17.180200 Set Vref, RX VrefLevel [Byte0]: 54
1701 01:24:17.183392 [Byte1]: 54
1702 01:24:17.187863
1703 01:24:17.187946 Set Vref, RX VrefLevel [Byte0]: 55
1704 01:24:17.191031 [Byte1]: 55
1705 01:24:17.195438
1706 01:24:17.195521 Set Vref, RX VrefLevel [Byte0]: 56
1707 01:24:17.198663 [Byte1]: 56
1708 01:24:17.203033
1709 01:24:17.203116 Set Vref, RX VrefLevel [Byte0]: 57
1710 01:24:17.206381 [Byte1]: 57
1711 01:24:17.210536
1712 01:24:17.210620 Set Vref, RX VrefLevel [Byte0]: 58
1713 01:24:17.213745 [Byte1]: 58
1714 01:24:17.218049
1715 01:24:17.218133 Set Vref, RX VrefLevel [Byte0]: 59
1716 01:24:17.221545 [Byte1]: 59
1717 01:24:17.225625
1718 01:24:17.225712 Set Vref, RX VrefLevel [Byte0]: 60
1719 01:24:17.228960 [Byte1]: 60
1720 01:24:17.233759
1721 01:24:17.233843 Set Vref, RX VrefLevel [Byte0]: 61
1722 01:24:17.236683 [Byte1]: 61
1723 01:24:17.240986
1724 01:24:17.241069 Set Vref, RX VrefLevel [Byte0]: 62
1725 01:24:17.244299 [Byte1]: 62
1726 01:24:17.248668
1727 01:24:17.248777 Set Vref, RX VrefLevel [Byte0]: 63
1728 01:24:17.251762 [Byte1]: 63
1729 01:24:17.256695
1730 01:24:17.256814 Set Vref, RX VrefLevel [Byte0]: 64
1731 01:24:17.259448 [Byte1]: 64
1732 01:24:17.263645
1733 01:24:17.263728 Set Vref, RX VrefLevel [Byte0]: 65
1734 01:24:17.267464 [Byte1]: 65
1735 01:24:17.271549
1736 01:24:17.271632 Set Vref, RX VrefLevel [Byte0]: 66
1737 01:24:17.274686 [Byte1]: 66
1738 01:24:17.278943
1739 01:24:17.279027 Set Vref, RX VrefLevel [Byte0]: 67
1740 01:24:17.282350 [Byte1]: 67
1741 01:24:17.286664
1742 01:24:17.286748 Set Vref, RX VrefLevel [Byte0]: 68
1743 01:24:17.289690 [Byte1]: 68
1744 01:24:17.294326
1745 01:24:17.294409 Set Vref, RX VrefLevel [Byte0]: 69
1746 01:24:17.297505 [Byte1]: 69
1747 01:24:17.302293
1748 01:24:17.302376 Set Vref, RX VrefLevel [Byte0]: 70
1749 01:24:17.304958 [Byte1]: 70
1750 01:24:17.309385
1751 01:24:17.309469 Set Vref, RX VrefLevel [Byte0]: 71
1752 01:24:17.312489 [Byte1]: 71
1753 01:24:17.316933
1754 01:24:17.317017 Set Vref, RX VrefLevel [Byte0]: 72
1755 01:24:17.320450 [Byte1]: 72
1756 01:24:17.324738
1757 01:24:17.324830 Set Vref, RX VrefLevel [Byte0]: 73
1758 01:24:17.327814 [Byte1]: 73
1759 01:24:17.332029
1760 01:24:17.332112 Set Vref, RX VrefLevel [Byte0]: 74
1761 01:24:17.335628 [Byte1]: 74
1762 01:24:17.339887
1763 01:24:17.339970 Set Vref, RX VrefLevel [Byte0]: 75
1764 01:24:17.342924 [Byte1]: 75
1765 01:24:17.347307
1766 01:24:17.347390 Set Vref, RX VrefLevel [Byte0]: 76
1767 01:24:17.350708 [Byte1]: 76
1768 01:24:17.355402
1769 01:24:17.355485 Final RX Vref Byte 0 = 52 to rank0
1770 01:24:17.358586 Final RX Vref Byte 1 = 59 to rank0
1771 01:24:17.361823 Final RX Vref Byte 0 = 52 to rank1
1772 01:24:17.364912 Final RX Vref Byte 1 = 59 to rank1==
1773 01:24:17.368286 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 01:24:17.374994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 01:24:17.375078 ==
1776 01:24:17.375145 DQS Delay:
1777 01:24:17.375207 DQS0 = 0, DQS1 = 0
1778 01:24:17.378519 DQM Delay:
1779 01:24:17.378602 DQM0 = 93, DQM1 = 82
1780 01:24:17.381963 DQ Delay:
1781 01:24:17.385013 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1782 01:24:17.388585 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1783 01:24:17.388669 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1784 01:24:17.394889 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1785 01:24:17.395019
1786 01:24:17.395137
1787 01:24:17.402129 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1788 01:24:17.404954 CH1 RK0: MR19=606, MR18=304D
1789 01:24:17.411926 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1790 01:24:17.412050
1791 01:24:17.414867 ----->DramcWriteLeveling(PI) begin...
1792 01:24:17.414992 ==
1793 01:24:17.418821 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 01:24:17.421720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 01:24:17.421846 ==
1796 01:24:17.425095 Write leveling (Byte 0): 28 => 28
1797 01:24:17.428250 Write leveling (Byte 1): 29 => 29
1798 01:24:17.431755 DramcWriteLeveling(PI) end<-----
1799 01:24:17.431840
1800 01:24:17.431907 ==
1801 01:24:17.435212 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 01:24:17.438824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 01:24:17.438916 ==
1804 01:24:17.442046 [Gating] SW mode calibration
1805 01:24:17.448546 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 01:24:17.455207 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 01:24:17.458411 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 01:24:17.462241 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1809 01:24:17.468451 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1810 01:24:17.472128 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:24:17.475314 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 01:24:17.481840 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 01:24:17.485451 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 01:24:17.488798 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 01:24:17.492198 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:24:17.498963 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:24:17.502343 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:24:17.505480 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:24:17.512229 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:24:17.515726 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:24:17.519004 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:24:17.525468 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 01:24:17.529149 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 01:24:17.532472 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1825 01:24:17.539011 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:24:17.542266 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:24:17.545917 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:24:17.548998 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 01:24:17.555887 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 01:24:17.559109 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:24:17.562636 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:24:17.569011 0 9 4 | B1->B0 | 2929 2727 | 1 1 | (0 0) (1 1)
1833 01:24:17.572385 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1834 01:24:17.576177 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 01:24:17.582468 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 01:24:17.586050 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 01:24:17.589222 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 01:24:17.596217 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 01:24:17.599567 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 01:24:17.602459 0 10 4 | B1->B0 | 2f2f 3131 | 0 0 | (1 0) (0 0)
1841 01:24:17.609162 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 01:24:17.612769 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 01:24:17.616223 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 01:24:17.622840 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 01:24:17.625590 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 01:24:17.629107 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 01:24:17.635773 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 01:24:17.638973 0 11 4 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 0)
1849 01:24:17.642469 0 11 8 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
1850 01:24:17.645699 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 01:24:17.652424 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 01:24:17.655883 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 01:24:17.659113 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 01:24:17.665933 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 01:24:17.669497 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 01:24:17.672549 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1857 01:24:17.679280 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 01:24:17.683148 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 01:24:17.686443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 01:24:17.692847 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 01:24:17.696030 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 01:24:17.699545 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 01:24:17.702920 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 01:24:17.709508 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 01:24:17.713044 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 01:24:17.716096 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 01:24:17.722798 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 01:24:17.726187 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 01:24:17.730049 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 01:24:17.737204 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 01:24:17.739645 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 01:24:17.743106 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1873 01:24:17.746344 Total UI for P1: 0, mck2ui 16
1874 01:24:17.749769 best dqsien dly found for B1: ( 0, 14, 2)
1875 01:24:17.756864 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 01:24:17.756966 Total UI for P1: 0, mck2ui 16
1877 01:24:17.759833 best dqsien dly found for B0: ( 0, 14, 4)
1878 01:24:17.767079 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1879 01:24:17.769826 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1880 01:24:17.769910
1881 01:24:17.773247 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 01:24:17.776362 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1883 01:24:17.779982 [Gating] SW calibration Done
1884 01:24:17.780067 ==
1885 01:24:17.783163 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 01:24:17.786336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1887 01:24:17.786421 ==
1888 01:24:17.786488 RX Vref Scan: 0
1889 01:24:17.789857
1890 01:24:17.789940 RX Vref 0 -> 0, step: 1
1891 01:24:17.790008
1892 01:24:17.793532 RX Delay -130 -> 252, step: 16
1893 01:24:17.796717 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1894 01:24:17.800274 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1895 01:24:17.806718 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1896 01:24:17.810106 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1897 01:24:17.813409 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1898 01:24:17.816771 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1899 01:24:17.820412 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1900 01:24:17.823466 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1901 01:24:17.830477 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1902 01:24:17.833474 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1903 01:24:17.837036 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1904 01:24:17.840212 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1905 01:24:17.847072 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1906 01:24:17.850240 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1907 01:24:17.853484 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1908 01:24:17.856962 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1909 01:24:17.857047 ==
1910 01:24:17.859952 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 01:24:17.863932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 01:24:17.867144 ==
1913 01:24:17.867227 DQS Delay:
1914 01:24:17.867293 DQS0 = 0, DQS1 = 0
1915 01:24:17.870251 DQM Delay:
1916 01:24:17.870335 DQM0 = 91, DQM1 = 81
1917 01:24:17.873469 DQ Delay:
1918 01:24:17.876714 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =93
1919 01:24:17.880012 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1920 01:24:17.880138 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1921 01:24:17.886745 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1922 01:24:17.886869
1923 01:24:17.886980
1924 01:24:17.887092 ==
1925 01:24:17.890755 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 01:24:17.893509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 01:24:17.893614 ==
1928 01:24:17.893709
1929 01:24:17.893799
1930 01:24:17.896655 TX Vref Scan disable
1931 01:24:17.896760 == TX Byte 0 ==
1932 01:24:17.903412 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1933 01:24:17.906826 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1934 01:24:17.906910 == TX Byte 1 ==
1935 01:24:17.913773 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1936 01:24:17.916868 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1937 01:24:17.916953 ==
1938 01:24:17.920212 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 01:24:17.923483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 01:24:17.923611 ==
1941 01:24:17.936936 TX Vref=22, minBit 13, minWin=27, winSum=450
1942 01:24:17.940419 TX Vref=24, minBit 15, minWin=27, winSum=457
1943 01:24:17.943628 TX Vref=26, minBit 13, minWin=27, winSum=454
1944 01:24:17.946953 TX Vref=28, minBit 13, minWin=27, winSum=457
1945 01:24:17.950204 TX Vref=30, minBit 8, minWin=28, winSum=459
1946 01:24:17.957456 TX Vref=32, minBit 9, minWin=27, winSum=457
1947 01:24:17.960381 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1948 01:24:17.960504
1949 01:24:17.963922 Final TX Range 1 Vref 30
1950 01:24:17.964027
1951 01:24:17.964121 ==
1952 01:24:17.967066 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 01:24:17.970344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 01:24:17.970428 ==
1955 01:24:17.974355
1956 01:24:17.974438
1957 01:24:17.974505 TX Vref Scan disable
1958 01:24:17.977455 == TX Byte 0 ==
1959 01:24:17.980511 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1960 01:24:17.983700 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1961 01:24:17.987283 == TX Byte 1 ==
1962 01:24:17.990422 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1963 01:24:17.993909 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1964 01:24:17.997301
1965 01:24:17.997384 [DATLAT]
1966 01:24:17.997451 Freq=800, CH1 RK1
1967 01:24:17.997515
1968 01:24:18.000796 DATLAT Default: 0xa
1969 01:24:18.000880 0, 0xFFFF, sum = 0
1970 01:24:18.005025 1, 0xFFFF, sum = 0
1971 01:24:18.005111 2, 0xFFFF, sum = 0
1972 01:24:18.007385 3, 0xFFFF, sum = 0
1973 01:24:18.007470 4, 0xFFFF, sum = 0
1974 01:24:18.010685 5, 0xFFFF, sum = 0
1975 01:24:18.010771 6, 0xFFFF, sum = 0
1976 01:24:18.014289 7, 0xFFFF, sum = 0
1977 01:24:18.014375 8, 0xFFFF, sum = 0
1978 01:24:18.017633 9, 0x0, sum = 1
1979 01:24:18.017719 10, 0x0, sum = 2
1980 01:24:18.020737 11, 0x0, sum = 3
1981 01:24:18.020842 12, 0x0, sum = 4
1982 01:24:18.024193 best_step = 10
1983 01:24:18.024277
1984 01:24:18.024343 ==
1985 01:24:18.027302 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 01:24:18.030515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 01:24:18.030600 ==
1988 01:24:18.034595 RX Vref Scan: 0
1989 01:24:18.034678
1990 01:24:18.034744 RX Vref 0 -> 0, step: 1
1991 01:24:18.034807
1992 01:24:18.037905 RX Delay -95 -> 252, step: 8
1993 01:24:18.044085 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1994 01:24:18.047488 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1995 01:24:18.050659 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1996 01:24:18.054166 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1997 01:24:18.057673 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1998 01:24:18.061052 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1999 01:24:18.068455 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2000 01:24:18.070924 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2001 01:24:18.074328 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2002 01:24:18.077637 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2003 01:24:18.081058 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2004 01:24:18.087642 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2005 01:24:18.091358 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2006 01:24:18.094712 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2007 01:24:18.098185 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2008 01:24:18.101150 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2009 01:24:18.101234 ==
2010 01:24:18.104878 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 01:24:18.111155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 01:24:18.111240 ==
2013 01:24:18.111307 DQS Delay:
2014 01:24:18.114860 DQS0 = 0, DQS1 = 0
2015 01:24:18.114944 DQM Delay:
2016 01:24:18.115011 DQM0 = 91, DQM1 = 83
2017 01:24:18.117911 DQ Delay:
2018 01:24:18.121239 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2019 01:24:18.124407 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2020 01:24:18.127824 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2021 01:24:18.131614 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2022 01:24:18.131697
2023 01:24:18.131764
2024 01:24:18.138145 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2025 01:24:18.141184 CH1 RK1: MR19=606, MR18=3B12
2026 01:24:18.147953 CH1_RK1: MR19=0x606, MR18=0x3B12, DQSOSC=394, MR23=63, INC=95, DEC=63
2027 01:24:18.151325 [RxdqsGatingPostProcess] freq 800
2028 01:24:18.154433 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2029 01:24:18.158277 Pre-setting of DQS Precalculation
2030 01:24:18.165031 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2031 01:24:18.171311 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2032 01:24:18.178043 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2033 01:24:18.178128
2034 01:24:18.178194
2035 01:24:18.181425 [Calibration Summary] 1600 Mbps
2036 01:24:18.181546 CH 0, Rank 0
2037 01:24:18.184581 SW Impedance : PASS
2038 01:24:18.187935 DUTY Scan : NO K
2039 01:24:18.188057 ZQ Calibration : PASS
2040 01:24:18.191225 Jitter Meter : NO K
2041 01:24:18.194719 CBT Training : PASS
2042 01:24:18.194824 Write leveling : PASS
2043 01:24:18.198221 RX DQS gating : PASS
2044 01:24:18.201320 RX DQ/DQS(RDDQC) : PASS
2045 01:24:18.201417 TX DQ/DQS : PASS
2046 01:24:18.204718 RX DATLAT : PASS
2047 01:24:18.208100 RX DQ/DQS(Engine): PASS
2048 01:24:18.208183 TX OE : NO K
2049 01:24:18.208250 All Pass.
2050 01:24:18.211428
2051 01:24:18.211510 CH 0, Rank 1
2052 01:24:18.211577 SW Impedance : PASS
2053 01:24:18.214934 DUTY Scan : NO K
2054 01:24:18.218175 ZQ Calibration : PASS
2055 01:24:18.218258 Jitter Meter : NO K
2056 01:24:18.221872 CBT Training : PASS
2057 01:24:18.224707 Write leveling : PASS
2058 01:24:18.224798 RX DQS gating : PASS
2059 01:24:18.228457 RX DQ/DQS(RDDQC) : PASS
2060 01:24:18.231695 TX DQ/DQS : PASS
2061 01:24:18.231778 RX DATLAT : PASS
2062 01:24:18.234819 RX DQ/DQS(Engine): PASS
2063 01:24:18.238290 TX OE : NO K
2064 01:24:18.238373 All Pass.
2065 01:24:18.238439
2066 01:24:18.238500 CH 1, Rank 0
2067 01:24:18.241470 SW Impedance : PASS
2068 01:24:18.244880 DUTY Scan : NO K
2069 01:24:18.244963 ZQ Calibration : PASS
2070 01:24:18.248061 Jitter Meter : NO K
2071 01:24:18.251736 CBT Training : PASS
2072 01:24:18.251819 Write leveling : PASS
2073 01:24:18.254725 RX DQS gating : PASS
2074 01:24:18.254808 RX DQ/DQS(RDDQC) : PASS
2075 01:24:18.258596 TX DQ/DQS : PASS
2076 01:24:18.261371 RX DATLAT : PASS
2077 01:24:18.261454 RX DQ/DQS(Engine): PASS
2078 01:24:18.264702 TX OE : NO K
2079 01:24:18.264806 All Pass.
2080 01:24:18.264872
2081 01:24:18.267910 CH 1, Rank 1
2082 01:24:18.267992 SW Impedance : PASS
2083 01:24:18.271469 DUTY Scan : NO K
2084 01:24:18.274722 ZQ Calibration : PASS
2085 01:24:18.274806 Jitter Meter : NO K
2086 01:24:18.278086 CBT Training : PASS
2087 01:24:18.281242 Write leveling : PASS
2088 01:24:18.281325 RX DQS gating : PASS
2089 01:24:18.284909 RX DQ/DQS(RDDQC) : PASS
2090 01:24:18.287825 TX DQ/DQS : PASS
2091 01:24:18.287909 RX DATLAT : PASS
2092 01:24:18.291282 RX DQ/DQS(Engine): PASS
2093 01:24:18.295021 TX OE : NO K
2094 01:24:18.295103 All Pass.
2095 01:24:18.295170
2096 01:24:18.295230 DramC Write-DBI off
2097 01:24:18.297895 PER_BANK_REFRESH: Hybrid Mode
2098 01:24:18.301266 TX_TRACKING: ON
2099 01:24:18.305073 [GetDramInforAfterCalByMRR] Vendor 6.
2100 01:24:18.308054 [GetDramInforAfterCalByMRR] Revision 606.
2101 01:24:18.311954 [GetDramInforAfterCalByMRR] Revision 2 0.
2102 01:24:18.312036 MR0 0x3b3b
2103 01:24:18.314424 MR8 0x5151
2104 01:24:18.318006 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 01:24:18.318090
2106 01:24:18.318156 MR0 0x3b3b
2107 01:24:18.318220 MR8 0x5151
2108 01:24:18.321363 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 01:24:18.321446
2110 01:24:18.331319 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2111 01:24:18.334672 [FAST_K] Save calibration result to emmc
2112 01:24:18.337904 [FAST_K] Save calibration result to emmc
2113 01:24:18.341222 dram_init: config_dvfs: 1
2114 01:24:18.344693 dramc_set_vcore_voltage set vcore to 662500
2115 01:24:18.347843 Read voltage for 1200, 2
2116 01:24:18.347971 Vio18 = 0
2117 01:24:18.351247 Vcore = 662500
2118 01:24:18.351366 Vdram = 0
2119 01:24:18.351484 Vddq = 0
2120 01:24:18.351590 Vmddr = 0
2121 01:24:18.358160 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2122 01:24:18.361433 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2123 01:24:18.364693 MEM_TYPE=3, freq_sel=15
2124 01:24:18.368105 sv_algorithm_assistance_LP4_1600
2125 01:24:18.371504 ============ PULL DRAM RESETB DOWN ============
2126 01:24:18.374922 ========== PULL DRAM RESETB DOWN end =========
2127 01:24:18.381289 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 01:24:18.385003 ===================================
2129 01:24:18.388107 LPDDR4 DRAM CONFIGURATION
2130 01:24:18.391372 ===================================
2131 01:24:18.391494 EX_ROW_EN[0] = 0x0
2132 01:24:18.394711 EX_ROW_EN[1] = 0x0
2133 01:24:18.394832 LP4Y_EN = 0x0
2134 01:24:18.398534 WORK_FSP = 0x0
2135 01:24:18.398654 WL = 0x4
2136 01:24:18.401441 RL = 0x4
2137 01:24:18.401562 BL = 0x2
2138 01:24:18.404829 RPST = 0x0
2139 01:24:18.404950 RD_PRE = 0x0
2140 01:24:18.408365 WR_PRE = 0x1
2141 01:24:18.408486 WR_PST = 0x0
2142 01:24:18.411621 DBI_WR = 0x0
2143 01:24:18.411742 DBI_RD = 0x0
2144 01:24:18.415279 OTF = 0x1
2145 01:24:18.418095 ===================================
2146 01:24:18.421650 ===================================
2147 01:24:18.421774 ANA top config
2148 01:24:18.424725 ===================================
2149 01:24:18.428302 DLL_ASYNC_EN = 0
2150 01:24:18.431601 ALL_SLAVE_EN = 0
2151 01:24:18.435017 NEW_RANK_MODE = 1
2152 01:24:18.435144 DLL_IDLE_MODE = 1
2153 01:24:18.438436 LP45_APHY_COMB_EN = 1
2154 01:24:18.441561 TX_ODT_DIS = 1
2155 01:24:18.444907 NEW_8X_MODE = 1
2156 01:24:18.448201 ===================================
2157 01:24:18.451511 ===================================
2158 01:24:18.454683 data_rate = 2400
2159 01:24:18.454805 CKR = 1
2160 01:24:18.458224 DQ_P2S_RATIO = 8
2161 01:24:18.461605 ===================================
2162 01:24:18.464973 CA_P2S_RATIO = 8
2163 01:24:18.468254 DQ_CA_OPEN = 0
2164 01:24:18.471793 DQ_SEMI_OPEN = 0
2165 01:24:18.471909 CA_SEMI_OPEN = 0
2166 01:24:18.474641 CA_FULL_RATE = 0
2167 01:24:18.478546 DQ_CKDIV4_EN = 0
2168 01:24:18.481564 CA_CKDIV4_EN = 0
2169 01:24:18.484745 CA_PREDIV_EN = 0
2170 01:24:18.488886 PH8_DLY = 17
2171 01:24:18.489009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2172 01:24:18.491375 DQ_AAMCK_DIV = 4
2173 01:24:18.495017 CA_AAMCK_DIV = 4
2174 01:24:18.498099 CA_ADMCK_DIV = 4
2175 01:24:18.501436 DQ_TRACK_CA_EN = 0
2176 01:24:18.504875 CA_PICK = 1200
2177 01:24:18.508345 CA_MCKIO = 1200
2178 01:24:18.508467 MCKIO_SEMI = 0
2179 01:24:18.511717 PLL_FREQ = 2366
2180 01:24:18.514908 DQ_UI_PI_RATIO = 32
2181 01:24:18.518353 CA_UI_PI_RATIO = 0
2182 01:24:18.522313 ===================================
2183 01:24:18.525217 ===================================
2184 01:24:18.528460 memory_type:LPDDR4
2185 01:24:18.528582 GP_NUM : 10
2186 01:24:18.531549 SRAM_EN : 1
2187 01:24:18.531668 MD32_EN : 0
2188 01:24:18.535186 ===================================
2189 01:24:18.538385 [ANA_INIT] >>>>>>>>>>>>>>
2190 01:24:18.541634 <<<<<< [CONFIGURE PHASE]: ANA_TX
2191 01:24:18.545656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2192 01:24:18.548654 ===================================
2193 01:24:18.551935 data_rate = 2400,PCW = 0X5b00
2194 01:24:18.555297 ===================================
2195 01:24:18.558329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2196 01:24:18.565305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 01:24:18.568299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 01:24:18.575369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2199 01:24:18.578725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2200 01:24:18.581709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2201 01:24:18.581836 [ANA_INIT] flow start
2202 01:24:18.585563 [ANA_INIT] PLL >>>>>>>>
2203 01:24:18.588497 [ANA_INIT] PLL <<<<<<<<
2204 01:24:18.588617 [ANA_INIT] MIDPI >>>>>>>>
2205 01:24:18.591915 [ANA_INIT] MIDPI <<<<<<<<
2206 01:24:18.595427 [ANA_INIT] DLL >>>>>>>>
2207 01:24:18.595549 [ANA_INIT] DLL <<<<<<<<
2208 01:24:18.598639 [ANA_INIT] flow end
2209 01:24:18.602092 ============ LP4 DIFF to SE enter ============
2210 01:24:18.605202 ============ LP4 DIFF to SE exit ============
2211 01:24:18.608704 [ANA_INIT] <<<<<<<<<<<<<
2212 01:24:18.611882 [Flow] Enable top DCM control >>>>>
2213 01:24:18.615452 [Flow] Enable top DCM control <<<<<
2214 01:24:18.618598 Enable DLL master slave shuffle
2215 01:24:18.625293 ==============================================================
2216 01:24:18.625418 Gating Mode config
2217 01:24:18.631926 ==============================================================
2218 01:24:18.632053 Config description:
2219 01:24:18.641873 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2220 01:24:18.648511 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2221 01:24:18.655201 SELPH_MODE 0: By rank 1: By Phase
2222 01:24:18.658940 ==============================================================
2223 01:24:18.662056 GAT_TRACK_EN = 1
2224 01:24:18.665801 RX_GATING_MODE = 2
2225 01:24:18.668650 RX_GATING_TRACK_MODE = 2
2226 01:24:18.671807 SELPH_MODE = 1
2227 01:24:18.675594 PICG_EARLY_EN = 1
2228 01:24:18.678810 VALID_LAT_VALUE = 1
2229 01:24:18.682165 ==============================================================
2230 01:24:18.685885 Enter into Gating configuration >>>>
2231 01:24:18.688732 Exit from Gating configuration <<<<
2232 01:24:18.692211 Enter into DVFS_PRE_config >>>>>
2233 01:24:18.705507 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2234 01:24:18.705638 Exit from DVFS_PRE_config <<<<<
2235 01:24:18.708959 Enter into PICG configuration >>>>
2236 01:24:18.712164 Exit from PICG configuration <<<<
2237 01:24:18.715632 [RX_INPUT] configuration >>>>>
2238 01:24:18.719520 [RX_INPUT] configuration <<<<<
2239 01:24:18.725923 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2240 01:24:18.729029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2241 01:24:18.735646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 01:24:18.742284 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 01:24:18.749195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 01:24:18.756303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 01:24:18.759197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2246 01:24:18.762311 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2247 01:24:18.765855 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2248 01:24:18.772397 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2249 01:24:18.775945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2250 01:24:18.779112 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2251 01:24:18.782707 ===================================
2252 01:24:18.785894 LPDDR4 DRAM CONFIGURATION
2253 01:24:18.789137 ===================================
2254 01:24:18.789222 EX_ROW_EN[0] = 0x0
2255 01:24:18.792757 EX_ROW_EN[1] = 0x0
2256 01:24:18.792841 LP4Y_EN = 0x0
2257 01:24:18.796055 WORK_FSP = 0x0
2258 01:24:18.796139 WL = 0x4
2259 01:24:18.799157 RL = 0x4
2260 01:24:18.799241 BL = 0x2
2261 01:24:18.802833 RPST = 0x0
2262 01:24:18.802917 RD_PRE = 0x0
2263 01:24:18.805839 WR_PRE = 0x1
2264 01:24:18.809504 WR_PST = 0x0
2265 01:24:18.809587 DBI_WR = 0x0
2266 01:24:18.812926 DBI_RD = 0x0
2267 01:24:18.813009 OTF = 0x1
2268 01:24:18.815980 ===================================
2269 01:24:18.819497 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2270 01:24:18.822801 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2271 01:24:18.829498 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2272 01:24:18.832936 ===================================
2273 01:24:18.833067 LPDDR4 DRAM CONFIGURATION
2274 01:24:18.836328 ===================================
2275 01:24:18.839803 EX_ROW_EN[0] = 0x10
2276 01:24:18.842943 EX_ROW_EN[1] = 0x0
2277 01:24:18.843071 LP4Y_EN = 0x0
2278 01:24:18.846096 WORK_FSP = 0x0
2279 01:24:18.846210 WL = 0x4
2280 01:24:18.849876 RL = 0x4
2281 01:24:18.849997 BL = 0x2
2282 01:24:18.852690 RPST = 0x0
2283 01:24:18.852815 RD_PRE = 0x0
2284 01:24:18.856522 WR_PRE = 0x1
2285 01:24:18.856642 WR_PST = 0x0
2286 01:24:18.859731 DBI_WR = 0x0
2287 01:24:18.859852 DBI_RD = 0x0
2288 01:24:18.863201 OTF = 0x1
2289 01:24:18.866526 ===================================
2290 01:24:18.872850 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2291 01:24:18.872974 ==
2292 01:24:18.876140 Dram Type= 6, Freq= 0, CH_0, rank 0
2293 01:24:18.879872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2294 01:24:18.879996 ==
2295 01:24:18.883017 [Duty_Offset_Calibration]
2296 01:24:18.883138 B0:2 B1:0 CA:1
2297 01:24:18.883245
2298 01:24:18.886461 [DutyScan_Calibration_Flow] k_type=0
2299 01:24:18.895561
2300 01:24:18.895641 ==CLK 0==
2301 01:24:18.899229 Final CLK duty delay cell = -4
2302 01:24:18.902373 [-4] MAX Duty = 5062%(X100), DQS PI = 22
2303 01:24:18.905560 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2304 01:24:18.909007 [-4] AVG Duty = 4968%(X100)
2305 01:24:18.909087
2306 01:24:18.912309 CH0 CLK Duty spec in!! Max-Min= 187%
2307 01:24:18.915649 [DutyScan_Calibration_Flow] ====Done====
2308 01:24:18.915730
2309 01:24:18.918808 [DutyScan_Calibration_Flow] k_type=1
2310 01:24:18.934754
2311 01:24:18.934835 ==DQS 0 ==
2312 01:24:18.938274 Final DQS duty delay cell = 0
2313 01:24:18.941130 [0] MAX Duty = 5187%(X100), DQS PI = 30
2314 01:24:18.944538 [0] MIN Duty = 4938%(X100), DQS PI = 0
2315 01:24:18.944619 [0] AVG Duty = 5062%(X100)
2316 01:24:18.947736
2317 01:24:18.947817 ==DQS 1 ==
2318 01:24:18.951209 Final DQS duty delay cell = -4
2319 01:24:18.954575 [-4] MAX Duty = 5093%(X100), DQS PI = 18
2320 01:24:18.957860 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2321 01:24:18.961890 [-4] AVG Duty = 5015%(X100)
2322 01:24:18.961971
2323 01:24:18.964894 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2324 01:24:18.964967
2325 01:24:18.968292 CH0 DQS 1 Duty spec in!! Max-Min= 155%
2326 01:24:18.971476 [DutyScan_Calibration_Flow] ====Done====
2327 01:24:18.971556
2328 01:24:18.974593 [DutyScan_Calibration_Flow] k_type=3
2329 01:24:18.991351
2330 01:24:18.991475 ==DQM 0 ==
2331 01:24:18.994489 Final DQM duty delay cell = 0
2332 01:24:18.997860 [0] MAX Duty = 5062%(X100), DQS PI = 24
2333 01:24:19.001685 [0] MIN Duty = 4813%(X100), DQS PI = 2
2334 01:24:19.001804 [0] AVG Duty = 4937%(X100)
2335 01:24:19.004530
2336 01:24:19.004646 ==DQM 1 ==
2337 01:24:19.007875 Final DQM duty delay cell = 0
2338 01:24:19.011261 [0] MAX Duty = 5187%(X100), DQS PI = 48
2339 01:24:19.014443 [0] MIN Duty = 5000%(X100), DQS PI = 22
2340 01:24:19.014561 [0] AVG Duty = 5093%(X100)
2341 01:24:19.018103
2342 01:24:19.021527 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2343 01:24:19.021646
2344 01:24:19.024678 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2345 01:24:19.027978 [DutyScan_Calibration_Flow] ====Done====
2346 01:24:19.028102
2347 01:24:19.031112 [DutyScan_Calibration_Flow] k_type=2
2348 01:24:19.047617
2349 01:24:19.047737 ==DQ 0 ==
2350 01:24:19.051011 Final DQ duty delay cell = -4
2351 01:24:19.054444 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2352 01:24:19.058002 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2353 01:24:19.061076 [-4] AVG Duty = 4953%(X100)
2354 01:24:19.061197
2355 01:24:19.061307 ==DQ 1 ==
2356 01:24:19.064842 Final DQ duty delay cell = 4
2357 01:24:19.068637 [4] MAX Duty = 5093%(X100), DQS PI = 4
2358 01:24:19.071101 [4] MIN Duty = 5031%(X100), DQS PI = 0
2359 01:24:19.071225 [4] AVG Duty = 5062%(X100)
2360 01:24:19.071332
2361 01:24:19.074390 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2362 01:24:19.078415
2363 01:24:19.081036 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2364 01:24:19.084905 [DutyScan_Calibration_Flow] ====Done====
2365 01:24:19.085039 ==
2366 01:24:19.087890 Dram Type= 6, Freq= 0, CH_1, rank 0
2367 01:24:19.091796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 01:24:19.091916 ==
2369 01:24:19.094599 [Duty_Offset_Calibration]
2370 01:24:19.094723 B0:0 B1:-1 CA:2
2371 01:24:19.094837
2372 01:24:19.098671 [DutyScan_Calibration_Flow] k_type=0
2373 01:24:19.108148
2374 01:24:19.108270 ==CLK 0==
2375 01:24:19.111794 Final CLK duty delay cell = 0
2376 01:24:19.114564 [0] MAX Duty = 5156%(X100), DQS PI = 12
2377 01:24:19.117802 [0] MIN Duty = 4938%(X100), DQS PI = 44
2378 01:24:19.117923 [0] AVG Duty = 5047%(X100)
2379 01:24:19.121454
2380 01:24:19.124446 CH1 CLK Duty spec in!! Max-Min= 218%
2381 01:24:19.127876 [DutyScan_Calibration_Flow] ====Done====
2382 01:24:19.127996
2383 01:24:19.131320 [DutyScan_Calibration_Flow] k_type=1
2384 01:24:19.147495
2385 01:24:19.147613 ==DQS 0 ==
2386 01:24:19.150812 Final DQS duty delay cell = 0
2387 01:24:19.153952 [0] MAX Duty = 5093%(X100), DQS PI = 24
2388 01:24:19.157448 [0] MIN Duty = 4969%(X100), DQS PI = 0
2389 01:24:19.157567 [0] AVG Duty = 5031%(X100)
2390 01:24:19.160476
2391 01:24:19.160598 ==DQS 1 ==
2392 01:24:19.163973 Final DQS duty delay cell = 0
2393 01:24:19.167430 [0] MAX Duty = 5156%(X100), DQS PI = 0
2394 01:24:19.170724 [0] MIN Duty = 4844%(X100), DQS PI = 36
2395 01:24:19.170847 [0] AVG Duty = 5000%(X100)
2396 01:24:19.170957
2397 01:24:19.177327 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2398 01:24:19.177449
2399 01:24:19.181088 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2400 01:24:19.183920 [DutyScan_Calibration_Flow] ====Done====
2401 01:24:19.184042
2402 01:24:19.187355 [DutyScan_Calibration_Flow] k_type=3
2403 01:24:19.203773
2404 01:24:19.203895 ==DQM 0 ==
2405 01:24:19.206967 Final DQM duty delay cell = 4
2406 01:24:19.210457 [4] MAX Duty = 5093%(X100), DQS PI = 6
2407 01:24:19.213796 [4] MIN Duty = 4969%(X100), DQS PI = 28
2408 01:24:19.213915 [4] AVG Duty = 5031%(X100)
2409 01:24:19.217182
2410 01:24:19.217299 ==DQM 1 ==
2411 01:24:19.220414 Final DQM duty delay cell = -4
2412 01:24:19.223770 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2413 01:24:19.227441 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2414 01:24:19.230860 [-4] AVG Duty = 4891%(X100)
2415 01:24:19.230980
2416 01:24:19.233740 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2417 01:24:19.233861
2418 01:24:19.236986 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2419 01:24:19.240681 [DutyScan_Calibration_Flow] ====Done====
2420 01:24:19.240839
2421 01:24:19.243914 [DutyScan_Calibration_Flow] k_type=2
2422 01:24:19.260611
2423 01:24:19.260728 ==DQ 0 ==
2424 01:24:19.264383 Final DQ duty delay cell = 0
2425 01:24:19.267442 [0] MAX Duty = 5062%(X100), DQS PI = 18
2426 01:24:19.270559 [0] MIN Duty = 4938%(X100), DQS PI = 0
2427 01:24:19.270680 [0] AVG Duty = 5000%(X100)
2428 01:24:19.270789
2429 01:24:19.274535 ==DQ 1 ==
2430 01:24:19.277776 Final DQ duty delay cell = 0
2431 01:24:19.280771 [0] MAX Duty = 5062%(X100), DQS PI = 4
2432 01:24:19.283989 [0] MIN Duty = 4813%(X100), DQS PI = 36
2433 01:24:19.284106 [0] AVG Duty = 4937%(X100)
2434 01:24:19.284218
2435 01:24:19.287492 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2436 01:24:19.287614
2437 01:24:19.290741 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2438 01:24:19.297474 [DutyScan_Calibration_Flow] ====Done====
2439 01:24:19.300797 nWR fixed to 30
2440 01:24:19.300917 [ModeRegInit_LP4] CH0 RK0
2441 01:24:19.304110 [ModeRegInit_LP4] CH0 RK1
2442 01:24:19.307434 [ModeRegInit_LP4] CH1 RK0
2443 01:24:19.307555 [ModeRegInit_LP4] CH1 RK1
2444 01:24:19.310958 match AC timing 7
2445 01:24:19.314220 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2446 01:24:19.317459 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2447 01:24:19.324707 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2448 01:24:19.327309 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2449 01:24:19.334185 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2450 01:24:19.334306 ==
2451 01:24:19.337580 Dram Type= 6, Freq= 0, CH_0, rank 0
2452 01:24:19.340677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 01:24:19.340830 ==
2454 01:24:19.347576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2455 01:24:19.350710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2456 01:24:19.360468 [CA 0] Center 38 (8~69) winsize 62
2457 01:24:19.363892 [CA 1] Center 38 (7~69) winsize 63
2458 01:24:19.367212 [CA 2] Center 35 (5~66) winsize 62
2459 01:24:19.370457 [CA 3] Center 35 (5~66) winsize 62
2460 01:24:19.373735 [CA 4] Center 34 (4~65) winsize 62
2461 01:24:19.377255 [CA 5] Center 33 (3~63) winsize 61
2462 01:24:19.377378
2463 01:24:19.380466 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2464 01:24:19.380584
2465 01:24:19.383619 [CATrainingPosCal] consider 1 rank data
2466 01:24:19.386879 u2DelayCellTimex100 = 270/100 ps
2467 01:24:19.390323 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2468 01:24:19.394189 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2469 01:24:19.400374 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 01:24:19.404132 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2471 01:24:19.407152 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2472 01:24:19.410679 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2473 01:24:19.410799
2474 01:24:19.414017 CA PerBit enable=1, Macro0, CA PI delay=33
2475 01:24:19.414135
2476 01:24:19.417250 [CBTSetCACLKResult] CA Dly = 33
2477 01:24:19.417370 CS Dly: 6 (0~37)
2478 01:24:19.417478 ==
2479 01:24:19.420720 Dram Type= 6, Freq= 0, CH_0, rank 1
2480 01:24:19.427269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2481 01:24:19.427389 ==
2482 01:24:19.431259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2483 01:24:19.437303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2484 01:24:19.446151 [CA 0] Center 39 (8~70) winsize 63
2485 01:24:19.449551 [CA 1] Center 38 (8~69) winsize 62
2486 01:24:19.453040 [CA 2] Center 35 (5~66) winsize 62
2487 01:24:19.456271 [CA 3] Center 35 (5~66) winsize 62
2488 01:24:19.459717 [CA 4] Center 34 (4~65) winsize 62
2489 01:24:19.462745 [CA 5] Center 34 (4~64) winsize 61
2490 01:24:19.462864
2491 01:24:19.466115 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2492 01:24:19.466242
2493 01:24:19.469786 [CATrainingPosCal] consider 2 rank data
2494 01:24:19.472741 u2DelayCellTimex100 = 270/100 ps
2495 01:24:19.476079 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2496 01:24:19.479522 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2497 01:24:19.486169 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 01:24:19.489536 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2499 01:24:19.493024 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2500 01:24:19.496136 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2501 01:24:19.496255
2502 01:24:19.499711 CA PerBit enable=1, Macro0, CA PI delay=33
2503 01:24:19.499830
2504 01:24:19.502981 [CBTSetCACLKResult] CA Dly = 33
2505 01:24:19.503100 CS Dly: 7 (0~39)
2506 01:24:19.503210
2507 01:24:19.506284 ----->DramcWriteLeveling(PI) begin...
2508 01:24:19.506406 ==
2509 01:24:19.509681 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 01:24:19.516400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 01:24:19.516523 ==
2512 01:24:19.519606 Write leveling (Byte 0): 34 => 34
2513 01:24:19.523004 Write leveling (Byte 1): 31 => 31
2514 01:24:19.523123 DramcWriteLeveling(PI) end<-----
2515 01:24:19.523237
2516 01:24:19.526336 ==
2517 01:24:19.530124 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 01:24:19.533413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 01:24:19.533534 ==
2520 01:24:19.536591 [Gating] SW mode calibration
2521 01:24:19.542951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2522 01:24:19.546295 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2523 01:24:19.553211 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2524 01:24:19.556441 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2525 01:24:19.559929 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 01:24:19.566389 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 01:24:19.569701 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 01:24:19.572994 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 01:24:19.579702 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
2530 01:24:19.583394 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2531 01:24:19.586426 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2532 01:24:19.592996 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 01:24:19.596331 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 01:24:19.599783 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 01:24:19.603156 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 01:24:19.609909 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 01:24:19.612972 1 0 24 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)
2538 01:24:19.616433 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2539 01:24:19.623010 1 1 0 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
2540 01:24:19.626349 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 01:24:19.629701 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 01:24:19.636463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 01:24:19.639920 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 01:24:19.642872 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 01:24:19.649668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 01:24:19.652981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 01:24:19.656464 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 01:24:19.663109 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 01:24:19.666326 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 01:24:19.670046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 01:24:19.676656 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 01:24:19.679949 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 01:24:19.683186 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 01:24:19.686640 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 01:24:19.693463 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 01:24:19.696480 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 01:24:19.699905 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 01:24:19.706722 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 01:24:19.709781 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 01:24:19.713474 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 01:24:19.719860 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 01:24:19.723133 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2563 01:24:19.726454 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 01:24:19.730180 Total UI for P1: 0, mck2ui 16
2565 01:24:19.733643 best dqsien dly found for B0: ( 1, 3, 26)
2566 01:24:19.739969 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 01:24:19.740092 Total UI for P1: 0, mck2ui 16
2568 01:24:19.747047 best dqsien dly found for B1: ( 1, 3, 30)
2569 01:24:19.749805 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2570 01:24:19.753165 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2571 01:24:19.753286
2572 01:24:19.756522 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2573 01:24:19.759728 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2574 01:24:19.763001 [Gating] SW calibration Done
2575 01:24:19.763121 ==
2576 01:24:19.766902 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 01:24:19.769860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 01:24:19.769980 ==
2579 01:24:19.773138 RX Vref Scan: 0
2580 01:24:19.773256
2581 01:24:19.773368 RX Vref 0 -> 0, step: 1
2582 01:24:19.773478
2583 01:24:19.776791 RX Delay -40 -> 252, step: 8
2584 01:24:19.780379 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2585 01:24:19.786520 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2586 01:24:19.789753 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2587 01:24:19.793167 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2588 01:24:19.796427 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2589 01:24:19.799974 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2590 01:24:19.806491 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2591 01:24:19.810002 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2592 01:24:19.813220 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2593 01:24:19.817053 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2594 01:24:19.819831 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2595 01:24:19.823248 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2596 01:24:19.830116 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2597 01:24:19.833223 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2598 01:24:19.836693 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2599 01:24:19.839900 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2600 01:24:19.839983 ==
2601 01:24:19.843210 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 01:24:19.850014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 01:24:19.850098 ==
2604 01:24:19.850164 DQS Delay:
2605 01:24:19.853244 DQS0 = 0, DQS1 = 0
2606 01:24:19.853327 DQM Delay:
2607 01:24:19.853393 DQM0 = 123, DQM1 = 110
2608 01:24:19.856969 DQ Delay:
2609 01:24:19.859936 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2610 01:24:19.863234 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2611 01:24:19.867000 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2612 01:24:19.870241 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2613 01:24:19.870324
2614 01:24:19.870389
2615 01:24:19.870451 ==
2616 01:24:19.873403 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 01:24:19.876624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 01:24:19.876708 ==
2619 01:24:19.880219
2620 01:24:19.880301
2621 01:24:19.880367 TX Vref Scan disable
2622 01:24:19.883681 == TX Byte 0 ==
2623 01:24:19.886756 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2624 01:24:19.890038 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2625 01:24:19.893423 == TX Byte 1 ==
2626 01:24:19.896623 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2627 01:24:19.900348 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2628 01:24:19.900431 ==
2629 01:24:19.903422 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 01:24:19.909883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 01:24:19.909966 ==
2632 01:24:19.920626 TX Vref=22, minBit 7, minWin=23, winSum=406
2633 01:24:19.923739 TX Vref=24, minBit 7, minWin=23, winSum=409
2634 01:24:19.927165 TX Vref=26, minBit 0, minWin=24, winSum=418
2635 01:24:19.930745 TX Vref=28, minBit 1, minWin=25, winSum=420
2636 01:24:19.933808 TX Vref=30, minBit 3, minWin=25, winSum=421
2637 01:24:19.937455 TX Vref=32, minBit 0, minWin=25, winSum=414
2638 01:24:19.943920 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 30
2639 01:24:19.944003
2640 01:24:19.947334 Final TX Range 1 Vref 30
2641 01:24:19.947420
2642 01:24:19.947497 ==
2643 01:24:19.950520 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 01:24:19.953981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 01:24:19.954065 ==
2646 01:24:19.954131
2647 01:24:19.957465
2648 01:24:19.957546 TX Vref Scan disable
2649 01:24:19.960669 == TX Byte 0 ==
2650 01:24:19.963905 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2651 01:24:19.968160 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2652 01:24:19.970401 == TX Byte 1 ==
2653 01:24:19.974116 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2654 01:24:19.977192 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2655 01:24:19.977275
2656 01:24:19.980701 [DATLAT]
2657 01:24:19.980804 Freq=1200, CH0 RK0
2658 01:24:19.980871
2659 01:24:19.983994 DATLAT Default: 0xd
2660 01:24:19.984077 0, 0xFFFF, sum = 0
2661 01:24:19.987642 1, 0xFFFF, sum = 0
2662 01:24:19.987727 2, 0xFFFF, sum = 0
2663 01:24:19.990798 3, 0xFFFF, sum = 0
2664 01:24:19.990883 4, 0xFFFF, sum = 0
2665 01:24:19.994205 5, 0xFFFF, sum = 0
2666 01:24:19.994289 6, 0xFFFF, sum = 0
2667 01:24:19.997590 7, 0xFFFF, sum = 0
2668 01:24:19.997674 8, 0xFFFF, sum = 0
2669 01:24:20.000702 9, 0xFFFF, sum = 0
2670 01:24:20.000821 10, 0xFFFF, sum = 0
2671 01:24:20.004085 11, 0xFFFF, sum = 0
2672 01:24:20.004168 12, 0x0, sum = 1
2673 01:24:20.007704 13, 0x0, sum = 2
2674 01:24:20.007788 14, 0x0, sum = 3
2675 01:24:20.010860 15, 0x0, sum = 4
2676 01:24:20.010944 best_step = 13
2677 01:24:20.011010
2678 01:24:20.011070 ==
2679 01:24:20.014441 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 01:24:20.021347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 01:24:20.021432 ==
2682 01:24:20.021498 RX Vref Scan: 1
2683 01:24:20.021559
2684 01:24:20.024459 Set Vref Range= 32 -> 127
2685 01:24:20.024542
2686 01:24:20.027494 RX Vref 32 -> 127, step: 1
2687 01:24:20.027577
2688 01:24:20.030874 RX Delay -13 -> 252, step: 4
2689 01:24:20.030956
2690 01:24:20.034050 Set Vref, RX VrefLevel [Byte0]: 32
2691 01:24:20.034133 [Byte1]: 32
2692 01:24:20.038738
2693 01:24:20.038820 Set Vref, RX VrefLevel [Byte0]: 33
2694 01:24:20.042005 [Byte1]: 33
2695 01:24:20.046720
2696 01:24:20.046802 Set Vref, RX VrefLevel [Byte0]: 34
2697 01:24:20.050380 [Byte1]: 34
2698 01:24:20.054658
2699 01:24:20.054740 Set Vref, RX VrefLevel [Byte0]: 35
2700 01:24:20.057987 [Byte1]: 35
2701 01:24:20.062337
2702 01:24:20.062419 Set Vref, RX VrefLevel [Byte0]: 36
2703 01:24:20.065812 [Byte1]: 36
2704 01:24:20.070343
2705 01:24:20.070426 Set Vref, RX VrefLevel [Byte0]: 37
2706 01:24:20.076873 [Byte1]: 37
2707 01:24:20.076956
2708 01:24:20.080655 Set Vref, RX VrefLevel [Byte0]: 38
2709 01:24:20.083483 [Byte1]: 38
2710 01:24:20.083565
2711 01:24:20.086881 Set Vref, RX VrefLevel [Byte0]: 39
2712 01:24:20.090547 [Byte1]: 39
2713 01:24:20.094057
2714 01:24:20.094140 Set Vref, RX VrefLevel [Byte0]: 40
2715 01:24:20.097567 [Byte1]: 40
2716 01:24:20.101817
2717 01:24:20.101900 Set Vref, RX VrefLevel [Byte0]: 41
2718 01:24:20.105074 [Byte1]: 41
2719 01:24:20.110165
2720 01:24:20.110248 Set Vref, RX VrefLevel [Byte0]: 42
2721 01:24:20.113062 [Byte1]: 42
2722 01:24:20.117610
2723 01:24:20.117694 Set Vref, RX VrefLevel [Byte0]: 43
2724 01:24:20.121027 [Byte1]: 43
2725 01:24:20.125942
2726 01:24:20.126024 Set Vref, RX VrefLevel [Byte0]: 44
2727 01:24:20.128781 [Byte1]: 44
2728 01:24:20.133485
2729 01:24:20.133608 Set Vref, RX VrefLevel [Byte0]: 45
2730 01:24:20.136686 [Byte1]: 45
2731 01:24:20.141367
2732 01:24:20.141488 Set Vref, RX VrefLevel [Byte0]: 46
2733 01:24:20.144580 [Byte1]: 46
2734 01:24:20.149102
2735 01:24:20.149222 Set Vref, RX VrefLevel [Byte0]: 47
2736 01:24:20.152487 [Byte1]: 47
2737 01:24:20.157362
2738 01:24:20.157483 Set Vref, RX VrefLevel [Byte0]: 48
2739 01:24:20.160419 [Byte1]: 48
2740 01:24:20.164913
2741 01:24:20.165031 Set Vref, RX VrefLevel [Byte0]: 49
2742 01:24:20.168257 [Byte1]: 49
2743 01:24:20.173220
2744 01:24:20.173341 Set Vref, RX VrefLevel [Byte0]: 50
2745 01:24:20.176252 [Byte1]: 50
2746 01:24:20.181296
2747 01:24:20.181416 Set Vref, RX VrefLevel [Byte0]: 51
2748 01:24:20.184156 [Byte1]: 51
2749 01:24:20.189088
2750 01:24:20.189205 Set Vref, RX VrefLevel [Byte0]: 52
2751 01:24:20.191856 [Byte1]: 52
2752 01:24:20.196324
2753 01:24:20.196443 Set Vref, RX VrefLevel [Byte0]: 53
2754 01:24:20.199816 [Byte1]: 53
2755 01:24:20.204676
2756 01:24:20.204803 Set Vref, RX VrefLevel [Byte0]: 54
2757 01:24:20.207762 [Byte1]: 54
2758 01:24:20.212322
2759 01:24:20.212442 Set Vref, RX VrefLevel [Byte0]: 55
2760 01:24:20.215663 [Byte1]: 55
2761 01:24:20.220259
2762 01:24:20.220377 Set Vref, RX VrefLevel [Byte0]: 56
2763 01:24:20.223519 [Byte1]: 56
2764 01:24:20.228111
2765 01:24:20.228230 Set Vref, RX VrefLevel [Byte0]: 57
2766 01:24:20.231226 [Byte1]: 57
2767 01:24:20.235864
2768 01:24:20.235985 Set Vref, RX VrefLevel [Byte0]: 58
2769 01:24:20.239131 [Byte1]: 58
2770 01:24:20.243774
2771 01:24:20.243894 Set Vref, RX VrefLevel [Byte0]: 59
2772 01:24:20.247120 [Byte1]: 59
2773 01:24:20.251653
2774 01:24:20.251776 Set Vref, RX VrefLevel [Byte0]: 60
2775 01:24:20.254993 [Byte1]: 60
2776 01:24:20.259729
2777 01:24:20.259848 Set Vref, RX VrefLevel [Byte0]: 61
2778 01:24:20.263743 [Byte1]: 61
2779 01:24:20.267352
2780 01:24:20.267471 Set Vref, RX VrefLevel [Byte0]: 62
2781 01:24:20.270853 [Byte1]: 62
2782 01:24:20.275435
2783 01:24:20.275557 Set Vref, RX VrefLevel [Byte0]: 63
2784 01:24:20.278999 [Byte1]: 63
2785 01:24:20.283311
2786 01:24:20.283432 Set Vref, RX VrefLevel [Byte0]: 64
2787 01:24:20.286785 [Byte1]: 64
2788 01:24:20.290996
2789 01:24:20.291116 Set Vref, RX VrefLevel [Byte0]: 65
2790 01:24:20.295270 [Byte1]: 65
2791 01:24:20.299141
2792 01:24:20.299262 Set Vref, RX VrefLevel [Byte0]: 66
2793 01:24:20.302296 [Byte1]: 66
2794 01:24:20.307063
2795 01:24:20.307184 Set Vref, RX VrefLevel [Byte0]: 67
2796 01:24:20.310593 [Byte1]: 67
2797 01:24:20.315264
2798 01:24:20.315384 Set Vref, RX VrefLevel [Byte0]: 68
2799 01:24:20.318025 [Byte1]: 68
2800 01:24:20.322601
2801 01:24:20.322705 Set Vref, RX VrefLevel [Byte0]: 69
2802 01:24:20.326080 [Byte1]: 69
2803 01:24:20.330711
2804 01:24:20.330808 Set Vref, RX VrefLevel [Byte0]: 70
2805 01:24:20.333861 [Byte1]: 70
2806 01:24:20.338778
2807 01:24:20.338860 Set Vref, RX VrefLevel [Byte0]: 71
2808 01:24:20.341703 [Byte1]: 71
2809 01:24:20.346412
2810 01:24:20.346494 Final RX Vref Byte 0 = 59 to rank0
2811 01:24:20.349799 Final RX Vref Byte 1 = 50 to rank0
2812 01:24:20.352929 Final RX Vref Byte 0 = 59 to rank1
2813 01:24:20.356891 Final RX Vref Byte 1 = 50 to rank1==
2814 01:24:20.359855 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 01:24:20.363102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 01:24:20.366428 ==
2817 01:24:20.366511 DQS Delay:
2818 01:24:20.366576 DQS0 = 0, DQS1 = 0
2819 01:24:20.370101 DQM Delay:
2820 01:24:20.370183 DQM0 = 122, DQM1 = 109
2821 01:24:20.373489 DQ Delay:
2822 01:24:20.376599 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2823 01:24:20.379883 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2824 01:24:20.383757 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2825 01:24:20.386643 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2826 01:24:20.386726
2827 01:24:20.386792
2828 01:24:20.393877 [DQSOSCAuto] RK0, (LSB)MR18= 0xa06, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2829 01:24:20.397119 CH0 RK0: MR19=404, MR18=A06
2830 01:24:20.404351 CH0_RK0: MR19=0x404, MR18=0xA06, DQSOSC=406, MR23=63, INC=39, DEC=26
2831 01:24:20.404435
2832 01:24:20.407166 ----->DramcWriteLeveling(PI) begin...
2833 01:24:20.407250 ==
2834 01:24:20.411024 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 01:24:20.414058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 01:24:20.414141 ==
2837 01:24:20.417070 Write leveling (Byte 0): 35 => 35
2838 01:24:20.420841 Write leveling (Byte 1): 30 => 30
2839 01:24:20.423863 DramcWriteLeveling(PI) end<-----
2840 01:24:20.423946
2841 01:24:20.424012 ==
2842 01:24:20.427276 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 01:24:20.430753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 01:24:20.430836 ==
2845 01:24:20.433857 [Gating] SW mode calibration
2846 01:24:20.440424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 01:24:20.447598 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 01:24:20.450577 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2849 01:24:20.454417 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 01:24:20.460467 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 01:24:20.464115 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 01:24:20.467273 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 01:24:20.474425 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 01:24:20.477668 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2855 01:24:20.481290 0 15 28 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
2856 01:24:20.487427 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 01:24:20.490801 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 01:24:20.494070 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 01:24:20.501306 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 01:24:20.504359 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 01:24:20.507395 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 01:24:20.510879 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 01:24:20.517637 1 0 28 | B1->B0 | 3a3a 4141 | 1 0 | (0 0) (0 0)
2864 01:24:20.520979 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 01:24:20.524309 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 01:24:20.531044 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 01:24:20.534177 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 01:24:20.537619 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 01:24:20.544495 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 01:24:20.547907 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 01:24:20.551082 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2872 01:24:20.558041 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 01:24:20.561158 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 01:24:20.564841 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 01:24:20.571135 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 01:24:20.574436 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 01:24:20.577986 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 01:24:20.584804 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 01:24:20.587865 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 01:24:20.591057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 01:24:20.594308 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 01:24:20.601513 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 01:24:20.604991 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 01:24:20.607841 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 01:24:20.615114 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 01:24:20.618138 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 01:24:20.621659 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2888 01:24:20.628137 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 01:24:20.628266 Total UI for P1: 0, mck2ui 16
2890 01:24:20.634617 best dqsien dly found for B0: ( 1, 3, 28)
2891 01:24:20.634740 Total UI for P1: 0, mck2ui 16
2892 01:24:20.641467 best dqsien dly found for B1: ( 1, 3, 28)
2893 01:24:20.645016 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2894 01:24:20.648341 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2895 01:24:20.648462
2896 01:24:20.651555 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2897 01:24:20.655644 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2898 01:24:20.658175 [Gating] SW calibration Done
2899 01:24:20.658293 ==
2900 01:24:20.661420 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 01:24:20.664877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 01:24:20.664996 ==
2903 01:24:20.668174 RX Vref Scan: 0
2904 01:24:20.668292
2905 01:24:20.668403 RX Vref 0 -> 0, step: 1
2906 01:24:20.668513
2907 01:24:20.671892 RX Delay -40 -> 252, step: 8
2908 01:24:20.675694 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2909 01:24:20.678294 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2910 01:24:20.684990 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2911 01:24:20.688580 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2912 01:24:20.691943 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2913 01:24:20.695131 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2914 01:24:20.698969 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2915 01:24:20.705067 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2916 01:24:20.708503 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2917 01:24:20.711805 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2918 01:24:20.715174 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2919 01:24:20.718772 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2920 01:24:20.721689 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2921 01:24:20.728687 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2922 01:24:20.732061 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2923 01:24:20.735193 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2924 01:24:20.735312 ==
2925 01:24:20.738350 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 01:24:20.742212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 01:24:20.745499 ==
2928 01:24:20.745623 DQS Delay:
2929 01:24:20.745734 DQS0 = 0, DQS1 = 0
2930 01:24:20.748546 DQM Delay:
2931 01:24:20.748666 DQM0 = 120, DQM1 = 108
2932 01:24:20.751826 DQ Delay:
2933 01:24:20.755149 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2934 01:24:20.758623 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2935 01:24:20.761785 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2936 01:24:20.765561 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2937 01:24:20.765680
2938 01:24:20.765795
2939 01:24:20.765904 ==
2940 01:24:20.768742 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 01:24:20.771965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 01:24:20.772086 ==
2943 01:24:20.772195
2944 01:24:20.772305
2945 01:24:20.775270 TX Vref Scan disable
2946 01:24:20.778899 == TX Byte 0 ==
2947 01:24:20.782011 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2948 01:24:20.785871 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2949 01:24:20.789097 == TX Byte 1 ==
2950 01:24:20.792274 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2951 01:24:20.795630 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2952 01:24:20.795754 ==
2953 01:24:20.799282 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 01:24:20.802205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 01:24:20.802306 ==
2956 01:24:20.816037 TX Vref=22, minBit 5, minWin=24, winSum=414
2957 01:24:20.819233 TX Vref=24, minBit 3, minWin=24, winSum=415
2958 01:24:20.822517 TX Vref=26, minBit 1, minWin=25, winSum=421
2959 01:24:20.826089 TX Vref=28, minBit 3, minWin=24, winSum=422
2960 01:24:20.829334 TX Vref=30, minBit 1, minWin=25, winSum=421
2961 01:24:20.832571 TX Vref=32, minBit 2, minWin=25, winSum=425
2962 01:24:20.839163 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 32
2963 01:24:20.839266
2964 01:24:20.842357 Final TX Range 1 Vref 32
2965 01:24:20.842441
2966 01:24:20.842507 ==
2967 01:24:20.846032 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 01:24:20.848920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 01:24:20.849005 ==
2970 01:24:20.849072
2971 01:24:20.849133
2972 01:24:20.852618 TX Vref Scan disable
2973 01:24:20.855807 == TX Byte 0 ==
2974 01:24:20.859329 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2975 01:24:20.862409 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2976 01:24:20.865720 == TX Byte 1 ==
2977 01:24:20.869187 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2978 01:24:20.872310 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2979 01:24:20.872394
2980 01:24:20.875935 [DATLAT]
2981 01:24:20.876019 Freq=1200, CH0 RK1
2982 01:24:20.876086
2983 01:24:20.878965 DATLAT Default: 0xd
2984 01:24:20.879048 0, 0xFFFF, sum = 0
2985 01:24:20.882378 1, 0xFFFF, sum = 0
2986 01:24:20.882463 2, 0xFFFF, sum = 0
2987 01:24:20.885727 3, 0xFFFF, sum = 0
2988 01:24:20.885812 4, 0xFFFF, sum = 0
2989 01:24:20.889275 5, 0xFFFF, sum = 0
2990 01:24:20.889360 6, 0xFFFF, sum = 0
2991 01:24:20.892979 7, 0xFFFF, sum = 0
2992 01:24:20.893064 8, 0xFFFF, sum = 0
2993 01:24:20.895889 9, 0xFFFF, sum = 0
2994 01:24:20.899259 10, 0xFFFF, sum = 0
2995 01:24:20.899344 11, 0xFFFF, sum = 0
2996 01:24:20.902477 12, 0x0, sum = 1
2997 01:24:20.902562 13, 0x0, sum = 2
2998 01:24:20.902630 14, 0x0, sum = 3
2999 01:24:20.905870 15, 0x0, sum = 4
3000 01:24:20.905955 best_step = 13
3001 01:24:20.906022
3002 01:24:20.908998 ==
3003 01:24:20.909082 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 01:24:20.916207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 01:24:20.916292 ==
3006 01:24:20.916359 RX Vref Scan: 0
3007 01:24:20.916422
3008 01:24:20.919315 RX Vref 0 -> 0, step: 1
3009 01:24:20.919399
3010 01:24:20.922442 RX Delay -21 -> 252, step: 4
3011 01:24:20.925791 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3012 01:24:20.929116 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3013 01:24:20.935641 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3014 01:24:20.939117 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3015 01:24:20.942539 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3016 01:24:20.946554 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3017 01:24:20.949766 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3018 01:24:20.956017 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3019 01:24:20.959279 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3020 01:24:20.962380 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3021 01:24:20.966134 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3022 01:24:20.969619 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3023 01:24:20.976208 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3024 01:24:20.979263 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3025 01:24:20.982623 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3026 01:24:20.986043 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3027 01:24:20.986127 ==
3028 01:24:20.989351 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 01:24:20.992620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 01:24:20.996012 ==
3031 01:24:20.996096 DQS Delay:
3032 01:24:20.996164 DQS0 = 0, DQS1 = 0
3033 01:24:20.999397 DQM Delay:
3034 01:24:20.999480 DQM0 = 120, DQM1 = 108
3035 01:24:21.002484 DQ Delay:
3036 01:24:21.006143 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3037 01:24:21.009532 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
3038 01:24:21.012660 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =106
3039 01:24:21.016183 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3040 01:24:21.016267
3041 01:24:21.016334
3042 01:24:21.022718 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3043 01:24:21.026024 CH0 RK1: MR19=403, MR18=CF4
3044 01:24:21.032736 CH0_RK1: MR19=0x403, MR18=0xCF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3045 01:24:21.036191 [RxdqsGatingPostProcess] freq 1200
3046 01:24:21.042773 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3047 01:24:21.042858 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 01:24:21.046414 best DQS1 dly(2T, 0.5T) = (0, 11)
3049 01:24:21.049626 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 01:24:21.052937 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3051 01:24:21.056657 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 01:24:21.059523 best DQS1 dly(2T, 0.5T) = (0, 11)
3053 01:24:21.062943 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 01:24:21.065987 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3055 01:24:21.069649 Pre-setting of DQS Precalculation
3056 01:24:21.072959 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3057 01:24:21.076130 ==
3058 01:24:21.076214 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 01:24:21.082867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 01:24:21.082952 ==
3061 01:24:21.086134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3062 01:24:21.092669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3063 01:24:21.101668 [CA 0] Center 37 (7~68) winsize 62
3064 01:24:21.105247 [CA 1] Center 37 (7~68) winsize 62
3065 01:24:21.108591 [CA 2] Center 35 (5~65) winsize 61
3066 01:24:21.112455 [CA 3] Center 34 (4~65) winsize 62
3067 01:24:21.115142 [CA 4] Center 34 (4~64) winsize 61
3068 01:24:21.118733 [CA 5] Center 33 (3~64) winsize 62
3069 01:24:21.118818
3070 01:24:21.121852 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3071 01:24:21.121937
3072 01:24:21.125299 [CATrainingPosCal] consider 1 rank data
3073 01:24:21.128529 u2DelayCellTimex100 = 270/100 ps
3074 01:24:21.132263 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 01:24:21.135156 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 01:24:21.139043 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3077 01:24:21.145282 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3078 01:24:21.148632 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3079 01:24:21.152109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3080 01:24:21.152192
3081 01:24:21.155329 CA PerBit enable=1, Macro0, CA PI delay=33
3082 01:24:21.155413
3083 01:24:21.158919 [CBTSetCACLKResult] CA Dly = 33
3084 01:24:21.159003 CS Dly: 5 (0~36)
3085 01:24:21.159070 ==
3086 01:24:21.162638 Dram Type= 6, Freq= 0, CH_1, rank 1
3087 01:24:21.168602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 01:24:21.168686 ==
3089 01:24:21.172265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 01:24:21.178972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 01:24:21.187600 [CA 0] Center 38 (8~68) winsize 61
3092 01:24:21.191364 [CA 1] Center 37 (7~68) winsize 62
3093 01:24:21.194063 [CA 2] Center 35 (5~66) winsize 62
3094 01:24:21.197601 [CA 3] Center 34 (4~65) winsize 62
3095 01:24:21.200779 [CA 4] Center 35 (5~65) winsize 61
3096 01:24:21.204268 [CA 5] Center 34 (4~64) winsize 61
3097 01:24:21.204371
3098 01:24:21.207820 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 01:24:21.207904
3100 01:24:21.210751 [CATrainingPosCal] consider 2 rank data
3101 01:24:21.214194 u2DelayCellTimex100 = 270/100 ps
3102 01:24:21.217606 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3103 01:24:21.220978 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3104 01:24:21.227512 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3105 01:24:21.231145 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3106 01:24:21.234150 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3107 01:24:21.237914 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3108 01:24:21.237998
3109 01:24:21.241060 CA PerBit enable=1, Macro0, CA PI delay=34
3110 01:24:21.241143
3111 01:24:21.244393 [CBTSetCACLKResult] CA Dly = 34
3112 01:24:21.244476 CS Dly: 6 (0~39)
3113 01:24:21.244541
3114 01:24:21.247637 ----->DramcWriteLeveling(PI) begin...
3115 01:24:21.247722 ==
3116 01:24:21.250887 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 01:24:21.257975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 01:24:21.258101 ==
3119 01:24:21.260772 Write leveling (Byte 0): 24 => 24
3120 01:24:21.264363 Write leveling (Byte 1): 28 => 28
3121 01:24:21.264483 DramcWriteLeveling(PI) end<-----
3122 01:24:21.264596
3123 01:24:21.267639 ==
3124 01:24:21.270976 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 01:24:21.274359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 01:24:21.274481 ==
3127 01:24:21.277903 [Gating] SW mode calibration
3128 01:24:21.284434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3129 01:24:21.287605 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3130 01:24:21.294237 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 01:24:21.297663 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 01:24:21.301169 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 01:24:21.307636 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 01:24:21.311149 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 01:24:21.314320 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3136 01:24:21.321739 0 15 24 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
3137 01:24:21.324625 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3138 01:24:21.328021 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 01:24:21.331194 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 01:24:21.337895 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 01:24:21.341530 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 01:24:21.344893 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 01:24:21.351406 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3144 01:24:21.355596 1 0 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3145 01:24:21.358192 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 01:24:21.364643 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 01:24:21.368007 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 01:24:21.371335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 01:24:21.378231 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 01:24:21.381266 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 01:24:21.384533 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 01:24:21.391568 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3153 01:24:21.394891 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3154 01:24:21.398061 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 01:24:21.405135 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 01:24:21.408344 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 01:24:21.411359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 01:24:21.414769 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 01:24:21.421328 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 01:24:21.424636 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 01:24:21.428183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 01:24:21.434685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 01:24:21.438393 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 01:24:21.441343 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 01:24:21.448314 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 01:24:21.451443 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 01:24:21.454869 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3168 01:24:21.461367 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3169 01:24:21.464606 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3170 01:24:21.468340 Total UI for P1: 0, mck2ui 16
3171 01:24:21.471321 best dqsien dly found for B0: ( 1, 3, 22)
3172 01:24:21.475059 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 01:24:21.478114 Total UI for P1: 0, mck2ui 16
3174 01:24:21.481423 best dqsien dly found for B1: ( 1, 3, 26)
3175 01:24:21.484693 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3176 01:24:21.488323 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3177 01:24:21.488447
3178 01:24:21.491447 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3179 01:24:21.497985 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3180 01:24:21.498111 [Gating] SW calibration Done
3181 01:24:21.498219 ==
3182 01:24:21.502063 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 01:24:21.508579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 01:24:21.508703 ==
3185 01:24:21.508825 RX Vref Scan: 0
3186 01:24:21.508934
3187 01:24:21.511725 RX Vref 0 -> 0, step: 1
3188 01:24:21.511844
3189 01:24:21.515022 RX Delay -40 -> 252, step: 8
3190 01:24:21.518650 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3191 01:24:21.521674 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3192 01:24:21.525095 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3193 01:24:21.528668 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3194 01:24:21.535783 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3195 01:24:21.538546 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3196 01:24:21.542102 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3197 01:24:21.545587 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3198 01:24:21.548704 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3199 01:24:21.551909 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3200 01:24:21.558774 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3201 01:24:21.562481 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3202 01:24:21.565630 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3203 01:24:21.568717 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3204 01:24:21.575653 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3205 01:24:21.579020 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3206 01:24:21.579162 ==
3207 01:24:21.582349 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 01:24:21.585793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 01:24:21.585924 ==
3210 01:24:21.586033 DQS Delay:
3211 01:24:21.589021 DQS0 = 0, DQS1 = 0
3212 01:24:21.589144 DQM Delay:
3213 01:24:21.592212 DQM0 = 119, DQM1 = 112
3214 01:24:21.592334 DQ Delay:
3215 01:24:21.595656 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3216 01:24:21.598749 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3217 01:24:21.602233 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3218 01:24:21.605571 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3219 01:24:21.605702
3220 01:24:21.605818
3221 01:24:21.608838 ==
3222 01:24:21.612448 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 01:24:21.615778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 01:24:21.615911 ==
3225 01:24:21.616027
3226 01:24:21.616134
3227 01:24:21.618840 TX Vref Scan disable
3228 01:24:21.618962 == TX Byte 0 ==
3229 01:24:21.622498 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3230 01:24:21.629035 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3231 01:24:21.629171 == TX Byte 1 ==
3232 01:24:21.632500 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3233 01:24:21.639073 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3234 01:24:21.639218 ==
3235 01:24:21.642210 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 01:24:21.645614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 01:24:21.645743 ==
3238 01:24:21.657597 TX Vref=22, minBit 10, minWin=24, winSum=407
3239 01:24:21.660987 TX Vref=24, minBit 3, minWin=25, winSum=412
3240 01:24:21.664096 TX Vref=26, minBit 9, minWin=25, winSum=416
3241 01:24:21.667871 TX Vref=28, minBit 9, minWin=25, winSum=420
3242 01:24:21.671478 TX Vref=30, minBit 11, minWin=25, winSum=423
3243 01:24:21.677770 TX Vref=32, minBit 1, minWin=26, winSum=422
3244 01:24:21.680996 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 32
3245 01:24:21.681107
3246 01:24:21.684394 Final TX Range 1 Vref 32
3247 01:24:21.684514
3248 01:24:21.684618 ==
3249 01:24:21.687900 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 01:24:21.691220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 01:24:21.691386 ==
3252 01:24:21.691501
3253 01:24:21.691602
3254 01:24:21.694507 TX Vref Scan disable
3255 01:24:21.698109 == TX Byte 0 ==
3256 01:24:21.701208 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3257 01:24:21.704364 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3258 01:24:21.707982 == TX Byte 1 ==
3259 01:24:21.711299 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3260 01:24:21.714682 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3261 01:24:21.714823
3262 01:24:21.717908 [DATLAT]
3263 01:24:21.718008 Freq=1200, CH1 RK0
3264 01:24:21.718098
3265 01:24:21.721361 DATLAT Default: 0xd
3266 01:24:21.721449 0, 0xFFFF, sum = 0
3267 01:24:21.724640 1, 0xFFFF, sum = 0
3268 01:24:21.724731 2, 0xFFFF, sum = 0
3269 01:24:21.727808 3, 0xFFFF, sum = 0
3270 01:24:21.727907 4, 0xFFFF, sum = 0
3271 01:24:21.731337 5, 0xFFFF, sum = 0
3272 01:24:21.731484 6, 0xFFFF, sum = 0
3273 01:24:21.734494 7, 0xFFFF, sum = 0
3274 01:24:21.734597 8, 0xFFFF, sum = 0
3275 01:24:21.737929 9, 0xFFFF, sum = 0
3276 01:24:21.738073 10, 0xFFFF, sum = 0
3277 01:24:21.741281 11, 0xFFFF, sum = 0
3278 01:24:21.741434 12, 0x0, sum = 1
3279 01:24:21.744907 13, 0x0, sum = 2
3280 01:24:21.745014 14, 0x0, sum = 3
3281 01:24:21.747996 15, 0x0, sum = 4
3282 01:24:21.748087 best_step = 13
3283 01:24:21.748158
3284 01:24:21.748222 ==
3285 01:24:21.751360 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 01:24:21.757942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 01:24:21.758061 ==
3288 01:24:21.758135 RX Vref Scan: 1
3289 01:24:21.758200
3290 01:24:21.762260 Set Vref Range= 32 -> 127
3291 01:24:21.762360
3292 01:24:21.764532 RX Vref 32 -> 127, step: 1
3293 01:24:21.764637
3294 01:24:21.764708 RX Delay -13 -> 252, step: 4
3295 01:24:21.768036
3296 01:24:21.768125 Set Vref, RX VrefLevel [Byte0]: 32
3297 01:24:21.771495 [Byte1]: 32
3298 01:24:21.775964
3299 01:24:21.776062 Set Vref, RX VrefLevel [Byte0]: 33
3300 01:24:21.779389 [Byte1]: 33
3301 01:24:21.783725
3302 01:24:21.783860 Set Vref, RX VrefLevel [Byte0]: 34
3303 01:24:21.787000 [Byte1]: 34
3304 01:24:21.791481
3305 01:24:21.791612 Set Vref, RX VrefLevel [Byte0]: 35
3306 01:24:21.794827 [Byte1]: 35
3307 01:24:21.799995
3308 01:24:21.800154 Set Vref, RX VrefLevel [Byte0]: 36
3309 01:24:21.802706 [Byte1]: 36
3310 01:24:21.807600
3311 01:24:21.807733 Set Vref, RX VrefLevel [Byte0]: 37
3312 01:24:21.810750 [Byte1]: 37
3313 01:24:21.815289
3314 01:24:21.815427 Set Vref, RX VrefLevel [Byte0]: 38
3315 01:24:21.818828 [Byte1]: 38
3316 01:24:21.823114
3317 01:24:21.823245 Set Vref, RX VrefLevel [Byte0]: 39
3318 01:24:21.826681 [Byte1]: 39
3319 01:24:21.831250
3320 01:24:21.831381 Set Vref, RX VrefLevel [Byte0]: 40
3321 01:24:21.834288 [Byte1]: 40
3322 01:24:21.839098
3323 01:24:21.839228 Set Vref, RX VrefLevel [Byte0]: 41
3324 01:24:21.842222 [Byte1]: 41
3325 01:24:21.846899
3326 01:24:21.847042 Set Vref, RX VrefLevel [Byte0]: 42
3327 01:24:21.850057 [Byte1]: 42
3328 01:24:21.855247
3329 01:24:21.855353 Set Vref, RX VrefLevel [Byte0]: 43
3330 01:24:21.858048 [Byte1]: 43
3331 01:24:21.862789
3332 01:24:21.862871 Set Vref, RX VrefLevel [Byte0]: 44
3333 01:24:21.866411 [Byte1]: 44
3334 01:24:21.870526
3335 01:24:21.870613 Set Vref, RX VrefLevel [Byte0]: 45
3336 01:24:21.873809 [Byte1]: 45
3337 01:24:21.878506
3338 01:24:21.878588 Set Vref, RX VrefLevel [Byte0]: 46
3339 01:24:21.881911 [Byte1]: 46
3340 01:24:21.886164
3341 01:24:21.886246 Set Vref, RX VrefLevel [Byte0]: 47
3342 01:24:21.889591 [Byte1]: 47
3343 01:24:21.894494
3344 01:24:21.894576 Set Vref, RX VrefLevel [Byte0]: 48
3345 01:24:21.897733 [Byte1]: 48
3346 01:24:21.902585
3347 01:24:21.902669 Set Vref, RX VrefLevel [Byte0]: 49
3348 01:24:21.905320 [Byte1]: 49
3349 01:24:21.910197
3350 01:24:21.910281 Set Vref, RX VrefLevel [Byte0]: 50
3351 01:24:21.913180 [Byte1]: 50
3352 01:24:21.917768
3353 01:24:21.917852 Set Vref, RX VrefLevel [Byte0]: 51
3354 01:24:21.921045 [Byte1]: 51
3355 01:24:21.925828
3356 01:24:21.925912 Set Vref, RX VrefLevel [Byte0]: 52
3357 01:24:21.928913 [Byte1]: 52
3358 01:24:21.933761
3359 01:24:21.933877 Set Vref, RX VrefLevel [Byte0]: 53
3360 01:24:21.936925 [Byte1]: 53
3361 01:24:21.941615
3362 01:24:21.941726 Set Vref, RX VrefLevel [Byte0]: 54
3363 01:24:21.944675 [Byte1]: 54
3364 01:24:21.949302
3365 01:24:21.949386 Set Vref, RX VrefLevel [Byte0]: 55
3366 01:24:21.952620 [Byte1]: 55
3367 01:24:21.957276
3368 01:24:21.957359 Set Vref, RX VrefLevel [Byte0]: 56
3369 01:24:21.961153 [Byte1]: 56
3370 01:24:21.965094
3371 01:24:21.965203 Set Vref, RX VrefLevel [Byte0]: 57
3372 01:24:21.968408 [Byte1]: 57
3373 01:24:21.972881
3374 01:24:21.973009 Set Vref, RX VrefLevel [Byte0]: 58
3375 01:24:21.976664 [Byte1]: 58
3376 01:24:21.981096
3377 01:24:21.981201 Set Vref, RX VrefLevel [Byte0]: 59
3378 01:24:21.984610 [Byte1]: 59
3379 01:24:21.988672
3380 01:24:21.992183 Set Vref, RX VrefLevel [Byte0]: 60
3381 01:24:21.995219 [Byte1]: 60
3382 01:24:21.995302
3383 01:24:21.998876 Set Vref, RX VrefLevel [Byte0]: 61
3384 01:24:22.002096 [Byte1]: 61
3385 01:24:22.002180
3386 01:24:22.005276 Set Vref, RX VrefLevel [Byte0]: 62
3387 01:24:22.008557 [Byte1]: 62
3388 01:24:22.012339
3389 01:24:22.012423 Set Vref, RX VrefLevel [Byte0]: 63
3390 01:24:22.015703 [Byte1]: 63
3391 01:24:22.020494
3392 01:24:22.020576 Set Vref, RX VrefLevel [Byte0]: 64
3393 01:24:22.023956 [Byte1]: 64
3394 01:24:22.028185
3395 01:24:22.028269 Set Vref, RX VrefLevel [Byte0]: 65
3396 01:24:22.031881 [Byte1]: 65
3397 01:24:22.036191
3398 01:24:22.036299 Set Vref, RX VrefLevel [Byte0]: 66
3399 01:24:22.039655 [Byte1]: 66
3400 01:24:22.043924
3401 01:24:22.044007 Set Vref, RX VrefLevel [Byte0]: 67
3402 01:24:22.047424 [Byte1]: 67
3403 01:24:22.051789
3404 01:24:22.051872 Final RX Vref Byte 0 = 51 to rank0
3405 01:24:22.055370 Final RX Vref Byte 1 = 53 to rank0
3406 01:24:22.058384 Final RX Vref Byte 0 = 51 to rank1
3407 01:24:22.062015 Final RX Vref Byte 1 = 53 to rank1==
3408 01:24:22.065238 Dram Type= 6, Freq= 0, CH_1, rank 0
3409 01:24:22.072044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 01:24:22.072128 ==
3411 01:24:22.072196 DQS Delay:
3412 01:24:22.072259 DQS0 = 0, DQS1 = 0
3413 01:24:22.075453 DQM Delay:
3414 01:24:22.075536 DQM0 = 119, DQM1 = 112
3415 01:24:22.078911 DQ Delay:
3416 01:24:22.082362 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3417 01:24:22.085254 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3418 01:24:22.088641 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3419 01:24:22.092309 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3420 01:24:22.092393
3421 01:24:22.092465
3422 01:24:22.098934 [DQSOSCAuto] RK0, (LSB)MR18= 0x619, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3423 01:24:22.102190 CH1 RK0: MR19=404, MR18=619
3424 01:24:22.108769 CH1_RK0: MR19=0x404, MR18=0x619, DQSOSC=400, MR23=63, INC=40, DEC=27
3425 01:24:22.108854
3426 01:24:22.112152 ----->DramcWriteLeveling(PI) begin...
3427 01:24:22.112238 ==
3428 01:24:22.115498 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 01:24:22.119044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 01:24:22.119129 ==
3431 01:24:22.122142 Write leveling (Byte 0): 25 => 25
3432 01:24:22.125646 Write leveling (Byte 1): 31 => 31
3433 01:24:22.128683 DramcWriteLeveling(PI) end<-----
3434 01:24:22.128789
3435 01:24:22.128871 ==
3436 01:24:22.131956 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 01:24:22.135603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 01:24:22.138836 ==
3439 01:24:22.138920 [Gating] SW mode calibration
3440 01:24:22.148959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3441 01:24:22.152000 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3442 01:24:22.155416 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 01:24:22.162113 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 01:24:22.165688 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 01:24:22.169343 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 01:24:22.175406 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 01:24:22.178722 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3448 01:24:22.182428 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (1 0) (1 0)
3449 01:24:22.188725 0 15 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 1)
3450 01:24:22.192281 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 01:24:22.195370 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 01:24:22.202199 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 01:24:22.205587 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 01:24:22.209317 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 01:24:22.212399 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 01:24:22.218801 1 0 24 | B1->B0 | 3535 2727 | 0 0 | (0 0) (0 0)
3457 01:24:22.222407 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3458 01:24:22.225599 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 01:24:22.232764 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 01:24:22.236011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 01:24:22.239382 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 01:24:22.245526 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 01:24:22.249285 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 01:24:22.252286 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3465 01:24:22.259030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3466 01:24:22.262298 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 01:24:22.265864 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 01:24:22.272225 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 01:24:22.275632 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 01:24:22.279156 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 01:24:22.285812 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 01:24:22.288903 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 01:24:22.292030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 01:24:22.299011 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 01:24:22.302222 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 01:24:22.305355 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 01:24:22.311961 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 01:24:22.315744 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 01:24:22.318914 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 01:24:22.322310 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3481 01:24:22.329042 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 01:24:22.332141 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 01:24:22.335720 Total UI for P1: 0, mck2ui 16
3484 01:24:22.338875 best dqsien dly found for B0: ( 1, 3, 26)
3485 01:24:22.342294 Total UI for P1: 0, mck2ui 16
3486 01:24:22.345495 best dqsien dly found for B1: ( 1, 3, 26)
3487 01:24:22.348871 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3488 01:24:22.352580 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3489 01:24:22.352682
3490 01:24:22.355366 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3491 01:24:22.359083 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3492 01:24:22.362139 [Gating] SW calibration Done
3493 01:24:22.362223 ==
3494 01:24:22.365671 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 01:24:22.368915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 01:24:22.372199 ==
3497 01:24:22.372283 RX Vref Scan: 0
3498 01:24:22.372349
3499 01:24:22.375394 RX Vref 0 -> 0, step: 1
3500 01:24:22.375477
3501 01:24:22.378673 RX Delay -40 -> 252, step: 8
3502 01:24:22.382283 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3503 01:24:22.385240 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3504 01:24:22.388716 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3505 01:24:22.392042 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3506 01:24:22.398843 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3507 01:24:22.402060 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 01:24:22.405298 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3509 01:24:22.408682 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3510 01:24:22.411808 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3511 01:24:22.418710 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3512 01:24:22.421701 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3513 01:24:22.425351 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3514 01:24:22.429081 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3515 01:24:22.431755 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3516 01:24:22.438412 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3517 01:24:22.441865 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3518 01:24:22.441950 ==
3519 01:24:22.444978 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 01:24:22.448224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 01:24:22.448311 ==
3522 01:24:22.451679 DQS Delay:
3523 01:24:22.451764 DQS0 = 0, DQS1 = 0
3524 01:24:22.451849 DQM Delay:
3525 01:24:22.454985 DQM0 = 120, DQM1 = 113
3526 01:24:22.455070 DQ Delay:
3527 01:24:22.458445 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3528 01:24:22.461835 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3529 01:24:22.465763 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3530 01:24:22.471745 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3531 01:24:22.471853
3532 01:24:22.471955
3533 01:24:22.472034 ==
3534 01:24:22.475069 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 01:24:22.478369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 01:24:22.478454 ==
3537 01:24:22.478540
3538 01:24:22.478619
3539 01:24:22.481685 TX Vref Scan disable
3540 01:24:22.481770 == TX Byte 0 ==
3541 01:24:22.488581 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3542 01:24:22.491784 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3543 01:24:22.491869 == TX Byte 1 ==
3544 01:24:22.498683 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3545 01:24:22.501503 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3546 01:24:22.501626 ==
3547 01:24:22.504762 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 01:24:22.508140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 01:24:22.508262 ==
3550 01:24:22.521436 TX Vref=22, minBit 0, minWin=26, winSum=420
3551 01:24:22.524542 TX Vref=24, minBit 1, minWin=25, winSum=422
3552 01:24:22.528103 TX Vref=26, minBit 1, minWin=26, winSum=427
3553 01:24:22.531565 TX Vref=28, minBit 15, minWin=25, winSum=430
3554 01:24:22.534996 TX Vref=30, minBit 9, minWin=26, winSum=431
3555 01:24:22.541755 TX Vref=32, minBit 10, minWin=26, winSum=431
3556 01:24:22.544715 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 30
3557 01:24:22.544821
3558 01:24:22.548161 Final TX Range 1 Vref 30
3559 01:24:22.548244
3560 01:24:22.548310 ==
3561 01:24:22.551347 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 01:24:22.554910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 01:24:22.557665 ==
3564 01:24:22.557747
3565 01:24:22.557813
3566 01:24:22.557874 TX Vref Scan disable
3567 01:24:22.562609 == TX Byte 0 ==
3568 01:24:22.564535 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 01:24:22.567934 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 01:24:22.571450 == TX Byte 1 ==
3571 01:24:22.574524 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3572 01:24:22.577949 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3573 01:24:22.581082
3574 01:24:22.581165 [DATLAT]
3575 01:24:22.581231 Freq=1200, CH1 RK1
3576 01:24:22.581293
3577 01:24:22.584709 DATLAT Default: 0xd
3578 01:24:22.584815 0, 0xFFFF, sum = 0
3579 01:24:22.587859 1, 0xFFFF, sum = 0
3580 01:24:22.587943 2, 0xFFFF, sum = 0
3581 01:24:22.591201 3, 0xFFFF, sum = 0
3582 01:24:22.594486 4, 0xFFFF, sum = 0
3583 01:24:22.594571 5, 0xFFFF, sum = 0
3584 01:24:22.597847 6, 0xFFFF, sum = 0
3585 01:24:22.597931 7, 0xFFFF, sum = 0
3586 01:24:22.601416 8, 0xFFFF, sum = 0
3587 01:24:22.601500 9, 0xFFFF, sum = 0
3588 01:24:22.604470 10, 0xFFFF, sum = 0
3589 01:24:22.604555 11, 0xFFFF, sum = 0
3590 01:24:22.607952 12, 0x0, sum = 1
3591 01:24:22.608037 13, 0x0, sum = 2
3592 01:24:22.611332 14, 0x0, sum = 3
3593 01:24:22.611416 15, 0x0, sum = 4
3594 01:24:22.611484 best_step = 13
3595 01:24:22.614463
3596 01:24:22.614546 ==
3597 01:24:22.617677 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 01:24:22.621125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 01:24:22.621208 ==
3600 01:24:22.621274 RX Vref Scan: 0
3601 01:24:22.621337
3602 01:24:22.624382 RX Vref 0 -> 0, step: 1
3603 01:24:22.624506
3604 01:24:22.628105 RX Delay -13 -> 252, step: 4
3605 01:24:22.630980 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3606 01:24:22.637704 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3607 01:24:22.641007 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3608 01:24:22.644334 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3609 01:24:22.647993 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3610 01:24:22.651135 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3611 01:24:22.657649 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3612 01:24:22.660865 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3613 01:24:22.664263 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3614 01:24:22.667662 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3615 01:24:22.670898 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3616 01:24:22.677958 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3617 01:24:22.681521 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3618 01:24:22.684511 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3619 01:24:22.687510 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3620 01:24:22.690710 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3621 01:24:22.693995 ==
3622 01:24:22.697449 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 01:24:22.700697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 01:24:22.700817 ==
3625 01:24:22.700907 DQS Delay:
3626 01:24:22.704114 DQS0 = 0, DQS1 = 0
3627 01:24:22.704207 DQM Delay:
3628 01:24:22.707651 DQM0 = 119, DQM1 = 113
3629 01:24:22.707734 DQ Delay:
3630 01:24:22.710726 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3631 01:24:22.714379 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3632 01:24:22.717579 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3633 01:24:22.721052 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3634 01:24:22.721135
3635 01:24:22.721200
3636 01:24:22.730702 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3637 01:24:22.730787 CH1 RK1: MR19=403, MR18=9ED
3638 01:24:22.737575 CH1_RK1: MR19=0x403, MR18=0x9ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3639 01:24:22.740994 [RxdqsGatingPostProcess] freq 1200
3640 01:24:22.747376 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 01:24:22.750969 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 01:24:22.754098 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 01:24:22.757632 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 01:24:22.761036 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 01:24:22.764014 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 01:24:22.764097 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 01:24:22.768110 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 01:24:22.770660 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 01:24:22.774263 Pre-setting of DQS Precalculation
3650 01:24:22.780707 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 01:24:22.787258 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 01:24:22.794073 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 01:24:22.794159
3654 01:24:22.794242
3655 01:24:22.797267 [Calibration Summary] 2400 Mbps
3656 01:24:22.800808 CH 0, Rank 0
3657 01:24:22.800892 SW Impedance : PASS
3658 01:24:22.804017 DUTY Scan : NO K
3659 01:24:22.804101 ZQ Calibration : PASS
3660 01:24:22.807542 Jitter Meter : NO K
3661 01:24:22.810521 CBT Training : PASS
3662 01:24:22.810604 Write leveling : PASS
3663 01:24:22.813839 RX DQS gating : PASS
3664 01:24:22.817129 RX DQ/DQS(RDDQC) : PASS
3665 01:24:22.817213 TX DQ/DQS : PASS
3666 01:24:22.820545 RX DATLAT : PASS
3667 01:24:22.823851 RX DQ/DQS(Engine): PASS
3668 01:24:22.823935 TX OE : NO K
3669 01:24:22.827499 All Pass.
3670 01:24:22.827583
3671 01:24:22.827650 CH 0, Rank 1
3672 01:24:22.830734 SW Impedance : PASS
3673 01:24:22.830820 DUTY Scan : NO K
3674 01:24:22.833882 ZQ Calibration : PASS
3675 01:24:22.837362 Jitter Meter : NO K
3676 01:24:22.837447 CBT Training : PASS
3677 01:24:22.840910 Write leveling : PASS
3678 01:24:22.840995 RX DQS gating : PASS
3679 01:24:22.844184 RX DQ/DQS(RDDQC) : PASS
3680 01:24:22.847231 TX DQ/DQS : PASS
3681 01:24:22.847320 RX DATLAT : PASS
3682 01:24:22.850842 RX DQ/DQS(Engine): PASS
3683 01:24:22.854435 TX OE : NO K
3684 01:24:22.854519 All Pass.
3685 01:24:22.854587
3686 01:24:22.854649 CH 1, Rank 0
3687 01:24:22.857233 SW Impedance : PASS
3688 01:24:22.860594 DUTY Scan : NO K
3689 01:24:22.860680 ZQ Calibration : PASS
3690 01:24:22.864086 Jitter Meter : NO K
3691 01:24:22.867171 CBT Training : PASS
3692 01:24:22.867256 Write leveling : PASS
3693 01:24:22.870695 RX DQS gating : PASS
3694 01:24:22.873883 RX DQ/DQS(RDDQC) : PASS
3695 01:24:22.873969 TX DQ/DQS : PASS
3696 01:24:22.877278 RX DATLAT : PASS
3697 01:24:22.880397 RX DQ/DQS(Engine): PASS
3698 01:24:22.880482 TX OE : NO K
3699 01:24:22.880550 All Pass.
3700 01:24:22.883736
3701 01:24:22.883821 CH 1, Rank 1
3702 01:24:22.887192 SW Impedance : PASS
3703 01:24:22.887277 DUTY Scan : NO K
3704 01:24:22.890309 ZQ Calibration : PASS
3705 01:24:22.893687 Jitter Meter : NO K
3706 01:24:22.893772 CBT Training : PASS
3707 01:24:22.897153 Write leveling : PASS
3708 01:24:22.897239 RX DQS gating : PASS
3709 01:24:22.900755 RX DQ/DQS(RDDQC) : PASS
3710 01:24:22.903624 TX DQ/DQS : PASS
3711 01:24:22.903715 RX DATLAT : PASS
3712 01:24:22.906854 RX DQ/DQS(Engine): PASS
3713 01:24:22.910489 TX OE : NO K
3714 01:24:22.910576 All Pass.
3715 01:24:22.910645
3716 01:24:22.913577 DramC Write-DBI off
3717 01:24:22.913663 PER_BANK_REFRESH: Hybrid Mode
3718 01:24:22.916790 TX_TRACKING: ON
3719 01:24:22.926802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 01:24:22.929991 [FAST_K] Save calibration result to emmc
3721 01:24:22.934201 dramc_set_vcore_voltage set vcore to 650000
3722 01:24:22.934289 Read voltage for 600, 5
3723 01:24:22.936873 Vio18 = 0
3724 01:24:22.936959 Vcore = 650000
3725 01:24:22.937046 Vdram = 0
3726 01:24:22.939860 Vddq = 0
3727 01:24:22.939972 Vmddr = 0
3728 01:24:22.943295 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 01:24:22.949769 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 01:24:22.953149 MEM_TYPE=3, freq_sel=19
3731 01:24:22.956896 sv_algorithm_assistance_LP4_1600
3732 01:24:22.960053 ============ PULL DRAM RESETB DOWN ============
3733 01:24:22.963151 ========== PULL DRAM RESETB DOWN end =========
3734 01:24:22.970167 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 01:24:22.973053 ===================================
3736 01:24:22.973138 LPDDR4 DRAM CONFIGURATION
3737 01:24:22.977273 ===================================
3738 01:24:22.980089 EX_ROW_EN[0] = 0x0
3739 01:24:22.983064 EX_ROW_EN[1] = 0x0
3740 01:24:22.983148 LP4Y_EN = 0x0
3741 01:24:22.986685 WORK_FSP = 0x0
3742 01:24:22.986770 WL = 0x2
3743 01:24:22.989921 RL = 0x2
3744 01:24:22.990006 BL = 0x2
3745 01:24:22.993245 RPST = 0x0
3746 01:24:22.993330 RD_PRE = 0x0
3747 01:24:22.996217 WR_PRE = 0x1
3748 01:24:22.996301 WR_PST = 0x0
3749 01:24:22.999772 DBI_WR = 0x0
3750 01:24:22.999863 DBI_RD = 0x0
3751 01:24:23.002978 OTF = 0x1
3752 01:24:23.006289 ===================================
3753 01:24:23.010126 ===================================
3754 01:24:23.010210 ANA top config
3755 01:24:23.012995 ===================================
3756 01:24:23.016663 DLL_ASYNC_EN = 0
3757 01:24:23.019737 ALL_SLAVE_EN = 1
3758 01:24:23.019822 NEW_RANK_MODE = 1
3759 01:24:23.022952 DLL_IDLE_MODE = 1
3760 01:24:23.026202 LP45_APHY_COMB_EN = 1
3761 01:24:23.029568 TX_ODT_DIS = 1
3762 01:24:23.032698 NEW_8X_MODE = 1
3763 01:24:23.036400 ===================================
3764 01:24:23.039517 ===================================
3765 01:24:23.039602 data_rate = 1200
3766 01:24:23.043059 CKR = 1
3767 01:24:23.046180 DQ_P2S_RATIO = 8
3768 01:24:23.049339 ===================================
3769 01:24:23.052805 CA_P2S_RATIO = 8
3770 01:24:23.056173 DQ_CA_OPEN = 0
3771 01:24:23.059653 DQ_SEMI_OPEN = 0
3772 01:24:23.059778 CA_SEMI_OPEN = 0
3773 01:24:23.063195 CA_FULL_RATE = 0
3774 01:24:23.066250 DQ_CKDIV4_EN = 1
3775 01:24:23.069503 CA_CKDIV4_EN = 1
3776 01:24:23.073172 CA_PREDIV_EN = 0
3777 01:24:23.076013 PH8_DLY = 0
3778 01:24:23.076134 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 01:24:23.079771 DQ_AAMCK_DIV = 4
3780 01:24:23.082591 CA_AAMCK_DIV = 4
3781 01:24:23.086053 CA_ADMCK_DIV = 4
3782 01:24:23.089434 DQ_TRACK_CA_EN = 0
3783 01:24:23.092598 CA_PICK = 600
3784 01:24:23.092722 CA_MCKIO = 600
3785 01:24:23.096446 MCKIO_SEMI = 0
3786 01:24:23.099399 PLL_FREQ = 2288
3787 01:24:23.102754 DQ_UI_PI_RATIO = 32
3788 01:24:23.106128 CA_UI_PI_RATIO = 0
3789 01:24:23.109667 ===================================
3790 01:24:23.113053 ===================================
3791 01:24:23.116404 memory_type:LPDDR4
3792 01:24:23.116487 GP_NUM : 10
3793 01:24:23.119584 SRAM_EN : 1
3794 01:24:23.119667 MD32_EN : 0
3795 01:24:23.122664 ===================================
3796 01:24:23.126080 [ANA_INIT] >>>>>>>>>>>>>>
3797 01:24:23.130149 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 01:24:23.133251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 01:24:23.136209 ===================================
3800 01:24:23.139386 data_rate = 1200,PCW = 0X5800
3801 01:24:23.142623 ===================================
3802 01:24:23.146154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 01:24:23.149544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 01:24:23.155795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 01:24:23.163365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 01:24:23.166003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 01:24:23.169404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 01:24:23.169487 [ANA_INIT] flow start
3809 01:24:23.172938 [ANA_INIT] PLL >>>>>>>>
3810 01:24:23.176001 [ANA_INIT] PLL <<<<<<<<
3811 01:24:23.176085 [ANA_INIT] MIDPI >>>>>>>>
3812 01:24:23.179244 [ANA_INIT] MIDPI <<<<<<<<
3813 01:24:23.183040 [ANA_INIT] DLL >>>>>>>>
3814 01:24:23.183124 [ANA_INIT] flow end
3815 01:24:23.186176 ============ LP4 DIFF to SE enter ============
3816 01:24:23.193369 ============ LP4 DIFF to SE exit ============
3817 01:24:23.193453 [ANA_INIT] <<<<<<<<<<<<<
3818 01:24:23.195813 [Flow] Enable top DCM control >>>>>
3819 01:24:23.199375 [Flow] Enable top DCM control <<<<<
3820 01:24:23.202731 Enable DLL master slave shuffle
3821 01:24:23.209293 ==============================================================
3822 01:24:23.209376 Gating Mode config
3823 01:24:23.216038 ==============================================================
3824 01:24:23.219498 Config description:
3825 01:24:23.228949 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 01:24:23.235796 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 01:24:23.239032 SELPH_MODE 0: By rank 1: By Phase
3828 01:24:23.245754 ==============================================================
3829 01:24:23.248965 GAT_TRACK_EN = 1
3830 01:24:23.252182 RX_GATING_MODE = 2
3831 01:24:23.252265 RX_GATING_TRACK_MODE = 2
3832 01:24:23.255567 SELPH_MODE = 1
3833 01:24:23.258972 PICG_EARLY_EN = 1
3834 01:24:23.262488 VALID_LAT_VALUE = 1
3835 01:24:23.269161 ==============================================================
3836 01:24:23.272142 Enter into Gating configuration >>>>
3837 01:24:23.275652 Exit from Gating configuration <<<<
3838 01:24:23.278927 Enter into DVFS_PRE_config >>>>>
3839 01:24:23.288977 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 01:24:23.292201 Exit from DVFS_PRE_config <<<<<
3841 01:24:23.295794 Enter into PICG configuration >>>>
3842 01:24:23.299493 Exit from PICG configuration <<<<
3843 01:24:23.302339 [RX_INPUT] configuration >>>>>
3844 01:24:23.305676 [RX_INPUT] configuration <<<<<
3845 01:24:23.308655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 01:24:23.315372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 01:24:23.321891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 01:24:23.328733 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 01:24:23.331832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 01:24:23.338436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 01:24:23.341888 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 01:24:23.348518 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 01:24:23.351887 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 01:24:23.355146 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 01:24:23.358385 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 01:24:23.365025 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 01:24:23.368493 ===================================
3858 01:24:23.368577 LPDDR4 DRAM CONFIGURATION
3859 01:24:23.371750 ===================================
3860 01:24:23.375207 EX_ROW_EN[0] = 0x0
3861 01:24:23.378394 EX_ROW_EN[1] = 0x0
3862 01:24:23.378478 LP4Y_EN = 0x0
3863 01:24:23.381671 WORK_FSP = 0x0
3864 01:24:23.381755 WL = 0x2
3865 01:24:23.385046 RL = 0x2
3866 01:24:23.385130 BL = 0x2
3867 01:24:23.388325 RPST = 0x0
3868 01:24:23.388409 RD_PRE = 0x0
3869 01:24:23.391994 WR_PRE = 0x1
3870 01:24:23.392097 WR_PST = 0x0
3871 01:24:23.395017 DBI_WR = 0x0
3872 01:24:23.395101 DBI_RD = 0x0
3873 01:24:23.398079 OTF = 0x1
3874 01:24:23.401678 ===================================
3875 01:24:23.404901 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 01:24:23.408236 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 01:24:23.414635 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 01:24:23.418300 ===================================
3879 01:24:23.418385 LPDDR4 DRAM CONFIGURATION
3880 01:24:23.421265 ===================================
3881 01:24:23.424552 EX_ROW_EN[0] = 0x10
3882 01:24:23.427917 EX_ROW_EN[1] = 0x0
3883 01:24:23.428001 LP4Y_EN = 0x0
3884 01:24:23.431749 WORK_FSP = 0x0
3885 01:24:23.431834 WL = 0x2
3886 01:24:23.434729 RL = 0x2
3887 01:24:23.434814 BL = 0x2
3888 01:24:23.438186 RPST = 0x0
3889 01:24:23.438270 RD_PRE = 0x0
3890 01:24:23.441109 WR_PRE = 0x1
3891 01:24:23.441194 WR_PST = 0x0
3892 01:24:23.444555 DBI_WR = 0x0
3893 01:24:23.444640 DBI_RD = 0x0
3894 01:24:23.447881 OTF = 0x1
3895 01:24:23.451110 ===================================
3896 01:24:23.457834 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 01:24:23.461036 nWR fixed to 30
3898 01:24:23.464442 [ModeRegInit_LP4] CH0 RK0
3899 01:24:23.464526 [ModeRegInit_LP4] CH0 RK1
3900 01:24:23.467708 [ModeRegInit_LP4] CH1 RK0
3901 01:24:23.471004 [ModeRegInit_LP4] CH1 RK1
3902 01:24:23.471128 match AC timing 17
3903 01:24:23.477792 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 01:24:23.481250 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 01:24:23.484464 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 01:24:23.490898 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 01:24:23.494792 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 01:24:23.494879 ==
3909 01:24:23.498144 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 01:24:23.501169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 01:24:23.501256 ==
3912 01:24:23.508023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 01:24:23.514516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3914 01:24:23.517659 [CA 0] Center 36 (6~67) winsize 62
3915 01:24:23.521400 [CA 1] Center 36 (6~67) winsize 62
3916 01:24:23.524699 [CA 2] Center 34 (4~65) winsize 62
3917 01:24:23.528259 [CA 3] Center 34 (3~65) winsize 63
3918 01:24:23.531238 [CA 4] Center 33 (3~64) winsize 62
3919 01:24:23.534555 [CA 5] Center 33 (2~64) winsize 63
3920 01:24:23.534642
3921 01:24:23.537758 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3922 01:24:23.537845
3923 01:24:23.540928 [CATrainingPosCal] consider 1 rank data
3924 01:24:23.544395 u2DelayCellTimex100 = 270/100 ps
3925 01:24:23.547864 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 01:24:23.551048 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 01:24:23.554429 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 01:24:23.557419 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3929 01:24:23.561143 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 01:24:23.564244 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3931 01:24:23.564331
3932 01:24:23.571557 CA PerBit enable=1, Macro0, CA PI delay=33
3933 01:24:23.571644
3934 01:24:23.571730 [CBTSetCACLKResult] CA Dly = 33
3935 01:24:23.574265 CS Dly: 4 (0~35)
3936 01:24:23.574351 ==
3937 01:24:23.577594 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 01:24:23.580931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 01:24:23.581018 ==
3940 01:24:23.587600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 01:24:23.594108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3942 01:24:23.597405 [CA 0] Center 36 (6~67) winsize 62
3943 01:24:23.600929 [CA 1] Center 36 (6~67) winsize 62
3944 01:24:23.603963 [CA 2] Center 34 (4~65) winsize 62
3945 01:24:23.607514 [CA 3] Center 34 (4~65) winsize 62
3946 01:24:23.610830 [CA 4] Center 34 (3~65) winsize 63
3947 01:24:23.614188 [CA 5] Center 33 (3~64) winsize 62
3948 01:24:23.614310
3949 01:24:23.617367 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3950 01:24:23.617488
3951 01:24:23.620989 [CATrainingPosCal] consider 2 rank data
3952 01:24:23.623977 u2DelayCellTimex100 = 270/100 ps
3953 01:24:23.627150 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 01:24:23.630611 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 01:24:23.633998 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 01:24:23.637168 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 01:24:23.640872 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 01:24:23.647112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 01:24:23.647237
3960 01:24:23.650498 CA PerBit enable=1, Macro0, CA PI delay=33
3961 01:24:23.650621
3962 01:24:23.654109 [CBTSetCACLKResult] CA Dly = 33
3963 01:24:23.654234 CS Dly: 5 (0~38)
3964 01:24:23.654350
3965 01:24:23.656940 ----->DramcWriteLeveling(PI) begin...
3966 01:24:23.657065 ==
3967 01:24:23.660283 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 01:24:23.663862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 01:24:23.666873 ==
3970 01:24:23.666999 Write leveling (Byte 0): 33 => 33
3971 01:24:23.670205 Write leveling (Byte 1): 33 => 33
3972 01:24:23.673680 DramcWriteLeveling(PI) end<-----
3973 01:24:23.673804
3974 01:24:23.673918 ==
3975 01:24:23.676928 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 01:24:23.684041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 01:24:23.684168 ==
3978 01:24:23.687118 [Gating] SW mode calibration
3979 01:24:23.694144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 01:24:23.696673 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 01:24:23.703595 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 01:24:23.707022 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 01:24:23.710059 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3984 01:24:23.716920 0 9 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
3985 01:24:23.720147 0 9 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3986 01:24:23.723245 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 01:24:23.726784 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 01:24:23.733452 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 01:24:23.736579 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 01:24:23.739915 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 01:24:23.746611 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3992 01:24:23.750205 0 10 12 | B1->B0 | 2828 3e3e | 0 1 | (1 1) (0 0)
3993 01:24:23.753410 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3994 01:24:23.759870 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 01:24:23.763680 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 01:24:23.767126 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 01:24:23.773225 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 01:24:23.776620 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 01:24:23.780044 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4000 01:24:23.786496 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 01:24:23.789819 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4002 01:24:23.793725 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 01:24:23.799674 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 01:24:23.802993 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 01:24:23.806481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 01:24:23.813400 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 01:24:23.816385 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 01:24:23.819996 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 01:24:23.826729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 01:24:23.829897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 01:24:23.833014 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 01:24:23.839918 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 01:24:23.843199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 01:24:23.846235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 01:24:23.853447 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 01:24:23.856428 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4017 01:24:23.859659 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 01:24:23.863366 Total UI for P1: 0, mck2ui 16
4019 01:24:23.866709 best dqsien dly found for B0: ( 0, 13, 12)
4020 01:24:23.869623 Total UI for P1: 0, mck2ui 16
4021 01:24:23.873239 best dqsien dly found for B1: ( 0, 13, 14)
4022 01:24:23.876389 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4023 01:24:23.879716 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4024 01:24:23.879791
4025 01:24:23.883488 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4026 01:24:23.886749 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4027 01:24:23.889685 [Gating] SW calibration Done
4028 01:24:23.889769 ==
4029 01:24:23.893082 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 01:24:23.899619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 01:24:23.899704 ==
4032 01:24:23.899772 RX Vref Scan: 0
4033 01:24:23.899836
4034 01:24:23.903447 RX Vref 0 -> 0, step: 1
4035 01:24:23.903533
4036 01:24:23.906403 RX Delay -230 -> 252, step: 16
4037 01:24:23.909707 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4038 01:24:23.913095 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 01:24:23.916205 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4040 01:24:23.923093 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4041 01:24:23.926376 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4042 01:24:23.929779 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4043 01:24:23.933046 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4044 01:24:23.936258 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4045 01:24:23.943000 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 01:24:23.946501 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4047 01:24:23.949749 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4048 01:24:23.953036 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4049 01:24:23.959656 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4050 01:24:23.962809 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4051 01:24:23.966110 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 01:24:23.969781 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4053 01:24:23.973334 ==
4054 01:24:23.973419 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 01:24:23.979847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 01:24:23.979932 ==
4057 01:24:23.979998 DQS Delay:
4058 01:24:23.982903 DQS0 = 0, DQS1 = 0
4059 01:24:23.983003 DQM Delay:
4060 01:24:23.986121 DQM0 = 53, DQM1 = 43
4061 01:24:23.986193 DQ Delay:
4062 01:24:23.989532 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4063 01:24:23.992773 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4064 01:24:23.996223 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4065 01:24:23.999461 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4066 01:24:23.999569
4067 01:24:23.999662
4068 01:24:23.999751 ==
4069 01:24:24.002962 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 01:24:24.006685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 01:24:24.006769 ==
4072 01:24:24.006836
4073 01:24:24.006896
4074 01:24:24.009487 TX Vref Scan disable
4075 01:24:24.012868 == TX Byte 0 ==
4076 01:24:24.016654 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 01:24:24.019483 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 01:24:24.022942 == TX Byte 1 ==
4079 01:24:24.026037 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4080 01:24:24.029364 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4081 01:24:24.029464 ==
4082 01:24:24.032868 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 01:24:24.036354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 01:24:24.039519 ==
4085 01:24:24.039627
4086 01:24:24.039720
4087 01:24:24.039809 TX Vref Scan disable
4088 01:24:24.043139 == TX Byte 0 ==
4089 01:24:24.046548 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4090 01:24:24.050054 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4091 01:24:24.053209 == TX Byte 1 ==
4092 01:24:24.056288 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4093 01:24:24.063184 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4094 01:24:24.063268
4095 01:24:24.063336 [DATLAT]
4096 01:24:24.063399 Freq=600, CH0 RK0
4097 01:24:24.063460
4098 01:24:24.066584 DATLAT Default: 0x9
4099 01:24:24.066668 0, 0xFFFF, sum = 0
4100 01:24:24.070112 1, 0xFFFF, sum = 0
4101 01:24:24.070198 2, 0xFFFF, sum = 0
4102 01:24:24.073162 3, 0xFFFF, sum = 0
4103 01:24:24.076403 4, 0xFFFF, sum = 0
4104 01:24:24.076489 5, 0xFFFF, sum = 0
4105 01:24:24.079738 6, 0xFFFF, sum = 0
4106 01:24:24.079824 7, 0xFFFF, sum = 0
4107 01:24:24.082978 8, 0x0, sum = 1
4108 01:24:24.083063 9, 0x0, sum = 2
4109 01:24:24.083133 10, 0x0, sum = 3
4110 01:24:24.086549 11, 0x0, sum = 4
4111 01:24:24.086635 best_step = 9
4112 01:24:24.086702
4113 01:24:24.086765 ==
4114 01:24:24.089806 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 01:24:24.096352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 01:24:24.096436 ==
4117 01:24:24.096503 RX Vref Scan: 1
4118 01:24:24.096566
4119 01:24:24.099577 RX Vref 0 -> 0, step: 1
4120 01:24:24.099660
4121 01:24:24.102855 RX Delay -179 -> 252, step: 8
4122 01:24:24.102964
4123 01:24:24.106071 Set Vref, RX VrefLevel [Byte0]: 59
4124 01:24:24.109334 [Byte1]: 50
4125 01:24:24.109418
4126 01:24:24.112962 Final RX Vref Byte 0 = 59 to rank0
4127 01:24:24.116102 Final RX Vref Byte 1 = 50 to rank0
4128 01:24:24.119699 Final RX Vref Byte 0 = 59 to rank1
4129 01:24:24.122834 Final RX Vref Byte 1 = 50 to rank1==
4130 01:24:24.125952 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 01:24:24.129491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 01:24:24.129575 ==
4133 01:24:24.132711 DQS Delay:
4134 01:24:24.132831 DQS0 = 0, DQS1 = 0
4135 01:24:24.132899 DQM Delay:
4136 01:24:24.136364 DQM0 = 50, DQM1 = 38
4137 01:24:24.136448 DQ Delay:
4138 01:24:24.139390 DQ0 =44, DQ1 =52, DQ2 =48, DQ3 =44
4139 01:24:24.142790 DQ4 =52, DQ5 =40, DQ6 =64, DQ7 =56
4140 01:24:24.146316 DQ8 =32, DQ9 =24, DQ10 =40, DQ11 =32
4141 01:24:24.149435 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4142 01:24:24.149519
4143 01:24:24.149586
4144 01:24:24.159736 [DQSOSCAuto] RK0, (LSB)MR18= 0x5851, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4145 01:24:24.162886 CH0 RK0: MR19=808, MR18=5851
4146 01:24:24.166205 CH0_RK0: MR19=0x808, MR18=0x5851, DQSOSC=393, MR23=63, INC=169, DEC=113
4147 01:24:24.166290
4148 01:24:24.169788 ----->DramcWriteLeveling(PI) begin...
4149 01:24:24.172964 ==
4150 01:24:24.176393 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 01:24:24.179531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 01:24:24.179651 ==
4153 01:24:24.182706 Write leveling (Byte 0): 33 => 33
4154 01:24:24.186195 Write leveling (Byte 1): 33 => 33
4155 01:24:24.189324 DramcWriteLeveling(PI) end<-----
4156 01:24:24.189445
4157 01:24:24.189558 ==
4158 01:24:24.192913 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 01:24:24.196144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 01:24:24.196266 ==
4161 01:24:24.199413 [Gating] SW mode calibration
4162 01:24:24.206057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 01:24:24.209580 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 01:24:24.216089 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 01:24:24.219331 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 01:24:24.222494 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 01:24:24.229286 0 9 12 | B1->B0 | 3232 3131 | 0 1 | (0 0) (0 0)
4168 01:24:24.232742 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
4169 01:24:24.235995 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 01:24:24.242818 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 01:24:24.245912 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 01:24:24.249379 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 01:24:24.256119 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 01:24:24.259438 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 01:24:24.262869 0 10 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (0 0)
4176 01:24:24.269416 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4177 01:24:24.273453 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 01:24:24.275817 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 01:24:24.282501 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 01:24:24.286376 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 01:24:24.289369 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 01:24:24.295812 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 01:24:24.299132 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4184 01:24:24.302423 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 01:24:24.309147 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 01:24:24.312335 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 01:24:24.315977 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 01:24:24.322473 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 01:24:24.325849 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 01:24:24.329369 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 01:24:24.332724 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 01:24:24.339254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 01:24:24.342300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 01:24:24.346044 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 01:24:24.352528 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 01:24:24.355710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 01:24:24.359042 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 01:24:24.365697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 01:24:24.368933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4200 01:24:24.372512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 01:24:24.375565 Total UI for P1: 0, mck2ui 16
4202 01:24:24.378845 best dqsien dly found for B0: ( 0, 13, 12)
4203 01:24:24.382371 Total UI for P1: 0, mck2ui 16
4204 01:24:24.385870 best dqsien dly found for B1: ( 0, 13, 14)
4205 01:24:24.389009 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 01:24:24.392557 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4207 01:24:24.392642
4208 01:24:24.398958 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 01:24:24.402232 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4210 01:24:24.405659 [Gating] SW calibration Done
4211 01:24:24.405744 ==
4212 01:24:24.409328 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 01:24:24.412424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 01:24:24.412508 ==
4215 01:24:24.412576 RX Vref Scan: 0
4216 01:24:24.412640
4217 01:24:24.415939 RX Vref 0 -> 0, step: 1
4218 01:24:24.416023
4219 01:24:24.419061 RX Delay -230 -> 252, step: 16
4220 01:24:24.422468 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4221 01:24:24.425550 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4222 01:24:24.432604 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4223 01:24:24.435720 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4224 01:24:24.438941 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4225 01:24:24.442243 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4226 01:24:24.449149 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4227 01:24:24.452395 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4228 01:24:24.455679 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4229 01:24:24.459092 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4230 01:24:24.462709 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4231 01:24:24.469095 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4232 01:24:24.472702 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4233 01:24:24.475709 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4234 01:24:24.479144 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4235 01:24:24.485840 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4236 01:24:24.485925 ==
4237 01:24:24.489670 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 01:24:24.492332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 01:24:24.492417 ==
4240 01:24:24.492485 DQS Delay:
4241 01:24:24.495728 DQS0 = 0, DQS1 = 0
4242 01:24:24.495812 DQM Delay:
4243 01:24:24.498919 DQM0 = 50, DQM1 = 41
4244 01:24:24.499003 DQ Delay:
4245 01:24:24.502225 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4246 01:24:24.505783 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4247 01:24:24.509382 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4248 01:24:24.512510 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4249 01:24:24.512595
4250 01:24:24.512662
4251 01:24:24.512725 ==
4252 01:24:24.515744 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 01:24:24.519449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 01:24:24.519534 ==
4255 01:24:24.519602
4256 01:24:24.519664
4257 01:24:24.522602 TX Vref Scan disable
4258 01:24:24.526112 == TX Byte 0 ==
4259 01:24:24.529148 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4260 01:24:24.533085 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4261 01:24:24.535611 == TX Byte 1 ==
4262 01:24:24.539053 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4263 01:24:24.542893 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4264 01:24:24.542977 ==
4265 01:24:24.545757 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 01:24:24.552570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 01:24:24.552674 ==
4268 01:24:24.552743
4269 01:24:24.552827
4270 01:24:24.552888 TX Vref Scan disable
4271 01:24:24.556826 == TX Byte 0 ==
4272 01:24:24.559904 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4273 01:24:24.566656 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4274 01:24:24.566740 == TX Byte 1 ==
4275 01:24:24.569845 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4276 01:24:24.576762 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4277 01:24:24.576860
4278 01:24:24.576926 [DATLAT]
4279 01:24:24.576989 Freq=600, CH0 RK1
4280 01:24:24.577051
4281 01:24:24.580048 DATLAT Default: 0x9
4282 01:24:24.580145 0, 0xFFFF, sum = 0
4283 01:24:24.582947 1, 0xFFFF, sum = 0
4284 01:24:24.583032 2, 0xFFFF, sum = 0
4285 01:24:24.586567 3, 0xFFFF, sum = 0
4286 01:24:24.590030 4, 0xFFFF, sum = 0
4287 01:24:24.590117 5, 0xFFFF, sum = 0
4288 01:24:24.593082 6, 0xFFFF, sum = 0
4289 01:24:24.593167 7, 0xFFFF, sum = 0
4290 01:24:24.593236 8, 0x0, sum = 1
4291 01:24:24.596376 9, 0x0, sum = 2
4292 01:24:24.596462 10, 0x0, sum = 3
4293 01:24:24.599669 11, 0x0, sum = 4
4294 01:24:24.599753 best_step = 9
4295 01:24:24.599818
4296 01:24:24.599879 ==
4297 01:24:24.603061 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 01:24:24.609693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 01:24:24.609776 ==
4300 01:24:24.609841 RX Vref Scan: 0
4301 01:24:24.609902
4302 01:24:24.612967 RX Vref 0 -> 0, step: 1
4303 01:24:24.613052
4304 01:24:24.616401 RX Delay -179 -> 252, step: 8
4305 01:24:24.619317 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4306 01:24:24.626013 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4307 01:24:24.629757 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4308 01:24:24.633038 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4309 01:24:24.636000 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4310 01:24:24.639621 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4311 01:24:24.646268 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4312 01:24:24.649472 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4313 01:24:24.652710 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4314 01:24:24.656051 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4315 01:24:24.659334 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4316 01:24:24.666062 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4317 01:24:24.669681 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4318 01:24:24.673091 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4319 01:24:24.676222 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4320 01:24:24.679618 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4321 01:24:24.682848 ==
4322 01:24:24.686766 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 01:24:24.689381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 01:24:24.689462 ==
4325 01:24:24.689527 DQS Delay:
4326 01:24:24.692769 DQS0 = 0, DQS1 = 0
4327 01:24:24.692850 DQM Delay:
4328 01:24:24.696440 DQM0 = 48, DQM1 = 42
4329 01:24:24.696521 DQ Delay:
4330 01:24:24.699410 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4331 01:24:24.703009 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4332 01:24:24.706244 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4333 01:24:24.709246 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4334 01:24:24.709328
4335 01:24:24.709393
4336 01:24:24.716199 [DQSOSCAuto] RK1, (LSB)MR18= 0x6836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4337 01:24:24.719398 CH0 RK1: MR19=808, MR18=6836
4338 01:24:24.725786 CH0_RK1: MR19=0x808, MR18=0x6836, DQSOSC=390, MR23=63, INC=172, DEC=114
4339 01:24:24.729215 [RxdqsGatingPostProcess] freq 600
4340 01:24:24.735741 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 01:24:24.739271 Pre-setting of DQS Precalculation
4342 01:24:24.742727 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 01:24:24.742810 ==
4344 01:24:24.746047 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 01:24:24.749194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 01:24:24.749277 ==
4347 01:24:24.756015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 01:24:24.762358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4349 01:24:24.765661 [CA 0] Center 35 (5~66) winsize 62
4350 01:24:24.769175 [CA 1] Center 35 (5~66) winsize 62
4351 01:24:24.772300 [CA 2] Center 34 (4~65) winsize 62
4352 01:24:24.775670 [CA 3] Center 33 (3~64) winsize 62
4353 01:24:24.779064 [CA 4] Center 34 (3~65) winsize 63
4354 01:24:24.782508 [CA 5] Center 33 (3~64) winsize 62
4355 01:24:24.782591
4356 01:24:24.785734 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4357 01:24:24.785817
4358 01:24:24.789142 [CATrainingPosCal] consider 1 rank data
4359 01:24:24.792437 u2DelayCellTimex100 = 270/100 ps
4360 01:24:24.795739 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4361 01:24:24.798797 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4362 01:24:24.802213 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 01:24:24.805871 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4364 01:24:24.809380 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4365 01:24:24.812279 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 01:24:24.815556
4367 01:24:24.818889 CA PerBit enable=1, Macro0, CA PI delay=33
4368 01:24:24.818973
4369 01:24:24.822338 [CBTSetCACLKResult] CA Dly = 33
4370 01:24:24.822422 CS Dly: 5 (0~36)
4371 01:24:24.822491 ==
4372 01:24:24.825828 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 01:24:24.828827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 01:24:24.828911 ==
4375 01:24:24.835551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 01:24:24.842098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 01:24:24.845402 [CA 0] Center 35 (5~66) winsize 62
4378 01:24:24.848651 [CA 1] Center 35 (5~66) winsize 62
4379 01:24:24.852341 [CA 2] Center 34 (4~65) winsize 62
4380 01:24:24.855204 [CA 3] Center 34 (4~65) winsize 62
4381 01:24:24.858572 [CA 4] Center 34 (4~65) winsize 62
4382 01:24:24.861927 [CA 5] Center 33 (3~64) winsize 62
4383 01:24:24.862011
4384 01:24:24.866001 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 01:24:24.866085
4386 01:24:24.868474 [CATrainingPosCal] consider 2 rank data
4387 01:24:24.871878 u2DelayCellTimex100 = 270/100 ps
4388 01:24:24.875479 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 01:24:24.878490 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 01:24:24.881930 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 01:24:24.885372 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4392 01:24:24.891905 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 01:24:24.895392 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 01:24:24.895475
4395 01:24:24.898988 CA PerBit enable=1, Macro0, CA PI delay=33
4396 01:24:24.899071
4397 01:24:24.902090 [CBTSetCACLKResult] CA Dly = 33
4398 01:24:24.902173 CS Dly: 5 (0~37)
4399 01:24:24.902240
4400 01:24:24.905773 ----->DramcWriteLeveling(PI) begin...
4401 01:24:24.905859 ==
4402 01:24:24.908702 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 01:24:24.915382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 01:24:24.915466 ==
4405 01:24:24.918430 Write leveling (Byte 0): 31 => 31
4406 01:24:24.918514 Write leveling (Byte 1): 30 => 30
4407 01:24:24.922065 DramcWriteLeveling(PI) end<-----
4408 01:24:24.922148
4409 01:24:24.922214 ==
4410 01:24:24.925069 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 01:24:24.931708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 01:24:24.931792 ==
4413 01:24:24.935156 [Gating] SW mode calibration
4414 01:24:24.942038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 01:24:24.945158 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 01:24:24.951723 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 01:24:24.955339 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 01:24:24.958504 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 01:24:24.965256 0 9 12 | B1->B0 | 2d2d 2d2d | 1 1 | (1 1) (1 0)
4420 01:24:24.968288 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 01:24:24.971825 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 01:24:24.978379 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 01:24:24.981521 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 01:24:24.985070 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 01:24:24.991713 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 01:24:24.994938 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4427 01:24:24.998191 0 10 12 | B1->B0 | 3838 3c3c | 1 0 | (0 0) (0 0)
4428 01:24:25.001596 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 01:24:25.008170 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 01:24:25.011833 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 01:24:25.014814 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 01:24:25.021641 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 01:24:25.025081 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 01:24:25.028289 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4435 01:24:25.035029 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4436 01:24:25.037760 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 01:24:25.041207 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 01:24:25.047956 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 01:24:25.051181 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 01:24:25.054407 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 01:24:25.061769 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 01:24:25.064662 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 01:24:25.067661 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 01:24:25.074381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 01:24:25.077823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 01:24:25.080906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 01:24:25.087679 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 01:24:25.091188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 01:24:25.094214 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 01:24:25.100927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 01:24:25.104276 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4452 01:24:25.107954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 01:24:25.111087 Total UI for P1: 0, mck2ui 16
4454 01:24:25.114769 best dqsien dly found for B0: ( 0, 13, 12)
4455 01:24:25.117589 Total UI for P1: 0, mck2ui 16
4456 01:24:25.120930 best dqsien dly found for B1: ( 0, 13, 14)
4457 01:24:25.124256 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4458 01:24:25.127612 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4459 01:24:25.127696
4460 01:24:25.134170 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4461 01:24:25.137541 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4462 01:24:25.137625 [Gating] SW calibration Done
4463 01:24:25.141005 ==
4464 01:24:25.141088 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 01:24:25.148112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 01:24:25.148197 ==
4467 01:24:25.148263 RX Vref Scan: 0
4468 01:24:25.148327
4469 01:24:25.150965 RX Vref 0 -> 0, step: 1
4470 01:24:25.151048
4471 01:24:25.154541 RX Delay -230 -> 252, step: 16
4472 01:24:25.157551 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4473 01:24:25.161068 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4474 01:24:25.167409 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4475 01:24:25.170927 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4476 01:24:25.174316 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4477 01:24:25.177586 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4478 01:24:25.180781 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 01:24:25.187392 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4480 01:24:25.190837 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4481 01:24:25.193922 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4482 01:24:25.197396 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4483 01:24:25.203992 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4484 01:24:25.207256 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4485 01:24:25.210532 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4486 01:24:25.213953 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4487 01:24:25.220673 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4488 01:24:25.220815 ==
4489 01:24:25.224238 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 01:24:25.227040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 01:24:25.227124 ==
4492 01:24:25.227191 DQS Delay:
4493 01:24:25.230616 DQS0 = 0, DQS1 = 0
4494 01:24:25.230699 DQM Delay:
4495 01:24:25.233689 DQM0 = 52, DQM1 = 42
4496 01:24:25.233772 DQ Delay:
4497 01:24:25.237228 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4498 01:24:25.240289 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4499 01:24:25.243682 DQ8 =25, DQ9 =25, DQ10 =49, DQ11 =33
4500 01:24:25.247091 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4501 01:24:25.247175
4502 01:24:25.247241
4503 01:24:25.247302 ==
4504 01:24:25.250903 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 01:24:25.253790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 01:24:25.253874 ==
4507 01:24:25.253940
4508 01:24:25.254001
4509 01:24:25.257197 TX Vref Scan disable
4510 01:24:25.260453 == TX Byte 0 ==
4511 01:24:25.264017 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4512 01:24:25.267336 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4513 01:24:25.270618 == TX Byte 1 ==
4514 01:24:25.274023 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 01:24:25.277120 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 01:24:25.277208 ==
4517 01:24:25.280239 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 01:24:25.287065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 01:24:25.287153 ==
4520 01:24:25.287240
4521 01:24:25.287322
4522 01:24:25.287401 TX Vref Scan disable
4523 01:24:25.291228 == TX Byte 0 ==
4524 01:24:25.294602 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4525 01:24:25.297944 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4526 01:24:25.301227 == TX Byte 1 ==
4527 01:24:25.305130 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4528 01:24:25.308097 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4529 01:24:25.311505
4530 01:24:25.311627 [DATLAT]
4531 01:24:25.311714 Freq=600, CH1 RK0
4532 01:24:25.311796
4533 01:24:25.314556 DATLAT Default: 0x9
4534 01:24:25.314643 0, 0xFFFF, sum = 0
4535 01:24:25.318032 1, 0xFFFF, sum = 0
4536 01:24:25.318120 2, 0xFFFF, sum = 0
4537 01:24:25.321563 3, 0xFFFF, sum = 0
4538 01:24:25.321651 4, 0xFFFF, sum = 0
4539 01:24:25.324910 5, 0xFFFF, sum = 0
4540 01:24:25.324997 6, 0xFFFF, sum = 0
4541 01:24:25.328415 7, 0xFFFF, sum = 0
4542 01:24:25.328503 8, 0x0, sum = 1
4543 01:24:25.331700 9, 0x0, sum = 2
4544 01:24:25.331813 10, 0x0, sum = 3
4545 01:24:25.334955 11, 0x0, sum = 4
4546 01:24:25.335041 best_step = 9
4547 01:24:25.335108
4548 01:24:25.335170 ==
4549 01:24:25.338205 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 01:24:25.344777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 01:24:25.344876 ==
4552 01:24:25.344944 RX Vref Scan: 1
4553 01:24:25.345007
4554 01:24:25.347890 RX Vref 0 -> 0, step: 1
4555 01:24:25.347975
4556 01:24:25.351812 RX Delay -179 -> 252, step: 8
4557 01:24:25.351897
4558 01:24:25.354658 Set Vref, RX VrefLevel [Byte0]: 51
4559 01:24:25.357856 [Byte1]: 53
4560 01:24:25.357940
4561 01:24:25.361132 Final RX Vref Byte 0 = 51 to rank0
4562 01:24:25.364436 Final RX Vref Byte 1 = 53 to rank0
4563 01:24:25.367865 Final RX Vref Byte 0 = 51 to rank1
4564 01:24:25.371148 Final RX Vref Byte 1 = 53 to rank1==
4565 01:24:25.374467 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 01:24:25.377749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 01:24:25.377873 ==
4568 01:24:25.381150 DQS Delay:
4569 01:24:25.381273 DQS0 = 0, DQS1 = 0
4570 01:24:25.381388 DQM Delay:
4571 01:24:25.384413 DQM0 = 49, DQM1 = 41
4572 01:24:25.384531 DQ Delay:
4573 01:24:25.388389 DQ0 =56, DQ1 =48, DQ2 =36, DQ3 =44
4574 01:24:25.391252 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4575 01:24:25.394268 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4576 01:24:25.397730 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4577 01:24:25.397851
4578 01:24:25.397966
4579 01:24:25.407679 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4580 01:24:25.407801 CH1 RK0: MR19=808, MR18=4C73
4581 01:24:25.414653 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4582 01:24:25.414738
4583 01:24:25.418099 ----->DramcWriteLeveling(PI) begin...
4584 01:24:25.420872 ==
4585 01:24:25.424039 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 01:24:25.427797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 01:24:25.427882 ==
4588 01:24:25.430871 Write leveling (Byte 0): 29 => 29
4589 01:24:25.434110 Write leveling (Byte 1): 31 => 31
4590 01:24:25.437441 DramcWriteLeveling(PI) end<-----
4591 01:24:25.437526
4592 01:24:25.437593 ==
4593 01:24:25.441093 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 01:24:25.444458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 01:24:25.444542 ==
4596 01:24:25.447761 [Gating] SW mode calibration
4597 01:24:25.454120 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 01:24:25.460783 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 01:24:25.464374 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 01:24:25.467216 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 01:24:25.473933 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4602 01:24:25.477737 0 9 12 | B1->B0 | 2929 3030 | 0 0 | (0 1) (0 1)
4603 01:24:25.480724 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4604 01:24:25.484093 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 01:24:25.490815 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 01:24:25.494204 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 01:24:25.497585 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 01:24:25.504074 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 01:24:25.507442 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4610 01:24:25.510828 0 10 12 | B1->B0 | 4040 3231 | 0 1 | (0 0) (0 0)
4611 01:24:25.517467 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4612 01:24:25.520641 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 01:24:25.523991 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 01:24:25.530844 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 01:24:25.533902 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 01:24:25.537181 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 01:24:25.543854 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 01:24:25.547332 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 01:24:25.550949 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 01:24:25.557286 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 01:24:25.560498 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 01:24:25.564269 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 01:24:25.571155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 01:24:25.573744 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 01:24:25.577069 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 01:24:25.583763 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 01:24:25.587638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 01:24:25.590196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 01:24:25.593701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 01:24:25.600348 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 01:24:25.604042 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 01:24:25.606932 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 01:24:25.613688 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 01:24:25.617343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 01:24:25.620400 Total UI for P1: 0, mck2ui 16
4636 01:24:25.623518 best dqsien dly found for B0: ( 0, 13, 10)
4637 01:24:25.626900 Total UI for P1: 0, mck2ui 16
4638 01:24:25.630325 best dqsien dly found for B1: ( 0, 13, 10)
4639 01:24:25.633918 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4640 01:24:25.637015 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4641 01:24:25.637098
4642 01:24:25.640347 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4643 01:24:25.647041 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4644 01:24:25.647145 [Gating] SW calibration Done
4645 01:24:25.647237 ==
4646 01:24:25.650069 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 01:24:25.656956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 01:24:25.657079 ==
4649 01:24:25.657190 RX Vref Scan: 0
4650 01:24:25.657302
4651 01:24:25.660623 RX Vref 0 -> 0, step: 1
4652 01:24:25.660741
4653 01:24:25.663898 RX Delay -230 -> 252, step: 16
4654 01:24:25.667195 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4655 01:24:25.670152 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4656 01:24:25.673680 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4657 01:24:25.680275 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4658 01:24:25.683801 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4659 01:24:25.686766 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4660 01:24:25.690097 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4661 01:24:25.693545 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4662 01:24:25.700115 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4663 01:24:25.703661 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4664 01:24:25.706973 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4665 01:24:25.710221 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4666 01:24:25.716982 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4667 01:24:25.719955 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4668 01:24:25.723312 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4669 01:24:25.726448 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4670 01:24:25.726573 ==
4671 01:24:25.729946 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 01:24:25.736540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 01:24:25.736627 ==
4674 01:24:25.736696 DQS Delay:
4675 01:24:25.739823 DQS0 = 0, DQS1 = 0
4676 01:24:25.739906 DQM Delay:
4677 01:24:25.739973 DQM0 = 52, DQM1 = 47
4678 01:24:25.743393 DQ Delay:
4679 01:24:25.746419 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4680 01:24:25.749997 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4681 01:24:25.753658 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4682 01:24:25.756663 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4683 01:24:25.756748
4684 01:24:25.756858
4685 01:24:25.756922 ==
4686 01:24:25.759752 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 01:24:25.763710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 01:24:25.763794 ==
4689 01:24:25.763862
4690 01:24:25.763924
4691 01:24:25.766380 TX Vref Scan disable
4692 01:24:25.770338 == TX Byte 0 ==
4693 01:24:25.773328 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 01:24:25.776352 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 01:24:25.779616 == TX Byte 1 ==
4696 01:24:25.783245 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4697 01:24:25.786259 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4698 01:24:25.786343 ==
4699 01:24:25.790008 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 01:24:25.793038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 01:24:25.796458 ==
4702 01:24:25.796542
4703 01:24:25.796608
4704 01:24:25.796670 TX Vref Scan disable
4705 01:24:25.800040 == TX Byte 0 ==
4706 01:24:25.803271 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 01:24:25.806936 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 01:24:25.810015 == TX Byte 1 ==
4709 01:24:25.814074 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4710 01:24:25.819951 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4711 01:24:25.820037
4712 01:24:25.820104 [DATLAT]
4713 01:24:25.820167 Freq=600, CH1 RK1
4714 01:24:25.820229
4715 01:24:25.823378 DATLAT Default: 0x9
4716 01:24:25.823463 0, 0xFFFF, sum = 0
4717 01:24:25.826660 1, 0xFFFF, sum = 0
4718 01:24:25.826746 2, 0xFFFF, sum = 0
4719 01:24:25.829875 3, 0xFFFF, sum = 0
4720 01:24:25.833372 4, 0xFFFF, sum = 0
4721 01:24:25.833458 5, 0xFFFF, sum = 0
4722 01:24:25.836533 6, 0xFFFF, sum = 0
4723 01:24:25.836619 7, 0xFFFF, sum = 0
4724 01:24:25.836688 8, 0x0, sum = 1
4725 01:24:25.840074 9, 0x0, sum = 2
4726 01:24:25.840160 10, 0x0, sum = 3
4727 01:24:25.843318 11, 0x0, sum = 4
4728 01:24:25.843440 best_step = 9
4729 01:24:25.843535
4730 01:24:25.843626 ==
4731 01:24:25.846513 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 01:24:25.853424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 01:24:25.853508 ==
4734 01:24:25.853575 RX Vref Scan: 0
4735 01:24:25.853638
4736 01:24:25.856631 RX Vref 0 -> 0, step: 1
4737 01:24:25.856723
4738 01:24:25.860003 RX Delay -163 -> 252, step: 8
4739 01:24:25.863373 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4740 01:24:25.867000 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4741 01:24:25.873511 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4742 01:24:25.876652 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4743 01:24:25.880497 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4744 01:24:25.883513 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4745 01:24:25.886824 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4746 01:24:25.893457 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4747 01:24:25.896418 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4748 01:24:25.899769 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4749 01:24:25.903049 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4750 01:24:25.909620 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4751 01:24:25.913096 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4752 01:24:25.916352 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4753 01:24:25.920090 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4754 01:24:25.923214 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4755 01:24:25.926774 ==
4756 01:24:25.929813 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 01:24:25.933264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 01:24:25.933386 ==
4759 01:24:25.933503 DQS Delay:
4760 01:24:25.936704 DQS0 = 0, DQS1 = 0
4761 01:24:25.936846 DQM Delay:
4762 01:24:25.939641 DQM0 = 49, DQM1 = 44
4763 01:24:25.939763 DQ Delay:
4764 01:24:25.943097 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4765 01:24:25.946385 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4766 01:24:25.949853 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4767 01:24:25.953341 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =56
4768 01:24:25.953423
4769 01:24:25.953489
4770 01:24:25.959590 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4771 01:24:25.963143 CH1 RK1: MR19=808, MR18=5A20
4772 01:24:25.969840 CH1_RK1: MR19=0x808, MR18=0x5A20, DQSOSC=392, MR23=63, INC=170, DEC=113
4773 01:24:25.973058 [RxdqsGatingPostProcess] freq 600
4774 01:24:25.979369 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4775 01:24:25.979453 Pre-setting of DQS Precalculation
4776 01:24:25.985865 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4777 01:24:25.992544 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4778 01:24:25.999518 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4779 01:24:25.999602
4780 01:24:25.999668
4781 01:24:26.002572 [Calibration Summary] 1200 Mbps
4782 01:24:26.006050 CH 0, Rank 0
4783 01:24:26.006176 SW Impedance : PASS
4784 01:24:26.009518 DUTY Scan : NO K
4785 01:24:26.012679 ZQ Calibration : PASS
4786 01:24:26.012820 Jitter Meter : NO K
4787 01:24:26.015896 CBT Training : PASS
4788 01:24:26.019222 Write leveling : PASS
4789 01:24:26.019344 RX DQS gating : PASS
4790 01:24:26.022709 RX DQ/DQS(RDDQC) : PASS
4791 01:24:26.022830 TX DQ/DQS : PASS
4792 01:24:26.025808 RX DATLAT : PASS
4793 01:24:26.029352 RX DQ/DQS(Engine): PASS
4794 01:24:26.029475 TX OE : NO K
4795 01:24:26.032602 All Pass.
4796 01:24:26.032723
4797 01:24:26.032871 CH 0, Rank 1
4798 01:24:26.035735 SW Impedance : PASS
4799 01:24:26.035856 DUTY Scan : NO K
4800 01:24:26.039250 ZQ Calibration : PASS
4801 01:24:26.042516 Jitter Meter : NO K
4802 01:24:26.042637 CBT Training : PASS
4803 01:24:26.045718 Write leveling : PASS
4804 01:24:26.049351 RX DQS gating : PASS
4805 01:24:26.049474 RX DQ/DQS(RDDQC) : PASS
4806 01:24:26.052327 TX DQ/DQS : PASS
4807 01:24:26.055976 RX DATLAT : PASS
4808 01:24:26.056102 RX DQ/DQS(Engine): PASS
4809 01:24:26.059233 TX OE : NO K
4810 01:24:26.059354 All Pass.
4811 01:24:26.059470
4812 01:24:26.059575 CH 1, Rank 0
4813 01:24:26.062379 SW Impedance : PASS
4814 01:24:26.065661 DUTY Scan : NO K
4815 01:24:26.065744 ZQ Calibration : PASS
4816 01:24:26.069013 Jitter Meter : NO K
4817 01:24:26.072413 CBT Training : PASS
4818 01:24:26.072522 Write leveling : PASS
4819 01:24:26.076086 RX DQS gating : PASS
4820 01:24:26.078918 RX DQ/DQS(RDDQC) : PASS
4821 01:24:26.079001 TX DQ/DQS : PASS
4822 01:24:26.082836 RX DATLAT : PASS
4823 01:24:26.085717 RX DQ/DQS(Engine): PASS
4824 01:24:26.085800 TX OE : NO K
4825 01:24:26.089050 All Pass.
4826 01:24:26.089158
4827 01:24:26.089251 CH 1, Rank 1
4828 01:24:26.092660 SW Impedance : PASS
4829 01:24:26.092803 DUTY Scan : NO K
4830 01:24:26.095715 ZQ Calibration : PASS
4831 01:24:26.099503 Jitter Meter : NO K
4832 01:24:26.099585 CBT Training : PASS
4833 01:24:26.102675 Write leveling : PASS
4834 01:24:26.105732 RX DQS gating : PASS
4835 01:24:26.105829 RX DQ/DQS(RDDQC) : PASS
4836 01:24:26.108978 TX DQ/DQS : PASS
4837 01:24:26.109081 RX DATLAT : PASS
4838 01:24:26.112250 RX DQ/DQS(Engine): PASS
4839 01:24:26.115491 TX OE : NO K
4840 01:24:26.115575 All Pass.
4841 01:24:26.115642
4842 01:24:26.119127 DramC Write-DBI off
4843 01:24:26.119211 PER_BANK_REFRESH: Hybrid Mode
4844 01:24:26.122136 TX_TRACKING: ON
4845 01:24:26.132147 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4846 01:24:26.135669 [FAST_K] Save calibration result to emmc
4847 01:24:26.138912 dramc_set_vcore_voltage set vcore to 662500
4848 01:24:26.138995 Read voltage for 933, 3
4849 01:24:26.142166 Vio18 = 0
4850 01:24:26.142249 Vcore = 662500
4851 01:24:26.142316 Vdram = 0
4852 01:24:26.145590 Vddq = 0
4853 01:24:26.145674 Vmddr = 0
4854 01:24:26.149391 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4855 01:24:26.155325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4856 01:24:26.158937 MEM_TYPE=3, freq_sel=17
4857 01:24:26.162113 sv_algorithm_assistance_LP4_1600
4858 01:24:26.165444 ============ PULL DRAM RESETB DOWN ============
4859 01:24:26.169041 ========== PULL DRAM RESETB DOWN end =========
4860 01:24:26.175461 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 01:24:26.179446 ===================================
4862 01:24:26.179530 LPDDR4 DRAM CONFIGURATION
4863 01:24:26.182205 ===================================
4864 01:24:26.185709 EX_ROW_EN[0] = 0x0
4865 01:24:26.185794 EX_ROW_EN[1] = 0x0
4866 01:24:26.189349 LP4Y_EN = 0x0
4867 01:24:26.189433 WORK_FSP = 0x0
4868 01:24:26.192125 WL = 0x3
4869 01:24:26.192208 RL = 0x3
4870 01:24:26.195820 BL = 0x2
4871 01:24:26.198983 RPST = 0x0
4872 01:24:26.199067 RD_PRE = 0x0
4873 01:24:26.202302 WR_PRE = 0x1
4874 01:24:26.202386 WR_PST = 0x0
4875 01:24:26.205509 DBI_WR = 0x0
4876 01:24:26.205593 DBI_RD = 0x0
4877 01:24:26.209031 OTF = 0x1
4878 01:24:26.212636 ===================================
4879 01:24:26.215690 ===================================
4880 01:24:26.215773 ANA top config
4881 01:24:26.218905 ===================================
4882 01:24:26.222282 DLL_ASYNC_EN = 0
4883 01:24:26.225458 ALL_SLAVE_EN = 1
4884 01:24:26.225541 NEW_RANK_MODE = 1
4885 01:24:26.228773 DLL_IDLE_MODE = 1
4886 01:24:26.232128 LP45_APHY_COMB_EN = 1
4887 01:24:26.235498 TX_ODT_DIS = 1
4888 01:24:26.235582 NEW_8X_MODE = 1
4889 01:24:26.239320 ===================================
4890 01:24:26.241923 ===================================
4891 01:24:26.245282 data_rate = 1866
4892 01:24:26.248495 CKR = 1
4893 01:24:26.252111 DQ_P2S_RATIO = 8
4894 01:24:26.255336 ===================================
4895 01:24:26.258768 CA_P2S_RATIO = 8
4896 01:24:26.262171 DQ_CA_OPEN = 0
4897 01:24:26.262255 DQ_SEMI_OPEN = 0
4898 01:24:26.265623 CA_SEMI_OPEN = 0
4899 01:24:26.268726 CA_FULL_RATE = 0
4900 01:24:26.272029 DQ_CKDIV4_EN = 1
4901 01:24:26.275643 CA_CKDIV4_EN = 1
4902 01:24:26.278663 CA_PREDIV_EN = 0
4903 01:24:26.278747 PH8_DLY = 0
4904 01:24:26.281767 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4905 01:24:26.285407 DQ_AAMCK_DIV = 4
4906 01:24:26.288509 CA_AAMCK_DIV = 4
4907 01:24:26.292100 CA_ADMCK_DIV = 4
4908 01:24:26.295525 DQ_TRACK_CA_EN = 0
4909 01:24:26.295610 CA_PICK = 933
4910 01:24:26.298480 CA_MCKIO = 933
4911 01:24:26.302039 MCKIO_SEMI = 0
4912 01:24:26.304898 PLL_FREQ = 3732
4913 01:24:26.308595 DQ_UI_PI_RATIO = 32
4914 01:24:26.311662 CA_UI_PI_RATIO = 0
4915 01:24:26.315346 ===================================
4916 01:24:26.318379 ===================================
4917 01:24:26.321553 memory_type:LPDDR4
4918 01:24:26.321636 GP_NUM : 10
4919 01:24:26.325722 SRAM_EN : 1
4920 01:24:26.325806 MD32_EN : 0
4921 01:24:26.328667 ===================================
4922 01:24:26.331874 [ANA_INIT] >>>>>>>>>>>>>>
4923 01:24:26.334870 <<<<<< [CONFIGURE PHASE]: ANA_TX
4924 01:24:26.338278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4925 01:24:26.342054 ===================================
4926 01:24:26.345133 data_rate = 1866,PCW = 0X8f00
4927 01:24:26.348618 ===================================
4928 01:24:26.351590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4929 01:24:26.355022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 01:24:26.361660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 01:24:26.365137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4932 01:24:26.371463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4933 01:24:26.374806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4934 01:24:26.374891 [ANA_INIT] flow start
4935 01:24:26.378091 [ANA_INIT] PLL >>>>>>>>
4936 01:24:26.381708 [ANA_INIT] PLL <<<<<<<<
4937 01:24:26.381793 [ANA_INIT] MIDPI >>>>>>>>
4938 01:24:26.385018 [ANA_INIT] MIDPI <<<<<<<<
4939 01:24:26.388157 [ANA_INIT] DLL >>>>>>>>
4940 01:24:26.388241 [ANA_INIT] flow end
4941 01:24:26.391531 ============ LP4 DIFF to SE enter ============
4942 01:24:26.398132 ============ LP4 DIFF to SE exit ============
4943 01:24:26.398221 [ANA_INIT] <<<<<<<<<<<<<
4944 01:24:26.401972 [Flow] Enable top DCM control >>>>>
4945 01:24:26.405118 [Flow] Enable top DCM control <<<<<
4946 01:24:26.408160 Enable DLL master slave shuffle
4947 01:24:26.414930 ==============================================================
4948 01:24:26.415055 Gating Mode config
4949 01:24:26.421721 ==============================================================
4950 01:24:26.424786 Config description:
4951 01:24:26.434957 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4952 01:24:26.441823 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4953 01:24:26.445055 SELPH_MODE 0: By rank 1: By Phase
4954 01:24:26.452146 ==============================================================
4955 01:24:26.454908 GAT_TRACK_EN = 1
4956 01:24:26.455029 RX_GATING_MODE = 2
4957 01:24:26.459266 RX_GATING_TRACK_MODE = 2
4958 01:24:26.461357 SELPH_MODE = 1
4959 01:24:26.464826 PICG_EARLY_EN = 1
4960 01:24:26.468242 VALID_LAT_VALUE = 1
4961 01:24:26.474888 ==============================================================
4962 01:24:26.478347 Enter into Gating configuration >>>>
4963 01:24:26.481812 Exit from Gating configuration <<<<
4964 01:24:26.484770 Enter into DVFS_PRE_config >>>>>
4965 01:24:26.494717 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4966 01:24:26.498154 Exit from DVFS_PRE_config <<<<<
4967 01:24:26.501491 Enter into PICG configuration >>>>
4968 01:24:26.504881 Exit from PICG configuration <<<<
4969 01:24:26.508044 [RX_INPUT] configuration >>>>>
4970 01:24:26.511375 [RX_INPUT] configuration <<<<<
4971 01:24:26.514710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4972 01:24:26.521414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4973 01:24:26.528157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 01:24:26.531172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 01:24:26.537917 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 01:24:26.545056 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 01:24:26.547532 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4978 01:24:26.554228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4979 01:24:26.557729 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4980 01:24:26.560997 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4981 01:24:26.564532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4982 01:24:26.570711 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4983 01:24:26.574048 ===================================
4984 01:24:26.574132 LPDDR4 DRAM CONFIGURATION
4985 01:24:26.577420 ===================================
4986 01:24:26.580674 EX_ROW_EN[0] = 0x0
4987 01:24:26.584245 EX_ROW_EN[1] = 0x0
4988 01:24:26.584367 LP4Y_EN = 0x0
4989 01:24:26.587349 WORK_FSP = 0x0
4990 01:24:26.587473 WL = 0x3
4991 01:24:26.590743 RL = 0x3
4992 01:24:26.590848 BL = 0x2
4993 01:24:26.594195 RPST = 0x0
4994 01:24:26.594279 RD_PRE = 0x0
4995 01:24:26.597281 WR_PRE = 0x1
4996 01:24:26.597365 WR_PST = 0x0
4997 01:24:26.600523 DBI_WR = 0x0
4998 01:24:26.600607 DBI_RD = 0x0
4999 01:24:26.604407 OTF = 0x1
5000 01:24:26.607224 ===================================
5001 01:24:26.610380 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5002 01:24:26.613678 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5003 01:24:26.620335 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5004 01:24:26.624048 ===================================
5005 01:24:26.624133 LPDDR4 DRAM CONFIGURATION
5006 01:24:26.627159 ===================================
5007 01:24:26.630359 EX_ROW_EN[0] = 0x10
5008 01:24:26.633527 EX_ROW_EN[1] = 0x0
5009 01:24:26.633659 LP4Y_EN = 0x0
5010 01:24:26.637130 WORK_FSP = 0x0
5011 01:24:26.637253 WL = 0x3
5012 01:24:26.640177 RL = 0x3
5013 01:24:26.640302 BL = 0x2
5014 01:24:26.643437 RPST = 0x0
5015 01:24:26.643566 RD_PRE = 0x0
5016 01:24:26.646868 WR_PRE = 0x1
5017 01:24:26.646994 WR_PST = 0x0
5018 01:24:26.649972 DBI_WR = 0x0
5019 01:24:26.650095 DBI_RD = 0x0
5020 01:24:26.653351 OTF = 0x1
5021 01:24:26.656597 ===================================
5022 01:24:26.663420 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5023 01:24:26.666695 nWR fixed to 30
5024 01:24:26.673405 [ModeRegInit_LP4] CH0 RK0
5025 01:24:26.673528 [ModeRegInit_LP4] CH0 RK1
5026 01:24:26.673834 [ModeRegInit_LP4] CH1 RK0
5027 01:24:26.676763 [ModeRegInit_LP4] CH1 RK1
5028 01:24:26.676899 match AC timing 9
5029 01:24:26.683353 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5030 01:24:26.686781 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5031 01:24:26.690025 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5032 01:24:26.696430 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5033 01:24:26.699687 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5034 01:24:26.699772 ==
5035 01:24:26.703204 Dram Type= 6, Freq= 0, CH_0, rank 0
5036 01:24:26.706672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5037 01:24:26.706773 ==
5038 01:24:26.713036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5039 01:24:26.720042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5040 01:24:26.723252 [CA 0] Center 38 (7~69) winsize 63
5041 01:24:26.726341 [CA 1] Center 38 (8~69) winsize 62
5042 01:24:26.729716 [CA 2] Center 35 (5~66) winsize 62
5043 01:24:26.732962 [CA 3] Center 35 (5~66) winsize 62
5044 01:24:26.736660 [CA 4] Center 34 (4~65) winsize 62
5045 01:24:26.739760 [CA 5] Center 33 (3~64) winsize 62
5046 01:24:26.739844
5047 01:24:26.743484 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5048 01:24:26.743556
5049 01:24:26.746193 [CATrainingPosCal] consider 1 rank data
5050 01:24:26.749684 u2DelayCellTimex100 = 270/100 ps
5051 01:24:26.752697 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5052 01:24:26.756023 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5053 01:24:26.759803 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5054 01:24:26.762720 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5055 01:24:26.766014 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5056 01:24:26.770086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5057 01:24:26.772858
5058 01:24:26.776153 CA PerBit enable=1, Macro0, CA PI delay=33
5059 01:24:26.776237
5060 01:24:26.779144 [CBTSetCACLKResult] CA Dly = 33
5061 01:24:26.779229 CS Dly: 7 (0~38)
5062 01:24:26.779295 ==
5063 01:24:26.782485 Dram Type= 6, Freq= 0, CH_0, rank 1
5064 01:24:26.785842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 01:24:26.785927 ==
5066 01:24:26.792636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 01:24:26.799554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5068 01:24:26.802643 [CA 0] Center 38 (8~69) winsize 62
5069 01:24:26.805800 [CA 1] Center 38 (8~69) winsize 62
5070 01:24:26.809005 [CA 2] Center 35 (5~66) winsize 62
5071 01:24:26.812523 [CA 3] Center 35 (5~66) winsize 62
5072 01:24:26.815792 [CA 4] Center 34 (4~65) winsize 62
5073 01:24:26.819235 [CA 5] Center 34 (4~64) winsize 61
5074 01:24:26.819319
5075 01:24:26.822469 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5076 01:24:26.822553
5077 01:24:26.825964 [CATrainingPosCal] consider 2 rank data
5078 01:24:26.829173 u2DelayCellTimex100 = 270/100 ps
5079 01:24:26.832511 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 01:24:26.835798 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5081 01:24:26.839341 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5082 01:24:26.842811 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5083 01:24:26.845699 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5084 01:24:26.852409 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 01:24:26.852495
5086 01:24:26.855646 CA PerBit enable=1, Macro0, CA PI delay=34
5087 01:24:26.855731
5088 01:24:26.859222 [CBTSetCACLKResult] CA Dly = 34
5089 01:24:26.859307 CS Dly: 7 (0~39)
5090 01:24:26.859392
5091 01:24:26.862521 ----->DramcWriteLeveling(PI) begin...
5092 01:24:26.862609 ==
5093 01:24:26.865917 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 01:24:26.869231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 01:24:26.872487 ==
5096 01:24:26.872562 Write leveling (Byte 0): 32 => 32
5097 01:24:26.875687 Write leveling (Byte 1): 30 => 30
5098 01:24:26.878928 DramcWriteLeveling(PI) end<-----
5099 01:24:26.879014
5100 01:24:26.879099 ==
5101 01:24:26.882124 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 01:24:26.889470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 01:24:26.889556 ==
5104 01:24:26.892502 [Gating] SW mode calibration
5105 01:24:26.899051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5106 01:24:26.902308 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5107 01:24:26.908906 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 01:24:26.912172 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 01:24:26.915596 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 01:24:26.918915 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 01:24:26.925528 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 01:24:26.928771 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 01:24:26.932244 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5114 01:24:26.938758 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5115 01:24:26.942157 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5116 01:24:26.945679 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 01:24:26.952179 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 01:24:26.955461 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 01:24:26.958709 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 01:24:26.965466 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 01:24:26.969094 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5122 01:24:26.971974 0 15 28 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
5123 01:24:26.978795 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5124 01:24:26.982002 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 01:24:26.985360 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 01:24:26.992244 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 01:24:26.995112 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 01:24:26.998521 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 01:24:27.005543 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 01:24:27.008534 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5131 01:24:27.012562 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5132 01:24:27.018540 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 01:24:27.021804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 01:24:27.025524 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 01:24:27.031747 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 01:24:27.034983 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 01:24:27.038483 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 01:24:27.045094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 01:24:27.048263 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 01:24:27.052105 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 01:24:27.058521 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 01:24:27.061570 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 01:24:27.065188 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 01:24:27.071699 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 01:24:27.074894 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5146 01:24:27.078125 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 01:24:27.081519 Total UI for P1: 0, mck2ui 16
5148 01:24:27.084877 best dqsien dly found for B0: ( 1, 2, 24)
5149 01:24:27.088107 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 01:24:27.091526 Total UI for P1: 0, mck2ui 16
5151 01:24:27.094763 best dqsien dly found for B1: ( 1, 2, 28)
5152 01:24:27.098243 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5153 01:24:27.101624 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5154 01:24:27.104892
5155 01:24:27.108040 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5156 01:24:27.111809 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5157 01:24:27.114999 [Gating] SW calibration Done
5158 01:24:27.115083 ==
5159 01:24:27.118264 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 01:24:27.121325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 01:24:27.121410 ==
5162 01:24:27.121477 RX Vref Scan: 0
5163 01:24:27.124744
5164 01:24:27.124880 RX Vref 0 -> 0, step: 1
5165 01:24:27.124978
5166 01:24:27.128047 RX Delay -80 -> 252, step: 8
5167 01:24:27.131465 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5168 01:24:27.134807 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5169 01:24:27.141480 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5170 01:24:27.144626 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5171 01:24:27.148181 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5172 01:24:27.151514 iDelay=208, Bit 5, Center 103 (16 ~ 191) 176
5173 01:24:27.154839 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5174 01:24:27.161967 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5175 01:24:27.164933 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5176 01:24:27.168025 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5177 01:24:27.171283 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5178 01:24:27.174830 iDelay=208, Bit 11, Center 95 (16 ~ 175) 160
5179 01:24:27.178138 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5180 01:24:27.184713 iDelay=208, Bit 13, Center 99 (16 ~ 183) 168
5181 01:24:27.188662 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5182 01:24:27.191451 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5183 01:24:27.191535 ==
5184 01:24:27.194740 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 01:24:27.198137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 01:24:27.198222 ==
5187 01:24:27.201455 DQS Delay:
5188 01:24:27.201538 DQS0 = 0, DQS1 = 0
5189 01:24:27.204573 DQM Delay:
5190 01:24:27.204681 DQM0 = 108, DQM1 = 93
5191 01:24:27.204815 DQ Delay:
5192 01:24:27.208254 DQ0 =111, DQ1 =107, DQ2 =103, DQ3 =103
5193 01:24:27.214615 DQ4 =111, DQ5 =103, DQ6 =115, DQ7 =115
5194 01:24:27.218303 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =95
5195 01:24:27.221722 DQ12 =91, DQ13 =99, DQ14 =103, DQ15 =103
5196 01:24:27.221806
5197 01:24:27.221873
5198 01:24:27.221942 ==
5199 01:24:27.225141 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 01:24:27.228102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 01:24:27.228186 ==
5202 01:24:27.228253
5203 01:24:27.228313
5204 01:24:27.231384 TX Vref Scan disable
5205 01:24:27.231472 == TX Byte 0 ==
5206 01:24:27.238237 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5207 01:24:27.241238 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5208 01:24:27.241323 == TX Byte 1 ==
5209 01:24:27.247863 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5210 01:24:27.251307 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5211 01:24:27.251392 ==
5212 01:24:27.254680 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 01:24:27.258190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 01:24:27.258276 ==
5215 01:24:27.258361
5216 01:24:27.261369
5217 01:24:27.261454 TX Vref Scan disable
5218 01:24:27.264897 == TX Byte 0 ==
5219 01:24:27.267750 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5220 01:24:27.271016 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5221 01:24:27.274241 == TX Byte 1 ==
5222 01:24:27.277430 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5223 01:24:27.284411 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5224 01:24:27.284496
5225 01:24:27.284582 [DATLAT]
5226 01:24:27.284681 Freq=933, CH0 RK0
5227 01:24:27.284784
5228 01:24:27.287534 DATLAT Default: 0xd
5229 01:24:27.287620 0, 0xFFFF, sum = 0
5230 01:24:27.290866 1, 0xFFFF, sum = 0
5231 01:24:27.290953 2, 0xFFFF, sum = 0
5232 01:24:27.294070 3, 0xFFFF, sum = 0
5233 01:24:27.297626 4, 0xFFFF, sum = 0
5234 01:24:27.297713 5, 0xFFFF, sum = 0
5235 01:24:27.300700 6, 0xFFFF, sum = 0
5236 01:24:27.300822 7, 0xFFFF, sum = 0
5237 01:24:27.304446 8, 0xFFFF, sum = 0
5238 01:24:27.304532 9, 0xFFFF, sum = 0
5239 01:24:27.307619 10, 0x0, sum = 1
5240 01:24:27.307715 11, 0x0, sum = 2
5241 01:24:27.310667 12, 0x0, sum = 3
5242 01:24:27.310754 13, 0x0, sum = 4
5243 01:24:27.310840 best_step = 11
5244 01:24:27.310921
5245 01:24:27.314373 ==
5246 01:24:27.317490 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 01:24:27.320524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 01:24:27.320638 ==
5249 01:24:27.320742 RX Vref Scan: 1
5250 01:24:27.320868
5251 01:24:27.323880 RX Vref 0 -> 0, step: 1
5252 01:24:27.323982
5253 01:24:27.327529 RX Delay -53 -> 252, step: 4
5254 01:24:27.327604
5255 01:24:27.330679 Set Vref, RX VrefLevel [Byte0]: 59
5256 01:24:27.333858 [Byte1]: 50
5257 01:24:27.333943
5258 01:24:27.337323 Final RX Vref Byte 0 = 59 to rank0
5259 01:24:27.340788 Final RX Vref Byte 1 = 50 to rank0
5260 01:24:27.344052 Final RX Vref Byte 0 = 59 to rank1
5261 01:24:27.347367 Final RX Vref Byte 1 = 50 to rank1==
5262 01:24:27.350662 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 01:24:27.354392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 01:24:27.354476 ==
5265 01:24:27.357125 DQS Delay:
5266 01:24:27.357210 DQS0 = 0, DQS1 = 0
5267 01:24:27.361412 DQM Delay:
5268 01:24:27.361496 DQM0 = 107, DQM1 = 91
5269 01:24:27.363966 DQ Delay:
5270 01:24:27.367491 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5271 01:24:27.370674 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5272 01:24:27.373615 DQ8 =86, DQ9 =78, DQ10 =90, DQ11 =90
5273 01:24:27.377056 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =98
5274 01:24:27.377140
5275 01:24:27.377207
5276 01:24:27.383758 [DQSOSCAuto] RK0, (LSB)MR18= 0x221d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5277 01:24:27.386921 CH0 RK0: MR19=505, MR18=221D
5278 01:24:27.394142 CH0_RK0: MR19=0x505, MR18=0x221D, DQSOSC=411, MR23=63, INC=64, DEC=42
5279 01:24:27.394226
5280 01:24:27.397077 ----->DramcWriteLeveling(PI) begin...
5281 01:24:27.397163 ==
5282 01:24:27.400208 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 01:24:27.403490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 01:24:27.403596 ==
5285 01:24:27.406665 Write leveling (Byte 0): 32 => 32
5286 01:24:27.410045 Write leveling (Byte 1): 29 => 29
5287 01:24:27.413396 DramcWriteLeveling(PI) end<-----
5288 01:24:27.413480
5289 01:24:27.413551 ==
5290 01:24:27.417338 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 01:24:27.419921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 01:24:27.423261 ==
5293 01:24:27.423343 [Gating] SW mode calibration
5294 01:24:27.429992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5295 01:24:27.436657 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5296 01:24:27.439942 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 01:24:27.446442 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 01:24:27.449855 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 01:24:27.453163 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 01:24:27.460378 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 01:24:27.463139 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 01:24:27.466332 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 0)
5303 01:24:27.473314 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 1) (1 0)
5304 01:24:27.476647 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5305 01:24:27.479834 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 01:24:27.486727 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 01:24:27.489814 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 01:24:27.493586 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 01:24:27.499665 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 01:24:27.503324 0 15 24 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 0)
5311 01:24:27.506446 0 15 28 | B1->B0 | 3b3b 4241 | 0 1 | (0 0) (0 0)
5312 01:24:27.509663 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 01:24:27.516541 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 01:24:27.519778 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 01:24:27.523099 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 01:24:27.529749 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 01:24:27.532854 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 01:24:27.536239 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5319 01:24:27.543048 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5320 01:24:27.546312 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 01:24:27.549593 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 01:24:27.555903 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 01:24:27.559724 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 01:24:27.562791 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 01:24:27.569573 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 01:24:27.572963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 01:24:27.576213 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 01:24:27.583087 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 01:24:27.586362 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 01:24:27.590166 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 01:24:27.596138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 01:24:27.599513 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 01:24:27.603134 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 01:24:27.609673 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5335 01:24:27.612680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5336 01:24:27.616302 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 01:24:27.619687 Total UI for P1: 0, mck2ui 16
5338 01:24:27.623143 best dqsien dly found for B0: ( 1, 2, 26)
5339 01:24:27.625914 Total UI for P1: 0, mck2ui 16
5340 01:24:27.629418 best dqsien dly found for B1: ( 1, 2, 28)
5341 01:24:27.632879 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5342 01:24:27.636220 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5343 01:24:27.636302
5344 01:24:27.639524 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5345 01:24:27.646208 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 01:24:27.646291 [Gating] SW calibration Done
5347 01:24:27.646357 ==
5348 01:24:27.649283 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 01:24:27.656194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 01:24:27.656278 ==
5351 01:24:27.656345 RX Vref Scan: 0
5352 01:24:27.656407
5353 01:24:27.659414 RX Vref 0 -> 0, step: 1
5354 01:24:27.659498
5355 01:24:27.662552 RX Delay -80 -> 252, step: 8
5356 01:24:27.666116 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5357 01:24:27.669268 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5358 01:24:27.672743 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5359 01:24:27.675994 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5360 01:24:27.682608 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5361 01:24:27.685887 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5362 01:24:27.689254 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5363 01:24:27.692721 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5364 01:24:27.696113 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5365 01:24:27.699573 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5366 01:24:27.706804 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5367 01:24:27.709441 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5368 01:24:27.712683 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5369 01:24:27.716470 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5370 01:24:27.719484 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5371 01:24:27.722762 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5372 01:24:27.722846 ==
5373 01:24:27.726273 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 01:24:27.732617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 01:24:27.732731 ==
5376 01:24:27.732834 DQS Delay:
5377 01:24:27.736395 DQS0 = 0, DQS1 = 0
5378 01:24:27.736478 DQM Delay:
5379 01:24:27.739616 DQM0 = 104, DQM1 = 90
5380 01:24:27.739700 DQ Delay:
5381 01:24:27.742780 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5382 01:24:27.746327 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5383 01:24:27.749384 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5384 01:24:27.752597 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5385 01:24:27.752682
5386 01:24:27.752748
5387 01:24:27.752859 ==
5388 01:24:27.755968 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 01:24:27.759694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 01:24:27.759778 ==
5391 01:24:27.759845
5392 01:24:27.759908
5393 01:24:27.762979 TX Vref Scan disable
5394 01:24:27.765965 == TX Byte 0 ==
5395 01:24:27.769410 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5396 01:24:27.772515 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5397 01:24:27.776217 == TX Byte 1 ==
5398 01:24:27.779340 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5399 01:24:27.782677 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5400 01:24:27.782761 ==
5401 01:24:27.785902 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 01:24:27.792430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 01:24:27.792515 ==
5404 01:24:27.792582
5405 01:24:27.792644
5406 01:24:27.792704 TX Vref Scan disable
5407 01:24:27.796817 == TX Byte 0 ==
5408 01:24:27.799681 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5409 01:24:27.803218 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5410 01:24:27.806151 == TX Byte 1 ==
5411 01:24:27.809710 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5412 01:24:27.813023 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5413 01:24:27.816406
5414 01:24:27.816488 [DATLAT]
5415 01:24:27.816555 Freq=933, CH0 RK1
5416 01:24:27.816618
5417 01:24:27.819701 DATLAT Default: 0xb
5418 01:24:27.819785 0, 0xFFFF, sum = 0
5419 01:24:27.823140 1, 0xFFFF, sum = 0
5420 01:24:27.823224 2, 0xFFFF, sum = 0
5421 01:24:27.826547 3, 0xFFFF, sum = 0
5422 01:24:27.826632 4, 0xFFFF, sum = 0
5423 01:24:27.829580 5, 0xFFFF, sum = 0
5424 01:24:27.829665 6, 0xFFFF, sum = 0
5425 01:24:27.832976 7, 0xFFFF, sum = 0
5426 01:24:27.836438 8, 0xFFFF, sum = 0
5427 01:24:27.836565 9, 0xFFFF, sum = 0
5428 01:24:27.839820 10, 0x0, sum = 1
5429 01:24:27.839906 11, 0x0, sum = 2
5430 01:24:27.839975 12, 0x0, sum = 3
5431 01:24:27.843023 13, 0x0, sum = 4
5432 01:24:27.843108 best_step = 11
5433 01:24:27.843175
5434 01:24:27.843237 ==
5435 01:24:27.846450 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 01:24:27.852954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 01:24:27.853084 ==
5438 01:24:27.853197 RX Vref Scan: 0
5439 01:24:27.853313
5440 01:24:27.856359 RX Vref 0 -> 0, step: 1
5441 01:24:27.856482
5442 01:24:27.859654 RX Delay -53 -> 252, step: 4
5443 01:24:27.862979 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5444 01:24:27.869586 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5445 01:24:27.873764 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5446 01:24:27.876188 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5447 01:24:27.879369 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5448 01:24:27.882702 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5449 01:24:27.889474 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5450 01:24:27.892726 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5451 01:24:27.896611 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5452 01:24:27.899756 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5453 01:24:27.903054 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5454 01:24:27.906093 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5455 01:24:27.912684 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5456 01:24:27.916309 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5457 01:24:27.919599 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5458 01:24:27.922901 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5459 01:24:27.922986 ==
5460 01:24:27.926222 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 01:24:27.932771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 01:24:27.932855 ==
5463 01:24:27.932926 DQS Delay:
5464 01:24:27.932988 DQS0 = 0, DQS1 = 0
5465 01:24:27.936185 DQM Delay:
5466 01:24:27.936268 DQM0 = 104, DQM1 = 92
5467 01:24:27.939492 DQ Delay:
5468 01:24:27.942614 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5469 01:24:27.946187 DQ4 =104, DQ5 =100, DQ6 =112, DQ7 =110
5470 01:24:27.949346 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5471 01:24:27.952728 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =100
5472 01:24:27.952848
5473 01:24:27.952914
5474 01:24:27.959241 [DQSOSCAuto] RK1, (LSB)MR18= 0x2607, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5475 01:24:27.962909 CH0 RK1: MR19=505, MR18=2607
5476 01:24:27.969204 CH0_RK1: MR19=0x505, MR18=0x2607, DQSOSC=409, MR23=63, INC=64, DEC=43
5477 01:24:27.972806 [RxdqsGatingPostProcess] freq 933
5478 01:24:27.979561 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5479 01:24:27.979645 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 01:24:27.982570 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 01:24:27.985823 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 01:24:27.989465 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 01:24:27.992407 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 01:24:27.996326 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 01:24:27.999067 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 01:24:28.002392 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 01:24:28.006093 Pre-setting of DQS Precalculation
5488 01:24:28.012345 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5489 01:24:28.012429 ==
5490 01:24:28.015735 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 01:24:28.019055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 01:24:28.019139 ==
5493 01:24:28.022587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5494 01:24:28.028944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5495 01:24:28.032949 [CA 0] Center 37 (7~68) winsize 62
5496 01:24:28.036113 [CA 1] Center 37 (7~68) winsize 62
5497 01:24:28.039459 [CA 2] Center 35 (5~66) winsize 62
5498 01:24:28.043168 [CA 3] Center 34 (4~65) winsize 62
5499 01:24:28.046228 [CA 4] Center 35 (5~65) winsize 61
5500 01:24:28.049691 [CA 5] Center 34 (4~65) winsize 62
5501 01:24:28.049775
5502 01:24:28.052919 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5503 01:24:28.053003
5504 01:24:28.055951 [CATrainingPosCal] consider 1 rank data
5505 01:24:28.059370 u2DelayCellTimex100 = 270/100 ps
5506 01:24:28.062790 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5507 01:24:28.069287 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5508 01:24:28.072640 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5509 01:24:28.076594 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5510 01:24:28.079604 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5511 01:24:28.082672 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5512 01:24:28.082755
5513 01:24:28.086059 CA PerBit enable=1, Macro0, CA PI delay=34
5514 01:24:28.086143
5515 01:24:28.089728 [CBTSetCACLKResult] CA Dly = 34
5516 01:24:28.089812 CS Dly: 6 (0~37)
5517 01:24:28.092693 ==
5518 01:24:28.096132 Dram Type= 6, Freq= 0, CH_1, rank 1
5519 01:24:28.099207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 01:24:28.099291 ==
5521 01:24:28.102413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 01:24:28.109066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 01:24:28.113237 [CA 0] Center 38 (8~69) winsize 62
5524 01:24:28.116255 [CA 1] Center 38 (8~69) winsize 62
5525 01:24:28.119342 [CA 2] Center 36 (6~66) winsize 61
5526 01:24:28.123249 [CA 3] Center 35 (5~65) winsize 61
5527 01:24:28.126386 [CA 4] Center 35 (6~65) winsize 60
5528 01:24:28.129450 [CA 5] Center 35 (5~65) winsize 61
5529 01:24:28.129534
5530 01:24:28.132699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 01:24:28.132806
5532 01:24:28.136126 [CATrainingPosCal] consider 2 rank data
5533 01:24:28.139429 u2DelayCellTimex100 = 270/100 ps
5534 01:24:28.142983 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5535 01:24:28.149445 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5536 01:24:28.153039 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5537 01:24:28.156105 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5538 01:24:28.159356 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5539 01:24:28.162640 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5540 01:24:28.162725
5541 01:24:28.165869 CA PerBit enable=1, Macro0, CA PI delay=35
5542 01:24:28.165954
5543 01:24:28.169102 [CBTSetCACLKResult] CA Dly = 35
5544 01:24:28.169186 CS Dly: 7 (0~39)
5545 01:24:28.172529
5546 01:24:28.175764 ----->DramcWriteLeveling(PI) begin...
5547 01:24:28.175850 ==
5548 01:24:28.179210 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 01:24:28.183081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 01:24:28.183207 ==
5551 01:24:28.185728 Write leveling (Byte 0): 28 => 28
5552 01:24:28.188938 Write leveling (Byte 1): 28 => 28
5553 01:24:28.192662 DramcWriteLeveling(PI) end<-----
5554 01:24:28.192767
5555 01:24:28.192850 ==
5556 01:24:28.195940 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 01:24:28.199543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 01:24:28.199666 ==
5559 01:24:28.202611 [Gating] SW mode calibration
5560 01:24:28.209378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5561 01:24:28.215788 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5562 01:24:28.219501 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 01:24:28.222649 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 01:24:28.229009 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 01:24:28.232862 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 01:24:28.235698 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 01:24:28.239046 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 01:24:28.246067 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
5569 01:24:28.249076 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 01:24:28.252173 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 01:24:28.259366 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 01:24:28.262376 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 01:24:28.265395 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 01:24:28.272143 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 01:24:28.275299 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 01:24:28.278882 0 15 24 | B1->B0 | 2625 2a2a | 1 0 | (0 0) (0 0)
5577 01:24:28.285497 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5578 01:24:28.288976 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 01:24:28.291963 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 01:24:28.298493 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 01:24:28.301812 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 01:24:28.305591 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 01:24:28.311964 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 01:24:28.315690 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5585 01:24:28.318461 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 01:24:28.325344 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 01:24:28.328627 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 01:24:28.331866 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 01:24:28.338602 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 01:24:28.341932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 01:24:28.345082 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 01:24:28.352106 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 01:24:28.355355 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 01:24:28.358843 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 01:24:28.365470 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 01:24:28.368640 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 01:24:28.371961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 01:24:28.375555 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 01:24:28.381860 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 01:24:28.385058 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5601 01:24:28.388653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 01:24:28.391744 Total UI for P1: 0, mck2ui 16
5603 01:24:28.395247 best dqsien dly found for B0: ( 1, 2, 24)
5604 01:24:28.398723 Total UI for P1: 0, mck2ui 16
5605 01:24:28.401790 best dqsien dly found for B1: ( 1, 2, 24)
5606 01:24:28.405201 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5607 01:24:28.408594 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5608 01:24:28.412384
5609 01:24:28.415075 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 01:24:28.418566 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5611 01:24:28.422139 [Gating] SW calibration Done
5612 01:24:28.422223 ==
5613 01:24:28.424964 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 01:24:28.428359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 01:24:28.428444 ==
5616 01:24:28.428510 RX Vref Scan: 0
5617 01:24:28.428572
5618 01:24:28.431970 RX Vref 0 -> 0, step: 1
5619 01:24:28.432055
5620 01:24:28.435329 RX Delay -80 -> 252, step: 8
5621 01:24:28.438758 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5622 01:24:28.441807 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5623 01:24:28.445318 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5624 01:24:28.451980 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5625 01:24:28.455513 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5626 01:24:28.458368 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5627 01:24:28.461921 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5628 01:24:28.465083 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5629 01:24:28.471826 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5630 01:24:28.475165 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5631 01:24:28.478311 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5632 01:24:28.481786 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5633 01:24:28.485204 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5634 01:24:28.488219 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5635 01:24:28.494870 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5636 01:24:28.498096 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5637 01:24:28.498180 ==
5638 01:24:28.501546 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 01:24:28.504918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 01:24:28.505003 ==
5641 01:24:28.508416 DQS Delay:
5642 01:24:28.508505 DQS0 = 0, DQS1 = 0
5643 01:24:28.508595 DQM Delay:
5644 01:24:28.511682 DQM0 = 101, DQM1 = 95
5645 01:24:28.511769 DQ Delay:
5646 01:24:28.514881 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5647 01:24:28.518219 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5648 01:24:28.521355 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5649 01:24:28.524670 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5650 01:24:28.524779
5651 01:24:28.528225
5652 01:24:28.528311 ==
5653 01:24:28.531448 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 01:24:28.534792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 01:24:28.534879 ==
5656 01:24:28.534965
5657 01:24:28.535047
5658 01:24:28.537923 TX Vref Scan disable
5659 01:24:28.538011 == TX Byte 0 ==
5660 01:24:28.544668 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5661 01:24:28.548236 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5662 01:24:28.548322 == TX Byte 1 ==
5663 01:24:28.551303 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5664 01:24:28.558257 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5665 01:24:28.558343 ==
5666 01:24:28.561303 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 01:24:28.565129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 01:24:28.565213 ==
5669 01:24:28.565279
5670 01:24:28.565341
5671 01:24:28.568269 TX Vref Scan disable
5672 01:24:28.571404 == TX Byte 0 ==
5673 01:24:28.574589 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5674 01:24:28.578264 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5675 01:24:28.581273 == TX Byte 1 ==
5676 01:24:28.584936 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5677 01:24:28.587820 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5678 01:24:28.587903
5679 01:24:28.587969 [DATLAT]
5680 01:24:28.591380 Freq=933, CH1 RK0
5681 01:24:28.591465
5682 01:24:28.594476 DATLAT Default: 0xd
5683 01:24:28.594559 0, 0xFFFF, sum = 0
5684 01:24:28.598034 1, 0xFFFF, sum = 0
5685 01:24:28.598120 2, 0xFFFF, sum = 0
5686 01:24:28.601065 3, 0xFFFF, sum = 0
5687 01:24:28.601168 4, 0xFFFF, sum = 0
5688 01:24:28.604348 5, 0xFFFF, sum = 0
5689 01:24:28.604434 6, 0xFFFF, sum = 0
5690 01:24:28.607783 7, 0xFFFF, sum = 0
5691 01:24:28.607869 8, 0xFFFF, sum = 0
5692 01:24:28.611220 9, 0xFFFF, sum = 0
5693 01:24:28.611306 10, 0x0, sum = 1
5694 01:24:28.614471 11, 0x0, sum = 2
5695 01:24:28.614556 12, 0x0, sum = 3
5696 01:24:28.618196 13, 0x0, sum = 4
5697 01:24:28.618282 best_step = 11
5698 01:24:28.618350
5699 01:24:28.618413 ==
5700 01:24:28.621072 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 01:24:28.624373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 01:24:28.628118 ==
5703 01:24:28.628202 RX Vref Scan: 1
5704 01:24:28.628270
5705 01:24:28.631029 RX Vref 0 -> 0, step: 1
5706 01:24:28.631113
5707 01:24:28.631180 RX Delay -53 -> 252, step: 4
5708 01:24:28.634519
5709 01:24:28.634603 Set Vref, RX VrefLevel [Byte0]: 51
5710 01:24:28.637859 [Byte1]: 53
5711 01:24:28.642697
5712 01:24:28.642781 Final RX Vref Byte 0 = 51 to rank0
5713 01:24:28.646304 Final RX Vref Byte 1 = 53 to rank0
5714 01:24:28.649504 Final RX Vref Byte 0 = 51 to rank1
5715 01:24:28.652763 Final RX Vref Byte 1 = 53 to rank1==
5716 01:24:28.656333 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 01:24:28.662544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 01:24:28.662664 ==
5719 01:24:28.662780 DQS Delay:
5720 01:24:28.665720 DQS0 = 0, DQS1 = 0
5721 01:24:28.665847 DQM Delay:
5722 01:24:28.665960 DQM0 = 104, DQM1 = 97
5723 01:24:28.669269 DQ Delay:
5724 01:24:28.672472 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5725 01:24:28.675893 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5726 01:24:28.679104 DQ8 =88, DQ9 =84, DQ10 =102, DQ11 =92
5727 01:24:28.682381 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5728 01:24:28.682504
5729 01:24:28.682619
5730 01:24:28.689058 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5731 01:24:28.692553 CH1 RK0: MR19=505, MR18=1A32
5732 01:24:28.699047 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5733 01:24:28.699172
5734 01:24:28.702269 ----->DramcWriteLeveling(PI) begin...
5735 01:24:28.702395 ==
5736 01:24:28.705408 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 01:24:28.708875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 01:24:28.712202 ==
5739 01:24:28.712330 Write leveling (Byte 0): 29 => 29
5740 01:24:28.715293 Write leveling (Byte 1): 26 => 26
5741 01:24:28.718806 DramcWriteLeveling(PI) end<-----
5742 01:24:28.718928
5743 01:24:28.719046 ==
5744 01:24:28.721923 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 01:24:28.728437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 01:24:28.728564 ==
5747 01:24:28.732495 [Gating] SW mode calibration
5748 01:24:28.738513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5749 01:24:28.742318 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5750 01:24:28.748583 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 01:24:28.751705 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 01:24:28.755085 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 01:24:28.761834 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 01:24:28.765463 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 01:24:28.768639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 01:24:28.775320 0 14 24 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (1 1)
5757 01:24:28.778406 0 14 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (0 0)
5758 01:24:28.782252 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5759 01:24:28.785211 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 01:24:28.792277 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 01:24:28.795390 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 01:24:28.798928 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 01:24:28.805391 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 01:24:28.808728 0 15 24 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
5765 01:24:28.812138 0 15 28 | B1->B0 | 4040 3737 | 0 0 | (0 0) (0 0)
5766 01:24:28.818872 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5767 01:24:28.821855 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 01:24:28.825315 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 01:24:28.832215 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 01:24:28.835497 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 01:24:28.838527 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 01:24:28.845219 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5773 01:24:28.848416 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5774 01:24:28.851722 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 01:24:28.858216 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 01:24:28.861594 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 01:24:28.865327 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 01:24:28.871806 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 01:24:28.874938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 01:24:28.878564 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 01:24:28.884962 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 01:24:28.888300 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 01:24:28.891887 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 01:24:28.894934 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 01:24:28.901566 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 01:24:28.905460 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 01:24:28.908056 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5788 01:24:28.914677 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5789 01:24:28.918267 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5790 01:24:28.921386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 01:24:28.924691 Total UI for P1: 0, mck2ui 16
5792 01:24:28.928116 best dqsien dly found for B0: ( 1, 2, 24)
5793 01:24:28.931318 Total UI for P1: 0, mck2ui 16
5794 01:24:28.935006 best dqsien dly found for B1: ( 1, 2, 26)
5795 01:24:28.938190 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5796 01:24:28.941594 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5797 01:24:28.944939
5798 01:24:28.948058 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5799 01:24:28.951344 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5800 01:24:28.954484 [Gating] SW calibration Done
5801 01:24:28.954568 ==
5802 01:24:28.957898 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 01:24:28.961482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 01:24:28.961566 ==
5805 01:24:28.961634 RX Vref Scan: 0
5806 01:24:28.964511
5807 01:24:28.964594 RX Vref 0 -> 0, step: 1
5808 01:24:28.964661
5809 01:24:28.967973 RX Delay -80 -> 252, step: 8
5810 01:24:28.971132 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5811 01:24:28.974404 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5812 01:24:28.981205 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5813 01:24:28.984242 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5814 01:24:28.987638 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5815 01:24:28.991046 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5816 01:24:28.994479 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5817 01:24:29.001314 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5818 01:24:29.004496 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5819 01:24:29.007536 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5820 01:24:29.011020 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5821 01:24:29.014417 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5822 01:24:29.018016 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5823 01:24:29.024398 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5824 01:24:29.027465 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5825 01:24:29.031005 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5826 01:24:29.031088 ==
5827 01:24:29.034347 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 01:24:29.037448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 01:24:29.037533 ==
5830 01:24:29.041077 DQS Delay:
5831 01:24:29.041162 DQS0 = 0, DQS1 = 0
5832 01:24:29.044010 DQM Delay:
5833 01:24:29.044094 DQM0 = 103, DQM1 = 95
5834 01:24:29.044161 DQ Delay:
5835 01:24:29.047378 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5836 01:24:29.054633 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =103
5837 01:24:29.054718 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5838 01:24:29.060874 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5839 01:24:29.060960
5840 01:24:29.061027
5841 01:24:29.061089 ==
5842 01:24:29.064029 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 01:24:29.067578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 01:24:29.067663 ==
5845 01:24:29.067731
5846 01:24:29.067794
5847 01:24:29.070705 TX Vref Scan disable
5848 01:24:29.070807 == TX Byte 0 ==
5849 01:24:29.077872 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5850 01:24:29.081535 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5851 01:24:29.081620 == TX Byte 1 ==
5852 01:24:29.087372 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5853 01:24:29.091041 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5854 01:24:29.091126 ==
5855 01:24:29.094084 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 01:24:29.097484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 01:24:29.097569 ==
5858 01:24:29.097636
5859 01:24:29.101079
5860 01:24:29.101210 TX Vref Scan disable
5861 01:24:29.103876 == TX Byte 0 ==
5862 01:24:29.107508 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5863 01:24:29.110599 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5864 01:24:29.113837 == TX Byte 1 ==
5865 01:24:29.117192 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5866 01:24:29.120851 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5867 01:24:29.123988
5868 01:24:29.124108 [DATLAT]
5869 01:24:29.124223 Freq=933, CH1 RK1
5870 01:24:29.124336
5871 01:24:29.127313 DATLAT Default: 0xb
5872 01:24:29.127436 0, 0xFFFF, sum = 0
5873 01:24:29.130894 1, 0xFFFF, sum = 0
5874 01:24:29.131019 2, 0xFFFF, sum = 0
5875 01:24:29.133883 3, 0xFFFF, sum = 0
5876 01:24:29.134007 4, 0xFFFF, sum = 0
5877 01:24:29.137266 5, 0xFFFF, sum = 0
5878 01:24:29.137393 6, 0xFFFF, sum = 0
5879 01:24:29.140732 7, 0xFFFF, sum = 0
5880 01:24:29.143809 8, 0xFFFF, sum = 0
5881 01:24:29.143917 9, 0xFFFF, sum = 0
5882 01:24:29.144015 10, 0x0, sum = 1
5883 01:24:29.147005 11, 0x0, sum = 2
5884 01:24:29.147102 12, 0x0, sum = 3
5885 01:24:29.150788 13, 0x0, sum = 4
5886 01:24:29.150885 best_step = 11
5887 01:24:29.150973
5888 01:24:29.151060 ==
5889 01:24:29.154307 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 01:24:29.160668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 01:24:29.160777 ==
5892 01:24:29.160861 RX Vref Scan: 0
5893 01:24:29.160925
5894 01:24:29.163820 RX Vref 0 -> 0, step: 1
5895 01:24:29.163904
5896 01:24:29.167578 RX Delay -53 -> 252, step: 4
5897 01:24:29.170972 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5898 01:24:29.177121 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5899 01:24:29.180549 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5900 01:24:29.184113 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5901 01:24:29.187407 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5902 01:24:29.190522 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5903 01:24:29.194006 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5904 01:24:29.200620 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5905 01:24:29.203714 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5906 01:24:29.207127 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5907 01:24:29.210658 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5908 01:24:29.213908 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5909 01:24:29.220581 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5910 01:24:29.224085 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5911 01:24:29.227756 iDelay=199, Bit 14, Center 108 (23 ~ 194) 172
5912 01:24:29.231083 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5913 01:24:29.231169 ==
5914 01:24:29.233742 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 01:24:29.237039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 01:24:29.240660 ==
5917 01:24:29.240746 DQS Delay:
5918 01:24:29.240820 DQS0 = 0, DQS1 = 0
5919 01:24:29.243744 DQM Delay:
5920 01:24:29.243830 DQM0 = 105, DQM1 = 98
5921 01:24:29.247166 DQ Delay:
5922 01:24:29.250391 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =104
5923 01:24:29.253614 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =104
5924 01:24:29.256906 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5925 01:24:29.260236 DQ12 =108, DQ13 =102, DQ14 =108, DQ15 =108
5926 01:24:29.260363
5927 01:24:29.260484
5928 01:24:29.267047 [DQSOSCAuto] RK1, (LSB)MR18= 0x2501, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5929 01:24:29.270383 CH1 RK1: MR19=505, MR18=2501
5930 01:24:29.276578 CH1_RK1: MR19=0x505, MR18=0x2501, DQSOSC=410, MR23=63, INC=64, DEC=42
5931 01:24:29.280193 [RxdqsGatingPostProcess] freq 933
5932 01:24:29.286982 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 01:24:29.287109 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 01:24:29.290189 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 01:24:29.293335 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 01:24:29.296689 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 01:24:29.300012 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 01:24:29.303338 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 01:24:29.307016 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 01:24:29.309826 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 01:24:29.313314 Pre-setting of DQS Precalculation
5942 01:24:29.320355 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 01:24:29.326480 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 01:24:29.333124 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 01:24:29.333208
5946 01:24:29.333275
5947 01:24:29.336514 [Calibration Summary] 1866 Mbps
5948 01:24:29.336598 CH 0, Rank 0
5949 01:24:29.339643 SW Impedance : PASS
5950 01:24:29.343460 DUTY Scan : NO K
5951 01:24:29.343545 ZQ Calibration : PASS
5952 01:24:29.346706 Jitter Meter : NO K
5953 01:24:29.346791 CBT Training : PASS
5954 01:24:29.349818 Write leveling : PASS
5955 01:24:29.353248 RX DQS gating : PASS
5956 01:24:29.353332 RX DQ/DQS(RDDQC) : PASS
5957 01:24:29.356678 TX DQ/DQS : PASS
5958 01:24:29.360163 RX DATLAT : PASS
5959 01:24:29.360273 RX DQ/DQS(Engine): PASS
5960 01:24:29.362871 TX OE : NO K
5961 01:24:29.362956 All Pass.
5962 01:24:29.363022
5963 01:24:29.366256 CH 0, Rank 1
5964 01:24:29.366340 SW Impedance : PASS
5965 01:24:29.369496 DUTY Scan : NO K
5966 01:24:29.372955 ZQ Calibration : PASS
5967 01:24:29.373057 Jitter Meter : NO K
5968 01:24:29.376176 CBT Training : PASS
5969 01:24:29.379585 Write leveling : PASS
5970 01:24:29.379686 RX DQS gating : PASS
5971 01:24:29.382928 RX DQ/DQS(RDDQC) : PASS
5972 01:24:29.386304 TX DQ/DQS : PASS
5973 01:24:29.386388 RX DATLAT : PASS
5974 01:24:29.389370 RX DQ/DQS(Engine): PASS
5975 01:24:29.392707 TX OE : NO K
5976 01:24:29.392835 All Pass.
5977 01:24:29.392901
5978 01:24:29.392961 CH 1, Rank 0
5979 01:24:29.396053 SW Impedance : PASS
5980 01:24:29.399503 DUTY Scan : NO K
5981 01:24:29.399588 ZQ Calibration : PASS
5982 01:24:29.402996 Jitter Meter : NO K
5983 01:24:29.406111 CBT Training : PASS
5984 01:24:29.406195 Write leveling : PASS
5985 01:24:29.409463 RX DQS gating : PASS
5986 01:24:29.409573 RX DQ/DQS(RDDQC) : PASS
5987 01:24:29.412632 TX DQ/DQS : PASS
5988 01:24:29.416000 RX DATLAT : PASS
5989 01:24:29.416084 RX DQ/DQS(Engine): PASS
5990 01:24:29.419574 TX OE : NO K
5991 01:24:29.419659 All Pass.
5992 01:24:29.419726
5993 01:24:29.422760 CH 1, Rank 1
5994 01:24:29.422844 SW Impedance : PASS
5995 01:24:29.425960 DUTY Scan : NO K
5996 01:24:29.429274 ZQ Calibration : PASS
5997 01:24:29.429358 Jitter Meter : NO K
5998 01:24:29.432681 CBT Training : PASS
5999 01:24:29.436110 Write leveling : PASS
6000 01:24:29.436194 RX DQS gating : PASS
6001 01:24:29.439464 RX DQ/DQS(RDDQC) : PASS
6002 01:24:29.442790 TX DQ/DQS : PASS
6003 01:24:29.442875 RX DATLAT : PASS
6004 01:24:29.445799 RX DQ/DQS(Engine): PASS
6005 01:24:29.449207 TX OE : NO K
6006 01:24:29.449292 All Pass.
6007 01:24:29.449359
6008 01:24:29.449421 DramC Write-DBI off
6009 01:24:29.452965 PER_BANK_REFRESH: Hybrid Mode
6010 01:24:29.456601 TX_TRACKING: ON
6011 01:24:29.462488 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 01:24:29.466117 [FAST_K] Save calibration result to emmc
6013 01:24:29.473110 dramc_set_vcore_voltage set vcore to 650000
6014 01:24:29.473194 Read voltage for 400, 6
6015 01:24:29.475946 Vio18 = 0
6016 01:24:29.476029 Vcore = 650000
6017 01:24:29.476096 Vdram = 0
6018 01:24:29.476158 Vddq = 0
6019 01:24:29.479313 Vmddr = 0
6020 01:24:29.482706 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 01:24:29.489109 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 01:24:29.492577 MEM_TYPE=3, freq_sel=20
6023 01:24:29.492679 sv_algorithm_assistance_LP4_800
6024 01:24:29.499892 ============ PULL DRAM RESETB DOWN ============
6025 01:24:29.502742 ========== PULL DRAM RESETB DOWN end =========
6026 01:24:29.505752 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 01:24:29.509086 ===================================
6028 01:24:29.512396 LPDDR4 DRAM CONFIGURATION
6029 01:24:29.515741 ===================================
6030 01:24:29.519057 EX_ROW_EN[0] = 0x0
6031 01:24:29.519142 EX_ROW_EN[1] = 0x0
6032 01:24:29.522460 LP4Y_EN = 0x0
6033 01:24:29.522544 WORK_FSP = 0x0
6034 01:24:29.526050 WL = 0x2
6035 01:24:29.526134 RL = 0x2
6036 01:24:29.529116 BL = 0x2
6037 01:24:29.529201 RPST = 0x0
6038 01:24:29.533216 RD_PRE = 0x0
6039 01:24:29.533300 WR_PRE = 0x1
6040 01:24:29.536119 WR_PST = 0x0
6041 01:24:29.536204 DBI_WR = 0x0
6042 01:24:29.539376 DBI_RD = 0x0
6043 01:24:29.539460 OTF = 0x1
6044 01:24:29.542734 ===================================
6045 01:24:29.545742 ===================================
6046 01:24:29.549108 ANA top config
6047 01:24:29.552410 ===================================
6048 01:24:29.556370 DLL_ASYNC_EN = 0
6049 01:24:29.556455 ALL_SLAVE_EN = 1
6050 01:24:29.559213 NEW_RANK_MODE = 1
6051 01:24:29.562244 DLL_IDLE_MODE = 1
6052 01:24:29.565595 LP45_APHY_COMB_EN = 1
6053 01:24:29.565681 TX_ODT_DIS = 1
6054 01:24:29.569200 NEW_8X_MODE = 1
6055 01:24:29.572189 ===================================
6056 01:24:29.575915 ===================================
6057 01:24:29.578980 data_rate = 800
6058 01:24:29.582314 CKR = 1
6059 01:24:29.585669 DQ_P2S_RATIO = 4
6060 01:24:29.588743 ===================================
6061 01:24:29.592539 CA_P2S_RATIO = 4
6062 01:24:29.592622 DQ_CA_OPEN = 0
6063 01:24:29.595422 DQ_SEMI_OPEN = 1
6064 01:24:29.598703 CA_SEMI_OPEN = 1
6065 01:24:29.602231 CA_FULL_RATE = 0
6066 01:24:29.605306 DQ_CKDIV4_EN = 0
6067 01:24:29.608927 CA_CKDIV4_EN = 1
6068 01:24:29.609036 CA_PREDIV_EN = 0
6069 01:24:29.612117 PH8_DLY = 0
6070 01:24:29.615630 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 01:24:29.618845 DQ_AAMCK_DIV = 0
6072 01:24:29.622281 CA_AAMCK_DIV = 0
6073 01:24:29.625400 CA_ADMCK_DIV = 4
6074 01:24:29.625483 DQ_TRACK_CA_EN = 0
6075 01:24:29.628745 CA_PICK = 800
6076 01:24:29.632166 CA_MCKIO = 400
6077 01:24:29.635315 MCKIO_SEMI = 400
6078 01:24:29.638954 PLL_FREQ = 3016
6079 01:24:29.642134 DQ_UI_PI_RATIO = 32
6080 01:24:29.645725 CA_UI_PI_RATIO = 32
6081 01:24:29.649028 ===================================
6082 01:24:29.652028 ===================================
6083 01:24:29.652112 memory_type:LPDDR4
6084 01:24:29.655660 GP_NUM : 10
6085 01:24:29.658590 SRAM_EN : 1
6086 01:24:29.658675 MD32_EN : 0
6087 01:24:29.662091 ===================================
6088 01:24:29.665497 [ANA_INIT] >>>>>>>>>>>>>>
6089 01:24:29.668487 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 01:24:29.671980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 01:24:29.675348 ===================================
6092 01:24:29.678600 data_rate = 800,PCW = 0X7400
6093 01:24:29.681964 ===================================
6094 01:24:29.685355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 01:24:29.688532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 01:24:29.702253 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 01:24:29.705184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 01:24:29.708593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 01:24:29.711893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 01:24:29.715469 [ANA_INIT] flow start
6101 01:24:29.715554 [ANA_INIT] PLL >>>>>>>>
6102 01:24:29.718457 [ANA_INIT] PLL <<<<<<<<
6103 01:24:29.721829 [ANA_INIT] MIDPI >>>>>>>>
6104 01:24:29.725165 [ANA_INIT] MIDPI <<<<<<<<
6105 01:24:29.725250 [ANA_INIT] DLL >>>>>>>>
6106 01:24:29.728705 [ANA_INIT] flow end
6107 01:24:29.731684 ============ LP4 DIFF to SE enter ============
6108 01:24:29.734983 ============ LP4 DIFF to SE exit ============
6109 01:24:29.738408 [ANA_INIT] <<<<<<<<<<<<<
6110 01:24:29.741801 [Flow] Enable top DCM control >>>>>
6111 01:24:29.745032 [Flow] Enable top DCM control <<<<<
6112 01:24:29.748532 Enable DLL master slave shuffle
6113 01:24:29.755030 ==============================================================
6114 01:24:29.755114 Gating Mode config
6115 01:24:29.761647 ==============================================================
6116 01:24:29.761731 Config description:
6117 01:24:29.772277 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 01:24:29.778539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 01:24:29.785021 SELPH_MODE 0: By rank 1: By Phase
6120 01:24:29.788369 ==============================================================
6121 01:24:29.792053 GAT_TRACK_EN = 0
6122 01:24:29.795195 RX_GATING_MODE = 2
6123 01:24:29.798579 RX_GATING_TRACK_MODE = 2
6124 01:24:29.801848 SELPH_MODE = 1
6125 01:24:29.805093 PICG_EARLY_EN = 1
6126 01:24:29.808735 VALID_LAT_VALUE = 1
6127 01:24:29.811876 ==============================================================
6128 01:24:29.815187 Enter into Gating configuration >>>>
6129 01:24:29.818899 Exit from Gating configuration <<<<
6130 01:24:29.822154 Enter into DVFS_PRE_config >>>>>
6131 01:24:29.835144 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 01:24:29.835235 Exit from DVFS_PRE_config <<<<<
6133 01:24:29.838506 Enter into PICG configuration >>>>
6134 01:24:29.841814 Exit from PICG configuration <<<<
6135 01:24:29.845070 [RX_INPUT] configuration >>>>>
6136 01:24:29.848635 [RX_INPUT] configuration <<<<<
6137 01:24:29.855099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 01:24:29.858316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 01:24:29.865013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 01:24:29.871832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 01:24:29.878151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 01:24:29.884890 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 01:24:29.888217 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 01:24:29.891482 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 01:24:29.894987 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 01:24:29.901555 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 01:24:29.905282 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 01:24:29.908689 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 01:24:29.911819 ===================================
6150 01:24:29.915068 LPDDR4 DRAM CONFIGURATION
6151 01:24:29.918505 ===================================
6152 01:24:29.918588 EX_ROW_EN[0] = 0x0
6153 01:24:29.921780 EX_ROW_EN[1] = 0x0
6154 01:24:29.925153 LP4Y_EN = 0x0
6155 01:24:29.925237 WORK_FSP = 0x0
6156 01:24:29.928265 WL = 0x2
6157 01:24:29.928349 RL = 0x2
6158 01:24:29.931810 BL = 0x2
6159 01:24:29.931894 RPST = 0x0
6160 01:24:29.934862 RD_PRE = 0x0
6161 01:24:29.934947 WR_PRE = 0x1
6162 01:24:29.938380 WR_PST = 0x0
6163 01:24:29.938464 DBI_WR = 0x0
6164 01:24:29.941786 DBI_RD = 0x0
6165 01:24:29.941871 OTF = 0x1
6166 01:24:29.944746 ===================================
6167 01:24:29.948134 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 01:24:29.954890 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 01:24:29.958370 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 01:24:29.961468 ===================================
6171 01:24:29.964951 LPDDR4 DRAM CONFIGURATION
6172 01:24:29.968497 ===================================
6173 01:24:29.968582 EX_ROW_EN[0] = 0x10
6174 01:24:29.971322 EX_ROW_EN[1] = 0x0
6175 01:24:29.971423 LP4Y_EN = 0x0
6176 01:24:29.974758 WORK_FSP = 0x0
6177 01:24:29.977916 WL = 0x2
6178 01:24:29.978001 RL = 0x2
6179 01:24:29.981287 BL = 0x2
6180 01:24:29.981371 RPST = 0x0
6181 01:24:29.984621 RD_PRE = 0x0
6182 01:24:29.984705 WR_PRE = 0x1
6183 01:24:29.988288 WR_PST = 0x0
6184 01:24:29.988372 DBI_WR = 0x0
6185 01:24:29.991545 DBI_RD = 0x0
6186 01:24:29.991630 OTF = 0x1
6187 01:24:29.994870 ===================================
6188 01:24:30.001583 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 01:24:30.005673 nWR fixed to 30
6190 01:24:30.008616 [ModeRegInit_LP4] CH0 RK0
6191 01:24:30.008705 [ModeRegInit_LP4] CH0 RK1
6192 01:24:30.012376 [ModeRegInit_LP4] CH1 RK0
6193 01:24:30.015280 [ModeRegInit_LP4] CH1 RK1
6194 01:24:30.015364 match AC timing 19
6195 01:24:30.022323 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 01:24:30.025289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 01:24:30.029014 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 01:24:30.035530 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 01:24:30.038660 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 01:24:30.038744 ==
6201 01:24:30.041946 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 01:24:30.045533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 01:24:30.045619 ==
6204 01:24:30.051917 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 01:24:30.058711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6206 01:24:30.061891 [CA 0] Center 36 (8~64) winsize 57
6207 01:24:30.065188 [CA 1] Center 36 (8~64) winsize 57
6208 01:24:30.068773 [CA 2] Center 36 (8~64) winsize 57
6209 01:24:30.068871 [CA 3] Center 36 (8~64) winsize 57
6210 01:24:30.071935 [CA 4] Center 36 (8~64) winsize 57
6211 01:24:30.075305 [CA 5] Center 36 (8~64) winsize 57
6212 01:24:30.075389
6213 01:24:30.078546 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6214 01:24:30.082171
6215 01:24:30.085048 [CATrainingPosCal] consider 1 rank data
6216 01:24:30.085165 u2DelayCellTimex100 = 270/100 ps
6217 01:24:30.091808 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 01:24:30.095280 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 01:24:30.098975 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 01:24:30.102275 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 01:24:30.105473 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 01:24:30.108653 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 01:24:30.108739
6224 01:24:30.111868 CA PerBit enable=1, Macro0, CA PI delay=36
6225 01:24:30.111953
6226 01:24:30.115186 [CBTSetCACLKResult] CA Dly = 36
6227 01:24:30.118808 CS Dly: 1 (0~32)
6228 01:24:30.118896 ==
6229 01:24:30.122078 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 01:24:30.125393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 01:24:30.125502 ==
6232 01:24:30.128726 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 01:24:30.135388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6234 01:24:30.139032 [CA 0] Center 36 (8~64) winsize 57
6235 01:24:30.141808 [CA 1] Center 36 (8~64) winsize 57
6236 01:24:30.145242 [CA 2] Center 36 (8~64) winsize 57
6237 01:24:30.148956 [CA 3] Center 36 (8~64) winsize 57
6238 01:24:30.151832 [CA 4] Center 36 (8~64) winsize 57
6239 01:24:30.155870 [CA 5] Center 36 (8~64) winsize 57
6240 01:24:30.155954
6241 01:24:30.158568 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6242 01:24:30.158653
6243 01:24:30.162348 [CATrainingPosCal] consider 2 rank data
6244 01:24:30.165337 u2DelayCellTimex100 = 270/100 ps
6245 01:24:30.168714 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 01:24:30.171911 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 01:24:30.175159 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 01:24:30.178516 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 01:24:30.182190 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 01:24:30.188732 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 01:24:30.188839
6252 01:24:30.192078 CA PerBit enable=1, Macro0, CA PI delay=36
6253 01:24:30.192177
6254 01:24:30.195370 [CBTSetCACLKResult] CA Dly = 36
6255 01:24:30.195455 CS Dly: 1 (0~32)
6256 01:24:30.195525
6257 01:24:30.198650 ----->DramcWriteLeveling(PI) begin...
6258 01:24:30.198735 ==
6259 01:24:30.202190 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 01:24:30.205346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 01:24:30.208656 ==
6262 01:24:30.208739 Write leveling (Byte 0): 40 => 8
6263 01:24:30.212231 Write leveling (Byte 1): 32 => 0
6264 01:24:30.215282 DramcWriteLeveling(PI) end<-----
6265 01:24:30.215366
6266 01:24:30.215433 ==
6267 01:24:30.219012 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 01:24:30.225308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 01:24:30.225393 ==
6270 01:24:30.225463 [Gating] SW mode calibration
6271 01:24:30.235260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 01:24:30.238568 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 01:24:30.241888 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 01:24:30.248500 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 01:24:30.251859 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 01:24:30.255305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 01:24:30.261722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 01:24:30.265026 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 01:24:30.268592 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 01:24:30.275109 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 01:24:30.278545 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 01:24:30.282192 Total UI for P1: 0, mck2ui 16
6283 01:24:30.285041 best dqsien dly found for B0: ( 0, 14, 24)
6284 01:24:30.288531 Total UI for P1: 0, mck2ui 16
6285 01:24:30.291685 best dqsien dly found for B1: ( 0, 14, 24)
6286 01:24:30.295016 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 01:24:30.298258 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 01:24:30.298381
6289 01:24:30.301809 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 01:24:30.304948 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 01:24:30.308306 [Gating] SW calibration Done
6292 01:24:30.308428 ==
6293 01:24:30.311867 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 01:24:30.318488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 01:24:30.318616 ==
6296 01:24:30.318728 RX Vref Scan: 0
6297 01:24:30.318836
6298 01:24:30.321850 RX Vref 0 -> 0, step: 1
6299 01:24:30.321970
6300 01:24:30.325295 RX Delay -410 -> 252, step: 16
6301 01:24:30.328487 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6302 01:24:30.331809 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6303 01:24:30.335318 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6304 01:24:30.341876 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6305 01:24:30.345054 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6306 01:24:30.348201 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6307 01:24:30.352068 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6308 01:24:30.358440 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6309 01:24:30.361724 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6310 01:24:30.365099 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6311 01:24:30.368660 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6312 01:24:30.375339 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6313 01:24:30.378453 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6314 01:24:30.381700 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6315 01:24:30.385269 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6316 01:24:30.392027 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6317 01:24:30.392108 ==
6318 01:24:30.394999 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 01:24:30.398316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 01:24:30.398399 ==
6321 01:24:30.398464 DQS Delay:
6322 01:24:30.401663 DQS0 = 27, DQS1 = 43
6323 01:24:30.401780 DQM Delay:
6324 01:24:30.404696 DQM0 = 12, DQM1 = 13
6325 01:24:30.404791 DQ Delay:
6326 01:24:30.408030 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6327 01:24:30.411921 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6328 01:24:30.414877 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6329 01:24:30.418095 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6330 01:24:30.418176
6331 01:24:30.418240
6332 01:24:30.418300 ==
6333 01:24:30.421503 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 01:24:30.424596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 01:24:30.424677 ==
6336 01:24:30.424742
6337 01:24:30.428102
6338 01:24:30.428182 TX Vref Scan disable
6339 01:24:30.431803 == TX Byte 0 ==
6340 01:24:30.435048 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 01:24:30.438394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 01:24:30.441394 == TX Byte 1 ==
6343 01:24:30.444577 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6344 01:24:30.448176 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6345 01:24:30.448261 ==
6346 01:24:30.451493 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 01:24:30.454785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 01:24:30.457921 ==
6349 01:24:30.458005
6350 01:24:30.458072
6351 01:24:30.458134 TX Vref Scan disable
6352 01:24:30.461179 == TX Byte 0 ==
6353 01:24:30.464534 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 01:24:30.468118 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 01:24:30.471462 == TX Byte 1 ==
6356 01:24:30.474694 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6357 01:24:30.478072 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6358 01:24:30.478157
6359 01:24:30.481364 [DATLAT]
6360 01:24:30.481448 Freq=400, CH0 RK0
6361 01:24:30.481517
6362 01:24:30.484783 DATLAT Default: 0xf
6363 01:24:30.484869 0, 0xFFFF, sum = 0
6364 01:24:30.487781 1, 0xFFFF, sum = 0
6365 01:24:30.487865 2, 0xFFFF, sum = 0
6366 01:24:30.491234 3, 0xFFFF, sum = 0
6367 01:24:30.491318 4, 0xFFFF, sum = 0
6368 01:24:30.494504 5, 0xFFFF, sum = 0
6369 01:24:30.494589 6, 0xFFFF, sum = 0
6370 01:24:30.498128 7, 0xFFFF, sum = 0
6371 01:24:30.498212 8, 0xFFFF, sum = 0
6372 01:24:30.501256 9, 0xFFFF, sum = 0
6373 01:24:30.501341 10, 0xFFFF, sum = 0
6374 01:24:30.504426 11, 0xFFFF, sum = 0
6375 01:24:30.504510 12, 0xFFFF, sum = 0
6376 01:24:30.507685 13, 0x0, sum = 1
6377 01:24:30.507773 14, 0x0, sum = 2
6378 01:24:30.511240 15, 0x0, sum = 3
6379 01:24:30.511324 16, 0x0, sum = 4
6380 01:24:30.514699 best_step = 14
6381 01:24:30.514790
6382 01:24:30.514858 ==
6383 01:24:30.517722 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 01:24:30.521180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 01:24:30.521265 ==
6386 01:24:30.524645 RX Vref Scan: 1
6387 01:24:30.524728
6388 01:24:30.524805 RX Vref 0 -> 0, step: 1
6389 01:24:30.524869
6390 01:24:30.527691 RX Delay -327 -> 252, step: 8
6391 01:24:30.527775
6392 01:24:30.531114 Set Vref, RX VrefLevel [Byte0]: 59
6393 01:24:30.534244 [Byte1]: 50
6394 01:24:30.539051
6395 01:24:30.539134 Final RX Vref Byte 0 = 59 to rank0
6396 01:24:30.542476 Final RX Vref Byte 1 = 50 to rank0
6397 01:24:30.545758 Final RX Vref Byte 0 = 59 to rank1
6398 01:24:30.549233 Final RX Vref Byte 1 = 50 to rank1==
6399 01:24:30.552426 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 01:24:30.559272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 01:24:30.559356 ==
6402 01:24:30.559433 DQS Delay:
6403 01:24:30.562119 DQS0 = 28, DQS1 = 48
6404 01:24:30.562206 DQM Delay:
6405 01:24:30.562273 DQM0 = 12, DQM1 = 14
6406 01:24:30.565554 DQ Delay:
6407 01:24:30.568729 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6408 01:24:30.568834 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6409 01:24:30.572548 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6410 01:24:30.575934 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6411 01:24:30.576018
6412 01:24:30.578933
6413 01:24:30.585977 [DQSOSCAuto] RK0, (LSB)MR18= 0xb4ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6414 01:24:30.589045 CH0 RK0: MR19=C0C, MR18=B4AC
6415 01:24:30.595542 CH0_RK0: MR19=0xC0C, MR18=0xB4AC, DQSOSC=387, MR23=63, INC=394, DEC=262
6416 01:24:30.595625 ==
6417 01:24:30.599233 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 01:24:30.602204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 01:24:30.602289 ==
6420 01:24:30.606307 [Gating] SW mode calibration
6421 01:24:30.612454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 01:24:30.615528 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 01:24:30.622369 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 01:24:30.625868 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 01:24:30.629156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 01:24:30.635541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 01:24:30.639104 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 01:24:30.642125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 01:24:30.648659 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 01:24:30.652349 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 01:24:30.655624 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 01:24:30.658682 Total UI for P1: 0, mck2ui 16
6433 01:24:30.662020 best dqsien dly found for B0: ( 0, 14, 24)
6434 01:24:30.665871 Total UI for P1: 0, mck2ui 16
6435 01:24:30.668767 best dqsien dly found for B1: ( 0, 14, 24)
6436 01:24:30.672204 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 01:24:30.675345 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 01:24:30.678705
6439 01:24:30.682366 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 01:24:30.685378 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 01:24:30.688574 [Gating] SW calibration Done
6442 01:24:30.688659 ==
6443 01:24:30.692274 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 01:24:30.695546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 01:24:30.695631 ==
6446 01:24:30.695699 RX Vref Scan: 0
6447 01:24:30.695763
6448 01:24:30.698649 RX Vref 0 -> 0, step: 1
6449 01:24:30.698737
6450 01:24:30.701935 RX Delay -410 -> 252, step: 16
6451 01:24:30.705350 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6452 01:24:30.711968 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6453 01:24:30.715349 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6454 01:24:30.718512 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6455 01:24:30.722251 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6456 01:24:30.728697 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6457 01:24:30.732537 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6458 01:24:30.735443 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6459 01:24:30.738613 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6460 01:24:30.742027 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6461 01:24:30.748769 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6462 01:24:30.751927 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6463 01:24:30.755755 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6464 01:24:30.762390 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6465 01:24:30.765165 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6466 01:24:30.768699 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6467 01:24:30.768805 ==
6468 01:24:30.772097 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 01:24:30.775653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 01:24:30.775738 ==
6471 01:24:30.778884 DQS Delay:
6472 01:24:30.778968 DQS0 = 27, DQS1 = 43
6473 01:24:30.782421 DQM Delay:
6474 01:24:30.782505 DQM0 = 9, DQM1 = 13
6475 01:24:30.782603 DQ Delay:
6476 01:24:30.785331 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6477 01:24:30.788668 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6478 01:24:30.792188 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6479 01:24:30.795528 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6480 01:24:30.795612
6481 01:24:30.795678
6482 01:24:30.795738 ==
6483 01:24:30.798648 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 01:24:30.805330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 01:24:30.805414 ==
6486 01:24:30.805480
6487 01:24:30.805541
6488 01:24:30.805600 TX Vref Scan disable
6489 01:24:30.808962 == TX Byte 0 ==
6490 01:24:30.812079 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6491 01:24:30.815618 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6492 01:24:30.818727 == TX Byte 1 ==
6493 01:24:30.822129 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6494 01:24:30.825173 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6495 01:24:30.825259 ==
6496 01:24:30.828598 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 01:24:30.835488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 01:24:30.835575 ==
6499 01:24:30.835660
6500 01:24:30.835740
6501 01:24:30.835819 TX Vref Scan disable
6502 01:24:30.838623 == TX Byte 0 ==
6503 01:24:30.841857 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6504 01:24:30.845448 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6505 01:24:30.848303 == TX Byte 1 ==
6506 01:24:30.851845 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6507 01:24:30.855359 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6508 01:24:30.855445
6509 01:24:30.858556 [DATLAT]
6510 01:24:30.858640 Freq=400, CH0 RK1
6511 01:24:30.858726
6512 01:24:30.861751 DATLAT Default: 0xe
6513 01:24:30.861836 0, 0xFFFF, sum = 0
6514 01:24:30.865550 1, 0xFFFF, sum = 0
6515 01:24:30.865637 2, 0xFFFF, sum = 0
6516 01:24:30.868706 3, 0xFFFF, sum = 0
6517 01:24:30.868811 4, 0xFFFF, sum = 0
6518 01:24:30.871952 5, 0xFFFF, sum = 0
6519 01:24:30.872038 6, 0xFFFF, sum = 0
6520 01:24:30.875181 7, 0xFFFF, sum = 0
6521 01:24:30.875267 8, 0xFFFF, sum = 0
6522 01:24:30.879002 9, 0xFFFF, sum = 0
6523 01:24:30.879088 10, 0xFFFF, sum = 0
6524 01:24:30.882016 11, 0xFFFF, sum = 0
6525 01:24:30.885031 12, 0xFFFF, sum = 0
6526 01:24:30.885119 13, 0x0, sum = 1
6527 01:24:30.885208 14, 0x0, sum = 2
6528 01:24:30.888377 15, 0x0, sum = 3
6529 01:24:30.888464 16, 0x0, sum = 4
6530 01:24:30.891753 best_step = 14
6531 01:24:30.891838
6532 01:24:30.891921 ==
6533 01:24:30.895299 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 01:24:30.898414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 01:24:30.898499 ==
6536 01:24:30.901700 RX Vref Scan: 0
6537 01:24:30.901784
6538 01:24:30.901868 RX Vref 0 -> 0, step: 1
6539 01:24:30.901949
6540 01:24:30.904790 RX Delay -327 -> 252, step: 8
6541 01:24:30.913163 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6542 01:24:30.916331 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6543 01:24:30.920598 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6544 01:24:30.926256 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6545 01:24:30.929561 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6546 01:24:30.932786 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6547 01:24:30.936222 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6548 01:24:30.939746 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6549 01:24:30.946463 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6550 01:24:30.949450 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6551 01:24:30.952821 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6552 01:24:30.956335 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6553 01:24:30.962808 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6554 01:24:30.966172 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6555 01:24:30.970014 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6556 01:24:30.976095 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6557 01:24:30.976180 ==
6558 01:24:30.979635 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 01:24:30.982781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 01:24:30.982866 ==
6561 01:24:30.982933 DQS Delay:
6562 01:24:30.986223 DQS0 = 28, DQS1 = 44
6563 01:24:30.986307 DQM Delay:
6564 01:24:30.989464 DQM0 = 10, DQM1 = 16
6565 01:24:30.989548 DQ Delay:
6566 01:24:30.992945 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6567 01:24:30.996294 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6568 01:24:30.999521 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6569 01:24:31.002574 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6570 01:24:31.002658
6571 01:24:31.002724
6572 01:24:31.009507 [DQSOSCAuto] RK1, (LSB)MR18= 0xba70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6573 01:24:31.012745 CH0 RK1: MR19=C0C, MR18=BA70
6574 01:24:31.019481 CH0_RK1: MR19=0xC0C, MR18=0xBA70, DQSOSC=386, MR23=63, INC=396, DEC=264
6575 01:24:31.023009 [RxdqsGatingPostProcess] freq 400
6576 01:24:31.026301 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 01:24:31.029632 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 01:24:31.033026 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 01:24:31.036355 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 01:24:31.039734 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 01:24:31.042779 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 01:24:31.046240 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 01:24:31.049515 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 01:24:31.053233 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 01:24:31.056175 Pre-setting of DQS Precalculation
6586 01:24:31.059628 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 01:24:31.059750 ==
6588 01:24:31.063130 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 01:24:31.069612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 01:24:31.069737 ==
6591 01:24:31.073278 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 01:24:31.080070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6593 01:24:31.083648 [CA 0] Center 36 (8~64) winsize 57
6594 01:24:31.086448 [CA 1] Center 36 (8~64) winsize 57
6595 01:24:31.089847 [CA 2] Center 36 (8~64) winsize 57
6596 01:24:31.093030 [CA 3] Center 36 (8~64) winsize 57
6597 01:24:31.096119 [CA 4] Center 36 (8~64) winsize 57
6598 01:24:31.099647 [CA 5] Center 36 (8~64) winsize 57
6599 01:24:31.099771
6600 01:24:31.102883 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6601 01:24:31.103006
6602 01:24:31.106034 [CATrainingPosCal] consider 1 rank data
6603 01:24:31.109329 u2DelayCellTimex100 = 270/100 ps
6604 01:24:31.112563 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 01:24:31.116351 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 01:24:31.119386 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 01:24:31.122720 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 01:24:31.126039 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 01:24:31.132645 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 01:24:31.132775
6611 01:24:31.136058 CA PerBit enable=1, Macro0, CA PI delay=36
6612 01:24:31.136142
6613 01:24:31.139425 [CBTSetCACLKResult] CA Dly = 36
6614 01:24:31.139510 CS Dly: 1 (0~32)
6615 01:24:31.139576 ==
6616 01:24:31.142440 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 01:24:31.145871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 01:24:31.149281 ==
6619 01:24:31.152566 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 01:24:31.158967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6621 01:24:31.162256 [CA 0] Center 36 (8~64) winsize 57
6622 01:24:31.165748 [CA 1] Center 36 (8~64) winsize 57
6623 01:24:31.169196 [CA 2] Center 36 (8~64) winsize 57
6624 01:24:31.172576 [CA 3] Center 36 (8~64) winsize 57
6625 01:24:31.175875 [CA 4] Center 36 (8~64) winsize 57
6626 01:24:31.179087 [CA 5] Center 36 (8~64) winsize 57
6627 01:24:31.179173
6628 01:24:31.182427 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6629 01:24:31.182512
6630 01:24:31.185896 [CATrainingPosCal] consider 2 rank data
6631 01:24:31.189573 u2DelayCellTimex100 = 270/100 ps
6632 01:24:31.192491 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 01:24:31.195832 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 01:24:31.199563 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 01:24:31.202730 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 01:24:31.205734 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 01:24:31.209205 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 01:24:31.209289
6639 01:24:31.212480 CA PerBit enable=1, Macro0, CA PI delay=36
6640 01:24:31.212564
6641 01:24:31.215975 [CBTSetCACLKResult] CA Dly = 36
6642 01:24:31.219421 CS Dly: 1 (0~32)
6643 01:24:31.219505
6644 01:24:31.222615 ----->DramcWriteLeveling(PI) begin...
6645 01:24:31.222747 ==
6646 01:24:31.226080 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 01:24:31.229005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 01:24:31.229090 ==
6649 01:24:31.232649 Write leveling (Byte 0): 40 => 8
6650 01:24:31.235732 Write leveling (Byte 1): 32 => 0
6651 01:24:31.239085 DramcWriteLeveling(PI) end<-----
6652 01:24:31.239169
6653 01:24:31.239236 ==
6654 01:24:31.242445 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 01:24:31.246010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 01:24:31.246094 ==
6657 01:24:31.249213 [Gating] SW mode calibration
6658 01:24:31.255581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 01:24:31.262277 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 01:24:31.265628 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 01:24:31.269238 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 01:24:31.275783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 01:24:31.279785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 01:24:31.283122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 01:24:31.289014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 01:24:31.292404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 01:24:31.295913 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 01:24:31.302396 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 01:24:31.302521 Total UI for P1: 0, mck2ui 16
6670 01:24:31.308967 best dqsien dly found for B0: ( 0, 14, 24)
6671 01:24:31.309091 Total UI for P1: 0, mck2ui 16
6672 01:24:31.316030 best dqsien dly found for B1: ( 0, 14, 24)
6673 01:24:31.318992 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 01:24:31.322221 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 01:24:31.322304
6676 01:24:31.325556 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 01:24:31.328931 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 01:24:31.332912 [Gating] SW calibration Done
6679 01:24:31.332995 ==
6680 01:24:31.335898 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 01:24:31.338595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 01:24:31.338679 ==
6683 01:24:31.342044 RX Vref Scan: 0
6684 01:24:31.342127
6685 01:24:31.342194 RX Vref 0 -> 0, step: 1
6686 01:24:31.345487
6687 01:24:31.345611 RX Delay -410 -> 252, step: 16
6688 01:24:31.352389 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6689 01:24:31.355425 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6690 01:24:31.358584 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6691 01:24:31.361740 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6692 01:24:31.368579 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6693 01:24:31.371679 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6694 01:24:31.375093 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6695 01:24:31.378571 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6696 01:24:31.384998 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6697 01:24:31.388172 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6698 01:24:31.391623 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6699 01:24:31.398302 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6700 01:24:31.401585 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6701 01:24:31.405331 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6702 01:24:31.408272 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6703 01:24:31.414930 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6704 01:24:31.415014 ==
6705 01:24:31.418531 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 01:24:31.421930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 01:24:31.422014 ==
6708 01:24:31.422081 DQS Delay:
6709 01:24:31.424960 DQS0 = 27, DQS1 = 43
6710 01:24:31.425043 DQM Delay:
6711 01:24:31.428281 DQM0 = 6, DQM1 = 17
6712 01:24:31.428364 DQ Delay:
6713 01:24:31.431496 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6714 01:24:31.434950 DQ4 =0, DQ5 =24, DQ6 =16, DQ7 =0
6715 01:24:31.438174 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6716 01:24:31.441488 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6717 01:24:31.441577
6718 01:24:31.441644
6719 01:24:31.441743 ==
6720 01:24:31.445411 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 01:24:31.448473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 01:24:31.448559 ==
6723 01:24:31.448626
6724 01:24:31.448689
6725 01:24:31.451529 TX Vref Scan disable
6726 01:24:31.451612 == TX Byte 0 ==
6727 01:24:31.458003 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 01:24:31.461394 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 01:24:31.461481 == TX Byte 1 ==
6730 01:24:31.468251 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6731 01:24:31.471626 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6732 01:24:31.471711 ==
6733 01:24:31.474676 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 01:24:31.478168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 01:24:31.478251 ==
6736 01:24:31.478318
6737 01:24:31.478378
6738 01:24:31.481378 TX Vref Scan disable
6739 01:24:31.481461 == TX Byte 0 ==
6740 01:24:31.488223 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 01:24:31.491311 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 01:24:31.491411 == TX Byte 1 ==
6743 01:24:31.498033 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6744 01:24:31.501364 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6745 01:24:31.501448
6746 01:24:31.501514 [DATLAT]
6747 01:24:31.504885 Freq=400, CH1 RK0
6748 01:24:31.504968
6749 01:24:31.505034 DATLAT Default: 0xf
6750 01:24:31.508175 0, 0xFFFF, sum = 0
6751 01:24:31.508260 1, 0xFFFF, sum = 0
6752 01:24:31.511521 2, 0xFFFF, sum = 0
6753 01:24:31.511606 3, 0xFFFF, sum = 0
6754 01:24:31.514810 4, 0xFFFF, sum = 0
6755 01:24:31.514895 5, 0xFFFF, sum = 0
6756 01:24:31.518107 6, 0xFFFF, sum = 0
6757 01:24:31.521517 7, 0xFFFF, sum = 0
6758 01:24:31.521637 8, 0xFFFF, sum = 0
6759 01:24:31.525132 9, 0xFFFF, sum = 0
6760 01:24:31.525255 10, 0xFFFF, sum = 0
6761 01:24:31.528066 11, 0xFFFF, sum = 0
6762 01:24:31.528186 12, 0xFFFF, sum = 0
6763 01:24:31.531568 13, 0x0, sum = 1
6764 01:24:31.531690 14, 0x0, sum = 2
6765 01:24:31.534908 15, 0x0, sum = 3
6766 01:24:31.535031 16, 0x0, sum = 4
6767 01:24:31.535149 best_step = 14
6768 01:24:31.535255
6769 01:24:31.538315 ==
6770 01:24:31.541468 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 01:24:31.545008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 01:24:31.545133 ==
6773 01:24:31.545245 RX Vref Scan: 1
6774 01:24:31.545359
6775 01:24:31.548172 RX Vref 0 -> 0, step: 1
6776 01:24:31.548288
6777 01:24:31.551367 RX Delay -327 -> 252, step: 8
6778 01:24:31.551485
6779 01:24:31.554733 Set Vref, RX VrefLevel [Byte0]: 51
6780 01:24:31.558148 [Byte1]: 53
6781 01:24:31.561594
6782 01:24:31.561697 Final RX Vref Byte 0 = 51 to rank0
6783 01:24:31.565144 Final RX Vref Byte 1 = 53 to rank0
6784 01:24:31.568131 Final RX Vref Byte 0 = 51 to rank1
6785 01:24:31.571809 Final RX Vref Byte 1 = 53 to rank1==
6786 01:24:31.574939 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 01:24:31.578161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 01:24:31.581739 ==
6789 01:24:31.581822 DQS Delay:
6790 01:24:31.581888 DQS0 = 32, DQS1 = 40
6791 01:24:31.584889 DQM Delay:
6792 01:24:31.584972 DQM0 = 12, DQM1 = 12
6793 01:24:31.588424 DQ Delay:
6794 01:24:31.592013 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6795 01:24:31.592097 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6796 01:24:31.594852 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6797 01:24:31.598147 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6798 01:24:31.598230
6799 01:24:31.598297
6800 01:24:31.608492 [DQSOSCAuto] RK0, (LSB)MR18= 0x97d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6801 01:24:31.611843 CH1 RK0: MR19=C0C, MR18=97D1
6802 01:24:31.618375 CH1_RK0: MR19=0xC0C, MR18=0x97D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6803 01:24:31.618474 ==
6804 01:24:31.621608 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 01:24:31.624848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 01:24:31.624933 ==
6807 01:24:31.628218 [Gating] SW mode calibration
6808 01:24:31.634748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 01:24:31.638454 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 01:24:31.645406 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 01:24:31.648080 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 01:24:31.651433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 01:24:31.658322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 01:24:31.661803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 01:24:31.665063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 01:24:31.671902 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 01:24:31.675046 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 01:24:31.678457 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 01:24:31.681802 Total UI for P1: 0, mck2ui 16
6820 01:24:31.685123 best dqsien dly found for B0: ( 0, 14, 24)
6821 01:24:31.688886 Total UI for P1: 0, mck2ui 16
6822 01:24:31.691630 best dqsien dly found for B1: ( 0, 14, 24)
6823 01:24:31.695257 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 01:24:31.698273 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 01:24:31.698357
6826 01:24:31.701741 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 01:24:31.708486 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 01:24:31.708570 [Gating] SW calibration Done
6829 01:24:31.711799 ==
6830 01:24:31.711882 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 01:24:31.718254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 01:24:31.718338 ==
6833 01:24:31.718405 RX Vref Scan: 0
6834 01:24:31.718468
6835 01:24:31.721534 RX Vref 0 -> 0, step: 1
6836 01:24:31.721617
6837 01:24:31.725095 RX Delay -410 -> 252, step: 16
6838 01:24:31.729073 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6839 01:24:31.731636 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6840 01:24:31.738416 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6841 01:24:31.741618 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6842 01:24:31.745366 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6843 01:24:31.748350 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6844 01:24:31.755119 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6845 01:24:31.758490 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6846 01:24:31.761575 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6847 01:24:31.765295 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6848 01:24:31.771552 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6849 01:24:31.775292 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6850 01:24:31.778211 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6851 01:24:31.781577 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6852 01:24:31.788230 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6853 01:24:31.791771 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6854 01:24:31.791854 ==
6855 01:24:31.795008 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 01:24:31.798193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 01:24:31.798277 ==
6858 01:24:31.801661 DQS Delay:
6859 01:24:31.801745 DQS0 = 35, DQS1 = 43
6860 01:24:31.805206 DQM Delay:
6861 01:24:31.805289 DQM0 = 16, DQM1 = 18
6862 01:24:31.805356 DQ Delay:
6863 01:24:31.808374 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6864 01:24:31.811748 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6865 01:24:31.815187 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6866 01:24:31.818492 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6867 01:24:31.818589
6868 01:24:31.818656
6869 01:24:31.818719 ==
6870 01:24:31.821748 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 01:24:31.828231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 01:24:31.828315 ==
6873 01:24:31.828381
6874 01:24:31.828443
6875 01:24:31.828502 TX Vref Scan disable
6876 01:24:31.831501 == TX Byte 0 ==
6877 01:24:31.834969 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6878 01:24:31.838113 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6879 01:24:31.841707 == TX Byte 1 ==
6880 01:24:31.845051 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6881 01:24:31.848267 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6882 01:24:31.848350 ==
6883 01:24:31.851473 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 01:24:31.858227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 01:24:31.858311 ==
6886 01:24:31.858377
6887 01:24:31.858439
6888 01:24:31.858498 TX Vref Scan disable
6889 01:24:31.861522 == TX Byte 0 ==
6890 01:24:31.864838 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6891 01:24:31.868143 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6892 01:24:31.871277 == TX Byte 1 ==
6893 01:24:31.874693 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6894 01:24:31.878090 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6895 01:24:31.878174
6896 01:24:31.881388 [DATLAT]
6897 01:24:31.881471 Freq=400, CH1 RK1
6898 01:24:31.881538
6899 01:24:31.884493 DATLAT Default: 0xe
6900 01:24:31.884577 0, 0xFFFF, sum = 0
6901 01:24:31.887865 1, 0xFFFF, sum = 0
6902 01:24:31.887951 2, 0xFFFF, sum = 0
6903 01:24:31.891329 3, 0xFFFF, sum = 0
6904 01:24:31.891414 4, 0xFFFF, sum = 0
6905 01:24:31.894571 5, 0xFFFF, sum = 0
6906 01:24:31.894655 6, 0xFFFF, sum = 0
6907 01:24:31.897793 7, 0xFFFF, sum = 0
6908 01:24:31.897877 8, 0xFFFF, sum = 0
6909 01:24:31.901022 9, 0xFFFF, sum = 0
6910 01:24:31.904856 10, 0xFFFF, sum = 0
6911 01:24:31.904941 11, 0xFFFF, sum = 0
6912 01:24:31.907869 12, 0xFFFF, sum = 0
6913 01:24:31.907955 13, 0x0, sum = 1
6914 01:24:31.911560 14, 0x0, sum = 2
6915 01:24:31.911644 15, 0x0, sum = 3
6916 01:24:31.911712 16, 0x0, sum = 4
6917 01:24:31.914843 best_step = 14
6918 01:24:31.914969
6919 01:24:31.915083 ==
6920 01:24:31.917890 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 01:24:31.920980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 01:24:31.921100 ==
6923 01:24:31.924388 RX Vref Scan: 0
6924 01:24:31.924508
6925 01:24:31.924619 RX Vref 0 -> 0, step: 1
6926 01:24:31.927714
6927 01:24:31.927817 RX Delay -327 -> 252, step: 8
6928 01:24:31.936306 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6929 01:24:31.939451 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6930 01:24:31.943041 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6931 01:24:31.946344 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6932 01:24:31.952720 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6933 01:24:31.956171 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6934 01:24:31.959346 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6935 01:24:31.962880 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6936 01:24:31.969313 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6937 01:24:31.973081 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6938 01:24:31.976124 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6939 01:24:31.979759 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6940 01:24:31.985989 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6941 01:24:31.989632 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6942 01:24:31.992886 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6943 01:24:31.999170 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6944 01:24:31.999254 ==
6945 01:24:32.002728 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 01:24:32.006047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 01:24:32.006134 ==
6948 01:24:32.006202 DQS Delay:
6949 01:24:32.009358 DQS0 = 32, DQS1 = 36
6950 01:24:32.009441 DQM Delay:
6951 01:24:32.012634 DQM0 = 13, DQM1 = 10
6952 01:24:32.012720 DQ Delay:
6953 01:24:32.015864 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6954 01:24:32.019161 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6955 01:24:32.022332 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6956 01:24:32.025675 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6957 01:24:32.025762
6958 01:24:32.025848
6959 01:24:32.032643 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf58, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6960 01:24:32.035900 CH1 RK1: MR19=C0C, MR18=AF58
6961 01:24:32.042329 CH1_RK1: MR19=0xC0C, MR18=0xAF58, DQSOSC=388, MR23=63, INC=392, DEC=261
6962 01:24:32.046124 [RxdqsGatingPostProcess] freq 400
6963 01:24:32.052139 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 01:24:32.052225 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 01:24:32.055762 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 01:24:32.059102 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 01:24:32.062207 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 01:24:32.065207 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 01:24:32.069167 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 01:24:32.072010 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 01:24:32.075322 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 01:24:32.078662 Pre-setting of DQS Precalculation
6973 01:24:32.085215 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 01:24:32.092316 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 01:24:32.099050 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 01:24:32.099135
6977 01:24:32.099202
6978 01:24:32.101717 [Calibration Summary] 800 Mbps
6979 01:24:32.101801 CH 0, Rank 0
6980 01:24:32.105179 SW Impedance : PASS
6981 01:24:32.108660 DUTY Scan : NO K
6982 01:24:32.108768 ZQ Calibration : PASS
6983 01:24:32.111951 Jitter Meter : NO K
6984 01:24:32.112035 CBT Training : PASS
6985 01:24:32.115413 Write leveling : PASS
6986 01:24:32.118348 RX DQS gating : PASS
6987 01:24:32.118433 RX DQ/DQS(RDDQC) : PASS
6988 01:24:32.122288 TX DQ/DQS : PASS
6989 01:24:32.125336 RX DATLAT : PASS
6990 01:24:32.125421 RX DQ/DQS(Engine): PASS
6991 01:24:32.128630 TX OE : NO K
6992 01:24:32.128715 All Pass.
6993 01:24:32.128821
6994 01:24:32.131990 CH 0, Rank 1
6995 01:24:32.132075 SW Impedance : PASS
6996 01:24:32.135048 DUTY Scan : NO K
6997 01:24:32.138473 ZQ Calibration : PASS
6998 01:24:32.138557 Jitter Meter : NO K
6999 01:24:32.141809 CBT Training : PASS
7000 01:24:32.145305 Write leveling : NO K
7001 01:24:32.145390 RX DQS gating : PASS
7002 01:24:32.148399 RX DQ/DQS(RDDQC) : PASS
7003 01:24:32.151434 TX DQ/DQS : PASS
7004 01:24:32.151556 RX DATLAT : PASS
7005 01:24:32.154875 RX DQ/DQS(Engine): PASS
7006 01:24:32.158125 TX OE : NO K
7007 01:24:32.158246 All Pass.
7008 01:24:32.158359
7009 01:24:32.158475 CH 1, Rank 0
7010 01:24:32.161408 SW Impedance : PASS
7011 01:24:32.165038 DUTY Scan : NO K
7012 01:24:32.165159 ZQ Calibration : PASS
7013 01:24:32.168199 Jitter Meter : NO K
7014 01:24:32.171487 CBT Training : PASS
7015 01:24:32.171611 Write leveling : PASS
7016 01:24:32.174773 RX DQS gating : PASS
7017 01:24:32.174893 RX DQ/DQS(RDDQC) : PASS
7018 01:24:32.178343 TX DQ/DQS : PASS
7019 01:24:32.181377 RX DATLAT : PASS
7020 01:24:32.181496 RX DQ/DQS(Engine): PASS
7021 01:24:32.184899 TX OE : NO K
7022 01:24:32.185021 All Pass.
7023 01:24:32.185133
7024 01:24:32.188061 CH 1, Rank 1
7025 01:24:32.188146 SW Impedance : PASS
7026 01:24:32.191312 DUTY Scan : NO K
7027 01:24:32.194861 ZQ Calibration : PASS
7028 01:24:32.194944 Jitter Meter : NO K
7029 01:24:32.197783 CBT Training : PASS
7030 01:24:32.201833 Write leveling : NO K
7031 01:24:32.201916 RX DQS gating : PASS
7032 01:24:32.204613 RX DQ/DQS(RDDQC) : PASS
7033 01:24:32.208206 TX DQ/DQS : PASS
7034 01:24:32.208289 RX DATLAT : PASS
7035 01:24:32.211221 RX DQ/DQS(Engine): PASS
7036 01:24:32.214523 TX OE : NO K
7037 01:24:32.214606 All Pass.
7038 01:24:32.214672
7039 01:24:32.214739 DramC Write-DBI off
7040 01:24:32.218002 PER_BANK_REFRESH: Hybrid Mode
7041 01:24:32.220979 TX_TRACKING: ON
7042 01:24:32.228300 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 01:24:32.234317 [FAST_K] Save calibration result to emmc
7044 01:24:32.237754 dramc_set_vcore_voltage set vcore to 725000
7045 01:24:32.237838 Read voltage for 1600, 0
7046 01:24:32.241233 Vio18 = 0
7047 01:24:32.241316 Vcore = 725000
7048 01:24:32.241382 Vdram = 0
7049 01:24:32.244215 Vddq = 0
7050 01:24:32.244298 Vmddr = 0
7051 01:24:32.247990 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 01:24:32.254342 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 01:24:32.257708 MEM_TYPE=3, freq_sel=13
7054 01:24:32.261014 sv_algorithm_assistance_LP4_3733
7055 01:24:32.264317 ============ PULL DRAM RESETB DOWN ============
7056 01:24:32.267457 ========== PULL DRAM RESETB DOWN end =========
7057 01:24:32.273970 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 01:24:32.277298 ===================================
7059 01:24:32.277382 LPDDR4 DRAM CONFIGURATION
7060 01:24:32.280536 ===================================
7061 01:24:32.283992 EX_ROW_EN[0] = 0x0
7062 01:24:32.284075 EX_ROW_EN[1] = 0x0
7063 01:24:32.287826 LP4Y_EN = 0x0
7064 01:24:32.287912 WORK_FSP = 0x1
7065 01:24:32.290670 WL = 0x5
7066 01:24:32.290753 RL = 0x5
7067 01:24:32.293930 BL = 0x2
7068 01:24:32.294014 RPST = 0x0
7069 01:24:32.297281 RD_PRE = 0x0
7070 01:24:32.300414 WR_PRE = 0x1
7071 01:24:32.300497 WR_PST = 0x1
7072 01:24:32.303975 DBI_WR = 0x0
7073 01:24:32.304059 DBI_RD = 0x0
7074 01:24:32.306970 OTF = 0x1
7075 01:24:32.310481 ===================================
7076 01:24:32.314192 ===================================
7077 01:24:32.314277 ANA top config
7078 01:24:32.317060 ===================================
7079 01:24:32.320390 DLL_ASYNC_EN = 0
7080 01:24:32.323770 ALL_SLAVE_EN = 0
7081 01:24:32.323854 NEW_RANK_MODE = 1
7082 01:24:32.327503 DLL_IDLE_MODE = 1
7083 01:24:32.330571 LP45_APHY_COMB_EN = 1
7084 01:24:32.333932 TX_ODT_DIS = 0
7085 01:24:32.334016 NEW_8X_MODE = 1
7086 01:24:32.337134 ===================================
7087 01:24:32.340342 ===================================
7088 01:24:32.343633 data_rate = 3200
7089 01:24:32.347364 CKR = 1
7090 01:24:32.351020 DQ_P2S_RATIO = 8
7091 01:24:32.353665 ===================================
7092 01:24:32.357229 CA_P2S_RATIO = 8
7093 01:24:32.360358 DQ_CA_OPEN = 0
7094 01:24:32.360442 DQ_SEMI_OPEN = 0
7095 01:24:32.363768 CA_SEMI_OPEN = 0
7096 01:24:32.366908 CA_FULL_RATE = 0
7097 01:24:32.370467 DQ_CKDIV4_EN = 0
7098 01:24:32.373621 CA_CKDIV4_EN = 0
7099 01:24:32.376983 CA_PREDIV_EN = 0
7100 01:24:32.377068 PH8_DLY = 12
7101 01:24:32.380186 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 01:24:32.383501 DQ_AAMCK_DIV = 4
7103 01:24:32.386851 CA_AAMCK_DIV = 4
7104 01:24:32.390304 CA_ADMCK_DIV = 4
7105 01:24:32.393506 DQ_TRACK_CA_EN = 0
7106 01:24:32.396989 CA_PICK = 1600
7107 01:24:32.397075 CA_MCKIO = 1600
7108 01:24:32.400524 MCKIO_SEMI = 0
7109 01:24:32.403449 PLL_FREQ = 3068
7110 01:24:32.406915 DQ_UI_PI_RATIO = 32
7111 01:24:32.410345 CA_UI_PI_RATIO = 0
7112 01:24:32.413648 ===================================
7113 01:24:32.416933 ===================================
7114 01:24:32.420035 memory_type:LPDDR4
7115 01:24:32.420119 GP_NUM : 10
7116 01:24:32.423395 SRAM_EN : 1
7117 01:24:32.423480 MD32_EN : 0
7118 01:24:32.427011 ===================================
7119 01:24:32.430575 [ANA_INIT] >>>>>>>>>>>>>>
7120 01:24:32.433777 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 01:24:32.437292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 01:24:32.440195 ===================================
7123 01:24:32.443806 data_rate = 3200,PCW = 0X7600
7124 01:24:32.446779 ===================================
7125 01:24:32.450738 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 01:24:32.453924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 01:24:32.460110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 01:24:32.466721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 01:24:32.470352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 01:24:32.473410 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 01:24:32.473495 [ANA_INIT] flow start
7132 01:24:32.476837 [ANA_INIT] PLL >>>>>>>>
7133 01:24:32.480174 [ANA_INIT] PLL <<<<<<<<
7134 01:24:32.480259 [ANA_INIT] MIDPI >>>>>>>>
7135 01:24:32.483220 [ANA_INIT] MIDPI <<<<<<<<
7136 01:24:32.486903 [ANA_INIT] DLL >>>>>>>>
7137 01:24:32.486987 [ANA_INIT] DLL <<<<<<<<
7138 01:24:32.490438 [ANA_INIT] flow end
7139 01:24:32.493195 ============ LP4 DIFF to SE enter ============
7140 01:24:32.496611 ============ LP4 DIFF to SE exit ============
7141 01:24:32.499858 [ANA_INIT] <<<<<<<<<<<<<
7142 01:24:32.503304 [Flow] Enable top DCM control >>>>>
7143 01:24:32.506688 [Flow] Enable top DCM control <<<<<
7144 01:24:32.510129 Enable DLL master slave shuffle
7145 01:24:32.517019 ==============================================================
7146 01:24:32.517105 Gating Mode config
7147 01:24:32.523371 ==============================================================
7148 01:24:32.523456 Config description:
7149 01:24:32.533182 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 01:24:32.540277 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 01:24:32.546365 SELPH_MODE 0: By rank 1: By Phase
7152 01:24:32.549754 ==============================================================
7153 01:24:32.553324 GAT_TRACK_EN = 1
7154 01:24:32.556563 RX_GATING_MODE = 2
7155 01:24:32.560115 RX_GATING_TRACK_MODE = 2
7156 01:24:32.563130 SELPH_MODE = 1
7157 01:24:32.566480 PICG_EARLY_EN = 1
7158 01:24:32.569843 VALID_LAT_VALUE = 1
7159 01:24:32.576550 ==============================================================
7160 01:24:32.579562 Enter into Gating configuration >>>>
7161 01:24:32.583209 Exit from Gating configuration <<<<
7162 01:24:32.583294 Enter into DVFS_PRE_config >>>>>
7163 01:24:32.596397 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 01:24:32.599656 Exit from DVFS_PRE_config <<<<<
7165 01:24:32.602812 Enter into PICG configuration >>>>
7166 01:24:32.606330 Exit from PICG configuration <<<<
7167 01:24:32.606415 [RX_INPUT] configuration >>>>>
7168 01:24:32.609705 [RX_INPUT] configuration <<<<<
7169 01:24:32.616417 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 01:24:32.619461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 01:24:32.626585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 01:24:32.632867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 01:24:32.639351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 01:24:32.646584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 01:24:32.649607 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 01:24:32.652780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 01:24:32.659664 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 01:24:32.662719 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 01:24:32.666026 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 01:24:32.669794 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 01:24:32.672730 ===================================
7182 01:24:32.676021 LPDDR4 DRAM CONFIGURATION
7183 01:24:32.679368 ===================================
7184 01:24:32.683237 EX_ROW_EN[0] = 0x0
7185 01:24:32.683322 EX_ROW_EN[1] = 0x0
7186 01:24:32.686124 LP4Y_EN = 0x0
7187 01:24:32.686209 WORK_FSP = 0x1
7188 01:24:32.689355 WL = 0x5
7189 01:24:32.689440 RL = 0x5
7190 01:24:32.692860 BL = 0x2
7191 01:24:32.692944 RPST = 0x0
7192 01:24:32.696118 RD_PRE = 0x0
7193 01:24:32.696202 WR_PRE = 0x1
7194 01:24:32.699315 WR_PST = 0x1
7195 01:24:32.699424 DBI_WR = 0x0
7196 01:24:32.702653 DBI_RD = 0x0
7197 01:24:32.702737 OTF = 0x1
7198 01:24:32.706131 ===================================
7199 01:24:32.712879 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 01:24:32.716564 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 01:24:32.719580 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 01:24:32.722834 ===================================
7203 01:24:32.726092 LPDDR4 DRAM CONFIGURATION
7204 01:24:32.729324 ===================================
7205 01:24:32.732731 EX_ROW_EN[0] = 0x10
7206 01:24:32.732868 EX_ROW_EN[1] = 0x0
7207 01:24:32.735819 LP4Y_EN = 0x0
7208 01:24:32.735938 WORK_FSP = 0x1
7209 01:24:32.739497 WL = 0x5
7210 01:24:32.739615 RL = 0x5
7211 01:24:32.742987 BL = 0x2
7212 01:24:32.743108 RPST = 0x0
7213 01:24:32.745934 RD_PRE = 0x0
7214 01:24:32.746053 WR_PRE = 0x1
7215 01:24:32.749285 WR_PST = 0x1
7216 01:24:32.749405 DBI_WR = 0x0
7217 01:24:32.752530 DBI_RD = 0x0
7218 01:24:32.752635 OTF = 0x1
7219 01:24:32.756088 ===================================
7220 01:24:32.762628 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 01:24:32.762712 ==
7222 01:24:32.765925 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 01:24:32.769441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 01:24:32.772866 ==
7225 01:24:32.772951 [Duty_Offset_Calibration]
7226 01:24:32.776080 B0:2 B1:0 CA:1
7227 01:24:32.776188
7228 01:24:32.779478 [DutyScan_Calibration_Flow] k_type=0
7229 01:24:32.787532
7230 01:24:32.787615 ==CLK 0==
7231 01:24:32.790686 Final CLK duty delay cell = -4
7232 01:24:32.794090 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7233 01:24:32.797569 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7234 01:24:32.800893 [-4] AVG Duty = 4922%(X100)
7235 01:24:32.800976
7236 01:24:32.803946 CH0 CLK Duty spec in!! Max-Min= 218%
7237 01:24:32.807495 [DutyScan_Calibration_Flow] ====Done====
7238 01:24:32.807604
7239 01:24:32.810665 [DutyScan_Calibration_Flow] k_type=1
7240 01:24:32.826799
7241 01:24:32.826883 ==DQS 0 ==
7242 01:24:32.830515 Final DQS duty delay cell = 0
7243 01:24:32.833360 [0] MAX Duty = 5249%(X100), DQS PI = 32
7244 01:24:32.837065 [0] MIN Duty = 4969%(X100), DQS PI = 0
7245 01:24:32.837150 [0] AVG Duty = 5109%(X100)
7246 01:24:32.840470
7247 01:24:32.840554 ==DQS 1 ==
7248 01:24:32.843585 Final DQS duty delay cell = -4
7249 01:24:32.847310 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7250 01:24:32.849958 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7251 01:24:32.853384 [-4] AVG Duty = 5000%(X100)
7252 01:24:32.853468
7253 01:24:32.856608 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7254 01:24:32.856708
7255 01:24:32.860609 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7256 01:24:32.863764 [DutyScan_Calibration_Flow] ====Done====
7257 01:24:32.863849
7258 01:24:32.866714 [DutyScan_Calibration_Flow] k_type=3
7259 01:24:32.884490
7260 01:24:32.884574 ==DQM 0 ==
7261 01:24:32.887781 Final DQM duty delay cell = 0
7262 01:24:32.891110 [0] MAX Duty = 5093%(X100), DQS PI = 28
7263 01:24:32.894556 [0] MIN Duty = 4813%(X100), DQS PI = 50
7264 01:24:32.894640 [0] AVG Duty = 4953%(X100)
7265 01:24:32.897590
7266 01:24:32.897674 ==DQM 1 ==
7267 01:24:32.901499 Final DQM duty delay cell = 0
7268 01:24:32.904596 [0] MAX Duty = 5249%(X100), DQS PI = 28
7269 01:24:32.907936 [0] MIN Duty = 5000%(X100), DQS PI = 20
7270 01:24:32.908081 [0] AVG Duty = 5124%(X100)
7271 01:24:32.908215
7272 01:24:32.914563 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7273 01:24:32.914647
7274 01:24:32.917802 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7275 01:24:32.921053 [DutyScan_Calibration_Flow] ====Done====
7276 01:24:32.921137
7277 01:24:32.924213 [DutyScan_Calibration_Flow] k_type=2
7278 01:24:32.941881
7279 01:24:32.941969 ==DQ 0 ==
7280 01:24:32.944745 Final DQ duty delay cell = 0
7281 01:24:32.948376 [0] MAX Duty = 5156%(X100), DQS PI = 36
7282 01:24:32.951795 [0] MIN Duty = 5000%(X100), DQS PI = 0
7283 01:24:32.951880 [0] AVG Duty = 5078%(X100)
7284 01:24:32.954886
7285 01:24:32.954970 ==DQ 1 ==
7286 01:24:32.958296 Final DQ duty delay cell = 0
7287 01:24:32.961387 [0] MAX Duty = 4969%(X100), DQS PI = 42
7288 01:24:32.964926 [0] MIN Duty = 4875%(X100), DQS PI = 10
7289 01:24:32.965054 [0] AVG Duty = 4922%(X100)
7290 01:24:32.965165
7291 01:24:32.967958 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7292 01:24:32.971413
7293 01:24:32.974596 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7294 01:24:32.977916 [DutyScan_Calibration_Flow] ====Done====
7295 01:24:32.978036 ==
7296 01:24:32.981551 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 01:24:32.984870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 01:24:32.984992 ==
7299 01:24:32.988046 [Duty_Offset_Calibration]
7300 01:24:32.988169 B0:0 B1:-1 CA:2
7301 01:24:32.988283
7302 01:24:32.991395 [DutyScan_Calibration_Flow] k_type=0
7303 01:24:33.001558
7304 01:24:33.001642 ==CLK 0==
7305 01:24:33.005467 Final CLK duty delay cell = 0
7306 01:24:33.008243 [0] MAX Duty = 5156%(X100), DQS PI = 10
7307 01:24:33.011767 [0] MIN Duty = 4938%(X100), DQS PI = 46
7308 01:24:33.011869 [0] AVG Duty = 5047%(X100)
7309 01:24:33.015115
7310 01:24:33.018334 CH1 CLK Duty spec in!! Max-Min= 218%
7311 01:24:33.021767 [DutyScan_Calibration_Flow] ====Done====
7312 01:24:33.021849
7313 01:24:33.025029 [DutyScan_Calibration_Flow] k_type=1
7314 01:24:33.041512
7315 01:24:33.041594 ==DQS 0 ==
7316 01:24:33.044890 Final DQS duty delay cell = 0
7317 01:24:33.048365 [0] MAX Duty = 5124%(X100), DQS PI = 28
7318 01:24:33.051510 [0] MIN Duty = 4969%(X100), DQS PI = 0
7319 01:24:33.051593 [0] AVG Duty = 5046%(X100)
7320 01:24:33.054965
7321 01:24:33.055046 ==DQS 1 ==
7322 01:24:33.058145 Final DQS duty delay cell = 0
7323 01:24:33.061502 [0] MAX Duty = 5187%(X100), DQS PI = 0
7324 01:24:33.064997 [0] MIN Duty = 4844%(X100), DQS PI = 34
7325 01:24:33.065079 [0] AVG Duty = 5015%(X100)
7326 01:24:33.065144
7327 01:24:33.071497 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7328 01:24:33.071582
7329 01:24:33.075606 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7330 01:24:33.078075 [DutyScan_Calibration_Flow] ====Done====
7331 01:24:33.078157
7332 01:24:33.081306 [DutyScan_Calibration_Flow] k_type=3
7333 01:24:33.099090
7334 01:24:33.099176 ==DQM 0 ==
7335 01:24:33.102507 Final DQM duty delay cell = 4
7336 01:24:33.105687 [4] MAX Duty = 5125%(X100), DQS PI = 8
7337 01:24:33.109024 [4] MIN Duty = 4938%(X100), DQS PI = 48
7338 01:24:33.109111 [4] AVG Duty = 5031%(X100)
7339 01:24:33.112542
7340 01:24:33.112627 ==DQM 1 ==
7341 01:24:33.115584 Final DQM duty delay cell = 0
7342 01:24:33.118953 [0] MAX Duty = 5281%(X100), DQS PI = 58
7343 01:24:33.122515 [0] MIN Duty = 4876%(X100), DQS PI = 34
7344 01:24:33.122639 [0] AVG Duty = 5078%(X100)
7345 01:24:33.125617
7346 01:24:33.129290 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7347 01:24:33.129411
7348 01:24:33.132556 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7349 01:24:33.135866 [DutyScan_Calibration_Flow] ====Done====
7350 01:24:33.135987
7351 01:24:33.138935 [DutyScan_Calibration_Flow] k_type=2
7352 01:24:33.156006
7353 01:24:33.156132 ==DQ 0 ==
7354 01:24:33.159334 Final DQ duty delay cell = 0
7355 01:24:33.162781 [0] MAX Duty = 5093%(X100), DQS PI = 20
7356 01:24:33.166454 [0] MIN Duty = 4969%(X100), DQS PI = 46
7357 01:24:33.166577 [0] AVG Duty = 5031%(X100)
7358 01:24:33.169236
7359 01:24:33.169344 ==DQ 1 ==
7360 01:24:33.172583 Final DQ duty delay cell = 0
7361 01:24:33.175945 [0] MAX Duty = 5062%(X100), DQS PI = 0
7362 01:24:33.179159 [0] MIN Duty = 4844%(X100), DQS PI = 32
7363 01:24:33.179269 [0] AVG Duty = 4953%(X100)
7364 01:24:33.179373
7365 01:24:33.182327 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7366 01:24:33.185662
7367 01:24:33.189205 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7368 01:24:33.192866 [DutyScan_Calibration_Flow] ====Done====
7369 01:24:33.195989 nWR fixed to 30
7370 01:24:33.196076 [ModeRegInit_LP4] CH0 RK0
7371 01:24:33.198984 [ModeRegInit_LP4] CH0 RK1
7372 01:24:33.202196 [ModeRegInit_LP4] CH1 RK0
7373 01:24:33.205490 [ModeRegInit_LP4] CH1 RK1
7374 01:24:33.205576 match AC timing 5
7375 01:24:33.208993 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 01:24:33.215648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 01:24:33.219023 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 01:24:33.222235 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 01:24:33.229003 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 01:24:33.229090 [MiockJmeterHQA]
7381 01:24:33.229177
7382 01:24:33.232234 [DramcMiockJmeter] u1RxGatingPI = 0
7383 01:24:33.235497 0 : 4255, 4026
7384 01:24:33.235584 4 : 4363, 4138
7385 01:24:33.235673 8 : 4252, 4027
7386 01:24:33.238909 12 : 4252, 4027
7387 01:24:33.238997 16 : 4253, 4026
7388 01:24:33.242176 20 : 4252, 4027
7389 01:24:33.242263 24 : 4255, 4029
7390 01:24:33.245520 28 : 4253, 4026
7391 01:24:33.245608 32 : 4252, 4027
7392 01:24:33.248974 36 : 4366, 4140
7393 01:24:33.249061 40 : 4252, 4027
7394 01:24:33.249148 44 : 4255, 4029
7395 01:24:33.252795 48 : 4253, 4027
7396 01:24:33.252883 52 : 4360, 4138
7397 01:24:33.255703 56 : 4252, 4027
7398 01:24:33.255805 60 : 4360, 4138
7399 01:24:33.259022 64 : 4249, 4027
7400 01:24:33.259110 68 : 4250, 4027
7401 01:24:33.259198 72 : 4250, 4027
7402 01:24:33.262120 76 : 4253, 4029
7403 01:24:33.262207 80 : 4250, 4026
7404 01:24:33.265867 84 : 4250, 4027
7405 01:24:33.265954 88 : 4363, 3868
7406 01:24:33.269132 92 : 4253, 1
7407 01:24:33.269220 96 : 4363, 0
7408 01:24:33.269308 100 : 4252, 0
7409 01:24:33.272271 104 : 4250, 0
7410 01:24:33.272358 108 : 4250, 0
7411 01:24:33.276072 112 : 4250, 0
7412 01:24:33.276159 116 : 4252, 0
7413 01:24:33.276247 120 : 4360, 0
7414 01:24:33.279020 124 : 4250, 0
7415 01:24:33.279107 128 : 4250, 0
7416 01:24:33.279196 132 : 4249, 0
7417 01:24:33.282395 136 : 4360, 0
7418 01:24:33.282482 140 : 4360, 0
7419 01:24:33.285615 144 : 4249, 0
7420 01:24:33.285702 148 : 4250, 0
7421 01:24:33.285790 152 : 4250, 0
7422 01:24:33.289286 156 : 4252, 0
7423 01:24:33.289373 160 : 4250, 0
7424 01:24:33.292222 164 : 4250, 0
7425 01:24:33.292309 168 : 4252, 0
7426 01:24:33.292396 172 : 4360, 0
7427 01:24:33.295729 176 : 4250, 0
7428 01:24:33.295816 180 : 4250, 0
7429 01:24:33.295904 184 : 4249, 0
7430 01:24:33.298776 188 : 4361, 0
7431 01:24:33.298864 192 : 4360, 0
7432 01:24:33.302340 196 : 4250, 0
7433 01:24:33.302454 200 : 4250, 1
7434 01:24:33.305388 204 : 4250, 2219
7435 01:24:33.305500 208 : 4361, 4137
7436 01:24:33.305612 212 : 4360, 4138
7437 01:24:33.309310 216 : 4250, 4027
7438 01:24:33.309403 220 : 4363, 4140
7439 01:24:33.312055 224 : 4250, 4027
7440 01:24:33.312158 228 : 4250, 4027
7441 01:24:33.315522 232 : 4249, 4027
7442 01:24:33.315637 236 : 4252, 4029
7443 01:24:33.319131 240 : 4250, 4027
7444 01:24:33.319209 244 : 4250, 4027
7445 01:24:33.322261 248 : 4250, 4027
7446 01:24:33.322348 252 : 4252, 4029
7447 01:24:33.325658 256 : 4250, 4027
7448 01:24:33.325745 260 : 4361, 4137
7449 01:24:33.328877 264 : 4361, 4138
7450 01:24:33.328964 268 : 4250, 4027
7451 01:24:33.329082 272 : 4363, 4140
7452 01:24:33.332328 276 : 4360, 4138
7453 01:24:33.332415 280 : 4250, 4027
7454 01:24:33.335665 284 : 4249, 4027
7455 01:24:33.335753 288 : 4252, 4029
7456 01:24:33.339236 292 : 4250, 4027
7457 01:24:33.339323 296 : 4250, 4026
7458 01:24:33.342192 300 : 4249, 4027
7459 01:24:33.342280 304 : 4252, 4029
7460 01:24:33.345723 308 : 4250, 4027
7461 01:24:33.345811 312 : 4361, 4073
7462 01:24:33.349216 316 : 4360, 2198
7463 01:24:33.349305 320 : 4250, 12
7464 01:24:33.349394
7465 01:24:33.352390 MIOCK jitter meter ch=0
7466 01:24:33.352477
7467 01:24:33.355787 1T = (320-92) = 228 dly cells
7468 01:24:33.358650 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7469 01:24:33.358738 ==
7470 01:24:33.362371 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 01:24:33.368875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 01:24:33.368962 ==
7473 01:24:33.372040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 01:24:33.378630 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 01:24:33.382502 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 01:24:33.389021 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 01:24:33.396303 [CA 0] Center 43 (13~73) winsize 61
7478 01:24:33.399625 [CA 1] Center 43 (13~73) winsize 61
7479 01:24:33.403134 [CA 2] Center 38 (8~68) winsize 61
7480 01:24:33.406269 [CA 3] Center 37 (8~67) winsize 60
7481 01:24:33.409290 [CA 4] Center 36 (6~66) winsize 61
7482 01:24:33.412630 [CA 5] Center 35 (5~65) winsize 61
7483 01:24:33.412717
7484 01:24:33.416152 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 01:24:33.416239
7486 01:24:33.419257 [CATrainingPosCal] consider 1 rank data
7487 01:24:33.422636 u2DelayCellTimex100 = 285/100 ps
7488 01:24:33.425894 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7489 01:24:33.432527 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7490 01:24:33.436025 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7491 01:24:33.439371 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7492 01:24:33.442483 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 01:24:33.446137 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7494 01:24:33.446249
7495 01:24:33.449127 CA PerBit enable=1, Macro0, CA PI delay=35
7496 01:24:33.449213
7497 01:24:33.452637 [CBTSetCACLKResult] CA Dly = 35
7498 01:24:33.455824 CS Dly: 8 (0~39)
7499 01:24:33.459205 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 01:24:33.462696 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 01:24:33.462780 ==
7502 01:24:33.465906 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 01:24:33.469376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 01:24:33.472478 ==
7505 01:24:33.475957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 01:24:33.479148 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 01:24:33.485640 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 01:24:33.489109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 01:24:33.499627 [CA 0] Center 43 (13~74) winsize 62
7510 01:24:33.502817 [CA 1] Center 43 (13~73) winsize 61
7511 01:24:33.506627 [CA 2] Center 38 (9~68) winsize 60
7512 01:24:33.509641 [CA 3] Center 38 (9~68) winsize 60
7513 01:24:33.512919 [CA 4] Center 37 (7~67) winsize 61
7514 01:24:33.516135 [CA 5] Center 36 (7~66) winsize 60
7515 01:24:33.516219
7516 01:24:33.519549 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 01:24:33.519634
7518 01:24:33.522824 [CATrainingPosCal] consider 2 rank data
7519 01:24:33.525837 u2DelayCellTimex100 = 285/100 ps
7520 01:24:33.529460 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7521 01:24:33.536017 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7522 01:24:33.539268 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7523 01:24:33.542898 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7524 01:24:33.546147 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7525 01:24:33.549193 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7526 01:24:33.549282
7527 01:24:33.552736 CA PerBit enable=1, Macro0, CA PI delay=36
7528 01:24:33.552863
7529 01:24:33.555872 [CBTSetCACLKResult] CA Dly = 36
7530 01:24:33.559328 CS Dly: 10 (0~43)
7531 01:24:33.562739 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 01:24:33.565935 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 01:24:33.566050
7534 01:24:33.569256 ----->DramcWriteLeveling(PI) begin...
7535 01:24:33.569354 ==
7536 01:24:33.572745 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 01:24:33.575913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 01:24:33.579225 ==
7539 01:24:33.579323 Write leveling (Byte 0): 36 => 36
7540 01:24:33.583348 Write leveling (Byte 1): 31 => 31
7541 01:24:33.585853 DramcWriteLeveling(PI) end<-----
7542 01:24:33.585935
7543 01:24:33.586001 ==
7544 01:24:33.589343 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 01:24:33.596197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 01:24:33.596306 ==
7547 01:24:33.599806 [Gating] SW mode calibration
7548 01:24:33.605789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 01:24:33.609229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 01:24:33.615713 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 01:24:33.619080 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 01:24:33.622659 1 4 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7553 01:24:33.629131 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7554 01:24:33.632573 1 4 16 | B1->B0 | 2524 3434 | 1 1 | (1 1) (1 1)
7555 01:24:33.635874 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7556 01:24:33.639147 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 01:24:33.645538 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 01:24:33.649081 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 01:24:33.652327 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 01:24:33.658859 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7561 01:24:33.662384 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7562 01:24:33.665694 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7563 01:24:33.672293 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7564 01:24:33.675613 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 01:24:33.679002 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 01:24:33.685515 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 01:24:33.689096 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7568 01:24:33.692308 1 6 8 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7569 01:24:33.700081 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7570 01:24:33.702414 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7571 01:24:33.705791 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7572 01:24:33.712409 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 01:24:33.715321 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 01:24:33.718665 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 01:24:33.725376 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 01:24:33.729101 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 01:24:33.732106 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 01:24:33.738889 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 01:24:33.742225 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 01:24:33.745688 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 01:24:33.752000 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 01:24:33.755511 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 01:24:33.758736 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 01:24:33.761896 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 01:24:33.768992 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 01:24:33.771867 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 01:24:33.775276 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 01:24:33.781767 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 01:24:33.785407 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 01:24:33.788364 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 01:24:33.795401 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 01:24:33.798635 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 01:24:33.801965 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 01:24:33.808370 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7595 01:24:33.811840 Total UI for P1: 0, mck2ui 16
7596 01:24:33.815378 best dqsien dly found for B0: ( 1, 9, 12)
7597 01:24:33.818661 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 01:24:33.821920 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 01:24:33.828222 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 01:24:33.828344 Total UI for P1: 0, mck2ui 16
7601 01:24:33.835236 best dqsien dly found for B1: ( 1, 9, 22)
7602 01:24:33.838422 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7603 01:24:33.841920 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7604 01:24:33.842040
7605 01:24:33.845020 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7606 01:24:33.848300 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7607 01:24:33.851759 [Gating] SW calibration Done
7608 01:24:33.851880 ==
7609 01:24:33.855022 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 01:24:33.858180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 01:24:33.858302 ==
7612 01:24:33.861834 RX Vref Scan: 0
7613 01:24:33.861959
7614 01:24:33.862076 RX Vref 0 -> 0, step: 1
7615 01:24:33.862188
7616 01:24:33.864918 RX Delay 0 -> 252, step: 8
7617 01:24:33.868249 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7618 01:24:33.874901 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7619 01:24:33.878449 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7620 01:24:33.881425 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7621 01:24:33.885047 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7622 01:24:33.888394 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7623 01:24:33.894725 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7624 01:24:33.898470 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7625 01:24:33.901703 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7626 01:24:33.904668 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7627 01:24:33.908229 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7628 01:24:33.914627 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7629 01:24:33.918450 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7630 01:24:33.921635 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7631 01:24:33.924650 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7632 01:24:33.928339 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7633 01:24:33.928423 ==
7634 01:24:33.931245 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 01:24:33.938897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 01:24:33.938982 ==
7637 01:24:33.939049 DQS Delay:
7638 01:24:33.941820 DQS0 = 0, DQS1 = 0
7639 01:24:33.941903 DQM Delay:
7640 01:24:33.944620 DQM0 = 138, DQM1 = 126
7641 01:24:33.944703 DQ Delay:
7642 01:24:33.948019 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7643 01:24:33.951455 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7644 01:24:33.955180 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7645 01:24:33.958098 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7646 01:24:33.958181
7647 01:24:33.958247
7648 01:24:33.958307 ==
7649 01:24:33.961388 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 01:24:33.964827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 01:24:33.968166 ==
7652 01:24:33.968292
7653 01:24:33.968404
7654 01:24:33.968510 TX Vref Scan disable
7655 01:24:33.971580 == TX Byte 0 ==
7656 01:24:33.974637 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7657 01:24:33.978186 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7658 01:24:33.981712 == TX Byte 1 ==
7659 01:24:33.984519 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7660 01:24:33.987820 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7661 01:24:33.991244 ==
7662 01:24:33.994634 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 01:24:33.997845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 01:24:33.997968 ==
7665 01:24:34.010257
7666 01:24:34.013673 TX Vref early break, caculate TX vref
7667 01:24:34.017250 TX Vref=16, minBit 12, minWin=22, winSum=375
7668 01:24:34.020235 TX Vref=18, minBit 6, minWin=23, winSum=384
7669 01:24:34.023590 TX Vref=20, minBit 5, minWin=24, winSum=394
7670 01:24:34.026901 TX Vref=22, minBit 7, minWin=24, winSum=405
7671 01:24:34.030350 TX Vref=24, minBit 4, minWin=25, winSum=415
7672 01:24:34.036902 TX Vref=26, minBit 12, minWin=25, winSum=423
7673 01:24:34.040326 TX Vref=28, minBit 0, minWin=26, winSum=428
7674 01:24:34.043479 TX Vref=30, minBit 0, minWin=26, winSum=424
7675 01:24:34.047015 TX Vref=32, minBit 0, minWin=25, winSum=415
7676 01:24:34.050176 TX Vref=34, minBit 0, minWin=24, winSum=405
7677 01:24:34.056765 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
7678 01:24:34.056864
7679 01:24:34.060455 Final TX Range 0 Vref 28
7680 01:24:34.060539
7681 01:24:34.060606 ==
7682 01:24:34.063674 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 01:24:34.066914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 01:24:34.066998 ==
7685 01:24:34.067066
7686 01:24:34.067129
7687 01:24:34.070377 TX Vref Scan disable
7688 01:24:34.076784 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7689 01:24:34.076883 == TX Byte 0 ==
7690 01:24:34.080627 u2DelayCellOfst[0]=10 cells (3 PI)
7691 01:24:34.083723 u2DelayCellOfst[1]=17 cells (5 PI)
7692 01:24:34.087005 u2DelayCellOfst[2]=10 cells (3 PI)
7693 01:24:34.090407 u2DelayCellOfst[3]=10 cells (3 PI)
7694 01:24:34.093648 u2DelayCellOfst[4]=6 cells (2 PI)
7695 01:24:34.097154 u2DelayCellOfst[5]=0 cells (0 PI)
7696 01:24:34.100302 u2DelayCellOfst[6]=17 cells (5 PI)
7697 01:24:34.103778 u2DelayCellOfst[7]=13 cells (4 PI)
7698 01:24:34.106748 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7699 01:24:34.110215 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7700 01:24:34.113598 == TX Byte 1 ==
7701 01:24:34.113682 u2DelayCellOfst[8]=3 cells (1 PI)
7702 01:24:34.116780 u2DelayCellOfst[9]=0 cells (0 PI)
7703 01:24:34.120327 u2DelayCellOfst[10]=6 cells (2 PI)
7704 01:24:34.123440 u2DelayCellOfst[11]=3 cells (1 PI)
7705 01:24:34.126887 u2DelayCellOfst[12]=10 cells (3 PI)
7706 01:24:34.130171 u2DelayCellOfst[13]=10 cells (3 PI)
7707 01:24:34.133805 u2DelayCellOfst[14]=13 cells (4 PI)
7708 01:24:34.136789 u2DelayCellOfst[15]=10 cells (3 PI)
7709 01:24:34.140044 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7710 01:24:34.146628 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7711 01:24:34.146714 DramC Write-DBI on
7712 01:24:34.146781 ==
7713 01:24:34.150100 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 01:24:34.153374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 01:24:34.157248 ==
7716 01:24:34.157336
7717 01:24:34.157403
7718 01:24:34.157465 TX Vref Scan disable
7719 01:24:34.160296 == TX Byte 0 ==
7720 01:24:34.163422 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7721 01:24:34.166711 == TX Byte 1 ==
7722 01:24:34.170133 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7723 01:24:34.170253 DramC Write-DBI off
7724 01:24:34.173606
7725 01:24:34.173720 [DATLAT]
7726 01:24:34.173814 Freq=1600, CH0 RK0
7727 01:24:34.173900
7728 01:24:34.176647 DATLAT Default: 0xf
7729 01:24:34.176762 0, 0xFFFF, sum = 0
7730 01:24:34.179941 1, 0xFFFF, sum = 0
7731 01:24:34.180064 2, 0xFFFF, sum = 0
7732 01:24:34.183283 3, 0xFFFF, sum = 0
7733 01:24:34.186575 4, 0xFFFF, sum = 0
7734 01:24:34.186691 5, 0xFFFF, sum = 0
7735 01:24:34.189862 6, 0xFFFF, sum = 0
7736 01:24:34.189975 7, 0xFFFF, sum = 0
7737 01:24:34.193094 8, 0xFFFF, sum = 0
7738 01:24:34.193180 9, 0xFFFF, sum = 0
7739 01:24:34.196645 10, 0xFFFF, sum = 0
7740 01:24:34.196730 11, 0xFFFF, sum = 0
7741 01:24:34.199900 12, 0xFFFF, sum = 0
7742 01:24:34.199985 13, 0xFFFF, sum = 0
7743 01:24:34.203327 14, 0x0, sum = 1
7744 01:24:34.203412 15, 0x0, sum = 2
7745 01:24:34.206467 16, 0x0, sum = 3
7746 01:24:34.206552 17, 0x0, sum = 4
7747 01:24:34.209835 best_step = 15
7748 01:24:34.209919
7749 01:24:34.209985 ==
7750 01:24:34.213221 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 01:24:34.216485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 01:24:34.216569 ==
7753 01:24:34.219865 RX Vref Scan: 1
7754 01:24:34.219948
7755 01:24:34.220014 Set Vref Range= 24 -> 127
7756 01:24:34.220075
7757 01:24:34.223124 RX Vref 24 -> 127, step: 1
7758 01:24:34.223207
7759 01:24:34.226502 RX Delay 19 -> 252, step: 4
7760 01:24:34.226599
7761 01:24:34.229716 Set Vref, RX VrefLevel [Byte0]: 24
7762 01:24:34.233441 [Byte1]: 24
7763 01:24:34.233524
7764 01:24:34.236474 Set Vref, RX VrefLevel [Byte0]: 25
7765 01:24:34.239703 [Byte1]: 25
7766 01:24:34.239786
7767 01:24:34.242981 Set Vref, RX VrefLevel [Byte0]: 26
7768 01:24:34.246216 [Byte1]: 26
7769 01:24:34.250650
7770 01:24:34.250733 Set Vref, RX VrefLevel [Byte0]: 27
7771 01:24:34.253851 [Byte1]: 27
7772 01:24:34.257856
7773 01:24:34.257939 Set Vref, RX VrefLevel [Byte0]: 28
7774 01:24:34.261171 [Byte1]: 28
7775 01:24:34.265723
7776 01:24:34.265806 Set Vref, RX VrefLevel [Byte0]: 29
7777 01:24:34.268588 [Byte1]: 29
7778 01:24:34.272914
7779 01:24:34.272997 Set Vref, RX VrefLevel [Byte0]: 30
7780 01:24:34.276408 [Byte1]: 30
7781 01:24:34.280370
7782 01:24:34.280455 Set Vref, RX VrefLevel [Byte0]: 31
7783 01:24:34.284352 [Byte1]: 31
7784 01:24:34.288409
7785 01:24:34.288518 Set Vref, RX VrefLevel [Byte0]: 32
7786 01:24:34.291520 [Byte1]: 32
7787 01:24:34.295717
7788 01:24:34.295815 Set Vref, RX VrefLevel [Byte0]: 33
7789 01:24:34.299162 [Byte1]: 33
7790 01:24:34.303038
7791 01:24:34.303125 Set Vref, RX VrefLevel [Byte0]: 34
7792 01:24:34.306748 [Byte1]: 34
7793 01:24:34.311209
7794 01:24:34.311293 Set Vref, RX VrefLevel [Byte0]: 35
7795 01:24:34.314086 [Byte1]: 35
7796 01:24:34.318470
7797 01:24:34.318555 Set Vref, RX VrefLevel [Byte0]: 36
7798 01:24:34.321705 [Byte1]: 36
7799 01:24:34.326026
7800 01:24:34.326124 Set Vref, RX VrefLevel [Byte0]: 37
7801 01:24:34.329449 [Byte1]: 37
7802 01:24:34.333575
7803 01:24:34.333743 Set Vref, RX VrefLevel [Byte0]: 38
7804 01:24:34.336966 [Byte1]: 38
7805 01:24:34.341278
7806 01:24:34.341365 Set Vref, RX VrefLevel [Byte0]: 39
7807 01:24:34.344631 [Byte1]: 39
7808 01:24:34.348581
7809 01:24:34.348681 Set Vref, RX VrefLevel [Byte0]: 40
7810 01:24:34.351817 [Byte1]: 40
7811 01:24:34.356205
7812 01:24:34.356291 Set Vref, RX VrefLevel [Byte0]: 41
7813 01:24:34.359868 [Byte1]: 41
7814 01:24:34.363915
7815 01:24:34.364032 Set Vref, RX VrefLevel [Byte0]: 42
7816 01:24:34.367746 [Byte1]: 42
7817 01:24:34.371247
7818 01:24:34.371347 Set Vref, RX VrefLevel [Byte0]: 43
7819 01:24:34.374499 [Byte1]: 43
7820 01:24:34.378909
7821 01:24:34.379039 Set Vref, RX VrefLevel [Byte0]: 44
7822 01:24:34.382699 [Byte1]: 44
7823 01:24:34.386527
7824 01:24:34.386651 Set Vref, RX VrefLevel [Byte0]: 45
7825 01:24:34.389987 [Byte1]: 45
7826 01:24:34.394046
7827 01:24:34.394184 Set Vref, RX VrefLevel [Byte0]: 46
7828 01:24:34.397407 [Byte1]: 46
7829 01:24:34.401545
7830 01:24:34.401684 Set Vref, RX VrefLevel [Byte0]: 47
7831 01:24:34.404785 [Byte1]: 47
7832 01:24:34.409417
7833 01:24:34.409502 Set Vref, RX VrefLevel [Byte0]: 48
7834 01:24:34.412671 [Byte1]: 48
7835 01:24:34.416639
7836 01:24:34.416763 Set Vref, RX VrefLevel [Byte0]: 49
7837 01:24:34.419917 [Byte1]: 49
7838 01:24:34.424497
7839 01:24:34.424583 Set Vref, RX VrefLevel [Byte0]: 50
7840 01:24:34.427476 [Byte1]: 50
7841 01:24:34.432128
7842 01:24:34.432265 Set Vref, RX VrefLevel [Byte0]: 51
7843 01:24:34.435575 [Byte1]: 51
7844 01:24:34.440002
7845 01:24:34.440087 Set Vref, RX VrefLevel [Byte0]: 52
7846 01:24:34.442814 [Byte1]: 52
7847 01:24:34.447259
7848 01:24:34.447343 Set Vref, RX VrefLevel [Byte0]: 53
7849 01:24:34.450471 [Byte1]: 53
7850 01:24:34.454655
7851 01:24:34.454789 Set Vref, RX VrefLevel [Byte0]: 54
7852 01:24:34.458121 [Byte1]: 54
7853 01:24:34.462620
7854 01:24:34.462745 Set Vref, RX VrefLevel [Byte0]: 55
7855 01:24:34.465734 [Byte1]: 55
7856 01:24:34.470296
7857 01:24:34.470422 Set Vref, RX VrefLevel [Byte0]: 56
7858 01:24:34.473193 [Byte1]: 56
7859 01:24:34.477648
7860 01:24:34.477789 Set Vref, RX VrefLevel [Byte0]: 57
7861 01:24:34.481062 [Byte1]: 57
7862 01:24:34.484873
7863 01:24:34.485000 Set Vref, RX VrefLevel [Byte0]: 58
7864 01:24:34.488294 [Byte1]: 58
7865 01:24:34.492607
7866 01:24:34.492736 Set Vref, RX VrefLevel [Byte0]: 59
7867 01:24:34.495798 [Byte1]: 59
7868 01:24:34.500368
7869 01:24:34.500477 Set Vref, RX VrefLevel [Byte0]: 60
7870 01:24:34.503556 [Byte1]: 60
7871 01:24:34.507617
7872 01:24:34.507706 Set Vref, RX VrefLevel [Byte0]: 61
7873 01:24:34.511011 [Byte1]: 61
7874 01:24:34.515127
7875 01:24:34.515243 Set Vref, RX VrefLevel [Byte0]: 62
7876 01:24:34.518758 [Byte1]: 62
7877 01:24:34.523362
7878 01:24:34.523464 Set Vref, RX VrefLevel [Byte0]: 63
7879 01:24:34.526200 [Byte1]: 63
7880 01:24:34.530440
7881 01:24:34.530593 Set Vref, RX VrefLevel [Byte0]: 64
7882 01:24:34.533705 [Byte1]: 64
7883 01:24:34.538302
7884 01:24:34.538401 Set Vref, RX VrefLevel [Byte0]: 65
7885 01:24:34.541171 [Byte1]: 65
7886 01:24:34.545628
7887 01:24:34.545734 Set Vref, RX VrefLevel [Byte0]: 66
7888 01:24:34.549012 [Byte1]: 66
7889 01:24:34.553269
7890 01:24:34.553356 Set Vref, RX VrefLevel [Byte0]: 67
7891 01:24:34.556391 [Byte1]: 67
7892 01:24:34.560618
7893 01:24:34.560733 Set Vref, RX VrefLevel [Byte0]: 68
7894 01:24:34.563988 [Byte1]: 68
7895 01:24:34.568470
7896 01:24:34.568557 Set Vref, RX VrefLevel [Byte0]: 69
7897 01:24:34.571619 [Byte1]: 69
7898 01:24:34.575656
7899 01:24:34.579570 Set Vref, RX VrefLevel [Byte0]: 70
7900 01:24:34.579716 [Byte1]: 70
7901 01:24:34.583648
7902 01:24:34.583790 Set Vref, RX VrefLevel [Byte0]: 71
7903 01:24:34.586842 [Byte1]: 71
7904 01:24:34.591041
7905 01:24:34.591182 Set Vref, RX VrefLevel [Byte0]: 72
7906 01:24:34.594426 [Byte1]: 72
7907 01:24:34.598578
7908 01:24:34.598718 Set Vref, RX VrefLevel [Byte0]: 73
7909 01:24:34.602015 [Byte1]: 73
7910 01:24:34.606046
7911 01:24:34.606179 Set Vref, RX VrefLevel [Byte0]: 74
7912 01:24:34.609459 [Byte1]: 74
7913 01:24:34.613521
7914 01:24:34.613639 Set Vref, RX VrefLevel [Byte0]: 75
7915 01:24:34.616869 [Byte1]: 75
7916 01:24:34.622022
7917 01:24:34.622153 Set Vref, RX VrefLevel [Byte0]: 76
7918 01:24:34.624722 [Byte1]: 76
7919 01:24:34.628824
7920 01:24:34.628944 Set Vref, RX VrefLevel [Byte0]: 77
7921 01:24:34.632087 [Byte1]: 77
7922 01:24:34.636283
7923 01:24:34.636372 Set Vref, RX VrefLevel [Byte0]: 78
7924 01:24:34.639697 [Byte1]: 78
7925 01:24:34.644104
7926 01:24:34.644238 Set Vref, RX VrefLevel [Byte0]: 79
7927 01:24:34.647240 [Byte1]: 79
7928 01:24:34.651399
7929 01:24:34.651494 Set Vref, RX VrefLevel [Byte0]: 80
7930 01:24:34.654980 [Byte1]: 80
7931 01:24:34.658928
7932 01:24:34.659017 Final RX Vref Byte 0 = 59 to rank0
7933 01:24:34.662786 Final RX Vref Byte 1 = 62 to rank0
7934 01:24:34.665912 Final RX Vref Byte 0 = 59 to rank1
7935 01:24:34.669017 Final RX Vref Byte 1 = 62 to rank1==
7936 01:24:34.672419 Dram Type= 6, Freq= 0, CH_0, rank 0
7937 01:24:34.679396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7938 01:24:34.679498 ==
7939 01:24:34.679570 DQS Delay:
7940 01:24:34.679634 DQS0 = 0, DQS1 = 0
7941 01:24:34.682581 DQM Delay:
7942 01:24:34.682667 DQM0 = 136, DQM1 = 123
7943 01:24:34.685550 DQ Delay:
7944 01:24:34.689073 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7945 01:24:34.692250 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7946 01:24:34.695819 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7947 01:24:34.698771 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7948 01:24:34.698897
7949 01:24:34.699011
7950 01:24:34.699125
7951 01:24:34.702753 [DramC_TX_OE_Calibration] TA2
7952 01:24:34.705496 Original DQ_B0 (3 6) =30, OEN = 27
7953 01:24:34.708883 Original DQ_B1 (3 6) =30, OEN = 27
7954 01:24:34.712188 24, 0x0, End_B0=24 End_B1=24
7955 01:24:34.712300 25, 0x0, End_B0=25 End_B1=25
7956 01:24:34.715688 26, 0x0, End_B0=26 End_B1=26
7957 01:24:34.718745 27, 0x0, End_B0=27 End_B1=27
7958 01:24:34.722143 28, 0x0, End_B0=28 End_B1=28
7959 01:24:34.725427 29, 0x0, End_B0=29 End_B1=29
7960 01:24:34.725515 30, 0x0, End_B0=30 End_B1=30
7961 01:24:34.728767 31, 0x4545, End_B0=30 End_B1=30
7962 01:24:34.732281 Byte0 end_step=30 best_step=27
7963 01:24:34.735369 Byte1 end_step=30 best_step=27
7964 01:24:34.738725 Byte0 TX OE(2T, 0.5T) = (3, 3)
7965 01:24:34.742287 Byte1 TX OE(2T, 0.5T) = (3, 3)
7966 01:24:34.742420
7967 01:24:34.742536
7968 01:24:34.748629 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7969 01:24:34.752103 CH0 RK0: MR19=303, MR18=1E1C
7970 01:24:34.758595 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7971 01:24:34.758686
7972 01:24:34.762205 ----->DramcWriteLeveling(PI) begin...
7973 01:24:34.762294 ==
7974 01:24:34.765546 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 01:24:34.768891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 01:24:34.768977 ==
7977 01:24:34.772376 Write leveling (Byte 0): 38 => 38
7978 01:24:34.775614 Write leveling (Byte 1): 30 => 30
7979 01:24:34.778793 DramcWriteLeveling(PI) end<-----
7980 01:24:34.778922
7981 01:24:34.779038 ==
7982 01:24:34.782559 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 01:24:34.785281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 01:24:34.785408 ==
7985 01:24:34.789703 [Gating] SW mode calibration
7986 01:24:34.795446 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7987 01:24:34.802039 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7988 01:24:34.805433 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 01:24:34.808403 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 01:24:34.815463 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7991 01:24:34.818531 1 4 12 | B1->B0 | 2524 3232 | 1 1 | (1 1) (1 1)
7992 01:24:34.821765 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7993 01:24:34.828630 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 01:24:34.832086 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 01:24:34.835290 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 01:24:34.841830 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 01:24:34.845074 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 01:24:34.848338 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7999 01:24:34.855352 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
8000 01:24:34.858610 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8001 01:24:34.861907 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 01:24:34.868346 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 01:24:34.871679 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 01:24:34.874898 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 01:24:34.881521 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 01:24:34.885098 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
8007 01:24:34.888261 1 6 12 | B1->B0 | 2b2b 4444 | 1 0 | (1 1) (0 0)
8008 01:24:34.895310 1 6 16 | B1->B0 | 4544 4646 | 1 0 | (0 0) (0 0)
8009 01:24:34.898530 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 01:24:34.901787 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 01:24:34.905584 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 01:24:34.911650 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 01:24:34.915330 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 01:24:34.918294 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 01:24:34.925116 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8016 01:24:34.928396 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8017 01:24:34.931527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 01:24:34.938579 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 01:24:34.941798 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 01:24:34.945018 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 01:24:34.951686 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 01:24:34.954952 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 01:24:34.958159 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 01:24:34.964873 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 01:24:34.968241 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 01:24:34.971691 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 01:24:34.978479 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 01:24:34.981662 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 01:24:34.985081 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 01:24:34.991750 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 01:24:34.994871 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8032 01:24:34.998578 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8033 01:24:35.001571 Total UI for P1: 0, mck2ui 16
8034 01:24:35.004880 best dqsien dly found for B0: ( 1, 9, 12)
8035 01:24:35.011499 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 01:24:35.011610 Total UI for P1: 0, mck2ui 16
8037 01:24:35.014780 best dqsien dly found for B1: ( 1, 9, 14)
8038 01:24:35.021765 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8039 01:24:35.024650 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8040 01:24:35.024737
8041 01:24:35.027943 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8042 01:24:35.031337 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8043 01:24:35.034832 [Gating] SW calibration Done
8044 01:24:35.034919 ==
8045 01:24:35.037778 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 01:24:35.041912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 01:24:35.042000 ==
8048 01:24:35.044565 RX Vref Scan: 0
8049 01:24:35.044651
8050 01:24:35.044719 RX Vref 0 -> 0, step: 1
8051 01:24:35.044794
8052 01:24:35.047864 RX Delay 0 -> 252, step: 8
8053 01:24:35.051082 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8054 01:24:35.057988 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8055 01:24:35.061384 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8056 01:24:35.064649 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8057 01:24:35.068318 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8058 01:24:35.071021 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8059 01:24:35.077932 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8060 01:24:35.081180 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8061 01:24:35.084320 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8062 01:24:35.087679 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8063 01:24:35.091347 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8064 01:24:35.097652 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8065 01:24:35.100951 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8066 01:24:35.104615 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8067 01:24:35.107867 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8068 01:24:35.111406 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8069 01:24:35.111540 ==
8070 01:24:35.114407 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 01:24:35.121444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 01:24:35.121570 ==
8073 01:24:35.121686 DQS Delay:
8074 01:24:35.124739 DQS0 = 0, DQS1 = 0
8075 01:24:35.124878 DQM Delay:
8076 01:24:35.127578 DQM0 = 136, DQM1 = 125
8077 01:24:35.127709 DQ Delay:
8078 01:24:35.131003 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8079 01:24:35.134330 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8080 01:24:35.137515 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8081 01:24:35.140796 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8082 01:24:35.140948
8083 01:24:35.141076
8084 01:24:35.141182 ==
8085 01:24:35.144098 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 01:24:35.150560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 01:24:35.150703 ==
8088 01:24:35.150814
8089 01:24:35.150951
8090 01:24:35.151072 TX Vref Scan disable
8091 01:24:35.154029 == TX Byte 0 ==
8092 01:24:35.157898 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8093 01:24:35.164232 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8094 01:24:35.164336 == TX Byte 1 ==
8095 01:24:35.167486 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8096 01:24:35.170795 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8097 01:24:35.174292 ==
8098 01:24:35.178156 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 01:24:35.180765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 01:24:35.180880 ==
8101 01:24:35.195853
8102 01:24:35.198768 TX Vref early break, caculate TX vref
8103 01:24:35.201870 TX Vref=16, minBit 0, minWin=23, winSum=388
8104 01:24:35.205324 TX Vref=18, minBit 0, minWin=23, winSum=402
8105 01:24:35.208630 TX Vref=20, minBit 0, minWin=24, winSum=409
8106 01:24:35.211614 TX Vref=22, minBit 0, minWin=25, winSum=416
8107 01:24:35.215160 TX Vref=24, minBit 0, minWin=26, winSum=427
8108 01:24:35.221522 TX Vref=26, minBit 0, minWin=26, winSum=430
8109 01:24:35.225104 TX Vref=28, minBit 0, minWin=26, winSum=432
8110 01:24:35.228346 TX Vref=30, minBit 0, minWin=26, winSum=430
8111 01:24:35.231452 TX Vref=32, minBit 2, minWin=25, winSum=419
8112 01:24:35.234834 TX Vref=34, minBit 3, minWin=24, winSum=410
8113 01:24:35.238641 TX Vref=36, minBit 2, minWin=24, winSum=405
8114 01:24:35.244991 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8115 01:24:35.245163
8116 01:24:35.248265 Final TX Range 0 Vref 28
8117 01:24:35.248396
8118 01:24:35.248506 ==
8119 01:24:35.251918 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 01:24:35.254797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 01:24:35.254889 ==
8122 01:24:35.254977
8123 01:24:35.255061
8124 01:24:35.258307 TX Vref Scan disable
8125 01:24:35.264896 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8126 01:24:35.265030 == TX Byte 0 ==
8127 01:24:35.267964 u2DelayCellOfst[0]=13 cells (4 PI)
8128 01:24:35.271415 u2DelayCellOfst[1]=20 cells (6 PI)
8129 01:24:35.274694 u2DelayCellOfst[2]=13 cells (4 PI)
8130 01:24:35.278259 u2DelayCellOfst[3]=13 cells (4 PI)
8131 01:24:35.282015 u2DelayCellOfst[4]=10 cells (3 PI)
8132 01:24:35.284704 u2DelayCellOfst[5]=0 cells (0 PI)
8133 01:24:35.288185 u2DelayCellOfst[6]=20 cells (6 PI)
8134 01:24:35.291241 u2DelayCellOfst[7]=20 cells (6 PI)
8135 01:24:35.294744 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8136 01:24:35.297855 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8137 01:24:35.301302 == TX Byte 1 ==
8138 01:24:35.304896 u2DelayCellOfst[8]=3 cells (1 PI)
8139 01:24:35.308071 u2DelayCellOfst[9]=0 cells (0 PI)
8140 01:24:35.311573 u2DelayCellOfst[10]=6 cells (2 PI)
8141 01:24:35.311661 u2DelayCellOfst[11]=3 cells (1 PI)
8142 01:24:35.314480 u2DelayCellOfst[12]=13 cells (4 PI)
8143 01:24:35.317811 u2DelayCellOfst[13]=13 cells (4 PI)
8144 01:24:35.321106 u2DelayCellOfst[14]=13 cells (4 PI)
8145 01:24:35.324624 u2DelayCellOfst[15]=10 cells (3 PI)
8146 01:24:35.331022 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8147 01:24:35.334601 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8148 01:24:35.334691 DramC Write-DBI on
8149 01:24:35.334761 ==
8150 01:24:35.337670 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 01:24:35.344695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 01:24:35.344799 ==
8153 01:24:35.344871
8154 01:24:35.344937
8155 01:24:35.344998 TX Vref Scan disable
8156 01:24:35.348873 == TX Byte 0 ==
8157 01:24:35.352360 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8158 01:24:35.355151 == TX Byte 1 ==
8159 01:24:35.358873 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8160 01:24:35.361804 DramC Write-DBI off
8161 01:24:35.361899
8162 01:24:35.361969 [DATLAT]
8163 01:24:35.362035 Freq=1600, CH0 RK1
8164 01:24:35.362101
8165 01:24:35.365280 DATLAT Default: 0xf
8166 01:24:35.365392 0, 0xFFFF, sum = 0
8167 01:24:35.368625 1, 0xFFFF, sum = 0
8168 01:24:35.368712 2, 0xFFFF, sum = 0
8169 01:24:35.371891 3, 0xFFFF, sum = 0
8170 01:24:35.375557 4, 0xFFFF, sum = 0
8171 01:24:35.375647 5, 0xFFFF, sum = 0
8172 01:24:35.378540 6, 0xFFFF, sum = 0
8173 01:24:35.378630 7, 0xFFFF, sum = 0
8174 01:24:35.381901 8, 0xFFFF, sum = 0
8175 01:24:35.381990 9, 0xFFFF, sum = 0
8176 01:24:35.385186 10, 0xFFFF, sum = 0
8177 01:24:35.385316 11, 0xFFFF, sum = 0
8178 01:24:35.388439 12, 0xFFFF, sum = 0
8179 01:24:35.388569 13, 0xFFFF, sum = 0
8180 01:24:35.391768 14, 0x0, sum = 1
8181 01:24:35.391901 15, 0x0, sum = 2
8182 01:24:35.395070 16, 0x0, sum = 3
8183 01:24:35.395198 17, 0x0, sum = 4
8184 01:24:35.398894 best_step = 15
8185 01:24:35.398983
8186 01:24:35.399053 ==
8187 01:24:35.401631 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 01:24:35.405052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 01:24:35.405166 ==
8190 01:24:35.408749 RX Vref Scan: 0
8191 01:24:35.408840
8192 01:24:35.408907 RX Vref 0 -> 0, step: 1
8193 01:24:35.408971
8194 01:24:35.411787 RX Delay 11 -> 252, step: 4
8195 01:24:35.415076 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8196 01:24:35.421754 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8197 01:24:35.425339 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8198 01:24:35.428602 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8199 01:24:35.432082 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8200 01:24:35.435155 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8201 01:24:35.441956 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8202 01:24:35.444881 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8203 01:24:35.448846 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8204 01:24:35.451764 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8205 01:24:35.455274 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8206 01:24:35.461762 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8207 01:24:35.465470 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8208 01:24:35.468448 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8209 01:24:35.471806 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8210 01:24:35.474908 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8211 01:24:35.474989 ==
8212 01:24:35.478782 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 01:24:35.485225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 01:24:35.485310 ==
8215 01:24:35.485384 DQS Delay:
8216 01:24:35.488541 DQS0 = 0, DQS1 = 0
8217 01:24:35.488648 DQM Delay:
8218 01:24:35.491628 DQM0 = 132, DQM1 = 123
8219 01:24:35.491736 DQ Delay:
8220 01:24:35.495002 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8221 01:24:35.498390 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8222 01:24:35.501694 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8223 01:24:35.504952 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8224 01:24:35.505038
8225 01:24:35.505106
8226 01:24:35.505168
8227 01:24:35.508504 [DramC_TX_OE_Calibration] TA2
8228 01:24:35.511869 Original DQ_B0 (3 6) =30, OEN = 27
8229 01:24:35.514936 Original DQ_B1 (3 6) =30, OEN = 27
8230 01:24:35.518433 24, 0x0, End_B0=24 End_B1=24
8231 01:24:35.521641 25, 0x0, End_B0=25 End_B1=25
8232 01:24:35.521725 26, 0x0, End_B0=26 End_B1=26
8233 01:24:35.525035 27, 0x0, End_B0=27 End_B1=27
8234 01:24:35.528461 28, 0x0, End_B0=28 End_B1=28
8235 01:24:35.531825 29, 0x0, End_B0=29 End_B1=29
8236 01:24:35.531915 30, 0x0, End_B0=30 End_B1=30
8237 01:24:35.535070 31, 0x4545, End_B0=30 End_B1=30
8238 01:24:35.538303 Byte0 end_step=30 best_step=27
8239 01:24:35.541860 Byte1 end_step=30 best_step=27
8240 01:24:35.545118 Byte0 TX OE(2T, 0.5T) = (3, 3)
8241 01:24:35.548092 Byte1 TX OE(2T, 0.5T) = (3, 3)
8242 01:24:35.548215
8243 01:24:35.548328
8244 01:24:35.555080 [DQSOSCAuto] RK1, (LSB)MR18= 0x200c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8245 01:24:35.558105 CH0 RK1: MR19=303, MR18=200C
8246 01:24:35.564709 CH0_RK1: MR19=0x303, MR18=0x200C, DQSOSC=393, MR23=63, INC=23, DEC=15
8247 01:24:35.568121 [RxdqsGatingPostProcess] freq 1600
8248 01:24:35.571264 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8249 01:24:35.574826 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 01:24:35.578288 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 01:24:35.581677 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 01:24:35.584565 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 01:24:35.588054 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 01:24:35.591517 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 01:24:35.594729 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 01:24:35.598049 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 01:24:35.601249 Pre-setting of DQS Precalculation
8258 01:24:35.604653 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8259 01:24:35.604763 ==
8260 01:24:35.607960 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 01:24:35.611312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 01:24:35.615029 ==
8263 01:24:35.617687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 01:24:35.621554 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 01:24:35.627941 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 01:24:35.631664 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 01:24:35.641808 [CA 0] Center 41 (12~71) winsize 60
8268 01:24:35.645346 [CA 1] Center 42 (12~72) winsize 61
8269 01:24:35.648191 [CA 2] Center 38 (9~67) winsize 59
8270 01:24:35.651732 [CA 3] Center 36 (7~66) winsize 60
8271 01:24:35.654813 [CA 4] Center 37 (7~68) winsize 62
8272 01:24:35.658240 [CA 5] Center 37 (7~67) winsize 61
8273 01:24:35.658375
8274 01:24:35.661547 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8275 01:24:35.661676
8276 01:24:35.664742 [CATrainingPosCal] consider 1 rank data
8277 01:24:35.668539 u2DelayCellTimex100 = 285/100 ps
8278 01:24:35.671871 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8279 01:24:35.678662 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8280 01:24:35.681495 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8281 01:24:35.684960 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8282 01:24:35.688265 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8283 01:24:35.691446 CA5 delay=37 (7~67),Diff = 1 PI (3 cell)
8284 01:24:35.691555
8285 01:24:35.695374 CA PerBit enable=1, Macro0, CA PI delay=36
8286 01:24:35.695487
8287 01:24:35.698227 [CBTSetCACLKResult] CA Dly = 36
8288 01:24:35.698337 CS Dly: 9 (0~40)
8289 01:24:35.705366 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 01:24:35.708427 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 01:24:35.708538 ==
8292 01:24:35.711522 Dram Type= 6, Freq= 0, CH_1, rank 1
8293 01:24:35.714960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 01:24:35.715071 ==
8295 01:24:35.721842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 01:24:35.725001 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 01:24:35.731423 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 01:24:35.734680 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 01:24:35.744523 [CA 0] Center 41 (12~71) winsize 60
8300 01:24:35.748009 [CA 1] Center 41 (12~71) winsize 60
8301 01:24:35.751643 [CA 2] Center 38 (9~68) winsize 60
8302 01:24:35.754676 [CA 3] Center 37 (8~67) winsize 60
8303 01:24:35.757904 [CA 4] Center 37 (8~67) winsize 60
8304 01:24:35.761378 [CA 5] Center 37 (7~67) winsize 61
8305 01:24:35.761486
8306 01:24:35.764472 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 01:24:35.764563
8308 01:24:35.768107 [CATrainingPosCal] consider 2 rank data
8309 01:24:35.771182 u2DelayCellTimex100 = 285/100 ps
8310 01:24:35.774705 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8311 01:24:35.781271 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8312 01:24:35.784425 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8313 01:24:35.787739 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8314 01:24:35.791260 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 01:24:35.794598 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8316 01:24:35.794706
8317 01:24:35.797673 CA PerBit enable=1, Macro0, CA PI delay=37
8318 01:24:35.797780
8319 01:24:35.800941 [CBTSetCACLKResult] CA Dly = 37
8320 01:24:35.804411 CS Dly: 10 (0~42)
8321 01:24:35.807555 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 01:24:35.810943 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 01:24:35.811051
8324 01:24:35.814496 ----->DramcWriteLeveling(PI) begin...
8325 01:24:35.814605 ==
8326 01:24:35.817579 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 01:24:35.824182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 01:24:35.824307 ==
8329 01:24:35.827391 Write leveling (Byte 0): 23 => 23
8330 01:24:35.827498 Write leveling (Byte 1): 28 => 28
8331 01:24:35.830819 DramcWriteLeveling(PI) end<-----
8332 01:24:35.830933
8333 01:24:35.834139 ==
8334 01:24:35.834259 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 01:24:35.840915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 01:24:35.841024 ==
8337 01:24:35.843981 [Gating] SW mode calibration
8338 01:24:35.850697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8339 01:24:35.854005 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8340 01:24:35.860867 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 01:24:35.863933 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 01:24:35.867307 1 4 8 | B1->B0 | 2b2b 2e2d | 1 1 | (1 1) (1 1)
8343 01:24:35.874077 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 01:24:35.877220 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 01:24:35.880654 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 01:24:35.887433 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 01:24:35.890671 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 01:24:35.894041 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 01:24:35.900624 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8350 01:24:35.904014 1 5 8 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (1 0)
8351 01:24:35.907237 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8352 01:24:35.910592 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8353 01:24:35.917437 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 01:24:35.920620 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 01:24:35.924114 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 01:24:35.930733 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 01:24:35.934037 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 01:24:35.937044 1 6 8 | B1->B0 | 3d3d 4545 | 1 0 | (0 0) (0 0)
8359 01:24:35.943683 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 01:24:35.947315 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 01:24:35.950324 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 01:24:35.957136 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 01:24:35.960224 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 01:24:35.963749 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 01:24:35.970349 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 01:24:35.973674 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8367 01:24:35.977006 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8368 01:24:35.983606 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 01:24:35.987344 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 01:24:35.990632 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 01:24:35.997119 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 01:24:36.000699 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 01:24:36.003603 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 01:24:36.010656 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 01:24:36.013572 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 01:24:36.016970 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 01:24:36.020244 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 01:24:36.026938 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 01:24:36.030095 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 01:24:36.033637 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 01:24:36.040154 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8382 01:24:36.043766 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8383 01:24:36.047008 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8384 01:24:36.053496 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 01:24:36.056952 Total UI for P1: 0, mck2ui 16
8386 01:24:36.060094 best dqsien dly found for B0: ( 1, 9, 8)
8387 01:24:36.063451 Total UI for P1: 0, mck2ui 16
8388 01:24:36.066868 best dqsien dly found for B1: ( 1, 9, 10)
8389 01:24:36.070070 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8390 01:24:36.073551 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8391 01:24:36.073668
8392 01:24:36.076864 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8393 01:24:36.080353 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8394 01:24:36.083481 [Gating] SW calibration Done
8395 01:24:36.083594 ==
8396 01:24:36.086706 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 01:24:36.090162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 01:24:36.090277 ==
8399 01:24:36.093633 RX Vref Scan: 0
8400 01:24:36.093745
8401 01:24:36.093847 RX Vref 0 -> 0, step: 1
8402 01:24:36.093946
8403 01:24:36.096847 RX Delay 0 -> 252, step: 8
8404 01:24:36.100125 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8405 01:24:36.107151 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8406 01:24:36.110207 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8407 01:24:36.113565 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8408 01:24:36.116661 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8409 01:24:36.120099 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8410 01:24:36.126677 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8411 01:24:36.130104 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8412 01:24:36.133583 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8413 01:24:36.136556 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8414 01:24:36.140144 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8415 01:24:36.147122 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8416 01:24:36.150009 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8417 01:24:36.153329 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8418 01:24:36.156632 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8419 01:24:36.160102 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8420 01:24:36.160192 ==
8421 01:24:36.163396 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 01:24:36.170158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 01:24:36.170275 ==
8424 01:24:36.170373 DQS Delay:
8425 01:24:36.173363 DQS0 = 0, DQS1 = 0
8426 01:24:36.173455 DQM Delay:
8427 01:24:36.176664 DQM0 = 136, DQM1 = 130
8428 01:24:36.176787 DQ Delay:
8429 01:24:36.179934 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8430 01:24:36.183277 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8431 01:24:36.186631 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8432 01:24:36.190153 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8433 01:24:36.190242
8434 01:24:36.190310
8435 01:24:36.190373 ==
8436 01:24:36.193812 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 01:24:36.200062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 01:24:36.200157 ==
8439 01:24:36.200227
8440 01:24:36.200290
8441 01:24:36.200351 TX Vref Scan disable
8442 01:24:36.203339 == TX Byte 0 ==
8443 01:24:36.206534 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8444 01:24:36.209827 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8445 01:24:36.213341 == TX Byte 1 ==
8446 01:24:36.216640 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8447 01:24:36.219945 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 01:24:36.223114 ==
8449 01:24:36.226584 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 01:24:36.229576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 01:24:36.229700 ==
8452 01:24:36.241906
8453 01:24:36.246121 TX Vref early break, caculate TX vref
8454 01:24:36.248816 TX Vref=16, minBit 8, minWin=21, winSum=363
8455 01:24:36.252109 TX Vref=18, minBit 10, minWin=22, winSum=375
8456 01:24:36.255368 TX Vref=20, minBit 10, minWin=23, winSum=386
8457 01:24:36.258716 TX Vref=22, minBit 10, minWin=22, winSum=396
8458 01:24:36.262580 TX Vref=24, minBit 10, minWin=24, winSum=407
8459 01:24:36.268590 TX Vref=26, minBit 1, minWin=25, winSum=415
8460 01:24:36.271925 TX Vref=28, minBit 10, minWin=25, winSum=421
8461 01:24:36.275500 TX Vref=30, minBit 14, minWin=24, winSum=415
8462 01:24:36.278835 TX Vref=32, minBit 8, minWin=24, winSum=405
8463 01:24:36.281877 TX Vref=34, minBit 12, minWin=23, winSum=396
8464 01:24:36.288761 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 28
8465 01:24:36.288906
8466 01:24:36.291833 Final TX Range 0 Vref 28
8467 01:24:36.291959
8468 01:24:36.292075 ==
8469 01:24:36.295222 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 01:24:36.298685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 01:24:36.298811 ==
8472 01:24:36.298928
8473 01:24:36.299040
8474 01:24:36.302014 TX Vref Scan disable
8475 01:24:36.308599 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8476 01:24:36.308731 == TX Byte 0 ==
8477 01:24:36.311964 u2DelayCellOfst[0]=17 cells (5 PI)
8478 01:24:36.315400 u2DelayCellOfst[1]=10 cells (3 PI)
8479 01:24:36.319071 u2DelayCellOfst[2]=0 cells (0 PI)
8480 01:24:36.321746 u2DelayCellOfst[3]=6 cells (2 PI)
8481 01:24:36.325407 u2DelayCellOfst[4]=6 cells (2 PI)
8482 01:24:36.328877 u2DelayCellOfst[5]=17 cells (5 PI)
8483 01:24:36.331829 u2DelayCellOfst[6]=17 cells (5 PI)
8484 01:24:36.335876 u2DelayCellOfst[7]=6 cells (2 PI)
8485 01:24:36.338449 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8486 01:24:36.341874 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8487 01:24:36.345087 == TX Byte 1 ==
8488 01:24:36.348492 u2DelayCellOfst[8]=0 cells (0 PI)
8489 01:24:36.348579 u2DelayCellOfst[9]=6 cells (2 PI)
8490 01:24:36.351720 u2DelayCellOfst[10]=13 cells (4 PI)
8491 01:24:36.355337 u2DelayCellOfst[11]=6 cells (2 PI)
8492 01:24:36.358501 u2DelayCellOfst[12]=17 cells (5 PI)
8493 01:24:36.361918 u2DelayCellOfst[13]=20 cells (6 PI)
8494 01:24:36.365045 u2DelayCellOfst[14]=20 cells (6 PI)
8495 01:24:36.368276 u2DelayCellOfst[15]=20 cells (6 PI)
8496 01:24:36.371668 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8497 01:24:36.378122 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8498 01:24:36.378257 DramC Write-DBI on
8499 01:24:36.378378 ==
8500 01:24:36.381661 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 01:24:36.388266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 01:24:36.388396 ==
8503 01:24:36.388510
8504 01:24:36.388621
8505 01:24:36.388730 TX Vref Scan disable
8506 01:24:36.391882 == TX Byte 0 ==
8507 01:24:36.395321 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8508 01:24:36.399085 == TX Byte 1 ==
8509 01:24:36.402375 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8510 01:24:36.405290 DramC Write-DBI off
8511 01:24:36.405415
8512 01:24:36.405532 [DATLAT]
8513 01:24:36.405643 Freq=1600, CH1 RK0
8514 01:24:36.405752
8515 01:24:36.408824 DATLAT Default: 0xf
8516 01:24:36.408963 0, 0xFFFF, sum = 0
8517 01:24:36.411885 1, 0xFFFF, sum = 0
8518 01:24:36.414990 2, 0xFFFF, sum = 0
8519 01:24:36.415115 3, 0xFFFF, sum = 0
8520 01:24:36.418497 4, 0xFFFF, sum = 0
8521 01:24:36.418621 5, 0xFFFF, sum = 0
8522 01:24:36.422096 6, 0xFFFF, sum = 0
8523 01:24:36.422222 7, 0xFFFF, sum = 0
8524 01:24:36.425187 8, 0xFFFF, sum = 0
8525 01:24:36.425350 9, 0xFFFF, sum = 0
8526 01:24:36.428518 10, 0xFFFF, sum = 0
8527 01:24:36.428648 11, 0xFFFF, sum = 0
8528 01:24:36.431933 12, 0xFFFF, sum = 0
8529 01:24:36.432055 13, 0xFFFF, sum = 0
8530 01:24:36.435010 14, 0x0, sum = 1
8531 01:24:36.435111 15, 0x0, sum = 2
8532 01:24:36.438508 16, 0x0, sum = 3
8533 01:24:36.438606 17, 0x0, sum = 4
8534 01:24:36.442029 best_step = 15
8535 01:24:36.442130
8536 01:24:36.442200 ==
8537 01:24:36.445282 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 01:24:36.448518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 01:24:36.448604 ==
8540 01:24:36.448672 RX Vref Scan: 1
8541 01:24:36.451945
8542 01:24:36.452034 Set Vref Range= 24 -> 127
8543 01:24:36.452104
8544 01:24:36.455692 RX Vref 24 -> 127, step: 1
8545 01:24:36.455815
8546 01:24:36.458788 RX Delay 19 -> 252, step: 4
8547 01:24:36.458873
8548 01:24:36.461989 Set Vref, RX VrefLevel [Byte0]: 24
8549 01:24:36.465104 [Byte1]: 24
8550 01:24:36.465191
8551 01:24:36.468685 Set Vref, RX VrefLevel [Byte0]: 25
8552 01:24:36.472326 [Byte1]: 25
8553 01:24:36.472413
8554 01:24:36.475261 Set Vref, RX VrefLevel [Byte0]: 26
8555 01:24:36.478618 [Byte1]: 26
8556 01:24:36.482322
8557 01:24:36.482477 Set Vref, RX VrefLevel [Byte0]: 27
8558 01:24:36.485626 [Byte1]: 27
8559 01:24:36.490057
8560 01:24:36.490177 Set Vref, RX VrefLevel [Byte0]: 28
8561 01:24:36.493157 [Byte1]: 28
8562 01:24:36.497471
8563 01:24:36.497557 Set Vref, RX VrefLevel [Byte0]: 29
8564 01:24:36.501056 [Byte1]: 29
8565 01:24:36.504949
8566 01:24:36.505035 Set Vref, RX VrefLevel [Byte0]: 30
8567 01:24:36.508614 [Byte1]: 30
8568 01:24:36.512525
8569 01:24:36.512617 Set Vref, RX VrefLevel [Byte0]: 31
8570 01:24:36.515830 [Byte1]: 31
8571 01:24:36.520265
8572 01:24:36.520393 Set Vref, RX VrefLevel [Byte0]: 32
8573 01:24:36.523523 [Byte1]: 32
8574 01:24:36.527656
8575 01:24:36.527782 Set Vref, RX VrefLevel [Byte0]: 33
8576 01:24:36.531001 [Byte1]: 33
8577 01:24:36.535429
8578 01:24:36.535555 Set Vref, RX VrefLevel [Byte0]: 34
8579 01:24:36.538589 [Byte1]: 34
8580 01:24:36.542701
8581 01:24:36.542817 Set Vref, RX VrefLevel [Byte0]: 35
8582 01:24:36.546055 [Byte1]: 35
8583 01:24:36.550506
8584 01:24:36.550595 Set Vref, RX VrefLevel [Byte0]: 36
8585 01:24:36.553661 [Byte1]: 36
8586 01:24:36.558441
8587 01:24:36.558530 Set Vref, RX VrefLevel [Byte0]: 37
8588 01:24:36.561600 [Byte1]: 37
8589 01:24:36.565921
8590 01:24:36.566014 Set Vref, RX VrefLevel [Byte0]: 38
8591 01:24:36.569063 [Byte1]: 38
8592 01:24:36.573220
8593 01:24:36.573347 Set Vref, RX VrefLevel [Byte0]: 39
8594 01:24:36.576586 [Byte1]: 39
8595 01:24:36.580658
8596 01:24:36.580778 Set Vref, RX VrefLevel [Byte0]: 40
8597 01:24:36.584176 [Byte1]: 40
8598 01:24:36.588319
8599 01:24:36.588407 Set Vref, RX VrefLevel [Byte0]: 41
8600 01:24:36.591697 [Byte1]: 41
8601 01:24:36.595980
8602 01:24:36.596068 Set Vref, RX VrefLevel [Byte0]: 42
8603 01:24:36.599233 [Byte1]: 42
8604 01:24:36.603499
8605 01:24:36.603587 Set Vref, RX VrefLevel [Byte0]: 43
8606 01:24:36.607329 [Byte1]: 43
8607 01:24:36.611046
8608 01:24:36.611161 Set Vref, RX VrefLevel [Byte0]: 44
8609 01:24:36.614262 [Byte1]: 44
8610 01:24:36.618580
8611 01:24:36.618696 Set Vref, RX VrefLevel [Byte0]: 45
8612 01:24:36.621997 [Byte1]: 45
8613 01:24:36.626102
8614 01:24:36.626194 Set Vref, RX VrefLevel [Byte0]: 46
8615 01:24:36.629416 [Byte1]: 46
8616 01:24:36.633951
8617 01:24:36.634041 Set Vref, RX VrefLevel [Byte0]: 47
8618 01:24:36.637422 [Byte1]: 47
8619 01:24:36.641393
8620 01:24:36.641481 Set Vref, RX VrefLevel [Byte0]: 48
8621 01:24:36.644545 [Byte1]: 48
8622 01:24:36.649749
8623 01:24:36.649839 Set Vref, RX VrefLevel [Byte0]: 49
8624 01:24:36.652244 [Byte1]: 49
8625 01:24:36.656383
8626 01:24:36.656505 Set Vref, RX VrefLevel [Byte0]: 50
8627 01:24:36.659838 [Byte1]: 50
8628 01:24:36.664265
8629 01:24:36.664354 Set Vref, RX VrefLevel [Byte0]: 51
8630 01:24:36.667632 [Byte1]: 51
8631 01:24:36.672071
8632 01:24:36.672159 Set Vref, RX VrefLevel [Byte0]: 52
8633 01:24:36.676876 [Byte1]: 52
8634 01:24:36.679271
8635 01:24:36.679398 Set Vref, RX VrefLevel [Byte0]: 53
8636 01:24:36.682603 [Byte1]: 53
8637 01:24:36.686692
8638 01:24:36.686820 Set Vref, RX VrefLevel [Byte0]: 54
8639 01:24:36.689855 [Byte1]: 54
8640 01:24:36.694161
8641 01:24:36.694289 Set Vref, RX VrefLevel [Byte0]: 55
8642 01:24:36.697782 [Byte1]: 55
8643 01:24:36.701756
8644 01:24:36.701883 Set Vref, RX VrefLevel [Byte0]: 56
8645 01:24:36.705092 [Byte1]: 56
8646 01:24:36.709454
8647 01:24:36.709585 Set Vref, RX VrefLevel [Byte0]: 57
8648 01:24:36.712733 [Byte1]: 57
8649 01:24:36.716980
8650 01:24:36.717107 Set Vref, RX VrefLevel [Byte0]: 58
8651 01:24:36.721002 [Byte1]: 58
8652 01:24:36.724757
8653 01:24:36.724885 Set Vref, RX VrefLevel [Byte0]: 59
8654 01:24:36.728074 [Byte1]: 59
8655 01:24:36.732068
8656 01:24:36.732197 Set Vref, RX VrefLevel [Byte0]: 60
8657 01:24:36.735610 [Byte1]: 60
8658 01:24:36.739951
8659 01:24:36.740077 Set Vref, RX VrefLevel [Byte0]: 61
8660 01:24:36.743411 [Byte1]: 61
8661 01:24:36.747363
8662 01:24:36.747472 Set Vref, RX VrefLevel [Byte0]: 62
8663 01:24:36.750758 [Byte1]: 62
8664 01:24:36.755146
8665 01:24:36.755275 Set Vref, RX VrefLevel [Byte0]: 63
8666 01:24:36.757926 [Byte1]: 63
8667 01:24:36.762254
8668 01:24:36.762383 Set Vref, RX VrefLevel [Byte0]: 64
8669 01:24:36.765842 [Byte1]: 64
8670 01:24:36.769795
8671 01:24:36.769922 Set Vref, RX VrefLevel [Byte0]: 65
8672 01:24:36.773808 [Byte1]: 65
8673 01:24:36.777806
8674 01:24:36.777940 Set Vref, RX VrefLevel [Byte0]: 66
8675 01:24:36.781174 [Byte1]: 66
8676 01:24:36.785431
8677 01:24:36.785565 Set Vref, RX VrefLevel [Byte0]: 67
8678 01:24:36.788634 [Byte1]: 67
8679 01:24:36.792870
8680 01:24:36.792998 Set Vref, RX VrefLevel [Byte0]: 68
8681 01:24:36.796335 [Byte1]: 68
8682 01:24:36.800532
8683 01:24:36.800661 Set Vref, RX VrefLevel [Byte0]: 69
8684 01:24:36.803664 [Byte1]: 69
8685 01:24:36.807886
8686 01:24:36.808011 Set Vref, RX VrefLevel [Byte0]: 70
8687 01:24:36.811028 [Byte1]: 70
8688 01:24:36.815440
8689 01:24:36.815567 Set Vref, RX VrefLevel [Byte0]: 71
8690 01:24:36.818713 [Byte1]: 71
8691 01:24:36.823044
8692 01:24:36.823170 Set Vref, RX VrefLevel [Byte0]: 72
8693 01:24:36.826851 [Byte1]: 72
8694 01:24:36.830617
8695 01:24:36.830746 Set Vref, RX VrefLevel [Byte0]: 73
8696 01:24:36.833735 [Byte1]: 73
8697 01:24:36.838723
8698 01:24:36.838804 Set Vref, RX VrefLevel [Byte0]: 74
8699 01:24:36.841519 [Byte1]: 74
8700 01:24:36.845839
8701 01:24:36.845920 Set Vref, RX VrefLevel [Byte0]: 75
8702 01:24:36.849057 [Byte1]: 75
8703 01:24:36.853796
8704 01:24:36.853882 Set Vref, RX VrefLevel [Byte0]: 76
8705 01:24:36.856630 [Byte1]: 76
8706 01:24:36.860711
8707 01:24:36.860811 Final RX Vref Byte 0 = 60 to rank0
8708 01:24:36.864307 Final RX Vref Byte 1 = 64 to rank0
8709 01:24:36.867390 Final RX Vref Byte 0 = 60 to rank1
8710 01:24:36.870711 Final RX Vref Byte 1 = 64 to rank1==
8711 01:24:36.874209 Dram Type= 6, Freq= 0, CH_1, rank 0
8712 01:24:36.880833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8713 01:24:36.880933 ==
8714 01:24:36.881005 DQS Delay:
8715 01:24:36.881070 DQS0 = 0, DQS1 = 0
8716 01:24:36.884434 DQM Delay:
8717 01:24:36.884521 DQM0 = 134, DQM1 = 129
8718 01:24:36.887675 DQ Delay:
8719 01:24:36.891195 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8720 01:24:36.894160 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8721 01:24:36.897735 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8722 01:24:36.900774 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8723 01:24:36.900864
8724 01:24:36.900933
8725 01:24:36.900998
8726 01:24:36.904278 [DramC_TX_OE_Calibration] TA2
8727 01:24:36.907518 Original DQ_B0 (3 6) =30, OEN = 27
8728 01:24:36.910629 Original DQ_B1 (3 6) =30, OEN = 27
8729 01:24:36.914095 24, 0x0, End_B0=24 End_B1=24
8730 01:24:36.914207 25, 0x0, End_B0=25 End_B1=25
8731 01:24:36.917335 26, 0x0, End_B0=26 End_B1=26
8732 01:24:36.920705 27, 0x0, End_B0=27 End_B1=27
8733 01:24:36.924324 28, 0x0, End_B0=28 End_B1=28
8734 01:24:36.924412 29, 0x0, End_B0=29 End_B1=29
8735 01:24:36.927269 30, 0x0, End_B0=30 End_B1=30
8736 01:24:36.930588 31, 0x4545, End_B0=30 End_B1=30
8737 01:24:36.934097 Byte0 end_step=30 best_step=27
8738 01:24:36.937209 Byte1 end_step=30 best_step=27
8739 01:24:36.940674 Byte0 TX OE(2T, 0.5T) = (3, 3)
8740 01:24:36.940788 Byte1 TX OE(2T, 0.5T) = (3, 3)
8741 01:24:36.944360
8742 01:24:36.944445
8743 01:24:36.950826 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8744 01:24:36.954126 CH1 RK0: MR19=303, MR18=1624
8745 01:24:36.960746 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8746 01:24:36.960843
8747 01:24:36.964225 ----->DramcWriteLeveling(PI) begin...
8748 01:24:36.964312 ==
8749 01:24:36.967963 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 01:24:36.970582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 01:24:36.970669 ==
8752 01:24:36.973973 Write leveling (Byte 0): 24 => 24
8753 01:24:36.977267 Write leveling (Byte 1): 28 => 28
8754 01:24:36.980791 DramcWriteLeveling(PI) end<-----
8755 01:24:36.980920
8756 01:24:36.981037 ==
8757 01:24:36.983857 Dram Type= 6, Freq= 0, CH_1, rank 1
8758 01:24:36.987384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 01:24:36.987514 ==
8760 01:24:36.990609 [Gating] SW mode calibration
8761 01:24:36.997439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8762 01:24:37.004381 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8763 01:24:37.007448 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 01:24:37.010539 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 01:24:37.017288 1 4 8 | B1->B0 | 3333 2323 | 0 1 | (0 0) (1 1)
8766 01:24:37.020676 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8767 01:24:37.024063 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 01:24:37.030727 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 01:24:37.034279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 01:24:37.037811 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 01:24:37.044011 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 01:24:37.047200 1 5 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8773 01:24:37.051064 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8774 01:24:37.057177 1 5 12 | B1->B0 | 2323 3232 | 0 0 | (1 0) (0 1)
8775 01:24:37.060564 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 01:24:37.063831 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 01:24:37.070587 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 01:24:37.073855 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 01:24:37.077096 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 01:24:37.080587 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8781 01:24:37.087113 1 6 8 | B1->B0 | 4141 2424 | 0 0 | (0 0) (0 0)
8782 01:24:37.090304 1 6 12 | B1->B0 | 4646 3b3b | 0 1 | (0 0) (0 0)
8783 01:24:37.093643 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 01:24:37.100536 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 01:24:37.103848 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 01:24:37.106955 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 01:24:37.113766 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 01:24:37.117055 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 01:24:37.120327 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8790 01:24:37.127233 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8791 01:24:37.130762 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8792 01:24:37.133908 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 01:24:37.140765 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 01:24:37.143771 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 01:24:37.146993 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 01:24:37.153512 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 01:24:37.157124 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 01:24:37.160654 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 01:24:37.167477 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 01:24:37.170381 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 01:24:37.173468 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 01:24:37.180152 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 01:24:37.183497 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 01:24:37.187234 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 01:24:37.193413 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8806 01:24:37.196871 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8807 01:24:37.200071 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 01:24:37.203200 Total UI for P1: 0, mck2ui 16
8809 01:24:37.206745 best dqsien dly found for B0: ( 1, 9, 10)
8810 01:24:37.210186 Total UI for P1: 0, mck2ui 16
8811 01:24:37.213493 best dqsien dly found for B1: ( 1, 9, 10)
8812 01:24:37.216650 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8813 01:24:37.220332 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8814 01:24:37.220422
8815 01:24:37.223479 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8816 01:24:37.230264 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8817 01:24:37.230356 [Gating] SW calibration Done
8818 01:24:37.230427 ==
8819 01:24:37.233677 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 01:24:37.240392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 01:24:37.240482 ==
8822 01:24:37.240552 RX Vref Scan: 0
8823 01:24:37.240617
8824 01:24:37.243299 RX Vref 0 -> 0, step: 1
8825 01:24:37.243386
8826 01:24:37.246473 RX Delay 0 -> 252, step: 8
8827 01:24:37.250136 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8828 01:24:37.253539 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8829 01:24:37.256541 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8830 01:24:37.260415 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8831 01:24:37.266635 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8832 01:24:37.270535 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8833 01:24:37.273598 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8834 01:24:37.276731 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8835 01:24:37.279766 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8836 01:24:37.287120 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8837 01:24:37.289639 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8838 01:24:37.293938 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8839 01:24:37.296308 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8840 01:24:37.303436 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8841 01:24:37.306403 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8842 01:24:37.309978 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8843 01:24:37.310093 ==
8844 01:24:37.313127 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 01:24:37.316249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 01:24:37.316383 ==
8847 01:24:37.319584 DQS Delay:
8848 01:24:37.319709 DQS0 = 0, DQS1 = 0
8849 01:24:37.322651 DQM Delay:
8850 01:24:37.322785 DQM0 = 136, DQM1 = 131
8851 01:24:37.326229 DQ Delay:
8852 01:24:37.329736 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8853 01:24:37.333093 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8854 01:24:37.336062 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8855 01:24:37.339402 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8856 01:24:37.339530
8857 01:24:37.339651
8858 01:24:37.339768 ==
8859 01:24:37.342977 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 01:24:37.346419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 01:24:37.346550 ==
8862 01:24:37.346658
8863 01:24:37.346761
8864 01:24:37.349243 TX Vref Scan disable
8865 01:24:37.352514 == TX Byte 0 ==
8866 01:24:37.355824 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8867 01:24:37.359024 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 01:24:37.362528 == TX Byte 1 ==
8869 01:24:37.366002 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8870 01:24:37.369434 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8871 01:24:37.369522 ==
8872 01:24:37.372407 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 01:24:37.379235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 01:24:37.379326 ==
8875 01:24:37.390623
8876 01:24:37.393756 TX Vref early break, caculate TX vref
8877 01:24:37.397014 TX Vref=16, minBit 1, minWin=23, winSum=385
8878 01:24:37.400555 TX Vref=18, minBit 8, minWin=23, winSum=392
8879 01:24:37.403971 TX Vref=20, minBit 10, minWin=23, winSum=394
8880 01:24:37.407255 TX Vref=22, minBit 9, minWin=24, winSum=410
8881 01:24:37.410612 TX Vref=24, minBit 12, minWin=24, winSum=420
8882 01:24:37.417153 TX Vref=26, minBit 12, minWin=24, winSum=419
8883 01:24:37.420319 TX Vref=28, minBit 11, minWin=25, winSum=424
8884 01:24:37.423771 TX Vref=30, minBit 9, minWin=24, winSum=418
8885 01:24:37.426760 TX Vref=32, minBit 8, minWin=24, winSum=406
8886 01:24:37.430312 TX Vref=34, minBit 8, minWin=23, winSum=394
8887 01:24:37.436690 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 28
8888 01:24:37.436807
8889 01:24:37.440312 Final TX Range 0 Vref 28
8890 01:24:37.440419
8891 01:24:37.440516 ==
8892 01:24:37.443350 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 01:24:37.446596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 01:24:37.446713 ==
8895 01:24:37.446812
8896 01:24:37.446905
8897 01:24:37.450071 TX Vref Scan disable
8898 01:24:37.456879 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8899 01:24:37.456992 == TX Byte 0 ==
8900 01:24:37.459976 u2DelayCellOfst[0]=17 cells (5 PI)
8901 01:24:37.463952 u2DelayCellOfst[1]=13 cells (4 PI)
8902 01:24:37.466768 u2DelayCellOfst[2]=0 cells (0 PI)
8903 01:24:37.469835 u2DelayCellOfst[3]=6 cells (2 PI)
8904 01:24:37.473344 u2DelayCellOfst[4]=10 cells (3 PI)
8905 01:24:37.476526 u2DelayCellOfst[5]=20 cells (6 PI)
8906 01:24:37.480160 u2DelayCellOfst[6]=20 cells (6 PI)
8907 01:24:37.483334 u2DelayCellOfst[7]=6 cells (2 PI)
8908 01:24:37.487028 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8909 01:24:37.490378 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8910 01:24:37.493785 == TX Byte 1 ==
8911 01:24:37.496777 u2DelayCellOfst[8]=0 cells (0 PI)
8912 01:24:37.496890 u2DelayCellOfst[9]=3 cells (1 PI)
8913 01:24:37.499792 u2DelayCellOfst[10]=10 cells (3 PI)
8914 01:24:37.503443 u2DelayCellOfst[11]=3 cells (1 PI)
8915 01:24:37.506715 u2DelayCellOfst[12]=13 cells (4 PI)
8916 01:24:37.509823 u2DelayCellOfst[13]=17 cells (5 PI)
8917 01:24:37.513339 u2DelayCellOfst[14]=20 cells (6 PI)
8918 01:24:37.516368 u2DelayCellOfst[15]=20 cells (6 PI)
8919 01:24:37.520321 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8920 01:24:37.526633 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8921 01:24:37.526753 DramC Write-DBI on
8922 01:24:37.526860 ==
8923 01:24:37.529759 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 01:24:37.537327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 01:24:37.537450 ==
8926 01:24:37.537554
8927 01:24:37.537652
8928 01:24:37.537750 TX Vref Scan disable
8929 01:24:37.540175 == TX Byte 0 ==
8930 01:24:37.543538 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8931 01:24:37.547358 == TX Byte 1 ==
8932 01:24:37.550253 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8933 01:24:37.550368 DramC Write-DBI off
8934 01:24:37.553699
8935 01:24:37.553812 [DATLAT]
8936 01:24:37.553909 Freq=1600, CH1 RK1
8937 01:24:37.554005
8938 01:24:37.556882 DATLAT Default: 0xf
8939 01:24:37.556991 0, 0xFFFF, sum = 0
8940 01:24:37.560374 1, 0xFFFF, sum = 0
8941 01:24:37.560490 2, 0xFFFF, sum = 0
8942 01:24:37.563651 3, 0xFFFF, sum = 0
8943 01:24:37.567002 4, 0xFFFF, sum = 0
8944 01:24:37.567117 5, 0xFFFF, sum = 0
8945 01:24:37.570082 6, 0xFFFF, sum = 0
8946 01:24:37.570201 7, 0xFFFF, sum = 0
8947 01:24:37.574029 8, 0xFFFF, sum = 0
8948 01:24:37.574145 9, 0xFFFF, sum = 0
8949 01:24:37.576939 10, 0xFFFF, sum = 0
8950 01:24:37.577052 11, 0xFFFF, sum = 0
8951 01:24:37.580421 12, 0xFFFF, sum = 0
8952 01:24:37.580537 13, 0xFFFF, sum = 0
8953 01:24:37.583681 14, 0x0, sum = 1
8954 01:24:37.583797 15, 0x0, sum = 2
8955 01:24:37.586771 16, 0x0, sum = 3
8956 01:24:37.586886 17, 0x0, sum = 4
8957 01:24:37.590292 best_step = 15
8958 01:24:37.590405
8959 01:24:37.590506 ==
8960 01:24:37.594202 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 01:24:37.597504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 01:24:37.597620 ==
8963 01:24:37.597725 RX Vref Scan: 0
8964 01:24:37.597826
8965 01:24:37.600228 RX Vref 0 -> 0, step: 1
8966 01:24:37.600342
8967 01:24:37.603764 RX Delay 19 -> 252, step: 4
8968 01:24:37.607072 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8969 01:24:37.610547 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8970 01:24:37.617202 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8971 01:24:37.620076 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8972 01:24:37.623541 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8973 01:24:37.626598 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8974 01:24:37.629973 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8975 01:24:37.637103 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8976 01:24:37.640093 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8977 01:24:37.643547 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8978 01:24:37.646522 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8979 01:24:37.650403 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8980 01:24:37.656419 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8981 01:24:37.660000 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8982 01:24:37.663226 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8983 01:24:37.666566 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8984 01:24:37.666682 ==
8985 01:24:37.669827 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 01:24:37.676496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 01:24:37.676609 ==
8988 01:24:37.676714 DQS Delay:
8989 01:24:37.679713 DQS0 = 0, DQS1 = 0
8990 01:24:37.679824 DQM Delay:
8991 01:24:37.679923 DQM0 = 133, DQM1 = 129
8992 01:24:37.683402 DQ Delay:
8993 01:24:37.686837 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8994 01:24:37.689838 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8995 01:24:37.693168 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8996 01:24:37.696441 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8997 01:24:37.696554
8998 01:24:37.696653
8999 01:24:37.696749
9000 01:24:37.699852 [DramC_TX_OE_Calibration] TA2
9001 01:24:37.703032 Original DQ_B0 (3 6) =30, OEN = 27
9002 01:24:37.706333 Original DQ_B1 (3 6) =30, OEN = 27
9003 01:24:37.710485 24, 0x0, End_B0=24 End_B1=24
9004 01:24:37.710601 25, 0x0, End_B0=25 End_B1=25
9005 01:24:37.713048 26, 0x0, End_B0=26 End_B1=26
9006 01:24:37.716435 27, 0x0, End_B0=27 End_B1=27
9007 01:24:37.719629 28, 0x0, End_B0=28 End_B1=28
9008 01:24:37.723058 29, 0x0, End_B0=29 End_B1=29
9009 01:24:37.723177 30, 0x0, End_B0=30 End_B1=30
9010 01:24:37.726631 31, 0x4141, End_B0=30 End_B1=30
9011 01:24:37.729828 Byte0 end_step=30 best_step=27
9012 01:24:37.733004 Byte1 end_step=30 best_step=27
9013 01:24:37.736580 Byte0 TX OE(2T, 0.5T) = (3, 3)
9014 01:24:37.739823 Byte1 TX OE(2T, 0.5T) = (3, 3)
9015 01:24:37.739908
9016 01:24:37.739976
9017 01:24:37.746511 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9018 01:24:37.749500 CH1 RK1: MR19=303, MR18=1C07
9019 01:24:37.756426 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9020 01:24:37.759627 [RxdqsGatingPostProcess] freq 1600
9021 01:24:37.763066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9022 01:24:37.766197 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 01:24:37.769608 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 01:24:37.773480 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 01:24:37.776179 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 01:24:37.779722 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 01:24:37.782717 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 01:24:37.786298 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 01:24:37.789464 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 01:24:37.792864 Pre-setting of DQS Precalculation
9031 01:24:37.796022 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9032 01:24:37.803209 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9033 01:24:37.809401 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9034 01:24:37.809533
9035 01:24:37.812704
9036 01:24:37.812801 [Calibration Summary] 3200 Mbps
9037 01:24:37.816404 CH 0, Rank 0
9038 01:24:37.816490 SW Impedance : PASS
9039 01:24:37.819955 DUTY Scan : NO K
9040 01:24:37.822855 ZQ Calibration : PASS
9041 01:24:37.822942 Jitter Meter : NO K
9042 01:24:37.826265 CBT Training : PASS
9043 01:24:37.829667 Write leveling : PASS
9044 01:24:37.829754 RX DQS gating : PASS
9045 01:24:37.832749 RX DQ/DQS(RDDQC) : PASS
9046 01:24:37.836206 TX DQ/DQS : PASS
9047 01:24:37.836293 RX DATLAT : PASS
9048 01:24:37.839438 RX DQ/DQS(Engine): PASS
9049 01:24:37.839525 TX OE : PASS
9050 01:24:37.842784 All Pass.
9051 01:24:37.842870
9052 01:24:37.842938 CH 0, Rank 1
9053 01:24:37.846372 SW Impedance : PASS
9054 01:24:37.846500 DUTY Scan : NO K
9055 01:24:37.849557 ZQ Calibration : PASS
9056 01:24:37.853107 Jitter Meter : NO K
9057 01:24:37.853237 CBT Training : PASS
9058 01:24:37.856422 Write leveling : PASS
9059 01:24:37.859657 RX DQS gating : PASS
9060 01:24:37.859785 RX DQ/DQS(RDDQC) : PASS
9061 01:24:37.862994 TX DQ/DQS : PASS
9062 01:24:37.866491 RX DATLAT : PASS
9063 01:24:37.866615 RX DQ/DQS(Engine): PASS
9064 01:24:37.869245 TX OE : PASS
9065 01:24:37.869368 All Pass.
9066 01:24:37.869482
9067 01:24:37.872722 CH 1, Rank 0
9068 01:24:37.872854 SW Impedance : PASS
9069 01:24:37.876177 DUTY Scan : NO K
9070 01:24:37.879256 ZQ Calibration : PASS
9071 01:24:37.879380 Jitter Meter : NO K
9072 01:24:37.882834 CBT Training : PASS
9073 01:24:37.886117 Write leveling : PASS
9074 01:24:37.886204 RX DQS gating : PASS
9075 01:24:37.889611 RX DQ/DQS(RDDQC) : PASS
9076 01:24:37.889697 TX DQ/DQS : PASS
9077 01:24:37.892721 RX DATLAT : PASS
9078 01:24:37.896296 RX DQ/DQS(Engine): PASS
9079 01:24:37.896383 TX OE : PASS
9080 01:24:37.899441 All Pass.
9081 01:24:37.899527
9082 01:24:37.899596 CH 1, Rank 1
9083 01:24:37.902805 SW Impedance : PASS
9084 01:24:37.902910 DUTY Scan : NO K
9085 01:24:37.906728 ZQ Calibration : PASS
9086 01:24:37.909435 Jitter Meter : NO K
9087 01:24:37.909521 CBT Training : PASS
9088 01:24:37.912945 Write leveling : PASS
9089 01:24:37.916001 RX DQS gating : PASS
9090 01:24:37.916087 RX DQ/DQS(RDDQC) : PASS
9091 01:24:37.919488 TX DQ/DQS : PASS
9092 01:24:37.923010 RX DATLAT : PASS
9093 01:24:37.923100 RX DQ/DQS(Engine): PASS
9094 01:24:37.926354 TX OE : PASS
9095 01:24:37.926443 All Pass.
9096 01:24:37.926512
9097 01:24:37.929764 DramC Write-DBI on
9098 01:24:37.933175 PER_BANK_REFRESH: Hybrid Mode
9099 01:24:37.933264 TX_TRACKING: ON
9100 01:24:37.942865 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9101 01:24:37.949954 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9102 01:24:37.956056 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 01:24:37.959696 [FAST_K] Save calibration result to emmc
9104 01:24:37.962826 sync common calibartion params.
9105 01:24:37.966215 sync cbt_mode0:1, 1:1
9106 01:24:37.966306 dram_init: ddr_geometry: 2
9107 01:24:37.969653 dram_init: ddr_geometry: 2
9108 01:24:37.973057 dram_init: ddr_geometry: 2
9109 01:24:37.975999 0:dram_rank_size:100000000
9110 01:24:37.976132 1:dram_rank_size:100000000
9111 01:24:37.982795 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9112 01:24:37.986284 DFS_SHUFFLE_HW_MODE: ON
9113 01:24:37.989964 dramc_set_vcore_voltage set vcore to 725000
9114 01:24:37.992919 Read voltage for 1600, 0
9115 01:24:37.993047 Vio18 = 0
9116 01:24:37.993163 Vcore = 725000
9117 01:24:37.996366 Vdram = 0
9118 01:24:37.996483 Vddq = 0
9119 01:24:37.996598 Vmddr = 0
9120 01:24:37.999358 switch to 3200 Mbps bootup
9121 01:24:37.999482 [DramcRunTimeConfig]
9122 01:24:38.003367 PHYPLL
9123 01:24:38.003494 DPM_CONTROL_AFTERK: ON
9124 01:24:38.006809 PER_BANK_REFRESH: ON
9125 01:24:38.009305 REFRESH_OVERHEAD_REDUCTION: ON
9126 01:24:38.009453 CMD_PICG_NEW_MODE: OFF
9127 01:24:38.012810 XRTWTW_NEW_MODE: ON
9128 01:24:38.012950 XRTRTR_NEW_MODE: ON
9129 01:24:38.016006 TX_TRACKING: ON
9130 01:24:38.016138 RDSEL_TRACKING: OFF
9131 01:24:38.019401 DQS Precalculation for DVFS: ON
9132 01:24:38.022741 RX_TRACKING: OFF
9133 01:24:38.022827 HW_GATING DBG: ON
9134 01:24:38.026461 ZQCS_ENABLE_LP4: ON
9135 01:24:38.026546 RX_PICG_NEW_MODE: ON
9136 01:24:38.029448 TX_PICG_NEW_MODE: ON
9137 01:24:38.029550 ENABLE_RX_DCM_DPHY: ON
9138 01:24:38.032682 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9139 01:24:38.036045 DUMMY_READ_FOR_TRACKING: OFF
9140 01:24:38.039371 !!! SPM_CONTROL_AFTERK: OFF
9141 01:24:38.043396 !!! SPM could not control APHY
9142 01:24:38.043501 IMPEDANCE_TRACKING: ON
9143 01:24:38.046119 TEMP_SENSOR: ON
9144 01:24:38.046221 HW_SAVE_FOR_SR: OFF
9145 01:24:38.049633 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9146 01:24:38.053309 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9147 01:24:38.055969 Read ODT Tracking: ON
9148 01:24:38.059611 Refresh Rate DeBounce: ON
9149 01:24:38.059715 DFS_NO_QUEUE_FLUSH: ON
9150 01:24:38.063251 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9151 01:24:38.066280 ENABLE_DFS_RUNTIME_MRW: OFF
9152 01:24:38.069141 DDR_RESERVE_NEW_MODE: ON
9153 01:24:38.069230 MR_CBT_SWITCH_FREQ: ON
9154 01:24:38.073197 =========================
9155 01:24:38.091129 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9156 01:24:38.094480 dram_init: ddr_geometry: 2
9157 01:24:38.112698 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9158 01:24:38.116131 dram_init: dram init end (result: 0)
9159 01:24:38.122986 DRAM-K: Full calibration passed in 24522 msecs
9160 01:24:38.126283 MRC: failed to locate region type 0.
9161 01:24:38.126373 DRAM rank0 size:0x100000000,
9162 01:24:38.129345 DRAM rank1 size=0x100000000
9163 01:24:38.139296 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9164 01:24:38.146323 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9165 01:24:38.152517 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9166 01:24:38.159225 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9167 01:24:38.162764 DRAM rank0 size:0x100000000,
9168 01:24:38.165860 DRAM rank1 size=0x100000000
9169 01:24:38.165973 CBMEM:
9170 01:24:38.169511 IMD: root @ 0xfffff000 254 entries.
9171 01:24:38.172760 IMD: root @ 0xffffec00 62 entries.
9172 01:24:38.175909 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9173 01:24:38.179550 WARNING: RO_VPD is uninitialized or empty.
9174 01:24:38.185902 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9175 01:24:38.192834 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9176 01:24:38.205499 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9177 01:24:38.217068 BS: romstage times (exec / console): total (unknown) / 24018 ms
9178 01:24:38.217216
9179 01:24:38.217336
9180 01:24:38.227194 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9181 01:24:38.230170 ARM64: Exception handlers installed.
9182 01:24:38.233739 ARM64: Testing exception
9183 01:24:38.233865 ARM64: Done test exception
9184 01:24:38.237375 Enumerating buses...
9185 01:24:38.240266 Show all devs... Before device enumeration.
9186 01:24:38.244314 Root Device: enabled 1
9187 01:24:38.247075 CPU_CLUSTER: 0: enabled 1
9188 01:24:38.247162 CPU: 00: enabled 1
9189 01:24:38.250391 Compare with tree...
9190 01:24:38.250478 Root Device: enabled 1
9191 01:24:38.253495 CPU_CLUSTER: 0: enabled 1
9192 01:24:38.257083 CPU: 00: enabled 1
9193 01:24:38.257219 Root Device scanning...
9194 01:24:38.260295 scan_static_bus for Root Device
9195 01:24:38.263741 CPU_CLUSTER: 0 enabled
9196 01:24:38.267053 scan_static_bus for Root Device done
9197 01:24:38.270567 scan_bus: bus Root Device finished in 8 msecs
9198 01:24:38.270695 done
9199 01:24:38.277495 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9200 01:24:38.280706 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9201 01:24:38.287286 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9202 01:24:38.290680 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9203 01:24:38.293671 Allocating resources...
9204 01:24:38.293804 Reading resources...
9205 01:24:38.296971 Root Device read_resources bus 0 link: 0
9206 01:24:38.300424 DRAM rank0 size:0x100000000,
9207 01:24:38.303828 DRAM rank1 size=0x100000000
9208 01:24:38.307353 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9209 01:24:38.310833 CPU: 00 missing read_resources
9210 01:24:38.313864 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9211 01:24:38.317398 Root Device read_resources bus 0 link: 0 done
9212 01:24:38.320747 Done reading resources.
9213 01:24:38.327202 Show resources in subtree (Root Device)...After reading.
9214 01:24:38.330470 Root Device child on link 0 CPU_CLUSTER: 0
9215 01:24:38.333712 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 01:24:38.343513 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 01:24:38.343608 CPU: 00
9218 01:24:38.347157 Root Device assign_resources, bus 0 link: 0
9219 01:24:38.350114 CPU_CLUSTER: 0 missing set_resources
9220 01:24:38.353572 Root Device assign_resources, bus 0 link: 0 done
9221 01:24:38.356964 Done setting resources.
9222 01:24:38.363754 Show resources in subtree (Root Device)...After assigning values.
9223 01:24:38.366841 Root Device child on link 0 CPU_CLUSTER: 0
9224 01:24:38.370198 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 01:24:38.380232 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 01:24:38.380330 CPU: 00
9227 01:24:38.383681 Done allocating resources.
9228 01:24:38.386910 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9229 01:24:38.390362 Enabling resources...
9230 01:24:38.390450 done.
9231 01:24:38.393992 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9232 01:24:38.396875 Initializing devices...
9233 01:24:38.400049 Root Device init
9234 01:24:38.400138 init hardware done!
9235 01:24:38.403692 0x00000018: ctrlr->caps
9236 01:24:38.403779 52.000 MHz: ctrlr->f_max
9237 01:24:38.407141 0.400 MHz: ctrlr->f_min
9238 01:24:38.410257 0x40ff8080: ctrlr->voltages
9239 01:24:38.410350 sclk: 390625
9240 01:24:38.414245 Bus Width = 1
9241 01:24:38.414333 sclk: 390625
9242 01:24:38.414403 Bus Width = 1
9243 01:24:38.417029 Early init status = 3
9244 01:24:38.420114 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9245 01:24:38.424380 in-header: 03 fc 00 00 01 00 00 00
9246 01:24:38.427967 in-data: 00
9247 01:24:38.430905 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9248 01:24:38.436055 in-header: 03 fd 00 00 00 00 00 00
9249 01:24:38.439511 in-data:
9250 01:24:38.442540 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9251 01:24:38.447018 in-header: 03 fc 00 00 01 00 00 00
9252 01:24:38.450251 in-data: 00
9253 01:24:38.453689 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9254 01:24:38.458925 in-header: 03 fd 00 00 00 00 00 00
9255 01:24:38.462914 in-data:
9256 01:24:38.465588 [SSUSB] Setting up USB HOST controller...
9257 01:24:38.468769 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9258 01:24:38.471915 [SSUSB] phy power-on done.
9259 01:24:38.475518 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9260 01:24:38.482199 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9261 01:24:38.485356 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9262 01:24:38.492095 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9263 01:24:38.498600 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9264 01:24:38.505267 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9265 01:24:38.511804 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9266 01:24:38.518664 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9267 01:24:38.522242 SPM: binary array size = 0x9dc
9268 01:24:38.525148 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9269 01:24:38.531873 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9270 01:24:38.538612 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9271 01:24:38.541921 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9272 01:24:38.548304 configure_display: Starting display init
9273 01:24:38.582533 anx7625_power_on_init: Init interface.
9274 01:24:38.585927 anx7625_disable_pd_protocol: Disabled PD feature.
9275 01:24:38.588814 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9276 01:24:38.616449 anx7625_start_dp_work: Secure OCM version=00
9277 01:24:38.619983 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9278 01:24:38.634937 sp_tx_get_edid_block: EDID Block = 1
9279 01:24:38.737327 Extracted contents:
9280 01:24:38.740740 header: 00 ff ff ff ff ff ff 00
9281 01:24:38.743736 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9282 01:24:38.747235 version: 01 04
9283 01:24:38.750642 basic params: 95 1f 11 78 0a
9284 01:24:38.753841 chroma info: 76 90 94 55 54 90 27 21 50 54
9285 01:24:38.757289 established: 00 00 00
9286 01:24:38.764114 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9287 01:24:38.766809 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9288 01:24:38.773628 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9289 01:24:38.780159 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9290 01:24:38.786978 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9291 01:24:38.790314 extensions: 00
9292 01:24:38.790431 checksum: fb
9293 01:24:38.790530
9294 01:24:38.793701 Manufacturer: IVO Model 57d Serial Number 0
9295 01:24:38.796638 Made week 0 of 2020
9296 01:24:38.796747 EDID version: 1.4
9297 01:24:38.800284 Digital display
9298 01:24:38.803371 6 bits per primary color channel
9299 01:24:38.803519 DisplayPort interface
9300 01:24:38.806847 Maximum image size: 31 cm x 17 cm
9301 01:24:38.810050 Gamma: 220%
9302 01:24:38.810165 Check DPMS levels
9303 01:24:38.813257 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9304 01:24:38.819986 First detailed timing is preferred timing
9305 01:24:38.820112 Established timings supported:
9306 01:24:38.823529 Standard timings supported:
9307 01:24:38.826961 Detailed timings
9308 01:24:38.830157 Hex of detail: 383680a07038204018303c0035ae10000019
9309 01:24:38.833205 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9310 01:24:38.839872 0780 0798 07c8 0820 hborder 0
9311 01:24:38.843505 0438 043b 0447 0458 vborder 0
9312 01:24:38.846561 -hsync -vsync
9313 01:24:38.846675 Did detailed timing
9314 01:24:38.853169 Hex of detail: 000000000000000000000000000000000000
9315 01:24:38.856483 Manufacturer-specified data, tag 0
9316 01:24:38.859985 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9317 01:24:38.862813 ASCII string: InfoVision
9318 01:24:38.866567 Hex of detail: 000000fe00523134304e574635205248200a
9319 01:24:38.870275 ASCII string: R140NWF5 RH
9320 01:24:38.870389 Checksum
9321 01:24:38.872845 Checksum: 0xfb (valid)
9322 01:24:38.876356 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9323 01:24:38.879595 DSI data_rate: 832800000 bps
9324 01:24:38.886519 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9325 01:24:38.889560 anx7625_parse_edid: pixelclock(138800).
9326 01:24:38.892832 hactive(1920), hsync(48), hfp(24), hbp(88)
9327 01:24:38.896366 vactive(1080), vsync(12), vfp(3), vbp(17)
9328 01:24:38.899513 anx7625_dsi_config: config dsi.
9329 01:24:38.906053 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9330 01:24:38.919154 anx7625_dsi_config: success to config DSI
9331 01:24:38.922770 anx7625_dp_start: MIPI phy setup OK.
9332 01:24:38.925948 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9333 01:24:38.929473 mtk_ddp_mode_set invalid vrefresh 60
9334 01:24:38.932566 main_disp_path_setup
9335 01:24:38.932683 ovl_layer_smi_id_en
9336 01:24:38.935671 ovl_layer_smi_id_en
9337 01:24:38.935786 ccorr_config
9338 01:24:38.935886 aal_config
9339 01:24:38.939201 gamma_config
9340 01:24:38.939316 postmask_config
9341 01:24:38.942368 dither_config
9342 01:24:38.945772 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9343 01:24:38.952272 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9344 01:24:38.955544 Root Device init finished in 553 msecs
9345 01:24:38.958865 CPU_CLUSTER: 0 init
9346 01:24:38.965393 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9347 01:24:38.971889 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9348 01:24:38.972008 APU_MBOX 0x190000b0 = 0x10001
9349 01:24:38.975182 APU_MBOX 0x190001b0 = 0x10001
9350 01:24:38.979248 APU_MBOX 0x190005b0 = 0x10001
9351 01:24:38.981893 APU_MBOX 0x190006b0 = 0x10001
9352 01:24:38.988445 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9353 01:24:38.998268 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9354 01:24:39.010752 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9355 01:24:39.017374 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9356 01:24:39.029015 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9357 01:24:39.038151 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9358 01:24:39.041499 CPU_CLUSTER: 0 init finished in 81 msecs
9359 01:24:39.044738 Devices initialized
9360 01:24:39.047888 Show all devs... After init.
9361 01:24:39.047972 Root Device: enabled 1
9362 01:24:39.051525 CPU_CLUSTER: 0: enabled 1
9363 01:24:39.055034 CPU: 00: enabled 1
9364 01:24:39.058054 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9365 01:24:39.061270 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9366 01:24:39.064855 ELOG: NV offset 0x57f000 size 0x1000
9367 01:24:39.071778 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9368 01:24:39.077882 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9369 01:24:39.081374 ELOG: Event(17) added with size 13 at 2023-08-28 01:24:34 UTC
9370 01:24:39.084433 out: cmd=0x121: 03 db 21 01 00 00 00 00
9371 01:24:39.088288 in-header: 03 21 00 00 2c 00 00 00
9372 01:24:39.101848 in-data: 3e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 01:24:39.108143 ELOG: Event(A1) added with size 10 at 2023-08-28 01:24:34 UTC
9374 01:24:39.114647 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9375 01:24:39.121715 ELOG: Event(A0) added with size 9 at 2023-08-28 01:24:34 UTC
9376 01:24:39.124683 elog_add_boot_reason: Logged dev mode boot
9377 01:24:39.128208 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9378 01:24:39.131807 Finalize devices...
9379 01:24:39.131896 Devices finalized
9380 01:24:39.137978 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9381 01:24:39.141269 Writing coreboot table at 0xffe64000
9382 01:24:39.144467 0. 000000000010a000-0000000000113fff: RAMSTAGE
9383 01:24:39.147905 1. 0000000040000000-00000000400fffff: RAM
9384 01:24:39.154453 2. 0000000040100000-000000004032afff: RAMSTAGE
9385 01:24:39.158111 3. 000000004032b000-00000000545fffff: RAM
9386 01:24:39.161221 4. 0000000054600000-000000005465ffff: BL31
9387 01:24:39.164550 5. 0000000054660000-00000000ffe63fff: RAM
9388 01:24:39.171219 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9389 01:24:39.174676 7. 0000000100000000-000000023fffffff: RAM
9390 01:24:39.174766 Passing 5 GPIOs to payload:
9391 01:24:39.180919 NAME | PORT | POLARITY | VALUE
9392 01:24:39.184364 EC in RW | 0x000000aa | low | undefined
9393 01:24:39.191625 EC interrupt | 0x00000005 | low | undefined
9394 01:24:39.194673 TPM interrupt | 0x000000ab | high | undefined
9395 01:24:39.197766 SD card detect | 0x00000011 | high | undefined
9396 01:24:39.204284 speaker enable | 0x00000093 | high | undefined
9397 01:24:39.207431 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9398 01:24:39.210858 in-header: 03 f9 00 00 02 00 00 00
9399 01:24:39.210993 in-data: 02 00
9400 01:24:39.214025 ADC[4]: Raw value=900663 ID=7
9401 01:24:39.217633 ADC[3]: Raw value=212810 ID=1
9402 01:24:39.220863 RAM Code: 0x71
9403 01:24:39.220989 ADC[6]: Raw value=74502 ID=0
9404 01:24:39.224230 ADC[5]: Raw value=212072 ID=1
9405 01:24:39.227333 SKU Code: 0x1
9406 01:24:39.230738 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd8
9407 01:24:39.233889 coreboot table: 964 bytes.
9408 01:24:39.237285 IMD ROOT 0. 0xfffff000 0x00001000
9409 01:24:39.240607 IMD SMALL 1. 0xffffe000 0x00001000
9410 01:24:39.244047 RO MCACHE 2. 0xffffc000 0x00001104
9411 01:24:39.247396 CONSOLE 3. 0xfff7c000 0x00080000
9412 01:24:39.250922 FMAP 4. 0xfff7b000 0x00000452
9413 01:24:39.253784 TIME STAMP 5. 0xfff7a000 0x00000910
9414 01:24:39.257158 VBOOT WORK 6. 0xfff66000 0x00014000
9415 01:24:39.260624 RAMOOPS 7. 0xffe66000 0x00100000
9416 01:24:39.263936 COREBOOT 8. 0xffe64000 0x00002000
9417 01:24:39.264047 IMD small region:
9418 01:24:39.267021 IMD ROOT 0. 0xffffec00 0x00000400
9419 01:24:39.270503 VPD 1. 0xffffeb80 0x0000006c
9420 01:24:39.277382 MMC STATUS 2. 0xffffeb60 0x00000004
9421 01:24:39.280977 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9422 01:24:39.283862 Probing TPM: done!
9423 01:24:39.287146 Connected to device vid:did:rid of 1ae0:0028:00
9424 01:24:39.297089 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9425 01:24:39.300457 Initialized TPM device CR50 revision 0
9426 01:24:39.304506 Checking cr50 for pending updates
9427 01:24:39.307753 Reading cr50 TPM mode
9428 01:24:39.316403 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9429 01:24:39.322981 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9430 01:24:39.363103 read SPI 0x3990ec 0x4f1b0: 34844 us, 9299 KB/s, 74.392 Mbps
9431 01:24:39.366215 Checking segment from ROM address 0x40100000
9432 01:24:39.369834 Checking segment from ROM address 0x4010001c
9433 01:24:39.376138 Loading segment from ROM address 0x40100000
9434 01:24:39.376261 code (compression=0)
9435 01:24:39.386351 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9436 01:24:39.393203 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9437 01:24:39.393300 it's not compressed!
9438 01:24:39.400072 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9439 01:24:39.403101 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9440 01:24:39.423254 Loading segment from ROM address 0x4010001c
9441 01:24:39.423383 Entry Point 0x80000000
9442 01:24:39.426836 Loaded segments
9443 01:24:39.430486 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9444 01:24:39.437188 Jumping to boot code at 0x80000000(0xffe64000)
9445 01:24:39.443704 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9446 01:24:39.450511 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9447 01:24:39.457783 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9448 01:24:39.461759 Checking segment from ROM address 0x40100000
9449 01:24:39.464783 Checking segment from ROM address 0x4010001c
9450 01:24:39.471370 Loading segment from ROM address 0x40100000
9451 01:24:39.471497 code (compression=1)
9452 01:24:39.477905 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9453 01:24:39.487796 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9454 01:24:39.487947 using LZMA
9455 01:24:39.496270 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9456 01:24:39.503037 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9457 01:24:39.506230 Loading segment from ROM address 0x4010001c
9458 01:24:39.506352 Entry Point 0x54601000
9459 01:24:39.509546 Loaded segments
9460 01:24:39.512741 NOTICE: MT8192 bl31_setup
9461 01:24:39.520191 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9462 01:24:39.523223 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9463 01:24:39.526494 WARNING: region 0:
9464 01:24:39.530255 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 01:24:39.530373 WARNING: region 1:
9466 01:24:39.536682 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9467 01:24:39.539789 WARNING: region 2:
9468 01:24:39.543103 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9469 01:24:39.546948 WARNING: region 3:
9470 01:24:39.549755 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 01:24:39.553293 WARNING: region 4:
9472 01:24:39.559733 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 01:24:39.559861 WARNING: region 5:
9474 01:24:39.563200 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 01:24:39.566459 WARNING: region 6:
9476 01:24:39.569727 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 01:24:39.573299 WARNING: region 7:
9478 01:24:39.576763 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 01:24:39.583190 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9480 01:24:39.586927 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9481 01:24:39.589947 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9482 01:24:39.596290 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9483 01:24:39.599725 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9484 01:24:39.603118 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9485 01:24:39.609796 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9486 01:24:39.613557 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9487 01:24:39.616473 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9488 01:24:39.623437 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9489 01:24:39.626576 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9490 01:24:39.633538 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9491 01:24:39.636741 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9492 01:24:39.640236 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9493 01:24:39.646890 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9494 01:24:39.650170 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9495 01:24:39.653437 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9496 01:24:39.660682 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9497 01:24:39.663488 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9498 01:24:39.667047 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9499 01:24:39.673344 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9500 01:24:39.676775 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9501 01:24:39.683631 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9502 01:24:39.686782 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9503 01:24:39.693484 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9504 01:24:39.696585 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9505 01:24:39.699979 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9506 01:24:39.706891 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9507 01:24:39.710087 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9508 01:24:39.713328 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9509 01:24:39.719922 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9510 01:24:39.723505 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9511 01:24:39.726811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9512 01:24:39.733588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9513 01:24:39.736710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9514 01:24:39.740208 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9515 01:24:39.743384 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9516 01:24:39.750238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9517 01:24:39.753456 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9518 01:24:39.756757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9519 01:24:39.760331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9520 01:24:39.766872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9521 01:24:39.770096 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9522 01:24:39.773612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9523 01:24:39.776961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9524 01:24:39.783529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9525 01:24:39.786972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9526 01:24:39.790376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9527 01:24:39.796843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9528 01:24:39.800286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9529 01:24:39.803577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9530 01:24:39.810322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9531 01:24:39.813823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9532 01:24:39.820384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9533 01:24:39.823531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9534 01:24:39.830369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9535 01:24:39.833803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9536 01:24:39.836939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9537 01:24:39.843885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9538 01:24:39.847389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9539 01:24:39.853790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9540 01:24:39.857117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9541 01:24:39.863644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9542 01:24:39.867019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9543 01:24:39.870336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9544 01:24:39.877064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9545 01:24:39.881069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9546 01:24:39.887248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9547 01:24:39.890663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9548 01:24:39.897561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9549 01:24:39.900535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9550 01:24:39.904095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9551 01:24:39.910638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9552 01:24:39.913997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9553 01:24:39.920903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9554 01:24:39.923976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9555 01:24:39.927841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9556 01:24:39.934074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9557 01:24:39.937465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9558 01:24:39.944274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9559 01:24:39.947661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9560 01:24:39.954406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9561 01:24:39.957382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9562 01:24:39.964071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9563 01:24:39.967364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9564 01:24:39.970556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9565 01:24:39.977260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9566 01:24:39.980636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9567 01:24:39.987427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9568 01:24:39.990472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9569 01:24:39.997089 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9570 01:24:40.000737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9571 01:24:40.003836 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9572 01:24:40.010560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9573 01:24:40.014152 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9574 01:24:40.020735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9575 01:24:40.023934 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9576 01:24:40.027318 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9577 01:24:40.033894 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9578 01:24:40.037240 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9579 01:24:40.040521 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9580 01:24:40.043718 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9581 01:24:40.050562 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9582 01:24:40.054169 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9583 01:24:40.060609 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9584 01:24:40.063776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9585 01:24:40.067137 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9586 01:24:40.073769 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9587 01:24:40.077233 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9588 01:24:40.084159 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9589 01:24:40.087599 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9590 01:24:40.090799 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9591 01:24:40.097293 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9592 01:24:40.100588 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9593 01:24:40.107285 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9594 01:24:40.110696 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9595 01:24:40.113956 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9596 01:24:40.117648 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9597 01:24:40.123987 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9598 01:24:40.127477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9599 01:24:40.130811 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9600 01:24:40.134500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9601 01:24:40.140764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9602 01:24:40.144502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9603 01:24:40.147821 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9604 01:24:40.154570 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9605 01:24:40.157664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9606 01:24:40.161276 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9607 01:24:40.167664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9608 01:24:40.170895 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9609 01:24:40.177604 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9610 01:24:40.181103 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9611 01:24:40.184917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9612 01:24:40.190769 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9613 01:24:40.194388 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9614 01:24:40.201356 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9615 01:24:40.204231 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9616 01:24:40.207552 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9617 01:24:40.214459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9618 01:24:40.217624 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9619 01:24:40.224638 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9620 01:24:40.227555 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9621 01:24:40.231086 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9622 01:24:40.237319 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9623 01:24:40.241023 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9624 01:24:40.244644 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9625 01:24:40.250755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9626 01:24:40.254213 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9627 01:24:40.261134 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9628 01:24:40.264210 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9629 01:24:40.267557 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9630 01:24:40.274518 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9631 01:24:40.278148 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9632 01:24:40.280926 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9633 01:24:40.287781 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9634 01:24:40.291144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9635 01:24:40.297710 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9636 01:24:40.301562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9637 01:24:40.304210 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9638 01:24:40.310968 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9639 01:24:40.314449 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9640 01:24:40.321235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9641 01:24:40.324710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9642 01:24:40.327748 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9643 01:24:40.334392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9644 01:24:40.337764 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9645 01:24:40.341199 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9646 01:24:40.347983 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9647 01:24:40.351011 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9648 01:24:40.357431 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9649 01:24:40.361321 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9650 01:24:40.367860 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9651 01:24:40.370738 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9652 01:24:40.374078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9653 01:24:40.380594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9654 01:24:40.383895 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9655 01:24:40.387232 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9656 01:24:40.393979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9657 01:24:40.397460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9658 01:24:40.404095 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9659 01:24:40.407229 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9660 01:24:40.410756 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9661 01:24:40.417630 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9662 01:24:40.420708 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9663 01:24:40.427289 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9664 01:24:40.430748 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9665 01:24:40.433995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9666 01:24:40.440603 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9667 01:24:40.443769 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9668 01:24:40.450545 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9669 01:24:40.453854 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9670 01:24:40.457201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9671 01:24:40.464035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9672 01:24:40.467599 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9673 01:24:40.473889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9674 01:24:40.477002 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9675 01:24:40.480666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9676 01:24:40.487138 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9677 01:24:40.490188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9678 01:24:40.496821 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9679 01:24:40.500263 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9680 01:24:40.507157 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9681 01:24:40.510218 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9682 01:24:40.513368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9683 01:24:40.519993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9684 01:24:40.523347 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9685 01:24:40.530071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9686 01:24:40.533549 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9687 01:24:40.536678 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9688 01:24:40.543516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9689 01:24:40.546814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9690 01:24:40.553551 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9691 01:24:40.556677 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9692 01:24:40.563156 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9693 01:24:40.566476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9694 01:24:40.570072 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9695 01:24:40.576848 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9696 01:24:40.579917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9697 01:24:40.586575 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9698 01:24:40.589810 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9699 01:24:40.596590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9700 01:24:40.599951 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9701 01:24:40.603237 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9702 01:24:40.609666 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9703 01:24:40.613246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9704 01:24:40.619476 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9705 01:24:40.622966 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9706 01:24:40.626360 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9707 01:24:40.633082 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9708 01:24:40.636484 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9709 01:24:40.639405 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9710 01:24:40.642884 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9711 01:24:40.649584 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9712 01:24:40.653054 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9713 01:24:40.656088 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9714 01:24:40.662654 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9715 01:24:40.666201 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9716 01:24:40.672719 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9717 01:24:40.676502 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9718 01:24:40.680046 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9719 01:24:40.686681 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9720 01:24:40.689385 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9721 01:24:40.692823 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9722 01:24:40.699393 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9723 01:24:40.702824 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9724 01:24:40.706503 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9725 01:24:40.712971 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9726 01:24:40.716364 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9727 01:24:40.719307 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9728 01:24:40.726458 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9729 01:24:40.729988 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9730 01:24:40.735829 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9731 01:24:40.739231 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9732 01:24:40.742761 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9733 01:24:40.749174 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9734 01:24:40.752548 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9735 01:24:40.755785 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9736 01:24:40.762633 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9737 01:24:40.765713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9738 01:24:40.769318 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9739 01:24:40.775769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9740 01:24:40.779082 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9741 01:24:40.786046 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9742 01:24:40.789053 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9743 01:24:40.792416 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9744 01:24:40.798947 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9745 01:24:40.802525 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9746 01:24:40.805919 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9747 01:24:40.812382 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9748 01:24:40.816408 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9749 01:24:40.819115 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9750 01:24:40.822228 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9751 01:24:40.825718 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9752 01:24:40.832271 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9753 01:24:40.835691 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9754 01:24:40.838814 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9755 01:24:40.842316 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9756 01:24:40.848936 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9757 01:24:40.852454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9758 01:24:40.855524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9759 01:24:40.862173 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9760 01:24:40.865580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9761 01:24:40.868629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9762 01:24:40.875259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9763 01:24:40.878765 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9764 01:24:40.885418 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9765 01:24:40.888544 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9766 01:24:40.891695 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9767 01:24:40.898465 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9768 01:24:40.901894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9769 01:24:40.908723 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9770 01:24:40.911619 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9771 01:24:40.915067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9772 01:24:40.921545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9773 01:24:40.925306 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9774 01:24:40.931812 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9775 01:24:40.934645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9776 01:24:40.938148 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9777 01:24:40.944757 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9778 01:24:40.947962 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9779 01:24:40.954493 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9780 01:24:40.958070 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9781 01:24:40.964472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9782 01:24:40.967756 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9783 01:24:40.971352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9784 01:24:40.977891 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9785 01:24:40.981217 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9786 01:24:40.988079 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9787 01:24:40.991042 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9788 01:24:40.994770 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9789 01:24:41.001303 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9790 01:24:41.004417 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9791 01:24:41.011002 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9792 01:24:41.014352 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9793 01:24:41.017739 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9794 01:24:41.024311 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9795 01:24:41.027581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9796 01:24:41.034503 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9797 01:24:41.037557 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9798 01:24:41.044191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9799 01:24:41.047525 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9800 01:24:41.050936 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9801 01:24:41.057607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9802 01:24:41.060840 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9803 01:24:41.067740 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9804 01:24:41.070736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9805 01:24:41.074276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9806 01:24:41.081093 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9807 01:24:41.084138 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9808 01:24:41.090793 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9809 01:24:41.094076 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9810 01:24:41.097521 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9811 01:24:41.104135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9812 01:24:41.107446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9813 01:24:41.114217 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9814 01:24:41.117641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9815 01:24:41.124062 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9816 01:24:41.127455 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9817 01:24:41.130590 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9818 01:24:41.137281 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9819 01:24:41.140444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9820 01:24:41.147169 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9821 01:24:41.150371 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9822 01:24:41.153805 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9823 01:24:41.160233 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9824 01:24:41.163574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9825 01:24:41.167241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9826 01:24:41.174075 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9827 01:24:41.177168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9828 01:24:41.183728 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9829 01:24:41.186860 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9830 01:24:41.193927 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9831 01:24:41.197534 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9832 01:24:41.200315 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9833 01:24:41.206727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9834 01:24:41.210237 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9835 01:24:41.216875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9836 01:24:41.220042 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9837 01:24:41.226697 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9838 01:24:41.230010 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9839 01:24:41.236605 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9840 01:24:41.240226 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9841 01:24:41.243611 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9842 01:24:41.250161 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9843 01:24:41.253101 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9844 01:24:41.259911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9845 01:24:41.263572 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9846 01:24:41.270085 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9847 01:24:41.273026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9848 01:24:41.276511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9849 01:24:41.283266 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9850 01:24:41.286705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9851 01:24:41.293359 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9852 01:24:41.297010 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9853 01:24:41.303132 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9854 01:24:41.306436 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9855 01:24:41.313550 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9856 01:24:41.316243 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9857 01:24:41.319696 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9858 01:24:41.326323 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9859 01:24:41.329605 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9860 01:24:41.336583 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9861 01:24:41.339767 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9862 01:24:41.343143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9863 01:24:41.349908 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9864 01:24:41.353157 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9865 01:24:41.359835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9866 01:24:41.362921 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9867 01:24:41.369550 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9868 01:24:41.372961 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9869 01:24:41.379749 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9870 01:24:41.382826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9871 01:24:41.385958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9872 01:24:41.393030 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9873 01:24:41.396190 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9874 01:24:41.402844 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9875 01:24:41.406537 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9876 01:24:41.409594 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9877 01:24:41.416136 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9878 01:24:41.419360 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9879 01:24:41.426246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9880 01:24:41.430087 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9881 01:24:41.432874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9882 01:24:41.439452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9883 01:24:41.442930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9884 01:24:41.449468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9885 01:24:41.452771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9886 01:24:41.459383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9887 01:24:41.462611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9888 01:24:41.469189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9889 01:24:41.472544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9890 01:24:41.479446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9891 01:24:41.482754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9892 01:24:41.489712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9893 01:24:41.492702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9894 01:24:41.499286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9895 01:24:41.502715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9896 01:24:41.509194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9897 01:24:41.512722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9898 01:24:41.519171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9899 01:24:41.522659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9900 01:24:41.528972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9901 01:24:41.532534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9902 01:24:41.539364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9903 01:24:41.542405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9904 01:24:41.548827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9905 01:24:41.552185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9906 01:24:41.558971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9907 01:24:41.562269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9908 01:24:41.568827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9909 01:24:41.572124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9910 01:24:41.578787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9911 01:24:41.582017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9912 01:24:41.588699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9913 01:24:41.592229 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9914 01:24:41.592360 INFO: [APUAPC] vio 0
9915 01:24:41.600334 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9916 01:24:41.602864 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9917 01:24:41.606434 INFO: [APUAPC] D0_APC_0: 0x400510
9918 01:24:41.609575 INFO: [APUAPC] D0_APC_1: 0x0
9919 01:24:41.612778 INFO: [APUAPC] D0_APC_2: 0x1540
9920 01:24:41.616200 INFO: [APUAPC] D0_APC_3: 0x0
9921 01:24:41.619610 INFO: [APUAPC] D1_APC_0: 0xffffffff
9922 01:24:41.622715 INFO: [APUAPC] D1_APC_1: 0xffffffff
9923 01:24:41.626029 INFO: [APUAPC] D1_APC_2: 0x3fffff
9924 01:24:41.629479 INFO: [APUAPC] D1_APC_3: 0x0
9925 01:24:41.632861 INFO: [APUAPC] D2_APC_0: 0xffffffff
9926 01:24:41.636107 INFO: [APUAPC] D2_APC_1: 0xffffffff
9927 01:24:41.639547 INFO: [APUAPC] D2_APC_2: 0x3fffff
9928 01:24:41.643052 INFO: [APUAPC] D2_APC_3: 0x0
9929 01:24:41.646098 INFO: [APUAPC] D3_APC_0: 0xffffffff
9930 01:24:41.649538 INFO: [APUAPC] D3_APC_1: 0xffffffff
9931 01:24:41.652969 INFO: [APUAPC] D3_APC_2: 0x3fffff
9932 01:24:41.656218 INFO: [APUAPC] D3_APC_3: 0x0
9933 01:24:41.659327 INFO: [APUAPC] D4_APC_0: 0xffffffff
9934 01:24:41.662703 INFO: [APUAPC] D4_APC_1: 0xffffffff
9935 01:24:41.666117 INFO: [APUAPC] D4_APC_2: 0x3fffff
9936 01:24:41.666241 INFO: [APUAPC] D4_APC_3: 0x0
9937 01:24:41.669896 INFO: [APUAPC] D5_APC_0: 0xffffffff
9938 01:24:41.676870 INFO: [APUAPC] D5_APC_1: 0xffffffff
9939 01:24:41.677006 INFO: [APUAPC] D5_APC_2: 0x3fffff
9940 01:24:41.679176 INFO: [APUAPC] D5_APC_3: 0x0
9941 01:24:41.682805 INFO: [APUAPC] D6_APC_0: 0xffffffff
9942 01:24:41.685944 INFO: [APUAPC] D6_APC_1: 0xffffffff
9943 01:24:41.689241 INFO: [APUAPC] D6_APC_2: 0x3fffff
9944 01:24:41.692381 INFO: [APUAPC] D6_APC_3: 0x0
9945 01:24:41.695962 INFO: [APUAPC] D7_APC_0: 0xffffffff
9946 01:24:41.699289 INFO: [APUAPC] D7_APC_1: 0xffffffff
9947 01:24:41.702422 INFO: [APUAPC] D7_APC_2: 0x3fffff
9948 01:24:41.705954 INFO: [APUAPC] D7_APC_3: 0x0
9949 01:24:41.709312 INFO: [APUAPC] D8_APC_0: 0xffffffff
9950 01:24:41.712456 INFO: [APUAPC] D8_APC_1: 0xffffffff
9951 01:24:41.716012 INFO: [APUAPC] D8_APC_2: 0x3fffff
9952 01:24:41.719355 INFO: [APUAPC] D8_APC_3: 0x0
9953 01:24:41.722618 INFO: [APUAPC] D9_APC_0: 0xffffffff
9954 01:24:41.725884 INFO: [APUAPC] D9_APC_1: 0xffffffff
9955 01:24:41.729052 INFO: [APUAPC] D9_APC_2: 0x3fffff
9956 01:24:41.732617 INFO: [APUAPC] D9_APC_3: 0x0
9957 01:24:41.735708 INFO: [APUAPC] D10_APC_0: 0xffffffff
9958 01:24:41.739224 INFO: [APUAPC] D10_APC_1: 0xffffffff
9959 01:24:41.742393 INFO: [APUAPC] D10_APC_2: 0x3fffff
9960 01:24:41.745964 INFO: [APUAPC] D10_APC_3: 0x0
9961 01:24:41.749092 INFO: [APUAPC] D11_APC_0: 0xffffffff
9962 01:24:41.752350 INFO: [APUAPC] D11_APC_1: 0xffffffff
9963 01:24:41.755606 INFO: [APUAPC] D11_APC_2: 0x3fffff
9964 01:24:41.759074 INFO: [APUAPC] D11_APC_3: 0x0
9965 01:24:41.762333 INFO: [APUAPC] D12_APC_0: 0xffffffff
9966 01:24:41.765995 INFO: [APUAPC] D12_APC_1: 0xffffffff
9967 01:24:41.768921 INFO: [APUAPC] D12_APC_2: 0x3fffff
9968 01:24:41.772562 INFO: [APUAPC] D12_APC_3: 0x0
9969 01:24:41.775523 INFO: [APUAPC] D13_APC_0: 0xffffffff
9970 01:24:41.778812 INFO: [APUAPC] D13_APC_1: 0xffffffff
9971 01:24:41.782067 INFO: [APUAPC] D13_APC_2: 0x3fffff
9972 01:24:41.785561 INFO: [APUAPC] D13_APC_3: 0x0
9973 01:24:41.788856 INFO: [APUAPC] D14_APC_0: 0xffffffff
9974 01:24:41.792281 INFO: [APUAPC] D14_APC_1: 0xffffffff
9975 01:24:41.795676 INFO: [APUAPC] D14_APC_2: 0x3fffff
9976 01:24:41.798790 INFO: [APUAPC] D14_APC_3: 0x0
9977 01:24:41.802440 INFO: [APUAPC] D15_APC_0: 0xffffffff
9978 01:24:41.805524 INFO: [APUAPC] D15_APC_1: 0xffffffff
9979 01:24:41.808810 INFO: [APUAPC] D15_APC_2: 0x3fffff
9980 01:24:41.812186 INFO: [APUAPC] D15_APC_3: 0x0
9981 01:24:41.815894 INFO: [APUAPC] APC_CON: 0x4
9982 01:24:41.818813 INFO: [NOCDAPC] D0_APC_0: 0x0
9983 01:24:41.822069 INFO: [NOCDAPC] D0_APC_1: 0x0
9984 01:24:41.825830 INFO: [NOCDAPC] D1_APC_0: 0x0
9985 01:24:41.829029 INFO: [NOCDAPC] D1_APC_1: 0xfff
9986 01:24:41.829164 INFO: [NOCDAPC] D2_APC_0: 0x0
9987 01:24:41.831973 INFO: [NOCDAPC] D2_APC_1: 0xfff
9988 01:24:41.835613 INFO: [NOCDAPC] D3_APC_0: 0x0
9989 01:24:41.838707 INFO: [NOCDAPC] D3_APC_1: 0xfff
9990 01:24:41.842025 INFO: [NOCDAPC] D4_APC_0: 0x0
9991 01:24:41.845514 INFO: [NOCDAPC] D4_APC_1: 0xfff
9992 01:24:41.848629 INFO: [NOCDAPC] D5_APC_0: 0x0
9993 01:24:41.851998 INFO: [NOCDAPC] D5_APC_1: 0xfff
9994 01:24:41.855740 INFO: [NOCDAPC] D6_APC_0: 0x0
9995 01:24:41.858654 INFO: [NOCDAPC] D6_APC_1: 0xfff
9996 01:24:41.862667 INFO: [NOCDAPC] D7_APC_0: 0x0
9997 01:24:41.862756 INFO: [NOCDAPC] D7_APC_1: 0xfff
9998 01:24:41.865350 INFO: [NOCDAPC] D8_APC_0: 0x0
9999 01:24:41.868557 INFO: [NOCDAPC] D8_APC_1: 0xfff
10000 01:24:41.872112 INFO: [NOCDAPC] D9_APC_0: 0x0
10001 01:24:41.875610 INFO: [NOCDAPC] D9_APC_1: 0xfff
10002 01:24:41.878617 INFO: [NOCDAPC] D10_APC_0: 0x0
10003 01:24:41.881907 INFO: [NOCDAPC] D10_APC_1: 0xfff
10004 01:24:41.885098 INFO: [NOCDAPC] D11_APC_0: 0x0
10005 01:24:41.888348 INFO: [NOCDAPC] D11_APC_1: 0xfff
10006 01:24:41.891867 INFO: [NOCDAPC] D12_APC_0: 0x0
10007 01:24:41.895129 INFO: [NOCDAPC] D12_APC_1: 0xfff
10008 01:24:41.898119 INFO: [NOCDAPC] D13_APC_0: 0x0
10009 01:24:41.901412 INFO: [NOCDAPC] D13_APC_1: 0xfff
10010 01:24:41.905089 INFO: [NOCDAPC] D14_APC_0: 0x0
10011 01:24:41.905228 INFO: [NOCDAPC] D14_APC_1: 0xfff
10012 01:24:41.908104 INFO: [NOCDAPC] D15_APC_0: 0x0
10013 01:24:41.911488 INFO: [NOCDAPC] D15_APC_1: 0xfff
10014 01:24:41.914725 INFO: [NOCDAPC] APC_CON: 0x4
10015 01:24:41.918302 INFO: [APUAPC] set_apusys_apc done
10016 01:24:41.921347 INFO: [DEVAPC] devapc_init done
10017 01:24:41.924900 INFO: GICv3 without legacy support detected.
10018 01:24:41.931424 INFO: ARM GICv3 driver initialized in EL3
10019 01:24:41.934802 INFO: Maximum SPI INTID supported: 639
10020 01:24:41.938146 INFO: BL31: Initializing runtime services
10021 01:24:41.944837 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10022 01:24:41.948144 INFO: SPM: enable CPC mode
10023 01:24:41.951267 INFO: mcdi ready for mcusys-off-idle and system suspend
10024 01:24:41.957873 INFO: BL31: Preparing for EL3 exit to normal world
10025 01:24:41.961390 INFO: Entry point address = 0x80000000
10026 01:24:41.961523 INFO: SPSR = 0x8
10027 01:24:41.967706
10028 01:24:41.967818
10029 01:24:41.967915
10030 01:24:41.971082 Starting depthcharge on Spherion...
10031 01:24:41.971198
10032 01:24:41.971290 Wipe memory regions:
10033 01:24:41.971365
10034 01:24:41.972009 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10035 01:24:41.972158 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10036 01:24:41.972276 Setting prompt string to ['asurada:']
10037 01:24:41.972387 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10038 01:24:41.974481 [0x00000040000000, 0x00000054600000)
10039 01:24:42.096727
10040 01:24:42.096920 [0x00000054660000, 0x00000080000000)
10041 01:24:42.357526
10042 01:24:42.357682 [0x000000821a7280, 0x000000ffe64000)
10043 01:24:43.102214
10044 01:24:43.102361 [0x00000100000000, 0x00000240000000)
10045 01:24:44.992748
10046 01:24:44.995999 Initializing XHCI USB controller at 0x11200000.
10047 01:24:46.034466
10048 01:24:46.037523 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10049 01:24:46.037612
10050 01:24:46.037679
10051 01:24:46.037743
10052 01:24:46.038024 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 01:24:46.138322 asurada: tftpboot 192.168.201.1 11368530/tftp-deploy-8rmbjqvi/kernel/image.itb 11368530/tftp-deploy-8rmbjqvi/kernel/cmdline
10055 01:24:46.138473 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 01:24:46.138590 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10057 01:24:46.142714 tftpboot 192.168.201.1 11368530/tftp-deploy-8rmbjqvi/kernel/image.ittp-deploy-8rmbjqvi/kernel/cmdline
10058 01:24:46.142818
10059 01:24:46.142916 Waiting for link
10060 01:24:46.303017
10061 01:24:46.303203 R8152: Initializing
10062 01:24:46.303321
10063 01:24:46.306608 Version 9 (ocp_data = 6010)
10064 01:24:46.306733
10065 01:24:46.309394 R8152: Done initializing
10066 01:24:46.309518
10067 01:24:46.309632 Adding net device
10068 01:24:48.192546
10069 01:24:48.192808 done.
10070 01:24:48.192987
10071 01:24:48.193127 MAC: 00:e0:4c:72:2d:d6
10072 01:24:48.193268
10073 01:24:48.196116 Sending DHCP discover... done.
10074 01:24:48.196243
10075 01:24:48.199288 Waiting for reply... done.
10076 01:24:48.199414
10077 01:24:48.202560 Sending DHCP request... done.
10078 01:24:48.202710
10079 01:24:48.202851 Waiting for reply... done.
10080 01:24:48.202972
10081 01:24:48.206132 My ip is 192.168.201.21
10082 01:24:48.206251
10083 01:24:48.209165 The DHCP server ip is 192.168.201.1
10084 01:24:48.209289
10085 01:24:48.212537 TFTP server IP predefined by user: 192.168.201.1
10086 01:24:48.212661
10087 01:24:48.219339 Bootfile predefined by user: 11368530/tftp-deploy-8rmbjqvi/kernel/image.itb
10088 01:24:48.219464
10089 01:24:48.222654 Sending tftp read request... done.
10090 01:24:48.222776
10091 01:24:48.225833 Waiting for the transfer...
10092 01:24:48.225938
10093 01:24:48.519543 00000000 ################################################################
10094 01:24:48.519689
10095 01:24:48.814507 00080000 ################################################################
10096 01:24:48.814653
10097 01:24:49.110843 00100000 ################################################################
10098 01:24:49.110990
10099 01:24:49.405058 00180000 ################################################################
10100 01:24:49.405269
10101 01:24:49.680877 00200000 ################################################################
10102 01:24:49.681026
10103 01:24:49.975479 00280000 ################################################################
10104 01:24:49.975689
10105 01:24:50.260023 00300000 ################################################################
10106 01:24:50.260178
10107 01:24:50.521121 00380000 ################################################################
10108 01:24:50.521265
10109 01:24:50.786271 00400000 ################################################################
10110 01:24:50.786408
10111 01:24:51.068245 00480000 ################################################################
10112 01:24:51.068398
10113 01:24:51.366667 00500000 ################################################################
10114 01:24:51.366809
10115 01:24:51.662654 00580000 ################################################################
10116 01:24:51.662792
10117 01:24:51.946204 00600000 ################################################################
10118 01:24:51.946353
10119 01:24:52.225521 00680000 ################################################################
10120 01:24:52.225661
10121 01:24:52.494530 00700000 ################################################################
10122 01:24:52.494680
10123 01:24:52.767527 00780000 ################################################################
10124 01:24:52.767682
10125 01:24:53.036150 00800000 ################################################################
10126 01:24:53.036288
10127 01:24:53.312309 00880000 ################################################################
10128 01:24:53.312447
10129 01:24:53.574955 00900000 ################################################################
10130 01:24:53.575118
10131 01:24:53.852664 00980000 ################################################################
10132 01:24:53.852890
10133 01:24:54.126677 00a00000 ################################################################
10134 01:24:54.126860
10135 01:24:54.415739 00a80000 ################################################################
10136 01:24:54.415889
10137 01:24:54.696622 00b00000 ################################################################
10138 01:24:54.696765
10139 01:24:54.972196 00b80000 ################################################################
10140 01:24:54.972384
10141 01:24:55.244122 00c00000 ################################################################
10142 01:24:55.244273
10143 01:24:55.502011 00c80000 ################################################################
10144 01:24:55.502148
10145 01:24:55.764555 00d00000 ################################################################
10146 01:24:55.764744
10147 01:24:56.022340 00d80000 ################################################################
10148 01:24:56.022475
10149 01:24:56.291734 00e00000 ################################################################
10150 01:24:56.291920
10151 01:24:56.551454 00e80000 ################################################################
10152 01:24:56.551589
10153 01:24:56.821370 00f00000 ################################################################
10154 01:24:56.821506
10155 01:24:57.077241 00f80000 ################################################################
10156 01:24:57.077381
10157 01:24:57.340632 01000000 ################################################################
10158 01:24:57.340802
10159 01:24:57.602833 01080000 ################################################################
10160 01:24:57.602971
10161 01:24:57.864076 01100000 ################################################################
10162 01:24:57.864235
10163 01:24:58.128163 01180000 ################################################################
10164 01:24:58.128300
10165 01:24:58.392968 01200000 ################################################################
10166 01:24:58.393175
10167 01:24:58.649297 01280000 ################################################################
10168 01:24:58.649458
10169 01:24:58.927191 01300000 ################################################################
10170 01:24:58.927340
10171 01:24:59.200138 01380000 ################################################################
10172 01:24:59.200290
10173 01:24:59.453837 01400000 ################################################################
10174 01:24:59.453980
10175 01:24:59.706556 01480000 ################################################################
10176 01:24:59.706691
10177 01:24:59.956350 01500000 ################################################################
10178 01:24:59.956485
10179 01:25:00.211849 01580000 ################################################################
10180 01:25:00.211985
10181 01:25:00.470432 01600000 ################################################################
10182 01:25:00.470591
10183 01:25:00.724420 01680000 ################################################################
10184 01:25:00.724551
10185 01:25:00.981020 01700000 ################################################################
10186 01:25:00.981192
10187 01:25:01.236780 01780000 ################################################################
10188 01:25:01.236918
10189 01:25:01.493154 01800000 ################################################################
10190 01:25:01.493290
10191 01:25:01.745664 01880000 ################################################################
10192 01:25:01.745805
10193 01:25:01.999435 01900000 ################################################################
10194 01:25:01.999601
10195 01:25:02.256655 01980000 ################################################################
10196 01:25:02.256804
10197 01:25:02.513328 01a00000 ################################################################
10198 01:25:02.513524
10199 01:25:02.774748 01a80000 ################################################################
10200 01:25:02.774913
10201 01:25:03.029883 01b00000 ################################################################
10202 01:25:03.030032
10203 01:25:03.280696 01b80000 ################################################################
10204 01:25:03.280871
10205 01:25:03.534466 01c00000 ################################################################
10206 01:25:03.534653
10207 01:25:03.795166 01c80000 ################################################################
10208 01:25:03.795341
10209 01:25:04.053470 01d00000 ################################################################
10210 01:25:04.053647
10211 01:25:04.308030 01d80000 ################################################################
10212 01:25:04.308178
10213 01:25:04.567749 01e00000 ################################################################
10214 01:25:04.567957
10215 01:25:04.822663 01e80000 ################################################################
10216 01:25:04.822874
10217 01:25:05.075845 01f00000 ################################################################
10218 01:25:05.076005
10219 01:25:05.331220 01f80000 ################################################################
10220 01:25:05.331392
10221 01:25:05.588681 02000000 ################################################################
10222 01:25:05.588859
10223 01:25:05.850232 02080000 ################################################################
10224 01:25:05.850381
10225 01:25:06.107809 02100000 ################################################################
10226 01:25:06.107958
10227 01:25:06.366300 02180000 ################################################################
10228 01:25:06.366448
10229 01:25:06.625151 02200000 ################################################################
10230 01:25:06.625355
10231 01:25:06.888643 02280000 ################################################################
10232 01:25:06.888800
10233 01:25:07.143284 02300000 ################################################################
10234 01:25:07.143432
10235 01:25:07.407453 02380000 ################################################################
10236 01:25:07.407655
10237 01:25:07.667433 02400000 ################################################################
10238 01:25:07.667618
10239 01:25:07.928922 02480000 ################################################################
10240 01:25:07.929096
10241 01:25:08.189981 02500000 ################################################################
10242 01:25:08.190192
10243 01:25:08.450389 02580000 ################################################################
10244 01:25:08.450598
10245 01:25:08.707296 02600000 ################################################################
10246 01:25:08.707447
10247 01:25:08.956458 02680000 ################################################################
10248 01:25:08.956612
10249 01:25:09.205961 02700000 ################################################################
10250 01:25:09.206145
10251 01:25:09.454400 02780000 ################################################################
10252 01:25:09.454557
10253 01:25:09.711491 02800000 ################################################################
10254 01:25:09.711669
10255 01:25:09.972580 02880000 ################################################################
10256 01:25:09.972780
10257 01:25:10.240457 02900000 ################################################################
10258 01:25:10.240603
10259 01:25:10.494642 02980000 ################################################################
10260 01:25:10.494826
10261 01:25:10.751490 02a00000 ################################################################
10262 01:25:10.751637
10263 01:25:11.015438 02a80000 ################################################################
10264 01:25:11.015648
10265 01:25:11.270481 02b00000 ################################################################
10266 01:25:11.270632
10267 01:25:11.531166 02b80000 ################################################################
10268 01:25:11.531363
10269 01:25:11.796130 02c00000 ################################################################
10270 01:25:11.796277
10271 01:25:12.064598 02c80000 ################################################################
10272 01:25:12.064780
10273 01:25:12.325324 02d00000 ################################################################
10274 01:25:12.325505
10275 01:25:12.581564 02d80000 ################################################################
10276 01:25:12.581714
10277 01:25:12.848118 02e00000 ################################################################
10278 01:25:12.848318
10279 01:25:13.116473 02e80000 ################################################################
10280 01:25:13.116650
10281 01:25:13.376934 02f00000 ################################################################
10282 01:25:13.377136
10283 01:25:13.637503 02f80000 ################################################################
10284 01:25:13.637648
10285 01:25:13.900860 03000000 ################################################################
10286 01:25:13.901033
10287 01:25:14.161227 03080000 ################################################################
10288 01:25:14.161370
10289 01:25:14.422112 03100000 ################################################################
10290 01:25:14.422314
10291 01:25:14.675529 03180000 ################################################################
10292 01:25:14.675689
10293 01:25:14.925168 03200000 ################################################################
10294 01:25:14.925320
10295 01:25:15.174636 03280000 ################################################################
10296 01:25:15.174794
10297 01:25:15.425302 03300000 ################################################################
10298 01:25:15.425458
10299 01:25:15.679566 03380000 ################################################################
10300 01:25:15.679729
10301 01:25:15.937520 03400000 ################################################################
10302 01:25:15.937689
10303 01:25:16.199246 03480000 ################################################################
10304 01:25:16.199418
10305 01:25:16.455794 03500000 ################################################################
10306 01:25:16.455934
10307 01:25:16.711462 03580000 ################################################################
10308 01:25:16.711602
10309 01:25:16.975993 03600000 ################################################################
10310 01:25:16.976134
10311 01:25:17.244619 03680000 ################################################################
10312 01:25:17.244820
10313 01:25:17.507085 03700000 ################################################################
10314 01:25:17.507258
10315 01:25:17.711122 03780000 ################################################## done.
10316 01:25:17.711264
10317 01:25:17.714657 The bootfile was 58600622 bytes long.
10318 01:25:17.714743
10319 01:25:17.718460 Sending tftp read request... done.
10320 01:25:17.718547
10321 01:25:17.721274 Waiting for the transfer...
10322 01:25:17.721361
10323 01:25:17.721428 00000000 # done.
10324 01:25:17.721493
10325 01:25:17.731204 Command line loaded dynamically from TFTP file: 11368530/tftp-deploy-8rmbjqvi/kernel/cmdline
10326 01:25:17.731291
10327 01:25:17.744550 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10328 01:25:17.744640
10329 01:25:17.744724 Loading FIT.
10330 01:25:17.744827
10331 01:25:17.748564 Image ramdisk-1 has 47512644 bytes.
10332 01:25:17.748650
10333 01:25:17.751399 Image fdt-1 has 47278 bytes.
10334 01:25:17.751483
10335 01:25:17.754677 Image kernel-1 has 11038667 bytes.
10336 01:25:17.754762
10337 01:25:17.764757 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10338 01:25:17.764880
10339 01:25:17.781652 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10340 01:25:17.781744
10341 01:25:17.784919 Choosing best match conf-1 for compat google,spherion-rev2.
10342 01:25:17.790555
10343 01:25:17.794838 Connected to device vid:did:rid of 1ae0:0028:00
10344 01:25:17.801329
10345 01:25:17.805112 tpm_get_response: command 0x17b, return code 0x0
10346 01:25:17.805197
10347 01:25:17.808588 ec_init: CrosEC protocol v3 supported (256, 248)
10348 01:25:17.813524
10349 01:25:17.816911 tpm_cleanup: add release locality here.
10350 01:25:17.816996
10351 01:25:17.817064 Shutting down all USB controllers.
10352 01:25:17.820075
10353 01:25:17.820158 Removing current net device
10354 01:25:17.820226
10355 01:25:17.826913 Exiting depthcharge with code 4 at timestamp: 65175288
10356 01:25:17.826999
10357 01:25:17.830571 LZMA decompressing kernel-1 to 0x821a6718
10358 01:25:17.830667
10359 01:25:17.833357 LZMA decompressing kernel-1 to 0x40000000
10360 01:25:19.220110
10361 01:25:19.220285 jumping to kernel
10362 01:25:19.221044 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10363 01:25:19.221175 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10364 01:25:19.221280 Setting prompt string to ['Linux version [0-9]']
10365 01:25:19.221380 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10366 01:25:19.221479 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10367 01:25:19.301673
10368 01:25:19.305001 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10369 01:25:19.308571 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10370 01:25:19.308708 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10371 01:25:19.308868 Setting prompt string to []
10372 01:25:19.309000 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10373 01:25:19.309128 Using line separator: #'\n'#
10374 01:25:19.309239 No login prompt set.
10375 01:25:19.309357 Parsing kernel messages
10376 01:25:19.309467 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10377 01:25:19.309663 [login-action] Waiting for messages, (timeout 00:03:48)
10378 01:25:19.328315 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j24548-arm64-gcc-10-defconfig-arm64-chromebook-xnj4p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023
10379 01:25:19.331870 [ 0.000000] random: crng init done
10380 01:25:19.338298 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10381 01:25:19.338382 [ 0.000000] efi: UEFI not found.
10382 01:25:19.348299 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10383 01:25:19.354904 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10384 01:25:19.364705 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10385 01:25:19.374664 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10386 01:25:19.381211 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10387 01:25:19.388230 [ 0.000000] printk: bootconsole [mtk8250] enabled
10388 01:25:19.391506 [ 0.000000] NUMA: No NUMA configuration found
10389 01:25:19.401213 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10390 01:25:19.404389 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10391 01:25:19.407933 [ 0.000000] Zone ranges:
10392 01:25:19.414495 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10393 01:25:19.417885 [ 0.000000] DMA32 empty
10394 01:25:19.424588 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10395 01:25:19.428089 [ 0.000000] Movable zone start for each node
10396 01:25:19.431440 [ 0.000000] Early memory node ranges
10397 01:25:19.438014 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10398 01:25:19.444599 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10399 01:25:19.451098 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10400 01:25:19.454350 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10401 01:25:19.461073 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10402 01:25:19.467851 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10403 01:25:19.526669 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10404 01:25:19.532859 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10405 01:25:19.540308 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10406 01:25:19.542827 [ 0.000000] psci: probing for conduit method from DT.
10407 01:25:19.549621 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10408 01:25:19.553191 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10409 01:25:19.559331 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10410 01:25:19.562680 [ 0.000000] psci: SMC Calling Convention v1.2
10411 01:25:19.569361 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10412 01:25:19.572442 [ 0.000000] Detected VIPT I-cache on CPU0
10413 01:25:19.579238 [ 0.000000] CPU features: detected: GIC system register CPU interface
10414 01:25:19.586129 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10415 01:25:19.592823 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10416 01:25:19.599368 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10417 01:25:19.606526 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10418 01:25:19.612548 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10419 01:25:19.619662 [ 0.000000] alternatives: applying boot alternatives
10420 01:25:19.623157 [ 0.000000] Fallback order for Node 0: 0
10421 01:25:19.629307 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10422 01:25:19.632390 [ 0.000000] Policy zone: Normal
10423 01:25:19.649394 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10424 01:25:19.659123 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10425 01:25:19.670592 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10426 01:25:19.680520 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10427 01:25:19.686955 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10428 01:25:19.690222 <6>[ 0.000000] software IO TLB: area num 8.
10429 01:25:19.746845 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10430 01:25:19.895906 <6>[ 0.000000] Memory: 7923156K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 429612K reserved, 32768K cma-reserved)
10431 01:25:19.902527 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10432 01:25:19.909447 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10433 01:25:19.912780 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10434 01:25:19.919320 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10435 01:25:19.925989 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10436 01:25:19.929677 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10437 01:25:19.939122 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10438 01:25:19.945934 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10439 01:25:19.949073 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10440 01:25:19.956984 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10441 01:25:19.960213 <6>[ 0.000000] GICv3: 608 SPIs implemented
10442 01:25:19.966822 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10443 01:25:19.970147 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10444 01:25:19.973268 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10445 01:25:19.983474 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10446 01:25:19.993363 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10447 01:25:20.006631 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10448 01:25:20.013526 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10449 01:25:20.022371 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10450 01:25:20.035224 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10451 01:25:20.042253 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10452 01:25:20.048683 <6>[ 0.009182] Console: colour dummy device 80x25
10453 01:25:20.058952 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10454 01:25:20.062547 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10455 01:25:20.069130 <6>[ 0.029225] LSM: Security Framework initializing
10456 01:25:20.075383 <6>[ 0.034164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10457 01:25:20.085268 <6>[ 0.042025] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10458 01:25:20.091990 <6>[ 0.051353] cblist_init_generic: Setting adjustable number of callback queues.
10459 01:25:20.098839 <6>[ 0.058801] cblist_init_generic: Setting shift to 3 and lim to 1.
10460 01:25:20.109129 <6>[ 0.065140] cblist_init_generic: Setting adjustable number of callback queues.
10461 01:25:20.112129 <6>[ 0.072567] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 01:25:20.118900 <6>[ 0.078967] rcu: Hierarchical SRCU implementation.
10463 01:25:20.125301 <6>[ 0.083979] rcu: Max phase no-delay instances is 1000.
10464 01:25:20.131757 <6>[ 0.091017] EFI services will not be available.
10465 01:25:20.135040 <6>[ 0.095987] smp: Bringing up secondary CPUs ...
10466 01:25:20.143304 <6>[ 0.101069] Detected VIPT I-cache on CPU1
10467 01:25:20.149647 <6>[ 0.101141] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10468 01:25:20.156385 <6>[ 0.101171] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10469 01:25:20.160368 <6>[ 0.101504] Detected VIPT I-cache on CPU2
10470 01:25:20.166503 <6>[ 0.101553] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10471 01:25:20.173023 <6>[ 0.101568] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10472 01:25:20.179706 <6>[ 0.101832] Detected VIPT I-cache on CPU3
10473 01:25:20.186227 <6>[ 0.101879] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10474 01:25:20.193260 <6>[ 0.101892] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10475 01:25:20.196325 <6>[ 0.102199] CPU features: detected: Spectre-v4
10476 01:25:20.202859 <6>[ 0.102206] CPU features: detected: Spectre-BHB
10477 01:25:20.206508 <6>[ 0.102211] Detected PIPT I-cache on CPU4
10478 01:25:20.212858 <6>[ 0.102267] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10479 01:25:20.219722 <6>[ 0.102284] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10480 01:25:20.226450 <6>[ 0.102580] Detected PIPT I-cache on CPU5
10481 01:25:20.233262 <6>[ 0.102642] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10482 01:25:20.239373 <6>[ 0.102658] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10483 01:25:20.243066 <6>[ 0.102945] Detected PIPT I-cache on CPU6
10484 01:25:20.249420 <6>[ 0.103008] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10485 01:25:20.256732 <6>[ 0.103024] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10486 01:25:20.259551 <6>[ 0.103322] Detected PIPT I-cache on CPU7
10487 01:25:20.269684 <6>[ 0.103385] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10488 01:25:20.276360 <6>[ 0.103402] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10489 01:25:20.279638 <6>[ 0.103448] smp: Brought up 1 node, 8 CPUs
10490 01:25:20.282969 <6>[ 0.244759] SMP: Total of 8 processors activated.
10491 01:25:20.289778 <6>[ 0.249710] CPU features: detected: 32-bit EL0 Support
10492 01:25:20.299468 <6>[ 0.255072] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10493 01:25:20.306019 <6>[ 0.263872] CPU features: detected: Common not Private translations
10494 01:25:20.309264 <6>[ 0.270388] CPU features: detected: CRC32 instructions
10495 01:25:20.316152 <6>[ 0.275740] CPU features: detected: RCpc load-acquire (LDAPR)
10496 01:25:20.322910 <6>[ 0.281736] CPU features: detected: LSE atomic instructions
10497 01:25:20.329309 <6>[ 0.287553] CPU features: detected: Privileged Access Never
10498 01:25:20.332452 <6>[ 0.293332] CPU features: detected: RAS Extension Support
10499 01:25:20.339348 <6>[ 0.298941] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10500 01:25:20.345763 <6>[ 0.306162] CPU: All CPU(s) started at EL2
10501 01:25:20.352692 <6>[ 0.310478] alternatives: applying system-wide alternatives
10502 01:25:20.360610 <6>[ 0.321152] devtmpfs: initialized
10503 01:25:20.376317 <6>[ 0.330024] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10504 01:25:20.383305 <6>[ 0.339985] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10505 01:25:20.389498 <6>[ 0.348007] pinctrl core: initialized pinctrl subsystem
10506 01:25:20.392691 <6>[ 0.354643] DMI not present or invalid.
10507 01:25:20.399534 <6>[ 0.359055] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10508 01:25:20.409577 <6>[ 0.365908] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10509 01:25:20.415902 <6>[ 0.373490] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10510 01:25:20.425959 <6>[ 0.381711] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10511 01:25:20.429481 <6>[ 0.389955] audit: initializing netlink subsys (disabled)
10512 01:25:20.440182 <5>[ 0.395649] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10513 01:25:20.446114 <6>[ 0.396350] thermal_sys: Registered thermal governor 'step_wise'
10514 01:25:20.452654 <6>[ 0.403615] thermal_sys: Registered thermal governor 'power_allocator'
10515 01:25:20.455879 <6>[ 0.409869] cpuidle: using governor menu
10516 01:25:20.459241 <6>[ 0.420829] NET: Registered PF_QIPCRTR protocol family
10517 01:25:20.469183 <6>[ 0.426315] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10518 01:25:20.472368 <6>[ 0.433422] ASID allocator initialised with 32768 entries
10519 01:25:20.479560 <6>[ 0.439970] Serial: AMBA PL011 UART driver
10520 01:25:20.488240 <4>[ 0.448692] Trying to register duplicate clock ID: 134
10521 01:25:20.542273 <6>[ 0.505970] KASLR enabled
10522 01:25:20.556660 <6>[ 0.513647] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10523 01:25:20.563406 <6>[ 0.520659] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10524 01:25:20.570540 <6>[ 0.527149] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10525 01:25:20.576973 <6>[ 0.534156] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10526 01:25:20.583364 <6>[ 0.540643] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10527 01:25:20.589890 <6>[ 0.547647] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10528 01:25:20.596693 <6>[ 0.554135] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10529 01:25:20.603081 <6>[ 0.561139] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10530 01:25:20.606302 <6>[ 0.568585] ACPI: Interpreter disabled.
10531 01:25:20.614680 <6>[ 0.575032] iommu: Default domain type: Translated
10532 01:25:20.621528 <6>[ 0.580146] iommu: DMA domain TLB invalidation policy: strict mode
10533 01:25:20.624639 <5>[ 0.586778] SCSI subsystem initialized
10534 01:25:20.631219 <6>[ 0.591026] usbcore: registered new interface driver usbfs
10535 01:25:20.637891 <6>[ 0.596755] usbcore: registered new interface driver hub
10536 01:25:20.641186 <6>[ 0.602309] usbcore: registered new device driver usb
10537 01:25:20.648644 <6>[ 0.608425] pps_core: LinuxPPS API ver. 1 registered
10538 01:25:20.657821 <6>[ 0.613617] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10539 01:25:20.661215 <6>[ 0.622961] PTP clock support registered
10540 01:25:20.664643 <6>[ 0.627203] EDAC MC: Ver: 3.0.0
10541 01:25:20.671968 <6>[ 0.632401] FPGA manager framework
10542 01:25:20.675303 <6>[ 0.636076] Advanced Linux Sound Architecture Driver Initialized.
10543 01:25:20.678991 <6>[ 0.642837] vgaarb: loaded
10544 01:25:20.685555 <6>[ 0.645994] clocksource: Switched to clocksource arch_sys_counter
10545 01:25:20.692585 <5>[ 0.652435] VFS: Disk quotas dquot_6.6.0
10546 01:25:20.698978 <6>[ 0.656623] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10547 01:25:20.702094 <6>[ 0.663815] pnp: PnP ACPI: disabled
10548 01:25:20.710007 <6>[ 0.670433] NET: Registered PF_INET protocol family
10549 01:25:20.719866 <6>[ 0.676020] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10550 01:25:20.731222 <6>[ 0.688321] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10551 01:25:20.741350 <6>[ 0.697133] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10552 01:25:20.747739 <6>[ 0.705105] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10553 01:25:20.754344 <6>[ 0.713803] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10554 01:25:20.766612 <6>[ 0.723551] TCP: Hash tables configured (established 65536 bind 65536)
10555 01:25:20.773187 <6>[ 0.730412] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 01:25:20.779569 <6>[ 0.737609] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10557 01:25:20.786152 <6>[ 0.745316] NET: Registered PF_UNIX/PF_LOCAL protocol family
10558 01:25:20.792837 <6>[ 0.751484] RPC: Registered named UNIX socket transport module.
10559 01:25:20.796142 <6>[ 0.757637] RPC: Registered udp transport module.
10560 01:25:20.802901 <6>[ 0.762569] RPC: Registered tcp transport module.
10561 01:25:20.809682 <6>[ 0.767501] RPC: Registered tcp NFSv4.1 backchannel transport module.
10562 01:25:20.812933 <6>[ 0.774166] PCI: CLS 0 bytes, default 64
10563 01:25:20.816560 <6>[ 0.778567] Unpacking initramfs...
10564 01:25:20.841021 <6>[ 0.798118] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10565 01:25:20.850896 <6>[ 0.806768] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10566 01:25:20.854356 <6>[ 0.815610] kvm [1]: IPA Size Limit: 40 bits
10567 01:25:20.860782 <6>[ 0.820138] kvm [1]: GICv3: no GICV resource entry
10568 01:25:20.863939 <6>[ 0.825161] kvm [1]: disabling GICv2 emulation
10569 01:25:20.870981 <6>[ 0.829847] kvm [1]: GIC system register CPU interface enabled
10570 01:25:20.874290 <6>[ 0.836030] kvm [1]: vgic interrupt IRQ18
10571 01:25:20.880397 <6>[ 0.840396] kvm [1]: VHE mode initialized successfully
10572 01:25:20.887320 <5>[ 0.846950] Initialise system trusted keyrings
10573 01:25:20.893751 <6>[ 0.851796] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10574 01:25:20.901212 <6>[ 0.861793] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10575 01:25:20.908239 <5>[ 0.868162] NFS: Registering the id_resolver key type
10576 01:25:20.911203 <5>[ 0.873464] Key type id_resolver registered
10577 01:25:20.917932 <5>[ 0.877881] Key type id_legacy registered
10578 01:25:20.924853 <6>[ 0.882163] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10579 01:25:20.931372 <6>[ 0.889083] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10580 01:25:20.938261 <6>[ 0.896817] 9p: Installing v9fs 9p2000 file system support
10581 01:25:20.974683 <5>[ 0.935187] Key type asymmetric registered
10582 01:25:20.977990 <5>[ 0.939517] Asymmetric key parser 'x509' registered
10583 01:25:20.988066 <6>[ 0.944673] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10584 01:25:20.992337 <6>[ 0.952288] io scheduler mq-deadline registered
10585 01:25:20.994740 <6>[ 0.957069] io scheduler kyber registered
10586 01:25:21.013613 <6>[ 0.974002] EINJ: ACPI disabled.
10587 01:25:21.046174 <4>[ 0.999639] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 01:25:21.055745 <4>[ 1.010266] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 01:25:21.070584 <6>[ 1.030860] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10590 01:25:21.078514 <6>[ 1.038830] printk: console [ttyS0] disabled
10591 01:25:21.106719 <6>[ 1.063474] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10592 01:25:21.113281 <6>[ 1.072947] printk: console [ttyS0] enabled
10593 01:25:21.116285 <6>[ 1.072947] printk: console [ttyS0] enabled
10594 01:25:21.122865 <6>[ 1.081841] printk: bootconsole [mtk8250] disabled
10595 01:25:21.126309 <6>[ 1.081841] printk: bootconsole [mtk8250] disabled
10596 01:25:21.133030 <6>[ 1.093064] SuperH (H)SCI(F) driver initialized
10597 01:25:21.136410 <6>[ 1.098363] msm_serial: driver initialized
10598 01:25:21.150037 <6>[ 1.107314] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10599 01:25:21.160469 <6>[ 1.115860] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10600 01:25:21.167008 <6>[ 1.124401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10601 01:25:21.176687 <6>[ 1.133030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10602 01:25:21.183974 <6>[ 1.141737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10603 01:25:21.193439 <6>[ 1.150450] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10604 01:25:21.203130 <6>[ 1.158990] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10605 01:25:21.210011 <6>[ 1.167802] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10606 01:25:21.220096 <6>[ 1.176345] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10607 01:25:21.231467 <6>[ 1.191874] loop: module loaded
10608 01:25:21.237764 <6>[ 1.197891] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10609 01:25:21.260890 <4>[ 1.221261] mtk-pmic-keys: Failed to locate of_node [id: -1]
10610 01:25:21.267665 <6>[ 1.228256] megasas: 07.719.03.00-rc1
10611 01:25:21.277242 <6>[ 1.237942] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10612 01:25:21.284994 <6>[ 1.245392] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10613 01:25:21.301923 <6>[ 1.262171] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10614 01:25:21.358731 <6>[ 1.312514] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10615 01:25:22.838380 <6>[ 2.798850] Freeing initrd memory: 46396K
10616 01:25:22.848740 <6>[ 2.809122] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10617 01:25:22.859542 <6>[ 2.820153] tun: Universal TUN/TAP device driver, 1.6
10618 01:25:22.863070 <6>[ 2.826239] thunder_xcv, ver 1.0
10619 01:25:22.866310 <6>[ 2.829737] thunder_bgx, ver 1.0
10620 01:25:22.869244 <6>[ 2.833233] nicpf, ver 1.0
10621 01:25:22.880181 <6>[ 2.837256] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10622 01:25:22.883500 <6>[ 2.844733] hns3: Copyright (c) 2017 Huawei Corporation.
10623 01:25:22.886455 <6>[ 2.850323] hclge is initializing
10624 01:25:22.893517 <6>[ 2.853899] e1000: Intel(R) PRO/1000 Network Driver
10625 01:25:22.899785 <6>[ 2.859029] e1000: Copyright (c) 1999-2006 Intel Corporation.
10626 01:25:22.903090 <6>[ 2.865041] e1000e: Intel(R) PRO/1000 Network Driver
10627 01:25:22.909843 <6>[ 2.870257] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10628 01:25:22.917170 <6>[ 2.876443] igb: Intel(R) Gigabit Ethernet Network Driver
10629 01:25:22.922938 <6>[ 2.882092] igb: Copyright (c) 2007-2014 Intel Corporation.
10630 01:25:22.929817 <6>[ 2.887932] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10631 01:25:22.936213 <6>[ 2.894450] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10632 01:25:22.939370 <6>[ 2.900910] sky2: driver version 1.30
10633 01:25:22.946726 <6>[ 2.905906] VFIO - User Level meta-driver version: 0.3
10634 01:25:22.953427 <6>[ 2.914133] usbcore: registered new interface driver usb-storage
10635 01:25:22.960034 <6>[ 2.920579] usbcore: registered new device driver onboard-usb-hub
10636 01:25:22.969175 <6>[ 2.929724] mt6397-rtc mt6359-rtc: registered as rtc0
10637 01:25:22.979008 <6>[ 2.935190] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T01:25:18 UTC (1693185918)
10638 01:25:22.982392 <6>[ 2.944756] i2c_dev: i2c /dev entries driver
10639 01:25:22.998986 <6>[ 2.956622] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10640 01:25:23.020252 <6>[ 2.980624] cpu cpu0: EM: created perf domain
10641 01:25:23.023173 <6>[ 2.985619] cpu cpu4: EM: created perf domain
10642 01:25:23.030366 <6>[ 2.991258] sdhci: Secure Digital Host Controller Interface driver
10643 01:25:23.036995 <6>[ 2.997690] sdhci: Copyright(c) Pierre Ossman
10644 01:25:23.044022 <6>[ 3.002648] Synopsys Designware Multimedia Card Interface Driver
10645 01:25:23.050680 <6>[ 3.009272] sdhci-pltfm: SDHCI platform and OF driver helper
10646 01:25:23.053775 <6>[ 3.009294] mmc0: CQHCI version 5.10
10647 01:25:23.060440 <6>[ 3.019459] ledtrig-cpu: registered to indicate activity on CPUs
10648 01:25:23.066962 <6>[ 3.026566] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10649 01:25:23.074001 <6>[ 3.033600] usbcore: registered new interface driver usbhid
10650 01:25:23.077142 <6>[ 3.039422] usbhid: USB HID core driver
10651 01:25:23.083679 <6>[ 3.043626] spi_master spi0: will run message pump with realtime priority
10652 01:25:23.126526 <6>[ 3.080634] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10653 01:25:23.145568 <6>[ 3.096588] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10654 01:25:23.149407 <6>[ 3.110209] mmc0: Command Queue Engine enabled
10655 01:25:23.155649 <6>[ 3.115030] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10656 01:25:23.162597 <6>[ 3.122310] mmcblk0: mmc0:0001 DA4128 116 GiB
10657 01:25:23.165724 <6>[ 3.127260] cros-ec-spi spi0.0: Chrome EC device registered
10658 01:25:23.172329 <6>[ 3.131038] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10659 01:25:23.180029 <6>[ 3.140640] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10660 01:25:23.186402 <6>[ 3.146730] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10661 01:25:23.193206 <6>[ 3.152654] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10662 01:25:23.211911 <6>[ 3.169207] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10663 01:25:23.219097 <6>[ 3.179681] NET: Registered PF_PACKET protocol family
10664 01:25:23.222389 <6>[ 3.185095] 9pnet: Installing 9P2000 support
10665 01:25:23.228957 <5>[ 3.189659] Key type dns_resolver registered
10666 01:25:23.232355 <6>[ 3.194642] registered taskstats version 1
10667 01:25:23.238822 <5>[ 3.199026] Loading compiled-in X.509 certificates
10668 01:25:23.268684 <4>[ 3.222857] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 01:25:23.278904 <4>[ 3.233577] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10670 01:25:23.285801 <3>[ 3.244110] debugfs: File 'uA_load' in directory '/' already present!
10671 01:25:23.292229 <3>[ 3.250811] debugfs: File 'min_uV' in directory '/' already present!
10672 01:25:23.298510 <3>[ 3.257417] debugfs: File 'max_uV' in directory '/' already present!
10673 01:25:23.305124 <3>[ 3.264023] debugfs: File 'constraint_flags' in directory '/' already present!
10674 01:25:23.315956 <3>[ 3.273538] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10675 01:25:23.327506 <6>[ 3.288287] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10676 01:25:23.334662 <6>[ 3.295225] xhci-mtk 11200000.usb: xHCI Host Controller
10677 01:25:23.341022 <6>[ 3.300742] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10678 01:25:23.351185 <6>[ 3.308601] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10679 01:25:23.358031 <6>[ 3.318017] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10680 01:25:23.364682 <6>[ 3.324101] xhci-mtk 11200000.usb: xHCI Host Controller
10681 01:25:23.371534 <6>[ 3.329581] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10682 01:25:23.377724 <6>[ 3.337230] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10683 01:25:23.384534 <6>[ 3.344870] hub 1-0:1.0: USB hub found
10684 01:25:23.387866 <6>[ 3.348880] hub 1-0:1.0: 1 port detected
10685 01:25:23.394725 <6>[ 3.353158] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10686 01:25:23.400942 <6>[ 3.361671] hub 2-0:1.0: USB hub found
10687 01:25:23.404062 <6>[ 3.365685] hub 2-0:1.0: 1 port detected
10688 01:25:23.411735 <6>[ 3.372655] mtk-msdc 11f70000.mmc: Got CD GPIO
10689 01:25:23.423857 <6>[ 3.381212] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10690 01:25:23.430294 <6>[ 3.389244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10691 01:25:23.440437 <4>[ 3.397159] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10692 01:25:23.450335 <6>[ 3.406709] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10693 01:25:23.457113 <6>[ 3.414787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10694 01:25:23.463325 <6>[ 3.422814] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10695 01:25:23.473709 <6>[ 3.430727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10696 01:25:23.480182 <6>[ 3.438549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10697 01:25:23.489945 <6>[ 3.446366] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10698 01:25:23.499772 <6>[ 3.456785] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10699 01:25:23.506822 <6>[ 3.465144] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10700 01:25:23.516409 <6>[ 3.473492] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10701 01:25:23.523337 <6>[ 3.481830] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10702 01:25:23.532780 <6>[ 3.490177] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10703 01:25:23.539712 <6>[ 3.498516] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10704 01:25:23.549377 <6>[ 3.506853] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10705 01:25:23.556420 <6>[ 3.515193] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10706 01:25:23.566579 <6>[ 3.523532] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10707 01:25:23.575895 <6>[ 3.531870] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10708 01:25:23.582665 <6>[ 3.540208] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10709 01:25:23.592570 <6>[ 3.548546] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10710 01:25:23.599484 <6>[ 3.556884] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10711 01:25:23.609224 <6>[ 3.565223] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10712 01:25:23.615855 <6>[ 3.573561] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10713 01:25:23.622559 <6>[ 3.582304] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10714 01:25:23.629144 <6>[ 3.589482] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10715 01:25:23.635727 <6>[ 3.596268] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10716 01:25:23.642560 <6>[ 3.603023] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10717 01:25:23.653030 <6>[ 3.609956] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10718 01:25:23.659169 <6>[ 3.616809] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10719 01:25:23.669144 <6>[ 3.625941] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10720 01:25:23.678897 <6>[ 3.635061] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10721 01:25:23.689163 <6>[ 3.644355] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10722 01:25:23.698942 <6>[ 3.653823] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10723 01:25:23.706237 <6>[ 3.663306] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10724 01:25:23.715467 <6>[ 3.672427] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10725 01:25:23.725621 <6>[ 3.681894] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10726 01:25:23.735627 <6>[ 3.691013] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10727 01:25:23.745789 <6>[ 3.700308] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10728 01:25:23.755111 <6>[ 3.710467] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10729 01:25:23.765249 <6>[ 3.721893] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10730 01:25:23.812593 <6>[ 3.770266] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10731 01:25:23.967509 <6>[ 3.928302] hub 1-1:1.0: USB hub found
10732 01:25:23.971056 <6>[ 3.932814] hub 1-1:1.0: 4 ports detected
10733 01:25:24.093173 <6>[ 4.050506] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10734 01:25:24.119121 <6>[ 4.079481] hub 2-1:1.0: USB hub found
10735 01:25:24.122226 <6>[ 4.083950] hub 2-1:1.0: 3 ports detected
10736 01:25:24.292676 <6>[ 4.250313] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10737 01:25:24.425376 <6>[ 4.386058] hub 1-1.4:1.0: USB hub found
10738 01:25:24.428668 <6>[ 4.390715] hub 1-1.4:1.0: 2 ports detected
10739 01:25:24.505015 <6>[ 4.462483] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10740 01:25:24.724998 <6>[ 4.682311] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10741 01:25:24.916979 <6>[ 4.874285] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10742 01:25:36.050183 <6>[ 16.015274] ALSA device list:
10743 01:25:36.056291 <6>[ 16.018560] No soundcards found.
10744 01:25:36.064486 <6>[ 16.026540] Freeing unused kernel memory: 8384K
10745 01:25:36.067945 <6>[ 16.031557] Run /init as init process
10746 01:25:36.116297 <6>[ 16.078727] NET: Registered PF_INET6 protocol family
10747 01:25:36.123054 <6>[ 16.085142] Segment Routing with IPv6
10748 01:25:36.126312 <6>[ 16.089088] In-situ OAM (IOAM) with IPv6
10749 01:25:36.162597 <30>[ 16.104959] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10750 01:25:36.165894 <30>[ 16.128867] systemd[1]: Detected architecture arm64.
10751 01:25:36.165979
10752 01:25:36.172408 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10753 01:25:36.172493
10754 01:25:36.192033 <30>[ 16.154290] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10755 01:25:36.333218 <30>[ 16.292105] systemd[1]: Queued start job for default target Graphical Interface.
10756 01:25:36.377321 <30>[ 16.339239] systemd[1]: Created slice system-getty.slice.
10757 01:25:36.384116 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10758 01:25:36.401335 <30>[ 16.363190] systemd[1]: Created slice system-modprobe.slice.
10759 01:25:36.407759 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10760 01:25:36.424566 <30>[ 16.386863] systemd[1]: Created slice system-serial\x2dgetty.slice.
10761 01:25:36.434715 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10762 01:25:36.449841 <30>[ 16.411837] systemd[1]: Created slice User and Session Slice.
10763 01:25:36.456340 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10764 01:25:36.476364 <30>[ 16.434591] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10765 01:25:36.485541 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10766 01:25:36.504086 <30>[ 16.463053] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10767 01:25:36.510721 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10768 01:25:36.534671 <30>[ 16.490375] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10769 01:25:36.541493 <30>[ 16.502558] systemd[1]: Reached target Local Encrypted Volumes.
10770 01:25:36.548138 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10771 01:25:36.564340 <30>[ 16.526417] systemd[1]: Reached target Paths.
10772 01:25:36.567237 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10773 01:25:36.584376 <30>[ 16.546271] systemd[1]: Reached target Remote File Systems.
10774 01:25:36.590555 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10775 01:25:36.604211 <30>[ 16.566248] systemd[1]: Reached target Slices.
10776 01:25:36.607150 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10777 01:25:36.623970 <30>[ 16.586305] systemd[1]: Reached target Swap.
10778 01:25:36.627340 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10779 01:25:36.647631 <30>[ 16.606677] systemd[1]: Listening on initctl Compatibility Named Pipe.
10780 01:25:36.654292 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10781 01:25:36.661325 <30>[ 16.621769] systemd[1]: Listening on Journal Audit Socket.
10782 01:25:36.667793 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10783 01:25:36.680503 <30>[ 16.642753] systemd[1]: Listening on Journal Socket (/dev/log).
10784 01:25:36.687219 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10785 01:25:36.705290 <30>[ 16.667550] systemd[1]: Listening on Journal Socket.
10786 01:25:36.711947 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10787 01:25:36.724796 <30>[ 16.686959] systemd[1]: Listening on Network Service Netlink Socket.
10788 01:25:36.735101 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10789 01:25:36.749362 <30>[ 16.711507] systemd[1]: Listening on udev Control Socket.
10790 01:25:36.755871 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10791 01:25:36.773306 <30>[ 16.735391] systemd[1]: Listening on udev Kernel Socket.
10792 01:25:36.779490 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10793 01:25:36.836350 <30>[ 16.798557] systemd[1]: Mounting Huge Pages File System...
10794 01:25:36.842921 Mounting [0;1;39mHuge Pages File System[0m...
10795 01:25:36.858337 <30>[ 16.820677] systemd[1]: Mounting POSIX Message Queue File System...
10796 01:25:36.865201 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10797 01:25:36.883990 <30>[ 16.846367] systemd[1]: Mounting Kernel Debug File System...
10798 01:25:36.890403 Mounting [0;1;39mKernel Debug File System[0m...
10799 01:25:36.908187 <30>[ 16.866772] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10800 01:25:36.921176 <30>[ 16.880063] systemd[1]: Starting Create list of static device nodes for the current kernel...
10801 01:25:36.927765 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10802 01:25:36.948575 <30>[ 16.910912] systemd[1]: Starting Load Kernel Module configfs...
10803 01:25:36.955238 Starting [0;1;39mLoad Kernel Module configfs[0m...
10804 01:25:36.972937 <30>[ 16.935012] systemd[1]: Starting Load Kernel Module drm...
10805 01:25:36.979382 Starting [0;1;39mLoad Kernel Module drm[0m...
10806 01:25:36.995649 <30>[ 16.954644] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10807 01:25:37.040916 <30>[ 17.003118] systemd[1]: Starting Journal Service...
10808 01:25:37.044408 Starting [0;1;39mJournal Service[0m...
10809 01:25:37.064970 <30>[ 17.027093] systemd[1]: Starting Load Kernel Modules...
10810 01:25:37.071708 Starting [0;1;39mLoad Kernel Modules[0m...
10811 01:25:37.116434 <30>[ 17.075304] systemd[1]: Starting Remount Root and Kernel File Systems...
10812 01:25:37.123228 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10813 01:25:37.140402 <30>[ 17.102352] systemd[1]: Starting Coldplug All udev Devices...
10814 01:25:37.146918 Starting [0;1;39mColdplug All udev Devices[0m...
10815 01:25:37.163900 <30>[ 17.124825] systemd[1]: Started Journal Service.
10816 01:25:37.169230 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10817 01:25:37.185904 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10818 01:25:37.200746 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10819 01:25:37.216717 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10820 01:25:37.236745 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10821 01:25:37.258737 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10822 01:25:37.283507 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10823 01:25:37.305914 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10824 01:25:37.326098 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10825 01:25:37.340084 See 'systemctl status systemd-remount-fs.service' for details.
10826 01:25:37.383990 Mounting [0;1;39mKernel Configuration File System[0m...
10827 01:25:37.404531 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10828 01:25:37.417928 <46>[ 17.376600] systemd-journald[189]: Received client request to flush runtime journal.
10829 01:25:37.428487 Starting [0;1;39mLoad/Save Random Seed[0m...
10830 01:25:37.448283 Starting [0;1;39mApply Kernel Variables[0m...
10831 01:25:37.467232 Starting [0;1;39mCreate System Users[0m...
10832 01:25:37.485962 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10833 01:25:37.501021 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10834 01:25:37.525473 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10835 01:25:37.537989 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10836 01:25:37.553958 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10837 01:25:37.569689 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10838 01:25:37.608867 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10839 01:25:37.630997 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10840 01:25:37.644737 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10841 01:25:37.660043 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10842 01:25:37.725379 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10843 01:25:37.751423 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10844 01:25:37.769260 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10845 01:25:37.791297 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10846 01:25:37.843215 Starting [0;1;39mNetwork Service[0m...
10847 01:25:37.873978 Starting [0;1;39mNetwork Time Synchronization[0m...
10848 01:25:37.895148 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10849 01:25:37.936732 <6>[ 17.895897] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10850 01:25:37.939997 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10851 01:25:37.959596 <6>[ 17.918542] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10852 01:25:37.966409 <6>[ 17.926495] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10853 01:25:37.975995 <6>[ 17.935298] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10854 01:25:37.982749 <6>[ 17.938285] remoteproc remoteproc0: scp is available
10855 01:25:37.989629 [[0;32m OK [<6>[ 17.949690] remoteproc remoteproc0: powering up scp
10856 01:25:37.999781 0m] Found device<3>[ 17.952546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 01:25:38.006446 <6>[ 17.956403] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10858 01:25:38.016224 <3>[ 17.965896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 01:25:38.022680 [0;1;39m/dev/t<6>[ 17.974016] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10860 01:25:38.029234 <3>[ 17.982065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 01:25:38.029321 tyS0[0m.
10862 01:25:38.035879 <6>[ 17.990218] mc: Linux media interface: v0.10
10863 01:25:38.042631 <3>[ 17.990637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 01:25:38.052487 <3>[ 17.990663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 01:25:38.058910 <3>[ 17.990668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 01:25:38.069159 <3>[ 17.990673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 01:25:38.075565 <3>[ 17.990677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 01:25:38.085388 <3>[ 17.991224] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 01:25:38.092024 <3>[ 17.991288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 01:25:38.098729 <3>[ 17.991292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 01:25:38.108856 <3>[ 17.991298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 01:25:38.115977 <3>[ 17.991351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 01:25:38.123120 <3>[ 17.991358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 01:25:38.133073 <3>[ 17.991365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 01:25:38.139673 <3>[ 17.991376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 01:25:38.149525 <3>[ 17.991382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 01:25:38.155852 <3>[ 17.991431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 01:25:38.165986 <6>[ 17.991782] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10879 01:25:38.169187 <6>[ 18.012876] usbcore: registered new interface driver r8152
10880 01:25:38.179299 <4>[ 18.013247] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10881 01:25:38.185766 <4>[ 18.013366] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10882 01:25:38.192195 <4>[ 18.032960] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10883 01:25:38.198876 <4>[ 18.032960] Fallback method does not support PEC.
10884 01:25:38.205757 <6>[ 18.057853] videodev: Linux video capture interface: v2.00
10885 01:25:38.212123 <6>[ 18.060070] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10886 01:25:38.218762 <3>[ 18.087942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 01:25:38.225663 <6>[ 18.091936] pci_bus 0000:00: root bus resource [bus 00-ff]
10888 01:25:38.236069 <6>[ 18.117132] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10889 01:25:38.242829 <6>[ 18.122465] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10890 01:25:38.249421 <6>[ 18.123679] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10891 01:25:38.256374 <6>[ 18.123700] remoteproc remoteproc0: remote processor scp is now up
10892 01:25:38.262899 <6>[ 18.125081] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10893 01:25:38.270149 <6>[ 18.146284] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10894 01:25:38.280630 <6>[ 18.152453] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10895 01:25:38.287391 <6>[ 18.152500] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10896 01:25:38.297476 <6>[ 18.167340] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10897 01:25:38.307394 <6>[ 18.168950] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10898 01:25:38.313992 <6>[ 18.169354] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10899 01:25:38.323895 <6>[ 18.171906] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10900 01:25:38.327368 <6>[ 18.172160] pci 0000:00:00.0: supports D1 D2
10901 01:25:38.334602 <6>[ 18.184886] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10902 01:25:38.341856 <6>[ 18.187625] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10903 01:25:38.351943 <6>[ 18.188746] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10904 01:25:38.355855 <6>[ 18.195424] Bluetooth: Core ver 2.22
10905 01:25:38.359172 <6>[ 18.195507] usbcore: registered new interface driver cdc_ether
10906 01:25:38.365672 <6>[ 18.202856] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10907 01:25:38.372543 <6>[ 18.203076] usbcore: registered new interface driver r8153_ecm
10908 01:25:38.379337 <6>[ 18.209814] NET: Registered PF_BLUETOOTH protocol family
10909 01:25:38.385856 <6>[ 18.214097] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10910 01:25:38.392513 <6>[ 18.218288] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10911 01:25:38.399014 <6>[ 18.224691] Bluetooth: HCI device and connection manager initialized
10912 01:25:38.405832 <6>[ 18.231830] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10913 01:25:38.412471 <6>[ 18.238967] Bluetooth: HCI socket layer initialized
10914 01:25:38.418773 <6>[ 18.240256] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10915 01:25:38.431866 <6>[ 18.241278] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10916 01:25:38.438499 <6>[ 18.241393] usbcore: registered new interface driver uvcvideo
10917 01:25:38.445008 <6>[ 18.249181] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10918 01:25:38.452061 <6>[ 18.255200] Bluetooth: L2CAP socket layer initialized
10919 01:25:38.455015 <6>[ 18.255215] Bluetooth: SCO socket layer initialized
10920 01:25:38.465812 <3>[ 18.258869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 01:25:38.471801 <3>[ 18.260404] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10922 01:25:38.478261 <6>[ 18.263580] pci 0000:01:00.0: supports D1 D2
10923 01:25:38.481811 <6>[ 18.266089] r8152 2-1.3:1.0 eth0: v1.12.13
10924 01:25:38.488522 <6>[ 18.274188] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10925 01:25:38.494963 <6>[ 18.283605] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10926 01:25:38.501917 <6>[ 18.284615] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10927 01:25:38.511518 <3>[ 18.314789] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 01:25:38.518066 <3>[ 18.315586] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10929 01:25:38.524623 <6>[ 18.322806] usbcore: registered new interface driver btusb
10930 01:25:38.534804 <4>[ 18.323679] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10931 01:25:38.541530 <3>[ 18.323691] Bluetooth: hci0: Failed to load firmware file (-2)
10932 01:25:38.548546 <3>[ 18.323695] Bluetooth: hci0: Failed to set up firmware (-2)
10933 01:25:38.557975 <4>[ 18.323701] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10934 01:25:38.567608 <3>[ 18.328938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 01:25:38.574288 <6>[ 18.330063] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10936 01:25:38.581053 <6>[ 18.330100] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10937 01:25:38.590951 <6>[ 18.330106] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10938 01:25:38.597463 <6>[ 18.330114] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10939 01:25:38.604032 <6>[ 18.330127] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10940 01:25:38.614072 <6>[ 18.330139] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10941 01:25:38.617550 <6>[ 18.330151] pci 0000:00:00.0: PCI bridge to [bus 01]
10942 01:25:38.627674 <6>[ 18.330156] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10943 01:25:38.633919 <6>[ 18.330285] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10944 01:25:38.640874 <6>[ 18.330716] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10945 01:25:38.643692 <6>[ 18.331098] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10946 01:25:38.653839 <5>[ 18.344817] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10947 01:25:38.660273 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10948 01:25:38.679604 <5>[ 18.638325] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10949 01:25:38.685963 <4>[ 18.645221] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10950 01:25:38.692344 <6>[ 18.654098] cfg80211: failed to load regulatory.db
10951 01:25:38.704433 <3>[ 18.663574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 01:25:38.724079 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10953 01:25:38.734717 <3>[ 18.693816] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 01:25:38.745950 <6>[ 18.705085] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10955 01:25:38.752385 <6>[ 18.712584] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10956 01:25:38.765096 <3>[ 18.723770] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 01:25:38.775830 <6>[ 18.738180] mt7921e 0000:01:00.0: ASIC revision: 79610010
10958 01:25:38.795089 <3>[ 18.754312] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 01:25:38.829151 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10960 01:25:38.844254 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10961 01:25:38.859834 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10962 01:25:38.868029 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10963 01:25:38.882640 <4>[ 18.838469] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10964 01:25:38.890143 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10965 01:25:38.944058 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10966 01:25:38.967690 Starting [0;1;39mNetwork Name Resolution[0m...
10967 01:25:39.003481 [[0;32m OK [0m] Finished [0<4>[ 18.957795] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10968 01:25:39.006810 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10969 01:25:39.025222 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10970 01:25:39.043819 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10971 01:25:39.063776 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10972 01:25:39.080474 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10973 01:25:39.103858 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10974 01:25:39.125998 [[0;32m OK [0m] Reached targ<4>[ 19.080335] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 01:25:39.126089 et [0;1;39mSockets[0m.
10976 01:25:39.145254 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10977 01:25:39.188923 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10978 01:25:39.220102 Starting [0;1;39mUser Login Management[0m...
10979 01:25:39.245016 <4>[ 19.200772] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10980 01:25:39.251243 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10981 01:25:39.268904 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10982 01:25:39.286232 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10983 01:25:39.304731 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10984 01:25:39.323292 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10985 01:25:39.364463 <4>[ 19.320586] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10986 01:25:39.386478 Starting [0;1;39mPermit User Sessions[0m...
10987 01:25:39.402672 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10988 01:25:39.420607 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10989 01:25:39.434285 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10990 01:25:39.454393 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10991 01:25:39.483993 [[0;32m OK [<4>[ 19.441345] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 01:25:39.490650 0m] Reached target [0;1;39mLogin Prompts[0m.
10993 01:25:39.506254 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10994 01:25:39.524964 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10995 01:25:39.585579 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10996 01:25:39.606348 <4>[ 19.562102] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 01:25:39.642167 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10998 01:25:39.682404
10999 01:25:39.682540
11000 01:25:39.685488 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11001 01:25:39.685612
11002 01:25:39.688447 debian-bullseye-arm64 login: root (automatic login)
11003 01:25:39.688571
11004 01:25:39.688682
11005 01:25:39.727020 <4>[ 19.682685] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 01:25:39.733539 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023 aarch64
11007 01:25:39.733623
11008 01:25:39.740375 The programs included with the Debian GNU/Linux system are free software;
11009 01:25:39.746833 the exact distribution terms for each program are described in the
11010 01:25:39.753445 individual files in /usr/share/doc/*/copyright.
11011 01:25:39.753529
11012 01:25:39.756538 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11013 01:25:39.759856 permitted by applicable law.
11014 01:25:39.760228 Matched prompt #10: / #
11016 01:25:39.760441 Setting prompt string to ['/ #']
11017 01:25:39.760537 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11019 01:25:39.760735 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11020 01:25:39.760875 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
11021 01:25:39.760952 Setting prompt string to ['/ #']
11022 01:25:39.761017 Forcing a shell prompt, looking for ['/ #']
11024 01:25:39.811212 / #
11025 01:25:39.811368 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11026 01:25:39.811496 Waiting using forced prompt support (timeout 00:02:30)
11027 01:25:39.816315
11028 01:25:39.816637 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11029 01:25:39.816839 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
11030 01:25:39.817026 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11031 01:25:39.817173 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
11032 01:25:39.817318 end: 2 depthcharge-action (duration 00:01:33) [common]
11033 01:25:39.817475 start: 3 lava-test-retry (timeout 00:05:00) [common]
11034 01:25:39.817625 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11035 01:25:39.817757 Using namespace: common
11037 01:25:39.918170 / # #
11038 01:25:39.918294 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11039 01:25:39.918449 <4>[ 19.804564] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11040 01:25:39.923292 #
11041 01:25:39.923558 Using /lava-11368530
11043 01:25:40.023833 / # export SHELL=/bin/sh
11044 01:25:40.024029 <6>[ 19.894189] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11045 01:25:40.024146 <6>[ 19.901890] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11046 01:25:40.024243 <4>[ 19.925337] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11047 01:25:40.028970 export SHELL=/bin/sh
11049 01:25:40.129437 / # . /lava-11368530/environment
11050 01:25:40.129607 <3>[ 20.042532] mt7921e 0000:01:00.0: hardware init failed
11051 01:25:40.134710 . /lava-11368530/environment
11053 01:25:40.235184 / # /lava-11368530/bin/lava-test-runner /lava-11368530/0
11054 01:25:40.235345 Test shell timeout: 10s (minimum of the action and connection timeout)
11055 01:25:40.241112 /lava-11368530/bin/lava-test-runner /lava-11368530/0
11056 01:25:40.268089 + export TESTRUN<8>[ 20.228575] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11368530_1.5.2.3.1>
11057 01:25:40.268221 _ID=0_cros-ec
11058 01:25:40.268519 Received signal: <STARTRUN> 0_cros-ec 11368530_1.5.2.3.1
11059 01:25:40.268645 Starting test lava.0_cros-ec (11368530_1.5.2.3.1)
11060 01:25:40.268815 Skipping test definition patterns.
11061 01:25:40.271213 + cd /lava-11368530/0/tests/0_cros-ec
11062 01:25:40.271343 + cat uuid
11063 01:25:40.274870 + UUID=11368530_1.5.2.3.1
11064 01:25:40.274992 + set +x
11065 01:25:40.281647 + python3 -m cros.runners.lava_runner -v
11066 01:25:40.660814 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11067 01:25:40.667435 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11068 01:25:40.667569
11069 01:25:40.674247 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11071 01:25:40.677594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11072 01:25:40.684476 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11073 01:25:40.690721 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11074 01:25:40.690849
11075 01:25:40.700877 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
11076 01:25:40.701014 Bad test result: ski<8
11077 01:25:40.704030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 20.665771] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11368530_1.5.2.3.1>
11078 01:25:40.704331 Received signal: <ENDRUN> 0_cros-ec 11368530_1.5.2.3.1
11079 01:25:40.704469 Ending use of test pattern.
11080 01:25:40.704581 Ending test lava.0_cros-ec (11368530_1.5.2.3.1), duration 0.44
11082 01:25:40.707481 p>
11083 01:25:40.710625 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11084 01:25:40.717060 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11085 01:25:40.717185
11086 01:25:40.723774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11087 01:25:40.724076 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11089 01:25:40.730518 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11090 01:25:40.737349 Checks the standard ABI for the main Embedded Controller. ... ok
11091 01:25:40.737482
11092 01:25:40.740729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11093 01:25:40.741062 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11095 01:25:40.746842 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11096 01:25:40.753904 Checks the main Embedded controller character device. ... ok
11097 01:25:40.754037
11098 01:25:40.757049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11099 01:25:40.757352 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11101 01:25:40.763997 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11102 01:25:40.770026 Checks basic comunication with the main Embedded controller. ... ok
11103 01:25:40.770112
11104 01:25:40.776682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11105 01:25:40.776973 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11107 01:25:40.779890 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11108 01:25:40.787045 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11109 01:25:40.787130
11110 01:25:40.793369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11111 01:25:40.793622 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11113 01:25:40.800343 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11114 01:25:40.806565 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11115 01:25:40.806650
11116 01:25:40.813338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11117 01:25:40.813591 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11119 01:25:40.820098 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11120 01:25:40.826441 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11121 01:25:40.826527
11122 01:25:40.830308 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11124 01:25:40.833245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11125 01:25:40.836551 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11126 01:25:40.842902 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11127 01:25:40.842987
11128 01:25:40.849804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11129 01:25:40.850058 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11131 01:25:40.856199 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11132 01:25:40.862858 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11133 01:25:40.862944
11134 01:25:40.869500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11135 01:25:40.869753 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11137 01:25:40.876161 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11138 01:25:40.882881 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11139 01:25:40.882980
11140 01:25:40.889722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11141 01:25:40.889980 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11143 01:25:40.892848 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11144 01:25:40.903099 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11145 01:25:40.903181
11146 01:25:40.906452 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11148 01:25:40.909201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11149 01:25:40.912425 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11150 01:25:40.922380 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11151 01:25:40.922466
11152 01:25:40.929359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11153 01:25:40.929613 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11155 01:25:40.936176 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11156 01:25:40.939363 Check the cros battery ABI. ... skipped 'No BAT found'
11157 01:25:40.939448
11158 01:25:40.945909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11159 01:25:40.946163 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11161 01:25:40.952294 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11162 01:25:40.958844 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11163 01:25:40.958968
11164 01:25:40.966034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11165 01:25:40.966290 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11167 01:25:40.972593 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11168 01:25:40.979066 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11169 01:25:40.979195
11170 01:25:40.985347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11171 01:25:40.985652 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11173 01:25:40.992567 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11174 01:25:40.998785 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11175 01:25:40.998913
11176 01:25:41.005292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11177 01:25:41.005422
11178 01:25:41.005716 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11180 01:25:41.011809 ----------------------------------------------------------------------
11181 01:25:41.011941 Ran 18 tests in 0.006s
11182 01:25:41.014916
11183 01:25:41.015038 OK (skipped=15)
11184 01:25:41.015152 + set +x
11185 01:25:41.018474 <LAVA_TEST_RUNNER EXIT>
11186 01:25:41.018792 ok: lava_test_shell seems to have completed
11187 01:25:41.018982 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11188 01:25:41.019085 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11189 01:25:41.019171 end: 3 lava-test-retry (duration 00:00:01) [common]
11190 01:25:41.019263 start: 4 finalize (timeout 00:08:02) [common]
11191 01:25:41.019358 start: 4.1 power-off (timeout 00:00:30) [common]
11192 01:25:41.019512 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11193 01:25:41.094245 >> Command sent successfully.
11194 01:25:41.097510 Returned 0 in 0 seconds
11195 01:25:41.197964 end: 4.1 power-off (duration 00:00:00) [common]
11197 01:25:41.198293 start: 4.2 read-feedback (timeout 00:08:02) [common]
11198 01:25:41.198556 Listened to connection for namespace 'common' for up to 1s
11199 01:25:42.199497 Finalising connection for namespace 'common'
11200 01:25:42.199744 Disconnecting from shell: Finalise
11201 01:25:42.199877 / #
11202 01:25:42.300252 end: 4.2 read-feedback (duration 00:00:01) [common]
11203 01:25:42.300501 end: 4 finalize (duration 00:00:01) [common]
11204 01:25:42.300682 Cleaning after the job
11205 01:25:42.300871 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/ramdisk
11206 01:25:42.307823 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/kernel
11207 01:25:42.316462 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/dtb
11208 01:25:42.316711 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368530/tftp-deploy-8rmbjqvi/modules
11209 01:25:42.324155 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11368530
11210 01:25:42.454072 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11368530
11211 01:25:42.454247 Job finished correctly