Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 66
1 01:23:14.261594 lava-dispatcher, installed at version: 2023.06
2 01:23:14.261855 start: 0 validate
3 01:23:14.262002 Start time: 2023-08-28 01:23:14.261995+00:00 (UTC)
4 01:23:14.262146 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:23:14.262293 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 01:23:14.532303 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:23:14.532693 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:23:49.814745 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:23:49.815549 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:23:50.077804 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:23:50.078489 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:23:52.835134 validate duration: 38.57
14 01:23:52.835440 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:23:52.835540 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:23:52.835631 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:23:52.835753 Not decompressing ramdisk as can be used compressed.
18 01:23:52.835841 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 01:23:52.835909 saving as /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/ramdisk/rootfs.cpio.gz
20 01:23:52.835975 total size: 26246609 (25 MB)
21 01:23:53.102786 progress 0 % (0 MB)
22 01:23:53.109992 progress 5 % (1 MB)
23 01:23:53.116981 progress 10 % (2 MB)
24 01:23:53.123885 progress 15 % (3 MB)
25 01:23:53.130706 progress 20 % (5 MB)
26 01:23:53.137597 progress 25 % (6 MB)
27 01:23:53.144662 progress 30 % (7 MB)
28 01:23:53.151531 progress 35 % (8 MB)
29 01:23:53.158502 progress 40 % (10 MB)
30 01:23:53.165465 progress 45 % (11 MB)
31 01:23:53.172448 progress 50 % (12 MB)
32 01:23:53.179442 progress 55 % (13 MB)
33 01:23:53.186298 progress 60 % (15 MB)
34 01:23:53.193257 progress 65 % (16 MB)
35 01:23:53.200178 progress 70 % (17 MB)
36 01:23:53.207202 progress 75 % (18 MB)
37 01:23:53.214284 progress 80 % (20 MB)
38 01:23:53.221244 progress 85 % (21 MB)
39 01:23:53.228057 progress 90 % (22 MB)
40 01:23:53.234855 progress 95 % (23 MB)
41 01:23:53.241617 progress 100 % (25 MB)
42 01:23:53.241887 25 MB downloaded in 0.41 s (61.67 MB/s)
43 01:23:53.242051 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:23:53.242293 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:23:53.242382 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:23:53.242467 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:23:53.242609 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:23:53.242679 saving as /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/kernel/Image
50 01:23:53.242740 total size: 49220096 (46 MB)
51 01:23:53.242803 No compression specified
52 01:23:53.244037 progress 0 % (0 MB)
53 01:23:53.257118 progress 5 % (2 MB)
54 01:23:53.269945 progress 10 % (4 MB)
55 01:23:53.283696 progress 15 % (7 MB)
56 01:23:53.297265 progress 20 % (9 MB)
57 01:23:53.310297 progress 25 % (11 MB)
58 01:23:53.323458 progress 30 % (14 MB)
59 01:23:53.336421 progress 35 % (16 MB)
60 01:23:53.349455 progress 40 % (18 MB)
61 01:23:53.362519 progress 45 % (21 MB)
62 01:23:53.375570 progress 50 % (23 MB)
63 01:23:53.388570 progress 55 % (25 MB)
64 01:23:53.401726 progress 60 % (28 MB)
65 01:23:53.414833 progress 65 % (30 MB)
66 01:23:53.427896 progress 70 % (32 MB)
67 01:23:53.440791 progress 75 % (35 MB)
68 01:23:53.453802 progress 80 % (37 MB)
69 01:23:53.466807 progress 85 % (39 MB)
70 01:23:53.479656 progress 90 % (42 MB)
71 01:23:53.492420 progress 95 % (44 MB)
72 01:23:53.505398 progress 100 % (46 MB)
73 01:23:53.505576 46 MB downloaded in 0.26 s (178.59 MB/s)
74 01:23:53.505733 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:23:53.505971 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:23:53.506064 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:23:53.506163 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:23:53.506355 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:23:53.506429 saving as /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/dtb/mt8192-asurada-spherion-r0.dtb
81 01:23:53.506493 total size: 47278 (0 MB)
82 01:23:53.506558 No compression specified
83 01:23:53.507753 progress 69 % (0 MB)
84 01:23:53.508032 progress 100 % (0 MB)
85 01:23:53.508189 0 MB downloaded in 0.00 s (26.63 MB/s)
86 01:23:53.508313 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:23:53.508537 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:23:53.508623 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:23:53.508705 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:23:53.508820 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:23:53.508889 saving as /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/modules/modules.tar
93 01:23:53.508950 total size: 8616896 (8 MB)
94 01:23:53.509012 Using unxz to decompress xz
95 01:23:53.513414 progress 0 % (0 MB)
96 01:23:53.534600 progress 5 % (0 MB)
97 01:23:53.558547 progress 10 % (0 MB)
98 01:23:53.587829 progress 15 % (1 MB)
99 01:23:53.616472 progress 20 % (1 MB)
100 01:23:53.640296 progress 25 % (2 MB)
101 01:23:53.664681 progress 30 % (2 MB)
102 01:23:53.691549 progress 35 % (2 MB)
103 01:23:53.716465 progress 40 % (3 MB)
104 01:23:53.742569 progress 45 % (3 MB)
105 01:23:53.768174 progress 50 % (4 MB)
106 01:23:53.793510 progress 55 % (4 MB)
107 01:23:53.818960 progress 60 % (4 MB)
108 01:23:53.843294 progress 65 % (5 MB)
109 01:23:53.869080 progress 70 % (5 MB)
110 01:23:53.894697 progress 75 % (6 MB)
111 01:23:53.919168 progress 80 % (6 MB)
112 01:23:53.944874 progress 85 % (7 MB)
113 01:23:53.970060 progress 90 % (7 MB)
114 01:23:53.994279 progress 95 % (7 MB)
115 01:23:54.020820 progress 100 % (8 MB)
116 01:23:54.027104 8 MB downloaded in 0.52 s (15.86 MB/s)
117 01:23:54.027367 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:23:54.027673 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:23:54.027765 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:23:54.027862 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:23:54.027942 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:23:54.028035 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:23:54.028264 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3
125 01:23:54.028399 makedir: /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin
126 01:23:54.028507 makedir: /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/tests
127 01:23:54.028606 makedir: /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/results
128 01:23:54.028724 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-add-keys
129 01:23:54.028878 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-add-sources
130 01:23:54.029021 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-background-process-start
131 01:23:54.029152 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-background-process-stop
132 01:23:54.029280 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-common-functions
133 01:23:54.029404 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-echo-ipv4
134 01:23:54.029530 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-install-packages
135 01:23:54.029654 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-installed-packages
136 01:23:54.029777 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-os-build
137 01:23:54.029900 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-probe-channel
138 01:23:54.030022 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-probe-ip
139 01:23:54.030144 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-target-ip
140 01:23:54.030267 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-target-mac
141 01:23:54.030388 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-target-storage
142 01:23:54.030519 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-case
143 01:23:54.030644 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-event
144 01:23:54.030767 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-feedback
145 01:23:54.030891 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-raise
146 01:23:54.031016 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-reference
147 01:23:54.031143 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-runner
148 01:23:54.031267 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-set
149 01:23:54.031419 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-test-shell
150 01:23:54.031561 Updating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-install-packages (oe)
151 01:23:54.031717 Updating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/bin/lava-installed-packages (oe)
152 01:23:54.031841 Creating /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/environment
153 01:23:54.031941 LAVA metadata
154 01:23:54.032015 - LAVA_JOB_ID=11368524
155 01:23:54.032081 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:23:54.032180 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:23:54.032249 skipped lava-vland-overlay
158 01:23:54.032323 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:23:54.032402 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:23:54.032468 skipped lava-multinode-overlay
161 01:23:54.032539 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:23:54.032620 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:23:54.032695 Loading test definitions
164 01:23:54.032785 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:23:54.032857 Using /lava-11368524 at stage 0
166 01:23:54.033167 uuid=11368524_1.5.2.3.1 testdef=None
167 01:23:54.033254 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:23:54.033337 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:23:54.033860 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:23:54.034079 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:23:54.034689 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:23:54.034917 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:23:54.035513 runner path: /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11368524_1.5.2.3.1
176 01:23:54.035668 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:23:54.035873 Creating lava-test-runner.conf files
179 01:23:54.035936 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11368524/lava-overlay-t7gfn6g3/lava-11368524/0 for stage 0
180 01:23:54.036026 - 0_v4l2-compliance-mtk-vcodec-enc
181 01:23:54.036123 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:23:54.036210 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:23:54.042917 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:23:54.043035 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:23:54.043122 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:23:54.043206 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:23:54.043293 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:23:54.770985 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:23:54.771505 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:23:54.771690 extracting modules file /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11368524/extract-overlay-ramdisk-zibsmin4/ramdisk
191 01:23:55.023878 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:23:55.024053 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:23:55.024152 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368524/compress-overlay-26w9t8cn/overlay-1.5.2.4.tar.gz to ramdisk
194 01:23:55.024226 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368524/compress-overlay-26w9t8cn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11368524/extract-overlay-ramdisk-zibsmin4/ramdisk
195 01:23:55.031055 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:23:55.031195 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:23:55.031293 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:23:55.031407 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:23:55.031500 Building ramdisk /var/lib/lava/dispatcher/tmp/11368524/extract-overlay-ramdisk-zibsmin4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11368524/extract-overlay-ramdisk-zibsmin4/ramdisk
200 01:23:55.704167 >> 228248 blocks
201 01:23:59.707409 rename /var/lib/lava/dispatcher/tmp/11368524/extract-overlay-ramdisk-zibsmin4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/ramdisk/ramdisk.cpio.gz
202 01:23:59.707951 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 01:23:59.708080 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 01:23:59.708187 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 01:23:59.708299 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/kernel/Image'
206 01:24:12.842478 Returned 0 in 13 seconds
207 01:24:12.943239 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/kernel/image.itb
208 01:24:13.569694 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:24:13.570165 output: Created: Mon Aug 28 02:24:13 2023
210 01:24:13.570277 output: Image 0 (kernel-1)
211 01:24:13.570379 output: Description:
212 01:24:13.570479 output: Created: Mon Aug 28 02:24:13 2023
213 01:24:13.570580 output: Type: Kernel Image
214 01:24:13.570674 output: Compression: lzma compressed
215 01:24:13.570769 output: Data Size: 11038667 Bytes = 10779.95 KiB = 10.53 MiB
216 01:24:13.570865 output: Architecture: AArch64
217 01:24:13.570961 output: OS: Linux
218 01:24:13.571058 output: Load Address: 0x00000000
219 01:24:13.571148 output: Entry Point: 0x00000000
220 01:24:13.571238 output: Hash algo: crc32
221 01:24:13.571326 output: Hash value: 3affb6e1
222 01:24:13.571424 output: Image 1 (fdt-1)
223 01:24:13.571514 output: Description: mt8192-asurada-spherion-r0
224 01:24:13.571605 output: Created: Mon Aug 28 02:24:13 2023
225 01:24:13.571695 output: Type: Flat Device Tree
226 01:24:13.571785 output: Compression: uncompressed
227 01:24:13.571874 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 01:24:13.571962 output: Architecture: AArch64
229 01:24:13.572050 output: Hash algo: crc32
230 01:24:13.572140 output: Hash value: cc4352de
231 01:24:13.572229 output: Image 2 (ramdisk-1)
232 01:24:13.572319 output: Description: unavailable
233 01:24:13.572407 output: Created: Mon Aug 28 02:24:13 2023
234 01:24:13.572495 output: Type: RAMDisk Image
235 01:24:13.572584 output: Compression: Unknown Compression
236 01:24:13.572673 output: Data Size: 39327600 Bytes = 38405.86 KiB = 37.51 MiB
237 01:24:13.572762 output: Architecture: AArch64
238 01:24:13.572849 output: OS: Linux
239 01:24:13.572937 output: Load Address: unavailable
240 01:24:13.573024 output: Entry Point: unavailable
241 01:24:13.573111 output: Hash algo: crc32
242 01:24:13.573199 output: Hash value: e6220a05
243 01:24:13.573286 output: Default Configuration: 'conf-1'
244 01:24:13.573373 output: Configuration 0 (conf-1)
245 01:24:13.573461 output: Description: mt8192-asurada-spherion-r0
246 01:24:13.573548 output: Kernel: kernel-1
247 01:24:13.573636 output: Init Ramdisk: ramdisk-1
248 01:24:13.573723 output: FDT: fdt-1
249 01:24:13.573811 output: Loadables: kernel-1
250 01:24:13.573897 output:
251 01:24:13.574168 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:24:13.574311 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:24:13.574463 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 01:24:13.574604 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 01:24:13.574727 No LXC device requested
256 01:24:13.574851 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:24:13.574984 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 01:24:13.575102 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:24:13.575218 Checking files for TFTP limit of 4294967296 bytes.
260 01:24:13.575912 end: 1 tftp-deploy (duration 00:00:21) [common]
261 01:24:13.576050 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:24:13.576181 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:24:13.576352 substitutions:
264 01:24:13.576452 - {DTB}: 11368524/tftp-deploy-rw4vapas/dtb/mt8192-asurada-spherion-r0.dtb
265 01:24:13.576549 - {INITRD}: 11368524/tftp-deploy-rw4vapas/ramdisk/ramdisk.cpio.gz
266 01:24:13.576642 - {KERNEL}: 11368524/tftp-deploy-rw4vapas/kernel/Image
267 01:24:13.576733 - {LAVA_MAC}: None
268 01:24:13.576823 - {PRESEED_CONFIG}: None
269 01:24:13.576912 - {PRESEED_LOCAL}: None
270 01:24:13.577001 - {RAMDISK}: 11368524/tftp-deploy-rw4vapas/ramdisk/ramdisk.cpio.gz
271 01:24:13.577090 - {ROOT_PART}: None
272 01:24:13.577179 - {ROOT}: None
273 01:24:13.577266 - {SERVER_IP}: 192.168.201.1
274 01:24:13.577354 - {TEE}: None
275 01:24:13.577441 Parsed boot commands:
276 01:24:13.577528 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:24:13.577770 Parsed boot commands: tftpboot 192.168.201.1 11368524/tftp-deploy-rw4vapas/kernel/image.itb 11368524/tftp-deploy-rw4vapas/kernel/cmdline
278 01:24:13.577905 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:24:13.578031 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:24:13.578166 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:24:13.578294 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:24:13.578404 Not connected, no need to disconnect.
283 01:24:13.578520 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:24:13.578645 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:24:13.578752 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 01:24:13.583503 Setting prompt string to ['lava-test: # ']
287 01:24:13.583956 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:24:13.584128 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:24:13.584300 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:24:13.584446 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:24:13.584746 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 01:24:18.728038 >> Command sent successfully.
293 01:24:18.738706 Returned 0 in 5 seconds
294 01:24:18.839879 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:24:18.841328 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:24:18.841827 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:24:18.842251 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:24:18.842580 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:24:18.842932 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:24:18.844332 [Enter `^Ec?' for help]
302 01:24:19.005381
303 01:24:19.005901
304 01:24:19.006237 F0: 102B 0000
305 01:24:19.006556
306 01:24:19.006857 F3: 1001 0000 [0200]
307 01:24:19.007920
308 01:24:19.008358 F3: 1001 0000
309 01:24:19.008699
310 01:24:19.009015 F7: 102D 0000
311 01:24:19.009320
312 01:24:19.011572 F1: 0000 0000
313 01:24:19.012004
314 01:24:19.012345 V0: 0000 0000 [0001]
315 01:24:19.012677
316 01:24:19.014966 00: 0007 8000
317 01:24:19.015546
318 01:24:19.015909 01: 0000 0000
319 01:24:19.016241
320 01:24:19.018722 BP: 0C00 0209 [0000]
321 01:24:19.019152
322 01:24:19.019541 G0: 1182 0000
323 01:24:19.019869
324 01:24:19.021833 EC: 0000 0021 [4000]
325 01:24:19.022262
326 01:24:19.022602 S7: 0000 0000 [0000]
327 01:24:19.022925
328 01:24:19.025456 CC: 0000 0000 [0001]
329 01:24:19.025888
330 01:24:19.026234 T0: 0000 0040 [010F]
331 01:24:19.026570
332 01:24:19.026881 Jump to BL
333 01:24:19.028843
334 01:24:19.052162
335 01:24:19.052685
336 01:24:19.053028
337 01:24:19.058536 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:24:19.062132 ARM64: Exception handlers installed.
339 01:24:19.066047 ARM64: Testing exception
340 01:24:19.069079 ARM64: Done test exception
341 01:24:19.076080 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:24:19.086293 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:24:19.093248 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:24:19.103569 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:24:19.109926 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:24:19.120269 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:24:19.130870 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:24:19.136974 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:24:19.154958 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:24:19.158102 WDT: Last reset was cold boot
351 01:24:19.161689 SPI1(PAD0) initialized at 2873684 Hz
352 01:24:19.165011 SPI5(PAD0) initialized at 992727 Hz
353 01:24:19.168010 VBOOT: Loading verstage.
354 01:24:19.174604 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:24:19.178014 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:24:19.182231 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:24:19.185358 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:24:19.192618 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:24:19.198865 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:24:19.210237 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 01:24:19.210805
362 01:24:19.211167
363 01:24:19.220288 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:24:19.223422 ARM64: Exception handlers installed.
365 01:24:19.227181 ARM64: Testing exception
366 01:24:19.227819 ARM64: Done test exception
367 01:24:19.233832 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:24:19.237693 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:24:19.251450 Probing TPM: . done!
370 01:24:19.252037 TPM ready after 0 ms
371 01:24:19.258025 Connected to device vid:did:rid of 1ae0:0028:00
372 01:24:19.264563 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 01:24:19.305760 Initialized TPM device CR50 revision 0
374 01:24:19.318183 tlcl_send_startup: Startup return code is 0
375 01:24:19.318792 TPM: setup succeeded
376 01:24:19.328981 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:24:19.337683 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:24:19.350170 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:24:19.358552 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:24:19.361827 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:24:19.365527 in-header: 03 07 00 00 08 00 00 00
382 01:24:19.369021 in-data: aa e4 47 04 13 02 00 00
383 01:24:19.372519 Chrome EC: UHEPI supported
384 01:24:19.380019 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:24:19.383626 in-header: 03 9d 00 00 08 00 00 00
386 01:24:19.387281 in-data: 10 20 20 08 00 00 00 00
387 01:24:19.387861 Phase 1
388 01:24:19.390814 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:24:19.397961 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:24:19.405624 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:24:19.406053 Recovery requested (1009000e)
392 01:24:19.413445 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:24:19.419320 tlcl_extend: response is 0
394 01:24:19.426872 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:24:19.433124 tlcl_extend: response is 0
396 01:24:19.438920 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:24:19.460462 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 01:24:19.467673 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:24:19.468330
400 01:24:19.468707
401 01:24:19.475183 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:24:19.478750 ARM64: Exception handlers installed.
403 01:24:19.482389 ARM64: Testing exception
404 01:24:19.485618 ARM64: Done test exception
405 01:24:19.506102 pmic_efuse_setting: Set efuses in 11 msecs
406 01:24:19.509627 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:24:19.513130 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:24:19.520610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:24:19.524190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:24:19.527516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:24:19.535142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:24:19.538630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:24:19.542594 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:24:19.549368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:24:19.552565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:24:19.555820 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:24:19.563100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:24:19.566016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:24:19.573233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:24:19.576416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:24:19.582745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:24:19.589355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:24:19.596385 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:24:19.599453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:24:19.606799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:24:19.610264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:24:19.617686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:24:19.620853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:24:19.627496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:24:19.634816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:24:19.638314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:24:19.644427 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:24:19.648742 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:24:19.655903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:24:19.659403 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:24:19.665909 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:24:19.669295 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:24:19.673183 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:24:19.681106 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:24:19.684670 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:24:19.688742 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:24:19.695838 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:24:19.699146 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:24:19.702682 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:24:19.709226 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:24:19.712887 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:24:19.716220 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:24:19.722922 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:24:19.725613 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:24:19.729178 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:24:19.735886 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:24:19.738998 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:24:19.742515 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:24:19.749158 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:24:19.752635 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:24:19.756075 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:24:19.758934 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:24:19.769579 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:24:19.775593 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:24:19.782032 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:24:19.788912 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:24:19.798874 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:24:19.802313 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:24:19.805512 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:24:19.812929 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:24:19.819694 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x4
467 01:24:19.822371 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:24:19.829851 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 01:24:19.833118 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:24:19.842608 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 01:24:19.845997 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 01:24:19.852649 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 01:24:19.856026 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 01:24:19.859144 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 01:24:19.862736 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 01:24:19.865742 ADC[4]: Raw value=894081 ID=7
477 01:24:19.869073 ADC[3]: Raw value=213070 ID=1
478 01:24:19.869553 RAM Code: 0x71
479 01:24:19.875883 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 01:24:19.879196 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 01:24:19.889546 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 01:24:19.896413 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 01:24:19.900032 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 01:24:19.903009 in-header: 03 07 00 00 08 00 00 00
485 01:24:19.906409 in-data: aa e4 47 04 13 02 00 00
486 01:24:19.906882 Chrome EC: UHEPI supported
487 01:24:19.913421 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 01:24:19.917357 in-header: 03 d5 00 00 08 00 00 00
489 01:24:19.920955 in-data: 98 20 60 08 00 00 00 00
490 01:24:19.924533 MRC: failed to locate region type 0.
491 01:24:19.932241 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 01:24:19.935789 DRAM-K: Running full calibration
493 01:24:19.942320 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 01:24:19.942771 header.status = 0x0
495 01:24:19.945688 header.version = 0x6 (expected: 0x6)
496 01:24:19.948822 header.size = 0xd00 (expected: 0xd00)
497 01:24:19.949056 header.flags = 0x0
498 01:24:19.956159 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 01:24:19.974588 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
500 01:24:19.980959 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 01:24:19.984994 dram_init: ddr_geometry: 2
502 01:24:19.987662 [EMI] MDL number = 2
503 01:24:19.987850 [EMI] Get MDL freq = 0
504 01:24:19.990941 dram_init: ddr_type: 0
505 01:24:19.991129 is_discrete_lpddr4: 1
506 01:24:19.994812 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 01:24:19.994999
508 01:24:19.995147
509 01:24:19.997864 [Bian_co] ETT version 0.0.0.1
510 01:24:20.004696 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 01:24:20.004883
512 01:24:20.007873 dramc_set_vcore_voltage set vcore to 650000
513 01:24:20.008076 Read voltage for 800, 4
514 01:24:20.011474 Vio18 = 0
515 01:24:20.011658 Vcore = 650000
516 01:24:20.011802 Vdram = 0
517 01:24:20.014477 Vddq = 0
518 01:24:20.014659 Vmddr = 0
519 01:24:20.017604 dram_init: config_dvfs: 1
520 01:24:20.021164 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 01:24:20.027483 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 01:24:20.030893 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 01:24:20.034467 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 01:24:20.037668 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 01:24:20.041356 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 01:24:20.044337 MEM_TYPE=3, freq_sel=18
527 01:24:20.047767 sv_algorithm_assistance_LP4_1600
528 01:24:20.051526 ============ PULL DRAM RESETB DOWN ============
529 01:24:20.054639 ========== PULL DRAM RESETB DOWN end =========
530 01:24:20.061228 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 01:24:20.064399 ===================================
532 01:24:20.064635 LPDDR4 DRAM CONFIGURATION
533 01:24:20.067979 ===================================
534 01:24:20.070757 EX_ROW_EN[0] = 0x0
535 01:24:20.074517 EX_ROW_EN[1] = 0x0
536 01:24:20.074693 LP4Y_EN = 0x0
537 01:24:20.078039 WORK_FSP = 0x0
538 01:24:20.078241 WL = 0x2
539 01:24:20.081941 RL = 0x2
540 01:24:20.082217 BL = 0x2
541 01:24:20.085391 RPST = 0x0
542 01:24:20.085634 RD_PRE = 0x0
543 01:24:20.085828 WR_PRE = 0x1
544 01:24:20.089282 WR_PST = 0x0
545 01:24:20.089593 DBI_WR = 0x0
546 01:24:20.093270 DBI_RD = 0x0
547 01:24:20.093663 OTF = 0x1
548 01:24:20.096645 ===================================
549 01:24:20.101253 ===================================
550 01:24:20.101982 ANA top config
551 01:24:20.104510 ===================================
552 01:24:20.108444 DLL_ASYNC_EN = 0
553 01:24:20.112161 ALL_SLAVE_EN = 1
554 01:24:20.112607 NEW_RANK_MODE = 1
555 01:24:20.115730 DLL_IDLE_MODE = 1
556 01:24:20.119631 LP45_APHY_COMB_EN = 1
557 01:24:20.120062 TX_ODT_DIS = 1
558 01:24:20.123445 NEW_8X_MODE = 1
559 01:24:20.127291 ===================================
560 01:24:20.130839 ===================================
561 01:24:20.134696 data_rate = 1600
562 01:24:20.135160 CKR = 1
563 01:24:20.138534 DQ_P2S_RATIO = 8
564 01:24:20.142047 ===================================
565 01:24:20.146059 CA_P2S_RATIO = 8
566 01:24:20.146484 DQ_CA_OPEN = 0
567 01:24:20.149283 DQ_SEMI_OPEN = 0
568 01:24:20.153136 CA_SEMI_OPEN = 0
569 01:24:20.156450 CA_FULL_RATE = 0
570 01:24:20.160659 DQ_CKDIV4_EN = 1
571 01:24:20.161091 CA_CKDIV4_EN = 1
572 01:24:20.164360 CA_PREDIV_EN = 0
573 01:24:20.167359 PH8_DLY = 0
574 01:24:20.170833 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 01:24:20.171362 DQ_AAMCK_DIV = 4
576 01:24:20.173999 CA_AAMCK_DIV = 4
577 01:24:20.177526 CA_ADMCK_DIV = 4
578 01:24:20.180573 DQ_TRACK_CA_EN = 0
579 01:24:20.183969 CA_PICK = 800
580 01:24:20.187527 CA_MCKIO = 800
581 01:24:20.190538 MCKIO_SEMI = 0
582 01:24:20.191278 PLL_FREQ = 3068
583 01:24:20.193954 DQ_UI_PI_RATIO = 32
584 01:24:20.197575 CA_UI_PI_RATIO = 0
585 01:24:20.200928 ===================================
586 01:24:20.203857 ===================================
587 01:24:20.207293 memory_type:LPDDR4
588 01:24:20.207914 GP_NUM : 10
589 01:24:20.210538 SRAM_EN : 1
590 01:24:20.213919 MD32_EN : 0
591 01:24:20.217071 ===================================
592 01:24:20.217620 [ANA_INIT] >>>>>>>>>>>>>>
593 01:24:20.220619 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 01:24:20.224109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 01:24:20.227353 ===================================
596 01:24:20.230717 data_rate = 1600,PCW = 0X7600
597 01:24:20.234765 ===================================
598 01:24:20.237778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 01:24:20.244779 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 01:24:20.247509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 01:24:20.254070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 01:24:20.257583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 01:24:20.261646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 01:24:20.262225 [ANA_INIT] flow start
605 01:24:20.264551 [ANA_INIT] PLL >>>>>>>>
606 01:24:20.268574 [ANA_INIT] PLL <<<<<<<<
607 01:24:20.269008 [ANA_INIT] MIDPI >>>>>>>>
608 01:24:20.272413 [ANA_INIT] MIDPI <<<<<<<<
609 01:24:20.275582 [ANA_INIT] DLL >>>>>>>>
610 01:24:20.276022 [ANA_INIT] flow end
611 01:24:20.279582 ============ LP4 DIFF to SE enter ============
612 01:24:20.283904 ============ LP4 DIFF to SE exit ============
613 01:24:20.287220 [ANA_INIT] <<<<<<<<<<<<<
614 01:24:20.291094 [Flow] Enable top DCM control >>>>>
615 01:24:20.294744 [Flow] Enable top DCM control <<<<<
616 01:24:20.295181 Enable DLL master slave shuffle
617 01:24:20.302545 ==============================================================
618 01:24:20.303084 Gating Mode config
619 01:24:20.308876 ==============================================================
620 01:24:20.309315 Config description:
621 01:24:20.319137 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 01:24:20.325841 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 01:24:20.332658 SELPH_MODE 0: By rank 1: By Phase
624 01:24:20.336171 ==============================================================
625 01:24:20.339422 GAT_TRACK_EN = 1
626 01:24:20.342763 RX_GATING_MODE = 2
627 01:24:20.345717 RX_GATING_TRACK_MODE = 2
628 01:24:20.349177 SELPH_MODE = 1
629 01:24:20.352231 PICG_EARLY_EN = 1
630 01:24:20.355581 VALID_LAT_VALUE = 1
631 01:24:20.359136 ==============================================================
632 01:24:20.362399 Enter into Gating configuration >>>>
633 01:24:20.366145 Exit from Gating configuration <<<<
634 01:24:20.369265 Enter into DVFS_PRE_config >>>>>
635 01:24:20.382242 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 01:24:20.385725 Exit from DVFS_PRE_config <<<<<
637 01:24:20.389353 Enter into PICG configuration >>>>
638 01:24:20.392114 Exit from PICG configuration <<<<
639 01:24:20.392551 [RX_INPUT] configuration >>>>>
640 01:24:20.395434 [RX_INPUT] configuration <<<<<
641 01:24:20.402588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 01:24:20.406420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 01:24:20.412595 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 01:24:20.418923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 01:24:20.426555 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 01:24:20.432855 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 01:24:20.435692 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 01:24:20.439427 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 01:24:20.442588 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 01:24:20.449239 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 01:24:20.452509 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 01:24:20.455781 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 01:24:20.459156 ===================================
654 01:24:20.462254 LPDDR4 DRAM CONFIGURATION
655 01:24:20.465815 ===================================
656 01:24:20.469014 EX_ROW_EN[0] = 0x0
657 01:24:20.469518 EX_ROW_EN[1] = 0x0
658 01:24:20.472184 LP4Y_EN = 0x0
659 01:24:20.472806 WORK_FSP = 0x0
660 01:24:20.475758 WL = 0x2
661 01:24:20.476483 RL = 0x2
662 01:24:20.478938 BL = 0x2
663 01:24:20.479515 RPST = 0x0
664 01:24:20.482563 RD_PRE = 0x0
665 01:24:20.483059 WR_PRE = 0x1
666 01:24:20.485960 WR_PST = 0x0
667 01:24:20.486478 DBI_WR = 0x0
668 01:24:20.489212 DBI_RD = 0x0
669 01:24:20.489871 OTF = 0x1
670 01:24:20.492694 ===================================
671 01:24:20.495579 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 01:24:20.502558 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 01:24:20.505723 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 01:24:20.509428 ===================================
675 01:24:20.512355 LPDDR4 DRAM CONFIGURATION
676 01:24:20.515744 ===================================
677 01:24:20.516350 EX_ROW_EN[0] = 0x10
678 01:24:20.518803 EX_ROW_EN[1] = 0x0
679 01:24:20.519322 LP4Y_EN = 0x0
680 01:24:20.522281 WORK_FSP = 0x0
681 01:24:20.526003 WL = 0x2
682 01:24:20.526429 RL = 0x2
683 01:24:20.529121 BL = 0x2
684 01:24:20.529547 RPST = 0x0
685 01:24:20.532644 RD_PRE = 0x0
686 01:24:20.533071 WR_PRE = 0x1
687 01:24:20.535943 WR_PST = 0x0
688 01:24:20.536369 DBI_WR = 0x0
689 01:24:20.539059 DBI_RD = 0x0
690 01:24:20.539745 OTF = 0x1
691 01:24:20.542802 ===================================
692 01:24:20.549291 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 01:24:20.553612 nWR fixed to 40
694 01:24:20.557178 [ModeRegInit_LP4] CH0 RK0
695 01:24:20.557607 [ModeRegInit_LP4] CH0 RK1
696 01:24:20.560515 [ModeRegInit_LP4] CH1 RK0
697 01:24:20.560944 [ModeRegInit_LP4] CH1 RK1
698 01:24:20.564633 match AC timing 13
699 01:24:20.568038 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 01:24:20.571737 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 01:24:20.575138 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 01:24:20.582627 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 01:24:20.586030 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 01:24:20.586458 [EMI DOE] emi_dcm 0
705 01:24:20.593452 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 01:24:20.593880 ==
707 01:24:20.597242 Dram Type= 6, Freq= 0, CH_0, rank 0
708 01:24:20.601296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 01:24:20.601727 ==
710 01:24:20.604642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 01:24:20.611913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 01:24:20.620323 [CA 0] Center 38 (7~69) winsize 63
713 01:24:20.623898 [CA 1] Center 38 (7~69) winsize 63
714 01:24:20.627620 [CA 2] Center 35 (5~66) winsize 62
715 01:24:20.631461 [CA 3] Center 35 (5~66) winsize 62
716 01:24:20.635387 [CA 4] Center 34 (4~65) winsize 62
717 01:24:20.635482 [CA 5] Center 34 (4~64) winsize 61
718 01:24:20.639224
719 01:24:20.642767 [CmdBusTrainingLP45] Vref(ca) range 1: 30
720 01:24:20.642852
721 01:24:20.646227 [CATrainingPosCal] consider 1 rank data
722 01:24:20.646312 u2DelayCellTimex100 = 270/100 ps
723 01:24:20.650253 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 01:24:20.653739 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
725 01:24:20.658056 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 01:24:20.661189 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 01:24:20.664982 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 01:24:20.668849 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 01:24:20.668947
730 01:24:20.672500 CA PerBit enable=1, Macro0, CA PI delay=34
731 01:24:20.672598
732 01:24:20.676213 [CBTSetCACLKResult] CA Dly = 34
733 01:24:20.680320 CS Dly: 5 (0~36)
734 01:24:20.680862 ==
735 01:24:20.683585 Dram Type= 6, Freq= 0, CH_0, rank 1
736 01:24:20.687191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 01:24:20.687797 ==
738 01:24:20.691259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 01:24:20.698017 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 01:24:20.707032 [CA 0] Center 38 (7~69) winsize 63
741 01:24:20.710991 [CA 1] Center 38 (7~69) winsize 63
742 01:24:20.714304 [CA 2] Center 35 (5~66) winsize 62
743 01:24:20.718095 [CA 3] Center 35 (5~66) winsize 62
744 01:24:20.721930 [CA 4] Center 34 (4~65) winsize 62
745 01:24:20.722389 [CA 5] Center 34 (4~65) winsize 62
746 01:24:20.725744
747 01:24:20.729871 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 01:24:20.730308
749 01:24:20.733279 [CATrainingPosCal] consider 2 rank data
750 01:24:20.733827 u2DelayCellTimex100 = 270/100 ps
751 01:24:20.737271 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 01:24:20.740988 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
753 01:24:20.744639 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 01:24:20.748645 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 01:24:20.752135 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 01:24:20.756409 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 01:24:20.756987
758 01:24:20.759661 CA PerBit enable=1, Macro0, CA PI delay=34
759 01:24:20.760173
760 01:24:20.763437 [CBTSetCACLKResult] CA Dly = 34
761 01:24:20.763873 CS Dly: 6 (0~38)
762 01:24:20.764428
763 01:24:20.767189 ----->DramcWriteLeveling(PI) begin...
764 01:24:20.767840 ==
765 01:24:20.771257 Dram Type= 6, Freq= 0, CH_0, rank 0
766 01:24:20.774427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 01:24:20.775065 ==
768 01:24:20.777904 Write leveling (Byte 0): 31 => 31
769 01:24:20.782024 Write leveling (Byte 1): 29 => 29
770 01:24:20.785461 DramcWriteLeveling(PI) end<-----
771 01:24:20.785896
772 01:24:20.786242 ==
773 01:24:20.789153 Dram Type= 6, Freq= 0, CH_0, rank 0
774 01:24:20.792689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 01:24:20.793266 ==
776 01:24:20.796651 [Gating] SW mode calibration
777 01:24:20.804056 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 01:24:20.807692 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 01:24:20.811128 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 01:24:20.818610 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 01:24:20.822439 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 01:24:20.825783 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 01:24:20.829954 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 01:24:20.833677 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 01:24:20.840981 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 01:24:20.844368 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 01:24:20.847838 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 01:24:20.852032 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 01:24:20.855919 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:24:20.859148 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:24:20.866180 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:24:20.869835 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:24:20.873351 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:24:20.876744 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:24:20.884005 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:24:20.887065 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 01:24:20.890325 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 01:24:20.896958 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 01:24:20.900708 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:24:20.903704 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:24:20.910284 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:24:20.913828 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:24:20.916994 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 01:24:20.923965 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 01:24:20.927844 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
806 01:24:20.930118 0 9 12 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
807 01:24:20.936967 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 01:24:20.940428 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 01:24:20.943831 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 01:24:20.950177 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 01:24:20.953601 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 01:24:20.957118 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 01:24:20.960532 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
814 01:24:20.967221 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
815 01:24:20.970226 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 01:24:20.974196 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 01:24:20.980647 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 01:24:20.983858 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 01:24:20.987269 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 01:24:20.993825 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 01:24:20.996958 0 11 8 | B1->B0 | 2727 3030 | 0 1 | (0 0) (0 0)
822 01:24:21.000210 0 11 12 | B1->B0 | 3333 4141 | 1 1 | (1 1) (0 0)
823 01:24:21.006792 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 01:24:21.009764 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 01:24:21.013294 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 01:24:21.019755 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 01:24:21.023125 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 01:24:21.026266 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 01:24:21.033022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 01:24:21.036100 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 01:24:21.039852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 01:24:21.046084 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 01:24:21.049779 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 01:24:21.053260 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 01:24:21.059706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 01:24:21.062890 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 01:24:21.066557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 01:24:21.072797 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:24:21.076383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:24:21.079750 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:24:21.086476 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:24:21.089901 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:24:21.092858 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:24:21.096459 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:24:21.103129 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:24:21.106787 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 01:24:21.109762 Total UI for P1: 0, mck2ui 16
848 01:24:21.113236 best dqsien dly found for B0: ( 0, 14, 10)
849 01:24:21.116860 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 01:24:21.119844 Total UI for P1: 0, mck2ui 16
851 01:24:21.123441 best dqsien dly found for B1: ( 0, 14, 12)
852 01:24:21.126561 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
853 01:24:21.129737 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 01:24:21.133130
855 01:24:21.136479 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 01:24:21.139885 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 01:24:21.143444 [Gating] SW calibration Done
858 01:24:21.143894 ==
859 01:24:21.146315 Dram Type= 6, Freq= 0, CH_0, rank 0
860 01:24:21.150087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 01:24:21.150537 ==
862 01:24:21.151039 RX Vref Scan: 0
863 01:24:21.151588
864 01:24:21.153475 RX Vref 0 -> 0, step: 1
865 01:24:21.153905
866 01:24:21.156307 RX Delay -130 -> 252, step: 16
867 01:24:21.160151 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 01:24:21.163430 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 01:24:21.169648 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 01:24:21.173314 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 01:24:21.176674 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 01:24:21.179954 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 01:24:21.183057 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 01:24:21.190205 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 01:24:21.193267 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 01:24:21.196272 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 01:24:21.199924 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 01:24:21.203238 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 01:24:21.210184 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 01:24:21.213036 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 01:24:21.216657 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 01:24:21.219494 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 01:24:21.219929 ==
884 01:24:21.222933 Dram Type= 6, Freq= 0, CH_0, rank 0
885 01:24:21.229696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 01:24:21.230130 ==
887 01:24:21.230470 DQS Delay:
888 01:24:21.233360 DQS0 = 0, DQS1 = 0
889 01:24:21.233791 DQM Delay:
890 01:24:21.234132 DQM0 = 82, DQM1 = 69
891 01:24:21.236659 DQ Delay:
892 01:24:21.239440 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 01:24:21.243470 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 01:24:21.246242 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 01:24:21.249517 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 01:24:21.249943
897 01:24:21.250278
898 01:24:21.250589 ==
899 01:24:21.253764 Dram Type= 6, Freq= 0, CH_0, rank 0
900 01:24:21.256852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 01:24:21.257295 ==
902 01:24:21.257644
903 01:24:21.257964
904 01:24:21.260377 TX Vref Scan disable
905 01:24:21.260815 == TX Byte 0 ==
906 01:24:21.263527 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
907 01:24:21.270542 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
908 01:24:21.270981 == TX Byte 1 ==
909 01:24:21.273697 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
910 01:24:21.280379 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
911 01:24:21.280820 ==
912 01:24:21.283764 Dram Type= 6, Freq= 0, CH_0, rank 0
913 01:24:21.287103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 01:24:21.287590 ==
915 01:24:21.300551 TX Vref=22, minBit 1, minWin=26, winSum=433
916 01:24:21.303919 TX Vref=24, minBit 11, minWin=26, winSum=438
917 01:24:21.307121 TX Vref=26, minBit 8, minWin=27, winSum=443
918 01:24:21.310400 TX Vref=28, minBit 0, minWin=27, winSum=443
919 01:24:21.314267 TX Vref=30, minBit 9, minWin=27, winSum=443
920 01:24:21.316887 TX Vref=32, minBit 9, minWin=26, winSum=441
921 01:24:21.323991 [TxChooseVref] Worse bit 8, Min win 27, Win sum 443, Final Vref 26
922 01:24:21.324434
923 01:24:21.327097 Final TX Range 1 Vref 26
924 01:24:21.327635
925 01:24:21.328007 ==
926 01:24:21.330455 Dram Type= 6, Freq= 0, CH_0, rank 0
927 01:24:21.333836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 01:24:21.334274 ==
929 01:24:21.334624
930 01:24:21.336796
931 01:24:21.337278 TX Vref Scan disable
932 01:24:21.340143 == TX Byte 0 ==
933 01:24:21.343453 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
934 01:24:21.350421 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
935 01:24:21.350861 == TX Byte 1 ==
936 01:24:21.353535 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
937 01:24:21.360271 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
938 01:24:21.360708
939 01:24:21.361050 [DATLAT]
940 01:24:21.361370 Freq=800, CH0 RK0
941 01:24:21.361682
942 01:24:21.363850 DATLAT Default: 0xa
943 01:24:21.364302 0, 0xFFFF, sum = 0
944 01:24:21.367081 1, 0xFFFF, sum = 0
945 01:24:21.367568 2, 0xFFFF, sum = 0
946 01:24:21.370477 3, 0xFFFF, sum = 0
947 01:24:21.370914 4, 0xFFFF, sum = 0
948 01:24:21.373609 5, 0xFFFF, sum = 0
949 01:24:21.376668 6, 0xFFFF, sum = 0
950 01:24:21.377111 7, 0xFFFF, sum = 0
951 01:24:21.380184 8, 0xFFFF, sum = 0
952 01:24:21.380628 9, 0x0, sum = 1
953 01:24:21.380977 10, 0x0, sum = 2
954 01:24:21.383847 11, 0x0, sum = 3
955 01:24:21.384286 12, 0x0, sum = 4
956 01:24:21.387040 best_step = 10
957 01:24:21.387589
958 01:24:21.387950 ==
959 01:24:21.390238 Dram Type= 6, Freq= 0, CH_0, rank 0
960 01:24:21.393485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 01:24:21.393927 ==
962 01:24:21.397043 RX Vref Scan: 1
963 01:24:21.397476
964 01:24:21.397818 Set Vref Range= 32 -> 127
965 01:24:21.398140
966 01:24:21.400096 RX Vref 32 -> 127, step: 1
967 01:24:21.400528
968 01:24:21.403500 RX Delay -111 -> 252, step: 8
969 01:24:21.404071
970 01:24:21.406805 Set Vref, RX VrefLevel [Byte0]: 32
971 01:24:21.410143 [Byte1]: 32
972 01:24:21.410579
973 01:24:21.413516 Set Vref, RX VrefLevel [Byte0]: 33
974 01:24:21.417049 [Byte1]: 33
975 01:24:21.420676
976 01:24:21.421108 Set Vref, RX VrefLevel [Byte0]: 34
977 01:24:21.424025 [Byte1]: 34
978 01:24:21.428268
979 01:24:21.428360 Set Vref, RX VrefLevel [Byte0]: 35
980 01:24:21.431131 [Byte1]: 35
981 01:24:21.435704
982 01:24:21.435788 Set Vref, RX VrefLevel [Byte0]: 36
983 01:24:21.439797 [Byte1]: 36
984 01:24:21.443730
985 01:24:21.443870 Set Vref, RX VrefLevel [Byte0]: 37
986 01:24:21.447094 [Byte1]: 37
987 01:24:21.450959
988 01:24:21.451044 Set Vref, RX VrefLevel [Byte0]: 38
989 01:24:21.454158 [Byte1]: 38
990 01:24:21.458680
991 01:24:21.461692 Set Vref, RX VrefLevel [Byte0]: 39
992 01:24:21.465120 [Byte1]: 39
993 01:24:21.465211
994 01:24:21.468597 Set Vref, RX VrefLevel [Byte0]: 40
995 01:24:21.471887 [Byte1]: 40
996 01:24:21.471984
997 01:24:21.474942 Set Vref, RX VrefLevel [Byte0]: 41
998 01:24:21.478213 [Byte1]: 41
999 01:24:21.478319
1000 01:24:21.481540 Set Vref, RX VrefLevel [Byte0]: 42
1001 01:24:21.484843 [Byte1]: 42
1002 01:24:21.489486
1003 01:24:21.489625 Set Vref, RX VrefLevel [Byte0]: 43
1004 01:24:21.492586 [Byte1]: 43
1005 01:24:21.497375
1006 01:24:21.497532 Set Vref, RX VrefLevel [Byte0]: 44
1007 01:24:21.500451 [Byte1]: 44
1008 01:24:21.504863
1009 01:24:21.505042 Set Vref, RX VrefLevel [Byte0]: 45
1010 01:24:21.508503 [Byte1]: 45
1011 01:24:21.512685
1012 01:24:21.512874 Set Vref, RX VrefLevel [Byte0]: 46
1013 01:24:21.516041 [Byte1]: 46
1014 01:24:21.520287
1015 01:24:21.520489 Set Vref, RX VrefLevel [Byte0]: 47
1016 01:24:21.523718 [Byte1]: 47
1017 01:24:21.528461
1018 01:24:21.528664 Set Vref, RX VrefLevel [Byte0]: 48
1019 01:24:21.531324 [Byte1]: 48
1020 01:24:21.536110
1021 01:24:21.536348 Set Vref, RX VrefLevel [Byte0]: 49
1022 01:24:21.539469 [Byte1]: 49
1023 01:24:21.542880
1024 01:24:21.543125 Set Vref, RX VrefLevel [Byte0]: 50
1025 01:24:21.546097 [Byte1]: 50
1026 01:24:21.550272
1027 01:24:21.550533 Set Vref, RX VrefLevel [Byte0]: 51
1028 01:24:21.553720 [Byte1]: 51
1029 01:24:21.558274
1030 01:24:21.561373 Set Vref, RX VrefLevel [Byte0]: 52
1031 01:24:21.561572 [Byte1]: 52
1032 01:24:21.566129
1033 01:24:21.566328 Set Vref, RX VrefLevel [Byte0]: 53
1034 01:24:21.568947 [Byte1]: 53
1035 01:24:21.573775
1036 01:24:21.573975 Set Vref, RX VrefLevel [Byte0]: 54
1037 01:24:21.576771 [Byte1]: 54
1038 01:24:21.581081
1039 01:24:21.581281 Set Vref, RX VrefLevel [Byte0]: 55
1040 01:24:21.584442 [Byte1]: 55
1041 01:24:21.588509
1042 01:24:21.588781 Set Vref, RX VrefLevel [Byte0]: 56
1043 01:24:21.592188 [Byte1]: 56
1044 01:24:21.596729
1045 01:24:21.596927 Set Vref, RX VrefLevel [Byte0]: 57
1046 01:24:21.599596 [Byte1]: 57
1047 01:24:21.603766
1048 01:24:21.603964 Set Vref, RX VrefLevel [Byte0]: 58
1049 01:24:21.607448 [Byte1]: 58
1050 01:24:21.611770
1051 01:24:21.612014 Set Vref, RX VrefLevel [Byte0]: 59
1052 01:24:21.614945 [Byte1]: 59
1053 01:24:21.619211
1054 01:24:21.619634 Set Vref, RX VrefLevel [Byte0]: 60
1055 01:24:21.622545 [Byte1]: 60
1056 01:24:21.627107
1057 01:24:21.627681 Set Vref, RX VrefLevel [Byte0]: 61
1058 01:24:21.630604 [Byte1]: 61
1059 01:24:21.634785
1060 01:24:21.635263 Set Vref, RX VrefLevel [Byte0]: 62
1061 01:24:21.638168 [Byte1]: 62
1062 01:24:21.642309
1063 01:24:21.642772 Set Vref, RX VrefLevel [Byte0]: 63
1064 01:24:21.645697 [Byte1]: 63
1065 01:24:21.650083
1066 01:24:21.650471 Set Vref, RX VrefLevel [Byte0]: 64
1067 01:24:21.653824 [Byte1]: 64
1068 01:24:21.657884
1069 01:24:21.658359 Set Vref, RX VrefLevel [Byte0]: 65
1070 01:24:21.660752 [Byte1]: 65
1071 01:24:21.665132
1072 01:24:21.665522 Set Vref, RX VrefLevel [Byte0]: 66
1073 01:24:21.668767 [Byte1]: 66
1074 01:24:21.673530
1075 01:24:21.674060 Set Vref, RX VrefLevel [Byte0]: 67
1076 01:24:21.676255 [Byte1]: 67
1077 01:24:21.680407
1078 01:24:21.680803 Set Vref, RX VrefLevel [Byte0]: 68
1079 01:24:21.684287 [Byte1]: 68
1080 01:24:21.688201
1081 01:24:21.688592 Set Vref, RX VrefLevel [Byte0]: 69
1082 01:24:21.691863 [Byte1]: 69
1083 01:24:21.696051
1084 01:24:21.696439 Set Vref, RX VrefLevel [Byte0]: 70
1085 01:24:21.699315 [Byte1]: 70
1086 01:24:21.703352
1087 01:24:21.703789 Set Vref, RX VrefLevel [Byte0]: 71
1088 01:24:21.706725 [Byte1]: 71
1089 01:24:21.710989
1090 01:24:21.711565 Set Vref, RX VrefLevel [Byte0]: 72
1091 01:24:21.714234 [Byte1]: 72
1092 01:24:21.718706
1093 01:24:21.719212 Set Vref, RX VrefLevel [Byte0]: 73
1094 01:24:21.722233 [Byte1]: 73
1095 01:24:21.726521
1096 01:24:21.726965 Set Vref, RX VrefLevel [Byte0]: 74
1097 01:24:21.730009 [Byte1]: 74
1098 01:24:21.734380
1099 01:24:21.734760 Set Vref, RX VrefLevel [Byte0]: 75
1100 01:24:21.737531 [Byte1]: 75
1101 01:24:21.741598
1102 01:24:21.741980 Set Vref, RX VrefLevel [Byte0]: 76
1103 01:24:21.744926 [Byte1]: 76
1104 01:24:21.749270
1105 01:24:21.749706 Set Vref, RX VrefLevel [Byte0]: 77
1106 01:24:21.752579 [Byte1]: 77
1107 01:24:21.757059
1108 01:24:21.757450 Set Vref, RX VrefLevel [Byte0]: 78
1109 01:24:21.760495 [Byte1]: 78
1110 01:24:21.764430
1111 01:24:21.764818 Set Vref, RX VrefLevel [Byte0]: 79
1112 01:24:21.768261 [Byte1]: 79
1113 01:24:21.772414
1114 01:24:21.772917 Final RX Vref Byte 0 = 56 to rank0
1115 01:24:21.775880 Final RX Vref Byte 1 = 58 to rank0
1116 01:24:21.778990 Final RX Vref Byte 0 = 56 to rank1
1117 01:24:21.782561 Final RX Vref Byte 1 = 58 to rank1==
1118 01:24:21.785594 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 01:24:21.792647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 01:24:21.793048 ==
1121 01:24:21.793355 DQS Delay:
1122 01:24:21.793641 DQS0 = 0, DQS1 = 0
1123 01:24:21.795757 DQM Delay:
1124 01:24:21.796272 DQM0 = 82, DQM1 = 67
1125 01:24:21.799020 DQ Delay:
1126 01:24:21.802601 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 01:24:21.805583 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1128 01:24:21.806021 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 01:24:21.812596 DQ12 =76, DQ13 =68, DQ14 =76, DQ15 =76
1130 01:24:21.813034
1131 01:24:21.813341
1132 01:24:21.818918 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1133 01:24:21.822167 CH0 RK0: MR19=606, MR18=2525
1134 01:24:21.829182 CH0_RK0: MR19=0x606, MR18=0x2525, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 01:24:21.829676
1136 01:24:21.832400 ----->DramcWriteLeveling(PI) begin...
1137 01:24:21.832793 ==
1138 01:24:21.835708 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 01:24:21.839106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 01:24:21.839818 ==
1141 01:24:21.841914 Write leveling (Byte 0): 32 => 32
1142 01:24:21.845978 Write leveling (Byte 1): 31 => 31
1143 01:24:21.848781 DramcWriteLeveling(PI) end<-----
1144 01:24:21.849177
1145 01:24:21.849480 ==
1146 01:24:21.852307 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 01:24:21.855629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 01:24:21.856118 ==
1149 01:24:21.858925 [Gating] SW mode calibration
1150 01:24:21.865705 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 01:24:21.872816 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 01:24:21.875991 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 01:24:21.879697 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 01:24:21.886563 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 01:24:21.888948 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:24:21.892530 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:24:21.899152 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:24:21.902445 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:24:21.905810 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:24:21.912682 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:24:21.915782 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:24:21.919669 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:24:21.925905 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:24:21.929314 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:24:21.973863 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:24:21.974774 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 01:24:21.975331 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:24:21.975775 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:24:21.976122 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1170 01:24:21.976533 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 01:24:21.976878 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 01:24:21.977198 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:24:21.977518 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:24:21.977832 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:24:22.001560 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:24:22.002677 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:24:22.003130 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:24:22.003617 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1179 01:24:22.004158 0 9 12 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
1180 01:24:22.004665 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:24:22.005288 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 01:24:22.009049 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 01:24:22.012321 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 01:24:22.015865 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 01:24:22.022468 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 01:24:22.026069 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 0)
1187 01:24:22.029098 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1188 01:24:22.035901 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:24:22.039673 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 01:24:22.042891 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 01:24:22.045671 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 01:24:22.052753 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 01:24:22.055582 0 11 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
1194 01:24:22.059506 0 11 8 | B1->B0 | 2e2e 3939 | 1 0 | (0 0) (1 1)
1195 01:24:22.065362 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:24:22.068614 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:24:22.071964 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 01:24:22.078907 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 01:24:22.082116 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 01:24:22.085733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 01:24:22.089609 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 01:24:22.097219 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 01:24:22.100621 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:24:22.103556 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:24:22.110524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:24:22.114010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:24:22.117840 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:24:22.120967 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:24:22.127742 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:24:22.131491 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:24:22.134218 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:24:22.140815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:24:22.144679 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:24:22.147747 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 01:24:22.154089 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 01:24:22.157332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 01:24:22.160904 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 01:24:22.167802 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1219 01:24:22.170579 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 01:24:22.174349 Total UI for P1: 0, mck2ui 16
1221 01:24:22.177279 best dqsien dly found for B0: ( 0, 14, 6)
1222 01:24:22.180732 Total UI for P1: 0, mck2ui 16
1223 01:24:22.184250 best dqsien dly found for B1: ( 0, 14, 10)
1224 01:24:22.187148 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 01:24:22.190643 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1226 01:24:22.191114
1227 01:24:22.193876 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 01:24:22.197403 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1229 01:24:22.200745 [Gating] SW calibration Done
1230 01:24:22.201171 ==
1231 01:24:22.204146 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 01:24:22.207910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 01:24:22.208336 ==
1234 01:24:22.210948 RX Vref Scan: 0
1235 01:24:22.211404
1236 01:24:22.211761 RX Vref 0 -> 0, step: 1
1237 01:24:22.214134
1238 01:24:22.214573 RX Delay -130 -> 252, step: 16
1239 01:24:22.220593 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1240 01:24:22.224410 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1241 01:24:22.227236 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1242 01:24:22.230941 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1243 01:24:22.233755 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1244 01:24:22.240610 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1245 01:24:22.244245 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1246 01:24:22.247087 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1247 01:24:22.250613 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1248 01:24:22.253925 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1249 01:24:22.257110 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1250 01:24:22.264259 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1251 01:24:22.267430 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1252 01:24:22.270747 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1253 01:24:22.274093 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1254 01:24:22.280423 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1255 01:24:22.280937 ==
1256 01:24:22.284028 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 01:24:22.287207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 01:24:22.287787 ==
1259 01:24:22.288306 DQS Delay:
1260 01:24:22.290359 DQS0 = 0, DQS1 = 0
1261 01:24:22.290832 DQM Delay:
1262 01:24:22.293872 DQM0 = 76, DQM1 = 71
1263 01:24:22.294309 DQ Delay:
1264 01:24:22.297126 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1265 01:24:22.300772 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =85
1266 01:24:22.303880 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1267 01:24:22.307553 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1268 01:24:22.307991
1269 01:24:22.308445
1270 01:24:22.308760 ==
1271 01:24:22.310192 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 01:24:22.313911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 01:24:22.314337 ==
1274 01:24:22.314719
1275 01:24:22.315035
1276 01:24:22.317299 TX Vref Scan disable
1277 01:24:22.320704 == TX Byte 0 ==
1278 01:24:22.324207 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1279 01:24:22.327986 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1280 01:24:22.330500 == TX Byte 1 ==
1281 01:24:22.333982 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 01:24:22.337555 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 01:24:22.338075 ==
1284 01:24:22.340880 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 01:24:22.346920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 01:24:22.347864 ==
1287 01:24:22.358559 TX Vref=22, minBit 13, minWin=26, winSum=433
1288 01:24:22.361965 TX Vref=24, minBit 1, minWin=27, winSum=437
1289 01:24:22.365120 TX Vref=26, minBit 1, minWin=27, winSum=437
1290 01:24:22.368700 TX Vref=28, minBit 11, minWin=26, winSum=438
1291 01:24:22.371964 TX Vref=30, minBit 1, minWin=27, winSum=441
1292 01:24:22.378457 TX Vref=32, minBit 11, minWin=26, winSum=441
1293 01:24:22.382273 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
1294 01:24:22.382692
1295 01:24:22.385544 Final TX Range 1 Vref 30
1296 01:24:22.386098
1297 01:24:22.386434 ==
1298 01:24:22.388501 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 01:24:22.392238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 01:24:22.392662 ==
1301 01:24:22.395653
1302 01:24:22.396109
1303 01:24:22.396444 TX Vref Scan disable
1304 01:24:22.398864 == TX Byte 0 ==
1305 01:24:22.402107 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1306 01:24:22.409045 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1307 01:24:22.409633 == TX Byte 1 ==
1308 01:24:22.412573 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 01:24:22.418559 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 01:24:22.419185
1311 01:24:22.419712 [DATLAT]
1312 01:24:22.420168 Freq=800, CH0 RK1
1313 01:24:22.420629
1314 01:24:22.421956 DATLAT Default: 0xa
1315 01:24:22.422432 0, 0xFFFF, sum = 0
1316 01:24:22.425397 1, 0xFFFF, sum = 0
1317 01:24:22.425823 2, 0xFFFF, sum = 0
1318 01:24:22.428596 3, 0xFFFF, sum = 0
1319 01:24:22.429168 4, 0xFFFF, sum = 0
1320 01:24:22.432591 5, 0xFFFF, sum = 0
1321 01:24:22.435336 6, 0xFFFF, sum = 0
1322 01:24:22.435745 7, 0xFFFF, sum = 0
1323 01:24:22.438773 8, 0xFFFF, sum = 0
1324 01:24:22.439194 9, 0x0, sum = 1
1325 01:24:22.439583 10, 0x0, sum = 2
1326 01:24:22.442096 11, 0x0, sum = 3
1327 01:24:22.442589 12, 0x0, sum = 4
1328 01:24:22.445634 best_step = 10
1329 01:24:22.446147
1330 01:24:22.446470 ==
1331 01:24:22.449181 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 01:24:22.452255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 01:24:22.452674 ==
1334 01:24:22.456326 RX Vref Scan: 0
1335 01:24:22.456840
1336 01:24:22.457169 RX Vref 0 -> 0, step: 1
1337 01:24:22.457483
1338 01:24:22.458730 RX Delay -111 -> 252, step: 8
1339 01:24:22.465965 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1340 01:24:22.468795 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1341 01:24:22.472677 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1342 01:24:22.476342 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1343 01:24:22.478913 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1344 01:24:22.485691 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1345 01:24:22.488904 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1346 01:24:22.492287 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1347 01:24:22.495831 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1348 01:24:22.498894 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1349 01:24:22.505628 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 01:24:22.508860 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1351 01:24:22.511954 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1352 01:24:22.515635 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1353 01:24:22.519197 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 01:24:22.525532 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1355 01:24:22.525983 ==
1356 01:24:22.528972 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 01:24:22.532317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 01:24:22.532737 ==
1359 01:24:22.533064 DQS Delay:
1360 01:24:22.535724 DQS0 = 0, DQS1 = 0
1361 01:24:22.536140 DQM Delay:
1362 01:24:22.538990 DQM0 = 78, DQM1 = 71
1363 01:24:22.539436 DQ Delay:
1364 01:24:22.542179 DQ0 =80, DQ1 =84, DQ2 =72, DQ3 =72
1365 01:24:22.545565 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1366 01:24:22.548766 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1367 01:24:22.552590 DQ12 =80, DQ13 =72, DQ14 =80, DQ15 =80
1368 01:24:22.553006
1369 01:24:22.553332
1370 01:24:22.558666 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1371 01:24:22.562259 CH0 RK1: MR19=606, MR18=4D28
1372 01:24:22.568800 CH0_RK1: MR19=0x606, MR18=0x4D28, DQSOSC=390, MR23=63, INC=97, DEC=64
1373 01:24:22.572200 [RxdqsGatingPostProcess] freq 800
1374 01:24:22.578923 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 01:24:22.582140 Pre-setting of DQS Precalculation
1376 01:24:22.585447 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 01:24:22.586012 ==
1378 01:24:22.589018 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 01:24:22.592061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 01:24:22.592497 ==
1381 01:24:22.598510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 01:24:22.605472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 01:24:22.613885 [CA 0] Center 36 (6~67) winsize 62
1384 01:24:22.617379 [CA 1] Center 37 (7~67) winsize 61
1385 01:24:22.621238 [CA 2] Center 34 (5~64) winsize 60
1386 01:24:22.624106 [CA 3] Center 34 (4~64) winsize 61
1387 01:24:22.627977 [CA 4] Center 34 (4~65) winsize 62
1388 01:24:22.630824 [CA 5] Center 34 (4~64) winsize 61
1389 01:24:22.631420
1390 01:24:22.633924 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 01:24:22.634442
1392 01:24:22.637748 [CATrainingPosCal] consider 1 rank data
1393 01:24:22.641105 u2DelayCellTimex100 = 270/100 ps
1394 01:24:22.644234 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 01:24:22.647663 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1396 01:24:22.654319 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1397 01:24:22.657359 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 01:24:22.660795 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 01:24:22.664358 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 01:24:22.664919
1401 01:24:22.667308 CA PerBit enable=1, Macro0, CA PI delay=34
1402 01:24:22.667805
1403 01:24:22.671005 [CBTSetCACLKResult] CA Dly = 34
1404 01:24:22.671612 CS Dly: 5 (0~36)
1405 01:24:22.671991 ==
1406 01:24:22.674669 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 01:24:22.680700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 01:24:22.681253 ==
1409 01:24:22.684722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 01:24:22.690691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 01:24:22.700630 [CA 0] Center 36 (6~67) winsize 62
1412 01:24:22.703260 [CA 1] Center 36 (6~67) winsize 62
1413 01:24:22.707422 [CA 2] Center 35 (5~65) winsize 61
1414 01:24:22.710093 [CA 3] Center 33 (3~64) winsize 62
1415 01:24:22.713797 [CA 4] Center 34 (4~65) winsize 62
1416 01:24:22.716650 [CA 5] Center 33 (3~64) winsize 62
1417 01:24:22.717124
1418 01:24:22.719978 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 01:24:22.720666
1420 01:24:22.723866 [CATrainingPosCal] consider 2 rank data
1421 01:24:22.727199 u2DelayCellTimex100 = 270/100 ps
1422 01:24:22.730317 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 01:24:22.733472 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1424 01:24:22.739840 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1425 01:24:22.743692 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 01:24:22.746758 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 01:24:22.750311 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 01:24:22.750785
1429 01:24:22.753735 CA PerBit enable=1, Macro0, CA PI delay=34
1430 01:24:22.754206
1431 01:24:22.757739 [CBTSetCACLKResult] CA Dly = 34
1432 01:24:22.758199 CS Dly: 5 (0~37)
1433 01:24:22.758565
1434 01:24:22.761351 ----->DramcWriteLeveling(PI) begin...
1435 01:24:22.761773 ==
1436 01:24:22.765009 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 01:24:22.768568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 01:24:22.769100 ==
1439 01:24:22.772673 Write leveling (Byte 0): 28 => 28
1440 01:24:22.776152 Write leveling (Byte 1): 28 => 28
1441 01:24:22.779615 DramcWriteLeveling(PI) end<-----
1442 01:24:22.780048
1443 01:24:22.780386 ==
1444 01:24:22.783267 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 01:24:22.785943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 01:24:22.786371 ==
1447 01:24:22.789336 [Gating] SW mode calibration
1448 01:24:22.795979 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 01:24:22.802628 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 01:24:22.805891 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 01:24:22.809024 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 01:24:22.815899 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1453 01:24:22.819613 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:24:22.822446 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:24:22.829574 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:24:22.832522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:24:22.835712 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:24:22.839095 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:24:22.845867 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:24:22.849086 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:24:22.852623 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:24:22.859303 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:24:22.862334 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 01:24:22.866313 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 01:24:22.872665 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 01:24:22.876077 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:24:22.879180 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 01:24:22.885954 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 01:24:22.889047 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:24:22.892464 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:24:22.899031 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:24:22.902483 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:24:22.905866 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:24:22.912424 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:24:22.915676 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 01:24:22.919279 0 9 8 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
1477 01:24:22.925791 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 01:24:22.929259 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 01:24:22.932629 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 01:24:22.939322 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 01:24:22.942812 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 01:24:22.946499 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 01:24:22.949426 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1484 01:24:22.955627 0 10 8 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
1485 01:24:22.958941 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:24:22.962368 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 01:24:22.969342 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 01:24:22.972336 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:24:22.975541 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 01:24:22.982514 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 01:24:22.985449 0 11 4 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
1492 01:24:22.988727 0 11 8 | B1->B0 | 3a3a 3e3e | 0 1 | (0 0) (0 0)
1493 01:24:22.995791 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:24:22.999465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 01:24:23.002145 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 01:24:23.009120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:24:23.012594 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 01:24:23.015692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 01:24:23.022524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1500 01:24:23.025468 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 01:24:23.029151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:24:23.035841 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:24:23.038946 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:24:23.042293 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:24:23.049158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:24:23.052462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:24:23.055807 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:24:23.059054 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:24:23.065502 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:24:23.069182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:24:23.072027 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:24:23.078838 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:24:23.082321 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 01:24:23.085906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 01:24:23.092259 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 01:24:23.095756 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1517 01:24:23.099172 Total UI for P1: 0, mck2ui 16
1518 01:24:23.102317 best dqsien dly found for B1: ( 0, 14, 6)
1519 01:24:23.105704 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 01:24:23.108770 Total UI for P1: 0, mck2ui 16
1521 01:24:23.111955 best dqsien dly found for B0: ( 0, 14, 8)
1522 01:24:23.115485 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1523 01:24:23.119026 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 01:24:23.119257
1525 01:24:23.125766 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1526 01:24:23.128927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 01:24:23.129173 [Gating] SW calibration Done
1528 01:24:23.132241 ==
1529 01:24:23.132471 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 01:24:23.138904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 01:24:23.139147 ==
1532 01:24:23.139332 RX Vref Scan: 0
1533 01:24:23.139542
1534 01:24:23.142073 RX Vref 0 -> 0, step: 1
1535 01:24:23.142158
1536 01:24:23.145404 RX Delay -130 -> 252, step: 16
1537 01:24:23.148651 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1538 01:24:23.151954 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 01:24:23.155435 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1540 01:24:23.162075 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 01:24:23.165842 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 01:24:23.169278 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 01:24:23.172416 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 01:24:23.175542 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 01:24:23.181778 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 01:24:23.185337 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 01:24:23.188627 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 01:24:23.191831 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1549 01:24:23.195548 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1550 01:24:23.202152 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1551 01:24:23.205782 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1552 01:24:23.208526 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1553 01:24:23.208603 ==
1554 01:24:23.212134 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 01:24:23.215376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 01:24:23.215453 ==
1557 01:24:23.218850 DQS Delay:
1558 01:24:23.218946 DQS0 = 0, DQS1 = 0
1559 01:24:23.222404 DQM Delay:
1560 01:24:23.222476 DQM0 = 79, DQM1 = 70
1561 01:24:23.222537 DQ Delay:
1562 01:24:23.225285 DQ0 =77, DQ1 =77, DQ2 =61, DQ3 =77
1563 01:24:23.229206 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 01:24:23.232343 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1565 01:24:23.235650 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1566 01:24:23.235740
1567 01:24:23.235805
1568 01:24:23.235864 ==
1569 01:24:23.239047 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 01:24:23.245485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 01:24:23.245561 ==
1572 01:24:23.245624
1573 01:24:23.245687
1574 01:24:23.245747 TX Vref Scan disable
1575 01:24:23.249333 == TX Byte 0 ==
1576 01:24:23.252689 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1577 01:24:23.258896 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1578 01:24:23.258976 == TX Byte 1 ==
1579 01:24:23.262622 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1580 01:24:23.268936 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1581 01:24:23.269013 ==
1582 01:24:23.272498 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 01:24:23.275551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 01:24:23.275629 ==
1585 01:24:23.288206 TX Vref=22, minBit 1, minWin=27, winSum=440
1586 01:24:23.291435 TX Vref=24, minBit 1, minWin=27, winSum=443
1587 01:24:23.295171 TX Vref=26, minBit 1, minWin=27, winSum=443
1588 01:24:23.298306 TX Vref=28, minBit 0, minWin=27, winSum=444
1589 01:24:23.301550 TX Vref=30, minBit 0, minWin=27, winSum=443
1590 01:24:23.304932 TX Vref=32, minBit 0, minWin=27, winSum=445
1591 01:24:23.311360 [TxChooseVref] Worse bit 0, Min win 27, Win sum 445, Final Vref 32
1592 01:24:23.311448
1593 01:24:23.315200 Final TX Range 1 Vref 32
1594 01:24:23.315300
1595 01:24:23.315396 ==
1596 01:24:23.317989 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 01:24:23.322112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 01:24:23.322187 ==
1599 01:24:23.322287
1600 01:24:23.322374
1601 01:24:23.325474 TX Vref Scan disable
1602 01:24:23.328389 == TX Byte 0 ==
1603 01:24:23.332162 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 01:24:23.335027 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 01:24:23.338624 == TX Byte 1 ==
1606 01:24:23.342085 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 01:24:23.345077 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 01:24:23.345152
1609 01:24:23.348472 [DATLAT]
1610 01:24:23.348546 Freq=800, CH1 RK0
1611 01:24:23.348607
1612 01:24:23.351944 DATLAT Default: 0xa
1613 01:24:23.352014 0, 0xFFFF, sum = 0
1614 01:24:23.355326 1, 0xFFFF, sum = 0
1615 01:24:23.355419 2, 0xFFFF, sum = 0
1616 01:24:23.358476 3, 0xFFFF, sum = 0
1617 01:24:23.358575 4, 0xFFFF, sum = 0
1618 01:24:23.361922 5, 0xFFFF, sum = 0
1619 01:24:23.361998 6, 0xFFFF, sum = 0
1620 01:24:23.365376 7, 0xFFFF, sum = 0
1621 01:24:23.365454 8, 0xFFFF, sum = 0
1622 01:24:23.368722 9, 0x0, sum = 1
1623 01:24:23.368823 10, 0x0, sum = 2
1624 01:24:23.372252 11, 0x0, sum = 3
1625 01:24:23.372328 12, 0x0, sum = 4
1626 01:24:23.375529 best_step = 10
1627 01:24:23.375603
1628 01:24:23.375684 ==
1629 01:24:23.378514 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 01:24:23.382218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 01:24:23.382298 ==
1632 01:24:23.382381 RX Vref Scan: 1
1633 01:24:23.385412
1634 01:24:23.385511 Set Vref Range= 32 -> 127
1635 01:24:23.385612
1636 01:24:23.388845 RX Vref 32 -> 127, step: 1
1637 01:24:23.388922
1638 01:24:23.392242 RX Delay -111 -> 252, step: 8
1639 01:24:23.392326
1640 01:24:23.395274 Set Vref, RX VrefLevel [Byte0]: 32
1641 01:24:23.398573 [Byte1]: 32
1642 01:24:23.398650
1643 01:24:23.402137 Set Vref, RX VrefLevel [Byte0]: 33
1644 01:24:23.405501 [Byte1]: 33
1645 01:24:23.405582
1646 01:24:23.408840 Set Vref, RX VrefLevel [Byte0]: 34
1647 01:24:23.412270 [Byte1]: 34
1648 01:24:23.416538
1649 01:24:23.416615 Set Vref, RX VrefLevel [Byte0]: 35
1650 01:24:23.419656 [Byte1]: 35
1651 01:24:23.424042
1652 01:24:23.424122 Set Vref, RX VrefLevel [Byte0]: 36
1653 01:24:23.427145 [Byte1]: 36
1654 01:24:23.431286
1655 01:24:23.431359 Set Vref, RX VrefLevel [Byte0]: 37
1656 01:24:23.434436 [Byte1]: 37
1657 01:24:23.439147
1658 01:24:23.439216 Set Vref, RX VrefLevel [Byte0]: 38
1659 01:24:23.442725 [Byte1]: 38
1660 01:24:23.446721
1661 01:24:23.446820 Set Vref, RX VrefLevel [Byte0]: 39
1662 01:24:23.450109 [Byte1]: 39
1663 01:24:23.454070
1664 01:24:23.454167 Set Vref, RX VrefLevel [Byte0]: 40
1665 01:24:23.457540 [Byte1]: 40
1666 01:24:23.461930
1667 01:24:23.462013 Set Vref, RX VrefLevel [Byte0]: 41
1668 01:24:23.465138 [Byte1]: 41
1669 01:24:23.469665
1670 01:24:23.469741 Set Vref, RX VrefLevel [Byte0]: 42
1671 01:24:23.473218 [Byte1]: 42
1672 01:24:23.477387
1673 01:24:23.477460 Set Vref, RX VrefLevel [Byte0]: 43
1674 01:24:23.480743 [Byte1]: 43
1675 01:24:23.484984
1676 01:24:23.485058 Set Vref, RX VrefLevel [Byte0]: 44
1677 01:24:23.488077 [Byte1]: 44
1678 01:24:23.492975
1679 01:24:23.493050 Set Vref, RX VrefLevel [Byte0]: 45
1680 01:24:23.495810 [Byte1]: 45
1681 01:24:23.500019
1682 01:24:23.500108 Set Vref, RX VrefLevel [Byte0]: 46
1683 01:24:23.503865 [Byte1]: 46
1684 01:24:23.508061
1685 01:24:23.508132 Set Vref, RX VrefLevel [Byte0]: 47
1686 01:24:23.511027 [Byte1]: 47
1687 01:24:23.515769
1688 01:24:23.515841 Set Vref, RX VrefLevel [Byte0]: 48
1689 01:24:23.518723 [Byte1]: 48
1690 01:24:23.523292
1691 01:24:23.523425 Set Vref, RX VrefLevel [Byte0]: 49
1692 01:24:23.526664 [Byte1]: 49
1693 01:24:23.530785
1694 01:24:23.530885 Set Vref, RX VrefLevel [Byte0]: 50
1695 01:24:23.534029 [Byte1]: 50
1696 01:24:23.538199
1697 01:24:23.538272 Set Vref, RX VrefLevel [Byte0]: 51
1698 01:24:23.541712 [Byte1]: 51
1699 01:24:23.545902
1700 01:24:23.546010 Set Vref, RX VrefLevel [Byte0]: 52
1701 01:24:23.549556 [Byte1]: 52
1702 01:24:23.553543
1703 01:24:23.553658 Set Vref, RX VrefLevel [Byte0]: 53
1704 01:24:23.557252 [Byte1]: 53
1705 01:24:23.561161
1706 01:24:23.561245 Set Vref, RX VrefLevel [Byte0]: 54
1707 01:24:23.564689 [Byte1]: 54
1708 01:24:23.569493
1709 01:24:23.569586 Set Vref, RX VrefLevel [Byte0]: 55
1710 01:24:23.572107 [Byte1]: 55
1711 01:24:23.576451
1712 01:24:23.576562 Set Vref, RX VrefLevel [Byte0]: 56
1713 01:24:23.579892 [Byte1]: 56
1714 01:24:23.584400
1715 01:24:23.584489 Set Vref, RX VrefLevel [Byte0]: 57
1716 01:24:23.587889 [Byte1]: 57
1717 01:24:23.591807
1718 01:24:23.591889 Set Vref, RX VrefLevel [Byte0]: 58
1719 01:24:23.595196 [Byte1]: 58
1720 01:24:23.599925
1721 01:24:23.600007 Set Vref, RX VrefLevel [Byte0]: 59
1722 01:24:23.602664 [Byte1]: 59
1723 01:24:23.607225
1724 01:24:23.607307 Set Vref, RX VrefLevel [Byte0]: 60
1725 01:24:23.610587 [Byte1]: 60
1726 01:24:23.615228
1727 01:24:23.615326 Set Vref, RX VrefLevel [Byte0]: 61
1728 01:24:23.618028 [Byte1]: 61
1729 01:24:23.622793
1730 01:24:23.622876 Set Vref, RX VrefLevel [Byte0]: 62
1731 01:24:23.625953 [Byte1]: 62
1732 01:24:23.630262
1733 01:24:23.630344 Set Vref, RX VrefLevel [Byte0]: 63
1734 01:24:23.633202 [Byte1]: 63
1735 01:24:23.637764
1736 01:24:23.637846 Set Vref, RX VrefLevel [Byte0]: 64
1737 01:24:23.640916 [Byte1]: 64
1738 01:24:23.645631
1739 01:24:23.645729 Set Vref, RX VrefLevel [Byte0]: 65
1740 01:24:23.648699 [Byte1]: 65
1741 01:24:23.653122
1742 01:24:23.653204 Set Vref, RX VrefLevel [Byte0]: 66
1743 01:24:23.656844 [Byte1]: 66
1744 01:24:23.660747
1745 01:24:23.660829 Set Vref, RX VrefLevel [Byte0]: 67
1746 01:24:23.664088 [Byte1]: 67
1747 01:24:23.668291
1748 01:24:23.668403 Set Vref, RX VrefLevel [Byte0]: 68
1749 01:24:23.671777 [Byte1]: 68
1750 01:24:23.676522
1751 01:24:23.676607 Set Vref, RX VrefLevel [Byte0]: 69
1752 01:24:23.679298 [Byte1]: 69
1753 01:24:23.683531
1754 01:24:23.683613 Set Vref, RX VrefLevel [Byte0]: 70
1755 01:24:23.687217 [Byte1]: 70
1756 01:24:23.691048
1757 01:24:23.691130 Set Vref, RX VrefLevel [Byte0]: 71
1758 01:24:23.694625 [Byte1]: 71
1759 01:24:23.698759
1760 01:24:23.698866 Final RX Vref Byte 0 = 55 to rank0
1761 01:24:23.702652 Final RX Vref Byte 1 = 56 to rank0
1762 01:24:23.705856 Final RX Vref Byte 0 = 55 to rank1
1763 01:24:23.708879 Final RX Vref Byte 1 = 56 to rank1==
1764 01:24:23.712333 Dram Type= 6, Freq= 0, CH_1, rank 0
1765 01:24:23.719041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1766 01:24:23.719125 ==
1767 01:24:23.719190 DQS Delay:
1768 01:24:23.719251 DQS0 = 0, DQS1 = 0
1769 01:24:23.722386 DQM Delay:
1770 01:24:23.722468 DQM0 = 81, DQM1 = 71
1771 01:24:23.725861 DQ Delay:
1772 01:24:23.725943 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1773 01:24:23.729451 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1774 01:24:23.732459 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1775 01:24:23.735792 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1776 01:24:23.735874
1777 01:24:23.739257
1778 01:24:23.746216 [DQSOSCAuto] RK0, (LSB)MR18= 0x1520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1779 01:24:23.749072 CH1 RK0: MR19=606, MR18=1520
1780 01:24:23.755806 CH1_RK0: MR19=0x606, MR18=0x1520, DQSOSC=401, MR23=63, INC=91, DEC=61
1781 01:24:23.755890
1782 01:24:23.759133 ----->DramcWriteLeveling(PI) begin...
1783 01:24:23.759217 ==
1784 01:24:23.762505 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 01:24:23.765705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 01:24:23.765789 ==
1787 01:24:23.769254 Write leveling (Byte 0): 27 => 27
1788 01:24:23.772685 Write leveling (Byte 1): 28 => 28
1789 01:24:23.775559 DramcWriteLeveling(PI) end<-----
1790 01:24:23.775642
1791 01:24:23.775707 ==
1792 01:24:23.779188 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 01:24:23.782498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 01:24:23.782673 ==
1795 01:24:23.785794 [Gating] SW mode calibration
1796 01:24:23.792434 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1797 01:24:23.799323 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1798 01:24:23.802465 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1799 01:24:23.805811 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1800 01:24:23.812560 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 01:24:23.816095 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 01:24:23.819117 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 01:24:23.825932 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 01:24:23.829312 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 01:24:23.832495 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 01:24:23.838884 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 01:24:23.842443 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 01:24:23.845745 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 01:24:23.849150 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 01:24:23.855860 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:24:23.859162 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 01:24:23.862632 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 01:24:23.869150 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 01:24:23.872974 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1815 01:24:23.876307 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1816 01:24:23.882395 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 01:24:23.885883 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:24:23.888864 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:24:23.895842 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:24:23.898796 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:24:23.902462 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:24:23.909405 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 01:24:23.912393 0 9 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1824 01:24:23.915611 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1825 01:24:23.922545 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 01:24:23.925817 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 01:24:23.929052 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 01:24:23.935893 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 01:24:23.939202 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 01:24:23.942470 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1831 01:24:23.945901 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (1 1)
1832 01:24:23.952264 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1833 01:24:23.955666 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:24:23.959030 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:24:23.966146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:24:23.969174 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:24:23.972530 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 01:24:23.978813 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 01:24:23.982597 0 11 4 | B1->B0 | 2c2c 3b3b | 0 1 | (0 0) (0 0)
1840 01:24:23.985808 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1841 01:24:23.992357 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 01:24:23.995690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 01:24:23.999278 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 01:24:24.005634 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 01:24:24.009045 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 01:24:24.012511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 01:24:24.019323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1848 01:24:24.022296 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1849 01:24:24.025794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 01:24:24.029562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 01:24:24.035609 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 01:24:24.039517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 01:24:24.042414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 01:24:24.049266 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 01:24:24.052563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 01:24:24.055846 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 01:24:24.062312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 01:24:24.065684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 01:24:24.069508 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 01:24:24.075888 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 01:24:24.079606 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 01:24:24.082398 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 01:24:24.089075 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1864 01:24:24.092403 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 01:24:24.095922 Total UI for P1: 0, mck2ui 16
1866 01:24:24.098986 best dqsien dly found for B0: ( 0, 14, 4)
1867 01:24:24.102492 Total UI for P1: 0, mck2ui 16
1868 01:24:24.105783 best dqsien dly found for B1: ( 0, 14, 4)
1869 01:24:24.109166 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1870 01:24:24.112562 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1871 01:24:24.112643
1872 01:24:24.115805 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 01:24:24.119152 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1874 01:24:24.122535 [Gating] SW calibration Done
1875 01:24:24.122616 ==
1876 01:24:24.125896 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 01:24:24.129742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 01:24:24.129833 ==
1879 01:24:24.133034 RX Vref Scan: 0
1880 01:24:24.133115
1881 01:24:24.135993 RX Vref 0 -> 0, step: 1
1882 01:24:24.136074
1883 01:24:24.136137 RX Delay -130 -> 252, step: 16
1884 01:24:24.142780 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1885 01:24:24.146137 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1886 01:24:24.149211 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1887 01:24:24.152472 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1888 01:24:24.155754 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1889 01:24:24.162739 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1890 01:24:24.165933 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1891 01:24:24.169030 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1892 01:24:24.172715 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1893 01:24:24.175942 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1894 01:24:24.179677 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1895 01:24:24.186665 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1896 01:24:24.189328 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1897 01:24:24.192628 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1898 01:24:24.195958 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1899 01:24:24.203074 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1900 01:24:24.203158 ==
1901 01:24:24.205926 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 01:24:24.209526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 01:24:24.209610 ==
1904 01:24:24.209675 DQS Delay:
1905 01:24:24.212808 DQS0 = 0, DQS1 = 0
1906 01:24:24.212890 DQM Delay:
1907 01:24:24.216275 DQM0 = 79, DQM1 = 71
1908 01:24:24.216357 DQ Delay:
1909 01:24:24.219253 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1910 01:24:24.222656 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1911 01:24:24.225862 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1912 01:24:24.229525 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1913 01:24:24.229608
1914 01:24:24.229673
1915 01:24:24.229732 ==
1916 01:24:24.232361 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 01:24:24.235872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 01:24:24.235955 ==
1919 01:24:24.236020
1920 01:24:24.236080
1921 01:24:24.239316 TX Vref Scan disable
1922 01:24:24.242729 == TX Byte 0 ==
1923 01:24:24.246127 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1924 01:24:24.249069 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1925 01:24:24.252510 == TX Byte 1 ==
1926 01:24:24.256014 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1927 01:24:24.259298 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1928 01:24:24.259429 ==
1929 01:24:24.262443 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 01:24:24.268968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 01:24:24.269051 ==
1932 01:24:24.280859 TX Vref=22, minBit 0, minWin=27, winSum=446
1933 01:24:24.284152 TX Vref=24, minBit 0, minWin=28, winSum=453
1934 01:24:24.287630 TX Vref=26, minBit 1, minWin=28, winSum=457
1935 01:24:24.290904 TX Vref=28, minBit 5, minWin=27, winSum=456
1936 01:24:24.293963 TX Vref=30, minBit 5, minWin=27, winSum=459
1937 01:24:24.300351 TX Vref=32, minBit 1, minWin=27, winSum=456
1938 01:24:24.304117 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
1939 01:24:24.304200
1940 01:24:24.307405 Final TX Range 1 Vref 26
1941 01:24:24.307488
1942 01:24:24.307553 ==
1943 01:24:24.310468 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 01:24:24.314348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 01:24:24.314431 ==
1946 01:24:24.314496
1947 01:24:24.317256
1948 01:24:24.317338 TX Vref Scan disable
1949 01:24:24.320428 == TX Byte 0 ==
1950 01:24:24.324481 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1951 01:24:24.330549 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1952 01:24:24.330632 == TX Byte 1 ==
1953 01:24:24.333664 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1954 01:24:24.340592 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1955 01:24:24.340675
1956 01:24:24.340740 [DATLAT]
1957 01:24:24.340800 Freq=800, CH1 RK1
1958 01:24:24.340859
1959 01:24:24.343976 DATLAT Default: 0xa
1960 01:24:24.344058 0, 0xFFFF, sum = 0
1961 01:24:24.347256 1, 0xFFFF, sum = 0
1962 01:24:24.347339 2, 0xFFFF, sum = 0
1963 01:24:24.350585 3, 0xFFFF, sum = 0
1964 01:24:24.350670 4, 0xFFFF, sum = 0
1965 01:24:24.354069 5, 0xFFFF, sum = 0
1966 01:24:24.357041 6, 0xFFFF, sum = 0
1967 01:24:24.357125 7, 0xFFFF, sum = 0
1968 01:24:24.360700 8, 0xFFFF, sum = 0
1969 01:24:24.360784 9, 0x0, sum = 1
1970 01:24:24.360851 10, 0x0, sum = 2
1971 01:24:24.363902 11, 0x0, sum = 3
1972 01:24:24.363986 12, 0x0, sum = 4
1973 01:24:24.366864 best_step = 10
1974 01:24:24.366947
1975 01:24:24.367011 ==
1976 01:24:24.370547 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 01:24:24.374078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 01:24:24.374161 ==
1979 01:24:24.377211 RX Vref Scan: 0
1980 01:24:24.377293
1981 01:24:24.377358 RX Vref 0 -> 0, step: 1
1982 01:24:24.377419
1983 01:24:24.380522 RX Delay -111 -> 252, step: 8
1984 01:24:24.387230 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1985 01:24:24.390805 iDelay=209, Bit 1, Center 68 (-55 ~ 192) 248
1986 01:24:24.394300 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1987 01:24:24.397665 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1988 01:24:24.400947 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1989 01:24:24.407386 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1990 01:24:24.410592 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1991 01:24:24.414106 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1992 01:24:24.417584 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1993 01:24:24.420557 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1994 01:24:24.427377 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
1995 01:24:24.430902 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
1996 01:24:24.434087 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1997 01:24:24.438089 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1998 01:24:24.440383 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1999 01:24:24.447176 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2000 01:24:24.447259 ==
2001 01:24:24.450551 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 01:24:24.454175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 01:24:24.454265 ==
2004 01:24:24.454331 DQS Delay:
2005 01:24:24.457125 DQS0 = 0, DQS1 = 0
2006 01:24:24.457207 DQM Delay:
2007 01:24:24.460716 DQM0 = 76, DQM1 = 73
2008 01:24:24.460798 DQ Delay:
2009 01:24:24.463951 DQ0 =80, DQ1 =68, DQ2 =64, DQ3 =72
2010 01:24:24.467467 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2011 01:24:24.470463 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2012 01:24:24.473802 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2013 01:24:24.473884
2014 01:24:24.473949
2015 01:24:24.483993 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2016 01:24:24.484078 CH1 RK1: MR19=606, MR18=1E36
2017 01:24:24.490404 CH1_RK1: MR19=0x606, MR18=0x1E36, DQSOSC=396, MR23=63, INC=94, DEC=62
2018 01:24:24.493791 [RxdqsGatingPostProcess] freq 800
2019 01:24:24.500383 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2020 01:24:24.503791 Pre-setting of DQS Precalculation
2021 01:24:24.507130 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2022 01:24:24.513804 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2023 01:24:24.520222 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2024 01:24:24.520305
2025 01:24:24.523695
2026 01:24:24.523777 [Calibration Summary] 1600 Mbps
2027 01:24:24.527046 CH 0, Rank 0
2028 01:24:24.527128 SW Impedance : PASS
2029 01:24:24.530266 DUTY Scan : NO K
2030 01:24:24.533911 ZQ Calibration : PASS
2031 01:24:24.533994 Jitter Meter : NO K
2032 01:24:24.537344 CBT Training : PASS
2033 01:24:24.540633 Write leveling : PASS
2034 01:24:24.540715 RX DQS gating : PASS
2035 01:24:24.544240 RX DQ/DQS(RDDQC) : PASS
2036 01:24:24.546953 TX DQ/DQS : PASS
2037 01:24:24.547035 RX DATLAT : PASS
2038 01:24:24.550363 RX DQ/DQS(Engine): PASS
2039 01:24:24.553719 TX OE : NO K
2040 01:24:24.553803 All Pass.
2041 01:24:24.553869
2042 01:24:24.553929 CH 0, Rank 1
2043 01:24:24.557660 SW Impedance : PASS
2044 01:24:24.557742 DUTY Scan : NO K
2045 01:24:24.560933 ZQ Calibration : PASS
2046 01:24:24.563594 Jitter Meter : NO K
2047 01:24:24.563676 CBT Training : PASS
2048 01:24:24.567590 Write leveling : PASS
2049 01:24:24.570642 RX DQS gating : PASS
2050 01:24:24.570724 RX DQ/DQS(RDDQC) : PASS
2051 01:24:24.573758 TX DQ/DQS : PASS
2052 01:24:24.577158 RX DATLAT : PASS
2053 01:24:24.577240 RX DQ/DQS(Engine): PASS
2054 01:24:24.580534 TX OE : NO K
2055 01:24:24.580617 All Pass.
2056 01:24:24.580682
2057 01:24:24.583789 CH 1, Rank 0
2058 01:24:24.583871 SW Impedance : PASS
2059 01:24:24.586811 DUTY Scan : NO K
2060 01:24:24.590297 ZQ Calibration : PASS
2061 01:24:24.590380 Jitter Meter : NO K
2062 01:24:24.593712 CBT Training : PASS
2063 01:24:24.597148 Write leveling : PASS
2064 01:24:24.597231 RX DQS gating : PASS
2065 01:24:24.600399 RX DQ/DQS(RDDQC) : PASS
2066 01:24:24.603987 TX DQ/DQS : PASS
2067 01:24:24.604069 RX DATLAT : PASS
2068 01:24:24.607187 RX DQ/DQS(Engine): PASS
2069 01:24:24.607269 TX OE : NO K
2070 01:24:24.610202 All Pass.
2071 01:24:24.610283
2072 01:24:24.610348 CH 1, Rank 1
2073 01:24:24.613644 SW Impedance : PASS
2074 01:24:24.613726 DUTY Scan : NO K
2075 01:24:24.616840 ZQ Calibration : PASS
2076 01:24:24.620260 Jitter Meter : NO K
2077 01:24:24.620342 CBT Training : PASS
2078 01:24:24.623881 Write leveling : PASS
2079 01:24:24.627248 RX DQS gating : PASS
2080 01:24:24.627357 RX DQ/DQS(RDDQC) : PASS
2081 01:24:24.630496 TX DQ/DQS : PASS
2082 01:24:24.633831 RX DATLAT : PASS
2083 01:24:24.633914 RX DQ/DQS(Engine): PASS
2084 01:24:24.637279 TX OE : NO K
2085 01:24:24.637361 All Pass.
2086 01:24:24.637426
2087 01:24:24.640810 DramC Write-DBI off
2088 01:24:24.643858 PER_BANK_REFRESH: Hybrid Mode
2089 01:24:24.643941 TX_TRACKING: ON
2090 01:24:24.647317 [GetDramInforAfterCalByMRR] Vendor 6.
2091 01:24:24.650249 [GetDramInforAfterCalByMRR] Revision 606.
2092 01:24:24.653784 [GetDramInforAfterCalByMRR] Revision 2 0.
2093 01:24:24.657183 MR0 0x3b3b
2094 01:24:24.657265 MR8 0x5151
2095 01:24:24.660445 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 01:24:24.660527
2097 01:24:24.660591 MR0 0x3b3b
2098 01:24:24.664036 MR8 0x5151
2099 01:24:24.666962 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 01:24:24.667045
2101 01:24:24.674015 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2102 01:24:24.680649 [FAST_K] Save calibration result to emmc
2103 01:24:24.684048 [FAST_K] Save calibration result to emmc
2104 01:24:24.684130 dram_init: config_dvfs: 1
2105 01:24:24.687111 dramc_set_vcore_voltage set vcore to 662500
2106 01:24:24.690239 Read voltage for 1200, 2
2107 01:24:24.690322 Vio18 = 0
2108 01:24:24.694280 Vcore = 662500
2109 01:24:24.694362 Vdram = 0
2110 01:24:24.694426 Vddq = 0
2111 01:24:24.696957 Vmddr = 0
2112 01:24:24.700480 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2113 01:24:24.707152 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2114 01:24:24.707235 MEM_TYPE=3, freq_sel=15
2115 01:24:24.710371 sv_algorithm_assistance_LP4_1600
2116 01:24:24.717464 ============ PULL DRAM RESETB DOWN ============
2117 01:24:24.720731 ========== PULL DRAM RESETB DOWN end =========
2118 01:24:24.723837 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2119 01:24:24.727214 ===================================
2120 01:24:24.730805 LPDDR4 DRAM CONFIGURATION
2121 01:24:24.733611 ===================================
2122 01:24:24.737442 EX_ROW_EN[0] = 0x0
2123 01:24:24.737525 EX_ROW_EN[1] = 0x0
2124 01:24:24.740337 LP4Y_EN = 0x0
2125 01:24:24.740419 WORK_FSP = 0x0
2126 01:24:24.743828 WL = 0x4
2127 01:24:24.743910 RL = 0x4
2128 01:24:24.747165 BL = 0x2
2129 01:24:24.747248 RPST = 0x0
2130 01:24:24.750688 RD_PRE = 0x0
2131 01:24:24.750800 WR_PRE = 0x1
2132 01:24:24.754144 WR_PST = 0x0
2133 01:24:24.754226 DBI_WR = 0x0
2134 01:24:24.756933 DBI_RD = 0x0
2135 01:24:24.757015 OTF = 0x1
2136 01:24:24.760575 ===================================
2137 01:24:24.764109 ===================================
2138 01:24:24.767190 ANA top config
2139 01:24:24.770536 ===================================
2140 01:24:24.770619 DLL_ASYNC_EN = 0
2141 01:24:24.773446 ALL_SLAVE_EN = 0
2142 01:24:24.776925 NEW_RANK_MODE = 1
2143 01:24:24.780340 DLL_IDLE_MODE = 1
2144 01:24:24.783507 LP45_APHY_COMB_EN = 1
2145 01:24:24.783590 TX_ODT_DIS = 1
2146 01:24:24.786947 NEW_8X_MODE = 1
2147 01:24:24.790461 ===================================
2148 01:24:24.793532 ===================================
2149 01:24:24.797037 data_rate = 2400
2150 01:24:24.800130 CKR = 1
2151 01:24:24.803479 DQ_P2S_RATIO = 8
2152 01:24:24.807077 ===================================
2153 01:24:24.807181 CA_P2S_RATIO = 8
2154 01:24:24.810544 DQ_CA_OPEN = 0
2155 01:24:24.813541 DQ_SEMI_OPEN = 0
2156 01:24:24.817282 CA_SEMI_OPEN = 0
2157 01:24:24.820047 CA_FULL_RATE = 0
2158 01:24:24.823340 DQ_CKDIV4_EN = 0
2159 01:24:24.823489 CA_CKDIV4_EN = 0
2160 01:24:24.827122 CA_PREDIV_EN = 0
2161 01:24:24.830225 PH8_DLY = 17
2162 01:24:24.833803 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2163 01:24:24.836856 DQ_AAMCK_DIV = 4
2164 01:24:24.840610 CA_AAMCK_DIV = 4
2165 01:24:24.840725 CA_ADMCK_DIV = 4
2166 01:24:24.843526 DQ_TRACK_CA_EN = 0
2167 01:24:24.847066 CA_PICK = 1200
2168 01:24:24.850560 CA_MCKIO = 1200
2169 01:24:24.853717 MCKIO_SEMI = 0
2170 01:24:24.857031 PLL_FREQ = 2366
2171 01:24:24.860548 DQ_UI_PI_RATIO = 32
2172 01:24:24.860636 CA_UI_PI_RATIO = 0
2173 01:24:24.863983 ===================================
2174 01:24:24.866810 ===================================
2175 01:24:24.870286 memory_type:LPDDR4
2176 01:24:24.873532 GP_NUM : 10
2177 01:24:24.873612 SRAM_EN : 1
2178 01:24:24.877364 MD32_EN : 0
2179 01:24:24.880296 ===================================
2180 01:24:24.883711 [ANA_INIT] >>>>>>>>>>>>>>
2181 01:24:24.887338 <<<<<< [CONFIGURE PHASE]: ANA_TX
2182 01:24:24.890396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2183 01:24:24.893846 ===================================
2184 01:24:24.893944 data_rate = 2400,PCW = 0X5b00
2185 01:24:24.897171 ===================================
2186 01:24:24.900504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2187 01:24:24.907090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 01:24:24.913507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 01:24:24.917051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2190 01:24:24.920277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2191 01:24:24.923980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2192 01:24:24.927230 [ANA_INIT] flow start
2193 01:24:24.927316 [ANA_INIT] PLL >>>>>>>>
2194 01:24:24.930795 [ANA_INIT] PLL <<<<<<<<
2195 01:24:24.933947 [ANA_INIT] MIDPI >>>>>>>>
2196 01:24:24.937109 [ANA_INIT] MIDPI <<<<<<<<
2197 01:24:24.937193 [ANA_INIT] DLL >>>>>>>>
2198 01:24:24.940424 [ANA_INIT] DLL <<<<<<<<
2199 01:24:24.940506 [ANA_INIT] flow end
2200 01:24:24.947137 ============ LP4 DIFF to SE enter ============
2201 01:24:24.950196 ============ LP4 DIFF to SE exit ============
2202 01:24:24.953689 [ANA_INIT] <<<<<<<<<<<<<
2203 01:24:24.957431 [Flow] Enable top DCM control >>>>>
2204 01:24:24.961063 [Flow] Enable top DCM control <<<<<
2205 01:24:24.961148 Enable DLL master slave shuffle
2206 01:24:24.967454 ==============================================================
2207 01:24:24.970555 Gating Mode config
2208 01:24:24.973883 ==============================================================
2209 01:24:24.977137 Config description:
2210 01:24:24.987563 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2211 01:24:24.994142 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2212 01:24:24.997273 SELPH_MODE 0: By rank 1: By Phase
2213 01:24:25.004006 ==============================================================
2214 01:24:25.007318 GAT_TRACK_EN = 1
2215 01:24:25.010200 RX_GATING_MODE = 2
2216 01:24:25.013940 RX_GATING_TRACK_MODE = 2
2217 01:24:25.017361 SELPH_MODE = 1
2218 01:24:25.017447 PICG_EARLY_EN = 1
2219 01:24:25.020401 VALID_LAT_VALUE = 1
2220 01:24:25.027096 ==============================================================
2221 01:24:25.030717 Enter into Gating configuration >>>>
2222 01:24:25.033947 Exit from Gating configuration <<<<
2223 01:24:25.037333 Enter into DVFS_PRE_config >>>>>
2224 01:24:25.047137 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2225 01:24:25.050633 Exit from DVFS_PRE_config <<<<<
2226 01:24:25.053903 Enter into PICG configuration >>>>
2227 01:24:25.057565 Exit from PICG configuration <<<<
2228 01:24:25.060236 [RX_INPUT] configuration >>>>>
2229 01:24:25.063727 [RX_INPUT] configuration <<<<<
2230 01:24:25.067127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2231 01:24:25.073881 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2232 01:24:25.081009 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 01:24:25.087660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 01:24:25.090589 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 01:24:25.097462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 01:24:25.100678 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2237 01:24:25.106958 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2238 01:24:25.110362 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2239 01:24:25.113801 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2240 01:24:25.117430 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2241 01:24:25.123816 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2242 01:24:25.127293 ===================================
2243 01:24:25.127391 LPDDR4 DRAM CONFIGURATION
2244 01:24:25.130620 ===================================
2245 01:24:25.133937 EX_ROW_EN[0] = 0x0
2246 01:24:25.137182 EX_ROW_EN[1] = 0x0
2247 01:24:25.137283 LP4Y_EN = 0x0
2248 01:24:25.140367 WORK_FSP = 0x0
2249 01:24:25.140480 WL = 0x4
2250 01:24:25.144026 RL = 0x4
2251 01:24:25.144108 BL = 0x2
2252 01:24:25.147106 RPST = 0x0
2253 01:24:25.147191 RD_PRE = 0x0
2254 01:24:25.150366 WR_PRE = 0x1
2255 01:24:25.150481 WR_PST = 0x0
2256 01:24:25.154124 DBI_WR = 0x0
2257 01:24:25.154226 DBI_RD = 0x0
2258 01:24:25.157568 OTF = 0x1
2259 01:24:25.160498 ===================================
2260 01:24:25.163868 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2261 01:24:25.167339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2262 01:24:25.173850 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 01:24:25.177262 ===================================
2264 01:24:25.177349 LPDDR4 DRAM CONFIGURATION
2265 01:24:25.180487 ===================================
2266 01:24:25.184138 EX_ROW_EN[0] = 0x10
2267 01:24:25.184223 EX_ROW_EN[1] = 0x0
2268 01:24:25.187256 LP4Y_EN = 0x0
2269 01:24:25.190485 WORK_FSP = 0x0
2270 01:24:25.190563 WL = 0x4
2271 01:24:25.193766 RL = 0x4
2272 01:24:25.193850 BL = 0x2
2273 01:24:25.197334 RPST = 0x0
2274 01:24:25.197416 RD_PRE = 0x0
2275 01:24:25.200345 WR_PRE = 0x1
2276 01:24:25.200491 WR_PST = 0x0
2277 01:24:25.204227 DBI_WR = 0x0
2278 01:24:25.204313 DBI_RD = 0x0
2279 01:24:25.207486 OTF = 0x1
2280 01:24:25.210450 ===================================
2281 01:24:25.214330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2282 01:24:25.217586 ==
2283 01:24:25.220404 Dram Type= 6, Freq= 0, CH_0, rank 0
2284 01:24:25.224001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2285 01:24:25.224085 ==
2286 01:24:25.227037 [Duty_Offset_Calibration]
2287 01:24:25.227145 B0:2 B1:0 CA:3
2288 01:24:25.227238
2289 01:24:25.230474 [DutyScan_Calibration_Flow] k_type=0
2290 01:24:25.240438
2291 01:24:25.240533 ==CLK 0==
2292 01:24:25.243596 Final CLK duty delay cell = 0
2293 01:24:25.246863 [0] MAX Duty = 5031%(X100), DQS PI = 20
2294 01:24:25.249740 [0] MIN Duty = 4906%(X100), DQS PI = 54
2295 01:24:25.249823 [0] AVG Duty = 4968%(X100)
2296 01:24:25.253293
2297 01:24:25.256731 CH0 CLK Duty spec in!! Max-Min= 125%
2298 01:24:25.260134 [DutyScan_Calibration_Flow] ====Done====
2299 01:24:25.260218
2300 01:24:25.263185 [DutyScan_Calibration_Flow] k_type=1
2301 01:24:25.278475
2302 01:24:25.278567 ==DQS 0 ==
2303 01:24:25.282142 Final DQS duty delay cell = 0
2304 01:24:25.285231 [0] MAX Duty = 5062%(X100), DQS PI = 28
2305 01:24:25.288636 [0] MIN Duty = 4907%(X100), DQS PI = 2
2306 01:24:25.288748 [0] AVG Duty = 4984%(X100)
2307 01:24:25.292129
2308 01:24:25.292271 ==DQS 1 ==
2309 01:24:25.295091 Final DQS duty delay cell = -4
2310 01:24:25.298578 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2311 01:24:25.301707 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2312 01:24:25.305246 [-4] AVG Duty = 4937%(X100)
2313 01:24:25.305351
2314 01:24:25.308515 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2315 01:24:25.308622
2316 01:24:25.311920 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2317 01:24:25.314892 [DutyScan_Calibration_Flow] ====Done====
2318 01:24:25.314996
2319 01:24:25.318241 [DutyScan_Calibration_Flow] k_type=3
2320 01:24:25.336211
2321 01:24:25.336322 ==DQM 0 ==
2322 01:24:25.339625 Final DQM duty delay cell = 0
2323 01:24:25.342875 [0] MAX Duty = 5124%(X100), DQS PI = 28
2324 01:24:25.346051 [0] MIN Duty = 4907%(X100), DQS PI = 0
2325 01:24:25.346156 [0] AVG Duty = 5015%(X100)
2326 01:24:25.349479
2327 01:24:25.349588 ==DQM 1 ==
2328 01:24:25.352748 Final DQM duty delay cell = 4
2329 01:24:25.356365 [4] MAX Duty = 5124%(X100), DQS PI = 50
2330 01:24:25.359738 [4] MIN Duty = 5000%(X100), DQS PI = 12
2331 01:24:25.359844 [4] AVG Duty = 5062%(X100)
2332 01:24:25.362913
2333 01:24:25.365763 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2334 01:24:25.365871
2335 01:24:25.369121 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2336 01:24:25.372485 [DutyScan_Calibration_Flow] ====Done====
2337 01:24:25.372611
2338 01:24:25.375781 [DutyScan_Calibration_Flow] k_type=2
2339 01:24:25.390877
2340 01:24:25.390969 ==DQ 0 ==
2341 01:24:25.394311 Final DQ duty delay cell = -4
2342 01:24:25.397283 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2343 01:24:25.400641 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2344 01:24:25.404218 [-4] AVG Duty = 4969%(X100)
2345 01:24:25.404306
2346 01:24:25.404369 ==DQ 1 ==
2347 01:24:25.407640 Final DQ duty delay cell = -4
2348 01:24:25.410953 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2349 01:24:25.414058 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2350 01:24:25.417436 [-4] AVG Duty = 4938%(X100)
2351 01:24:25.417508
2352 01:24:25.420509 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2353 01:24:25.420608
2354 01:24:25.424567 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2355 01:24:25.427332 [DutyScan_Calibration_Flow] ====Done====
2356 01:24:25.427437 ==
2357 01:24:25.430811 Dram Type= 6, Freq= 0, CH_1, rank 0
2358 01:24:25.434494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 01:24:25.434576 ==
2360 01:24:25.437423 [Duty_Offset_Calibration]
2361 01:24:25.437505 B0:1 B1:-2 CA:0
2362 01:24:25.437597
2363 01:24:25.440717 [DutyScan_Calibration_Flow] k_type=0
2364 01:24:25.451986
2365 01:24:25.452068 ==CLK 0==
2366 01:24:25.454741 Final CLK duty delay cell = 0
2367 01:24:25.458452 [0] MAX Duty = 5031%(X100), DQS PI = 50
2368 01:24:25.462089 [0] MIN Duty = 4844%(X100), DQS PI = 26
2369 01:24:25.462171 [0] AVG Duty = 4937%(X100)
2370 01:24:25.464894
2371 01:24:25.464992 CH1 CLK Duty spec in!! Max-Min= 187%
2372 01:24:25.471567 [DutyScan_Calibration_Flow] ====Done====
2373 01:24:25.471679
2374 01:24:25.474917 [DutyScan_Calibration_Flow] k_type=1
2375 01:24:25.489917
2376 01:24:25.490019 ==DQS 0 ==
2377 01:24:25.493355 Final DQS duty delay cell = -4
2378 01:24:25.496745 [-4] MAX Duty = 5031%(X100), DQS PI = 56
2379 01:24:25.499995 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2380 01:24:25.503650 [-4] AVG Duty = 4969%(X100)
2381 01:24:25.503747
2382 01:24:25.503843 ==DQS 1 ==
2383 01:24:25.507248 Final DQS duty delay cell = 0
2384 01:24:25.510225 [0] MAX Duty = 5093%(X100), DQS PI = 32
2385 01:24:25.513364 [0] MIN Duty = 4844%(X100), DQS PI = 58
2386 01:24:25.516981 [0] AVG Duty = 4968%(X100)
2387 01:24:25.517060
2388 01:24:25.519814 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2389 01:24:25.519892
2390 01:24:25.523336 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2391 01:24:25.526790 [DutyScan_Calibration_Flow] ====Done====
2392 01:24:25.526889
2393 01:24:25.529668 [DutyScan_Calibration_Flow] k_type=3
2394 01:24:25.547005
2395 01:24:25.547091 ==DQM 0 ==
2396 01:24:25.549915 Final DQM duty delay cell = 0
2397 01:24:25.553574 [0] MAX Duty = 5000%(X100), DQS PI = 54
2398 01:24:25.556610 [0] MIN Duty = 4876%(X100), DQS PI = 20
2399 01:24:25.560030 [0] AVG Duty = 4938%(X100)
2400 01:24:25.560112
2401 01:24:25.560176 ==DQM 1 ==
2402 01:24:25.563477 Final DQM duty delay cell = 0
2403 01:24:25.566914 [0] MAX Duty = 5031%(X100), DQS PI = 4
2404 01:24:25.569983 [0] MIN Duty = 4907%(X100), DQS PI = 10
2405 01:24:25.573559 [0] AVG Duty = 4969%(X100)
2406 01:24:25.573642
2407 01:24:25.577231 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2408 01:24:25.577341
2409 01:24:25.580218 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2410 01:24:25.583723 [DutyScan_Calibration_Flow] ====Done====
2411 01:24:25.583826
2412 01:24:25.586522 [DutyScan_Calibration_Flow] k_type=2
2413 01:24:25.603077
2414 01:24:25.603217 ==DQ 0 ==
2415 01:24:25.606325 Final DQ duty delay cell = 0
2416 01:24:25.609953 [0] MAX Duty = 5062%(X100), DQS PI = 0
2417 01:24:25.613379 [0] MIN Duty = 4938%(X100), DQS PI = 22
2418 01:24:25.613464 [0] AVG Duty = 5000%(X100)
2419 01:24:25.613530
2420 01:24:25.616635 ==DQ 1 ==
2421 01:24:25.620123 Final DQ duty delay cell = 0
2422 01:24:25.623326 [0] MAX Duty = 5156%(X100), DQS PI = 14
2423 01:24:25.626557 [0] MIN Duty = 4969%(X100), DQS PI = 58
2424 01:24:25.626642 [0] AVG Duty = 5062%(X100)
2425 01:24:25.626708
2426 01:24:25.629722 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2427 01:24:25.629807
2428 01:24:25.633059 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2429 01:24:25.639633 [DutyScan_Calibration_Flow] ====Done====
2430 01:24:25.643612 nWR fixed to 30
2431 01:24:25.643698 [ModeRegInit_LP4] CH0 RK0
2432 01:24:25.646366 [ModeRegInit_LP4] CH0 RK1
2433 01:24:25.649934 [ModeRegInit_LP4] CH1 RK0
2434 01:24:25.650018 [ModeRegInit_LP4] CH1 RK1
2435 01:24:25.653226 match AC timing 7
2436 01:24:25.656843 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2437 01:24:25.660168 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2438 01:24:25.666609 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2439 01:24:25.669624 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2440 01:24:25.676379 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2441 01:24:25.676470 ==
2442 01:24:25.680000 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 01:24:25.683524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2444 01:24:25.683611 ==
2445 01:24:25.689926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2446 01:24:25.693126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2447 01:24:25.703623 [CA 0] Center 40 (10~71) winsize 62
2448 01:24:25.706253 [CA 1] Center 39 (9~70) winsize 62
2449 01:24:25.709585 [CA 2] Center 36 (6~66) winsize 61
2450 01:24:25.712983 [CA 3] Center 35 (5~66) winsize 62
2451 01:24:25.716363 [CA 4] Center 34 (4~65) winsize 62
2452 01:24:25.719562 [CA 5] Center 33 (3~64) winsize 62
2453 01:24:25.719665
2454 01:24:25.723275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2455 01:24:25.723360
2456 01:24:25.726337 [CATrainingPosCal] consider 1 rank data
2457 01:24:25.729479 u2DelayCellTimex100 = 270/100 ps
2458 01:24:25.732911 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2459 01:24:25.739382 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2460 01:24:25.742957 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2461 01:24:25.746066 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2462 01:24:25.749346 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2463 01:24:25.752684 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2464 01:24:25.752772
2465 01:24:25.755931 CA PerBit enable=1, Macro0, CA PI delay=33
2466 01:24:25.756033
2467 01:24:25.759295 [CBTSetCACLKResult] CA Dly = 33
2468 01:24:25.763021 CS Dly: 7 (0~38)
2469 01:24:25.763104 ==
2470 01:24:25.766060 Dram Type= 6, Freq= 0, CH_0, rank 1
2471 01:24:25.769489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 01:24:25.769573 ==
2473 01:24:25.775902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 01:24:25.779227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2475 01:24:25.789237 [CA 0] Center 40 (10~70) winsize 61
2476 01:24:25.792787 [CA 1] Center 40 (10~70) winsize 61
2477 01:24:25.795601 [CA 2] Center 35 (5~66) winsize 62
2478 01:24:25.799451 [CA 3] Center 35 (5~66) winsize 62
2479 01:24:25.802561 [CA 4] Center 34 (3~65) winsize 63
2480 01:24:25.805538 [CA 5] Center 33 (3~64) winsize 62
2481 01:24:25.805624
2482 01:24:25.809318 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2483 01:24:25.809406
2484 01:24:25.812562 [CATrainingPosCal] consider 2 rank data
2485 01:24:25.815727 u2DelayCellTimex100 = 270/100 ps
2486 01:24:25.819271 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2487 01:24:25.825955 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2488 01:24:25.829625 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2489 01:24:25.832525 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 01:24:25.836124 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2491 01:24:25.839565 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2492 01:24:25.839665
2493 01:24:25.843025 CA PerBit enable=1, Macro0, CA PI delay=33
2494 01:24:25.843136
2495 01:24:25.845948 [CBTSetCACLKResult] CA Dly = 33
2496 01:24:25.846034 CS Dly: 8 (0~40)
2497 01:24:25.846101
2498 01:24:25.849496 ----->DramcWriteLeveling(PI) begin...
2499 01:24:25.852712 ==
2500 01:24:25.855957 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 01:24:25.859393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 01:24:25.859487 ==
2503 01:24:25.862659 Write leveling (Byte 0): 33 => 33
2504 01:24:25.865990 Write leveling (Byte 1): 29 => 29
2505 01:24:25.869066 DramcWriteLeveling(PI) end<-----
2506 01:24:25.869168
2507 01:24:25.869241 ==
2508 01:24:25.872452 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 01:24:25.875790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 01:24:25.875882 ==
2511 01:24:25.879332 [Gating] SW mode calibration
2512 01:24:25.886029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2513 01:24:25.889166 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2514 01:24:25.896182 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2515 01:24:25.899622 0 15 4 | B1->B0 | 2727 3434 | 1 0 | (1 1) (0 0)
2516 01:24:25.902564 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 01:24:25.909183 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 01:24:25.912844 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 01:24:25.916199 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 01:24:25.922686 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 01:24:25.926114 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2522 01:24:25.929568 1 0 0 | B1->B0 | 3131 2828 | 1 0 | (1 1) (1 0)
2523 01:24:25.936114 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 01:24:25.939789 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 01:24:25.942440 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 01:24:25.949343 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 01:24:25.952747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 01:24:25.956077 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 01:24:25.962464 1 0 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
2530 01:24:25.965854 1 1 0 | B1->B0 | 2929 3636 | 0 0 | (0 0) (1 1)
2531 01:24:25.969077 1 1 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2532 01:24:25.975810 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 01:24:25.979922 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 01:24:25.982825 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 01:24:25.989647 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 01:24:25.992716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 01:24:25.995795 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 01:24:25.999168 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2539 01:24:26.005820 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 01:24:26.009392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 01:24:26.012512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 01:24:26.019102 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 01:24:26.022594 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 01:24:26.026230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 01:24:26.032922 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 01:24:26.035840 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 01:24:26.039308 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 01:24:26.046198 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 01:24:26.049636 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 01:24:26.052677 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 01:24:26.059430 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 01:24:26.063238 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 01:24:26.066608 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 01:24:26.072897 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2555 01:24:26.076221 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 01:24:26.079560 Total UI for P1: 0, mck2ui 16
2557 01:24:26.083040 best dqsien dly found for B0: ( 1, 4, 0)
2558 01:24:26.085845 Total UI for P1: 0, mck2ui 16
2559 01:24:26.089577 best dqsien dly found for B1: ( 1, 4, 0)
2560 01:24:26.093126 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2561 01:24:26.095932 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2562 01:24:26.096046
2563 01:24:26.099551 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 01:24:26.102834 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2565 01:24:26.106440 [Gating] SW calibration Done
2566 01:24:26.106545 ==
2567 01:24:26.109510 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 01:24:26.112757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 01:24:26.112860 ==
2570 01:24:26.116449 RX Vref Scan: 0
2571 01:24:26.116555
2572 01:24:26.116658 RX Vref 0 -> 0, step: 1
2573 01:24:26.116755
2574 01:24:26.119494 RX Delay -40 -> 252, step: 8
2575 01:24:26.122731 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2576 01:24:26.129229 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2577 01:24:26.132559 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2578 01:24:26.136117 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2579 01:24:26.139433 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2580 01:24:26.142500 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2581 01:24:26.149297 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2582 01:24:26.153145 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2583 01:24:26.156051 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2584 01:24:26.159364 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2585 01:24:26.162985 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2586 01:24:26.166448 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2587 01:24:26.172774 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2588 01:24:26.176426 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2589 01:24:26.179573 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2590 01:24:26.182989 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2591 01:24:26.183097 ==
2592 01:24:26.186486 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 01:24:26.192908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 01:24:26.193038 ==
2595 01:24:26.193144 DQS Delay:
2596 01:24:26.196317 DQS0 = 0, DQS1 = 0
2597 01:24:26.196405 DQM Delay:
2598 01:24:26.196473 DQM0 = 112, DQM1 = 103
2599 01:24:26.199460 DQ Delay:
2600 01:24:26.203023 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2601 01:24:26.206113 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2602 01:24:26.209830 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2603 01:24:26.212656 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2604 01:24:26.212768
2605 01:24:26.212862
2606 01:24:26.212952 ==
2607 01:24:26.216077 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 01:24:26.219588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 01:24:26.219674 ==
2610 01:24:26.219740
2611 01:24:26.222669
2612 01:24:26.222751 TX Vref Scan disable
2613 01:24:26.226048 == TX Byte 0 ==
2614 01:24:26.229446 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2615 01:24:26.233264 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2616 01:24:26.236000 == TX Byte 1 ==
2617 01:24:26.239706 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2618 01:24:26.242961 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2619 01:24:26.243088 ==
2620 01:24:26.246711 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 01:24:26.252766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 01:24:26.252855 ==
2623 01:24:26.263480 TX Vref=22, minBit 7, minWin=25, winSum=418
2624 01:24:26.266993 TX Vref=24, minBit 0, minWin=26, winSum=422
2625 01:24:26.269975 TX Vref=26, minBit 7, minWin=26, winSum=431
2626 01:24:26.273606 TX Vref=28, minBit 7, minWin=26, winSum=434
2627 01:24:26.276780 TX Vref=30, minBit 2, minWin=26, winSum=430
2628 01:24:26.280321 TX Vref=32, minBit 2, minWin=26, winSum=429
2629 01:24:26.287001 [TxChooseVref] Worse bit 7, Min win 26, Win sum 434, Final Vref 28
2630 01:24:26.287102
2631 01:24:26.290151 Final TX Range 1 Vref 28
2632 01:24:26.290260
2633 01:24:26.290354 ==
2634 01:24:26.293425 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 01:24:26.296999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 01:24:26.297122 ==
2637 01:24:26.297221
2638 01:24:26.300285
2639 01:24:26.300405 TX Vref Scan disable
2640 01:24:26.303843 == TX Byte 0 ==
2641 01:24:26.307365 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2642 01:24:26.310283 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2643 01:24:26.313986 == TX Byte 1 ==
2644 01:24:26.316639 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2645 01:24:26.320583 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2646 01:24:26.320677
2647 01:24:26.323492 [DATLAT]
2648 01:24:26.323578 Freq=1200, CH0 RK0
2649 01:24:26.323649
2650 01:24:26.326993 DATLAT Default: 0xd
2651 01:24:26.327077 0, 0xFFFF, sum = 0
2652 01:24:26.330188 1, 0xFFFF, sum = 0
2653 01:24:26.330273 2, 0xFFFF, sum = 0
2654 01:24:26.333855 3, 0xFFFF, sum = 0
2655 01:24:26.333955 4, 0xFFFF, sum = 0
2656 01:24:26.336778 5, 0xFFFF, sum = 0
2657 01:24:26.336856 6, 0xFFFF, sum = 0
2658 01:24:26.340368 7, 0xFFFF, sum = 0
2659 01:24:26.340452 8, 0xFFFF, sum = 0
2660 01:24:26.343696 9, 0xFFFF, sum = 0
2661 01:24:26.346816 10, 0xFFFF, sum = 0
2662 01:24:26.346898 11, 0xFFFF, sum = 0
2663 01:24:26.350017 12, 0x0, sum = 1
2664 01:24:26.350105 13, 0x0, sum = 2
2665 01:24:26.353380 14, 0x0, sum = 3
2666 01:24:26.353464 15, 0x0, sum = 4
2667 01:24:26.353529 best_step = 13
2668 01:24:26.353591
2669 01:24:26.356934 ==
2670 01:24:26.357044 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 01:24:26.363732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 01:24:26.363829 ==
2673 01:24:26.363917 RX Vref Scan: 1
2674 01:24:26.363982
2675 01:24:26.366787 Set Vref Range= 32 -> 127
2676 01:24:26.366897
2677 01:24:26.370542 RX Vref 32 -> 127, step: 1
2678 01:24:26.370654
2679 01:24:26.373270 RX Delay -37 -> 252, step: 4
2680 01:24:26.373381
2681 01:24:26.376776 Set Vref, RX VrefLevel [Byte0]: 32
2682 01:24:26.380704 [Byte1]: 32
2683 01:24:26.380793
2684 01:24:26.383467 Set Vref, RX VrefLevel [Byte0]: 33
2685 01:24:26.386594 [Byte1]: 33
2686 01:24:26.389748
2687 01:24:26.389839 Set Vref, RX VrefLevel [Byte0]: 34
2688 01:24:26.393251 [Byte1]: 34
2689 01:24:26.397700
2690 01:24:26.397790 Set Vref, RX VrefLevel [Byte0]: 35
2691 01:24:26.401493 [Byte1]: 35
2692 01:24:26.405684
2693 01:24:26.405772 Set Vref, RX VrefLevel [Byte0]: 36
2694 01:24:26.409155 [Byte1]: 36
2695 01:24:26.413798
2696 01:24:26.413892 Set Vref, RX VrefLevel [Byte0]: 37
2697 01:24:26.417623 [Byte1]: 37
2698 01:24:26.421701
2699 01:24:26.421792 Set Vref, RX VrefLevel [Byte0]: 38
2700 01:24:26.425024 [Byte1]: 38
2701 01:24:26.429698
2702 01:24:26.429781 Set Vref, RX VrefLevel [Byte0]: 39
2703 01:24:26.433352 [Byte1]: 39
2704 01:24:26.438115
2705 01:24:26.438197 Set Vref, RX VrefLevel [Byte0]: 40
2706 01:24:26.441395 [Byte1]: 40
2707 01:24:26.445976
2708 01:24:26.446072 Set Vref, RX VrefLevel [Byte0]: 41
2709 01:24:26.449480 [Byte1]: 41
2710 01:24:26.454019
2711 01:24:26.454139 Set Vref, RX VrefLevel [Byte0]: 42
2712 01:24:26.460257 [Byte1]: 42
2713 01:24:26.460345
2714 01:24:26.463654 Set Vref, RX VrefLevel [Byte0]: 43
2715 01:24:26.467337 [Byte1]: 43
2716 01:24:26.467451
2717 01:24:26.470655 Set Vref, RX VrefLevel [Byte0]: 44
2718 01:24:26.474002 [Byte1]: 44
2719 01:24:26.478176
2720 01:24:26.478267 Set Vref, RX VrefLevel [Byte0]: 45
2721 01:24:26.481193 [Byte1]: 45
2722 01:24:26.485940
2723 01:24:26.486026 Set Vref, RX VrefLevel [Byte0]: 46
2724 01:24:26.489219 [Byte1]: 46
2725 01:24:26.493877
2726 01:24:26.493969 Set Vref, RX VrefLevel [Byte0]: 47
2727 01:24:26.497315 [Byte1]: 47
2728 01:24:26.502045
2729 01:24:26.502144 Set Vref, RX VrefLevel [Byte0]: 48
2730 01:24:26.505124 [Byte1]: 48
2731 01:24:26.510100
2732 01:24:26.510188 Set Vref, RX VrefLevel [Byte0]: 49
2733 01:24:26.513274 [Byte1]: 49
2734 01:24:26.518143
2735 01:24:26.518227 Set Vref, RX VrefLevel [Byte0]: 50
2736 01:24:26.521072 [Byte1]: 50
2737 01:24:26.526229
2738 01:24:26.526317 Set Vref, RX VrefLevel [Byte0]: 51
2739 01:24:26.529785 [Byte1]: 51
2740 01:24:26.533973
2741 01:24:26.534067 Set Vref, RX VrefLevel [Byte0]: 52
2742 01:24:26.537396 [Byte1]: 52
2743 01:24:26.542623
2744 01:24:26.542713 Set Vref, RX VrefLevel [Byte0]: 53
2745 01:24:26.544981 [Byte1]: 53
2746 01:24:26.550137
2747 01:24:26.550228 Set Vref, RX VrefLevel [Byte0]: 54
2748 01:24:26.553396 [Byte1]: 54
2749 01:24:26.557917
2750 01:24:26.558004 Set Vref, RX VrefLevel [Byte0]: 55
2751 01:24:26.561204 [Byte1]: 55
2752 01:24:26.565839
2753 01:24:26.565929 Set Vref, RX VrefLevel [Byte0]: 56
2754 01:24:26.569570 [Byte1]: 56
2755 01:24:26.573883
2756 01:24:26.573975 Set Vref, RX VrefLevel [Byte0]: 57
2757 01:24:26.577497 [Byte1]: 57
2758 01:24:26.581784
2759 01:24:26.581879 Set Vref, RX VrefLevel [Byte0]: 58
2760 01:24:26.585558 [Byte1]: 58
2761 01:24:26.590415
2762 01:24:26.590510 Set Vref, RX VrefLevel [Byte0]: 59
2763 01:24:26.593550 [Byte1]: 59
2764 01:24:26.598077
2765 01:24:26.598206 Set Vref, RX VrefLevel [Byte0]: 60
2766 01:24:26.601429 [Byte1]: 60
2767 01:24:26.605853
2768 01:24:26.605967 Set Vref, RX VrefLevel [Byte0]: 61
2769 01:24:26.609158 [Byte1]: 61
2770 01:24:26.614184
2771 01:24:26.614295 Set Vref, RX VrefLevel [Byte0]: 62
2772 01:24:26.617084 [Byte1]: 62
2773 01:24:26.621883
2774 01:24:26.621998 Set Vref, RX VrefLevel [Byte0]: 63
2775 01:24:26.625491 [Byte1]: 63
2776 01:24:26.630389
2777 01:24:26.630475 Set Vref, RX VrefLevel [Byte0]: 64
2778 01:24:26.633328 [Byte1]: 64
2779 01:24:26.638256
2780 01:24:26.638341 Set Vref, RX VrefLevel [Byte0]: 65
2781 01:24:26.641242 [Byte1]: 65
2782 01:24:26.645753
2783 01:24:26.645838 Set Vref, RX VrefLevel [Byte0]: 66
2784 01:24:26.649589 [Byte1]: 66
2785 01:24:26.653818
2786 01:24:26.653927 Set Vref, RX VrefLevel [Byte0]: 67
2787 01:24:26.657415 [Byte1]: 67
2788 01:24:26.661844
2789 01:24:26.661939 Set Vref, RX VrefLevel [Byte0]: 68
2790 01:24:26.665348 [Byte1]: 68
2791 01:24:26.669926
2792 01:24:26.670020 Set Vref, RX VrefLevel [Byte0]: 69
2793 01:24:26.673384 [Byte1]: 69
2794 01:24:26.678340
2795 01:24:26.678431 Set Vref, RX VrefLevel [Byte0]: 70
2796 01:24:26.681346 [Byte1]: 70
2797 01:24:26.686007
2798 01:24:26.686092 Set Vref, RX VrefLevel [Byte0]: 71
2799 01:24:26.689476 [Byte1]: 71
2800 01:24:26.693910
2801 01:24:26.694033 Set Vref, RX VrefLevel [Byte0]: 72
2802 01:24:26.697817 [Byte1]: 72
2803 01:24:26.702084
2804 01:24:26.702204 Set Vref, RX VrefLevel [Byte0]: 73
2805 01:24:26.705771 [Byte1]: 73
2806 01:24:26.710232
2807 01:24:26.710337 Set Vref, RX VrefLevel [Byte0]: 74
2808 01:24:26.713492 [Byte1]: 74
2809 01:24:26.718497
2810 01:24:26.718583 Final RX Vref Byte 0 = 62 to rank0
2811 01:24:26.721405 Final RX Vref Byte 1 = 53 to rank0
2812 01:24:26.724266 Final RX Vref Byte 0 = 62 to rank1
2813 01:24:26.727763 Final RX Vref Byte 1 = 53 to rank1==
2814 01:24:26.731152 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 01:24:26.737847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 01:24:26.737945 ==
2817 01:24:26.738024 DQS Delay:
2818 01:24:26.738090 DQS0 = 0, DQS1 = 0
2819 01:24:26.741235 DQM Delay:
2820 01:24:26.741315 DQM0 = 112, DQM1 = 101
2821 01:24:26.744517 DQ Delay:
2822 01:24:26.747604 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2823 01:24:26.750983 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2824 01:24:26.754380 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2825 01:24:26.757971 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2826 01:24:26.758062
2827 01:24:26.758129
2828 01:24:26.764423 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2829 01:24:26.767893 CH0 RK0: MR19=303, MR18=FBFA
2830 01:24:26.774488 CH0_RK0: MR19=0x303, MR18=0xFBFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2831 01:24:26.774590
2832 01:24:26.777653 ----->DramcWriteLeveling(PI) begin...
2833 01:24:26.777736 ==
2834 01:24:26.781129 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 01:24:26.784385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 01:24:26.787406 ==
2837 01:24:26.790745 Write leveling (Byte 0): 31 => 31
2838 01:24:26.790865 Write leveling (Byte 1): 29 => 29
2839 01:24:26.794186 DramcWriteLeveling(PI) end<-----
2840 01:24:26.794277
2841 01:24:26.794344 ==
2842 01:24:26.797501 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 01:24:26.804652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 01:24:26.804739 ==
2845 01:24:26.807666 [Gating] SW mode calibration
2846 01:24:26.814197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 01:24:26.817414 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 01:24:26.824494 0 15 0 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2849 01:24:26.827842 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 01:24:26.831232 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 01:24:26.834168 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 01:24:26.841002 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 01:24:26.844194 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 01:24:26.847346 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2855 01:24:26.853902 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2856 01:24:26.857545 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2857 01:24:26.860998 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 01:24:26.867254 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 01:24:26.870635 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 01:24:26.873825 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 01:24:26.880852 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 01:24:26.883961 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2863 01:24:26.887307 1 0 28 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
2864 01:24:26.893989 1 1 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
2865 01:24:26.897430 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 01:24:26.900454 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 01:24:26.907516 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 01:24:26.910648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 01:24:26.914012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 01:24:26.920761 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 01:24:26.924197 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 01:24:26.927386 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2873 01:24:26.934085 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 01:24:26.937992 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 01:24:26.940544 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 01:24:26.947169 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 01:24:26.950612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 01:24:26.954518 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 01:24:26.957749 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 01:24:26.964215 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 01:24:26.967581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 01:24:26.970712 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 01:24:26.977379 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 01:24:26.980870 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 01:24:26.983818 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 01:24:26.990426 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2887 01:24:26.993775 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 01:24:26.997306 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2889 01:24:27.000661 Total UI for P1: 0, mck2ui 16
2890 01:24:27.004234 best dqsien dly found for B0: ( 1, 3, 26)
2891 01:24:27.010438 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 01:24:27.010527 Total UI for P1: 0, mck2ui 16
2893 01:24:27.017495 best dqsien dly found for B1: ( 1, 4, 0)
2894 01:24:27.021172 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2895 01:24:27.024005 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2896 01:24:27.024116
2897 01:24:27.027264 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2898 01:24:27.030691 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2899 01:24:27.034081 [Gating] SW calibration Done
2900 01:24:27.034197 ==
2901 01:24:27.037550 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 01:24:27.040585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 01:24:27.040700 ==
2904 01:24:27.044058 RX Vref Scan: 0
2905 01:24:27.044144
2906 01:24:27.044214 RX Vref 0 -> 0, step: 1
2907 01:24:27.044277
2908 01:24:27.047738 RX Delay -40 -> 252, step: 8
2909 01:24:27.050575 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2910 01:24:27.053822 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2911 01:24:27.061048 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2912 01:24:27.064417 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2913 01:24:27.067409 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2914 01:24:27.070654 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2915 01:24:27.074116 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2916 01:24:27.080643 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2917 01:24:27.084044 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2918 01:24:27.087253 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2919 01:24:27.090988 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2920 01:24:27.094220 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2921 01:24:27.100707 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2922 01:24:27.103947 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2923 01:24:27.107133 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2924 01:24:27.110822 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2925 01:24:27.110939 ==
2926 01:24:27.114286 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 01:24:27.117216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 01:24:27.120781 ==
2929 01:24:27.120866 DQS Delay:
2930 01:24:27.120933 DQS0 = 0, DQS1 = 0
2931 01:24:27.124140 DQM Delay:
2932 01:24:27.124224 DQM0 = 111, DQM1 = 102
2933 01:24:27.127225 DQ Delay:
2934 01:24:27.130865 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2935 01:24:27.133770 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2936 01:24:27.137108 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2937 01:24:27.140457 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2938 01:24:27.140543
2939 01:24:27.140609
2940 01:24:27.140671 ==
2941 01:24:27.144162 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 01:24:27.147697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 01:24:27.147788 ==
2944 01:24:27.147857
2945 01:24:27.147918
2946 01:24:27.150423 TX Vref Scan disable
2947 01:24:27.154176 == TX Byte 0 ==
2948 01:24:27.157268 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2949 01:24:27.160714 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2950 01:24:27.163868 == TX Byte 1 ==
2951 01:24:27.166969 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2952 01:24:27.170346 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2953 01:24:27.170424 ==
2954 01:24:27.173697 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 01:24:27.177525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 01:24:27.180596 ==
2957 01:24:27.190880 TX Vref=22, minBit 2, minWin=26, winSum=430
2958 01:24:27.194407 TX Vref=24, minBit 5, minWin=26, winSum=432
2959 01:24:27.197364 TX Vref=26, minBit 5, minWin=26, winSum=436
2960 01:24:27.200931 TX Vref=28, minBit 1, minWin=27, winSum=439
2961 01:24:27.204281 TX Vref=30, minBit 1, minWin=27, winSum=440
2962 01:24:27.207742 TX Vref=32, minBit 8, minWin=26, winSum=439
2963 01:24:27.213952 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 30
2964 01:24:27.214047
2965 01:24:27.217457 Final TX Range 1 Vref 30
2966 01:24:27.217542
2967 01:24:27.217608 ==
2968 01:24:27.220744 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 01:24:27.224196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 01:24:27.224281 ==
2971 01:24:27.224347
2972 01:24:27.227478
2973 01:24:27.227562 TX Vref Scan disable
2974 01:24:27.230648 == TX Byte 0 ==
2975 01:24:27.234317 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2976 01:24:27.237495 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2977 01:24:27.241002 == TX Byte 1 ==
2978 01:24:27.243911 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2979 01:24:27.247818 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2980 01:24:27.247934
2981 01:24:27.250838 [DATLAT]
2982 01:24:27.250953 Freq=1200, CH0 RK1
2983 01:24:27.251055
2984 01:24:27.254107 DATLAT Default: 0xd
2985 01:24:27.254224 0, 0xFFFF, sum = 0
2986 01:24:27.257883 1, 0xFFFF, sum = 0
2987 01:24:27.257996 2, 0xFFFF, sum = 0
2988 01:24:27.261208 3, 0xFFFF, sum = 0
2989 01:24:27.261328 4, 0xFFFF, sum = 0
2990 01:24:27.264398 5, 0xFFFF, sum = 0
2991 01:24:27.264514 6, 0xFFFF, sum = 0
2992 01:24:27.267504 7, 0xFFFF, sum = 0
2993 01:24:27.267629 8, 0xFFFF, sum = 0
2994 01:24:27.270769 9, 0xFFFF, sum = 0
2995 01:24:27.273989 10, 0xFFFF, sum = 0
2996 01:24:27.274110 11, 0xFFFF, sum = 0
2997 01:24:27.277701 12, 0x0, sum = 1
2998 01:24:27.277816 13, 0x0, sum = 2
2999 01:24:27.277915 14, 0x0, sum = 3
3000 01:24:27.280787 15, 0x0, sum = 4
3001 01:24:27.280903 best_step = 13
3002 01:24:27.281000
3003 01:24:27.283997 ==
3004 01:24:27.284110 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 01:24:27.290756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 01:24:27.290879 ==
3007 01:24:27.290979 RX Vref Scan: 0
3008 01:24:27.291084
3009 01:24:27.294369 RX Vref 0 -> 0, step: 1
3010 01:24:27.294488
3011 01:24:27.297896 RX Delay -37 -> 252, step: 4
3012 01:24:27.300732 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3013 01:24:27.304231 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3014 01:24:27.310898 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3015 01:24:27.314221 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3016 01:24:27.317980 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3017 01:24:27.320785 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3018 01:24:27.324344 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3019 01:24:27.331239 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3020 01:24:27.334617 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3021 01:24:27.337500 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3022 01:24:27.341078 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3023 01:24:27.344573 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3024 01:24:27.351454 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3025 01:24:27.354363 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3026 01:24:27.357594 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3027 01:24:27.361037 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3028 01:24:27.361164 ==
3029 01:24:27.364538 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 01:24:27.367905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 01:24:27.370918 ==
3032 01:24:27.371034 DQS Delay:
3033 01:24:27.371136 DQS0 = 0, DQS1 = 0
3034 01:24:27.374282 DQM Delay:
3035 01:24:27.374398 DQM0 = 111, DQM1 = 101
3036 01:24:27.377855 DQ Delay:
3037 01:24:27.381295 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3038 01:24:27.384115 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3039 01:24:27.387468 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3040 01:24:27.391229 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3041 01:24:27.391350
3042 01:24:27.391462
3043 01:24:27.397536 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3044 01:24:27.401109 CH0 RK1: MR19=403, MR18=11F8
3045 01:24:27.408040 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3046 01:24:27.411214 [RxdqsGatingPostProcess] freq 1200
3047 01:24:27.417719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 01:24:27.420867 best DQS0 dly(2T, 0.5T) = (0, 12)
3049 01:24:27.420988 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 01:24:27.424470 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3051 01:24:27.427669 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 01:24:27.430832 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 01:24:27.434640 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 01:24:27.437523 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 01:24:27.440667 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 01:24:27.444108 Pre-setting of DQS Precalculation
3057 01:24:27.447534 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 01:24:27.451050 ==
3059 01:24:27.454194 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 01:24:27.457838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 01:24:27.457960 ==
3062 01:24:27.461111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 01:24:27.467487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3064 01:24:27.476824 [CA 0] Center 37 (8~67) winsize 60
3065 01:24:27.479734 [CA 1] Center 37 (7~68) winsize 62
3066 01:24:27.483530 [CA 2] Center 34 (5~64) winsize 60
3067 01:24:27.486557 [CA 3] Center 34 (4~64) winsize 61
3068 01:24:27.489806 [CA 4] Center 34 (4~64) winsize 61
3069 01:24:27.493340 [CA 5] Center 33 (3~63) winsize 61
3070 01:24:27.493461
3071 01:24:27.496668 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3072 01:24:27.496761
3073 01:24:27.499759 [CATrainingPosCal] consider 1 rank data
3074 01:24:27.503585 u2DelayCellTimex100 = 270/100 ps
3075 01:24:27.506506 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3076 01:24:27.510012 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 01:24:27.516741 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3078 01:24:27.520147 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3079 01:24:27.523069 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 01:24:27.526409 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3081 01:24:27.526519
3082 01:24:27.529811 CA PerBit enable=1, Macro0, CA PI delay=33
3083 01:24:27.529900
3084 01:24:27.533259 [CBTSetCACLKResult] CA Dly = 33
3085 01:24:27.533340 CS Dly: 5 (0~36)
3086 01:24:27.533451 ==
3087 01:24:27.536449 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 01:24:27.543274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 01:24:27.543377 ==
3090 01:24:27.546812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 01:24:27.553208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3092 01:24:27.562504 [CA 0] Center 37 (7~68) winsize 62
3093 01:24:27.565892 [CA 1] Center 37 (7~68) winsize 62
3094 01:24:27.569013 [CA 2] Center 34 (4~65) winsize 62
3095 01:24:27.571980 [CA 3] Center 33 (3~64) winsize 62
3096 01:24:27.576057 [CA 4] Center 34 (4~65) winsize 62
3097 01:24:27.578693 [CA 5] Center 33 (3~63) winsize 61
3098 01:24:27.578810
3099 01:24:27.582390 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3100 01:24:27.582489
3101 01:24:27.585740 [CATrainingPosCal] consider 2 rank data
3102 01:24:27.589267 u2DelayCellTimex100 = 270/100 ps
3103 01:24:27.591932 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3104 01:24:27.595514 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 01:24:27.602288 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3106 01:24:27.605423 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 01:24:27.608844 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 01:24:27.612485 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3109 01:24:27.612602
3110 01:24:27.615968 CA PerBit enable=1, Macro0, CA PI delay=33
3111 01:24:27.616081
3112 01:24:27.619116 [CBTSetCACLKResult] CA Dly = 33
3113 01:24:27.619229 CS Dly: 7 (0~40)
3114 01:24:27.619331
3115 01:24:27.622934 ----->DramcWriteLeveling(PI) begin...
3116 01:24:27.625371 ==
3117 01:24:27.625488 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 01:24:27.632253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 01:24:27.632386 ==
3120 01:24:27.635670 Write leveling (Byte 0): 25 => 25
3121 01:24:27.639272 Write leveling (Byte 1): 29 => 29
3122 01:24:27.639408 DramcWriteLeveling(PI) end<-----
3123 01:24:27.642559
3124 01:24:27.642689 ==
3125 01:24:27.645510 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 01:24:27.648956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 01:24:27.649115 ==
3128 01:24:27.652226 [Gating] SW mode calibration
3129 01:24:27.659278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 01:24:27.662406 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 01:24:27.669050 0 15 0 | B1->B0 | 2929 2d2d | 1 1 | (0 0) (0 0)
3132 01:24:27.672574 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 01:24:27.675935 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 01:24:27.682248 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 01:24:27.685765 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 01:24:27.688779 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 01:24:27.695623 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3138 01:24:27.699059 0 15 28 | B1->B0 | 2929 2e2e | 0 0 | (1 0) (1 0)
3139 01:24:27.702025 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3140 01:24:27.709149 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 01:24:27.712277 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 01:24:27.715629 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 01:24:27.722139 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 01:24:27.725352 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 01:24:27.728517 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3146 01:24:27.735248 1 0 28 | B1->B0 | 3939 3333 | 0 0 | (0 0) (0 0)
3147 01:24:27.738376 1 1 0 | B1->B0 | 4242 4343 | 0 0 | (0 0) (0 0)
3148 01:24:27.741807 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 01:24:27.748217 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 01:24:27.751731 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 01:24:27.755115 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 01:24:27.761502 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 01:24:27.765110 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 01:24:27.768271 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3155 01:24:27.775175 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3156 01:24:27.778403 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 01:24:27.781730 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 01:24:27.788125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 01:24:27.791613 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 01:24:27.794719 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 01:24:27.801939 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 01:24:27.805306 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 01:24:27.808146 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 01:24:27.811467 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 01:24:27.818074 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 01:24:27.821416 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 01:24:27.824630 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 01:24:27.831942 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 01:24:27.835179 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 01:24:27.838082 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 01:24:27.844910 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 01:24:27.848126 Total UI for P1: 0, mck2ui 16
3173 01:24:27.851751 best dqsien dly found for B0: ( 1, 3, 28)
3174 01:24:27.851838 Total UI for P1: 0, mck2ui 16
3175 01:24:27.858101 best dqsien dly found for B1: ( 1, 3, 28)
3176 01:24:27.861746 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3177 01:24:27.865141 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3178 01:24:27.865226
3179 01:24:27.868200 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3180 01:24:27.871578 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3181 01:24:27.875026 [Gating] SW calibration Done
3182 01:24:27.875109 ==
3183 01:24:27.878002 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 01:24:27.881448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 01:24:27.881535 ==
3186 01:24:27.884804 RX Vref Scan: 0
3187 01:24:27.884888
3188 01:24:27.884954 RX Vref 0 -> 0, step: 1
3189 01:24:27.885015
3190 01:24:27.888414 RX Delay -40 -> 252, step: 8
3191 01:24:27.891692 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3192 01:24:27.898071 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3193 01:24:27.901639 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3194 01:24:27.904679 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3195 01:24:27.908242 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3196 01:24:27.911487 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3197 01:24:27.918018 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3198 01:24:27.921484 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3199 01:24:27.924820 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3200 01:24:27.928270 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3201 01:24:27.931279 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3202 01:24:27.938051 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3203 01:24:27.941298 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3204 01:24:27.944587 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3205 01:24:27.947981 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3206 01:24:27.951571 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3207 01:24:27.951684 ==
3208 01:24:27.955196 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 01:24:27.961195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 01:24:27.961283 ==
3211 01:24:27.961349 DQS Delay:
3212 01:24:27.964819 DQS0 = 0, DQS1 = 0
3213 01:24:27.964903 DQM Delay:
3214 01:24:27.968241 DQM0 = 114, DQM1 = 107
3215 01:24:27.968342 DQ Delay:
3216 01:24:27.971698 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3217 01:24:27.974810 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3218 01:24:27.978252 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3219 01:24:27.982032 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =111
3220 01:24:27.982118
3221 01:24:27.982184
3222 01:24:27.982244 ==
3223 01:24:27.985164 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 01:24:27.988071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 01:24:27.991314 ==
3226 01:24:27.991424
3227 01:24:27.991490
3228 01:24:27.991551 TX Vref Scan disable
3229 01:24:27.994786 == TX Byte 0 ==
3230 01:24:27.998026 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3231 01:24:28.001506 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3232 01:24:28.004921 == TX Byte 1 ==
3233 01:24:28.008160 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3234 01:24:28.011415 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3235 01:24:28.014988 ==
3236 01:24:28.015073 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 01:24:28.021256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 01:24:28.021342 ==
3239 01:24:28.032568 TX Vref=22, minBit 1, minWin=24, winSum=404
3240 01:24:28.036030 TX Vref=24, minBit 1, minWin=24, winSum=410
3241 01:24:28.039553 TX Vref=26, minBit 1, minWin=24, winSum=414
3242 01:24:28.042679 TX Vref=28, minBit 1, minWin=25, winSum=418
3243 01:24:28.046039 TX Vref=30, minBit 3, minWin=24, winSum=417
3244 01:24:28.048922 TX Vref=32, minBit 1, minWin=25, winSum=417
3245 01:24:28.055751 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
3246 01:24:28.055843
3247 01:24:28.059175 Final TX Range 1 Vref 28
3248 01:24:28.059261
3249 01:24:28.059326 ==
3250 01:24:28.062663 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 01:24:28.065631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 01:24:28.065715 ==
3253 01:24:28.065781
3254 01:24:28.069233
3255 01:24:28.069316 TX Vref Scan disable
3256 01:24:28.072872 == TX Byte 0 ==
3257 01:24:28.075625 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3258 01:24:28.079084 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3259 01:24:28.082475 == TX Byte 1 ==
3260 01:24:28.085757 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3261 01:24:28.089135 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3262 01:24:28.089222
3263 01:24:28.092794 [DATLAT]
3264 01:24:28.092879 Freq=1200, CH1 RK0
3265 01:24:28.092945
3266 01:24:28.095470 DATLAT Default: 0xd
3267 01:24:28.095544 0, 0xFFFF, sum = 0
3268 01:24:28.098868 1, 0xFFFF, sum = 0
3269 01:24:28.098959 2, 0xFFFF, sum = 0
3270 01:24:28.102205 3, 0xFFFF, sum = 0
3271 01:24:28.102292 4, 0xFFFF, sum = 0
3272 01:24:28.105539 5, 0xFFFF, sum = 0
3273 01:24:28.109220 6, 0xFFFF, sum = 0
3274 01:24:28.109336 7, 0xFFFF, sum = 0
3275 01:24:28.112211 8, 0xFFFF, sum = 0
3276 01:24:28.112334 9, 0xFFFF, sum = 0
3277 01:24:28.115658 10, 0xFFFF, sum = 0
3278 01:24:28.115770 11, 0xFFFF, sum = 0
3279 01:24:28.118830 12, 0x0, sum = 1
3280 01:24:28.118947 13, 0x0, sum = 2
3281 01:24:28.122093 14, 0x0, sum = 3
3282 01:24:28.122198 15, 0x0, sum = 4
3283 01:24:28.122292 best_step = 13
3284 01:24:28.122387
3285 01:24:28.125462 ==
3286 01:24:28.128785 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 01:24:28.132539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 01:24:28.132653 ==
3289 01:24:28.132749 RX Vref Scan: 1
3290 01:24:28.132851
3291 01:24:28.135547 Set Vref Range= 32 -> 127
3292 01:24:28.135639
3293 01:24:28.138642 RX Vref 32 -> 127, step: 1
3294 01:24:28.138747
3295 01:24:28.142091 RX Delay -21 -> 252, step: 4
3296 01:24:28.142177
3297 01:24:28.145442 Set Vref, RX VrefLevel [Byte0]: 32
3298 01:24:28.148715 [Byte1]: 32
3299 01:24:28.148800
3300 01:24:28.152286 Set Vref, RX VrefLevel [Byte0]: 33
3301 01:24:28.155714 [Byte1]: 33
3302 01:24:28.155798
3303 01:24:28.158725 Set Vref, RX VrefLevel [Byte0]: 34
3304 01:24:28.162102 [Byte1]: 34
3305 01:24:28.166499
3306 01:24:28.166584 Set Vref, RX VrefLevel [Byte0]: 35
3307 01:24:28.169665 [Byte1]: 35
3308 01:24:28.174747
3309 01:24:28.174834 Set Vref, RX VrefLevel [Byte0]: 36
3310 01:24:28.177610 [Byte1]: 36
3311 01:24:28.182295
3312 01:24:28.182380 Set Vref, RX VrefLevel [Byte0]: 37
3313 01:24:28.186008 [Byte1]: 37
3314 01:24:28.190271
3315 01:24:28.190355 Set Vref, RX VrefLevel [Byte0]: 38
3316 01:24:28.193558 [Byte1]: 38
3317 01:24:28.198327
3318 01:24:28.198417 Set Vref, RX VrefLevel [Byte0]: 39
3319 01:24:28.201745 [Byte1]: 39
3320 01:24:28.206229
3321 01:24:28.206314 Set Vref, RX VrefLevel [Byte0]: 40
3322 01:24:28.209349 [Byte1]: 40
3323 01:24:28.214269
3324 01:24:28.214361 Set Vref, RX VrefLevel [Byte0]: 41
3325 01:24:28.217458 [Byte1]: 41
3326 01:24:28.222105
3327 01:24:28.222192 Set Vref, RX VrefLevel [Byte0]: 42
3328 01:24:28.225437 [Byte1]: 42
3329 01:24:28.230050
3330 01:24:28.230134 Set Vref, RX VrefLevel [Byte0]: 43
3331 01:24:28.233544 [Byte1]: 43
3332 01:24:28.237873
3333 01:24:28.237958 Set Vref, RX VrefLevel [Byte0]: 44
3334 01:24:28.241124 [Byte1]: 44
3335 01:24:28.245997
3336 01:24:28.246082 Set Vref, RX VrefLevel [Byte0]: 45
3337 01:24:28.249677 [Byte1]: 45
3338 01:24:28.253727
3339 01:24:28.253811 Set Vref, RX VrefLevel [Byte0]: 46
3340 01:24:28.257080 [Byte1]: 46
3341 01:24:28.261606
3342 01:24:28.261690 Set Vref, RX VrefLevel [Byte0]: 47
3343 01:24:28.265320 [Byte1]: 47
3344 01:24:28.269548
3345 01:24:28.269631 Set Vref, RX VrefLevel [Byte0]: 48
3346 01:24:28.273100 [Byte1]: 48
3347 01:24:28.277654
3348 01:24:28.277739 Set Vref, RX VrefLevel [Byte0]: 49
3349 01:24:28.280502 [Byte1]: 49
3350 01:24:28.285474
3351 01:24:28.285554 Set Vref, RX VrefLevel [Byte0]: 50
3352 01:24:28.288994 [Byte1]: 50
3353 01:24:28.293427
3354 01:24:28.293513 Set Vref, RX VrefLevel [Byte0]: 51
3355 01:24:28.296850 [Byte1]: 51
3356 01:24:28.301325
3357 01:24:28.301408 Set Vref, RX VrefLevel [Byte0]: 52
3358 01:24:28.304437 [Byte1]: 52
3359 01:24:28.309451
3360 01:24:28.309533 Set Vref, RX VrefLevel [Byte0]: 53
3361 01:24:28.312347 [Byte1]: 53
3362 01:24:28.317270
3363 01:24:28.317360 Set Vref, RX VrefLevel [Byte0]: 54
3364 01:24:28.320520 [Byte1]: 54
3365 01:24:28.325014
3366 01:24:28.325103 Set Vref, RX VrefLevel [Byte0]: 55
3367 01:24:28.328104 [Byte1]: 55
3368 01:24:28.333361
3369 01:24:28.333451 Set Vref, RX VrefLevel [Byte0]: 56
3370 01:24:28.336453 [Byte1]: 56
3371 01:24:28.341191
3372 01:24:28.341299 Set Vref, RX VrefLevel [Byte0]: 57
3373 01:24:28.344130 [Byte1]: 57
3374 01:24:28.348829
3375 01:24:28.348914 Set Vref, RX VrefLevel [Byte0]: 58
3376 01:24:28.352221 [Byte1]: 58
3377 01:24:28.356974
3378 01:24:28.357060 Set Vref, RX VrefLevel [Byte0]: 59
3379 01:24:28.360097 [Byte1]: 59
3380 01:24:28.364500
3381 01:24:28.364589 Set Vref, RX VrefLevel [Byte0]: 60
3382 01:24:28.367988 [Byte1]: 60
3383 01:24:28.372171
3384 01:24:28.375851 Set Vref, RX VrefLevel [Byte0]: 61
3385 01:24:28.379097 [Byte1]: 61
3386 01:24:28.379211
3387 01:24:28.382071 Set Vref, RX VrefLevel [Byte0]: 62
3388 01:24:28.385751 [Byte1]: 62
3389 01:24:28.385870
3390 01:24:28.389209 Set Vref, RX VrefLevel [Byte0]: 63
3391 01:24:28.392215 [Byte1]: 63
3392 01:24:28.396277
3393 01:24:28.396366 Set Vref, RX VrefLevel [Byte0]: 64
3394 01:24:28.399385 [Byte1]: 64
3395 01:24:28.404034
3396 01:24:28.404121 Set Vref, RX VrefLevel [Byte0]: 65
3397 01:24:28.407496 [Byte1]: 65
3398 01:24:28.412201
3399 01:24:28.412313 Set Vref, RX VrefLevel [Byte0]: 66
3400 01:24:28.415304 [Byte1]: 66
3401 01:24:28.419828
3402 01:24:28.419913 Set Vref, RX VrefLevel [Byte0]: 67
3403 01:24:28.423298 [Byte1]: 67
3404 01:24:28.427820
3405 01:24:28.427900 Set Vref, RX VrefLevel [Byte0]: 68
3406 01:24:28.431172 [Byte1]: 68
3407 01:24:28.436051
3408 01:24:28.436140 Final RX Vref Byte 0 = 55 to rank0
3409 01:24:28.439312 Final RX Vref Byte 1 = 52 to rank0
3410 01:24:28.442535 Final RX Vref Byte 0 = 55 to rank1
3411 01:24:28.445943 Final RX Vref Byte 1 = 52 to rank1==
3412 01:24:28.449080 Dram Type= 6, Freq= 0, CH_1, rank 0
3413 01:24:28.456173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 01:24:28.456262 ==
3415 01:24:28.456329 DQS Delay:
3416 01:24:28.456390 DQS0 = 0, DQS1 = 0
3417 01:24:28.459274 DQM Delay:
3418 01:24:28.459358 DQM0 = 114, DQM1 = 108
3419 01:24:28.462428 DQ Delay:
3420 01:24:28.466559 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =112
3421 01:24:28.469666 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =112
3422 01:24:28.472820 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3423 01:24:28.475742 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3424 01:24:28.475829
3425 01:24:28.475894
3426 01:24:28.482869 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3427 01:24:28.485620 CH1 RK0: MR19=303, MR18=EFF6
3428 01:24:28.492540 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3429 01:24:28.492648
3430 01:24:28.496031 ----->DramcWriteLeveling(PI) begin...
3431 01:24:28.496120 ==
3432 01:24:28.499054 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 01:24:28.502584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 01:24:28.506111 ==
3435 01:24:28.506197 Write leveling (Byte 0): 25 => 25
3436 01:24:28.509275 Write leveling (Byte 1): 26 => 26
3437 01:24:28.512516 DramcWriteLeveling(PI) end<-----
3438 01:24:28.512604
3439 01:24:28.512673 ==
3440 01:24:28.516233 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 01:24:28.522824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 01:24:28.522916 ==
3443 01:24:28.522984 [Gating] SW mode calibration
3444 01:24:28.532458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3445 01:24:28.536014 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3446 01:24:28.539210 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 01:24:28.546179 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 01:24:28.549418 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 01:24:28.552668 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 01:24:28.559509 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 01:24:28.562354 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3452 01:24:28.565991 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 1) (1 0)
3453 01:24:28.572676 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3454 01:24:28.575710 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 01:24:28.579147 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 01:24:28.585546 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 01:24:28.589208 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 01:24:28.592578 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 01:24:28.598834 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3460 01:24:28.602590 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3461 01:24:28.605725 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3462 01:24:28.612422 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 01:24:28.615566 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 01:24:28.618763 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 01:24:28.625790 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 01:24:28.629187 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 01:24:28.632282 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 01:24:28.639538 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3469 01:24:28.642206 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3470 01:24:28.645496 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 01:24:28.648865 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 01:24:28.655917 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 01:24:28.659234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 01:24:28.662486 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 01:24:28.668953 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 01:24:28.672429 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 01:24:28.675778 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 01:24:28.682071 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 01:24:28.685641 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 01:24:28.689227 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 01:24:28.695442 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 01:24:28.699099 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 01:24:28.701995 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 01:24:28.708990 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3485 01:24:28.712008 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 01:24:28.715393 Total UI for P1: 0, mck2ui 16
3487 01:24:28.718681 best dqsien dly found for B0: ( 1, 3, 24)
3488 01:24:28.722052 Total UI for P1: 0, mck2ui 16
3489 01:24:28.725394 best dqsien dly found for B1: ( 1, 3, 24)
3490 01:24:28.728713 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3491 01:24:28.732194 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3492 01:24:28.732277
3493 01:24:28.735353 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3494 01:24:28.738552 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3495 01:24:28.742514 [Gating] SW calibration Done
3496 01:24:28.742593 ==
3497 01:24:28.745640 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 01:24:28.748681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 01:24:28.752039 ==
3500 01:24:28.752123 RX Vref Scan: 0
3501 01:24:28.752189
3502 01:24:28.755276 RX Vref 0 -> 0, step: 1
3503 01:24:28.755358
3504 01:24:28.758619 RX Delay -40 -> 252, step: 8
3505 01:24:28.761982 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3506 01:24:28.765062 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3507 01:24:28.768648 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3508 01:24:28.771603 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3509 01:24:28.778125 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3510 01:24:28.781416 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3511 01:24:28.785257 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3512 01:24:28.788484 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3513 01:24:28.791662 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3514 01:24:28.795220 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3515 01:24:28.801469 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3516 01:24:28.805063 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3517 01:24:28.808446 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3518 01:24:28.811505 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3519 01:24:28.818296 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3520 01:24:28.821501 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3521 01:24:28.821624 ==
3522 01:24:28.824715 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 01:24:28.828261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 01:24:28.828371 ==
3525 01:24:28.831075 DQS Delay:
3526 01:24:28.831182 DQS0 = 0, DQS1 = 0
3527 01:24:28.831287 DQM Delay:
3528 01:24:28.834510 DQM0 = 111, DQM1 = 109
3529 01:24:28.834624 DQ Delay:
3530 01:24:28.838248 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3531 01:24:28.841075 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3532 01:24:28.844558 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3533 01:24:28.850749 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3534 01:24:28.850867
3535 01:24:28.850963
3536 01:24:28.851068 ==
3537 01:24:28.854525 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 01:24:28.857985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 01:24:28.858096 ==
3540 01:24:28.858192
3541 01:24:28.858287
3542 01:24:28.860705 TX Vref Scan disable
3543 01:24:28.860817 == TX Byte 0 ==
3544 01:24:28.867836 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3545 01:24:28.870812 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3546 01:24:28.870923 == TX Byte 1 ==
3547 01:24:28.877730 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3548 01:24:28.880488 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3549 01:24:28.880568 ==
3550 01:24:28.884032 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 01:24:28.887362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 01:24:28.887465 ==
3553 01:24:28.900797 TX Vref=22, minBit 0, minWin=25, winSum=413
3554 01:24:28.903635 TX Vref=24, minBit 0, minWin=25, winSum=420
3555 01:24:28.907168 TX Vref=26, minBit 0, minWin=26, winSum=425
3556 01:24:28.910307 TX Vref=28, minBit 1, minWin=25, winSum=423
3557 01:24:28.913560 TX Vref=30, minBit 1, minWin=25, winSum=426
3558 01:24:28.916801 TX Vref=32, minBit 0, minWin=26, winSum=425
3559 01:24:28.923447 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
3560 01:24:28.923537
3561 01:24:28.926898 Final TX Range 1 Vref 26
3562 01:24:28.926987
3563 01:24:28.927053 ==
3564 01:24:28.930147 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 01:24:28.933263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 01:24:28.933350 ==
3567 01:24:28.936748
3568 01:24:28.936833
3569 01:24:28.936897 TX Vref Scan disable
3570 01:24:28.940154 == TX Byte 0 ==
3571 01:24:28.943509 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3572 01:24:28.946895 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3573 01:24:28.950179 == TX Byte 1 ==
3574 01:24:28.953098 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3575 01:24:28.956907 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3576 01:24:28.959790
3577 01:24:28.959877 [DATLAT]
3578 01:24:28.959963 Freq=1200, CH1 RK1
3579 01:24:28.960045
3580 01:24:28.963382 DATLAT Default: 0xd
3581 01:24:28.963495 0, 0xFFFF, sum = 0
3582 01:24:28.966410 1, 0xFFFF, sum = 0
3583 01:24:28.966525 2, 0xFFFF, sum = 0
3584 01:24:28.969628 3, 0xFFFF, sum = 0
3585 01:24:28.973226 4, 0xFFFF, sum = 0
3586 01:24:28.973316 5, 0xFFFF, sum = 0
3587 01:24:28.976414 6, 0xFFFF, sum = 0
3588 01:24:28.976502 7, 0xFFFF, sum = 0
3589 01:24:28.979644 8, 0xFFFF, sum = 0
3590 01:24:28.979733 9, 0xFFFF, sum = 0
3591 01:24:28.983181 10, 0xFFFF, sum = 0
3592 01:24:28.983296 11, 0xFFFF, sum = 0
3593 01:24:28.986519 12, 0x0, sum = 1
3594 01:24:28.986607 13, 0x0, sum = 2
3595 01:24:28.989888 14, 0x0, sum = 3
3596 01:24:28.989976 15, 0x0, sum = 4
3597 01:24:28.993322 best_step = 13
3598 01:24:28.993408
3599 01:24:28.993498 ==
3600 01:24:28.996223 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 01:24:28.999331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 01:24:28.999461 ==
3603 01:24:28.999565 RX Vref Scan: 0
3604 01:24:29.002814
3605 01:24:29.002902 RX Vref 0 -> 0, step: 1
3606 01:24:29.002968
3607 01:24:29.006398 RX Delay -21 -> 252, step: 4
3608 01:24:29.012825 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3609 01:24:29.016130 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3610 01:24:29.019151 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3611 01:24:29.022369 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3612 01:24:29.025773 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3613 01:24:29.032716 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3614 01:24:29.035870 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3615 01:24:29.038988 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3616 01:24:29.042575 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3617 01:24:29.045862 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3618 01:24:29.052371 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3619 01:24:29.055856 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3620 01:24:29.059112 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3621 01:24:29.062168 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3622 01:24:29.065538 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3623 01:24:29.072349 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3624 01:24:29.072439 ==
3625 01:24:29.075263 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 01:24:29.078883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 01:24:29.079006 ==
3628 01:24:29.079109 DQS Delay:
3629 01:24:29.082292 DQS0 = 0, DQS1 = 0
3630 01:24:29.082410 DQM Delay:
3631 01:24:29.085594 DQM0 = 112, DQM1 = 110
3632 01:24:29.085699 DQ Delay:
3633 01:24:29.088408 DQ0 =116, DQ1 =110, DQ2 =102, DQ3 =110
3634 01:24:29.091833 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3635 01:24:29.095299 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
3636 01:24:29.098706 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3637 01:24:29.101952
3638 01:24:29.102049
3639 01:24:29.108676 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3640 01:24:29.111700 CH1 RK1: MR19=304, MR18=FA09
3641 01:24:29.118338 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3642 01:24:29.121705 [RxdqsGatingPostProcess] freq 1200
3643 01:24:29.125238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3644 01:24:29.128380 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 01:24:29.131472 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 01:24:29.134928 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 01:24:29.138380 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 01:24:29.142053 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 01:24:29.144656 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 01:24:29.148250 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 01:24:29.151622 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 01:24:29.155165 Pre-setting of DQS Precalculation
3653 01:24:29.158139 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3654 01:24:29.168306 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3655 01:24:29.174367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3656 01:24:29.174462
3657 01:24:29.174528
3658 01:24:29.177705 [Calibration Summary] 2400 Mbps
3659 01:24:29.177790 CH 0, Rank 0
3660 01:24:29.181069 SW Impedance : PASS
3661 01:24:29.181153 DUTY Scan : NO K
3662 01:24:29.184709 ZQ Calibration : PASS
3663 01:24:29.187651 Jitter Meter : NO K
3664 01:24:29.187736 CBT Training : PASS
3665 01:24:29.191316 Write leveling : PASS
3666 01:24:29.194520 RX DQS gating : PASS
3667 01:24:29.194605 RX DQ/DQS(RDDQC) : PASS
3668 01:24:29.197764 TX DQ/DQS : PASS
3669 01:24:29.201043 RX DATLAT : PASS
3670 01:24:29.201155 RX DQ/DQS(Engine): PASS
3671 01:24:29.204027 TX OE : NO K
3672 01:24:29.204112 All Pass.
3673 01:24:29.204178
3674 01:24:29.207840 CH 0, Rank 1
3675 01:24:29.207923 SW Impedance : PASS
3676 01:24:29.210555 DUTY Scan : NO K
3677 01:24:29.214307 ZQ Calibration : PASS
3678 01:24:29.214391 Jitter Meter : NO K
3679 01:24:29.217236 CBT Training : PASS
3680 01:24:29.220641 Write leveling : PASS
3681 01:24:29.220729 RX DQS gating : PASS
3682 01:24:29.224104 RX DQ/DQS(RDDQC) : PASS
3683 01:24:29.224191 TX DQ/DQS : PASS
3684 01:24:29.227258 RX DATLAT : PASS
3685 01:24:29.230847 RX DQ/DQS(Engine): PASS
3686 01:24:29.230933 TX OE : NO K
3687 01:24:29.233838 All Pass.
3688 01:24:29.233930
3689 01:24:29.234015 CH 1, Rank 0
3690 01:24:29.237716 SW Impedance : PASS
3691 01:24:29.237803 DUTY Scan : NO K
3692 01:24:29.241183 ZQ Calibration : PASS
3693 01:24:29.243655 Jitter Meter : NO K
3694 01:24:29.243772 CBT Training : PASS
3695 01:24:29.247156 Write leveling : PASS
3696 01:24:29.250795 RX DQS gating : PASS
3697 01:24:29.250881 RX DQ/DQS(RDDQC) : PASS
3698 01:24:29.253814 TX DQ/DQS : PASS
3699 01:24:29.256899 RX DATLAT : PASS
3700 01:24:29.256986 RX DQ/DQS(Engine): PASS
3701 01:24:29.260379 TX OE : NO K
3702 01:24:29.260467 All Pass.
3703 01:24:29.260554
3704 01:24:29.263637 CH 1, Rank 1
3705 01:24:29.263724 SW Impedance : PASS
3706 01:24:29.267388 DUTY Scan : NO K
3707 01:24:29.270367 ZQ Calibration : PASS
3708 01:24:29.270453 Jitter Meter : NO K
3709 01:24:29.273539 CBT Training : PASS
3710 01:24:29.276922 Write leveling : PASS
3711 01:24:29.277009 RX DQS gating : PASS
3712 01:24:29.280261 RX DQ/DQS(RDDQC) : PASS
3713 01:24:29.280349 TX DQ/DQS : PASS
3714 01:24:29.283420 RX DATLAT : PASS
3715 01:24:29.286670 RX DQ/DQS(Engine): PASS
3716 01:24:29.286774 TX OE : NO K
3717 01:24:29.290474 All Pass.
3718 01:24:29.290585
3719 01:24:29.290683 DramC Write-DBI off
3720 01:24:29.293829 PER_BANK_REFRESH: Hybrid Mode
3721 01:24:29.296874 TX_TRACKING: ON
3722 01:24:29.303223 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3723 01:24:29.306629 [FAST_K] Save calibration result to emmc
3724 01:24:29.313386 dramc_set_vcore_voltage set vcore to 650000
3725 01:24:29.313521 Read voltage for 600, 5
3726 01:24:29.313624 Vio18 = 0
3727 01:24:29.316661 Vcore = 650000
3728 01:24:29.316772 Vdram = 0
3729 01:24:29.316869 Vddq = 0
3730 01:24:29.319989 Vmddr = 0
3731 01:24:29.323483 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3732 01:24:29.329988 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3733 01:24:29.333087 MEM_TYPE=3, freq_sel=19
3734 01:24:29.333202 sv_algorithm_assistance_LP4_1600
3735 01:24:29.339912 ============ PULL DRAM RESETB DOWN ============
3736 01:24:29.342997 ========== PULL DRAM RESETB DOWN end =========
3737 01:24:29.346825 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 01:24:29.350243 ===================================
3739 01:24:29.353072 LPDDR4 DRAM CONFIGURATION
3740 01:24:29.356390 ===================================
3741 01:24:29.359722 EX_ROW_EN[0] = 0x0
3742 01:24:29.359832 EX_ROW_EN[1] = 0x0
3743 01:24:29.362690 LP4Y_EN = 0x0
3744 01:24:29.362797 WORK_FSP = 0x0
3745 01:24:29.366090 WL = 0x2
3746 01:24:29.366198 RL = 0x2
3747 01:24:29.369704 BL = 0x2
3748 01:24:29.369812 RPST = 0x0
3749 01:24:29.372996 RD_PRE = 0x0
3750 01:24:29.373103 WR_PRE = 0x1
3751 01:24:29.376309 WR_PST = 0x0
3752 01:24:29.376400 DBI_WR = 0x0
3753 01:24:29.379319 DBI_RD = 0x0
3754 01:24:29.379448 OTF = 0x1
3755 01:24:29.382788 ===================================
3756 01:24:29.386413 ===================================
3757 01:24:29.389460 ANA top config
3758 01:24:29.392798 ===================================
3759 01:24:29.396487 DLL_ASYNC_EN = 0
3760 01:24:29.396591 ALL_SLAVE_EN = 1
3761 01:24:29.399140 NEW_RANK_MODE = 1
3762 01:24:29.402458 DLL_IDLE_MODE = 1
3763 01:24:29.406132 LP45_APHY_COMB_EN = 1
3764 01:24:29.409328 TX_ODT_DIS = 1
3765 01:24:29.409415 NEW_8X_MODE = 1
3766 01:24:29.412341 ===================================
3767 01:24:29.415846 ===================================
3768 01:24:29.419189 data_rate = 1200
3769 01:24:29.422562 CKR = 1
3770 01:24:29.425622 DQ_P2S_RATIO = 8
3771 01:24:29.429126 ===================================
3772 01:24:29.432072 CA_P2S_RATIO = 8
3773 01:24:29.435539 DQ_CA_OPEN = 0
3774 01:24:29.435646 DQ_SEMI_OPEN = 0
3775 01:24:29.439055 CA_SEMI_OPEN = 0
3776 01:24:29.442028 CA_FULL_RATE = 0
3777 01:24:29.445493 DQ_CKDIV4_EN = 1
3778 01:24:29.448768 CA_CKDIV4_EN = 1
3779 01:24:29.452352 CA_PREDIV_EN = 0
3780 01:24:29.452429 PH8_DLY = 0
3781 01:24:29.455825 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3782 01:24:29.458992 DQ_AAMCK_DIV = 4
3783 01:24:29.462434 CA_AAMCK_DIV = 4
3784 01:24:29.465621 CA_ADMCK_DIV = 4
3785 01:24:29.468871 DQ_TRACK_CA_EN = 0
3786 01:24:29.468950 CA_PICK = 600
3787 01:24:29.472231 CA_MCKIO = 600
3788 01:24:29.475364 MCKIO_SEMI = 0
3789 01:24:29.478735 PLL_FREQ = 2288
3790 01:24:29.481966 DQ_UI_PI_RATIO = 32
3791 01:24:29.485511 CA_UI_PI_RATIO = 0
3792 01:24:29.489003 ===================================
3793 01:24:29.492521 ===================================
3794 01:24:29.492600 memory_type:LPDDR4
3795 01:24:29.495661 GP_NUM : 10
3796 01:24:29.498784 SRAM_EN : 1
3797 01:24:29.498899 MD32_EN : 0
3798 01:24:29.502298 ===================================
3799 01:24:29.505338 [ANA_INIT] >>>>>>>>>>>>>>
3800 01:24:29.509168 <<<<<< [CONFIGURE PHASE]: ANA_TX
3801 01:24:29.512691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3802 01:24:29.515713 ===================================
3803 01:24:29.518859 data_rate = 1200,PCW = 0X5800
3804 01:24:29.522470 ===================================
3805 01:24:29.525066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3806 01:24:29.528763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 01:24:29.534978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 01:24:29.538570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3809 01:24:29.542274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3810 01:24:29.548350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3811 01:24:29.548464 [ANA_INIT] flow start
3812 01:24:29.551591 [ANA_INIT] PLL >>>>>>>>
3813 01:24:29.551696 [ANA_INIT] PLL <<<<<<<<
3814 01:24:29.554813 [ANA_INIT] MIDPI >>>>>>>>
3815 01:24:29.558697 [ANA_INIT] MIDPI <<<<<<<<
3816 01:24:29.561677 [ANA_INIT] DLL >>>>>>>>
3817 01:24:29.561786 [ANA_INIT] flow end
3818 01:24:29.565046 ============ LP4 DIFF to SE enter ============
3819 01:24:29.571767 ============ LP4 DIFF to SE exit ============
3820 01:24:29.571863 [ANA_INIT] <<<<<<<<<<<<<
3821 01:24:29.575184 [Flow] Enable top DCM control >>>>>
3822 01:24:29.578541 [Flow] Enable top DCM control <<<<<
3823 01:24:29.581432 Enable DLL master slave shuffle
3824 01:24:29.588256 ==============================================================
3825 01:24:29.588356 Gating Mode config
3826 01:24:29.595023 ==============================================================
3827 01:24:29.597918 Config description:
3828 01:24:29.608235 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3829 01:24:29.615006 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3830 01:24:29.618377 SELPH_MODE 0: By rank 1: By Phase
3831 01:24:29.624520 ==============================================================
3832 01:24:29.627631 GAT_TRACK_EN = 1
3833 01:24:29.631205 RX_GATING_MODE = 2
3834 01:24:29.631315 RX_GATING_TRACK_MODE = 2
3835 01:24:29.634480 SELPH_MODE = 1
3836 01:24:29.637775 PICG_EARLY_EN = 1
3837 01:24:29.640980 VALID_LAT_VALUE = 1
3838 01:24:29.647698 ==============================================================
3839 01:24:29.651088 Enter into Gating configuration >>>>
3840 01:24:29.654532 Exit from Gating configuration <<<<
3841 01:24:29.657396 Enter into DVFS_PRE_config >>>>>
3842 01:24:29.667651 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3843 01:24:29.671133 Exit from DVFS_PRE_config <<<<<
3844 01:24:29.674232 Enter into PICG configuration >>>>
3845 01:24:29.677721 Exit from PICG configuration <<<<
3846 01:24:29.681038 [RX_INPUT] configuration >>>>>
3847 01:24:29.684495 [RX_INPUT] configuration <<<<<
3848 01:24:29.687826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3849 01:24:29.693961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3850 01:24:29.700960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 01:24:29.707440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 01:24:29.714022 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 01:24:29.717017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 01:24:29.723953 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3855 01:24:29.726969 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3856 01:24:29.730930 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3857 01:24:29.733951 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3858 01:24:29.740755 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3859 01:24:29.743801 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 01:24:29.747177 ===================================
3861 01:24:29.750323 LPDDR4 DRAM CONFIGURATION
3862 01:24:29.754228 ===================================
3863 01:24:29.754335 EX_ROW_EN[0] = 0x0
3864 01:24:29.757194 EX_ROW_EN[1] = 0x0
3865 01:24:29.757277 LP4Y_EN = 0x0
3866 01:24:29.760188 WORK_FSP = 0x0
3867 01:24:29.760277 WL = 0x2
3868 01:24:29.763832 RL = 0x2
3869 01:24:29.763908 BL = 0x2
3870 01:24:29.766822 RPST = 0x0
3871 01:24:29.766895 RD_PRE = 0x0
3872 01:24:29.770151 WR_PRE = 0x1
3873 01:24:29.770263 WR_PST = 0x0
3874 01:24:29.773764 DBI_WR = 0x0
3875 01:24:29.776854 DBI_RD = 0x0
3876 01:24:29.776934 OTF = 0x1
3877 01:24:29.780037 ===================================
3878 01:24:29.783506 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3879 01:24:29.787128 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3880 01:24:29.793541 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 01:24:29.796970 ===================================
3882 01:24:29.800010 LPDDR4 DRAM CONFIGURATION
3883 01:24:29.803260 ===================================
3884 01:24:29.803386 EX_ROW_EN[0] = 0x10
3885 01:24:29.806735 EX_ROW_EN[1] = 0x0
3886 01:24:29.806845 LP4Y_EN = 0x0
3887 01:24:29.810010 WORK_FSP = 0x0
3888 01:24:29.810119 WL = 0x2
3889 01:24:29.813754 RL = 0x2
3890 01:24:29.813870 BL = 0x2
3891 01:24:29.816597 RPST = 0x0
3892 01:24:29.816710 RD_PRE = 0x0
3893 01:24:29.820121 WR_PRE = 0x1
3894 01:24:29.820232 WR_PST = 0x0
3895 01:24:29.823437 DBI_WR = 0x0
3896 01:24:29.823544 DBI_RD = 0x0
3897 01:24:29.826664 OTF = 0x1
3898 01:24:29.830041 ===================================
3899 01:24:29.836431 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3900 01:24:29.840060 nWR fixed to 30
3901 01:24:29.843290 [ModeRegInit_LP4] CH0 RK0
3902 01:24:29.843416 [ModeRegInit_LP4] CH0 RK1
3903 01:24:29.846517 [ModeRegInit_LP4] CH1 RK0
3904 01:24:29.849867 [ModeRegInit_LP4] CH1 RK1
3905 01:24:29.849977 match AC timing 17
3906 01:24:29.856527 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3907 01:24:29.860093 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3908 01:24:29.863040 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3909 01:24:29.869883 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3910 01:24:29.872832 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3911 01:24:29.872951 ==
3912 01:24:29.876297 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 01:24:29.879546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3914 01:24:29.879662 ==
3915 01:24:29.886439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3916 01:24:29.893060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3917 01:24:29.896000 [CA 0] Center 37 (7~67) winsize 61
3918 01:24:29.899488 [CA 1] Center 36 (6~67) winsize 62
3919 01:24:29.902571 [CA 2] Center 35 (5~65) winsize 61
3920 01:24:29.906064 [CA 3] Center 35 (5~65) winsize 61
3921 01:24:29.909288 [CA 4] Center 34 (4~64) winsize 61
3922 01:24:29.912698 [CA 5] Center 34 (4~64) winsize 61
3923 01:24:29.912814
3924 01:24:29.915975 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3925 01:24:29.916087
3926 01:24:29.919406 [CATrainingPosCal] consider 1 rank data
3927 01:24:29.922356 u2DelayCellTimex100 = 270/100 ps
3928 01:24:29.925671 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3929 01:24:29.929461 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3930 01:24:29.932583 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3931 01:24:29.935593 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3932 01:24:29.942440 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3933 01:24:29.945404 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3934 01:24:29.945516
3935 01:24:29.948709 CA PerBit enable=1, Macro0, CA PI delay=34
3936 01:24:29.948818
3937 01:24:29.951957 [CBTSetCACLKResult] CA Dly = 34
3938 01:24:29.952068 CS Dly: 4 (0~35)
3939 01:24:29.952172 ==
3940 01:24:29.955258 Dram Type= 6, Freq= 0, CH_0, rank 1
3941 01:24:29.962610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 01:24:29.962726 ==
3943 01:24:29.965236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 01:24:29.972485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 01:24:29.975033 [CA 0] Center 37 (7~67) winsize 61
3946 01:24:29.978825 [CA 1] Center 36 (6~67) winsize 62
3947 01:24:29.981656 [CA 2] Center 35 (5~65) winsize 61
3948 01:24:29.985378 [CA 3] Center 34 (4~65) winsize 62
3949 01:24:29.988302 [CA 4] Center 34 (4~65) winsize 62
3950 01:24:29.991912 [CA 5] Center 33 (3~64) winsize 62
3951 01:24:29.992029
3952 01:24:29.995065 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 01:24:29.995173
3954 01:24:29.998613 [CATrainingPosCal] consider 2 rank data
3955 01:24:30.001624 u2DelayCellTimex100 = 270/100 ps
3956 01:24:30.004881 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3957 01:24:30.011638 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3958 01:24:30.014822 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3959 01:24:30.018151 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3960 01:24:30.021445 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3961 01:24:30.024482 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3962 01:24:30.024563
3963 01:24:30.027866 CA PerBit enable=1, Macro0, CA PI delay=34
3964 01:24:30.027943
3965 01:24:30.031344 [CBTSetCACLKResult] CA Dly = 34
3966 01:24:30.034743 CS Dly: 4 (0~36)
3967 01:24:30.034858
3968 01:24:30.038096 ----->DramcWriteLeveling(PI) begin...
3969 01:24:30.038209 ==
3970 01:24:30.041257 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 01:24:30.044724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 01:24:30.044835 ==
3973 01:24:30.047720 Write leveling (Byte 0): 35 => 35
3974 01:24:30.051265 Write leveling (Byte 1): 31 => 31
3975 01:24:30.054725 DramcWriteLeveling(PI) end<-----
3976 01:24:30.054837
3977 01:24:30.054932 ==
3978 01:24:30.057482 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 01:24:30.060928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 01:24:30.061037 ==
3981 01:24:30.064411 [Gating] SW mode calibration
3982 01:24:30.070894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3983 01:24:30.077983 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3984 01:24:30.080675 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 01:24:30.084256 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 01:24:30.090916 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 01:24:30.094098 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3988 01:24:30.097748 0 9 16 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)
3989 01:24:30.104343 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 01:24:30.107697 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 01:24:30.110455 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 01:24:30.117582 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 01:24:30.120553 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 01:24:30.124212 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 01:24:30.130602 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3996 01:24:30.133668 0 10 16 | B1->B0 | 2f2f 4242 | 0 0 | (0 0) (0 0)
3997 01:24:30.137143 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 01:24:30.143559 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 01:24:30.147332 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 01:24:30.150497 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 01:24:30.157389 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 01:24:30.160326 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 01:24:30.163782 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4004 01:24:30.170261 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4005 01:24:30.173629 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 01:24:30.177139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 01:24:30.183314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 01:24:30.186738 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 01:24:30.189740 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 01:24:30.196647 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 01:24:30.199668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 01:24:30.203476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 01:24:30.209705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 01:24:30.213294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 01:24:30.216688 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 01:24:30.223115 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 01:24:30.226277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 01:24:30.229848 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 01:24:30.236658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 01:24:30.239859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4021 01:24:30.242963 Total UI for P1: 0, mck2ui 16
4022 01:24:30.246124 best dqsien dly found for B0: ( 0, 13, 14)
4023 01:24:30.249777 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 01:24:30.253177 Total UI for P1: 0, mck2ui 16
4025 01:24:30.256123 best dqsien dly found for B1: ( 0, 13, 16)
4026 01:24:30.259457 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4027 01:24:30.262756 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4028 01:24:30.262866
4029 01:24:30.266381 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4030 01:24:30.273132 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4031 01:24:30.273219 [Gating] SW calibration Done
4032 01:24:30.273286 ==
4033 01:24:30.276146 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 01:24:30.283005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 01:24:30.283118 ==
4036 01:24:30.283212 RX Vref Scan: 0
4037 01:24:30.283303
4038 01:24:30.286015 RX Vref 0 -> 0, step: 1
4039 01:24:30.286127
4040 01:24:30.289632 RX Delay -230 -> 252, step: 16
4041 01:24:30.293068 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4042 01:24:30.296044 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4043 01:24:30.299414 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4044 01:24:30.306087 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4045 01:24:30.309722 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4046 01:24:30.312548 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4047 01:24:30.316149 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4048 01:24:30.323215 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4049 01:24:30.326318 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4050 01:24:30.329545 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4051 01:24:30.332423 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4052 01:24:30.339724 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4053 01:24:30.342553 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4054 01:24:30.346285 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4055 01:24:30.349138 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4056 01:24:30.355861 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4057 01:24:30.355954 ==
4058 01:24:30.359514 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 01:24:30.362610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 01:24:30.362718 ==
4061 01:24:30.362817 DQS Delay:
4062 01:24:30.365920 DQS0 = 0, DQS1 = 0
4063 01:24:30.366025 DQM Delay:
4064 01:24:30.369048 DQM0 = 36, DQM1 = 28
4065 01:24:30.369154 DQ Delay:
4066 01:24:30.372829 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4067 01:24:30.375628 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4068 01:24:30.379331 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4069 01:24:30.382127 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4070 01:24:30.382237
4071 01:24:30.382343
4072 01:24:30.382446 ==
4073 01:24:30.385568 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 01:24:30.389218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 01:24:30.389328 ==
4076 01:24:30.389434
4077 01:24:30.392061
4078 01:24:30.392164 TX Vref Scan disable
4079 01:24:30.395285 == TX Byte 0 ==
4080 01:24:30.399055 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4081 01:24:30.402289 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4082 01:24:30.405249 == TX Byte 1 ==
4083 01:24:30.408804 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4084 01:24:30.412453 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4085 01:24:30.412562 ==
4086 01:24:30.415445 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 01:24:30.422019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 01:24:30.422137 ==
4089 01:24:30.422245
4090 01:24:30.422351
4091 01:24:30.422456 TX Vref Scan disable
4092 01:24:30.426900 == TX Byte 0 ==
4093 01:24:30.430231 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4094 01:24:30.436459 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4095 01:24:30.436575 == TX Byte 1 ==
4096 01:24:30.440194 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4097 01:24:30.446694 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4098 01:24:30.446809
4099 01:24:30.446915 [DATLAT]
4100 01:24:30.447020 Freq=600, CH0 RK0
4101 01:24:30.447132
4102 01:24:30.449753 DATLAT Default: 0x9
4103 01:24:30.449866 0, 0xFFFF, sum = 0
4104 01:24:30.453032 1, 0xFFFF, sum = 0
4105 01:24:30.453141 2, 0xFFFF, sum = 0
4106 01:24:30.456219 3, 0xFFFF, sum = 0
4107 01:24:30.459889 4, 0xFFFF, sum = 0
4108 01:24:30.460009 5, 0xFFFF, sum = 0
4109 01:24:30.463059 6, 0xFFFF, sum = 0
4110 01:24:30.463167 7, 0xFFFF, sum = 0
4111 01:24:30.466534 8, 0x0, sum = 1
4112 01:24:30.466645 9, 0x0, sum = 2
4113 01:24:30.466744 10, 0x0, sum = 3
4114 01:24:30.469415 11, 0x0, sum = 4
4115 01:24:30.469524 best_step = 9
4116 01:24:30.469621
4117 01:24:30.469713 ==
4118 01:24:30.472731 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 01:24:30.479349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 01:24:30.479448 ==
4121 01:24:30.479525 RX Vref Scan: 1
4122 01:24:30.479621
4123 01:24:30.482715 RX Vref 0 -> 0, step: 1
4124 01:24:30.482820
4125 01:24:30.486036 RX Delay -195 -> 252, step: 8
4126 01:24:30.486148
4127 01:24:30.489414 Set Vref, RX VrefLevel [Byte0]: 62
4128 01:24:30.493156 [Byte1]: 53
4129 01:24:30.493249
4130 01:24:30.496301 Final RX Vref Byte 0 = 62 to rank0
4131 01:24:30.499508 Final RX Vref Byte 1 = 53 to rank0
4132 01:24:30.502973 Final RX Vref Byte 0 = 62 to rank1
4133 01:24:30.506353 Final RX Vref Byte 1 = 53 to rank1==
4134 01:24:30.509586 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 01:24:30.512733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 01:24:30.512823 ==
4137 01:24:30.516430 DQS Delay:
4138 01:24:30.516540 DQS0 = 0, DQS1 = 0
4139 01:24:30.519319 DQM Delay:
4140 01:24:30.519414 DQM0 = 35, DQM1 = 29
4141 01:24:30.519485 DQ Delay:
4142 01:24:30.522358 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4143 01:24:30.526205 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4144 01:24:30.529499 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4145 01:24:30.532457 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4146 01:24:30.532548
4147 01:24:30.532635
4148 01:24:30.542909 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4149 01:24:30.546124 CH0 RK0: MR19=808, MR18=3F3E
4150 01:24:30.552341 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4151 01:24:30.552429
4152 01:24:30.555920 ----->DramcWriteLeveling(PI) begin...
4153 01:24:30.556011 ==
4154 01:24:30.559024 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 01:24:30.562320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 01:24:30.562409 ==
4157 01:24:30.565571 Write leveling (Byte 0): 31 => 31
4158 01:24:30.569591 Write leveling (Byte 1): 31 => 31
4159 01:24:30.572312 DramcWriteLeveling(PI) end<-----
4160 01:24:30.572394
4161 01:24:30.572479 ==
4162 01:24:30.575795 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 01:24:30.579269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 01:24:30.579379 ==
4165 01:24:30.582775 [Gating] SW mode calibration
4166 01:24:30.589235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4167 01:24:30.595553 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4168 01:24:30.598988 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 01:24:30.602013 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 01:24:30.608724 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 01:24:30.612427 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4172 01:24:30.615567 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
4173 01:24:30.622490 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 01:24:30.625243 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 01:24:30.628511 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 01:24:30.635399 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 01:24:30.638451 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 01:24:30.642368 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4179 01:24:30.648569 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4180 01:24:30.651827 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4181 01:24:30.655206 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 01:24:30.661905 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 01:24:30.665619 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 01:24:30.668638 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 01:24:30.675280 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 01:24:30.678312 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 01:24:30.681848 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4188 01:24:30.688768 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 01:24:30.691775 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 01:24:30.694887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 01:24:30.701670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 01:24:30.705149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 01:24:30.708369 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 01:24:30.714660 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 01:24:30.718022 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 01:24:30.721726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 01:24:30.728076 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 01:24:30.731522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 01:24:30.734891 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 01:24:30.738040 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 01:24:30.744689 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 01:24:30.748110 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 01:24:30.751445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4204 01:24:30.758290 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4205 01:24:30.761145 Total UI for P1: 0, mck2ui 16
4206 01:24:30.764769 best dqsien dly found for B0: ( 0, 13, 12)
4207 01:24:30.768292 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 01:24:30.771209 Total UI for P1: 0, mck2ui 16
4209 01:24:30.774725 best dqsien dly found for B1: ( 0, 13, 16)
4210 01:24:30.777972 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 01:24:30.781492 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4212 01:24:30.781570
4213 01:24:30.784499 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 01:24:30.787956 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4215 01:24:30.791152 [Gating] SW calibration Done
4216 01:24:30.791232 ==
4217 01:24:30.794479 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 01:24:30.800847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 01:24:30.800932 ==
4220 01:24:30.801000 RX Vref Scan: 0
4221 01:24:30.801099
4222 01:24:30.804434 RX Vref 0 -> 0, step: 1
4223 01:24:30.804512
4224 01:24:30.807720 RX Delay -230 -> 252, step: 16
4225 01:24:30.811100 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4226 01:24:30.814366 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4227 01:24:30.817401 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4228 01:24:30.824228 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4229 01:24:30.827450 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4230 01:24:30.830818 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4231 01:24:30.834318 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4232 01:24:30.840857 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4233 01:24:30.844394 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4234 01:24:30.847487 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4235 01:24:30.850795 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4236 01:24:30.857222 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4237 01:24:30.860391 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4238 01:24:30.864890 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4239 01:24:30.867365 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4240 01:24:30.873740 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4241 01:24:30.873826 ==
4242 01:24:30.877164 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 01:24:30.880683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 01:24:30.880769 ==
4245 01:24:30.880835 DQS Delay:
4246 01:24:30.883450 DQS0 = 0, DQS1 = 0
4247 01:24:30.883561 DQM Delay:
4248 01:24:30.887250 DQM0 = 36, DQM1 = 29
4249 01:24:30.887360 DQ Delay:
4250 01:24:30.890722 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4251 01:24:30.893561 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4252 01:24:30.897044 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4253 01:24:30.900471 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4254 01:24:30.900582
4255 01:24:30.900677
4256 01:24:30.900775 ==
4257 01:24:30.903857 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 01:24:30.906976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 01:24:30.907079 ==
4260 01:24:30.907171
4261 01:24:30.907263
4262 01:24:30.910221 TX Vref Scan disable
4263 01:24:30.913740 == TX Byte 0 ==
4264 01:24:30.917018 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4265 01:24:30.920090 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4266 01:24:30.923567 == TX Byte 1 ==
4267 01:24:30.926580 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4268 01:24:30.930060 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4269 01:24:30.930136 ==
4270 01:24:30.933354 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 01:24:30.940091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 01:24:30.940173 ==
4273 01:24:30.940238
4274 01:24:30.940298
4275 01:24:30.940356 TX Vref Scan disable
4276 01:24:30.944462 == TX Byte 0 ==
4277 01:24:30.947736 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4278 01:24:30.954626 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4279 01:24:30.954715 == TX Byte 1 ==
4280 01:24:30.958081 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4281 01:24:30.964255 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4282 01:24:30.964340
4283 01:24:30.964406 [DATLAT]
4284 01:24:30.964467 Freq=600, CH0 RK1
4285 01:24:30.964526
4286 01:24:30.967665 DATLAT Default: 0x9
4287 01:24:30.967785 0, 0xFFFF, sum = 0
4288 01:24:30.970783 1, 0xFFFF, sum = 0
4289 01:24:30.974359 2, 0xFFFF, sum = 0
4290 01:24:30.974445 3, 0xFFFF, sum = 0
4291 01:24:30.977586 4, 0xFFFF, sum = 0
4292 01:24:30.977696 5, 0xFFFF, sum = 0
4293 01:24:30.980923 6, 0xFFFF, sum = 0
4294 01:24:30.981041 7, 0xFFFF, sum = 0
4295 01:24:30.983805 8, 0x0, sum = 1
4296 01:24:30.983915 9, 0x0, sum = 2
4297 01:24:30.987812 10, 0x0, sum = 3
4298 01:24:30.987899 11, 0x0, sum = 4
4299 01:24:30.987965 best_step = 9
4300 01:24:30.988026
4301 01:24:30.990678 ==
4302 01:24:30.990788 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 01:24:30.997483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 01:24:30.997570 ==
4305 01:24:30.997635 RX Vref Scan: 0
4306 01:24:30.997696
4307 01:24:31.000999 RX Vref 0 -> 0, step: 1
4308 01:24:31.001108
4309 01:24:31.004209 RX Delay -195 -> 252, step: 8
4310 01:24:31.010720 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4311 01:24:31.014099 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4312 01:24:31.017599 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4313 01:24:31.020597 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4314 01:24:31.023995 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4315 01:24:31.031069 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4316 01:24:31.033855 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4317 01:24:31.037435 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4318 01:24:31.040502 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4319 01:24:31.044028 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4320 01:24:31.050249 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4321 01:24:31.053628 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4322 01:24:31.057228 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4323 01:24:31.063564 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4324 01:24:31.066549 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4325 01:24:31.070538 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4326 01:24:31.070621 ==
4327 01:24:31.073324 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 01:24:31.076599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 01:24:31.076688 ==
4330 01:24:31.079735 DQS Delay:
4331 01:24:31.079821 DQS0 = 0, DQS1 = 0
4332 01:24:31.082971 DQM Delay:
4333 01:24:31.083079 DQM0 = 34, DQM1 = 28
4334 01:24:31.086570 DQ Delay:
4335 01:24:31.086679 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4336 01:24:31.089765 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4337 01:24:31.092879 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4338 01:24:31.096233 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4339 01:24:31.096319
4340 01:24:31.099940
4341 01:24:31.106256 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4342 01:24:31.109954 CH0 RK1: MR19=808, MR18=6E3C
4343 01:24:31.116375 CH0_RK1: MR19=0x808, MR18=0x6E3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4344 01:24:31.119597 [RxdqsGatingPostProcess] freq 600
4345 01:24:31.122715 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 01:24:31.126191 Pre-setting of DQS Precalculation
4347 01:24:31.132560 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 01:24:31.132646 ==
4349 01:24:31.135970 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 01:24:31.139350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 01:24:31.139466 ==
4352 01:24:31.145693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 01:24:31.149311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4354 01:24:31.153352 [CA 0] Center 35 (5~66) winsize 62
4355 01:24:31.156721 [CA 1] Center 36 (6~66) winsize 61
4356 01:24:31.159983 [CA 2] Center 34 (4~65) winsize 62
4357 01:24:31.163732 [CA 3] Center 34 (4~65) winsize 62
4358 01:24:31.166684 [CA 4] Center 34 (4~65) winsize 62
4359 01:24:31.170106 [CA 5] Center 33 (3~64) winsize 62
4360 01:24:31.170182
4361 01:24:31.173728 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4362 01:24:31.173802
4363 01:24:31.176656 [CATrainingPosCal] consider 1 rank data
4364 01:24:31.180196 u2DelayCellTimex100 = 270/100 ps
4365 01:24:31.183563 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 01:24:31.186580 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4367 01:24:31.193656 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4368 01:24:31.197000 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4369 01:24:31.200004 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4370 01:24:31.203254 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 01:24:31.203366
4372 01:24:31.206833 CA PerBit enable=1, Macro0, CA PI delay=33
4373 01:24:31.206942
4374 01:24:31.209876 [CBTSetCACLKResult] CA Dly = 33
4375 01:24:31.209983 CS Dly: 4 (0~35)
4376 01:24:31.213141 ==
4377 01:24:31.213254 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 01:24:31.220095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 01:24:31.220206 ==
4380 01:24:31.223485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 01:24:31.229943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 01:24:31.233950 [CA 0] Center 36 (6~66) winsize 61
4383 01:24:31.237096 [CA 1] Center 35 (5~66) winsize 62
4384 01:24:31.240220 [CA 2] Center 34 (4~65) winsize 62
4385 01:24:31.243733 [CA 3] Center 34 (3~65) winsize 63
4386 01:24:31.246757 [CA 4] Center 34 (4~65) winsize 62
4387 01:24:31.249985 [CA 5] Center 33 (3~64) winsize 62
4388 01:24:31.250065
4389 01:24:31.253367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 01:24:31.253442
4391 01:24:31.256880 [CATrainingPosCal] consider 2 rank data
4392 01:24:31.260166 u2DelayCellTimex100 = 270/100 ps
4393 01:24:31.263513 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4394 01:24:31.270050 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4395 01:24:31.273758 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 01:24:31.276439 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 01:24:31.279785 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 01:24:31.283245 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 01:24:31.283355
4400 01:24:31.286312 CA PerBit enable=1, Macro0, CA PI delay=33
4401 01:24:31.286397
4402 01:24:31.289663 [CBTSetCACLKResult] CA Dly = 33
4403 01:24:31.289773 CS Dly: 4 (0~36)
4404 01:24:31.293219
4405 01:24:31.296485 ----->DramcWriteLeveling(PI) begin...
4406 01:24:31.296570 ==
4407 01:24:31.299625 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 01:24:31.303044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 01:24:31.303157 ==
4410 01:24:31.306451 Write leveling (Byte 0): 28 => 28
4411 01:24:31.310038 Write leveling (Byte 1): 30 => 30
4412 01:24:31.312984 DramcWriteLeveling(PI) end<-----
4413 01:24:31.313068
4414 01:24:31.313134 ==
4415 01:24:31.316359 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 01:24:31.319724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 01:24:31.319812 ==
4418 01:24:31.323193 [Gating] SW mode calibration
4419 01:24:31.329624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 01:24:31.336565 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 01:24:31.339735 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 01:24:31.342964 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 01:24:31.349389 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 01:24:31.352761 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 0)
4425 01:24:31.356224 0 9 16 | B1->B0 | 2525 2525 | 0 0 | (1 1) (0 0)
4426 01:24:31.362649 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 01:24:31.366170 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 01:24:31.369806 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 01:24:31.376000 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 01:24:31.379491 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 01:24:31.382678 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 01:24:31.389286 0 10 12 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
4433 01:24:31.392752 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 01:24:31.395618 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 01:24:31.402418 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 01:24:31.405894 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 01:24:31.409151 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 01:24:31.412210 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 01:24:31.419105 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 01:24:31.422562 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 01:24:31.425769 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4442 01:24:31.431991 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 01:24:31.435544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 01:24:31.438876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 01:24:31.445671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 01:24:31.448646 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 01:24:31.452173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 01:24:31.458579 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 01:24:31.461978 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 01:24:31.465345 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 01:24:31.472306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 01:24:31.475394 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 01:24:31.478543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 01:24:31.484980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 01:24:31.488396 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 01:24:31.491896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4457 01:24:31.498353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4458 01:24:31.501952 Total UI for P1: 0, mck2ui 16
4459 01:24:31.505174 best dqsien dly found for B1: ( 0, 13, 14)
4460 01:24:31.508458 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 01:24:31.511569 Total UI for P1: 0, mck2ui 16
4462 01:24:31.514975 best dqsien dly found for B0: ( 0, 13, 14)
4463 01:24:31.518532 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4464 01:24:31.522119 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4465 01:24:31.522226
4466 01:24:31.524810 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4467 01:24:31.528212 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4468 01:24:31.531501 [Gating] SW calibration Done
4469 01:24:31.531609 ==
4470 01:24:31.535453 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 01:24:31.541787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 01:24:31.541905 ==
4473 01:24:31.542004 RX Vref Scan: 0
4474 01:24:31.542100
4475 01:24:31.545549 RX Vref 0 -> 0, step: 1
4476 01:24:31.545658
4477 01:24:31.548022 RX Delay -230 -> 252, step: 16
4478 01:24:31.551398 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4479 01:24:31.555273 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4480 01:24:31.558588 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4481 01:24:31.564553 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4482 01:24:31.568269 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4483 01:24:31.571104 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4484 01:24:31.574583 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4485 01:24:31.580987 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4486 01:24:31.584734 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4487 01:24:31.587584 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4488 01:24:31.591200 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4489 01:24:31.597487 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4490 01:24:31.600855 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4491 01:24:31.604551 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4492 01:24:31.608061 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4493 01:24:31.610787 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4494 01:24:31.614308 ==
4495 01:24:31.617355 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 01:24:31.620845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 01:24:31.620929 ==
4498 01:24:31.620995 DQS Delay:
4499 01:24:31.624296 DQS0 = 0, DQS1 = 0
4500 01:24:31.624376 DQM Delay:
4501 01:24:31.628013 DQM0 = 36, DQM1 = 28
4502 01:24:31.628100 DQ Delay:
4503 01:24:31.630571 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4504 01:24:31.633969 DQ4 =33, DQ5 =41, DQ6 =49, DQ7 =33
4505 01:24:31.637512 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4506 01:24:31.640778 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4507 01:24:31.640860
4508 01:24:31.640929
4509 01:24:31.640989 ==
4510 01:24:31.643991 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 01:24:31.647202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 01:24:31.647310 ==
4513 01:24:31.647409
4514 01:24:31.647474
4515 01:24:31.650980 TX Vref Scan disable
4516 01:24:31.654344 == TX Byte 0 ==
4517 01:24:31.657279 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4518 01:24:31.660940 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4519 01:24:31.663963 == TX Byte 1 ==
4520 01:24:31.666958 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4521 01:24:31.670795 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4522 01:24:31.670909 ==
4523 01:24:31.673701 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 01:24:31.680665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 01:24:31.680785 ==
4526 01:24:31.680889
4527 01:24:31.680983
4528 01:24:31.681077 TX Vref Scan disable
4529 01:24:31.684727 == TX Byte 0 ==
4530 01:24:31.688195 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 01:24:31.694719 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 01:24:31.694815 == TX Byte 1 ==
4533 01:24:31.698116 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4534 01:24:31.705014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4535 01:24:31.705162
4536 01:24:31.705270 [DATLAT]
4537 01:24:31.705361 Freq=600, CH1 RK0
4538 01:24:31.705459
4539 01:24:31.707932 DATLAT Default: 0x9
4540 01:24:31.708040 0, 0xFFFF, sum = 0
4541 01:24:31.711748 1, 0xFFFF, sum = 0
4542 01:24:31.711887 2, 0xFFFF, sum = 0
4543 01:24:31.715148 3, 0xFFFF, sum = 0
4544 01:24:31.718581 4, 0xFFFF, sum = 0
4545 01:24:31.718702 5, 0xFFFF, sum = 0
4546 01:24:31.721315 6, 0xFFFF, sum = 0
4547 01:24:31.721460 7, 0xFFFF, sum = 0
4548 01:24:31.721573 8, 0x0, sum = 1
4549 01:24:31.725087 9, 0x0, sum = 2
4550 01:24:31.725232 10, 0x0, sum = 3
4551 01:24:31.728098 11, 0x0, sum = 4
4552 01:24:31.728215 best_step = 9
4553 01:24:31.728313
4554 01:24:31.728411 ==
4555 01:24:31.731460 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 01:24:31.737852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 01:24:31.738008 ==
4558 01:24:31.738111 RX Vref Scan: 1
4559 01:24:31.738208
4560 01:24:31.741242 RX Vref 0 -> 0, step: 1
4561 01:24:31.741383
4562 01:24:31.744573 RX Delay -195 -> 252, step: 8
4563 01:24:31.744725
4564 01:24:31.748003 Set Vref, RX VrefLevel [Byte0]: 55
4565 01:24:31.751178 [Byte1]: 52
4566 01:24:31.751338
4567 01:24:31.754520 Final RX Vref Byte 0 = 55 to rank0
4568 01:24:31.758226 Final RX Vref Byte 1 = 52 to rank0
4569 01:24:31.761095 Final RX Vref Byte 0 = 55 to rank1
4570 01:24:31.764189 Final RX Vref Byte 1 = 52 to rank1==
4571 01:24:31.767641 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 01:24:31.771101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 01:24:31.771222 ==
4574 01:24:31.774517 DQS Delay:
4575 01:24:31.774644 DQS0 = 0, DQS1 = 0
4576 01:24:31.777566 DQM Delay:
4577 01:24:31.777678 DQM0 = 39, DQM1 = 28
4578 01:24:31.777776 DQ Delay:
4579 01:24:31.780975 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =32
4580 01:24:31.784523 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4581 01:24:31.788018 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4582 01:24:31.791077 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4583 01:24:31.791198
4584 01:24:31.791297
4585 01:24:31.801133 [DQSOSCAuto] RK0, (LSB)MR18= 0x2331, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4586 01:24:31.804224 CH1 RK0: MR19=808, MR18=2331
4587 01:24:31.811176 CH1_RK0: MR19=0x808, MR18=0x2331, DQSOSC=400, MR23=63, INC=163, DEC=109
4588 01:24:31.811310
4589 01:24:31.814552 ----->DramcWriteLeveling(PI) begin...
4590 01:24:31.814666 ==
4591 01:24:31.817356 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 01:24:31.820767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 01:24:31.820861 ==
4594 01:24:31.824382 Write leveling (Byte 0): 29 => 29
4595 01:24:31.827181 Write leveling (Byte 1): 29 => 29
4596 01:24:31.830881 DramcWriteLeveling(PI) end<-----
4597 01:24:31.830980
4598 01:24:31.831048 ==
4599 01:24:31.834257 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 01:24:31.837159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 01:24:31.837268 ==
4602 01:24:31.840605 [Gating] SW mode calibration
4603 01:24:31.847414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4604 01:24:31.854145 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4605 01:24:31.857299 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 01:24:31.860704 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 01:24:31.867228 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 01:24:31.870408 0 9 12 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
4609 01:24:31.873545 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4610 01:24:31.880307 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 01:24:31.883771 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 01:24:31.887221 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 01:24:31.894030 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 01:24:31.896757 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 01:24:31.900161 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4616 01:24:31.906807 0 10 12 | B1->B0 | 2424 3a3a | 1 0 | (0 0) (0 0)
4617 01:24:31.910129 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 01:24:31.913457 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 01:24:31.920281 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 01:24:31.923491 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 01:24:31.926859 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 01:24:31.933436 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 01:24:31.936450 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 01:24:31.939907 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4625 01:24:31.946645 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 01:24:31.950285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 01:24:31.953377 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 01:24:31.960283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 01:24:31.963359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 01:24:31.966538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 01:24:31.969918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 01:24:31.976724 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 01:24:31.980200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 01:24:31.983097 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 01:24:31.989705 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 01:24:31.993164 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 01:24:31.996265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 01:24:32.003065 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 01:24:32.006339 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 01:24:32.009567 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 01:24:32.013075 Total UI for P1: 0, mck2ui 16
4642 01:24:32.016705 best dqsien dly found for B0: ( 0, 13, 10)
4643 01:24:32.019632 Total UI for P1: 0, mck2ui 16
4644 01:24:32.023091 best dqsien dly found for B1: ( 0, 13, 10)
4645 01:24:32.026986 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4646 01:24:32.029931 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4647 01:24:32.030049
4648 01:24:32.036221 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4649 01:24:32.039467 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4650 01:24:32.042778 [Gating] SW calibration Done
4651 01:24:32.042897 ==
4652 01:24:32.046222 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 01:24:32.049734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 01:24:32.049855 ==
4655 01:24:32.049951 RX Vref Scan: 0
4656 01:24:32.050050
4657 01:24:32.053044 RX Vref 0 -> 0, step: 1
4658 01:24:32.053152
4659 01:24:32.056385 RX Delay -230 -> 252, step: 16
4660 01:24:32.059361 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4661 01:24:32.066246 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4662 01:24:32.069987 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4663 01:24:32.073197 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4664 01:24:32.076683 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4665 01:24:32.079890 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4666 01:24:32.086458 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4667 01:24:32.089641 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4668 01:24:32.093191 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4669 01:24:32.096136 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4670 01:24:32.099655 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4671 01:24:32.106663 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4672 01:24:32.109188 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4673 01:24:32.113134 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4674 01:24:32.119215 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4675 01:24:32.122427 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4676 01:24:32.122512 ==
4677 01:24:32.126293 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 01:24:32.128926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 01:24:32.129012 ==
4680 01:24:32.132736 DQS Delay:
4681 01:24:32.132822 DQS0 = 0, DQS1 = 0
4682 01:24:32.132888 DQM Delay:
4683 01:24:32.135791 DQM0 = 34, DQM1 = 29
4684 01:24:32.135875 DQ Delay:
4685 01:24:32.139503 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4686 01:24:32.142575 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4687 01:24:32.145779 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4688 01:24:32.148887 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4689 01:24:32.149008
4690 01:24:32.149100
4691 01:24:32.149198 ==
4692 01:24:32.152292 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 01:24:32.159110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 01:24:32.159230 ==
4695 01:24:32.159330
4696 01:24:32.159436
4697 01:24:32.159522 TX Vref Scan disable
4698 01:24:32.162464 == TX Byte 0 ==
4699 01:24:32.165459 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 01:24:32.172434 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 01:24:32.172525 == TX Byte 1 ==
4702 01:24:32.175897 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 01:24:32.182304 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 01:24:32.182432 ==
4705 01:24:32.185752 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 01:24:32.188730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 01:24:32.188850 ==
4708 01:24:32.188944
4709 01:24:32.189029
4710 01:24:32.192412 TX Vref Scan disable
4711 01:24:32.195675 == TX Byte 0 ==
4712 01:24:32.198381 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 01:24:32.202219 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 01:24:32.205259 == TX Byte 1 ==
4715 01:24:32.208268 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 01:24:32.211735 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 01:24:32.211873
4718 01:24:32.211971 [DATLAT]
4719 01:24:32.214882 Freq=600, CH1 RK1
4720 01:24:32.214990
4721 01:24:32.218256 DATLAT Default: 0x9
4722 01:24:32.218372 0, 0xFFFF, sum = 0
4723 01:24:32.222012 1, 0xFFFF, sum = 0
4724 01:24:32.222134 2, 0xFFFF, sum = 0
4725 01:24:32.225113 3, 0xFFFF, sum = 0
4726 01:24:32.225264 4, 0xFFFF, sum = 0
4727 01:24:32.228596 5, 0xFFFF, sum = 0
4728 01:24:32.228746 6, 0xFFFF, sum = 0
4729 01:24:32.231758 7, 0xFFFF, sum = 0
4730 01:24:32.231883 8, 0x0, sum = 1
4731 01:24:32.235007 9, 0x0, sum = 2
4732 01:24:32.235130 10, 0x0, sum = 3
4733 01:24:32.238042 11, 0x0, sum = 4
4734 01:24:32.238159 best_step = 9
4735 01:24:32.238258
4736 01:24:32.238357 ==
4737 01:24:32.241537 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 01:24:32.245063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 01:24:32.245183 ==
4740 01:24:32.248033 RX Vref Scan: 0
4741 01:24:32.248151
4742 01:24:32.251171 RX Vref 0 -> 0, step: 1
4743 01:24:32.251286
4744 01:24:32.251392 RX Delay -195 -> 252, step: 8
4745 01:24:32.259131 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4746 01:24:32.262877 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4747 01:24:32.265929 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4748 01:24:32.269134 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4749 01:24:32.276269 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4750 01:24:32.278960 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4751 01:24:32.282912 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4752 01:24:32.285674 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4753 01:24:32.289443 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4754 01:24:32.295890 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4755 01:24:32.299202 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4756 01:24:32.302604 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4757 01:24:32.305756 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4758 01:24:32.312519 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4759 01:24:32.315891 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4760 01:24:32.318746 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4761 01:24:32.318867 ==
4762 01:24:32.322092 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 01:24:32.329022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 01:24:32.329144 ==
4765 01:24:32.329245 DQS Delay:
4766 01:24:32.329346 DQS0 = 0, DQS1 = 0
4767 01:24:32.331940 DQM Delay:
4768 01:24:32.332053 DQM0 = 36, DQM1 = 28
4769 01:24:32.335603 DQ Delay:
4770 01:24:32.338898 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4771 01:24:32.342254 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =28
4772 01:24:32.345904 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4773 01:24:32.348795 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4774 01:24:32.348912
4775 01:24:32.349014
4776 01:24:32.355651 [DQSOSCAuto] RK1, (LSB)MR18= 0x3455, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4777 01:24:32.358982 CH1 RK1: MR19=808, MR18=3455
4778 01:24:32.365390 CH1_RK1: MR19=0x808, MR18=0x3455, DQSOSC=393, MR23=63, INC=169, DEC=113
4779 01:24:32.368604 [RxdqsGatingPostProcess] freq 600
4780 01:24:32.372261 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 01:24:32.375171 Pre-setting of DQS Precalculation
4782 01:24:32.382086 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 01:24:32.388410 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 01:24:32.395210 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 01:24:32.395346
4786 01:24:32.395459
4787 01:24:32.398942 [Calibration Summary] 1200 Mbps
4788 01:24:32.399060 CH 0, Rank 0
4789 01:24:32.402144 SW Impedance : PASS
4790 01:24:32.405282 DUTY Scan : NO K
4791 01:24:32.405408 ZQ Calibration : PASS
4792 01:24:32.408751 Jitter Meter : NO K
4793 01:24:32.411780 CBT Training : PASS
4794 01:24:32.411902 Write leveling : PASS
4795 01:24:32.415290 RX DQS gating : PASS
4796 01:24:32.415416 RX DQ/DQS(RDDQC) : PASS
4797 01:24:32.418648 TX DQ/DQS : PASS
4798 01:24:32.421952 RX DATLAT : PASS
4799 01:24:32.422066 RX DQ/DQS(Engine): PASS
4800 01:24:32.425458 TX OE : NO K
4801 01:24:32.425573 All Pass.
4802 01:24:32.425676
4803 01:24:32.428273 CH 0, Rank 1
4804 01:24:32.428389 SW Impedance : PASS
4805 01:24:32.431764 DUTY Scan : NO K
4806 01:24:32.434990 ZQ Calibration : PASS
4807 01:24:32.435112 Jitter Meter : NO K
4808 01:24:32.438779 CBT Training : PASS
4809 01:24:32.441822 Write leveling : PASS
4810 01:24:32.441942 RX DQS gating : PASS
4811 01:24:32.444999 RX DQ/DQS(RDDQC) : PASS
4812 01:24:32.448323 TX DQ/DQS : PASS
4813 01:24:32.448442 RX DATLAT : PASS
4814 01:24:32.451719 RX DQ/DQS(Engine): PASS
4815 01:24:32.455235 TX OE : NO K
4816 01:24:32.455358 All Pass.
4817 01:24:32.455470
4818 01:24:32.455571 CH 1, Rank 0
4819 01:24:32.458342 SW Impedance : PASS
4820 01:24:32.461724 DUTY Scan : NO K
4821 01:24:32.461840 ZQ Calibration : PASS
4822 01:24:32.464961 Jitter Meter : NO K
4823 01:24:32.468217 CBT Training : PASS
4824 01:24:32.468336 Write leveling : PASS
4825 01:24:32.471764 RX DQS gating : PASS
4826 01:24:32.471881 RX DQ/DQS(RDDQC) : PASS
4827 01:24:32.474880 TX DQ/DQS : PASS
4828 01:24:32.478434 RX DATLAT : PASS
4829 01:24:32.478558 RX DQ/DQS(Engine): PASS
4830 01:24:32.481348 TX OE : NO K
4831 01:24:32.481464 All Pass.
4832 01:24:32.481568
4833 01:24:32.485255 CH 1, Rank 1
4834 01:24:32.485372 SW Impedance : PASS
4835 01:24:32.488175 DUTY Scan : NO K
4836 01:24:32.491694 ZQ Calibration : PASS
4837 01:24:32.491821 Jitter Meter : NO K
4838 01:24:32.495012 CBT Training : PASS
4839 01:24:32.498310 Write leveling : PASS
4840 01:24:32.498429 RX DQS gating : PASS
4841 01:24:32.501385 RX DQ/DQS(RDDQC) : PASS
4842 01:24:32.505141 TX DQ/DQS : PASS
4843 01:24:32.505264 RX DATLAT : PASS
4844 01:24:32.508173 RX DQ/DQS(Engine): PASS
4845 01:24:32.511731 TX OE : NO K
4846 01:24:32.511849 All Pass.
4847 01:24:32.511953
4848 01:24:32.512050 DramC Write-DBI off
4849 01:24:32.515086 PER_BANK_REFRESH: Hybrid Mode
4850 01:24:32.518381 TX_TRACKING: ON
4851 01:24:32.524747 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 01:24:32.528102 [FAST_K] Save calibration result to emmc
4853 01:24:32.534744 dramc_set_vcore_voltage set vcore to 662500
4854 01:24:32.534876 Read voltage for 933, 3
4855 01:24:32.534986 Vio18 = 0
4856 01:24:32.537968 Vcore = 662500
4857 01:24:32.538095 Vdram = 0
4858 01:24:32.538197 Vddq = 0
4859 01:24:32.541879 Vmddr = 0
4860 01:24:32.544767 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 01:24:32.551277 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 01:24:32.554825 MEM_TYPE=3, freq_sel=17
4863 01:24:32.554954 sv_algorithm_assistance_LP4_1600
4864 01:24:32.561232 ============ PULL DRAM RESETB DOWN ============
4865 01:24:32.564545 ========== PULL DRAM RESETB DOWN end =========
4866 01:24:32.567961 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 01:24:32.571467 ===================================
4868 01:24:32.574367 LPDDR4 DRAM CONFIGURATION
4869 01:24:32.577794 ===================================
4870 01:24:32.581077 EX_ROW_EN[0] = 0x0
4871 01:24:32.581176 EX_ROW_EN[1] = 0x0
4872 01:24:32.584545 LP4Y_EN = 0x0
4873 01:24:32.584651 WORK_FSP = 0x0
4874 01:24:32.587859 WL = 0x3
4875 01:24:32.587951 RL = 0x3
4876 01:24:32.591327 BL = 0x2
4877 01:24:32.591452 RPST = 0x0
4878 01:24:32.594797 RD_PRE = 0x0
4879 01:24:32.594879 WR_PRE = 0x1
4880 01:24:32.597740 WR_PST = 0x0
4881 01:24:32.597853 DBI_WR = 0x0
4882 01:24:32.601291 DBI_RD = 0x0
4883 01:24:32.601373 OTF = 0x1
4884 01:24:32.604402 ===================================
4885 01:24:32.608137 ===================================
4886 01:24:32.611051 ANA top config
4887 01:24:32.614572 ===================================
4888 01:24:32.617786 DLL_ASYNC_EN = 0
4889 01:24:32.617869 ALL_SLAVE_EN = 1
4890 01:24:32.621174 NEW_RANK_MODE = 1
4891 01:24:32.624213 DLL_IDLE_MODE = 1
4892 01:24:32.627622 LP45_APHY_COMB_EN = 1
4893 01:24:32.631037 TX_ODT_DIS = 1
4894 01:24:32.631143 NEW_8X_MODE = 1
4895 01:24:32.633971 ===================================
4896 01:24:32.637773 ===================================
4897 01:24:32.640719 data_rate = 1866
4898 01:24:32.644066 CKR = 1
4899 01:24:32.647575 DQ_P2S_RATIO = 8
4900 01:24:32.650755 ===================================
4901 01:24:32.654140 CA_P2S_RATIO = 8
4902 01:24:32.657608 DQ_CA_OPEN = 0
4903 01:24:32.657697 DQ_SEMI_OPEN = 0
4904 01:24:32.660553 CA_SEMI_OPEN = 0
4905 01:24:32.664209 CA_FULL_RATE = 0
4906 01:24:32.667393 DQ_CKDIV4_EN = 1
4907 01:24:32.670981 CA_CKDIV4_EN = 1
4908 01:24:32.674268 CA_PREDIV_EN = 0
4909 01:24:32.674354 PH8_DLY = 0
4910 01:24:32.677242 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 01:24:32.680279 DQ_AAMCK_DIV = 4
4912 01:24:32.684108 CA_AAMCK_DIV = 4
4913 01:24:32.687072 CA_ADMCK_DIV = 4
4914 01:24:32.690534 DQ_TRACK_CA_EN = 0
4915 01:24:32.690616 CA_PICK = 933
4916 01:24:32.693876 CA_MCKIO = 933
4917 01:24:32.696724 MCKIO_SEMI = 0
4918 01:24:32.700207 PLL_FREQ = 3732
4919 01:24:32.703413 DQ_UI_PI_RATIO = 32
4920 01:24:32.706993 CA_UI_PI_RATIO = 0
4921 01:24:32.710174 ===================================
4922 01:24:32.713503 ===================================
4923 01:24:32.716787 memory_type:LPDDR4
4924 01:24:32.716874 GP_NUM : 10
4925 01:24:32.720291 SRAM_EN : 1
4926 01:24:32.720378 MD32_EN : 0
4927 01:24:32.723388 ===================================
4928 01:24:32.727000 [ANA_INIT] >>>>>>>>>>>>>>
4929 01:24:32.729861 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 01:24:32.733125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 01:24:32.736427 ===================================
4932 01:24:32.740176 data_rate = 1866,PCW = 0X8f00
4933 01:24:32.743724 ===================================
4934 01:24:32.747131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 01:24:32.750219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 01:24:32.756643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 01:24:32.763514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 01:24:32.766704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 01:24:32.769907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 01:24:32.770025 [ANA_INIT] flow start
4941 01:24:32.773673 [ANA_INIT] PLL >>>>>>>>
4942 01:24:32.776306 [ANA_INIT] PLL <<<<<<<<
4943 01:24:32.776391 [ANA_INIT] MIDPI >>>>>>>>
4944 01:24:32.780106 [ANA_INIT] MIDPI <<<<<<<<
4945 01:24:32.783098 [ANA_INIT] DLL >>>>>>>>
4946 01:24:32.783184 [ANA_INIT] flow end
4947 01:24:32.790146 ============ LP4 DIFF to SE enter ============
4948 01:24:32.792924 ============ LP4 DIFF to SE exit ============
4949 01:24:32.793028 [ANA_INIT] <<<<<<<<<<<<<
4950 01:24:32.796299 [Flow] Enable top DCM control >>>>>
4951 01:24:32.799527 [Flow] Enable top DCM control <<<<<
4952 01:24:32.802932 Enable DLL master slave shuffle
4953 01:24:32.810246 ==============================================================
4954 01:24:32.812805 Gating Mode config
4955 01:24:32.816291 ==============================================================
4956 01:24:32.819635 Config description:
4957 01:24:32.829463 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 01:24:32.836353 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 01:24:32.839061 SELPH_MODE 0: By rank 1: By Phase
4960 01:24:32.846209 ==============================================================
4961 01:24:32.849454 GAT_TRACK_EN = 1
4962 01:24:32.852389 RX_GATING_MODE = 2
4963 01:24:32.855818 RX_GATING_TRACK_MODE = 2
4964 01:24:32.855934 SELPH_MODE = 1
4965 01:24:32.859174 PICG_EARLY_EN = 1
4966 01:24:32.862512 VALID_LAT_VALUE = 1
4967 01:24:32.869164 ==============================================================
4968 01:24:32.872584 Enter into Gating configuration >>>>
4969 01:24:32.875713 Exit from Gating configuration <<<<
4970 01:24:32.879309 Enter into DVFS_PRE_config >>>>>
4971 01:24:32.889190 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 01:24:32.892347 Exit from DVFS_PRE_config <<<<<
4973 01:24:32.895743 Enter into PICG configuration >>>>
4974 01:24:32.898779 Exit from PICG configuration <<<<
4975 01:24:32.902336 [RX_INPUT] configuration >>>>>
4976 01:24:32.905334 [RX_INPUT] configuration <<<<<
4977 01:24:32.908736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 01:24:32.915197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 01:24:32.921749 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 01:24:32.928530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 01:24:32.935333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 01:24:32.942143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 01:24:32.945150 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 01:24:32.948367 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 01:24:32.951838 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 01:24:32.958261 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 01:24:32.961506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 01:24:32.965231 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 01:24:32.968221 ===================================
4990 01:24:32.971442 LPDDR4 DRAM CONFIGURATION
4991 01:24:32.975178 ===================================
4992 01:24:32.975291 EX_ROW_EN[0] = 0x0
4993 01:24:32.978197 EX_ROW_EN[1] = 0x0
4994 01:24:32.978274 LP4Y_EN = 0x0
4995 01:24:32.981905 WORK_FSP = 0x0
4996 01:24:32.982013 WL = 0x3
4997 01:24:32.984751 RL = 0x3
4998 01:24:32.988130 BL = 0x2
4999 01:24:32.988207 RPST = 0x0
5000 01:24:32.991365 RD_PRE = 0x0
5001 01:24:32.991475 WR_PRE = 0x1
5002 01:24:32.994926 WR_PST = 0x0
5003 01:24:32.995000 DBI_WR = 0x0
5004 01:24:32.998334 DBI_RD = 0x0
5005 01:24:32.998439 OTF = 0x1
5006 01:24:33.001106 ===================================
5007 01:24:33.004750 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 01:24:33.011458 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 01:24:33.014889 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 01:24:33.017822 ===================================
5011 01:24:33.021412 LPDDR4 DRAM CONFIGURATION
5012 01:24:33.024728 ===================================
5013 01:24:33.024814 EX_ROW_EN[0] = 0x10
5014 01:24:33.028218 EX_ROW_EN[1] = 0x0
5015 01:24:33.028303 LP4Y_EN = 0x0
5016 01:24:33.031725 WORK_FSP = 0x0
5017 01:24:33.031810 WL = 0x3
5018 01:24:33.034346 RL = 0x3
5019 01:24:33.034430 BL = 0x2
5020 01:24:33.038096 RPST = 0x0
5021 01:24:33.038220 RD_PRE = 0x0
5022 01:24:33.041161 WR_PRE = 0x1
5023 01:24:33.044615 WR_PST = 0x0
5024 01:24:33.044700 DBI_WR = 0x0
5025 01:24:33.048085 DBI_RD = 0x0
5026 01:24:33.048212 OTF = 0x1
5027 01:24:33.051036 ===================================
5028 01:24:33.057756 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 01:24:33.061259 nWR fixed to 30
5030 01:24:33.064550 [ModeRegInit_LP4] CH0 RK0
5031 01:24:33.064636 [ModeRegInit_LP4] CH0 RK1
5032 01:24:33.068321 [ModeRegInit_LP4] CH1 RK0
5033 01:24:33.071228 [ModeRegInit_LP4] CH1 RK1
5034 01:24:33.071313 match AC timing 9
5035 01:24:33.078147 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 01:24:33.081224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 01:24:33.084815 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 01:24:33.091203 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 01:24:33.094486 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 01:24:33.094571 ==
5041 01:24:33.097684 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 01:24:33.101279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 01:24:33.101367 ==
5044 01:24:33.107754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 01:24:33.114690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5046 01:24:33.117629 [CA 0] Center 38 (8~69) winsize 62
5047 01:24:33.121575 [CA 1] Center 38 (8~69) winsize 62
5048 01:24:33.124316 [CA 2] Center 35 (5~65) winsize 61
5049 01:24:33.127809 [CA 3] Center 35 (5~65) winsize 61
5050 01:24:33.130811 [CA 4] Center 34 (4~65) winsize 62
5051 01:24:33.134403 [CA 5] Center 34 (4~64) winsize 61
5052 01:24:33.134489
5053 01:24:33.137649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5054 01:24:33.137734
5055 01:24:33.141097 [CATrainingPosCal] consider 1 rank data
5056 01:24:33.144639 u2DelayCellTimex100 = 270/100 ps
5057 01:24:33.147539 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5058 01:24:33.150777 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5059 01:24:33.154242 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5060 01:24:33.157374 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5061 01:24:33.161028 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5062 01:24:33.167293 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5063 01:24:33.167407
5064 01:24:33.170587 CA PerBit enable=1, Macro0, CA PI delay=34
5065 01:24:33.170686
5066 01:24:33.174189 [CBTSetCACLKResult] CA Dly = 34
5067 01:24:33.174280 CS Dly: 7 (0~38)
5068 01:24:33.174345 ==
5069 01:24:33.177605 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 01:24:33.181335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 01:24:33.183887 ==
5072 01:24:33.187300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 01:24:33.193829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5074 01:24:33.197528 [CA 0] Center 38 (8~69) winsize 62
5075 01:24:33.200908 [CA 1] Center 38 (8~69) winsize 62
5076 01:24:33.203675 [CA 2] Center 35 (5~65) winsize 61
5077 01:24:33.207289 [CA 3] Center 35 (5~65) winsize 61
5078 01:24:33.211021 [CA 4] Center 34 (4~65) winsize 62
5079 01:24:33.213494 [CA 5] Center 33 (3~64) winsize 62
5080 01:24:33.213599
5081 01:24:33.216900 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5082 01:24:33.216985
5083 01:24:33.220212 [CATrainingPosCal] consider 2 rank data
5084 01:24:33.223680 u2DelayCellTimex100 = 270/100 ps
5085 01:24:33.226793 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5086 01:24:33.230297 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5087 01:24:33.233742 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5088 01:24:33.239993 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5089 01:24:33.243684 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5090 01:24:33.246495 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5091 01:24:33.246597
5092 01:24:33.249794 CA PerBit enable=1, Macro0, CA PI delay=34
5093 01:24:33.249870
5094 01:24:33.253355 [CBTSetCACLKResult] CA Dly = 34
5095 01:24:33.253455 CS Dly: 7 (0~39)
5096 01:24:33.253547
5097 01:24:33.256650 ----->DramcWriteLeveling(PI) begin...
5098 01:24:33.259797 ==
5099 01:24:33.259900 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 01:24:33.266271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 01:24:33.266355 ==
5102 01:24:33.269771 Write leveling (Byte 0): 32 => 32
5103 01:24:33.273094 Write leveling (Byte 1): 30 => 30
5104 01:24:33.276316 DramcWriteLeveling(PI) end<-----
5105 01:24:33.276391
5106 01:24:33.276455 ==
5107 01:24:33.279741 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 01:24:33.283078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 01:24:33.283153 ==
5110 01:24:33.286553 [Gating] SW mode calibration
5111 01:24:33.293275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 01:24:33.296746 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 01:24:33.303155 0 14 0 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
5114 01:24:33.306358 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5115 01:24:33.309929 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 01:24:33.316275 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 01:24:33.319921 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 01:24:33.323175 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 01:24:33.329315 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 01:24:33.332675 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5121 01:24:33.336103 0 15 0 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)
5122 01:24:33.343171 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5123 01:24:33.346138 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 01:24:33.349601 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 01:24:33.355991 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 01:24:33.359564 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 01:24:33.362652 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 01:24:33.369209 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5129 01:24:33.372570 1 0 0 | B1->B0 | 2c2c 3c3c | 0 1 | (0 0) (1 1)
5130 01:24:33.376145 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 01:24:33.382431 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 01:24:33.385792 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 01:24:33.389273 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 01:24:33.395628 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 01:24:33.398991 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 01:24:33.402386 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5137 01:24:33.408943 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5138 01:24:33.412056 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 01:24:33.415338 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 01:24:33.422004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 01:24:33.425528 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 01:24:33.429047 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 01:24:33.435467 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 01:24:33.438847 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 01:24:33.442654 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 01:24:33.448990 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 01:24:33.452294 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 01:24:33.455797 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 01:24:33.462256 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 01:24:33.465716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 01:24:33.469090 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 01:24:33.472144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5153 01:24:33.478772 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5154 01:24:33.482172 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5155 01:24:33.485477 Total UI for P1: 0, mck2ui 16
5156 01:24:33.488542 best dqsien dly found for B0: ( 1, 2, 30)
5157 01:24:33.492196 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 01:24:33.495281 Total UI for P1: 0, mck2ui 16
5159 01:24:33.498779 best dqsien dly found for B1: ( 1, 3, 4)
5160 01:24:33.502416 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5161 01:24:33.505222 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5162 01:24:33.505305
5163 01:24:33.511833 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5164 01:24:33.515249 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5165 01:24:33.518549 [Gating] SW calibration Done
5166 01:24:33.518677 ==
5167 01:24:33.522157 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 01:24:33.525476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 01:24:33.525561 ==
5170 01:24:33.525646 RX Vref Scan: 0
5171 01:24:33.525726
5172 01:24:33.528780 RX Vref 0 -> 0, step: 1
5173 01:24:33.528863
5174 01:24:33.531954 RX Delay -80 -> 252, step: 8
5175 01:24:33.535172 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5176 01:24:33.538615 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5177 01:24:33.541996 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5178 01:24:33.548643 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5179 01:24:33.552278 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5180 01:24:33.555313 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5181 01:24:33.558777 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5182 01:24:33.562403 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5183 01:24:33.565178 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5184 01:24:33.572176 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5185 01:24:33.575230 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5186 01:24:33.578940 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5187 01:24:33.581914 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5188 01:24:33.585238 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5189 01:24:33.591868 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5190 01:24:33.594872 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5191 01:24:33.594955 ==
5192 01:24:33.598408 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 01:24:33.601726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 01:24:33.601811 ==
5195 01:24:33.605359 DQS Delay:
5196 01:24:33.605459 DQS0 = 0, DQS1 = 0
5197 01:24:33.605540 DQM Delay:
5198 01:24:33.608198 DQM0 = 95, DQM1 = 83
5199 01:24:33.608326 DQ Delay:
5200 01:24:33.611669 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5201 01:24:33.615106 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5202 01:24:33.618346 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5203 01:24:33.621279 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5204 01:24:33.621362
5205 01:24:33.621443
5206 01:24:33.621533 ==
5207 01:24:33.625170 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 01:24:33.631294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 01:24:33.631435 ==
5210 01:24:33.631550
5211 01:24:33.631627
5212 01:24:33.631701 TX Vref Scan disable
5213 01:24:33.635614 == TX Byte 0 ==
5214 01:24:33.638557 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5215 01:24:33.641881 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5216 01:24:33.645192 == TX Byte 1 ==
5217 01:24:33.648787 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5218 01:24:33.655213 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5219 01:24:33.655341 ==
5220 01:24:33.658340 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 01:24:33.661608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 01:24:33.661756 ==
5223 01:24:33.661861
5224 01:24:33.662004
5225 01:24:33.665015 TX Vref Scan disable
5226 01:24:33.665124 == TX Byte 0 ==
5227 01:24:33.671898 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5228 01:24:33.674888 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5229 01:24:33.675001 == TX Byte 1 ==
5230 01:24:33.681511 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5231 01:24:33.684881 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5232 01:24:33.685008
5233 01:24:33.685109 [DATLAT]
5234 01:24:33.688334 Freq=933, CH0 RK0
5235 01:24:33.688455
5236 01:24:33.688555 DATLAT Default: 0xd
5237 01:24:33.691411 0, 0xFFFF, sum = 0
5238 01:24:33.691512 1, 0xFFFF, sum = 0
5239 01:24:33.694921 2, 0xFFFF, sum = 0
5240 01:24:33.695051 3, 0xFFFF, sum = 0
5241 01:24:33.698142 4, 0xFFFF, sum = 0
5242 01:24:33.701307 5, 0xFFFF, sum = 0
5243 01:24:33.701426 6, 0xFFFF, sum = 0
5244 01:24:33.704800 7, 0xFFFF, sum = 0
5245 01:24:33.704926 8, 0xFFFF, sum = 0
5246 01:24:33.708404 9, 0xFFFF, sum = 0
5247 01:24:33.708571 10, 0x0, sum = 1
5248 01:24:33.711607 11, 0x0, sum = 2
5249 01:24:33.711712 12, 0x0, sum = 3
5250 01:24:33.711812 13, 0x0, sum = 4
5251 01:24:33.714559 best_step = 11
5252 01:24:33.714644
5253 01:24:33.714741 ==
5254 01:24:33.718300 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 01:24:33.721530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 01:24:33.721678 ==
5257 01:24:33.724958 RX Vref Scan: 1
5258 01:24:33.725044
5259 01:24:33.728005 RX Vref 0 -> 0, step: 1
5260 01:24:33.728098
5261 01:24:33.728164 RX Delay -69 -> 252, step: 4
5262 01:24:33.728224
5263 01:24:33.731546 Set Vref, RX VrefLevel [Byte0]: 62
5264 01:24:33.735080 [Byte1]: 53
5265 01:24:33.739368
5266 01:24:33.739482 Final RX Vref Byte 0 = 62 to rank0
5267 01:24:33.742747 Final RX Vref Byte 1 = 53 to rank0
5268 01:24:33.746093 Final RX Vref Byte 0 = 62 to rank1
5269 01:24:33.749487 Final RX Vref Byte 1 = 53 to rank1==
5270 01:24:33.752572 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 01:24:33.759059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 01:24:33.759186 ==
5273 01:24:33.759285 DQS Delay:
5274 01:24:33.759406 DQS0 = 0, DQS1 = 0
5275 01:24:33.762375 DQM Delay:
5276 01:24:33.762477 DQM0 = 95, DQM1 = 83
5277 01:24:33.765526 DQ Delay:
5278 01:24:33.768976 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5279 01:24:33.772479 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5280 01:24:33.775740 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =78
5281 01:24:33.779397 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5282 01:24:33.779498
5283 01:24:33.779562
5284 01:24:33.785695 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5285 01:24:33.789361 CH0 RK0: MR19=505, MR18=1313
5286 01:24:33.795542 CH0_RK0: MR19=0x505, MR18=0x1313, DQSOSC=415, MR23=63, INC=62, DEC=41
5287 01:24:33.795634
5288 01:24:33.799069 ----->DramcWriteLeveling(PI) begin...
5289 01:24:33.799189 ==
5290 01:24:33.802377 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 01:24:33.805309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 01:24:33.805426 ==
5293 01:24:33.808798 Write leveling (Byte 0): 32 => 32
5294 01:24:33.812346 Write leveling (Byte 1): 32 => 32
5295 01:24:33.815298 DramcWriteLeveling(PI) end<-----
5296 01:24:33.815408
5297 01:24:33.815475 ==
5298 01:24:33.818798 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 01:24:33.822170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 01:24:33.822253 ==
5301 01:24:33.825309 [Gating] SW mode calibration
5302 01:24:33.831746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5303 01:24:33.838693 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5304 01:24:33.842181 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5305 01:24:33.848401 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 01:24:33.852297 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 01:24:33.855101 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 01:24:33.862039 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 01:24:33.865134 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 01:24:33.868493 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5311 01:24:33.875157 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (1 1)
5312 01:24:33.878596 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5313 01:24:33.881729 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 01:24:33.888438 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 01:24:33.891984 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 01:24:33.895167 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 01:24:33.901423 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 01:24:33.904720 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 01:24:33.908084 0 15 28 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
5320 01:24:33.914546 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5321 01:24:33.918037 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 01:24:33.921452 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 01:24:33.927781 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 01:24:33.931449 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 01:24:33.934417 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 01:24:33.938257 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 01:24:33.944513 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5328 01:24:33.948182 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5329 01:24:33.950988 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5330 01:24:33.957777 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 01:24:33.961325 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 01:24:33.964822 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 01:24:33.971695 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 01:24:33.974451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 01:24:33.977757 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 01:24:33.984887 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 01:24:33.987380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 01:24:33.991071 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 01:24:33.997864 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 01:24:34.000724 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 01:24:34.004748 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 01:24:34.010853 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5343 01:24:34.014183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5344 01:24:34.017473 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5345 01:24:34.020937 Total UI for P1: 0, mck2ui 16
5346 01:24:34.024256 best dqsien dly found for B0: ( 1, 2, 26)
5347 01:24:34.030855 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 01:24:34.030995 Total UI for P1: 0, mck2ui 16
5349 01:24:34.037430 best dqsien dly found for B1: ( 1, 3, 0)
5350 01:24:34.040729 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5351 01:24:34.043752 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5352 01:24:34.043885
5353 01:24:34.046999 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5354 01:24:34.050346 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5355 01:24:34.053642 [Gating] SW calibration Done
5356 01:24:34.053765 ==
5357 01:24:34.057134 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 01:24:34.060364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 01:24:34.060488 ==
5360 01:24:34.063349 RX Vref Scan: 0
5361 01:24:34.063476
5362 01:24:34.063588 RX Vref 0 -> 0, step: 1
5363 01:24:34.063700
5364 01:24:34.066778 RX Delay -80 -> 252, step: 8
5365 01:24:34.073635 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5366 01:24:34.077083 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5367 01:24:34.080437 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5368 01:24:34.083258 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5369 01:24:34.086557 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5370 01:24:34.090117 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5371 01:24:34.096673 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5372 01:24:34.100152 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5373 01:24:34.103006 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5374 01:24:34.106614 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5375 01:24:34.109930 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5376 01:24:34.116506 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5377 01:24:34.119936 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5378 01:24:34.122883 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5379 01:24:34.126285 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5380 01:24:34.129740 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5381 01:24:34.129826 ==
5382 01:24:34.133040 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 01:24:34.139352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 01:24:34.139534 ==
5385 01:24:34.139643 DQS Delay:
5386 01:24:34.143108 DQS0 = 0, DQS1 = 0
5387 01:24:34.143231 DQM Delay:
5388 01:24:34.143344 DQM0 = 92, DQM1 = 83
5389 01:24:34.146067 DQ Delay:
5390 01:24:34.149703 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =91
5391 01:24:34.153141 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5392 01:24:34.156292 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5393 01:24:34.159483 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =87
5394 01:24:34.159588
5395 01:24:34.159653
5396 01:24:34.159713 ==
5397 01:24:34.162766 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 01:24:34.166100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 01:24:34.166229 ==
5400 01:24:34.166322
5401 01:24:34.166416
5402 01:24:34.169221 TX Vref Scan disable
5403 01:24:34.172568 == TX Byte 0 ==
5404 01:24:34.175722 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5405 01:24:34.179166 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5406 01:24:34.182703 == TX Byte 1 ==
5407 01:24:34.185908 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5408 01:24:34.189370 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5409 01:24:34.189452 ==
5410 01:24:34.192457 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 01:24:34.198787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 01:24:34.198932 ==
5413 01:24:34.199003
5414 01:24:34.199064
5415 01:24:34.199121 TX Vref Scan disable
5416 01:24:34.202738 == TX Byte 0 ==
5417 01:24:34.205944 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5418 01:24:34.209331 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5419 01:24:34.212812 == TX Byte 1 ==
5420 01:24:34.216049 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5421 01:24:34.222752 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5422 01:24:34.222903
5423 01:24:34.223036 [DATLAT]
5424 01:24:34.223158 Freq=933, CH0 RK1
5425 01:24:34.223246
5426 01:24:34.226128 DATLAT Default: 0xb
5427 01:24:34.226217 0, 0xFFFF, sum = 0
5428 01:24:34.229660 1, 0xFFFF, sum = 0
5429 01:24:34.229755 2, 0xFFFF, sum = 0
5430 01:24:34.233088 3, 0xFFFF, sum = 0
5431 01:24:34.233181 4, 0xFFFF, sum = 0
5432 01:24:34.235860 5, 0xFFFF, sum = 0
5433 01:24:34.239606 6, 0xFFFF, sum = 0
5434 01:24:34.239702 7, 0xFFFF, sum = 0
5435 01:24:34.242915 8, 0xFFFF, sum = 0
5436 01:24:34.243004 9, 0xFFFF, sum = 0
5437 01:24:34.245812 10, 0x0, sum = 1
5438 01:24:34.245919 11, 0x0, sum = 2
5439 01:24:34.246016 12, 0x0, sum = 3
5440 01:24:34.249239 13, 0x0, sum = 4
5441 01:24:34.249378 best_step = 11
5442 01:24:34.249515
5443 01:24:34.252495 ==
5444 01:24:34.252597 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 01:24:34.259282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 01:24:34.259461 ==
5447 01:24:34.259570 RX Vref Scan: 0
5448 01:24:34.259681
5449 01:24:34.262610 RX Vref 0 -> 0, step: 1
5450 01:24:34.262733
5451 01:24:34.266175 RX Delay -77 -> 252, step: 4
5452 01:24:34.269474 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5453 01:24:34.275883 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5454 01:24:34.279080 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5455 01:24:34.282150 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5456 01:24:34.285736 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5457 01:24:34.289248 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5458 01:24:34.295882 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5459 01:24:34.298638 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5460 01:24:34.302274 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5461 01:24:34.305558 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5462 01:24:34.308647 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5463 01:24:34.315619 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5464 01:24:34.318426 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5465 01:24:34.321923 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5466 01:24:34.325403 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5467 01:24:34.328940 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5468 01:24:34.329089 ==
5469 01:24:34.332093 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 01:24:34.338347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 01:24:34.338515 ==
5472 01:24:34.338633 DQS Delay:
5473 01:24:34.341802 DQS0 = 0, DQS1 = 0
5474 01:24:34.341933 DQM Delay:
5475 01:24:34.342044 DQM0 = 93, DQM1 = 84
5476 01:24:34.345308 DQ Delay:
5477 01:24:34.348861 DQ0 =90, DQ1 =96, DQ2 =90, DQ3 =88
5478 01:24:34.351794 DQ4 =92, DQ5 =82, DQ6 =104, DQ7 =104
5479 01:24:34.355547 DQ8 =78, DQ9 =68, DQ10 =86, DQ11 =80
5480 01:24:34.358445 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5481 01:24:34.358564
5482 01:24:34.358679
5483 01:24:34.364939 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5484 01:24:34.368346 CH0 RK1: MR19=505, MR18=2D0E
5485 01:24:34.374955 CH0_RK1: MR19=0x505, MR18=0x2D0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5486 01:24:34.378146 [RxdqsGatingPostProcess] freq 933
5487 01:24:34.381716 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5488 01:24:34.384679 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 01:24:34.388310 best DQS1 dly(2T, 0.5T) = (0, 11)
5490 01:24:34.391394 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 01:24:34.394996 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5492 01:24:34.398739 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 01:24:34.401309 best DQS1 dly(2T, 0.5T) = (0, 11)
5494 01:24:34.404600 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 01:24:34.407954 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5496 01:24:34.411608 Pre-setting of DQS Precalculation
5497 01:24:34.414799 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5498 01:24:34.418231 ==
5499 01:24:34.421520 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 01:24:34.424590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 01:24:34.424737 ==
5502 01:24:34.427886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 01:24:34.434827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5504 01:24:34.438275 [CA 0] Center 37 (7~67) winsize 61
5505 01:24:34.441784 [CA 1] Center 37 (7~67) winsize 61
5506 01:24:34.444695 [CA 2] Center 34 (5~64) winsize 60
5507 01:24:34.448172 [CA 3] Center 34 (4~64) winsize 61
5508 01:24:34.451629 [CA 4] Center 34 (5~64) winsize 60
5509 01:24:34.454827 [CA 5] Center 33 (4~63) winsize 60
5510 01:24:34.454965
5511 01:24:34.457881 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5512 01:24:34.458006
5513 01:24:34.461422 [CATrainingPosCal] consider 1 rank data
5514 01:24:34.465040 u2DelayCellTimex100 = 270/100 ps
5515 01:24:34.468094 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5516 01:24:34.474546 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5517 01:24:34.477662 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5518 01:24:34.481371 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 01:24:34.484358 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5520 01:24:34.488009 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5521 01:24:34.488133
5522 01:24:34.491751 CA PerBit enable=1, Macro0, CA PI delay=33
5523 01:24:34.491886
5524 01:24:34.494561 [CBTSetCACLKResult] CA Dly = 33
5525 01:24:34.494693 CS Dly: 5 (0~36)
5526 01:24:34.497747 ==
5527 01:24:34.501276 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 01:24:34.504585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 01:24:34.504700 ==
5530 01:24:34.507642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 01:24:34.514448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 01:24:34.518181 [CA 0] Center 37 (7~67) winsize 61
5533 01:24:34.521239 [CA 1] Center 37 (7~68) winsize 62
5534 01:24:34.524735 [CA 2] Center 35 (5~65) winsize 61
5535 01:24:34.528046 [CA 3] Center 34 (4~64) winsize 61
5536 01:24:34.531635 [CA 4] Center 35 (5~65) winsize 61
5537 01:24:34.534629 [CA 5] Center 34 (4~64) winsize 61
5538 01:24:34.534751
5539 01:24:34.538009 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 01:24:34.538132
5541 01:24:34.541280 [CATrainingPosCal] consider 2 rank data
5542 01:24:34.544832 u2DelayCellTimex100 = 270/100 ps
5543 01:24:34.548164 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5544 01:24:34.554783 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5545 01:24:34.558085 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5546 01:24:34.561110 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 01:24:34.564629 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5548 01:24:34.567746 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5549 01:24:34.567877
5550 01:24:34.570810 CA PerBit enable=1, Macro0, CA PI delay=33
5551 01:24:34.570936
5552 01:24:34.574515 [CBTSetCACLKResult] CA Dly = 33
5553 01:24:34.577896 CS Dly: 6 (0~39)
5554 01:24:34.578032
5555 01:24:34.581355 ----->DramcWriteLeveling(PI) begin...
5556 01:24:34.581476 ==
5557 01:24:34.584604 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 01:24:34.587414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 01:24:34.587541 ==
5560 01:24:34.591084 Write leveling (Byte 0): 28 => 28
5561 01:24:34.594110 Write leveling (Byte 1): 29 => 29
5562 01:24:34.597510 DramcWriteLeveling(PI) end<-----
5563 01:24:34.597641
5564 01:24:34.597760 ==
5565 01:24:34.600933 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 01:24:34.604097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 01:24:34.604217 ==
5568 01:24:34.607495 [Gating] SW mode calibration
5569 01:24:34.614182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5570 01:24:34.621058 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5571 01:24:34.623676 0 14 0 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
5572 01:24:34.627077 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 01:24:34.633685 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 01:24:34.636995 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 01:24:34.640854 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 01:24:34.647547 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 01:24:34.650334 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 01:24:34.653798 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 0)
5579 01:24:34.660204 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
5580 01:24:34.663837 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 01:24:34.666998 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 01:24:34.674299 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 01:24:34.677395 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 01:24:34.680456 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 01:24:34.687089 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 01:24:34.690330 0 15 28 | B1->B0 | 3939 3232 | 1 0 | (0 0) (0 0)
5587 01:24:34.693240 1 0 0 | B1->B0 | 4545 4141 | 0 1 | (0 0) (0 0)
5588 01:24:34.699975 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 01:24:34.703426 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 01:24:34.706883 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 01:24:34.713422 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 01:24:34.716692 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 01:24:34.720265 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 01:24:34.726660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5595 01:24:34.730006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5596 01:24:34.733530 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 01:24:34.740009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 01:24:34.743623 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 01:24:34.746717 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 01:24:34.750180 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 01:24:34.757047 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 01:24:34.760302 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 01:24:34.763255 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 01:24:34.770282 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 01:24:34.773246 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 01:24:34.776632 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 01:24:34.783495 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 01:24:34.786444 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 01:24:34.789849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5610 01:24:34.796087 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 01:24:34.799562 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5612 01:24:34.803015 Total UI for P1: 0, mck2ui 16
5613 01:24:34.806081 best dqsien dly found for B0: ( 1, 2, 30)
5614 01:24:34.809245 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 01:24:34.812778 Total UI for P1: 0, mck2ui 16
5616 01:24:34.816073 best dqsien dly found for B1: ( 1, 3, 0)
5617 01:24:34.819558 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5618 01:24:34.822527 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5619 01:24:34.822610
5620 01:24:34.829971 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5621 01:24:34.832880 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5622 01:24:34.835809 [Gating] SW calibration Done
5623 01:24:34.835890 ==
5624 01:24:34.839288 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 01:24:34.842600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 01:24:34.842679 ==
5627 01:24:34.842742 RX Vref Scan: 0
5628 01:24:34.842801
5629 01:24:34.846051 RX Vref 0 -> 0, step: 1
5630 01:24:34.846123
5631 01:24:34.849003 RX Delay -80 -> 252, step: 8
5632 01:24:34.852372 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5633 01:24:34.855978 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5634 01:24:34.862447 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5635 01:24:34.865644 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5636 01:24:34.868994 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5637 01:24:34.872320 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5638 01:24:34.875229 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5639 01:24:34.878598 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5640 01:24:34.885781 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5641 01:24:34.889168 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5642 01:24:34.891959 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5643 01:24:34.895167 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5644 01:24:34.898393 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5645 01:24:34.905321 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5646 01:24:34.908939 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5647 01:24:34.912004 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5648 01:24:34.912088 ==
5649 01:24:34.915077 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 01:24:34.918497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 01:24:34.918579 ==
5652 01:24:34.922365 DQS Delay:
5653 01:24:34.922447 DQS0 = 0, DQS1 = 0
5654 01:24:34.925424 DQM Delay:
5655 01:24:34.925506 DQM0 = 94, DQM1 = 87
5656 01:24:34.925600 DQ Delay:
5657 01:24:34.928692 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5658 01:24:34.931548 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5659 01:24:34.935143 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5660 01:24:34.938404 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5661 01:24:34.938488
5662 01:24:34.938551
5663 01:24:34.941507 ==
5664 01:24:34.945028 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 01:24:34.948183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 01:24:34.948266 ==
5667 01:24:34.948331
5668 01:24:34.948390
5669 01:24:34.951713 TX Vref Scan disable
5670 01:24:34.951795 == TX Byte 0 ==
5671 01:24:34.958413 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5672 01:24:34.961686 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5673 01:24:34.961795 == TX Byte 1 ==
5674 01:24:34.968109 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5675 01:24:34.971516 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5676 01:24:34.971599 ==
5677 01:24:34.974790 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 01:24:34.978134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 01:24:34.978227 ==
5680 01:24:34.978299
5681 01:24:34.978360
5682 01:24:34.981561 TX Vref Scan disable
5683 01:24:34.985001 == TX Byte 0 ==
5684 01:24:34.987659 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5685 01:24:34.991012 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5686 01:24:34.994407 == TX Byte 1 ==
5687 01:24:34.997833 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5688 01:24:35.000882 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5689 01:24:35.000960
5690 01:24:35.004615 [DATLAT]
5691 01:24:35.004696 Freq=933, CH1 RK0
5692 01:24:35.004761
5693 01:24:35.007565 DATLAT Default: 0xd
5694 01:24:35.007646 0, 0xFFFF, sum = 0
5695 01:24:35.011072 1, 0xFFFF, sum = 0
5696 01:24:35.011156 2, 0xFFFF, sum = 0
5697 01:24:35.014203 3, 0xFFFF, sum = 0
5698 01:24:35.014287 4, 0xFFFF, sum = 0
5699 01:24:35.017680 5, 0xFFFF, sum = 0
5700 01:24:35.017764 6, 0xFFFF, sum = 0
5701 01:24:35.020724 7, 0xFFFF, sum = 0
5702 01:24:35.020808 8, 0xFFFF, sum = 0
5703 01:24:35.024347 9, 0xFFFF, sum = 0
5704 01:24:35.024431 10, 0x0, sum = 1
5705 01:24:35.027578 11, 0x0, sum = 2
5706 01:24:35.027681 12, 0x0, sum = 3
5707 01:24:35.030924 13, 0x0, sum = 4
5708 01:24:35.031007 best_step = 11
5709 01:24:35.031103
5710 01:24:35.031196 ==
5711 01:24:35.034412 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 01:24:35.040599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 01:24:35.040723 ==
5714 01:24:35.040806 RX Vref Scan: 1
5715 01:24:35.040866
5716 01:24:35.044043 RX Vref 0 -> 0, step: 1
5717 01:24:35.044134
5718 01:24:35.047361 RX Delay -61 -> 252, step: 4
5719 01:24:35.047485
5720 01:24:35.050577 Set Vref, RX VrefLevel [Byte0]: 55
5721 01:24:35.054189 [Byte1]: 52
5722 01:24:35.054279
5723 01:24:35.057111 Final RX Vref Byte 0 = 55 to rank0
5724 01:24:35.060431 Final RX Vref Byte 1 = 52 to rank0
5725 01:24:35.064078 Final RX Vref Byte 0 = 55 to rank1
5726 01:24:35.067277 Final RX Vref Byte 1 = 52 to rank1==
5727 01:24:35.071018 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 01:24:35.073897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 01:24:35.073987 ==
5730 01:24:35.076921 DQS Delay:
5731 01:24:35.077007 DQS0 = 0, DQS1 = 0
5732 01:24:35.080374 DQM Delay:
5733 01:24:35.080465 DQM0 = 95, DQM1 = 88
5734 01:24:35.080532 DQ Delay:
5735 01:24:35.083913 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
5736 01:24:35.087257 DQ4 =92, DQ5 =106, DQ6 =108, DQ7 =92
5737 01:24:35.090201 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =84
5738 01:24:35.093959 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =94
5739 01:24:35.094053
5740 01:24:35.094120
5741 01:24:35.103788 [DQSOSCAuto] RK0, (LSB)MR18= 0x10a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5742 01:24:35.107392 CH1 RK0: MR19=505, MR18=10A
5743 01:24:35.110081 CH1_RK0: MR19=0x505, MR18=0x10A, DQSOSC=418, MR23=63, INC=62, DEC=41
5744 01:24:35.113331
5745 01:24:35.116993 ----->DramcWriteLeveling(PI) begin...
5746 01:24:35.117079 ==
5747 01:24:35.120236 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 01:24:35.123591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 01:24:35.123670 ==
5750 01:24:35.126534 Write leveling (Byte 0): 23 => 23
5751 01:24:35.129957 Write leveling (Byte 1): 29 => 29
5752 01:24:35.133311 DramcWriteLeveling(PI) end<-----
5753 01:24:35.133384
5754 01:24:35.133447 ==
5755 01:24:35.136799 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 01:24:35.139828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 01:24:35.139910 ==
5758 01:24:35.143143 [Gating] SW mode calibration
5759 01:24:35.150113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5760 01:24:35.156201 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5761 01:24:35.159550 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 01:24:35.162902 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 01:24:35.170062 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 01:24:35.173473 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 01:24:35.176433 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 01:24:35.183331 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5767 01:24:35.186041 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5768 01:24:35.189594 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5769 01:24:35.195949 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 01:24:35.199549 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 01:24:35.202744 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 01:24:35.209422 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 01:24:35.212577 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 01:24:35.215996 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 01:24:35.222398 0 15 24 | B1->B0 | 2a2a 3535 | 1 1 | (0 0) (0 0)
5776 01:24:35.225618 0 15 28 | B1->B0 | 3c3c 4545 | 1 0 | (0 0) (0 0)
5777 01:24:35.229104 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 01:24:35.235983 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 01:24:35.239249 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 01:24:35.242613 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 01:24:35.249369 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 01:24:35.252191 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 01:24:35.255517 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5784 01:24:35.262684 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5785 01:24:35.265461 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 01:24:35.269014 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 01:24:35.275654 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 01:24:35.279014 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 01:24:35.282028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 01:24:35.285516 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 01:24:35.292611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 01:24:35.295595 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 01:24:35.299110 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 01:24:35.305502 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 01:24:35.308540 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 01:24:35.312290 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 01:24:35.318525 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 01:24:35.322115 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 01:24:35.325265 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 01:24:35.332052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 01:24:35.335461 Total UI for P1: 0, mck2ui 16
5802 01:24:35.338505 best dqsien dly found for B0: ( 1, 2, 26)
5803 01:24:35.338613 Total UI for P1: 0, mck2ui 16
5804 01:24:35.345412 best dqsien dly found for B1: ( 1, 2, 26)
5805 01:24:35.348448 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5806 01:24:35.351869 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5807 01:24:35.351975
5808 01:24:35.355270 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5809 01:24:35.358540 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5810 01:24:35.362411 [Gating] SW calibration Done
5811 01:24:35.362504 ==
5812 01:24:35.365159 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 01:24:35.368490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 01:24:35.368565 ==
5815 01:24:35.371781 RX Vref Scan: 0
5816 01:24:35.371861
5817 01:24:35.371930 RX Vref 0 -> 0, step: 1
5818 01:24:35.372024
5819 01:24:35.375257 RX Delay -80 -> 252, step: 8
5820 01:24:35.378819 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5821 01:24:35.385038 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5822 01:24:35.388795 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5823 01:24:35.391828 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5824 01:24:35.394978 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5825 01:24:35.398352 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5826 01:24:35.404914 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5827 01:24:35.408318 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5828 01:24:35.411888 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5829 01:24:35.414811 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5830 01:24:35.418221 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5831 01:24:35.425104 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5832 01:24:35.428385 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5833 01:24:35.431546 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5834 01:24:35.435007 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5835 01:24:35.438166 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5836 01:24:35.438253 ==
5837 01:24:35.441443 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 01:24:35.448085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 01:24:35.448169 ==
5840 01:24:35.448233 DQS Delay:
5841 01:24:35.448292 DQS0 = 0, DQS1 = 0
5842 01:24:35.451183 DQM Delay:
5843 01:24:35.451281 DQM0 = 95, DQM1 = 88
5844 01:24:35.454830 DQ Delay:
5845 01:24:35.458200 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5846 01:24:35.461361 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5847 01:24:35.464809 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5848 01:24:35.468182 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5849 01:24:35.468275
5850 01:24:35.468341
5851 01:24:35.468437 ==
5852 01:24:35.471227 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 01:24:35.474601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 01:24:35.474677 ==
5855 01:24:35.474740
5856 01:24:35.474799
5857 01:24:35.477995 TX Vref Scan disable
5858 01:24:35.478094 == TX Byte 0 ==
5859 01:24:35.484429 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5860 01:24:35.488025 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5861 01:24:35.488113 == TX Byte 1 ==
5862 01:24:35.494715 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5863 01:24:35.497976 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5864 01:24:35.498082 ==
5865 01:24:35.501296 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 01:24:35.504385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 01:24:35.504463 ==
5868 01:24:35.507877
5869 01:24:35.507959
5870 01:24:35.508024 TX Vref Scan disable
5871 01:24:35.510828 == TX Byte 0 ==
5872 01:24:35.514149 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5873 01:24:35.521185 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5874 01:24:35.521281 == TX Byte 1 ==
5875 01:24:35.524263 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5876 01:24:35.530730 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5877 01:24:35.530913
5878 01:24:35.531012 [DATLAT]
5879 01:24:35.531104 Freq=933, CH1 RK1
5880 01:24:35.531215
5881 01:24:35.534371 DATLAT Default: 0xb
5882 01:24:35.534476 0, 0xFFFF, sum = 0
5883 01:24:35.537697 1, 0xFFFF, sum = 0
5884 01:24:35.537805 2, 0xFFFF, sum = 0
5885 01:24:35.541429 3, 0xFFFF, sum = 0
5886 01:24:35.544120 4, 0xFFFF, sum = 0
5887 01:24:35.544226 5, 0xFFFF, sum = 0
5888 01:24:35.547519 6, 0xFFFF, sum = 0
5889 01:24:35.547621 7, 0xFFFF, sum = 0
5890 01:24:35.550957 8, 0xFFFF, sum = 0
5891 01:24:35.551068 9, 0xFFFF, sum = 0
5892 01:24:35.554764 10, 0x0, sum = 1
5893 01:24:35.554854 11, 0x0, sum = 2
5894 01:24:35.557649 12, 0x0, sum = 3
5895 01:24:35.557761 13, 0x0, sum = 4
5896 01:24:35.557855 best_step = 11
5897 01:24:35.557943
5898 01:24:35.560698 ==
5899 01:24:35.563936 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 01:24:35.567259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 01:24:35.567376 ==
5902 01:24:35.567516 RX Vref Scan: 0
5903 01:24:35.567607
5904 01:24:35.570567 RX Vref 0 -> 0, step: 1
5905 01:24:35.570661
5906 01:24:35.574130 RX Delay -61 -> 252, step: 4
5907 01:24:35.577150 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5908 01:24:35.584015 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5909 01:24:35.587148 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5910 01:24:35.590299 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5911 01:24:35.593740 iDelay=203, Bit 4, Center 92 (-5 ~ 190) 196
5912 01:24:35.597286 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5913 01:24:35.600336 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5914 01:24:35.607163 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5915 01:24:35.610372 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5916 01:24:35.613976 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5917 01:24:35.617658 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5918 01:24:35.620510 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5919 01:24:35.627163 iDelay=203, Bit 12, Center 94 (-1 ~ 190) 192
5920 01:24:35.630527 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5921 01:24:35.634031 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5922 01:24:35.637156 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5923 01:24:35.637255 ==
5924 01:24:35.640759 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 01:24:35.647269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 01:24:35.647394 ==
5927 01:24:35.647510 DQS Delay:
5928 01:24:35.647599 DQS0 = 0, DQS1 = 0
5929 01:24:35.650448 DQM Delay:
5930 01:24:35.650549 DQM0 = 93, DQM1 = 88
5931 01:24:35.653532 DQ Delay:
5932 01:24:35.656755 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =90
5933 01:24:35.660245 DQ4 =92, DQ5 =102, DQ6 =104, DQ7 =90
5934 01:24:35.663761 DQ8 =78, DQ9 =80, DQ10 =90, DQ11 =82
5935 01:24:35.666751 DQ12 =94, DQ13 =94, DQ14 =94, DQ15 =94
5936 01:24:35.666859
5937 01:24:35.666953
5938 01:24:35.673430 [DQSOSCAuto] RK1, (LSB)MR18= 0x1023, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5939 01:24:35.677097 CH1 RK1: MR19=505, MR18=1023
5940 01:24:35.683525 CH1_RK1: MR19=0x505, MR18=0x1023, DQSOSC=410, MR23=63, INC=64, DEC=42
5941 01:24:35.687321 [RxdqsGatingPostProcess] freq 933
5942 01:24:35.690187 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 01:24:35.693361 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 01:24:35.697192 best DQS1 dly(2T, 0.5T) = (0, 11)
5945 01:24:35.700105 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 01:24:35.703541 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5947 01:24:35.706639 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 01:24:35.710180 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 01:24:35.713178 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 01:24:35.717167 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 01:24:35.719911 Pre-setting of DQS Precalculation
5952 01:24:35.723159 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 01:24:35.733407 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 01:24:35.740197 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 01:24:35.740305
5956 01:24:35.740409
5957 01:24:35.742975 [Calibration Summary] 1866 Mbps
5958 01:24:35.743084 CH 0, Rank 0
5959 01:24:35.746505 SW Impedance : PASS
5960 01:24:35.746607 DUTY Scan : NO K
5961 01:24:35.750177 ZQ Calibration : PASS
5962 01:24:35.753467 Jitter Meter : NO K
5963 01:24:35.753569 CBT Training : PASS
5964 01:24:35.756607 Write leveling : PASS
5965 01:24:35.759821 RX DQS gating : PASS
5966 01:24:35.759898 RX DQ/DQS(RDDQC) : PASS
5967 01:24:35.763260 TX DQ/DQS : PASS
5968 01:24:35.763364 RX DATLAT : PASS
5969 01:24:35.766333 RX DQ/DQS(Engine): PASS
5970 01:24:35.770199 TX OE : NO K
5971 01:24:35.770276 All Pass.
5972 01:24:35.770340
5973 01:24:35.770404 CH 0, Rank 1
5974 01:24:35.773170 SW Impedance : PASS
5975 01:24:35.776594 DUTY Scan : NO K
5976 01:24:35.776707 ZQ Calibration : PASS
5977 01:24:35.779625 Jitter Meter : NO K
5978 01:24:35.783067 CBT Training : PASS
5979 01:24:35.783169 Write leveling : PASS
5980 01:24:35.786391 RX DQS gating : PASS
5981 01:24:35.789860 RX DQ/DQS(RDDQC) : PASS
5982 01:24:35.789963 TX DQ/DQS : PASS
5983 01:24:35.793419 RX DATLAT : PASS
5984 01:24:35.796623 RX DQ/DQS(Engine): PASS
5985 01:24:35.796702 TX OE : NO K
5986 01:24:35.799671 All Pass.
5987 01:24:35.799761
5988 01:24:35.799855 CH 1, Rank 0
5989 01:24:35.803163 SW Impedance : PASS
5990 01:24:35.803264 DUTY Scan : NO K
5991 01:24:35.806575 ZQ Calibration : PASS
5992 01:24:35.809457 Jitter Meter : NO K
5993 01:24:35.809569 CBT Training : PASS
5994 01:24:35.812963 Write leveling : PASS
5995 01:24:35.816134 RX DQS gating : PASS
5996 01:24:35.816235 RX DQ/DQS(RDDQC) : PASS
5997 01:24:35.819709 TX DQ/DQS : PASS
5998 01:24:35.819812 RX DATLAT : PASS
5999 01:24:35.822975 RX DQ/DQS(Engine): PASS
6000 01:24:35.826169 TX OE : NO K
6001 01:24:35.826277 All Pass.
6002 01:24:35.826400
6003 01:24:35.826480 CH 1, Rank 1
6004 01:24:35.829613 SW Impedance : PASS
6005 01:24:35.833175 DUTY Scan : NO K
6006 01:24:35.833256 ZQ Calibration : PASS
6007 01:24:35.835926 Jitter Meter : NO K
6008 01:24:35.839354 CBT Training : PASS
6009 01:24:35.839484 Write leveling : PASS
6010 01:24:35.842699 RX DQS gating : PASS
6011 01:24:35.845986 RX DQ/DQS(RDDQC) : PASS
6012 01:24:35.846069 TX DQ/DQS : PASS
6013 01:24:35.849277 RX DATLAT : PASS
6014 01:24:35.852531 RX DQ/DQS(Engine): PASS
6015 01:24:35.852630 TX OE : NO K
6016 01:24:35.855887 All Pass.
6017 01:24:35.855965
6018 01:24:35.856028 DramC Write-DBI off
6019 01:24:35.859046 PER_BANK_REFRESH: Hybrid Mode
6020 01:24:35.859146 TX_TRACKING: ON
6021 01:24:35.869433 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 01:24:35.872406 [FAST_K] Save calibration result to emmc
6023 01:24:35.875978 dramc_set_vcore_voltage set vcore to 650000
6024 01:24:35.879055 Read voltage for 400, 6
6025 01:24:35.879156 Vio18 = 0
6026 01:24:35.882210 Vcore = 650000
6027 01:24:35.882283 Vdram = 0
6028 01:24:35.882349 Vddq = 0
6029 01:24:35.885669 Vmddr = 0
6030 01:24:35.889314 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 01:24:35.895527 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 01:24:35.895606 MEM_TYPE=3, freq_sel=20
6033 01:24:35.899095 sv_algorithm_assistance_LP4_800
6034 01:24:35.902511 ============ PULL DRAM RESETB DOWN ============
6035 01:24:35.909609 ========== PULL DRAM RESETB DOWN end =========
6036 01:24:35.912236 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 01:24:35.915737 ===================================
6038 01:24:35.918957 LPDDR4 DRAM CONFIGURATION
6039 01:24:35.922311 ===================================
6040 01:24:35.922396 EX_ROW_EN[0] = 0x0
6041 01:24:35.925664 EX_ROW_EN[1] = 0x0
6042 01:24:35.929082 LP4Y_EN = 0x0
6043 01:24:35.929167 WORK_FSP = 0x0
6044 01:24:35.932243 WL = 0x2
6045 01:24:35.932348 RL = 0x2
6046 01:24:35.935752 BL = 0x2
6047 01:24:35.935836 RPST = 0x0
6048 01:24:35.938755 RD_PRE = 0x0
6049 01:24:35.938839 WR_PRE = 0x1
6050 01:24:35.942171 WR_PST = 0x0
6051 01:24:35.942256 DBI_WR = 0x0
6052 01:24:35.945550 DBI_RD = 0x0
6053 01:24:35.945634 OTF = 0x1
6054 01:24:35.948934 ===================================
6055 01:24:35.951922 ===================================
6056 01:24:35.955405 ANA top config
6057 01:24:35.958473 ===================================
6058 01:24:35.958558 DLL_ASYNC_EN = 0
6059 01:24:35.961826 ALL_SLAVE_EN = 1
6060 01:24:35.965019 NEW_RANK_MODE = 1
6061 01:24:35.968346 DLL_IDLE_MODE = 1
6062 01:24:35.971692 LP45_APHY_COMB_EN = 1
6063 01:24:35.971776 TX_ODT_DIS = 1
6064 01:24:35.975181 NEW_8X_MODE = 1
6065 01:24:35.978535 ===================================
6066 01:24:35.981729 ===================================
6067 01:24:35.985522 data_rate = 800
6068 01:24:35.988057 CKR = 1
6069 01:24:35.991583 DQ_P2S_RATIO = 4
6070 01:24:35.994792 ===================================
6071 01:24:35.998683 CA_P2S_RATIO = 4
6072 01:24:35.998767 DQ_CA_OPEN = 0
6073 01:24:36.001329 DQ_SEMI_OPEN = 1
6074 01:24:36.004507 CA_SEMI_OPEN = 1
6075 01:24:36.008313 CA_FULL_RATE = 0
6076 01:24:36.011361 DQ_CKDIV4_EN = 0
6077 01:24:36.014789 CA_CKDIV4_EN = 1
6078 01:24:36.014873 CA_PREDIV_EN = 0
6079 01:24:36.018137 PH8_DLY = 0
6080 01:24:36.021127 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 01:24:36.024512 DQ_AAMCK_DIV = 0
6082 01:24:36.027725 CA_AAMCK_DIV = 0
6083 01:24:36.031334 CA_ADMCK_DIV = 4
6084 01:24:36.031429 DQ_TRACK_CA_EN = 0
6085 01:24:36.034880 CA_PICK = 800
6086 01:24:36.037706 CA_MCKIO = 400
6087 01:24:36.041400 MCKIO_SEMI = 400
6088 01:24:36.044809 PLL_FREQ = 3016
6089 01:24:36.047604 DQ_UI_PI_RATIO = 32
6090 01:24:36.051064 CA_UI_PI_RATIO = 32
6091 01:24:36.054722 ===================================
6092 01:24:36.058318 ===================================
6093 01:24:36.058403 memory_type:LPDDR4
6094 01:24:36.061237 GP_NUM : 10
6095 01:24:36.064367 SRAM_EN : 1
6096 01:24:36.064484 MD32_EN : 0
6097 01:24:36.067723 ===================================
6098 01:24:36.070617 [ANA_INIT] >>>>>>>>>>>>>>
6099 01:24:36.074456 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 01:24:36.077468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 01:24:36.080581 ===================================
6102 01:24:36.084156 data_rate = 800,PCW = 0X7400
6103 01:24:36.087306 ===================================
6104 01:24:36.090862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 01:24:36.093989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 01:24:36.107194 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 01:24:36.110294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 01:24:36.114133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 01:24:36.116972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 01:24:36.120664 [ANA_INIT] flow start
6111 01:24:36.123573 [ANA_INIT] PLL >>>>>>>>
6112 01:24:36.123679 [ANA_INIT] PLL <<<<<<<<
6113 01:24:36.127009 [ANA_INIT] MIDPI >>>>>>>>
6114 01:24:36.130287 [ANA_INIT] MIDPI <<<<<<<<
6115 01:24:36.130397 [ANA_INIT] DLL >>>>>>>>
6116 01:24:36.133930 [ANA_INIT] flow end
6117 01:24:36.137177 ============ LP4 DIFF to SE enter ============
6118 01:24:36.140174 ============ LP4 DIFF to SE exit ============
6119 01:24:36.143547 [ANA_INIT] <<<<<<<<<<<<<
6120 01:24:36.146965 [Flow] Enable top DCM control >>>>>
6121 01:24:36.150546 [Flow] Enable top DCM control <<<<<
6122 01:24:36.153524 Enable DLL master slave shuffle
6123 01:24:36.160366 ==============================================================
6124 01:24:36.160473 Gating Mode config
6125 01:24:36.166843 ==============================================================
6126 01:24:36.170407 Config description:
6127 01:24:36.177127 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 01:24:36.183715 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 01:24:36.189755 SELPH_MODE 0: By rank 1: By Phase
6130 01:24:36.196344 ==============================================================
6131 01:24:36.199869 GAT_TRACK_EN = 0
6132 01:24:36.199981 RX_GATING_MODE = 2
6133 01:24:36.202970 RX_GATING_TRACK_MODE = 2
6134 01:24:36.206697 SELPH_MODE = 1
6135 01:24:36.209579 PICG_EARLY_EN = 1
6136 01:24:36.213130 VALID_LAT_VALUE = 1
6137 01:24:36.219602 ==============================================================
6138 01:24:36.223181 Enter into Gating configuration >>>>
6139 01:24:36.226165 Exit from Gating configuration <<<<
6140 01:24:36.229705 Enter into DVFS_PRE_config >>>>>
6141 01:24:36.239332 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 01:24:36.242785 Exit from DVFS_PRE_config <<<<<
6143 01:24:36.246110 Enter into PICG configuration >>>>
6144 01:24:36.249246 Exit from PICG configuration <<<<
6145 01:24:36.252709 [RX_INPUT] configuration >>>>>
6146 01:24:36.256161 [RX_INPUT] configuration <<<<<
6147 01:24:36.259109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 01:24:36.265714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 01:24:36.272419 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 01:24:36.279337 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 01:24:36.282324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 01:24:36.289201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 01:24:36.292458 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 01:24:36.299008 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 01:24:36.302148 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 01:24:36.305617 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 01:24:36.308505 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 01:24:36.315350 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 01:24:36.318908 ===================================
6160 01:24:36.322225 LPDDR4 DRAM CONFIGURATION
6161 01:24:36.325488 ===================================
6162 01:24:36.325592 EX_ROW_EN[0] = 0x0
6163 01:24:36.328558 EX_ROW_EN[1] = 0x0
6164 01:24:36.328665 LP4Y_EN = 0x0
6165 01:24:36.332164 WORK_FSP = 0x0
6166 01:24:36.332271 WL = 0x2
6167 01:24:36.335157 RL = 0x2
6168 01:24:36.335259 BL = 0x2
6169 01:24:36.338440 RPST = 0x0
6170 01:24:36.338546 RD_PRE = 0x0
6171 01:24:36.341754 WR_PRE = 0x1
6172 01:24:36.341859 WR_PST = 0x0
6173 01:24:36.345076 DBI_WR = 0x0
6174 01:24:36.345183 DBI_RD = 0x0
6175 01:24:36.348917 OTF = 0x1
6176 01:24:36.351866 ===================================
6177 01:24:36.354991 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 01:24:36.358266 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 01:24:36.364838 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 01:24:36.368497 ===================================
6181 01:24:36.371624 LPDDR4 DRAM CONFIGURATION
6182 01:24:36.374960 ===================================
6183 01:24:36.375068 EX_ROW_EN[0] = 0x10
6184 01:24:36.378250 EX_ROW_EN[1] = 0x0
6185 01:24:36.378357 LP4Y_EN = 0x0
6186 01:24:36.381715 WORK_FSP = 0x0
6187 01:24:36.381821 WL = 0x2
6188 01:24:36.384482 RL = 0x2
6189 01:24:36.384589 BL = 0x2
6190 01:24:36.388141 RPST = 0x0
6191 01:24:36.388245 RD_PRE = 0x0
6192 01:24:36.391514 WR_PRE = 0x1
6193 01:24:36.391626 WR_PST = 0x0
6194 01:24:36.394427 DBI_WR = 0x0
6195 01:24:36.394534 DBI_RD = 0x0
6196 01:24:36.397613 OTF = 0x1
6197 01:24:36.400850 ===================================
6198 01:24:36.407700 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 01:24:36.411214 nWR fixed to 30
6200 01:24:36.414817 [ModeRegInit_LP4] CH0 RK0
6201 01:24:36.414926 [ModeRegInit_LP4] CH0 RK1
6202 01:24:36.417930 [ModeRegInit_LP4] CH1 RK0
6203 01:24:36.420973 [ModeRegInit_LP4] CH1 RK1
6204 01:24:36.421078 match AC timing 19
6205 01:24:36.427493 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 01:24:36.430927 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 01:24:36.434572 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 01:24:36.440844 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 01:24:36.444343 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 01:24:36.444450 ==
6211 01:24:36.447828 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 01:24:36.451053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 01:24:36.451173 ==
6214 01:24:36.457619 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 01:24:36.464354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6216 01:24:36.467615 [CA 0] Center 36 (8~64) winsize 57
6217 01:24:36.470809 [CA 1] Center 36 (8~64) winsize 57
6218 01:24:36.474341 [CA 2] Center 36 (8~64) winsize 57
6219 01:24:36.477678 [CA 3] Center 36 (8~64) winsize 57
6220 01:24:36.477784 [CA 4] Center 36 (8~64) winsize 57
6221 01:24:36.480668 [CA 5] Center 36 (8~64) winsize 57
6222 01:24:36.480774
6223 01:24:36.487151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6224 01:24:36.487276
6225 01:24:36.491238 [CATrainingPosCal] consider 1 rank data
6226 01:24:36.493929 u2DelayCellTimex100 = 270/100 ps
6227 01:24:36.497301 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 01:24:36.500702 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 01:24:36.504354 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 01:24:36.507064 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 01:24:36.511013 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 01:24:36.513791 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 01:24:36.513890
6234 01:24:36.517440 CA PerBit enable=1, Macro0, CA PI delay=36
6235 01:24:36.517526
6236 01:24:36.520830 [CBTSetCACLKResult] CA Dly = 36
6237 01:24:36.524045 CS Dly: 1 (0~32)
6238 01:24:36.524132 ==
6239 01:24:36.526867 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 01:24:36.530456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 01:24:36.530542 ==
6242 01:24:36.537407 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 01:24:36.543832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 01:24:36.547085 [CA 0] Center 36 (8~64) winsize 57
6245 01:24:36.547170 [CA 1] Center 36 (8~64) winsize 57
6246 01:24:36.550364 [CA 2] Center 36 (8~64) winsize 57
6247 01:24:36.553762 [CA 3] Center 36 (8~64) winsize 57
6248 01:24:36.557447 [CA 4] Center 36 (8~64) winsize 57
6249 01:24:36.560129 [CA 5] Center 36 (8~64) winsize 57
6250 01:24:36.560247
6251 01:24:36.563379 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 01:24:36.563466
6253 01:24:36.566937 [CATrainingPosCal] consider 2 rank data
6254 01:24:36.570035 u2DelayCellTimex100 = 270/100 ps
6255 01:24:36.573508 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 01:24:36.580077 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 01:24:36.583197 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 01:24:36.586609 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 01:24:36.589838 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 01:24:36.593325 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 01:24:36.593433
6262 01:24:36.596520 CA PerBit enable=1, Macro0, CA PI delay=36
6263 01:24:36.596628
6264 01:24:36.599867 [CBTSetCACLKResult] CA Dly = 36
6265 01:24:36.599974 CS Dly: 1 (0~32)
6266 01:24:36.603394
6267 01:24:36.606812 ----->DramcWriteLeveling(PI) begin...
6268 01:24:36.606913 ==
6269 01:24:36.610109 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 01:24:36.613622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 01:24:36.613720 ==
6272 01:24:36.617033 Write leveling (Byte 0): 40 => 8
6273 01:24:36.620130 Write leveling (Byte 1): 40 => 8
6274 01:24:36.623264 DramcWriteLeveling(PI) end<-----
6275 01:24:36.623368
6276 01:24:36.623445 ==
6277 01:24:36.626818 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 01:24:36.629712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 01:24:36.629791 ==
6280 01:24:36.633239 [Gating] SW mode calibration
6281 01:24:36.639696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 01:24:36.646509 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 01:24:36.649958 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 01:24:36.653226 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 01:24:36.656502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 01:24:36.663056 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 01:24:36.666665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 01:24:36.670275 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 01:24:36.676491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 01:24:36.679621 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 01:24:36.683197 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 01:24:36.686288 Total UI for P1: 0, mck2ui 16
6293 01:24:36.689696 best dqsien dly found for B0: ( 0, 14, 24)
6294 01:24:36.692881 Total UI for P1: 0, mck2ui 16
6295 01:24:36.696204 best dqsien dly found for B1: ( 0, 14, 24)
6296 01:24:36.699742 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 01:24:36.705987 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 01:24:36.706070
6299 01:24:36.709262 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 01:24:36.712709 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 01:24:36.716072 [Gating] SW calibration Done
6302 01:24:36.716155 ==
6303 01:24:36.719237 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 01:24:36.722648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 01:24:36.722731 ==
6306 01:24:36.726143 RX Vref Scan: 0
6307 01:24:36.726259
6308 01:24:36.726353 RX Vref 0 -> 0, step: 1
6309 01:24:36.726442
6310 01:24:36.729127 RX Delay -410 -> 252, step: 16
6311 01:24:36.732578 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6312 01:24:36.739667 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6313 01:24:36.742296 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6314 01:24:36.745857 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6315 01:24:36.749111 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6316 01:24:36.756276 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6317 01:24:36.759055 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6318 01:24:36.762616 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6319 01:24:36.766231 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6320 01:24:36.772382 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6321 01:24:36.775548 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6322 01:24:36.779268 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6323 01:24:36.785975 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6324 01:24:36.789173 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6325 01:24:36.792569 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6326 01:24:36.795884 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6327 01:24:36.795980 ==
6328 01:24:36.798850 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 01:24:36.805838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 01:24:36.805949 ==
6331 01:24:36.806054 DQS Delay:
6332 01:24:36.809073 DQS0 = 59, DQS1 = 59
6333 01:24:36.809188 DQM Delay:
6334 01:24:36.812212 DQM0 = 18, DQM1 = 10
6335 01:24:36.812322 DQ Delay:
6336 01:24:36.815541 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6337 01:24:36.818714 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6338 01:24:36.822183 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6339 01:24:36.825185 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6340 01:24:36.825299
6341 01:24:36.825390
6342 01:24:36.825478 ==
6343 01:24:36.828743 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 01:24:36.832198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 01:24:36.832303 ==
6346 01:24:36.832396
6347 01:24:36.832489
6348 01:24:36.835358 TX Vref Scan disable
6349 01:24:36.835458 == TX Byte 0 ==
6350 01:24:36.841997 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 01:24:36.845524 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 01:24:36.845613 == TX Byte 1 ==
6353 01:24:36.852013 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 01:24:36.854906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 01:24:36.855011 ==
6356 01:24:36.858470 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 01:24:36.862010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 01:24:36.862114 ==
6359 01:24:36.862223
6360 01:24:36.862313
6361 01:24:36.865156 TX Vref Scan disable
6362 01:24:36.865258 == TX Byte 0 ==
6363 01:24:36.872063 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 01:24:36.874926 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 01:24:36.875030 == TX Byte 1 ==
6366 01:24:36.881807 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 01:24:36.884807 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 01:24:36.884887
6369 01:24:36.884950 [DATLAT]
6370 01:24:36.888232 Freq=400, CH0 RK0
6371 01:24:36.888333
6372 01:24:36.888424 DATLAT Default: 0xf
6373 01:24:36.891291 0, 0xFFFF, sum = 0
6374 01:24:36.891426 1, 0xFFFF, sum = 0
6375 01:24:36.894517 2, 0xFFFF, sum = 0
6376 01:24:36.894623 3, 0xFFFF, sum = 0
6377 01:24:36.897842 4, 0xFFFF, sum = 0
6378 01:24:36.897947 5, 0xFFFF, sum = 0
6379 01:24:36.901378 6, 0xFFFF, sum = 0
6380 01:24:36.901467 7, 0xFFFF, sum = 0
6381 01:24:36.904530 8, 0xFFFF, sum = 0
6382 01:24:36.904617 9, 0xFFFF, sum = 0
6383 01:24:36.908537 10, 0xFFFF, sum = 0
6384 01:24:36.911587 11, 0xFFFF, sum = 0
6385 01:24:36.911705 12, 0xFFFF, sum = 0
6386 01:24:36.914777 13, 0x0, sum = 1
6387 01:24:36.914881 14, 0x0, sum = 2
6388 01:24:36.918203 15, 0x0, sum = 3
6389 01:24:36.918288 16, 0x0, sum = 4
6390 01:24:36.918398 best_step = 14
6391 01:24:36.918491
6392 01:24:36.921434 ==
6393 01:24:36.924831 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 01:24:36.927835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 01:24:36.927950 ==
6396 01:24:36.928046 RX Vref Scan: 1
6397 01:24:36.928148
6398 01:24:36.931364 RX Vref 0 -> 0, step: 1
6399 01:24:36.931502
6400 01:24:36.934766 RX Delay -359 -> 252, step: 8
6401 01:24:36.934868
6402 01:24:36.937904 Set Vref, RX VrefLevel [Byte0]: 62
6403 01:24:36.941299 [Byte1]: 53
6404 01:24:36.945301
6405 01:24:36.945418 Final RX Vref Byte 0 = 62 to rank0
6406 01:24:36.948252 Final RX Vref Byte 1 = 53 to rank0
6407 01:24:36.951400 Final RX Vref Byte 0 = 62 to rank1
6408 01:24:36.954677 Final RX Vref Byte 1 = 53 to rank1==
6409 01:24:36.958305 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 01:24:36.965269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 01:24:36.965393 ==
6412 01:24:36.965521 DQS Delay:
6413 01:24:36.965618 DQS0 = 60, DQS1 = 68
6414 01:24:36.967997 DQM Delay:
6415 01:24:36.968093 DQM0 = 14, DQM1 = 14
6416 01:24:36.971497 DQ Delay:
6417 01:24:36.975156 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6418 01:24:36.975263 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6419 01:24:36.977964 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6420 01:24:36.981352 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6421 01:24:36.981439
6422 01:24:36.984908
6423 01:24:36.991706 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6424 01:24:36.995204 CH0 RK0: MR19=C0C, MR18=7E7E
6425 01:24:37.001409 CH0_RK0: MR19=0xC0C, MR18=0x7E7E, DQSOSC=393, MR23=63, INC=382, DEC=254
6426 01:24:37.001536 ==
6427 01:24:37.004755 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 01:24:37.007981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 01:24:37.008068 ==
6430 01:24:37.011385 [Gating] SW mode calibration
6431 01:24:37.018517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 01:24:37.022019 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 01:24:37.028078 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 01:24:37.031386 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 01:24:37.034703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 01:24:37.041465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 01:24:37.045237 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 01:24:37.048056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 01:24:37.054425 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 01:24:37.057833 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 01:24:37.061142 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 01:24:37.064658 Total UI for P1: 0, mck2ui 16
6443 01:24:37.068108 best dqsien dly found for B0: ( 0, 14, 24)
6444 01:24:37.071188 Total UI for P1: 0, mck2ui 16
6445 01:24:37.074655 best dqsien dly found for B1: ( 0, 14, 24)
6446 01:24:37.078104 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 01:24:37.084490 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 01:24:37.084573
6449 01:24:37.087507 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 01:24:37.091095 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 01:24:37.094465 [Gating] SW calibration Done
6452 01:24:37.094545 ==
6453 01:24:37.097715 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 01:24:37.101302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 01:24:37.101380 ==
6456 01:24:37.104791 RX Vref Scan: 0
6457 01:24:37.104872
6458 01:24:37.104937 RX Vref 0 -> 0, step: 1
6459 01:24:37.104997
6460 01:24:37.107663 RX Delay -410 -> 252, step: 16
6461 01:24:37.110739 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6462 01:24:37.117828 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6463 01:24:37.120501 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6464 01:24:37.123867 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6465 01:24:37.127858 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6466 01:24:37.134096 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6467 01:24:37.137786 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6468 01:24:37.140964 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6469 01:24:37.143981 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6470 01:24:37.151062 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6471 01:24:37.153943 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6472 01:24:37.157356 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6473 01:24:37.163718 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6474 01:24:37.167055 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6475 01:24:37.170562 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6476 01:24:37.173831 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6477 01:24:37.173915 ==
6478 01:24:37.176727 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 01:24:37.183852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 01:24:37.183936 ==
6481 01:24:37.184050 DQS Delay:
6482 01:24:37.186720 DQS0 = 59, DQS1 = 59
6483 01:24:37.186854 DQM Delay:
6484 01:24:37.190227 DQM0 = 16, DQM1 = 10
6485 01:24:37.190301 DQ Delay:
6486 01:24:37.193602 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6487 01:24:37.197205 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6488 01:24:37.199983 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6489 01:24:37.203688 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6490 01:24:37.203768
6491 01:24:37.203834
6492 01:24:37.203927 ==
6493 01:24:37.206944 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 01:24:37.210098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 01:24:37.210176 ==
6496 01:24:37.210245
6497 01:24:37.210305
6498 01:24:37.213340 TX Vref Scan disable
6499 01:24:37.213434 == TX Byte 0 ==
6500 01:24:37.220118 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6501 01:24:37.223393 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6502 01:24:37.223479 == TX Byte 1 ==
6503 01:24:37.229642 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6504 01:24:37.233177 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6505 01:24:37.233265 ==
6506 01:24:37.236567 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 01:24:37.239915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 01:24:37.240000 ==
6509 01:24:37.240067
6510 01:24:37.240129
6511 01:24:37.243020 TX Vref Scan disable
6512 01:24:37.246645 == TX Byte 0 ==
6513 01:24:37.250022 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6514 01:24:37.252875 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6515 01:24:37.256089 == TX Byte 1 ==
6516 01:24:37.260030 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6517 01:24:37.263221 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6518 01:24:37.263307
6519 01:24:37.263383 [DATLAT]
6520 01:24:37.266212 Freq=400, CH0 RK1
6521 01:24:37.266297
6522 01:24:37.269828 DATLAT Default: 0xe
6523 01:24:37.269913 0, 0xFFFF, sum = 0
6524 01:24:37.272664 1, 0xFFFF, sum = 0
6525 01:24:37.272751 2, 0xFFFF, sum = 0
6526 01:24:37.276562 3, 0xFFFF, sum = 0
6527 01:24:37.276665 4, 0xFFFF, sum = 0
6528 01:24:37.279575 5, 0xFFFF, sum = 0
6529 01:24:37.279662 6, 0xFFFF, sum = 0
6530 01:24:37.282864 7, 0xFFFF, sum = 0
6531 01:24:37.282950 8, 0xFFFF, sum = 0
6532 01:24:37.286283 9, 0xFFFF, sum = 0
6533 01:24:37.286370 10, 0xFFFF, sum = 0
6534 01:24:37.289133 11, 0xFFFF, sum = 0
6535 01:24:37.289220 12, 0xFFFF, sum = 0
6536 01:24:37.292888 13, 0x0, sum = 1
6537 01:24:37.292975 14, 0x0, sum = 2
6538 01:24:37.296047 15, 0x0, sum = 3
6539 01:24:37.296135 16, 0x0, sum = 4
6540 01:24:37.299513 best_step = 14
6541 01:24:37.299600
6542 01:24:37.299667 ==
6543 01:24:37.302582 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 01:24:37.305504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 01:24:37.305589 ==
6546 01:24:37.309085 RX Vref Scan: 0
6547 01:24:37.309243
6548 01:24:37.309370 RX Vref 0 -> 0, step: 1
6549 01:24:37.309434
6550 01:24:37.312294 RX Delay -359 -> 252, step: 8
6551 01:24:37.320658 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6552 01:24:37.323667 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6553 01:24:37.327036 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6554 01:24:37.334018 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6555 01:24:37.337339 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6556 01:24:37.340294 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6557 01:24:37.343849 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6558 01:24:37.350090 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6559 01:24:37.353599 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6560 01:24:37.357095 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6561 01:24:37.360049 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6562 01:24:37.366780 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6563 01:24:37.370183 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6564 01:24:37.373456 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6565 01:24:37.376799 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6566 01:24:37.383362 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6567 01:24:37.383506 ==
6568 01:24:37.386876 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 01:24:37.389948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 01:24:37.390032 ==
6571 01:24:37.390099 DQS Delay:
6572 01:24:37.393494 DQS0 = 60, DQS1 = 72
6573 01:24:37.393580 DQM Delay:
6574 01:24:37.396841 DQM0 = 11, DQM1 = 17
6575 01:24:37.396921 DQ Delay:
6576 01:24:37.399960 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6577 01:24:37.403061 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =20
6578 01:24:37.406733 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6579 01:24:37.409884 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =20
6580 01:24:37.410023
6581 01:24:37.410109
6582 01:24:37.416440 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6583 01:24:37.419518 CH0 RK1: MR19=C0C, MR18=C57A
6584 01:24:37.426520 CH0_RK1: MR19=0xC0C, MR18=0xC57A, DQSOSC=385, MR23=63, INC=398, DEC=265
6585 01:24:37.429751 [RxdqsGatingPostProcess] freq 400
6586 01:24:37.436227 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 01:24:37.439688 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 01:24:37.439822 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 01:24:37.443246 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 01:24:37.446729 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 01:24:37.449505 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 01:24:37.452944 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 01:24:37.456278 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 01:24:37.459932 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 01:24:37.463091 Pre-setting of DQS Precalculation
6596 01:24:37.469828 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 01:24:37.469934 ==
6598 01:24:37.473114 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 01:24:37.475993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 01:24:37.476075 ==
6601 01:24:37.482786 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 01:24:37.485958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6603 01:24:37.489615 [CA 0] Center 36 (8~64) winsize 57
6604 01:24:37.493203 [CA 1] Center 36 (8~64) winsize 57
6605 01:24:37.495984 [CA 2] Center 36 (8~64) winsize 57
6606 01:24:37.499476 [CA 3] Center 36 (8~64) winsize 57
6607 01:24:37.503043 [CA 4] Center 36 (8~64) winsize 57
6608 01:24:37.505988 [CA 5] Center 36 (8~64) winsize 57
6609 01:24:37.506074
6610 01:24:37.509378 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6611 01:24:37.509463
6612 01:24:37.513162 [CATrainingPosCal] consider 1 rank data
6613 01:24:37.516085 u2DelayCellTimex100 = 270/100 ps
6614 01:24:37.519581 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 01:24:37.522545 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 01:24:37.529299 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 01:24:37.532344 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 01:24:37.535840 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 01:24:37.539083 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 01:24:37.539167
6621 01:24:37.542868 CA PerBit enable=1, Macro0, CA PI delay=36
6622 01:24:37.542953
6623 01:24:37.545701 [CBTSetCACLKResult] CA Dly = 36
6624 01:24:37.545806 CS Dly: 1 (0~32)
6625 01:24:37.545874 ==
6626 01:24:37.549027 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 01:24:37.555663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 01:24:37.555756 ==
6629 01:24:37.559136 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 01:24:37.565840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 01:24:37.568762 [CA 0] Center 36 (8~64) winsize 57
6632 01:24:37.572271 [CA 1] Center 36 (8~64) winsize 57
6633 01:24:37.575632 [CA 2] Center 36 (8~64) winsize 57
6634 01:24:37.578700 [CA 3] Center 36 (8~64) winsize 57
6635 01:24:37.581997 [CA 4] Center 36 (8~64) winsize 57
6636 01:24:37.585642 [CA 5] Center 36 (8~64) winsize 57
6637 01:24:37.585756
6638 01:24:37.589139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 01:24:37.589225
6640 01:24:37.592091 [CATrainingPosCal] consider 2 rank data
6641 01:24:37.595302 u2DelayCellTimex100 = 270/100 ps
6642 01:24:37.598835 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 01:24:37.601933 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 01:24:37.605438 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 01:24:37.608262 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 01:24:37.615285 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 01:24:37.618267 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 01:24:37.618391
6649 01:24:37.621761 CA PerBit enable=1, Macro0, CA PI delay=36
6650 01:24:37.621864
6651 01:24:37.625320 [CBTSetCACLKResult] CA Dly = 36
6652 01:24:37.625441 CS Dly: 1 (0~32)
6653 01:24:37.625506
6654 01:24:37.628490 ----->DramcWriteLeveling(PI) begin...
6655 01:24:37.628574 ==
6656 01:24:37.631680 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 01:24:37.638362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 01:24:37.638502 ==
6659 01:24:37.642021 Write leveling (Byte 0): 40 => 8
6660 01:24:37.642118 Write leveling (Byte 1): 40 => 8
6661 01:24:37.645043 DramcWriteLeveling(PI) end<-----
6662 01:24:37.645125
6663 01:24:37.648474 ==
6664 01:24:37.648557 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 01:24:37.654876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 01:24:37.654967 ==
6667 01:24:37.658283 [Gating] SW mode calibration
6668 01:24:37.664695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 01:24:37.668058 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 01:24:37.674577 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 01:24:37.678156 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 01:24:37.681028 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 01:24:37.687839 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 01:24:37.691309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 01:24:37.694992 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 01:24:37.701145 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 01:24:37.704537 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 01:24:37.707943 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 01:24:37.711082 Total UI for P1: 0, mck2ui 16
6680 01:24:37.714745 best dqsien dly found for B0: ( 0, 14, 24)
6681 01:24:37.717615 Total UI for P1: 0, mck2ui 16
6682 01:24:37.721493 best dqsien dly found for B1: ( 0, 14, 24)
6683 01:24:37.724532 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 01:24:37.727667 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 01:24:37.727782
6686 01:24:37.734671 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 01:24:37.737725 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 01:24:37.737833 [Gating] SW calibration Done
6689 01:24:37.740992 ==
6690 01:24:37.744448 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 01:24:37.747357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 01:24:37.747488 ==
6693 01:24:37.747582 RX Vref Scan: 0
6694 01:24:37.747681
6695 01:24:37.751158 RX Vref 0 -> 0, step: 1
6696 01:24:37.751262
6697 01:24:37.754229 RX Delay -410 -> 252, step: 16
6698 01:24:37.757607 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6699 01:24:37.760916 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6700 01:24:37.767270 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6701 01:24:37.771033 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6702 01:24:37.774073 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6703 01:24:37.777189 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6704 01:24:37.783984 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6705 01:24:37.787447 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6706 01:24:37.790498 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6707 01:24:37.797425 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6708 01:24:37.800505 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6709 01:24:37.803713 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6710 01:24:37.807499 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6711 01:24:37.813630 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6712 01:24:37.816883 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6713 01:24:37.820273 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6714 01:24:37.820408 ==
6715 01:24:37.823683 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 01:24:37.827256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 01:24:37.830630 ==
6718 01:24:37.830834 DQS Delay:
6719 01:24:37.830963 DQS0 = 51, DQS1 = 67
6720 01:24:37.833487 DQM Delay:
6721 01:24:37.833622 DQM0 = 12, DQM1 = 18
6722 01:24:37.836731 DQ Delay:
6723 01:24:37.836874 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6724 01:24:37.840186 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6725 01:24:37.843889 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6726 01:24:37.847127 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6727 01:24:37.847265
6728 01:24:37.847399
6729 01:24:37.850295 ==
6730 01:24:37.853415 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 01:24:37.857012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 01:24:37.857131 ==
6733 01:24:37.857226
6734 01:24:37.857319
6735 01:24:37.860151 TX Vref Scan disable
6736 01:24:37.860266 == TX Byte 0 ==
6737 01:24:37.863710 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 01:24:37.869888 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 01:24:37.870030 == TX Byte 1 ==
6740 01:24:37.873243 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 01:24:37.880074 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 01:24:37.880171 ==
6743 01:24:37.883163 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 01:24:37.886676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 01:24:37.886758 ==
6746 01:24:37.886822
6747 01:24:37.886882
6748 01:24:37.890134 TX Vref Scan disable
6749 01:24:37.890238 == TX Byte 0 ==
6750 01:24:37.893194 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 01:24:37.900210 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 01:24:37.900349 == TX Byte 1 ==
6753 01:24:37.903053 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 01:24:37.910225 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 01:24:37.910375
6756 01:24:37.910470 [DATLAT]
6757 01:24:37.910533 Freq=400, CH1 RK0
6758 01:24:37.910593
6759 01:24:37.913007 DATLAT Default: 0xf
6760 01:24:37.916487 0, 0xFFFF, sum = 0
6761 01:24:37.916611 1, 0xFFFF, sum = 0
6762 01:24:37.919936 2, 0xFFFF, sum = 0
6763 01:24:37.920027 3, 0xFFFF, sum = 0
6764 01:24:37.923481 4, 0xFFFF, sum = 0
6765 01:24:37.923587 5, 0xFFFF, sum = 0
6766 01:24:37.926351 6, 0xFFFF, sum = 0
6767 01:24:37.926454 7, 0xFFFF, sum = 0
6768 01:24:37.930026 8, 0xFFFF, sum = 0
6769 01:24:37.930139 9, 0xFFFF, sum = 0
6770 01:24:37.933395 10, 0xFFFF, sum = 0
6771 01:24:37.933506 11, 0xFFFF, sum = 0
6772 01:24:37.936472 12, 0xFFFF, sum = 0
6773 01:24:37.936550 13, 0x0, sum = 1
6774 01:24:37.939714 14, 0x0, sum = 2
6775 01:24:37.939785 15, 0x0, sum = 3
6776 01:24:37.943251 16, 0x0, sum = 4
6777 01:24:37.943347 best_step = 14
6778 01:24:37.943472
6779 01:24:37.943556 ==
6780 01:24:37.947108 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 01:24:37.949879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 01:24:37.953481 ==
6783 01:24:37.953572 RX Vref Scan: 1
6784 01:24:37.953636
6785 01:24:37.956321 RX Vref 0 -> 0, step: 1
6786 01:24:37.956419
6787 01:24:37.959890 RX Delay -375 -> 252, step: 8
6788 01:24:37.959969
6789 01:24:37.963225 Set Vref, RX VrefLevel [Byte0]: 55
6790 01:24:37.963351 [Byte1]: 52
6791 01:24:37.968984
6792 01:24:37.969095 Final RX Vref Byte 0 = 55 to rank0
6793 01:24:37.972356 Final RX Vref Byte 1 = 52 to rank0
6794 01:24:37.975353 Final RX Vref Byte 0 = 55 to rank1
6795 01:24:37.979397 Final RX Vref Byte 1 = 52 to rank1==
6796 01:24:37.982102 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 01:24:37.988989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 01:24:37.989080 ==
6799 01:24:37.989147 DQS Delay:
6800 01:24:37.989208 DQS0 = 56, DQS1 = 64
6801 01:24:37.992335 DQM Delay:
6802 01:24:37.992413 DQM0 = 13, DQM1 = 11
6803 01:24:37.995529 DQ Delay:
6804 01:24:37.998715 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6805 01:24:37.998823 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6806 01:24:38.002599 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6807 01:24:38.005719 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6808 01:24:38.005825
6809 01:24:38.008927
6810 01:24:38.015711 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6811 01:24:38.018749 CH1 RK0: MR19=C0C, MR18=5E71
6812 01:24:38.025564 CH1_RK0: MR19=0xC0C, MR18=0x5E71, DQSOSC=395, MR23=63, INC=378, DEC=252
6813 01:24:38.025692 ==
6814 01:24:38.028619 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 01:24:38.032200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 01:24:38.032305 ==
6817 01:24:38.035123 [Gating] SW mode calibration
6818 01:24:38.041846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 01:24:38.048914 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 01:24:38.052140 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 01:24:38.055057 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 01:24:38.061871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 01:24:38.065021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 01:24:38.068538 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 01:24:38.071944 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 01:24:38.078309 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 01:24:38.081508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 01:24:38.088440 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 01:24:38.088539 Total UI for P1: 0, mck2ui 16
6830 01:24:38.091731 best dqsien dly found for B0: ( 0, 14, 24)
6831 01:24:38.094937 Total UI for P1: 0, mck2ui 16
6832 01:24:38.098422 best dqsien dly found for B1: ( 0, 14, 24)
6833 01:24:38.104710 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 01:24:38.108496 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 01:24:38.108624
6836 01:24:38.111669 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 01:24:38.114684 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 01:24:38.118231 [Gating] SW calibration Done
6839 01:24:38.118357 ==
6840 01:24:38.121796 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 01:24:38.125062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 01:24:38.125179 ==
6843 01:24:38.128247 RX Vref Scan: 0
6844 01:24:38.128359
6845 01:24:38.128464 RX Vref 0 -> 0, step: 1
6846 01:24:38.128563
6847 01:24:38.131309 RX Delay -410 -> 252, step: 16
6848 01:24:38.134764 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6849 01:24:38.142018 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6850 01:24:38.145042 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6851 01:24:38.148136 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6852 01:24:38.151156 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6853 01:24:38.158164 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6854 01:24:38.161539 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6855 01:24:38.164542 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6856 01:24:38.168025 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6857 01:24:38.174743 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6858 01:24:38.178177 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6859 01:24:38.181943 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6860 01:24:38.185056 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6861 01:24:38.191306 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6862 01:24:38.194600 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6863 01:24:38.197703 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6864 01:24:38.197805 ==
6865 01:24:38.201262 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 01:24:38.208189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 01:24:38.208312 ==
6868 01:24:38.208385 DQS Delay:
6869 01:24:38.211038 DQS0 = 59, DQS1 = 59
6870 01:24:38.211123 DQM Delay:
6871 01:24:38.211191 DQM0 = 19, DQM1 = 13
6872 01:24:38.214272 DQ Delay:
6873 01:24:38.217686 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6874 01:24:38.221313 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6875 01:24:38.224212 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6876 01:24:38.227650 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6877 01:24:38.227749
6878 01:24:38.227835
6879 01:24:38.227916 ==
6880 01:24:38.230915 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 01:24:38.234365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 01:24:38.234450 ==
6883 01:24:38.234535
6884 01:24:38.234614
6885 01:24:38.237746 TX Vref Scan disable
6886 01:24:38.237831 == TX Byte 0 ==
6887 01:24:38.244522 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6888 01:24:38.247562 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6889 01:24:38.247685 == TX Byte 1 ==
6890 01:24:38.254116 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6891 01:24:38.257730 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6892 01:24:38.257815 ==
6893 01:24:38.261229 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 01:24:38.264222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 01:24:38.264306 ==
6896 01:24:38.264393
6897 01:24:38.264473
6898 01:24:38.267854 TX Vref Scan disable
6899 01:24:38.267939 == TX Byte 0 ==
6900 01:24:38.274448 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6901 01:24:38.277300 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6902 01:24:38.277384 == TX Byte 1 ==
6903 01:24:38.284211 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6904 01:24:38.287492 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6905 01:24:38.287576
6906 01:24:38.287662 [DATLAT]
6907 01:24:38.290717 Freq=400, CH1 RK1
6908 01:24:38.290801
6909 01:24:38.290887 DATLAT Default: 0xe
6910 01:24:38.294294 0, 0xFFFF, sum = 0
6911 01:24:38.294380 1, 0xFFFF, sum = 0
6912 01:24:38.297253 2, 0xFFFF, sum = 0
6913 01:24:38.297338 3, 0xFFFF, sum = 0
6914 01:24:38.300458 4, 0xFFFF, sum = 0
6915 01:24:38.304072 5, 0xFFFF, sum = 0
6916 01:24:38.304173 6, 0xFFFF, sum = 0
6917 01:24:38.307119 7, 0xFFFF, sum = 0
6918 01:24:38.307204 8, 0xFFFF, sum = 0
6919 01:24:38.310232 9, 0xFFFF, sum = 0
6920 01:24:38.310309 10, 0xFFFF, sum = 0
6921 01:24:38.313732 11, 0xFFFF, sum = 0
6922 01:24:38.313822 12, 0xFFFF, sum = 0
6923 01:24:38.316917 13, 0x0, sum = 1
6924 01:24:38.317004 14, 0x0, sum = 2
6925 01:24:38.320404 15, 0x0, sum = 3
6926 01:24:38.320517 16, 0x0, sum = 4
6927 01:24:38.323547 best_step = 14
6928 01:24:38.323632
6929 01:24:38.323717 ==
6930 01:24:38.327276 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 01:24:38.330236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 01:24:38.330332 ==
6933 01:24:38.330419 RX Vref Scan: 0
6934 01:24:38.330499
6935 01:24:38.333376 RX Vref 0 -> 0, step: 1
6936 01:24:38.333476
6937 01:24:38.336763 RX Delay -359 -> 252, step: 8
6938 01:24:38.344425 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6939 01:24:38.347539 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6940 01:24:38.350975 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6941 01:24:38.357532 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6942 01:24:38.361039 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6943 01:24:38.364023 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6944 01:24:38.367650 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6945 01:24:38.370806 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6946 01:24:38.377649 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6947 01:24:38.380637 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6948 01:24:38.384147 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6949 01:24:38.387962 iDelay=217, Bit 11, Center -64 (-319 ~ 192) 512
6950 01:24:38.394398 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6951 01:24:38.397512 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6952 01:24:38.401062 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6953 01:24:38.407405 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6954 01:24:38.407490 ==
6955 01:24:38.411012 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 01:24:38.414457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 01:24:38.414544 ==
6958 01:24:38.414646 DQS Delay:
6959 01:24:38.417317 DQS0 = 60, DQS1 = 64
6960 01:24:38.417420 DQM Delay:
6961 01:24:38.420833 DQM0 = 13, DQM1 = 10
6962 01:24:38.420917 DQ Delay:
6963 01:24:38.423843 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6964 01:24:38.427263 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6965 01:24:38.430755 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6966 01:24:38.434037 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6967 01:24:38.434121
6968 01:24:38.434205
6969 01:24:38.440376 [DQSOSCAuto] RK1, (LSB)MR18= 0x75a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6970 01:24:38.443828 CH1 RK1: MR19=C0C, MR18=75A7
6971 01:24:38.450358 CH1_RK1: MR19=0xC0C, MR18=0x75A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6972 01:24:38.453922 [RxdqsGatingPostProcess] freq 400
6973 01:24:38.460421 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 01:24:38.460511 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 01:24:38.464044 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 01:24:38.467026 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 01:24:38.470595 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 01:24:38.473937 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 01:24:38.477449 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 01:24:38.480284 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 01:24:38.484041 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 01:24:38.486888 Pre-setting of DQS Precalculation
6983 01:24:38.493871 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 01:24:38.500413 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 01:24:38.506825 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 01:24:38.506914
6987 01:24:38.506999
6988 01:24:38.510480 [Calibration Summary] 800 Mbps
6989 01:24:38.510566 CH 0, Rank 0
6990 01:24:38.513603 SW Impedance : PASS
6991 01:24:38.513692 DUTY Scan : NO K
6992 01:24:38.517022 ZQ Calibration : PASS
6993 01:24:38.520569 Jitter Meter : NO K
6994 01:24:38.520656 CBT Training : PASS
6995 01:24:38.523750 Write leveling : PASS
6996 01:24:38.527305 RX DQS gating : PASS
6997 01:24:38.527415 RX DQ/DQS(RDDQC) : PASS
6998 01:24:38.530172 TX DQ/DQS : PASS
6999 01:24:38.533579 RX DATLAT : PASS
7000 01:24:38.533663 RX DQ/DQS(Engine): PASS
7001 01:24:38.536753 TX OE : NO K
7002 01:24:38.536837 All Pass.
7003 01:24:38.536922
7004 01:24:38.540156 CH 0, Rank 1
7005 01:24:38.540240 SW Impedance : PASS
7006 01:24:38.543672 DUTY Scan : NO K
7007 01:24:38.546984 ZQ Calibration : PASS
7008 01:24:38.547068 Jitter Meter : NO K
7009 01:24:38.550456 CBT Training : PASS
7010 01:24:38.553493 Write leveling : NO K
7011 01:24:38.553576 RX DQS gating : PASS
7012 01:24:38.556671 RX DQ/DQS(RDDQC) : PASS
7013 01:24:38.560368 TX DQ/DQS : PASS
7014 01:24:38.560452 RX DATLAT : PASS
7015 01:24:38.563285 RX DQ/DQS(Engine): PASS
7016 01:24:38.563378 TX OE : NO K
7017 01:24:38.566655 All Pass.
7018 01:24:38.566769
7019 01:24:38.566855 CH 1, Rank 0
7020 01:24:38.569887 SW Impedance : PASS
7021 01:24:38.569970 DUTY Scan : NO K
7022 01:24:38.574078 ZQ Calibration : PASS
7023 01:24:38.576782 Jitter Meter : NO K
7024 01:24:38.576866 CBT Training : PASS
7025 01:24:38.580134 Write leveling : PASS
7026 01:24:38.583209 RX DQS gating : PASS
7027 01:24:38.583293 RX DQ/DQS(RDDQC) : PASS
7028 01:24:38.587015 TX DQ/DQS : PASS
7029 01:24:38.590445 RX DATLAT : PASS
7030 01:24:38.590529 RX DQ/DQS(Engine): PASS
7031 01:24:38.593431 TX OE : NO K
7032 01:24:38.593515 All Pass.
7033 01:24:38.593600
7034 01:24:38.596692 CH 1, Rank 1
7035 01:24:38.596776 SW Impedance : PASS
7036 01:24:38.600072 DUTY Scan : NO K
7037 01:24:38.603497 ZQ Calibration : PASS
7038 01:24:38.603580 Jitter Meter : NO K
7039 01:24:38.606482 CBT Training : PASS
7040 01:24:38.610075 Write leveling : NO K
7041 01:24:38.610158 RX DQS gating : PASS
7042 01:24:38.613050 RX DQ/DQS(RDDQC) : PASS
7043 01:24:38.616556 TX DQ/DQS : PASS
7044 01:24:38.616640 RX DATLAT : PASS
7045 01:24:38.620185 RX DQ/DQS(Engine): PASS
7046 01:24:38.620269 TX OE : NO K
7047 01:24:38.623186 All Pass.
7048 01:24:38.623270
7049 01:24:38.623376 DramC Write-DBI off
7050 01:24:38.626587 PER_BANK_REFRESH: Hybrid Mode
7051 01:24:38.629453 TX_TRACKING: ON
7052 01:24:38.636595 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 01:24:38.639981 [FAST_K] Save calibration result to emmc
7054 01:24:38.646476 dramc_set_vcore_voltage set vcore to 725000
7055 01:24:38.646560 Read voltage for 1600, 0
7056 01:24:38.649709 Vio18 = 0
7057 01:24:38.649793 Vcore = 725000
7058 01:24:38.649878 Vdram = 0
7059 01:24:38.649959 Vddq = 0
7060 01:24:38.652738 Vmddr = 0
7061 01:24:38.656233 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 01:24:38.662877 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 01:24:38.666361 MEM_TYPE=3, freq_sel=13
7064 01:24:38.666445 sv_algorithm_assistance_LP4_3733
7065 01:24:38.672465 ============ PULL DRAM RESETB DOWN ============
7066 01:24:38.676281 ========== PULL DRAM RESETB DOWN end =========
7067 01:24:38.679502 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 01:24:38.682554 ===================================
7069 01:24:38.685949 LPDDR4 DRAM CONFIGURATION
7070 01:24:38.689191 ===================================
7071 01:24:38.692908 EX_ROW_EN[0] = 0x0
7072 01:24:38.692992 EX_ROW_EN[1] = 0x0
7073 01:24:38.695796 LP4Y_EN = 0x0
7074 01:24:38.695879 WORK_FSP = 0x1
7075 01:24:38.698881 WL = 0x5
7076 01:24:38.698962 RL = 0x5
7077 01:24:38.702495 BL = 0x2
7078 01:24:38.702578 RPST = 0x0
7079 01:24:38.705427 RD_PRE = 0x0
7080 01:24:38.708852 WR_PRE = 0x1
7081 01:24:38.708933 WR_PST = 0x1
7082 01:24:38.712122 DBI_WR = 0x0
7083 01:24:38.712204 DBI_RD = 0x0
7084 01:24:38.715503 OTF = 0x1
7085 01:24:38.718732 ===================================
7086 01:24:38.722431 ===================================
7087 01:24:38.722513 ANA top config
7088 01:24:38.725588 ===================================
7089 01:24:38.728985 DLL_ASYNC_EN = 0
7090 01:24:38.732257 ALL_SLAVE_EN = 0
7091 01:24:38.732362 NEW_RANK_MODE = 1
7092 01:24:38.735542 DLL_IDLE_MODE = 1
7093 01:24:38.738738 LP45_APHY_COMB_EN = 1
7094 01:24:38.741826 TX_ODT_DIS = 0
7095 01:24:38.741907 NEW_8X_MODE = 1
7096 01:24:38.745445 ===================================
7097 01:24:38.748700 ===================================
7098 01:24:38.751959 data_rate = 3200
7099 01:24:38.755293 CKR = 1
7100 01:24:38.759081 DQ_P2S_RATIO = 8
7101 01:24:38.761874 ===================================
7102 01:24:38.765591 CA_P2S_RATIO = 8
7103 01:24:38.769183 DQ_CA_OPEN = 0
7104 01:24:38.769263 DQ_SEMI_OPEN = 0
7105 01:24:38.771930 CA_SEMI_OPEN = 0
7106 01:24:38.774881 CA_FULL_RATE = 0
7107 01:24:38.778408 DQ_CKDIV4_EN = 0
7108 01:24:38.781721 CA_CKDIV4_EN = 0
7109 01:24:38.784782 CA_PREDIV_EN = 0
7110 01:24:38.788467 PH8_DLY = 12
7111 01:24:38.788550 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 01:24:38.791563 DQ_AAMCK_DIV = 4
7113 01:24:38.794910 CA_AAMCK_DIV = 4
7114 01:24:38.798046 CA_ADMCK_DIV = 4
7115 01:24:38.801415 DQ_TRACK_CA_EN = 0
7116 01:24:38.804721 CA_PICK = 1600
7117 01:24:38.808400 CA_MCKIO = 1600
7118 01:24:38.808484 MCKIO_SEMI = 0
7119 01:24:38.811624 PLL_FREQ = 3068
7120 01:24:38.814611 DQ_UI_PI_RATIO = 32
7121 01:24:38.818060 CA_UI_PI_RATIO = 0
7122 01:24:38.821296 ===================================
7123 01:24:38.824306 ===================================
7124 01:24:38.827876 memory_type:LPDDR4
7125 01:24:38.827960 GP_NUM : 10
7126 01:24:38.830974 SRAM_EN : 1
7127 01:24:38.834471 MD32_EN : 0
7128 01:24:38.838039 ===================================
7129 01:24:38.838124 [ANA_INIT] >>>>>>>>>>>>>>
7130 01:24:38.840835 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 01:24:38.844251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 01:24:38.847783 ===================================
7133 01:24:38.851171 data_rate = 3200,PCW = 0X7600
7134 01:24:38.854184 ===================================
7135 01:24:38.857714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 01:24:38.864115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 01:24:38.867162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 01:24:38.873885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 01:24:38.877187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 01:24:38.880689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 01:24:38.884365 [ANA_INIT] flow start
7142 01:24:38.884447 [ANA_INIT] PLL >>>>>>>>
7143 01:24:38.887050 [ANA_INIT] PLL <<<<<<<<
7144 01:24:38.890273 [ANA_INIT] MIDPI >>>>>>>>
7145 01:24:38.890355 [ANA_INIT] MIDPI <<<<<<<<
7146 01:24:38.893570 [ANA_INIT] DLL >>>>>>>>
7147 01:24:38.897442 [ANA_INIT] DLL <<<<<<<<
7148 01:24:38.897524 [ANA_INIT] flow end
7149 01:24:38.900431 ============ LP4 DIFF to SE enter ============
7150 01:24:38.907049 ============ LP4 DIFF to SE exit ============
7151 01:24:38.907132 [ANA_INIT] <<<<<<<<<<<<<
7152 01:24:38.910354 [Flow] Enable top DCM control >>>>>
7153 01:24:38.913922 [Flow] Enable top DCM control <<<<<
7154 01:24:38.917009 Enable DLL master slave shuffle
7155 01:24:38.923414 ==============================================================
7156 01:24:38.926834 Gating Mode config
7157 01:24:38.930313 ==============================================================
7158 01:24:38.933675 Config description:
7159 01:24:38.943224 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 01:24:38.950000 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 01:24:38.953217 SELPH_MODE 0: By rank 1: By Phase
7162 01:24:38.960310 ==============================================================
7163 01:24:38.963359 GAT_TRACK_EN = 1
7164 01:24:38.966552 RX_GATING_MODE = 2
7165 01:24:38.970008 RX_GATING_TRACK_MODE = 2
7166 01:24:38.970106 SELPH_MODE = 1
7167 01:24:38.973060 PICG_EARLY_EN = 1
7168 01:24:38.976594 VALID_LAT_VALUE = 1
7169 01:24:38.983086 ==============================================================
7170 01:24:38.986488 Enter into Gating configuration >>>>
7171 01:24:38.989530 Exit from Gating configuration <<<<
7172 01:24:38.992931 Enter into DVFS_PRE_config >>>>>
7173 01:24:39.002956 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 01:24:39.006243 Exit from DVFS_PRE_config <<<<<
7175 01:24:39.009527 Enter into PICG configuration >>>>
7176 01:24:39.012670 Exit from PICG configuration <<<<
7177 01:24:39.016351 [RX_INPUT] configuration >>>>>
7178 01:24:39.019571 [RX_INPUT] configuration <<<<<
7179 01:24:39.022785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 01:24:39.029153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 01:24:39.036073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 01:24:39.042546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 01:24:39.049139 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 01:24:39.052693 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 01:24:39.059411 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 01:24:39.062222 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 01:24:39.065694 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 01:24:39.072225 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 01:24:39.075677 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 01:24:39.078866 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 01:24:39.082104 ===================================
7192 01:24:39.085746 LPDDR4 DRAM CONFIGURATION
7193 01:24:39.088844 ===================================
7194 01:24:39.088944 EX_ROW_EN[0] = 0x0
7195 01:24:39.091763 EX_ROW_EN[1] = 0x0
7196 01:24:39.091842 LP4Y_EN = 0x0
7197 01:24:39.095566 WORK_FSP = 0x1
7198 01:24:39.098689 WL = 0x5
7199 01:24:39.098792 RL = 0x5
7200 01:24:39.102226 BL = 0x2
7201 01:24:39.102326 RPST = 0x0
7202 01:24:39.105365 RD_PRE = 0x0
7203 01:24:39.105464 WR_PRE = 0x1
7204 01:24:39.108678 WR_PST = 0x1
7205 01:24:39.108778 DBI_WR = 0x0
7206 01:24:39.112319 DBI_RD = 0x0
7207 01:24:39.112426 OTF = 0x1
7208 01:24:39.115228 ===================================
7209 01:24:39.118748 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 01:24:39.125084 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 01:24:39.128723 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 01:24:39.131880 ===================================
7213 01:24:39.135223 LPDDR4 DRAM CONFIGURATION
7214 01:24:39.138801 ===================================
7215 01:24:39.138915 EX_ROW_EN[0] = 0x10
7216 01:24:39.141740 EX_ROW_EN[1] = 0x0
7217 01:24:39.141840 LP4Y_EN = 0x0
7218 01:24:39.145308 WORK_FSP = 0x1
7219 01:24:39.145412 WL = 0x5
7220 01:24:39.148261 RL = 0x5
7221 01:24:39.148366 BL = 0x2
7222 01:24:39.151913 RPST = 0x0
7223 01:24:39.154836 RD_PRE = 0x0
7224 01:24:39.154937 WR_PRE = 0x1
7225 01:24:39.158447 WR_PST = 0x1
7226 01:24:39.158551 DBI_WR = 0x0
7227 01:24:39.161515 DBI_RD = 0x0
7228 01:24:39.161617 OTF = 0x1
7229 01:24:39.164685 ===================================
7230 01:24:39.171781 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 01:24:39.171860 ==
7232 01:24:39.175052 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 01:24:39.178001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 01:24:39.178101 ==
7235 01:24:39.181511 [Duty_Offset_Calibration]
7236 01:24:39.185018 B0:2 B1:0 CA:3
7237 01:24:39.185124
7238 01:24:39.188440 [DutyScan_Calibration_Flow] k_type=0
7239 01:24:39.196847
7240 01:24:39.196944 ==CLK 0==
7241 01:24:39.199905 Final CLK duty delay cell = 0
7242 01:24:39.202988 [0] MAX Duty = 5031%(X100), DQS PI = 12
7243 01:24:39.206568 [0] MIN Duty = 4907%(X100), DQS PI = 2
7244 01:24:39.206671 [0] AVG Duty = 4969%(X100)
7245 01:24:39.209608
7246 01:24:39.213045 CH0 CLK Duty spec in!! Max-Min= 124%
7247 01:24:39.216408 [DutyScan_Calibration_Flow] ====Done====
7248 01:24:39.216515
7249 01:24:39.219521 [DutyScan_Calibration_Flow] k_type=1
7250 01:24:39.236796
7251 01:24:39.236885 ==DQS 0 ==
7252 01:24:39.239781 Final DQS duty delay cell = 0
7253 01:24:39.243547 [0] MAX Duty = 5125%(X100), DQS PI = 30
7254 01:24:39.246198 [0] MIN Duty = 4875%(X100), DQS PI = 48
7255 01:24:39.249970 [0] AVG Duty = 5000%(X100)
7256 01:24:39.250046
7257 01:24:39.250110 ==DQS 1 ==
7258 01:24:39.253177 Final DQS duty delay cell = 0
7259 01:24:39.256160 [0] MAX Duty = 5156%(X100), DQS PI = 30
7260 01:24:39.260104 [0] MIN Duty = 5062%(X100), DQS PI = 0
7261 01:24:39.263219 [0] AVG Duty = 5109%(X100)
7262 01:24:39.263321
7263 01:24:39.266601 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7264 01:24:39.266674
7265 01:24:39.269755 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7266 01:24:39.273013 [DutyScan_Calibration_Flow] ====Done====
7267 01:24:39.273115
7268 01:24:39.276404 [DutyScan_Calibration_Flow] k_type=3
7269 01:24:39.294325
7270 01:24:39.294414 ==DQM 0 ==
7271 01:24:39.297421 Final DQM duty delay cell = 0
7272 01:24:39.301087 [0] MAX Duty = 5187%(X100), DQS PI = 32
7273 01:24:39.304274 [0] MIN Duty = 4875%(X100), DQS PI = 0
7274 01:24:39.307937 [0] AVG Duty = 5031%(X100)
7275 01:24:39.308020
7276 01:24:39.308086 ==DQM 1 ==
7277 01:24:39.310865 Final DQM duty delay cell = 4
7278 01:24:39.313947 [4] MAX Duty = 5187%(X100), DQS PI = 62
7279 01:24:39.317607 [4] MIN Duty = 5031%(X100), DQS PI = 12
7280 01:24:39.321046 [4] AVG Duty = 5109%(X100)
7281 01:24:39.321151
7282 01:24:39.324074 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7283 01:24:39.324175
7284 01:24:39.327720 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7285 01:24:39.331056 [DutyScan_Calibration_Flow] ====Done====
7286 01:24:39.331159
7287 01:24:39.334131 [DutyScan_Calibration_Flow] k_type=2
7288 01:24:39.350759
7289 01:24:39.350869 ==DQ 0 ==
7290 01:24:39.354136 Final DQ duty delay cell = -4
7291 01:24:39.357298 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7292 01:24:39.361194 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7293 01:24:39.363989 [-4] AVG Duty = 4938%(X100)
7294 01:24:39.364085
7295 01:24:39.364150 ==DQ 1 ==
7296 01:24:39.367607 Final DQ duty delay cell = 0
7297 01:24:39.370619 [0] MAX Duty = 5156%(X100), DQS PI = 58
7298 01:24:39.373714 [0] MIN Duty = 5000%(X100), DQS PI = 14
7299 01:24:39.376832 [0] AVG Duty = 5078%(X100)
7300 01:24:39.376935
7301 01:24:39.380611 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7302 01:24:39.380691
7303 01:24:39.383881 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7304 01:24:39.387045 [DutyScan_Calibration_Flow] ====Done====
7305 01:24:39.387149 ==
7306 01:24:39.390132 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 01:24:39.393552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 01:24:39.393658 ==
7309 01:24:39.397252 [Duty_Offset_Calibration]
7310 01:24:39.397353 B0:1 B1:-2 CA:0
7311 01:24:39.397455
7312 01:24:39.400200 [DutyScan_Calibration_Flow] k_type=0
7313 01:24:39.411206
7314 01:24:39.411311 ==CLK 0==
7315 01:24:39.414270 Final CLK duty delay cell = 0
7316 01:24:39.417765 [0] MAX Duty = 5062%(X100), DQS PI = 22
7317 01:24:39.421205 [0] MIN Duty = 4844%(X100), DQS PI = 4
7318 01:24:39.421310 [0] AVG Duty = 4953%(X100)
7319 01:24:39.424288
7320 01:24:39.427832 CH1 CLK Duty spec in!! Max-Min= 218%
7321 01:24:39.431119 [DutyScan_Calibration_Flow] ====Done====
7322 01:24:39.431223
7323 01:24:39.434421 [DutyScan_Calibration_Flow] k_type=1
7324 01:24:39.450454
7325 01:24:39.450559 ==DQS 0 ==
7326 01:24:39.453451 Final DQS duty delay cell = -4
7327 01:24:39.457015 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7328 01:24:39.460363 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7329 01:24:39.463156 [-4] AVG Duty = 4906%(X100)
7330 01:24:39.463259
7331 01:24:39.463352 ==DQS 1 ==
7332 01:24:39.466401 Final DQS duty delay cell = 0
7333 01:24:39.469993 [0] MAX Duty = 5093%(X100), DQS PI = 60
7334 01:24:39.473215 [0] MIN Duty = 4844%(X100), DQS PI = 24
7335 01:24:39.476535 [0] AVG Duty = 4968%(X100)
7336 01:24:39.476644
7337 01:24:39.479689 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7338 01:24:39.479790
7339 01:24:39.483121 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7340 01:24:39.486425 [DutyScan_Calibration_Flow] ====Done====
7341 01:24:39.486501
7342 01:24:39.489830 [DutyScan_Calibration_Flow] k_type=3
7343 01:24:39.507154
7344 01:24:39.507263 ==DQM 0 ==
7345 01:24:39.510694 Final DQM duty delay cell = 0
7346 01:24:39.514255 [0] MAX Duty = 5031%(X100), DQS PI = 24
7347 01:24:39.517078 [0] MIN Duty = 4813%(X100), DQS PI = 54
7348 01:24:39.520584 [0] AVG Duty = 4922%(X100)
7349 01:24:39.520688
7350 01:24:39.520781 ==DQM 1 ==
7351 01:24:39.524283 Final DQM duty delay cell = 0
7352 01:24:39.527091 [0] MAX Duty = 5062%(X100), DQS PI = 34
7353 01:24:39.530718 [0] MIN Duty = 4875%(X100), DQS PI = 26
7354 01:24:39.533920 [0] AVG Duty = 4968%(X100)
7355 01:24:39.534024
7356 01:24:39.537541 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7357 01:24:39.537641
7358 01:24:39.541093 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7359 01:24:39.543887 [DutyScan_Calibration_Flow] ====Done====
7360 01:24:39.543981
7361 01:24:39.547584 [DutyScan_Calibration_Flow] k_type=2
7362 01:24:39.564405
7363 01:24:39.564510 ==DQ 0 ==
7364 01:24:39.567529 Final DQ duty delay cell = 0
7365 01:24:39.570956 [0] MAX Duty = 5093%(X100), DQS PI = 22
7366 01:24:39.574420 [0] MIN Duty = 4938%(X100), DQS PI = 0
7367 01:24:39.574529 [0] AVG Duty = 5015%(X100)
7368 01:24:39.577528
7369 01:24:39.577627 ==DQ 1 ==
7370 01:24:39.581038 Final DQ duty delay cell = 0
7371 01:24:39.584265 [0] MAX Duty = 5125%(X100), DQS PI = 34
7372 01:24:39.587529 [0] MIN Duty = 4969%(X100), DQS PI = 26
7373 01:24:39.587630 [0] AVG Duty = 5047%(X100)
7374 01:24:39.590908
7375 01:24:39.593796 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7376 01:24:39.593868
7377 01:24:39.597413 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7378 01:24:39.600739 [DutyScan_Calibration_Flow] ====Done====
7379 01:24:39.603886 nWR fixed to 30
7380 01:24:39.603969 [ModeRegInit_LP4] CH0 RK0
7381 01:24:39.607147 [ModeRegInit_LP4] CH0 RK1
7382 01:24:39.610965 [ModeRegInit_LP4] CH1 RK0
7383 01:24:39.614083 [ModeRegInit_LP4] CH1 RK1
7384 01:24:39.614195 match AC timing 5
7385 01:24:39.620544 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 01:24:39.623847 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 01:24:39.627530 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 01:24:39.633841 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 01:24:39.637406 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 01:24:39.637480 [MiockJmeterHQA]
7391 01:24:39.637555
7392 01:24:39.640344 [DramcMiockJmeter] u1RxGatingPI = 0
7393 01:24:39.643767 0 : 4368, 4140
7394 01:24:39.643866 4 : 4253, 4026
7395 01:24:39.647435 8 : 4257, 4027
7396 01:24:39.647534 12 : 4257, 4029
7397 01:24:39.647624 16 : 4258, 4030
7398 01:24:39.650228 20 : 4363, 4138
7399 01:24:39.650316 24 : 4252, 4027
7400 01:24:39.653694 28 : 4252, 4027
7401 01:24:39.653793 32 : 4258, 4029
7402 01:24:39.657208 36 : 4260, 4032
7403 01:24:39.657325 40 : 4252, 4027
7404 01:24:39.660509 44 : 4252, 4027
7405 01:24:39.660615 48 : 4365, 4140
7406 01:24:39.660720 52 : 4255, 4029
7407 01:24:39.663758 56 : 4255, 4029
7408 01:24:39.663861 60 : 4250, 4026
7409 01:24:39.667532 64 : 4363, 4137
7410 01:24:39.667643 68 : 4250, 4027
7411 01:24:39.670445 72 : 4361, 4137
7412 01:24:39.670555 76 : 4252, 4029
7413 01:24:39.670651 80 : 4250, 4027
7414 01:24:39.674026 84 : 4250, 4027
7415 01:24:39.674138 88 : 4253, 4029
7416 01:24:39.677043 92 : 4361, 4137
7417 01:24:39.677148 96 : 4250, 4027
7418 01:24:39.680505 100 : 4360, 4138
7419 01:24:39.680609 104 : 4361, 4028
7420 01:24:39.683447 108 : 4250, 4
7421 01:24:39.683527 112 : 4250, 0
7422 01:24:39.683643 116 : 4252, 0
7423 01:24:39.686962 120 : 4361, 0
7424 01:24:39.687070 124 : 4250, 0
7425 01:24:39.690169 128 : 4250, 0
7426 01:24:39.690272 132 : 4250, 0
7427 01:24:39.690369 136 : 4361, 0
7428 01:24:39.693586 140 : 4360, 0
7429 01:24:39.693697 144 : 4250, 0
7430 01:24:39.693793 148 : 4361, 0
7431 01:24:39.697449 152 : 4361, 0
7432 01:24:39.697558 156 : 4247, 0
7433 01:24:39.700211 160 : 4250, 0
7434 01:24:39.700325 164 : 4250, 0
7435 01:24:39.700422 168 : 4250, 0
7436 01:24:39.703669 172 : 4361, 0
7437 01:24:39.703745 176 : 4250, 0
7438 01:24:39.707126 180 : 4250, 0
7439 01:24:39.707237 184 : 4250, 0
7440 01:24:39.707330 188 : 4361, 0
7441 01:24:39.710069 192 : 4361, 0
7442 01:24:39.710176 196 : 4250, 0
7443 01:24:39.710271 200 : 4360, 0
7444 01:24:39.713390 204 : 4250, 0
7445 01:24:39.713499 208 : 4250, 0
7446 01:24:39.716975 212 : 4250, 0
7447 01:24:39.717063 216 : 4250, 0
7448 01:24:39.717161 220 : 4252, 0
7449 01:24:39.720112 224 : 4361, 0
7450 01:24:39.720218 228 : 4250, 0
7451 01:24:39.723579 232 : 4250, 1
7452 01:24:39.723681 236 : 4250, 1512
7453 01:24:39.726978 240 : 4253, 4029
7454 01:24:39.727096 244 : 4250, 4027
7455 01:24:39.727190 248 : 4363, 4139
7456 01:24:39.729993 252 : 4361, 4137
7457 01:24:39.730095 256 : 4250, 4026
7458 01:24:39.733417 260 : 4363, 4139
7459 01:24:39.733521 264 : 4361, 4137
7460 01:24:39.737043 268 : 4250, 4027
7461 01:24:39.737154 272 : 4250, 4027
7462 01:24:39.740040 276 : 4252, 4029
7463 01:24:39.740143 280 : 4250, 4027
7464 01:24:39.743615 284 : 4253, 4027
7465 01:24:39.743724 288 : 4250, 4027
7466 01:24:39.746817 292 : 4253, 4029
7467 01:24:39.746920 296 : 4250, 4027
7468 01:24:39.750069 300 : 4361, 4137
7469 01:24:39.750173 304 : 4361, 4137
7470 01:24:39.750266 308 : 4250, 4026
7471 01:24:39.753450 312 : 4363, 4139
7472 01:24:39.753530 316 : 4250, 4027
7473 01:24:39.756526 320 : 4250, 4027
7474 01:24:39.756639 324 : 4250, 4027
7475 01:24:39.759908 328 : 4252, 4029
7476 01:24:39.759985 332 : 4250, 4027
7477 01:24:39.763012 336 : 4252, 4029
7478 01:24:39.763114 340 : 4250, 4027
7479 01:24:39.766741 344 : 4252, 4029
7480 01:24:39.766843 348 : 4250, 4027
7481 01:24:39.769982 352 : 4360, 4136
7482 01:24:39.770076 356 : 4361, 2899
7483 01:24:39.770172 360 : 4250, 8
7484 01:24:39.773069
7485 01:24:39.773170 MIOCK jitter meter ch=0
7486 01:24:39.773260
7487 01:24:39.776590 1T = (360-108) = 252 dly cells
7488 01:24:39.783144 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7489 01:24:39.783248 ==
7490 01:24:39.786597 Dram Type= 6, Freq= 0, CH_0, rank 0
7491 01:24:39.789552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7492 01:24:39.789656 ==
7493 01:24:39.796419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7494 01:24:39.799915 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7495 01:24:39.802906 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7496 01:24:39.809576 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7497 01:24:39.819233 [CA 0] Center 44 (14~75) winsize 62
7498 01:24:39.822351 [CA 1] Center 43 (13~74) winsize 62
7499 01:24:39.825760 [CA 2] Center 39 (10~69) winsize 60
7500 01:24:39.829044 [CA 3] Center 39 (10~68) winsize 59
7501 01:24:39.832543 [CA 4] Center 37 (8~67) winsize 60
7502 01:24:39.835611 [CA 5] Center 37 (7~67) winsize 61
7503 01:24:39.835689
7504 01:24:39.839200 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7505 01:24:39.839301
7506 01:24:39.845697 [CATrainingPosCal] consider 1 rank data
7507 01:24:39.845801 u2DelayCellTimex100 = 258/100 ps
7508 01:24:39.852383 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7509 01:24:39.855588 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7510 01:24:39.859064 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7511 01:24:39.862215 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7512 01:24:39.865872 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7513 01:24:39.869150 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7514 01:24:39.869254
7515 01:24:39.872580 CA PerBit enable=1, Macro0, CA PI delay=37
7516 01:24:39.872706
7517 01:24:39.875337 [CBTSetCACLKResult] CA Dly = 37
7518 01:24:39.878981 CS Dly: 11 (0~42)
7519 01:24:39.882555 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7520 01:24:39.885502 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7521 01:24:39.885612 ==
7522 01:24:39.888973 Dram Type= 6, Freq= 0, CH_0, rank 1
7523 01:24:39.895999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 01:24:39.896115 ==
7525 01:24:39.898934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 01:24:39.905346 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 01:24:39.908563 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 01:24:39.915508 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 01:24:39.923031 [CA 0] Center 44 (13~75) winsize 63
7530 01:24:39.926463 [CA 1] Center 43 (13~74) winsize 62
7531 01:24:39.930012 [CA 2] Center 39 (10~69) winsize 60
7532 01:24:39.932979 [CA 3] Center 39 (10~68) winsize 59
7533 01:24:39.936498 [CA 4] Center 38 (9~67) winsize 59
7534 01:24:39.939759 [CA 5] Center 37 (8~66) winsize 59
7535 01:24:39.939845
7536 01:24:39.943059 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7537 01:24:39.943130
7538 01:24:39.946165 [CATrainingPosCal] consider 2 rank data
7539 01:24:39.949678 u2DelayCellTimex100 = 258/100 ps
7540 01:24:39.956267 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7541 01:24:39.959953 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7542 01:24:39.962908 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7543 01:24:39.966437 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7544 01:24:39.969657 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7545 01:24:39.972850 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7546 01:24:39.972958
7547 01:24:39.976091 CA PerBit enable=1, Macro0, CA PI delay=37
7548 01:24:39.976179
7549 01:24:39.979675 [CBTSetCACLKResult] CA Dly = 37
7550 01:24:39.982830 CS Dly: 11 (0~42)
7551 01:24:39.986296 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 01:24:39.989667 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 01:24:39.989777
7554 01:24:39.993162 ----->DramcWriteLeveling(PI) begin...
7555 01:24:39.993264 ==
7556 01:24:39.995950 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 01:24:40.002532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 01:24:40.002641 ==
7559 01:24:40.006112 Write leveling (Byte 0): 36 => 36
7560 01:24:40.006225 Write leveling (Byte 1): 29 => 29
7561 01:24:40.009714 DramcWriteLeveling(PI) end<-----
7562 01:24:40.009817
7563 01:24:40.012708 ==
7564 01:24:40.012811 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 01:24:40.019289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 01:24:40.019441 ==
7567 01:24:40.022635 [Gating] SW mode calibration
7568 01:24:40.029145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7569 01:24:40.032774 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7570 01:24:40.039134 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 01:24:40.042843 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 01:24:40.045671 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 01:24:40.052474 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 01:24:40.056308 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7575 01:24:40.059149 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7576 01:24:40.065836 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7577 01:24:40.069346 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 01:24:40.072180 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 01:24:40.079266 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 01:24:40.082534 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 01:24:40.085570 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 01:24:40.092377 1 5 16 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
7583 01:24:40.095720 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7584 01:24:40.099084 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7585 01:24:40.106086 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 01:24:40.108852 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 01:24:40.112805 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 01:24:40.118798 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 01:24:40.122178 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7590 01:24:40.125538 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7591 01:24:40.128549 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7592 01:24:40.135592 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7593 01:24:40.138521 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 01:24:40.142209 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 01:24:40.148812 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 01:24:40.152113 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 01:24:40.155710 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 01:24:40.161828 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7599 01:24:40.165504 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7600 01:24:40.169021 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7601 01:24:40.175049 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 01:24:40.178676 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 01:24:40.181766 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 01:24:40.188383 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 01:24:40.191967 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 01:24:40.195527 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 01:24:40.201849 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 01:24:40.205624 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 01:24:40.208250 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 01:24:40.215180 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 01:24:40.218337 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 01:24:40.221598 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 01:24:40.228323 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7614 01:24:40.231570 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7615 01:24:40.234962 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7616 01:24:40.238293 Total UI for P1: 0, mck2ui 16
7617 01:24:40.241336 best dqsien dly found for B0: ( 1, 9, 14)
7618 01:24:40.248007 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 01:24:40.251705 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 01:24:40.254577 Total UI for P1: 0, mck2ui 16
7621 01:24:40.258111 best dqsien dly found for B1: ( 1, 9, 24)
7622 01:24:40.261655 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7623 01:24:40.264503 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7624 01:24:40.264580
7625 01:24:40.268228 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7626 01:24:40.271253 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7627 01:24:40.274946 [Gating] SW calibration Done
7628 01:24:40.275051 ==
7629 01:24:40.278047 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 01:24:40.281291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 01:24:40.284714 ==
7632 01:24:40.284812 RX Vref Scan: 0
7633 01:24:40.284902
7634 01:24:40.288179 RX Vref 0 -> 0, step: 1
7635 01:24:40.288248
7636 01:24:40.288315 RX Delay 0 -> 252, step: 8
7637 01:24:40.294469 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7638 01:24:40.298007 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7639 01:24:40.301548 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7640 01:24:40.304387 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7641 01:24:40.308222 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7642 01:24:40.314354 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7643 01:24:40.317802 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7644 01:24:40.321008 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7645 01:24:40.324416 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7646 01:24:40.327902 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7647 01:24:40.334283 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7648 01:24:40.337839 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7649 01:24:40.340891 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7650 01:24:40.344351 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7651 01:24:40.351469 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7652 01:24:40.353964 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7653 01:24:40.354068 ==
7654 01:24:40.357339 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 01:24:40.361285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 01:24:40.361393 ==
7657 01:24:40.364236 DQS Delay:
7658 01:24:40.364312 DQS0 = 0, DQS1 = 0
7659 01:24:40.364379 DQM Delay:
7660 01:24:40.367408 DQM0 = 127, DQM1 = 123
7661 01:24:40.367504 DQ Delay:
7662 01:24:40.370996 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7663 01:24:40.374102 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =135
7664 01:24:40.377318 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7665 01:24:40.383729 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7666 01:24:40.383827
7667 01:24:40.383894
7668 01:24:40.383958 ==
7669 01:24:40.387488 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 01:24:40.390752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 01:24:40.390849 ==
7672 01:24:40.390915
7673 01:24:40.390976
7674 01:24:40.394060 TX Vref Scan disable
7675 01:24:40.394169 == TX Byte 0 ==
7676 01:24:40.400668 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7677 01:24:40.404220 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7678 01:24:40.404332 == TX Byte 1 ==
7679 01:24:40.410556 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7680 01:24:40.413874 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7681 01:24:40.413982 ==
7682 01:24:40.417226 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 01:24:40.420587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 01:24:40.420700 ==
7685 01:24:40.436344
7686 01:24:40.439957 TX Vref early break, caculate TX vref
7687 01:24:40.442839 TX Vref=16, minBit 8, minWin=21, winSum=365
7688 01:24:40.446382 TX Vref=18, minBit 8, minWin=22, winSum=376
7689 01:24:40.449414 TX Vref=20, minBit 13, minWin=22, winSum=386
7690 01:24:40.453046 TX Vref=22, minBit 8, minWin=23, winSum=397
7691 01:24:40.456370 TX Vref=24, minBit 8, minWin=24, winSum=405
7692 01:24:40.463358 TX Vref=26, minBit 4, minWin=23, winSum=409
7693 01:24:40.466114 TX Vref=28, minBit 4, minWin=25, winSum=413
7694 01:24:40.469630 TX Vref=30, minBit 9, minWin=24, winSum=405
7695 01:24:40.473117 TX Vref=32, minBit 8, minWin=23, winSum=396
7696 01:24:40.476016 TX Vref=34, minBit 8, minWin=22, winSum=392
7697 01:24:40.479877 TX Vref=36, minBit 8, minWin=21, winSum=374
7698 01:24:40.486430 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 28
7699 01:24:40.486542
7700 01:24:40.489719 Final TX Range 0 Vref 28
7701 01:24:40.489830
7702 01:24:40.489924 ==
7703 01:24:40.492657 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 01:24:40.495828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 01:24:40.495906 ==
7706 01:24:40.495970
7707 01:24:40.499068
7708 01:24:40.499168 TX Vref Scan disable
7709 01:24:40.505876 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7710 01:24:40.505982 == TX Byte 0 ==
7711 01:24:40.509313 u2DelayCellOfst[0]=15 cells (4 PI)
7712 01:24:40.512407 u2DelayCellOfst[1]=18 cells (5 PI)
7713 01:24:40.515766 u2DelayCellOfst[2]=15 cells (4 PI)
7714 01:24:40.519255 u2DelayCellOfst[3]=15 cells (4 PI)
7715 01:24:40.522199 u2DelayCellOfst[4]=11 cells (3 PI)
7716 01:24:40.525739 u2DelayCellOfst[5]=0 cells (0 PI)
7717 01:24:40.529228 u2DelayCellOfst[6]=22 cells (6 PI)
7718 01:24:40.532704 u2DelayCellOfst[7]=22 cells (6 PI)
7719 01:24:40.535517 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7720 01:24:40.539170 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7721 01:24:40.542577 == TX Byte 1 ==
7722 01:24:40.545370 u2DelayCellOfst[8]=0 cells (0 PI)
7723 01:24:40.549252 u2DelayCellOfst[9]=3 cells (1 PI)
7724 01:24:40.552361 u2DelayCellOfst[10]=7 cells (2 PI)
7725 01:24:40.555298 u2DelayCellOfst[11]=3 cells (1 PI)
7726 01:24:40.558786 u2DelayCellOfst[12]=15 cells (4 PI)
7727 01:24:40.558863 u2DelayCellOfst[13]=11 cells (3 PI)
7728 01:24:40.562151 u2DelayCellOfst[14]=15 cells (4 PI)
7729 01:24:40.565450 u2DelayCellOfst[15]=11 cells (3 PI)
7730 01:24:40.572008 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7731 01:24:40.575607 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7732 01:24:40.575708 DramC Write-DBI on
7733 01:24:40.578878 ==
7734 01:24:40.581999 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 01:24:40.585976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 01:24:40.586087 ==
7737 01:24:40.586179
7738 01:24:40.586269
7739 01:24:40.588474 TX Vref Scan disable
7740 01:24:40.588548 == TX Byte 0 ==
7741 01:24:40.595359 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7742 01:24:40.595478 == TX Byte 1 ==
7743 01:24:40.599190 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7744 01:24:40.601931 DramC Write-DBI off
7745 01:24:40.602050
7746 01:24:40.602142 [DATLAT]
7747 01:24:40.605545 Freq=1600, CH0 RK0
7748 01:24:40.605646
7749 01:24:40.605738 DATLAT Default: 0xf
7750 01:24:40.608698 0, 0xFFFF, sum = 0
7751 01:24:40.608807 1, 0xFFFF, sum = 0
7752 01:24:40.612195 2, 0xFFFF, sum = 0
7753 01:24:40.612299 3, 0xFFFF, sum = 0
7754 01:24:40.615295 4, 0xFFFF, sum = 0
7755 01:24:40.615442 5, 0xFFFF, sum = 0
7756 01:24:40.618972 6, 0xFFFF, sum = 0
7757 01:24:40.619089 7, 0xFFFF, sum = 0
7758 01:24:40.622014 8, 0xFFFF, sum = 0
7759 01:24:40.622126 9, 0xFFFF, sum = 0
7760 01:24:40.625251 10, 0xFFFF, sum = 0
7761 01:24:40.628517 11, 0xFFFF, sum = 0
7762 01:24:40.628624 12, 0xFFFF, sum = 0
7763 01:24:40.632304 13, 0xEFFF, sum = 0
7764 01:24:40.632409 14, 0x0, sum = 1
7765 01:24:40.635376 15, 0x0, sum = 2
7766 01:24:40.635491 16, 0x0, sum = 3
7767 01:24:40.638614 17, 0x0, sum = 4
7768 01:24:40.638719 best_step = 15
7769 01:24:40.638814
7770 01:24:40.638904 ==
7771 01:24:40.642064 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 01:24:40.645038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 01:24:40.645142 ==
7774 01:24:40.648982 RX Vref Scan: 1
7775 01:24:40.649083
7776 01:24:40.652003 Set Vref Range= 24 -> 127
7777 01:24:40.652113
7778 01:24:40.652219 RX Vref 24 -> 127, step: 1
7779 01:24:40.652307
7780 01:24:40.655519 RX Delay 11 -> 252, step: 4
7781 01:24:40.655595
7782 01:24:40.658542 Set Vref, RX VrefLevel [Byte0]: 24
7783 01:24:40.661601 [Byte1]: 24
7784 01:24:40.665377
7785 01:24:40.665477 Set Vref, RX VrefLevel [Byte0]: 25
7786 01:24:40.668612 [Byte1]: 25
7787 01:24:40.672587
7788 01:24:40.672688 Set Vref, RX VrefLevel [Byte0]: 26
7789 01:24:40.676185 [Byte1]: 26
7790 01:24:40.680227
7791 01:24:40.680330 Set Vref, RX VrefLevel [Byte0]: 27
7792 01:24:40.683754 [Byte1]: 27
7793 01:24:40.687990
7794 01:24:40.688093 Set Vref, RX VrefLevel [Byte0]: 28
7795 01:24:40.691169 [Byte1]: 28
7796 01:24:40.695290
7797 01:24:40.695430 Set Vref, RX VrefLevel [Byte0]: 29
7798 01:24:40.698965 [Byte1]: 29
7799 01:24:40.702927
7800 01:24:40.703032 Set Vref, RX VrefLevel [Byte0]: 30
7801 01:24:40.706208 [Byte1]: 30
7802 01:24:40.711269
7803 01:24:40.711399 Set Vref, RX VrefLevel [Byte0]: 31
7804 01:24:40.713895 [Byte1]: 31
7805 01:24:40.718235
7806 01:24:40.718344 Set Vref, RX VrefLevel [Byte0]: 32
7807 01:24:40.721627 [Byte1]: 32
7808 01:24:40.725998
7809 01:24:40.726081 Set Vref, RX VrefLevel [Byte0]: 33
7810 01:24:40.729152 [Byte1]: 33
7811 01:24:40.733792
7812 01:24:40.733899 Set Vref, RX VrefLevel [Byte0]: 34
7813 01:24:40.736711 [Byte1]: 34
7814 01:24:40.741148
7815 01:24:40.741222 Set Vref, RX VrefLevel [Byte0]: 35
7816 01:24:40.744441 [Byte1]: 35
7817 01:24:40.748637
7818 01:24:40.748713 Set Vref, RX VrefLevel [Byte0]: 36
7819 01:24:40.752089 [Byte1]: 36
7820 01:24:40.756568
7821 01:24:40.756644 Set Vref, RX VrefLevel [Byte0]: 37
7822 01:24:40.760162 [Byte1]: 37
7823 01:24:40.763858
7824 01:24:40.763932 Set Vref, RX VrefLevel [Byte0]: 38
7825 01:24:40.767604 [Byte1]: 38
7826 01:24:40.771660
7827 01:24:40.771760 Set Vref, RX VrefLevel [Byte0]: 39
7828 01:24:40.774703 [Byte1]: 39
7829 01:24:40.779567
7830 01:24:40.779646 Set Vref, RX VrefLevel [Byte0]: 40
7831 01:24:40.782566 [Byte1]: 40
7832 01:24:40.786603
7833 01:24:40.786681 Set Vref, RX VrefLevel [Byte0]: 41
7834 01:24:40.790071 [Byte1]: 41
7835 01:24:40.794264
7836 01:24:40.794346 Set Vref, RX VrefLevel [Byte0]: 42
7837 01:24:40.797833 [Byte1]: 42
7838 01:24:40.802035
7839 01:24:40.802116 Set Vref, RX VrefLevel [Byte0]: 43
7840 01:24:40.805176 [Byte1]: 43
7841 01:24:40.809953
7842 01:24:40.810034 Set Vref, RX VrefLevel [Byte0]: 44
7843 01:24:40.812725 [Byte1]: 44
7844 01:24:40.817504
7845 01:24:40.817586 Set Vref, RX VrefLevel [Byte0]: 45
7846 01:24:40.820590 [Byte1]: 45
7847 01:24:40.825073
7848 01:24:40.825155 Set Vref, RX VrefLevel [Byte0]: 46
7849 01:24:40.828038 [Byte1]: 46
7850 01:24:40.832479
7851 01:24:40.832561 Set Vref, RX VrefLevel [Byte0]: 47
7852 01:24:40.835756 [Byte1]: 47
7853 01:24:40.840546
7854 01:24:40.840627 Set Vref, RX VrefLevel [Byte0]: 48
7855 01:24:40.843346 [Byte1]: 48
7856 01:24:40.848194
7857 01:24:40.848276 Set Vref, RX VrefLevel [Byte0]: 49
7858 01:24:40.851429 [Byte1]: 49
7859 01:24:40.855622
7860 01:24:40.855704 Set Vref, RX VrefLevel [Byte0]: 50
7861 01:24:40.858857 [Byte1]: 50
7862 01:24:40.863263
7863 01:24:40.863360 Set Vref, RX VrefLevel [Byte0]: 51
7864 01:24:40.867500 [Byte1]: 51
7865 01:24:40.870841
7866 01:24:40.870922 Set Vref, RX VrefLevel [Byte0]: 52
7867 01:24:40.874214 [Byte1]: 52
7868 01:24:40.878374
7869 01:24:40.878455 Set Vref, RX VrefLevel [Byte0]: 53
7870 01:24:40.881515 [Byte1]: 53
7871 01:24:40.885717
7872 01:24:40.885799 Set Vref, RX VrefLevel [Byte0]: 54
7873 01:24:40.889178 [Byte1]: 54
7874 01:24:40.893511
7875 01:24:40.893609 Set Vref, RX VrefLevel [Byte0]: 55
7876 01:24:40.896545 [Byte1]: 55
7877 01:24:40.900916
7878 01:24:40.900998 Set Vref, RX VrefLevel [Byte0]: 56
7879 01:24:40.904494 [Byte1]: 56
7880 01:24:40.908784
7881 01:24:40.908865 Set Vref, RX VrefLevel [Byte0]: 57
7882 01:24:40.911767 [Byte1]: 57
7883 01:24:40.916203
7884 01:24:40.916286 Set Vref, RX VrefLevel [Byte0]: 58
7885 01:24:40.919708 [Byte1]: 58
7886 01:24:40.923721
7887 01:24:40.923802 Set Vref, RX VrefLevel [Byte0]: 59
7888 01:24:40.927290 [Byte1]: 59
7889 01:24:40.931501
7890 01:24:40.931583 Set Vref, RX VrefLevel [Byte0]: 60
7891 01:24:40.934759 [Byte1]: 60
7892 01:24:40.939409
7893 01:24:40.939490 Set Vref, RX VrefLevel [Byte0]: 61
7894 01:24:40.942205 [Byte1]: 61
7895 01:24:40.947247
7896 01:24:40.947331 Set Vref, RX VrefLevel [Byte0]: 62
7897 01:24:40.949988 [Byte1]: 62
7898 01:24:40.954479
7899 01:24:40.954564 Set Vref, RX VrefLevel [Byte0]: 63
7900 01:24:40.958020 [Byte1]: 63
7901 01:24:40.962086
7902 01:24:40.962160 Set Vref, RX VrefLevel [Byte0]: 64
7903 01:24:40.965189 [Byte1]: 64
7904 01:24:40.969680
7905 01:24:40.969758 Set Vref, RX VrefLevel [Byte0]: 65
7906 01:24:40.972768 [Byte1]: 65
7907 01:24:40.977913
7908 01:24:40.977985 Set Vref, RX VrefLevel [Byte0]: 66
7909 01:24:40.980854 [Byte1]: 66
7910 01:24:40.984920
7911 01:24:40.984993 Set Vref, RX VrefLevel [Byte0]: 67
7912 01:24:40.988523 [Byte1]: 67
7913 01:24:40.992416
7914 01:24:40.992488 Set Vref, RX VrefLevel [Byte0]: 68
7915 01:24:40.996077 [Byte1]: 68
7916 01:24:41.000016
7917 01:24:41.000115 Set Vref, RX VrefLevel [Byte0]: 69
7918 01:24:41.003976 [Byte1]: 69
7919 01:24:41.007770
7920 01:24:41.007843 Set Vref, RX VrefLevel [Byte0]: 70
7921 01:24:41.010727 [Byte1]: 70
7922 01:24:41.015218
7923 01:24:41.015308 Set Vref, RX VrefLevel [Byte0]: 71
7924 01:24:41.018753 [Byte1]: 71
7925 01:24:41.022649
7926 01:24:41.022724 Set Vref, RX VrefLevel [Byte0]: 72
7927 01:24:41.026292 [Byte1]: 72
7928 01:24:41.030566
7929 01:24:41.030642 Set Vref, RX VrefLevel [Byte0]: 73
7930 01:24:41.033782 [Byte1]: 73
7931 01:24:41.038137
7932 01:24:41.038235 Set Vref, RX VrefLevel [Byte0]: 74
7933 01:24:41.041413 [Byte1]: 74
7934 01:24:41.045824
7935 01:24:41.045905 Final RX Vref Byte 0 = 62 to rank0
7936 01:24:41.049038 Final RX Vref Byte 1 = 61 to rank0
7937 01:24:41.052009 Final RX Vref Byte 0 = 62 to rank1
7938 01:24:41.055762 Final RX Vref Byte 1 = 61 to rank1==
7939 01:24:41.058631 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 01:24:41.065814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 01:24:41.065896 ==
7942 01:24:41.065960 DQS Delay:
7943 01:24:41.069193 DQS0 = 0, DQS1 = 0
7944 01:24:41.069276 DQM Delay:
7945 01:24:41.069341 DQM0 = 126, DQM1 = 119
7946 01:24:41.072403 DQ Delay:
7947 01:24:41.075895 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7948 01:24:41.079153 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7949 01:24:41.082060 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7950 01:24:41.085499 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7951 01:24:41.085581
7952 01:24:41.085645
7953 01:24:41.085704
7954 01:24:41.088470 [DramC_TX_OE_Calibration] TA2
7955 01:24:41.092029 Original DQ_B0 (3 6) =30, OEN = 27
7956 01:24:41.095645 Original DQ_B1 (3 6) =30, OEN = 27
7957 01:24:41.098766 24, 0x0, End_B0=24 End_B1=24
7958 01:24:41.098848 25, 0x0, End_B0=25 End_B1=25
7959 01:24:41.102025 26, 0x0, End_B0=26 End_B1=26
7960 01:24:41.105582 27, 0x0, End_B0=27 End_B1=27
7961 01:24:41.108627 28, 0x0, End_B0=28 End_B1=28
7962 01:24:41.112190 29, 0x0, End_B0=29 End_B1=29
7963 01:24:41.112273 30, 0x0, End_B0=30 End_B1=30
7964 01:24:41.115314 31, 0x4141, End_B0=30 End_B1=30
7965 01:24:41.118330 Byte0 end_step=30 best_step=27
7966 01:24:41.121655 Byte1 end_step=30 best_step=27
7967 01:24:41.125069 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 01:24:41.128496 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 01:24:41.128578
7970 01:24:41.128642
7971 01:24:41.135109 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7972 01:24:41.138172 CH0 RK0: MR19=303, MR18=1212
7973 01:24:41.145296 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
7974 01:24:41.145378
7975 01:24:41.148043 ----->DramcWriteLeveling(PI) begin...
7976 01:24:41.148127 ==
7977 01:24:41.151869 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 01:24:41.154751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 01:24:41.154833 ==
7980 01:24:41.157997 Write leveling (Byte 0): 33 => 33
7981 01:24:41.161504 Write leveling (Byte 1): 27 => 27
7982 01:24:41.164654 DramcWriteLeveling(PI) end<-----
7983 01:24:41.164736
7984 01:24:41.164801 ==
7985 01:24:41.168323 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 01:24:41.171615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 01:24:41.171696 ==
7988 01:24:41.174974 [Gating] SW mode calibration
7989 01:24:41.181517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 01:24:41.188419 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 01:24:41.191296 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 01:24:41.197902 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 01:24:41.201357 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 01:24:41.204725 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7995 01:24:41.211294 1 4 16 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
7996 01:24:41.214977 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7997 01:24:41.217741 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 01:24:41.224657 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 01:24:41.227912 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 01:24:41.231516 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 01:24:41.237779 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8002 01:24:41.240749 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8003 01:24:41.244310 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8004 01:24:41.250819 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8005 01:24:41.254408 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 01:24:41.257296 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 01:24:41.264540 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 01:24:41.267340 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 01:24:41.270552 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8010 01:24:41.277411 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8011 01:24:41.280667 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8012 01:24:41.283927 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 01:24:41.290810 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 01:24:41.293776 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 01:24:41.297094 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 01:24:41.303845 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 01:24:41.306831 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 01:24:41.310516 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8019 01:24:41.314082 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 01:24:41.320632 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 01:24:41.323827 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 01:24:41.327191 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 01:24:41.333897 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 01:24:41.336830 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 01:24:41.340190 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 01:24:41.346736 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 01:24:41.350377 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 01:24:41.353689 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 01:24:41.360446 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 01:24:41.363330 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 01:24:41.366897 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 01:24:41.373373 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 01:24:41.376679 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 01:24:41.380192 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8035 01:24:41.386346 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8036 01:24:41.390278 Total UI for P1: 0, mck2ui 16
8037 01:24:41.393431 best dqsien dly found for B0: ( 1, 9, 10)
8038 01:24:41.396847 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 01:24:41.399727 Total UI for P1: 0, mck2ui 16
8040 01:24:41.403003 best dqsien dly found for B1: ( 1, 9, 16)
8041 01:24:41.406591 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8042 01:24:41.409759 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8043 01:24:41.409841
8044 01:24:41.413021 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8045 01:24:41.416090 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8046 01:24:41.419267 [Gating] SW calibration Done
8047 01:24:41.419350 ==
8048 01:24:41.422625 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 01:24:41.429637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 01:24:41.429720 ==
8051 01:24:41.429784 RX Vref Scan: 0
8052 01:24:41.429845
8053 01:24:41.432876 RX Vref 0 -> 0, step: 1
8054 01:24:41.432958
8055 01:24:41.436021 RX Delay 0 -> 252, step: 8
8056 01:24:41.439216 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8057 01:24:41.442842 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8058 01:24:41.446229 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8059 01:24:41.449355 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8060 01:24:41.456151 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8061 01:24:41.459404 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8062 01:24:41.462766 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8063 01:24:41.465737 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8064 01:24:41.469426 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8065 01:24:41.475846 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8066 01:24:41.479200 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8067 01:24:41.482459 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8068 01:24:41.485831 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8069 01:24:41.492191 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8070 01:24:41.495480 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8071 01:24:41.499122 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8072 01:24:41.499204 ==
8073 01:24:41.502469 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 01:24:41.505555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 01:24:41.505638 ==
8076 01:24:41.509035 DQS Delay:
8077 01:24:41.509116 DQS0 = 0, DQS1 = 0
8078 01:24:41.512590 DQM Delay:
8079 01:24:41.512672 DQM0 = 128, DQM1 = 122
8080 01:24:41.512736 DQ Delay:
8081 01:24:41.515607 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8082 01:24:41.522288 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8083 01:24:41.525338 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8084 01:24:41.529144 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8085 01:24:41.529226
8086 01:24:41.529291
8087 01:24:41.529351 ==
8088 01:24:41.532582 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 01:24:41.535350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 01:24:41.535438 ==
8091 01:24:41.535503
8092 01:24:41.535563
8093 01:24:41.539001 TX Vref Scan disable
8094 01:24:41.541938 == TX Byte 0 ==
8095 01:24:41.545493 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8096 01:24:41.548803 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8097 01:24:41.552343 == TX Byte 1 ==
8098 01:24:41.555298 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8099 01:24:41.558607 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8100 01:24:41.558689 ==
8101 01:24:41.562498 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 01:24:41.565507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 01:24:41.568462 ==
8104 01:24:41.581378
8105 01:24:41.585279 TX Vref early break, caculate TX vref
8106 01:24:41.588182 TX Vref=16, minBit 0, minWin=22, winSum=363
8107 01:24:41.591575 TX Vref=18, minBit 8, minWin=22, winSum=373
8108 01:24:41.594777 TX Vref=20, minBit 8, minWin=22, winSum=382
8109 01:24:41.598033 TX Vref=22, minBit 1, minWin=23, winSum=388
8110 01:24:41.601632 TX Vref=24, minBit 0, minWin=24, winSum=399
8111 01:24:41.607693 TX Vref=26, minBit 8, minWin=24, winSum=402
8112 01:24:41.611159 TX Vref=28, minBit 1, minWin=24, winSum=405
8113 01:24:41.614494 TX Vref=30, minBit 8, minWin=24, winSum=406
8114 01:24:41.617978 TX Vref=32, minBit 8, minWin=22, winSum=394
8115 01:24:41.621036 TX Vref=34, minBit 8, minWin=22, winSum=389
8116 01:24:41.624370 TX Vref=36, minBit 8, minWin=21, winSum=372
8117 01:24:41.631113 [TxChooseVref] Worse bit 8, Min win 24, Win sum 406, Final Vref 30
8118 01:24:41.631197
8119 01:24:41.634387 Final TX Range 0 Vref 30
8120 01:24:41.634471
8121 01:24:41.634535 ==
8122 01:24:41.637773 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 01:24:41.641050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 01:24:41.641132 ==
8125 01:24:41.641197
8126 01:24:41.644273
8127 01:24:41.644355 TX Vref Scan disable
8128 01:24:41.651478 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8129 01:24:41.651560 == TX Byte 0 ==
8130 01:24:41.654374 u2DelayCellOfst[0]=15 cells (4 PI)
8131 01:24:41.657492 u2DelayCellOfst[1]=18 cells (5 PI)
8132 01:24:41.660961 u2DelayCellOfst[2]=11 cells (3 PI)
8133 01:24:41.664041 u2DelayCellOfst[3]=11 cells (3 PI)
8134 01:24:41.667842 u2DelayCellOfst[4]=7 cells (2 PI)
8135 01:24:41.671121 u2DelayCellOfst[5]=0 cells (0 PI)
8136 01:24:41.674035 u2DelayCellOfst[6]=18 cells (5 PI)
8137 01:24:41.677631 u2DelayCellOfst[7]=18 cells (5 PI)
8138 01:24:41.681095 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8139 01:24:41.684089 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8140 01:24:41.687392 == TX Byte 1 ==
8141 01:24:41.691176 u2DelayCellOfst[8]=0 cells (0 PI)
8142 01:24:41.693991 u2DelayCellOfst[9]=3 cells (1 PI)
8143 01:24:41.697606 u2DelayCellOfst[10]=11 cells (3 PI)
8144 01:24:41.697687 u2DelayCellOfst[11]=3 cells (1 PI)
8145 01:24:41.700585 u2DelayCellOfst[12]=15 cells (4 PI)
8146 01:24:41.704182 u2DelayCellOfst[13]=11 cells (3 PI)
8147 01:24:41.707573 u2DelayCellOfst[14]=18 cells (5 PI)
8148 01:24:41.711174 u2DelayCellOfst[15]=11 cells (3 PI)
8149 01:24:41.717122 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8150 01:24:41.720581 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8151 01:24:41.720663 DramC Write-DBI on
8152 01:24:41.720727 ==
8153 01:24:41.723809 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 01:24:41.731183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 01:24:41.731305 ==
8156 01:24:41.731447
8157 01:24:41.731572
8158 01:24:41.731635 TX Vref Scan disable
8159 01:24:41.734892 == TX Byte 0 ==
8160 01:24:41.738177 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8161 01:24:41.741454 == TX Byte 1 ==
8162 01:24:41.744864 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8163 01:24:41.744946 DramC Write-DBI off
8164 01:24:41.748494
8165 01:24:41.748576 [DATLAT]
8166 01:24:41.748640 Freq=1600, CH0 RK1
8167 01:24:41.748700
8168 01:24:41.751848 DATLAT Default: 0xf
8169 01:24:41.751929 0, 0xFFFF, sum = 0
8170 01:24:41.754850 1, 0xFFFF, sum = 0
8171 01:24:41.754933 2, 0xFFFF, sum = 0
8172 01:24:41.758053 3, 0xFFFF, sum = 0
8173 01:24:41.761289 4, 0xFFFF, sum = 0
8174 01:24:41.761372 5, 0xFFFF, sum = 0
8175 01:24:41.765261 6, 0xFFFF, sum = 0
8176 01:24:41.765344 7, 0xFFFF, sum = 0
8177 01:24:41.768132 8, 0xFFFF, sum = 0
8178 01:24:41.768215 9, 0xFFFF, sum = 0
8179 01:24:41.771769 10, 0xFFFF, sum = 0
8180 01:24:41.771852 11, 0xFFFF, sum = 0
8181 01:24:41.775167 12, 0xFFFF, sum = 0
8182 01:24:41.775250 13, 0xCFFF, sum = 0
8183 01:24:41.778159 14, 0x0, sum = 1
8184 01:24:41.778265 15, 0x0, sum = 2
8185 01:24:41.781553 16, 0x0, sum = 3
8186 01:24:41.781636 17, 0x0, sum = 4
8187 01:24:41.784854 best_step = 15
8188 01:24:41.784935
8189 01:24:41.784999 ==
8190 01:24:41.788262 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 01:24:41.791772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 01:24:41.791854 ==
8193 01:24:41.791918 RX Vref Scan: 0
8194 01:24:41.794886
8195 01:24:41.794967 RX Vref 0 -> 0, step: 1
8196 01:24:41.795031
8197 01:24:41.798207 RX Delay 3 -> 252, step: 4
8198 01:24:41.801618 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8199 01:24:41.808153 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8200 01:24:41.811844 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8201 01:24:41.815152 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8202 01:24:41.818281 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8203 01:24:41.821146 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8204 01:24:41.827941 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8205 01:24:41.831494 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8206 01:24:41.834744 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8207 01:24:41.838113 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8208 01:24:41.840881 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8209 01:24:41.847875 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8210 01:24:41.851289 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8211 01:24:41.854525 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8212 01:24:41.857767 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8213 01:24:41.864397 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8214 01:24:41.864474 ==
8215 01:24:41.867351 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 01:24:41.870593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 01:24:41.870671 ==
8218 01:24:41.870732 DQS Delay:
8219 01:24:41.874221 DQS0 = 0, DQS1 = 0
8220 01:24:41.874289 DQM Delay:
8221 01:24:41.877751 DQM0 = 124, DQM1 = 117
8222 01:24:41.877819 DQ Delay:
8223 01:24:41.881311 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8224 01:24:41.884017 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8225 01:24:41.887303 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8226 01:24:41.890625 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8227 01:24:41.890698
8228 01:24:41.890765
8229 01:24:41.893798
8230 01:24:41.893875 [DramC_TX_OE_Calibration] TA2
8231 01:24:41.897330 Original DQ_B0 (3 6) =30, OEN = 27
8232 01:24:41.900446 Original DQ_B1 (3 6) =30, OEN = 27
8233 01:24:41.903959 24, 0x0, End_B0=24 End_B1=24
8234 01:24:41.907224 25, 0x0, End_B0=25 End_B1=25
8235 01:24:41.910157 26, 0x0, End_B0=26 End_B1=26
8236 01:24:41.910240 27, 0x0, End_B0=27 End_B1=27
8237 01:24:41.913435 28, 0x0, End_B0=28 End_B1=28
8238 01:24:41.916920 29, 0x0, End_B0=29 End_B1=29
8239 01:24:41.920254 30, 0x0, End_B0=30 End_B1=30
8240 01:24:41.923319 31, 0x4141, End_B0=30 End_B1=30
8241 01:24:41.923441 Byte0 end_step=30 best_step=27
8242 01:24:41.926756 Byte1 end_step=30 best_step=27
8243 01:24:41.930297 Byte0 TX OE(2T, 0.5T) = (3, 3)
8244 01:24:41.933426 Byte1 TX OE(2T, 0.5T) = (3, 3)
8245 01:24:41.933508
8246 01:24:41.933572
8247 01:24:41.943367 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8248 01:24:41.943470 CH0 RK1: MR19=303, MR18=210F
8249 01:24:41.950196 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8250 01:24:41.953216 [RxdqsGatingPostProcess] freq 1600
8251 01:24:41.959885 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8252 01:24:41.963343 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 01:24:41.966549 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 01:24:41.966631 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 01:24:41.970014 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 01:24:41.973111 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 01:24:41.976799 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 01:24:41.980158 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 01:24:41.983202 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 01:24:41.986774 Pre-setting of DQS Precalculation
8261 01:24:41.993394 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8262 01:24:41.993472 ==
8263 01:24:41.996362 Dram Type= 6, Freq= 0, CH_1, rank 0
8264 01:24:42.000023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 01:24:42.000097 ==
8266 01:24:42.006766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8267 01:24:42.010140 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8268 01:24:42.012836 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8269 01:24:42.019700 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8270 01:24:42.027792 [CA 0] Center 42 (13~71) winsize 59
8271 01:24:42.031256 [CA 1] Center 42 (12~72) winsize 61
8272 01:24:42.034634 [CA 2] Center 37 (9~66) winsize 58
8273 01:24:42.038524 [CA 3] Center 36 (7~66) winsize 60
8274 01:24:42.041412 [CA 4] Center 37 (8~67) winsize 60
8275 01:24:42.044457 [CA 5] Center 37 (8~66) winsize 59
8276 01:24:42.044538
8277 01:24:42.048225 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8278 01:24:42.048303
8279 01:24:42.051516 [CATrainingPosCal] consider 1 rank data
8280 01:24:42.054794 u2DelayCellTimex100 = 258/100 ps
8281 01:24:42.057996 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8282 01:24:42.064429 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8283 01:24:42.068199 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8284 01:24:42.071062 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8285 01:24:42.074223 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8286 01:24:42.077832 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8287 01:24:42.077907
8288 01:24:42.081273 CA PerBit enable=1, Macro0, CA PI delay=36
8289 01:24:42.081347
8290 01:24:42.084204 [CBTSetCACLKResult] CA Dly = 36
8291 01:24:42.087781 CS Dly: 9 (0~40)
8292 01:24:42.090783 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8293 01:24:42.094210 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8294 01:24:42.094289 ==
8295 01:24:42.097561 Dram Type= 6, Freq= 0, CH_1, rank 1
8296 01:24:42.101118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 01:24:42.104052 ==
8298 01:24:42.107490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 01:24:42.110815 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 01:24:42.117265 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 01:24:42.124170 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 01:24:42.131261 [CA 0] Center 42 (13~71) winsize 59
8303 01:24:42.134443 [CA 1] Center 42 (12~72) winsize 61
8304 01:24:42.137747 [CA 2] Center 38 (9~67) winsize 59
8305 01:24:42.141570 [CA 3] Center 36 (7~66) winsize 60
8306 01:24:42.144811 [CA 4] Center 38 (8~68) winsize 61
8307 01:24:42.148024 [CA 5] Center 37 (7~67) winsize 61
8308 01:24:42.148098
8309 01:24:42.151460 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8310 01:24:42.151539
8311 01:24:42.154397 [CATrainingPosCal] consider 2 rank data
8312 01:24:42.157722 u2DelayCellTimex100 = 258/100 ps
8313 01:24:42.160999 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8314 01:24:42.167573 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8315 01:24:42.171130 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8316 01:24:42.174524 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 01:24:42.178146 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8318 01:24:42.181182 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8319 01:24:42.181260
8320 01:24:42.184438 CA PerBit enable=1, Macro0, CA PI delay=36
8321 01:24:42.184520
8322 01:24:42.187564 [CBTSetCACLKResult] CA Dly = 36
8323 01:24:42.191072 CS Dly: 10 (0~43)
8324 01:24:42.194272 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 01:24:42.197399 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 01:24:42.197481
8327 01:24:42.200630 ----->DramcWriteLeveling(PI) begin...
8328 01:24:42.200712 ==
8329 01:24:42.204287 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 01:24:42.210643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 01:24:42.210724 ==
8332 01:24:42.214035 Write leveling (Byte 0): 25 => 25
8333 01:24:42.214117 Write leveling (Byte 1): 31 => 31
8334 01:24:42.217521 DramcWriteLeveling(PI) end<-----
8335 01:24:42.217602
8336 01:24:42.217666 ==
8337 01:24:42.221093 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 01:24:42.227410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 01:24:42.227506 ==
8340 01:24:42.230864 [Gating] SW mode calibration
8341 01:24:42.237342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8342 01:24:42.240813 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8343 01:24:42.247031 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 01:24:42.250350 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 01:24:42.254096 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 01:24:42.260637 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 01:24:42.263970 1 4 16 | B1->B0 | 3333 3232 | 1 0 | (0 0) (0 0)
8348 01:24:42.266911 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 01:24:42.273399 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 01:24:42.276973 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 01:24:42.280167 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 01:24:42.287085 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 01:24:42.290108 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 01:24:42.293337 1 5 12 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
8355 01:24:42.300140 1 5 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
8356 01:24:42.303198 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8357 01:24:42.306366 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 01:24:42.313515 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 01:24:42.316680 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 01:24:42.319634 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 01:24:42.326917 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 01:24:42.329988 1 6 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8363 01:24:42.333362 1 6 16 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
8364 01:24:42.339845 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 01:24:42.342894 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 01:24:42.346310 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 01:24:42.349873 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 01:24:42.356538 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 01:24:42.359654 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 01:24:42.363179 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 01:24:42.369488 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 01:24:42.373162 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8373 01:24:42.376037 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 01:24:42.382995 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 01:24:42.385835 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 01:24:42.389215 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 01:24:42.395916 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 01:24:42.399287 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 01:24:42.402489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 01:24:42.409383 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 01:24:42.412878 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 01:24:42.416040 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 01:24:42.422693 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 01:24:42.425577 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 01:24:42.429446 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 01:24:42.435769 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8387 01:24:42.438851 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 01:24:42.442574 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 01:24:42.445891 Total UI for P1: 0, mck2ui 16
8390 01:24:42.448836 best dqsien dly found for B0: ( 1, 9, 16)
8391 01:24:42.452263 Total UI for P1: 0, mck2ui 16
8392 01:24:42.455280 best dqsien dly found for B1: ( 1, 9, 14)
8393 01:24:42.459116 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8394 01:24:42.462084 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8395 01:24:42.462158
8396 01:24:42.468945 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8397 01:24:42.472347 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8398 01:24:42.475215 [Gating] SW calibration Done
8399 01:24:42.475288 ==
8400 01:24:42.478576 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 01:24:42.482191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 01:24:42.482272 ==
8403 01:24:42.482335 RX Vref Scan: 0
8404 01:24:42.485430
8405 01:24:42.485508 RX Vref 0 -> 0, step: 1
8406 01:24:42.485568
8407 01:24:42.488735 RX Delay 0 -> 252, step: 8
8408 01:24:42.492002 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8409 01:24:42.495048 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8410 01:24:42.502064 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8411 01:24:42.505521 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8412 01:24:42.508389 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8413 01:24:42.511715 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8414 01:24:42.515274 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8415 01:24:42.522341 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8416 01:24:42.525389 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8417 01:24:42.528621 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8418 01:24:42.531828 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8419 01:24:42.534767 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8420 01:24:42.541520 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8421 01:24:42.544963 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8422 01:24:42.548677 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8423 01:24:42.552117 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8424 01:24:42.552192 ==
8425 01:24:42.554752 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 01:24:42.561393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 01:24:42.561470 ==
8428 01:24:42.561532 DQS Delay:
8429 01:24:42.564832 DQS0 = 0, DQS1 = 0
8430 01:24:42.564904 DQM Delay:
8431 01:24:42.568378 DQM0 = 132, DQM1 = 126
8432 01:24:42.568449 DQ Delay:
8433 01:24:42.571640 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8434 01:24:42.574647 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8435 01:24:42.577924 DQ8 =111, DQ9 =119, DQ10 =123, DQ11 =119
8436 01:24:42.581458 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8437 01:24:42.581534
8438 01:24:42.581596
8439 01:24:42.581662 ==
8440 01:24:42.584886 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 01:24:42.591382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 01:24:42.591459 ==
8443 01:24:42.591531
8444 01:24:42.591590
8445 01:24:42.591648 TX Vref Scan disable
8446 01:24:42.594755 == TX Byte 0 ==
8447 01:24:42.597735 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8448 01:24:42.601086 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8449 01:24:42.604832 == TX Byte 1 ==
8450 01:24:42.608215 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8451 01:24:42.614649 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8452 01:24:42.614731 ==
8453 01:24:42.617413 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 01:24:42.621110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 01:24:42.621187 ==
8456 01:24:42.633968
8457 01:24:42.636988 TX Vref early break, caculate TX vref
8458 01:24:42.640409 TX Vref=16, minBit 8, minWin=21, winSum=359
8459 01:24:42.643727 TX Vref=18, minBit 11, minWin=21, winSum=366
8460 01:24:42.647151 TX Vref=20, minBit 8, minWin=22, winSum=380
8461 01:24:42.650170 TX Vref=22, minBit 8, minWin=22, winSum=387
8462 01:24:42.654008 TX Vref=24, minBit 8, minWin=23, winSum=394
8463 01:24:42.659935 TX Vref=26, minBit 0, minWin=25, winSum=411
8464 01:24:42.663303 TX Vref=28, minBit 6, minWin=24, winSum=410
8465 01:24:42.667127 TX Vref=30, minBit 6, minWin=24, winSum=404
8466 01:24:42.670205 TX Vref=32, minBit 0, minWin=23, winSum=399
8467 01:24:42.673767 TX Vref=34, minBit 1, minWin=23, winSum=389
8468 01:24:42.680027 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 26
8469 01:24:42.680107
8470 01:24:42.683164 Final TX Range 0 Vref 26
8471 01:24:42.683237
8472 01:24:42.683297 ==
8473 01:24:42.686728 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 01:24:42.689877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 01:24:42.689947 ==
8476 01:24:42.690014
8477 01:24:42.690072
8478 01:24:42.693581 TX Vref Scan disable
8479 01:24:42.700160 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8480 01:24:42.700241 == TX Byte 0 ==
8481 01:24:42.702994 u2DelayCellOfst[0]=22 cells (6 PI)
8482 01:24:42.706621 u2DelayCellOfst[1]=15 cells (4 PI)
8483 01:24:42.709525 u2DelayCellOfst[2]=0 cells (0 PI)
8484 01:24:42.712969 u2DelayCellOfst[3]=7 cells (2 PI)
8485 01:24:42.716535 u2DelayCellOfst[4]=11 cells (3 PI)
8486 01:24:42.719396 u2DelayCellOfst[5]=22 cells (6 PI)
8487 01:24:42.722781 u2DelayCellOfst[6]=22 cells (6 PI)
8488 01:24:42.726215 u2DelayCellOfst[7]=7 cells (2 PI)
8489 01:24:42.729815 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8490 01:24:42.732827 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8491 01:24:42.736361 == TX Byte 1 ==
8492 01:24:42.739716 u2DelayCellOfst[8]=0 cells (0 PI)
8493 01:24:42.742561 u2DelayCellOfst[9]=11 cells (3 PI)
8494 01:24:42.742646 u2DelayCellOfst[10]=15 cells (4 PI)
8495 01:24:42.746031 u2DelayCellOfst[11]=7 cells (2 PI)
8496 01:24:42.749111 u2DelayCellOfst[12]=15 cells (4 PI)
8497 01:24:42.753025 u2DelayCellOfst[13]=18 cells (5 PI)
8498 01:24:42.756054 u2DelayCellOfst[14]=18 cells (5 PI)
8499 01:24:42.759255 u2DelayCellOfst[15]=18 cells (5 PI)
8500 01:24:42.765555 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8501 01:24:42.769492 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8502 01:24:42.769569 DramC Write-DBI on
8503 01:24:42.769633 ==
8504 01:24:42.772381 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 01:24:42.778856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 01:24:42.778940 ==
8507 01:24:42.779005
8508 01:24:42.779065
8509 01:24:42.779124 TX Vref Scan disable
8510 01:24:42.783555 == TX Byte 0 ==
8511 01:24:42.786364 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8512 01:24:42.789899 == TX Byte 1 ==
8513 01:24:42.793570 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8514 01:24:42.796406 DramC Write-DBI off
8515 01:24:42.796487
8516 01:24:42.796551 [DATLAT]
8517 01:24:42.796610 Freq=1600, CH1 RK0
8518 01:24:42.796669
8519 01:24:42.799716 DATLAT Default: 0xf
8520 01:24:42.799805 0, 0xFFFF, sum = 0
8521 01:24:42.803094 1, 0xFFFF, sum = 0
8522 01:24:42.806611 2, 0xFFFF, sum = 0
8523 01:24:42.806692 3, 0xFFFF, sum = 0
8524 01:24:42.809752 4, 0xFFFF, sum = 0
8525 01:24:42.809830 5, 0xFFFF, sum = 0
8526 01:24:42.813004 6, 0xFFFF, sum = 0
8527 01:24:42.813082 7, 0xFFFF, sum = 0
8528 01:24:42.816396 8, 0xFFFF, sum = 0
8529 01:24:42.816478 9, 0xFFFF, sum = 0
8530 01:24:42.819894 10, 0xFFFF, sum = 0
8531 01:24:42.820010 11, 0xFFFF, sum = 0
8532 01:24:42.822762 12, 0xFFFF, sum = 0
8533 01:24:42.822866 13, 0x8FFF, sum = 0
8534 01:24:42.826349 14, 0x0, sum = 1
8535 01:24:42.826452 15, 0x0, sum = 2
8536 01:24:42.829552 16, 0x0, sum = 3
8537 01:24:42.829634 17, 0x0, sum = 4
8538 01:24:42.833544 best_step = 15
8539 01:24:42.833657
8540 01:24:42.833749 ==
8541 01:24:42.836248 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 01:24:42.839969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 01:24:42.840051 ==
8544 01:24:42.842923 RX Vref Scan: 1
8545 01:24:42.843029
8546 01:24:42.843120 Set Vref Range= 24 -> 127
8547 01:24:42.843207
8548 01:24:42.846276 RX Vref 24 -> 127, step: 1
8549 01:24:42.846375
8550 01:24:42.850013 RX Delay 11 -> 252, step: 4
8551 01:24:42.850121
8552 01:24:42.852881 Set Vref, RX VrefLevel [Byte0]: 24
8553 01:24:42.856293 [Byte1]: 24
8554 01:24:42.856372
8555 01:24:42.859530 Set Vref, RX VrefLevel [Byte0]: 25
8556 01:24:42.862808 [Byte1]: 25
8557 01:24:42.866336
8558 01:24:42.866408 Set Vref, RX VrefLevel [Byte0]: 26
8559 01:24:42.869190 [Byte1]: 26
8560 01:24:42.873755
8561 01:24:42.873856 Set Vref, RX VrefLevel [Byte0]: 27
8562 01:24:42.876758 [Byte1]: 27
8563 01:24:42.881632
8564 01:24:42.881704 Set Vref, RX VrefLevel [Byte0]: 28
8565 01:24:42.884233 [Byte1]: 28
8566 01:24:42.889075
8567 01:24:42.889153 Set Vref, RX VrefLevel [Byte0]: 29
8568 01:24:42.892352 [Byte1]: 29
8569 01:24:42.896154
8570 01:24:42.896244 Set Vref, RX VrefLevel [Byte0]: 30
8571 01:24:42.899744 [Byte1]: 30
8572 01:24:42.904098
8573 01:24:42.904206 Set Vref, RX VrefLevel [Byte0]: 31
8574 01:24:42.907479 [Byte1]: 31
8575 01:24:42.911717
8576 01:24:42.911806 Set Vref, RX VrefLevel [Byte0]: 32
8577 01:24:42.915202 [Byte1]: 32
8578 01:24:42.918971
8579 01:24:42.919054 Set Vref, RX VrefLevel [Byte0]: 33
8580 01:24:42.922408 [Byte1]: 33
8581 01:24:42.926752
8582 01:24:42.926846 Set Vref, RX VrefLevel [Byte0]: 34
8583 01:24:42.930195 [Byte1]: 34
8584 01:24:42.934344
8585 01:24:42.934421 Set Vref, RX VrefLevel [Byte0]: 35
8586 01:24:42.937602 [Byte1]: 35
8587 01:24:42.942447
8588 01:24:42.942529 Set Vref, RX VrefLevel [Byte0]: 36
8589 01:24:42.945322 [Byte1]: 36
8590 01:24:42.949508
8591 01:24:42.949615 Set Vref, RX VrefLevel [Byte0]: 37
8592 01:24:42.952821 [Byte1]: 37
8593 01:24:42.957341
8594 01:24:42.957449 Set Vref, RX VrefLevel [Byte0]: 38
8595 01:24:42.960370 [Byte1]: 38
8596 01:24:42.965399
8597 01:24:42.965551 Set Vref, RX VrefLevel [Byte0]: 39
8598 01:24:42.968237 [Byte1]: 39
8599 01:24:42.972378
8600 01:24:42.972470 Set Vref, RX VrefLevel [Byte0]: 40
8601 01:24:42.975693 [Byte1]: 40
8602 01:24:42.980383
8603 01:24:42.980478 Set Vref, RX VrefLevel [Byte0]: 41
8604 01:24:42.983231 [Byte1]: 41
8605 01:24:42.988335
8606 01:24:42.988417 Set Vref, RX VrefLevel [Byte0]: 42
8607 01:24:42.991143 [Byte1]: 42
8608 01:24:42.995137
8609 01:24:42.995214 Set Vref, RX VrefLevel [Byte0]: 43
8610 01:24:42.998494 [Byte1]: 43
8611 01:24:43.003518
8612 01:24:43.003597 Set Vref, RX VrefLevel [Byte0]: 44
8613 01:24:43.006248 [Byte1]: 44
8614 01:24:43.010862
8615 01:24:43.011009 Set Vref, RX VrefLevel [Byte0]: 45
8616 01:24:43.013811 [Byte1]: 45
8617 01:24:43.018245
8618 01:24:43.018319 Set Vref, RX VrefLevel [Byte0]: 46
8619 01:24:43.021726 [Byte1]: 46
8620 01:24:43.026268
8621 01:24:43.026375 Set Vref, RX VrefLevel [Byte0]: 47
8622 01:24:43.029217 [Byte1]: 47
8623 01:24:43.033178
8624 01:24:43.033254 Set Vref, RX VrefLevel [Byte0]: 48
8625 01:24:43.037031 [Byte1]: 48
8626 01:24:43.041364
8627 01:24:43.041439 Set Vref, RX VrefLevel [Byte0]: 49
8628 01:24:43.044556 [Byte1]: 49
8629 01:24:43.048800
8630 01:24:43.048903 Set Vref, RX VrefLevel [Byte0]: 50
8631 01:24:43.052389 [Byte1]: 50
8632 01:24:43.056138
8633 01:24:43.056216 Set Vref, RX VrefLevel [Byte0]: 51
8634 01:24:43.059778 [Byte1]: 51
8635 01:24:43.063816
8636 01:24:43.063902 Set Vref, RX VrefLevel [Byte0]: 52
8637 01:24:43.067411 [Byte1]: 52
8638 01:24:43.071301
8639 01:24:43.071420 Set Vref, RX VrefLevel [Byte0]: 53
8640 01:24:43.074941 [Byte1]: 53
8641 01:24:43.078926
8642 01:24:43.079002 Set Vref, RX VrefLevel [Byte0]: 54
8643 01:24:43.082525 [Byte1]: 54
8644 01:24:43.086499
8645 01:24:43.086579 Set Vref, RX VrefLevel [Byte0]: 55
8646 01:24:43.090257 [Byte1]: 55
8647 01:24:43.094514
8648 01:24:43.094615 Set Vref, RX VrefLevel [Byte0]: 56
8649 01:24:43.097762 [Byte1]: 56
8650 01:24:43.102292
8651 01:24:43.102365 Set Vref, RX VrefLevel [Byte0]: 57
8652 01:24:43.105499 [Byte1]: 57
8653 01:24:43.109594
8654 01:24:43.109664 Set Vref, RX VrefLevel [Byte0]: 58
8655 01:24:43.113307 [Byte1]: 58
8656 01:24:43.117100
8657 01:24:43.117181 Set Vref, RX VrefLevel [Byte0]: 59
8658 01:24:43.120694 [Byte1]: 59
8659 01:24:43.124817
8660 01:24:43.124900 Set Vref, RX VrefLevel [Byte0]: 60
8661 01:24:43.128335 [Byte1]: 60
8662 01:24:43.132218
8663 01:24:43.132295 Set Vref, RX VrefLevel [Byte0]: 61
8664 01:24:43.135504 [Byte1]: 61
8665 01:24:43.139990
8666 01:24:43.140068 Set Vref, RX VrefLevel [Byte0]: 62
8667 01:24:43.143036 [Byte1]: 62
8668 01:24:43.147644
8669 01:24:43.147719 Set Vref, RX VrefLevel [Byte0]: 63
8670 01:24:43.150780 [Byte1]: 63
8671 01:24:43.155433
8672 01:24:43.155530 Set Vref, RX VrefLevel [Byte0]: 64
8673 01:24:43.158740 [Byte1]: 64
8674 01:24:43.162944
8675 01:24:43.163019 Set Vref, RX VrefLevel [Byte0]: 65
8676 01:24:43.165810 [Byte1]: 65
8677 01:24:43.170366
8678 01:24:43.170465 Set Vref, RX VrefLevel [Byte0]: 66
8679 01:24:43.173541 [Byte1]: 66
8680 01:24:43.177833
8681 01:24:43.177915 Set Vref, RX VrefLevel [Byte0]: 67
8682 01:24:43.181413 [Byte1]: 67
8683 01:24:43.185423
8684 01:24:43.185508 Set Vref, RX VrefLevel [Byte0]: 68
8685 01:24:43.188723 [Byte1]: 68
8686 01:24:43.193482
8687 01:24:43.193552 Set Vref, RX VrefLevel [Byte0]: 69
8688 01:24:43.196344 [Byte1]: 69
8689 01:24:43.200811
8690 01:24:43.200914 Set Vref, RX VrefLevel [Byte0]: 70
8691 01:24:43.204413 [Byte1]: 70
8692 01:24:43.208611
8693 01:24:43.208685 Set Vref, RX VrefLevel [Byte0]: 71
8694 01:24:43.212224 [Byte1]: 71
8695 01:24:43.216418
8696 01:24:43.216527 Final RX Vref Byte 0 = 57 to rank0
8697 01:24:43.219218 Final RX Vref Byte 1 = 54 to rank0
8698 01:24:43.222987 Final RX Vref Byte 0 = 57 to rank1
8699 01:24:43.225787 Final RX Vref Byte 1 = 54 to rank1==
8700 01:24:43.229206 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 01:24:43.236185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 01:24:43.236264 ==
8703 01:24:43.236329 DQS Delay:
8704 01:24:43.236397 DQS0 = 0, DQS1 = 0
8705 01:24:43.239133 DQM Delay:
8706 01:24:43.239211 DQM0 = 131, DQM1 = 123
8707 01:24:43.242577 DQ Delay:
8708 01:24:43.245732 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8709 01:24:43.249228 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8710 01:24:43.252791 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8711 01:24:43.255988 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8712 01:24:43.256061
8713 01:24:43.256130
8714 01:24:43.256190
8715 01:24:43.259205 [DramC_TX_OE_Calibration] TA2
8716 01:24:43.262756 Original DQ_B0 (3 6) =30, OEN = 27
8717 01:24:43.265984 Original DQ_B1 (3 6) =30, OEN = 27
8718 01:24:43.269290 24, 0x0, End_B0=24 End_B1=24
8719 01:24:43.269368 25, 0x0, End_B0=25 End_B1=25
8720 01:24:43.272430 26, 0x0, End_B0=26 End_B1=26
8721 01:24:43.275780 27, 0x0, End_B0=27 End_B1=27
8722 01:24:43.278937 28, 0x0, End_B0=28 End_B1=28
8723 01:24:43.282902 29, 0x0, End_B0=29 End_B1=29
8724 01:24:43.282980 30, 0x0, End_B0=30 End_B1=30
8725 01:24:43.285924 31, 0x5151, End_B0=30 End_B1=30
8726 01:24:43.289136 Byte0 end_step=30 best_step=27
8727 01:24:43.292498 Byte1 end_step=30 best_step=27
8728 01:24:43.296076 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 01:24:43.299306 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 01:24:43.299428
8731 01:24:43.299523
8732 01:24:43.305867 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8733 01:24:43.309352 CH1 RK0: MR19=303, MR18=80D
8734 01:24:43.315526 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8735 01:24:43.315612
8736 01:24:43.319225 ----->DramcWriteLeveling(PI) begin...
8737 01:24:43.319336 ==
8738 01:24:43.322424 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 01:24:43.325738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 01:24:43.325848 ==
8741 01:24:43.328788 Write leveling (Byte 0): 23 => 23
8742 01:24:43.332416 Write leveling (Byte 1): 25 => 25
8743 01:24:43.335284 DramcWriteLeveling(PI) end<-----
8744 01:24:43.335429
8745 01:24:43.335513 ==
8746 01:24:43.338594 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 01:24:43.341970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 01:24:43.342054 ==
8749 01:24:43.345757 [Gating] SW mode calibration
8750 01:24:43.352096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 01:24:43.358649 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 01:24:43.361788 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 01:24:43.365232 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 01:24:43.371960 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8755 01:24:43.374900 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8756 01:24:43.378698 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 01:24:43.384900 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 01:24:43.388357 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 01:24:43.391796 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 01:24:43.398343 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 01:24:43.401677 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 01:24:43.404595 1 5 8 | B1->B0 | 3434 2626 | 0 1 | (0 0) (1 0)
8763 01:24:43.411606 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
8764 01:24:43.414572 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 01:24:43.417975 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 01:24:43.424821 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 01:24:43.428025 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 01:24:43.431507 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 01:24:43.438338 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8770 01:24:43.441099 1 6 8 | B1->B0 | 2525 4343 | 0 0 | (0 0) (0 0)
8771 01:24:43.444807 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8772 01:24:43.451437 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 01:24:43.454698 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 01:24:43.458255 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 01:24:43.464969 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 01:24:43.467850 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 01:24:43.471111 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 01:24:43.478158 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8779 01:24:43.480905 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8780 01:24:43.484574 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 01:24:43.490930 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 01:24:43.493976 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 01:24:43.497420 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 01:24:43.504143 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 01:24:43.507940 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 01:24:43.510991 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 01:24:43.517538 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 01:24:43.521225 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 01:24:43.524110 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 01:24:43.530586 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 01:24:43.533708 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 01:24:43.537546 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 01:24:43.543964 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 01:24:43.547841 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8795 01:24:43.550466 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8796 01:24:43.554129 Total UI for P1: 0, mck2ui 16
8797 01:24:43.557199 best dqsien dly found for B0: ( 1, 9, 8)
8798 01:24:43.563753 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 01:24:43.563837 Total UI for P1: 0, mck2ui 16
8800 01:24:43.566920 best dqsien dly found for B1: ( 1, 9, 10)
8801 01:24:43.573816 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8802 01:24:43.576985 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8803 01:24:43.577067
8804 01:24:43.580436 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8805 01:24:43.584020 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8806 01:24:43.586848 [Gating] SW calibration Done
8807 01:24:43.586929 ==
8808 01:24:43.590736 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 01:24:43.593978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 01:24:43.594063 ==
8811 01:24:43.596789 RX Vref Scan: 0
8812 01:24:43.596862
8813 01:24:43.596925 RX Vref 0 -> 0, step: 1
8814 01:24:43.596984
8815 01:24:43.600543 RX Delay 0 -> 252, step: 8
8816 01:24:43.603832 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8817 01:24:43.606578 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8818 01:24:43.613679 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8819 01:24:43.617101 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8820 01:24:43.619919 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8821 01:24:43.623574 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8822 01:24:43.627053 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8823 01:24:43.633414 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8824 01:24:43.636427 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8825 01:24:43.639715 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8826 01:24:43.643573 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8827 01:24:43.649744 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8828 01:24:43.653261 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8829 01:24:43.656353 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8830 01:24:43.659704 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8831 01:24:43.663261 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8832 01:24:43.666302 ==
8833 01:24:43.666462 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 01:24:43.673079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 01:24:43.673162 ==
8836 01:24:43.673227 DQS Delay:
8837 01:24:43.676531 DQS0 = 0, DQS1 = 0
8838 01:24:43.676612 DQM Delay:
8839 01:24:43.679831 DQM0 = 130, DQM1 = 127
8840 01:24:43.679938 DQ Delay:
8841 01:24:43.683072 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8842 01:24:43.686610 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8843 01:24:43.689898 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8844 01:24:43.692995 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8845 01:24:43.693076
8846 01:24:43.693141
8847 01:24:43.693200 ==
8848 01:24:43.696351 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 01:24:43.702686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 01:24:43.702772 ==
8851 01:24:43.702837
8852 01:24:43.702896
8853 01:24:43.702955 TX Vref Scan disable
8854 01:24:43.706193 == TX Byte 0 ==
8855 01:24:43.709971 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8856 01:24:43.716609 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8857 01:24:43.716691 == TX Byte 1 ==
8858 01:24:43.719545 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8859 01:24:43.726529 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8860 01:24:43.726613 ==
8861 01:24:43.729604 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 01:24:43.732995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 01:24:43.733078 ==
8864 01:24:43.746198
8865 01:24:43.749698 TX Vref early break, caculate TX vref
8866 01:24:43.752804 TX Vref=16, minBit 0, minWin=22, winSum=378
8867 01:24:43.756341 TX Vref=18, minBit 0, minWin=22, winSum=392
8868 01:24:43.759480 TX Vref=20, minBit 0, minWin=23, winSum=397
8869 01:24:43.762776 TX Vref=22, minBit 0, minWin=24, winSum=404
8870 01:24:43.766160 TX Vref=24, minBit 0, minWin=24, winSum=416
8871 01:24:43.772569 TX Vref=26, minBit 0, minWin=25, winSum=424
8872 01:24:43.776290 TX Vref=28, minBit 1, minWin=25, winSum=421
8873 01:24:43.779143 TX Vref=30, minBit 1, minWin=24, winSum=415
8874 01:24:43.782603 TX Vref=32, minBit 1, minWin=23, winSum=404
8875 01:24:43.786288 TX Vref=34, minBit 1, minWin=22, winSum=402
8876 01:24:43.789211 TX Vref=36, minBit 5, minWin=22, winSum=393
8877 01:24:43.796391 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8878 01:24:43.796476
8879 01:24:43.799288 Final TX Range 0 Vref 26
8880 01:24:43.799425
8881 01:24:43.799561 ==
8882 01:24:43.802649 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 01:24:43.806152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 01:24:43.806235 ==
8885 01:24:43.806299
8886 01:24:43.809374
8887 01:24:43.809460 TX Vref Scan disable
8888 01:24:43.816293 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8889 01:24:43.816377 == TX Byte 0 ==
8890 01:24:43.819362 u2DelayCellOfst[0]=18 cells (5 PI)
8891 01:24:43.822886 u2DelayCellOfst[1]=15 cells (4 PI)
8892 01:24:43.825857 u2DelayCellOfst[2]=0 cells (0 PI)
8893 01:24:43.829325 u2DelayCellOfst[3]=3 cells (1 PI)
8894 01:24:43.832710 u2DelayCellOfst[4]=7 cells (2 PI)
8895 01:24:43.836193 u2DelayCellOfst[5]=22 cells (6 PI)
8896 01:24:43.838948 u2DelayCellOfst[6]=18 cells (5 PI)
8897 01:24:43.842317 u2DelayCellOfst[7]=3 cells (1 PI)
8898 01:24:43.845805 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8899 01:24:43.849329 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8900 01:24:43.852147 == TX Byte 1 ==
8901 01:24:43.855739 u2DelayCellOfst[8]=0 cells (0 PI)
8902 01:24:43.855822 u2DelayCellOfst[9]=7 cells (2 PI)
8903 01:24:43.858884 u2DelayCellOfst[10]=15 cells (4 PI)
8904 01:24:43.862198 u2DelayCellOfst[11]=7 cells (2 PI)
8905 01:24:43.865813 u2DelayCellOfst[12]=15 cells (4 PI)
8906 01:24:43.868690 u2DelayCellOfst[13]=18 cells (5 PI)
8907 01:24:43.872251 u2DelayCellOfst[14]=22 cells (6 PI)
8908 01:24:43.875498 u2DelayCellOfst[15]=22 cells (6 PI)
8909 01:24:43.882076 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8910 01:24:43.885247 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8911 01:24:43.885363 DramC Write-DBI on
8912 01:24:43.885460 ==
8913 01:24:43.888937 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 01:24:43.895336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 01:24:43.895451 ==
8916 01:24:43.895517
8917 01:24:43.895577
8918 01:24:43.895634 TX Vref Scan disable
8919 01:24:43.899202 == TX Byte 0 ==
8920 01:24:43.902498 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8921 01:24:43.905786 == TX Byte 1 ==
8922 01:24:43.909194 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8923 01:24:43.912764 DramC Write-DBI off
8924 01:24:43.912846
8925 01:24:43.912910 [DATLAT]
8926 01:24:43.912971 Freq=1600, CH1 RK1
8927 01:24:43.913030
8928 01:24:43.915835 DATLAT Default: 0xf
8929 01:24:43.915917 0, 0xFFFF, sum = 0
8930 01:24:43.919446 1, 0xFFFF, sum = 0
8931 01:24:43.922314 2, 0xFFFF, sum = 0
8932 01:24:43.922424 3, 0xFFFF, sum = 0
8933 01:24:43.926145 4, 0xFFFF, sum = 0
8934 01:24:43.926258 5, 0xFFFF, sum = 0
8935 01:24:43.929210 6, 0xFFFF, sum = 0
8936 01:24:43.929295 7, 0xFFFF, sum = 0
8937 01:24:43.932233 8, 0xFFFF, sum = 0
8938 01:24:43.932317 9, 0xFFFF, sum = 0
8939 01:24:43.935874 10, 0xFFFF, sum = 0
8940 01:24:43.935998 11, 0xFFFF, sum = 0
8941 01:24:43.939094 12, 0xFFFF, sum = 0
8942 01:24:43.939208 13, 0x8FFF, sum = 0
8943 01:24:43.942769 14, 0x0, sum = 1
8944 01:24:43.942879 15, 0x0, sum = 2
8945 01:24:43.946135 16, 0x0, sum = 3
8946 01:24:43.946259 17, 0x0, sum = 4
8947 01:24:43.948910 best_step = 15
8948 01:24:43.948993
8949 01:24:43.949057 ==
8950 01:24:43.952753 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 01:24:43.956014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 01:24:43.956097 ==
8953 01:24:43.959070 RX Vref Scan: 0
8954 01:24:43.959152
8955 01:24:43.959217 RX Vref 0 -> 0, step: 1
8956 01:24:43.959278
8957 01:24:43.962660 RX Delay 3 -> 252, step: 4
8958 01:24:43.966003 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8959 01:24:43.972483 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8960 01:24:43.975356 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8961 01:24:43.979064 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8962 01:24:43.982073 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8963 01:24:43.985352 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8964 01:24:43.991954 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8965 01:24:43.995383 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8966 01:24:43.999175 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8967 01:24:44.002041 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8968 01:24:44.005827 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8969 01:24:44.012136 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8970 01:24:44.015401 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8971 01:24:44.018798 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8972 01:24:44.021866 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8973 01:24:44.028399 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8974 01:24:44.028483 ==
8975 01:24:44.031745 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 01:24:44.035256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 01:24:44.035340 ==
8978 01:24:44.035455 DQS Delay:
8979 01:24:44.038805 DQS0 = 0, DQS1 = 0
8980 01:24:44.038912 DQM Delay:
8981 01:24:44.041660 DQM0 = 128, DQM1 = 125
8982 01:24:44.041768 DQ Delay:
8983 01:24:44.045238 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =126
8984 01:24:44.048162 DQ4 =124, DQ5 =138, DQ6 =140, DQ7 =124
8985 01:24:44.051539 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =118
8986 01:24:44.054851 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =134
8987 01:24:44.054937
8988 01:24:44.058413
8989 01:24:44.058511
8990 01:24:44.058592 [DramC_TX_OE_Calibration] TA2
8991 01:24:44.061354 Original DQ_B0 (3 6) =30, OEN = 27
8992 01:24:44.065391 Original DQ_B1 (3 6) =30, OEN = 27
8993 01:24:44.068416 24, 0x0, End_B0=24 End_B1=24
8994 01:24:44.071346 25, 0x0, End_B0=25 End_B1=25
8995 01:24:44.074970 26, 0x0, End_B0=26 End_B1=26
8996 01:24:44.075053 27, 0x0, End_B0=27 End_B1=27
8997 01:24:44.078707 28, 0x0, End_B0=28 End_B1=28
8998 01:24:44.081649 29, 0x0, End_B0=29 End_B1=29
8999 01:24:44.085471 30, 0x0, End_B0=30 End_B1=30
9000 01:24:44.085584 31, 0x5151, End_B0=30 End_B1=30
9001 01:24:44.088425 Byte0 end_step=30 best_step=27
9002 01:24:44.091551 Byte1 end_step=30 best_step=27
9003 01:24:44.094787 Byte0 TX OE(2T, 0.5T) = (3, 3)
9004 01:24:44.098357 Byte1 TX OE(2T, 0.5T) = (3, 3)
9005 01:24:44.098464
9006 01:24:44.098560
9007 01:24:44.104991 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9008 01:24:44.108381 CH1 RK1: MR19=303, MR18=D1B
9009 01:24:44.114892 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9010 01:24:44.118175 [RxdqsGatingPostProcess] freq 1600
9011 01:24:44.124665 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9012 01:24:44.124777 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 01:24:44.128472 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 01:24:44.131569 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 01:24:44.134728 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 01:24:44.137951 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 01:24:44.141498 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 01:24:44.145107 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 01:24:44.147963 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 01:24:44.151495 Pre-setting of DQS Precalculation
9021 01:24:44.154688 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9022 01:24:44.164579 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9023 01:24:44.171535 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9024 01:24:44.171617
9025 01:24:44.171682
9026 01:24:44.174723 [Calibration Summary] 3200 Mbps
9027 01:24:44.174824 CH 0, Rank 0
9028 01:24:44.177843 SW Impedance : PASS
9029 01:24:44.177919 DUTY Scan : NO K
9030 01:24:44.181398 ZQ Calibration : PASS
9031 01:24:44.184278 Jitter Meter : NO K
9032 01:24:44.184351 CBT Training : PASS
9033 01:24:44.188213 Write leveling : PASS
9034 01:24:44.191329 RX DQS gating : PASS
9035 01:24:44.191475 RX DQ/DQS(RDDQC) : PASS
9036 01:24:44.194383 TX DQ/DQS : PASS
9037 01:24:44.197950 RX DATLAT : PASS
9038 01:24:44.198047 RX DQ/DQS(Engine): PASS
9039 01:24:44.200954 TX OE : PASS
9040 01:24:44.201050 All Pass.
9041 01:24:44.201150
9042 01:24:44.204560 CH 0, Rank 1
9043 01:24:44.204664 SW Impedance : PASS
9044 01:24:44.207837 DUTY Scan : NO K
9045 01:24:44.207907 ZQ Calibration : PASS
9046 01:24:44.211524 Jitter Meter : NO K
9047 01:24:44.214164 CBT Training : PASS
9048 01:24:44.214269 Write leveling : PASS
9049 01:24:44.217893 RX DQS gating : PASS
9050 01:24:44.221096 RX DQ/DQS(RDDQC) : PASS
9051 01:24:44.221196 TX DQ/DQS : PASS
9052 01:24:44.224202 RX DATLAT : PASS
9053 01:24:44.227579 RX DQ/DQS(Engine): PASS
9054 01:24:44.227661 TX OE : PASS
9055 01:24:44.230764 All Pass.
9056 01:24:44.230866
9057 01:24:44.230958 CH 1, Rank 0
9058 01:24:44.234412 SW Impedance : PASS
9059 01:24:44.234518 DUTY Scan : NO K
9060 01:24:44.237755 ZQ Calibration : PASS
9061 01:24:44.240947 Jitter Meter : NO K
9062 01:24:44.241053 CBT Training : PASS
9063 01:24:44.244617 Write leveling : PASS
9064 01:24:44.247503 RX DQS gating : PASS
9065 01:24:44.247579 RX DQ/DQS(RDDQC) : PASS
9066 01:24:44.250957 TX DQ/DQS : PASS
9067 01:24:44.253942 RX DATLAT : PASS
9068 01:24:44.254027 RX DQ/DQS(Engine): PASS
9069 01:24:44.257182 TX OE : PASS
9070 01:24:44.257263 All Pass.
9071 01:24:44.257327
9072 01:24:44.261146 CH 1, Rank 1
9073 01:24:44.261221 SW Impedance : PASS
9074 01:24:44.263879 DUTY Scan : NO K
9075 01:24:44.267469 ZQ Calibration : PASS
9076 01:24:44.267538 Jitter Meter : NO K
9077 01:24:44.270530 CBT Training : PASS
9078 01:24:44.270641 Write leveling : PASS
9079 01:24:44.274373 RX DQS gating : PASS
9080 01:24:44.277549 RX DQ/DQS(RDDQC) : PASS
9081 01:24:44.277655 TX DQ/DQS : PASS
9082 01:24:44.280600 RX DATLAT : PASS
9083 01:24:44.283617 RX DQ/DQS(Engine): PASS
9084 01:24:44.283695 TX OE : PASS
9085 01:24:44.287270 All Pass.
9086 01:24:44.287382
9087 01:24:44.287482 DramC Write-DBI on
9088 01:24:44.290553 PER_BANK_REFRESH: Hybrid Mode
9089 01:24:44.293697 TX_TRACKING: ON
9090 01:24:44.300301 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9091 01:24:44.310129 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9092 01:24:44.317338 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 01:24:44.320730 [FAST_K] Save calibration result to emmc
9094 01:24:44.323732 sync common calibartion params.
9095 01:24:44.323845 sync cbt_mode0:1, 1:1
9096 01:24:44.327257 dram_init: ddr_geometry: 2
9097 01:24:44.330183 dram_init: ddr_geometry: 2
9098 01:24:44.333326 dram_init: ddr_geometry: 2
9099 01:24:44.333429 0:dram_rank_size:100000000
9100 01:24:44.336885 1:dram_rank_size:100000000
9101 01:24:44.343359 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9102 01:24:44.343483 DFS_SHUFFLE_HW_MODE: ON
9103 01:24:44.346724 dramc_set_vcore_voltage set vcore to 725000
9104 01:24:44.350207 Read voltage for 1600, 0
9105 01:24:44.350289 Vio18 = 0
9106 01:24:44.353853 Vcore = 725000
9107 01:24:44.353934 Vdram = 0
9108 01:24:44.353999 Vddq = 0
9109 01:24:44.356961 Vmddr = 0
9110 01:24:44.357044 switch to 3200 Mbps bootup
9111 01:24:44.360150 [DramcRunTimeConfig]
9112 01:24:44.360231 PHYPLL
9113 01:24:44.363513 DPM_CONTROL_AFTERK: ON
9114 01:24:44.363594 PER_BANK_REFRESH: ON
9115 01:24:44.366611 REFRESH_OVERHEAD_REDUCTION: ON
9116 01:24:44.370158 CMD_PICG_NEW_MODE: OFF
9117 01:24:44.370239 XRTWTW_NEW_MODE: ON
9118 01:24:44.373317 XRTRTR_NEW_MODE: ON
9119 01:24:44.373398 TX_TRACKING: ON
9120 01:24:44.376704 RDSEL_TRACKING: OFF
9121 01:24:44.380103 DQS Precalculation for DVFS: ON
9122 01:24:44.380211 RX_TRACKING: OFF
9123 01:24:44.383609 HW_GATING DBG: ON
9124 01:24:44.383690 ZQCS_ENABLE_LP4: ON
9125 01:24:44.386627 RX_PICG_NEW_MODE: ON
9126 01:24:44.386708 TX_PICG_NEW_MODE: ON
9127 01:24:44.390269 ENABLE_RX_DCM_DPHY: ON
9128 01:24:44.393276 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9129 01:24:44.396994 DUMMY_READ_FOR_TRACKING: OFF
9130 01:24:44.399826 !!! SPM_CONTROL_AFTERK: OFF
9131 01:24:44.399915 !!! SPM could not control APHY
9132 01:24:44.403302 IMPEDANCE_TRACKING: ON
9133 01:24:44.403427 TEMP_SENSOR: ON
9134 01:24:44.406654 HW_SAVE_FOR_SR: OFF
9135 01:24:44.409703 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9136 01:24:44.413220 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9137 01:24:44.416830 Read ODT Tracking: ON
9138 01:24:44.416911 Refresh Rate DeBounce: ON
9139 01:24:44.419814 DFS_NO_QUEUE_FLUSH: ON
9140 01:24:44.423231 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9141 01:24:44.426533 ENABLE_DFS_RUNTIME_MRW: OFF
9142 01:24:44.426615 DDR_RESERVE_NEW_MODE: ON
9143 01:24:44.429593 MR_CBT_SWITCH_FREQ: ON
9144 01:24:44.433112 =========================
9145 01:24:44.450789 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9146 01:24:44.453868 dram_init: ddr_geometry: 2
9147 01:24:44.473092 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9148 01:24:44.475275 dram_init: dram init end (result: 0)
9149 01:24:44.482208 DRAM-K: Full calibration passed in 24536 msecs
9150 01:24:44.485198 MRC: failed to locate region type 0.
9151 01:24:44.485279 DRAM rank0 size:0x100000000,
9152 01:24:44.488849 DRAM rank1 size=0x100000000
9153 01:24:44.498745 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9154 01:24:44.505200 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9155 01:24:44.511887 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9156 01:24:44.521684 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9157 01:24:44.521766 DRAM rank0 size:0x100000000,
9158 01:24:44.524947 DRAM rank1 size=0x100000000
9159 01:24:44.525030 CBMEM:
9160 01:24:44.528598 IMD: root @ 0xfffff000 254 entries.
9161 01:24:44.532014 IMD: root @ 0xffffec00 62 entries.
9162 01:24:44.534726 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9163 01:24:44.542241 WARNING: RO_VPD is uninitialized or empty.
9164 01:24:44.544877 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9165 01:24:44.552571 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9166 01:24:44.564937 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9167 01:24:44.576434 BS: romstage times (exec / console): total (unknown) / 24004 ms
9168 01:24:44.576518
9169 01:24:44.576584
9170 01:24:44.586566 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9171 01:24:44.590001 ARM64: Exception handlers installed.
9172 01:24:44.592886 ARM64: Testing exception
9173 01:24:44.596182 ARM64: Done test exception
9174 01:24:44.596265 Enumerating buses...
9175 01:24:44.599645 Show all devs... Before device enumeration.
9176 01:24:44.602991 Root Device: enabled 1
9177 01:24:44.605999 CPU_CLUSTER: 0: enabled 1
9178 01:24:44.606083 CPU: 00: enabled 1
9179 01:24:44.609893 Compare with tree...
9180 01:24:44.609976 Root Device: enabled 1
9181 01:24:44.612841 CPU_CLUSTER: 0: enabled 1
9182 01:24:44.616229 CPU: 00: enabled 1
9183 01:24:44.616312 Root Device scanning...
9184 01:24:44.619471 scan_static_bus for Root Device
9185 01:24:44.622833 CPU_CLUSTER: 0 enabled
9186 01:24:44.626005 scan_static_bus for Root Device done
9187 01:24:44.629593 scan_bus: bus Root Device finished in 8 msecs
9188 01:24:44.629677 done
9189 01:24:44.635930 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9190 01:24:44.639323 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9191 01:24:44.646064 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9192 01:24:44.649121 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9193 01:24:44.652518 Allocating resources...
9194 01:24:44.656126 Reading resources...
9195 01:24:44.659093 Root Device read_resources bus 0 link: 0
9196 01:24:44.659190 DRAM rank0 size:0x100000000,
9197 01:24:44.662170 DRAM rank1 size=0x100000000
9198 01:24:44.666082 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9199 01:24:44.669261 CPU: 00 missing read_resources
9200 01:24:44.675581 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9201 01:24:44.679092 Root Device read_resources bus 0 link: 0 done
9202 01:24:44.679171 Done reading resources.
9203 01:24:44.685719 Show resources in subtree (Root Device)...After reading.
9204 01:24:44.689385 Root Device child on link 0 CPU_CLUSTER: 0
9205 01:24:44.692426 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 01:24:44.702141 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 01:24:44.702229 CPU: 00
9208 01:24:44.705682 Root Device assign_resources, bus 0 link: 0
9209 01:24:44.708954 CPU_CLUSTER: 0 missing set_resources
9210 01:24:44.715982 Root Device assign_resources, bus 0 link: 0 done
9211 01:24:44.716065 Done setting resources.
9212 01:24:44.722669 Show resources in subtree (Root Device)...After assigning values.
9213 01:24:44.725911 Root Device child on link 0 CPU_CLUSTER: 0
9214 01:24:44.728971 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 01:24:44.739018 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 01:24:44.739103 CPU: 00
9217 01:24:44.742193 Done allocating resources.
9218 01:24:44.748773 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9219 01:24:44.748861 Enabling resources...
9220 01:24:44.748927 done.
9221 01:24:44.755059 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9222 01:24:44.755142 Initializing devices...
9223 01:24:44.758419 Root Device init
9224 01:24:44.758502 init hardware done!
9225 01:24:44.761940 0x00000018: ctrlr->caps
9226 01:24:44.765554 52.000 MHz: ctrlr->f_max
9227 01:24:44.765640 0.400 MHz: ctrlr->f_min
9228 01:24:44.768466 0x40ff8080: ctrlr->voltages
9229 01:24:44.772080 sclk: 390625
9230 01:24:44.772163 Bus Width = 1
9231 01:24:44.772227 sclk: 390625
9232 01:24:44.774987 Bus Width = 1
9233 01:24:44.775087 Early init status = 3
9234 01:24:44.781967 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9235 01:24:44.784728 in-header: 03 fc 00 00 01 00 00 00
9236 01:24:44.788442 in-data: 00
9237 01:24:44.791303 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9238 01:24:44.796779 in-header: 03 fd 00 00 00 00 00 00
9239 01:24:44.800311 in-data:
9240 01:24:44.803276 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9241 01:24:44.807849 in-header: 03 fc 00 00 01 00 00 00
9242 01:24:44.811273 in-data: 00
9243 01:24:44.814227 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9244 01:24:44.819998 in-header: 03 fd 00 00 00 00 00 00
9245 01:24:44.823693 in-data:
9246 01:24:44.826540 [SSUSB] Setting up USB HOST controller...
9247 01:24:44.830062 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9248 01:24:44.833550 [SSUSB] phy power-on done.
9249 01:24:44.836511 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9250 01:24:44.843022 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9251 01:24:44.846438 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9252 01:24:44.853090 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9253 01:24:44.859701 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9254 01:24:44.866236 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9255 01:24:44.872823 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9256 01:24:44.879360 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9257 01:24:44.883113 SPM: binary array size = 0x9dc
9258 01:24:44.886199 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9259 01:24:44.892850 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9260 01:24:44.899316 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9261 01:24:44.905939 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9262 01:24:44.909433 configure_display: Starting display init
9263 01:24:44.943549 anx7625_power_on_init: Init interface.
9264 01:24:44.946980 anx7625_disable_pd_protocol: Disabled PD feature.
9265 01:24:44.950290 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9266 01:24:44.977758 anx7625_start_dp_work: Secure OCM version=00
9267 01:24:44.981065 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9268 01:24:44.995543 sp_tx_get_edid_block: EDID Block = 1
9269 01:24:45.098427 Extracted contents:
9270 01:24:45.101636 header: 00 ff ff ff ff ff ff 00
9271 01:24:45.104948 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9272 01:24:45.108661 version: 01 04
9273 01:24:45.112016 basic params: 95 1f 11 78 0a
9274 01:24:45.115331 chroma info: 76 90 94 55 54 90 27 21 50 54
9275 01:24:45.118591 established: 00 00 00
9276 01:24:45.124814 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9277 01:24:45.128106 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9278 01:24:45.135197 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9279 01:24:45.141297 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9280 01:24:45.148233 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9281 01:24:45.151376 extensions: 00
9282 01:24:45.151465 checksum: fb
9283 01:24:45.151532
9284 01:24:45.154626 Manufacturer: IVO Model 57d Serial Number 0
9285 01:24:45.158113 Made week 0 of 2020
9286 01:24:45.158193 EDID version: 1.4
9287 01:24:45.161223 Digital display
9288 01:24:45.164631 6 bits per primary color channel
9289 01:24:45.164708 DisplayPort interface
9290 01:24:45.167977 Maximum image size: 31 cm x 17 cm
9291 01:24:45.171250 Gamma: 220%
9292 01:24:45.171343 Check DPMS levels
9293 01:24:45.174772 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9294 01:24:45.181603 First detailed timing is preferred timing
9295 01:24:45.181687 Established timings supported:
9296 01:24:45.184248 Standard timings supported:
9297 01:24:45.187980 Detailed timings
9298 01:24:45.190925 Hex of detail: 383680a07038204018303c0035ae10000019
9299 01:24:45.194488 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9300 01:24:45.201090 0780 0798 07c8 0820 hborder 0
9301 01:24:45.204116 0438 043b 0447 0458 vborder 0
9302 01:24:45.207409 -hsync -vsync
9303 01:24:45.207506 Did detailed timing
9304 01:24:45.213935 Hex of detail: 000000000000000000000000000000000000
9305 01:24:45.217369 Manufacturer-specified data, tag 0
9306 01:24:45.221035 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9307 01:24:45.224007 ASCII string: InfoVision
9308 01:24:45.227571 Hex of detail: 000000fe00523134304e574635205248200a
9309 01:24:45.231055 ASCII string: R140NWF5 RH
9310 01:24:45.231140 Checksum
9311 01:24:45.233934 Checksum: 0xfb (valid)
9312 01:24:45.237362 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9313 01:24:45.240781 DSI data_rate: 832800000 bps
9314 01:24:45.247347 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9315 01:24:45.250380 anx7625_parse_edid: pixelclock(138800).
9316 01:24:45.253648 hactive(1920), hsync(48), hfp(24), hbp(88)
9317 01:24:45.257382 vactive(1080), vsync(12), vfp(3), vbp(17)
9318 01:24:45.260494 anx7625_dsi_config: config dsi.
9319 01:24:45.267071 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9320 01:24:45.280402 anx7625_dsi_config: success to config DSI
9321 01:24:45.283554 anx7625_dp_start: MIPI phy setup OK.
9322 01:24:45.286971 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9323 01:24:45.290365 mtk_ddp_mode_set invalid vrefresh 60
9324 01:24:45.293976 main_disp_path_setup
9325 01:24:45.294057 ovl_layer_smi_id_en
9326 01:24:45.296975 ovl_layer_smi_id_en
9327 01:24:45.297056 ccorr_config
9328 01:24:45.297120 aal_config
9329 01:24:45.300739 gamma_config
9330 01:24:45.300820 postmask_config
9331 01:24:45.303531 dither_config
9332 01:24:45.307119 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9333 01:24:45.313333 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9334 01:24:45.316583 Root Device init finished in 555 msecs
9335 01:24:45.320084 CPU_CLUSTER: 0 init
9336 01:24:45.326928 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9337 01:24:45.329870 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9338 01:24:45.333635 APU_MBOX 0x190000b0 = 0x10001
9339 01:24:45.336522 APU_MBOX 0x190001b0 = 0x10001
9340 01:24:45.339827 APU_MBOX 0x190005b0 = 0x10001
9341 01:24:45.343591 APU_MBOX 0x190006b0 = 0x10001
9342 01:24:45.346377 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9343 01:24:45.359412 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9344 01:24:45.372009 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9345 01:24:45.378784 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9346 01:24:45.390246 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9347 01:24:45.399334 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9348 01:24:45.402717 CPU_CLUSTER: 0 init finished in 81 msecs
9349 01:24:45.405724 Devices initialized
9350 01:24:45.409444 Show all devs... After init.
9351 01:24:45.409526 Root Device: enabled 1
9352 01:24:45.412529 CPU_CLUSTER: 0: enabled 1
9353 01:24:45.416200 CPU: 00: enabled 1
9354 01:24:45.419190 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9355 01:24:45.422404 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9356 01:24:45.425579 ELOG: NV offset 0x57f000 size 0x1000
9357 01:24:45.432440 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9358 01:24:45.438991 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9359 01:24:45.442593 ELOG: Event(17) added with size 13 at 2023-08-28 01:24:46 UTC
9360 01:24:45.445805 out: cmd=0x121: 03 db 21 01 00 00 00 00
9361 01:24:45.449706 in-header: 03 80 00 00 2c 00 00 00
9362 01:24:45.463140 in-data: df 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9363 01:24:45.469692 ELOG: Event(A1) added with size 10 at 2023-08-28 01:24:46 UTC
9364 01:24:45.476152 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9365 01:24:45.482559 ELOG: Event(A0) added with size 9 at 2023-08-28 01:24:46 UTC
9366 01:24:45.486520 elog_add_boot_reason: Logged dev mode boot
9367 01:24:45.489299 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9368 01:24:45.492991 Finalize devices...
9369 01:24:45.493080 Devices finalized
9370 01:24:45.499123 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9371 01:24:45.502284 Writing coreboot table at 0xffe64000
9372 01:24:45.506019 0. 000000000010a000-0000000000113fff: RAMSTAGE
9373 01:24:45.509015 1. 0000000040000000-00000000400fffff: RAM
9374 01:24:45.515886 2. 0000000040100000-000000004032afff: RAMSTAGE
9375 01:24:45.519061 3. 000000004032b000-00000000545fffff: RAM
9376 01:24:45.522017 4. 0000000054600000-000000005465ffff: BL31
9377 01:24:45.525681 5. 0000000054660000-00000000ffe63fff: RAM
9378 01:24:45.532175 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9379 01:24:45.535432 7. 0000000100000000-000000023fffffff: RAM
9380 01:24:45.538610 Passing 5 GPIOs to payload:
9381 01:24:45.541986 NAME | PORT | POLARITY | VALUE
9382 01:24:45.545248 EC in RW | 0x000000aa | low | undefined
9383 01:24:45.552234 EC interrupt | 0x00000005 | low | undefined
9384 01:24:45.555206 TPM interrupt | 0x000000ab | high | undefined
9385 01:24:45.562493 SD card detect | 0x00000011 | high | undefined
9386 01:24:45.565269 speaker enable | 0x00000093 | high | undefined
9387 01:24:45.568740 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9388 01:24:45.571667 in-header: 03 f9 00 00 02 00 00 00
9389 01:24:45.575337 in-data: 02 00
9390 01:24:45.575434 ADC[4]: Raw value=894081 ID=7
9391 01:24:45.578510 ADC[3]: Raw value=213440 ID=1
9392 01:24:45.581583 RAM Code: 0x71
9393 01:24:45.581688 ADC[6]: Raw value=74722 ID=0
9394 01:24:45.585376 ADC[5]: Raw value=212330 ID=1
9395 01:24:45.588580 SKU Code: 0x1
9396 01:24:45.591969 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2dff
9397 01:24:45.595172 coreboot table: 964 bytes.
9398 01:24:45.598158 IMD ROOT 0. 0xfffff000 0x00001000
9399 01:24:45.601628 IMD SMALL 1. 0xffffe000 0x00001000
9400 01:24:45.605226 RO MCACHE 2. 0xffffc000 0x00001104
9401 01:24:45.608391 CONSOLE 3. 0xfff7c000 0x00080000
9402 01:24:45.611782 FMAP 4. 0xfff7b000 0x00000452
9403 01:24:45.615341 TIME STAMP 5. 0xfff7a000 0x00000910
9404 01:24:45.618131 VBOOT WORK 6. 0xfff66000 0x00014000
9405 01:24:45.621237 RAMOOPS 7. 0xffe66000 0x00100000
9406 01:24:45.624871 COREBOOT 8. 0xffe64000 0x00002000
9407 01:24:45.624952 IMD small region:
9408 01:24:45.631269 IMD ROOT 0. 0xffffec00 0x00000400
9409 01:24:45.634477 VPD 1. 0xffffeb80 0x0000006c
9410 01:24:45.638276 MMC STATUS 2. 0xffffeb60 0x00000004
9411 01:24:45.641275 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9412 01:24:45.644801 Probing TPM: done!
9413 01:24:45.648152 Connected to device vid:did:rid of 1ae0:0028:00
9414 01:24:45.658470 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9415 01:24:45.661596 Initialized TPM device CR50 revision 0
9416 01:24:45.665394 Checking cr50 for pending updates
9417 01:24:45.668811 Reading cr50 TPM mode
9418 01:24:45.677761 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9419 01:24:45.684369 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9420 01:24:45.724090 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9421 01:24:45.727697 Checking segment from ROM address 0x40100000
9422 01:24:45.731456 Checking segment from ROM address 0x4010001c
9423 01:24:45.737933 Loading segment from ROM address 0x40100000
9424 01:24:45.738011 code (compression=0)
9425 01:24:45.747451 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9426 01:24:45.754695 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9427 01:24:45.754773 it's not compressed!
9428 01:24:45.761022 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9429 01:24:45.763985 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9430 01:24:45.784643 Loading segment from ROM address 0x4010001c
9431 01:24:45.784733 Entry Point 0x80000000
9432 01:24:45.788003 Loaded segments
9433 01:24:45.791295 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9434 01:24:45.798014 Jumping to boot code at 0x80000000(0xffe64000)
9435 01:24:45.804845 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9436 01:24:45.811125 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9437 01:24:45.819667 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9438 01:24:45.822529 Checking segment from ROM address 0x40100000
9439 01:24:45.825772 Checking segment from ROM address 0x4010001c
9440 01:24:45.832524 Loading segment from ROM address 0x40100000
9441 01:24:45.832605 code (compression=1)
9442 01:24:45.839123 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9443 01:24:45.849035 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9444 01:24:45.849131 using LZMA
9445 01:24:45.857768 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9446 01:24:45.864233 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9447 01:24:45.867720 Loading segment from ROM address 0x4010001c
9448 01:24:45.867796 Entry Point 0x54601000
9449 01:24:45.870623 Loaded segments
9450 01:24:45.874128 NOTICE: MT8192 bl31_setup
9451 01:24:45.881042 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9452 01:24:45.884188 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9453 01:24:45.887508 WARNING: region 0:
9454 01:24:45.891089 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 01:24:45.891211 WARNING: region 1:
9456 01:24:45.897722 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9457 01:24:45.901247 WARNING: region 2:
9458 01:24:45.904789 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9459 01:24:45.907761 WARNING: region 3:
9460 01:24:45.911186 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9461 01:24:45.914451 WARNING: region 4:
9462 01:24:45.917803 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 01:24:45.921477 WARNING: region 5:
9464 01:24:45.924393 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 01:24:45.928294 WARNING: region 6:
9466 01:24:45.931402 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 01:24:45.931523 WARNING: region 7:
9468 01:24:45.938037 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 01:24:45.944454 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9470 01:24:45.948212 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9471 01:24:45.951409 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9472 01:24:45.957696 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9473 01:24:45.961156 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9474 01:24:45.964913 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9475 01:24:45.971273 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9476 01:24:45.975157 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9477 01:24:45.977913 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9478 01:24:45.984433 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9479 01:24:45.988076 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9480 01:24:45.994256 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9481 01:24:45.998400 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9482 01:24:46.001041 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9483 01:24:46.007505 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9484 01:24:46.011175 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9485 01:24:46.014367 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9486 01:24:46.021361 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9487 01:24:46.024304 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9488 01:24:46.030918 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9489 01:24:46.034330 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9490 01:24:46.038196 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9491 01:24:46.044879 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9492 01:24:46.048112 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9493 01:24:46.054712 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9494 01:24:46.057673 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9495 01:24:46.061152 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9496 01:24:46.067825 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9497 01:24:46.071477 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9498 01:24:46.074537 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9499 01:24:46.081175 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9500 01:24:46.084319 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9501 01:24:46.091677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9502 01:24:46.094660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9503 01:24:46.098043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9504 01:24:46.101124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9505 01:24:46.105000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9506 01:24:46.111265 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9507 01:24:46.114542 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9508 01:24:46.118063 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9509 01:24:46.121336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9510 01:24:46.128463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9511 01:24:46.131176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9512 01:24:46.134650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9513 01:24:46.137792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9514 01:24:46.144617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9515 01:24:46.147763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9516 01:24:46.151205 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9517 01:24:46.158355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9518 01:24:46.161469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9519 01:24:46.168196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9520 01:24:46.171000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9521 01:24:46.174552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9522 01:24:46.181115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9523 01:24:46.184599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9524 01:24:46.191526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9525 01:24:46.194385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9526 01:24:46.197682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9527 01:24:46.204745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9528 01:24:46.208024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9529 01:24:46.214434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9530 01:24:46.217804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9531 01:24:46.224737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9532 01:24:46.227938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9533 01:24:46.234495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9534 01:24:46.238139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9535 01:24:46.241741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9536 01:24:46.247835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9537 01:24:46.251187 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9538 01:24:46.258255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9539 01:24:46.260955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9540 01:24:46.267780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9541 01:24:46.271483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9542 01:24:46.274380 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9543 01:24:46.281174 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9544 01:24:46.284323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9545 01:24:46.291562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9546 01:24:46.294787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9547 01:24:46.301194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9548 01:24:46.304662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9549 01:24:46.308046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9550 01:24:46.314779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9551 01:24:46.317976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9552 01:24:46.324561 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9553 01:24:46.328247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9554 01:24:46.334598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9555 01:24:46.338222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9556 01:24:46.341538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9557 01:24:46.348005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9558 01:24:46.351531 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9559 01:24:46.358221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9560 01:24:46.361324 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9561 01:24:46.368127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9562 01:24:46.371197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9563 01:24:46.378297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9564 01:24:46.381424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9565 01:24:46.384623 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9566 01:24:46.387778 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9567 01:24:46.394885 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9568 01:24:46.397761 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9569 01:24:46.401474 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9570 01:24:46.408326 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9571 01:24:46.411518 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9572 01:24:46.414438 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9573 01:24:46.421177 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9574 01:24:46.424449 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9575 01:24:46.431134 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9576 01:24:46.434443 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9577 01:24:46.437991 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9578 01:24:46.444666 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9579 01:24:46.447873 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9580 01:24:46.454881 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9581 01:24:46.458202 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9582 01:24:46.461777 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9583 01:24:46.467884 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9584 01:24:46.471759 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9585 01:24:46.474777 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9586 01:24:46.481377 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9587 01:24:46.484682 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9588 01:24:46.488037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9589 01:24:46.491744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9590 01:24:46.497927 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9591 01:24:46.501579 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9592 01:24:46.504533 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9593 01:24:46.511337 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9594 01:24:46.514624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9595 01:24:46.518036 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9596 01:24:46.524999 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9597 01:24:46.528021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9598 01:24:46.534567 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9599 01:24:46.537902 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9600 01:24:46.541455 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9601 01:24:46.548324 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9602 01:24:46.551815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9603 01:24:46.554597 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9604 01:24:46.561105 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9605 01:24:46.564645 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9606 01:24:46.571430 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9607 01:24:46.574980 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9608 01:24:46.577726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9609 01:24:46.584788 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9610 01:24:46.587858 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9611 01:24:46.594495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9612 01:24:46.597724 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9613 01:24:46.600961 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9614 01:24:46.608080 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9615 01:24:46.611345 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9616 01:24:46.614783 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9617 01:24:46.621414 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9618 01:24:46.624891 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9619 01:24:46.631226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9620 01:24:46.634453 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9621 01:24:46.638190 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9622 01:24:46.644970 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9623 01:24:46.647910 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9624 01:24:46.654783 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9625 01:24:46.658393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9626 01:24:46.661358 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9627 01:24:46.667822 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9628 01:24:46.671261 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9629 01:24:46.674707 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9630 01:24:46.681335 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9631 01:24:46.684736 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9632 01:24:46.690947 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9633 01:24:46.694526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9634 01:24:46.698040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9635 01:24:46.704371 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9636 01:24:46.708175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9637 01:24:46.714484 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9638 01:24:46.717467 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9639 01:24:46.721332 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9640 01:24:46.727864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9641 01:24:46.731211 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9642 01:24:46.737746 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9643 01:24:46.741059 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9644 01:24:46.744169 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9645 01:24:46.750834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9646 01:24:46.754002 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9647 01:24:46.760614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9648 01:24:46.764120 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9649 01:24:46.768009 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9650 01:24:46.774114 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9651 01:24:46.777103 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9652 01:24:46.784106 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9653 01:24:46.787029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9654 01:24:46.790672 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9655 01:24:46.797459 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9656 01:24:46.800371 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9657 01:24:46.807336 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9658 01:24:46.810236 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9659 01:24:46.814102 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9660 01:24:46.820665 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9661 01:24:46.823990 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9662 01:24:46.830123 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9663 01:24:46.833619 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9664 01:24:46.837048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9665 01:24:46.843473 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9666 01:24:46.847081 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9667 01:24:46.853463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9668 01:24:46.856767 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9669 01:24:46.863550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9670 01:24:46.866591 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9671 01:24:46.869967 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9672 01:24:46.876590 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9673 01:24:46.880377 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9674 01:24:46.886858 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9675 01:24:46.889896 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9676 01:24:46.893413 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9677 01:24:46.899964 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9678 01:24:46.902983 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9679 01:24:46.909864 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9680 01:24:46.913265 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9681 01:24:46.919684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9682 01:24:46.923212 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9683 01:24:46.926910 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9684 01:24:46.933347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9685 01:24:46.936232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9686 01:24:46.943094 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9687 01:24:46.946608 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9688 01:24:46.952838 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9689 01:24:46.956203 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9690 01:24:46.959805 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9691 01:24:46.966075 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9692 01:24:46.969821 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9693 01:24:46.976083 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9694 01:24:46.979922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9695 01:24:46.982724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9696 01:24:46.989194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9697 01:24:46.992894 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9698 01:24:46.995828 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9699 01:24:47.002964 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9700 01:24:47.005937 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9701 01:24:47.009460 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9702 01:24:47.012849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9703 01:24:47.019210 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9704 01:24:47.022647 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9705 01:24:47.029158 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9706 01:24:47.032770 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9707 01:24:47.036297 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9708 01:24:47.042274 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9709 01:24:47.046069 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9710 01:24:47.049317 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9711 01:24:47.056276 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9712 01:24:47.059549 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9713 01:24:47.062803 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9714 01:24:47.069090 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9715 01:24:47.072563 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9716 01:24:47.078847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9717 01:24:47.082257 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9718 01:24:47.085583 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9719 01:24:47.092133 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9720 01:24:47.095527 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9721 01:24:47.099085 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9722 01:24:47.105504 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9723 01:24:47.108929 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9724 01:24:47.112067 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9725 01:24:47.118827 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9726 01:24:47.122467 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9727 01:24:47.125615 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9728 01:24:47.132107 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9729 01:24:47.135703 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9730 01:24:47.142139 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9731 01:24:47.145228 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9732 01:24:47.148863 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9733 01:24:47.155390 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9734 01:24:47.158615 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9735 01:24:47.165277 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9736 01:24:47.168507 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9737 01:24:47.171797 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9738 01:24:47.175016 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9739 01:24:47.181574 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9740 01:24:47.184918 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9741 01:24:47.188580 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9742 01:24:47.191773 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9743 01:24:47.198346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9744 01:24:47.201553 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9745 01:24:47.205003 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9746 01:24:47.207910 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9747 01:24:47.215243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9748 01:24:47.217966 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9749 01:24:47.221507 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9750 01:24:47.225103 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9751 01:24:47.231129 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9752 01:24:47.234763 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9753 01:24:47.241187 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9754 01:24:47.244840 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9755 01:24:47.251603 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9756 01:24:47.254401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9757 01:24:47.257995 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9758 01:24:47.264327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9759 01:24:47.267912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9760 01:24:47.274825 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9761 01:24:47.277837 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9762 01:24:47.281253 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9763 01:24:47.287491 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9764 01:24:47.290858 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9765 01:24:47.297909 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9766 01:24:47.300592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9767 01:24:47.307240 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9768 01:24:47.310786 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9769 01:24:47.314106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9770 01:24:47.320659 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9771 01:24:47.323611 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9772 01:24:47.330316 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9773 01:24:47.333934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9774 01:24:47.337294 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9775 01:24:47.343938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9776 01:24:47.346808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9777 01:24:47.353995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9778 01:24:47.356854 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9779 01:24:47.363700 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9780 01:24:47.367167 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9781 01:24:47.370065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9782 01:24:47.376567 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9783 01:24:47.380106 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9784 01:24:47.386447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9785 01:24:47.389727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9786 01:24:47.393363 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9787 01:24:47.400058 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9788 01:24:47.403065 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9789 01:24:47.410130 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9790 01:24:47.413148 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9791 01:24:47.416374 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9792 01:24:47.423237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9793 01:24:47.426819 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9794 01:24:47.432762 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9795 01:24:47.436269 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9796 01:24:47.443063 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9797 01:24:47.446166 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9798 01:24:47.449730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9799 01:24:47.456269 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9800 01:24:47.459288 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9801 01:24:47.466204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9802 01:24:47.469624 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9803 01:24:47.472877 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9804 01:24:47.479378 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9805 01:24:47.483065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9806 01:24:47.489397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9807 01:24:47.492754 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9808 01:24:47.496199 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9809 01:24:47.502966 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9810 01:24:47.505871 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9811 01:24:47.512454 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9812 01:24:47.516084 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9813 01:24:47.522942 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9814 01:24:47.525911 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9815 01:24:47.529292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9816 01:24:47.535804 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9817 01:24:47.539191 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9818 01:24:47.545779 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9819 01:24:47.549272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9820 01:24:47.552473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9821 01:24:47.559340 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9822 01:24:47.562568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9823 01:24:47.569008 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9824 01:24:47.572549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9825 01:24:47.575580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9826 01:24:47.582327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9827 01:24:47.586053 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9828 01:24:47.592104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9829 01:24:47.595644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9830 01:24:47.601804 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9831 01:24:47.605117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9832 01:24:47.611996 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9833 01:24:47.615532 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9834 01:24:47.621543 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9835 01:24:47.624973 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9836 01:24:47.628704 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9837 01:24:47.634945 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9838 01:24:47.638418 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9839 01:24:47.645241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9840 01:24:47.648126 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9841 01:24:47.655055 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9842 01:24:47.658757 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9843 01:24:47.661763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9844 01:24:47.668294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9845 01:24:47.671290 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9846 01:24:47.678454 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9847 01:24:47.681482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9848 01:24:47.687949 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9849 01:24:47.691721 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9850 01:24:47.695002 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9851 01:24:47.701945 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9852 01:24:47.705171 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9853 01:24:47.711363 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9854 01:24:47.715274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9855 01:24:47.721519 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9856 01:24:47.725068 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9857 01:24:47.728173 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9858 01:24:47.734586 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9859 01:24:47.738096 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9860 01:24:47.744642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9861 01:24:47.748302 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9862 01:24:47.754282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9863 01:24:47.757648 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9864 01:24:47.764299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9865 01:24:47.767710 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9866 01:24:47.770895 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9867 01:24:47.777694 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9868 01:24:47.780834 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9869 01:24:47.787828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9870 01:24:47.790826 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9871 01:24:47.794582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9872 01:24:47.801001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9873 01:24:47.804402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9874 01:24:47.810764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9875 01:24:47.814249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9876 01:24:47.820578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9877 01:24:47.823863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9878 01:24:47.831084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9879 01:24:47.834288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9880 01:24:47.840959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9881 01:24:47.844283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9882 01:24:47.851081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9883 01:24:47.853915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9884 01:24:47.860522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9885 01:24:47.864172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9886 01:24:47.870646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9887 01:24:47.873828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9888 01:24:47.880507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9889 01:24:47.883889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9890 01:24:47.887477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9891 01:24:47.893621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9892 01:24:47.900553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9893 01:24:47.904044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9894 01:24:47.907188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9895 01:24:47.914162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9896 01:24:47.920482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9897 01:24:47.923847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9898 01:24:47.930383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9899 01:24:47.933789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9900 01:24:47.940326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9901 01:24:47.943624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9902 01:24:47.950115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9903 01:24:47.953648 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9904 01:24:47.953731 INFO: [APUAPC] vio 0
9905 01:24:47.960788 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9906 01:24:47.964342 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9907 01:24:47.967711 INFO: [APUAPC] D0_APC_0: 0x400510
9908 01:24:47.971086 INFO: [APUAPC] D0_APC_1: 0x0
9909 01:24:47.974004 INFO: [APUAPC] D0_APC_2: 0x1540
9910 01:24:47.977402 INFO: [APUAPC] D0_APC_3: 0x0
9911 01:24:47.980989 INFO: [APUAPC] D1_APC_0: 0xffffffff
9912 01:24:47.984443 INFO: [APUAPC] D1_APC_1: 0xffffffff
9913 01:24:47.987693 INFO: [APUAPC] D1_APC_2: 0x3fffff
9914 01:24:47.991513 INFO: [APUAPC] D1_APC_3: 0x0
9915 01:24:47.994524 INFO: [APUAPC] D2_APC_0: 0xffffffff
9916 01:24:47.998089 INFO: [APUAPC] D2_APC_1: 0xffffffff
9917 01:24:48.001136 INFO: [APUAPC] D2_APC_2: 0x3fffff
9918 01:24:48.004242 INFO: [APUAPC] D2_APC_3: 0x0
9919 01:24:48.007736 INFO: [APUAPC] D3_APC_0: 0xffffffff
9920 01:24:48.010927 INFO: [APUAPC] D3_APC_1: 0xffffffff
9921 01:24:48.014290 INFO: [APUAPC] D3_APC_2: 0x3fffff
9922 01:24:48.017418 INFO: [APUAPC] D3_APC_3: 0x0
9923 01:24:48.020959 INFO: [APUAPC] D4_APC_0: 0xffffffff
9924 01:24:48.024421 INFO: [APUAPC] D4_APC_1: 0xffffffff
9925 01:24:48.027163 INFO: [APUAPC] D4_APC_2: 0x3fffff
9926 01:24:48.027246 INFO: [APUAPC] D4_APC_3: 0x0
9927 01:24:48.033642 INFO: [APUAPC] D5_APC_0: 0xffffffff
9928 01:24:48.037094 INFO: [APUAPC] D5_APC_1: 0xffffffff
9929 01:24:48.040482 INFO: [APUAPC] D5_APC_2: 0x3fffff
9930 01:24:48.040566 INFO: [APUAPC] D5_APC_3: 0x0
9931 01:24:48.043817 INFO: [APUAPC] D6_APC_0: 0xffffffff
9932 01:24:48.046950 INFO: [APUAPC] D6_APC_1: 0xffffffff
9933 01:24:48.050620 INFO: [APUAPC] D6_APC_2: 0x3fffff
9934 01:24:48.053999 INFO: [APUAPC] D6_APC_3: 0x0
9935 01:24:48.057027 INFO: [APUAPC] D7_APC_0: 0xffffffff
9936 01:24:48.060554 INFO: [APUAPC] D7_APC_1: 0xffffffff
9937 01:24:48.063374 INFO: [APUAPC] D7_APC_2: 0x3fffff
9938 01:24:48.066996 INFO: [APUAPC] D7_APC_3: 0x0
9939 01:24:48.070238 INFO: [APUAPC] D8_APC_0: 0xffffffff
9940 01:24:48.073463 INFO: [APUAPC] D8_APC_1: 0xffffffff
9941 01:24:48.076936 INFO: [APUAPC] D8_APC_2: 0x3fffff
9942 01:24:48.080446 INFO: [APUAPC] D8_APC_3: 0x0
9943 01:24:48.083972 INFO: [APUAPC] D9_APC_0: 0xffffffff
9944 01:24:48.087011 INFO: [APUAPC] D9_APC_1: 0xffffffff
9945 01:24:48.090549 INFO: [APUAPC] D9_APC_2: 0x3fffff
9946 01:24:48.093320 INFO: [APUAPC] D9_APC_3: 0x0
9947 01:24:48.096994 INFO: [APUAPC] D10_APC_0: 0xffffffff
9948 01:24:48.099962 INFO: [APUAPC] D10_APC_1: 0xffffffff
9949 01:24:48.103379 INFO: [APUAPC] D10_APC_2: 0x3fffff
9950 01:24:48.106719 INFO: [APUAPC] D10_APC_3: 0x0
9951 01:24:48.109894 INFO: [APUAPC] D11_APC_0: 0xffffffff
9952 01:24:48.113464 INFO: [APUAPC] D11_APC_1: 0xffffffff
9953 01:24:48.116600 INFO: [APUAPC] D11_APC_2: 0x3fffff
9954 01:24:48.120060 INFO: [APUAPC] D11_APC_3: 0x0
9955 01:24:48.123292 INFO: [APUAPC] D12_APC_0: 0xffffffff
9956 01:24:48.126576 INFO: [APUAPC] D12_APC_1: 0xffffffff
9957 01:24:48.130150 INFO: [APUAPC] D12_APC_2: 0x3fffff
9958 01:24:48.133214 INFO: [APUAPC] D12_APC_3: 0x0
9959 01:24:48.136620 INFO: [APUAPC] D13_APC_0: 0xffffffff
9960 01:24:48.139717 INFO: [APUAPC] D13_APC_1: 0xffffffff
9961 01:24:48.143353 INFO: [APUAPC] D13_APC_2: 0x3fffff
9962 01:24:48.146398 INFO: [APUAPC] D13_APC_3: 0x0
9963 01:24:48.149624 INFO: [APUAPC] D14_APC_0: 0xffffffff
9964 01:24:48.153412 INFO: [APUAPC] D14_APC_1: 0xffffffff
9965 01:24:48.156584 INFO: [APUAPC] D14_APC_2: 0x3fffff
9966 01:24:48.159745 INFO: [APUAPC] D14_APC_3: 0x0
9967 01:24:48.163083 INFO: [APUAPC] D15_APC_0: 0xffffffff
9968 01:24:48.166803 INFO: [APUAPC] D15_APC_1: 0xffffffff
9969 01:24:48.169474 INFO: [APUAPC] D15_APC_2: 0x3fffff
9970 01:24:48.173138 INFO: [APUAPC] D15_APC_3: 0x0
9971 01:24:48.175987 INFO: [APUAPC] APC_CON: 0x4
9972 01:24:48.179408 INFO: [NOCDAPC] D0_APC_0: 0x0
9973 01:24:48.182929 INFO: [NOCDAPC] D0_APC_1: 0x0
9974 01:24:48.186399 INFO: [NOCDAPC] D1_APC_0: 0x0
9975 01:24:48.189318 INFO: [NOCDAPC] D1_APC_1: 0xfff
9976 01:24:48.192865 INFO: [NOCDAPC] D2_APC_0: 0x0
9977 01:24:48.195935 INFO: [NOCDAPC] D2_APC_1: 0xfff
9978 01:24:48.196018 INFO: [NOCDAPC] D3_APC_0: 0x0
9979 01:24:48.199261 INFO: [NOCDAPC] D3_APC_1: 0xfff
9980 01:24:48.202844 INFO: [NOCDAPC] D4_APC_0: 0x0
9981 01:24:48.205885 INFO: [NOCDAPC] D4_APC_1: 0xfff
9982 01:24:48.209428 INFO: [NOCDAPC] D5_APC_0: 0x0
9983 01:24:48.212388 INFO: [NOCDAPC] D5_APC_1: 0xfff
9984 01:24:48.215991 INFO: [NOCDAPC] D6_APC_0: 0x0
9985 01:24:48.218984 INFO: [NOCDAPC] D6_APC_1: 0xfff
9986 01:24:48.222591 INFO: [NOCDAPC] D7_APC_0: 0x0
9987 01:24:48.226188 INFO: [NOCDAPC] D7_APC_1: 0xfff
9988 01:24:48.229101 INFO: [NOCDAPC] D8_APC_0: 0x0
9989 01:24:48.232418 INFO: [NOCDAPC] D8_APC_1: 0xfff
9990 01:24:48.232501 INFO: [NOCDAPC] D9_APC_0: 0x0
9991 01:24:48.235581 INFO: [NOCDAPC] D9_APC_1: 0xfff
9992 01:24:48.238817 INFO: [NOCDAPC] D10_APC_0: 0x0
9993 01:24:48.242598 INFO: [NOCDAPC] D10_APC_1: 0xfff
9994 01:24:48.245473 INFO: [NOCDAPC] D11_APC_0: 0x0
9995 01:24:48.249041 INFO: [NOCDAPC] D11_APC_1: 0xfff
9996 01:24:48.252397 INFO: [NOCDAPC] D12_APC_0: 0x0
9997 01:24:48.255895 INFO: [NOCDAPC] D12_APC_1: 0xfff
9998 01:24:48.258765 INFO: [NOCDAPC] D13_APC_0: 0x0
9999 01:24:48.262125 INFO: [NOCDAPC] D13_APC_1: 0xfff
10000 01:24:48.265550 INFO: [NOCDAPC] D14_APC_0: 0x0
10001 01:24:48.268683 INFO: [NOCDAPC] D14_APC_1: 0xfff
10002 01:24:48.272086 INFO: [NOCDAPC] D15_APC_0: 0x0
10003 01:24:48.275722 INFO: [NOCDAPC] D15_APC_1: 0xfff
10004 01:24:48.275806 INFO: [NOCDAPC] APC_CON: 0x4
10005 01:24:48.282041 INFO: [APUAPC] set_apusys_apc done
10006 01:24:48.282124 INFO: [DEVAPC] devapc_init done
10007 01:24:48.288551 INFO: GICv3 without legacy support detected.
10008 01:24:48.292094 INFO: ARM GICv3 driver initialized in EL3
10009 01:24:48.295070 INFO: Maximum SPI INTID supported: 639
10010 01:24:48.298480 INFO: BL31: Initializing runtime services
10011 01:24:48.305313 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10012 01:24:48.308359 INFO: SPM: enable CPC mode
10013 01:24:48.311858 INFO: mcdi ready for mcusys-off-idle and system suspend
10014 01:24:48.318511 INFO: BL31: Preparing for EL3 exit to normal world
10015 01:24:48.322296 INFO: Entry point address = 0x80000000
10016 01:24:48.322379 INFO: SPSR = 0x8
10017 01:24:48.329181
10018 01:24:48.329263
10019 01:24:48.329328
10020 01:24:48.332268 Starting depthcharge on Spherion...
10021 01:24:48.332350
10022 01:24:48.332415 Wipe memory regions:
10023 01:24:48.332475
10024 01:24:48.333134 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10025 01:24:48.333236 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10026 01:24:48.333319 Setting prompt string to ['asurada:']
10027 01:24:48.333399 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10028 01:24:48.335805 [0x00000040000000, 0x00000054600000)
10029 01:24:48.457713
10030 01:24:48.457840 [0x00000054660000, 0x00000080000000)
10031 01:24:48.718477
10032 01:24:48.718626 [0x000000821a7280, 0x000000ffe64000)
10033 01:24:49.463467
10034 01:24:49.466167 [0x00000100000000, 0x00000240000000)
10035 01:24:51.354074
10036 01:24:51.357150 Initializing XHCI USB controller at 0x11200000.
10037 01:24:52.394596
10038 01:24:52.397964 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10039 01:24:52.398053
10040 01:24:52.398119
10041 01:24:52.398181
10042 01:24:52.398460 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 01:24:52.498790 asurada: tftpboot 192.168.201.1 11368524/tftp-deploy-rw4vapas/kernel/image.itb 11368524/tftp-deploy-rw4vapas/kernel/cmdline
10045 01:24:52.498931 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 01:24:52.499016 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10047 01:24:52.503677 tftpboot 192.168.201.1 11368524/tftp-deploy-rw4vapas/kernel/image.itp-deploy-rw4vapas/kernel/cmdline
10048 01:24:52.503763
10049 01:24:52.503829 Waiting for link
10050 01:24:52.664064
10051 01:24:52.664205 R8152: Initializing
10052 01:24:52.664274
10053 01:24:52.667366 Version 6 (ocp_data = 5c30)
10054 01:24:52.667491
10055 01:24:52.670292 R8152: Done initializing
10056 01:24:52.670375
10057 01:24:52.670441 Adding net device
10058 01:24:54.573807
10059 01:24:54.573941 done.
10060 01:24:54.574010
10061 01:24:54.574073 MAC: 00:24:32:30:78:ff
10062 01:24:54.574132
10063 01:24:54.576772 Sending DHCP discover... done.
10064 01:24:54.576882
10065 01:24:54.580471 Waiting for reply... done.
10066 01:24:54.580556
10067 01:24:54.583636 Sending DHCP request... done.
10068 01:24:54.583719
10069 01:24:54.587715 Waiting for reply... done.
10070 01:24:54.587798
10071 01:24:54.587863 My ip is 192.168.201.21
10072 01:24:54.587924
10073 01:24:54.591117 The DHCP server ip is 192.168.201.1
10074 01:24:54.591201
10075 01:24:54.597891 TFTP server IP predefined by user: 192.168.201.1
10076 01:24:54.597974
10077 01:24:54.604288 Bootfile predefined by user: 11368524/tftp-deploy-rw4vapas/kernel/image.itb
10078 01:24:54.604371
10079 01:24:54.607840 Sending tftp read request... done.
10080 01:24:54.607923
10081 01:24:54.611339 Waiting for the transfer...
10082 01:24:54.611465
10083 01:24:55.184628 00000000 ################################################################
10084 01:24:55.184768
10085 01:24:55.769797 00080000 ################################################################
10086 01:24:55.769957
10087 01:24:56.354716 00100000 ################################################################
10088 01:24:56.354855
10089 01:24:56.936121 00180000 ################################################################
10090 01:24:56.936265
10091 01:24:57.519933 00200000 ################################################################
10092 01:24:57.520066
10093 01:24:58.117073 00280000 ################################################################
10094 01:24:58.117266
10095 01:24:58.738738 00300000 ################################################################
10096 01:24:58.738884
10097 01:24:59.315507 00380000 ################################################################
10098 01:24:59.315757
10099 01:24:59.870049 00400000 ################################################################
10100 01:24:59.870196
10101 01:25:00.415180 00480000 ################################################################
10102 01:25:00.415346
10103 01:25:00.958095 00500000 ################################################################
10104 01:25:00.958267
10105 01:25:01.508869 00580000 ################################################################
10106 01:25:01.509007
10107 01:25:02.070290 00600000 ################################################################
10108 01:25:02.070466
10109 01:25:02.620473 00680000 ################################################################
10110 01:25:02.620614
10111 01:25:03.175667 00700000 ################################################################
10112 01:25:03.175817
10113 01:25:03.720148 00780000 ################################################################
10114 01:25:03.720293
10115 01:25:04.275146 00800000 ################################################################
10116 01:25:04.275321
10117 01:25:04.829151 00880000 ################################################################
10118 01:25:04.829322
10119 01:25:05.373522 00900000 ################################################################
10120 01:25:05.373692
10121 01:25:05.919907 00980000 ################################################################
10122 01:25:05.920077
10123 01:25:06.466595 00a00000 ################################################################
10124 01:25:06.466746
10125 01:25:07.013468 00a80000 ################################################################
10126 01:25:07.013622
10127 01:25:07.561578 00b00000 ################################################################
10128 01:25:07.561728
10129 01:25:08.100911 00b80000 ################################################################
10130 01:25:08.101068
10131 01:25:08.645272 00c00000 ################################################################
10132 01:25:08.645423
10133 01:25:09.176252 00c80000 ################################################################
10134 01:25:09.176426
10135 01:25:09.710583 00d00000 ################################################################
10136 01:25:09.710732
10137 01:25:10.261267 00d80000 ################################################################
10138 01:25:10.261402
10139 01:25:10.814607 00e00000 ################################################################
10140 01:25:10.814749
10141 01:25:11.340614 00e80000 ################################################################
10142 01:25:11.340752
10143 01:25:11.879648 00f00000 ################################################################
10144 01:25:11.879787
10145 01:25:12.439530 00f80000 ################################################################
10146 01:25:12.439684
10147 01:25:12.988539 01000000 ################################################################
10148 01:25:12.988692
10149 01:25:13.529704 01080000 ################################################################
10150 01:25:13.529864
10151 01:25:14.077878 01100000 ################################################################
10152 01:25:14.078042
10153 01:25:14.621088 01180000 ################################################################
10154 01:25:14.621253
10155 01:25:15.165601 01200000 ################################################################
10156 01:25:15.165740
10157 01:25:15.715542 01280000 ################################################################
10158 01:25:15.715695
10159 01:25:16.253004 01300000 ################################################################
10160 01:25:16.253146
10161 01:25:16.799094 01380000 ################################################################
10162 01:25:16.799264
10163 01:25:17.325488 01400000 ################################################################
10164 01:25:17.325640
10165 01:25:17.867121 01480000 ################################################################
10166 01:25:17.867291
10167 01:25:18.395768 01500000 ################################################################
10168 01:25:18.395915
10169 01:25:18.929176 01580000 ################################################################
10170 01:25:18.929340
10171 01:25:19.453390 01600000 ################################################################
10172 01:25:19.453535
10173 01:25:20.112118 01680000 ################################################################
10174 01:25:20.112741
10175 01:25:20.825958 01700000 ################################################################
10176 01:25:20.826552
10177 01:25:21.551501 01780000 ################################################################
10178 01:25:21.552028
10179 01:25:22.286817 01800000 ################################################################
10180 01:25:22.287366
10181 01:25:23.001919 01880000 ################################################################
10182 01:25:23.002432
10183 01:25:23.700727 01900000 ################################################################
10184 01:25:23.701308
10185 01:25:24.432790 01980000 ################################################################
10186 01:25:24.433292
10187 01:25:25.156831 01a00000 ################################################################
10188 01:25:25.157421
10189 01:25:25.883247 01a80000 ################################################################
10190 01:25:25.883787
10191 01:25:26.607745 01b00000 ################################################################
10192 01:25:26.608324
10193 01:25:27.328014 01b80000 ################################################################
10194 01:25:27.328747
10195 01:25:27.962727 01c00000 ################################################################
10196 01:25:27.963226
10197 01:25:28.668623 01c80000 ################################################################
10198 01:25:28.669407
10199 01:25:29.337825 01d00000 ################################################################
10200 01:25:29.337961
10201 01:25:30.000993 01d80000 ################################################################
10202 01:25:30.001141
10203 01:25:30.626687 01e00000 ################################################################
10204 01:25:30.627186
10205 01:25:31.334904 01e80000 ################################################################
10206 01:25:31.335561
10207 01:25:32.066685 01f00000 ################################################################
10208 01:25:32.067421
10209 01:25:32.700705 01f80000 ################################################################
10210 01:25:32.701205
10211 01:25:33.419841 02000000 ################################################################
10212 01:25:33.420350
10213 01:25:34.048526 02080000 ################################################################
10214 01:25:34.048679
10215 01:25:34.669115 02100000 ################################################################
10216 01:25:34.669262
10217 01:25:35.319225 02180000 ################################################################
10218 01:25:35.319803
10219 01:25:35.994388 02200000 ################################################################
10220 01:25:35.994535
10221 01:25:36.677953 02280000 ################################################################
10222 01:25:36.678493
10223 01:25:37.347320 02300000 ################################################################
10224 01:25:37.347940
10225 01:25:38.056277 02380000 ################################################################
10226 01:25:38.056859
10227 01:25:38.718139 02400000 ################################################################
10228 01:25:38.718421
10229 01:25:39.327075 02480000 ################################################################
10230 01:25:39.327224
10231 01:25:39.932592 02500000 ################################################################
10232 01:25:39.933137
10233 01:25:40.641555 02580000 ################################################################
10234 01:25:40.642072
10235 01:25:41.365205 02600000 ################################################################
10236 01:25:41.365781
10237 01:25:42.097486 02680000 ################################################################
10238 01:25:42.098104
10239 01:25:42.815488 02700000 ################################################################
10240 01:25:42.815987
10241 01:25:43.468737 02780000 ################################################################
10242 01:25:43.468873
10243 01:25:44.106220 02800000 ################################################################
10244 01:25:44.106858
10245 01:25:44.749734 02880000 ################################################################
10246 01:25:44.749888
10247 01:25:45.428113 02900000 ################################################################
10248 01:25:45.428799
10249 01:25:46.126303 02980000 ################################################################
10250 01:25:46.126831
10251 01:25:46.800526 02a00000 ################################################################
10252 01:25:46.801095
10253 01:25:47.507745 02a80000 ################################################################
10254 01:25:47.508304
10255 01:25:48.252222 02b00000 ################################################################
10256 01:25:48.252810
10257 01:25:48.942585 02b80000 ################################################################
10258 01:25:48.943149
10259 01:25:49.667408 02c00000 ################################################################
10260 01:25:49.667916
10261 01:25:50.339483 02c80000 ################################################################
10262 01:25:50.339706
10263 01:25:50.992069 02d00000 ################################################################
10264 01:25:50.992738
10265 01:25:51.741929 02d80000 ################################################################
10266 01:25:51.742484
10267 01:25:52.469255 02e00000 ################################################################
10268 01:25:52.469770
10269 01:25:53.198741 02e80000 ################################################################
10270 01:25:53.199289
10271 01:25:53.935233 02f00000 ################################################################
10272 01:25:53.935787
10273 01:25:54.670898 02f80000 ################################################################
10274 01:25:54.671489
10275 01:25:54.789502 03000000 ########### done.
10276 01:25:54.790047
10277 01:25:54.792737 The bootfile was 50415578 bytes long.
10278 01:25:54.793169
10279 01:25:54.795783 Sending tftp read request... done.
10280 01:25:54.796339
10281 01:25:54.799094 Waiting for the transfer...
10282 01:25:54.799564
10283 01:25:54.802163 00000000 # done.
10284 01:25:54.802589
10285 01:25:54.808990 Command line loaded dynamically from TFTP file: 11368524/tftp-deploy-rw4vapas/kernel/cmdline
10286 01:25:54.809571
10287 01:25:54.822344 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10288 01:25:54.822875
10289 01:25:54.825561 Loading FIT.
10290 01:25:54.825981
10291 01:25:54.828834 Image ramdisk-1 has 39327600 bytes.
10292 01:25:54.829253
10293 01:25:54.829580 Image fdt-1 has 47278 bytes.
10294 01:25:54.829892
10295 01:25:54.832345 Image kernel-1 has 11038667 bytes.
10296 01:25:54.832775
10297 01:25:54.842035 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10298 01:25:54.842466
10299 01:25:54.858911 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10300 01:25:54.859649
10301 01:25:54.865151 Choosing best match conf-1 for compat google,spherion-rev2.
10302 01:25:54.869554
10303 01:25:54.874508 Connected to device vid:did:rid of 1ae0:0028:00
10304 01:25:54.881465
10305 01:25:54.884184 tpm_get_response: command 0x17b, return code 0x0
10306 01:25:54.884658
10307 01:25:54.887927 ec_init: CrosEC protocol v3 supported (256, 248)
10308 01:25:54.891968
10309 01:25:54.894793 tpm_cleanup: add release locality here.
10310 01:25:54.895269
10311 01:25:54.895710 Shutting down all USB controllers.
10312 01:25:54.898221
10313 01:25:54.898787 Removing current net device
10314 01:25:54.899164
10315 01:25:54.904644 Exiting depthcharge with code 4 at timestamp: 95849038
10316 01:25:54.905207
10317 01:25:54.908437 LZMA decompressing kernel-1 to 0x821a6718
10318 01:25:54.908914
10319 01:25:54.911643 LZMA decompressing kernel-1 to 0x40000000
10320 01:25:56.298031
10321 01:25:56.298661 jumping to kernel
10322 01:25:56.300315 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10323 01:25:56.300869 start: 2.2.5 auto-login-action (timeout 00:03:17) [common]
10324 01:25:56.301461 Setting prompt string to ['Linux version [0-9]']
10325 01:25:56.301855 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10326 01:25:56.302241 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10327 01:25:56.380049
10328 01:25:56.383352 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10329 01:25:56.387129 start: 2.2.5.1 login-action (timeout 00:03:17) [common]
10330 01:25:56.387759 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10331 01:25:56.388170 Setting prompt string to []
10332 01:25:56.388619 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10333 01:25:56.389032 Using line separator: #'\n'#
10334 01:25:56.389375 No login prompt set.
10335 01:25:56.389708 Parsing kernel messages
10336 01:25:56.390023 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10337 01:25:56.390592 [login-action] Waiting for messages, (timeout 00:03:17)
10338 01:25:56.406223 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j24548-arm64-gcc-10-defconfig-arm64-chromebook-xnj4p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023
10339 01:25:56.410350 [ 0.000000] random: crng init done
10340 01:25:56.416681 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10341 01:25:56.417256 [ 0.000000] efi: UEFI not found.
10342 01:25:56.426561 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10343 01:25:56.433054 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10344 01:25:56.443214 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10345 01:25:56.452601 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10346 01:25:56.459710 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10347 01:25:56.462732 [ 0.000000] printk: bootconsole [mtk8250] enabled
10348 01:25:56.471723 [ 0.000000] NUMA: No NUMA configuration found
10349 01:25:56.478104 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10350 01:25:56.484542 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10351 01:25:56.485255 [ 0.000000] Zone ranges:
10352 01:25:56.492131 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10353 01:25:56.494858 [ 0.000000] DMA32 empty
10354 01:25:56.501551 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10355 01:25:56.504600 [ 0.000000] Movable zone start for each node
10356 01:25:56.507773 [ 0.000000] Early memory node ranges
10357 01:25:56.514902 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10358 01:25:56.520885 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10359 01:25:56.527701 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10360 01:25:56.534051 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10361 01:25:56.540697 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10362 01:25:56.547454 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10363 01:25:56.604594 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10364 01:25:56.610780 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10365 01:25:56.617290 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10366 01:25:56.620677 [ 0.000000] psci: probing for conduit method from DT.
10367 01:25:56.627245 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10368 01:25:56.630597 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10369 01:25:56.637097 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10370 01:25:56.640847 [ 0.000000] psci: SMC Calling Convention v1.2
10371 01:25:56.647032 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10372 01:25:56.650583 [ 0.000000] Detected VIPT I-cache on CPU0
10373 01:25:56.657043 [ 0.000000] CPU features: detected: GIC system register CPU interface
10374 01:25:56.663721 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10375 01:25:56.670632 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10376 01:25:56.676952 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10377 01:25:56.683495 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10378 01:25:56.693663 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10379 01:25:56.696602 [ 0.000000] alternatives: applying boot alternatives
10380 01:25:56.703500 [ 0.000000] Fallback order for Node 0: 0
10381 01:25:56.710100 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10382 01:25:56.713286 [ 0.000000] Policy zone: Normal
10383 01:25:56.726464 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10384 01:25:56.736177 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10385 01:25:56.748244 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10386 01:25:56.758320 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10387 01:25:56.764687 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10388 01:25:56.768035 <6>[ 0.000000] software IO TLB: area num 8.
10389 01:25:56.825737 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10390 01:25:56.974770 <6>[ 0.000000] Memory: 7931148K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 421620K reserved, 32768K cma-reserved)
10391 01:25:56.981381 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10392 01:25:56.988326 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10393 01:25:56.991594 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10394 01:25:56.997653 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10395 01:25:57.004121 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10396 01:25:57.007447 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10397 01:25:57.017478 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10398 01:25:57.024255 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10399 01:25:57.027537 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10400 01:25:57.035967 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10401 01:25:57.039074 <6>[ 0.000000] GICv3: 608 SPIs implemented
10402 01:25:57.045381 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10403 01:25:57.048982 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10404 01:25:57.052062 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10405 01:25:57.062200 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10406 01:25:57.071989 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10407 01:25:57.085774 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10408 01:25:57.091746 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10409 01:25:57.101022 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10410 01:25:57.114175 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10411 01:25:57.121148 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10412 01:25:57.127446 <6>[ 0.009232] Console: colour dummy device 80x25
10413 01:25:57.137633 <6>[ 0.013986] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10414 01:25:57.141262 <6>[ 0.024429] pid_max: default: 32768 minimum: 301
10415 01:25:57.147914 <6>[ 0.029301] LSM: Security Framework initializing
10416 01:25:57.154177 <6>[ 0.034240] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10417 01:25:57.164100 <6>[ 0.042053] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 01:25:57.171241 <6>[ 0.051474] cblist_init_generic: Setting adjustable number of callback queues.
10419 01:25:57.177821 <6>[ 0.058966] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 01:25:57.187491 <6>[ 0.065303] cblist_init_generic: Setting adjustable number of callback queues.
10421 01:25:57.194006 <6>[ 0.072729] cblist_init_generic: Setting shift to 3 and lim to 1.
10422 01:25:57.197608 <6>[ 0.079129] rcu: Hierarchical SRCU implementation.
10423 01:25:57.204050 <6>[ 0.084173] rcu: Max phase no-delay instances is 1000.
10424 01:25:57.211021 <6>[ 0.091210] EFI services will not be available.
10425 01:25:57.213854 <6>[ 0.096179] smp: Bringing up secondary CPUs ...
10426 01:25:57.222079 <6>[ 0.101232] Detected VIPT I-cache on CPU1
10427 01:25:57.228770 <6>[ 0.101303] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10428 01:25:57.235398 <6>[ 0.101336] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10429 01:25:57.238854 <6>[ 0.101668] Detected VIPT I-cache on CPU2
10430 01:25:57.245206 <6>[ 0.101716] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10431 01:25:57.255269 <6>[ 0.101730] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10432 01:25:57.258360 <6>[ 0.101986] Detected VIPT I-cache on CPU3
10433 01:25:57.264982 <6>[ 0.102031] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10434 01:25:57.271721 <6>[ 0.102045] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10435 01:25:57.274983 <6>[ 0.102348] CPU features: detected: Spectre-v4
10436 01:25:57.281730 <6>[ 0.102355] CPU features: detected: Spectre-BHB
10437 01:25:57.285127 <6>[ 0.102359] Detected PIPT I-cache on CPU4
10438 01:25:57.291651 <6>[ 0.102415] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10439 01:25:57.298128 <6>[ 0.102432] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10440 01:25:57.304828 <6>[ 0.102726] Detected PIPT I-cache on CPU5
10441 01:25:57.311946 <6>[ 0.102787] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10442 01:25:57.318098 <6>[ 0.102803] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10443 01:25:57.321492 <6>[ 0.103090] Detected PIPT I-cache on CPU6
10444 01:25:57.328157 <6>[ 0.103153] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10445 01:25:57.334470 <6>[ 0.103169] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10446 01:25:57.340916 <6>[ 0.103470] Detected PIPT I-cache on CPU7
10447 01:25:57.348004 <6>[ 0.103533] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10448 01:25:57.354206 <6>[ 0.103550] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10449 01:25:57.357607 <6>[ 0.103597] smp: Brought up 1 node, 8 CPUs
10450 01:25:57.364140 <6>[ 0.244912] SMP: Total of 8 processors activated.
10451 01:25:57.367504 <6>[ 0.249863] CPU features: detected: 32-bit EL0 Support
10452 01:25:57.377889 <6>[ 0.255259] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10453 01:25:57.384312 <6>[ 0.264059] CPU features: detected: Common not Private translations
10454 01:25:57.390689 <6>[ 0.270534] CPU features: detected: CRC32 instructions
10455 01:25:57.394100 <6>[ 0.275886] CPU features: detected: RCpc load-acquire (LDAPR)
10456 01:25:57.400515 <6>[ 0.281845] CPU features: detected: LSE atomic instructions
10457 01:25:57.407854 <6>[ 0.287627] CPU features: detected: Privileged Access Never
10458 01:25:57.414180 <6>[ 0.293406] CPU features: detected: RAS Extension Support
10459 01:25:57.420328 <6>[ 0.299015] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10460 01:25:57.423436 <6>[ 0.306235] CPU: All CPU(s) started at EL2
10461 01:25:57.430573 <6>[ 0.310578] alternatives: applying system-wide alternatives
10462 01:25:57.439175 <6>[ 0.321233] devtmpfs: initialized
10463 01:25:57.455009 <6>[ 0.330187] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10464 01:25:57.461821 <6>[ 0.340152] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10465 01:25:57.468296 <6>[ 0.348188] pinctrl core: initialized pinctrl subsystem
10466 01:25:57.472166 <6>[ 0.354830] DMI not present or invalid.
10467 01:25:57.477886 <6>[ 0.359242] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10468 01:25:57.488136 <6>[ 0.366101] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10469 01:25:57.494961 <6>[ 0.373690] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10470 01:25:57.504964 <6>[ 0.381907] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10471 01:25:57.507861 <6>[ 0.390153] audit: initializing netlink subsys (disabled)
10472 01:25:57.518032 <5>[ 0.395849] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10473 01:25:57.524279 <6>[ 0.396553] thermal_sys: Registered thermal governor 'step_wise'
10474 01:25:57.530780 <6>[ 0.403818] thermal_sys: Registered thermal governor 'power_allocator'
10475 01:25:57.534448 <6>[ 0.410073] cpuidle: using governor menu
10476 01:25:57.540852 <6>[ 0.421039] NET: Registered PF_QIPCRTR protocol family
10477 01:25:57.547481 <6>[ 0.426524] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10478 01:25:57.555039 <6>[ 0.433632] ASID allocator initialised with 32768 entries
10479 01:25:57.557766 <6>[ 0.440197] Serial: AMBA PL011 UART driver
10480 01:25:57.567105 <4>[ 0.448935] Trying to register duplicate clock ID: 134
10481 01:25:57.623129 <6>[ 0.508298] KASLR enabled
10482 01:25:57.637371 <6>[ 0.516013] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10483 01:25:57.643804 <6>[ 0.523030] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10484 01:25:57.650278 <6>[ 0.529523] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10485 01:25:57.656833 <6>[ 0.536528] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10486 01:25:57.663652 <6>[ 0.543015] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10487 01:25:57.670078 <6>[ 0.550022] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10488 01:25:57.676748 <6>[ 0.556511] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10489 01:25:57.683313 <6>[ 0.563518] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10490 01:25:57.686766 <6>[ 0.570978] ACPI: Interpreter disabled.
10491 01:25:57.695243 <6>[ 0.577400] iommu: Default domain type: Translated
10492 01:25:57.701859 <6>[ 0.582558] iommu: DMA domain TLB invalidation policy: strict mode
10493 01:25:57.705055 <5>[ 0.589218] SCSI subsystem initialized
10494 01:25:57.711859 <6>[ 0.593469] usbcore: registered new interface driver usbfs
10495 01:25:57.718389 <6>[ 0.599202] usbcore: registered new interface driver hub
10496 01:25:57.722057 <6>[ 0.604756] usbcore: registered new device driver usb
10497 01:25:57.728895 <6>[ 0.610875] pps_core: LinuxPPS API ver. 1 registered
10498 01:25:57.738904 <6>[ 0.616071] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10499 01:25:57.742507 <6>[ 0.625416] PTP clock support registered
10500 01:25:57.746021 <6>[ 0.629660] EDAC MC: Ver: 3.0.0
10501 01:25:57.753218 <6>[ 0.634848] FPGA manager framework
10502 01:25:57.759336 <6>[ 0.638526] Advanced Linux Sound Architecture Driver Initialized.
10503 01:25:57.763523 <6>[ 0.645299] vgaarb: loaded
10504 01:25:57.769748 <6>[ 0.648462] clocksource: Switched to clocksource arch_sys_counter
10505 01:25:57.773429 <5>[ 0.654910] VFS: Disk quotas dquot_6.6.0
10506 01:25:57.780140 <6>[ 0.659096] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10507 01:25:57.783097 <6>[ 0.666291] pnp: PnP ACPI: disabled
10508 01:25:57.791243 <6>[ 0.673027] NET: Registered PF_INET protocol family
10509 01:25:57.801186 <6>[ 0.678622] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10510 01:25:57.812346 <6>[ 0.690921] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10511 01:25:57.822594 <6>[ 0.699738] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10512 01:25:57.829010 <6>[ 0.707713] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10513 01:25:57.835831 <6>[ 0.716413] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10514 01:25:57.847749 <6>[ 0.726151] TCP: Hash tables configured (established 65536 bind 65536)
10515 01:25:57.854089 <6>[ 0.733018] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10516 01:25:57.860549 <6>[ 0.740220] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10517 01:25:57.867503 <6>[ 0.747923] NET: Registered PF_UNIX/PF_LOCAL protocol family
10518 01:25:57.874208 <6>[ 0.754012] RPC: Registered named UNIX socket transport module.
10519 01:25:57.877550 <6>[ 0.760164] RPC: Registered udp transport module.
10520 01:25:57.884199 <6>[ 0.765097] RPC: Registered tcp transport module.
10521 01:25:57.890818 <6>[ 0.770030] RPC: Registered tcp NFSv4.1 backchannel transport module.
10522 01:25:57.893849 <6>[ 0.776699] PCI: CLS 0 bytes, default 64
10523 01:25:57.897268 <6>[ 0.781134] Unpacking initramfs...
10524 01:25:57.907273 <6>[ 0.784878] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10525 01:25:57.914053 <6>[ 0.793548] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10526 01:25:57.920608 <6>[ 0.802400] kvm [1]: IPA Size Limit: 40 bits
10527 01:25:57.924256 <6>[ 0.806931] kvm [1]: GICv3: no GICV resource entry
10528 01:25:57.930834 <6>[ 0.811955] kvm [1]: disabling GICv2 emulation
10529 01:25:57.937522 <6>[ 0.816646] kvm [1]: GIC system register CPU interface enabled
10530 01:25:57.940788 <6>[ 0.822827] kvm [1]: vgic interrupt IRQ18
10531 01:25:57.947627 <6>[ 0.828507] kvm [1]: VHE mode initialized successfully
10532 01:25:57.953895 <5>[ 0.834934] Initialise system trusted keyrings
10533 01:25:57.960149 <6>[ 0.839758] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10534 01:25:57.968210 <6>[ 0.849852] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10535 01:25:57.974890 <5>[ 0.856238] NFS: Registering the id_resolver key type
10536 01:25:57.978215 <5>[ 0.861541] Key type id_resolver registered
10537 01:25:57.985067 <5>[ 0.865957] Key type id_legacy registered
10538 01:25:57.991132 <6>[ 0.870240] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10539 01:25:57.997957 <6>[ 0.877166] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10540 01:25:58.004824 <6>[ 0.884899] 9p: Installing v9fs 9p2000 file system support
10541 01:25:58.040897 <5>[ 0.922674] Key type asymmetric registered
10542 01:25:58.044087 <5>[ 0.927007] Asymmetric key parser 'x509' registered
10543 01:25:58.054136 <6>[ 0.932154] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10544 01:25:58.057457 <6>[ 0.939772] io scheduler mq-deadline registered
10545 01:25:58.060949 <6>[ 0.944536] io scheduler kyber registered
10546 01:25:58.079992 <6>[ 0.961721] EINJ: ACPI disabled.
10547 01:25:58.112122 <4>[ 0.987558] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10548 01:25:58.121956 <4>[ 0.998212] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 01:25:58.137593 <6>[ 1.019345] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10550 01:25:58.145594 <6>[ 1.027362] printk: console [ttyS0] disabled
10551 01:25:58.173692 <6>[ 1.052037] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10552 01:25:58.180306 <6>[ 1.061516] printk: console [ttyS0] enabled
10553 01:25:58.183489 <6>[ 1.061516] printk: console [ttyS0] enabled
10554 01:25:58.190102 <6>[ 1.070410] printk: bootconsole [mtk8250] disabled
10555 01:25:58.193298 <6>[ 1.070410] printk: bootconsole [mtk8250] disabled
10556 01:25:58.200341 <6>[ 1.081648] SuperH (H)SCI(F) driver initialized
10557 01:25:58.203598 <6>[ 1.086921] msm_serial: driver initialized
10558 01:25:58.218121 <6>[ 1.095920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10559 01:25:58.227275 <6>[ 1.104473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10560 01:25:58.234036 <6>[ 1.113017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10561 01:25:58.244011 <6>[ 1.121645] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10562 01:25:58.254255 <6>[ 1.130353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10563 01:25:58.261208 <6>[ 1.139071] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10564 01:25:58.270522 <6>[ 1.147611] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10565 01:25:58.277464 <6>[ 1.156416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10566 01:25:58.287183 <6>[ 1.164961] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10567 01:25:58.299202 <6>[ 1.180940] loop: module loaded
10568 01:25:58.305847 <6>[ 1.186972] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10569 01:25:58.328609 <4>[ 1.210474] mtk-pmic-keys: Failed to locate of_node [id: -1]
10570 01:25:58.335933 <6>[ 1.217474] megasas: 07.719.03.00-rc1
10571 01:25:58.345452 <6>[ 1.227004] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10572 01:25:58.358502 <6>[ 1.239846] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10573 01:25:58.374705 <6>[ 1.255828] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10574 01:25:58.430045 <6>[ 1.304999] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10575 01:25:59.490154 <6>[ 2.372434] Freeing initrd memory: 38404K
10576 01:25:59.500686 <6>[ 2.382641] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10577 01:25:59.512428 <6>[ 2.393787] tun: Universal TUN/TAP device driver, 1.6
10578 01:25:59.515475 <6>[ 2.399867] thunder_xcv, ver 1.0
10579 01:25:59.518817 <6>[ 2.403373] thunder_bgx, ver 1.0
10580 01:25:59.521552 <6>[ 2.406869] nicpf, ver 1.0
10581 01:25:59.532327 <6>[ 2.410913] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10582 01:25:59.535928 <6>[ 2.418388] hns3: Copyright (c) 2017 Huawei Corporation.
10583 01:25:59.541947 <6>[ 2.423994] hclge is initializing
10584 01:25:59.545200 <6>[ 2.427574] e1000: Intel(R) PRO/1000 Network Driver
10585 01:25:59.552052 <6>[ 2.432704] e1000: Copyright (c) 1999-2006 Intel Corporation.
10586 01:25:59.555686 <6>[ 2.438716] e1000e: Intel(R) PRO/1000 Network Driver
10587 01:25:59.562006 <6>[ 2.443931] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10588 01:25:59.568759 <6>[ 2.450124] igb: Intel(R) Gigabit Ethernet Network Driver
10589 01:25:59.575341 <6>[ 2.455774] igb: Copyright (c) 2007-2014 Intel Corporation.
10590 01:25:59.581959 <6>[ 2.461611] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10591 01:25:59.589007 <6>[ 2.468129] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10592 01:25:59.592293 <6>[ 2.474594] sky2: driver version 1.30
10593 01:25:59.598383 <6>[ 2.479579] VFIO - User Level meta-driver version: 0.3
10594 01:25:59.605885 <6>[ 2.487808] usbcore: registered new interface driver usb-storage
10595 01:25:59.612403 <6>[ 2.494257] usbcore: registered new device driver onboard-usb-hub
10596 01:25:59.621682 <6>[ 2.503391] mt6397-rtc mt6359-rtc: registered as rtc0
10597 01:25:59.631518 <6>[ 2.508857] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T01:26:00 UTC (1693185960)
10598 01:25:59.634560 <6>[ 2.518423] i2c_dev: i2c /dev entries driver
10599 01:25:59.652317 <6>[ 2.530243] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10600 01:25:59.671450 <6>[ 2.553236] cpu cpu0: EM: created perf domain
10601 01:25:59.675039 <6>[ 2.558264] cpu cpu4: EM: created perf domain
10602 01:25:59.682299 <6>[ 2.563918] sdhci: Secure Digital Host Controller Interface driver
10603 01:25:59.688987 <6>[ 2.570351] sdhci: Copyright(c) Pierre Ossman
10604 01:25:59.695354 <6>[ 2.575303] Synopsys Designware Multimedia Card Interface Driver
10605 01:25:59.702037 <6>[ 2.581935] sdhci-pltfm: SDHCI platform and OF driver helper
10606 01:25:59.705728 <6>[ 2.581991] mmc0: CQHCI version 5.10
10607 01:25:59.712263 <6>[ 2.591866] ledtrig-cpu: registered to indicate activity on CPUs
10608 01:25:59.718738 <6>[ 2.598843] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10609 01:25:59.725448 <6>[ 2.605895] usbcore: registered new interface driver usbhid
10610 01:25:59.729307 <6>[ 2.611718] usbhid: USB HID core driver
10611 01:25:59.735333 <6>[ 2.615914] spi_master spi0: will run message pump with realtime priority
10612 01:25:59.781239 <6>[ 2.656328] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10613 01:25:59.800333 <6>[ 2.672012] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10614 01:25:59.807474 <6>[ 2.686931] cros-ec-spi spi0.0: Chrome EC device registered
10615 01:25:59.810716 <6>[ 2.693015] mmc0: Command Queue Engine enabled
10616 01:25:59.817632 <6>[ 2.697805] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10617 01:25:59.823810 <6>[ 2.705329] mmcblk0: mmc0:0001 DA4128 116 GiB
10618 01:25:59.833785 <6>[ 2.705979] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10619 01:25:59.837492 <6>[ 2.713690] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10620 01:25:59.843596 <6>[ 2.720397] NET: Registered PF_PACKET protocol family
10621 01:25:59.851101 <6>[ 2.726750] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 01:25:59.853542 <6>[ 2.730694] 9pnet: Installing 9P2000 support
10623 01:25:59.857443 <6>[ 2.736441] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10624 01:25:59.864000 <5>[ 2.740380] Key type dns_resolver registered
10625 01:25:59.870214 <6>[ 2.746197] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10626 01:25:59.873530 <6>[ 2.750637] registered taskstats version 1
10627 01:25:59.880762 <5>[ 2.760977] Loading compiled-in X.509 certificates
10628 01:25:59.907703 <4>[ 2.783036] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 01:25:59.918344 <4>[ 2.793726] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 01:25:59.924399 <3>[ 2.804256] debugfs: File 'uA_load' in directory '/' already present!
10631 01:25:59.930791 <3>[ 2.810955] debugfs: File 'min_uV' in directory '/' already present!
10632 01:25:59.937088 <3>[ 2.817626] debugfs: File 'max_uV' in directory '/' already present!
10633 01:25:59.944521 <3>[ 2.824238] debugfs: File 'constraint_flags' in directory '/' already present!
10634 01:25:59.956362 <3>[ 2.834714] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10635 01:25:59.969361 <6>[ 2.851101] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10636 01:25:59.976232 <6>[ 2.857933] xhci-mtk 11200000.usb: xHCI Host Controller
10637 01:25:59.982901 <6>[ 2.863442] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10638 01:25:59.993095 <6>[ 2.871406] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10639 01:25:59.999842 <6>[ 2.880837] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10640 01:26:00.006470 <6>[ 2.886907] xhci-mtk 11200000.usb: xHCI Host Controller
10641 01:26:00.012752 <6>[ 2.892387] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10642 01:26:00.019353 <6>[ 2.900036] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10643 01:26:00.025793 <6>[ 2.907818] hub 1-0:1.0: USB hub found
10644 01:26:00.029009 <6>[ 2.911839] hub 1-0:1.0: 1 port detected
10645 01:26:00.039481 <6>[ 2.916132] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10646 01:26:00.042604 <6>[ 2.924833] hub 2-0:1.0: USB hub found
10647 01:26:00.045662 <6>[ 2.928854] hub 2-0:1.0: 1 port detected
10648 01:26:00.054286 <6>[ 2.935941] mtk-msdc 11f70000.mmc: Got CD GPIO
10649 01:26:00.065272 <6>[ 2.943870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10650 01:26:00.072031 <6>[ 2.951893] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10651 01:26:00.081519 <4>[ 2.959808] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10652 01:26:00.092096 <6>[ 2.969343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10653 01:26:00.098337 <6>[ 2.977421] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10654 01:26:00.105275 <6>[ 2.985433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10655 01:26:00.114876 <6>[ 2.993361] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10656 01:26:00.121484 <6>[ 3.001186] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10657 01:26:00.131874 <6>[ 3.009004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10658 01:26:00.141727 <6>[ 3.019378] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10659 01:26:00.147664 <6>[ 3.027743] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10660 01:26:00.157629 <6>[ 3.036086] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10661 01:26:00.164157 <6>[ 3.044431] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10662 01:26:00.174035 <6>[ 3.052770] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10663 01:26:00.180945 <6>[ 3.061109] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10664 01:26:00.191006 <6>[ 3.069446] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10665 01:26:00.200488 <6>[ 3.077785] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10666 01:26:00.207129 <6>[ 3.086123] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10667 01:26:00.217466 <6>[ 3.094461] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10668 01:26:00.223608 <6>[ 3.102799] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10669 01:26:00.233634 <6>[ 3.111137] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10670 01:26:00.240360 <6>[ 3.119475] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10671 01:26:00.250627 <6>[ 3.127813] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10672 01:26:00.257034 <6>[ 3.136151] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10673 01:26:00.263490 <6>[ 3.144890] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10674 01:26:00.270225 <6>[ 3.152081] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10675 01:26:00.277068 <6>[ 3.158864] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10676 01:26:00.286871 <6>[ 3.165614] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10677 01:26:00.293923 <6>[ 3.172563] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10678 01:26:00.300762 <6>[ 3.179403] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10679 01:26:00.310347 <6>[ 3.188535] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10680 01:26:00.320359 <6>[ 3.197655] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10681 01:26:00.330271 <6>[ 3.206949] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10682 01:26:00.339934 <6>[ 3.216417] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10683 01:26:00.349498 <6>[ 3.225884] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10684 01:26:00.357094 <6>[ 3.235005] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10685 01:26:00.366148 <6>[ 3.244475] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10686 01:26:00.376252 <6>[ 3.253615] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10687 01:26:00.386205 <6>[ 3.262911] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10688 01:26:00.395995 <6>[ 3.273071] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10689 01:26:00.402852 <6>[ 3.276817] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10690 01:26:00.412390 <6>[ 3.284574] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 01:26:00.434325 <6>[ 3.316080] hub 2-1:1.0: USB hub found
10692 01:26:00.437629 <6>[ 3.320529] hub 2-1:1.0: 3 ports detected
10693 01:26:00.558207 <6>[ 3.436728] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10694 01:26:00.713099 <6>[ 3.594862] hub 1-1:1.0: USB hub found
10695 01:26:00.716202 <6>[ 3.599337] hub 1-1:1.0: 4 ports detected
10696 01:26:00.793992 <6>[ 3.673044] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10697 01:26:01.037916 <6>[ 3.916781] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10698 01:26:01.171047 <6>[ 4.052735] hub 1-1.4:1.0: USB hub found
10699 01:26:01.173977 <6>[ 4.057402] hub 1-1.4:1.0: 2 ports detected
10700 01:26:01.469923 <6>[ 4.348757] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10701 01:26:01.662093 <6>[ 4.540754] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10702 01:26:12.687521 <6>[ 15.573782] ALSA device list:
10703 01:26:12.693447 <6>[ 15.577076] No soundcards found.
10704 01:26:12.701913 <6>[ 15.585059] Freeing unused kernel memory: 8384K
10705 01:26:12.705434 <6>[ 15.590061] Run /init as init process
10706 01:26:12.753999 <6>[ 15.637145] NET: Registered PF_INET6 protocol family
10707 01:26:12.760305 <6>[ 15.643714] Segment Routing with IPv6
10708 01:26:12.763687 <6>[ 15.647666] In-situ OAM (IOAM) with IPv6
10709 01:26:12.798945 <30>[ 15.661990] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10710 01:26:12.802169 <30>[ 15.685756] systemd[1]: Detected architecture arm64.
10711 01:26:12.802693
10712 01:26:12.808048 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10713 01:26:12.808563
10714 01:26:12.821601 <30>[ 15.704744] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10715 01:26:12.954491 <30>[ 15.834344] systemd[1]: Queued start job for default target Graphical Interface.
10716 01:26:12.990242 <30>[ 15.873431] systemd[1]: Created slice system-getty.slice.
10717 01:26:12.996774 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10718 01:26:13.014254 <30>[ 15.897043] systemd[1]: Created slice system-modprobe.slice.
10719 01:26:13.020376 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10720 01:26:13.038740 <30>[ 15.921887] systemd[1]: Created slice system-serial\x2dgetty.slice.
10721 01:26:13.048609 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10722 01:26:13.062752 <30>[ 15.945872] systemd[1]: Created slice User and Session Slice.
10723 01:26:13.069205 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10724 01:26:13.089104 <30>[ 15.969315] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10725 01:26:13.099079 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10726 01:26:13.117296 <30>[ 15.997247] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10727 01:26:13.124043 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10728 01:26:13.144110 <30>[ 16.020711] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10729 01:26:13.150377 <30>[ 16.032784] systemd[1]: Reached target Local Encrypted Volumes.
10730 01:26:13.156960 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10731 01:26:13.173800 <30>[ 16.057199] systemd[1]: Reached target Paths.
10732 01:26:13.177542 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10733 01:26:13.193403 <30>[ 16.076709] systemd[1]: Reached target Remote File Systems.
10734 01:26:13.200188 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10735 01:26:13.213577 <30>[ 16.096677] systemd[1]: Reached target Slices.
10736 01:26:13.216846 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10737 01:26:13.234239 <30>[ 16.117104] systemd[1]: Reached target Swap.
10738 01:26:13.237293 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10739 01:26:13.256834 <30>[ 16.137153] systemd[1]: Listening on initctl Compatibility Named Pipe.
10740 01:26:13.263187 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10741 01:26:13.278791 <30>[ 16.162119] systemd[1]: Listening on Journal Audit Socket.
10742 01:26:13.285375 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10743 01:26:13.302757 <30>[ 16.185807] systemd[1]: Listening on Journal Socket (/dev/log).
10744 01:26:13.309338 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10745 01:26:13.325923 <30>[ 16.209170] systemd[1]: Listening on Journal Socket.
10746 01:26:13.332448 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10747 01:26:13.349935 <30>[ 16.230014] systemd[1]: Listening on Network Service Netlink Socket.
10748 01:26:13.356197 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10749 01:26:13.369791 <30>[ 16.253239] systemd[1]: Listening on udev Control Socket.
10750 01:26:13.376104 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10751 01:26:13.394470 <30>[ 16.277703] systemd[1]: Listening on udev Kernel Socket.
10752 01:26:13.400836 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10753 01:26:13.453959 <30>[ 16.336872] systemd[1]: Mounting Huge Pages File System...
10754 01:26:13.459751 Mounting [0;1;39mHuge Pages File System[0m...
10755 01:26:13.474820 <30>[ 16.358531] systemd[1]: Mounting POSIX Message Queue File System...
10756 01:26:13.482357 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10757 01:26:13.499688 <30>[ 16.383020] systemd[1]: Mounting Kernel Debug File System...
10758 01:26:13.505890 Mounting [0;1;39mKernel Debug File System[0m...
10759 01:26:13.524887 <30>[ 16.404981] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10760 01:26:13.538585 <30>[ 16.418262] systemd[1]: Starting Create list of static device nodes for the current kernel...
10761 01:26:13.544761 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10762 01:26:13.566427 <30>[ 16.449316] systemd[1]: Starting Load Kernel Module configfs...
10763 01:26:13.572138 Starting [0;1;39mLoad Kernel Module configfs[0m...
10764 01:26:13.589577 <30>[ 16.473333] systemd[1]: Starting Load Kernel Module drm...
10765 01:26:13.595955 Starting [0;1;39mLoad Kernel Module drm[0m...
10766 01:26:13.612998 <30>[ 16.493145] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10767 01:26:13.627465 <30>[ 16.511065] systemd[1]: Starting Journal Service...
10768 01:26:13.630868 Starting [0;1;39mJournal Service[0m...
10769 01:26:13.654520 <30>[ 16.538029] systemd[1]: Starting Load Kernel Modules...
10770 01:26:13.661122 Starting [0;1;39mLoad Kernel Modules[0m...
10771 01:26:13.701856 <30>[ 16.581811] systemd[1]: Starting Remount Root and Kernel File Systems...
10772 01:26:13.708331 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10773 01:26:13.725384 <30>[ 16.608944] systemd[1]: Starting Coldplug All udev Devices...
10774 01:26:13.731922 Starting [0;1;39mColdplug All udev Devices[0m...
10775 01:26:13.747753 <30>[ 16.631574] systemd[1]: Started Journal Service.
10776 01:26:13.754888 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10777 01:26:13.772768 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10778 01:26:13.790024 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10779 01:26:13.806239 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10780 01:26:13.825879 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10781 01:26:13.843438 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10782 01:26:13.858251 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10783 01:26:13.873963 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10784 01:26:13.893874 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10785 01:26:13.909372 See 'systemctl status systemd-remount-fs.service' for details.
10786 01:26:13.950304 Mounting [0;1;39mKernel Configuration File System[0m...
10787 01:26:13.973122 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10788 01:26:13.986280 <46>[ 16.866474] systemd-journald[185]: Received client request to flush runtime journal.
10789 01:26:13.997488 Starting [0;1;39mLoad/Save Random Seed[0m...
10790 01:26:14.022905 Starting [0;1;39mApply Kernel Variables[0m...
10791 01:26:14.046205 Starting [0;1;39mCreate System Users[0m...
10792 01:26:14.071125 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10793 01:26:14.090381 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10794 01:26:14.110739 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10795 01:26:14.122869 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10796 01:26:14.139258 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10797 01:26:14.154995 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10798 01:26:14.218244 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10799 01:26:14.243480 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10800 01:26:14.258491 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10801 01:26:14.277188 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10802 01:26:14.329629 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10803 01:26:14.357757 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10804 01:26:14.381692 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10805 01:26:14.402558 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10806 01:26:14.451890 Starting [0;1;39mNetwork Service[0m...
10807 01:26:14.479367 Starting [0;1;39mNetwork Time Synchronization[0m...
10808 01:26:14.502231 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10809 01:26:14.529258 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10810 01:26:14.551351 <6>[ 17.431649] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10811 01:26:14.564947 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd<6>[ 17.444778] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10812 01:26:14.574722 _backlight[0m..<6>[ 17.455989] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10813 01:26:14.577943 .
10814 01:26:14.598063 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10815 01:26:14.614692 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10816 01:26:14.647184 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of l<6>[ 17.529562] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10817 01:26:14.656587 eds:white:kbd_ba<6>[ 17.537709] usbcore: registered new interface driver r8152
10818 01:26:14.656679 cklight[0m.
10819 01:26:14.663229 <6>[ 17.546136] remoteproc remoteproc0: scp is available
10820 01:26:14.666784 <6>[ 17.552009] remoteproc remoteproc0: powering up scp
10821 01:26:14.676490 <6>[ 17.557175] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10822 01:26:14.682994 <4>[ 17.557755] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10823 01:26:14.689588 <6>[ 17.565799] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10824 01:26:14.699444 <3>[ 17.567720] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 01:26:14.706433 <4>[ 17.581598] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10826 01:26:14.713311 <3>[ 17.587045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 01:26:14.719654 <6>[ 17.587332] mc: Linux media interface: v0.10
10828 01:26:14.726142 <6>[ 17.587492] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10829 01:26:14.732957 <6>[ 17.608694] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10830 01:26:14.740414 <4>[ 17.610354] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10831 01:26:14.746672 <4>[ 17.610354] Fallback method does not support PEC.
10832 01:26:14.753140 <3>[ 17.614622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 01:26:14.763535 <3>[ 17.615329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 01:26:14.769800 <6>[ 17.616028] videodev: Linux video capture interface: v2.00
10835 01:26:14.773149 <6>[ 17.621660] pci_bus 0000:00: root bus resource [bus 00-ff]
10836 01:26:14.783174 <6>[ 17.621676] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10837 01:26:14.793025 <6>[ 17.621682] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10838 01:26:14.796241 <6>[ 17.621793] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10839 01:26:14.806716 <3>[ 17.630391] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 01:26:14.813287 <6>[ 17.632987] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10841 01:26:14.823583 <3>[ 17.639112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 01:26:14.830343 <6>[ 17.643574] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10843 01:26:14.836714 <3>[ 17.652972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 01:26:14.843525 <6>[ 17.657670] pci 0000:00:00.0: supports D1 D2
10845 01:26:14.850157 <4>[ 17.661365] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10846 01:26:14.860319 <4>[ 17.661379] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10847 01:26:14.866721 <3>[ 17.663362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 01:26:14.876855 <6>[ 17.666267] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10849 01:26:14.886978 <6>[ 17.667020] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10850 01:26:14.892986 <6>[ 17.670386] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10851 01:26:14.903485 <3>[ 17.680928] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 01:26:14.909393 <6>[ 17.688221] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10853 01:26:14.919513 <6>[ 17.692697] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10854 01:26:14.926506 <6>[ 17.692706] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10855 01:26:14.932584 <6>[ 17.692708] remoteproc remoteproc0: remote processor scp is now up
10856 01:26:14.939650 <3>[ 17.695434] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 01:26:14.946107 <6>[ 17.702782] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10858 01:26:14.955951 <6>[ 17.710224] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10859 01:26:14.962915 <3>[ 17.710771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 01:26:14.972688 <6>[ 17.720947] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10861 01:26:14.978518 <3>[ 17.726231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 01:26:14.985146 <6>[ 17.730796] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10863 01:26:14.995077 <6>[ 17.730791] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10864 01:26:15.001660 <6>[ 17.737891] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10865 01:26:15.011705 <3>[ 17.740518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 01:26:15.015445 <6>[ 17.747994] r8152 2-1.3:1.0 eth0: v1.12.13
10867 01:26:15.018319 <6>[ 17.748547] Bluetooth: Core ver 2.22
10868 01:26:15.025014 <6>[ 17.748595] NET: Registered PF_BLUETOOTH protocol family
10869 01:26:15.032104 <6>[ 17.748597] Bluetooth: HCI device and connection manager initialized
10870 01:26:15.035003 <6>[ 17.748608] Bluetooth: HCI socket layer initialized
10871 01:26:15.041872 <6>[ 17.748616] Bluetooth: L2CAP socket layer initialized
10872 01:26:15.048492 <6>[ 17.748625] Bluetooth: SCO socket layer initialized
10873 01:26:15.055136 <3>[ 17.756105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 01:26:15.061224 <6>[ 17.756177] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10875 01:26:15.067953 <6>[ 17.756329] pci 0000:01:00.0: supports D1 D2
10876 01:26:15.074742 <6>[ 17.756333] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10877 01:26:15.081474 <6>[ 17.767295] usbcore: registered new interface driver cdc_ether
10878 01:26:15.087834 <6>[ 17.767370] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10879 01:26:15.097726 <6>[ 17.768394] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10880 01:26:15.104169 <6>[ 17.768502] usbcore: registered new interface driver uvcvideo
10881 01:26:15.113851 <3>[ 17.775135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 01:26:15.120714 <3>[ 17.775143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 01:26:15.127441 <6>[ 17.776717] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10884 01:26:15.137482 <6>[ 17.776766] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10885 01:26:15.144068 <6>[ 17.776770] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10886 01:26:15.153885 <6>[ 17.776781] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10887 01:26:15.160314 <6>[ 17.776794] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10888 01:26:15.166956 <6>[ 17.776807] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10889 01:26:15.173793 <6>[ 17.776820] pci 0000:00:00.0: PCI bridge to [bus 01]
10890 01:26:15.180417 <6>[ 17.776825] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10891 01:26:15.187151 <6>[ 17.777086] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10892 01:26:15.193561 <6>[ 17.777606] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10893 01:26:15.199874 <6>[ 17.777956] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10894 01:26:15.206205 <6>[ 17.799369] usbcore: registered new interface driver r8153_ecm
10895 01:26:15.213203 <5>[ 17.800206] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10896 01:26:15.222875 <3>[ 17.808172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 01:26:15.229318 <6>[ 17.809047] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10898 01:26:15.236436 <5>[ 17.810703] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10899 01:26:15.242752 <4>[ 17.810854] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10900 01:26:15.249488 <6>[ 17.810866] cfg80211: failed to load regulatory.db
10901 01:26:15.255844 <6>[ 17.829062] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10902 01:26:15.262590 <3>[ 17.834780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 01:26:15.269560 <6>[ 17.835314] usbcore: registered new interface driver btusb
10904 01:26:15.279473 <4>[ 17.836561] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10905 01:26:15.286043 <3>[ 17.836574] Bluetooth: hci0: Failed to load firmware file (-2)
10906 01:26:15.292853 <3>[ 17.836578] Bluetooth: hci0: Failed to set up firmware (-2)
10907 01:26:15.302948 <4>[ 17.836582] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10908 01:26:15.309521 <3>[ 18.190634] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 01:26:15.319504 <3>[ 18.191062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 01:26:15.328950 [[0;32m OK [<3>[ 18.207777] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10911 01:26:15.332257 0m] Found device [0;1;39m/dev/ttyS0[0m.
10912 01:26:15.371502 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System B<6>[ 18.252581] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10913 01:26:15.381647 oot/Shutdown[0m<3>[ 18.260315] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 01:26:15.381774 .
10915 01:26:15.392120 <3>[ 18.261196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10916 01:26:15.399129 <6>[ 18.261337] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10917 01:26:15.405898 <3>[ 18.284096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 01:26:15.423121 <6>[ 18.307047] mt7921e 0000:01:00.0: ASIC revision: 79610010
10919 01:26:15.436346 <3>[ 18.317131] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 01:26:15.467602 <3>[ 18.347937] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 01:26:15.485423 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10922 01:26:15.497336 <3>[ 18.377840] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 01:26:15.505161 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10924 01:26:15.534049 [[0;32m OK [0m] Started [0;1;39mDaily Clean<4>[ 18.409658] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10925 01:26:15.544158 up of Temporary <3>[ 18.413483] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 01:26:15.544645 Directories[0m.
10927 01:26:15.563004 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10928 01:26:15.577626 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10929 01:26:15.593851 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10930 01:26:15.609128 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10931 01:26:15.629427 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10932 01:26:15.641941 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10933 01:26:15.668009 [[0;32m OK [0m] Reached targ<4>[ 18.543771] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 01:26:15.671632 et [0;1;39mBasic System[0m.
10935 01:26:15.690457 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10936 01:26:15.746286 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10937 01:26:15.786352 <4>[ 18.663862] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10938 01:26:15.798311 Starting [0;1;39mUser Login Management[0m...
10939 01:26:15.818138 Starting [0;1;39mNetwork Name Resolution[0m...
10940 01:26:15.837551 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10941 01:26:15.854722 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10942 01:26:15.876079 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10943 01:26:15.908105 <4>[ 18.784928] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10944 01:26:15.914975 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10945 01:26:15.931115 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10946 01:26:15.949426 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10947 01:26:16.014902 Starting [0;1;39mPermit User Sessions[0m...
10948 01:26:16.027893 <4>[ 18.904103] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10949 01:26:16.042657 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10950 01:26:16.062423 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10951 01:26:16.082851 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10952 01:26:16.098498 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10953 01:26:16.113996 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10954 01:26:16.133277 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10955 01:26:16.146901 <4>[ 19.023864] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10956 01:26:16.202472 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10957 01:26:16.240510 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10958 01:26:16.267612 <4>[ 19.144760] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10959 01:26:16.289349
10960 01:26:16.289914
10961 01:26:16.292419 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10962 01:26:16.292981
10963 01:26:16.295827 debian-bullseye-arm64 login: root (automatic login)
10964 01:26:16.296302
10965 01:26:16.296672
10966 01:26:16.312092 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023 aarch64
10967 01:26:16.312648
10968 01:26:16.318678 The programs included with the Debian GNU/Linux system are free software;
10969 01:26:16.325354 the exact distribution terms for each program are described in the
10970 01:26:16.328871 individual files in /usr/share/doc/*/copyright.
10971 01:26:16.329435
10972 01:26:16.335311 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10973 01:26:16.338894 permitted by applicable law.
10974 01:26:16.340229 Matched prompt #10: / #
10976 01:26:16.341408 Setting prompt string to ['/ #']
10977 01:26:16.341883 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10979 01:26:16.342964 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10980 01:26:16.343519 start: 2.2.6 expect-shell-connection (timeout 00:02:57) [common]
10981 01:26:16.344011 Setting prompt string to ['/ #']
10982 01:26:16.344364 Forcing a shell prompt, looking for ['/ #']
10984 01:26:16.395233 / #
10985 01:26:16.395945 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10986 01:26:16.396517 Waiting using forced prompt support (timeout 00:02:30)
10987 01:26:16.397047 <4>[ 19.263486] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10988 01:26:16.402199
10989 01:26:16.403153 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10990 01:26:16.403749 start: 2.2.7 export-device-env (timeout 00:02:57) [common]
10991 01:26:16.404271 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10992 01:26:16.404749 end: 2.2 depthcharge-retry (duration 00:02:03) [common]
10993 01:26:16.405229 end: 2 depthcharge-action (duration 00:02:03) [common]
10994 01:26:16.405719 start: 3 lava-test-retry (timeout 00:07:36) [common]
10995 01:26:16.406198 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
10996 01:26:16.406618 Using namespace: common
10998 01:26:16.507856 / # #
10999 01:26:16.508511 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11000 01:26:16.509183 #<4>[ 19.383513] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11001 01:26:16.514420
11002 01:26:16.556032 / # <6>[ 19.407367] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11003 01:26:16.556957 Using /lava-11368524
11005 01:26:16.658342 <6>[ 19.415151] r8152 2-1.3:1.0 enx0export SHELL=/bin/sh
11006 01:26:16.659186 024323078ff: carrier on
11007 01:26:16.659789 export SHELL=/bin/sh<4>[ 19.503119] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11008 01:26:16.664931
11010 01:26:16.766682 / # . /lava-11368524/environment
11011 01:26:16.767627 . /lava-11368524/environment<3>[ 19.620874] mt7921e 0000:01:00.0: hardware init failed
11012 01:26:16.773568
11014 01:26:16.875571 / # /lava-11368524/bin/lava-test-runner /lava-11368524/0
11015 01:26:16.876184 Test shell timeout: 10s (minimum of the action and connection timeout)
11016 01:26:16.881834 /lava-11368524/bin/lava-test-runner /lava-11368524/0
11017 01:26:16.907071 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11018 01:26:16.913478 + cd /lava-11368524/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11019 01:26:16.914033 + cat uuid
11020 01:26:16.916461 + UUID=11368524_1.5.2.3.1
11021 01:26:16.916938 + set +x
11022 01:26:16.922985 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11368524_1.5.2.3.1>
11023 01:26:16.923804 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11368524_1.5.2.3.1
11024 01:26:16.924223 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11368524_1.5.2.3.1)
11025 01:26:16.924673 Skipping test definition patterns.
11026 01:26:16.926561 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11027 01:26:16.933167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11028 01:26:16.933986 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11030 01:26:16.943187 device: /dev/vide<4>[ 19.822351] use of bytesused == 0 is deprecated and will be removed in the future,
11031 01:26:16.943914 o2
11032 01:26:16.946561 <4>[ 19.830379] use the actual size instead.
11033 01:26:16.953426 <4>[ 19.837136] ------------[ cut here ]------------
11034 01:26:16.959901 <4>[ 19.842032] get_vaddr_frames() cannot follow VM_IO mapping
11035 01:26:16.969621 <4>[ 19.842183] WARNING: CPU: 0 PID: 311 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11036 01:26:17.019471 <4>[ 19.860281] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 btusb mac80211 libarc4 btintel mtk_vcodec_enc btmtk r8153_ecm btrtl cfg80211 mtk_vcodec_common mtk_vpu v4l2_mem2mem uvcvideo btbcm videobuf2_dma_contig videobuf2_vmalloc cdc_ether videobuf2_memops bluetooth cros_ec_rpmsg videobuf2_v4l2 usbnet videobuf2_common ecdh_generic crct10dif_ce ecc videodev cros_ec_chardev rfkill mc elants_i2c cros_ec_typec sbs_battery elan_i2c r8152 hid_google_hammer mtk_scp hid_vivaldi_common mtk_rpmsg pcie_mediatek_gen3 mtk_scp_ipi ip_tables x_tables ipv6
11037 01:26:17.028969 <4>[ 19.909667] CPU: 0 PID: 311 Comm: v4l2-compliance Not tainted 6.1.46-cip4 #1
11038 01:26:17.032743 <4>[ 19.916964] Hardware name: Google Spherion (rev0 - 3) (DT)
11039 01:26:17.042562 <4>[ 19.922699] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11040 01:26:17.046001 <4>[ 19.929910] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11041 01:26:17.052394 <4>[ 19.936001] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11042 01:26:17.055797 <4>[ 19.942093] sp : ffff8000091c3850
11043 01:26:17.065824 <4>[ 19.945656] x29: ffff8000091c3850 x28: ffffb97d695ed000 x27: ffffb97d695e9238
11044 01:26:17.072171 <4>[ 19.953043] x26: 0000000000000000 x25: ffffb97dd7a2c0e0 x24: ffff406b4ea31298
11045 01:26:17.078745 <4>[ 19.960430] x23: ffff406b4bf61800 x22: ffff406b40d48410 x21: 0000000000000000
11046 01:26:17.085383 <4>[ 19.967818] x20: 00000000fffffff2 x19: ffff406b4bde7f00 x18: fffffffffffe9778
11047 01:26:17.094695 <4>[ 19.975204] x17: 0000000000000000 x16: ffffb97dd588bb90 x15: 0000000000000038
11048 01:26:17.101539 <4>[ 19.982591] x14: 000000000000033c x13: 0000000000000000 x12: 0000000000000000
11049 01:26:17.108059 <4>[ 19.989977] x11: 0000000000000000 x10: 0000000000000a60 x9 : ffff8000091c3700
11050 01:26:17.114881 <4>[ 19.997364] x8 : ffff406b4aad9980 x7 : ffff406c7ef1ce40 x6 : 0000000000000339
11051 01:26:17.121257 <4>[ 20.004750] x5 : 00000000410fd050 x4 : 0000000000c0000e x3 : 0000000000200000
11052 01:26:17.131134 <4>[ 20.012137] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff406b4aad8ec0
11053 01:26:17.131275 <4>[ 20.019523] Call trace:
11054 01:26:17.137961 <4>[ 20.022220] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11055 01:26:17.144950 <4>[ 20.027964] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11056 01:26:17.151095 <4>[ 20.033965] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11057 01:26:17.157882 <4>[ 20.040317] __prepare_userptr+0x280/0x410 [videobuf2_common]
11058 01:26:17.161447 <4>[ 20.046322] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11059 01:26:17.167523 <4>[ 20.051978] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11060 01:26:17.174329 <4>[ 20.058155] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11061 01:26:17.181268 <4>[ 20.063656] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11062 01:26:17.188309 <4>[ 20.069431] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11063 01:26:17.191285 <4>[ 20.075696] v4l_prepare_buf+0x48/0x60 [videodev]
11064 01:26:17.197892 <4>[ 20.080717] __video_do_ioctl+0x184/0x3d0 [videodev]
11065 01:26:17.201009 <4>[ 20.085962] video_usercopy+0x358/0x680 [videodev]
11066 01:26:17.207899 <4>[ 20.091032] video_ioctl2+0x18/0x30 [videodev]
11067 01:26:17.211393 <4>[ 20.095755] v4l2_ioctl+0x40/0x60 [videodev]
11068 01:26:17.214994 <4>[ 20.100304] __arm64_sys_ioctl+0xa8/0xf0
11069 01:26:17.221039 <4>[ 20.104486] invoke_syscall+0x48/0x114
11070 01:26:17.224312 <4>[ 20.108492] el0_svc_common.constprop.0+0x44/0xec
11071 01:26:17.227968 <4>[ 20.113448] do_el0_svc+0x2c/0xd0
11072 01:26:17.231257 <4>[ 20.117015] el0_svc+0x2c/0x84
11073 01:26:17.234208 <4>[ 20.120323] el0t_64_sync_handler+0xb8/0xc0
11074 01:26:17.241277 <4>[ 20.124757] el0t_64_sync+0x18c/0x190
11075 01:26:17.244226 <4>[ 20.128671] ---[ end trace 0000000000000000 ]---
11076 01:26:17.258435 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11077 01:26:17.268796 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11078 01:26:17.281057
11079 01:26:17.294581 Compliance test for mtk-vcodec-enc device /dev/video2:
11080 01:26:17.303284
11081 01:26:17.314361 Driver Info:
11082 01:26:17.329252 Driver name : mtk-vcodec-enc
11083 01:26:17.342386 Card type : MT8192 video encoder
11084 01:26:17.354592 Bus info : platform:17020000.vcodec
11085 01:26:17.363019 Driver version : 6.1.46
11086 01:26:17.374078 Capabilities : 0x84204000
11087 01:26:17.384303 Video Memory-to-Memory Multiplanar
11088 01:26:17.398363 Streaming
11089 01:26:17.409497 Extended Pix Format
11090 01:26:17.421048 Device Capabilities
11091 01:26:17.430932 Device Caps : 0x04204000
11092 01:26:17.444012 Video Memory-to-Memory Multiplanar
11093 01:26:17.454291 Streaming
11094 01:26:17.469001 Extended Pix Format
11095 01:26:17.481178 Detected Stateful Encoder
11096 01:26:17.492114
11097 01:26:17.508480 Required ioctls:
11098 01:26:17.523725 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11099 01:26:17.524293 test VIDIOC_QUERYCAP: OK
11100 01:26:17.525113 Received signal: <TESTSET> START Required-ioctls
11101 01:26:17.525567 Starting test_set Required-ioctls
11102 01:26:17.547727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11103 01:26:17.548602 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11105 01:26:17.551418 test invalid ioctls: OK
11106 01:26:17.577631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11107 01:26:17.578205
11108 01:26:17.578964 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11110 01:26:17.589811 Allow for multiple opens:
11111 01:26:17.596512 <LAVA_SIGNAL_TESTSET STOP>
11112 01:26:17.597510 Received signal: <TESTSET> STOP
11113 01:26:17.598057 Closing test_set Required-ioctls
11114 01:26:17.606857 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11115 01:26:17.607740 Received signal: <TESTSET> START Allow-for-multiple-opens
11116 01:26:17.608317 Starting test_set Allow-for-multiple-opens
11117 01:26:17.610230 test second /dev/video2 open: OK
11118 01:26:17.631488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11119 01:26:17.632350 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11121 01:26:17.634554 test VIDIOC_QUERYCAP: OK
11122 01:26:17.656547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11123 01:26:17.657375 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11125 01:26:17.659728 test VIDIOC_G/S_PRIORITY: OK
11126 01:26:17.691195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11127 01:26:17.692095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11129 01:26:17.694303 test for unlimited opens: OK
11130 01:26:17.726656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11131 01:26:17.727159
11132 01:26:17.727797 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11134 01:26:17.734685 Debug ioctls:
11135 01:26:17.740954 <LAVA_SIGNAL_TESTSET STOP>
11136 01:26:17.741791 Received signal: <TESTSET> STOP
11137 01:26:17.742177 Closing test_set Allow-for-multiple-opens
11138 01:26:17.750194 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11139 01:26:17.751047 Received signal: <TESTSET> START Debug-ioctls
11140 01:26:17.751492 Starting test_set Debug-ioctls
11141 01:26:17.752829 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11142 01:26:17.779454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11143 01:26:17.780307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11145 01:26:17.785234 test VIDIOC_LOG_STATUS: OK (Not Supported)
11146 01:26:17.803009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11147 01:26:17.803615
11148 01:26:17.804255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11150 01:26:17.812956 Input ioctls:
11151 01:26:17.820848 <LAVA_SIGNAL_TESTSET STOP>
11152 01:26:17.821723 Received signal: <TESTSET> STOP
11153 01:26:17.822107 Closing test_set Debug-ioctls
11154 01:26:17.829109 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11155 01:26:17.829830 Received signal: <TESTSET> START Input-ioctls
11156 01:26:17.830211 Starting test_set Input-ioctls
11157 01:26:17.832168 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11158 01:26:17.860924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11159 01:26:17.861777 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11161 01:26:17.864170 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11162 01:26:17.882001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11163 01:26:17.882867 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11165 01:26:17.888209 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11166 01:26:17.910847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11167 01:26:17.911766 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11169 01:26:17.917580 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11170 01:26:17.940987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11171 01:26:17.941761 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11173 01:26:17.944761 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11174 01:26:17.966299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11175 01:26:17.967420 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11177 01:26:17.969482 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11178 01:26:17.995187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11179 01:26:17.996229 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11181 01:26:17.998442 Inputs: 0 Audio Inputs: 0 Tuners: 0
11182 01:26:18.008914
11183 01:26:18.025652 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11184 01:26:18.047244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11185 01:26:18.048140 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11187 01:26:18.053961 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11188 01:26:18.076199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11189 01:26:18.077015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11191 01:26:18.082528 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11192 01:26:18.100555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11193 01:26:18.101409 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11195 01:26:18.103947 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11196 01:26:18.125078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11197 01:26:18.125892 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11199 01:26:18.131559 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11200 01:26:18.151197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11201 01:26:18.152051 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11203 01:26:18.154540
11204 01:26:18.171263 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11205 01:26:18.194128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11206 01:26:18.194962 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11208 01:26:18.200176 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11209 01:26:18.223766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11210 01:26:18.224610 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11212 01:26:18.225882 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11213 01:26:18.245050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11214 01:26:18.245890 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11216 01:26:18.248099 test VIDIOC_G/S_EDID: OK (Not Supported)
11217 01:26:18.270837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11218 01:26:18.271451
11219 01:26:18.272108 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11221 01:26:18.282669 Control ioctls:
11222 01:26:18.290788 <LAVA_SIGNAL_TESTSET STOP>
11223 01:26:18.291634 Received signal: <TESTSET> STOP
11224 01:26:18.292033 Closing test_set Input-ioctls
11225 01:26:18.299740 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11226 01:26:18.300588 Received signal: <TESTSET> START Control-ioctls
11227 01:26:18.301020 Starting test_set Control-ioctls
11228 01:26:18.302811 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11229 01:26:18.326752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11230 01:26:18.327313 test VIDIOC_QUERYCTRL: OK
11231 01:26:18.327996 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11233 01:26:18.352287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11234 01:26:18.353140 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11236 01:26:18.354997 test VIDIOC_G/S_CTRL: OK
11237 01:26:18.382293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11238 01:26:18.383280 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11240 01:26:18.385349 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11241 01:26:18.405480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11242 01:26:18.406336 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11244 01:26:18.415332 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11245 01:26:18.418703 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11246 01:26:18.447042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11247 01:26:18.447950 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11249 01:26:18.450567 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11250 01:26:18.469177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11251 01:26:18.470011 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11253 01:26:18.472929 Standard Controls: 16 Private Controls: 0
11254 01:26:18.479502
11255 01:26:18.490632 Format ioctls:
11256 01:26:18.499226 <LAVA_SIGNAL_TESTSET STOP>
11257 01:26:18.500106 Received signal: <TESTSET> STOP
11258 01:26:18.500500 Closing test_set Control-ioctls
11259 01:26:18.508481 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11260 01:26:18.509330 Received signal: <TESTSET> START Format-ioctls
11261 01:26:18.509732 Starting test_set Format-ioctls
11262 01:26:18.511853 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11263 01:26:18.537516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11264 01:26:18.538356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11266 01:26:18.540567 test VIDIOC_G/S_PARM: OK
11267 01:26:18.559641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11268 01:26:18.560483 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11270 01:26:18.562547 test VIDIOC_G_FBUF: OK (Not Supported)
11271 01:26:18.591023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11272 01:26:18.591330 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11274 01:26:18.594303 test VIDIOC_G_FMT: OK
11275 01:26:18.619341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11276 01:26:18.619635 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11278 01:26:18.622630 test VIDIOC_TRY_FMT: OK
11279 01:26:18.645185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11280 01:26:18.645563 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11282 01:26:18.654930 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11283 01:26:18.655401 test VIDIOC_S_FMT: FAIL
11284 01:26:18.681984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11285 01:26:18.682710 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11287 01:26:18.685099 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11288 01:26:18.706322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11289 01:26:18.707125 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11291 01:26:18.709366 test Cropping: OK
11292 01:26:18.731556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11293 01:26:18.732259 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11295 01:26:18.734934 test Composing: OK (Not Supported)
11296 01:26:18.755564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11297 01:26:18.755922 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11299 01:26:18.758887 test Scaling: OK (Not Supported)
11300 01:26:18.779305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11301 01:26:18.779556
11302 01:26:18.779952 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11304 01:26:18.792690 Codec ioctls:
11305 01:26:18.799271 <LAVA_SIGNAL_TESTSET STOP>
11306 01:26:18.799960 Received signal: <TESTSET> STOP
11307 01:26:18.800224 Closing test_set Format-ioctls
11308 01:26:18.809011 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11309 01:26:18.809857 Received signal: <TESTSET> START Codec-ioctls
11310 01:26:18.810254 Starting test_set Codec-ioctls
11311 01:26:18.812278 test VIDIOC_(TRY_)ENCODER_CMD: OK
11312 01:26:18.836100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11313 01:26:18.837134 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11315 01:26:18.842662 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11316 01:26:18.861919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11317 01:26:18.862814 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11319 01:26:18.868426 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11320 01:26:18.890898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11321 01:26:18.891519
11322 01:26:18.892166 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11324 01:26:18.903766 Buffer ioctls:
11325 01:26:18.910892 <LAVA_SIGNAL_TESTSET STOP>
11326 01:26:18.911778 Received signal: <TESTSET> STOP
11327 01:26:18.912170 Closing test_set Codec-ioctls
11328 01:26:18.921028 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11329 01:26:18.921867 Received signal: <TESTSET> START Buffer-ioctls
11330 01:26:18.922272 Starting test_set Buffer-ioctls
11331 01:26:18.923547 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11332 01:26:18.948356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11333 01:26:18.948925 test VIDIOC_EXPBUF: OK
11334 01:26:18.949734 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11336 01:26:18.970471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11337 01:26:18.971286 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11339 01:26:18.974173 test Requests: OK (Not Supported)
11340 01:26:18.999258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11341 01:26:18.999895
11342 01:26:19.000538 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11344 01:26:19.012519 Test input 0:
11345 01:26:19.023213
11346 01:26:19.036053 Streaming ioctls:
11347 01:26:19.043610 <LAVA_SIGNAL_TESTSET STOP>
11348 01:26:19.044452 Received signal: <TESTSET> STOP
11349 01:26:19.044843 Closing test_set Buffer-ioctls
11350 01:26:19.052823 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11351 01:26:19.053679 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11352 01:26:19.054079 Starting test_set Streaming-ioctls_Test-input-0
11353 01:26:19.056132 test read/write: OK (Not Supported)
11354 01:26:19.079930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11355 01:26:19.080778 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11357 01:26:19.086865 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11358 01:26:19.097621 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11359 01:26:19.106888 test blocking wait: FAIL
11360 01:26:19.132453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11361 01:26:19.133405 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11363 01:26:19.142082 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11364 01:26:19.145353 test MMAP (select): FAIL
11365 01:26:19.173388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11366 01:26:19.174211 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11368 01:26:19.179868 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11369 01:26:19.188058 test MMAP (epoll): FAIL
11370 01:26:19.213000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11371 01:26:19.213832 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11373 01:26:19.219635 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11374 01:26:19.230760 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11375 01:26:19.235667 test USERPTR (select): FAIL
11376 01:26:19.261579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11377 01:26:19.262440 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11379 01:26:19.268294 test DMABUF: Cannot test, specify --expbuf-device
11380 01:26:19.273666
11381 01:26:19.294773 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11382 01:26:19.299340 <LAVA_TEST_RUNNER EXIT>
11383 01:26:19.300305 ok: lava_test_shell seems to have completed
11384 01:26:19.300798 Marking unfinished test run as failed
11386 01:26:19.306050 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11387 01:26:19.306796 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11388 01:26:19.307271 end: 3 lava-test-retry (duration 00:00:03) [common]
11389 01:26:19.307788 start: 4 finalize (timeout 00:07:34) [common]
11390 01:26:19.308306 start: 4.1 power-off (timeout 00:00:30) [common]
11391 01:26:19.309173 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11392 01:26:19.430637 >> Command sent successfully.
11393 01:26:19.434485 Returned 0 in 0 seconds
11394 01:26:19.535417 end: 4.1 power-off (duration 00:00:00) [common]
11396 01:26:19.536867 start: 4.2 read-feedback (timeout 00:07:33) [common]
11397 01:26:19.538085 Listened to connection for namespace 'common' for up to 1s
11398 01:26:20.538809 Finalising connection for namespace 'common'
11399 01:26:20.539545 Disconnecting from shell: Finalise
11400 01:26:20.539969 / #
11401 01:26:20.641014 end: 4.2 read-feedback (duration 00:00:01) [common]
11402 01:26:20.641722 end: 4 finalize (duration 00:00:01) [common]
11403 01:26:20.642409 Cleaning after the job
11404 01:26:20.642959 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/ramdisk
11405 01:26:20.669426 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/kernel
11406 01:26:20.689421 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/dtb
11407 01:26:20.689808 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368524/tftp-deploy-rw4vapas/modules
11408 01:26:20.700524 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11368524
11409 01:26:20.769684 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11368524
11410 01:26:20.769844 Job finished correctly