Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 19
1 01:24:13.154260 lava-dispatcher, installed at version: 2023.06
2 01:24:13.154503 start: 0 validate
3 01:24:13.154645 Start time: 2023-08-28 01:24:13.154637+00:00 (UTC)
4 01:24:13.154788 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:24:13.154947 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 01:24:13.425051 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:24:13.425832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:24:33.455250 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:24:33.456047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:24:33.726222 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:24:33.726940 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:24:38.004152 validate duration: 24.85
14 01:24:38.004407 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:24:38.004504 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:24:38.004592 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:24:38.004717 Not decompressing ramdisk as can be used compressed.
18 01:24:38.004805 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 01:24:38.004871 saving as /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/ramdisk/rootfs.cpio.gz
20 01:24:38.004936 total size: 8181372 (7 MB)
21 01:24:38.270297 progress 0 % (0 MB)
22 01:24:38.272808 progress 5 % (0 MB)
23 01:24:38.274872 progress 10 % (0 MB)
24 01:24:38.277195 progress 15 % (1 MB)
25 01:24:38.279273 progress 20 % (1 MB)
26 01:24:38.281673 progress 25 % (1 MB)
27 01:24:38.283885 progress 30 % (2 MB)
28 01:24:38.286235 progress 35 % (2 MB)
29 01:24:38.288381 progress 40 % (3 MB)
30 01:24:38.290671 progress 45 % (3 MB)
31 01:24:38.292874 progress 50 % (3 MB)
32 01:24:38.295125 progress 55 % (4 MB)
33 01:24:38.297198 progress 60 % (4 MB)
34 01:24:38.299402 progress 65 % (5 MB)
35 01:24:38.301499 progress 70 % (5 MB)
36 01:24:38.303807 progress 75 % (5 MB)
37 01:24:38.305897 progress 80 % (6 MB)
38 01:24:38.308191 progress 85 % (6 MB)
39 01:24:38.310204 progress 90 % (7 MB)
40 01:24:38.312529 progress 95 % (7 MB)
41 01:24:38.314700 progress 100 % (7 MB)
42 01:24:38.314899 7 MB downloaded in 0.31 s (25.17 MB/s)
43 01:24:38.315062 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:24:38.315299 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:24:38.315385 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:24:38.315469 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:24:38.315639 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:24:38.315723 saving as /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/kernel/Image
50 01:24:38.315785 total size: 49220096 (46 MB)
51 01:24:38.315846 No compression specified
52 01:24:38.316952 progress 0 % (0 MB)
53 01:24:38.329701 progress 5 % (2 MB)
54 01:24:38.342558 progress 10 % (4 MB)
55 01:24:38.355489 progress 15 % (7 MB)
56 01:24:38.368629 progress 20 % (9 MB)
57 01:24:38.381590 progress 25 % (11 MB)
58 01:24:38.394726 progress 30 % (14 MB)
59 01:24:38.407841 progress 35 % (16 MB)
60 01:24:38.421004 progress 40 % (18 MB)
61 01:24:38.433783 progress 45 % (21 MB)
62 01:24:38.446785 progress 50 % (23 MB)
63 01:24:38.459793 progress 55 % (25 MB)
64 01:24:38.472763 progress 60 % (28 MB)
65 01:24:38.485750 progress 65 % (30 MB)
66 01:24:38.498561 progress 70 % (32 MB)
67 01:24:38.511570 progress 75 % (35 MB)
68 01:24:38.524508 progress 80 % (37 MB)
69 01:24:38.537391 progress 85 % (39 MB)
70 01:24:38.550240 progress 90 % (42 MB)
71 01:24:38.563030 progress 95 % (44 MB)
72 01:24:38.575988 progress 100 % (46 MB)
73 01:24:38.576157 46 MB downloaded in 0.26 s (180.28 MB/s)
74 01:24:38.576311 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:24:38.576551 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:24:38.576641 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:24:38.576727 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:24:38.576870 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:24:38.576940 saving as /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/dtb/mt8192-asurada-spherion-r0.dtb
81 01:24:38.577002 total size: 47278 (0 MB)
82 01:24:38.577063 No compression specified
83 01:24:38.578151 progress 69 % (0 MB)
84 01:24:38.578433 progress 100 % (0 MB)
85 01:24:38.578592 0 MB downloaded in 0.00 s (28.39 MB/s)
86 01:24:38.578730 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:24:38.578950 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:24:38.579035 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:24:38.579116 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:24:38.579233 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:24:38.579302 saving as /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/modules/modules.tar
93 01:24:38.579363 total size: 8616896 (8 MB)
94 01:24:38.579424 Using unxz to decompress xz
95 01:24:38.583799 progress 0 % (0 MB)
96 01:24:38.605248 progress 5 % (0 MB)
97 01:24:38.629479 progress 10 % (0 MB)
98 01:24:38.659299 progress 15 % (1 MB)
99 01:24:38.687393 progress 20 % (1 MB)
100 01:24:38.711309 progress 25 % (2 MB)
101 01:24:38.735206 progress 30 % (2 MB)
102 01:24:38.762126 progress 35 % (2 MB)
103 01:24:38.786730 progress 40 % (3 MB)
104 01:24:38.813060 progress 45 % (3 MB)
105 01:24:38.839050 progress 50 % (4 MB)
106 01:24:38.865994 progress 55 % (4 MB)
107 01:24:38.892709 progress 60 % (4 MB)
108 01:24:38.918649 progress 65 % (5 MB)
109 01:24:38.944994 progress 70 % (5 MB)
110 01:24:38.971233 progress 75 % (6 MB)
111 01:24:38.996712 progress 80 % (6 MB)
112 01:24:39.023577 progress 85 % (7 MB)
113 01:24:39.049752 progress 90 % (7 MB)
114 01:24:39.075841 progress 95 % (7 MB)
115 01:24:39.103921 progress 100 % (8 MB)
116 01:24:39.110375 8 MB downloaded in 0.53 s (15.48 MB/s)
117 01:24:39.110641 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:24:39.110907 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:24:39.111001 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:24:39.111100 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:24:39.111184 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:24:39.111271 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:24:39.111512 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky
125 01:24:39.111690 makedir: /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin
126 01:24:39.111798 makedir: /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/tests
127 01:24:39.111899 makedir: /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/results
128 01:24:39.112022 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-add-keys
129 01:24:39.112174 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-add-sources
130 01:24:39.112319 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-background-process-start
131 01:24:39.112454 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-background-process-stop
132 01:24:39.112583 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-common-functions
133 01:24:39.112711 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-echo-ipv4
134 01:24:39.112840 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-install-packages
135 01:24:39.112969 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-installed-packages
136 01:24:39.113096 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-os-build
137 01:24:39.113226 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-probe-channel
138 01:24:39.113353 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-probe-ip
139 01:24:39.113479 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-target-ip
140 01:24:39.113606 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-target-mac
141 01:24:39.113732 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-target-storage
142 01:24:39.113862 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-case
143 01:24:39.113989 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-event
144 01:24:39.114115 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-feedback
145 01:24:39.114241 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-raise
146 01:24:39.114370 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-reference
147 01:24:39.114500 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-runner
148 01:24:39.114625 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-set
149 01:24:39.114755 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-test-shell
150 01:24:39.114887 Updating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-install-packages (oe)
151 01:24:39.115041 Updating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/bin/lava-installed-packages (oe)
152 01:24:39.115166 Creating /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/environment
153 01:24:39.115266 LAVA metadata
154 01:24:39.115340 - LAVA_JOB_ID=11368543
155 01:24:39.115406 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:24:39.115507 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:24:39.115573 skipped lava-vland-overlay
158 01:24:39.115689 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:24:39.115767 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:24:39.115833 skipped lava-multinode-overlay
161 01:24:39.115913 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:24:39.115996 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:24:39.116072 Loading test definitions
164 01:24:39.116166 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:24:39.116240 Using /lava-11368543 at stage 0
166 01:24:39.116551 uuid=11368543_1.5.2.3.1 testdef=None
167 01:24:39.116639 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:24:39.116725 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:24:39.117270 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:24:39.117491 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:24:39.118248 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:24:39.118491 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:24:39.119132 runner path: /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/0/tests/0_dmesg test_uuid 11368543_1.5.2.3.1
176 01:24:39.119296 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:24:39.119522 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 01:24:39.119602 Using /lava-11368543 at stage 1
180 01:24:39.119988 uuid=11368543_1.5.2.3.5 testdef=None
181 01:24:39.120083 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 01:24:39.120168 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 01:24:39.120659 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 01:24:39.120881 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 01:24:39.122095 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 01:24:39.122328 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 01:24:39.123012 runner path: /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/1/tests/1_bootrr test_uuid 11368543_1.5.2.3.5
190 01:24:39.123206 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 01:24:39.123420 Creating lava-test-runner.conf files
193 01:24:39.123485 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/0 for stage 0
194 01:24:39.123577 - 0_dmesg
195 01:24:39.123703 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11368543/lava-overlay-giz1vdky/lava-11368543/1 for stage 1
196 01:24:39.123800 - 1_bootrr
197 01:24:39.123897 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 01:24:39.123981 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 01:24:39.132651 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 01:24:39.132764 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 01:24:39.132851 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 01:24:39.132935 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 01:24:39.133077 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 01:24:39.387992 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 01:24:39.388448 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 01:24:39.388567 extracting modules file /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11368543/extract-overlay-ramdisk-ueqlkgqn/ramdisk
207 01:24:39.614470 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 01:24:39.614648 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 01:24:39.614746 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368543/compress-overlay-xfvxrgoc/overlay-1.5.2.4.tar.gz to ramdisk
210 01:24:39.614821 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368543/compress-overlay-xfvxrgoc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11368543/extract-overlay-ramdisk-ueqlkgqn/ramdisk
211 01:24:39.623237 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 01:24:39.623359 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 01:24:39.623449 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 01:24:39.623540 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 01:24:39.623661 Building ramdisk /var/lib/lava/dispatcher/tmp/11368543/extract-overlay-ramdisk-ueqlkgqn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11368543/extract-overlay-ramdisk-ueqlkgqn/ramdisk
216 01:24:40.008310 >> 145131 blocks
217 01:24:42.266502 rename /var/lib/lava/dispatcher/tmp/11368543/extract-overlay-ramdisk-ueqlkgqn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/ramdisk/ramdisk.cpio.gz
218 01:24:42.266939 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 01:24:42.267063 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 01:24:42.267166 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 01:24:42.267274 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/kernel/Image'
222 01:24:54.930377 Returned 0 in 12 seconds
223 01:24:55.031139 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/kernel/image.itb
224 01:24:55.440589 output: FIT description: Kernel Image image with one or more FDT blobs
225 01:24:55.441065 output: Created: Mon Aug 28 02:24:55 2023
226 01:24:55.441185 output: Image 0 (kernel-1)
227 01:24:55.441288 output: Description:
228 01:24:55.441383 output: Created: Mon Aug 28 02:24:55 2023
229 01:24:55.441475 output: Type: Kernel Image
230 01:24:55.441571 output: Compression: lzma compressed
231 01:24:55.441665 output: Data Size: 11038667 Bytes = 10779.95 KiB = 10.53 MiB
232 01:24:55.441765 output: Architecture: AArch64
233 01:24:55.441863 output: OS: Linux
234 01:24:55.441956 output: Load Address: 0x00000000
235 01:24:55.442043 output: Entry Point: 0x00000000
236 01:24:55.442128 output: Hash algo: crc32
237 01:24:55.442216 output: Hash value: 3affb6e1
238 01:24:55.442304 output: Image 1 (fdt-1)
239 01:24:55.442390 output: Description: mt8192-asurada-spherion-r0
240 01:24:55.442477 output: Created: Mon Aug 28 02:24:55 2023
241 01:24:55.442565 output: Type: Flat Device Tree
242 01:24:55.442653 output: Compression: uncompressed
243 01:24:55.442740 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 01:24:55.442828 output: Architecture: AArch64
245 01:24:55.442913 output: Hash algo: crc32
246 01:24:55.443000 output: Hash value: cc4352de
247 01:24:55.443087 output: Image 2 (ramdisk-1)
248 01:24:55.443173 output: Description: unavailable
249 01:24:55.443260 output: Created: Mon Aug 28 02:24:55 2023
250 01:24:55.443349 output: Type: RAMDisk Image
251 01:24:55.443436 output: Compression: Unknown Compression
252 01:24:55.443522 output: Data Size: 21376248 Bytes = 20875.24 KiB = 20.39 MiB
253 01:24:55.443642 output: Architecture: AArch64
254 01:24:55.443795 output: OS: Linux
255 01:24:55.443915 output: Load Address: unavailable
256 01:24:55.444017 output: Entry Point: unavailable
257 01:24:55.444105 output: Hash algo: crc32
258 01:24:55.444192 output: Hash value: 2c13fa86
259 01:24:55.444279 output: Default Configuration: 'conf-1'
260 01:24:55.444369 output: Configuration 0 (conf-1)
261 01:24:55.444456 output: Description: mt8192-asurada-spherion-r0
262 01:24:55.444542 output: Kernel: kernel-1
263 01:24:55.444629 output: Init Ramdisk: ramdisk-1
264 01:24:55.444715 output: FDT: fdt-1
265 01:24:55.444802 output: Loadables: kernel-1
266 01:24:55.444890 output:
267 01:24:55.445162 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 01:24:55.445312 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 01:24:55.445466 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 01:24:55.445607 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 01:24:55.445750 No LXC device requested
272 01:24:55.445888 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 01:24:55.446022 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 01:24:55.446140 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 01:24:55.446249 Checking files for TFTP limit of 4294967296 bytes.
276 01:24:55.446958 end: 1 tftp-deploy (duration 00:00:17) [common]
277 01:24:55.447096 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 01:24:55.447222 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 01:24:55.447393 substitutions:
280 01:24:55.447490 - {DTB}: 11368543/tftp-deploy-5parntst/dtb/mt8192-asurada-spherion-r0.dtb
281 01:24:55.447588 - {INITRD}: 11368543/tftp-deploy-5parntst/ramdisk/ramdisk.cpio.gz
282 01:24:55.447721 - {KERNEL}: 11368543/tftp-deploy-5parntst/kernel/Image
283 01:24:55.447812 - {LAVA_MAC}: None
284 01:24:55.447900 - {PRESEED_CONFIG}: None
285 01:24:55.447988 - {PRESEED_LOCAL}: None
286 01:24:55.448076 - {RAMDISK}: 11368543/tftp-deploy-5parntst/ramdisk/ramdisk.cpio.gz
287 01:24:55.448164 - {ROOT_PART}: None
288 01:24:55.448251 - {ROOT}: None
289 01:24:55.448338 - {SERVER_IP}: 192.168.201.1
290 01:24:55.448426 - {TEE}: None
291 01:24:55.448514 Parsed boot commands:
292 01:24:55.448599 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 01:24:55.448930 Parsed boot commands: tftpboot 192.168.201.1 11368543/tftp-deploy-5parntst/kernel/image.itb 11368543/tftp-deploy-5parntst/kernel/cmdline
294 01:24:55.449065 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 01:24:55.449191 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 01:24:55.449329 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 01:24:55.449462 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 01:24:55.449571 Not connected, no need to disconnect.
299 01:24:55.449687 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 01:24:55.449854 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 01:24:55.449961 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 01:24:55.454922 Setting prompt string to ['lava-test: # ']
303 01:24:55.455445 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 01:24:55.455630 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 01:24:55.455823 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 01:24:55.456147 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 01:24:55.456467 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 01:25:00.598497 >> Command sent successfully.
309 01:25:00.601032 Returned 0 in 5 seconds
310 01:25:00.701516 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 01:25:00.701998 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 01:25:00.702151 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 01:25:00.702279 Setting prompt string to 'Starting depthcharge on Spherion...'
315 01:25:00.702384 Changing prompt to 'Starting depthcharge on Spherion...'
316 01:25:00.702486 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 01:25:00.702880 [Enter `^Ec?' for help]
318 01:25:00.875205
319 01:25:00.875414
320 01:25:00.875521 F0: 102B 0000
321 01:25:00.875680
322 01:25:00.875788 F3: 1001 0000 [0200]
323 01:25:00.875882
324 01:25:00.878357 F3: 1001 0000
325 01:25:00.878475
326 01:25:00.878571 F7: 102D 0000
327 01:25:00.878664
328 01:25:00.878757 F1: 0000 0000
329 01:25:00.878849
330 01:25:00.882317 V0: 0000 0000 [0001]
331 01:25:00.882442
332 01:25:00.882539 00: 0007 8000
333 01:25:00.882639
334 01:25:00.886135 01: 0000 0000
335 01:25:00.886271
336 01:25:00.886369 BP: 0C00 0209 [0000]
337 01:25:00.886462
338 01:25:00.889854 G0: 1182 0000
339 01:25:00.889980
340 01:25:00.890082 EC: 0000 0021 [4000]
341 01:25:00.890177
342 01:25:00.893298 S7: 0000 0000 [0000]
343 01:25:00.893447
344 01:25:00.893562 CC: 0000 0000 [0001]
345 01:25:00.893686
346 01:25:00.896817 T0: 0000 0040 [010F]
347 01:25:00.896935
348 01:25:00.897033 Jump to BL
349 01:25:00.897126
350 01:25:00.922021
351 01:25:00.922218
352 01:25:00.922318
353 01:25:00.929487 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 01:25:00.932894 ARM64: Exception handlers installed.
355 01:25:00.936497 ARM64: Testing exception
356 01:25:00.940421 ARM64: Done test exception
357 01:25:00.947751 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 01:25:00.954850 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 01:25:00.961867 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 01:25:00.972642 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 01:25:00.978956 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 01:25:00.989710 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 01:25:01.000519 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 01:25:01.007135 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 01:25:01.024550 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 01:25:01.028074 WDT: Last reset was cold boot
367 01:25:01.030960 SPI1(PAD0) initialized at 2873684 Hz
368 01:25:01.034618 SPI5(PAD0) initialized at 992727 Hz
369 01:25:01.037586 VBOOT: Loading verstage.
370 01:25:01.044302 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 01:25:01.048268 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 01:25:01.051404 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 01:25:01.055062 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 01:25:01.062159 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 01:25:01.068295 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 01:25:01.079969 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 01:25:01.080143
378 01:25:01.080243
379 01:25:01.090152 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 01:25:01.093491 ARM64: Exception handlers installed.
381 01:25:01.093621 ARM64: Testing exception
382 01:25:01.097053 ARM64: Done test exception
383 01:25:01.100054 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 01:25:01.106877 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 01:25:01.120774 Probing TPM: . done!
386 01:25:01.120964 TPM ready after 0 ms
387 01:25:01.127501 Connected to device vid:did:rid of 1ae0:0028:00
388 01:25:01.134505 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 01:25:01.194405 Initialized TPM device CR50 revision 0
390 01:25:01.205927 tlcl_send_startup: Startup return code is 0
391 01:25:01.206107 TPM: setup succeeded
392 01:25:01.217375 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 01:25:01.225812 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 01:25:01.240419 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 01:25:01.246874 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 01:25:01.250502 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 01:25:01.254012 in-header: 03 07 00 00 08 00 00 00
398 01:25:01.257567 in-data: aa e4 47 04 13 02 00 00
399 01:25:01.261085 Chrome EC: UHEPI supported
400 01:25:01.268319 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 01:25:01.272460 in-header: 03 95 00 00 08 00 00 00
402 01:25:01.272576 in-data: 18 20 20 08 00 00 00 00
403 01:25:01.276237 Phase 1
404 01:25:01.279874 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 01:25:01.283422 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 01:25:01.291049 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 01:25:01.294879 Recovery requested (1009000e)
408 01:25:01.301951 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 01:25:01.307498 tlcl_extend: response is 0
410 01:25:01.316986 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 01:25:01.322514 tlcl_extend: response is 0
412 01:25:01.329592 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 01:25:01.349074 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 01:25:01.356006 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 01:25:01.356131
416 01:25:01.356226
417 01:25:01.366327 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 01:25:01.369152 ARM64: Exception handlers installed.
419 01:25:01.372688 ARM64: Testing exception
420 01:25:01.372802 ARM64: Done test exception
421 01:25:01.395008 pmic_efuse_setting: Set efuses in 11 msecs
422 01:25:01.398418 pmwrap_interface_init: Select PMIF_VLD_RDY
423 01:25:01.404854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 01:25:01.408613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 01:25:01.415805 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 01:25:01.419144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 01:25:01.423009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 01:25:01.426697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 01:25:01.434636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 01:25:01.438316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 01:25:01.441847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 01:25:01.449198 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 01:25:01.452999 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 01:25:01.457132 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 01:25:01.461143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 01:25:01.468968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 01:25:01.472833 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 01:25:01.479844 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 01:25:01.484025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 01:25:01.491266 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 01:25:01.494823 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 01:25:01.502600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 01:25:01.506085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 01:25:01.513462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 01:25:01.517306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 01:25:01.524832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 01:25:01.528664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 01:25:01.536288 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 01:25:01.539520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 01:25:01.543043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 01:25:01.550235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 01:25:01.553833 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 01:25:01.557356 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 01:25:01.565018 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 01:25:01.568966 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 01:25:01.572898 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 01:25:01.580007 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 01:25:01.583343 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 01:25:01.590632 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 01:25:01.594554 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 01:25:01.598000 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 01:25:01.601977 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 01:25:01.609150 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 01:25:01.612817 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 01:25:01.616373 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 01:25:01.620007 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 01:25:01.623828 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 01:25:01.631461 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 01:25:01.635200 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 01:25:01.638474 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 01:25:01.642523 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 01:25:01.646150 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 01:25:01.649538 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 01:25:01.657217 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 01:25:01.668253 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 01:25:01.671887 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 01:25:01.679501 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 01:25:01.686347 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 01:25:01.693866 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 01:25:01.698095 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 01:25:01.701252 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 01:25:01.708982 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1d
483 01:25:01.712420 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 01:25:01.720109 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 01:25:01.723716 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 01:25:01.732940 [RTC]rtc_get_frequency_meter,154: input=15, output=759
487 01:25:01.742065 [RTC]rtc_get_frequency_meter,154: input=23, output=940
488 01:25:01.752066 [RTC]rtc_get_frequency_meter,154: input=19, output=851
489 01:25:01.761388 [RTC]rtc_get_frequency_meter,154: input=17, output=804
490 01:25:01.770631 [RTC]rtc_get_frequency_meter,154: input=16, output=783
491 01:25:01.780454 [RTC]rtc_get_frequency_meter,154: input=16, output=784
492 01:25:01.790312 [RTC]rtc_get_frequency_meter,154: input=17, output=804
493 01:25:01.793932 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 01:25:01.797250 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 01:25:01.801087 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 01:25:01.809426 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 01:25:01.812656 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 01:25:01.816119 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 01:25:01.819914 ADC[4]: Raw value=906203 ID=7
500 01:25:01.820026 ADC[3]: Raw value=213810 ID=1
501 01:25:01.823804 RAM Code: 0x71
502 01:25:01.827695 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 01:25:01.831324 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 01:25:01.842380 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 01:25:01.846402 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 01:25:01.849537 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 01:25:01.853994 in-header: 03 07 00 00 08 00 00 00
508 01:25:01.857394 in-data: aa e4 47 04 13 02 00 00
509 01:25:01.861033 Chrome EC: UHEPI supported
510 01:25:01.868363 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 01:25:01.872679 in-header: 03 95 00 00 08 00 00 00
512 01:25:01.872800 in-data: 18 20 20 08 00 00 00 00
513 01:25:01.875907 MRC: failed to locate region type 0.
514 01:25:01.883509 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 01:25:01.886999 DRAM-K: Running full calibration
516 01:25:01.894547 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 01:25:01.894652 header.status = 0x0
518 01:25:01.897922 header.version = 0x6 (expected: 0x6)
519 01:25:01.901947 header.size = 0xd00 (expected: 0xd00)
520 01:25:01.902036 header.flags = 0x0
521 01:25:01.909177 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 01:25:01.927521 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 01:25:01.935416 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 01:25:01.935519 dram_init: ddr_geometry: 2
525 01:25:01.939481 [EMI] MDL number = 2
526 01:25:01.939572 [EMI] Get MDL freq = 0
527 01:25:01.943030 dram_init: ddr_type: 0
528 01:25:01.946345 is_discrete_lpddr4: 1
529 01:25:01.946431 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 01:25:01.950387
531 01:25:01.950471
532 01:25:01.950538 [Bian_co] ETT version 0.0.0.1
533 01:25:01.954298 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 01:25:01.957617
535 01:25:01.962131 dramc_set_vcore_voltage set vcore to 650000
536 01:25:01.962219 Read voltage for 800, 4
537 01:25:01.962286 Vio18 = 0
538 01:25:01.965952 Vcore = 650000
539 01:25:01.966039 Vdram = 0
540 01:25:01.966106 Vddq = 0
541 01:25:01.966168 Vmddr = 0
542 01:25:01.969860 dram_init: config_dvfs: 1
543 01:25:01.973701 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 01:25:01.980780 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 01:25:01.984455 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 01:25:01.988386 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 01:25:01.991604 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 01:25:01.994890 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 01:25:01.998151 MEM_TYPE=3, freq_sel=18
550 01:25:02.001690 sv_algorithm_assistance_LP4_1600
551 01:25:02.005016 ============ PULL DRAM RESETB DOWN ============
552 01:25:02.008340 ========== PULL DRAM RESETB DOWN end =========
553 01:25:02.012113 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 01:25:02.015941 ===================================
555 01:25:02.019482 LPDDR4 DRAM CONFIGURATION
556 01:25:02.023875 ===================================
557 01:25:02.023999 EX_ROW_EN[0] = 0x0
558 01:25:02.027270 EX_ROW_EN[1] = 0x0
559 01:25:02.027380 LP4Y_EN = 0x0
560 01:25:02.030720 WORK_FSP = 0x0
561 01:25:02.030829 WL = 0x2
562 01:25:02.033999 RL = 0x2
563 01:25:02.034107 BL = 0x2
564 01:25:02.037498 RPST = 0x0
565 01:25:02.037606 RD_PRE = 0x0
566 01:25:02.040649 WR_PRE = 0x1
567 01:25:02.040756 WR_PST = 0x0
568 01:25:02.043924 DBI_WR = 0x0
569 01:25:02.044034 DBI_RD = 0x0
570 01:25:02.047449 OTF = 0x1
571 01:25:02.051164 ===================================
572 01:25:02.054943 ===================================
573 01:25:02.055053 ANA top config
574 01:25:02.059086 ===================================
575 01:25:02.061728 DLL_ASYNC_EN = 0
576 01:25:02.061836 ALL_SLAVE_EN = 1
577 01:25:02.065469 NEW_RANK_MODE = 1
578 01:25:02.068608 DLL_IDLE_MODE = 1
579 01:25:02.072047 LP45_APHY_COMB_EN = 1
580 01:25:02.072156 TX_ODT_DIS = 1
581 01:25:02.075088 NEW_8X_MODE = 1
582 01:25:02.079541 ===================================
583 01:25:02.083024 ===================================
584 01:25:02.086284 data_rate = 1600
585 01:25:02.089709 CKR = 1
586 01:25:02.089823 DQ_P2S_RATIO = 8
587 01:25:02.092901 ===================================
588 01:25:02.096178 CA_P2S_RATIO = 8
589 01:25:02.099395 DQ_CA_OPEN = 0
590 01:25:02.102827 DQ_SEMI_OPEN = 0
591 01:25:02.106016 CA_SEMI_OPEN = 0
592 01:25:02.109480 CA_FULL_RATE = 0
593 01:25:02.109591 DQ_CKDIV4_EN = 1
594 01:25:02.112687 CA_CKDIV4_EN = 1
595 01:25:02.116501 CA_PREDIV_EN = 0
596 01:25:02.120047 PH8_DLY = 0
597 01:25:02.122632 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 01:25:02.126536 DQ_AAMCK_DIV = 4
599 01:25:02.126646 CA_AAMCK_DIV = 4
600 01:25:02.129659 CA_ADMCK_DIV = 4
601 01:25:02.133143 DQ_TRACK_CA_EN = 0
602 01:25:02.136363 CA_PICK = 800
603 01:25:02.139549 CA_MCKIO = 800
604 01:25:02.143753 MCKIO_SEMI = 0
605 01:25:02.143866 PLL_FREQ = 3068
606 01:25:02.147281 DQ_UI_PI_RATIO = 32
607 01:25:02.151211 CA_UI_PI_RATIO = 0
608 01:25:02.154955 ===================================
609 01:25:02.155068 ===================================
610 01:25:02.158526 memory_type:LPDDR4
611 01:25:02.162237 GP_NUM : 10
612 01:25:02.162361 SRAM_EN : 1
613 01:25:02.166584 MD32_EN : 0
614 01:25:02.169855 ===================================
615 01:25:02.169967 [ANA_INIT] >>>>>>>>>>>>>>
616 01:25:02.173346 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 01:25:02.177642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 01:25:02.180792 ===================================
619 01:25:02.184141 data_rate = 1600,PCW = 0X7600
620 01:25:02.187462 ===================================
621 01:25:02.190708 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 01:25:02.193927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 01:25:02.200965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 01:25:02.204424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 01:25:02.210640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 01:25:02.214513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 01:25:02.214610 [ANA_INIT] flow start
628 01:25:02.217266 [ANA_INIT] PLL >>>>>>>>
629 01:25:02.220501 [ANA_INIT] PLL <<<<<<<<
630 01:25:02.220590 [ANA_INIT] MIDPI >>>>>>>>
631 01:25:02.224056 [ANA_INIT] MIDPI <<<<<<<<
632 01:25:02.227524 [ANA_INIT] DLL >>>>>>>>
633 01:25:02.227672 [ANA_INIT] flow end
634 01:25:02.230741 ============ LP4 DIFF to SE enter ============
635 01:25:02.237484 ============ LP4 DIFF to SE exit ============
636 01:25:02.237599 [ANA_INIT] <<<<<<<<<<<<<
637 01:25:02.240852 [Flow] Enable top DCM control >>>>>
638 01:25:02.244581 [Flow] Enable top DCM control <<<<<
639 01:25:02.247952 Enable DLL master slave shuffle
640 01:25:02.254579 ==============================================================
641 01:25:02.254706 Gating Mode config
642 01:25:02.261097 ==============================================================
643 01:25:02.261217 Config description:
644 01:25:02.271683 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 01:25:02.277991 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 01:25:02.284763 SELPH_MODE 0: By rank 1: By Phase
647 01:25:02.287867 ==============================================================
648 01:25:02.291872 GAT_TRACK_EN = 1
649 01:25:02.294971 RX_GATING_MODE = 2
650 01:25:02.297872 RX_GATING_TRACK_MODE = 2
651 01:25:02.301461 SELPH_MODE = 1
652 01:25:02.304903 PICG_EARLY_EN = 1
653 01:25:02.307891 VALID_LAT_VALUE = 1
654 01:25:02.314698 ==============================================================
655 01:25:02.318673 Enter into Gating configuration >>>>
656 01:25:02.318788 Exit from Gating configuration <<<<
657 01:25:02.322036 Enter into DVFS_PRE_config >>>>>
658 01:25:02.335102 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 01:25:02.338389 Exit from DVFS_PRE_config <<<<<
660 01:25:02.341752 Enter into PICG configuration >>>>
661 01:25:02.341842 Exit from PICG configuration <<<<
662 01:25:02.345203 [RX_INPUT] configuration >>>>>
663 01:25:02.348631 [RX_INPUT] configuration <<<<<
664 01:25:02.355044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 01:25:02.358158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 01:25:02.365140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 01:25:02.371932 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 01:25:02.378655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 01:25:02.385331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 01:25:02.388674 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 01:25:02.392013 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 01:25:02.395035 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 01:25:02.402007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 01:25:02.405328 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 01:25:02.408629 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 01:25:02.411589 ===================================
677 01:25:02.415293 LPDDR4 DRAM CONFIGURATION
678 01:25:02.418685 ===================================
679 01:25:02.418796 EX_ROW_EN[0] = 0x0
680 01:25:02.421792 EX_ROW_EN[1] = 0x0
681 01:25:02.425609 LP4Y_EN = 0x0
682 01:25:02.425731 WORK_FSP = 0x0
683 01:25:02.428799 WL = 0x2
684 01:25:02.428909 RL = 0x2
685 01:25:02.432147 BL = 0x2
686 01:25:02.432255 RPST = 0x0
687 01:25:02.435378 RD_PRE = 0x0
688 01:25:02.435487 WR_PRE = 0x1
689 01:25:02.438891 WR_PST = 0x0
690 01:25:02.438999 DBI_WR = 0x0
691 01:25:02.442128 DBI_RD = 0x0
692 01:25:02.442234 OTF = 0x1
693 01:25:02.445828 ===================================
694 01:25:02.448757 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 01:25:02.455110 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 01:25:02.458585 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 01:25:02.461935 ===================================
698 01:25:02.465140 LPDDR4 DRAM CONFIGURATION
699 01:25:02.469029 ===================================
700 01:25:02.469140 EX_ROW_EN[0] = 0x10
701 01:25:02.472006 EX_ROW_EN[1] = 0x0
702 01:25:02.472114 LP4Y_EN = 0x0
703 01:25:02.475449 WORK_FSP = 0x0
704 01:25:02.475557 WL = 0x2
705 01:25:02.478576 RL = 0x2
706 01:25:02.478683 BL = 0x2
707 01:25:02.482245 RPST = 0x0
708 01:25:02.482355 RD_PRE = 0x0
709 01:25:02.485696 WR_PRE = 0x1
710 01:25:02.488714 WR_PST = 0x0
711 01:25:02.488823 DBI_WR = 0x0
712 01:25:02.492334 DBI_RD = 0x0
713 01:25:02.492445 OTF = 0x1
714 01:25:02.495124 ===================================
715 01:25:02.502148 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 01:25:02.505331 nWR fixed to 40
717 01:25:02.508751 [ModeRegInit_LP4] CH0 RK0
718 01:25:02.508862 [ModeRegInit_LP4] CH0 RK1
719 01:25:02.512503 [ModeRegInit_LP4] CH1 RK0
720 01:25:02.515378 [ModeRegInit_LP4] CH1 RK1
721 01:25:02.515489 match AC timing 13
722 01:25:02.522127 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 01:25:02.525682 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 01:25:02.528966 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 01:25:02.535546 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 01:25:02.538940 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 01:25:02.539057 [EMI DOE] emi_dcm 0
728 01:25:02.545445 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 01:25:02.545563 ==
730 01:25:02.548801 Dram Type= 6, Freq= 0, CH_0, rank 0
731 01:25:02.552688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 01:25:02.552803 ==
733 01:25:02.559234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 01:25:02.562670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 01:25:02.572821 [CA 0] Center 36 (6~67) winsize 62
736 01:25:02.576379 [CA 1] Center 36 (6~67) winsize 62
737 01:25:02.579537 [CA 2] Center 34 (4~65) winsize 62
738 01:25:02.583103 [CA 3] Center 34 (4~64) winsize 61
739 01:25:02.586017 [CA 4] Center 33 (3~63) winsize 61
740 01:25:02.589477 [CA 5] Center 32 (2~62) winsize 61
741 01:25:02.589588
742 01:25:02.592962 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 01:25:02.593071
744 01:25:02.596068 [CATrainingPosCal] consider 1 rank data
745 01:25:02.599884 u2DelayCellTimex100 = 270/100 ps
746 01:25:02.602743 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 01:25:02.606670 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 01:25:02.613325 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 01:25:02.616177 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
750 01:25:02.619618 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
751 01:25:02.622759 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
752 01:25:02.622846
753 01:25:02.626279 CA PerBit enable=1, Macro0, CA PI delay=32
754 01:25:02.626366
755 01:25:02.629501 [CBTSetCACLKResult] CA Dly = 32
756 01:25:02.629586 CS Dly: 4 (0~35)
757 01:25:02.632819 ==
758 01:25:02.632905 Dram Type= 6, Freq= 0, CH_0, rank 1
759 01:25:02.639529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 01:25:02.639645 ==
761 01:25:02.643147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 01:25:02.649576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 01:25:02.659273 [CA 0] Center 36 (6~67) winsize 62
764 01:25:02.662527 [CA 1] Center 36 (6~67) winsize 62
765 01:25:02.665859 [CA 2] Center 34 (3~65) winsize 63
766 01:25:02.669147 [CA 3] Center 34 (4~64) winsize 61
767 01:25:02.672988 [CA 4] Center 32 (2~63) winsize 62
768 01:25:02.676415 [CA 5] Center 32 (2~63) winsize 62
769 01:25:02.676530
770 01:25:02.679528 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 01:25:02.679678
772 01:25:02.682879 [CATrainingPosCal] consider 2 rank data
773 01:25:02.685611 u2DelayCellTimex100 = 270/100 ps
774 01:25:02.689086 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 01:25:02.692375 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 01:25:02.699056 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 01:25:02.702885 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
778 01:25:02.706046 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
779 01:25:02.709379 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
780 01:25:02.709493
781 01:25:02.712761 CA PerBit enable=1, Macro0, CA PI delay=32
782 01:25:02.712874
783 01:25:02.716099 [CBTSetCACLKResult] CA Dly = 32
784 01:25:02.716211 CS Dly: 4 (0~36)
785 01:25:02.716307
786 01:25:02.719343 ----->DramcWriteLeveling(PI) begin...
787 01:25:02.723203 ==
788 01:25:02.723316 Dram Type= 6, Freq= 0, CH_0, rank 0
789 01:25:02.727032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 01:25:02.730392 ==
791 01:25:02.730508 Write leveling (Byte 0): 35 => 35
792 01:25:02.734552 Write leveling (Byte 1): 30 => 30
793 01:25:02.738514 DramcWriteLeveling(PI) end<-----
794 01:25:02.738632
795 01:25:02.738730 ==
796 01:25:02.741760 Dram Type= 6, Freq= 0, CH_0, rank 0
797 01:25:02.744746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 01:25:02.744858 ==
799 01:25:02.748625 [Gating] SW mode calibration
800 01:25:02.755494 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 01:25:02.762279 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 01:25:02.765674 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 01:25:02.769224 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 01:25:02.772251 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
805 01:25:02.778975 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 01:25:02.782736 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:25:02.785810 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:25:02.792567 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:25:02.795891 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:25:02.799343 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 01:25:02.806019 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 01:25:02.809109 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 01:25:02.812903 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 01:25:02.819435 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 01:25:02.822420 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 01:25:02.825833 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 01:25:02.829324 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 01:25:02.835953 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 01:25:02.839032 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 01:25:02.842506 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
821 01:25:02.849655 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 01:25:02.852544 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:25:02.856239 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:25:02.862445 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:25:02.865804 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:25:02.869305 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:25:02.875844 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 01:25:02.879293 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
829 01:25:02.882658 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
830 01:25:02.889306 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 01:25:02.892508 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 01:25:02.896256 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 01:25:02.902672 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 01:25:02.906111 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 01:25:02.909370 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
836 01:25:02.916330 0 10 8 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
837 01:25:02.919325 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
838 01:25:02.922914 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 01:25:02.926095 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 01:25:02.932772 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 01:25:02.935946 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 01:25:02.939422 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 01:25:02.946266 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
844 01:25:02.949321 0 11 8 | B1->B0 | 2e2e 4141 | 1 0 | (0 0) (0 0)
845 01:25:02.952893 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
846 01:25:02.959532 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 01:25:02.962962 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 01:25:02.966183 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 01:25:02.973283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 01:25:02.976308 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 01:25:02.979527 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 01:25:02.986194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 01:25:02.989580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 01:25:02.993211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 01:25:02.996253 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 01:25:03.003347 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 01:25:03.006456 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 01:25:03.009834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 01:25:03.016190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 01:25:03.019487 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 01:25:03.023292 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 01:25:03.029822 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 01:25:03.033604 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 01:25:03.036436 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 01:25:03.043573 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 01:25:03.046551 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 01:25:03.049921 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 01:25:03.056556 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
869 01:25:03.056677 Total UI for P1: 0, mck2ui 16
870 01:25:03.063274 best dqsien dly found for B0: ( 0, 14, 4)
871 01:25:03.066765 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
872 01:25:03.070509 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 01:25:03.073440 Total UI for P1: 0, mck2ui 16
874 01:25:03.076799 best dqsien dly found for B1: ( 0, 14, 12)
875 01:25:03.080282 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
876 01:25:03.083783 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
877 01:25:03.083899
878 01:25:03.086965 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
879 01:25:03.090039 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
880 01:25:03.093654 [Gating] SW calibration Done
881 01:25:03.093766 ==
882 01:25:03.096817 Dram Type= 6, Freq= 0, CH_0, rank 0
883 01:25:03.099955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 01:25:03.103452 ==
885 01:25:03.103563 RX Vref Scan: 0
886 01:25:03.103669
887 01:25:03.106793 RX Vref 0 -> 0, step: 1
888 01:25:03.106903
889 01:25:03.110109 RX Delay -130 -> 252, step: 16
890 01:25:03.113794 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
891 01:25:03.116883 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
892 01:25:03.120253 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
893 01:25:03.123495 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
894 01:25:03.130503 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
895 01:25:03.133317 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
896 01:25:03.136582 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
897 01:25:03.140574 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
898 01:25:03.143770 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
899 01:25:03.150201 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
900 01:25:03.153574 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
901 01:25:03.157125 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
902 01:25:03.160117 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
903 01:25:03.163478 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
904 01:25:03.170310 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
905 01:25:03.173550 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
906 01:25:03.173665 ==
907 01:25:03.176842 Dram Type= 6, Freq= 0, CH_0, rank 0
908 01:25:03.180215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 01:25:03.180328 ==
910 01:25:03.184010 DQS Delay:
911 01:25:03.184122 DQS0 = 0, DQS1 = 0
912 01:25:03.184219 DQM Delay:
913 01:25:03.187240 DQM0 = 88, DQM1 = 81
914 01:25:03.187349 DQ Delay:
915 01:25:03.189899 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
916 01:25:03.193301 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
917 01:25:03.197184 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
918 01:25:03.199984 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
919 01:25:03.200093
920 01:25:03.200188
921 01:25:03.200279 ==
922 01:25:03.203441 Dram Type= 6, Freq= 0, CH_0, rank 0
923 01:25:03.210066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 01:25:03.210188 ==
925 01:25:03.210284
926 01:25:03.210377
927 01:25:03.210467 TX Vref Scan disable
928 01:25:03.213638 == TX Byte 0 ==
929 01:25:03.216943 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
930 01:25:03.220647 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
931 01:25:03.223560 == TX Byte 1 ==
932 01:25:03.226877 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
933 01:25:03.230092 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
934 01:25:03.233861 ==
935 01:25:03.237129 Dram Type= 6, Freq= 0, CH_0, rank 0
936 01:25:03.240311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 01:25:03.240400 ==
938 01:25:03.253233 TX Vref=22, minBit 7, minWin=27, winSum=445
939 01:25:03.256559 TX Vref=24, minBit 12, minWin=27, winSum=451
940 01:25:03.259992 TX Vref=26, minBit 0, minWin=28, winSum=452
941 01:25:03.262965 TX Vref=28, minBit 5, minWin=28, winSum=455
942 01:25:03.266684 TX Vref=30, minBit 5, minWin=28, winSum=459
943 01:25:03.270080 TX Vref=32, minBit 1, minWin=28, winSum=453
944 01:25:03.276506 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
945 01:25:03.276615
946 01:25:03.279959 Final TX Range 1 Vref 30
947 01:25:03.280048
948 01:25:03.280136 ==
949 01:25:03.283012 Dram Type= 6, Freq= 0, CH_0, rank 0
950 01:25:03.286926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 01:25:03.287016 ==
952 01:25:03.287104
953 01:25:03.287187
954 01:25:03.290082 TX Vref Scan disable
955 01:25:03.293448 == TX Byte 0 ==
956 01:25:03.296389 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
957 01:25:03.299989 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
958 01:25:03.303310 == TX Byte 1 ==
959 01:25:03.306874 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
960 01:25:03.310001 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
961 01:25:03.310093
962 01:25:03.313764 [DATLAT]
963 01:25:03.313853 Freq=800, CH0 RK0
964 01:25:03.313941
965 01:25:03.316531 DATLAT Default: 0xa
966 01:25:03.316619 0, 0xFFFF, sum = 0
967 01:25:03.320435 1, 0xFFFF, sum = 0
968 01:25:03.320525 2, 0xFFFF, sum = 0
969 01:25:03.323550 3, 0xFFFF, sum = 0
970 01:25:03.323653 4, 0xFFFF, sum = 0
971 01:25:03.326665 5, 0xFFFF, sum = 0
972 01:25:03.326752 6, 0xFFFF, sum = 0
973 01:25:03.329783 7, 0xFFFF, sum = 0
974 01:25:03.329872 8, 0xFFFF, sum = 0
975 01:25:03.333418 9, 0x0, sum = 1
976 01:25:03.333506 10, 0x0, sum = 2
977 01:25:03.336440 11, 0x0, sum = 3
978 01:25:03.336528 12, 0x0, sum = 4
979 01:25:03.339703 best_step = 10
980 01:25:03.339790
981 01:25:03.339878 ==
982 01:25:03.343456 Dram Type= 6, Freq= 0, CH_0, rank 0
983 01:25:03.346701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 01:25:03.346816 ==
985 01:25:03.349875 RX Vref Scan: 1
986 01:25:03.349987
987 01:25:03.350083 Set Vref Range= 32 -> 127
988 01:25:03.350174
989 01:25:03.353529 RX Vref 32 -> 127, step: 1
990 01:25:03.353639
991 01:25:03.356492 RX Delay -79 -> 252, step: 8
992 01:25:03.356602
993 01:25:03.360165 Set Vref, RX VrefLevel [Byte0]: 32
994 01:25:03.363350 [Byte1]: 32
995 01:25:03.363474
996 01:25:03.366661 Set Vref, RX VrefLevel [Byte0]: 33
997 01:25:03.370146 [Byte1]: 33
998 01:25:03.373354
999 01:25:03.373467 Set Vref, RX VrefLevel [Byte0]: 34
1000 01:25:03.376622 [Byte1]: 34
1001 01:25:03.380700
1002 01:25:03.380815 Set Vref, RX VrefLevel [Byte0]: 35
1003 01:25:03.384700 [Byte1]: 35
1004 01:25:03.388512
1005 01:25:03.388627 Set Vref, RX VrefLevel [Byte0]: 36
1006 01:25:03.391780 [Byte1]: 36
1007 01:25:03.396608
1008 01:25:03.396728 Set Vref, RX VrefLevel [Byte0]: 37
1009 01:25:03.400148 [Byte1]: 37
1010 01:25:03.403857
1011 01:25:03.403972 Set Vref, RX VrefLevel [Byte0]: 38
1012 01:25:03.407043 [Byte1]: 38
1013 01:25:03.411858
1014 01:25:03.411972 Set Vref, RX VrefLevel [Byte0]: 39
1015 01:25:03.415143 [Byte1]: 39
1016 01:25:03.418775
1017 01:25:03.418885 Set Vref, RX VrefLevel [Byte0]: 40
1018 01:25:03.421993 [Byte1]: 40
1019 01:25:03.426163
1020 01:25:03.426275 Set Vref, RX VrefLevel [Byte0]: 41
1021 01:25:03.429306 [Byte1]: 41
1022 01:25:03.433649
1023 01:25:03.433760 Set Vref, RX VrefLevel [Byte0]: 42
1024 01:25:03.437025 [Byte1]: 42
1025 01:25:03.441144
1026 01:25:03.441254 Set Vref, RX VrefLevel [Byte0]: 43
1027 01:25:03.444408 [Byte1]: 43
1028 01:25:03.448763
1029 01:25:03.448872 Set Vref, RX VrefLevel [Byte0]: 44
1030 01:25:03.452371 [Byte1]: 44
1031 01:25:03.456324
1032 01:25:03.456432 Set Vref, RX VrefLevel [Byte0]: 45
1033 01:25:03.459855 [Byte1]: 45
1034 01:25:03.463898
1035 01:25:03.464005 Set Vref, RX VrefLevel [Byte0]: 46
1036 01:25:03.466889 [Byte1]: 46
1037 01:25:03.471221
1038 01:25:03.471329 Set Vref, RX VrefLevel [Byte0]: 47
1039 01:25:03.474821 [Byte1]: 47
1040 01:25:03.479140
1041 01:25:03.479257 Set Vref, RX VrefLevel [Byte0]: 48
1042 01:25:03.482683 [Byte1]: 48
1043 01:25:03.486738
1044 01:25:03.486845 Set Vref, RX VrefLevel [Byte0]: 49
1045 01:25:03.489861 [Byte1]: 49
1046 01:25:03.494328
1047 01:25:03.494436 Set Vref, RX VrefLevel [Byte0]: 50
1048 01:25:03.497739 [Byte1]: 50
1049 01:25:03.501744
1050 01:25:03.501852 Set Vref, RX VrefLevel [Byte0]: 51
1051 01:25:03.505004 [Byte1]: 51
1052 01:25:03.509335
1053 01:25:03.509449 Set Vref, RX VrefLevel [Byte0]: 52
1054 01:25:03.512558 [Byte1]: 52
1055 01:25:03.516989
1056 01:25:03.517096 Set Vref, RX VrefLevel [Byte0]: 53
1057 01:25:03.520097 [Byte1]: 53
1058 01:25:03.524073
1059 01:25:03.524178 Set Vref, RX VrefLevel [Byte0]: 54
1060 01:25:03.527564 [Byte1]: 54
1061 01:25:03.531646
1062 01:25:03.531752 Set Vref, RX VrefLevel [Byte0]: 55
1063 01:25:03.534972 [Byte1]: 55
1064 01:25:03.539365
1065 01:25:03.539466 Set Vref, RX VrefLevel [Byte0]: 56
1066 01:25:03.542956 [Byte1]: 56
1067 01:25:03.547071
1068 01:25:03.547176 Set Vref, RX VrefLevel [Byte0]: 57
1069 01:25:03.550289 [Byte1]: 57
1070 01:25:03.554419
1071 01:25:03.554523 Set Vref, RX VrefLevel [Byte0]: 58
1072 01:25:03.558136 [Byte1]: 58
1073 01:25:03.561885
1074 01:25:03.561989 Set Vref, RX VrefLevel [Byte0]: 59
1075 01:25:03.565309 [Byte1]: 59
1076 01:25:03.569644
1077 01:25:03.569745 Set Vref, RX VrefLevel [Byte0]: 60
1078 01:25:03.572560 [Byte1]: 60
1079 01:25:03.576878
1080 01:25:03.576979 Set Vref, RX VrefLevel [Byte0]: 61
1081 01:25:03.580806 [Byte1]: 61
1082 01:25:03.584646
1083 01:25:03.584746 Set Vref, RX VrefLevel [Byte0]: 62
1084 01:25:03.588090 [Byte1]: 62
1085 01:25:03.592140
1086 01:25:03.592251 Set Vref, RX VrefLevel [Byte0]: 63
1087 01:25:03.595413 [Byte1]: 63
1088 01:25:03.600230
1089 01:25:03.600335 Set Vref, RX VrefLevel [Byte0]: 64
1090 01:25:03.602979 [Byte1]: 64
1091 01:25:03.607562
1092 01:25:03.607706 Set Vref, RX VrefLevel [Byte0]: 65
1093 01:25:03.611201 [Byte1]: 65
1094 01:25:03.614649
1095 01:25:03.614753 Set Vref, RX VrefLevel [Byte0]: 66
1096 01:25:03.618104 [Byte1]: 66
1097 01:25:03.622299
1098 01:25:03.622401 Set Vref, RX VrefLevel [Byte0]: 67
1099 01:25:03.625843 [Byte1]: 67
1100 01:25:03.630379
1101 01:25:03.630479 Set Vref, RX VrefLevel [Byte0]: 68
1102 01:25:03.633177 [Byte1]: 68
1103 01:25:03.637304
1104 01:25:03.637409 Set Vref, RX VrefLevel [Byte0]: 69
1105 01:25:03.640996 [Byte1]: 69
1106 01:25:03.645165
1107 01:25:03.645270 Set Vref, RX VrefLevel [Byte0]: 70
1108 01:25:03.648131 [Byte1]: 70
1109 01:25:03.652916
1110 01:25:03.653018 Set Vref, RX VrefLevel [Byte0]: 71
1111 01:25:03.656135 [Byte1]: 71
1112 01:25:03.660547
1113 01:25:03.660650 Set Vref, RX VrefLevel [Byte0]: 72
1114 01:25:03.663597 [Byte1]: 72
1115 01:25:03.667661
1116 01:25:03.667773 Set Vref, RX VrefLevel [Byte0]: 73
1117 01:25:03.671142 [Byte1]: 73
1118 01:25:03.675541
1119 01:25:03.675682 Set Vref, RX VrefLevel [Byte0]: 74
1120 01:25:03.678462 [Byte1]: 74
1121 01:25:03.682807
1122 01:25:03.682911 Set Vref, RX VrefLevel [Byte0]: 75
1123 01:25:03.686188 [Byte1]: 75
1124 01:25:03.690325
1125 01:25:03.690428 Set Vref, RX VrefLevel [Byte0]: 76
1126 01:25:03.693772 [Byte1]: 76
1127 01:25:03.698217
1128 01:25:03.698320 Set Vref, RX VrefLevel [Byte0]: 77
1129 01:25:03.700991 [Byte1]: 77
1130 01:25:03.705492
1131 01:25:03.705610 Set Vref, RX VrefLevel [Byte0]: 78
1132 01:25:03.711888 [Byte1]: 78
1133 01:25:03.711996
1134 01:25:03.715167 Final RX Vref Byte 0 = 59 to rank0
1135 01:25:03.718373 Final RX Vref Byte 1 = 58 to rank0
1136 01:25:03.721995 Final RX Vref Byte 0 = 59 to rank1
1137 01:25:03.725340 Final RX Vref Byte 1 = 58 to rank1==
1138 01:25:03.728580 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 01:25:03.731784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 01:25:03.731889 ==
1141 01:25:03.731980 DQS Delay:
1142 01:25:03.735590 DQS0 = 0, DQS1 = 0
1143 01:25:03.735732 DQM Delay:
1144 01:25:03.738586 DQM0 = 92, DQM1 = 84
1145 01:25:03.738686 DQ Delay:
1146 01:25:03.741825 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1147 01:25:03.745042 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1148 01:25:03.748989 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1149 01:25:03.751961 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1150 01:25:03.752065
1151 01:25:03.752157
1152 01:25:03.758900 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1153 01:25:03.761964 CH0 RK0: MR19=606, MR18=4B42
1154 01:25:03.768948 CH0_RK0: MR19=0x606, MR18=0x4B42, DQSOSC=391, MR23=63, INC=96, DEC=64
1155 01:25:03.769055
1156 01:25:03.771938 ----->DramcWriteLeveling(PI) begin...
1157 01:25:03.772041 ==
1158 01:25:03.775899 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 01:25:03.779178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 01:25:03.779282 ==
1161 01:25:03.782251 Write leveling (Byte 0): 32 => 32
1162 01:25:03.785369 Write leveling (Byte 1): 31 => 31
1163 01:25:03.789060 DramcWriteLeveling(PI) end<-----
1164 01:25:03.789162
1165 01:25:03.789251 ==
1166 01:25:03.792339 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 01:25:03.795486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 01:25:03.795596 ==
1169 01:25:03.839739 [Gating] SW mode calibration
1170 01:25:03.839902 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 01:25:03.840199 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 01:25:03.840298 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1173 01:25:03.840399 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1174 01:25:03.840683 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1175 01:25:03.840784 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:25:03.840890 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:25:03.841569 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:25:03.852806 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:25:03.853432 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 01:25:03.853536 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 01:25:03.856225 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 01:25:03.859402 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 01:25:03.865721 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 01:25:03.869365 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 01:25:03.872852 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 01:25:03.879295 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 01:25:03.882825 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:25:03.885916 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:25:03.892519 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1190 01:25:03.895912 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1191 01:25:03.899708 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 01:25:03.902664 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 01:25:03.909294 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 01:25:03.912958 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 01:25:03.915870 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 01:25:03.922628 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 01:25:03.925958 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 01:25:03.929427 0 9 8 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
1199 01:25:03.936443 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 01:25:03.939736 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 01:25:03.942830 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 01:25:03.949719 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 01:25:03.952970 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 01:25:03.956280 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 01:25:03.962925 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 01:25:03.966446 0 10 8 | B1->B0 | 2727 2929 | 1 0 | (1 1) (0 0)
1207 01:25:03.970162 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 01:25:03.973775 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 01:25:03.977706 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 01:25:03.985098 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 01:25:03.988304 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 01:25:03.991369 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 01:25:03.995185 0 11 4 | B1->B0 | 2525 2323 | 1 1 | (0 0) (0 0)
1214 01:25:04.001842 0 11 8 | B1->B0 | 3c3c 3838 | 0 1 | (0 0) (0 0)
1215 01:25:04.005921 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 01:25:04.009401 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 01:25:04.015425 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 01:25:04.018452 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 01:25:04.021846 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 01:25:04.028681 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 01:25:04.031880 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 01:25:04.035576 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1223 01:25:04.042461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1224 01:25:04.045370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 01:25:04.048601 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 01:25:04.052482 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 01:25:04.058794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 01:25:04.062379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 01:25:04.066004 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 01:25:04.072529 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 01:25:04.075638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 01:25:04.079297 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 01:25:04.085636 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 01:25:04.089298 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 01:25:04.092147 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 01:25:04.099142 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 01:25:04.102544 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 01:25:04.105585 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1239 01:25:04.112318 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 01:25:04.112458 Total UI for P1: 0, mck2ui 16
1241 01:25:04.118949 best dqsien dly found for B0: ( 0, 14, 10)
1242 01:25:04.119049 Total UI for P1: 0, mck2ui 16
1243 01:25:04.122295 best dqsien dly found for B1: ( 0, 14, 8)
1244 01:25:04.128904 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1245 01:25:04.132102 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1246 01:25:04.132186
1247 01:25:04.135452 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1248 01:25:04.138786 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1249 01:25:04.142365 [Gating] SW calibration Done
1250 01:25:04.142447 ==
1251 01:25:04.145478 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 01:25:04.149169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 01:25:04.149253 ==
1254 01:25:04.149319 RX Vref Scan: 0
1255 01:25:04.152292
1256 01:25:04.152379 RX Vref 0 -> 0, step: 1
1257 01:25:04.152464
1258 01:25:04.155960 RX Delay -130 -> 252, step: 16
1259 01:25:04.158784 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1260 01:25:04.162173 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1261 01:25:04.169564 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1262 01:25:04.172323 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1263 01:25:04.175589 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1264 01:25:04.179328 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1265 01:25:04.182390 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1266 01:25:04.188772 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1267 01:25:04.192323 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1268 01:25:04.195512 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1269 01:25:04.199085 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1270 01:25:04.202231 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1271 01:25:04.209303 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1272 01:25:04.212680 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1273 01:25:04.215438 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1274 01:25:04.218667 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1275 01:25:04.218752 ==
1276 01:25:04.222041 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 01:25:04.228868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 01:25:04.228958 ==
1279 01:25:04.229044 DQS Delay:
1280 01:25:04.232374 DQS0 = 0, DQS1 = 0
1281 01:25:04.232458 DQM Delay:
1282 01:25:04.232543 DQM0 = 92, DQM1 = 80
1283 01:25:04.235810 DQ Delay:
1284 01:25:04.239250 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1285 01:25:04.242116 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1286 01:25:04.245357 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1287 01:25:04.248901 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1288 01:25:04.248984
1289 01:25:04.249068
1290 01:25:04.249146 ==
1291 01:25:04.251975 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 01:25:04.255867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 01:25:04.255951 ==
1294 01:25:04.256035
1295 01:25:04.256113
1296 01:25:04.258835 TX Vref Scan disable
1297 01:25:04.258920 == TX Byte 0 ==
1298 01:25:04.265454 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1299 01:25:04.268907 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1300 01:25:04.268992 == TX Byte 1 ==
1301 01:25:04.275830 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1302 01:25:04.278956 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1303 01:25:04.279040 ==
1304 01:25:04.282372 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 01:25:04.285669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 01:25:04.285753 ==
1307 01:25:04.299827 TX Vref=22, minBit 8, minWin=27, winSum=449
1308 01:25:04.303022 TX Vref=24, minBit 8, minWin=27, winSum=450
1309 01:25:04.306621 TX Vref=26, minBit 1, minWin=28, winSum=455
1310 01:25:04.309692 TX Vref=28, minBit 1, minWin=28, winSum=457
1311 01:25:04.313123 TX Vref=30, minBit 8, minWin=27, winSum=453
1312 01:25:04.316497 TX Vref=32, minBit 10, minWin=27, winSum=451
1313 01:25:04.323614 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 28
1314 01:25:04.323777
1315 01:25:04.326355 Final TX Range 1 Vref 28
1316 01:25:04.326473
1317 01:25:04.326567 ==
1318 01:25:04.329610 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 01:25:04.333079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 01:25:04.333193 ==
1321 01:25:04.333261
1322 01:25:04.336014
1323 01:25:04.336099 TX Vref Scan disable
1324 01:25:04.339315 == TX Byte 0 ==
1325 01:25:04.342855 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1326 01:25:04.346173 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1327 01:25:04.349677 == TX Byte 1 ==
1328 01:25:04.352823 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1329 01:25:04.356390 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1330 01:25:04.359533
1331 01:25:04.359637 [DATLAT]
1332 01:25:04.359702 Freq=800, CH0 RK1
1333 01:25:04.359764
1334 01:25:04.362850 DATLAT Default: 0xa
1335 01:25:04.362931 0, 0xFFFF, sum = 0
1336 01:25:04.366152 1, 0xFFFF, sum = 0
1337 01:25:04.366234 2, 0xFFFF, sum = 0
1338 01:25:04.369483 3, 0xFFFF, sum = 0
1339 01:25:04.369566 4, 0xFFFF, sum = 0
1340 01:25:04.372910 5, 0xFFFF, sum = 0
1341 01:25:04.376623 6, 0xFFFF, sum = 0
1342 01:25:04.376703 7, 0xFFFF, sum = 0
1343 01:25:04.379819 8, 0xFFFF, sum = 0
1344 01:25:04.379900 9, 0x0, sum = 1
1345 01:25:04.379964 10, 0x0, sum = 2
1346 01:25:04.383502 11, 0x0, sum = 3
1347 01:25:04.383583 12, 0x0, sum = 4
1348 01:25:04.386733 best_step = 10
1349 01:25:04.386816
1350 01:25:04.386879 ==
1351 01:25:04.389812 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 01:25:04.392907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 01:25:04.392987 ==
1354 01:25:04.396594 RX Vref Scan: 0
1355 01:25:04.396673
1356 01:25:04.396736 RX Vref 0 -> 0, step: 1
1357 01:25:04.396795
1358 01:25:04.399913 RX Delay -95 -> 252, step: 8
1359 01:25:04.406491 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1360 01:25:04.409680 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1361 01:25:04.413248 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1362 01:25:04.416941 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1363 01:25:04.420049 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1364 01:25:04.423406 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1365 01:25:04.430166 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1366 01:25:04.433495 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1367 01:25:04.437100 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1368 01:25:04.440286 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1369 01:25:04.443803 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1370 01:25:04.449954 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1371 01:25:04.453418 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1372 01:25:04.457071 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1373 01:25:04.460638 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1374 01:25:04.467348 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1375 01:25:04.467507 ==
1376 01:25:04.470798 Dram Type= 6, Freq= 0, CH_0, rank 1
1377 01:25:04.473948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 01:25:04.474106 ==
1379 01:25:04.474192 DQS Delay:
1380 01:25:04.476581 DQS0 = 0, DQS1 = 0
1381 01:25:04.476708 DQM Delay:
1382 01:25:04.480416 DQM0 = 93, DQM1 = 83
1383 01:25:04.480593 DQ Delay:
1384 01:25:04.483414 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1385 01:25:04.487097 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1386 01:25:04.490777 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1387 01:25:04.493959 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1388 01:25:04.494157
1389 01:25:04.494266
1390 01:25:04.500200 [DQSOSCAuto] RK1, (LSB)MR18= 0x4717, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1391 01:25:04.503522 CH0 RK1: MR19=606, MR18=4717
1392 01:25:04.510252 CH0_RK1: MR19=0x606, MR18=0x4717, DQSOSC=392, MR23=63, INC=96, DEC=64
1393 01:25:04.513608 [RxdqsGatingPostProcess] freq 800
1394 01:25:04.520749 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1395 01:25:04.521151 Pre-setting of DQS Precalculation
1396 01:25:04.527243 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1397 01:25:04.527658 ==
1398 01:25:04.530638 Dram Type= 6, Freq= 0, CH_1, rank 0
1399 01:25:04.533831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 01:25:04.534187 ==
1401 01:25:04.540282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 01:25:04.547157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 01:25:04.555159 [CA 0] Center 36 (6~67) winsize 62
1404 01:25:04.558944 [CA 1] Center 36 (6~67) winsize 62
1405 01:25:04.562401 [CA 2] Center 35 (5~65) winsize 61
1406 01:25:04.565320 [CA 3] Center 34 (4~65) winsize 62
1407 01:25:04.568527 [CA 4] Center 35 (5~65) winsize 61
1408 01:25:04.572207 [CA 5] Center 34 (4~65) winsize 62
1409 01:25:04.572687
1410 01:25:04.575129 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1411 01:25:04.575509
1412 01:25:04.578888 [CATrainingPosCal] consider 1 rank data
1413 01:25:04.582084 u2DelayCellTimex100 = 270/100 ps
1414 01:25:04.585203 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 01:25:04.588306 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1416 01:25:04.591936 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1417 01:25:04.599106 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 01:25:04.602164 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1419 01:25:04.605856 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 01:25:04.606340
1421 01:25:04.608436 CA PerBit enable=1, Macro0, CA PI delay=34
1422 01:25:04.608817
1423 01:25:04.612230 [CBTSetCACLKResult] CA Dly = 34
1424 01:25:04.612711 CS Dly: 5 (0~36)
1425 01:25:04.613018 ==
1426 01:25:04.615886 Dram Type= 6, Freq= 0, CH_1, rank 1
1427 01:25:04.622434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 01:25:04.622916 ==
1429 01:25:04.625631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1430 01:25:04.632259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1431 01:25:04.641613 [CA 0] Center 36 (6~67) winsize 62
1432 01:25:04.645084 [CA 1] Center 37 (6~68) winsize 63
1433 01:25:04.648778 [CA 2] Center 35 (4~66) winsize 63
1434 01:25:04.652339 [CA 3] Center 34 (4~65) winsize 62
1435 01:25:04.656090 [CA 4] Center 35 (4~66) winsize 63
1436 01:25:04.659906 [CA 5] Center 34 (4~65) winsize 62
1437 01:25:04.660290
1438 01:25:04.663668 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1439 01:25:04.664139
1440 01:25:04.667387 [CATrainingPosCal] consider 2 rank data
1441 01:25:04.667906 u2DelayCellTimex100 = 270/100 ps
1442 01:25:04.673953 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1443 01:25:04.677350 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1444 01:25:04.680591 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1445 01:25:04.684102 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1446 01:25:04.687291 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1447 01:25:04.690756 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 01:25:04.691213
1449 01:25:04.694231 CA PerBit enable=1, Macro0, CA PI delay=34
1450 01:25:04.694585
1451 01:25:04.697317 [CBTSetCACLKResult] CA Dly = 34
1452 01:25:04.700566 CS Dly: 6 (0~38)
1453 01:25:04.700916
1454 01:25:04.704111 ----->DramcWriteLeveling(PI) begin...
1455 01:25:04.704469 ==
1456 01:25:04.707545 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 01:25:04.711110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 01:25:04.711563 ==
1459 01:25:04.713743 Write leveling (Byte 0): 25 => 25
1460 01:25:04.718055 Write leveling (Byte 1): 25 => 25
1461 01:25:04.720268 DramcWriteLeveling(PI) end<-----
1462 01:25:04.720621
1463 01:25:04.720898 ==
1464 01:25:04.723730 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 01:25:04.727253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 01:25:04.727866 ==
1467 01:25:04.730670 [Gating] SW mode calibration
1468 01:25:04.736798 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1469 01:25:04.744039 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1470 01:25:04.747684 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1471 01:25:04.750930 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1472 01:25:04.757458 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:25:04.760722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:25:04.764017 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:25:04.771003 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 01:25:04.773752 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 01:25:04.777763 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 01:25:04.780553 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 01:25:04.787514 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 01:25:04.790574 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 01:25:04.793768 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 01:25:04.800424 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 01:25:04.803809 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 01:25:04.807148 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 01:25:04.814107 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:25:04.817767 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1487 01:25:04.821375 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1488 01:25:04.827106 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:25:04.830703 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 01:25:04.834254 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 01:25:04.840764 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 01:25:04.843954 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 01:25:04.847823 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 01:25:04.854459 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 01:25:04.857786 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1496 01:25:04.860930 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1497 01:25:04.864252 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 01:25:04.871215 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 01:25:04.874179 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 01:25:04.877786 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 01:25:04.884542 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 01:25:04.887955 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 01:25:04.890939 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 1)
1504 01:25:04.898055 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 01:25:04.901319 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 01:25:04.904934 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 01:25:04.910834 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 01:25:04.914371 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 01:25:04.918005 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 01:25:04.921666 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 01:25:04.927713 0 11 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (0 0)
1512 01:25:04.931555 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1513 01:25:04.934601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 01:25:04.941403 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 01:25:04.944599 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 01:25:04.948285 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 01:25:04.954657 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 01:25:04.958008 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 01:25:04.961480 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1520 01:25:04.968257 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1521 01:25:04.971584 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 01:25:04.974035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 01:25:04.981104 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 01:25:04.984502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 01:25:04.987625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 01:25:04.994778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 01:25:04.997755 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 01:25:05.001601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 01:25:05.007828 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 01:25:05.011490 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 01:25:05.014694 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 01:25:05.018048 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 01:25:05.024911 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 01:25:05.028020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 01:25:05.030994 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1536 01:25:05.034517 Total UI for P1: 0, mck2ui 16
1537 01:25:05.038255 best dqsien dly found for B1: ( 0, 14, 2)
1538 01:25:05.044582 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1539 01:25:05.047783 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 01:25:05.051190 Total UI for P1: 0, mck2ui 16
1541 01:25:05.054608 best dqsien dly found for B0: ( 0, 14, 6)
1542 01:25:05.058265 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1543 01:25:05.061406 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1544 01:25:05.061853
1545 01:25:05.064549 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1546 01:25:05.068252 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1547 01:25:05.071099 [Gating] SW calibration Done
1548 01:25:05.071509 ==
1549 01:25:05.074421 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 01:25:05.077951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 01:25:05.078366 ==
1552 01:25:05.081125 RX Vref Scan: 0
1553 01:25:05.081500
1554 01:25:05.084789 RX Vref 0 -> 0, step: 1
1555 01:25:05.085269
1556 01:25:05.085567 RX Delay -130 -> 252, step: 16
1557 01:25:05.091479 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1558 01:25:05.094805 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1559 01:25:05.098398 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1560 01:25:05.101668 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1561 01:25:05.105017 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1562 01:25:05.111749 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1563 01:25:05.115402 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1564 01:25:05.118988 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1565 01:25:05.121662 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1566 01:25:05.125129 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1567 01:25:05.131653 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1568 01:25:05.135084 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1569 01:25:05.138983 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1570 01:25:05.141879 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1571 01:25:05.145837 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1572 01:25:05.152065 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1573 01:25:05.152576 ==
1574 01:25:05.155506 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 01:25:05.158666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 01:25:05.159081 ==
1577 01:25:05.159406 DQS Delay:
1578 01:25:05.161745 DQS0 = 0, DQS1 = 0
1579 01:25:05.162256 DQM Delay:
1580 01:25:05.165069 DQM0 = 93, DQM1 = 87
1581 01:25:05.165496 DQ Delay:
1582 01:25:05.168480 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1583 01:25:05.172174 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1584 01:25:05.175004 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1585 01:25:05.178568 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1586 01:25:05.178981
1587 01:25:05.179309
1588 01:25:05.179652 ==
1589 01:25:05.181499 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 01:25:05.185115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 01:25:05.185643 ==
1592 01:25:05.185958
1593 01:25:05.188559
1594 01:25:05.188934 TX Vref Scan disable
1595 01:25:05.192306 == TX Byte 0 ==
1596 01:25:05.195077 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1597 01:25:05.198653 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1598 01:25:05.201974 == TX Byte 1 ==
1599 01:25:05.205762 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1600 01:25:05.208407 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1601 01:25:05.208791 ==
1602 01:25:05.212019 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 01:25:05.215616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 01:25:05.216149 ==
1605 01:25:05.229999 TX Vref=22, minBit 0, minWin=26, winSum=430
1606 01:25:05.233711 TX Vref=24, minBit 1, minWin=26, winSum=435
1607 01:25:05.236817 TX Vref=26, minBit 5, minWin=26, winSum=439
1608 01:25:05.240296 TX Vref=28, minBit 0, minWin=27, winSum=447
1609 01:25:05.243776 TX Vref=30, minBit 3, minWin=26, winSum=446
1610 01:25:05.247021 TX Vref=32, minBit 1, minWin=27, winSum=446
1611 01:25:05.253926 [TxChooseVref] Worse bit 0, Min win 27, Win sum 447, Final Vref 28
1612 01:25:05.254466
1613 01:25:05.256774 Final TX Range 1 Vref 28
1614 01:25:05.257190
1615 01:25:05.257521 ==
1616 01:25:05.260455 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 01:25:05.264235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 01:25:05.264745 ==
1619 01:25:05.265076
1620 01:25:05.265382
1621 01:25:05.266575 TX Vref Scan disable
1622 01:25:05.270464 == TX Byte 0 ==
1623 01:25:05.273308 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1624 01:25:05.276983 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1625 01:25:05.280118 == TX Byte 1 ==
1626 01:25:05.283415 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1627 01:25:05.286612 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1628 01:25:05.287027
1629 01:25:05.290415 [DATLAT]
1630 01:25:05.290793 Freq=800, CH1 RK0
1631 01:25:05.291099
1632 01:25:05.293238 DATLAT Default: 0xa
1633 01:25:05.293615 0, 0xFFFF, sum = 0
1634 01:25:05.296802 1, 0xFFFF, sum = 0
1635 01:25:05.297188 2, 0xFFFF, sum = 0
1636 01:25:05.299935 3, 0xFFFF, sum = 0
1637 01:25:05.300322 4, 0xFFFF, sum = 0
1638 01:25:05.303454 5, 0xFFFF, sum = 0
1639 01:25:05.303900 6, 0xFFFF, sum = 0
1640 01:25:05.307112 7, 0xFFFF, sum = 0
1641 01:25:05.307495 8, 0xFFFF, sum = 0
1642 01:25:05.310113 9, 0x0, sum = 1
1643 01:25:05.310597 10, 0x0, sum = 2
1644 01:25:05.313570 11, 0x0, sum = 3
1645 01:25:05.314073 12, 0x0, sum = 4
1646 01:25:05.316788 best_step = 10
1647 01:25:05.317167
1648 01:25:05.317466 ==
1649 01:25:05.319678 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 01:25:05.323145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 01:25:05.323678 ==
1652 01:25:05.326725 RX Vref Scan: 1
1653 01:25:05.327105
1654 01:25:05.327404 Set Vref Range= 32 -> 127
1655 01:25:05.327736
1656 01:25:05.330431 RX Vref 32 -> 127, step: 1
1657 01:25:05.330914
1658 01:25:05.333822 RX Delay -79 -> 252, step: 8
1659 01:25:05.334219
1660 01:25:05.337360 Set Vref, RX VrefLevel [Byte0]: 32
1661 01:25:05.340894 [Byte1]: 32
1662 01:25:05.341377
1663 01:25:05.343418 Set Vref, RX VrefLevel [Byte0]: 33
1664 01:25:05.347029 [Byte1]: 33
1665 01:25:05.347509
1666 01:25:05.350434 Set Vref, RX VrefLevel [Byte0]: 34
1667 01:25:05.354075 [Byte1]: 34
1668 01:25:05.357845
1669 01:25:05.358315 Set Vref, RX VrefLevel [Byte0]: 35
1670 01:25:05.360681 [Byte1]: 35
1671 01:25:05.365245
1672 01:25:05.365738 Set Vref, RX VrefLevel [Byte0]: 36
1673 01:25:05.368984 [Byte1]: 36
1674 01:25:05.373222
1675 01:25:05.373699 Set Vref, RX VrefLevel [Byte0]: 37
1676 01:25:05.375899 [Byte1]: 37
1677 01:25:05.380414
1678 01:25:05.380888 Set Vref, RX VrefLevel [Byte0]: 38
1679 01:25:05.383524 [Byte1]: 38
1680 01:25:05.388115
1681 01:25:05.388606 Set Vref, RX VrefLevel [Byte0]: 39
1682 01:25:05.391221 [Byte1]: 39
1683 01:25:05.395162
1684 01:25:05.395675 Set Vref, RX VrefLevel [Byte0]: 40
1685 01:25:05.398842 [Byte1]: 40
1686 01:25:05.403088
1687 01:25:05.403623 Set Vref, RX VrefLevel [Byte0]: 41
1688 01:25:05.406228 [Byte1]: 41
1689 01:25:05.410736
1690 01:25:05.411259 Set Vref, RX VrefLevel [Byte0]: 42
1691 01:25:05.413729 [Byte1]: 42
1692 01:25:05.418224
1693 01:25:05.418738 Set Vref, RX VrefLevel [Byte0]: 43
1694 01:25:05.421037 [Byte1]: 43
1695 01:25:05.425349
1696 01:25:05.425757 Set Vref, RX VrefLevel [Byte0]: 44
1697 01:25:05.429517 [Byte1]: 44
1698 01:25:05.433139
1699 01:25:05.433551 Set Vref, RX VrefLevel [Byte0]: 45
1700 01:25:05.436244 [Byte1]: 45
1701 01:25:05.440727
1702 01:25:05.441207 Set Vref, RX VrefLevel [Byte0]: 46
1703 01:25:05.444276 [Byte1]: 46
1704 01:25:05.448026
1705 01:25:05.448451 Set Vref, RX VrefLevel [Byte0]: 47
1706 01:25:05.451668 [Byte1]: 47
1707 01:25:05.455914
1708 01:25:05.456321 Set Vref, RX VrefLevel [Byte0]: 48
1709 01:25:05.458742 [Byte1]: 48
1710 01:25:05.463751
1711 01:25:05.464257 Set Vref, RX VrefLevel [Byte0]: 49
1712 01:25:05.467056 [Byte1]: 49
1713 01:25:05.471205
1714 01:25:05.471760 Set Vref, RX VrefLevel [Byte0]: 50
1715 01:25:05.474444 [Byte1]: 50
1716 01:25:05.478170
1717 01:25:05.478582 Set Vref, RX VrefLevel [Byte0]: 51
1718 01:25:05.481671 [Byte1]: 51
1719 01:25:05.486075
1720 01:25:05.486609 Set Vref, RX VrefLevel [Byte0]: 52
1721 01:25:05.488982 [Byte1]: 52
1722 01:25:05.493524
1723 01:25:05.494030 Set Vref, RX VrefLevel [Byte0]: 53
1724 01:25:05.497319 [Byte1]: 53
1725 01:25:05.501223
1726 01:25:05.501730 Set Vref, RX VrefLevel [Byte0]: 54
1727 01:25:05.504131 [Byte1]: 54
1728 01:25:05.508696
1729 01:25:05.509198 Set Vref, RX VrefLevel [Byte0]: 55
1730 01:25:05.511567 [Byte1]: 55
1731 01:25:05.516175
1732 01:25:05.516685 Set Vref, RX VrefLevel [Byte0]: 56
1733 01:25:05.519881 [Byte1]: 56
1734 01:25:05.523849
1735 01:25:05.524357 Set Vref, RX VrefLevel [Byte0]: 57
1736 01:25:05.526876 [Byte1]: 57
1737 01:25:05.531398
1738 01:25:05.531938 Set Vref, RX VrefLevel [Byte0]: 58
1739 01:25:05.534576 [Byte1]: 58
1740 01:25:05.538623
1741 01:25:05.539128 Set Vref, RX VrefLevel [Byte0]: 59
1742 01:25:05.542024 [Byte1]: 59
1743 01:25:05.546262
1744 01:25:05.546768 Set Vref, RX VrefLevel [Byte0]: 60
1745 01:25:05.550067 [Byte1]: 60
1746 01:25:05.553951
1747 01:25:05.554458 Set Vref, RX VrefLevel [Byte0]: 61
1748 01:25:05.557408 [Byte1]: 61
1749 01:25:05.561258
1750 01:25:05.561670 Set Vref, RX VrefLevel [Byte0]: 62
1751 01:25:05.564772 [Byte1]: 62
1752 01:25:05.568995
1753 01:25:05.569421 Set Vref, RX VrefLevel [Byte0]: 63
1754 01:25:05.571899 [Byte1]: 63
1755 01:25:05.576388
1756 01:25:05.576904 Set Vref, RX VrefLevel [Byte0]: 64
1757 01:25:05.580267 [Byte1]: 64
1758 01:25:05.584014
1759 01:25:05.584518 Set Vref, RX VrefLevel [Byte0]: 65
1760 01:25:05.587674 [Byte1]: 65
1761 01:25:05.591463
1762 01:25:05.591924 Set Vref, RX VrefLevel [Byte0]: 66
1763 01:25:05.595101 [Byte1]: 66
1764 01:25:05.599170
1765 01:25:05.599536 Set Vref, RX VrefLevel [Byte0]: 67
1766 01:25:05.602645 [Byte1]: 67
1767 01:25:05.607020
1768 01:25:05.607522 Set Vref, RX VrefLevel [Byte0]: 68
1769 01:25:05.610558 [Byte1]: 68
1770 01:25:05.614438
1771 01:25:05.614943 Set Vref, RX VrefLevel [Byte0]: 69
1772 01:25:05.618035 [Byte1]: 69
1773 01:25:05.621641
1774 01:25:05.622152 Set Vref, RX VrefLevel [Byte0]: 70
1775 01:25:05.625128 [Byte1]: 70
1776 01:25:05.629740
1777 01:25:05.630148 Set Vref, RX VrefLevel [Byte0]: 71
1778 01:25:05.632418 [Byte1]: 71
1779 01:25:05.637177
1780 01:25:05.637682 Set Vref, RX VrefLevel [Byte0]: 72
1781 01:25:05.640202 [Byte1]: 72
1782 01:25:05.644508
1783 01:25:05.644936 Final RX Vref Byte 0 = 58 to rank0
1784 01:25:05.647703 Final RX Vref Byte 1 = 59 to rank0
1785 01:25:05.651165 Final RX Vref Byte 0 = 58 to rank1
1786 01:25:05.655129 Final RX Vref Byte 1 = 59 to rank1==
1787 01:25:05.657733 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 01:25:05.661204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 01:25:05.664703 ==
1790 01:25:05.665212 DQS Delay:
1791 01:25:05.665539 DQS0 = 0, DQS1 = 0
1792 01:25:05.668213 DQM Delay:
1793 01:25:05.668620 DQM0 = 96, DQM1 = 89
1794 01:25:05.671447 DQ Delay:
1795 01:25:05.674291 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1796 01:25:05.678109 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1797 01:25:05.681083 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1798 01:25:05.684353 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1799 01:25:05.684764
1800 01:25:05.685086
1801 01:25:05.691053 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1802 01:25:05.694220 CH1 RK0: MR19=606, MR18=2C48
1803 01:25:05.700897 CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64
1804 01:25:05.701313
1805 01:25:05.705140 ----->DramcWriteLeveling(PI) begin...
1806 01:25:05.705658 ==
1807 01:25:05.707636 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 01:25:05.711625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 01:25:05.712156 ==
1810 01:25:05.714738 Write leveling (Byte 0): 26 => 26
1811 01:25:05.717847 Write leveling (Byte 1): 30 => 30
1812 01:25:05.721377 DramcWriteLeveling(PI) end<-----
1813 01:25:05.721788
1814 01:25:05.722111 ==
1815 01:25:05.724497 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 01:25:05.728089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 01:25:05.728504 ==
1818 01:25:05.731351 [Gating] SW mode calibration
1819 01:25:05.738066 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 01:25:05.744556 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 01:25:05.747826 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1822 01:25:05.750999 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 01:25:05.758044 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 01:25:05.761462 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 01:25:05.764766 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:25:05.771567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:25:05.775041 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:25:05.778652 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 01:25:05.784941 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 01:25:05.788114 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:25:05.791283 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 01:25:05.794754 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:25:05.801457 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:25:05.805268 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:25:05.808344 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:25:05.815162 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:25:05.818473 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1838 01:25:05.821365 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1839 01:25:05.828393 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 01:25:05.831553 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 01:25:05.835086 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 01:25:05.841472 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 01:25:05.845272 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 01:25:05.848526 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 01:25:05.855541 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 01:25:05.858243 0 9 4 | B1->B0 | 2a2a 2323 | 1 1 | (1 1) (1 1)
1847 01:25:05.861527 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1848 01:25:05.865042 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 01:25:05.871835 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 01:25:05.875525 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 01:25:05.878445 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 01:25:05.885673 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 01:25:05.888587 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 01:25:05.891947 0 10 4 | B1->B0 | 2626 3131 | 0 0 | (1 0) (1 0)
1855 01:25:05.898664 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 01:25:05.902267 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 01:25:05.905476 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 01:25:05.912063 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 01:25:05.915664 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 01:25:05.918834 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 01:25:05.925694 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1862 01:25:05.928552 0 11 4 | B1->B0 | 3636 2929 | 0 0 | (0 0) (0 0)
1863 01:25:05.932039 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1864 01:25:05.935128 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 01:25:05.942731 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 01:25:05.945735 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 01:25:05.948672 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 01:25:05.955490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 01:25:05.958657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 01:25:05.961993 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1871 01:25:05.968934 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 01:25:05.972211 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 01:25:05.975680 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 01:25:05.982123 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 01:25:05.985680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 01:25:05.989457 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 01:25:05.995936 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 01:25:05.998881 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 01:25:06.002534 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 01:25:06.005855 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 01:25:06.012267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 01:25:06.015922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 01:25:06.019096 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 01:25:06.026005 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 01:25:06.029286 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 01:25:06.033037 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1887 01:25:06.039364 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1888 01:25:06.039970 Total UI for P1: 0, mck2ui 16
1889 01:25:06.045697 best dqsien dly found for B1: ( 0, 14, 4)
1890 01:25:06.049151 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 01:25:06.052508 Total UI for P1: 0, mck2ui 16
1892 01:25:06.056204 best dqsien dly found for B0: ( 0, 14, 6)
1893 01:25:06.058795 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1894 01:25:06.061989 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 01:25:06.062453
1896 01:25:06.065804 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 01:25:06.069073 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 01:25:06.072692 [Gating] SW calibration Done
1899 01:25:06.073102 ==
1900 01:25:06.075683 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 01:25:06.079171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 01:25:06.079584 ==
1903 01:25:06.082152 RX Vref Scan: 0
1904 01:25:06.082562
1905 01:25:06.085811 RX Vref 0 -> 0, step: 1
1906 01:25:06.086400
1907 01:25:06.086747 RX Delay -130 -> 252, step: 16
1908 01:25:06.092308 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1909 01:25:06.095663 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1910 01:25:06.099160 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1911 01:25:06.102508 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1912 01:25:06.105822 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1913 01:25:06.112292 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1914 01:25:06.115544 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1915 01:25:06.119251 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1916 01:25:06.122446 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1917 01:25:06.125863 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1918 01:25:06.133048 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1919 01:25:06.135766 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1920 01:25:06.139058 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1921 01:25:06.142657 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1922 01:25:06.146032 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1923 01:25:06.152846 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1924 01:25:06.153355 ==
1925 01:25:06.156312 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 01:25:06.159859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 01:25:06.160369 ==
1928 01:25:06.160699 DQS Delay:
1929 01:25:06.162638 DQS0 = 0, DQS1 = 0
1930 01:25:06.163086 DQM Delay:
1931 01:25:06.166536 DQM0 = 92, DQM1 = 90
1932 01:25:06.167044 DQ Delay:
1933 01:25:06.169730 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1934 01:25:06.173034 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1935 01:25:06.176217 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1936 01:25:06.179186 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1937 01:25:06.179625
1938 01:25:06.179956
1939 01:25:06.180256 ==
1940 01:25:06.182556 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 01:25:06.186078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 01:25:06.186590 ==
1943 01:25:06.186920
1944 01:25:06.189295
1945 01:25:06.189707 TX Vref Scan disable
1946 01:25:06.192715 == TX Byte 0 ==
1947 01:25:06.196367 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1948 01:25:06.199413 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1949 01:25:06.202998 == TX Byte 1 ==
1950 01:25:06.206389 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1951 01:25:06.209598 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1952 01:25:06.210012 ==
1953 01:25:06.212782 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 01:25:06.219533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 01:25:06.220097 ==
1956 01:25:06.231373 TX Vref=22, minBit 1, minWin=26, winSum=438
1957 01:25:06.234534 TX Vref=24, minBit 0, minWin=27, winSum=445
1958 01:25:06.238718 TX Vref=26, minBit 2, minWin=27, winSum=448
1959 01:25:06.241534 TX Vref=28, minBit 2, minWin=27, winSum=450
1960 01:25:06.244607 TX Vref=30, minBit 2, minWin=27, winSum=451
1961 01:25:06.247954 TX Vref=32, minBit 0, minWin=27, winSum=449
1962 01:25:06.255065 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1963 01:25:06.255575
1964 01:25:06.257906 Final TX Range 1 Vref 30
1965 01:25:06.258322
1966 01:25:06.258650 ==
1967 01:25:06.261560 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 01:25:06.265061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 01:25:06.265574 ==
1970 01:25:06.265903
1971 01:25:06.266204
1972 01:25:06.268519 TX Vref Scan disable
1973 01:25:06.271795 == TX Byte 0 ==
1974 01:25:06.275298 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 01:25:06.278597 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 01:25:06.281290 == TX Byte 1 ==
1977 01:25:06.284766 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1978 01:25:06.288564 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1979 01:25:06.289076
1980 01:25:06.291710 [DATLAT]
1981 01:25:06.292121 Freq=800, CH1 RK1
1982 01:25:06.292447
1983 01:25:06.294521 DATLAT Default: 0xa
1984 01:25:06.294930 0, 0xFFFF, sum = 0
1985 01:25:06.298205 1, 0xFFFF, sum = 0
1986 01:25:06.298717 2, 0xFFFF, sum = 0
1987 01:25:06.301657 3, 0xFFFF, sum = 0
1988 01:25:06.302170 4, 0xFFFF, sum = 0
1989 01:25:06.304875 5, 0xFFFF, sum = 0
1990 01:25:06.305295 6, 0xFFFF, sum = 0
1991 01:25:06.312245 7, 0xFFFF, sum = 0
1992 01:25:06.312661 8, 0xFFFF, sum = 0
1993 01:25:06.312997 9, 0x0, sum = 1
1994 01:25:06.313306 10, 0x0, sum = 2
1995 01:25:06.314848 11, 0x0, sum = 3
1996 01:25:06.315262 12, 0x0, sum = 4
1997 01:25:06.318237 best_step = 10
1998 01:25:06.318650
1999 01:25:06.318971 ==
2000 01:25:06.321872 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 01:25:06.325046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 01:25:06.325460 ==
2003 01:25:06.328447 RX Vref Scan: 0
2004 01:25:06.328858
2005 01:25:06.329184 RX Vref 0 -> 0, step: 1
2006 01:25:06.329486
2007 01:25:06.332392 RX Delay -63 -> 252, step: 8
2008 01:25:06.338194 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2009 01:25:06.341911 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2010 01:25:06.345506 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2011 01:25:06.348395 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2012 01:25:06.351923 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2013 01:25:06.355396 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2014 01:25:06.358690 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2015 01:25:06.365190 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2016 01:25:06.368421 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2017 01:25:06.372064 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2018 01:25:06.376137 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2019 01:25:06.378936 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2020 01:25:06.385450 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2021 01:25:06.389088 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2022 01:25:06.392066 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2023 01:25:06.395374 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2024 01:25:06.395846 ==
2025 01:25:06.399092 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 01:25:06.405026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 01:25:06.405527 ==
2028 01:25:06.405856 DQS Delay:
2029 01:25:06.406163 DQS0 = 0, DQS1 = 0
2030 01:25:06.408943 DQM Delay:
2031 01:25:06.409446 DQM0 = 97, DQM1 = 90
2032 01:25:06.412101 DQ Delay:
2033 01:25:06.415845 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2034 01:25:06.418937 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2035 01:25:06.419357 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
2036 01:25:06.425781 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2037 01:25:06.426282
2038 01:25:06.426610
2039 01:25:06.432225 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2040 01:25:06.440987 CH1 RK1: MR19=606, MR18=4A13
2041 01:25:06.442106 CH1_RK1: MR19=0x606, MR18=0x4A13, DQSOSC=391, MR23=63, INC=96, DEC=64
2042 01:25:06.445966 [RxdqsGatingPostProcess] freq 800
2043 01:25:06.448564 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 01:25:06.452004 Pre-setting of DQS Precalculation
2045 01:25:06.458929 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 01:25:06.465748 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 01:25:06.472168 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 01:25:06.472684
2049 01:25:06.473013
2050 01:25:06.475692 [Calibration Summary] 1600 Mbps
2051 01:25:06.476212 CH 0, Rank 0
2052 01:25:06.478869 SW Impedance : PASS
2053 01:25:06.482400 DUTY Scan : NO K
2054 01:25:06.482911 ZQ Calibration : PASS
2055 01:25:06.485784 Jitter Meter : NO K
2056 01:25:06.486293 CBT Training : PASS
2057 01:25:06.489078 Write leveling : PASS
2058 01:25:06.492199 RX DQS gating : PASS
2059 01:25:06.492614 RX DQ/DQS(RDDQC) : PASS
2060 01:25:06.495625 TX DQ/DQS : PASS
2061 01:25:06.499027 RX DATLAT : PASS
2062 01:25:06.499538 RX DQ/DQS(Engine): PASS
2063 01:25:06.502802 TX OE : NO K
2064 01:25:06.503313 All Pass.
2065 01:25:06.503701
2066 01:25:06.505581 CH 0, Rank 1
2067 01:25:06.505994 SW Impedance : PASS
2068 01:25:06.508732 DUTY Scan : NO K
2069 01:25:06.512090 ZQ Calibration : PASS
2070 01:25:06.512507 Jitter Meter : NO K
2071 01:25:06.515543 CBT Training : PASS
2072 01:25:06.518663 Write leveling : PASS
2073 01:25:06.519077 RX DQS gating : PASS
2074 01:25:06.522243 RX DQ/DQS(RDDQC) : PASS
2075 01:25:06.522657 TX DQ/DQS : PASS
2076 01:25:06.525557 RX DATLAT : PASS
2077 01:25:06.528932 RX DQ/DQS(Engine): PASS
2078 01:25:06.529347 TX OE : NO K
2079 01:25:06.532622 All Pass.
2080 01:25:06.533034
2081 01:25:06.533356 CH 1, Rank 0
2082 01:25:06.535319 SW Impedance : PASS
2083 01:25:06.535772 DUTY Scan : NO K
2084 01:25:06.538708 ZQ Calibration : PASS
2085 01:25:06.542616 Jitter Meter : NO K
2086 01:25:06.543125 CBT Training : PASS
2087 01:25:06.545818 Write leveling : PASS
2088 01:25:06.548833 RX DQS gating : PASS
2089 01:25:06.549250 RX DQ/DQS(RDDQC) : PASS
2090 01:25:06.552296 TX DQ/DQS : PASS
2091 01:25:06.555830 RX DATLAT : PASS
2092 01:25:06.556341 RX DQ/DQS(Engine): PASS
2093 01:25:06.559345 TX OE : NO K
2094 01:25:06.559985 All Pass.
2095 01:25:06.560335
2096 01:25:06.562719 CH 1, Rank 1
2097 01:25:06.563226 SW Impedance : PASS
2098 01:25:06.565645 DUTY Scan : NO K
2099 01:25:06.568846 ZQ Calibration : PASS
2100 01:25:06.569256 Jitter Meter : NO K
2101 01:25:06.572547 CBT Training : PASS
2102 01:25:06.573066 Write leveling : PASS
2103 01:25:06.575806 RX DQS gating : PASS
2104 01:25:06.579194 RX DQ/DQS(RDDQC) : PASS
2105 01:25:06.579747 TX DQ/DQS : PASS
2106 01:25:06.582291 RX DATLAT : PASS
2107 01:25:06.585797 RX DQ/DQS(Engine): PASS
2108 01:25:06.586207 TX OE : NO K
2109 01:25:06.588985 All Pass.
2110 01:25:06.589492
2111 01:25:06.589817 DramC Write-DBI off
2112 01:25:06.592102 PER_BANK_REFRESH: Hybrid Mode
2113 01:25:06.592515 TX_TRACKING: ON
2114 01:25:06.595520 [GetDramInforAfterCalByMRR] Vendor 6.
2115 01:25:06.602701 [GetDramInforAfterCalByMRR] Revision 606.
2116 01:25:06.606065 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 01:25:06.606578 MR0 0x3b3b
2118 01:25:06.606905 MR8 0x5151
2119 01:25:06.609300 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 01:25:06.609728
2121 01:25:06.612453 MR0 0x3b3b
2122 01:25:06.612967 MR8 0x5151
2123 01:25:06.615965 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 01:25:06.616376
2125 01:25:06.625910 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 01:25:06.629466 [FAST_K] Save calibration result to emmc
2127 01:25:06.633141 [FAST_K] Save calibration result to emmc
2128 01:25:06.635950 dram_init: config_dvfs: 1
2129 01:25:06.639363 dramc_set_vcore_voltage set vcore to 662500
2130 01:25:06.643105 Read voltage for 1200, 2
2131 01:25:06.643642 Vio18 = 0
2132 01:25:06.643978 Vcore = 662500
2133 01:25:06.644284 Vdram = 0
2134 01:25:06.646161 Vddq = 0
2135 01:25:06.646667 Vmddr = 0
2136 01:25:06.652963 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 01:25:06.656236 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 01:25:06.659563 MEM_TYPE=3, freq_sel=15
2139 01:25:06.662738 sv_algorithm_assistance_LP4_1600
2140 01:25:06.666503 ============ PULL DRAM RESETB DOWN ============
2141 01:25:06.669497 ========== PULL DRAM RESETB DOWN end =========
2142 01:25:06.676147 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 01:25:06.679733 ===================================
2144 01:25:06.680247 LPDDR4 DRAM CONFIGURATION
2145 01:25:06.682678 ===================================
2146 01:25:06.686258 EX_ROW_EN[0] = 0x0
2147 01:25:06.686668 EX_ROW_EN[1] = 0x0
2148 01:25:06.689625 LP4Y_EN = 0x0
2149 01:25:06.690134 WORK_FSP = 0x0
2150 01:25:06.692934 WL = 0x4
2151 01:25:06.693461 RL = 0x4
2152 01:25:06.696132 BL = 0x2
2153 01:25:06.699783 RPST = 0x0
2154 01:25:06.700314 RD_PRE = 0x0
2155 01:25:06.703115 WR_PRE = 0x1
2156 01:25:06.703653 WR_PST = 0x0
2157 01:25:06.706683 DBI_WR = 0x0
2158 01:25:06.707192 DBI_RD = 0x0
2159 01:25:06.710071 OTF = 0x1
2160 01:25:06.713396 ===================================
2161 01:25:06.716289 ===================================
2162 01:25:06.716703 ANA top config
2163 01:25:06.719438 ===================================
2164 01:25:06.723015 DLL_ASYNC_EN = 0
2165 01:25:06.726241 ALL_SLAVE_EN = 0
2166 01:25:06.726767 NEW_RANK_MODE = 1
2167 01:25:06.729440 DLL_IDLE_MODE = 1
2168 01:25:06.732796 LP45_APHY_COMB_EN = 1
2169 01:25:06.736569 TX_ODT_DIS = 1
2170 01:25:06.737078 NEW_8X_MODE = 1
2171 01:25:06.740254 ===================================
2172 01:25:06.742813 ===================================
2173 01:25:06.746426 data_rate = 2400
2174 01:25:06.749616 CKR = 1
2175 01:25:06.753118 DQ_P2S_RATIO = 8
2176 01:25:06.756667 ===================================
2177 01:25:06.759876 CA_P2S_RATIO = 8
2178 01:25:06.760707 DQ_CA_OPEN = 0
2179 01:25:06.762988 DQ_SEMI_OPEN = 0
2180 01:25:06.766246 CA_SEMI_OPEN = 0
2181 01:25:06.769386 CA_FULL_RATE = 0
2182 01:25:06.773050 DQ_CKDIV4_EN = 0
2183 01:25:06.776501 CA_CKDIV4_EN = 0
2184 01:25:06.776920 CA_PREDIV_EN = 0
2185 01:25:06.779921 PH8_DLY = 17
2186 01:25:06.783273 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 01:25:06.786634 DQ_AAMCK_DIV = 4
2188 01:25:06.790412 CA_AAMCK_DIV = 4
2189 01:25:06.793431 CA_ADMCK_DIV = 4
2190 01:25:06.793870 DQ_TRACK_CA_EN = 0
2191 01:25:06.796387 CA_PICK = 1200
2192 01:25:06.799801 CA_MCKIO = 1200
2193 01:25:06.803057 MCKIO_SEMI = 0
2194 01:25:06.807036 PLL_FREQ = 2366
2195 01:25:06.810212 DQ_UI_PI_RATIO = 32
2196 01:25:06.813152 CA_UI_PI_RATIO = 0
2197 01:25:06.817069 ===================================
2198 01:25:06.819736 ===================================
2199 01:25:06.820158 memory_type:LPDDR4
2200 01:25:06.823300 GP_NUM : 10
2201 01:25:06.826764 SRAM_EN : 1
2202 01:25:06.827175 MD32_EN : 0
2203 01:25:06.829892 ===================================
2204 01:25:06.833346 [ANA_INIT] >>>>>>>>>>>>>>
2205 01:25:06.836675 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 01:25:06.840052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 01:25:06.843131 ===================================
2208 01:25:06.846827 data_rate = 2400,PCW = 0X5b00
2209 01:25:06.847343 ===================================
2210 01:25:06.850367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 01:25:06.856831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 01:25:06.863780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 01:25:06.866776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 01:25:06.870732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 01:25:06.873767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 01:25:06.876997 [ANA_INIT] flow start
2217 01:25:06.880082 [ANA_INIT] PLL >>>>>>>>
2218 01:25:06.880496 [ANA_INIT] PLL <<<<<<<<
2219 01:25:06.883425 [ANA_INIT] MIDPI >>>>>>>>
2220 01:25:06.887239 [ANA_INIT] MIDPI <<<<<<<<
2221 01:25:06.887684 [ANA_INIT] DLL >>>>>>>>
2222 01:25:06.890329 [ANA_INIT] DLL <<<<<<<<
2223 01:25:06.893220 [ANA_INIT] flow end
2224 01:25:06.896632 ============ LP4 DIFF to SE enter ============
2225 01:25:06.900023 ============ LP4 DIFF to SE exit ============
2226 01:25:06.903556 [ANA_INIT] <<<<<<<<<<<<<
2227 01:25:06.906655 [Flow] Enable top DCM control >>>>>
2228 01:25:06.910228 [Flow] Enable top DCM control <<<<<
2229 01:25:06.913307 Enable DLL master slave shuffle
2230 01:25:06.916884 ==============================================================
2231 01:25:06.919869 Gating Mode config
2232 01:25:06.926664 ==============================================================
2233 01:25:06.927173 Config description:
2234 01:25:06.936708 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 01:25:06.943504 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 01:25:06.946828 SELPH_MODE 0: By rank 1: By Phase
2237 01:25:06.953676 ==============================================================
2238 01:25:06.957566 GAT_TRACK_EN = 1
2239 01:25:06.960220 RX_GATING_MODE = 2
2240 01:25:06.963964 RX_GATING_TRACK_MODE = 2
2241 01:25:06.967096 SELPH_MODE = 1
2242 01:25:06.970077 PICG_EARLY_EN = 1
2243 01:25:06.970585 VALID_LAT_VALUE = 1
2244 01:25:06.976699 ==============================================================
2245 01:25:06.980374 Enter into Gating configuration >>>>
2246 01:25:06.983483 Exit from Gating configuration <<<<
2247 01:25:06.986722 Enter into DVFS_PRE_config >>>>>
2248 01:25:06.997045 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 01:25:07.000125 Exit from DVFS_PRE_config <<<<<
2250 01:25:07.003368 Enter into PICG configuration >>>>
2251 01:25:07.006617 Exit from PICG configuration <<<<
2252 01:25:07.010284 [RX_INPUT] configuration >>>>>
2253 01:25:07.013570 [RX_INPUT] configuration <<<<<
2254 01:25:07.016471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 01:25:07.023688 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 01:25:07.030123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 01:25:07.037046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 01:25:07.043673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 01:25:07.046394 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 01:25:07.053634 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 01:25:07.056953 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 01:25:07.060258 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 01:25:07.063354 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 01:25:07.070001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 01:25:07.073387 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 01:25:07.076837 ===================================
2267 01:25:07.080245 LPDDR4 DRAM CONFIGURATION
2268 01:25:07.083844 ===================================
2269 01:25:07.084357 EX_ROW_EN[0] = 0x0
2270 01:25:07.087296 EX_ROW_EN[1] = 0x0
2271 01:25:07.087858 LP4Y_EN = 0x0
2272 01:25:07.090219 WORK_FSP = 0x0
2273 01:25:07.090729 WL = 0x4
2274 01:25:07.093434 RL = 0x4
2275 01:25:07.093942 BL = 0x2
2276 01:25:07.096577 RPST = 0x0
2277 01:25:07.097063 RD_PRE = 0x0
2278 01:25:07.099969 WR_PRE = 0x1
2279 01:25:07.100383 WR_PST = 0x0
2280 01:25:07.103751 DBI_WR = 0x0
2281 01:25:07.104266 DBI_RD = 0x0
2282 01:25:07.106715 OTF = 0x1
2283 01:25:07.110352 ===================================
2284 01:25:07.113802 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 01:25:07.117246 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 01:25:07.123725 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 01:25:07.126758 ===================================
2288 01:25:07.127176 LPDDR4 DRAM CONFIGURATION
2289 01:25:07.130438 ===================================
2290 01:25:07.133456 EX_ROW_EN[0] = 0x10
2291 01:25:07.136710 EX_ROW_EN[1] = 0x0
2292 01:25:07.137125 LP4Y_EN = 0x0
2293 01:25:07.140103 WORK_FSP = 0x0
2294 01:25:07.140515 WL = 0x4
2295 01:25:07.143844 RL = 0x4
2296 01:25:07.144357 BL = 0x2
2297 01:25:07.147033 RPST = 0x0
2298 01:25:07.147546 RD_PRE = 0x0
2299 01:25:07.149919 WR_PRE = 0x1
2300 01:25:07.150334 WR_PST = 0x0
2301 01:25:07.153760 DBI_WR = 0x0
2302 01:25:07.154271 DBI_RD = 0x0
2303 01:25:07.157182 OTF = 0x1
2304 01:25:07.160347 ===================================
2305 01:25:07.166745 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 01:25:07.167246 ==
2307 01:25:07.170028 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 01:25:07.173477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 01:25:07.173890 ==
2310 01:25:07.176721 [Duty_Offset_Calibration]
2311 01:25:07.177134 B0:2 B1:1 CA:1
2312 01:25:07.177459
2313 01:25:07.179763 [DutyScan_Calibration_Flow] k_type=0
2314 01:25:07.189988
2315 01:25:07.190397 ==CLK 0==
2316 01:25:07.193659 Final CLK duty delay cell = 0
2317 01:25:07.197057 [0] MAX Duty = 5218%(X100), DQS PI = 24
2318 01:25:07.200145 [0] MIN Duty = 4875%(X100), DQS PI = 0
2319 01:25:07.200557 [0] AVG Duty = 5046%(X100)
2320 01:25:07.200883
2321 01:25:07.203359 CH0 CLK Duty spec in!! Max-Min= 343%
2322 01:25:07.210451 [DutyScan_Calibration_Flow] ====Done====
2323 01:25:07.210963
2324 01:25:07.213609 [DutyScan_Calibration_Flow] k_type=1
2325 01:25:07.228612
2326 01:25:07.229113 ==DQS 0 ==
2327 01:25:07.231781 Final DQS duty delay cell = -4
2328 01:25:07.235367 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2329 01:25:07.238405 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2330 01:25:07.241979 [-4] AVG Duty = 4937%(X100)
2331 01:25:07.242488
2332 01:25:07.242808 ==DQS 1 ==
2333 01:25:07.245345 Final DQS duty delay cell = 0
2334 01:25:07.248606 [0] MAX Duty = 5156%(X100), DQS PI = 14
2335 01:25:07.252227 [0] MIN Duty = 5031%(X100), DQS PI = 34
2336 01:25:07.255614 [0] AVG Duty = 5093%(X100)
2337 01:25:07.256132
2338 01:25:07.258762 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2339 01:25:07.259173
2340 01:25:07.261985 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2341 01:25:07.265624 [DutyScan_Calibration_Flow] ====Done====
2342 01:25:07.266134
2343 01:25:07.268843 [DutyScan_Calibration_Flow] k_type=3
2344 01:25:07.285710
2345 01:25:07.286237 ==DQM 0 ==
2346 01:25:07.289155 Final DQM duty delay cell = 0
2347 01:25:07.292352 [0] MAX Duty = 5156%(X100), DQS PI = 30
2348 01:25:07.295528 [0] MIN Duty = 4907%(X100), DQS PI = 58
2349 01:25:07.295967 [0] AVG Duty = 5031%(X100)
2350 01:25:07.299269
2351 01:25:07.299843 ==DQM 1 ==
2352 01:25:07.302373 Final DQM duty delay cell = 0
2353 01:25:07.305681 [0] MAX Duty = 5125%(X100), DQS PI = 60
2354 01:25:07.309018 [0] MIN Duty = 5031%(X100), DQS PI = 50
2355 01:25:07.309432 [0] AVG Duty = 5078%(X100)
2356 01:25:07.313000
2357 01:25:07.315519 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2358 01:25:07.315972
2359 01:25:07.319530 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2360 01:25:07.322034 [DutyScan_Calibration_Flow] ====Done====
2361 01:25:07.322451
2362 01:25:07.325848 [DutyScan_Calibration_Flow] k_type=2
2363 01:25:07.342665
2364 01:25:07.343166 ==DQ 0 ==
2365 01:25:07.345442 Final DQ duty delay cell = 0
2366 01:25:07.349210 [0] MAX Duty = 5031%(X100), DQS PI = 24
2367 01:25:07.352269 [0] MIN Duty = 4906%(X100), DQS PI = 0
2368 01:25:07.352778 [0] AVG Duty = 4968%(X100)
2369 01:25:07.353106
2370 01:25:07.356063 ==DQ 1 ==
2371 01:25:07.359030 Final DQ duty delay cell = 0
2372 01:25:07.362620 [0] MAX Duty = 5093%(X100), DQS PI = 10
2373 01:25:07.365686 [0] MIN Duty = 4938%(X100), DQS PI = 36
2374 01:25:07.366097 [0] AVG Duty = 5015%(X100)
2375 01:25:07.366425
2376 01:25:07.368658 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2377 01:25:07.372068
2378 01:25:07.372761 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2379 01:25:07.379113 [DutyScan_Calibration_Flow] ====Done====
2380 01:25:07.379644 ==
2381 01:25:07.382600 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 01:25:07.385730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 01:25:07.386142 ==
2384 01:25:07.389189 [Duty_Offset_Calibration]
2385 01:25:07.389692 B0:1 B1:0 CA:0
2386 01:25:07.390019
2387 01:25:07.392135 [DutyScan_Calibration_Flow] k_type=0
2388 01:25:07.401388
2389 01:25:07.401916 ==CLK 0==
2390 01:25:07.404264 Final CLK duty delay cell = -4
2391 01:25:07.408168 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2392 01:25:07.411574 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2393 01:25:07.414603 [-4] AVG Duty = 4969%(X100)
2394 01:25:07.415021
2395 01:25:07.418054 CH1 CLK Duty spec in!! Max-Min= 124%
2396 01:25:07.421015 [DutyScan_Calibration_Flow] ====Done====
2397 01:25:07.421431
2398 01:25:07.424764 [DutyScan_Calibration_Flow] k_type=1
2399 01:25:07.441030
2400 01:25:07.441533 ==DQS 0 ==
2401 01:25:07.444497 Final DQS duty delay cell = 0
2402 01:25:07.447832 [0] MAX Duty = 5094%(X100), DQS PI = 26
2403 01:25:07.451152 [0] MIN Duty = 4844%(X100), DQS PI = 0
2404 01:25:07.451700 [0] AVG Duty = 4969%(X100)
2405 01:25:07.454590
2406 01:25:07.455097 ==DQS 1 ==
2407 01:25:07.457970 Final DQS duty delay cell = 0
2408 01:25:07.460947 [0] MAX Duty = 5187%(X100), DQS PI = 18
2409 01:25:07.464533 [0] MIN Duty = 4969%(X100), DQS PI = 10
2410 01:25:07.465048 [0] AVG Duty = 5078%(X100)
2411 01:25:07.467410
2412 01:25:07.471428 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2413 01:25:07.471996
2414 01:25:07.474832 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2415 01:25:07.477851 [DutyScan_Calibration_Flow] ====Done====
2416 01:25:07.478301
2417 01:25:07.480617 [DutyScan_Calibration_Flow] k_type=3
2418 01:25:07.497736
2419 01:25:07.498243 ==DQM 0 ==
2420 01:25:07.500949 Final DQM duty delay cell = 0
2421 01:25:07.504460 [0] MAX Duty = 5156%(X100), DQS PI = 6
2422 01:25:07.507332 [0] MIN Duty = 5031%(X100), DQS PI = 0
2423 01:25:07.507773 [0] AVG Duty = 5093%(X100)
2424 01:25:07.508105
2425 01:25:07.511191 ==DQM 1 ==
2426 01:25:07.514555 Final DQM duty delay cell = 0
2427 01:25:07.517516 [0] MAX Duty = 5031%(X100), DQS PI = 16
2428 01:25:07.521057 [0] MIN Duty = 4907%(X100), DQS PI = 34
2429 01:25:07.521612 [0] AVG Duty = 4969%(X100)
2430 01:25:07.521955
2431 01:25:07.527813 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2432 01:25:07.528338
2433 01:25:07.530619 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2434 01:25:07.535109 [DutyScan_Calibration_Flow] ====Done====
2435 01:25:07.535666
2436 01:25:07.537711 [DutyScan_Calibration_Flow] k_type=2
2437 01:25:07.553319
2438 01:25:07.553872 ==DQ 0 ==
2439 01:25:07.556615 Final DQ duty delay cell = -4
2440 01:25:07.560257 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2441 01:25:07.563043 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2442 01:25:07.566994 [-4] AVG Duty = 5000%(X100)
2443 01:25:07.567502
2444 01:25:07.567874 ==DQ 1 ==
2445 01:25:07.570065 Final DQ duty delay cell = 0
2446 01:25:07.573331 [0] MAX Duty = 5125%(X100), DQS PI = 20
2447 01:25:07.576627 [0] MIN Duty = 4969%(X100), DQS PI = 12
2448 01:25:07.577138 [0] AVG Duty = 5047%(X100)
2449 01:25:07.577468
2450 01:25:07.583670 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2451 01:25:07.584185
2452 01:25:07.586450 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2453 01:25:07.590449 [DutyScan_Calibration_Flow] ====Done====
2454 01:25:07.593337 nWR fixed to 30
2455 01:25:07.593759 [ModeRegInit_LP4] CH0 RK0
2456 01:25:07.597103 [ModeRegInit_LP4] CH0 RK1
2457 01:25:07.599823 [ModeRegInit_LP4] CH1 RK0
2458 01:25:07.600239 [ModeRegInit_LP4] CH1 RK1
2459 01:25:07.603281 match AC timing 7
2460 01:25:07.606870 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 01:25:07.609952 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 01:25:07.616945 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 01:25:07.619705 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 01:25:07.626567 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 01:25:07.627069 ==
2466 01:25:07.629742 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 01:25:07.633441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 01:25:07.633955 ==
2469 01:25:07.639856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 01:25:07.643289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 01:25:07.653686 [CA 0] Center 39 (8~70) winsize 63
2472 01:25:07.657121 [CA 1] Center 39 (8~70) winsize 63
2473 01:25:07.660564 [CA 2] Center 35 (5~66) winsize 62
2474 01:25:07.663518 [CA 3] Center 34 (4~65) winsize 62
2475 01:25:07.666811 [CA 4] Center 33 (3~64) winsize 62
2476 01:25:07.670406 [CA 5] Center 32 (3~62) winsize 60
2477 01:25:07.670921
2478 01:25:07.673965 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2479 01:25:07.674477
2480 01:25:07.676553 [CATrainingPosCal] consider 1 rank data
2481 01:25:07.680007 u2DelayCellTimex100 = 270/100 ps
2482 01:25:07.683693 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2483 01:25:07.686969 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2484 01:25:07.694058 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2485 01:25:07.696846 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2486 01:25:07.700135 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2487 01:25:07.703456 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2488 01:25:07.703895
2489 01:25:07.706981 CA PerBit enable=1, Macro0, CA PI delay=32
2490 01:25:07.707488
2491 01:25:07.710108 [CBTSetCACLKResult] CA Dly = 32
2492 01:25:07.710618 CS Dly: 6 (0~37)
2493 01:25:07.710954 ==
2494 01:25:07.714166 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 01:25:07.720075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 01:25:07.720495 ==
2497 01:25:07.723123 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 01:25:07.730079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2499 01:25:07.739234 [CA 0] Center 38 (8~69) winsize 62
2500 01:25:07.742622 [CA 1] Center 38 (8~69) winsize 62
2501 01:25:07.745607 [CA 2] Center 35 (4~66) winsize 63
2502 01:25:07.749262 [CA 3] Center 34 (4~65) winsize 62
2503 01:25:07.752351 [CA 4] Center 33 (3~64) winsize 62
2504 01:25:07.755959 [CA 5] Center 32 (3~62) winsize 60
2505 01:25:07.756381
2506 01:25:07.759256 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 01:25:07.759702
2508 01:25:07.762684 [CATrainingPosCal] consider 2 rank data
2509 01:25:07.765949 u2DelayCellTimex100 = 270/100 ps
2510 01:25:07.769533 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2511 01:25:07.772290 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2512 01:25:07.779157 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2513 01:25:07.782748 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2514 01:25:07.785781 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2515 01:25:07.789155 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2516 01:25:07.789703
2517 01:25:07.792415 CA PerBit enable=1, Macro0, CA PI delay=32
2518 01:25:07.792834
2519 01:25:07.795757 [CBTSetCACLKResult] CA Dly = 32
2520 01:25:07.796177 CS Dly: 6 (0~38)
2521 01:25:07.796523
2522 01:25:07.799172 ----->DramcWriteLeveling(PI) begin...
2523 01:25:07.799627 ==
2524 01:25:07.802417 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 01:25:07.809366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 01:25:07.809799 ==
2527 01:25:07.812726 Write leveling (Byte 0): 32 => 32
2528 01:25:07.816146 Write leveling (Byte 1): 29 => 29
2529 01:25:07.816560 DramcWriteLeveling(PI) end<-----
2530 01:25:07.816889
2531 01:25:07.819668 ==
2532 01:25:07.820086 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 01:25:07.826177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 01:25:07.826602 ==
2535 01:25:07.829725 [Gating] SW mode calibration
2536 01:25:07.836327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 01:25:07.839823 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 01:25:07.845870 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2539 01:25:07.849846 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2540 01:25:07.853081 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 01:25:07.859490 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 01:25:07.863122 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 01:25:07.866175 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 01:25:07.872946 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2545 01:25:07.876339 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2546 01:25:07.880062 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2547 01:25:07.882863 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 01:25:07.889829 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 01:25:07.893059 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 01:25:07.896143 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 01:25:07.903182 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 01:25:07.906341 1 0 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
2553 01:25:07.909887 1 0 28 | B1->B0 | 2727 4646 | 1 0 | (1 1) (0 0)
2554 01:25:07.916505 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2555 01:25:07.919278 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 01:25:07.923041 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 01:25:07.929560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 01:25:07.933101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 01:25:07.936965 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 01:25:07.942987 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 01:25:07.946395 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 01:25:07.949374 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2563 01:25:07.956612 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 01:25:07.959943 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 01:25:07.963474 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 01:25:07.970056 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 01:25:07.973339 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 01:25:07.976328 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 01:25:07.979534 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 01:25:07.986384 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 01:25:07.989342 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 01:25:07.992775 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 01:25:07.999428 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 01:25:08.002852 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 01:25:08.006570 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 01:25:08.013331 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 01:25:08.016010 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 01:25:08.019320 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2579 01:25:08.023095 Total UI for P1: 0, mck2ui 16
2580 01:25:08.026436 best dqsien dly found for B0: ( 1, 3, 28)
2581 01:25:08.032999 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 01:25:08.036572 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 01:25:08.039724 Total UI for P1: 0, mck2ui 16
2584 01:25:08.043150 best dqsien dly found for B1: ( 1, 4, 2)
2585 01:25:08.046699 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2586 01:25:08.050316 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2587 01:25:08.050866
2588 01:25:08.053318 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2589 01:25:08.056246 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 01:25:08.059716 [Gating] SW calibration Done
2591 01:25:08.060228 ==
2592 01:25:08.063464 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 01:25:08.066540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 01:25:08.067070 ==
2595 01:25:08.070307 RX Vref Scan: 0
2596 01:25:08.070834
2597 01:25:08.073347 RX Vref 0 -> 0, step: 1
2598 01:25:08.073857
2599 01:25:08.074186 RX Delay -40 -> 252, step: 8
2600 01:25:08.080180 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2601 01:25:08.083538 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2602 01:25:08.086481 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2603 01:25:08.090125 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2604 01:25:08.093167 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2605 01:25:08.097040 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2606 01:25:08.103567 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2607 01:25:08.106640 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2608 01:25:08.109765 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2609 01:25:08.113481 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2610 01:25:08.116902 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2611 01:25:08.123654 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2612 01:25:08.127007 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2613 01:25:08.130096 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2614 01:25:08.133490 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2615 01:25:08.136625 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2616 01:25:08.140717 ==
2617 01:25:08.141238 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 01:25:08.146956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 01:25:08.147467 ==
2620 01:25:08.147842 DQS Delay:
2621 01:25:08.150161 DQS0 = 0, DQS1 = 0
2622 01:25:08.150675 DQM Delay:
2623 01:25:08.153578 DQM0 = 121, DQM1 = 112
2624 01:25:08.154090 DQ Delay:
2625 01:25:08.157284 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2626 01:25:08.160957 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2627 01:25:08.163673 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2628 01:25:08.167170 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2629 01:25:08.167775
2630 01:25:08.168125
2631 01:25:08.168444 ==
2632 01:25:08.170739 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 01:25:08.176916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 01:25:08.177429 ==
2635 01:25:08.177766
2636 01:25:08.178070
2637 01:25:08.178359 TX Vref Scan disable
2638 01:25:08.180164 == TX Byte 0 ==
2639 01:25:08.183515 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2640 01:25:08.187161 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2641 01:25:08.190373 == TX Byte 1 ==
2642 01:25:08.193271 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2643 01:25:08.196934 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2644 01:25:08.200552 ==
2645 01:25:08.204033 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 01:25:08.206964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 01:25:08.207478 ==
2648 01:25:08.218468 TX Vref=22, minBit 0, minWin=25, winSum=407
2649 01:25:08.221697 TX Vref=24, minBit 0, minWin=25, winSum=409
2650 01:25:08.225304 TX Vref=26, minBit 0, minWin=25, winSum=416
2651 01:25:08.228499 TX Vref=28, minBit 1, minWin=26, winSum=422
2652 01:25:08.231664 TX Vref=30, minBit 4, minWin=26, winSum=423
2653 01:25:08.235100 TX Vref=32, minBit 10, minWin=25, winSum=416
2654 01:25:08.241544 [TxChooseVref] Worse bit 4, Min win 26, Win sum 423, Final Vref 30
2655 01:25:08.242057
2656 01:25:08.244681 Final TX Range 1 Vref 30
2657 01:25:08.245269
2658 01:25:08.245619 ==
2659 01:25:08.248345 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 01:25:08.251759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 01:25:08.252176 ==
2662 01:25:08.252508
2663 01:25:08.254942
2664 01:25:08.255356 TX Vref Scan disable
2665 01:25:08.258533 == TX Byte 0 ==
2666 01:25:08.261963 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2667 01:25:08.264716 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2668 01:25:08.268563 == TX Byte 1 ==
2669 01:25:08.271715 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2670 01:25:08.275169 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2671 01:25:08.275723
2672 01:25:08.278557 [DATLAT]
2673 01:25:08.279062 Freq=1200, CH0 RK0
2674 01:25:08.279397
2675 01:25:08.281937 DATLAT Default: 0xd
2676 01:25:08.282447 0, 0xFFFF, sum = 0
2677 01:25:08.285249 1, 0xFFFF, sum = 0
2678 01:25:08.285776 2, 0xFFFF, sum = 0
2679 01:25:08.288111 3, 0xFFFF, sum = 0
2680 01:25:08.288532 4, 0xFFFF, sum = 0
2681 01:25:08.292129 5, 0xFFFF, sum = 0
2682 01:25:08.292646 6, 0xFFFF, sum = 0
2683 01:25:08.294897 7, 0xFFFF, sum = 0
2684 01:25:08.295317 8, 0xFFFF, sum = 0
2685 01:25:08.298158 9, 0xFFFF, sum = 0
2686 01:25:08.298579 10, 0xFFFF, sum = 0
2687 01:25:08.302171 11, 0xFFFF, sum = 0
2688 01:25:08.305043 12, 0x0, sum = 1
2689 01:25:08.305465 13, 0x0, sum = 2
2690 01:25:08.305805 14, 0x0, sum = 3
2691 01:25:08.308758 15, 0x0, sum = 4
2692 01:25:08.309178 best_step = 13
2693 01:25:08.309506
2694 01:25:08.309811 ==
2695 01:25:08.311484 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 01:25:08.319411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 01:25:08.320055 ==
2698 01:25:08.320396 RX Vref Scan: 1
2699 01:25:08.320707
2700 01:25:08.321979 Set Vref Range= 32 -> 127
2701 01:25:08.322393
2702 01:25:08.325844 RX Vref 32 -> 127, step: 1
2703 01:25:08.326362
2704 01:25:08.328161 RX Delay -13 -> 252, step: 4
2705 01:25:08.328706
2706 01:25:08.332234 Set Vref, RX VrefLevel [Byte0]: 32
2707 01:25:08.332650 [Byte1]: 32
2708 01:25:08.336705
2709 01:25:08.337117 Set Vref, RX VrefLevel [Byte0]: 33
2710 01:25:08.339485 [Byte1]: 33
2711 01:25:08.344301
2712 01:25:08.344807 Set Vref, RX VrefLevel [Byte0]: 34
2713 01:25:08.347565 [Byte1]: 34
2714 01:25:08.352194
2715 01:25:08.352703 Set Vref, RX VrefLevel [Byte0]: 35
2716 01:25:08.355533 [Byte1]: 35
2717 01:25:08.360486
2718 01:25:08.360994 Set Vref, RX VrefLevel [Byte0]: 36
2719 01:25:08.363449 [Byte1]: 36
2720 01:25:08.367888
2721 01:25:08.368470 Set Vref, RX VrefLevel [Byte0]: 37
2722 01:25:08.371973 [Byte1]: 37
2723 01:25:08.376358
2724 01:25:08.376874 Set Vref, RX VrefLevel [Byte0]: 38
2725 01:25:08.379338 [Byte1]: 38
2726 01:25:08.383700
2727 01:25:08.384119 Set Vref, RX VrefLevel [Byte0]: 39
2728 01:25:08.387349 [Byte1]: 39
2729 01:25:08.391996
2730 01:25:08.392513 Set Vref, RX VrefLevel [Byte0]: 40
2731 01:25:08.395301 [Byte1]: 40
2732 01:25:08.399706
2733 01:25:08.400116 Set Vref, RX VrefLevel [Byte0]: 41
2734 01:25:08.402895 [Byte1]: 41
2735 01:25:08.407552
2736 01:25:08.407996 Set Vref, RX VrefLevel [Byte0]: 42
2737 01:25:08.410934 [Byte1]: 42
2738 01:25:08.415285
2739 01:25:08.415841 Set Vref, RX VrefLevel [Byte0]: 43
2740 01:25:08.418696 [Byte1]: 43
2741 01:25:08.423205
2742 01:25:08.423650 Set Vref, RX VrefLevel [Byte0]: 44
2743 01:25:08.427082 [Byte1]: 44
2744 01:25:08.430911
2745 01:25:08.431329 Set Vref, RX VrefLevel [Byte0]: 45
2746 01:25:08.434246 [Byte1]: 45
2747 01:25:08.438936
2748 01:25:08.439445 Set Vref, RX VrefLevel [Byte0]: 46
2749 01:25:08.442427 [Byte1]: 46
2750 01:25:08.447095
2751 01:25:08.447647 Set Vref, RX VrefLevel [Byte0]: 47
2752 01:25:08.450570 [Byte1]: 47
2753 01:25:08.455154
2754 01:25:08.455717 Set Vref, RX VrefLevel [Byte0]: 48
2755 01:25:08.458012 [Byte1]: 48
2756 01:25:08.462957
2757 01:25:08.463525 Set Vref, RX VrefLevel [Byte0]: 49
2758 01:25:08.466283 [Byte1]: 49
2759 01:25:08.470960
2760 01:25:08.471513 Set Vref, RX VrefLevel [Byte0]: 50
2761 01:25:08.474378 [Byte1]: 50
2762 01:25:08.478464
2763 01:25:08.479017 Set Vref, RX VrefLevel [Byte0]: 51
2764 01:25:08.482156 [Byte1]: 51
2765 01:25:08.486825
2766 01:25:08.487376 Set Vref, RX VrefLevel [Byte0]: 52
2767 01:25:08.489484 [Byte1]: 52
2768 01:25:08.494233
2769 01:25:08.494648 Set Vref, RX VrefLevel [Byte0]: 53
2770 01:25:08.497397 [Byte1]: 53
2771 01:25:08.501797
2772 01:25:08.505366 Set Vref, RX VrefLevel [Byte0]: 54
2773 01:25:08.508420 [Byte1]: 54
2774 01:25:08.508836
2775 01:25:08.511777 Set Vref, RX VrefLevel [Byte0]: 55
2776 01:25:08.515664 [Byte1]: 55
2777 01:25:08.516183
2778 01:25:08.518965 Set Vref, RX VrefLevel [Byte0]: 56
2779 01:25:08.522206 [Byte1]: 56
2780 01:25:08.525775
2781 01:25:08.526281 Set Vref, RX VrefLevel [Byte0]: 57
2782 01:25:08.529095 [Byte1]: 57
2783 01:25:08.533370
2784 01:25:08.533783 Set Vref, RX VrefLevel [Byte0]: 58
2785 01:25:08.536894 [Byte1]: 58
2786 01:25:08.541776
2787 01:25:08.542193 Set Vref, RX VrefLevel [Byte0]: 59
2788 01:25:08.545031 [Byte1]: 59
2789 01:25:08.549559
2790 01:25:08.550071 Set Vref, RX VrefLevel [Byte0]: 60
2791 01:25:08.552960 [Byte1]: 60
2792 01:25:08.557805
2793 01:25:08.558316 Set Vref, RX VrefLevel [Byte0]: 61
2794 01:25:08.560691 [Byte1]: 61
2795 01:25:08.565290
2796 01:25:08.565842 Set Vref, RX VrefLevel [Byte0]: 62
2797 01:25:08.568455 [Byte1]: 62
2798 01:25:08.573321
2799 01:25:08.573874 Set Vref, RX VrefLevel [Byte0]: 63
2800 01:25:08.576360 [Byte1]: 63
2801 01:25:08.581052
2802 01:25:08.581602 Set Vref, RX VrefLevel [Byte0]: 64
2803 01:25:08.584333 [Byte1]: 64
2804 01:25:08.589328
2805 01:25:08.589839 Set Vref, RX VrefLevel [Byte0]: 65
2806 01:25:08.591942 [Byte1]: 65
2807 01:25:08.596710
2808 01:25:08.597239 Set Vref, RX VrefLevel [Byte0]: 66
2809 01:25:08.600131 [Byte1]: 66
2810 01:25:08.604916
2811 01:25:08.605328 Set Vref, RX VrefLevel [Byte0]: 67
2812 01:25:08.608273 [Byte1]: 67
2813 01:25:08.612754
2814 01:25:08.613164 Set Vref, RX VrefLevel [Byte0]: 68
2815 01:25:08.616092 [Byte1]: 68
2816 01:25:08.620383
2817 01:25:08.620797 Set Vref, RX VrefLevel [Byte0]: 69
2818 01:25:08.623589 [Byte1]: 69
2819 01:25:08.628605
2820 01:25:08.629138 Set Vref, RX VrefLevel [Byte0]: 70
2821 01:25:08.631433 [Byte1]: 70
2822 01:25:08.636059
2823 01:25:08.636471 Set Vref, RX VrefLevel [Byte0]: 71
2824 01:25:08.639417 [Byte1]: 71
2825 01:25:08.644118
2826 01:25:08.644628 Set Vref, RX VrefLevel [Byte0]: 72
2827 01:25:08.647144 [Byte1]: 72
2828 01:25:08.652225
2829 01:25:08.652637 Final RX Vref Byte 0 = 54 to rank0
2830 01:25:08.655052 Final RX Vref Byte 1 = 55 to rank0
2831 01:25:08.658800 Final RX Vref Byte 0 = 54 to rank1
2832 01:25:08.662239 Final RX Vref Byte 1 = 55 to rank1==
2833 01:25:08.665801 Dram Type= 6, Freq= 0, CH_0, rank 0
2834 01:25:08.672088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 01:25:08.672605 ==
2836 01:25:08.672938 DQS Delay:
2837 01:25:08.673246 DQS0 = 0, DQS1 = 0
2838 01:25:08.675310 DQM Delay:
2839 01:25:08.675859 DQM0 = 120, DQM1 = 113
2840 01:25:08.678542 DQ Delay:
2841 01:25:08.681941 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2842 01:25:08.685634 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2843 01:25:08.688220 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2844 01:25:08.691955 DQ12 =118, DQ13 =118, DQ14 =126, DQ15 =122
2845 01:25:08.692471
2846 01:25:08.692803
2847 01:25:08.698531 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2848 01:25:08.701827 CH0 RK0: MR19=404, MR18=120B
2849 01:25:08.708614 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2850 01:25:08.709033
2851 01:25:08.712396 ----->DramcWriteLeveling(PI) begin...
2852 01:25:08.712818 ==
2853 01:25:08.715684 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 01:25:08.719037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 01:25:08.719551 ==
2856 01:25:08.722370 Write leveling (Byte 0): 33 => 33
2857 01:25:08.725945 Write leveling (Byte 1): 28 => 28
2858 01:25:08.728708 DramcWriteLeveling(PI) end<-----
2859 01:25:08.729147
2860 01:25:08.729471 ==
2861 01:25:08.732268 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 01:25:08.738736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 01:25:08.739152 ==
2864 01:25:08.739480 [Gating] SW mode calibration
2865 01:25:08.749500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2866 01:25:08.752345 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2867 01:25:08.755469 0 15 0 | B1->B0 | 3434 3030 | 0 1 | (0 0) (0 0)
2868 01:25:08.762325 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 01:25:08.766107 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2870 01:25:08.769089 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2871 01:25:08.776275 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2872 01:25:08.778986 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2873 01:25:08.782379 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 01:25:08.789173 0 15 28 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (1 0)
2875 01:25:08.793026 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2876 01:25:08.795960 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 01:25:08.802027 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2878 01:25:08.805598 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2879 01:25:08.809131 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2880 01:25:08.815423 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2881 01:25:08.819054 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
2882 01:25:08.823214 1 0 28 | B1->B0 | 3b3b 3c3c | 0 0 | (0 0) (0 0)
2883 01:25:08.825692 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2884 01:25:08.832477 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 01:25:08.836286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 01:25:08.839178 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 01:25:08.846301 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 01:25:08.849387 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 01:25:08.852215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 01:25:08.859747 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2891 01:25:08.862954 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 01:25:08.866152 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 01:25:08.872595 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 01:25:08.876161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 01:25:08.879655 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 01:25:08.886453 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 01:25:08.889077 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 01:25:08.893370 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 01:25:08.896261 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 01:25:08.902744 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 01:25:08.906080 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 01:25:08.909268 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 01:25:08.916264 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 01:25:08.919886 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 01:25:08.923196 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 01:25:08.929588 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2907 01:25:08.932646 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 01:25:08.936476 Total UI for P1: 0, mck2ui 16
2909 01:25:08.939457 best dqsien dly found for B0: ( 1, 3, 28)
2910 01:25:08.942725 Total UI for P1: 0, mck2ui 16
2911 01:25:08.946785 best dqsien dly found for B1: ( 1, 3, 28)
2912 01:25:08.949748 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2913 01:25:08.952513 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2914 01:25:08.952927
2915 01:25:08.956438 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2916 01:25:08.960128 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2917 01:25:08.963201 [Gating] SW calibration Done
2918 01:25:08.963766 ==
2919 01:25:08.966641 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 01:25:08.969673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 01:25:08.970110 ==
2922 01:25:08.973761 RX Vref Scan: 0
2923 01:25:08.974278
2924 01:25:08.976237 RX Vref 0 -> 0, step: 1
2925 01:25:08.976655
2926 01:25:08.976985 RX Delay -40 -> 252, step: 8
2927 01:25:08.982978 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2928 01:25:08.986550 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2929 01:25:08.990075 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2930 01:25:08.993383 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2931 01:25:08.996470 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2932 01:25:09.002731 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2933 01:25:09.006791 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2934 01:25:09.009831 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2935 01:25:09.013221 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2936 01:25:09.016113 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2937 01:25:09.022781 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2938 01:25:09.026479 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2939 01:25:09.029860 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2940 01:25:09.032667 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2941 01:25:09.036002 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2942 01:25:09.042915 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2943 01:25:09.043431 ==
2944 01:25:09.046710 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 01:25:09.049902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 01:25:09.050421 ==
2947 01:25:09.050757 DQS Delay:
2948 01:25:09.052820 DQS0 = 0, DQS1 = 0
2949 01:25:09.053336 DQM Delay:
2950 01:25:09.056165 DQM0 = 122, DQM1 = 114
2951 01:25:09.056585 DQ Delay:
2952 01:25:09.059701 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2953 01:25:09.063071 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2954 01:25:09.066730 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
2955 01:25:09.069383 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2956 01:25:09.069802
2957 01:25:09.070138
2958 01:25:09.073074 ==
2959 01:25:09.076257 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 01:25:09.079407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 01:25:09.079952 ==
2962 01:25:09.080291
2963 01:25:09.080604
2964 01:25:09.083251 TX Vref Scan disable
2965 01:25:09.083807 == TX Byte 0 ==
2966 01:25:09.086938 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2967 01:25:09.093383 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2968 01:25:09.093902 == TX Byte 1 ==
2969 01:25:09.096604 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2970 01:25:09.102878 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2971 01:25:09.103296 ==
2972 01:25:09.106362 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 01:25:09.109683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 01:25:09.110108 ==
2975 01:25:09.122046 TX Vref=22, minBit 3, minWin=25, winSum=415
2976 01:25:09.125451 TX Vref=24, minBit 3, minWin=25, winSum=419
2977 01:25:09.129058 TX Vref=26, minBit 0, minWin=26, winSum=423
2978 01:25:09.131933 TX Vref=28, minBit 1, minWin=26, winSum=429
2979 01:25:09.135420 TX Vref=30, minBit 7, minWin=26, winSum=433
2980 01:25:09.139107 TX Vref=32, minBit 0, minWin=26, winSum=426
2981 01:25:09.145383 [TxChooseVref] Worse bit 7, Min win 26, Win sum 433, Final Vref 30
2982 01:25:09.145950
2983 01:25:09.148502 Final TX Range 1 Vref 30
2984 01:25:09.148967
2985 01:25:09.149334 ==
2986 01:25:09.152354 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 01:25:09.155442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 01:25:09.156049 ==
2989 01:25:09.156426
2990 01:25:09.156768
2991 01:25:09.158565 TX Vref Scan disable
2992 01:25:09.162464 == TX Byte 0 ==
2993 01:25:09.165804 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2994 01:25:09.169432 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2995 01:25:09.172099 == TX Byte 1 ==
2996 01:25:09.175511 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2997 01:25:09.179103 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2998 01:25:09.179708
2999 01:25:09.182298 [DATLAT]
3000 01:25:09.182862 Freq=1200, CH0 RK1
3001 01:25:09.183259
3002 01:25:09.185577 DATLAT Default: 0xd
3003 01:25:09.186133 0, 0xFFFF, sum = 0
3004 01:25:09.189047 1, 0xFFFF, sum = 0
3005 01:25:09.189530 2, 0xFFFF, sum = 0
3006 01:25:09.191940 3, 0xFFFF, sum = 0
3007 01:25:09.192383 4, 0xFFFF, sum = 0
3008 01:25:09.195650 5, 0xFFFF, sum = 0
3009 01:25:09.196180 6, 0xFFFF, sum = 0
3010 01:25:09.198834 7, 0xFFFF, sum = 0
3011 01:25:09.199276 8, 0xFFFF, sum = 0
3012 01:25:09.202357 9, 0xFFFF, sum = 0
3013 01:25:09.205551 10, 0xFFFF, sum = 0
3014 01:25:09.206080 11, 0xFFFF, sum = 0
3015 01:25:09.208816 12, 0x0, sum = 1
3016 01:25:09.209237 13, 0x0, sum = 2
3017 01:25:09.209578 14, 0x0, sum = 3
3018 01:25:09.212012 15, 0x0, sum = 4
3019 01:25:09.212429 best_step = 13
3020 01:25:09.212760
3021 01:25:09.213070 ==
3022 01:25:09.215558 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 01:25:09.222613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 01:25:09.223028 ==
3025 01:25:09.223359 RX Vref Scan: 0
3026 01:25:09.223715
3027 01:25:09.226137 RX Vref 0 -> 0, step: 1
3028 01:25:09.226655
3029 01:25:09.229076 RX Delay -13 -> 252, step: 4
3030 01:25:09.232393 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3031 01:25:09.235335 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3032 01:25:09.242342 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3033 01:25:09.245689 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3034 01:25:09.248705 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3035 01:25:09.252049 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3036 01:25:09.255702 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3037 01:25:09.262579 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3038 01:25:09.266263 iDelay=195, Bit 8, Center 104 (39 ~ 170) 132
3039 01:25:09.268993 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3040 01:25:09.272345 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3041 01:25:09.275929 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3042 01:25:09.282637 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3043 01:25:09.286393 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3044 01:25:09.288744 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3045 01:25:09.292582 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3046 01:25:09.293143 ==
3047 01:25:09.296254 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 01:25:09.298743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 01:25:09.302122 ==
3050 01:25:09.302588 DQS Delay:
3051 01:25:09.302970 DQS0 = 0, DQS1 = 0
3052 01:25:09.306177 DQM Delay:
3053 01:25:09.306692 DQM0 = 121, DQM1 = 112
3054 01:25:09.308951 DQ Delay:
3055 01:25:09.312641 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3056 01:25:09.315481 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3057 01:25:09.318816 DQ8 =104, DQ9 =100, DQ10 =112, DQ11 =104
3058 01:25:09.322542 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3059 01:25:09.323067
3060 01:25:09.323408
3061 01:25:09.329018 [DQSOSCAuto] RK1, (LSB)MR18= 0xeef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3062 01:25:09.332463 CH0 RK1: MR19=403, MR18=EEF
3063 01:25:09.339093 CH0_RK1: MR19=0x403, MR18=0xEEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3064 01:25:09.342332 [RxdqsGatingPostProcess] freq 1200
3065 01:25:09.349249 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3066 01:25:09.349703 best DQS0 dly(2T, 0.5T) = (0, 11)
3067 01:25:09.352510 best DQS1 dly(2T, 0.5T) = (0, 12)
3068 01:25:09.355865 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3069 01:25:09.359237 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3070 01:25:09.362802 best DQS0 dly(2T, 0.5T) = (0, 11)
3071 01:25:09.366491 best DQS1 dly(2T, 0.5T) = (0, 11)
3072 01:25:09.369396 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3073 01:25:09.372526 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3074 01:25:09.376004 Pre-setting of DQS Precalculation
3075 01:25:09.379831 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3076 01:25:09.380402 ==
3077 01:25:09.382760 Dram Type= 6, Freq= 0, CH_1, rank 0
3078 01:25:09.389935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 01:25:09.390460 ==
3080 01:25:09.392541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 01:25:09.399269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3082 01:25:09.408151 [CA 0] Center 37 (7~68) winsize 62
3083 01:25:09.411530 [CA 1] Center 37 (7~68) winsize 62
3084 01:25:09.414612 [CA 2] Center 35 (5~65) winsize 61
3085 01:25:09.418182 [CA 3] Center 34 (4~64) winsize 61
3086 01:25:09.421159 [CA 4] Center 34 (5~64) winsize 60
3087 01:25:09.424704 [CA 5] Center 33 (3~63) winsize 61
3088 01:25:09.425139
3089 01:25:09.428285 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3090 01:25:09.428730
3091 01:25:09.431627 [CATrainingPosCal] consider 1 rank data
3092 01:25:09.435022 u2DelayCellTimex100 = 270/100 ps
3093 01:25:09.438113 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 01:25:09.441479 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 01:25:09.445130 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 01:25:09.451753 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 01:25:09.454854 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3098 01:25:09.458360 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3099 01:25:09.458778
3100 01:25:09.461858 CA PerBit enable=1, Macro0, CA PI delay=33
3101 01:25:09.462417
3102 01:25:09.465238 [CBTSetCACLKResult] CA Dly = 33
3103 01:25:09.465817 CS Dly: 8 (0~39)
3104 01:25:09.466292 ==
3105 01:25:09.467845 Dram Type= 6, Freq= 0, CH_1, rank 1
3106 01:25:09.474842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 01:25:09.475321 ==
3108 01:25:09.478227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 01:25:09.484871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 01:25:09.493806 [CA 0] Center 37 (7~68) winsize 62
3111 01:25:09.497064 [CA 1] Center 37 (7~68) winsize 62
3112 01:25:09.500777 [CA 2] Center 35 (5~65) winsize 61
3113 01:25:09.504095 [CA 3] Center 35 (5~65) winsize 61
3114 01:25:09.507353 [CA 4] Center 34 (4~65) winsize 62
3115 01:25:09.510609 [CA 5] Center 34 (4~64) winsize 61
3116 01:25:09.511053
3117 01:25:09.513931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3118 01:25:09.514349
3119 01:25:09.517208 [CATrainingPosCal] consider 2 rank data
3120 01:25:09.520673 u2DelayCellTimex100 = 270/100 ps
3121 01:25:09.524183 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 01:25:09.527518 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 01:25:09.530317 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3124 01:25:09.537011 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3125 01:25:09.540315 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3126 01:25:09.544058 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3127 01:25:09.544490
3128 01:25:09.547823 CA PerBit enable=1, Macro0, CA PI delay=33
3129 01:25:09.548320
3130 01:25:09.550152 [CBTSetCACLKResult] CA Dly = 33
3131 01:25:09.550708 CS Dly: 9 (0~41)
3132 01:25:09.551201
3133 01:25:09.553920 ----->DramcWriteLeveling(PI) begin...
3134 01:25:09.554498 ==
3135 01:25:09.557326 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 01:25:09.563888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 01:25:09.564126 ==
3138 01:25:09.567213 Write leveling (Byte 0): 25 => 25
3139 01:25:09.570235 Write leveling (Byte 1): 27 => 27
3140 01:25:09.570415 DramcWriteLeveling(PI) end<-----
3141 01:25:09.570558
3142 01:25:09.573640 ==
3143 01:25:09.576719 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 01:25:09.580433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 01:25:09.580564 ==
3146 01:25:09.583777 [Gating] SW mode calibration
3147 01:25:09.590306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3148 01:25:09.593208 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3149 01:25:09.599852 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3150 01:25:09.603441 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 01:25:09.606717 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3152 01:25:09.613635 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3153 01:25:09.616667 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3154 01:25:09.620305 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3155 01:25:09.626751 0 15 24 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 0)
3156 01:25:09.630205 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3157 01:25:09.633815 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 01:25:09.640585 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 01:25:09.643452 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 01:25:09.647109 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3161 01:25:09.650400 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3162 01:25:09.656964 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3163 01:25:09.660471 1 0 24 | B1->B0 | 3636 4343 | 1 0 | (0 0) (0 0)
3164 01:25:09.663953 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 01:25:09.670402 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 01:25:09.673837 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 01:25:09.676827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 01:25:09.684216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3169 01:25:09.687417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 01:25:09.690782 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 01:25:09.697465 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3172 01:25:09.701052 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3173 01:25:09.704440 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 01:25:09.710537 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 01:25:09.713942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 01:25:09.717102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 01:25:09.724097 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 01:25:09.727211 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 01:25:09.730487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 01:25:09.733806 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 01:25:09.740747 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 01:25:09.744100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 01:25:09.747685 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 01:25:09.754187 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 01:25:09.757756 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 01:25:09.761191 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 01:25:09.767824 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3188 01:25:09.771216 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3189 01:25:09.774639 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 01:25:09.777431 Total UI for P1: 0, mck2ui 16
3191 01:25:09.781220 best dqsien dly found for B0: ( 1, 3, 26)
3192 01:25:09.784286 Total UI for P1: 0, mck2ui 16
3193 01:25:09.787688 best dqsien dly found for B1: ( 1, 3, 26)
3194 01:25:09.791010 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3195 01:25:09.794514 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3196 01:25:09.794702
3197 01:25:09.797171 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3198 01:25:09.804053 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3199 01:25:09.804188 [Gating] SW calibration Done
3200 01:25:09.804291 ==
3201 01:25:09.807431 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 01:25:09.814023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 01:25:09.814140 ==
3204 01:25:09.814224 RX Vref Scan: 0
3205 01:25:09.814302
3206 01:25:09.817824 RX Vref 0 -> 0, step: 1
3207 01:25:09.817916
3208 01:25:09.820702 RX Delay -40 -> 252, step: 8
3209 01:25:09.824009 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3210 01:25:09.827367 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3211 01:25:09.830504 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3212 01:25:09.837621 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3213 01:25:09.840786 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3214 01:25:09.844245 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3215 01:25:09.847404 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3216 01:25:09.851083 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3217 01:25:09.854317 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3218 01:25:09.861543 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3219 01:25:09.864267 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3220 01:25:09.867464 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3221 01:25:09.871049 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3222 01:25:09.877880 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3223 01:25:09.881213 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3224 01:25:09.884492 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3225 01:25:09.884625 ==
3226 01:25:09.887363 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 01:25:09.891323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 01:25:09.891439 ==
3229 01:25:09.894124 DQS Delay:
3230 01:25:09.894227 DQS0 = 0, DQS1 = 0
3231 01:25:09.894308 DQM Delay:
3232 01:25:09.897737 DQM0 = 119, DQM1 = 116
3233 01:25:09.897855 DQ Delay:
3234 01:25:09.900835 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3235 01:25:09.904585 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3236 01:25:09.910614 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3237 01:25:09.914083 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3238 01:25:09.914166
3239 01:25:09.914255
3240 01:25:09.914321 ==
3241 01:25:09.917545 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 01:25:09.921232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 01:25:09.921316 ==
3244 01:25:09.921381
3245 01:25:09.921441
3246 01:25:09.924452 TX Vref Scan disable
3247 01:25:09.924555 == TX Byte 0 ==
3248 01:25:09.931046 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3249 01:25:09.934258 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3250 01:25:09.934384 == TX Byte 1 ==
3251 01:25:09.940991 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3252 01:25:09.944317 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3253 01:25:09.944424 ==
3254 01:25:09.947774 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 01:25:09.951369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 01:25:09.951484 ==
3257 01:25:09.963705 TX Vref=22, minBit 10, minWin=25, winSum=414
3258 01:25:09.966934 TX Vref=24, minBit 1, minWin=25, winSum=416
3259 01:25:09.970327 TX Vref=26, minBit 11, minWin=25, winSum=425
3260 01:25:09.973707 TX Vref=28, minBit 11, minWin=25, winSum=429
3261 01:25:09.976869 TX Vref=30, minBit 9, minWin=26, winSum=428
3262 01:25:09.983632 TX Vref=32, minBit 10, minWin=25, winSum=427
3263 01:25:09.987255 [TxChooseVref] Worse bit 9, Min win 26, Win sum 428, Final Vref 30
3264 01:25:09.987405
3265 01:25:09.990517 Final TX Range 1 Vref 30
3266 01:25:09.990665
3267 01:25:09.990762 ==
3268 01:25:09.993963 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 01:25:09.997401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 01:25:09.997547 ==
3271 01:25:10.000463
3272 01:25:10.000563
3273 01:25:10.000654 TX Vref Scan disable
3274 01:25:10.003523 == TX Byte 0 ==
3275 01:25:10.007089 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3276 01:25:10.010525 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3277 01:25:10.013581 == TX Byte 1 ==
3278 01:25:10.017427 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3279 01:25:10.020401 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3280 01:25:10.023991
3281 01:25:10.024192 [DATLAT]
3282 01:25:10.024352 Freq=1200, CH1 RK0
3283 01:25:10.024503
3284 01:25:10.027336 DATLAT Default: 0xd
3285 01:25:10.027578 0, 0xFFFF, sum = 0
3286 01:25:10.030751 1, 0xFFFF, sum = 0
3287 01:25:10.030996 2, 0xFFFF, sum = 0
3288 01:25:10.033609 3, 0xFFFF, sum = 0
3289 01:25:10.033997 4, 0xFFFF, sum = 0
3290 01:25:10.037401 5, 0xFFFF, sum = 0
3291 01:25:10.037721 6, 0xFFFF, sum = 0
3292 01:25:10.040467 7, 0xFFFF, sum = 0
3293 01:25:10.043969 8, 0xFFFF, sum = 0
3294 01:25:10.044319 9, 0xFFFF, sum = 0
3295 01:25:10.047617 10, 0xFFFF, sum = 0
3296 01:25:10.047927 11, 0xFFFF, sum = 0
3297 01:25:10.050840 12, 0x0, sum = 1
3298 01:25:10.051302 13, 0x0, sum = 2
3299 01:25:10.053536 14, 0x0, sum = 3
3300 01:25:10.053971 15, 0x0, sum = 4
3301 01:25:10.054251 best_step = 13
3302 01:25:10.054557
3303 01:25:10.057227 ==
3304 01:25:10.060329 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 01:25:10.064242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 01:25:10.064537 ==
3307 01:25:10.064772 RX Vref Scan: 1
3308 01:25:10.064994
3309 01:25:10.067313 Set Vref Range= 32 -> 127
3310 01:25:10.067632
3311 01:25:10.070579 RX Vref 32 -> 127, step: 1
3312 01:25:10.070868
3313 01:25:10.074030 RX Delay -5 -> 252, step: 4
3314 01:25:10.074319
3315 01:25:10.077077 Set Vref, RX VrefLevel [Byte0]: 32
3316 01:25:10.081017 [Byte1]: 32
3317 01:25:10.081314
3318 01:25:10.083814 Set Vref, RX VrefLevel [Byte0]: 33
3319 01:25:10.087205 [Byte1]: 33
3320 01:25:10.087696
3321 01:25:10.090763 Set Vref, RX VrefLevel [Byte0]: 34
3322 01:25:10.093486 [Byte1]: 34
3323 01:25:10.097526
3324 01:25:10.097606 Set Vref, RX VrefLevel [Byte0]: 35
3325 01:25:10.101498 [Byte1]: 35
3326 01:25:10.105629
3327 01:25:10.105706 Set Vref, RX VrefLevel [Byte0]: 36
3328 01:25:10.109038 [Byte1]: 36
3329 01:25:10.113819
3330 01:25:10.113898 Set Vref, RX VrefLevel [Byte0]: 37
3331 01:25:10.116592 [Byte1]: 37
3332 01:25:10.121559
3333 01:25:10.121639 Set Vref, RX VrefLevel [Byte0]: 38
3334 01:25:10.124292 [Byte1]: 38
3335 01:25:10.128770
3336 01:25:10.128856 Set Vref, RX VrefLevel [Byte0]: 39
3337 01:25:10.132449 [Byte1]: 39
3338 01:25:10.137078
3339 01:25:10.137178 Set Vref, RX VrefLevel [Byte0]: 40
3340 01:25:10.140057 [Byte1]: 40
3341 01:25:10.145230
3342 01:25:10.145344 Set Vref, RX VrefLevel [Byte0]: 41
3343 01:25:10.148025 [Byte1]: 41
3344 01:25:10.152926
3345 01:25:10.153059 Set Vref, RX VrefLevel [Byte0]: 42
3346 01:25:10.155826 [Byte1]: 42
3347 01:25:10.160509
3348 01:25:10.160658 Set Vref, RX VrefLevel [Byte0]: 43
3349 01:25:10.164130 [Byte1]: 43
3350 01:25:10.168559
3351 01:25:10.168757 Set Vref, RX VrefLevel [Byte0]: 44
3352 01:25:10.171833 [Byte1]: 44
3353 01:25:10.176403
3354 01:25:10.176638 Set Vref, RX VrefLevel [Byte0]: 45
3355 01:25:10.179931 [Byte1]: 45
3356 01:25:10.184186
3357 01:25:10.184623 Set Vref, RX VrefLevel [Byte0]: 46
3358 01:25:10.188005 [Byte1]: 46
3359 01:25:10.192036
3360 01:25:10.192450 Set Vref, RX VrefLevel [Byte0]: 47
3361 01:25:10.195221 [Byte1]: 47
3362 01:25:10.199706
3363 01:25:10.200371 Set Vref, RX VrefLevel [Byte0]: 48
3364 01:25:10.203545 [Byte1]: 48
3365 01:25:10.207662
3366 01:25:10.208359 Set Vref, RX VrefLevel [Byte0]: 49
3367 01:25:10.210911 [Byte1]: 49
3368 01:25:10.215866
3369 01:25:10.216301 Set Vref, RX VrefLevel [Byte0]: 50
3370 01:25:10.218817 [Byte1]: 50
3371 01:25:10.223818
3372 01:25:10.224302 Set Vref, RX VrefLevel [Byte0]: 51
3373 01:25:10.227186 [Byte1]: 51
3374 01:25:10.231832
3375 01:25:10.232252 Set Vref, RX VrefLevel [Byte0]: 52
3376 01:25:10.234726 [Byte1]: 52
3377 01:25:10.239378
3378 01:25:10.239975 Set Vref, RX VrefLevel [Byte0]: 53
3379 01:25:10.242652 [Byte1]: 53
3380 01:25:10.246993
3381 01:25:10.247507 Set Vref, RX VrefLevel [Byte0]: 54
3382 01:25:10.250302 [Byte1]: 54
3383 01:25:10.255244
3384 01:25:10.255704 Set Vref, RX VrefLevel [Byte0]: 55
3385 01:25:10.258386 [Byte1]: 55
3386 01:25:10.262943
3387 01:25:10.263465 Set Vref, RX VrefLevel [Byte0]: 56
3388 01:25:10.266933 [Byte1]: 56
3389 01:25:10.270978
3390 01:25:10.271486 Set Vref, RX VrefLevel [Byte0]: 57
3391 01:25:10.274227 [Byte1]: 57
3392 01:25:10.278760
3393 01:25:10.279184 Set Vref, RX VrefLevel [Byte0]: 58
3394 01:25:10.281790 [Byte1]: 58
3395 01:25:10.286481
3396 01:25:10.286934 Set Vref, RX VrefLevel [Byte0]: 59
3397 01:25:10.289580 [Byte1]: 59
3398 01:25:10.294456
3399 01:25:10.294962 Set Vref, RX VrefLevel [Byte0]: 60
3400 01:25:10.297644 [Byte1]: 60
3401 01:25:10.301929
3402 01:25:10.302469 Set Vref, RX VrefLevel [Byte0]: 61
3403 01:25:10.305266 [Byte1]: 61
3404 01:25:10.310069
3405 01:25:10.310498 Set Vref, RX VrefLevel [Byte0]: 62
3406 01:25:10.313679 [Byte1]: 62
3407 01:25:10.317932
3408 01:25:10.318347 Set Vref, RX VrefLevel [Byte0]: 63
3409 01:25:10.321030 [Byte1]: 63
3410 01:25:10.326277
3411 01:25:10.326780 Set Vref, RX VrefLevel [Byte0]: 64
3412 01:25:10.329138 [Byte1]: 64
3413 01:25:10.333420
3414 01:25:10.333830 Set Vref, RX VrefLevel [Byte0]: 65
3415 01:25:10.336797 [Byte1]: 65
3416 01:25:10.341671
3417 01:25:10.342190 Set Vref, RX VrefLevel [Byte0]: 66
3418 01:25:10.344938 [Byte1]: 66
3419 01:25:10.349402
3420 01:25:10.349818 Set Vref, RX VrefLevel [Byte0]: 67
3421 01:25:10.352810 [Byte1]: 67
3422 01:25:10.357734
3423 01:25:10.358241 Set Vref, RX VrefLevel [Byte0]: 68
3424 01:25:10.360268 [Byte1]: 68
3425 01:25:10.365470
3426 01:25:10.365970 Set Vref, RX VrefLevel [Byte0]: 69
3427 01:25:10.368011 [Byte1]: 69
3428 01:25:10.372648
3429 01:25:10.373164 Final RX Vref Byte 0 = 53 to rank0
3430 01:25:10.376288 Final RX Vref Byte 1 = 49 to rank0
3431 01:25:10.379190 Final RX Vref Byte 0 = 53 to rank1
3432 01:25:10.382631 Final RX Vref Byte 1 = 49 to rank1==
3433 01:25:10.386474 Dram Type= 6, Freq= 0, CH_1, rank 0
3434 01:25:10.392884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 01:25:10.393322 ==
3436 01:25:10.393800 DQS Delay:
3437 01:25:10.394239 DQS0 = 0, DQS1 = 0
3438 01:25:10.396454 DQM Delay:
3439 01:25:10.397079 DQM0 = 120, DQM1 = 116
3440 01:25:10.399375 DQ Delay:
3441 01:25:10.402891 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3442 01:25:10.405848 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3443 01:25:10.409045 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3444 01:25:10.412318 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3445 01:25:10.412607
3446 01:25:10.412759
3447 01:25:10.419590 [DQSOSCAuto] RK0, (LSB)MR18= 0x12, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3448 01:25:10.422407 CH1 RK0: MR19=404, MR18=12
3449 01:25:10.429569 CH1_RK0: MR19=0x404, MR18=0x12, DQSOSC=403, MR23=63, INC=40, DEC=26
3450 01:25:10.429808
3451 01:25:10.432516 ----->DramcWriteLeveling(PI) begin...
3452 01:25:10.432800 ==
3453 01:25:10.436173 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 01:25:10.439309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 01:25:10.439511 ==
3456 01:25:10.442317 Write leveling (Byte 0): 26 => 26
3457 01:25:10.445920 Write leveling (Byte 1): 28 => 28
3458 01:25:10.448988 DramcWriteLeveling(PI) end<-----
3459 01:25:10.449068
3460 01:25:10.449132 ==
3461 01:25:10.452208 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 01:25:10.455776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 01:25:10.459264 ==
3464 01:25:10.459346 [Gating] SW mode calibration
3465 01:25:10.465559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3466 01:25:10.472499 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3467 01:25:10.476258 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 01:25:10.482618 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 01:25:10.486443 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 01:25:10.489480 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 01:25:10.496151 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 01:25:10.499518 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3473 01:25:10.502973 0 15 24 | B1->B0 | 2929 3333 | 0 1 | (1 0) (1 0)
3474 01:25:10.509308 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3475 01:25:10.512865 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 01:25:10.516091 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 01:25:10.519153 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 01:25:10.526357 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 01:25:10.529313 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 01:25:10.532773 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3481 01:25:10.539457 1 0 24 | B1->B0 | 4141 2626 | 0 0 | (0 0) (0 0)
3482 01:25:10.542641 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 01:25:10.546128 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 01:25:10.552916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 01:25:10.556048 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 01:25:10.559469 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 01:25:10.566299 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 01:25:10.569142 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 01:25:10.572699 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3490 01:25:10.579210 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3491 01:25:10.582858 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 01:25:10.586207 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 01:25:10.592632 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 01:25:10.596035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 01:25:10.599277 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 01:25:10.605687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 01:25:10.609379 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 01:25:10.612407 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 01:25:10.619223 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 01:25:10.622404 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 01:25:10.625943 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 01:25:10.632599 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 01:25:10.636310 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 01:25:10.639195 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3505 01:25:10.642791 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3506 01:25:10.649207 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3507 01:25:10.652659 Total UI for P1: 0, mck2ui 16
3508 01:25:10.656264 best dqsien dly found for B1: ( 1, 3, 22)
3509 01:25:10.658939 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 01:25:10.662402 Total UI for P1: 0, mck2ui 16
3511 01:25:10.665714 best dqsien dly found for B0: ( 1, 3, 28)
3512 01:25:10.669251 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3513 01:25:10.672451 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3514 01:25:10.672950
3515 01:25:10.675731 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3516 01:25:10.679235 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3517 01:25:10.682370 [Gating] SW calibration Done
3518 01:25:10.682608 ==
3519 01:25:10.685854 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 01:25:10.692566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 01:25:10.692651 ==
3522 01:25:10.692784 RX Vref Scan: 0
3523 01:25:10.692880
3524 01:25:10.695644 RX Vref 0 -> 0, step: 1
3525 01:25:10.695729
3526 01:25:10.699315 RX Delay -40 -> 252, step: 8
3527 01:25:10.702066 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3528 01:25:10.705813 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3529 01:25:10.708817 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3530 01:25:10.712596 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3531 01:25:10.718561 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3532 01:25:10.722003 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3533 01:25:10.725210 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3534 01:25:10.729154 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3535 01:25:10.732424 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3536 01:25:10.738718 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3537 01:25:10.742162 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3538 01:25:10.745376 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3539 01:25:10.748776 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3540 01:25:10.751770 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3541 01:25:10.758481 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3542 01:25:10.762193 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3543 01:25:10.762324 ==
3544 01:25:10.765170 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 01:25:10.768467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 01:25:10.768614 ==
3547 01:25:10.771824 DQS Delay:
3548 01:25:10.772000 DQS0 = 0, DQS1 = 0
3549 01:25:10.772202 DQM Delay:
3550 01:25:10.775401 DQM0 = 119, DQM1 = 118
3551 01:25:10.775574 DQ Delay:
3552 01:25:10.778344 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3553 01:25:10.781776 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3554 01:25:10.788782 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3555 01:25:10.792334 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3556 01:25:10.792699
3557 01:25:10.793002
3558 01:25:10.793275 ==
3559 01:25:10.795336 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 01:25:10.799013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 01:25:10.799272 ==
3562 01:25:10.799475
3563 01:25:10.799696
3564 01:25:10.802102 TX Vref Scan disable
3565 01:25:10.802367 == TX Byte 0 ==
3566 01:25:10.808949 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 01:25:10.812290 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 01:25:10.812547 == TX Byte 1 ==
3569 01:25:10.818347 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3570 01:25:10.821963 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3571 01:25:10.822232 ==
3572 01:25:10.825248 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 01:25:10.828445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 01:25:10.828719 ==
3575 01:25:10.841848 TX Vref=22, minBit 10, minWin=24, winSum=419
3576 01:25:10.844461 TX Vref=24, minBit 10, minWin=25, winSum=426
3577 01:25:10.848317 TX Vref=26, minBit 10, minWin=25, winSum=427
3578 01:25:10.851653 TX Vref=28, minBit 2, minWin=26, winSum=430
3579 01:25:10.854529 TX Vref=30, minBit 9, minWin=26, winSum=434
3580 01:25:10.861604 TX Vref=32, minBit 9, minWin=26, winSum=432
3581 01:25:10.864471 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3582 01:25:10.864762
3583 01:25:10.868050 Final TX Range 1 Vref 30
3584 01:25:10.868371
3585 01:25:10.868661 ==
3586 01:25:10.871264 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 01:25:10.874872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 01:25:10.875134 ==
3589 01:25:10.877819
3590 01:25:10.878072
3591 01:25:10.878271 TX Vref Scan disable
3592 01:25:10.881890 == TX Byte 0 ==
3593 01:25:10.884730 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 01:25:10.888154 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 01:25:10.891520 == TX Byte 1 ==
3596 01:25:10.895464 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3597 01:25:10.898145 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3598 01:25:10.901466
3599 01:25:10.901717 [DATLAT]
3600 01:25:10.901915 Freq=1200, CH1 RK1
3601 01:25:10.902104
3602 01:25:10.905191 DATLAT Default: 0xd
3603 01:25:10.905446 0, 0xFFFF, sum = 0
3604 01:25:10.908449 1, 0xFFFF, sum = 0
3605 01:25:10.908530 2, 0xFFFF, sum = 0
3606 01:25:10.911232 3, 0xFFFF, sum = 0
3607 01:25:10.911345 4, 0xFFFF, sum = 0
3608 01:25:10.914561 5, 0xFFFF, sum = 0
3609 01:25:10.918431 6, 0xFFFF, sum = 0
3610 01:25:10.919043 7, 0xFFFF, sum = 0
3611 01:25:10.921586 8, 0xFFFF, sum = 0
3612 01:25:10.922151 9, 0xFFFF, sum = 0
3613 01:25:10.924861 10, 0xFFFF, sum = 0
3614 01:25:10.925316 11, 0xFFFF, sum = 0
3615 01:25:10.927950 12, 0x0, sum = 1
3616 01:25:10.928445 13, 0x0, sum = 2
3617 01:25:10.931719 14, 0x0, sum = 3
3618 01:25:10.932295 15, 0x0, sum = 4
3619 01:25:10.932850 best_step = 13
3620 01:25:10.933286
3621 01:25:10.934769 ==
3622 01:25:10.937989 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 01:25:10.941497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 01:25:10.941899 ==
3625 01:25:10.942249 RX Vref Scan: 0
3626 01:25:10.942572
3627 01:25:10.944785 RX Vref 0 -> 0, step: 1
3628 01:25:10.945200
3629 01:25:10.947814 RX Delay -5 -> 252, step: 4
3630 01:25:10.951334 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3631 01:25:10.958352 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3632 01:25:10.961851 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3633 01:25:10.964611 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3634 01:25:10.968320 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3635 01:25:10.970984 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3636 01:25:10.978295 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3637 01:25:10.980815 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3638 01:25:10.984264 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3639 01:25:10.987438 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3640 01:25:10.991108 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3641 01:25:10.997723 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3642 01:25:11.000981 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3643 01:25:11.004486 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3644 01:25:11.007532 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3645 01:25:11.011191 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3646 01:25:11.011294 ==
3647 01:25:11.014279 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 01:25:11.021219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 01:25:11.021307 ==
3650 01:25:11.021374 DQS Delay:
3651 01:25:11.024732 DQS0 = 0, DQS1 = 0
3652 01:25:11.024816 DQM Delay:
3653 01:25:11.027831 DQM0 = 120, DQM1 = 116
3654 01:25:11.027926 DQ Delay:
3655 01:25:11.031063 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3656 01:25:11.034714 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3657 01:25:11.037508 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3658 01:25:11.041272 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3659 01:25:11.041377
3660 01:25:11.041479
3661 01:25:11.051265 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3662 01:25:11.051350 CH1 RK1: MR19=403, MR18=12EF
3663 01:25:11.057703 CH1_RK1: MR19=0x403, MR18=0x12EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3664 01:25:11.060939 [RxdqsGatingPostProcess] freq 1200
3665 01:25:11.067360 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 01:25:11.070512 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 01:25:11.074422 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 01:25:11.077510 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 01:25:11.080837 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 01:25:11.083863 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 01:25:11.087271 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 01:25:11.090991 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 01:25:11.091105 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 01:25:11.094298 Pre-setting of DQS Precalculation
3675 01:25:11.100912 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 01:25:11.107259 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 01:25:11.114038 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 01:25:11.114255
3679 01:25:11.114476
3680 01:25:11.117372 [Calibration Summary] 2400 Mbps
3681 01:25:11.120933 CH 0, Rank 0
3682 01:25:11.121195 SW Impedance : PASS
3683 01:25:11.124192 DUTY Scan : NO K
3684 01:25:11.124528 ZQ Calibration : PASS
3685 01:25:11.127481 Jitter Meter : NO K
3686 01:25:11.130973 CBT Training : PASS
3687 01:25:11.131404 Write leveling : PASS
3688 01:25:11.134566 RX DQS gating : PASS
3689 01:25:11.137635 RX DQ/DQS(RDDQC) : PASS
3690 01:25:11.138049 TX DQ/DQS : PASS
3691 01:25:11.140929 RX DATLAT : PASS
3692 01:25:11.144034 RX DQ/DQS(Engine): PASS
3693 01:25:11.144501 TX OE : NO K
3694 01:25:11.147790 All Pass.
3695 01:25:11.148205
3696 01:25:11.148536 CH 0, Rank 1
3697 01:25:11.150885 SW Impedance : PASS
3698 01:25:11.151297 DUTY Scan : NO K
3699 01:25:11.154320 ZQ Calibration : PASS
3700 01:25:11.157763 Jitter Meter : NO K
3701 01:25:11.158179 CBT Training : PASS
3702 01:25:11.160598 Write leveling : PASS
3703 01:25:11.164067 RX DQS gating : PASS
3704 01:25:11.164481 RX DQ/DQS(RDDQC) : PASS
3705 01:25:11.168008 TX DQ/DQS : PASS
3706 01:25:11.171416 RX DATLAT : PASS
3707 01:25:11.171966 RX DQ/DQS(Engine): PASS
3708 01:25:11.174547 TX OE : NO K
3709 01:25:11.174983 All Pass.
3710 01:25:11.175399
3711 01:25:11.177274 CH 1, Rank 0
3712 01:25:11.177837 SW Impedance : PASS
3713 01:25:11.180706 DUTY Scan : NO K
3714 01:25:11.181122 ZQ Calibration : PASS
3715 01:25:11.184097 Jitter Meter : NO K
3716 01:25:11.187657 CBT Training : PASS
3717 01:25:11.188075 Write leveling : PASS
3718 01:25:11.191134 RX DQS gating : PASS
3719 01:25:11.194014 RX DQ/DQS(RDDQC) : PASS
3720 01:25:11.194561 TX DQ/DQS : PASS
3721 01:25:11.197487 RX DATLAT : PASS
3722 01:25:11.200699 RX DQ/DQS(Engine): PASS
3723 01:25:11.201114 TX OE : NO K
3724 01:25:11.204025 All Pass.
3725 01:25:11.204438
3726 01:25:11.204763 CH 1, Rank 1
3727 01:25:11.207657 SW Impedance : PASS
3728 01:25:11.208076 DUTY Scan : NO K
3729 01:25:11.210788 ZQ Calibration : PASS
3730 01:25:11.213864 Jitter Meter : NO K
3731 01:25:11.214277 CBT Training : PASS
3732 01:25:11.217310 Write leveling : PASS
3733 01:25:11.220642 RX DQS gating : PASS
3734 01:25:11.221102 RX DQ/DQS(RDDQC) : PASS
3735 01:25:11.224048 TX DQ/DQS : PASS
3736 01:25:11.227570 RX DATLAT : PASS
3737 01:25:11.228175 RX DQ/DQS(Engine): PASS
3738 01:25:11.230550 TX OE : NO K
3739 01:25:11.230965 All Pass.
3740 01:25:11.231297
3741 01:25:11.234073 DramC Write-DBI off
3742 01:25:11.236823 PER_BANK_REFRESH: Hybrid Mode
3743 01:25:11.237239 TX_TRACKING: ON
3744 01:25:11.247571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 01:25:11.250592 [FAST_K] Save calibration result to emmc
3746 01:25:11.253926 dramc_set_vcore_voltage set vcore to 650000
3747 01:25:11.257543 Read voltage for 600, 5
3748 01:25:11.257847 Vio18 = 0
3749 01:25:11.258084 Vcore = 650000
3750 01:25:11.258325 Vdram = 0
3751 01:25:11.260041 Vddq = 0
3752 01:25:11.260341 Vmddr = 0
3753 01:25:11.267106 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 01:25:11.270469 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 01:25:11.273791 MEM_TYPE=3, freq_sel=19
3756 01:25:11.277210 sv_algorithm_assistance_LP4_1600
3757 01:25:11.280690 ============ PULL DRAM RESETB DOWN ============
3758 01:25:11.284030 ========== PULL DRAM RESETB DOWN end =========
3759 01:25:11.290583 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 01:25:11.294121 ===================================
3761 01:25:11.294530 LPDDR4 DRAM CONFIGURATION
3762 01:25:11.297438 ===================================
3763 01:25:11.300818 EX_ROW_EN[0] = 0x0
3764 01:25:11.301211 EX_ROW_EN[1] = 0x0
3765 01:25:11.304273 LP4Y_EN = 0x0
3766 01:25:11.307278 WORK_FSP = 0x0
3767 01:25:11.307576 WL = 0x2
3768 01:25:11.310174 RL = 0x2
3769 01:25:11.310549 BL = 0x2
3770 01:25:11.313214 RPST = 0x0
3771 01:25:11.313295 RD_PRE = 0x0
3772 01:25:11.316776 WR_PRE = 0x1
3773 01:25:11.316857 WR_PST = 0x0
3774 01:25:11.319965 DBI_WR = 0x0
3775 01:25:11.320047 DBI_RD = 0x0
3776 01:25:11.323123 OTF = 0x1
3777 01:25:11.326473 ===================================
3778 01:25:11.330310 ===================================
3779 01:25:11.330390 ANA top config
3780 01:25:11.333313 ===================================
3781 01:25:11.336541 DLL_ASYNC_EN = 0
3782 01:25:11.340087 ALL_SLAVE_EN = 1
3783 01:25:11.340168 NEW_RANK_MODE = 1
3784 01:25:11.343498 DLL_IDLE_MODE = 1
3785 01:25:11.346892 LP45_APHY_COMB_EN = 1
3786 01:25:11.349949 TX_ODT_DIS = 1
3787 01:25:11.353394 NEW_8X_MODE = 1
3788 01:25:11.356592 ===================================
3789 01:25:11.359770 ===================================
3790 01:25:11.359871 data_rate = 1200
3791 01:25:11.363467 CKR = 1
3792 01:25:11.366496 DQ_P2S_RATIO = 8
3793 01:25:11.369778 ===================================
3794 01:25:11.372972 CA_P2S_RATIO = 8
3795 01:25:11.376619 DQ_CA_OPEN = 0
3796 01:25:11.379639 DQ_SEMI_OPEN = 0
3797 01:25:11.379789 CA_SEMI_OPEN = 0
3798 01:25:11.383581 CA_FULL_RATE = 0
3799 01:25:11.386770 DQ_CKDIV4_EN = 1
3800 01:25:11.389982 CA_CKDIV4_EN = 1
3801 01:25:11.393053 CA_PREDIV_EN = 0
3802 01:25:11.396370 PH8_DLY = 0
3803 01:25:11.396706 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 01:25:11.399836 DQ_AAMCK_DIV = 4
3805 01:25:11.403397 CA_AAMCK_DIV = 4
3806 01:25:11.406705 CA_ADMCK_DIV = 4
3807 01:25:11.409754 DQ_TRACK_CA_EN = 0
3808 01:25:11.412968 CA_PICK = 600
3809 01:25:11.413267 CA_MCKIO = 600
3810 01:25:11.416853 MCKIO_SEMI = 0
3811 01:25:11.419708 PLL_FREQ = 2288
3812 01:25:11.423457 DQ_UI_PI_RATIO = 32
3813 01:25:11.426517 CA_UI_PI_RATIO = 0
3814 01:25:11.429991 ===================================
3815 01:25:11.433737 ===================================
3816 01:25:11.436305 memory_type:LPDDR4
3817 01:25:11.436395 GP_NUM : 10
3818 01:25:11.439555 SRAM_EN : 1
3819 01:25:11.439698 MD32_EN : 0
3820 01:25:11.442632 ===================================
3821 01:25:11.446087 [ANA_INIT] >>>>>>>>>>>>>>
3822 01:25:11.449644 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 01:25:11.452722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 01:25:11.456249 ===================================
3825 01:25:11.459832 data_rate = 1200,PCW = 0X5800
3826 01:25:11.462670 ===================================
3827 01:25:11.466224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 01:25:11.469748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 01:25:11.476224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 01:25:11.479624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 01:25:11.482939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 01:25:11.489712 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 01:25:11.489793 [ANA_INIT] flow start
3834 01:25:11.492735 [ANA_INIT] PLL >>>>>>>>
3835 01:25:11.496153 [ANA_INIT] PLL <<<<<<<<
3836 01:25:11.496237 [ANA_INIT] MIDPI >>>>>>>>
3837 01:25:11.499576 [ANA_INIT] MIDPI <<<<<<<<
3838 01:25:11.503005 [ANA_INIT] DLL >>>>>>>>
3839 01:25:11.503082 [ANA_INIT] flow end
3840 01:25:11.505864 ============ LP4 DIFF to SE enter ============
3841 01:25:11.512743 ============ LP4 DIFF to SE exit ============
3842 01:25:11.512826 [ANA_INIT] <<<<<<<<<<<<<
3843 01:25:11.516188 [Flow] Enable top DCM control >>>>>
3844 01:25:11.519964 [Flow] Enable top DCM control <<<<<
3845 01:25:11.522570 Enable DLL master slave shuffle
3846 01:25:11.529328 ==============================================================
3847 01:25:11.529417 Gating Mode config
3848 01:25:11.536152 ==============================================================
3849 01:25:11.539642 Config description:
3850 01:25:11.549594 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 01:25:11.556306 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 01:25:11.559870 SELPH_MODE 0: By rank 1: By Phase
3853 01:25:11.566426 ==============================================================
3854 01:25:11.569600 GAT_TRACK_EN = 1
3855 01:25:11.569682 RX_GATING_MODE = 2
3856 01:25:11.572520 RX_GATING_TRACK_MODE = 2
3857 01:25:11.576028 SELPH_MODE = 1
3858 01:25:11.579635 PICG_EARLY_EN = 1
3859 01:25:11.582832 VALID_LAT_VALUE = 1
3860 01:25:11.589310 ==============================================================
3861 01:25:11.593030 Enter into Gating configuration >>>>
3862 01:25:11.595980 Exit from Gating configuration <<<<
3863 01:25:11.599370 Enter into DVFS_PRE_config >>>>>
3864 01:25:11.609650 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 01:25:11.612570 Exit from DVFS_PRE_config <<<<<
3866 01:25:11.616035 Enter into PICG configuration >>>>
3867 01:25:11.619005 Exit from PICG configuration <<<<
3868 01:25:11.622631 [RX_INPUT] configuration >>>>>
3869 01:25:11.625513 [RX_INPUT] configuration <<<<<
3870 01:25:11.628842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 01:25:11.635440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 01:25:11.642795 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 01:25:11.649398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 01:25:11.652410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 01:25:11.658859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 01:25:11.662271 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 01:25:11.666115 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 01:25:11.672796 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 01:25:11.676135 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 01:25:11.678906 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 01:25:11.686052 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 01:25:11.689411 ===================================
3883 01:25:11.689493 LPDDR4 DRAM CONFIGURATION
3884 01:25:11.692200 ===================================
3885 01:25:11.695559 EX_ROW_EN[0] = 0x0
3886 01:25:11.698785 EX_ROW_EN[1] = 0x0
3887 01:25:11.698866 LP4Y_EN = 0x0
3888 01:25:11.702710 WORK_FSP = 0x0
3889 01:25:11.702791 WL = 0x2
3890 01:25:11.705815 RL = 0x2
3891 01:25:11.705896 BL = 0x2
3892 01:25:11.709044 RPST = 0x0
3893 01:25:11.709131 RD_PRE = 0x0
3894 01:25:11.712351 WR_PRE = 0x1
3895 01:25:11.712445 WR_PST = 0x0
3896 01:25:11.715488 DBI_WR = 0x0
3897 01:25:11.715582 DBI_RD = 0x0
3898 01:25:11.719067 OTF = 0x1
3899 01:25:11.722544 ===================================
3900 01:25:11.726327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 01:25:11.729707 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 01:25:11.735547 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 01:25:11.738698 ===================================
3904 01:25:11.738890 LPDDR4 DRAM CONFIGURATION
3905 01:25:11.742200 ===================================
3906 01:25:11.745812 EX_ROW_EN[0] = 0x10
3907 01:25:11.748732 EX_ROW_EN[1] = 0x0
3908 01:25:11.748932 LP4Y_EN = 0x0
3909 01:25:11.752348 WORK_FSP = 0x0
3910 01:25:11.752588 WL = 0x2
3911 01:25:11.755755 RL = 0x2
3912 01:25:11.756082 BL = 0x2
3913 01:25:11.758648 RPST = 0x0
3914 01:25:11.759060 RD_PRE = 0x0
3915 01:25:11.761970 WR_PRE = 0x1
3916 01:25:11.762296 WR_PST = 0x0
3917 01:25:11.765400 DBI_WR = 0x0
3918 01:25:11.765786 DBI_RD = 0x0
3919 01:25:11.768651 OTF = 0x1
3920 01:25:11.772239 ===================================
3921 01:25:11.778475 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 01:25:11.782130 nWR fixed to 30
3923 01:25:11.782231 [ModeRegInit_LP4] CH0 RK0
3924 01:25:11.785200 [ModeRegInit_LP4] CH0 RK1
3925 01:25:11.788912 [ModeRegInit_LP4] CH1 RK0
3926 01:25:11.789332 [ModeRegInit_LP4] CH1 RK1
3927 01:25:11.792381 match AC timing 17
3928 01:25:11.795513 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 01:25:11.799438 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 01:25:11.805469 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 01:25:11.808754 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 01:25:11.816131 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 01:25:11.816589 ==
3934 01:25:11.818758 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 01:25:11.822439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 01:25:11.822861 ==
3937 01:25:11.828771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 01:25:11.832107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3939 01:25:11.836686 [CA 0] Center 36 (5~67) winsize 63
3940 01:25:11.840319 [CA 1] Center 35 (5~66) winsize 62
3941 01:25:11.843559 [CA 2] Center 33 (3~64) winsize 62
3942 01:25:11.846895 [CA 3] Center 33 (2~64) winsize 63
3943 01:25:11.850534 [CA 4] Center 33 (2~64) winsize 63
3944 01:25:11.853478 [CA 5] Center 32 (2~63) winsize 62
3945 01:25:11.853901
3946 01:25:11.856559 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3947 01:25:11.856973
3948 01:25:11.860463 [CATrainingPosCal] consider 1 rank data
3949 01:25:11.863427 u2DelayCellTimex100 = 270/100 ps
3950 01:25:11.866622 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3951 01:25:11.869738 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3952 01:25:11.876633 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3953 01:25:11.880056 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3954 01:25:11.883203 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3955 01:25:11.886925 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3956 01:25:11.887344
3957 01:25:11.889719 CA PerBit enable=1, Macro0, CA PI delay=32
3958 01:25:11.890140
3959 01:25:11.893709 [CBTSetCACLKResult] CA Dly = 32
3960 01:25:11.894130 CS Dly: 4 (0~35)
3961 01:25:11.896521 ==
3962 01:25:11.897073 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 01:25:11.903055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 01:25:11.903472 ==
3965 01:25:11.906496 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 01:25:11.913761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3967 01:25:11.916751 [CA 0] Center 35 (5~66) winsize 62
3968 01:25:11.920220 [CA 1] Center 35 (5~66) winsize 62
3969 01:25:11.923290 [CA 2] Center 34 (3~65) winsize 63
3970 01:25:11.926709 [CA 3] Center 33 (3~64) winsize 62
3971 01:25:11.930769 [CA 4] Center 32 (2~63) winsize 62
3972 01:25:11.933329 [CA 5] Center 32 (2~62) winsize 61
3973 01:25:11.933752
3974 01:25:11.936771 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3975 01:25:11.937258
3976 01:25:11.940345 [CATrainingPosCal] consider 2 rank data
3977 01:25:11.943755 u2DelayCellTimex100 = 270/100 ps
3978 01:25:11.946937 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3979 01:25:11.950907 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3980 01:25:11.956874 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3981 01:25:11.960309 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3982 01:25:11.963636 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3983 01:25:11.966657 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3984 01:25:11.967089
3985 01:25:11.969867 CA PerBit enable=1, Macro0, CA PI delay=32
3986 01:25:11.970379
3987 01:25:11.973072 [CBTSetCACLKResult] CA Dly = 32
3988 01:25:11.973492 CS Dly: 4 (0~36)
3989 01:25:11.976994
3990 01:25:11.980226 ----->DramcWriteLeveling(PI) begin...
3991 01:25:11.980660 ==
3992 01:25:11.983453 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 01:25:11.986642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 01:25:11.987157 ==
3995 01:25:11.990109 Write leveling (Byte 0): 32 => 32
3996 01:25:11.993388 Write leveling (Byte 1): 31 => 31
3997 01:25:11.996800 DramcWriteLeveling(PI) end<-----
3998 01:25:11.997327
3999 01:25:11.997661 ==
4000 01:25:12.000217 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 01:25:12.002768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 01:25:12.003236 ==
4003 01:25:12.006492 [Gating] SW mode calibration
4004 01:25:12.012776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 01:25:12.020059 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 01:25:12.023050 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 01:25:12.026092 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 01:25:12.032778 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 01:25:12.036233 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
4010 01:25:12.039453 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4011 01:25:12.046401 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 01:25:12.049576 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 01:25:12.052516 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 01:25:12.059722 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 01:25:12.062707 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 01:25:12.066163 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4017 01:25:12.072467 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
4018 01:25:12.075940 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4019 01:25:12.079703 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 01:25:12.085805 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 01:25:12.089470 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 01:25:12.092621 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 01:25:12.099162 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 01:25:12.102270 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 01:25:12.105576 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4026 01:25:12.109158 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4027 01:25:12.115537 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 01:25:12.119200 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 01:25:12.122497 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 01:25:12.128850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 01:25:12.132038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 01:25:12.135844 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 01:25:12.142067 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 01:25:12.145867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 01:25:12.148962 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 01:25:12.155715 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 01:25:12.158821 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 01:25:12.162078 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 01:25:12.169432 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 01:25:12.172366 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4041 01:25:12.175989 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4042 01:25:12.182323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4043 01:25:12.182885 Total UI for P1: 0, mck2ui 16
4044 01:25:12.188976 best dqsien dly found for B0: ( 0, 13, 10)
4045 01:25:12.192378 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 01:25:12.196244 Total UI for P1: 0, mck2ui 16
4047 01:25:12.198865 best dqsien dly found for B1: ( 0, 13, 18)
4048 01:25:12.202041 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4049 01:25:12.205464 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4050 01:25:12.205943
4051 01:25:12.208742 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4052 01:25:12.212168 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4053 01:25:12.216004 [Gating] SW calibration Done
4054 01:25:12.216554 ==
4055 01:25:12.219230 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 01:25:12.222031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 01:25:12.225879 ==
4058 01:25:12.226431 RX Vref Scan: 0
4059 01:25:12.226798
4060 01:25:12.228915 RX Vref 0 -> 0, step: 1
4061 01:25:12.229462
4062 01:25:12.232737 RX Delay -230 -> 252, step: 16
4063 01:25:12.235829 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4064 01:25:12.238930 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4065 01:25:12.242458 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4066 01:25:12.245339 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4067 01:25:12.251855 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4068 01:25:12.255794 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4069 01:25:12.258616 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4070 01:25:12.261794 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4071 01:25:12.269322 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4072 01:25:12.271960 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4073 01:25:12.275514 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4074 01:25:12.279063 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4075 01:25:12.281906 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4076 01:25:12.288922 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4077 01:25:12.292281 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4078 01:25:12.295491 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4079 01:25:12.296118 ==
4080 01:25:12.298657 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 01:25:12.305094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 01:25:12.305641 ==
4083 01:25:12.306006 DQS Delay:
4084 01:25:12.306459 DQS0 = 0, DQS1 = 0
4085 01:25:12.308597 DQM Delay:
4086 01:25:12.309056 DQM0 = 49, DQM1 = 44
4087 01:25:12.311741 DQ Delay:
4088 01:25:12.315132 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4089 01:25:12.319178 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4090 01:25:12.319783 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4091 01:25:12.325472 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =57
4092 01:25:12.325931
4093 01:25:12.326292
4094 01:25:12.326626 ==
4095 01:25:12.329059 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 01:25:12.331684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 01:25:12.332145 ==
4098 01:25:12.332508
4099 01:25:12.332843
4100 01:25:12.335135 TX Vref Scan disable
4101 01:25:12.335589 == TX Byte 0 ==
4102 01:25:12.341845 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4103 01:25:12.345172 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4104 01:25:12.345631 == TX Byte 1 ==
4105 01:25:12.352083 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4106 01:25:12.355477 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4107 01:25:12.356086 ==
4108 01:25:12.359104 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 01:25:12.361627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 01:25:12.362090 ==
4111 01:25:12.362454
4112 01:25:12.362789
4113 01:25:12.365697 TX Vref Scan disable
4114 01:25:12.369086 == TX Byte 0 ==
4115 01:25:12.371822 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4116 01:25:12.375510 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4117 01:25:12.378663 == TX Byte 1 ==
4118 01:25:12.382108 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4119 01:25:12.385181 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4120 01:25:12.385639
4121 01:25:12.388465 [DATLAT]
4122 01:25:12.388919 Freq=600, CH0 RK0
4123 01:25:12.389283
4124 01:25:12.392217 DATLAT Default: 0x9
4125 01:25:12.392771 0, 0xFFFF, sum = 0
4126 01:25:12.394996 1, 0xFFFF, sum = 0
4127 01:25:12.395458 2, 0xFFFF, sum = 0
4128 01:25:12.398967 3, 0xFFFF, sum = 0
4129 01:25:12.399521 4, 0xFFFF, sum = 0
4130 01:25:12.402086 5, 0xFFFF, sum = 0
4131 01:25:12.402642 6, 0xFFFF, sum = 0
4132 01:25:12.405295 7, 0xFFFF, sum = 0
4133 01:25:12.405761 8, 0x0, sum = 1
4134 01:25:12.408778 9, 0x0, sum = 2
4135 01:25:12.409245 10, 0x0, sum = 3
4136 01:25:12.412200 11, 0x0, sum = 4
4137 01:25:12.412756 best_step = 9
4138 01:25:12.413116
4139 01:25:12.413463 ==
4140 01:25:12.415650 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 01:25:12.418670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 01:25:12.422093 ==
4143 01:25:12.422710 RX Vref Scan: 1
4144 01:25:12.423235
4145 01:25:12.424973 RX Vref 0 -> 0, step: 1
4146 01:25:12.425559
4147 01:25:12.428145 RX Delay -163 -> 252, step: 8
4148 01:25:12.428609
4149 01:25:12.432095 Set Vref, RX VrefLevel [Byte0]: 54
4150 01:25:12.434924 [Byte1]: 55
4151 01:25:12.435403
4152 01:25:12.438419 Final RX Vref Byte 0 = 54 to rank0
4153 01:25:12.441789 Final RX Vref Byte 1 = 55 to rank0
4154 01:25:12.444856 Final RX Vref Byte 0 = 54 to rank1
4155 01:25:12.448647 Final RX Vref Byte 1 = 55 to rank1==
4156 01:25:12.451823 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 01:25:12.454945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 01:25:12.455459 ==
4159 01:25:12.457997 DQS Delay:
4160 01:25:12.458415 DQS0 = 0, DQS1 = 0
4161 01:25:12.458747 DQM Delay:
4162 01:25:12.461492 DQM0 = 52, DQM1 = 46
4163 01:25:12.461911 DQ Delay:
4164 01:25:12.465206 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4165 01:25:12.468426 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4166 01:25:12.472041 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4167 01:25:12.475685 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4168 01:25:12.476203
4169 01:25:12.476540
4170 01:25:12.485141 [DQSOSCAuto] RK0, (LSB)MR18= 0x7064, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4171 01:25:12.485677 CH0 RK0: MR19=808, MR18=7064
4172 01:25:12.491887 CH0_RK0: MR19=0x808, MR18=0x7064, DQSOSC=388, MR23=63, INC=174, DEC=116
4173 01:25:12.492402
4174 01:25:12.494975 ----->DramcWriteLeveling(PI) begin...
4175 01:25:12.495501 ==
4176 01:25:12.498444 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 01:25:12.505342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 01:25:12.505864 ==
4179 01:25:12.508581 Write leveling (Byte 0): 35 => 35
4180 01:25:12.511882 Write leveling (Byte 1): 31 => 31
4181 01:25:12.512393 DramcWriteLeveling(PI) end<-----
4182 01:25:12.515371
4183 01:25:12.515965 ==
4184 01:25:12.518171 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 01:25:12.521743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 01:25:12.522260 ==
4187 01:25:12.525350 [Gating] SW mode calibration
4188 01:25:12.531511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4189 01:25:12.534535 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4190 01:25:12.541303 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 01:25:12.544824 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 01:25:12.548079 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 01:25:12.554850 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4194 01:25:12.558291 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4195 01:25:12.561399 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 01:25:12.567913 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 01:25:12.571327 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 01:25:12.575069 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 01:25:12.581481 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 01:25:12.584635 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 01:25:12.587962 0 10 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
4202 01:25:12.594532 0 10 16 | B1->B0 | 4242 4141 | 0 1 | (0 0) (0 0)
4203 01:25:12.598240 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 01:25:12.601288 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 01:25:12.608116 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 01:25:12.611484 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 01:25:12.614765 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 01:25:12.621418 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 01:25:12.624255 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4210 01:25:12.628204 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 01:25:12.631200 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 01:25:12.638376 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 01:25:12.641654 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 01:25:12.644386 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 01:25:12.651186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 01:25:12.654866 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 01:25:12.658038 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 01:25:12.664376 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 01:25:12.667978 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 01:25:12.671330 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 01:25:12.677773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 01:25:12.681534 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 01:25:12.684697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 01:25:12.691256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 01:25:12.694867 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4226 01:25:12.698391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 01:25:12.701516 Total UI for P1: 0, mck2ui 16
4228 01:25:12.704513 best dqsien dly found for B0: ( 0, 13, 12)
4229 01:25:12.707964 Total UI for P1: 0, mck2ui 16
4230 01:25:12.711182 best dqsien dly found for B1: ( 0, 13, 14)
4231 01:25:12.715086 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4232 01:25:12.717726 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4233 01:25:12.718183
4234 01:25:12.724579 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4235 01:25:12.727982 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4236 01:25:12.728544 [Gating] SW calibration Done
4237 01:25:12.731009 ==
4238 01:25:12.731558 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 01:25:12.737630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 01:25:12.738197 ==
4241 01:25:12.738562 RX Vref Scan: 0
4242 01:25:12.738966
4243 01:25:12.740922 RX Vref 0 -> 0, step: 1
4244 01:25:12.741380
4245 01:25:12.744334 RX Delay -230 -> 252, step: 16
4246 01:25:12.747545 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4247 01:25:12.750952 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4248 01:25:12.754385 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4249 01:25:12.761059 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4250 01:25:12.764447 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4251 01:25:12.768068 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4252 01:25:12.770863 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4253 01:25:12.774009 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4254 01:25:12.780655 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4255 01:25:12.784373 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4256 01:25:12.787429 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4257 01:25:12.790649 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4258 01:25:12.797148 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4259 01:25:12.800605 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4260 01:25:12.804113 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4261 01:25:12.807415 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4262 01:25:12.807883 ==
4263 01:25:12.810817 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 01:25:12.817163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 01:25:12.817512 ==
4266 01:25:12.817761 DQS Delay:
4267 01:25:12.820426 DQS0 = 0, DQS1 = 0
4268 01:25:12.820716 DQM Delay:
4269 01:25:12.820948 DQM0 = 58, DQM1 = 46
4270 01:25:12.823722 DQ Delay:
4271 01:25:12.826773 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4272 01:25:12.830314 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4273 01:25:12.833551 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4274 01:25:12.837020 DQ12 =57, DQ13 =57, DQ14 =65, DQ15 =57
4275 01:25:12.837149
4276 01:25:12.837251
4277 01:25:12.837343 ==
4278 01:25:12.839984 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 01:25:12.843643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 01:25:12.843757 ==
4281 01:25:12.843847
4282 01:25:12.843929
4283 01:25:12.847198 TX Vref Scan disable
4284 01:25:12.850542 == TX Byte 0 ==
4285 01:25:12.853450 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4286 01:25:12.856596 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4287 01:25:12.860156 == TX Byte 1 ==
4288 01:25:12.863232 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4289 01:25:12.866645 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4290 01:25:12.866731 ==
4291 01:25:12.870367 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 01:25:12.873362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 01:25:12.873473 ==
4294 01:25:12.876911
4295 01:25:12.876995
4296 01:25:12.877059 TX Vref Scan disable
4297 01:25:12.880029 == TX Byte 0 ==
4298 01:25:12.883537 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4299 01:25:12.890036 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4300 01:25:12.890130 == TX Byte 1 ==
4301 01:25:12.893994 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4302 01:25:12.900288 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4303 01:25:12.900387
4304 01:25:12.900453 [DATLAT]
4305 01:25:12.900513 Freq=600, CH0 RK1
4306 01:25:12.900572
4307 01:25:12.903372 DATLAT Default: 0x9
4308 01:25:12.903457 0, 0xFFFF, sum = 0
4309 01:25:12.906846 1, 0xFFFF, sum = 0
4310 01:25:12.906948 2, 0xFFFF, sum = 0
4311 01:25:12.910440 3, 0xFFFF, sum = 0
4312 01:25:12.910548 4, 0xFFFF, sum = 0
4313 01:25:12.913331 5, 0xFFFF, sum = 0
4314 01:25:12.917508 6, 0xFFFF, sum = 0
4315 01:25:12.917628 7, 0xFFFF, sum = 0
4316 01:25:12.917694 8, 0x0, sum = 1
4317 01:25:12.920151 9, 0x0, sum = 2
4318 01:25:12.920236 10, 0x0, sum = 3
4319 01:25:12.923633 11, 0x0, sum = 4
4320 01:25:12.923731 best_step = 9
4321 01:25:12.923797
4322 01:25:12.923857 ==
4323 01:25:12.927069 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 01:25:12.933559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 01:25:12.933680 ==
4326 01:25:12.933746 RX Vref Scan: 0
4327 01:25:12.933805
4328 01:25:12.936838 RX Vref 0 -> 0, step: 1
4329 01:25:12.936923
4330 01:25:12.940489 RX Delay -179 -> 252, step: 8
4331 01:25:12.943462 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4332 01:25:12.950321 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4333 01:25:12.953738 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4334 01:25:12.956985 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4335 01:25:12.960382 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4336 01:25:12.963601 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4337 01:25:12.966852 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4338 01:25:12.973596 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4339 01:25:12.976748 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4340 01:25:12.980443 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4341 01:25:12.983573 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4342 01:25:12.990408 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4343 01:25:12.993191 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4344 01:25:12.996514 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4345 01:25:13.000231 iDelay=197, Bit 14, Center 52 (-91 ~ 196) 288
4346 01:25:13.003437 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4347 01:25:13.006528 ==
4348 01:25:13.006652 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 01:25:13.013420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 01:25:13.013612 ==
4351 01:25:13.013730 DQS Delay:
4352 01:25:13.016918 DQS0 = 0, DQS1 = 0
4353 01:25:13.017010 DQM Delay:
4354 01:25:13.020315 DQM0 = 54, DQM1 = 45
4355 01:25:13.020409 DQ Delay:
4356 01:25:13.023296 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4357 01:25:13.026368 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4358 01:25:13.030090 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4359 01:25:13.033569 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4360 01:25:13.033667
4361 01:25:13.033730
4362 01:25:13.040102 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4363 01:25:13.043560 CH0 RK1: MR19=808, MR18=6323
4364 01:25:13.049828 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4365 01:25:13.053316 [RxdqsGatingPostProcess] freq 600
4366 01:25:13.059921 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4367 01:25:13.060102 Pre-setting of DQS Precalculation
4368 01:25:13.066343 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4369 01:25:13.066453 ==
4370 01:25:13.070073 Dram Type= 6, Freq= 0, CH_1, rank 0
4371 01:25:13.073412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 01:25:13.073550 ==
4373 01:25:13.079488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4374 01:25:13.086393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4375 01:25:13.089960 [CA 0] Center 35 (5~66) winsize 62
4376 01:25:13.092886 [CA 1] Center 36 (5~67) winsize 63
4377 01:25:13.096137 [CA 2] Center 34 (4~65) winsize 62
4378 01:25:13.099945 [CA 3] Center 34 (3~65) winsize 63
4379 01:25:13.103155 [CA 4] Center 34 (4~65) winsize 62
4380 01:25:13.106763 [CA 5] Center 33 (3~64) winsize 62
4381 01:25:13.106875
4382 01:25:13.109455 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4383 01:25:13.109542
4384 01:25:13.112957 [CATrainingPosCal] consider 1 rank data
4385 01:25:13.116418 u2DelayCellTimex100 = 270/100 ps
4386 01:25:13.119792 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4387 01:25:13.122976 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4388 01:25:13.126293 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 01:25:13.129713 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4390 01:25:13.133107 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 01:25:13.136364 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4392 01:25:13.136446
4393 01:25:13.142973 CA PerBit enable=1, Macro0, CA PI delay=33
4394 01:25:13.143097
4395 01:25:13.143165 [CBTSetCACLKResult] CA Dly = 33
4396 01:25:13.146332 CS Dly: 6 (0~37)
4397 01:25:13.146413 ==
4398 01:25:13.149641 Dram Type= 6, Freq= 0, CH_1, rank 1
4399 01:25:13.152983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 01:25:13.153071 ==
4401 01:25:13.159524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4402 01:25:13.166332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4403 01:25:13.169491 [CA 0] Center 36 (5~67) winsize 63
4404 01:25:13.172691 [CA 1] Center 36 (5~67) winsize 63
4405 01:25:13.175817 [CA 2] Center 34 (4~65) winsize 62
4406 01:25:13.179240 [CA 3] Center 34 (4~65) winsize 62
4407 01:25:13.182543 [CA 4] Center 35 (4~66) winsize 63
4408 01:25:13.186090 [CA 5] Center 34 (4~65) winsize 62
4409 01:25:13.186182
4410 01:25:13.189467 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4411 01:25:13.189554
4412 01:25:13.192932 [CATrainingPosCal] consider 2 rank data
4413 01:25:13.196265 u2DelayCellTimex100 = 270/100 ps
4414 01:25:13.199695 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4415 01:25:13.202715 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4416 01:25:13.206147 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4417 01:25:13.209426 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 01:25:13.212662 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 01:25:13.216081 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4420 01:25:13.219033
4421 01:25:13.222411 CA PerBit enable=1, Macro0, CA PI delay=34
4422 01:25:13.222493
4423 01:25:13.225990 [CBTSetCACLKResult] CA Dly = 34
4424 01:25:13.226073 CS Dly: 6 (0~38)
4425 01:25:13.226137
4426 01:25:13.229177 ----->DramcWriteLeveling(PI) begin...
4427 01:25:13.229260 ==
4428 01:25:13.232243 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 01:25:13.235894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 01:25:13.239115 ==
4431 01:25:13.239205 Write leveling (Byte 0): 31 => 31
4432 01:25:13.242504 Write leveling (Byte 1): 31 => 31
4433 01:25:13.245873 DramcWriteLeveling(PI) end<-----
4434 01:25:13.245955
4435 01:25:13.246018 ==
4436 01:25:13.248913 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 01:25:13.255870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 01:25:13.255963 ==
4439 01:25:13.256027 [Gating] SW mode calibration
4440 01:25:13.265604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4441 01:25:13.269063 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4442 01:25:13.272373 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 01:25:13.279314 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 01:25:13.282491 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4445 01:25:13.285779 0 9 12 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (1 1)
4446 01:25:13.292536 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4447 01:25:13.295895 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 01:25:13.299256 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 01:25:13.305612 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 01:25:13.308927 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 01:25:13.312689 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 01:25:13.318949 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4453 01:25:13.322144 0 10 12 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
4454 01:25:13.325572 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 01:25:13.332394 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 01:25:13.335361 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 01:25:13.338606 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 01:25:13.345270 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 01:25:13.348621 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 01:25:13.352085 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 01:25:13.358723 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4462 01:25:13.362281 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 01:25:13.365322 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 01:25:13.372175 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 01:25:13.375311 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 01:25:13.378483 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 01:25:13.385500 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 01:25:13.388672 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 01:25:13.392166 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 01:25:13.398669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 01:25:13.401830 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 01:25:13.405375 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 01:25:13.412022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 01:25:13.414822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 01:25:13.418515 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 01:25:13.421706 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4477 01:25:13.428776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4478 01:25:13.431924 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 01:25:13.435277 Total UI for P1: 0, mck2ui 16
4480 01:25:13.438536 best dqsien dly found for B0: ( 0, 13, 10)
4481 01:25:13.441622 Total UI for P1: 0, mck2ui 16
4482 01:25:13.445171 best dqsien dly found for B1: ( 0, 13, 12)
4483 01:25:13.448709 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4484 01:25:13.452140 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4485 01:25:13.452234
4486 01:25:13.455154 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4487 01:25:13.458252 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4488 01:25:13.461566 [Gating] SW calibration Done
4489 01:25:13.461649 ==
4490 01:25:13.464957 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 01:25:13.471568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 01:25:13.471704 ==
4493 01:25:13.471814 RX Vref Scan: 0
4494 01:25:13.471921
4495 01:25:13.475572 RX Vref 0 -> 0, step: 1
4496 01:25:13.475664
4497 01:25:13.478605 RX Delay -230 -> 252, step: 16
4498 01:25:13.481523 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4499 01:25:13.484910 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4500 01:25:13.488371 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4501 01:25:13.495321 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4502 01:25:13.498498 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4503 01:25:13.502271 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4504 01:25:13.505193 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4505 01:25:13.508534 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4506 01:25:13.515370 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4507 01:25:13.518624 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4508 01:25:13.522159 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4509 01:25:13.525141 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4510 01:25:13.531744 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4511 01:25:13.535522 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4512 01:25:13.538225 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4513 01:25:13.541570 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4514 01:25:13.541651 ==
4515 01:25:13.545254 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 01:25:13.548366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 01:25:13.551807 ==
4518 01:25:13.551900 DQS Delay:
4519 01:25:13.551965 DQS0 = 0, DQS1 = 0
4520 01:25:13.555159 DQM Delay:
4521 01:25:13.555238 DQM0 = 52, DQM1 = 50
4522 01:25:13.558527 DQ Delay:
4523 01:25:13.558608 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4524 01:25:13.561925 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4525 01:25:13.565388 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4526 01:25:13.569005 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4527 01:25:13.571581
4528 01:25:13.571737
4529 01:25:13.571810 ==
4530 01:25:13.574944 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 01:25:13.578575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 01:25:13.578733 ==
4533 01:25:13.578823
4534 01:25:13.578890
4535 01:25:13.581591 TX Vref Scan disable
4536 01:25:13.581753 == TX Byte 0 ==
4537 01:25:13.588423 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4538 01:25:13.591732 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4539 01:25:13.591899 == TX Byte 1 ==
4540 01:25:13.598317 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4541 01:25:13.602452 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4542 01:25:13.602632 ==
4543 01:25:13.604728 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 01:25:13.608543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 01:25:13.608767 ==
4546 01:25:13.608889
4547 01:25:13.609008
4548 01:25:13.611647 TX Vref Scan disable
4549 01:25:13.614669 == TX Byte 0 ==
4550 01:25:13.617693 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4551 01:25:13.622075 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4552 01:25:13.625141 == TX Byte 1 ==
4553 01:25:13.627998 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4554 01:25:13.631450 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4555 01:25:13.634621
4556 01:25:13.634905 [DATLAT]
4557 01:25:13.635073 Freq=600, CH1 RK0
4558 01:25:13.635233
4559 01:25:13.638004 DATLAT Default: 0x9
4560 01:25:13.638241 0, 0xFFFF, sum = 0
4561 01:25:13.641493 1, 0xFFFF, sum = 0
4562 01:25:13.641792 2, 0xFFFF, sum = 0
4563 01:25:13.644800 3, 0xFFFF, sum = 0
4564 01:25:13.648288 4, 0xFFFF, sum = 0
4565 01:25:13.648830 5, 0xFFFF, sum = 0
4566 01:25:13.652017 6, 0xFFFF, sum = 0
4567 01:25:13.652439 7, 0xFFFF, sum = 0
4568 01:25:13.652773 8, 0x0, sum = 1
4569 01:25:13.655100 9, 0x0, sum = 2
4570 01:25:13.655669 10, 0x0, sum = 3
4571 01:25:13.658077 11, 0x0, sum = 4
4572 01:25:13.658501 best_step = 9
4573 01:25:13.658828
4574 01:25:13.659133 ==
4575 01:25:13.661874 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 01:25:13.668731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 01:25:13.669246 ==
4578 01:25:13.669577 RX Vref Scan: 1
4579 01:25:13.669886
4580 01:25:13.672155 RX Vref 0 -> 0, step: 1
4581 01:25:13.672672
4582 01:25:13.675087 RX Delay -163 -> 252, step: 8
4583 01:25:13.675664
4584 01:25:13.678357 Set Vref, RX VrefLevel [Byte0]: 53
4585 01:25:13.682168 [Byte1]: 49
4586 01:25:13.682685
4587 01:25:13.685025 Final RX Vref Byte 0 = 53 to rank0
4588 01:25:13.688170 Final RX Vref Byte 1 = 49 to rank0
4589 01:25:13.691738 Final RX Vref Byte 0 = 53 to rank1
4590 01:25:13.695122 Final RX Vref Byte 1 = 49 to rank1==
4591 01:25:13.698677 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 01:25:13.702412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 01:25:13.702929 ==
4594 01:25:13.705041 DQS Delay:
4595 01:25:13.705557 DQS0 = 0, DQS1 = 0
4596 01:25:13.705889 DQM Delay:
4597 01:25:13.708230 DQM0 = 48, DQM1 = 45
4598 01:25:13.708663 DQ Delay:
4599 01:25:13.711942 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4600 01:25:13.715515 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4601 01:25:13.718981 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4602 01:25:13.721977 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4603 01:25:13.722495
4604 01:25:13.722829
4605 01:25:13.731335 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4606 01:25:13.731797 CH1 RK0: MR19=808, MR18=4D72
4607 01:25:13.738403 CH1_RK0: MR19=0x808, MR18=0x4D72, DQSOSC=388, MR23=63, INC=174, DEC=116
4608 01:25:13.738925
4609 01:25:13.741281 ----->DramcWriteLeveling(PI) begin...
4610 01:25:13.744424 ==
4611 01:25:13.744836 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 01:25:13.751293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 01:25:13.751879 ==
4614 01:25:13.755125 Write leveling (Byte 0): 29 => 29
4615 01:25:13.758189 Write leveling (Byte 1): 32 => 32
4616 01:25:13.761626 DramcWriteLeveling(PI) end<-----
4617 01:25:13.762139
4618 01:25:13.762468 ==
4619 01:25:13.764301 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 01:25:13.767661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 01:25:13.768083 ==
4622 01:25:13.772025 [Gating] SW mode calibration
4623 01:25:13.778219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4624 01:25:13.781477 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4625 01:25:13.787995 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 01:25:13.791347 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 01:25:13.794794 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4628 01:25:13.800878 0 9 12 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (1 0)
4629 01:25:13.804511 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4630 01:25:13.808007 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 01:25:13.814780 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 01:25:13.817643 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 01:25:13.820947 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 01:25:13.827826 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 01:25:13.830993 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 01:25:13.834388 0 10 12 | B1->B0 | 3838 3636 | 0 0 | (1 1) (0 0)
4637 01:25:13.840788 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 01:25:13.843860 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 01:25:13.847223 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 01:25:13.853626 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 01:25:13.857202 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 01:25:13.860530 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 01:25:13.867062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 01:25:13.870635 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 01:25:13.873713 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 01:25:13.880590 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 01:25:13.884045 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 01:25:13.887588 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 01:25:13.894072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 01:25:13.897044 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 01:25:13.900600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 01:25:13.907005 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 01:25:13.910259 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 01:25:13.913765 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 01:25:13.920462 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 01:25:13.924064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 01:25:13.927359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 01:25:13.933660 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 01:25:13.937194 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4660 01:25:13.940254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4661 01:25:13.946664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 01:25:13.947081 Total UI for P1: 0, mck2ui 16
4663 01:25:13.950118 best dqsien dly found for B0: ( 0, 13, 14)
4664 01:25:13.953331 Total UI for P1: 0, mck2ui 16
4665 01:25:13.956984 best dqsien dly found for B1: ( 0, 13, 10)
4666 01:25:13.963540 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4667 01:25:13.967129 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4668 01:25:13.967542
4669 01:25:13.970273 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4670 01:25:13.973397 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4671 01:25:13.976655 [Gating] SW calibration Done
4672 01:25:13.977072 ==
4673 01:25:13.980217 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 01:25:13.983682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 01:25:13.984183 ==
4676 01:25:13.986974 RX Vref Scan: 0
4677 01:25:13.987488
4678 01:25:13.988042 RX Vref 0 -> 0, step: 1
4679 01:25:13.988463
4680 01:25:13.990296 RX Delay -230 -> 252, step: 16
4681 01:25:13.993304 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4682 01:25:13.999928 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4683 01:25:14.003663 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4684 01:25:14.006549 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4685 01:25:14.010081 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4686 01:25:14.013689 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4687 01:25:14.020195 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4688 01:25:14.023304 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4689 01:25:14.027156 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4690 01:25:14.030007 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4691 01:25:14.036840 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4692 01:25:14.040085 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4693 01:25:14.043816 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4694 01:25:14.046563 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4695 01:25:14.053167 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4696 01:25:14.056820 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4697 01:25:14.057336 ==
4698 01:25:14.059905 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 01:25:14.063529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 01:25:14.064146 ==
4701 01:25:14.066843 DQS Delay:
4702 01:25:14.067475 DQS0 = 0, DQS1 = 0
4703 01:25:14.067953 DQM Delay:
4704 01:25:14.069779 DQM0 = 49, DQM1 = 48
4705 01:25:14.070357 DQ Delay:
4706 01:25:14.072954 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4707 01:25:14.076667 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4708 01:25:14.079573 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4709 01:25:14.083684 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4710 01:25:14.084153
4711 01:25:14.084524
4712 01:25:14.084869 ==
4713 01:25:14.086547 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 01:25:14.093149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 01:25:14.093751 ==
4716 01:25:14.094363
4717 01:25:14.094908
4718 01:25:14.095451 TX Vref Scan disable
4719 01:25:14.096825 == TX Byte 0 ==
4720 01:25:14.100141 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 01:25:14.103118 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 01:25:14.106773 == TX Byte 1 ==
4723 01:25:14.109705 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 01:25:14.113037 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 01:25:14.116674 ==
4726 01:25:14.119927 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 01:25:14.122980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 01:25:14.123646 ==
4729 01:25:14.124117
4730 01:25:14.124536
4731 01:25:14.126502 TX Vref Scan disable
4732 01:25:14.129781 == TX Byte 0 ==
4733 01:25:14.133227 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 01:25:14.136374 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 01:25:14.139673 == TX Byte 1 ==
4736 01:25:14.143096 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4737 01:25:14.146191 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4738 01:25:14.146681
4739 01:25:14.147072 [DATLAT]
4740 01:25:14.149894 Freq=600, CH1 RK1
4741 01:25:14.150291
4742 01:25:14.150647 DATLAT Default: 0x9
4743 01:25:14.153163 0, 0xFFFF, sum = 0
4744 01:25:14.153669 1, 0xFFFF, sum = 0
4745 01:25:14.156535 2, 0xFFFF, sum = 0
4746 01:25:14.159704 3, 0xFFFF, sum = 0
4747 01:25:14.160170 4, 0xFFFF, sum = 0
4748 01:25:14.162756 5, 0xFFFF, sum = 0
4749 01:25:14.163175 6, 0xFFFF, sum = 0
4750 01:25:14.166001 7, 0xFFFF, sum = 0
4751 01:25:14.166413 8, 0x0, sum = 1
4752 01:25:14.166790 9, 0x0, sum = 2
4753 01:25:14.169745 10, 0x0, sum = 3
4754 01:25:14.170261 11, 0x0, sum = 4
4755 01:25:14.172916 best_step = 9
4756 01:25:14.173409
4757 01:25:14.173779 ==
4758 01:25:14.176299 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 01:25:14.179829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 01:25:14.180334 ==
4761 01:25:14.182579 RX Vref Scan: 0
4762 01:25:14.183037
4763 01:25:14.183437 RX Vref 0 -> 0, step: 1
4764 01:25:14.183880
4765 01:25:14.186015 RX Delay -163 -> 252, step: 8
4766 01:25:14.193252 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4767 01:25:14.196505 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4768 01:25:14.200387 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4769 01:25:14.203095 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4770 01:25:14.206216 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4771 01:25:14.212817 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4772 01:25:14.216003 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4773 01:25:14.219814 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4774 01:25:14.222937 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4775 01:25:14.229682 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4776 01:25:14.232627 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4777 01:25:14.236444 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4778 01:25:14.239669 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4779 01:25:14.242891 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4780 01:25:14.249268 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4781 01:25:14.252885 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4782 01:25:14.252965 ==
4783 01:25:14.256072 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 01:25:14.259346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 01:25:14.259427 ==
4786 01:25:14.262967 DQS Delay:
4787 01:25:14.263038 DQS0 = 0, DQS1 = 0
4788 01:25:14.263098 DQM Delay:
4789 01:25:14.266218 DQM0 = 49, DQM1 = 44
4790 01:25:14.266288 DQ Delay:
4791 01:25:14.269498 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4792 01:25:14.272784 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4793 01:25:14.276394 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4794 01:25:14.279372 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4795 01:25:14.279452
4796 01:25:14.279521
4797 01:25:14.289828 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4798 01:25:14.289902 CH1 RK1: MR19=808, MR18=6C22
4799 01:25:14.296000 CH1_RK1: MR19=0x808, MR18=0x6C22, DQSOSC=389, MR23=63, INC=173, DEC=115
4800 01:25:14.299425 [RxdqsGatingPostProcess] freq 600
4801 01:25:14.306574 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 01:25:14.309452 Pre-setting of DQS Precalculation
4803 01:25:14.312759 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 01:25:14.319467 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 01:25:14.329449 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 01:25:14.329590
4807 01:25:14.329677
4808 01:25:14.329757 [Calibration Summary] 1200 Mbps
4809 01:25:14.332892 CH 0, Rank 0
4810 01:25:14.332978 SW Impedance : PASS
4811 01:25:14.336431 DUTY Scan : NO K
4812 01:25:14.339682 ZQ Calibration : PASS
4813 01:25:14.339810 Jitter Meter : NO K
4814 01:25:14.342853 CBT Training : PASS
4815 01:25:14.346431 Write leveling : PASS
4816 01:25:14.346531 RX DQS gating : PASS
4817 01:25:14.349269 RX DQ/DQS(RDDQC) : PASS
4818 01:25:14.352911 TX DQ/DQS : PASS
4819 01:25:14.352997 RX DATLAT : PASS
4820 01:25:14.356090 RX DQ/DQS(Engine): PASS
4821 01:25:14.359615 TX OE : NO K
4822 01:25:14.359701 All Pass.
4823 01:25:14.359789
4824 01:25:14.359871 CH 0, Rank 1
4825 01:25:14.362886 SW Impedance : PASS
4826 01:25:14.365955 DUTY Scan : NO K
4827 01:25:14.366039 ZQ Calibration : PASS
4828 01:25:14.369710 Jitter Meter : NO K
4829 01:25:14.372468 CBT Training : PASS
4830 01:25:14.372567 Write leveling : PASS
4831 01:25:14.376144 RX DQS gating : PASS
4832 01:25:14.379299 RX DQ/DQS(RDDQC) : PASS
4833 01:25:14.379385 TX DQ/DQS : PASS
4834 01:25:14.382437 RX DATLAT : PASS
4835 01:25:14.385612 RX DQ/DQS(Engine): PASS
4836 01:25:14.385696 TX OE : NO K
4837 01:25:14.385761 All Pass.
4838 01:25:14.385854
4839 01:25:14.389626 CH 1, Rank 0
4840 01:25:14.389698 SW Impedance : PASS
4841 01:25:14.392373 DUTY Scan : NO K
4842 01:25:14.395967 ZQ Calibration : PASS
4843 01:25:14.396077 Jitter Meter : NO K
4844 01:25:14.399532 CBT Training : PASS
4845 01:25:14.402254 Write leveling : PASS
4846 01:25:14.402329 RX DQS gating : PASS
4847 01:25:14.405595 RX DQ/DQS(RDDQC) : PASS
4848 01:25:14.408927 TX DQ/DQS : PASS
4849 01:25:14.409000 RX DATLAT : PASS
4850 01:25:14.412378 RX DQ/DQS(Engine): PASS
4851 01:25:14.415974 TX OE : NO K
4852 01:25:14.416057 All Pass.
4853 01:25:14.416128
4854 01:25:14.416188 CH 1, Rank 1
4855 01:25:14.419003 SW Impedance : PASS
4856 01:25:14.422397 DUTY Scan : NO K
4857 01:25:14.422473 ZQ Calibration : PASS
4858 01:25:14.425763 Jitter Meter : NO K
4859 01:25:14.428780 CBT Training : PASS
4860 01:25:14.428855 Write leveling : PASS
4861 01:25:14.432152 RX DQS gating : PASS
4862 01:25:14.436012 RX DQ/DQS(RDDQC) : PASS
4863 01:25:14.436089 TX DQ/DQS : PASS
4864 01:25:14.438819 RX DATLAT : PASS
4865 01:25:14.438889 RX DQ/DQS(Engine): PASS
4866 01:25:14.442281 TX OE : NO K
4867 01:25:14.442369 All Pass.
4868 01:25:14.442456
4869 01:25:14.445527 DramC Write-DBI off
4870 01:25:14.449185 PER_BANK_REFRESH: Hybrid Mode
4871 01:25:14.449271 TX_TRACKING: ON
4872 01:25:14.459100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 01:25:14.462236 [FAST_K] Save calibration result to emmc
4874 01:25:14.465639 dramc_set_vcore_voltage set vcore to 662500
4875 01:25:14.469253 Read voltage for 933, 3
4876 01:25:14.469339 Vio18 = 0
4877 01:25:14.469426 Vcore = 662500
4878 01:25:14.472170 Vdram = 0
4879 01:25:14.472255 Vddq = 0
4880 01:25:14.472342 Vmddr = 0
4881 01:25:14.479194 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 01:25:14.482344 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 01:25:14.485458 MEM_TYPE=3, freq_sel=17
4884 01:25:14.489306 sv_algorithm_assistance_LP4_1600
4885 01:25:14.492638 ============ PULL DRAM RESETB DOWN ============
4886 01:25:14.495759 ========== PULL DRAM RESETB DOWN end =========
4887 01:25:14.502600 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 01:25:14.506204 ===================================
4889 01:25:14.508852 LPDDR4 DRAM CONFIGURATION
4890 01:25:14.512455 ===================================
4891 01:25:14.512539 EX_ROW_EN[0] = 0x0
4892 01:25:14.515412 EX_ROW_EN[1] = 0x0
4893 01:25:14.515524 LP4Y_EN = 0x0
4894 01:25:14.519273 WORK_FSP = 0x0
4895 01:25:14.519363 WL = 0x3
4896 01:25:14.522241 RL = 0x3
4897 01:25:14.522316 BL = 0x2
4898 01:25:14.525587 RPST = 0x0
4899 01:25:14.525666 RD_PRE = 0x0
4900 01:25:14.528836 WR_PRE = 0x1
4901 01:25:14.528915 WR_PST = 0x0
4902 01:25:14.532196 DBI_WR = 0x0
4903 01:25:14.532280 DBI_RD = 0x0
4904 01:25:14.535902 OTF = 0x1
4905 01:25:14.538981 ===================================
4906 01:25:14.542481 ===================================
4907 01:25:14.542565 ANA top config
4908 01:25:14.545677 ===================================
4909 01:25:14.548838 DLL_ASYNC_EN = 0
4910 01:25:14.552108 ALL_SLAVE_EN = 1
4911 01:25:14.555331 NEW_RANK_MODE = 1
4912 01:25:14.555414 DLL_IDLE_MODE = 1
4913 01:25:14.558652 LP45_APHY_COMB_EN = 1
4914 01:25:14.562101 TX_ODT_DIS = 1
4915 01:25:14.565474 NEW_8X_MODE = 1
4916 01:25:14.568629 ===================================
4917 01:25:14.572689 ===================================
4918 01:25:14.575348 data_rate = 1866
4919 01:25:14.575417 CKR = 1
4920 01:25:14.578719 DQ_P2S_RATIO = 8
4921 01:25:14.582173 ===================================
4922 01:25:14.585121 CA_P2S_RATIO = 8
4923 01:25:14.589027 DQ_CA_OPEN = 0
4924 01:25:14.592287 DQ_SEMI_OPEN = 0
4925 01:25:14.595315 CA_SEMI_OPEN = 0
4926 01:25:14.595395 CA_FULL_RATE = 0
4927 01:25:14.598559 DQ_CKDIV4_EN = 1
4928 01:25:14.601826 CA_CKDIV4_EN = 1
4929 01:25:14.605114 CA_PREDIV_EN = 0
4930 01:25:14.608671 PH8_DLY = 0
4931 01:25:14.612002 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 01:25:14.612075 DQ_AAMCK_DIV = 4
4933 01:25:14.614998 CA_AAMCK_DIV = 4
4934 01:25:14.618491 CA_ADMCK_DIV = 4
4935 01:25:14.621934 DQ_TRACK_CA_EN = 0
4936 01:25:14.625150 CA_PICK = 933
4937 01:25:14.628194 CA_MCKIO = 933
4938 01:25:14.631866 MCKIO_SEMI = 0
4939 01:25:14.631949 PLL_FREQ = 3732
4940 01:25:14.635466 DQ_UI_PI_RATIO = 32
4941 01:25:14.638148 CA_UI_PI_RATIO = 0
4942 01:25:14.641716 ===================================
4943 01:25:14.645091 ===================================
4944 01:25:14.648057 memory_type:LPDDR4
4945 01:25:14.648130 GP_NUM : 10
4946 01:25:14.651727 SRAM_EN : 1
4947 01:25:14.655052 MD32_EN : 0
4948 01:25:14.658376 ===================================
4949 01:25:14.658459 [ANA_INIT] >>>>>>>>>>>>>>
4950 01:25:14.661552 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 01:25:14.664820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 01:25:14.668223 ===================================
4953 01:25:14.671744 data_rate = 1866,PCW = 0X8f00
4954 01:25:14.675213 ===================================
4955 01:25:14.678151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 01:25:14.684721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 01:25:14.688421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 01:25:14.694774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 01:25:14.698037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 01:25:14.701802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 01:25:14.705005 [ANA_INIT] flow start
4962 01:25:14.705086 [ANA_INIT] PLL >>>>>>>>
4963 01:25:14.708299 [ANA_INIT] PLL <<<<<<<<
4964 01:25:14.711390 [ANA_INIT] MIDPI >>>>>>>>
4965 01:25:14.711471 [ANA_INIT] MIDPI <<<<<<<<
4966 01:25:14.714686 [ANA_INIT] DLL >>>>>>>>
4967 01:25:14.718346 [ANA_INIT] flow end
4968 01:25:14.721355 ============ LP4 DIFF to SE enter ============
4969 01:25:14.724706 ============ LP4 DIFF to SE exit ============
4970 01:25:14.727786 [ANA_INIT] <<<<<<<<<<<<<
4971 01:25:14.731832 [Flow] Enable top DCM control >>>>>
4972 01:25:14.734352 [Flow] Enable top DCM control <<<<<
4973 01:25:14.738191 Enable DLL master slave shuffle
4974 01:25:14.741332 ==============================================================
4975 01:25:14.744461 Gating Mode config
4976 01:25:14.751470 ==============================================================
4977 01:25:14.751547 Config description:
4978 01:25:14.761895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 01:25:14.768020 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 01:25:14.771246 SELPH_MODE 0: By rank 1: By Phase
4981 01:25:14.778260 ==============================================================
4982 01:25:14.781204 GAT_TRACK_EN = 1
4983 01:25:14.784553 RX_GATING_MODE = 2
4984 01:25:14.787990 RX_GATING_TRACK_MODE = 2
4985 01:25:14.791523 SELPH_MODE = 1
4986 01:25:14.794715 PICG_EARLY_EN = 1
4987 01:25:14.794787 VALID_LAT_VALUE = 1
4988 01:25:14.801030 ==============================================================
4989 01:25:14.805023 Enter into Gating configuration >>>>
4990 01:25:14.808193 Exit from Gating configuration <<<<
4991 01:25:14.811490 Enter into DVFS_PRE_config >>>>>
4992 01:25:14.821572 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 01:25:14.824708 Exit from DVFS_PRE_config <<<<<
4994 01:25:14.828194 Enter into PICG configuration >>>>
4995 01:25:14.831075 Exit from PICG configuration <<<<
4996 01:25:14.834472 [RX_INPUT] configuration >>>>>
4997 01:25:14.838038 [RX_INPUT] configuration <<<<<
4998 01:25:14.841227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 01:25:14.847822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 01:25:14.854747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 01:25:14.860865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 01:25:14.868000 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 01:25:14.874280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 01:25:14.877457 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 01:25:14.881137 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 01:25:14.884397 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 01:25:14.888170 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 01:25:14.894397 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 01:25:14.897621 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 01:25:14.901061 ===================================
5011 01:25:14.904419 LPDDR4 DRAM CONFIGURATION
5012 01:25:14.907881 ===================================
5013 01:25:14.907964 EX_ROW_EN[0] = 0x0
5014 01:25:14.911236 EX_ROW_EN[1] = 0x0
5015 01:25:14.911318 LP4Y_EN = 0x0
5016 01:25:14.914616 WORK_FSP = 0x0
5017 01:25:14.914735 WL = 0x3
5018 01:25:14.917787 RL = 0x3
5019 01:25:14.917872 BL = 0x2
5020 01:25:14.920738 RPST = 0x0
5021 01:25:14.920829 RD_PRE = 0x0
5022 01:25:14.924438 WR_PRE = 0x1
5023 01:25:14.927488 WR_PST = 0x0
5024 01:25:14.927567 DBI_WR = 0x0
5025 01:25:14.931055 DBI_RD = 0x0
5026 01:25:14.931142 OTF = 0x1
5027 01:25:14.934494 ===================================
5028 01:25:14.937876 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 01:25:14.941227 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 01:25:14.947733 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 01:25:14.950946 ===================================
5032 01:25:14.954550 LPDDR4 DRAM CONFIGURATION
5033 01:25:14.957544 ===================================
5034 01:25:14.957651 EX_ROW_EN[0] = 0x10
5035 01:25:14.960862 EX_ROW_EN[1] = 0x0
5036 01:25:14.960944 LP4Y_EN = 0x0
5037 01:25:14.964366 WORK_FSP = 0x0
5038 01:25:14.964436 WL = 0x3
5039 01:25:14.967611 RL = 0x3
5040 01:25:14.967726 BL = 0x2
5041 01:25:14.971196 RPST = 0x0
5042 01:25:14.971274 RD_PRE = 0x0
5043 01:25:14.974587 WR_PRE = 0x1
5044 01:25:14.974661 WR_PST = 0x0
5045 01:25:14.977515 DBI_WR = 0x0
5046 01:25:14.977586 DBI_RD = 0x0
5047 01:25:14.980936 OTF = 0x1
5048 01:25:14.983999 ===================================
5049 01:25:14.990864 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 01:25:14.993912 nWR fixed to 30
5051 01:25:14.997553 [ModeRegInit_LP4] CH0 RK0
5052 01:25:14.997664 [ModeRegInit_LP4] CH0 RK1
5053 01:25:15.001109 [ModeRegInit_LP4] CH1 RK0
5054 01:25:15.004232 [ModeRegInit_LP4] CH1 RK1
5055 01:25:15.004325 match AC timing 9
5056 01:25:15.010778 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 01:25:15.014164 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 01:25:15.017643 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 01:25:15.024196 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 01:25:15.027085 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 01:25:15.027166 ==
5062 01:25:15.030797 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 01:25:15.033884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 01:25:15.033957 ==
5065 01:25:15.040467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 01:25:15.047215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5067 01:25:15.050588 [CA 0] Center 37 (6~68) winsize 63
5068 01:25:15.053932 [CA 1] Center 37 (6~68) winsize 63
5069 01:25:15.057199 [CA 2] Center 34 (4~65) winsize 62
5070 01:25:15.060378 [CA 3] Center 33 (3~64) winsize 62
5071 01:25:15.063564 [CA 4] Center 33 (3~64) winsize 62
5072 01:25:15.067081 [CA 5] Center 32 (2~62) winsize 61
5073 01:25:15.067152
5074 01:25:15.070529 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5075 01:25:15.070603
5076 01:25:15.073910 [CATrainingPosCal] consider 1 rank data
5077 01:25:15.077287 u2DelayCellTimex100 = 270/100 ps
5078 01:25:15.080326 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5079 01:25:15.083773 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5080 01:25:15.087129 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5081 01:25:15.090428 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5082 01:25:15.093709 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5083 01:25:15.097309 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5084 01:25:15.100723
5085 01:25:15.103696 CA PerBit enable=1, Macro0, CA PI delay=32
5086 01:25:15.103814
5087 01:25:15.107003 [CBTSetCACLKResult] CA Dly = 32
5088 01:25:15.107078 CS Dly: 5 (0~36)
5089 01:25:15.107139 ==
5090 01:25:15.110559 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 01:25:15.113488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 01:25:15.113570 ==
5093 01:25:15.120352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 01:25:15.127190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5095 01:25:15.130606 [CA 0] Center 37 (6~68) winsize 63
5096 01:25:15.133606 [CA 1] Center 37 (6~68) winsize 63
5097 01:25:15.137012 [CA 2] Center 34 (4~65) winsize 62
5098 01:25:15.140537 [CA 3] Center 34 (3~65) winsize 63
5099 01:25:15.143662 [CA 4] Center 32 (2~63) winsize 62
5100 01:25:15.147099 [CA 5] Center 32 (2~62) winsize 61
5101 01:25:15.147172
5102 01:25:15.150566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5103 01:25:15.150647
5104 01:25:15.154001 [CATrainingPosCal] consider 2 rank data
5105 01:25:15.156898 u2DelayCellTimex100 = 270/100 ps
5106 01:25:15.160626 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5107 01:25:15.163940 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5108 01:25:15.166815 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5109 01:25:15.170655 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5110 01:25:15.173361 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5111 01:25:15.176941 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5112 01:25:15.180457
5113 01:25:15.183536 CA PerBit enable=1, Macro0, CA PI delay=32
5114 01:25:15.183673
5115 01:25:15.187152 [CBTSetCACLKResult] CA Dly = 32
5116 01:25:15.187266 CS Dly: 5 (0~37)
5117 01:25:15.187378
5118 01:25:15.189911 ----->DramcWriteLeveling(PI) begin...
5119 01:25:15.190025 ==
5120 01:25:15.193342 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 01:25:15.196742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 01:25:15.199838 ==
5123 01:25:15.199935 Write leveling (Byte 0): 33 => 33
5124 01:25:15.203854 Write leveling (Byte 1): 29 => 29
5125 01:25:15.206665 DramcWriteLeveling(PI) end<-----
5126 01:25:15.206762
5127 01:25:15.206859 ==
5128 01:25:15.210162 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 01:25:15.216731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 01:25:15.216836 ==
5131 01:25:15.219893 [Gating] SW mode calibration
5132 01:25:15.226974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 01:25:15.230268 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 01:25:15.236850 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5135 01:25:15.240227 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 01:25:15.243479 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 01:25:15.247068 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 01:25:15.253732 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 01:25:15.256636 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 01:25:15.259875 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5141 01:25:15.266847 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
5142 01:25:15.270187 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5143 01:25:15.273434 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 01:25:15.280027 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 01:25:15.283819 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 01:25:15.287093 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 01:25:15.293250 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 01:25:15.296697 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5149 01:25:15.299861 0 15 28 | B1->B0 | 2828 3737 | 0 0 | (0 0) (0 0)
5150 01:25:15.306704 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5151 01:25:15.309714 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 01:25:15.313575 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 01:25:15.319925 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 01:25:15.323019 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 01:25:15.326547 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 01:25:15.333239 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5157 01:25:15.336606 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5158 01:25:15.339558 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5159 01:25:15.346522 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 01:25:15.350051 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 01:25:15.352972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 01:25:15.356281 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 01:25:15.363047 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 01:25:15.366406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 01:25:15.369544 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 01:25:15.376734 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 01:25:15.379610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 01:25:15.383362 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 01:25:15.389456 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 01:25:15.393513 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 01:25:15.396583 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 01:25:15.403103 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 01:25:15.406194 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5174 01:25:15.409444 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5175 01:25:15.412706 Total UI for P1: 0, mck2ui 16
5176 01:25:15.416271 best dqsien dly found for B0: ( 1, 2, 26)
5177 01:25:15.422735 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 01:25:15.422849 Total UI for P1: 0, mck2ui 16
5179 01:25:15.429471 best dqsien dly found for B1: ( 1, 3, 0)
5180 01:25:15.432705 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5181 01:25:15.436468 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5182 01:25:15.436544
5183 01:25:15.439258 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5184 01:25:15.442873 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5185 01:25:15.446238 [Gating] SW calibration Done
5186 01:25:15.446336 ==
5187 01:25:15.449191 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 01:25:15.452779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 01:25:15.452850 ==
5190 01:25:15.456100 RX Vref Scan: 0
5191 01:25:15.456206
5192 01:25:15.456332 RX Vref 0 -> 0, step: 1
5193 01:25:15.456427
5194 01:25:15.459576 RX Delay -80 -> 252, step: 8
5195 01:25:15.462695 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5196 01:25:15.469459 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5197 01:25:15.472717 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5198 01:25:15.476180 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5199 01:25:15.479168 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5200 01:25:15.482391 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5201 01:25:15.485892 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5202 01:25:15.492820 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5203 01:25:15.495965 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5204 01:25:15.499226 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5205 01:25:15.502908 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5206 01:25:15.505643 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5207 01:25:15.508969 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5208 01:25:15.515746 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5209 01:25:15.519047 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5210 01:25:15.522388 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5211 01:25:15.522463 ==
5212 01:25:15.525874 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 01:25:15.529126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 01:25:15.529207 ==
5215 01:25:15.532394 DQS Delay:
5216 01:25:15.532516 DQS0 = 0, DQS1 = 0
5217 01:25:15.535818 DQM Delay:
5218 01:25:15.535889 DQM0 = 103, DQM1 = 94
5219 01:25:15.535949 DQ Delay:
5220 01:25:15.539515 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5221 01:25:15.542752 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =107
5222 01:25:15.546046 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5223 01:25:15.552630 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5224 01:25:15.552704
5225 01:25:15.552777
5226 01:25:15.552836 ==
5227 01:25:15.555937 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 01:25:15.559228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 01:25:15.559305 ==
5230 01:25:15.559378
5231 01:25:15.559437
5232 01:25:15.562499 TX Vref Scan disable
5233 01:25:15.562594 == TX Byte 0 ==
5234 01:25:15.568962 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5235 01:25:15.572446 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5236 01:25:15.572532 == TX Byte 1 ==
5237 01:25:15.579073 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5238 01:25:15.582351 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5239 01:25:15.582437 ==
5240 01:25:15.585509 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 01:25:15.588776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 01:25:15.588919 ==
5243 01:25:15.589007
5244 01:25:15.589078
5245 01:25:15.591978 TX Vref Scan disable
5246 01:25:15.595501 == TX Byte 0 ==
5247 01:25:15.598939 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5248 01:25:15.602546 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5249 01:25:15.605766 == TX Byte 1 ==
5250 01:25:15.608811 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5251 01:25:15.612415 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5252 01:25:15.612516
5253 01:25:15.615770 [DATLAT]
5254 01:25:15.615908 Freq=933, CH0 RK0
5255 01:25:15.616031
5256 01:25:15.619140 DATLAT Default: 0xd
5257 01:25:15.619274 0, 0xFFFF, sum = 0
5258 01:25:15.621896 1, 0xFFFF, sum = 0
5259 01:25:15.622003 2, 0xFFFF, sum = 0
5260 01:25:15.625589 3, 0xFFFF, sum = 0
5261 01:25:15.625661 4, 0xFFFF, sum = 0
5262 01:25:15.629081 5, 0xFFFF, sum = 0
5263 01:25:15.629177 6, 0xFFFF, sum = 0
5264 01:25:15.632414 7, 0xFFFF, sum = 0
5265 01:25:15.632528 8, 0xFFFF, sum = 0
5266 01:25:15.635316 9, 0xFFFF, sum = 0
5267 01:25:15.635402 10, 0x0, sum = 1
5268 01:25:15.639077 11, 0x0, sum = 2
5269 01:25:15.639174 12, 0x0, sum = 3
5270 01:25:15.641914 13, 0x0, sum = 4
5271 01:25:15.642034 best_step = 11
5272 01:25:15.642120
5273 01:25:15.642240 ==
5274 01:25:15.645666 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 01:25:15.652395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 01:25:15.652472 ==
5277 01:25:15.652543 RX Vref Scan: 1
5278 01:25:15.652601
5279 01:25:15.655360 RX Vref 0 -> 0, step: 1
5280 01:25:15.655453
5281 01:25:15.658952 RX Delay -53 -> 252, step: 4
5282 01:25:15.659053
5283 01:25:15.662470 Set Vref, RX VrefLevel [Byte0]: 54
5284 01:25:15.665105 [Byte1]: 55
5285 01:25:15.665175
5286 01:25:15.668487 Final RX Vref Byte 0 = 54 to rank0
5287 01:25:15.671997 Final RX Vref Byte 1 = 55 to rank0
5288 01:25:15.675578 Final RX Vref Byte 0 = 54 to rank1
5289 01:25:15.678594 Final RX Vref Byte 1 = 55 to rank1==
5290 01:25:15.682166 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 01:25:15.685232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 01:25:15.685328 ==
5293 01:25:15.688628 DQS Delay:
5294 01:25:15.688734 DQS0 = 0, DQS1 = 0
5295 01:25:15.688855 DQM Delay:
5296 01:25:15.692086 DQM0 = 104, DQM1 = 96
5297 01:25:15.692186 DQ Delay:
5298 01:25:15.695153 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5299 01:25:15.698644 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5300 01:25:15.701980 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5301 01:25:15.708834 DQ12 =100, DQ13 =102, DQ14 =104, DQ15 =104
5302 01:25:15.708912
5303 01:25:15.708996
5304 01:25:15.715283 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f27, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5305 01:25:15.718482 CH0 RK0: MR19=505, MR18=2F27
5306 01:25:15.725492 CH0_RK0: MR19=0x505, MR18=0x2F27, DQSOSC=407, MR23=63, INC=65, DEC=43
5307 01:25:15.725571
5308 01:25:15.728301 ----->DramcWriteLeveling(PI) begin...
5309 01:25:15.728375 ==
5310 01:25:15.731752 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 01:25:15.735283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 01:25:15.735436 ==
5313 01:25:15.738829 Write leveling (Byte 0): 33 => 33
5314 01:25:15.742108 Write leveling (Byte 1): 30 => 30
5315 01:25:15.744770 DramcWriteLeveling(PI) end<-----
5316 01:25:15.744858
5317 01:25:15.744919 ==
5318 01:25:15.748118 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 01:25:15.751508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 01:25:15.751631 ==
5321 01:25:15.755075 [Gating] SW mode calibration
5322 01:25:15.761602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5323 01:25:15.768114 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5324 01:25:15.771623 0 14 0 | B1->B0 | 3232 3131 | 1 1 | (1 1) (1 1)
5325 01:25:15.778070 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 01:25:15.781357 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 01:25:15.785019 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 01:25:15.791387 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 01:25:15.794678 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 01:25:15.798323 0 14 24 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
5331 01:25:15.801722 0 14 28 | B1->B0 | 2828 2727 | 0 0 | (0 0) (1 0)
5332 01:25:15.807872 0 15 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
5333 01:25:15.811123 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 01:25:15.814773 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 01:25:15.821192 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 01:25:15.824652 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 01:25:15.827867 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 01:25:15.834366 0 15 24 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
5339 01:25:15.837617 0 15 28 | B1->B0 | 3b3b 3838 | 0 0 | (0 0) (0 0)
5340 01:25:15.841569 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 01:25:15.847643 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 01:25:15.850794 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 01:25:15.854485 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 01:25:15.860925 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 01:25:15.864701 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 01:25:15.867294 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 01:25:15.874359 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5348 01:25:15.877468 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 01:25:15.880917 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 01:25:15.887356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 01:25:15.890865 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 01:25:15.893797 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 01:25:15.900727 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 01:25:15.904170 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 01:25:15.907233 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 01:25:15.914268 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 01:25:15.917335 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 01:25:15.920710 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 01:25:15.927146 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 01:25:15.930903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 01:25:15.933736 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 01:25:15.940715 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 01:25:15.943909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5364 01:25:15.947771 Total UI for P1: 0, mck2ui 16
5365 01:25:15.950611 best dqsien dly found for B0: ( 1, 2, 26)
5366 01:25:15.954087 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5367 01:25:15.957515 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 01:25:15.960993 Total UI for P1: 0, mck2ui 16
5369 01:25:15.964418 best dqsien dly found for B1: ( 1, 2, 30)
5370 01:25:15.967476 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5371 01:25:15.974262 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5372 01:25:15.974368
5373 01:25:15.977496 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5374 01:25:15.980457 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5375 01:25:15.983904 [Gating] SW calibration Done
5376 01:25:15.983974 ==
5377 01:25:15.987188 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 01:25:15.990301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 01:25:15.990371 ==
5380 01:25:15.993719 RX Vref Scan: 0
5381 01:25:15.993784
5382 01:25:15.993846 RX Vref 0 -> 0, step: 1
5383 01:25:15.993905
5384 01:25:15.997397 RX Delay -80 -> 252, step: 8
5385 01:25:16.000299 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5386 01:25:16.006890 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5387 01:25:16.010341 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5388 01:25:16.013810 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5389 01:25:16.016872 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5390 01:25:16.020418 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5391 01:25:16.023666 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5392 01:25:16.030016 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5393 01:25:16.033521 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5394 01:25:16.036905 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5395 01:25:16.040589 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5396 01:25:16.043971 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5397 01:25:16.047104 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5398 01:25:16.050345 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5399 01:25:16.057286 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5400 01:25:16.060623 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5401 01:25:16.060699 ==
5402 01:25:16.063921 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 01:25:16.066842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 01:25:16.066920 ==
5405 01:25:16.066982 DQS Delay:
5406 01:25:16.070524 DQS0 = 0, DQS1 = 0
5407 01:25:16.070594 DQM Delay:
5408 01:25:16.073688 DQM0 = 104, DQM1 = 93
5409 01:25:16.073758 DQ Delay:
5410 01:25:16.077077 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5411 01:25:16.080355 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5412 01:25:16.083557 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5413 01:25:16.086782 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5414 01:25:16.086849
5415 01:25:16.086912
5416 01:25:16.086969 ==
5417 01:25:16.090640 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 01:25:16.096858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 01:25:16.096937 ==
5420 01:25:16.097002
5421 01:25:16.097065
5422 01:25:16.097122 TX Vref Scan disable
5423 01:25:16.100433 == TX Byte 0 ==
5424 01:25:16.103749 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5425 01:25:16.110233 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5426 01:25:16.110306 == TX Byte 1 ==
5427 01:25:16.113514 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5428 01:25:16.120606 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5429 01:25:16.120686 ==
5430 01:25:16.123791 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 01:25:16.127159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 01:25:16.127229 ==
5433 01:25:16.127292
5434 01:25:16.127351
5435 01:25:16.130261 TX Vref Scan disable
5436 01:25:16.130328 == TX Byte 0 ==
5437 01:25:16.136982 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5438 01:25:16.140218 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5439 01:25:16.140290 == TX Byte 1 ==
5440 01:25:16.146728 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5441 01:25:16.150038 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5442 01:25:16.150109
5443 01:25:16.150173 [DATLAT]
5444 01:25:16.153431 Freq=933, CH0 RK1
5445 01:25:16.153500
5446 01:25:16.153560 DATLAT Default: 0xb
5447 01:25:16.156873 0, 0xFFFF, sum = 0
5448 01:25:16.156945 1, 0xFFFF, sum = 0
5449 01:25:16.160471 2, 0xFFFF, sum = 0
5450 01:25:16.160541 3, 0xFFFF, sum = 0
5451 01:25:16.163755 4, 0xFFFF, sum = 0
5452 01:25:16.163821 5, 0xFFFF, sum = 0
5453 01:25:16.167180 6, 0xFFFF, sum = 0
5454 01:25:16.170511 7, 0xFFFF, sum = 0
5455 01:25:16.170587 8, 0xFFFF, sum = 0
5456 01:25:16.173454 9, 0xFFFF, sum = 0
5457 01:25:16.173525 10, 0x0, sum = 1
5458 01:25:16.173586 11, 0x0, sum = 2
5459 01:25:16.177255 12, 0x0, sum = 3
5460 01:25:16.177324 13, 0x0, sum = 4
5461 01:25:16.180203 best_step = 11
5462 01:25:16.180274
5463 01:25:16.180352 ==
5464 01:25:16.183474 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 01:25:16.187101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 01:25:16.187173 ==
5467 01:25:16.190682 RX Vref Scan: 0
5468 01:25:16.190753
5469 01:25:16.190812 RX Vref 0 -> 0, step: 1
5470 01:25:16.190869
5471 01:25:16.193748 RX Delay -53 -> 252, step: 4
5472 01:25:16.201000 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5473 01:25:16.204190 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5474 01:25:16.207646 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5475 01:25:16.210757 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5476 01:25:16.214071 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5477 01:25:16.220724 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5478 01:25:16.224027 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5479 01:25:16.227238 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5480 01:25:16.230984 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5481 01:25:16.234258 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5482 01:25:16.240963 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5483 01:25:16.243993 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5484 01:25:16.247225 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5485 01:25:16.250401 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5486 01:25:16.254110 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5487 01:25:16.260595 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5488 01:25:16.260682 ==
5489 01:25:16.264045 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 01:25:16.267365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 01:25:16.267437 ==
5492 01:25:16.267497 DQS Delay:
5493 01:25:16.270406 DQS0 = 0, DQS1 = 0
5494 01:25:16.270475 DQM Delay:
5495 01:25:16.274116 DQM0 = 104, DQM1 = 95
5496 01:25:16.274188 DQ Delay:
5497 01:25:16.277587 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5498 01:25:16.280312 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5499 01:25:16.283693 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =92
5500 01:25:16.287513 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5501 01:25:16.287585
5502 01:25:16.287670
5503 01:25:16.297084 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5504 01:25:16.297155 CH0 RK1: MR19=505, MR18=2C05
5505 01:25:16.304114 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5506 01:25:16.307502 [RxdqsGatingPostProcess] freq 933
5507 01:25:16.314350 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5508 01:25:16.317461 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 01:25:16.320961 best DQS1 dly(2T, 0.5T) = (0, 11)
5510 01:25:16.323962 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 01:25:16.327347 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5512 01:25:16.331031 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 01:25:16.331104 best DQS1 dly(2T, 0.5T) = (0, 10)
5514 01:25:16.333805 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 01:25:16.337418 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5516 01:25:16.340620 Pre-setting of DQS Precalculation
5517 01:25:16.347033 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5518 01:25:16.347107 ==
5519 01:25:16.350776 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 01:25:16.353865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 01:25:16.353939 ==
5522 01:25:16.360349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 01:25:16.367142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 01:25:16.370651 [CA 0] Center 36 (6~67) winsize 62
5525 01:25:16.374076 [CA 1] Center 37 (6~68) winsize 63
5526 01:25:16.377352 [CA 2] Center 34 (4~65) winsize 62
5527 01:25:16.380207 [CA 3] Center 34 (4~65) winsize 62
5528 01:25:16.383670 [CA 4] Center 34 (4~64) winsize 61
5529 01:25:16.387048 [CA 5] Center 33 (3~64) winsize 62
5530 01:25:16.387115
5531 01:25:16.390468 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 01:25:16.390534
5533 01:25:16.393736 [CATrainingPosCal] consider 1 rank data
5534 01:25:16.397091 u2DelayCellTimex100 = 270/100 ps
5535 01:25:16.400608 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 01:25:16.403788 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5537 01:25:16.407473 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5538 01:25:16.410243 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 01:25:16.413779 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 01:25:16.417013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 01:25:16.417083
5542 01:25:16.420695 CA PerBit enable=1, Macro0, CA PI delay=33
5543 01:25:16.423966
5544 01:25:16.424036 [CBTSetCACLKResult] CA Dly = 33
5545 01:25:16.427162 CS Dly: 6 (0~37)
5546 01:25:16.427232 ==
5547 01:25:16.430607 Dram Type= 6, Freq= 0, CH_1, rank 1
5548 01:25:16.433921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 01:25:16.433996 ==
5550 01:25:16.440640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5551 01:25:16.447113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5552 01:25:16.450740 [CA 0] Center 36 (6~67) winsize 62
5553 01:25:16.453821 [CA 1] Center 37 (6~68) winsize 63
5554 01:25:16.457339 [CA 2] Center 35 (4~66) winsize 63
5555 01:25:16.460420 [CA 3] Center 34 (4~65) winsize 62
5556 01:25:16.463614 [CA 4] Center 34 (4~65) winsize 62
5557 01:25:16.466946 [CA 5] Center 33 (3~64) winsize 62
5558 01:25:16.467034
5559 01:25:16.470217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5560 01:25:16.470291
5561 01:25:16.473481 [CATrainingPosCal] consider 2 rank data
5562 01:25:16.477136 u2DelayCellTimex100 = 270/100 ps
5563 01:25:16.480387 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 01:25:16.483788 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5565 01:25:16.486663 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5566 01:25:16.490097 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 01:25:16.493726 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 01:25:16.497168 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 01:25:16.497239
5570 01:25:16.503741 CA PerBit enable=1, Macro0, CA PI delay=33
5571 01:25:16.503819
5572 01:25:16.503882 [CBTSetCACLKResult] CA Dly = 33
5573 01:25:16.507139 CS Dly: 7 (0~40)
5574 01:25:16.507213
5575 01:25:16.510418 ----->DramcWriteLeveling(PI) begin...
5576 01:25:16.510491 ==
5577 01:25:16.513463 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 01:25:16.516706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 01:25:16.516849 ==
5580 01:25:16.519943 Write leveling (Byte 0): 27 => 27
5581 01:25:16.523080 Write leveling (Byte 1): 27 => 27
5582 01:25:16.527012 DramcWriteLeveling(PI) end<-----
5583 01:25:16.527083
5584 01:25:16.527148 ==
5585 01:25:16.530281 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 01:25:16.533500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 01:25:16.537031 ==
5588 01:25:16.537103 [Gating] SW mode calibration
5589 01:25:16.546430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5590 01:25:16.549918 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5591 01:25:16.553658 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 01:25:16.560200 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 01:25:16.563729 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 01:25:16.566962 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 01:25:16.573792 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 01:25:16.576972 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5597 01:25:16.579900 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5598 01:25:16.586545 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
5599 01:25:16.589815 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 01:25:16.593591 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 01:25:16.599733 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 01:25:16.603231 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 01:25:16.606778 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 01:25:16.613065 0 15 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
5605 01:25:16.616407 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5606 01:25:16.619912 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5607 01:25:16.623330 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 01:25:16.629915 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 01:25:16.633461 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 01:25:16.636355 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 01:25:16.642914 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 01:25:16.646235 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 01:25:16.649917 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5614 01:25:16.656418 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5615 01:25:16.660015 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 01:25:16.662900 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 01:25:16.669908 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 01:25:16.672923 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 01:25:16.676795 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 01:25:16.683555 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 01:25:16.686848 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 01:25:16.690307 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 01:25:16.696865 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 01:25:16.699908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 01:25:16.703559 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 01:25:16.709897 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 01:25:16.713405 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 01:25:16.716548 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 01:25:16.720021 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 01:25:16.726337 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 01:25:16.729916 Total UI for P1: 0, mck2ui 16
5632 01:25:16.733296 best dqsien dly found for B0: ( 1, 2, 26)
5633 01:25:16.736914 Total UI for P1: 0, mck2ui 16
5634 01:25:16.740040 best dqsien dly found for B1: ( 1, 2, 26)
5635 01:25:16.743361 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5636 01:25:16.746262 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5637 01:25:16.746350
5638 01:25:16.749756 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5639 01:25:16.753144 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5640 01:25:16.756436 [Gating] SW calibration Done
5641 01:25:16.756574 ==
5642 01:25:16.759778 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 01:25:16.763248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 01:25:16.763329 ==
5645 01:25:16.766742 RX Vref Scan: 0
5646 01:25:16.766823
5647 01:25:16.766886 RX Vref 0 -> 0, step: 1
5648 01:25:16.770231
5649 01:25:16.770314 RX Delay -80 -> 252, step: 8
5650 01:25:16.776547 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5651 01:25:16.779869 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5652 01:25:16.783096 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5653 01:25:16.786440 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5654 01:25:16.789819 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5655 01:25:16.793244 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5656 01:25:16.800218 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5657 01:25:16.803108 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5658 01:25:16.806581 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5659 01:25:16.809999 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5660 01:25:16.813366 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5661 01:25:16.816414 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5662 01:25:16.819861 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5663 01:25:16.826348 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5664 01:25:16.830244 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5665 01:25:16.833130 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5666 01:25:16.833211 ==
5667 01:25:16.836874 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 01:25:16.839996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 01:25:16.840078 ==
5670 01:25:16.843495 DQS Delay:
5671 01:25:16.843576 DQS0 = 0, DQS1 = 0
5672 01:25:16.846830 DQM Delay:
5673 01:25:16.846910 DQM0 = 103, DQM1 = 99
5674 01:25:16.850019 DQ Delay:
5675 01:25:16.850116 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5676 01:25:16.853335 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5677 01:25:16.856565 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5678 01:25:16.863199 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5679 01:25:16.863279
5680 01:25:16.863343
5681 01:25:16.863406 ==
5682 01:25:16.866536 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 01:25:16.870097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 01:25:16.870187 ==
5685 01:25:16.870251
5686 01:25:16.870308
5687 01:25:16.872947 TX Vref Scan disable
5688 01:25:16.873048 == TX Byte 0 ==
5689 01:25:16.880236 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5690 01:25:16.883094 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5691 01:25:16.883165 == TX Byte 1 ==
5692 01:25:16.889912 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5693 01:25:16.893620 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5694 01:25:16.893694 ==
5695 01:25:16.896509 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 01:25:16.899852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 01:25:16.899923 ==
5698 01:25:16.899984
5699 01:25:16.900045
5700 01:25:16.903498 TX Vref Scan disable
5701 01:25:16.906620 == TX Byte 0 ==
5702 01:25:16.909684 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5703 01:25:16.913185 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5704 01:25:16.916220 == TX Byte 1 ==
5705 01:25:16.919499 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5706 01:25:16.923032 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5707 01:25:16.923103
5708 01:25:16.926203 [DATLAT]
5709 01:25:16.926278 Freq=933, CH1 RK0
5710 01:25:16.926340
5711 01:25:16.929546 DATLAT Default: 0xd
5712 01:25:16.929619 0, 0xFFFF, sum = 0
5713 01:25:16.933070 1, 0xFFFF, sum = 0
5714 01:25:16.933146 2, 0xFFFF, sum = 0
5715 01:25:16.936436 3, 0xFFFF, sum = 0
5716 01:25:16.936506 4, 0xFFFF, sum = 0
5717 01:25:16.940001 5, 0xFFFF, sum = 0
5718 01:25:16.940073 6, 0xFFFF, sum = 0
5719 01:25:16.943021 7, 0xFFFF, sum = 0
5720 01:25:16.943093 8, 0xFFFF, sum = 0
5721 01:25:16.946099 9, 0xFFFF, sum = 0
5722 01:25:16.946198 10, 0x0, sum = 1
5723 01:25:16.949655 11, 0x0, sum = 2
5724 01:25:16.949748 12, 0x0, sum = 3
5725 01:25:16.953031 13, 0x0, sum = 4
5726 01:25:16.953116 best_step = 11
5727 01:25:16.953180
5728 01:25:16.953240 ==
5729 01:25:16.955951 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 01:25:16.962673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 01:25:16.962753 ==
5732 01:25:16.962821 RX Vref Scan: 1
5733 01:25:16.962882
5734 01:25:16.966136 RX Vref 0 -> 0, step: 1
5735 01:25:16.966211
5736 01:25:16.969136 RX Delay -45 -> 252, step: 4
5737 01:25:16.969213
5738 01:25:16.973171 Set Vref, RX VrefLevel [Byte0]: 53
5739 01:25:16.976157 [Byte1]: 49
5740 01:25:16.976228
5741 01:25:16.979214 Final RX Vref Byte 0 = 53 to rank0
5742 01:25:16.982501 Final RX Vref Byte 1 = 49 to rank0
5743 01:25:16.986056 Final RX Vref Byte 0 = 53 to rank1
5744 01:25:16.989716 Final RX Vref Byte 1 = 49 to rank1==
5745 01:25:16.992459 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 01:25:16.996093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 01:25:16.996167 ==
5748 01:25:16.999386 DQS Delay:
5749 01:25:16.999481 DQS0 = 0, DQS1 = 0
5750 01:25:17.002673 DQM Delay:
5751 01:25:17.002742 DQM0 = 103, DQM1 = 98
5752 01:25:17.002802 DQ Delay:
5753 01:25:17.005647 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5754 01:25:17.009059 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5755 01:25:17.012732 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5756 01:25:17.018926 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5757 01:25:17.019008
5758 01:25:17.019072
5759 01:25:17.025632 [DQSOSCAuto] RK0, (LSB)MR18= 0x182f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5760 01:25:17.028905 CH1 RK0: MR19=505, MR18=182F
5761 01:25:17.035638 CH1_RK0: MR19=0x505, MR18=0x182F, DQSOSC=407, MR23=63, INC=65, DEC=43
5762 01:25:17.035739
5763 01:25:17.038988 ----->DramcWriteLeveling(PI) begin...
5764 01:25:17.039070 ==
5765 01:25:17.042508 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 01:25:17.045819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 01:25:17.045898 ==
5768 01:25:17.049474 Write leveling (Byte 0): 27 => 27
5769 01:25:17.052373 Write leveling (Byte 1): 30 => 30
5770 01:25:17.056258 DramcWriteLeveling(PI) end<-----
5771 01:25:17.056336
5772 01:25:17.056397 ==
5773 01:25:17.059462 Dram Type= 6, Freq= 0, CH_1, rank 1
5774 01:25:17.062762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 01:25:17.062834 ==
5776 01:25:17.065925 [Gating] SW mode calibration
5777 01:25:17.072316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5778 01:25:17.078864 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5779 01:25:17.082580 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 01:25:17.088853 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 01:25:17.091879 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 01:25:17.095458 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 01:25:17.102109 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 01:25:17.105432 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 01:25:17.108605 0 14 24 | B1->B0 | 2f2f 3131 | 0 0 | (1 0) (1 0)
5786 01:25:17.114893 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5787 01:25:17.118384 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 01:25:17.121795 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 01:25:17.128476 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 01:25:17.131949 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 01:25:17.135162 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 01:25:17.138391 0 15 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
5793 01:25:17.144725 0 15 24 | B1->B0 | 3838 2f2f | 0 0 | (0 0) (0 0)
5794 01:25:17.148340 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
5795 01:25:17.151843 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 01:25:17.158452 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 01:25:17.161652 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 01:25:17.164782 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 01:25:17.171566 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 01:25:17.175237 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 01:25:17.178161 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5802 01:25:17.184875 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5803 01:25:17.188741 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 01:25:17.191755 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 01:25:17.197953 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 01:25:17.201815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 01:25:17.204725 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 01:25:17.211453 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 01:25:17.215068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 01:25:17.218065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 01:25:17.224910 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 01:25:17.227995 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 01:25:17.231297 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 01:25:17.238414 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 01:25:17.241653 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 01:25:17.244695 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 01:25:17.251171 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5818 01:25:17.254635 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 01:25:17.257891 Total UI for P1: 0, mck2ui 16
5820 01:25:17.261174 best dqsien dly found for B0: ( 1, 2, 24)
5821 01:25:17.264731 Total UI for P1: 0, mck2ui 16
5822 01:25:17.268085 best dqsien dly found for B1: ( 1, 2, 24)
5823 01:25:17.271215 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5824 01:25:17.274801 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5825 01:25:17.274886
5826 01:25:17.277946 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5827 01:25:17.281674 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5828 01:25:17.284540 [Gating] SW calibration Done
5829 01:25:17.284610 ==
5830 01:25:17.287906 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 01:25:17.291344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 01:25:17.291453 ==
5833 01:25:17.294709 RX Vref Scan: 0
5834 01:25:17.294782
5835 01:25:17.298285 RX Vref 0 -> 0, step: 1
5836 01:25:17.298358
5837 01:25:17.298418 RX Delay -80 -> 252, step: 8
5838 01:25:17.304679 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5839 01:25:17.307977 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5840 01:25:17.311100 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5841 01:25:17.314376 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5842 01:25:17.317649 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5843 01:25:17.321148 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5844 01:25:17.327748 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5845 01:25:17.331125 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5846 01:25:17.334641 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5847 01:25:17.337617 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5848 01:25:17.341046 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5849 01:25:17.344198 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5850 01:25:17.350944 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5851 01:25:17.354394 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5852 01:25:17.357518 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5853 01:25:17.361197 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5854 01:25:17.361270 ==
5855 01:25:17.364458 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 01:25:17.371096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 01:25:17.371175 ==
5858 01:25:17.371241 DQS Delay:
5859 01:25:17.374534 DQS0 = 0, DQS1 = 0
5860 01:25:17.374603 DQM Delay:
5861 01:25:17.374669 DQM0 = 102, DQM1 = 99
5862 01:25:17.377395 DQ Delay:
5863 01:25:17.381147 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5864 01:25:17.384706 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5865 01:25:17.387486 DQ8 =87, DQ9 =91, DQ10 =103, DQ11 =91
5866 01:25:17.390863 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5867 01:25:17.390934
5868 01:25:17.390996
5869 01:25:17.391057 ==
5870 01:25:17.394428 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 01:25:17.397506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 01:25:17.397577 ==
5873 01:25:17.397637
5874 01:25:17.397699
5875 01:25:17.400768 TX Vref Scan disable
5876 01:25:17.404047 == TX Byte 0 ==
5877 01:25:17.407510 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5878 01:25:17.411030 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5879 01:25:17.414371 == TX Byte 1 ==
5880 01:25:17.417444 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5881 01:25:17.420658 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5882 01:25:17.420728 ==
5883 01:25:17.424016 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 01:25:17.430483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 01:25:17.430558 ==
5886 01:25:17.430619
5887 01:25:17.430677
5888 01:25:17.430732 TX Vref Scan disable
5889 01:25:17.435017 == TX Byte 0 ==
5890 01:25:17.437777 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5891 01:25:17.441501 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5892 01:25:17.444945 == TX Byte 1 ==
5893 01:25:17.447705 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5894 01:25:17.454293 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5895 01:25:17.454388
5896 01:25:17.454464 [DATLAT]
5897 01:25:17.454557 Freq=933, CH1 RK1
5898 01:25:17.454633
5899 01:25:17.457556 DATLAT Default: 0xb
5900 01:25:17.457659 0, 0xFFFF, sum = 0
5901 01:25:17.460770 1, 0xFFFF, sum = 0
5902 01:25:17.460875 2, 0xFFFF, sum = 0
5903 01:25:17.464668 3, 0xFFFF, sum = 0
5904 01:25:17.467752 4, 0xFFFF, sum = 0
5905 01:25:17.467855 5, 0xFFFF, sum = 0
5906 01:25:17.470777 6, 0xFFFF, sum = 0
5907 01:25:17.470881 7, 0xFFFF, sum = 0
5908 01:25:17.474179 8, 0xFFFF, sum = 0
5909 01:25:17.474271 9, 0xFFFF, sum = 0
5910 01:25:17.477439 10, 0x0, sum = 1
5911 01:25:17.477527 11, 0x0, sum = 2
5912 01:25:17.480819 12, 0x0, sum = 3
5913 01:25:17.480895 13, 0x0, sum = 4
5914 01:25:17.480957 best_step = 11
5915 01:25:17.481015
5916 01:25:17.484119 ==
5917 01:25:17.487751 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 01:25:17.490644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 01:25:17.490729 ==
5920 01:25:17.490790 RX Vref Scan: 0
5921 01:25:17.490848
5922 01:25:17.494024 RX Vref 0 -> 0, step: 1
5923 01:25:17.494135
5924 01:25:17.497309 RX Delay -45 -> 252, step: 4
5925 01:25:17.501057 iDelay=203, Bit 0, Center 110 (31 ~ 190) 160
5926 01:25:17.507623 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5927 01:25:17.511171 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5928 01:25:17.514434 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5929 01:25:17.518165 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5930 01:25:17.520978 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5931 01:25:17.527342 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5932 01:25:17.530781 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5933 01:25:17.534290 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5934 01:25:17.537111 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5935 01:25:17.541315 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5936 01:25:17.543903 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5937 01:25:17.550727 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5938 01:25:17.554135 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5939 01:25:17.557372 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5940 01:25:17.560425 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5941 01:25:17.560500 ==
5942 01:25:17.564305 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 01:25:17.570586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 01:25:17.570667 ==
5945 01:25:17.570734 DQS Delay:
5946 01:25:17.573765 DQS0 = 0, DQS1 = 0
5947 01:25:17.573837 DQM Delay:
5948 01:25:17.577428 DQM0 = 104, DQM1 = 99
5949 01:25:17.577501 DQ Delay:
5950 01:25:17.580447 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5951 01:25:17.583748 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5952 01:25:17.587494 DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =94
5953 01:25:17.590588 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5954 01:25:17.590664
5955 01:25:17.590727
5956 01:25:17.600362 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5957 01:25:17.600447 CH1 RK1: MR19=504, MR18=2CFF
5958 01:25:17.606932 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5959 01:25:17.610598 [RxdqsGatingPostProcess] freq 933
5960 01:25:17.616720 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5961 01:25:17.620256 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 01:25:17.623828 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 01:25:17.627290 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 01:25:17.630328 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 01:25:17.633161 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 01:25:17.633232 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 01:25:17.636569 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 01:25:17.640044 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 01:25:17.643208 Pre-setting of DQS Precalculation
5970 01:25:17.650420 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5971 01:25:17.656605 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5972 01:25:17.663504 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5973 01:25:17.663629
5974 01:25:17.663712
5975 01:25:17.666272 [Calibration Summary] 1866 Mbps
5976 01:25:17.669580 CH 0, Rank 0
5977 01:25:17.669655 SW Impedance : PASS
5978 01:25:17.673036 DUTY Scan : NO K
5979 01:25:17.676743 ZQ Calibration : PASS
5980 01:25:17.676844 Jitter Meter : NO K
5981 01:25:17.679482 CBT Training : PASS
5982 01:25:17.679582 Write leveling : PASS
5983 01:25:17.682658 RX DQS gating : PASS
5984 01:25:17.686294 RX DQ/DQS(RDDQC) : PASS
5985 01:25:17.686368 TX DQ/DQS : PASS
5986 01:25:17.689623 RX DATLAT : PASS
5987 01:25:17.693206 RX DQ/DQS(Engine): PASS
5988 01:25:17.693277 TX OE : NO K
5989 01:25:17.696344 All Pass.
5990 01:25:17.696416
5991 01:25:17.696550 CH 0, Rank 1
5992 01:25:17.699116 SW Impedance : PASS
5993 01:25:17.699193 DUTY Scan : NO K
5994 01:25:17.702453 ZQ Calibration : PASS
5995 01:25:17.706110 Jitter Meter : NO K
5996 01:25:17.706186 CBT Training : PASS
5997 01:25:17.709317 Write leveling : PASS
5998 01:25:17.712594 RX DQS gating : PASS
5999 01:25:17.712668 RX DQ/DQS(RDDQC) : PASS
6000 01:25:17.716112 TX DQ/DQS : PASS
6001 01:25:17.719447 RX DATLAT : PASS
6002 01:25:17.719549 RX DQ/DQS(Engine): PASS
6003 01:25:17.723023 TX OE : NO K
6004 01:25:17.723094 All Pass.
6005 01:25:17.723160
6006 01:25:17.725830 CH 1, Rank 0
6007 01:25:17.725905 SW Impedance : PASS
6008 01:25:17.729400 DUTY Scan : NO K
6009 01:25:17.732961 ZQ Calibration : PASS
6010 01:25:17.733053 Jitter Meter : NO K
6011 01:25:17.736203 CBT Training : PASS
6012 01:25:17.736286 Write leveling : PASS
6013 01:25:17.739442 RX DQS gating : PASS
6014 01:25:17.743001 RX DQ/DQS(RDDQC) : PASS
6015 01:25:17.743074 TX DQ/DQS : PASS
6016 01:25:17.745814 RX DATLAT : PASS
6017 01:25:17.749660 RX DQ/DQS(Engine): PASS
6018 01:25:17.749733 TX OE : NO K
6019 01:25:17.752456 All Pass.
6020 01:25:17.752576
6021 01:25:17.752637 CH 1, Rank 1
6022 01:25:17.755740 SW Impedance : PASS
6023 01:25:17.755815 DUTY Scan : NO K
6024 01:25:17.759023 ZQ Calibration : PASS
6025 01:25:17.762715 Jitter Meter : NO K
6026 01:25:17.762803 CBT Training : PASS
6027 01:25:17.765578 Write leveling : PASS
6028 01:25:17.769665 RX DQS gating : PASS
6029 01:25:17.769739 RX DQ/DQS(RDDQC) : PASS
6030 01:25:17.772601 TX DQ/DQS : PASS
6031 01:25:17.775624 RX DATLAT : PASS
6032 01:25:17.775708 RX DQ/DQS(Engine): PASS
6033 01:25:17.778983 TX OE : NO K
6034 01:25:17.779059 All Pass.
6035 01:25:17.779120
6036 01:25:17.782566 DramC Write-DBI off
6037 01:25:17.785848 PER_BANK_REFRESH: Hybrid Mode
6038 01:25:17.785925 TX_TRACKING: ON
6039 01:25:17.795526 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6040 01:25:17.799053 [FAST_K] Save calibration result to emmc
6041 01:25:17.802134 dramc_set_vcore_voltage set vcore to 650000
6042 01:25:17.805984 Read voltage for 400, 6
6043 01:25:17.806056 Vio18 = 0
6044 01:25:17.806119 Vcore = 650000
6045 01:25:17.809336 Vdram = 0
6046 01:25:17.809409 Vddq = 0
6047 01:25:17.809469 Vmddr = 0
6048 01:25:17.815583 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6049 01:25:17.818805 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6050 01:25:17.822196 MEM_TYPE=3, freq_sel=20
6051 01:25:17.825429 sv_algorithm_assistance_LP4_800
6052 01:25:17.828724 ============ PULL DRAM RESETB DOWN ============
6053 01:25:17.832645 ========== PULL DRAM RESETB DOWN end =========
6054 01:25:17.838732 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6055 01:25:17.842262 ===================================
6056 01:25:17.842337 LPDDR4 DRAM CONFIGURATION
6057 01:25:17.845533 ===================================
6058 01:25:17.848687 EX_ROW_EN[0] = 0x0
6059 01:25:17.852137 EX_ROW_EN[1] = 0x0
6060 01:25:17.852215 LP4Y_EN = 0x0
6061 01:25:17.855883 WORK_FSP = 0x0
6062 01:25:17.855957 WL = 0x2
6063 01:25:17.859031 RL = 0x2
6064 01:25:17.859100 BL = 0x2
6065 01:25:17.862338 RPST = 0x0
6066 01:25:17.862416 RD_PRE = 0x0
6067 01:25:17.865764 WR_PRE = 0x1
6068 01:25:17.865834 WR_PST = 0x0
6069 01:25:17.868682 DBI_WR = 0x0
6070 01:25:17.868755 DBI_RD = 0x0
6071 01:25:17.872206 OTF = 0x1
6072 01:25:17.875241 ===================================
6073 01:25:17.878863 ===================================
6074 01:25:17.878934 ANA top config
6075 01:25:17.882130 ===================================
6076 01:25:17.885503 DLL_ASYNC_EN = 0
6077 01:25:17.888854 ALL_SLAVE_EN = 1
6078 01:25:17.888932 NEW_RANK_MODE = 1
6079 01:25:17.891776 DLL_IDLE_MODE = 1
6080 01:25:17.895277 LP45_APHY_COMB_EN = 1
6081 01:25:17.898769 TX_ODT_DIS = 1
6082 01:25:17.902040 NEW_8X_MODE = 1
6083 01:25:17.905414 ===================================
6084 01:25:17.909065 ===================================
6085 01:25:17.909139 data_rate = 800
6086 01:25:17.911791 CKR = 1
6087 01:25:17.915452 DQ_P2S_RATIO = 4
6088 01:25:17.918893 ===================================
6089 01:25:17.921664 CA_P2S_RATIO = 4
6090 01:25:17.925230 DQ_CA_OPEN = 0
6091 01:25:17.928370 DQ_SEMI_OPEN = 1
6092 01:25:17.928443 CA_SEMI_OPEN = 1
6093 01:25:17.931921 CA_FULL_RATE = 0
6094 01:25:17.935615 DQ_CKDIV4_EN = 0
6095 01:25:17.938437 CA_CKDIV4_EN = 1
6096 01:25:17.941642 CA_PREDIV_EN = 0
6097 01:25:17.945413 PH8_DLY = 0
6098 01:25:17.945489 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6099 01:25:17.948382 DQ_AAMCK_DIV = 0
6100 01:25:17.951554 CA_AAMCK_DIV = 0
6101 01:25:17.954891 CA_ADMCK_DIV = 4
6102 01:25:17.958558 DQ_TRACK_CA_EN = 0
6103 01:25:17.961503 CA_PICK = 800
6104 01:25:17.965384 CA_MCKIO = 400
6105 01:25:17.965479 MCKIO_SEMI = 400
6106 01:25:17.968275 PLL_FREQ = 3016
6107 01:25:17.971947 DQ_UI_PI_RATIO = 32
6108 01:25:17.975092 CA_UI_PI_RATIO = 32
6109 01:25:17.978202 ===================================
6110 01:25:17.981659 ===================================
6111 01:25:17.984682 memory_type:LPDDR4
6112 01:25:17.984763 GP_NUM : 10
6113 01:25:17.988037 SRAM_EN : 1
6114 01:25:17.991556 MD32_EN : 0
6115 01:25:17.994874 ===================================
6116 01:25:17.994973 [ANA_INIT] >>>>>>>>>>>>>>
6117 01:25:17.998345 <<<<<< [CONFIGURE PHASE]: ANA_TX
6118 01:25:18.001501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6119 01:25:18.004643 ===================================
6120 01:25:18.008271 data_rate = 800,PCW = 0X7400
6121 01:25:18.011781 ===================================
6122 01:25:18.014560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6123 01:25:18.021281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 01:25:18.031384 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 01:25:18.034872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6126 01:25:18.041509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6127 01:25:18.044611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6128 01:25:18.044687 [ANA_INIT] flow start
6129 01:25:18.048338 [ANA_INIT] PLL >>>>>>>>
6130 01:25:18.048426 [ANA_INIT] PLL <<<<<<<<
6131 01:25:18.051741 [ANA_INIT] MIDPI >>>>>>>>
6132 01:25:18.054927 [ANA_INIT] MIDPI <<<<<<<<
6133 01:25:18.058245 [ANA_INIT] DLL >>>>>>>>
6134 01:25:18.058376 [ANA_INIT] flow end
6135 01:25:18.061414 ============ LP4 DIFF to SE enter ============
6136 01:25:18.068129 ============ LP4 DIFF to SE exit ============
6137 01:25:18.068200 [ANA_INIT] <<<<<<<<<<<<<
6138 01:25:18.071175 [Flow] Enable top DCM control >>>>>
6139 01:25:18.074956 [Flow] Enable top DCM control <<<<<
6140 01:25:18.078348 Enable DLL master slave shuffle
6141 01:25:18.084855 ==============================================================
6142 01:25:18.084929 Gating Mode config
6143 01:25:18.091736 ==============================================================
6144 01:25:18.094714 Config description:
6145 01:25:18.104503 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6146 01:25:18.111318 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6147 01:25:18.114261 SELPH_MODE 0: By rank 1: By Phase
6148 01:25:18.121247 ==============================================================
6149 01:25:18.124591 GAT_TRACK_EN = 0
6150 01:25:18.128080 RX_GATING_MODE = 2
6151 01:25:18.128154 RX_GATING_TRACK_MODE = 2
6152 01:25:18.130977 SELPH_MODE = 1
6153 01:25:18.134431 PICG_EARLY_EN = 1
6154 01:25:18.137791 VALID_LAT_VALUE = 1
6155 01:25:18.144219 ==============================================================
6156 01:25:18.147602 Enter into Gating configuration >>>>
6157 01:25:18.150755 Exit from Gating configuration <<<<
6158 01:25:18.154153 Enter into DVFS_PRE_config >>>>>
6159 01:25:18.164344 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6160 01:25:18.167342 Exit from DVFS_PRE_config <<<<<
6161 01:25:18.170685 Enter into PICG configuration >>>>
6162 01:25:18.173940 Exit from PICG configuration <<<<
6163 01:25:18.177466 [RX_INPUT] configuration >>>>>
6164 01:25:18.180729 [RX_INPUT] configuration <<<<<
6165 01:25:18.184319 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6166 01:25:18.190996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6167 01:25:18.197420 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 01:25:18.200734 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 01:25:18.207393 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 01:25:18.214423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 01:25:18.217566 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6172 01:25:18.224112 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6173 01:25:18.227342 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6174 01:25:18.230640 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6175 01:25:18.233896 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6176 01:25:18.240792 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 01:25:18.243680 ===================================
6178 01:25:18.243754 LPDDR4 DRAM CONFIGURATION
6179 01:25:18.247144 ===================================
6180 01:25:18.250354 EX_ROW_EN[0] = 0x0
6181 01:25:18.253628 EX_ROW_EN[1] = 0x0
6182 01:25:18.253700 LP4Y_EN = 0x0
6183 01:25:18.257592 WORK_FSP = 0x0
6184 01:25:18.257664 WL = 0x2
6185 01:25:18.260530 RL = 0x2
6186 01:25:18.260615 BL = 0x2
6187 01:25:18.264027 RPST = 0x0
6188 01:25:18.264111 RD_PRE = 0x0
6189 01:25:18.267213 WR_PRE = 0x1
6190 01:25:18.267289 WR_PST = 0x0
6191 01:25:18.270480 DBI_WR = 0x0
6192 01:25:18.270557 DBI_RD = 0x0
6193 01:25:18.273947 OTF = 0x1
6194 01:25:18.277149 ===================================
6195 01:25:18.280699 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6196 01:25:18.283726 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6197 01:25:18.290342 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 01:25:18.294032 ===================================
6199 01:25:18.294117 LPDDR4 DRAM CONFIGURATION
6200 01:25:18.297149 ===================================
6201 01:25:18.300729 EX_ROW_EN[0] = 0x10
6202 01:25:18.303486 EX_ROW_EN[1] = 0x0
6203 01:25:18.303623 LP4Y_EN = 0x0
6204 01:25:18.306958 WORK_FSP = 0x0
6205 01:25:18.307029 WL = 0x2
6206 01:25:18.310524 RL = 0x2
6207 01:25:18.310617 BL = 0x2
6208 01:25:18.313680 RPST = 0x0
6209 01:25:18.313750 RD_PRE = 0x0
6210 01:25:18.317107 WR_PRE = 0x1
6211 01:25:18.317206 WR_PST = 0x0
6212 01:25:18.320498 DBI_WR = 0x0
6213 01:25:18.320568 DBI_RD = 0x0
6214 01:25:18.323472 OTF = 0x1
6215 01:25:18.326828 ===================================
6216 01:25:18.333343 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6217 01:25:18.336868 nWR fixed to 30
6218 01:25:18.336956 [ModeRegInit_LP4] CH0 RK0
6219 01:25:18.340220 [ModeRegInit_LP4] CH0 RK1
6220 01:25:18.343552 [ModeRegInit_LP4] CH1 RK0
6221 01:25:18.347190 [ModeRegInit_LP4] CH1 RK1
6222 01:25:18.347266 match AC timing 19
6223 01:25:18.350587 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6224 01:25:18.356946 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6225 01:25:18.360216 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6226 01:25:18.363842 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6227 01:25:18.370320 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6228 01:25:18.370393 ==
6229 01:25:18.373457 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 01:25:18.376702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 01:25:18.376790 ==
6232 01:25:18.383851 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 01:25:18.386778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6234 01:25:18.390167 [CA 0] Center 36 (8~64) winsize 57
6235 01:25:18.393814 [CA 1] Center 36 (8~64) winsize 57
6236 01:25:18.396925 [CA 2] Center 36 (8~64) winsize 57
6237 01:25:18.400659 [CA 3] Center 36 (8~64) winsize 57
6238 01:25:18.403805 [CA 4] Center 36 (8~64) winsize 57
6239 01:25:18.406923 [CA 5] Center 36 (8~64) winsize 57
6240 01:25:18.407024
6241 01:25:18.409999 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6242 01:25:18.410072
6243 01:25:18.413617 [CATrainingPosCal] consider 1 rank data
6244 01:25:18.416589 u2DelayCellTimex100 = 270/100 ps
6245 01:25:18.420156 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 01:25:18.423489 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 01:25:18.430439 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 01:25:18.433473 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 01:25:18.436674 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 01:25:18.440073 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 01:25:18.440165
6252 01:25:18.443462 CA PerBit enable=1, Macro0, CA PI delay=36
6253 01:25:18.443537
6254 01:25:18.446644 [CBTSetCACLKResult] CA Dly = 36
6255 01:25:18.446726 CS Dly: 1 (0~32)
6256 01:25:18.446789 ==
6257 01:25:18.450575 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 01:25:18.456637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 01:25:18.456715 ==
6260 01:25:18.460026 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 01:25:18.467250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 01:25:18.470084 [CA 0] Center 36 (8~64) winsize 57
6263 01:25:18.473400 [CA 1] Center 36 (8~64) winsize 57
6264 01:25:18.477089 [CA 2] Center 36 (8~64) winsize 57
6265 01:25:18.480417 [CA 3] Center 36 (8~64) winsize 57
6266 01:25:18.483393 [CA 4] Center 36 (8~64) winsize 57
6267 01:25:18.487205 [CA 5] Center 36 (8~64) winsize 57
6268 01:25:18.487281
6269 01:25:18.490154 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 01:25:18.490254
6271 01:25:18.493235 [CATrainingPosCal] consider 2 rank data
6272 01:25:18.496691 u2DelayCellTimex100 = 270/100 ps
6273 01:25:18.500267 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 01:25:18.503565 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 01:25:18.506506 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 01:25:18.510126 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 01:25:18.513387 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 01:25:18.516523 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 01:25:18.516604
6280 01:25:18.522839 CA PerBit enable=1, Macro0, CA PI delay=36
6281 01:25:18.522922
6282 01:25:18.526275 [CBTSetCACLKResult] CA Dly = 36
6283 01:25:18.526351 CS Dly: 1 (0~32)
6284 01:25:18.526419
6285 01:25:18.529780 ----->DramcWriteLeveling(PI) begin...
6286 01:25:18.529855 ==
6287 01:25:18.533126 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 01:25:18.536561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 01:25:18.539558 ==
6290 01:25:18.539707 Write leveling (Byte 0): 40 => 8
6291 01:25:18.542658 Write leveling (Byte 1): 40 => 8
6292 01:25:18.546334 DramcWriteLeveling(PI) end<-----
6293 01:25:18.546412
6294 01:25:18.546478 ==
6295 01:25:18.549536 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 01:25:18.555918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 01:25:18.556004 ==
6298 01:25:18.556067 [Gating] SW mode calibration
6299 01:25:18.566629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6300 01:25:18.569120 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6301 01:25:18.572891 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 01:25:18.579643 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 01:25:18.582655 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 01:25:18.586077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 01:25:18.592926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 01:25:18.595802 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 01:25:18.599291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 01:25:18.605863 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 01:25:18.609682 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 01:25:18.612761 Total UI for P1: 0, mck2ui 16
6311 01:25:18.615635 best dqsien dly found for B0: ( 0, 14, 24)
6312 01:25:18.619058 Total UI for P1: 0, mck2ui 16
6313 01:25:18.622608 best dqsien dly found for B1: ( 0, 14, 24)
6314 01:25:18.625943 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6315 01:25:18.629023 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6316 01:25:18.629103
6317 01:25:18.632225 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 01:25:18.638730 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 01:25:18.638826 [Gating] SW calibration Done
6320 01:25:18.638890 ==
6321 01:25:18.642180 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 01:25:18.648789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 01:25:18.648870 ==
6324 01:25:18.648933 RX Vref Scan: 0
6325 01:25:18.648992
6326 01:25:18.652240 RX Vref 0 -> 0, step: 1
6327 01:25:18.652320
6328 01:25:18.655818 RX Delay -410 -> 252, step: 16
6329 01:25:18.659123 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6330 01:25:18.662656 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6331 01:25:18.668943 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6332 01:25:18.672447 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6333 01:25:18.675105 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6334 01:25:18.678502 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6335 01:25:18.685468 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6336 01:25:18.688544 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6337 01:25:18.691991 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6338 01:25:18.695363 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6339 01:25:18.701655 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6340 01:25:18.705521 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6341 01:25:18.708464 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6342 01:25:18.711950 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6343 01:25:18.718836 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6344 01:25:18.722329 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6345 01:25:18.722432 ==
6346 01:25:18.725139 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 01:25:18.728508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 01:25:18.728607 ==
6349 01:25:18.731972 DQS Delay:
6350 01:25:18.732067 DQS0 = 27, DQS1 = 35
6351 01:25:18.732155 DQM Delay:
6352 01:25:18.735565 DQM0 = 8, DQM1 = 12
6353 01:25:18.735668 DQ Delay:
6354 01:25:18.738594 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6355 01:25:18.742238 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6356 01:25:18.745368 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6357 01:25:18.748733 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6358 01:25:18.748807
6359 01:25:18.748870
6360 01:25:18.748927 ==
6361 01:25:18.752113 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 01:25:18.755196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 01:25:18.755289 ==
6364 01:25:18.758546
6365 01:25:18.758639
6366 01:25:18.758724 TX Vref Scan disable
6367 01:25:18.761887 == TX Byte 0 ==
6368 01:25:18.765165 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 01:25:18.768710 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 01:25:18.772019 == TX Byte 1 ==
6371 01:25:18.775011 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 01:25:18.778415 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 01:25:18.778509 ==
6374 01:25:18.781898 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 01:25:18.784932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 01:25:18.788652 ==
6377 01:25:18.788725
6378 01:25:18.788784
6379 01:25:18.788841 TX Vref Scan disable
6380 01:25:18.791695 == TX Byte 0 ==
6381 01:25:18.795176 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 01:25:18.798648 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 01:25:18.801821 == TX Byte 1 ==
6384 01:25:18.805047 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 01:25:18.808188 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 01:25:18.808264
6387 01:25:18.811711 [DATLAT]
6388 01:25:18.811822 Freq=400, CH0 RK0
6389 01:25:18.811910
6390 01:25:18.814986 DATLAT Default: 0xf
6391 01:25:18.815100 0, 0xFFFF, sum = 0
6392 01:25:18.818333 1, 0xFFFF, sum = 0
6393 01:25:18.818409 2, 0xFFFF, sum = 0
6394 01:25:18.821357 3, 0xFFFF, sum = 0
6395 01:25:18.821457 4, 0xFFFF, sum = 0
6396 01:25:18.825011 5, 0xFFFF, sum = 0
6397 01:25:18.825083 6, 0xFFFF, sum = 0
6398 01:25:18.828251 7, 0xFFFF, sum = 0
6399 01:25:18.828353 8, 0xFFFF, sum = 0
6400 01:25:18.831914 9, 0xFFFF, sum = 0
6401 01:25:18.832016 10, 0xFFFF, sum = 0
6402 01:25:18.835234 11, 0xFFFF, sum = 0
6403 01:25:18.835350 12, 0xFFFF, sum = 0
6404 01:25:18.838122 13, 0x0, sum = 1
6405 01:25:18.838224 14, 0x0, sum = 2
6406 01:25:18.841574 15, 0x0, sum = 3
6407 01:25:18.841677 16, 0x0, sum = 4
6408 01:25:18.844919 best_step = 14
6409 01:25:18.844988
6410 01:25:18.845048 ==
6411 01:25:18.848217 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 01:25:18.851337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 01:25:18.851452 ==
6414 01:25:18.854950 RX Vref Scan: 1
6415 01:25:18.855067
6416 01:25:18.855133 RX Vref 0 -> 0, step: 1
6417 01:25:18.855195
6418 01:25:18.857993 RX Delay -311 -> 252, step: 8
6419 01:25:18.858092
6420 01:25:18.861732 Set Vref, RX VrefLevel [Byte0]: 54
6421 01:25:18.864934 [Byte1]: 55
6422 01:25:18.869407
6423 01:25:18.869504 Final RX Vref Byte 0 = 54 to rank0
6424 01:25:18.872670 Final RX Vref Byte 1 = 55 to rank0
6425 01:25:18.876195 Final RX Vref Byte 0 = 54 to rank1
6426 01:25:18.879237 Final RX Vref Byte 1 = 55 to rank1==
6427 01:25:18.882676 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 01:25:18.888934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 01:25:18.889039 ==
6430 01:25:18.889111 DQS Delay:
6431 01:25:18.892552 DQS0 = 28, DQS1 = 36
6432 01:25:18.892652 DQM Delay:
6433 01:25:18.892741 DQM0 = 11, DQM1 = 13
6434 01:25:18.895380 DQ Delay:
6435 01:25:18.898858 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6436 01:25:18.902323 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6437 01:25:18.902420 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6438 01:25:18.905798 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6439 01:25:18.909021
6440 01:25:18.909107
6441 01:25:18.915473 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6442 01:25:18.918955 CH0 RK0: MR19=C0C, MR18=CBB8
6443 01:25:18.925493 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6444 01:25:18.925580 ==
6445 01:25:18.928959 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 01:25:18.932309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 01:25:18.932416 ==
6448 01:25:18.935201 [Gating] SW mode calibration
6449 01:25:18.942069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6450 01:25:18.948657 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6451 01:25:18.951923 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 01:25:18.955395 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 01:25:18.961863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 01:25:18.964873 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 01:25:18.968318 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 01:25:18.975223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 01:25:18.978386 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 01:25:18.981964 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 01:25:18.988183 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 01:25:18.988379 Total UI for P1: 0, mck2ui 16
6461 01:25:18.994893 best dqsien dly found for B0: ( 0, 14, 24)
6462 01:25:18.995072 Total UI for P1: 0, mck2ui 16
6463 01:25:18.998113 best dqsien dly found for B1: ( 0, 14, 24)
6464 01:25:19.004779 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6465 01:25:19.008128 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6466 01:25:19.008204
6467 01:25:19.011714 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 01:25:19.015059 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 01:25:19.017815 [Gating] SW calibration Done
6470 01:25:19.017914 ==
6471 01:25:19.021360 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 01:25:19.025122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 01:25:19.025218 ==
6474 01:25:19.028114 RX Vref Scan: 0
6475 01:25:19.028181
6476 01:25:19.028278 RX Vref 0 -> 0, step: 1
6477 01:25:19.028368
6478 01:25:19.031295 RX Delay -410 -> 252, step: 16
6479 01:25:19.037634 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6480 01:25:19.041205 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6481 01:25:19.044751 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6482 01:25:19.047771 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6483 01:25:19.054449 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6484 01:25:19.057809 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6485 01:25:19.061222 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6486 01:25:19.065001 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6487 01:25:19.068214 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6488 01:25:19.074613 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6489 01:25:19.077962 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6490 01:25:19.081470 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6491 01:25:19.084836 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6492 01:25:19.091239 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6493 01:25:19.094772 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6494 01:25:19.098014 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6495 01:25:19.098122 ==
6496 01:25:19.101439 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 01:25:19.108130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 01:25:19.108224 ==
6499 01:25:19.108320 DQS Delay:
6500 01:25:19.110944 DQS0 = 19, DQS1 = 35
6501 01:25:19.111041 DQM Delay:
6502 01:25:19.111163 DQM0 = 5, DQM1 = 10
6503 01:25:19.114381 DQ Delay:
6504 01:25:19.117737 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6505 01:25:19.117816 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6506 01:25:19.121530 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6507 01:25:19.124636 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6508 01:25:19.124713
6509 01:25:19.124776
6510 01:25:19.128206 ==
6511 01:25:19.131503 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 01:25:19.134466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 01:25:19.134566 ==
6514 01:25:19.134658
6515 01:25:19.134748
6516 01:25:19.137738 TX Vref Scan disable
6517 01:25:19.137839 == TX Byte 0 ==
6518 01:25:19.141108 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6519 01:25:19.148174 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6520 01:25:19.148255 == TX Byte 1 ==
6521 01:25:19.150955 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 01:25:19.154306 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 01:25:19.157607 ==
6524 01:25:19.160922 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 01:25:19.164164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 01:25:19.164268 ==
6527 01:25:19.164336
6528 01:25:19.164397
6529 01:25:19.168086 TX Vref Scan disable
6530 01:25:19.168156 == TX Byte 0 ==
6531 01:25:19.171018 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6532 01:25:19.177741 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6533 01:25:19.177847 == TX Byte 1 ==
6534 01:25:19.181199 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 01:25:19.188120 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 01:25:19.188207
6537 01:25:19.188303 [DATLAT]
6538 01:25:19.188397 Freq=400, CH0 RK1
6539 01:25:19.188486
6540 01:25:19.191204 DATLAT Default: 0xe
6541 01:25:19.191302 0, 0xFFFF, sum = 0
6542 01:25:19.194382 1, 0xFFFF, sum = 0
6543 01:25:19.194482 2, 0xFFFF, sum = 0
6544 01:25:19.197957 3, 0xFFFF, sum = 0
6545 01:25:19.201144 4, 0xFFFF, sum = 0
6546 01:25:19.201221 5, 0xFFFF, sum = 0
6547 01:25:19.204579 6, 0xFFFF, sum = 0
6548 01:25:19.204684 7, 0xFFFF, sum = 0
6549 01:25:19.207439 8, 0xFFFF, sum = 0
6550 01:25:19.207539 9, 0xFFFF, sum = 0
6551 01:25:19.211016 10, 0xFFFF, sum = 0
6552 01:25:19.211113 11, 0xFFFF, sum = 0
6553 01:25:19.214171 12, 0xFFFF, sum = 0
6554 01:25:19.214271 13, 0x0, sum = 1
6555 01:25:19.217966 14, 0x0, sum = 2
6556 01:25:19.218040 15, 0x0, sum = 3
6557 01:25:19.220685 16, 0x0, sum = 4
6558 01:25:19.220759 best_step = 14
6559 01:25:19.220823
6560 01:25:19.220880 ==
6561 01:25:19.224080 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 01:25:19.227400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 01:25:19.230495 ==
6564 01:25:19.230595 RX Vref Scan: 0
6565 01:25:19.230684
6566 01:25:19.233807 RX Vref 0 -> 0, step: 1
6567 01:25:19.233904
6568 01:25:19.237280 RX Delay -311 -> 252, step: 8
6569 01:25:19.240484 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6570 01:25:19.247667 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6571 01:25:19.250564 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6572 01:25:19.253931 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6573 01:25:19.257441 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6574 01:25:19.263725 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6575 01:25:19.267479 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6576 01:25:19.270552 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6577 01:25:19.273704 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6578 01:25:19.280364 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6579 01:25:19.284077 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6580 01:25:19.286882 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6581 01:25:19.290255 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6582 01:25:19.296991 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6583 01:25:19.300300 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6584 01:25:19.303714 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6585 01:25:19.303785 ==
6586 01:25:19.306923 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 01:25:19.313891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 01:25:19.313988 ==
6589 01:25:19.314079 DQS Delay:
6590 01:25:19.317098 DQS0 = 24, DQS1 = 32
6591 01:25:19.317233 DQM Delay:
6592 01:25:19.317322 DQM0 = 8, DQM1 = 9
6593 01:25:19.320151 DQ Delay:
6594 01:25:19.320222 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6595 01:25:19.323839 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6596 01:25:19.326858 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6597 01:25:19.330095 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6598 01:25:19.330170
6599 01:25:19.330231
6600 01:25:19.340582 [DQSOSCAuto] RK1, (LSB)MR18= 0xba59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6601 01:25:19.343764 CH0 RK1: MR19=C0C, MR18=BA59
6602 01:25:19.347330 CH0_RK1: MR19=0xC0C, MR18=0xBA59, DQSOSC=386, MR23=63, INC=396, DEC=264
6603 01:25:19.350535 [RxdqsGatingPostProcess] freq 400
6604 01:25:19.356881 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6605 01:25:19.360357 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 01:25:19.363953 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 01:25:19.366972 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 01:25:19.370371 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 01:25:19.374353 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 01:25:19.377147 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 01:25:19.380497 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 01:25:19.383626 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 01:25:19.386846 Pre-setting of DQS Precalculation
6614 01:25:19.390287 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6615 01:25:19.390385 ==
6616 01:25:19.393783 Dram Type= 6, Freq= 0, CH_1, rank 0
6617 01:25:19.396941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 01:25:19.397014 ==
6619 01:25:19.404103 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 01:25:19.410622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6621 01:25:19.413585 [CA 0] Center 36 (8~64) winsize 57
6622 01:25:19.416957 [CA 1] Center 36 (8~64) winsize 57
6623 01:25:19.420230 [CA 2] Center 36 (8~64) winsize 57
6624 01:25:19.423825 [CA 3] Center 36 (8~64) winsize 57
6625 01:25:19.426954 [CA 4] Center 36 (8~64) winsize 57
6626 01:25:19.427047 [CA 5] Center 36 (8~64) winsize 57
6627 01:25:19.430166
6628 01:25:19.433332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6629 01:25:19.433400
6630 01:25:19.436628 [CATrainingPosCal] consider 1 rank data
6631 01:25:19.440167 u2DelayCellTimex100 = 270/100 ps
6632 01:25:19.443169 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 01:25:19.446946 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 01:25:19.449834 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 01:25:19.453232 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 01:25:19.456249 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 01:25:19.459713 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 01:25:19.459812
6639 01:25:19.462969 CA PerBit enable=1, Macro0, CA PI delay=36
6640 01:25:19.463092
6641 01:25:19.466447 [CBTSetCACLKResult] CA Dly = 36
6642 01:25:19.469966 CS Dly: 1 (0~32)
6643 01:25:19.470060 ==
6644 01:25:19.472889 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 01:25:19.476662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 01:25:19.476757 ==
6647 01:25:19.483345 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 01:25:19.489515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6649 01:25:19.493256 [CA 0] Center 36 (8~64) winsize 57
6650 01:25:19.493326 [CA 1] Center 36 (8~64) winsize 57
6651 01:25:19.496435 [CA 2] Center 36 (8~64) winsize 57
6652 01:25:19.499710 [CA 3] Center 36 (8~64) winsize 57
6653 01:25:19.503291 [CA 4] Center 36 (8~64) winsize 57
6654 01:25:19.506208 [CA 5] Center 36 (8~64) winsize 57
6655 01:25:19.506286
6656 01:25:19.509767 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6657 01:25:19.509868
6658 01:25:19.513324 [CATrainingPosCal] consider 2 rank data
6659 01:25:19.516209 u2DelayCellTimex100 = 270/100 ps
6660 01:25:19.519642 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 01:25:19.526220 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 01:25:19.529557 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 01:25:19.533135 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 01:25:19.536721 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 01:25:19.539801 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 01:25:19.539878
6667 01:25:19.543228 CA PerBit enable=1, Macro0, CA PI delay=36
6668 01:25:19.543329
6669 01:25:19.546214 [CBTSetCACLKResult] CA Dly = 36
6670 01:25:19.546313 CS Dly: 1 (0~32)
6671 01:25:19.549399
6672 01:25:19.553123 ----->DramcWriteLeveling(PI) begin...
6673 01:25:19.553225 ==
6674 01:25:19.556590 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 01:25:19.559514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 01:25:19.559638 ==
6677 01:25:19.562702 Write leveling (Byte 0): 40 => 8
6678 01:25:19.566646 Write leveling (Byte 1): 40 => 8
6679 01:25:19.569562 DramcWriteLeveling(PI) end<-----
6680 01:25:19.569669
6681 01:25:19.569805 ==
6682 01:25:19.573514 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 01:25:19.576331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 01:25:19.576400 ==
6685 01:25:19.579738 [Gating] SW mode calibration
6686 01:25:19.586581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6687 01:25:19.592830 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6688 01:25:19.596303 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 01:25:19.599630 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 01:25:19.602805 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 01:25:19.609750 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 01:25:19.613091 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 01:25:19.616071 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 01:25:19.623048 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 01:25:19.626169 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 01:25:19.629652 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 01:25:19.632818 Total UI for P1: 0, mck2ui 16
6698 01:25:19.636312 best dqsien dly found for B0: ( 0, 14, 24)
6699 01:25:19.639657 Total UI for P1: 0, mck2ui 16
6700 01:25:19.642904 best dqsien dly found for B1: ( 0, 14, 24)
6701 01:25:19.646177 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6702 01:25:19.649332 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6703 01:25:19.652758
6704 01:25:19.656039 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 01:25:19.659434 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 01:25:19.662871 [Gating] SW calibration Done
6707 01:25:19.662970 ==
6708 01:25:19.665985 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 01:25:19.669258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 01:25:19.669361 ==
6711 01:25:19.669452 RX Vref Scan: 0
6712 01:25:19.669540
6713 01:25:19.672657 RX Vref 0 -> 0, step: 1
6714 01:25:19.672726
6715 01:25:19.676039 RX Delay -410 -> 252, step: 16
6716 01:25:19.679476 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6717 01:25:19.686015 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6718 01:25:19.689532 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6719 01:25:19.692876 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6720 01:25:19.696428 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6721 01:25:19.702631 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6722 01:25:19.706292 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6723 01:25:19.709614 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6724 01:25:19.712365 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6725 01:25:19.716061 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6726 01:25:19.722544 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6727 01:25:19.725944 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6728 01:25:19.729869 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6729 01:25:19.736094 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6730 01:25:19.739372 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6731 01:25:19.743008 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6732 01:25:19.743105 ==
6733 01:25:19.745881 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 01:25:19.749409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 01:25:19.749510 ==
6736 01:25:19.752441 DQS Delay:
6737 01:25:19.752536 DQS0 = 35, DQS1 = 35
6738 01:25:19.756367 DQM Delay:
6739 01:25:19.756463 DQM0 = 17, DQM1 = 13
6740 01:25:19.759303 DQ Delay:
6741 01:25:19.759410 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6742 01:25:19.762618 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6743 01:25:19.765938 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6744 01:25:19.769069 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6745 01:25:19.769165
6746 01:25:19.769257
6747 01:25:19.772819 ==
6748 01:25:19.772921 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 01:25:19.779289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 01:25:19.779397 ==
6751 01:25:19.779493
6752 01:25:19.779583
6753 01:25:19.782601 TX Vref Scan disable
6754 01:25:19.782699 == TX Byte 0 ==
6755 01:25:19.785928 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 01:25:19.792381 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 01:25:19.792457 == TX Byte 1 ==
6758 01:25:19.795769 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 01:25:19.799156 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 01:25:19.802194 ==
6761 01:25:19.806108 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 01:25:19.808851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 01:25:19.808942 ==
6764 01:25:19.809005
6765 01:25:19.809088
6766 01:25:19.812435 TX Vref Scan disable
6767 01:25:19.812504 == TX Byte 0 ==
6768 01:25:19.815572 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 01:25:19.822316 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 01:25:19.822432 == TX Byte 1 ==
6771 01:25:19.825318 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 01:25:19.832214 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 01:25:19.832292
6774 01:25:19.832356 [DATLAT]
6775 01:25:19.832416 Freq=400, CH1 RK0
6776 01:25:19.832474
6777 01:25:19.835743 DATLAT Default: 0xf
6778 01:25:19.835838 0, 0xFFFF, sum = 0
6779 01:25:19.838690 1, 0xFFFF, sum = 0
6780 01:25:19.841714 2, 0xFFFF, sum = 0
6781 01:25:19.841817 3, 0xFFFF, sum = 0
6782 01:25:19.845608 4, 0xFFFF, sum = 0
6783 01:25:19.845713 5, 0xFFFF, sum = 0
6784 01:25:19.848923 6, 0xFFFF, sum = 0
6785 01:25:19.849023 7, 0xFFFF, sum = 0
6786 01:25:19.852189 8, 0xFFFF, sum = 0
6787 01:25:19.852264 9, 0xFFFF, sum = 0
6788 01:25:19.855307 10, 0xFFFF, sum = 0
6789 01:25:19.855407 11, 0xFFFF, sum = 0
6790 01:25:19.858558 12, 0xFFFF, sum = 0
6791 01:25:19.858654 13, 0x0, sum = 1
6792 01:25:19.861834 14, 0x0, sum = 2
6793 01:25:19.861937 15, 0x0, sum = 3
6794 01:25:19.865260 16, 0x0, sum = 4
6795 01:25:19.865358 best_step = 14
6796 01:25:19.865446
6797 01:25:19.865531 ==
6798 01:25:19.868931 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 01:25:19.871954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 01:25:19.875148 ==
6801 01:25:19.875243 RX Vref Scan: 1
6802 01:25:19.875333
6803 01:25:19.878939 RX Vref 0 -> 0, step: 1
6804 01:25:19.879032
6805 01:25:19.881843 RX Delay -311 -> 252, step: 8
6806 01:25:19.881937
6807 01:25:19.885308 Set Vref, RX VrefLevel [Byte0]: 53
6808 01:25:19.885406 [Byte1]: 49
6809 01:25:19.891107
6810 01:25:19.891213 Final RX Vref Byte 0 = 53 to rank0
6811 01:25:19.894473 Final RX Vref Byte 1 = 49 to rank0
6812 01:25:19.898035 Final RX Vref Byte 0 = 53 to rank1
6813 01:25:19.900642 Final RX Vref Byte 1 = 49 to rank1==
6814 01:25:19.904230 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 01:25:19.911129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 01:25:19.911241 ==
6817 01:25:19.911337 DQS Delay:
6818 01:25:19.914541 DQS0 = 32, DQS1 = 32
6819 01:25:19.914637 DQM Delay:
6820 01:25:19.914725 DQM0 = 13, DQM1 = 9
6821 01:25:19.917665 DQ Delay:
6822 01:25:19.921083 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6823 01:25:19.921188 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6824 01:25:19.924559 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6825 01:25:19.927414 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6826 01:25:19.927507
6827 01:25:19.930769
6828 01:25:19.937274 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc5, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6829 01:25:19.940582 CH1 RK0: MR19=C0C, MR18=8FC5
6830 01:25:19.947238 CH1_RK0: MR19=0xC0C, MR18=0x8FC5, DQSOSC=385, MR23=63, INC=398, DEC=265
6831 01:25:19.947340 ==
6832 01:25:19.950425 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 01:25:19.953967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 01:25:19.954065 ==
6835 01:25:19.957318 [Gating] SW mode calibration
6836 01:25:19.963755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6837 01:25:19.970817 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6838 01:25:19.973567 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 01:25:19.976879 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 01:25:19.983721 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 01:25:19.987399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 01:25:19.990112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 01:25:19.996600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 01:25:19.999956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 01:25:20.003388 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 01:25:20.009828 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 01:25:20.009935 Total UI for P1: 0, mck2ui 16
6848 01:25:20.016412 best dqsien dly found for B0: ( 0, 14, 24)
6849 01:25:20.016510 Total UI for P1: 0, mck2ui 16
6850 01:25:20.020010 best dqsien dly found for B1: ( 0, 14, 24)
6851 01:25:20.026778 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6852 01:25:20.030053 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6853 01:25:20.030156
6854 01:25:20.033423 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 01:25:20.036764 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 01:25:20.040191 [Gating] SW calibration Done
6857 01:25:20.040272 ==
6858 01:25:20.043130 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 01:25:20.046772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 01:25:20.046891 ==
6861 01:25:20.050276 RX Vref Scan: 0
6862 01:25:20.050414
6863 01:25:20.050521 RX Vref 0 -> 0, step: 1
6864 01:25:20.050612
6865 01:25:20.053148 RX Delay -410 -> 252, step: 16
6866 01:25:20.060258 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6867 01:25:20.063525 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6868 01:25:20.066447 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6869 01:25:20.069722 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6870 01:25:20.073314 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6871 01:25:20.080221 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6872 01:25:20.083506 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6873 01:25:20.086538 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6874 01:25:20.089674 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6875 01:25:20.096489 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6876 01:25:20.099877 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6877 01:25:20.103141 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6878 01:25:20.106407 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6879 01:25:20.113019 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6880 01:25:20.116628 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6881 01:25:20.119913 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6882 01:25:20.120020 ==
6883 01:25:20.123226 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 01:25:20.129578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 01:25:20.129651 ==
6886 01:25:20.129718 DQS Delay:
6887 01:25:20.133354 DQS0 = 35, DQS1 = 35
6888 01:25:20.133450 DQM Delay:
6889 01:25:20.133538 DQM0 = 18, DQM1 = 13
6890 01:25:20.136246 DQ Delay:
6891 01:25:20.139703 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6892 01:25:20.142755 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6893 01:25:20.146200 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6894 01:25:20.149770 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6895 01:25:20.149871
6896 01:25:20.149964
6897 01:25:20.150097 ==
6898 01:25:20.152920 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 01:25:20.156329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 01:25:20.156431 ==
6901 01:25:20.156521
6902 01:25:20.156621
6903 01:25:20.159468 TX Vref Scan disable
6904 01:25:20.159573 == TX Byte 0 ==
6905 01:25:20.162651 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6906 01:25:20.169322 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6907 01:25:20.169409 == TX Byte 1 ==
6908 01:25:20.172893 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 01:25:20.179137 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 01:25:20.179268 ==
6911 01:25:20.182505 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 01:25:20.185826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 01:25:20.185952 ==
6914 01:25:20.186074
6915 01:25:20.186190
6916 01:25:20.189501 TX Vref Scan disable
6917 01:25:20.189597 == TX Byte 0 ==
6918 01:25:20.195739 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6919 01:25:20.199233 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6920 01:25:20.199330 == TX Byte 1 ==
6921 01:25:20.206102 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 01:25:20.209423 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 01:25:20.209528
6924 01:25:20.209604 [DATLAT]
6925 01:25:20.212480 Freq=400, CH1 RK1
6926 01:25:20.212575
6927 01:25:20.212647 DATLAT Default: 0xe
6928 01:25:20.215720 0, 0xFFFF, sum = 0
6929 01:25:20.215842 1, 0xFFFF, sum = 0
6930 01:25:20.218944 2, 0xFFFF, sum = 0
6931 01:25:20.219073 3, 0xFFFF, sum = 0
6932 01:25:20.222294 4, 0xFFFF, sum = 0
6933 01:25:20.222419 5, 0xFFFF, sum = 0
6934 01:25:20.226000 6, 0xFFFF, sum = 0
6935 01:25:20.226127 7, 0xFFFF, sum = 0
6936 01:25:20.229190 8, 0xFFFF, sum = 0
6937 01:25:20.229319 9, 0xFFFF, sum = 0
6938 01:25:20.232595 10, 0xFFFF, sum = 0
6939 01:25:20.232692 11, 0xFFFF, sum = 0
6940 01:25:20.235990 12, 0xFFFF, sum = 0
6941 01:25:20.236112 13, 0x0, sum = 1
6942 01:25:20.239555 14, 0x0, sum = 2
6943 01:25:20.239674 15, 0x0, sum = 3
6944 01:25:20.242335 16, 0x0, sum = 4
6945 01:25:20.242458 best_step = 14
6946 01:25:20.242560
6947 01:25:20.242691 ==
6948 01:25:20.245737 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 01:25:20.252908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 01:25:20.253007 ==
6951 01:25:20.253096 RX Vref Scan: 0
6952 01:25:20.253184
6953 01:25:20.255806 RX Vref 0 -> 0, step: 1
6954 01:25:20.255904
6955 01:25:20.259131 RX Delay -311 -> 252, step: 8
6956 01:25:20.266193 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6957 01:25:20.269059 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6958 01:25:20.272663 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6959 01:25:20.275710 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6960 01:25:20.282321 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6961 01:25:20.285634 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6962 01:25:20.289092 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6963 01:25:20.292198 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6964 01:25:20.298956 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6965 01:25:20.302376 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6966 01:25:20.305275 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6967 01:25:20.308599 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6968 01:25:20.315451 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6969 01:25:20.318778 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6970 01:25:20.321911 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6971 01:25:20.325766 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6972 01:25:20.328611 ==
6973 01:25:20.328695 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 01:25:20.335428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 01:25:20.335529 ==
6976 01:25:20.335628 DQS Delay:
6977 01:25:20.338844 DQS0 = 28, DQS1 = 32
6978 01:25:20.338917 DQM Delay:
6979 01:25:20.342201 DQM0 = 10, DQM1 = 11
6980 01:25:20.342296 DQ Delay:
6981 01:25:20.345199 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6982 01:25:20.348485 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6983 01:25:20.352054 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6984 01:25:20.355489 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6985 01:25:20.355587
6986 01:25:20.355684
6987 01:25:20.361779 [DQSOSCAuto] RK1, (LSB)MR18= 0xc354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6988 01:25:20.365277 CH1 RK1: MR19=C0C, MR18=C354
6989 01:25:20.371909 CH1_RK1: MR19=0xC0C, MR18=0xC354, DQSOSC=385, MR23=63, INC=398, DEC=265
6990 01:25:20.375390 [RxdqsGatingPostProcess] freq 400
6991 01:25:20.378365 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6992 01:25:20.382152 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 01:25:20.384963 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 01:25:20.388880 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 01:25:20.391586 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 01:25:20.394850 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 01:25:20.398465 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 01:25:20.401697 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 01:25:20.405101 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 01:25:20.408265 Pre-setting of DQS Precalculation
7001 01:25:20.412324 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7002 01:25:20.421752 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7003 01:25:20.428362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7004 01:25:20.428482
7005 01:25:20.428555
7006 01:25:20.431632 [Calibration Summary] 800 Mbps
7007 01:25:20.431719 CH 0, Rank 0
7008 01:25:20.434762 SW Impedance : PASS
7009 01:25:20.434844 DUTY Scan : NO K
7010 01:25:20.438146 ZQ Calibration : PASS
7011 01:25:20.441773 Jitter Meter : NO K
7012 01:25:20.441889 CBT Training : PASS
7013 01:25:20.445426 Write leveling : PASS
7014 01:25:20.448018 RX DQS gating : PASS
7015 01:25:20.448119 RX DQ/DQS(RDDQC) : PASS
7016 01:25:20.451451 TX DQ/DQS : PASS
7017 01:25:20.451559 RX DATLAT : PASS
7018 01:25:20.454907 RX DQ/DQS(Engine): PASS
7019 01:25:20.458459 TX OE : NO K
7020 01:25:20.458576 All Pass.
7021 01:25:20.458678
7022 01:25:20.461647 CH 0, Rank 1
7023 01:25:20.461760 SW Impedance : PASS
7024 01:25:20.465131 DUTY Scan : NO K
7025 01:25:20.465220 ZQ Calibration : PASS
7026 01:25:20.468425 Jitter Meter : NO K
7027 01:25:20.471649 CBT Training : PASS
7028 01:25:20.471756 Write leveling : NO K
7029 01:25:20.474687 RX DQS gating : PASS
7030 01:25:20.478030 RX DQ/DQS(RDDQC) : PASS
7031 01:25:20.478138 TX DQ/DQS : PASS
7032 01:25:20.481576 RX DATLAT : PASS
7033 01:25:20.484869 RX DQ/DQS(Engine): PASS
7034 01:25:20.484971 TX OE : NO K
7035 01:25:20.487918 All Pass.
7036 01:25:20.487992
7037 01:25:20.488056 CH 1, Rank 0
7038 01:25:20.491685 SW Impedance : PASS
7039 01:25:20.491762 DUTY Scan : NO K
7040 01:25:20.494886 ZQ Calibration : PASS
7041 01:25:20.498203 Jitter Meter : NO K
7042 01:25:20.498306 CBT Training : PASS
7043 01:25:20.501507 Write leveling : PASS
7044 01:25:20.504636 RX DQS gating : PASS
7045 01:25:20.504740 RX DQ/DQS(RDDQC) : PASS
7046 01:25:20.507823 TX DQ/DQS : PASS
7047 01:25:20.507925 RX DATLAT : PASS
7048 01:25:20.511139 RX DQ/DQS(Engine): PASS
7049 01:25:20.514383 TX OE : NO K
7050 01:25:20.514500 All Pass.
7051 01:25:20.514597
7052 01:25:20.514687 CH 1, Rank 1
7053 01:25:20.517874 SW Impedance : PASS
7054 01:25:20.521300 DUTY Scan : NO K
7055 01:25:20.521408 ZQ Calibration : PASS
7056 01:25:20.524314 Jitter Meter : NO K
7057 01:25:20.528162 CBT Training : PASS
7058 01:25:20.528275 Write leveling : NO K
7059 01:25:20.531311 RX DQS gating : PASS
7060 01:25:20.534651 RX DQ/DQS(RDDQC) : PASS
7061 01:25:20.534726 TX DQ/DQS : PASS
7062 01:25:20.538091 RX DATLAT : PASS
7063 01:25:20.540924 RX DQ/DQS(Engine): PASS
7064 01:25:20.541065 TX OE : NO K
7065 01:25:20.544560 All Pass.
7066 01:25:20.544674
7067 01:25:20.544772 DramC Write-DBI off
7068 01:25:20.547867 PER_BANK_REFRESH: Hybrid Mode
7069 01:25:20.547979 TX_TRACKING: ON
7070 01:25:20.557630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7071 01:25:20.561261 [FAST_K] Save calibration result to emmc
7072 01:25:20.564551 dramc_set_vcore_voltage set vcore to 725000
7073 01:25:20.567801 Read voltage for 1600, 0
7074 01:25:20.567911 Vio18 = 0
7075 01:25:20.570873 Vcore = 725000
7076 01:25:20.570958 Vdram = 0
7077 01:25:20.571024 Vddq = 0
7078 01:25:20.574232 Vmddr = 0
7079 01:25:20.577577 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7080 01:25:20.584514 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7081 01:25:20.584628 MEM_TYPE=3, freq_sel=13
7082 01:25:20.587711 sv_algorithm_assistance_LP4_3733
7083 01:25:20.590799 ============ PULL DRAM RESETB DOWN ============
7084 01:25:20.598138 ========== PULL DRAM RESETB DOWN end =========
7085 01:25:20.600669 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7086 01:25:20.604350 ===================================
7087 01:25:20.607572 LPDDR4 DRAM CONFIGURATION
7088 01:25:20.610897 ===================================
7089 01:25:20.610998 EX_ROW_EN[0] = 0x0
7090 01:25:20.614147 EX_ROW_EN[1] = 0x0
7091 01:25:20.617516 LP4Y_EN = 0x0
7092 01:25:20.617686 WORK_FSP = 0x1
7093 01:25:20.620935 WL = 0x5
7094 01:25:20.621066 RL = 0x5
7095 01:25:20.624391 BL = 0x2
7096 01:25:20.624499 RPST = 0x0
7097 01:25:20.627780 RD_PRE = 0x0
7098 01:25:20.627881 WR_PRE = 0x1
7099 01:25:20.630947 WR_PST = 0x1
7100 01:25:20.631019 DBI_WR = 0x0
7101 01:25:20.633947 DBI_RD = 0x0
7102 01:25:20.634062 OTF = 0x1
7103 01:25:20.637104 ===================================
7104 01:25:20.640966 ===================================
7105 01:25:20.644116 ANA top config
7106 01:25:20.647364 ===================================
7107 01:25:20.647499 DLL_ASYNC_EN = 0
7108 01:25:20.650786 ALL_SLAVE_EN = 0
7109 01:25:20.654182 NEW_RANK_MODE = 1
7110 01:25:20.657324 DLL_IDLE_MODE = 1
7111 01:25:20.657426 LP45_APHY_COMB_EN = 1
7112 01:25:20.660829 TX_ODT_DIS = 0
7113 01:25:20.664129 NEW_8X_MODE = 1
7114 01:25:20.667171 ===================================
7115 01:25:20.670642 ===================================
7116 01:25:20.673871 data_rate = 3200
7117 01:25:20.677224 CKR = 1
7118 01:25:20.680687 DQ_P2S_RATIO = 8
7119 01:25:20.684137 ===================================
7120 01:25:20.684246 CA_P2S_RATIO = 8
7121 01:25:20.687343 DQ_CA_OPEN = 0
7122 01:25:20.690662 DQ_SEMI_OPEN = 0
7123 01:25:20.694246 CA_SEMI_OPEN = 0
7124 01:25:20.697504 CA_FULL_RATE = 0
7125 01:25:20.700567 DQ_CKDIV4_EN = 0
7126 01:25:20.700673 CA_CKDIV4_EN = 0
7127 01:25:20.703989 CA_PREDIV_EN = 0
7128 01:25:20.707516 PH8_DLY = 12
7129 01:25:20.711151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7130 01:25:20.713796 DQ_AAMCK_DIV = 4
7131 01:25:20.717381 CA_AAMCK_DIV = 4
7132 01:25:20.717478 CA_ADMCK_DIV = 4
7133 01:25:20.721151 DQ_TRACK_CA_EN = 0
7134 01:25:20.724026 CA_PICK = 1600
7135 01:25:20.727486 CA_MCKIO = 1600
7136 01:25:20.730743 MCKIO_SEMI = 0
7137 01:25:20.733685 PLL_FREQ = 3068
7138 01:25:20.737200 DQ_UI_PI_RATIO = 32
7139 01:25:20.737318 CA_UI_PI_RATIO = 0
7140 01:25:20.740800 ===================================
7141 01:25:20.743921 ===================================
7142 01:25:20.747368 memory_type:LPDDR4
7143 01:25:20.750794 GP_NUM : 10
7144 01:25:20.750906 SRAM_EN : 1
7145 01:25:20.753905 MD32_EN : 0
7146 01:25:20.757388 ===================================
7147 01:25:20.760652 [ANA_INIT] >>>>>>>>>>>>>>
7148 01:25:20.760746 <<<<<< [CONFIGURE PHASE]: ANA_TX
7149 01:25:20.767223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7150 01:25:20.770442 ===================================
7151 01:25:20.770560 data_rate = 3200,PCW = 0X7600
7152 01:25:20.774068 ===================================
7153 01:25:20.777266 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7154 01:25:20.784017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 01:25:20.790644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 01:25:20.794054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7157 01:25:20.797527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7158 01:25:20.800783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7159 01:25:20.803787 [ANA_INIT] flow start
7160 01:25:20.803858 [ANA_INIT] PLL >>>>>>>>
7161 01:25:20.807000 [ANA_INIT] PLL <<<<<<<<
7162 01:25:20.810328 [ANA_INIT] MIDPI >>>>>>>>
7163 01:25:20.813636 [ANA_INIT] MIDPI <<<<<<<<
7164 01:25:20.813765 [ANA_INIT] DLL >>>>>>>>
7165 01:25:20.817057 [ANA_INIT] DLL <<<<<<<<
7166 01:25:20.817160 [ANA_INIT] flow end
7167 01:25:20.823648 ============ LP4 DIFF to SE enter ============
7168 01:25:20.826998 ============ LP4 DIFF to SE exit ============
7169 01:25:20.830262 [ANA_INIT] <<<<<<<<<<<<<
7170 01:25:20.833589 [Flow] Enable top DCM control >>>>>
7171 01:25:20.837043 [Flow] Enable top DCM control <<<<<
7172 01:25:20.837152 Enable DLL master slave shuffle
7173 01:25:20.843772 ==============================================================
7174 01:25:20.847035 Gating Mode config
7175 01:25:20.850598 ==============================================================
7176 01:25:20.853884 Config description:
7177 01:25:20.863936 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7178 01:25:20.870642 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7179 01:25:20.873706 SELPH_MODE 0: By rank 1: By Phase
7180 01:25:20.880685 ==============================================================
7181 01:25:20.884115 GAT_TRACK_EN = 1
7182 01:25:20.887109 RX_GATING_MODE = 2
7183 01:25:20.890418 RX_GATING_TRACK_MODE = 2
7184 01:25:20.890522 SELPH_MODE = 1
7185 01:25:20.893593 PICG_EARLY_EN = 1
7186 01:25:20.896884 VALID_LAT_VALUE = 1
7187 01:25:20.904200 ==============================================================
7188 01:25:20.906932 Enter into Gating configuration >>>>
7189 01:25:20.910452 Exit from Gating configuration <<<<
7190 01:25:20.913814 Enter into DVFS_PRE_config >>>>>
7191 01:25:20.923658 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7192 01:25:20.926960 Exit from DVFS_PRE_config <<<<<
7193 01:25:20.930299 Enter into PICG configuration >>>>
7194 01:25:20.933369 Exit from PICG configuration <<<<
7195 01:25:20.936718 [RX_INPUT] configuration >>>>>
7196 01:25:20.940159 [RX_INPUT] configuration <<<<<
7197 01:25:20.943388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7198 01:25:20.950297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7199 01:25:20.956620 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 01:25:20.963630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 01:25:20.970239 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 01:25:20.973382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 01:25:20.980185 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7204 01:25:20.982988 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7205 01:25:20.986492 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7206 01:25:20.989717 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7207 01:25:20.996511 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7208 01:25:21.000326 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 01:25:21.002853 ===================================
7210 01:25:21.006483 LPDDR4 DRAM CONFIGURATION
7211 01:25:21.010117 ===================================
7212 01:25:21.010231 EX_ROW_EN[0] = 0x0
7213 01:25:21.012631 EX_ROW_EN[1] = 0x0
7214 01:25:21.012710 LP4Y_EN = 0x0
7215 01:25:21.016377 WORK_FSP = 0x1
7216 01:25:21.016492 WL = 0x5
7217 01:25:21.019776 RL = 0x5
7218 01:25:21.019859 BL = 0x2
7219 01:25:21.023167 RPST = 0x0
7220 01:25:21.026128 RD_PRE = 0x0
7221 01:25:21.026241 WR_PRE = 0x1
7222 01:25:21.029378 WR_PST = 0x1
7223 01:25:21.029454 DBI_WR = 0x0
7224 01:25:21.032909 DBI_RD = 0x0
7225 01:25:21.032999 OTF = 0x1
7226 01:25:21.036234 ===================================
7227 01:25:21.039465 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7228 01:25:21.046511 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7229 01:25:21.049763 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 01:25:21.052851 ===================================
7231 01:25:21.056051 LPDDR4 DRAM CONFIGURATION
7232 01:25:21.059454 ===================================
7233 01:25:21.059572 EX_ROW_EN[0] = 0x10
7234 01:25:21.063542 EX_ROW_EN[1] = 0x0
7235 01:25:21.063672 LP4Y_EN = 0x0
7236 01:25:21.066641 WORK_FSP = 0x1
7237 01:25:21.066728 WL = 0x5
7238 01:25:21.069416 RL = 0x5
7239 01:25:21.069526 BL = 0x2
7240 01:25:21.073289 RPST = 0x0
7241 01:25:21.073399 RD_PRE = 0x0
7242 01:25:21.076061 WR_PRE = 0x1
7243 01:25:21.076163 WR_PST = 0x1
7244 01:25:21.079313 DBI_WR = 0x0
7245 01:25:21.079423 DBI_RD = 0x0
7246 01:25:21.082669 OTF = 0x1
7247 01:25:21.085926 ===================================
7248 01:25:21.092566 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7249 01:25:21.092673 ==
7250 01:25:21.095962 Dram Type= 6, Freq= 0, CH_0, rank 0
7251 01:25:21.099339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7252 01:25:21.099442 ==
7253 01:25:21.102424 [Duty_Offset_Calibration]
7254 01:25:21.102534 B0:2 B1:1 CA:1
7255 01:25:21.102632
7256 01:25:21.105801 [DutyScan_Calibration_Flow] k_type=0
7257 01:25:21.117497
7258 01:25:21.117600 ==CLK 0==
7259 01:25:21.120737 Final CLK duty delay cell = 0
7260 01:25:21.124259 [0] MAX Duty = 5156%(X100), DQS PI = 22
7261 01:25:21.127170 [0] MIN Duty = 4907%(X100), DQS PI = 0
7262 01:25:21.127278 [0] AVG Duty = 5031%(X100)
7263 01:25:21.130758
7264 01:25:21.130863 CH0 CLK Duty spec in!! Max-Min= 249%
7265 01:25:21.137001 [DutyScan_Calibration_Flow] ====Done====
7266 01:25:21.137090
7267 01:25:21.140095 [DutyScan_Calibration_Flow] k_type=1
7268 01:25:21.156196
7269 01:25:21.156352 ==DQS 0 ==
7270 01:25:21.159662 Final DQS duty delay cell = -4
7271 01:25:21.163128 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7272 01:25:21.166322 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7273 01:25:21.169604 [-4] AVG Duty = 4891%(X100)
7274 01:25:21.169713
7275 01:25:21.169804 ==DQS 1 ==
7276 01:25:21.173063 Final DQS duty delay cell = 0
7277 01:25:21.176395 [0] MAX Duty = 5218%(X100), DQS PI = 22
7278 01:25:21.179671 [0] MIN Duty = 5062%(X100), DQS PI = 32
7279 01:25:21.183109 [0] AVG Duty = 5140%(X100)
7280 01:25:21.183216
7281 01:25:21.186330 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7282 01:25:21.186436
7283 01:25:21.189677 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7284 01:25:21.192936 [DutyScan_Calibration_Flow] ====Done====
7285 01:25:21.193024
7286 01:25:21.196075 [DutyScan_Calibration_Flow] k_type=3
7287 01:25:21.213172
7288 01:25:21.213344 ==DQM 0 ==
7289 01:25:21.216589 Final DQM duty delay cell = 0
7290 01:25:21.219548 [0] MAX Duty = 5187%(X100), DQS PI = 26
7291 01:25:21.222900 [0] MIN Duty = 4907%(X100), DQS PI = 56
7292 01:25:21.226210 [0] AVG Duty = 5047%(X100)
7293 01:25:21.226317
7294 01:25:21.226424 ==DQM 1 ==
7295 01:25:21.229450 Final DQM duty delay cell = -4
7296 01:25:21.232900 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7297 01:25:21.236471 [-4] MIN Duty = 4813%(X100), DQS PI = 34
7298 01:25:21.239746 [-4] AVG Duty = 4906%(X100)
7299 01:25:21.239824
7300 01:25:21.242732 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7301 01:25:21.242834
7302 01:25:21.246437 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7303 01:25:21.249497 [DutyScan_Calibration_Flow] ====Done====
7304 01:25:21.249606
7305 01:25:21.252733 [DutyScan_Calibration_Flow] k_type=2
7306 01:25:21.270956
7307 01:25:21.271068 ==DQ 0 ==
7308 01:25:21.273423 Final DQ duty delay cell = 0
7309 01:25:21.277293 [0] MAX Duty = 5062%(X100), DQS PI = 24
7310 01:25:21.280268 [0] MIN Duty = 4907%(X100), DQS PI = 0
7311 01:25:21.280345 [0] AVG Duty = 4984%(X100)
7312 01:25:21.283682
7313 01:25:21.283773 ==DQ 1 ==
7314 01:25:21.287133 Final DQ duty delay cell = 0
7315 01:25:21.290401 [0] MAX Duty = 5125%(X100), DQS PI = 6
7316 01:25:21.294216 [0] MIN Duty = 4938%(X100), DQS PI = 34
7317 01:25:21.294328 [0] AVG Duty = 5031%(X100)
7318 01:25:21.294419
7319 01:25:21.297111 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7320 01:25:21.297182
7321 01:25:21.300453 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7322 01:25:21.306951 [DutyScan_Calibration_Flow] ====Done====
7323 01:25:21.307056 ==
7324 01:25:21.310339 Dram Type= 6, Freq= 0, CH_1, rank 0
7325 01:25:21.313541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 01:25:21.313646 ==
7327 01:25:21.316892 [Duty_Offset_Calibration]
7328 01:25:21.316997 B0:1 B1:0 CA:0
7329 01:25:21.317086
7330 01:25:21.320171 [DutyScan_Calibration_Flow] k_type=0
7331 01:25:21.329705
7332 01:25:21.329782 ==CLK 0==
7333 01:25:21.333170 Final CLK duty delay cell = -4
7334 01:25:21.336493 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7335 01:25:21.339683 [-4] MIN Duty = 4875%(X100), DQS PI = 2
7336 01:25:21.343188 [-4] AVG Duty = 4937%(X100)
7337 01:25:21.343288
7338 01:25:21.346769 CH1 CLK Duty spec in!! Max-Min= 125%
7339 01:25:21.349886 [DutyScan_Calibration_Flow] ====Done====
7340 01:25:21.349988
7341 01:25:21.353136 [DutyScan_Calibration_Flow] k_type=1
7342 01:25:21.369962
7343 01:25:21.370047 ==DQS 0 ==
7344 01:25:21.373146 Final DQS duty delay cell = 0
7345 01:25:21.376508 [0] MAX Duty = 5094%(X100), DQS PI = 16
7346 01:25:21.379917 [0] MIN Duty = 4844%(X100), DQS PI = 48
7347 01:25:21.379989 [0] AVG Duty = 4969%(X100)
7348 01:25:21.382922
7349 01:25:21.383017 ==DQS 1 ==
7350 01:25:21.386515 Final DQS duty delay cell = 0
7351 01:25:21.389873 [0] MAX Duty = 5249%(X100), DQS PI = 16
7352 01:25:21.393368 [0] MIN Duty = 4938%(X100), DQS PI = 10
7353 01:25:21.393474 [0] AVG Duty = 5093%(X100)
7354 01:25:21.396270
7355 01:25:21.399566 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7356 01:25:21.399675
7357 01:25:21.403316 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7358 01:25:21.406268 [DutyScan_Calibration_Flow] ====Done====
7359 01:25:21.406372
7360 01:25:21.409555 [DutyScan_Calibration_Flow] k_type=3
7361 01:25:21.426447
7362 01:25:21.426561 ==DQM 0 ==
7363 01:25:21.429849 Final DQM duty delay cell = 0
7364 01:25:21.433150 [0] MAX Duty = 5218%(X100), DQS PI = 18
7365 01:25:21.436628 [0] MIN Duty = 4969%(X100), DQS PI = 48
7366 01:25:21.440147 [0] AVG Duty = 5093%(X100)
7367 01:25:21.440223
7368 01:25:21.440300 ==DQM 1 ==
7369 01:25:21.443097 Final DQM duty delay cell = 0
7370 01:25:21.446589 [0] MAX Duty = 5093%(X100), DQS PI = 16
7371 01:25:21.449845 [0] MIN Duty = 4907%(X100), DQS PI = 50
7372 01:25:21.453574 [0] AVG Duty = 5000%(X100)
7373 01:25:21.453670
7374 01:25:21.456799 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7375 01:25:21.456894
7376 01:25:21.460438 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7377 01:25:21.463180 [DutyScan_Calibration_Flow] ====Done====
7378 01:25:21.463289
7379 01:25:21.466588 [DutyScan_Calibration_Flow] k_type=2
7380 01:25:21.483147
7381 01:25:21.483250 ==DQ 0 ==
7382 01:25:21.486053 Final DQ duty delay cell = -4
7383 01:25:21.490149 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7384 01:25:21.493073 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7385 01:25:21.496512 [-4] AVG Duty = 4968%(X100)
7386 01:25:21.496614
7387 01:25:21.496705 ==DQ 1 ==
7388 01:25:21.499608 Final DQ duty delay cell = 0
7389 01:25:21.503231 [0] MAX Duty = 5156%(X100), DQS PI = 18
7390 01:25:21.506013 [0] MIN Duty = 4938%(X100), DQS PI = 8
7391 01:25:21.506089 [0] AVG Duty = 5047%(X100)
7392 01:25:21.509700
7393 01:25:21.513111 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7394 01:25:21.513209
7395 01:25:21.516484 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7396 01:25:21.519278 [DutyScan_Calibration_Flow] ====Done====
7397 01:25:21.522927 nWR fixed to 30
7398 01:25:21.523025 [ModeRegInit_LP4] CH0 RK0
7399 01:25:21.526194 [ModeRegInit_LP4] CH0 RK1
7400 01:25:21.529630 [ModeRegInit_LP4] CH1 RK0
7401 01:25:21.532437 [ModeRegInit_LP4] CH1 RK1
7402 01:25:21.532509 match AC timing 5
7403 01:25:21.539471 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7404 01:25:21.542782 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7405 01:25:21.546169 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7406 01:25:21.552653 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7407 01:25:21.556074 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7408 01:25:21.556169 [MiockJmeterHQA]
7409 01:25:21.556257
7410 01:25:21.559132 [DramcMiockJmeter] u1RxGatingPI = 0
7411 01:25:21.562528 0 : 4255, 4026
7412 01:25:21.562629 4 : 4252, 4026
7413 01:25:21.566361 8 : 4252, 4027
7414 01:25:21.566465 12 : 4252, 4027
7415 01:25:21.566556 16 : 4253, 4027
7416 01:25:21.569613 20 : 4363, 4138
7417 01:25:21.569683 24 : 4252, 4027
7418 01:25:21.572479 28 : 4362, 4137
7419 01:25:21.572575 32 : 4252, 4027
7420 01:25:21.576006 36 : 4252, 4027
7421 01:25:21.576100 40 : 4253, 4026
7422 01:25:21.576187 44 : 4255, 4029
7423 01:25:21.579218 48 : 4363, 4137
7424 01:25:21.579317 52 : 4253, 4027
7425 01:25:21.582502 56 : 4363, 4137
7426 01:25:21.582597 60 : 4250, 4026
7427 01:25:21.586020 64 : 4250, 4027
7428 01:25:21.586089 68 : 4250, 4027
7429 01:25:21.589246 72 : 4363, 4137
7430 01:25:21.589341 76 : 4250, 4027
7431 01:25:21.589403 80 : 4361, 4137
7432 01:25:21.592443 84 : 4250, 4027
7433 01:25:21.592535 88 : 4250, 124
7434 01:25:21.596021 92 : 4361, 0
7435 01:25:21.596119 96 : 4252, 0
7436 01:25:21.596206 100 : 4361, 0
7437 01:25:21.599061 104 : 4250, 0
7438 01:25:21.599155 108 : 4250, 0
7439 01:25:21.602519 112 : 4361, 0
7440 01:25:21.602620 116 : 4361, 0
7441 01:25:21.602710 120 : 4248, 0
7442 01:25:21.605790 124 : 4250, 0
7443 01:25:21.605883 128 : 4250, 0
7444 01:25:21.608788 132 : 4250, 0
7445 01:25:21.608855 136 : 4250, 0
7446 01:25:21.608914 140 : 4250, 0
7447 01:25:21.612101 144 : 4252, 0
7448 01:25:21.612169 148 : 4360, 0
7449 01:25:21.615837 152 : 4361, 0
7450 01:25:21.615938 156 : 4249, 0
7451 01:25:21.616029 160 : 4250, 0
7452 01:25:21.619092 164 : 4361, 0
7453 01:25:21.619197 168 : 4360, 0
7454 01:25:21.619292 172 : 4250, 0
7455 01:25:21.622142 176 : 4250, 0
7456 01:25:21.622239 180 : 4250, 0
7457 01:25:21.625837 184 : 4253, 0
7458 01:25:21.625939 188 : 4252, 0
7459 01:25:21.626029 192 : 4250, 0
7460 01:25:21.629255 196 : 4252, 0
7461 01:25:21.629355 200 : 4366, 0
7462 01:25:21.632716 204 : 4361, 1237
7463 01:25:21.632789 208 : 4363, 4115
7464 01:25:21.635495 212 : 4247, 4025
7465 01:25:21.635590 216 : 4360, 4138
7466 01:25:21.635686 220 : 4250, 4027
7467 01:25:21.638965 224 : 4253, 4026
7468 01:25:21.639058 228 : 4250, 4027
7469 01:25:21.642416 232 : 4252, 4030
7470 01:25:21.642519 236 : 4249, 4027
7471 01:25:21.645949 240 : 4250, 4026
7472 01:25:21.646045 244 : 4250, 4027
7473 01:25:21.649334 248 : 4252, 4030
7474 01:25:21.649430 252 : 4249, 4027
7475 01:25:21.652558 256 : 4360, 4137
7476 01:25:21.652625 260 : 4361, 4137
7477 01:25:21.656120 264 : 4250, 4027
7478 01:25:21.656185 268 : 4363, 4140
7479 01:25:21.656243 272 : 4361, 4137
7480 01:25:21.659279 276 : 4250, 4026
7481 01:25:21.659373 280 : 4250, 4027
7482 01:25:21.662736 284 : 4252, 4030
7483 01:25:21.662832 288 : 4249, 4027
7484 01:25:21.665837 292 : 4250, 4026
7485 01:25:21.665933 296 : 4250, 4027
7486 01:25:21.669466 300 : 4252, 4030
7487 01:25:21.669561 304 : 4249, 4027
7488 01:25:21.672337 308 : 4360, 4092
7489 01:25:21.672403 312 : 4363, 1790
7490 01:25:21.672462
7491 01:25:21.675844 MIOCK jitter meter ch=0
7492 01:25:21.675916
7493 01:25:21.678877 1T = (312-88) = 224 dly cells
7494 01:25:21.682670 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7495 01:25:21.685633 ==
7496 01:25:21.685745 Dram Type= 6, Freq= 0, CH_0, rank 0
7497 01:25:21.692369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 01:25:21.692444 ==
7499 01:25:21.695733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 01:25:21.702903 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 01:25:21.705886 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 01:25:21.712333 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 01:25:21.720393 [CA 0] Center 42 (12~73) winsize 62
7504 01:25:21.723715 [CA 1] Center 42 (12~73) winsize 62
7505 01:25:21.727497 [CA 2] Center 38 (8~68) winsize 61
7506 01:25:21.730354 [CA 3] Center 37 (8~67) winsize 60
7507 01:25:21.733748 [CA 4] Center 36 (6~66) winsize 61
7508 01:25:21.737488 [CA 5] Center 35 (6~64) winsize 59
7509 01:25:21.737582
7510 01:25:21.740217 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7511 01:25:21.740309
7512 01:25:21.743548 [CATrainingPosCal] consider 1 rank data
7513 01:25:21.747194 u2DelayCellTimex100 = 290/100 ps
7514 01:25:21.750717 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 01:25:21.757100 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7516 01:25:21.760261 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7517 01:25:21.763814 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7518 01:25:21.766803 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7519 01:25:21.770157 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7520 01:25:21.770265
7521 01:25:21.773656 CA PerBit enable=1, Macro0, CA PI delay=35
7522 01:25:21.773743
7523 01:25:21.777193 [CBTSetCACLKResult] CA Dly = 35
7524 01:25:21.780323 CS Dly: 9 (0~40)
7525 01:25:21.783400 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 01:25:21.786861 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 01:25:21.786937 ==
7528 01:25:21.790084 Dram Type= 6, Freq= 0, CH_0, rank 1
7529 01:25:21.793897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 01:25:21.796502 ==
7531 01:25:21.800476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 01:25:21.803403 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 01:25:21.809798 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 01:25:21.813448 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 01:25:21.823579 [CA 0] Center 42 (12~72) winsize 61
7536 01:25:21.827051 [CA 1] Center 42 (12~73) winsize 62
7537 01:25:21.830469 [CA 2] Center 37 (8~67) winsize 60
7538 01:25:21.833610 [CA 3] Center 37 (7~68) winsize 62
7539 01:25:21.836941 [CA 4] Center 35 (6~65) winsize 60
7540 01:25:21.840304 [CA 5] Center 35 (5~65) winsize 61
7541 01:25:21.840426
7542 01:25:21.843720 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7543 01:25:21.843816
7544 01:25:21.847166 [CATrainingPosCal] consider 2 rank data
7545 01:25:21.850767 u2DelayCellTimex100 = 290/100 ps
7546 01:25:21.853742 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7547 01:25:21.860179 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7548 01:25:21.863970 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7549 01:25:21.867342 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7550 01:25:21.870013 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7551 01:25:21.873774 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7552 01:25:21.873849
7553 01:25:21.877136 CA PerBit enable=1, Macro0, CA PI delay=35
7554 01:25:21.877235
7555 01:25:21.879949 [CBTSetCACLKResult] CA Dly = 35
7556 01:25:21.883383 CS Dly: 10 (0~42)
7557 01:25:21.886788 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 01:25:21.890189 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 01:25:21.890288
7560 01:25:21.893731 ----->DramcWriteLeveling(PI) begin...
7561 01:25:21.893833 ==
7562 01:25:21.896977 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 01:25:21.900242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 01:25:21.904173 ==
7565 01:25:21.904258 Write leveling (Byte 0): 35 => 35
7566 01:25:21.907049 Write leveling (Byte 1): 29 => 29
7567 01:25:21.910168 DramcWriteLeveling(PI) end<-----
7568 01:25:21.910279
7569 01:25:21.910370 ==
7570 01:25:21.913660 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 01:25:21.920271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 01:25:21.920364 ==
7573 01:25:21.920462 [Gating] SW mode calibration
7574 01:25:21.930202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7575 01:25:21.933349 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7576 01:25:21.937053 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 01:25:21.943776 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7578 01:25:21.946917 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7579 01:25:21.950019 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7580 01:25:21.957041 1 4 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
7581 01:25:21.960108 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7582 01:25:21.963433 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7583 01:25:21.970618 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7584 01:25:21.973661 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7585 01:25:21.977135 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 01:25:21.983507 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7587 01:25:21.986604 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
7588 01:25:21.989866 1 5 16 | B1->B0 | 3434 2827 | 1 1 | (1 0) (0 0)
7589 01:25:21.996635 1 5 20 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
7590 01:25:22.000211 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7591 01:25:22.003094 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 01:25:22.010258 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7593 01:25:22.013038 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7594 01:25:22.017309 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
7595 01:25:22.023457 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7596 01:25:22.027095 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (1 1)
7597 01:25:22.030029 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7598 01:25:22.036755 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 01:25:22.039876 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 01:25:22.043327 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 01:25:22.050280 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 01:25:22.053396 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 01:25:22.056549 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7604 01:25:22.063428 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7605 01:25:22.066755 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7606 01:25:22.070155 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7607 01:25:22.076112 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 01:25:22.079468 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 01:25:22.083057 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 01:25:22.089825 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 01:25:22.092839 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 01:25:22.096273 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 01:25:22.099675 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 01:25:22.106396 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 01:25:22.109975 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 01:25:22.113153 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 01:25:22.119188 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 01:25:22.122781 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7619 01:25:22.126181 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 01:25:22.132580 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7621 01:25:22.135790 Total UI for P1: 0, mck2ui 16
7622 01:25:22.139288 best dqsien dly found for B0: ( 1, 9, 10)
7623 01:25:22.142303 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7624 01:25:22.145527 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 01:25:22.148959 Total UI for P1: 0, mck2ui 16
7626 01:25:22.152352 best dqsien dly found for B1: ( 1, 9, 18)
7627 01:25:22.155687 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7628 01:25:22.159461 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7629 01:25:22.162796
7630 01:25:22.165602 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7631 01:25:22.169031 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7632 01:25:22.172386 [Gating] SW calibration Done
7633 01:25:22.172457 ==
7634 01:25:22.175908 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 01:25:22.179347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 01:25:22.179446 ==
7637 01:25:22.179547 RX Vref Scan: 0
7638 01:25:22.179664
7639 01:25:22.182585 RX Vref 0 -> 0, step: 1
7640 01:25:22.182682
7641 01:25:22.186152 RX Delay 0 -> 252, step: 8
7642 01:25:22.188990 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7643 01:25:22.192485 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7644 01:25:22.199234 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7645 01:25:22.202631 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7646 01:25:22.205859 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7647 01:25:22.209283 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7648 01:25:22.212258 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7649 01:25:22.215842 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7650 01:25:22.222714 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7651 01:25:22.225687 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7652 01:25:22.229271 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7653 01:25:22.232522 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7654 01:25:22.235675 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7655 01:25:22.242116 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7656 01:25:22.245806 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7657 01:25:22.249115 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7658 01:25:22.249190 ==
7659 01:25:22.252271 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 01:25:22.255734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 01:25:22.259247 ==
7662 01:25:22.259341 DQS Delay:
7663 01:25:22.259428 DQS0 = 0, DQS1 = 0
7664 01:25:22.262026 DQM Delay:
7665 01:25:22.262091 DQM0 = 137, DQM1 = 129
7666 01:25:22.265485 DQ Delay:
7667 01:25:22.268653 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7668 01:25:22.271979 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7669 01:25:22.275208 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7670 01:25:22.278842 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7671 01:25:22.278941
7672 01:25:22.279062
7673 01:25:22.279167 ==
7674 01:25:22.282201 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 01:25:22.285532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 01:25:22.285628 ==
7677 01:25:22.285719
7678 01:25:22.289057
7679 01:25:22.289168 TX Vref Scan disable
7680 01:25:22.292460 == TX Byte 0 ==
7681 01:25:22.295501 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7682 01:25:22.299242 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7683 01:25:22.302016 == TX Byte 1 ==
7684 01:25:22.305334 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7685 01:25:22.308752 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7686 01:25:22.308831 ==
7687 01:25:22.311787 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 01:25:22.318562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 01:25:22.318663 ==
7690 01:25:22.330793
7691 01:25:22.333913 TX Vref early break, caculate TX vref
7692 01:25:22.337463 TX Vref=16, minBit 4, minWin=22, winSum=375
7693 01:25:22.340616 TX Vref=18, minBit 7, minWin=23, winSum=387
7694 01:25:22.344427 TX Vref=20, minBit 0, minWin=23, winSum=402
7695 01:25:22.347215 TX Vref=22, minBit 1, minWin=24, winSum=407
7696 01:25:22.350593 TX Vref=24, minBit 2, minWin=25, winSum=415
7697 01:25:22.354118 TX Vref=26, minBit 0, minWin=25, winSum=425
7698 01:25:22.361015 TX Vref=28, minBit 0, minWin=25, winSum=422
7699 01:25:22.363959 TX Vref=30, minBit 1, minWin=24, winSum=411
7700 01:25:22.367361 TX Vref=32, minBit 1, minWin=24, winSum=406
7701 01:25:22.370745 TX Vref=34, minBit 6, minWin=23, winSum=393
7702 01:25:22.377268 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
7703 01:25:22.377383
7704 01:25:22.380854 Final TX Range 0 Vref 26
7705 01:25:22.380960
7706 01:25:22.381048 ==
7707 01:25:22.384218 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 01:25:22.387184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 01:25:22.387278 ==
7710 01:25:22.387376
7711 01:25:22.387470
7712 01:25:22.390837 TX Vref Scan disable
7713 01:25:22.397146 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7714 01:25:22.397251 == TX Byte 0 ==
7715 01:25:22.400719 u2DelayCellOfst[0]=10 cells (3 PI)
7716 01:25:22.403826 u2DelayCellOfst[1]=13 cells (4 PI)
7717 01:25:22.407512 u2DelayCellOfst[2]=10 cells (3 PI)
7718 01:25:22.410495 u2DelayCellOfst[3]=6 cells (2 PI)
7719 01:25:22.413829 u2DelayCellOfst[4]=6 cells (2 PI)
7720 01:25:22.417293 u2DelayCellOfst[5]=0 cells (0 PI)
7721 01:25:22.417381 u2DelayCellOfst[6]=16 cells (5 PI)
7722 01:25:22.420716 u2DelayCellOfst[7]=13 cells (4 PI)
7723 01:25:22.427230 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7724 01:25:22.430699 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7725 01:25:22.430770 == TX Byte 1 ==
7726 01:25:22.433940 u2DelayCellOfst[8]=0 cells (0 PI)
7727 01:25:22.437094 u2DelayCellOfst[9]=0 cells (0 PI)
7728 01:25:22.440733 u2DelayCellOfst[10]=10 cells (3 PI)
7729 01:25:22.443942 u2DelayCellOfst[11]=3 cells (1 PI)
7730 01:25:22.447599 u2DelayCellOfst[12]=10 cells (3 PI)
7731 01:25:22.450184 u2DelayCellOfst[13]=10 cells (3 PI)
7732 01:25:22.454005 u2DelayCellOfst[14]=13 cells (4 PI)
7733 01:25:22.457463 u2DelayCellOfst[15]=10 cells (3 PI)
7734 01:25:22.460841 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7735 01:25:22.467459 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7736 01:25:22.467568 DramC Write-DBI on
7737 01:25:22.467678 ==
7738 01:25:22.470651 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 01:25:22.473517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 01:25:22.473613 ==
7741 01:25:22.473700
7742 01:25:22.477068
7743 01:25:22.477142 TX Vref Scan disable
7744 01:25:22.480721 == TX Byte 0 ==
7745 01:25:22.483887 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7746 01:25:22.486808 == TX Byte 1 ==
7747 01:25:22.490318 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7748 01:25:22.490429 DramC Write-DBI off
7749 01:25:22.493567
7750 01:25:22.493636 [DATLAT]
7751 01:25:22.493695 Freq=1600, CH0 RK0
7752 01:25:22.493776
7753 01:25:22.496806 DATLAT Default: 0xf
7754 01:25:22.496875 0, 0xFFFF, sum = 0
7755 01:25:22.500515 1, 0xFFFF, sum = 0
7756 01:25:22.500612 2, 0xFFFF, sum = 0
7757 01:25:22.503786 3, 0xFFFF, sum = 0
7758 01:25:22.503862 4, 0xFFFF, sum = 0
7759 01:25:22.506771 5, 0xFFFF, sum = 0
7760 01:25:22.510271 6, 0xFFFF, sum = 0
7761 01:25:22.510390 7, 0xFFFF, sum = 0
7762 01:25:22.513567 8, 0xFFFF, sum = 0
7763 01:25:22.513637 9, 0xFFFF, sum = 0
7764 01:25:22.516855 10, 0xFFFF, sum = 0
7765 01:25:22.516951 11, 0xFFFF, sum = 0
7766 01:25:22.520195 12, 0xFFFF, sum = 0
7767 01:25:22.520271 13, 0xFFFF, sum = 0
7768 01:25:22.523709 14, 0x0, sum = 1
7769 01:25:22.523806 15, 0x0, sum = 2
7770 01:25:22.527069 16, 0x0, sum = 3
7771 01:25:22.527136 17, 0x0, sum = 4
7772 01:25:22.530716 best_step = 15
7773 01:25:22.530809
7774 01:25:22.530895 ==
7775 01:25:22.533851 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 01:25:22.536913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 01:25:22.536984 ==
7778 01:25:22.537046 RX Vref Scan: 1
7779 01:25:22.537101
7780 01:25:22.540516 Set Vref Range= 24 -> 127
7781 01:25:22.540606
7782 01:25:22.543935 RX Vref 24 -> 127, step: 1
7783 01:25:22.544027
7784 01:25:22.546673 RX Delay 19 -> 252, step: 4
7785 01:25:22.546775
7786 01:25:22.550226 Set Vref, RX VrefLevel [Byte0]: 24
7787 01:25:22.553906 [Byte1]: 24
7788 01:25:22.554008
7789 01:25:22.556704 Set Vref, RX VrefLevel [Byte0]: 25
7790 01:25:22.560401 [Byte1]: 25
7791 01:25:22.560514
7792 01:25:22.563289 Set Vref, RX VrefLevel [Byte0]: 26
7793 01:25:22.566833 [Byte1]: 26
7794 01:25:22.570594
7795 01:25:22.570703 Set Vref, RX VrefLevel [Byte0]: 27
7796 01:25:22.574147 [Byte1]: 27
7797 01:25:22.578255
7798 01:25:22.578326 Set Vref, RX VrefLevel [Byte0]: 28
7799 01:25:22.581345 [Byte1]: 28
7800 01:25:22.585322
7801 01:25:22.585433 Set Vref, RX VrefLevel [Byte0]: 29
7802 01:25:22.588844 [Byte1]: 29
7803 01:25:22.593387
7804 01:25:22.593485 Set Vref, RX VrefLevel [Byte0]: 30
7805 01:25:22.596794 [Byte1]: 30
7806 01:25:22.600786
7807 01:25:22.600869 Set Vref, RX VrefLevel [Byte0]: 31
7808 01:25:22.604081 [Byte1]: 31
7809 01:25:22.608482
7810 01:25:22.608581 Set Vref, RX VrefLevel [Byte0]: 32
7811 01:25:22.611909 [Byte1]: 32
7812 01:25:22.616052
7813 01:25:22.616149 Set Vref, RX VrefLevel [Byte0]: 33
7814 01:25:22.618920 [Byte1]: 33
7815 01:25:22.623314
7816 01:25:22.623406 Set Vref, RX VrefLevel [Byte0]: 34
7817 01:25:22.626497 [Byte1]: 34
7818 01:25:22.631249
7819 01:25:22.631328 Set Vref, RX VrefLevel [Byte0]: 35
7820 01:25:22.634412 [Byte1]: 35
7821 01:25:22.638627
7822 01:25:22.638710 Set Vref, RX VrefLevel [Byte0]: 36
7823 01:25:22.641834 [Byte1]: 36
7824 01:25:22.646326
7825 01:25:22.646405 Set Vref, RX VrefLevel [Byte0]: 37
7826 01:25:22.649541 [Byte1]: 37
7827 01:25:22.653564
7828 01:25:22.653648 Set Vref, RX VrefLevel [Byte0]: 38
7829 01:25:22.656897 [Byte1]: 38
7830 01:25:22.661436
7831 01:25:22.661515 Set Vref, RX VrefLevel [Byte0]: 39
7832 01:25:22.664656 [Byte1]: 39
7833 01:25:22.668892
7834 01:25:22.668971 Set Vref, RX VrefLevel [Byte0]: 40
7835 01:25:22.672429 [Byte1]: 40
7836 01:25:22.676611
7837 01:25:22.679931 Set Vref, RX VrefLevel [Byte0]: 41
7838 01:25:22.680055 [Byte1]: 41
7839 01:25:22.684408
7840 01:25:22.684502 Set Vref, RX VrefLevel [Byte0]: 42
7841 01:25:22.687342 [Byte1]: 42
7842 01:25:22.691903
7843 01:25:22.691997 Set Vref, RX VrefLevel [Byte0]: 43
7844 01:25:22.695106 [Byte1]: 43
7845 01:25:22.699106
7846 01:25:22.699262 Set Vref, RX VrefLevel [Byte0]: 44
7847 01:25:22.702209 [Byte1]: 44
7848 01:25:22.706908
7849 01:25:22.706982 Set Vref, RX VrefLevel [Byte0]: 45
7850 01:25:22.710183 [Byte1]: 45
7851 01:25:22.714211
7852 01:25:22.714282 Set Vref, RX VrefLevel [Byte0]: 46
7853 01:25:22.717770 [Byte1]: 46
7854 01:25:22.722224
7855 01:25:22.722297 Set Vref, RX VrefLevel [Byte0]: 47
7856 01:25:22.725045 [Byte1]: 47
7857 01:25:22.729494
7858 01:25:22.729564 Set Vref, RX VrefLevel [Byte0]: 48
7859 01:25:22.732568 [Byte1]: 48
7860 01:25:22.737208
7861 01:25:22.737280 Set Vref, RX VrefLevel [Byte0]: 49
7862 01:25:22.740479 [Byte1]: 49
7863 01:25:22.744707
7864 01:25:22.744797 Set Vref, RX VrefLevel [Byte0]: 50
7865 01:25:22.747686 [Byte1]: 50
7866 01:25:22.752202
7867 01:25:22.752277 Set Vref, RX VrefLevel [Byte0]: 51
7868 01:25:22.755713 [Byte1]: 51
7869 01:25:22.759552
7870 01:25:22.759642 Set Vref, RX VrefLevel [Byte0]: 52
7871 01:25:22.763033 [Byte1]: 52
7872 01:25:22.767530
7873 01:25:22.767612 Set Vref, RX VrefLevel [Byte0]: 53
7874 01:25:22.770680 [Byte1]: 53
7875 01:25:22.774880
7876 01:25:22.774949 Set Vref, RX VrefLevel [Byte0]: 54
7877 01:25:22.778516 [Byte1]: 54
7878 01:25:22.782653
7879 01:25:22.782726 Set Vref, RX VrefLevel [Byte0]: 55
7880 01:25:22.785780 [Byte1]: 55
7881 01:25:22.790343
7882 01:25:22.790414 Set Vref, RX VrefLevel [Byte0]: 56
7883 01:25:22.793347 [Byte1]: 56
7884 01:25:22.797491
7885 01:25:22.797561 Set Vref, RX VrefLevel [Byte0]: 57
7886 01:25:22.801207 [Byte1]: 57
7887 01:25:22.805050
7888 01:25:22.805150 Set Vref, RX VrefLevel [Byte0]: 58
7889 01:25:22.808535 [Byte1]: 58
7890 01:25:22.812785
7891 01:25:22.812854 Set Vref, RX VrefLevel [Byte0]: 59
7892 01:25:22.815926 [Byte1]: 59
7893 01:25:22.820584
7894 01:25:22.820664 Set Vref, RX VrefLevel [Byte0]: 60
7895 01:25:22.823499 [Byte1]: 60
7896 01:25:22.827790
7897 01:25:22.827865 Set Vref, RX VrefLevel [Byte0]: 61
7898 01:25:22.831270 [Byte1]: 61
7899 01:25:22.835655
7900 01:25:22.835739 Set Vref, RX VrefLevel [Byte0]: 62
7901 01:25:22.839049 [Byte1]: 62
7902 01:25:22.842914
7903 01:25:22.842989 Set Vref, RX VrefLevel [Byte0]: 63
7904 01:25:22.846244 [Byte1]: 63
7905 01:25:22.850837
7906 01:25:22.850915 Set Vref, RX VrefLevel [Byte0]: 64
7907 01:25:22.853806 [Byte1]: 64
7908 01:25:22.858296
7909 01:25:22.858370 Set Vref, RX VrefLevel [Byte0]: 65
7910 01:25:22.861628 [Byte1]: 65
7911 01:25:22.865634
7912 01:25:22.865712 Set Vref, RX VrefLevel [Byte0]: 66
7913 01:25:22.869184 [Byte1]: 66
7914 01:25:22.873726
7915 01:25:22.873805 Set Vref, RX VrefLevel [Byte0]: 67
7916 01:25:22.876362 [Byte1]: 67
7917 01:25:22.880931
7918 01:25:22.881061 Set Vref, RX VrefLevel [Byte0]: 68
7919 01:25:22.884261 [Byte1]: 68
7920 01:25:22.888290
7921 01:25:22.888387 Set Vref, RX VrefLevel [Byte0]: 69
7922 01:25:22.891459 [Byte1]: 69
7923 01:25:22.895840
7924 01:25:22.895918 Set Vref, RX VrefLevel [Byte0]: 70
7925 01:25:22.899527 [Byte1]: 70
7926 01:25:22.903475
7927 01:25:22.903554 Set Vref, RX VrefLevel [Byte0]: 71
7928 01:25:22.910030 [Byte1]: 71
7929 01:25:22.910101
7930 01:25:22.913511 Set Vref, RX VrefLevel [Byte0]: 72
7931 01:25:22.916622 [Byte1]: 72
7932 01:25:22.916692
7933 01:25:22.920117 Set Vref, RX VrefLevel [Byte0]: 73
7934 01:25:22.923519 [Byte1]: 73
7935 01:25:22.923639
7936 01:25:22.927136 Set Vref, RX VrefLevel [Byte0]: 74
7937 01:25:22.930203 [Byte1]: 74
7938 01:25:22.934314
7939 01:25:22.934384 Set Vref, RX VrefLevel [Byte0]: 75
7940 01:25:22.937031 [Byte1]: 75
7941 01:25:22.941614
7942 01:25:22.941700 Final RX Vref Byte 0 = 59 to rank0
7943 01:25:22.945019 Final RX Vref Byte 1 = 60 to rank0
7944 01:25:22.948227 Final RX Vref Byte 0 = 59 to rank1
7945 01:25:22.951370 Final RX Vref Byte 1 = 60 to rank1==
7946 01:25:22.954927 Dram Type= 6, Freq= 0, CH_0, rank 0
7947 01:25:22.961396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 01:25:22.961478 ==
7949 01:25:22.961542 DQS Delay:
7950 01:25:22.961607 DQS0 = 0, DQS1 = 0
7951 01:25:22.964762 DQM Delay:
7952 01:25:22.964834 DQM0 = 134, DQM1 = 127
7953 01:25:22.968346 DQ Delay:
7954 01:25:22.971579 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7955 01:25:22.974754 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
7956 01:25:22.977864 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7957 01:25:22.981398 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7958 01:25:22.981472
7959 01:25:22.981533
7960 01:25:22.981590
7961 01:25:22.984695 [DramC_TX_OE_Calibration] TA2
7962 01:25:22.988197 Original DQ_B0 (3 6) =30, OEN = 27
7963 01:25:22.991206 Original DQ_B1 (3 6) =30, OEN = 27
7964 01:25:22.994459 24, 0x0, End_B0=24 End_B1=24
7965 01:25:22.994533 25, 0x0, End_B0=25 End_B1=25
7966 01:25:22.998054 26, 0x0, End_B0=26 End_B1=26
7967 01:25:23.001389 27, 0x0, End_B0=27 End_B1=27
7968 01:25:23.004848 28, 0x0, End_B0=28 End_B1=28
7969 01:25:23.004923 29, 0x0, End_B0=29 End_B1=29
7970 01:25:23.007869 30, 0x0, End_B0=30 End_B1=30
7971 01:25:23.011097 31, 0x4141, End_B0=30 End_B1=30
7972 01:25:23.014587 Byte0 end_step=30 best_step=27
7973 01:25:23.017948 Byte1 end_step=30 best_step=27
7974 01:25:23.021053 Byte0 TX OE(2T, 0.5T) = (3, 3)
7975 01:25:23.021127 Byte1 TX OE(2T, 0.5T) = (3, 3)
7976 01:25:23.024668
7977 01:25:23.024739
7978 01:25:23.031134 [DQSOSCAuto] RK0, (LSB)MR18= 0x2621, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
7979 01:25:23.034459 CH0 RK0: MR19=303, MR18=2621
7980 01:25:23.041436 CH0_RK0: MR19=0x303, MR18=0x2621, DQSOSC=390, MR23=63, INC=24, DEC=16
7981 01:25:23.041545
7982 01:25:23.044683 ----->DramcWriteLeveling(PI) begin...
7983 01:25:23.044760 ==
7984 01:25:23.048308 Dram Type= 6, Freq= 0, CH_0, rank 1
7985 01:25:23.050963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 01:25:23.051046 ==
7987 01:25:23.054825 Write leveling (Byte 0): 36 => 36
7988 01:25:23.057677 Write leveling (Byte 1): 30 => 30
7989 01:25:23.061750 DramcWriteLeveling(PI) end<-----
7990 01:25:23.061825
7991 01:25:23.061893 ==
7992 01:25:23.064776 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 01:25:23.067526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 01:25:23.067632 ==
7995 01:25:23.071505 [Gating] SW mode calibration
7996 01:25:23.078237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7997 01:25:23.084603 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7998 01:25:23.088167 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7999 01:25:23.090873 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8000 01:25:23.097923 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 01:25:23.101226 1 4 12 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
8002 01:25:23.104275 1 4 16 | B1->B0 | 2929 3636 | 1 0 | (1 1) (0 0)
8003 01:25:23.111436 1 4 20 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
8004 01:25:23.114663 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8005 01:25:23.117920 1 4 28 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
8006 01:25:23.124300 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
8007 01:25:23.127557 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8008 01:25:23.131008 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 01:25:23.137297 1 5 12 | B1->B0 | 3434 3534 | 1 1 | (1 0) (0 0)
8010 01:25:23.140587 1 5 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 0) (0 0)
8011 01:25:23.144106 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8012 01:25:23.150899 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8013 01:25:23.153991 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
8014 01:25:23.157196 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8015 01:25:23.164036 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 01:25:23.167426 1 6 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8017 01:25:23.170589 1 6 12 | B1->B0 | 2424 3534 | 0 1 | (0 0) (0 0)
8018 01:25:23.177346 1 6 16 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
8019 01:25:23.180310 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 01:25:23.184308 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8021 01:25:23.190622 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 01:25:23.193915 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 01:25:23.197524 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 01:25:23.203660 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 01:25:23.207209 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8026 01:25:23.210611 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8027 01:25:23.213654 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8028 01:25:23.220466 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 01:25:23.224078 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 01:25:23.227136 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 01:25:23.234021 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 01:25:23.237247 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 01:25:23.240729 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 01:25:23.247631 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 01:25:23.250668 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 01:25:23.253911 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 01:25:23.260724 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 01:25:23.263806 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 01:25:23.267635 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 01:25:23.274042 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 01:25:23.277092 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8042 01:25:23.280859 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8043 01:25:23.284083 Total UI for P1: 0, mck2ui 16
8044 01:25:23.287083 best dqsien dly found for B0: ( 1, 9, 12)
8045 01:25:23.290346 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 01:25:23.294029 Total UI for P1: 0, mck2ui 16
8047 01:25:23.297293 best dqsien dly found for B1: ( 1, 9, 14)
8048 01:25:23.300709 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8049 01:25:23.307497 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8050 01:25:23.307577
8051 01:25:23.310323 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8052 01:25:23.313919 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8053 01:25:23.317544 [Gating] SW calibration Done
8054 01:25:23.317610 ==
8055 01:25:23.320727 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 01:25:23.323789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 01:25:23.323858 ==
8058 01:25:23.327265 RX Vref Scan: 0
8059 01:25:23.327349
8060 01:25:23.327421 RX Vref 0 -> 0, step: 1
8061 01:25:23.327477
8062 01:25:23.330537 RX Delay 0 -> 252, step: 8
8063 01:25:23.333972 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8064 01:25:23.337178 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8065 01:25:23.343505 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8066 01:25:23.346758 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8067 01:25:23.350377 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8068 01:25:23.354037 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8069 01:25:23.356934 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8070 01:25:23.363847 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8071 01:25:23.367113 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8072 01:25:23.370600 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8073 01:25:23.373506 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8074 01:25:23.376848 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8075 01:25:23.383497 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8076 01:25:23.387218 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8077 01:25:23.390506 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8078 01:25:23.393380 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8079 01:25:23.393451 ==
8080 01:25:23.396751 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 01:25:23.403738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 01:25:23.403835 ==
8083 01:25:23.403900 DQS Delay:
8084 01:25:23.406750 DQS0 = 0, DQS1 = 0
8085 01:25:23.406817 DQM Delay:
8086 01:25:23.409949 DQM0 = 137, DQM1 = 129
8087 01:25:23.410020 DQ Delay:
8088 01:25:23.413519 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8089 01:25:23.416759 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8090 01:25:23.419928 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8091 01:25:23.423203 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8092 01:25:23.423270
8093 01:25:23.423329
8094 01:25:23.423385 ==
8095 01:25:23.426651 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 01:25:23.433787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 01:25:23.433863 ==
8098 01:25:23.433930
8099 01:25:23.433990
8100 01:25:23.434046 TX Vref Scan disable
8101 01:25:23.437000 == TX Byte 0 ==
8102 01:25:23.440256 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8103 01:25:23.443247 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8104 01:25:23.446501 == TX Byte 1 ==
8105 01:25:23.450100 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8106 01:25:23.453356 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8107 01:25:23.456524 ==
8108 01:25:23.459958 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 01:25:23.463111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 01:25:23.463185 ==
8111 01:25:23.476009
8112 01:25:23.479524 TX Vref early break, caculate TX vref
8113 01:25:23.483019 TX Vref=16, minBit 0, minWin=23, winSum=387
8114 01:25:23.486156 TX Vref=18, minBit 1, minWin=23, winSum=391
8115 01:25:23.489420 TX Vref=20, minBit 2, minWin=24, winSum=405
8116 01:25:23.492979 TX Vref=22, minBit 1, minWin=24, winSum=412
8117 01:25:23.496560 TX Vref=24, minBit 1, minWin=25, winSum=421
8118 01:25:23.503025 TX Vref=26, minBit 2, minWin=25, winSum=424
8119 01:25:23.506109 TX Vref=28, minBit 3, minWin=25, winSum=428
8120 01:25:23.509266 TX Vref=30, minBit 1, minWin=24, winSum=418
8121 01:25:23.513070 TX Vref=32, minBit 4, minWin=24, winSum=407
8122 01:25:23.516488 TX Vref=34, minBit 0, minWin=24, winSum=398
8123 01:25:23.523064 [TxChooseVref] Worse bit 3, Min win 25, Win sum 428, Final Vref 28
8124 01:25:23.523142
8125 01:25:23.526349 Final TX Range 0 Vref 28
8126 01:25:23.526426
8127 01:25:23.526488 ==
8128 01:25:23.529230 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 01:25:23.532881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 01:25:23.532963 ==
8131 01:25:23.533027
8132 01:25:23.533085
8133 01:25:23.536277 TX Vref Scan disable
8134 01:25:23.542453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8135 01:25:23.542526 == TX Byte 0 ==
8136 01:25:23.546046 u2DelayCellOfst[0]=13 cells (4 PI)
8137 01:25:23.549552 u2DelayCellOfst[1]=16 cells (5 PI)
8138 01:25:23.552772 u2DelayCellOfst[2]=13 cells (4 PI)
8139 01:25:23.555704 u2DelayCellOfst[3]=13 cells (4 PI)
8140 01:25:23.558927 u2DelayCellOfst[4]=10 cells (3 PI)
8141 01:25:23.562491 u2DelayCellOfst[5]=0 cells (0 PI)
8142 01:25:23.566256 u2DelayCellOfst[6]=20 cells (6 PI)
8143 01:25:23.569100 u2DelayCellOfst[7]=20 cells (6 PI)
8144 01:25:23.572986 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8145 01:25:23.576204 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8146 01:25:23.576277 == TX Byte 1 ==
8147 01:25:23.579086 u2DelayCellOfst[8]=0 cells (0 PI)
8148 01:25:23.582417 u2DelayCellOfst[9]=0 cells (0 PI)
8149 01:25:23.585795 u2DelayCellOfst[10]=6 cells (2 PI)
8150 01:25:23.589338 u2DelayCellOfst[11]=3 cells (1 PI)
8151 01:25:23.592497 u2DelayCellOfst[12]=10 cells (3 PI)
8152 01:25:23.595948 u2DelayCellOfst[13]=10 cells (3 PI)
8153 01:25:23.599052 u2DelayCellOfst[14]=13 cells (4 PI)
8154 01:25:23.602503 u2DelayCellOfst[15]=10 cells (3 PI)
8155 01:25:23.605857 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8156 01:25:23.612522 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8157 01:25:23.612601 DramC Write-DBI on
8158 01:25:23.612668 ==
8159 01:25:23.615916 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 01:25:23.619439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 01:25:23.622614 ==
8162 01:25:23.622691
8163 01:25:23.622753
8164 01:25:23.622810 TX Vref Scan disable
8165 01:25:23.625836 == TX Byte 0 ==
8166 01:25:23.628985 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8167 01:25:23.632316 == TX Byte 1 ==
8168 01:25:23.635473 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8169 01:25:23.639323 DramC Write-DBI off
8170 01:25:23.639401
8171 01:25:23.639479 [DATLAT]
8172 01:25:23.639539 Freq=1600, CH0 RK1
8173 01:25:23.639632
8174 01:25:23.642154 DATLAT Default: 0xf
8175 01:25:23.642220 0, 0xFFFF, sum = 0
8176 01:25:23.645601 1, 0xFFFF, sum = 0
8177 01:25:23.648973 2, 0xFFFF, sum = 0
8178 01:25:23.649045 3, 0xFFFF, sum = 0
8179 01:25:23.652610 4, 0xFFFF, sum = 0
8180 01:25:23.652682 5, 0xFFFF, sum = 0
8181 01:25:23.655903 6, 0xFFFF, sum = 0
8182 01:25:23.655978 7, 0xFFFF, sum = 0
8183 01:25:23.658808 8, 0xFFFF, sum = 0
8184 01:25:23.658881 9, 0xFFFF, sum = 0
8185 01:25:23.662192 10, 0xFFFF, sum = 0
8186 01:25:23.662266 11, 0xFFFF, sum = 0
8187 01:25:23.665723 12, 0xFFFF, sum = 0
8188 01:25:23.665791 13, 0xFFFF, sum = 0
8189 01:25:23.668946 14, 0x0, sum = 1
8190 01:25:23.669025 15, 0x0, sum = 2
8191 01:25:23.672219 16, 0x0, sum = 3
8192 01:25:23.672292 17, 0x0, sum = 4
8193 01:25:23.675828 best_step = 15
8194 01:25:23.675912
8195 01:25:23.676042 ==
8196 01:25:23.678853 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 01:25:23.682792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 01:25:23.682864 ==
8199 01:25:23.682923 RX Vref Scan: 0
8200 01:25:23.685512
8201 01:25:23.685577 RX Vref 0 -> 0, step: 1
8202 01:25:23.685635
8203 01:25:23.689007 RX Delay 19 -> 252, step: 4
8204 01:25:23.692415 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8205 01:25:23.698827 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8206 01:25:23.702231 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8207 01:25:23.705732 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8208 01:25:23.709085 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8209 01:25:23.712146 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8210 01:25:23.718976 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8211 01:25:23.721851 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8212 01:25:23.725448 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8213 01:25:23.728650 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8214 01:25:23.732133 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8215 01:25:23.739615 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8216 01:25:23.741931 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8217 01:25:23.745238 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8218 01:25:23.748667 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8219 01:25:23.752020 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8220 01:25:23.755896 ==
8221 01:25:23.755967 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 01:25:23.762208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 01:25:23.762279 ==
8224 01:25:23.762350 DQS Delay:
8225 01:25:23.765359 DQS0 = 0, DQS1 = 0
8226 01:25:23.765440 DQM Delay:
8227 01:25:23.769122 DQM0 = 134, DQM1 = 127
8228 01:25:23.769263 DQ Delay:
8229 01:25:23.772354 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8230 01:25:23.775239 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8231 01:25:23.778697 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8232 01:25:23.781869 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8233 01:25:23.781938
8234 01:25:23.781997
8235 01:25:23.782060
8236 01:25:23.785517 [DramC_TX_OE_Calibration] TA2
8237 01:25:23.788659 Original DQ_B0 (3 6) =30, OEN = 27
8238 01:25:23.791959 Original DQ_B1 (3 6) =30, OEN = 27
8239 01:25:23.795760 24, 0x0, End_B0=24 End_B1=24
8240 01:25:23.798503 25, 0x0, End_B0=25 End_B1=25
8241 01:25:23.798575 26, 0x0, End_B0=26 End_B1=26
8242 01:25:23.802083 27, 0x0, End_B0=27 End_B1=27
8243 01:25:23.805121 28, 0x0, End_B0=28 End_B1=28
8244 01:25:23.808727 29, 0x0, End_B0=29 End_B1=29
8245 01:25:23.808795 30, 0x0, End_B0=30 End_B1=30
8246 01:25:23.811976 31, 0x4141, End_B0=30 End_B1=30
8247 01:25:23.815308 Byte0 end_step=30 best_step=27
8248 01:25:23.818869 Byte1 end_step=30 best_step=27
8249 01:25:23.822087 Byte0 TX OE(2T, 0.5T) = (3, 3)
8250 01:25:23.825615 Byte1 TX OE(2T, 0.5T) = (3, 3)
8251 01:25:23.825683
8252 01:25:23.825741
8253 01:25:23.831985 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8254 01:25:23.834993 CH0 RK1: MR19=303, MR18=2008
8255 01:25:23.842307 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8256 01:25:23.845301 [RxdqsGatingPostProcess] freq 1600
8257 01:25:23.848590 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8258 01:25:23.851942 best DQS0 dly(2T, 0.5T) = (1, 1)
8259 01:25:23.854941 best DQS1 dly(2T, 0.5T) = (1, 1)
8260 01:25:23.858611 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8261 01:25:23.861678 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8262 01:25:23.865148 best DQS0 dly(2T, 0.5T) = (1, 1)
8263 01:25:23.868582 best DQS1 dly(2T, 0.5T) = (1, 1)
8264 01:25:23.872327 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8265 01:25:23.875539 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8266 01:25:23.878415 Pre-setting of DQS Precalculation
8267 01:25:23.881836 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8268 01:25:23.881933 ==
8269 01:25:23.885329 Dram Type= 6, Freq= 0, CH_1, rank 0
8270 01:25:23.888363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 01:25:23.891652 ==
8272 01:25:23.895113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8273 01:25:23.898293 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8274 01:25:23.905019 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8275 01:25:23.911452 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8276 01:25:23.918593 [CA 0] Center 42 (13~72) winsize 60
8277 01:25:23.922388 [CA 1] Center 42 (12~72) winsize 61
8278 01:25:23.925763 [CA 2] Center 38 (9~68) winsize 60
8279 01:25:23.928713 [CA 3] Center 38 (9~67) winsize 59
8280 01:25:23.932284 [CA 4] Center 39 (10~68) winsize 59
8281 01:25:23.935424 [CA 5] Center 37 (8~67) winsize 60
8282 01:25:23.935501
8283 01:25:23.938638 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8284 01:25:23.938718
8285 01:25:23.942121 [CATrainingPosCal] consider 1 rank data
8286 01:25:23.945648 u2DelayCellTimex100 = 290/100 ps
8287 01:25:23.951976 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8288 01:25:23.954947 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8289 01:25:23.958329 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 01:25:23.961964 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8291 01:25:23.965338 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8292 01:25:23.968600 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8293 01:25:23.968676
8294 01:25:23.971698 CA PerBit enable=1, Macro0, CA PI delay=37
8295 01:25:23.971784
8296 01:25:23.974900 [CBTSetCACLKResult] CA Dly = 37
8297 01:25:23.978772 CS Dly: 12 (0~43)
8298 01:25:23.981894 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8299 01:25:23.985291 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8300 01:25:23.985409 ==
8301 01:25:23.988201 Dram Type= 6, Freq= 0, CH_1, rank 1
8302 01:25:23.995219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 01:25:23.995301 ==
8304 01:25:23.998951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 01:25:24.001841 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 01:25:24.008413 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 01:25:24.015465 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 01:25:24.022269 [CA 0] Center 42 (12~72) winsize 61
8309 01:25:24.025239 [CA 1] Center 41 (12~71) winsize 60
8310 01:25:24.028670 [CA 2] Center 38 (9~68) winsize 60
8311 01:25:24.032257 [CA 3] Center 37 (8~67) winsize 60
8312 01:25:24.035557 [CA 4] Center 38 (8~68) winsize 61
8313 01:25:24.038789 [CA 5] Center 37 (8~67) winsize 60
8314 01:25:24.038870
8315 01:25:24.042116 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8316 01:25:24.042197
8317 01:25:24.045553 [CATrainingPosCal] consider 2 rank data
8318 01:25:24.048987 u2DelayCellTimex100 = 290/100 ps
8319 01:25:24.051988 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8320 01:25:24.058753 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8321 01:25:24.062257 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8322 01:25:24.065318 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8323 01:25:24.068810 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8324 01:25:24.072458 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8325 01:25:24.072536
8326 01:25:24.075011 CA PerBit enable=1, Macro0, CA PI delay=37
8327 01:25:24.075081
8328 01:25:24.078478 [CBTSetCACLKResult] CA Dly = 37
8329 01:25:24.081949 CS Dly: 12 (0~44)
8330 01:25:24.084975 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 01:25:24.088405 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 01:25:24.088486
8333 01:25:24.091580 ----->DramcWriteLeveling(PI) begin...
8334 01:25:24.091675 ==
8335 01:25:24.094996 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 01:25:24.101458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 01:25:24.101570 ==
8338 01:25:24.104913 Write leveling (Byte 0): 25 => 25
8339 01:25:24.104987 Write leveling (Byte 1): 28 => 28
8340 01:25:24.108294 DramcWriteLeveling(PI) end<-----
8341 01:25:24.108370
8342 01:25:24.111283 ==
8343 01:25:24.115099 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 01:25:24.118212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 01:25:24.118284 ==
8346 01:25:24.121346 [Gating] SW mode calibration
8347 01:25:24.128454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8348 01:25:24.131882 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8349 01:25:24.138157 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 01:25:24.141764 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 01:25:24.144628 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8352 01:25:24.151147 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8353 01:25:24.154549 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 01:25:24.158061 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 01:25:24.164551 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 01:25:24.168109 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 01:25:24.171284 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 01:25:24.178116 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 01:25:24.181651 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8360 01:25:24.184405 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (1 0)
8361 01:25:24.191365 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 01:25:24.194977 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 01:25:24.197948 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 01:25:24.201440 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 01:25:24.207978 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 01:25:24.211170 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 01:25:24.214676 1 6 8 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
8368 01:25:24.221157 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 01:25:24.224780 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 01:25:24.228017 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 01:25:24.234916 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 01:25:24.238262 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 01:25:24.241515 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 01:25:24.247867 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 01:25:24.251301 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8376 01:25:24.254751 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8377 01:25:24.261337 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8378 01:25:24.264579 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 01:25:24.268046 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 01:25:24.275026 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 01:25:24.278491 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 01:25:24.281548 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 01:25:24.288165 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 01:25:24.291405 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 01:25:24.294580 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 01:25:24.297873 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 01:25:24.304806 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 01:25:24.308197 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 01:25:24.311338 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 01:25:24.318129 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 01:25:24.321510 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8392 01:25:24.324672 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8393 01:25:24.331155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8394 01:25:24.334579 Total UI for P1: 0, mck2ui 16
8395 01:25:24.337929 best dqsien dly found for B0: ( 1, 9, 10)
8396 01:25:24.341377 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 01:25:24.344195 Total UI for P1: 0, mck2ui 16
8398 01:25:24.347579 best dqsien dly found for B1: ( 1, 9, 12)
8399 01:25:24.351253 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8400 01:25:24.354644 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8401 01:25:24.354725
8402 01:25:24.357500 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8403 01:25:24.360800 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8404 01:25:24.364437 [Gating] SW calibration Done
8405 01:25:24.364512 ==
8406 01:25:24.367688 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 01:25:24.374143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 01:25:24.374225 ==
8409 01:25:24.374286 RX Vref Scan: 0
8410 01:25:24.374343
8411 01:25:24.377679 RX Vref 0 -> 0, step: 1
8412 01:25:24.377788
8413 01:25:24.380842 RX Delay 0 -> 252, step: 8
8414 01:25:24.384216 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8415 01:25:24.387349 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8416 01:25:24.390731 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8417 01:25:24.394080 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8418 01:25:24.400816 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8419 01:25:24.403991 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8420 01:25:24.407488 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8421 01:25:24.410782 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8422 01:25:24.414196 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8423 01:25:24.417798 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8424 01:25:24.424024 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8425 01:25:24.427675 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8426 01:25:24.430645 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8427 01:25:24.434414 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8428 01:25:24.440854 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8429 01:25:24.444445 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8430 01:25:24.444525 ==
8431 01:25:24.447329 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 01:25:24.450901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 01:25:24.450982 ==
8434 01:25:24.451045 DQS Delay:
8435 01:25:24.454051 DQS0 = 0, DQS1 = 0
8436 01:25:24.454130 DQM Delay:
8437 01:25:24.457647 DQM0 = 136, DQM1 = 132
8438 01:25:24.457726 DQ Delay:
8439 01:25:24.460898 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8440 01:25:24.463925 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8441 01:25:24.467534 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8442 01:25:24.474307 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8443 01:25:24.474387
8444 01:25:24.474450
8445 01:25:24.474509 ==
8446 01:25:24.477650 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 01:25:24.480591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 01:25:24.480671 ==
8449 01:25:24.480734
8450 01:25:24.480792
8451 01:25:24.484284 TX Vref Scan disable
8452 01:25:24.484364 == TX Byte 0 ==
8453 01:25:24.490990 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8454 01:25:24.494247 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8455 01:25:24.494355 == TX Byte 1 ==
8456 01:25:24.500777 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8457 01:25:24.504142 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8458 01:25:24.504222 ==
8459 01:25:24.507806 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 01:25:24.511005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 01:25:24.511086 ==
8462 01:25:24.524028
8463 01:25:24.527235 TX Vref early break, caculate TX vref
8464 01:25:24.530763 TX Vref=16, minBit 0, minWin=22, winSum=374
8465 01:25:24.534133 TX Vref=18, minBit 9, minWin=22, winSum=387
8466 01:25:24.537342 TX Vref=20, minBit 1, minWin=23, winSum=394
8467 01:25:24.541002 TX Vref=22, minBit 0, minWin=24, winSum=406
8468 01:25:24.544498 TX Vref=24, minBit 1, minWin=25, winSum=419
8469 01:25:24.550967 TX Vref=26, minBit 0, minWin=26, winSum=425
8470 01:25:24.554440 TX Vref=28, minBit 0, minWin=25, winSum=427
8471 01:25:24.557811 TX Vref=30, minBit 0, minWin=24, winSum=419
8472 01:25:24.560640 TX Vref=32, minBit 0, minWin=24, winSum=411
8473 01:25:24.563893 TX Vref=34, minBit 0, minWin=23, winSum=403
8474 01:25:24.570389 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8475 01:25:24.570470
8476 01:25:24.573962 Final TX Range 0 Vref 26
8477 01:25:24.574043
8478 01:25:24.574106 ==
8479 01:25:24.577381 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 01:25:24.580350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 01:25:24.580431 ==
8482 01:25:24.580494
8483 01:25:24.580553
8484 01:25:24.583942 TX Vref Scan disable
8485 01:25:24.591055 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8486 01:25:24.591135 == TX Byte 0 ==
8487 01:25:24.593934 u2DelayCellOfst[0]=20 cells (6 PI)
8488 01:25:24.597325 u2DelayCellOfst[1]=13 cells (4 PI)
8489 01:25:24.600413 u2DelayCellOfst[2]=0 cells (0 PI)
8490 01:25:24.604057 u2DelayCellOfst[3]=6 cells (2 PI)
8491 01:25:24.607124 u2DelayCellOfst[4]=13 cells (4 PI)
8492 01:25:24.610816 u2DelayCellOfst[5]=20 cells (6 PI)
8493 01:25:24.613910 u2DelayCellOfst[6]=20 cells (6 PI)
8494 01:25:24.613997 u2DelayCellOfst[7]=10 cells (3 PI)
8495 01:25:24.620455 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8496 01:25:24.623993 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8497 01:25:24.624071 == TX Byte 1 ==
8498 01:25:24.626905 u2DelayCellOfst[8]=0 cells (0 PI)
8499 01:25:24.630444 u2DelayCellOfst[9]=3 cells (1 PI)
8500 01:25:24.633851 u2DelayCellOfst[10]=13 cells (4 PI)
8501 01:25:24.637413 u2DelayCellOfst[11]=6 cells (2 PI)
8502 01:25:24.640273 u2DelayCellOfst[12]=13 cells (4 PI)
8503 01:25:24.643905 u2DelayCellOfst[13]=16 cells (5 PI)
8504 01:25:24.646898 u2DelayCellOfst[14]=16 cells (5 PI)
8505 01:25:24.650163 u2DelayCellOfst[15]=16 cells (5 PI)
8506 01:25:24.653941 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8507 01:25:24.660473 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8508 01:25:24.660550 DramC Write-DBI on
8509 01:25:24.660613 ==
8510 01:25:24.663480 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 01:25:24.666979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 01:25:24.667063 ==
8513 01:25:24.670353
8514 01:25:24.670438
8515 01:25:24.670508 TX Vref Scan disable
8516 01:25:24.673394 == TX Byte 0 ==
8517 01:25:24.676833 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8518 01:25:24.680146 == TX Byte 1 ==
8519 01:25:24.683569 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8520 01:25:24.683677 DramC Write-DBI off
8521 01:25:24.683745
8522 01:25:24.687189 [DATLAT]
8523 01:25:24.687266 Freq=1600, CH1 RK0
8524 01:25:24.687326
8525 01:25:24.690689 DATLAT Default: 0xf
8526 01:25:24.690757 0, 0xFFFF, sum = 0
8527 01:25:24.693520 1, 0xFFFF, sum = 0
8528 01:25:24.693591 2, 0xFFFF, sum = 0
8529 01:25:24.697255 3, 0xFFFF, sum = 0
8530 01:25:24.697327 4, 0xFFFF, sum = 0
8531 01:25:24.700356 5, 0xFFFF, sum = 0
8532 01:25:24.700434 6, 0xFFFF, sum = 0
8533 01:25:24.703711 7, 0xFFFF, sum = 0
8534 01:25:24.707405 8, 0xFFFF, sum = 0
8535 01:25:24.707514 9, 0xFFFF, sum = 0
8536 01:25:24.710143 10, 0xFFFF, sum = 0
8537 01:25:24.710246 11, 0xFFFF, sum = 0
8538 01:25:24.713492 12, 0xFFFF, sum = 0
8539 01:25:24.713592 13, 0xFFFF, sum = 0
8540 01:25:24.716816 14, 0x0, sum = 1
8541 01:25:24.716887 15, 0x0, sum = 2
8542 01:25:24.720202 16, 0x0, sum = 3
8543 01:25:24.720276 17, 0x0, sum = 4
8544 01:25:24.723529 best_step = 15
8545 01:25:24.723614
8546 01:25:24.723675 ==
8547 01:25:24.727041 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 01:25:24.729997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 01:25:24.730075 ==
8550 01:25:24.730138 RX Vref Scan: 1
8551 01:25:24.730195
8552 01:25:24.733337 Set Vref Range= 24 -> 127
8553 01:25:24.733402
8554 01:25:24.736833 RX Vref 24 -> 127, step: 1
8555 01:25:24.736907
8556 01:25:24.740391 RX Delay 27 -> 252, step: 4
8557 01:25:24.740462
8558 01:25:24.743596 Set Vref, RX VrefLevel [Byte0]: 24
8559 01:25:24.746775 [Byte1]: 24
8560 01:25:24.746861
8561 01:25:24.750138 Set Vref, RX VrefLevel [Byte0]: 25
8562 01:25:24.753713 [Byte1]: 25
8563 01:25:24.753783
8564 01:25:24.756840 Set Vref, RX VrefLevel [Byte0]: 26
8565 01:25:24.759979 [Byte1]: 26
8566 01:25:24.763675
8567 01:25:24.763750 Set Vref, RX VrefLevel [Byte0]: 27
8568 01:25:24.766900 [Byte1]: 27
8569 01:25:24.770887
8570 01:25:24.770976 Set Vref, RX VrefLevel [Byte0]: 28
8571 01:25:24.774476 [Byte1]: 28
8572 01:25:24.778444
8573 01:25:24.778519 Set Vref, RX VrefLevel [Byte0]: 29
8574 01:25:24.781833 [Byte1]: 29
8575 01:25:24.786442
8576 01:25:24.786525 Set Vref, RX VrefLevel [Byte0]: 30
8577 01:25:24.789593 [Byte1]: 30
8578 01:25:24.793617
8579 01:25:24.793708 Set Vref, RX VrefLevel [Byte0]: 31
8580 01:25:24.796868 [Byte1]: 31
8581 01:25:24.801385
8582 01:25:24.801470 Set Vref, RX VrefLevel [Byte0]: 32
8583 01:25:24.804691 [Byte1]: 32
8584 01:25:24.809031
8585 01:25:24.809101 Set Vref, RX VrefLevel [Byte0]: 33
8586 01:25:24.812516 [Byte1]: 33
8587 01:25:24.816342
8588 01:25:24.816422 Set Vref, RX VrefLevel [Byte0]: 34
8589 01:25:24.819806 [Byte1]: 34
8590 01:25:24.823575
8591 01:25:24.823667 Set Vref, RX VrefLevel [Byte0]: 35
8592 01:25:24.827003 [Byte1]: 35
8593 01:25:24.831600
8594 01:25:24.831683 Set Vref, RX VrefLevel [Byte0]: 36
8595 01:25:24.834869 [Byte1]: 36
8596 01:25:24.838918
8597 01:25:24.838994 Set Vref, RX VrefLevel [Byte0]: 37
8598 01:25:24.842375 [Byte1]: 37
8599 01:25:24.846475
8600 01:25:24.846551 Set Vref, RX VrefLevel [Byte0]: 38
8601 01:25:24.849882 [Byte1]: 38
8602 01:25:24.853943
8603 01:25:24.854021 Set Vref, RX VrefLevel [Byte0]: 39
8604 01:25:24.857090 [Byte1]: 39
8605 01:25:24.861524
8606 01:25:24.861597 Set Vref, RX VrefLevel [Byte0]: 40
8607 01:25:24.864788 [Byte1]: 40
8608 01:25:24.868862
8609 01:25:24.868946 Set Vref, RX VrefLevel [Byte0]: 41
8610 01:25:24.872149 [Byte1]: 41
8611 01:25:24.876452
8612 01:25:24.876521 Set Vref, RX VrefLevel [Byte0]: 42
8613 01:25:24.879830 [Byte1]: 42
8614 01:25:24.884355
8615 01:25:24.884427 Set Vref, RX VrefLevel [Byte0]: 43
8616 01:25:24.887431 [Byte1]: 43
8617 01:25:24.891746
8618 01:25:24.891833 Set Vref, RX VrefLevel [Byte0]: 44
8619 01:25:24.894849 [Byte1]: 44
8620 01:25:24.899084
8621 01:25:24.899157 Set Vref, RX VrefLevel [Byte0]: 45
8622 01:25:24.902607 [Byte1]: 45
8623 01:25:24.906757
8624 01:25:24.906836 Set Vref, RX VrefLevel [Byte0]: 46
8625 01:25:24.910021 [Byte1]: 46
8626 01:25:24.914112
8627 01:25:24.914221 Set Vref, RX VrefLevel [Byte0]: 47
8628 01:25:24.917428 [Byte1]: 47
8629 01:25:24.921980
8630 01:25:24.922098 Set Vref, RX VrefLevel [Byte0]: 48
8631 01:25:24.925125 [Byte1]: 48
8632 01:25:24.929331
8633 01:25:24.929421 Set Vref, RX VrefLevel [Byte0]: 49
8634 01:25:24.932712 [Byte1]: 49
8635 01:25:24.937126
8636 01:25:24.937223 Set Vref, RX VrefLevel [Byte0]: 50
8637 01:25:24.940518 [Byte1]: 50
8638 01:25:24.944724
8639 01:25:24.944833 Set Vref, RX VrefLevel [Byte0]: 51
8640 01:25:24.947911 [Byte1]: 51
8641 01:25:24.952034
8642 01:25:24.952111 Set Vref, RX VrefLevel [Byte0]: 52
8643 01:25:24.955514 [Byte1]: 52
8644 01:25:24.959519
8645 01:25:24.959632 Set Vref, RX VrefLevel [Byte0]: 53
8646 01:25:24.962846 [Byte1]: 53
8647 01:25:24.966926
8648 01:25:24.967026 Set Vref, RX VrefLevel [Byte0]: 54
8649 01:25:24.970485 [Byte1]: 54
8650 01:25:24.974396
8651 01:25:24.974466 Set Vref, RX VrefLevel [Byte0]: 55
8652 01:25:24.977808 [Byte1]: 55
8653 01:25:24.982351
8654 01:25:24.982427 Set Vref, RX VrefLevel [Byte0]: 56
8655 01:25:24.985581 [Byte1]: 56
8656 01:25:24.989447
8657 01:25:24.989534 Set Vref, RX VrefLevel [Byte0]: 57
8658 01:25:24.993257 [Byte1]: 57
8659 01:25:24.997204
8660 01:25:24.997305 Set Vref, RX VrefLevel [Byte0]: 58
8661 01:25:25.000699 [Byte1]: 58
8662 01:25:25.004993
8663 01:25:25.005067 Set Vref, RX VrefLevel [Byte0]: 59
8664 01:25:25.008475 [Byte1]: 59
8665 01:25:25.012270
8666 01:25:25.012346 Set Vref, RX VrefLevel [Byte0]: 60
8667 01:25:25.015534 [Byte1]: 60
8668 01:25:25.020249
8669 01:25:25.020357 Set Vref, RX VrefLevel [Byte0]: 61
8670 01:25:25.022988 [Byte1]: 61
8671 01:25:25.027365
8672 01:25:25.027441 Set Vref, RX VrefLevel [Byte0]: 62
8673 01:25:25.030869 [Byte1]: 62
8674 01:25:25.034662
8675 01:25:25.034745 Set Vref, RX VrefLevel [Byte0]: 63
8676 01:25:25.038206 [Byte1]: 63
8677 01:25:25.042173
8678 01:25:25.042292 Set Vref, RX VrefLevel [Byte0]: 64
8679 01:25:25.045655 [Byte1]: 64
8680 01:25:25.049889
8681 01:25:25.049972 Set Vref, RX VrefLevel [Byte0]: 65
8682 01:25:25.053222 [Byte1]: 65
8683 01:25:25.057614
8684 01:25:25.057697 Set Vref, RX VrefLevel [Byte0]: 66
8685 01:25:25.060891 [Byte1]: 66
8686 01:25:25.064972
8687 01:25:25.065056 Set Vref, RX VrefLevel [Byte0]: 67
8688 01:25:25.068450 [Byte1]: 67
8689 01:25:25.072272
8690 01:25:25.072365 Set Vref, RX VrefLevel [Byte0]: 68
8691 01:25:25.075744 [Byte1]: 68
8692 01:25:25.080443
8693 01:25:25.080529 Set Vref, RX VrefLevel [Byte0]: 69
8694 01:25:25.083156 [Byte1]: 69
8695 01:25:25.087379
8696 01:25:25.087489 Set Vref, RX VrefLevel [Byte0]: 70
8697 01:25:25.090923 [Byte1]: 70
8698 01:25:25.095085
8699 01:25:25.095183 Set Vref, RX VrefLevel [Byte0]: 71
8700 01:25:25.098338 [Byte1]: 71
8701 01:25:25.102600
8702 01:25:25.102683 Set Vref, RX VrefLevel [Byte0]: 72
8703 01:25:25.105585 [Byte1]: 72
8704 01:25:25.109924
8705 01:25:25.110003 Set Vref, RX VrefLevel [Byte0]: 73
8706 01:25:25.113405 [Byte1]: 73
8707 01:25:25.117363
8708 01:25:25.117438 Set Vref, RX VrefLevel [Byte0]: 74
8709 01:25:25.120783 [Byte1]: 74
8710 01:25:25.125226
8711 01:25:25.125295 Set Vref, RX VrefLevel [Byte0]: 75
8712 01:25:25.128715 [Byte1]: 75
8713 01:25:25.132707
8714 01:25:25.132776 Set Vref, RX VrefLevel [Byte0]: 76
8715 01:25:25.136352 [Byte1]: 76
8716 01:25:25.140421
8717 01:25:25.140502 Set Vref, RX VrefLevel [Byte0]: 77
8718 01:25:25.143625 [Byte1]: 77
8719 01:25:25.147520
8720 01:25:25.147660 Final RX Vref Byte 0 = 58 to rank0
8721 01:25:25.151043 Final RX Vref Byte 1 = 57 to rank0
8722 01:25:25.154492 Final RX Vref Byte 0 = 58 to rank1
8723 01:25:25.157961 Final RX Vref Byte 1 = 57 to rank1==
8724 01:25:25.160979 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 01:25:25.167582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 01:25:25.167727 ==
8727 01:25:25.167825 DQS Delay:
8728 01:25:25.167901 DQS0 = 0, DQS1 = 0
8729 01:25:25.170763 DQM Delay:
8730 01:25:25.170846 DQM0 = 134, DQM1 = 131
8731 01:25:25.174313 DQ Delay:
8732 01:25:25.177813 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8733 01:25:25.181358 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8734 01:25:25.184095 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8735 01:25:25.188034 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8736 01:25:25.188113
8737 01:25:25.188184
8738 01:25:25.188252
8739 01:25:25.190927 [DramC_TX_OE_Calibration] TA2
8740 01:25:25.194353 Original DQ_B0 (3 6) =30, OEN = 27
8741 01:25:25.197396 Original DQ_B1 (3 6) =30, OEN = 27
8742 01:25:25.201126 24, 0x0, End_B0=24 End_B1=24
8743 01:25:25.201205 25, 0x0, End_B0=25 End_B1=25
8744 01:25:25.204271 26, 0x0, End_B0=26 End_B1=26
8745 01:25:25.207566 27, 0x0, End_B0=27 End_B1=27
8746 01:25:25.210927 28, 0x0, End_B0=28 End_B1=28
8747 01:25:25.214248 29, 0x0, End_B0=29 End_B1=29
8748 01:25:25.214318 30, 0x0, End_B0=30 End_B1=30
8749 01:25:25.217374 31, 0x4141, End_B0=30 End_B1=30
8750 01:25:25.220804 Byte0 end_step=30 best_step=27
8751 01:25:25.223969 Byte1 end_step=30 best_step=27
8752 01:25:25.227415 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 01:25:25.230794 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 01:25:25.230863
8755 01:25:25.230928
8756 01:25:25.237662 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8757 01:25:25.240601 CH1 RK0: MR19=303, MR18=1725
8758 01:25:25.247457 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8759 01:25:25.247534
8760 01:25:25.250728 ----->DramcWriteLeveling(PI) begin...
8761 01:25:25.250801 ==
8762 01:25:25.253739 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 01:25:25.257525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 01:25:25.257598 ==
8765 01:25:25.260995 Write leveling (Byte 0): 26 => 26
8766 01:25:25.264159 Write leveling (Byte 1): 29 => 29
8767 01:25:25.267482 DramcWriteLeveling(PI) end<-----
8768 01:25:25.267571
8769 01:25:25.267660 ==
8770 01:25:25.270734 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 01:25:25.274169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 01:25:25.274239 ==
8773 01:25:25.277455 [Gating] SW mode calibration
8774 01:25:25.284220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 01:25:25.290419 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 01:25:25.294213 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 01:25:25.297162 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 01:25:25.304162 1 4 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8779 01:25:25.307181 1 4 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8780 01:25:25.310922 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 01:25:25.317207 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 01:25:25.320369 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 01:25:25.323847 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 01:25:25.330625 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 01:25:25.333966 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8786 01:25:25.337369 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8787 01:25:25.343760 1 5 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 0)
8788 01:25:25.347358 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 01:25:25.350680 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 01:25:25.357403 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 01:25:25.360648 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 01:25:25.364256 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 01:25:25.370934 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 01:25:25.374159 1 6 8 | B1->B0 | 2c2b 2323 | 1 0 | (0 0) (0 0)
8795 01:25:25.377177 1 6 12 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
8796 01:25:25.380272 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 01:25:25.387423 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 01:25:25.390707 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 01:25:25.394181 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 01:25:25.400599 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 01:25:25.403630 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8802 01:25:25.407069 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8803 01:25:25.413630 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8804 01:25:25.417016 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8805 01:25:25.420310 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 01:25:25.426882 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 01:25:25.430665 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 01:25:25.434011 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 01:25:25.440269 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 01:25:25.443702 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 01:25:25.447049 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 01:25:25.453761 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 01:25:25.457233 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 01:25:25.460307 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 01:25:25.466794 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 01:25:25.470656 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 01:25:25.473741 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8818 01:25:25.479971 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8819 01:25:25.483467 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8820 01:25:25.486950 Total UI for P1: 0, mck2ui 16
8821 01:25:25.490075 best dqsien dly found for B1: ( 1, 9, 6)
8822 01:25:25.493548 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 01:25:25.496656 Total UI for P1: 0, mck2ui 16
8824 01:25:25.499920 best dqsien dly found for B0: ( 1, 9, 12)
8825 01:25:25.503750 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8826 01:25:25.506824 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8827 01:25:25.506895
8828 01:25:25.509784 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8829 01:25:25.516315 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8830 01:25:25.516397 [Gating] SW calibration Done
8831 01:25:25.519691 ==
8832 01:25:25.519776 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 01:25:25.526511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 01:25:25.526600 ==
8835 01:25:25.526690 RX Vref Scan: 0
8836 01:25:25.526769
8837 01:25:25.529737 RX Vref 0 -> 0, step: 1
8838 01:25:25.529817
8839 01:25:25.533136 RX Delay 0 -> 252, step: 8
8840 01:25:25.536593 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8841 01:25:25.539901 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8842 01:25:25.543227 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8843 01:25:25.549486 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8844 01:25:25.553141 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8845 01:25:25.556128 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8846 01:25:25.559180 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8847 01:25:25.562998 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8848 01:25:25.569226 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8849 01:25:25.572666 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8850 01:25:25.575822 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8851 01:25:25.579496 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8852 01:25:25.585799 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8853 01:25:25.589365 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8854 01:25:25.592656 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8855 01:25:25.595736 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8856 01:25:25.595817 ==
8857 01:25:25.599136 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 01:25:25.602366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 01:25:25.605792 ==
8860 01:25:25.605879 DQS Delay:
8861 01:25:25.605939 DQS0 = 0, DQS1 = 0
8862 01:25:25.608711 DQM Delay:
8863 01:25:25.608782 DQM0 = 136, DQM1 = 133
8864 01:25:25.612081 DQ Delay:
8865 01:25:25.615791 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8866 01:25:25.618664 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8867 01:25:25.622290 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8868 01:25:25.625662 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8869 01:25:25.625731
8870 01:25:25.625796
8871 01:25:25.625859 ==
8872 01:25:25.628892 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 01:25:25.632599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 01:25:25.632675 ==
8875 01:25:25.635855
8876 01:25:25.635950
8877 01:25:25.636057 TX Vref Scan disable
8878 01:25:25.639356 == TX Byte 0 ==
8879 01:25:25.641969 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8880 01:25:25.645469 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8881 01:25:25.648756 == TX Byte 1 ==
8882 01:25:25.652278 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8883 01:25:25.655662 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8884 01:25:25.655745 ==
8885 01:25:25.658746 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 01:25:25.665612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 01:25:25.665707 ==
8888 01:25:25.678010
8889 01:25:25.681592 TX Vref early break, caculate TX vref
8890 01:25:25.684817 TX Vref=16, minBit 0, minWin=23, winSum=381
8891 01:25:25.688557 TX Vref=18, minBit 2, minWin=23, winSum=393
8892 01:25:25.691385 TX Vref=20, minBit 0, minWin=24, winSum=400
8893 01:25:25.695017 TX Vref=22, minBit 0, minWin=25, winSum=411
8894 01:25:25.698484 TX Vref=24, minBit 1, minWin=24, winSum=413
8895 01:25:25.705158 TX Vref=26, minBit 0, minWin=25, winSum=424
8896 01:25:25.708440 TX Vref=28, minBit 1, minWin=25, winSum=422
8897 01:25:25.711554 TX Vref=30, minBit 1, minWin=25, winSum=417
8898 01:25:25.714908 TX Vref=32, minBit 0, minWin=24, winSum=411
8899 01:25:25.718366 TX Vref=34, minBit 0, minWin=24, winSum=404
8900 01:25:25.721831 TX Vref=36, minBit 1, minWin=23, winSum=390
8901 01:25:25.728181 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8902 01:25:25.728271
8903 01:25:25.731504 Final TX Range 0 Vref 26
8904 01:25:25.731618
8905 01:25:25.731687 ==
8906 01:25:25.734934 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 01:25:25.738157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 01:25:25.738243 ==
8909 01:25:25.738308
8910 01:25:25.738369
8911 01:25:25.741547 TX Vref Scan disable
8912 01:25:25.748131 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8913 01:25:25.748222 == TX Byte 0 ==
8914 01:25:25.751467 u2DelayCellOfst[0]=16 cells (5 PI)
8915 01:25:25.754938 u2DelayCellOfst[1]=10 cells (3 PI)
8916 01:25:25.758663 u2DelayCellOfst[2]=0 cells (0 PI)
8917 01:25:25.761405 u2DelayCellOfst[3]=6 cells (2 PI)
8918 01:25:25.764823 u2DelayCellOfst[4]=6 cells (2 PI)
8919 01:25:25.768023 u2DelayCellOfst[5]=16 cells (5 PI)
8920 01:25:25.771254 u2DelayCellOfst[6]=16 cells (5 PI)
8921 01:25:25.771332 u2DelayCellOfst[7]=6 cells (2 PI)
8922 01:25:25.778063 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8923 01:25:25.781335 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8924 01:25:25.781420 == TX Byte 1 ==
8925 01:25:25.784802 u2DelayCellOfst[8]=0 cells (0 PI)
8926 01:25:25.787922 u2DelayCellOfst[9]=3 cells (1 PI)
8927 01:25:25.791301 u2DelayCellOfst[10]=10 cells (3 PI)
8928 01:25:25.794770 u2DelayCellOfst[11]=3 cells (1 PI)
8929 01:25:25.797949 u2DelayCellOfst[12]=13 cells (4 PI)
8930 01:25:25.801647 u2DelayCellOfst[13]=13 cells (4 PI)
8931 01:25:25.805127 u2DelayCellOfst[14]=16 cells (5 PI)
8932 01:25:25.808218 u2DelayCellOfst[15]=16 cells (5 PI)
8933 01:25:25.811323 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8934 01:25:25.818138 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8935 01:25:25.818228 DramC Write-DBI on
8936 01:25:25.818294 ==
8937 01:25:25.821666 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 01:25:25.825345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 01:25:25.825420 ==
8940 01:25:25.828055
8941 01:25:25.828128
8942 01:25:25.828189 TX Vref Scan disable
8943 01:25:25.831359 == TX Byte 0 ==
8944 01:25:25.835179 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8945 01:25:25.838183 == TX Byte 1 ==
8946 01:25:25.841617 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8947 01:25:25.841693 DramC Write-DBI off
8948 01:25:25.844557
8949 01:25:25.844633 [DATLAT]
8950 01:25:25.844695 Freq=1600, CH1 RK1
8951 01:25:25.844754
8952 01:25:25.848347 DATLAT Default: 0xf
8953 01:25:25.848424 0, 0xFFFF, sum = 0
8954 01:25:25.851256 1, 0xFFFF, sum = 0
8955 01:25:25.851323 2, 0xFFFF, sum = 0
8956 01:25:25.854795 3, 0xFFFF, sum = 0
8957 01:25:25.854864 4, 0xFFFF, sum = 0
8958 01:25:25.858315 5, 0xFFFF, sum = 0
8959 01:25:25.861704 6, 0xFFFF, sum = 0
8960 01:25:25.861775 7, 0xFFFF, sum = 0
8961 01:25:25.864596 8, 0xFFFF, sum = 0
8962 01:25:25.864666 9, 0xFFFF, sum = 0
8963 01:25:25.867938 10, 0xFFFF, sum = 0
8964 01:25:25.868009 11, 0xFFFF, sum = 0
8965 01:25:25.871151 12, 0xFFFF, sum = 0
8966 01:25:25.871219 13, 0xFFFF, sum = 0
8967 01:25:25.874579 14, 0x0, sum = 1
8968 01:25:25.874647 15, 0x0, sum = 2
8969 01:25:25.877773 16, 0x0, sum = 3
8970 01:25:25.877846 17, 0x0, sum = 4
8971 01:25:25.881500 best_step = 15
8972 01:25:25.881564
8973 01:25:25.881626 ==
8974 01:25:25.884750 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 01:25:25.887653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 01:25:25.887720 ==
8977 01:25:25.887777 RX Vref Scan: 0
8978 01:25:25.891475
8979 01:25:25.891538 RX Vref 0 -> 0, step: 1
8980 01:25:25.891628
8981 01:25:25.894475 RX Delay 19 -> 252, step: 4
8982 01:25:25.898237 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8983 01:25:25.904622 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8984 01:25:25.907792 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8985 01:25:25.911286 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8986 01:25:25.914631 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8987 01:25:25.918150 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8988 01:25:25.921295 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8989 01:25:25.927734 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8990 01:25:25.930919 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8991 01:25:25.934714 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8992 01:25:25.937713 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8993 01:25:25.940997 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8994 01:25:25.947980 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8995 01:25:25.951142 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8996 01:25:25.954574 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8997 01:25:25.958085 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8998 01:25:25.958166 ==
8999 01:25:25.961314 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 01:25:25.968175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 01:25:25.968258 ==
9002 01:25:25.968350 DQS Delay:
9003 01:25:25.971122 DQS0 = 0, DQS1 = 0
9004 01:25:25.971199 DQM Delay:
9005 01:25:25.971304 DQM0 = 134, DQM1 = 130
9006 01:25:25.974419 DQ Delay:
9007 01:25:25.977851 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9008 01:25:25.981015 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
9009 01:25:25.984518 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9010 01:25:25.988100 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9011 01:25:25.988184
9012 01:25:25.988253
9013 01:25:25.988314
9014 01:25:25.991349 [DramC_TX_OE_Calibration] TA2
9015 01:25:25.994641 Original DQ_B0 (3 6) =30, OEN = 27
9016 01:25:25.997694 Original DQ_B1 (3 6) =30, OEN = 27
9017 01:25:26.001640 24, 0x0, End_B0=24 End_B1=24
9018 01:25:26.001727 25, 0x0, End_B0=25 End_B1=25
9019 01:25:26.004480 26, 0x0, End_B0=26 End_B1=26
9020 01:25:26.008234 27, 0x0, End_B0=27 End_B1=27
9021 01:25:26.011639 28, 0x0, End_B0=28 End_B1=28
9022 01:25:26.011727 29, 0x0, End_B0=29 End_B1=29
9023 01:25:26.014522 30, 0x0, End_B0=30 End_B1=30
9024 01:25:26.018207 31, 0x4141, End_B0=30 End_B1=30
9025 01:25:26.021422 Byte0 end_step=30 best_step=27
9026 01:25:26.024689 Byte1 end_step=30 best_step=27
9027 01:25:26.028107 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 01:25:26.028195 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 01:25:26.028264
9030 01:25:26.031498
9031 01:25:26.037978 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9032 01:25:26.041056 CH1 RK1: MR19=303, MR18=2309
9033 01:25:26.047743 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9034 01:25:26.047917 [RxdqsGatingPostProcess] freq 1600
9035 01:25:26.055147 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 01:25:26.058024 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 01:25:26.061371 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 01:25:26.064684 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 01:25:26.068092 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 01:25:26.071126 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 01:25:26.074442 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 01:25:26.077714 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 01:25:26.081272 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 01:25:26.081383 Pre-setting of DQS Precalculation
9045 01:25:26.087693 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 01:25:26.094498 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 01:25:26.101194 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 01:25:26.101366
9049 01:25:26.101474
9050 01:25:26.104521 [Calibration Summary] 3200 Mbps
9051 01:25:26.107535 CH 0, Rank 0
9052 01:25:26.107657 SW Impedance : PASS
9053 01:25:26.111257 DUTY Scan : NO K
9054 01:25:26.114584 ZQ Calibration : PASS
9055 01:25:26.114716 Jitter Meter : NO K
9056 01:25:26.117834 CBT Training : PASS
9057 01:25:26.120999 Write leveling : PASS
9058 01:25:26.121151 RX DQS gating : PASS
9059 01:25:26.124360 RX DQ/DQS(RDDQC) : PASS
9060 01:25:26.124598 TX DQ/DQS : PASS
9061 01:25:26.127651 RX DATLAT : PASS
9062 01:25:26.130825 RX DQ/DQS(Engine): PASS
9063 01:25:26.130987 TX OE : PASS
9064 01:25:26.134723 All Pass.
9065 01:25:26.134815
9066 01:25:26.134882 CH 0, Rank 1
9067 01:25:26.137557 SW Impedance : PASS
9068 01:25:26.137683 DUTY Scan : NO K
9069 01:25:26.140824 ZQ Calibration : PASS
9070 01:25:26.144245 Jitter Meter : NO K
9071 01:25:26.144402 CBT Training : PASS
9072 01:25:26.147372 Write leveling : PASS
9073 01:25:26.150992 RX DQS gating : PASS
9074 01:25:26.151118 RX DQ/DQS(RDDQC) : PASS
9075 01:25:26.154578 TX DQ/DQS : PASS
9076 01:25:26.157642 RX DATLAT : PASS
9077 01:25:26.157779 RX DQ/DQS(Engine): PASS
9078 01:25:26.161070 TX OE : PASS
9079 01:25:26.161199 All Pass.
9080 01:25:26.161304
9081 01:25:26.164004 CH 1, Rank 0
9082 01:25:26.164124 SW Impedance : PASS
9083 01:25:26.167638 DUTY Scan : NO K
9084 01:25:26.170971 ZQ Calibration : PASS
9085 01:25:26.171110 Jitter Meter : NO K
9086 01:25:26.173851 CBT Training : PASS
9087 01:25:26.177329 Write leveling : PASS
9088 01:25:26.177459 RX DQS gating : PASS
9089 01:25:26.180732 RX DQ/DQS(RDDQC) : PASS
9090 01:25:26.180849 TX DQ/DQS : PASS
9091 01:25:26.184375 RX DATLAT : PASS
9092 01:25:26.187655 RX DQ/DQS(Engine): PASS
9093 01:25:26.187762 TX OE : PASS
9094 01:25:26.190921 All Pass.
9095 01:25:26.191041
9096 01:25:26.191144 CH 1, Rank 1
9097 01:25:26.194484 SW Impedance : PASS
9098 01:25:26.194603 DUTY Scan : NO K
9099 01:25:26.197785 ZQ Calibration : PASS
9100 01:25:26.201104 Jitter Meter : NO K
9101 01:25:26.201225 CBT Training : PASS
9102 01:25:26.203779 Write leveling : PASS
9103 01:25:26.207190 RX DQS gating : PASS
9104 01:25:26.207295 RX DQ/DQS(RDDQC) : PASS
9105 01:25:26.210673 TX DQ/DQS : PASS
9106 01:25:26.214029 RX DATLAT : PASS
9107 01:25:26.214127 RX DQ/DQS(Engine): PASS
9108 01:25:26.217519 TX OE : PASS
9109 01:25:26.217648 All Pass.
9110 01:25:26.217747
9111 01:25:26.220924 DramC Write-DBI on
9112 01:25:26.224156 PER_BANK_REFRESH: Hybrid Mode
9113 01:25:26.224274 TX_TRACKING: ON
9114 01:25:26.233973 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 01:25:26.240425 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 01:25:26.247159 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 01:25:26.250740 [FAST_K] Save calibration result to emmc
9118 01:25:26.253970 sync common calibartion params.
9119 01:25:26.257419 sync cbt_mode0:1, 1:1
9120 01:25:26.261008 dram_init: ddr_geometry: 2
9121 01:25:26.261176 dram_init: ddr_geometry: 2
9122 01:25:26.264354 dram_init: ddr_geometry: 2
9123 01:25:26.267457 0:dram_rank_size:100000000
9124 01:25:26.267613 1:dram_rank_size:100000000
9125 01:25:26.273789 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 01:25:26.276926 DFS_SHUFFLE_HW_MODE: ON
9127 01:25:26.280664 dramc_set_vcore_voltage set vcore to 725000
9128 01:25:26.283714 Read voltage for 1600, 0
9129 01:25:26.283850 Vio18 = 0
9130 01:25:26.283957 Vcore = 725000
9131 01:25:26.286889 Vdram = 0
9132 01:25:26.287025 Vddq = 0
9133 01:25:26.287133 Vmddr = 0
9134 01:25:26.290414 switch to 3200 Mbps bootup
9135 01:25:26.290548 [DramcRunTimeConfig]
9136 01:25:26.293644 PHYPLL
9137 01:25:26.293768 DPM_CONTROL_AFTERK: ON
9138 01:25:26.296905 PER_BANK_REFRESH: ON
9139 01:25:26.300739 REFRESH_OVERHEAD_REDUCTION: ON
9140 01:25:26.300894 CMD_PICG_NEW_MODE: OFF
9141 01:25:26.303526 XRTWTW_NEW_MODE: ON
9142 01:25:26.303686 XRTRTR_NEW_MODE: ON
9143 01:25:26.307039 TX_TRACKING: ON
9144 01:25:26.307167 RDSEL_TRACKING: OFF
9145 01:25:26.310507 DQS Precalculation for DVFS: ON
9146 01:25:26.313957 RX_TRACKING: OFF
9147 01:25:26.314099 HW_GATING DBG: ON
9148 01:25:26.317353 ZQCS_ENABLE_LP4: ON
9149 01:25:26.317478 RX_PICG_NEW_MODE: ON
9150 01:25:26.320266 TX_PICG_NEW_MODE: ON
9151 01:25:26.320414 ENABLE_RX_DCM_DPHY: ON
9152 01:25:26.323629 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 01:25:26.326803 DUMMY_READ_FOR_TRACKING: OFF
9154 01:25:26.329934 !!! SPM_CONTROL_AFTERK: OFF
9155 01:25:26.333787 !!! SPM could not control APHY
9156 01:25:26.333932 IMPEDANCE_TRACKING: ON
9157 01:25:26.337259 TEMP_SENSOR: ON
9158 01:25:26.337393 HW_SAVE_FOR_SR: OFF
9159 01:25:26.340131 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 01:25:26.344021 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 01:25:26.346869 Read ODT Tracking: ON
9162 01:25:26.350482 Refresh Rate DeBounce: ON
9163 01:25:26.350637 DFS_NO_QUEUE_FLUSH: ON
9164 01:25:26.354119 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 01:25:26.357242 ENABLE_DFS_RUNTIME_MRW: OFF
9166 01:25:26.360540 DDR_RESERVE_NEW_MODE: ON
9167 01:25:26.360675 MR_CBT_SWITCH_FREQ: ON
9168 01:25:26.363663 =========================
9169 01:25:26.382331 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 01:25:26.385596 dram_init: ddr_geometry: 2
9171 01:25:26.403921 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 01:25:26.407288 dram_init: dram init end (result: 0)
9173 01:25:26.413838 DRAM-K: Full calibration passed in 24515 msecs
9174 01:25:26.417167 MRC: failed to locate region type 0.
9175 01:25:26.417313 DRAM rank0 size:0x100000000,
9176 01:25:26.420606 DRAM rank1 size=0x100000000
9177 01:25:26.430453 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 01:25:26.437314 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 01:25:26.443634 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 01:25:26.450348 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 01:25:26.453773 DRAM rank0 size:0x100000000,
9182 01:25:26.456989 DRAM rank1 size=0x100000000
9183 01:25:26.457082 CBMEM:
9184 01:25:26.460549 IMD: root @ 0xfffff000 254 entries.
9185 01:25:26.463560 IMD: root @ 0xffffec00 62 entries.
9186 01:25:26.467232 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 01:25:26.470550 WARNING: RO_VPD is uninitialized or empty.
9188 01:25:26.476956 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 01:25:26.484073 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 01:25:26.497134 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9191 01:25:26.508460 BS: romstage times (exec / console): total (unknown) / 24040 ms
9192 01:25:26.508636
9193 01:25:26.508742
9194 01:25:26.518388 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 01:25:26.521530 ARM64: Exception handlers installed.
9196 01:25:26.525043 ARM64: Testing exception
9197 01:25:26.525187 ARM64: Done test exception
9198 01:25:26.528667 Enumerating buses...
9199 01:25:26.531517 Show all devs... Before device enumeration.
9200 01:25:26.535250 Root Device: enabled 1
9201 01:25:26.538458 CPU_CLUSTER: 0: enabled 1
9202 01:25:26.538611 CPU: 00: enabled 1
9203 01:25:26.542005 Compare with tree...
9204 01:25:26.542118 Root Device: enabled 1
9205 01:25:26.544991 CPU_CLUSTER: 0: enabled 1
9206 01:25:26.548329 CPU: 00: enabled 1
9207 01:25:26.548462 Root Device scanning...
9208 01:25:26.551873 scan_static_bus for Root Device
9209 01:25:26.554669 CPU_CLUSTER: 0 enabled
9210 01:25:26.558046 scan_static_bus for Root Device done
9211 01:25:26.561466 scan_bus: bus Root Device finished in 8 msecs
9212 01:25:26.561599 done
9213 01:25:26.567945 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 01:25:26.571375 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 01:25:26.578442 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 01:25:26.581032 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 01:25:26.584547 Allocating resources...
9218 01:25:26.587981 Reading resources...
9219 01:25:26.591633 Root Device read_resources bus 0 link: 0
9220 01:25:26.591752 DRAM rank0 size:0x100000000,
9221 01:25:26.594729 DRAM rank1 size=0x100000000
9222 01:25:26.597950 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 01:25:26.601575 CPU: 00 missing read_resources
9224 01:25:26.604338 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 01:25:26.611257 Root Device read_resources bus 0 link: 0 done
9226 01:25:26.611377 Done reading resources.
9227 01:25:26.617989 Show resources in subtree (Root Device)...After reading.
9228 01:25:26.621539 Root Device child on link 0 CPU_CLUSTER: 0
9229 01:25:26.624774 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 01:25:26.634515 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 01:25:26.634649 CPU: 00
9232 01:25:26.637809 Root Device assign_resources, bus 0 link: 0
9233 01:25:26.641420 CPU_CLUSTER: 0 missing set_resources
9234 01:25:26.644635 Root Device assign_resources, bus 0 link: 0 done
9235 01:25:26.647602 Done setting resources.
9236 01:25:26.654505 Show resources in subtree (Root Device)...After assigning values.
9237 01:25:26.657588 Root Device child on link 0 CPU_CLUSTER: 0
9238 01:25:26.660765 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 01:25:26.670723 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 01:25:26.670856 CPU: 00
9241 01:25:26.674464 Done allocating resources.
9242 01:25:26.677419 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 01:25:26.680834 Enabling resources...
9244 01:25:26.680954 done.
9245 01:25:26.687420 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 01:25:26.687564 Initializing devices...
9247 01:25:26.691072 Root Device init
9248 01:25:26.691195 init hardware done!
9249 01:25:26.694098 0x00000018: ctrlr->caps
9250 01:25:26.697358 52.000 MHz: ctrlr->f_max
9251 01:25:26.697476 0.400 MHz: ctrlr->f_min
9252 01:25:26.700613 0x40ff8080: ctrlr->voltages
9253 01:25:26.700728 sclk: 390625
9254 01:25:26.704146 Bus Width = 1
9255 01:25:26.704258 sclk: 390625
9256 01:25:26.707765 Bus Width = 1
9257 01:25:26.707875 Early init status = 3
9258 01:25:26.714557 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 01:25:26.717371 in-header: 03 fc 00 00 01 00 00 00
9260 01:25:26.717494 in-data: 00
9261 01:25:26.724070 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9262 01:25:26.727609 in-header: 03 fd 00 00 00 00 00 00
9263 01:25:26.731263 in-data:
9264 01:25:26.733839 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9265 01:25:26.737909 in-header: 03 fc 00 00 01 00 00 00
9266 01:25:26.741449 in-data: 00
9267 01:25:26.744445 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9268 01:25:26.749982 in-header: 03 fd 00 00 00 00 00 00
9269 01:25:26.753574 in-data:
9270 01:25:26.756490 [SSUSB] Setting up USB HOST controller...
9271 01:25:26.760131 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9272 01:25:26.763404 [SSUSB] phy power-on done.
9273 01:25:26.766724 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9274 01:25:26.773272 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9275 01:25:26.776691 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9276 01:25:26.783410 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9277 01:25:26.789864 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9278 01:25:26.796586 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9279 01:25:26.803156 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9280 01:25:26.809907 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9281 01:25:26.813279 SPM: binary array size = 0x9dc
9282 01:25:26.816615 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9283 01:25:26.823552 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9284 01:25:26.829693 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9285 01:25:26.833107 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9286 01:25:26.839538 configure_display: Starting display init
9287 01:25:26.873136 anx7625_power_on_init: Init interface.
9288 01:25:26.876729 anx7625_disable_pd_protocol: Disabled PD feature.
9289 01:25:26.879890 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9290 01:25:26.907452 anx7625_start_dp_work: Secure OCM version=00
9291 01:25:26.910639 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9292 01:25:26.925928 sp_tx_get_edid_block: EDID Block = 1
9293 01:25:27.028402 Extracted contents:
9294 01:25:27.031662 header: 00 ff ff ff ff ff ff 00
9295 01:25:27.035080 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9296 01:25:27.038414 version: 01 04
9297 01:25:27.041329 basic params: 95 1f 11 78 0a
9298 01:25:27.044952 chroma info: 76 90 94 55 54 90 27 21 50 54
9299 01:25:27.048273 established: 00 00 00
9300 01:25:27.055080 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9301 01:25:27.058381 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9302 01:25:27.064669 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9303 01:25:27.071481 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9304 01:25:27.078027 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9305 01:25:27.081351 extensions: 00
9306 01:25:27.081484 checksum: fb
9307 01:25:27.081581
9308 01:25:27.084731 Manufacturer: IVO Model 57d Serial Number 0
9309 01:25:27.088144 Made week 0 of 2020
9310 01:25:27.088275 EDID version: 1.4
9311 01:25:27.091440 Digital display
9312 01:25:27.094812 6 bits per primary color channel
9313 01:25:27.094953 DisplayPort interface
9314 01:25:27.097689 Maximum image size: 31 cm x 17 cm
9315 01:25:27.101126 Gamma: 220%
9316 01:25:27.101251 Check DPMS levels
9317 01:25:27.104778 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9318 01:25:27.107958 First detailed timing is preferred timing
9319 01:25:27.111371 Established timings supported:
9320 01:25:27.114408 Standard timings supported:
9321 01:25:27.118051 Detailed timings
9322 01:25:27.121603 Hex of detail: 383680a07038204018303c0035ae10000019
9323 01:25:27.124790 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9324 01:25:27.130946 0780 0798 07c8 0820 hborder 0
9325 01:25:27.134645 0438 043b 0447 0458 vborder 0
9326 01:25:27.137804 -hsync -vsync
9327 01:25:27.137984 Did detailed timing
9328 01:25:27.141568 Hex of detail: 000000000000000000000000000000000000
9329 01:25:27.144303 Manufacturer-specified data, tag 0
9330 01:25:27.151539 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9331 01:25:27.151774 ASCII string: InfoVision
9332 01:25:27.157410 Hex of detail: 000000fe00523134304e574635205248200a
9333 01:25:27.161088 ASCII string: R140NWF5 RH
9334 01:25:27.161278 Checksum
9335 01:25:27.164483 Checksum: 0xfb (valid)
9336 01:25:27.167676 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9337 01:25:27.170967 DSI data_rate: 832800000 bps
9338 01:25:27.174504 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9339 01:25:27.181001 anx7625_parse_edid: pixelclock(138800).
9340 01:25:27.184185 hactive(1920), hsync(48), hfp(24), hbp(88)
9341 01:25:27.187690 vactive(1080), vsync(12), vfp(3), vbp(17)
9342 01:25:27.191368 anx7625_dsi_config: config dsi.
9343 01:25:27.197875 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9344 01:25:27.210127 anx7625_dsi_config: success to config DSI
9345 01:25:27.213593 anx7625_dp_start: MIPI phy setup OK.
9346 01:25:27.217229 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9347 01:25:27.220205 mtk_ddp_mode_set invalid vrefresh 60
9348 01:25:27.223651 main_disp_path_setup
9349 01:25:27.223785 ovl_layer_smi_id_en
9350 01:25:27.226969 ovl_layer_smi_id_en
9351 01:25:27.227073 ccorr_config
9352 01:25:27.227163 aal_config
9353 01:25:27.230500 gamma_config
9354 01:25:27.230625 postmask_config
9355 01:25:27.233336 dither_config
9356 01:25:27.236603 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9357 01:25:27.243137 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9358 01:25:27.246889 Root Device init finished in 553 msecs
9359 01:25:27.249788 CPU_CLUSTER: 0 init
9360 01:25:27.256431 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9361 01:25:27.263372 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9362 01:25:27.263525 APU_MBOX 0x190000b0 = 0x10001
9363 01:25:27.266886 APU_MBOX 0x190001b0 = 0x10001
9364 01:25:27.270036 APU_MBOX 0x190005b0 = 0x10001
9365 01:25:27.273228 APU_MBOX 0x190006b0 = 0x10001
9366 01:25:27.279899 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9367 01:25:27.289191 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9368 01:25:27.301730 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9369 01:25:27.308566 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9370 01:25:27.320200 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9371 01:25:27.329397 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9372 01:25:27.332660 CPU_CLUSTER: 0 init finished in 81 msecs
9373 01:25:27.335801 Devices initialized
9374 01:25:27.338999 Show all devs... After init.
9375 01:25:27.339132 Root Device: enabled 1
9376 01:25:27.342362 CPU_CLUSTER: 0: enabled 1
9377 01:25:27.345644 CPU: 00: enabled 1
9378 01:25:27.348975 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9379 01:25:27.352572 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9380 01:25:27.355949 ELOG: NV offset 0x57f000 size 0x1000
9381 01:25:27.362316 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9382 01:25:27.369300 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9383 01:25:27.372197 ELOG: Event(17) added with size 13 at 2023-08-28 01:24:20 UTC
9384 01:25:27.375804 out: cmd=0x121: 03 db 21 01 00 00 00 00
9385 01:25:27.379705 in-header: 03 a4 00 00 2c 00 00 00
9386 01:25:27.392810 in-data: bb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9387 01:25:27.399714 ELOG: Event(A1) added with size 10 at 2023-08-28 01:24:20 UTC
9388 01:25:27.406332 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9389 01:25:27.409749 ELOG: Event(A0) added with size 9 at 2023-08-28 01:24:20 UTC
9390 01:25:27.416513 elog_add_boot_reason: Logged dev mode boot
9391 01:25:27.419740 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9392 01:25:27.422945 Finalize devices...
9393 01:25:27.423066 Devices finalized
9394 01:25:27.429942 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9395 01:25:27.433349 Writing coreboot table at 0xffe64000
9396 01:25:27.436256 0. 000000000010a000-0000000000113fff: RAMSTAGE
9397 01:25:27.439827 1. 0000000040000000-00000000400fffff: RAM
9398 01:25:27.442946 2. 0000000040100000-000000004032afff: RAMSTAGE
9399 01:25:27.449215 3. 000000004032b000-00000000545fffff: RAM
9400 01:25:27.453019 4. 0000000054600000-000000005465ffff: BL31
9401 01:25:27.456266 5. 0000000054660000-00000000ffe63fff: RAM
9402 01:25:27.459321 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9403 01:25:27.466163 7. 0000000100000000-000000023fffffff: RAM
9404 01:25:27.466287 Passing 5 GPIOs to payload:
9405 01:25:27.472409 NAME | PORT | POLARITY | VALUE
9406 01:25:27.476023 EC in RW | 0x000000aa | low | undefined
9407 01:25:27.482516 EC interrupt | 0x00000005 | low | undefined
9408 01:25:27.485976 TPM interrupt | 0x000000ab | high | undefined
9409 01:25:27.489291 SD card detect | 0x00000011 | high | undefined
9410 01:25:27.495548 speaker enable | 0x00000093 | high | undefined
9411 01:25:27.499083 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9412 01:25:27.502488 in-header: 03 f9 00 00 02 00 00 00
9413 01:25:27.502612 in-data: 02 00
9414 01:25:27.505581 ADC[4]: Raw value=905096 ID=7
9415 01:25:27.509241 ADC[3]: Raw value=213810 ID=1
9416 01:25:27.509360 RAM Code: 0x71
9417 01:25:27.512315 ADC[6]: Raw value=75332 ID=0
9418 01:25:27.515828 ADC[5]: Raw value=213072 ID=1
9419 01:25:27.515940 SKU Code: 0x1
9420 01:25:27.522395 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2fd0
9421 01:25:27.525837 coreboot table: 964 bytes.
9422 01:25:27.529443 IMD ROOT 0. 0xfffff000 0x00001000
9423 01:25:27.532339 IMD SMALL 1. 0xffffe000 0x00001000
9424 01:25:27.535894 RO MCACHE 2. 0xffffc000 0x00001104
9425 01:25:27.538978 CONSOLE 3. 0xfff7c000 0x00080000
9426 01:25:27.542416 FMAP 4. 0xfff7b000 0x00000452
9427 01:25:27.545642 TIME STAMP 5. 0xfff7a000 0x00000910
9428 01:25:27.548998 VBOOT WORK 6. 0xfff66000 0x00014000
9429 01:25:27.552654 RAMOOPS 7. 0xffe66000 0x00100000
9430 01:25:27.555872 COREBOOT 8. 0xffe64000 0x00002000
9431 01:25:27.555992 IMD small region:
9432 01:25:27.559339 IMD ROOT 0. 0xffffec00 0x00000400
9433 01:25:27.562132 VPD 1. 0xffffeb80 0x0000006c
9434 01:25:27.565885 MMC STATUS 2. 0xffffeb60 0x00000004
9435 01:25:27.572057 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9436 01:25:27.575950 Probing TPM: done!
9437 01:25:27.578816 Connected to device vid:did:rid of 1ae0:0028:00
9438 01:25:27.589165 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9439 01:25:27.592054 Initialized TPM device CR50 revision 0
9440 01:25:27.595519 Checking cr50 for pending updates
9441 01:25:27.599093 Reading cr50 TPM mode
9442 01:25:27.607958 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9443 01:25:27.614383 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9444 01:25:27.654627 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9445 01:25:27.657763 Checking segment from ROM address 0x40100000
9446 01:25:27.661232 Checking segment from ROM address 0x4010001c
9447 01:25:27.668226 Loading segment from ROM address 0x40100000
9448 01:25:27.668349 code (compression=0)
9449 01:25:27.678073 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9450 01:25:27.684584 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9451 01:25:27.684738 it's not compressed!
9452 01:25:27.691821 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9453 01:25:27.694970 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9454 01:25:27.714752 Loading segment from ROM address 0x4010001c
9455 01:25:27.714933 Entry Point 0x80000000
9456 01:25:27.718346 Loaded segments
9457 01:25:27.721595 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9458 01:25:27.728350 Jumping to boot code at 0x80000000(0xffe64000)
9459 01:25:27.735334 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9460 01:25:27.741462 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9461 01:25:27.749306 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9462 01:25:27.752807 Checking segment from ROM address 0x40100000
9463 01:25:27.755899 Checking segment from ROM address 0x4010001c
9464 01:25:27.762845 Loading segment from ROM address 0x40100000
9465 01:25:27.762996 code (compression=1)
9466 01:25:27.769404 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9467 01:25:27.779305 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9468 01:25:27.779474 using LZMA
9469 01:25:27.787707 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9470 01:25:27.794440 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9471 01:25:27.797988 Loading segment from ROM address 0x4010001c
9472 01:25:27.798095 Entry Point 0x54601000
9473 01:25:27.801264 Loaded segments
9474 01:25:27.804182 NOTICE: MT8192 bl31_setup
9475 01:25:27.811327 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9476 01:25:27.815098 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9477 01:25:27.818259 WARNING: region 0:
9478 01:25:27.821444 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 01:25:27.821569 WARNING: region 1:
9480 01:25:27.828316 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9481 01:25:27.828435 WARNING: region 2:
9482 01:25:27.834999 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9483 01:25:27.838143 WARNING: region 3:
9484 01:25:27.841451 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 01:25:27.845095 WARNING: region 4:
9486 01:25:27.848175 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 01:25:27.851520 WARNING: region 5:
9488 01:25:27.854911 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 01:25:27.858365 WARNING: region 6:
9490 01:25:27.861689 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 01:25:27.861822 WARNING: region 7:
9492 01:25:27.868709 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 01:25:27.875145 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9494 01:25:27.878183 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9495 01:25:27.881738 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9496 01:25:27.885100 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9497 01:25:27.891994 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9498 01:25:27.895103 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9499 01:25:27.901844 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9500 01:25:27.905272 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9501 01:25:27.908773 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9502 01:25:27.915507 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9503 01:25:27.918401 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9504 01:25:27.922318 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9505 01:25:27.928887 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9506 01:25:27.932031 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9507 01:25:27.938708 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9508 01:25:27.942184 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9509 01:25:27.945613 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9510 01:25:27.952298 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9511 01:25:27.955183 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9512 01:25:27.958660 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9513 01:25:27.965413 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9514 01:25:27.968961 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9515 01:25:27.975834 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9516 01:25:27.978975 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9517 01:25:27.982532 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9518 01:25:27.988549 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9519 01:25:27.992496 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9520 01:25:27.998870 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9521 01:25:28.002206 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9522 01:25:28.005564 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9523 01:25:28.012143 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9524 01:25:28.015339 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9525 01:25:28.018969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9526 01:25:28.025647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9527 01:25:28.028761 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9528 01:25:28.032363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9529 01:25:28.035938 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9530 01:25:28.039313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9531 01:25:28.045517 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9532 01:25:28.049062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9533 01:25:28.052361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9534 01:25:28.056140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9535 01:25:28.062181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9536 01:25:28.065982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9537 01:25:28.069024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9538 01:25:28.072466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9539 01:25:28.079287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9540 01:25:28.082396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9541 01:25:28.085610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9542 01:25:28.092401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9543 01:25:28.095861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9544 01:25:28.102820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9545 01:25:28.105904 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9546 01:25:28.109678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9547 01:25:28.115922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9548 01:25:28.119458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9549 01:25:28.126140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9550 01:25:28.129257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9551 01:25:28.136075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9552 01:25:28.139771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9553 01:25:28.143104 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9554 01:25:28.149966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9555 01:25:28.153160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9556 01:25:28.159642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9557 01:25:28.163288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9558 01:25:28.169568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9559 01:25:28.173143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9560 01:25:28.176462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9561 01:25:28.182939 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9562 01:25:28.186148 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9563 01:25:28.192878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9564 01:25:28.196067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9565 01:25:28.203160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9566 01:25:28.206495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9567 01:25:28.209809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9568 01:25:28.216480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9569 01:25:28.219412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9570 01:25:28.226231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9571 01:25:28.229732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9572 01:25:28.236325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9573 01:25:28.239403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9574 01:25:28.243160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9575 01:25:28.250075 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9576 01:25:28.253303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9577 01:25:28.259839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9578 01:25:28.263333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9579 01:25:28.269837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9580 01:25:28.272870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9581 01:25:28.276250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9582 01:25:28.283273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9583 01:25:28.286489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9584 01:25:28.293530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9585 01:25:28.296860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9586 01:25:28.303684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9587 01:25:28.306491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9588 01:25:28.310557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9589 01:25:28.316919 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9590 01:25:28.320458 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9591 01:25:28.323483 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9592 01:25:28.326660 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9593 01:25:28.333600 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9594 01:25:28.336575 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9595 01:25:28.340493 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9596 01:25:28.346716 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9597 01:25:28.350167 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9598 01:25:28.356577 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9599 01:25:28.360028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9600 01:25:28.363733 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9601 01:25:28.369989 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9602 01:25:28.373500 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9603 01:25:28.380369 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9604 01:25:28.383419 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9605 01:25:28.386543 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9606 01:25:28.393338 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9607 01:25:28.396758 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9608 01:25:28.403262 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9609 01:25:28.406511 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9610 01:25:28.410038 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9611 01:25:28.416450 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9612 01:25:28.420184 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9613 01:25:28.423632 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9614 01:25:28.426917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9615 01:25:28.430201 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9616 01:25:28.436637 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9617 01:25:28.439825 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9618 01:25:28.443328 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9619 01:25:28.449965 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9620 01:25:28.453340 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9621 01:25:28.460181 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9622 01:25:28.463738 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9623 01:25:28.467188 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9624 01:25:28.473520 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9625 01:25:28.477117 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9626 01:25:28.483834 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9627 01:25:28.487270 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9628 01:25:28.490245 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9629 01:25:28.497026 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9630 01:25:28.500239 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9631 01:25:28.503740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9632 01:25:28.510419 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9633 01:25:28.513574 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9634 01:25:28.520066 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9635 01:25:28.523765 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9636 01:25:28.527035 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9637 01:25:28.533937 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9638 01:25:28.536936 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9639 01:25:28.540102 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9640 01:25:28.546721 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9641 01:25:28.550133 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9642 01:25:28.557416 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9643 01:25:28.560697 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9644 01:25:28.563649 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9645 01:25:28.570313 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9646 01:25:28.573780 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9647 01:25:28.580632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9648 01:25:28.583737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9649 01:25:28.587108 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9650 01:25:28.593551 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9651 01:25:28.596948 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9652 01:25:28.600578 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9653 01:25:28.607168 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9654 01:25:28.610646 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9655 01:25:28.616886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9656 01:25:28.620378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9657 01:25:28.623503 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9658 01:25:28.630274 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9659 01:25:28.633695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9660 01:25:28.640137 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9661 01:25:28.643587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9662 01:25:28.647202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9663 01:25:28.653878 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9664 01:25:28.657364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9665 01:25:28.660047 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9666 01:25:28.666753 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9667 01:25:28.670332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9668 01:25:28.676562 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9669 01:25:28.680148 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9670 01:25:28.686977 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9671 01:25:28.689598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9672 01:25:28.693662 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9673 01:25:28.699753 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9674 01:25:28.703120 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9675 01:25:28.709752 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9676 01:25:28.712773 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9677 01:25:28.716589 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9678 01:25:28.722649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9679 01:25:28.726018 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9680 01:25:28.729356 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9681 01:25:28.736060 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9682 01:25:28.739428 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9683 01:25:28.746456 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9684 01:25:28.749649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9685 01:25:28.756206 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9686 01:25:28.759759 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9687 01:25:28.762826 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9688 01:25:28.769221 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9689 01:25:28.772503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9690 01:25:28.779456 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9691 01:25:28.782925 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9692 01:25:28.789246 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9693 01:25:28.792807 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9694 01:25:28.796085 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9695 01:25:28.802490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9696 01:25:28.806168 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9697 01:25:28.812709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9698 01:25:28.815999 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9699 01:25:28.819543 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9700 01:25:28.825673 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9701 01:25:28.829119 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9702 01:25:28.835757 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9703 01:25:28.839018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9704 01:25:28.842459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9705 01:25:28.849215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9706 01:25:28.852854 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9707 01:25:28.858921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9708 01:25:28.862455 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9709 01:25:28.869073 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9710 01:25:28.872821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9711 01:25:28.875926 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9712 01:25:28.882113 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9713 01:25:28.885503 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9714 01:25:28.892271 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9715 01:25:28.895828 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9716 01:25:28.899079 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9717 01:25:28.905810 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9718 01:25:28.908608 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9719 01:25:28.915316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9720 01:25:28.918817 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9721 01:25:28.925334 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9722 01:25:28.928736 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9723 01:25:28.931925 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9724 01:25:28.935447 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9725 01:25:28.938797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9726 01:25:28.945703 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9727 01:25:28.948917 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9728 01:25:28.951939 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9729 01:25:28.959093 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9730 01:25:28.962213 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9731 01:25:28.965793 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9732 01:25:28.971989 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9733 01:25:28.975278 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9734 01:25:28.982233 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9735 01:25:28.985798 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9736 01:25:28.988539 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9737 01:25:28.995329 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9738 01:25:28.998423 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9739 01:25:29.001928 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9740 01:25:29.008322 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9741 01:25:29.011731 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9742 01:25:29.015087 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9743 01:25:29.021970 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9744 01:25:29.025189 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9745 01:25:29.031960 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9746 01:25:29.035206 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9747 01:25:29.038826 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9748 01:25:29.045069 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9749 01:25:29.048230 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9750 01:25:29.051718 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9751 01:25:29.058746 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9752 01:25:29.061916 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9753 01:25:29.064920 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9754 01:25:29.071695 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9755 01:25:29.074906 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9756 01:25:29.081609 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9757 01:25:29.084866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9758 01:25:29.088240 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9759 01:25:29.094775 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9760 01:25:29.098318 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9761 01:25:29.101168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9762 01:25:29.107810 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9763 01:25:29.111494 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9764 01:25:29.114651 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9765 01:25:29.117862 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9766 01:25:29.121277 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9767 01:25:29.128154 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9768 01:25:29.131321 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9769 01:25:29.134701 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9770 01:25:29.137756 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9771 01:25:29.144457 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9772 01:25:29.147937 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9773 01:25:29.151224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9774 01:25:29.157694 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9775 01:25:29.161171 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9776 01:25:29.164869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9777 01:25:29.171031 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9778 01:25:29.174482 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9779 01:25:29.181265 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9780 01:25:29.184523 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9781 01:25:29.191396 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9782 01:25:29.194138 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9783 01:25:29.197804 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9784 01:25:29.204301 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9785 01:25:29.208259 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9786 01:25:29.214366 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9787 01:25:29.218039 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9788 01:25:29.220764 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9789 01:25:29.227431 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9790 01:25:29.230898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9791 01:25:29.237866 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9792 01:25:29.240886 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9793 01:25:29.244134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9794 01:25:29.251141 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9795 01:25:29.254531 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9796 01:25:29.261164 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9797 01:25:29.264457 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9798 01:25:29.267632 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9799 01:25:29.274131 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9800 01:25:29.277659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9801 01:25:29.284341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9802 01:25:29.287563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9803 01:25:29.290773 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9804 01:25:29.297758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9805 01:25:29.300824 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9806 01:25:29.307460 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9807 01:25:29.310735 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9808 01:25:29.314103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9809 01:25:29.320619 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9810 01:25:29.324322 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9811 01:25:29.330552 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9812 01:25:29.333960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9813 01:25:29.340603 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9814 01:25:29.343844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9815 01:25:29.347416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9816 01:25:29.354019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9817 01:25:29.357090 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9818 01:25:29.363921 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9819 01:25:29.367087 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9820 01:25:29.371164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9821 01:25:29.377232 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9822 01:25:29.380879 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9823 01:25:29.387583 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9824 01:25:29.390537 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9825 01:25:29.393806 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9826 01:25:29.400293 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9827 01:25:29.403849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9828 01:25:29.410597 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9829 01:25:29.414170 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9830 01:25:29.417465 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9831 01:25:29.423995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9832 01:25:29.427288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9833 01:25:29.434311 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9834 01:25:29.437172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9835 01:25:29.440303 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9836 01:25:29.447254 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9837 01:25:29.450310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9838 01:25:29.457115 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9839 01:25:29.460413 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9840 01:25:29.463493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9841 01:25:29.470535 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9842 01:25:29.473742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9843 01:25:29.480164 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9844 01:25:29.483747 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9845 01:25:29.490635 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9846 01:25:29.493820 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9847 01:25:29.496922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9848 01:25:29.503879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9849 01:25:29.507307 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9850 01:25:29.513507 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9851 01:25:29.516996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9852 01:25:29.523443 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9853 01:25:29.526815 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9854 01:25:29.530180 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9855 01:25:29.536750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9856 01:25:29.540137 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9857 01:25:29.546595 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9858 01:25:29.549799 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9859 01:25:29.557037 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9860 01:25:29.560229 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9861 01:25:29.563987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9862 01:25:29.570573 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9863 01:25:29.573465 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9864 01:25:29.580440 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9865 01:25:29.583489 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9866 01:25:29.590195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9867 01:25:29.593543 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9868 01:25:29.596884 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9869 01:25:29.603392 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9870 01:25:29.606575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9871 01:25:29.613283 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9872 01:25:29.616682 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9873 01:25:29.623417 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9874 01:25:29.626682 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9875 01:25:29.633305 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9876 01:25:29.636590 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9877 01:25:29.639861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9878 01:25:29.646345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9879 01:25:29.649777 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9880 01:25:29.656246 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9881 01:25:29.659839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9882 01:25:29.666142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9883 01:25:29.669762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9884 01:25:29.672819 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9885 01:25:29.679430 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9886 01:25:29.682888 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9887 01:25:29.689722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9888 01:25:29.692903 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9889 01:25:29.699368 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9890 01:25:29.702702 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9891 01:25:29.706227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9892 01:25:29.713067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9893 01:25:29.716214 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9894 01:25:29.722715 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9895 01:25:29.726459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9896 01:25:29.729633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9897 01:25:29.736338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9898 01:25:29.739268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9899 01:25:29.745991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9900 01:25:29.749413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9901 01:25:29.755882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9902 01:25:29.759233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9903 01:25:29.765956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9904 01:25:29.769266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9905 01:25:29.776172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9906 01:25:29.779457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9907 01:25:29.786168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9908 01:25:29.789835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9909 01:25:29.795881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9910 01:25:29.799288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9911 01:25:29.806003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9912 01:25:29.809068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9913 01:25:29.815937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9914 01:25:29.819075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9915 01:25:29.826007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9916 01:25:29.828879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9917 01:25:29.835489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9918 01:25:29.838976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9919 01:25:29.845611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9920 01:25:29.849158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9921 01:25:29.855960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9922 01:25:29.858991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9923 01:25:29.865533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9924 01:25:29.868598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9925 01:25:29.875550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9926 01:25:29.878560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9927 01:25:29.882171 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9928 01:25:29.885464 INFO: [APUAPC] vio 0
9929 01:25:29.888892 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9930 01:25:29.895611 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9931 01:25:29.899125 INFO: [APUAPC] D0_APC_0: 0x400510
9932 01:25:29.902482 INFO: [APUAPC] D0_APC_1: 0x0
9933 01:25:29.905553 INFO: [APUAPC] D0_APC_2: 0x1540
9934 01:25:29.905638 INFO: [APUAPC] D0_APC_3: 0x0
9935 01:25:29.909270 INFO: [APUAPC] D1_APC_0: 0xffffffff
9936 01:25:29.915896 INFO: [APUAPC] D1_APC_1: 0xffffffff
9937 01:25:29.915991 INFO: [APUAPC] D1_APC_2: 0x3fffff
9938 01:25:29.918750 INFO: [APUAPC] D1_APC_3: 0x0
9939 01:25:29.921953 INFO: [APUAPC] D2_APC_0: 0xffffffff
9940 01:25:29.925469 INFO: [APUAPC] D2_APC_1: 0xffffffff
9941 01:25:29.928993 INFO: [APUAPC] D2_APC_2: 0x3fffff
9942 01:25:29.932149 INFO: [APUAPC] D2_APC_3: 0x0
9943 01:25:29.935636 INFO: [APUAPC] D3_APC_0: 0xffffffff
9944 01:25:29.939049 INFO: [APUAPC] D3_APC_1: 0xffffffff
9945 01:25:29.942303 INFO: [APUAPC] D3_APC_2: 0x3fffff
9946 01:25:29.945390 INFO: [APUAPC] D3_APC_3: 0x0
9947 01:25:29.948684 INFO: [APUAPC] D4_APC_0: 0xffffffff
9948 01:25:29.952492 INFO: [APUAPC] D4_APC_1: 0xffffffff
9949 01:25:29.955273 INFO: [APUAPC] D4_APC_2: 0x3fffff
9950 01:25:29.959132 INFO: [APUAPC] D4_APC_3: 0x0
9951 01:25:29.962103 INFO: [APUAPC] D5_APC_0: 0xffffffff
9952 01:25:29.965820 INFO: [APUAPC] D5_APC_1: 0xffffffff
9953 01:25:29.968723 INFO: [APUAPC] D5_APC_2: 0x3fffff
9954 01:25:29.972083 INFO: [APUAPC] D5_APC_3: 0x0
9955 01:25:29.975493 INFO: [APUAPC] D6_APC_0: 0xffffffff
9956 01:25:29.978681 INFO: [APUAPC] D6_APC_1: 0xffffffff
9957 01:25:29.982568 INFO: [APUAPC] D6_APC_2: 0x3fffff
9958 01:25:29.985739 INFO: [APUAPC] D6_APC_3: 0x0
9959 01:25:29.988651 INFO: [APUAPC] D7_APC_0: 0xffffffff
9960 01:25:29.992108 INFO: [APUAPC] D7_APC_1: 0xffffffff
9961 01:25:29.995239 INFO: [APUAPC] D7_APC_2: 0x3fffff
9962 01:25:29.998794 INFO: [APUAPC] D7_APC_3: 0x0
9963 01:25:30.002373 INFO: [APUAPC] D8_APC_0: 0xffffffff
9964 01:25:30.005728 INFO: [APUAPC] D8_APC_1: 0xffffffff
9965 01:25:30.009013 INFO: [APUAPC] D8_APC_2: 0x3fffff
9966 01:25:30.012168 INFO: [APUAPC] D8_APC_3: 0x0
9967 01:25:30.015184 INFO: [APUAPC] D9_APC_0: 0xffffffff
9968 01:25:30.018481 INFO: [APUAPC] D9_APC_1: 0xffffffff
9969 01:25:30.022340 INFO: [APUAPC] D9_APC_2: 0x3fffff
9970 01:25:30.025563 INFO: [APUAPC] D9_APC_3: 0x0
9971 01:25:30.029029 INFO: [APUAPC] D10_APC_0: 0xffffffff
9972 01:25:30.031883 INFO: [APUAPC] D10_APC_1: 0xffffffff
9973 01:25:30.035494 INFO: [APUAPC] D10_APC_2: 0x3fffff
9974 01:25:30.038683 INFO: [APUAPC] D10_APC_3: 0x0
9975 01:25:30.042252 INFO: [APUAPC] D11_APC_0: 0xffffffff
9976 01:25:30.045540 INFO: [APUAPC] D11_APC_1: 0xffffffff
9977 01:25:30.048394 INFO: [APUAPC] D11_APC_2: 0x3fffff
9978 01:25:30.052423 INFO: [APUAPC] D11_APC_3: 0x0
9979 01:25:30.055177 INFO: [APUAPC] D12_APC_0: 0xffffffff
9980 01:25:30.058393 INFO: [APUAPC] D12_APC_1: 0xffffffff
9981 01:25:30.061622 INFO: [APUAPC] D12_APC_2: 0x3fffff
9982 01:25:30.064812 INFO: [APUAPC] D12_APC_3: 0x0
9983 01:25:30.068398 INFO: [APUAPC] D13_APC_0: 0xffffffff
9984 01:25:30.071633 INFO: [APUAPC] D13_APC_1: 0xffffffff
9985 01:25:30.075361 INFO: [APUAPC] D13_APC_2: 0x3fffff
9986 01:25:30.078567 INFO: [APUAPC] D13_APC_3: 0x0
9987 01:25:30.081777 INFO: [APUAPC] D14_APC_0: 0xffffffff
9988 01:25:30.085389 INFO: [APUAPC] D14_APC_1: 0xffffffff
9989 01:25:30.088264 INFO: [APUAPC] D14_APC_2: 0x3fffff
9990 01:25:30.092114 INFO: [APUAPC] D14_APC_3: 0x0
9991 01:25:30.095359 INFO: [APUAPC] D15_APC_0: 0xffffffff
9992 01:25:30.098119 INFO: [APUAPC] D15_APC_1: 0xffffffff
9993 01:25:30.101673 INFO: [APUAPC] D15_APC_2: 0x3fffff
9994 01:25:30.105067 INFO: [APUAPC] D15_APC_3: 0x0
9995 01:25:30.108547 INFO: [APUAPC] APC_CON: 0x4
9996 01:25:30.111448 INFO: [NOCDAPC] D0_APC_0: 0x0
9997 01:25:30.111566 INFO: [NOCDAPC] D0_APC_1: 0x0
9998 01:25:30.115239 INFO: [NOCDAPC] D1_APC_0: 0x0
9999 01:25:30.117982 INFO: [NOCDAPC] D1_APC_1: 0xfff
10000 01:25:30.121494 INFO: [NOCDAPC] D2_APC_0: 0x0
10001 01:25:30.124906 INFO: [NOCDAPC] D2_APC_1: 0xfff
10002 01:25:30.128105 INFO: [NOCDAPC] D3_APC_0: 0x0
10003 01:25:30.131613 INFO: [NOCDAPC] D3_APC_1: 0xfff
10004 01:25:30.134617 INFO: [NOCDAPC] D4_APC_0: 0x0
10005 01:25:30.137928 INFO: [NOCDAPC] D4_APC_1: 0xfff
10006 01:25:30.141391 INFO: [NOCDAPC] D5_APC_0: 0x0
10007 01:25:30.141507 INFO: [NOCDAPC] D5_APC_1: 0xfff
10008 01:25:30.144520 INFO: [NOCDAPC] D6_APC_0: 0x0
10009 01:25:30.148377 INFO: [NOCDAPC] D6_APC_1: 0xfff
10010 01:25:30.151141 INFO: [NOCDAPC] D7_APC_0: 0x0
10011 01:25:30.154537 INFO: [NOCDAPC] D7_APC_1: 0xfff
10012 01:25:30.158139 INFO: [NOCDAPC] D8_APC_0: 0x0
10013 01:25:30.161335 INFO: [NOCDAPC] D8_APC_1: 0xfff
10014 01:25:30.164562 INFO: [NOCDAPC] D9_APC_0: 0x0
10015 01:25:30.167969 INFO: [NOCDAPC] D9_APC_1: 0xfff
10016 01:25:30.171430 INFO: [NOCDAPC] D10_APC_0: 0x0
10017 01:25:30.174661 INFO: [NOCDAPC] D10_APC_1: 0xfff
10018 01:25:30.177793 INFO: [NOCDAPC] D11_APC_0: 0x0
10019 01:25:30.177919 INFO: [NOCDAPC] D11_APC_1: 0xfff
10020 01:25:30.181424 INFO: [NOCDAPC] D12_APC_0: 0x0
10021 01:25:30.184824 INFO: [NOCDAPC] D12_APC_1: 0xfff
10022 01:25:30.187902 INFO: [NOCDAPC] D13_APC_0: 0x0
10023 01:25:30.191307 INFO: [NOCDAPC] D13_APC_1: 0xfff
10024 01:25:30.194828 INFO: [NOCDAPC] D14_APC_0: 0x0
10025 01:25:30.198025 INFO: [NOCDAPC] D14_APC_1: 0xfff
10026 01:25:30.201024 INFO: [NOCDAPC] D15_APC_0: 0x0
10027 01:25:30.204530 INFO: [NOCDAPC] D15_APC_1: 0xfff
10028 01:25:30.207656 INFO: [NOCDAPC] APC_CON: 0x4
10029 01:25:30.210817 INFO: [APUAPC] set_apusys_apc done
10030 01:25:30.214347 INFO: [DEVAPC] devapc_init done
10031 01:25:30.217749 INFO: GICv3 without legacy support detected.
10032 01:25:30.221239 INFO: ARM GICv3 driver initialized in EL3
10033 01:25:30.224380 INFO: Maximum SPI INTID supported: 639
10034 01:25:30.230969 INFO: BL31: Initializing runtime services
10035 01:25:30.234134 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10036 01:25:30.237966 INFO: SPM: enable CPC mode
10037 01:25:30.244318 INFO: mcdi ready for mcusys-off-idle and system suspend
10038 01:25:30.247345 INFO: BL31: Preparing for EL3 exit to normal world
10039 01:25:30.251058 INFO: Entry point address = 0x80000000
10040 01:25:30.254001 INFO: SPSR = 0x8
10041 01:25:30.259306
10042 01:25:30.259429
10043 01:25:30.259526
10044 01:25:30.260324 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10045 01:25:30.260433 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10046 01:25:30.260532 Setting prompt string to ['asurada:']
10047 01:25:30.260647 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10048 01:25:30.262941 Starting depthcharge on Spherion...
10049 01:25:30.263043
10050 01:25:30.263132 Wipe memory regions:
10051 01:25:30.263218
10052 01:25:30.266154 [0x00000040000000, 0x00000054600000)
10053 01:25:30.388582
10054 01:25:30.388760 [0x00000054660000, 0x00000080000000)
10055 01:25:30.649413
10056 01:25:30.649584 [0x000000821a7280, 0x000000ffe64000)
10057 01:25:31.393765
10058 01:25:31.393925 [0x00000100000000, 0x00000240000000)
10059 01:25:33.284064
10060 01:25:33.287655 Initializing XHCI USB controller at 0x11200000.
10061 01:25:34.325457
10062 01:25:34.328770 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10063 01:25:34.328877
10064 01:25:34.328945
10065 01:25:34.329007
10066 01:25:34.329290 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 01:25:34.429642 asurada: tftpboot 192.168.201.1 11368543/tftp-deploy-5parntst/kernel/image.itb 11368543/tftp-deploy-5parntst/kernel/cmdline
10069 01:25:34.429849 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 01:25:34.429958 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10071 01:25:34.434091 tftpboot 192.168.201.1 11368543/tftp-deploy-5parntst/kernel/image.itp-deploy-5parntst/kernel/cmdline
10072 01:25:34.434214
10073 01:25:34.434310 Waiting for link
10074 01:25:34.594544
10075 01:25:34.594750 R8152: Initializing
10076 01:25:34.594847
10077 01:25:34.598134 Version 9 (ocp_data = 6010)
10078 01:25:34.598252
10079 01:25:34.601187 R8152: Done initializing
10080 01:25:34.601298
10081 01:25:34.601393 Adding net device
10082 01:25:36.547211
10083 01:25:36.547433 done.
10084 01:25:36.547552
10085 01:25:36.547704 MAC: 00:e0:4c:78:7a:aa
10086 01:25:36.547814
10087 01:25:36.550678 Sending DHCP discover... done.
10088 01:25:36.550839
10089 01:25:43.121385 Waiting for reply... done.
10090 01:25:43.121635
10091 01:25:43.121732 Sending DHCP request... done.
10092 01:25:43.121833
10093 01:25:43.128497 Waiting for reply... done.
10094 01:25:43.128606
10095 01:25:43.128698 My ip is 192.168.201.12
10096 01:25:43.128785
10097 01:25:43.131644 The DHCP server ip is 192.168.201.1
10098 01:25:43.131760
10099 01:25:43.138570 TFTP server IP predefined by user: 192.168.201.1
10100 01:25:43.138697
10101 01:25:43.145464 Bootfile predefined by user: 11368543/tftp-deploy-5parntst/kernel/image.itb
10102 01:25:43.145573
10103 01:25:43.145664 Sending tftp read request... done.
10104 01:25:43.148017
10105 01:25:43.152134 Waiting for the transfer...
10106 01:25:43.152242
10107 01:25:43.446869 00000000 ################################################################
10108 01:25:43.447051
10109 01:25:43.743890 00080000 ################################################################
10110 01:25:43.744080
10111 01:25:44.038067 00100000 ################################################################
10112 01:25:44.038252
10113 01:25:44.335807 00180000 ################################################################
10114 01:25:44.335994
10115 01:25:44.624208 00200000 ################################################################
10116 01:25:44.624364
10117 01:25:44.896382 00280000 ################################################################
10118 01:25:44.896555
10119 01:25:45.186947 00300000 ################################################################
10120 01:25:45.187094
10121 01:25:45.458917 00380000 ################################################################
10122 01:25:45.459065
10123 01:25:45.713930 00400000 ################################################################
10124 01:25:45.714063
10125 01:25:45.978755 00480000 ################################################################
10126 01:25:45.978884
10127 01:25:46.237677 00500000 ################################################################
10128 01:25:46.237818
10129 01:25:46.491780 00580000 ################################################################
10130 01:25:46.491994
10131 01:25:46.750771 00600000 ################################################################
10132 01:25:46.750932
10133 01:25:47.003426 00680000 ################################################################
10134 01:25:47.003640
10135 01:25:47.257902 00700000 ################################################################
10136 01:25:47.258078
10137 01:25:47.493053 00780000 ################################################################
10138 01:25:47.493223
10139 01:25:47.729994 00800000 ################################################################
10140 01:25:47.730163
10141 01:25:47.968514 00880000 ################################################################
10142 01:25:47.968666
10143 01:25:48.205824 00900000 ################################################################
10144 01:25:48.205973
10145 01:25:48.442108 00980000 ################################################################
10146 01:25:48.442303
10147 01:25:48.674464 00a00000 ################################################################
10148 01:25:48.674642
10149 01:25:48.908144 00a80000 ################################################################
10150 01:25:48.908293
10151 01:25:49.144942 00b00000 ################################################################
10152 01:25:49.145128
10153 01:25:49.384023 00b80000 ################################################################
10154 01:25:49.384191
10155 01:25:49.620851 00c00000 ################################################################
10156 01:25:49.620994
10157 01:25:49.868448 00c80000 ################################################################
10158 01:25:49.868623
10159 01:25:50.105778 00d00000 ################################################################
10160 01:25:50.105948
10161 01:25:50.342271 00d80000 ################################################################
10162 01:25:50.342439
10163 01:25:50.580497 00e00000 ################################################################
10164 01:25:50.580630
10165 01:25:50.840142 00e80000 ################################################################
10166 01:25:50.840280
10167 01:25:51.129455 00f00000 ################################################################
10168 01:25:51.129588
10169 01:25:51.394097 00f80000 ################################################################
10170 01:25:51.394229
10171 01:25:51.648240 01000000 ################################################################
10172 01:25:51.648372
10173 01:25:51.906451 01080000 ################################################################
10174 01:25:51.906616
10175 01:25:52.168215 01100000 ################################################################
10176 01:25:52.168347
10177 01:25:52.436055 01180000 ################################################################
10178 01:25:52.436236
10179 01:25:52.710173 01200000 ################################################################
10180 01:25:52.710309
10181 01:25:52.968143 01280000 ################################################################
10182 01:25:52.968276
10183 01:25:53.218776 01300000 ################################################################
10184 01:25:53.218909
10185 01:25:53.478865 01380000 ################################################################
10186 01:25:53.479025
10187 01:25:53.731052 01400000 ################################################################
10188 01:25:53.731191
10189 01:25:53.986164 01480000 ################################################################
10190 01:25:53.986302
10191 01:25:54.235388 01500000 ################################################################
10192 01:25:54.235548
10193 01:25:54.486188 01580000 ################################################################
10194 01:25:54.486330
10195 01:25:54.746263 01600000 ################################################################
10196 01:25:54.746394
10197 01:25:55.014636 01680000 ################################################################
10198 01:25:55.014796
10199 01:25:55.287739 01700000 ################################################################
10200 01:25:55.287901
10201 01:25:55.540945 01780000 ################################################################
10202 01:25:55.541111
10203 01:25:55.810343 01800000 ################################################################
10204 01:25:55.810508
10205 01:25:56.065487 01880000 ################################################################
10206 01:25:56.065623
10207 01:25:56.326969 01900000 ################################################################
10208 01:25:56.327152
10209 01:25:56.582947 01980000 ################################################################
10210 01:25:56.583111
10211 01:25:56.842045 01a00000 ################################################################
10212 01:25:56.842200
10213 01:25:57.093078 01a80000 ################################################################
10214 01:25:57.093237
10215 01:25:57.341901 01b00000 ################################################################
10216 01:25:57.342062
10217 01:25:57.596452 01b80000 ################################################################
10218 01:25:57.596585
10219 01:25:57.848669 01c00000 ################################################################
10220 01:25:57.848837
10221 01:25:58.099554 01c80000 ################################################################
10222 01:25:58.099698
10223 01:25:58.373277 01d00000 ################################################################
10224 01:25:58.373439
10225 01:25:58.634074 01d80000 ################################################################
10226 01:25:58.634206
10227 01:25:58.886933 01e00000 ################################################################
10228 01:25:58.887090
10229 01:25:59.117610 01e80000 ########################################################### done.
10230 01:25:59.117772
10231 01:25:59.121211 The bootfile was 32464226 bytes long.
10232 01:25:59.121327
10233 01:25:59.124321 Sending tftp read request... done.
10234 01:25:59.124426
10235 01:25:59.124519 Waiting for the transfer...
10236 01:25:59.124609
10237 01:25:59.127911 00000000 # done.
10238 01:25:59.128013
10239 01:25:59.134646 Command line loaded dynamically from TFTP file: 11368543/tftp-deploy-5parntst/kernel/cmdline
10240 01:25:59.134753
10241 01:25:59.147987 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10242 01:25:59.148073
10243 01:25:59.151261 Loading FIT.
10244 01:25:59.151340
10245 01:25:59.154505 Image ramdisk-1 has 21376248 bytes.
10246 01:25:59.154581
10247 01:25:59.154652 Image fdt-1 has 47278 bytes.
10248 01:25:59.154745
10249 01:25:59.157866 Image kernel-1 has 11038667 bytes.
10250 01:25:59.157971
10251 01:25:59.167391 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10252 01:25:59.167495
10253 01:25:59.184553 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10254 01:25:59.184669
10255 01:25:59.191252 Choosing best match conf-1 for compat google,spherion-rev2.
10256 01:25:59.195217
10257 01:25:59.199414 Connected to device vid:did:rid of 1ae0:0028:00
10258 01:25:59.207610
10259 01:25:59.211016 tpm_get_response: command 0x17b, return code 0x0
10260 01:25:59.211125
10261 01:25:59.214044 ec_init: CrosEC protocol v3 supported (256, 248)
10262 01:25:59.218148
10263 01:25:59.221544 tpm_cleanup: add release locality here.
10264 01:25:59.221647
10265 01:25:59.221746 Shutting down all USB controllers.
10266 01:25:59.221837
10267 01:25:59.225099 Removing current net device
10268 01:25:59.225197
10269 01:25:59.231466 Exiting depthcharge with code 4 at timestamp: 58306127
10270 01:25:59.231579
10271 01:25:59.235232 LZMA decompressing kernel-1 to 0x821a6718
10272 01:25:59.235334
10273 01:25:59.238241 LZMA decompressing kernel-1 to 0x40000000
10274 01:26:00.625820
10275 01:26:00.625993 jumping to kernel
10276 01:26:00.626699 end: 2.2.4 bootloader-commands (duration 00:00:30) [common]
10277 01:26:00.626847 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10278 01:26:00.626971 Setting prompt string to ['Linux version [0-9]']
10279 01:26:00.627081 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10280 01:26:00.627186 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10281 01:26:00.707780
10282 01:26:00.710683 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10283 01:26:00.714258 start: 2.2.5.1 login-action (timeout 00:03:55) [common]
10284 01:26:00.714366 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10285 01:26:00.714469 Setting prompt string to []
10286 01:26:00.714564 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10287 01:26:00.714669 Using line separator: #'\n'#
10288 01:26:00.714749 No login prompt set.
10289 01:26:00.714820 Parsing kernel messages
10290 01:26:00.714878 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10291 01:26:00.714991 [login-action] Waiting for messages, (timeout 00:03:55)
10292 01:26:00.733995 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j24548-arm64-gcc-10-defconfig-arm64-chromebook-xnj4p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023
10293 01:26:00.736952 [ 0.000000] random: crng init done
10294 01:26:00.743954 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10295 01:26:00.747193 [ 0.000000] efi: UEFI not found.
10296 01:26:00.753702 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10297 01:26:00.760836 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10298 01:26:00.770471 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10299 01:26:00.780456 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10300 01:26:00.786921 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10301 01:26:00.793578 [ 0.000000] printk: bootconsole [mtk8250] enabled
10302 01:26:00.799853 [ 0.000000] NUMA: No NUMA configuration found
10303 01:26:00.806515 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10304 01:26:00.810514 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10305 01:26:00.813125 [ 0.000000] Zone ranges:
10306 01:26:00.819873 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10307 01:26:00.823036 [ 0.000000] DMA32 empty
10308 01:26:00.830070 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10309 01:26:00.833089 [ 0.000000] Movable zone start for each node
10310 01:26:00.836647 [ 0.000000] Early memory node ranges
10311 01:26:00.843194 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10312 01:26:00.849650 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10313 01:26:00.856506 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10314 01:26:00.863196 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10315 01:26:00.866053 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10316 01:26:00.876330 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10317 01:26:00.931809 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10318 01:26:00.938527 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10319 01:26:00.945123 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10320 01:26:00.948061 [ 0.000000] psci: probing for conduit method from DT.
10321 01:26:00.955197 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10322 01:26:00.958187 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10323 01:26:00.965178 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10324 01:26:00.968018 [ 0.000000] psci: SMC Calling Convention v1.2
10325 01:26:00.975109 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10326 01:26:00.978604 [ 0.000000] Detected VIPT I-cache on CPU0
10327 01:26:00.985262 [ 0.000000] CPU features: detected: GIC system register CPU interface
10328 01:26:00.991823 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10329 01:26:00.998184 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10330 01:26:01.004870 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10331 01:26:01.011632 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10332 01:26:01.017984 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10333 01:26:01.024990 [ 0.000000] alternatives: applying boot alternatives
10334 01:26:01.028207 [ 0.000000] Fallback order for Node 0: 0
10335 01:26:01.038145 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10336 01:26:01.038270 [ 0.000000] Policy zone: Normal
10337 01:26:01.054503 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10338 01:26:01.064438 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10339 01:26:01.076173 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10340 01:26:01.086307 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10341 01:26:01.092845 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10342 01:26:01.095880 <6>[ 0.000000] software IO TLB: area num 8.
10343 01:26:01.153148 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10344 01:26:01.302792 <6>[ 0.000000] Memory: 7948680K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 404088K reserved, 32768K cma-reserved)
10345 01:26:01.309607 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10346 01:26:01.316461 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10347 01:26:01.319603 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10348 01:26:01.326258 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10349 01:26:01.332812 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10350 01:26:01.336482 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10351 01:26:01.345990 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10352 01:26:01.353097 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10353 01:26:01.355973 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10354 01:26:01.363466 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10355 01:26:01.367134 <6>[ 0.000000] GICv3: 608 SPIs implemented
10356 01:26:01.373701 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10357 01:26:01.377375 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10358 01:26:01.380460 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10359 01:26:01.390260 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10360 01:26:01.400356 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10361 01:26:01.413606 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10362 01:26:01.420467 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10363 01:26:01.429007 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10364 01:26:01.442265 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10365 01:26:01.449119 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10366 01:26:01.455913 <6>[ 0.009186] Console: colour dummy device 80x25
10367 01:26:01.465671 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10368 01:26:01.472095 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10369 01:26:01.475788 <6>[ 0.029217] LSM: Security Framework initializing
10370 01:26:01.482034 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10371 01:26:01.492283 <6>[ 0.042018] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 01:26:01.502134 <6>[ 0.051433] cblist_init_generic: Setting adjustable number of callback queues.
10373 01:26:01.505151 <6>[ 0.058880] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 01:26:01.515491 <6>[ 0.065258] cblist_init_generic: Setting adjustable number of callback queues.
10375 01:26:01.521795 <6>[ 0.072683] cblist_init_generic: Setting shift to 3 and lim to 1.
10376 01:26:01.525136 <6>[ 0.079119] rcu: Hierarchical SRCU implementation.
10377 01:26:01.531868 <6>[ 0.084132] rcu: Max phase no-delay instances is 1000.
10378 01:26:01.538653 <6>[ 0.091205] EFI services will not be available.
10379 01:26:01.541613 <6>[ 0.096178] smp: Bringing up secondary CPUs ...
10380 01:26:01.550093 <6>[ 0.101263] Detected VIPT I-cache on CPU1
10381 01:26:01.556538 <6>[ 0.101333] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10382 01:26:01.563581 <6>[ 0.101366] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10383 01:26:01.566819 <6>[ 0.101695] Detected VIPT I-cache on CPU2
10384 01:26:01.573015 <6>[ 0.101744] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10385 01:26:01.582851 <6>[ 0.101760] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10386 01:26:01.586401 <6>[ 0.102016] Detected VIPT I-cache on CPU3
10387 01:26:01.593112 <6>[ 0.102063] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10388 01:26:01.599812 <6>[ 0.102076] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10389 01:26:01.603255 <6>[ 0.102380] CPU features: detected: Spectre-v4
10390 01:26:01.609527 <6>[ 0.102386] CPU features: detected: Spectre-BHB
10391 01:26:01.613075 <6>[ 0.102391] Detected PIPT I-cache on CPU4
10392 01:26:01.619942 <6>[ 0.102447] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10393 01:26:01.626020 <6>[ 0.102464] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10394 01:26:01.632686 <6>[ 0.102758] Detected PIPT I-cache on CPU5
10395 01:26:01.639326 <6>[ 0.102820] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10396 01:26:01.646293 <6>[ 0.102836] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10397 01:26:01.649262 <6>[ 0.103121] Detected PIPT I-cache on CPU6
10398 01:26:01.655964 <6>[ 0.103186] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10399 01:26:01.662564 <6>[ 0.103202] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10400 01:26:01.669057 <6>[ 0.103501] Detected PIPT I-cache on CPU7
10401 01:26:01.675935 <6>[ 0.103564] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10402 01:26:01.682412 <6>[ 0.103581] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10403 01:26:01.685775 <6>[ 0.103627] smp: Brought up 1 node, 8 CPUs
10404 01:26:01.692463 <6>[ 0.245051] SMP: Total of 8 processors activated.
10405 01:26:01.695455 <6>[ 0.249972] CPU features: detected: 32-bit EL0 Support
10406 01:26:01.705381 <6>[ 0.255334] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10407 01:26:01.712162 <6>[ 0.264189] CPU features: detected: Common not Private translations
10408 01:26:01.718996 <6>[ 0.270704] CPU features: detected: CRC32 instructions
10409 01:26:01.722080 <6>[ 0.276055] CPU features: detected: RCpc load-acquire (LDAPR)
10410 01:26:01.728845 <6>[ 0.282015] CPU features: detected: LSE atomic instructions
10411 01:26:01.735636 <6>[ 0.287796] CPU features: detected: Privileged Access Never
10412 01:26:01.741907 <6>[ 0.293611] CPU features: detected: RAS Extension Support
10413 01:26:01.748767 <6>[ 0.299220] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10414 01:26:01.751896 <6>[ 0.306443] CPU: All CPU(s) started at EL2
10415 01:26:01.758479 <6>[ 0.310760] alternatives: applying system-wide alternatives
10416 01:26:01.768078 <6>[ 0.321485] devtmpfs: initialized
10417 01:26:01.780431 <6>[ 0.330350] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10418 01:26:01.790230 <6>[ 0.340311] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10419 01:26:01.796498 <6>[ 0.348325] pinctrl core: initialized pinctrl subsystem
10420 01:26:01.800039 <6>[ 0.354964] DMI not present or invalid.
10421 01:26:01.806398 <6>[ 0.359372] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10422 01:26:01.816440 <6>[ 0.366149] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10423 01:26:01.823071 <6>[ 0.373729] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10424 01:26:01.832941 <6>[ 0.381943] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10425 01:26:01.836732 <6>[ 0.390183] audit: initializing netlink subsys (disabled)
10426 01:26:01.846290 <5>[ 0.395879] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10427 01:26:01.852880 <6>[ 0.396586] thermal_sys: Registered thermal governor 'step_wise'
10428 01:26:01.859685 <6>[ 0.403846] thermal_sys: Registered thermal governor 'power_allocator'
10429 01:26:01.862680 <6>[ 0.410102] cpuidle: using governor menu
10430 01:26:01.866626 <6>[ 0.421063] NET: Registered PF_QIPCRTR protocol family
10431 01:26:01.876069 <6>[ 0.426546] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10432 01:26:01.879705 <6>[ 0.433650] ASID allocator initialised with 32768 entries
10433 01:26:01.886428 <6>[ 0.440214] Serial: AMBA PL011 UART driver
10434 01:26:01.895571 <4>[ 0.448948] Trying to register duplicate clock ID: 134
10435 01:26:01.949247 <6>[ 0.506209] KASLR enabled
10436 01:26:01.963440 <6>[ 0.513880] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10437 01:26:01.970196 <6>[ 0.520892] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10438 01:26:01.977006 <6>[ 0.527378] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10439 01:26:01.983451 <6>[ 0.534382] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10440 01:26:01.989916 <6>[ 0.540871] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10441 01:26:01.996489 <6>[ 0.547876] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10442 01:26:02.003230 <6>[ 0.554363] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10443 01:26:02.009988 <6>[ 0.561369] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10444 01:26:02.013275 <6>[ 0.568809] ACPI: Interpreter disabled.
10445 01:26:02.021782 <6>[ 0.575261] iommu: Default domain type: Translated
10446 01:26:02.028113 <6>[ 0.580377] iommu: DMA domain TLB invalidation policy: strict mode
10447 01:26:02.031914 <5>[ 0.587035] SCSI subsystem initialized
10448 01:26:02.038337 <6>[ 0.591280] usbcore: registered new interface driver usbfs
10449 01:26:02.044736 <6>[ 0.597009] usbcore: registered new interface driver hub
10450 01:26:02.048204 <6>[ 0.602564] usbcore: registered new device driver usb
10451 01:26:02.055358 <6>[ 0.608683] pps_core: LinuxPPS API ver. 1 registered
10452 01:26:02.065019 <6>[ 0.613876] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10453 01:26:02.068058 <6>[ 0.623220] PTP clock support registered
10454 01:26:02.071477 <6>[ 0.627460] EDAC MC: Ver: 3.0.0
10455 01:26:02.079463 <6>[ 0.632650] FPGA manager framework
10456 01:26:02.082332 <6>[ 0.636324] Advanced Linux Sound Architecture Driver Initialized.
10457 01:26:02.086045 <6>[ 0.643085] vgaarb: loaded
10458 01:26:02.092980 <6>[ 0.646262] clocksource: Switched to clocksource arch_sys_counter
10459 01:26:02.099609 <5>[ 0.652706] VFS: Disk quotas dquot_6.6.0
10460 01:26:02.106010 <6>[ 0.656894] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10461 01:26:02.109134 <6>[ 0.664084] pnp: PnP ACPI: disabled
10462 01:26:02.117326 <6>[ 0.670732] NET: Registered PF_INET protocol family
10463 01:26:02.126832 <6>[ 0.676323] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10464 01:26:02.138366 <6>[ 0.688618] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10465 01:26:02.148325 <6>[ 0.697433] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10466 01:26:02.155326 <6>[ 0.705401] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10467 01:26:02.161909 <6>[ 0.714102] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10468 01:26:02.173620 <6>[ 0.723847] TCP: Hash tables configured (established 65536 bind 65536)
10469 01:26:02.180274 <6>[ 0.730711] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10470 01:26:02.186878 <6>[ 0.737913] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 01:26:02.193865 <6>[ 0.745615] NET: Registered PF_UNIX/PF_LOCAL protocol family
10472 01:26:02.200380 <6>[ 0.751711] RPC: Registered named UNIX socket transport module.
10473 01:26:02.203552 <6>[ 0.757864] RPC: Registered udp transport module.
10474 01:26:02.210112 <6>[ 0.762799] RPC: Registered tcp transport module.
10475 01:26:02.217284 <6>[ 0.767730] RPC: Registered tcp NFSv4.1 backchannel transport module.
10476 01:26:02.220347 <6>[ 0.774397] PCI: CLS 0 bytes, default 64
10477 01:26:02.223344 <6>[ 0.778788] Unpacking initramfs...
10478 01:26:02.245143 <6>[ 0.794921] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10479 01:26:02.254396 <6>[ 0.803572] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10480 01:26:02.257779 <6>[ 0.812422] kvm [1]: IPA Size Limit: 40 bits
10481 01:26:02.264436 <6>[ 0.816947] kvm [1]: GICv3: no GICV resource entry
10482 01:26:02.268081 <6>[ 0.821968] kvm [1]: disabling GICv2 emulation
10483 01:26:02.274577 <6>[ 0.826655] kvm [1]: GIC system register CPU interface enabled
10484 01:26:02.277636 <6>[ 0.832814] kvm [1]: vgic interrupt IRQ18
10485 01:26:02.284349 <6>[ 0.837176] kvm [1]: VHE mode initialized successfully
10486 01:26:02.291063 <5>[ 0.843669] Initialise system trusted keyrings
10487 01:26:02.297831 <6>[ 0.848506] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10488 01:26:02.304785 <6>[ 0.858507] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10489 01:26:02.311798 <5>[ 0.864913] NFS: Registering the id_resolver key type
10490 01:26:02.314583 <5>[ 0.870210] Key type id_resolver registered
10491 01:26:02.321455 <5>[ 0.874626] Key type id_legacy registered
10492 01:26:02.327827 <6>[ 0.878904] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10493 01:26:02.334331 <6>[ 0.885824] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10494 01:26:02.341183 <6>[ 0.893558] 9p: Installing v9fs 9p2000 file system support
10495 01:26:02.378458 <5>[ 0.931851] Key type asymmetric registered
10496 01:26:02.381790 <5>[ 0.936181] Asymmetric key parser 'x509' registered
10497 01:26:02.391577 <6>[ 0.941323] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10498 01:26:02.395268 <6>[ 0.948937] io scheduler mq-deadline registered
10499 01:26:02.398313 <6>[ 0.953698] io scheduler kyber registered
10500 01:26:02.417301 <6>[ 0.970852] EINJ: ACPI disabled.
10501 01:26:02.449601 <4>[ 0.996545] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10502 01:26:02.459407 <4>[ 1.007338] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 01:26:02.474560 <6>[ 1.028272] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10504 01:26:02.482680 <6>[ 1.036249] printk: console [ttyS0] disabled
10505 01:26:02.511003 <6>[ 1.060898] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10506 01:26:02.517373 <6>[ 1.070376] printk: console [ttyS0] enabled
10507 01:26:02.520287 <6>[ 1.070376] printk: console [ttyS0] enabled
10508 01:26:02.526873 <6>[ 1.079271] printk: bootconsole [mtk8250] disabled
10509 01:26:02.530600 <6>[ 1.079271] printk: bootconsole [mtk8250] disabled
10510 01:26:02.537334 <6>[ 1.090562] SuperH (H)SCI(F) driver initialized
10511 01:26:02.540264 <6>[ 1.095865] msm_serial: driver initialized
10512 01:26:02.554775 <6>[ 1.104910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10513 01:26:02.564708 <6>[ 1.113460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10514 01:26:02.571404 <6>[ 1.122001] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10515 01:26:02.581309 <6>[ 1.130630] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10516 01:26:02.587703 <6>[ 1.139339] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10517 01:26:02.597926 <6>[ 1.148062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10518 01:26:02.607860 <6>[ 1.156603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10519 01:26:02.614631 <6>[ 1.165413] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10520 01:26:02.624724 <6>[ 1.173957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10521 01:26:02.636035 <6>[ 1.189579] loop: module loaded
10522 01:26:02.642316 <6>[ 1.195653] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10523 01:26:02.665565 <4>[ 1.219062] mtk-pmic-keys: Failed to locate of_node [id: -1]
10524 01:26:02.672039 <6>[ 1.225911] megasas: 07.719.03.00-rc1
10525 01:26:02.681798 <6>[ 1.235657] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10526 01:26:02.688957 <6>[ 1.241654] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10527 01:26:02.704567 <6>[ 1.258268] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10528 01:26:02.761444 <6>[ 1.308165] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10529 01:26:03.154870 <6>[ 1.708477] Freeing initrd memory: 20872K
10530 01:26:03.170167 <6>[ 1.724071] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10531 01:26:03.181174 <6>[ 1.735058] tun: Universal TUN/TAP device driver, 1.6
10532 01:26:03.184764 <6>[ 1.741116] thunder_xcv, ver 1.0
10533 01:26:03.188449 <6>[ 1.744618] thunder_bgx, ver 1.0
10534 01:26:03.191664 <6>[ 1.748116] nicpf, ver 1.0
10535 01:26:03.201841 <6>[ 1.752145] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10536 01:26:03.204946 <6>[ 1.759620] hns3: Copyright (c) 2017 Huawei Corporation.
10537 01:26:03.208571 <6>[ 1.765207] hclge is initializing
10538 01:26:03.215109 <6>[ 1.768784] e1000: Intel(R) PRO/1000 Network Driver
10539 01:26:03.221830 <6>[ 1.773913] e1000: Copyright (c) 1999-2006 Intel Corporation.
10540 01:26:03.224952 <6>[ 1.779925] e1000e: Intel(R) PRO/1000 Network Driver
10541 01:26:03.231905 <6>[ 1.785139] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10542 01:26:03.238501 <6>[ 1.791327] igb: Intel(R) Gigabit Ethernet Network Driver
10543 01:26:03.245170 <6>[ 1.796977] igb: Copyright (c) 2007-2014 Intel Corporation.
10544 01:26:03.251380 <6>[ 1.802813] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10545 01:26:03.258181 <6>[ 1.809331] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10546 01:26:03.261829 <6>[ 1.815790] sky2: driver version 1.30
10547 01:26:03.268042 <6>[ 1.820791] VFIO - User Level meta-driver version: 0.3
10548 01:26:03.275204 <6>[ 1.829091] usbcore: registered new interface driver usb-storage
10549 01:26:03.282083 <6>[ 1.835543] usbcore: registered new device driver onboard-usb-hub
10550 01:26:03.290927 <6>[ 1.844653] mt6397-rtc mt6359-rtc: registered as rtc0
10551 01:26:03.301302 <6>[ 1.850116] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T01:24:56 UTC (1693185896)
10552 01:26:03.304011 <6>[ 1.859689] i2c_dev: i2c /dev entries driver
10553 01:26:03.321322 <6>[ 1.871525] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10554 01:26:03.341861 <6>[ 1.895540] cpu cpu0: EM: created perf domain
10555 01:26:03.344884 <6>[ 1.900560] cpu cpu4: EM: created perf domain
10556 01:26:03.353038 <6>[ 1.906224] sdhci: Secure Digital Host Controller Interface driver
10557 01:26:03.359360 <6>[ 1.912657] sdhci: Copyright(c) Pierre Ossman
10558 01:26:03.365845 <6>[ 1.917619] Synopsys Designware Multimedia Card Interface Driver
10559 01:26:03.372881 <6>[ 1.924256] sdhci-pltfm: SDHCI platform and OF driver helper
10560 01:26:03.375757 <6>[ 1.924295] mmc0: CQHCI version 5.10
10561 01:26:03.382486 <6>[ 1.934320] ledtrig-cpu: registered to indicate activity on CPUs
10562 01:26:03.389683 <6>[ 1.941299] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10563 01:26:03.396000 <6>[ 1.948354] usbcore: registered new interface driver usbhid
10564 01:26:03.399008 <6>[ 1.954177] usbhid: USB HID core driver
10565 01:26:03.406220 <6>[ 1.958344] spi_master spi0: will run message pump with realtime priority
10566 01:26:03.449050 <6>[ 1.995957] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10567 01:26:03.465098 <6>[ 2.011896] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10568 01:26:03.472578 <6>[ 2.025478] mmc0: Command Queue Engine enabled
10569 01:26:03.478751 <6>[ 2.030243] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10570 01:26:03.485533 <6>[ 2.037192] cros-ec-spi spi0.0: Chrome EC device registered
10571 01:26:03.488830 <6>[ 2.037501] mmcblk0: mmc0:0001 DA4128 116 GiB
10572 01:26:03.498217 <6>[ 2.051816] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10573 01:26:03.505020 <6>[ 2.058921] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10574 01:26:03.511992 <6>[ 2.064791] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10575 01:26:03.518681 <6>[ 2.070679] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10576 01:26:03.533838 <6>[ 2.084217] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10577 01:26:03.541120 <6>[ 2.094825] NET: Registered PF_PACKET protocol family
10578 01:26:03.544761 <6>[ 2.100214] 9pnet: Installing 9P2000 support
10579 01:26:03.550880 <5>[ 2.104781] Key type dns_resolver registered
10580 01:26:03.554494 <6>[ 2.109772] registered taskstats version 1
10581 01:26:03.561168 <5>[ 2.114158] Loading compiled-in X.509 certificates
10582 01:26:03.590814 <4>[ 2.138035] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 01:26:03.601041 <4>[ 2.148785] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 01:26:03.607420 <3>[ 2.159376] debugfs: File 'uA_load' in directory '/' already present!
10585 01:26:03.614538 <3>[ 2.166086] debugfs: File 'min_uV' in directory '/' already present!
10586 01:26:03.621086 <3>[ 2.172696] debugfs: File 'max_uV' in directory '/' already present!
10587 01:26:03.627333 <3>[ 2.179302] debugfs: File 'constraint_flags' in directory '/' already present!
10588 01:26:03.638525 <3>[ 2.188975] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10589 01:26:03.651885 <6>[ 2.205402] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10590 01:26:03.658599 <6>[ 2.212247] xhci-mtk 11200000.usb: xHCI Host Controller
10591 01:26:03.664953 <6>[ 2.217754] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10592 01:26:03.675386 <6>[ 2.225632] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10593 01:26:03.682246 <6>[ 2.235081] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10594 01:26:03.688970 <6>[ 2.241178] xhci-mtk 11200000.usb: xHCI Host Controller
10595 01:26:03.695576 <6>[ 2.246678] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10596 01:26:03.702352 <6>[ 2.254485] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10597 01:26:03.709131 <6>[ 2.262454] hub 1-0:1.0: USB hub found
10598 01:26:03.712101 <6>[ 2.266479] hub 1-0:1.0: 1 port detected
10599 01:26:03.718673 <6>[ 2.270795] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10600 01:26:03.726066 <6>[ 2.279640] hub 2-0:1.0: USB hub found
10601 01:26:03.729082 <6>[ 2.283669] hub 2-0:1.0: 1 port detected
10602 01:26:03.736966 <6>[ 2.290310] mtk-msdc 11f70000.mmc: Got CD GPIO
10603 01:26:03.749843 <6>[ 2.300108] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10604 01:26:03.756220 <6>[ 2.308140] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10605 01:26:03.766218 <4>[ 2.316054] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10606 01:26:03.775984 <6>[ 2.325623] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10607 01:26:03.782790 <6>[ 2.333700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10608 01:26:03.789641 <6>[ 2.341718] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10609 01:26:03.799656 <6>[ 2.349635] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10610 01:26:03.806170 <6>[ 2.357452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10611 01:26:03.816084 <6>[ 2.365269] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10612 01:26:03.825880 <6>[ 2.375687] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10613 01:26:03.832599 <6>[ 2.384048] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10614 01:26:03.842296 <6>[ 2.392395] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10615 01:26:03.849039 <6>[ 2.400732] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10616 01:26:03.858582 <6>[ 2.409070] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10617 01:26:03.865234 <6>[ 2.417410] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10618 01:26:03.875124 <6>[ 2.425747] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10619 01:26:03.885254 <6>[ 2.434084] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10620 01:26:03.891950 <6>[ 2.442423] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10621 01:26:03.901991 <6>[ 2.450761] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10622 01:26:03.908122 <6>[ 2.459099] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10623 01:26:03.918153 <6>[ 2.467436] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10624 01:26:03.924810 <6>[ 2.475773] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10625 01:26:03.934994 <6>[ 2.484113] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10626 01:26:03.941848 <6>[ 2.492450] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10627 01:26:03.948207 <6>[ 2.501210] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10628 01:26:03.955249 <6>[ 2.508364] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10629 01:26:03.961972 <6>[ 2.515124] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10630 01:26:03.968292 <6>[ 2.521882] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10631 01:26:03.978675 <6>[ 2.528823] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10632 01:26:03.984807 <6>[ 2.535678] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10633 01:26:03.995007 <6>[ 2.544814] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10634 01:26:04.004784 <6>[ 2.553933] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10635 01:26:04.014556 <6>[ 2.563227] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10636 01:26:04.024990 <6>[ 2.572694] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10637 01:26:04.031600 <6>[ 2.582160] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10638 01:26:04.041240 <6>[ 2.591281] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10639 01:26:04.051160 <6>[ 2.600747] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10640 01:26:04.061452 <6>[ 2.609866] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10641 01:26:04.071411 <6>[ 2.619162] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10642 01:26:04.081014 <6>[ 2.629322] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10643 01:26:04.090939 <6>[ 2.640760] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10644 01:26:04.143995 <6>[ 2.694531] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10645 01:26:04.296884 <6>[ 2.850407] hub 1-1:1.0: USB hub found
10646 01:26:04.299907 <6>[ 2.854694] hub 1-1:1.0: 4 ports detected
10647 01:26:04.424469 <6>[ 2.974797] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10648 01:26:04.449970 <6>[ 3.003632] hub 2-1:1.0: USB hub found
10649 01:26:04.452959 <6>[ 3.008072] hub 2-1:1.0: 3 ports detected
10650 01:26:04.620101 <6>[ 3.170557] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10651 01:26:04.753049 <6>[ 3.307087] hub 1-1.4:1.0: USB hub found
10652 01:26:04.756744 <6>[ 3.311798] hub 1-1.4:1.0: 2 ports detected
10653 01:26:04.831862 <6>[ 3.382646] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10654 01:26:05.055812 <6>[ 3.606537] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10655 01:26:05.247905 <6>[ 3.798576] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10656 01:26:16.369077 <6>[ 14.927540] ALSA device list:
10657 01:26:16.375643 <6>[ 14.930835] No soundcards found.
10658 01:26:16.383703 <6>[ 14.938789] Freeing unused kernel memory: 8384K
10659 01:26:16.386769 <6>[ 14.943797] Run /init as init process
10660 01:26:16.420719 Starting syslogd: OK
10661 01:26:16.424784 Starting klogd: OK
10662 01:26:16.433883 Running sysctl: OK
10663 01:26:16.443744 Populating /dev using udev: <30>[ 14.998918] udevd[188]: starting version 3.2.9
10664 01:26:16.452450 <27>[ 15.007656] udevd[188]: specified user 'tss' unknown
10665 01:26:16.459199 <27>[ 15.013039] udevd[188]: specified group 'tss' unknown
10666 01:26:16.462644 <30>[ 15.019584] udevd[189]: starting eudev-3.2.9
10667 01:26:16.483343 <27>[ 15.038623] udevd[189]: specified user 'tss' unknown
10668 01:26:16.489914 <27>[ 15.043998] udevd[189]: specified group 'tss' unknown
10669 01:26:16.628979 <6>[ 15.181009] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10670 01:26:16.635622 <6>[ 15.189289] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10671 01:26:16.642287 <6>[ 15.197206] remoteproc remoteproc0: scp is available
10672 01:26:16.649075 <6>[ 15.202597] remoteproc remoteproc0: powering up scp
10673 01:26:16.655566 <6>[ 15.208034] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10674 01:26:16.665821 <6>[ 15.215329] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10675 01:26:16.672217 <6>[ 15.217201] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10676 01:26:16.678812 <6>[ 15.225208] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10677 01:26:16.685536 <6>[ 15.235619] usbcore: registered new interface driver r8152
10678 01:26:16.692051 <3>[ 15.236024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 01:26:16.701973 <3>[ 15.236055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 01:26:16.708866 <3>[ 15.236072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 01:26:16.718210 <3>[ 15.246981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 01:26:16.724767 <4>[ 15.263579] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10683 01:26:16.731493 <3>[ 15.269675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 01:26:16.741460 <6>[ 15.271503] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10685 01:26:16.748518 <4>[ 15.278727] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10686 01:26:16.755124 <3>[ 15.285158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 01:26:16.761882 <6>[ 15.291219] mc: Linux media interface: v0.10
10688 01:26:16.768755 <4>[ 15.296487] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10689 01:26:16.775386 <4>[ 15.296487] Fallback method does not support PEC.
10690 01:26:16.782163 <3>[ 15.300837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 01:26:16.791937 <3>[ 15.325375] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 01:26:16.798395 <3>[ 15.334368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 01:26:16.808535 <3>[ 15.334484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 01:26:16.812115 <6>[ 15.334983] videodev: Linux video capture interface: v2.00
10695 01:26:16.818945 <6>[ 15.342871] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10696 01:26:16.825689 <6>[ 15.347733] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10697 01:26:16.832574 <6>[ 15.347741] pci_bus 0000:00: root bus resource [bus 00-ff]
10698 01:26:16.839064 <6>[ 15.347746] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10699 01:26:16.848766 <6>[ 15.347748] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10700 01:26:16.855364 <6>[ 15.347789] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10701 01:26:16.862411 <6>[ 15.347803] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10702 01:26:16.868601 <6>[ 15.347873] pci 0000:00:00.0: supports D1 D2
10703 01:26:16.875666 <6>[ 15.347875] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10704 01:26:16.881883 <6>[ 15.349328] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10705 01:26:16.888523 <6>[ 15.349403] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10706 01:26:16.895174 <6>[ 15.349427] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10707 01:26:16.905225 <6>[ 15.349444] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10708 01:26:16.911892 <6>[ 15.349459] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10709 01:26:16.915476 <6>[ 15.349561] pci 0000:01:00.0: supports D1 D2
10710 01:26:16.921959 <6>[ 15.349563] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 01:26:16.931964 <3>[ 15.351312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 01:26:16.938391 <6>[ 15.358351] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10713 01:26:16.945088 <6>[ 15.358393] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10714 01:26:16.955197 <6>[ 15.358396] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10715 01:26:16.961613 <6>[ 15.358404] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10716 01:26:16.968702 <6>[ 15.358417] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10717 01:26:16.978851 <6>[ 15.358431] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10718 01:26:16.981754 <6>[ 15.358449] pci 0000:00:00.0: PCI bridge to [bus 01]
10719 01:26:16.991476 <6>[ 15.358458] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10720 01:26:16.998234 <6>[ 15.359089] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10721 01:26:17.004900 <6>[ 15.360378] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10722 01:26:17.011509 <6>[ 15.364814] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10723 01:26:17.018140 <3>[ 15.367448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 01:26:17.027929 <3>[ 15.367456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 01:26:17.034567 <3>[ 15.367515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 01:26:17.044938 <6>[ 15.373252] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10727 01:26:17.051483 <3>[ 15.380351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 01:26:17.061265 <3>[ 15.382060] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 01:26:17.071127 <4>[ 15.385247] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10730 01:26:17.078074 <4>[ 15.385258] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10731 01:26:17.084437 <6>[ 15.387215] remoteproc remoteproc0: remote processor scp is now up
10732 01:26:17.090940 <3>[ 15.392944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 01:26:17.097276 <6>[ 15.400240] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10734 01:26:17.107492 <6>[ 15.401656] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10735 01:26:17.114037 <3>[ 15.409968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 01:26:17.123721 <3>[ 15.409971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 01:26:17.130412 <3>[ 15.410007] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 01:26:17.140313 <6>[ 15.411604] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10739 01:26:17.147026 <6>[ 15.412901] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10740 01:26:17.157182 <6>[ 15.427121] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10741 01:26:17.163765 <6>[ 15.446607] r8152 2-1.3:1.0 eth0: v1.12.13
10742 01:26:17.170726 <6>[ 15.450161] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10743 01:26:17.181944 <6>[ 15.737192] usbcore: registered new interface driver cdc_ether
10744 01:26:17.189725 <6>[ 15.744836] usbcore: registered new interface driver r8153_ecm
10745 01:26:17.204979 <5>[ 15.757018] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10746 01:26:17.211932 <6>[ 15.763209] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10747 01:26:17.215131 <6>[ 15.773010] Bluetooth: Core ver 2.22
10748 01:26:17.228268 <6>[ 15.773973] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10749 01:26:17.234769 <6>[ 15.776982] NET: Registered PF_BLUETOOTH protocol family
10750 01:26:17.241392 <6>[ 15.777925] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10751 01:26:17.248174 <5>[ 15.786404] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10752 01:26:17.258488 <4>[ 15.786486] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10753 01:26:17.261480 <6>[ 15.786492] cfg80211: failed to load regulatory.db
10754 01:26:17.268118 <6>[ 15.789506] usbcore: registered new interface driver uvcvideo
10755 01:26:17.274607 <6>[ 15.794862] Bluetooth: HCI device and connection manager initialized
10756 01:26:17.277951 <6>[ 15.794881] Bluetooth: HCI socket layer initialized
10757 01:26:17.284836 <6>[ 15.839797] Bluetooth: L2CAP socket layer initialized
10758 01:26:17.291258 <6>[ 15.845114] Bluetooth: SCO socket layer initialized
10759 01:26:17.302392 <6>[ 15.857870] usbcore: registered new interface driver btusb
10760 01:26:17.312477 <4>[ 15.859328] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10761 01:26:17.318980 <3>[ 15.874291] Bluetooth: hci0: Failed to load firmware file (-2)
10762 01:26:17.326088 <6>[ 15.879474] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10763 01:26:17.332854 <3>[ 15.880404] Bluetooth: hci0: Failed to set up firmware (-2)
10764 01:26:17.338833 <6>[ 15.887857] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 01:26:17.349106 <4>[ 15.893611] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10766 01:26:17.363285 <6>[ 15.918565] mt7921e 0000:01:00.0: ASIC revision: 79610010
10767 01:26:17.469490 <4>[ 16.018375] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 01:26:17.478768 done
10769 01:26:17.493170 Saving random seed: OK
10770 01:26:17.510716 Starting network: OK
10771 01:26:17.539732 Starting dropbear sshd: <6>[ 16.095064] NET: Registered PF_INET6 protocol family
10772 01:26:17.546296 <6>[ 16.101683] Segment Routing with IPv6
10773 01:26:17.549808 <6>[ 16.105635] In-situ OAM (IOAM) with IPv6
10774 01:26:17.552851 OK
10775 01:26:17.562349 /bin/sh: can't access tty; job control turned off
10776 01:26:17.562802 Matched prompt #10: / #
10778 01:26:17.563145 Setting prompt string to ['/ #']
10779 01:26:17.563296 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10781 01:26:17.563640 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10782 01:26:17.563774 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
10783 01:26:17.563880 Setting prompt string to ['/ #']
10784 01:26:17.563977 Forcing a shell prompt, looking for ['/ #']
10786 01:26:17.614243 / #
10787 01:26:17.614443 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10788 01:26:17.614567 Waiting using forced prompt support (timeout 00:02:30)
10789 01:26:17.614726 <4>[ 16.136709] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 01:26:17.619636
10791 01:26:17.619953 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10792 01:26:17.620095 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
10793 01:26:17.620243 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10794 01:26:17.620381 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
10795 01:26:17.620520 end: 2 depthcharge-action (duration 00:01:22) [common]
10796 01:26:17.620664 start: 3 lava-test-retry (timeout 00:01:00) [common]
10797 01:26:17.620799 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10798 01:26:17.620916 Using namespace: common
10800 01:26:17.721298 / # #
10801 01:26:17.721504 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10802 01:26:17.721672 #<4>[ 16.257093] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10803 01:26:17.726399
10804 01:26:17.726699 Using /lava-11368543
10806 01:26:17.827085 / # export SHELL=/bin/sh
10807 01:26:17.828124 export SHELL=/bin/sh<4>[ 16.377013] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 01:26:17.875705
10810 01:26:17.976344 / # . /lava-11368543/environment
10811 01:26:17.976551 . /lava-11368543/environment<4>[ 16.497446] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 01:26:17.981737
10814 01:26:18.082291 / # /lava-11368543/bin/lava-test-runner /lava-11368543/0
10815 01:26:18.082489 Test shell timeout: 10s (minimum of the action and connection timeout)
10816 01:26:18.083054 /lava-11368543/bin/lava-test-runner /lava-11368543/0<4>[ 16.616747] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 01:26:18.087495
10818 01:26:18.127712 + export 'TESTRUN_ID=0_dmesg'
10819 01:26:18.127889 +<8>[ 16.668268] <LAVA_SIGNAL_STARTRUN 0_dmesg 11368543_1.5.2.3.1>
10820 01:26:18.127995 cd /lava-11368543/0/tests/0_dmesg
10821 01:26:18.128099 + cat uuid
10822 01:26:18.128203 + UUID=11368543_1.5.2.3.1
10823 01:26:18.128307 + set +x
10824 01:26:18.128412 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10825 01:26:18.128702 Received signal: <STARTRUN> 0_dmesg 11368543_1.5.2.3.1
10826 01:26:18.128810 Starting test lava.0_dmesg (11368543_1.5.2.3.1)
10827 01:26:18.128945 Skipping test definition patterns.
10828 01:26:18.134603 <8>[ 16.687189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10829 01:26:18.134894 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10831 01:26:18.157257 <8>[ 16.709017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10832 01:26:18.157590 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10834 01:26:18.182772 <8>[ 16.735047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10835 01:26:18.183099 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10837 01:26:18.192882 <4>[ 16.737665] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10838 01:26:18.196689 + set +x
10839 01:26:18.199766 Received signal: <ENDRUN> 0_dmesg 11368543_1.5.2.3.1
10840 01:26:18.199897 Ending use of test pattern.
10841 01:26:18.200007 Ending test lava.0_dmesg (11368543_1.5.2.3.1), duration 0.07
10843 01:26:18.203178 <8>[ 16.755184] <LAVA_SIGNAL_ENDRUN 0_dmesg 11368543_1.5.2.3.1>
10844 01:26:18.206151 <LAVA_TEST_RUNNER EXIT>
10845 01:26:18.206438 ok: lava_test_shell seems to have completed
10846 01:26:18.206585 alert: pass
crit: pass
emerg: pass
10847 01:26:18.206678 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10848 01:26:18.206784 end: 3 lava-test-retry (duration 00:00:01) [common]
10849 01:26:18.206872 start: 4 lava-test-retry (timeout 00:01:00) [common]
10850 01:26:18.206968 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10851 01:26:18.207043 Using namespace: common
10853 01:26:18.307377 / # #
10854 01:26:18.307586 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10855 01:26:18.307729 Using /lava-11368543
10857 01:26:18.408033 export SHELL=/bin/sh
10858 01:26:18.408278 #<4>[ 16.860838] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10859 01:26:18.408360
10861 01:26:18.508861 / # export SHELL=/bin/sh. /lava-11368543/environment
10862 01:26:18.509097
10863 01:26:18.509199 / # <4>[ 16.981475] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 01:26:18.609733 . /lava-11368543/environment/lava-11368543/bin/lava-test-runner /lava-11368543/1
10866 01:26:18.609890 Test shell timeout: 10s (minimum of the action and connection timeout)
10867 01:26:18.610012
10868 01:26:18.610082 / # <4>[ 17.101095] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 01:26:18.655659 /lava-11368543/bin/lava-test-runner /lava-11368543/1
10870 01:26:18.655798 + export 'TESTRU<8>[ 17.193231] <LAVA_SIGNAL_STARTRUN 1_bootrr 11368543_1.5.2.3.5>
10871 01:26:18.655873 N_ID=1_bootrr'
10872 01:26:18.655951 + cd /lava-11368543/1/tests/1_bootrr
10873 01:26:18.656017 + cat uuid
10874 01:26:18.656258 Received signal: <STARTRUN> 1_bootrr 11368543_1.5.2.3.5
10875 01:26:18.656330 Starting test lava.1_bootrr (11368543_1.5.2.3.5)
10876 01:26:18.656423 Skipping test definition patterns.
10877 01:26:18.656531 + UUID=11368543_1.5.2.3.5
10878 01:26:18.656596 + set +x
10879 01:26:18.656669 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11368543/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10880 01:26:18.666556 + cd /opt/bootrr/libexec/bootrr<3>[ 17.219461] mt7921e 0000:01:00.0: hardware init failed
10881 01:26:18.673062 <8>[ 17.221578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10882 01:26:18.673146
10883 01:26:18.673385 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10885 01:26:18.676795 + sh helpers/bootrr-auto
10886 01:26:18.679776 /lava-11368543/1/../bin/lava-test-case
10887 01:26:18.682778 /lava-11368543/1/../bin/lava-test-case
10888 01:26:18.692751 <8>[ 17.244261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10889 01:26:18.693047 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10891 01:26:18.697811 /usr/bin/tpm2_getcap
10892 01:26:18.731132 /lava-11368543/1/../bin/lava-test-case
10893 01:26:18.738111 <8>[ 17.291506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10894 01:26:18.738409 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10896 01:26:18.762626 /lava-11368543/1/../bin/lava-tes<8>[ 17.313782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10897 01:26:18.762750 t-case
10898 01:26:18.763027 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10900 01:26:18.780646 /lava-11368543/1/../bin/lava-tes<8>[ 17.331818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10901 01:26:18.780766 t-case
10902 01:26:18.781037 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10904 01:26:18.800038 /lava-11368543/1/../bin/lava-tes<8>[ 17.351265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10905 01:26:18.800161 t-case
10906 01:26:18.800435 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10908 01:26:18.809933 /lava-11368543/1/../bin/lava-test-case
10909 01:26:18.816827 <8>[ 17.370547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10910 01:26:18.817117 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10912 01:26:18.829596 /lava-11368543/1/../bin/lava-test-case
10913 01:26:18.836676 <8>[ 17.388876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10914 01:26:18.836969 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10916 01:26:18.846248 /lava-11368543/1/../bin/lava-test-case
10917 01:26:18.853052 <8>[ 17.405511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10918 01:26:18.853342 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10920 01:26:18.873431 /lava-11368543/1/../bin/lava-tes<8>[ 17.425033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10921 01:26:18.873552 t-case
10922 01:26:18.873825 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10924 01:26:18.881077 /lava-11368543/1/../bin/lava-test-case
10925 01:26:18.887660 <8>[ 17.440497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10926 01:26:18.887949 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10928 01:26:18.900431 /lava-11368543/1/../bin/lava-test-case
10929 01:26:18.907127 <8>[ 17.459424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10930 01:26:18.907416 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10932 01:26:18.919257 /lava-11368543/1/../bin/lava-test-case
10933 01:26:18.925306 <8>[ 17.477944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10934 01:26:18.925599 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10936 01:26:18.945290 /lava-11368543/1/../bin/lava-tes<8>[ 17.496764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10937 01:26:18.945448 t-case
10938 01:26:18.945732 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10940 01:26:18.963149 /lava-11368543/1/../bin/lava-tes<8>[ 17.514449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10941 01:26:18.963281 t-case
10942 01:26:18.963559 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10944 01:26:18.974447 /lava-11368543/1/../bin/lava-test-case
10945 01:26:18.981089 <8>[ 17.534137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10946 01:26:18.981384 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10948 01:26:18.999626 /lava-11368543/1/../bin/lava-tes<8>[ 17.551376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10949 01:26:18.999739 t-case
10950 01:26:19.000013 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10952 01:26:19.010007 /lava-11368543/1/../bin/lava-test-case
10953 01:26:19.016774 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10955 01:26:19.020289 <8>[ 17.570616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10956 01:26:19.029988 /lava-11368543/1/../bin/lava-test-case
10957 01:26:19.036485 <8>[ 17.588767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10958 01:26:19.036780 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10960 01:26:19.045534 /lava-11368543/1/../bin/lava-test-case
10961 01:26:19.052188 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10963 01:26:19.055942 <8>[ 17.606389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10964 01:26:19.065385 /lava-11368543/1/../bin/lava-test-case
10965 01:26:19.072030 <8>[ 17.624254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10966 01:26:19.072322 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10968 01:26:19.080580 /lava-11368543/1/../bin/lava-test-case
10969 01:26:19.090835 <8>[ 17.642923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10970 01:26:19.091133 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10972 01:26:19.108941 /lava-11368543/1/../bin/lava-tes<8>[ 17.660571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10973 01:26:19.109058 t-case
10974 01:26:19.109334 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10976 01:26:19.125156 /lava-11368543/1/../bin/lava-tes<8>[ 17.676493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10977 01:26:19.125275 t-case
10978 01:26:19.125557 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10980 01:26:19.136485 /lava-11368543/1/../bin/lava-test-case
10981 01:26:19.143074 <8>[ 17.695728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10982 01:26:19.143362 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10984 01:26:19.153734 /lava-11368543/1/../bin/lava-test-case
10985 01:26:19.160405 <8>[ 17.712658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10986 01:26:19.160694 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10988 01:26:19.176633 /lava-11368543/1/../bin/lava-tes<8>[ 17.727924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10989 01:26:19.176759 t-case
10990 01:26:19.177033 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10992 01:26:19.187229 /lava-11368543/1/../bin/lava-test-case
10993 01:26:19.193898 <8>[ 17.746349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10994 01:26:19.194194 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10996 01:26:19.203654 /lava-11368543/1/../bin/lava-test-case
10997 01:26:19.210283 <8>[ 17.762410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10998 01:26:19.210580 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11000 01:26:19.222400 /lava-11368543/1/../bin/lava-test-case
11001 01:26:19.228989 <8>[ 17.780559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11002 01:26:19.229278 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11004 01:26:19.246701 /lava-11368543/1/../bin/lava-tes<8>[ 17.797841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11005 01:26:19.246836 t-case
11006 01:26:19.247115 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11008 01:26:19.256398 /lava-11368543/1/../bin/lava-test-case
11009 01:26:19.263033 <8>[ 17.816124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11010 01:26:19.263322 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11012 01:26:19.282771 /lava-11368543/1/../bin/lava-tes<8>[ 17.834230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11013 01:26:19.282905 t-case
11014 01:26:19.283181 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11016 01:26:19.290786 /lava-11368543/1/../bin/lava-test-case
11017 01:26:19.296988 <8>[ 17.850269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11018 01:26:19.297282 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11020 01:26:19.310088 /lava-11368543/1/../bin/lava-test-case
11021 01:26:19.316399 <8>[ 17.868823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11022 01:26:19.316695 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11024 01:26:19.327240 /lava-11368543/1/../bin/lava-test-case
11025 01:26:19.333763 <8>[ 17.887408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11026 01:26:19.334057 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11028 01:26:19.341532 /lava-11368543/1/../bin/lava-test-case
11029 01:26:19.352177 <8>[ 17.904381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11030 01:26:19.352472 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11032 01:26:19.363263 /lava-11368543/1/../bin/lava-test-case
11033 01:26:19.370030 <8>[ 17.922496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11034 01:26:19.370325 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11036 01:26:19.378224 /lava-11368543/1/../bin/lava-test-case
11037 01:26:19.385021 <8>[ 17.938418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11038 01:26:19.385313 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11040 01:26:19.398080 /lava-11368543/1/../bin/lava-test-case
11041 01:26:19.404346 <8>[ 17.956409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11042 01:26:19.404639 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11044 01:26:19.420342 /lava-11368543/1/../bin/lava-tes<8>[ 17.971975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11045 01:26:19.420459 t-case
11046 01:26:19.420734 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11048 01:26:19.433362 /lava-11368543/1/../bin/lava-test-case
11049 01:26:19.440089 <8>[ 17.993951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11050 01:26:19.440378 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11052 01:26:19.450244 /lava-11368543/1/../bin/lava-test-case
11053 01:26:19.456757 <8>[ 18.008749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11054 01:26:19.457042 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11056 01:26:19.471490 /lava-11368543/1/../bin/lava-test-case
11057 01:26:19.478082 <8>[ 18.030844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11058 01:26:19.478380 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11060 01:26:19.487628 /lava-11368543/1/../bin/lava-test-case
11061 01:26:19.494203 <8>[ 18.046723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11062 01:26:19.494493 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11064 01:26:19.504883 /lava-11368543/1/../bin/lava-test-case
11065 01:26:19.511550 <8>[ 18.064669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11066 01:26:19.511843 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11068 01:26:19.522133 /lava-11368543/1/../bin/lava-test-case
11069 01:26:19.528532 <8>[ 18.081204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11070 01:26:19.528819 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11072 01:26:19.538784 /lava-11368543/1/../bin/lava-test-case
11073 01:26:19.549106 <8>[ 18.101104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11074 01:26:19.549401 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11076 01:26:19.558762 /lava-11368543/1/../bin/lava-test-case
11077 01:26:19.568078 <8>[ 18.119088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11078 01:26:19.568380 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11080 01:26:19.578421 /lava-11368543/1/../bin/lava-test-case
11081 01:26:19.585171 <8>[ 18.137608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11082 01:26:19.585460 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11084 01:26:19.596334 /lava-11368543/1/../bin/lava-test-case
11085 01:26:19.603201 <8>[ 18.155222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11086 01:26:19.603487 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11088 01:26:19.611455 /lava-11368543/1/../bin/lava-test-case
11089 01:26:19.618324 <8>[ 18.171440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11090 01:26:19.618622 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11092 01:26:19.630326 /lava-11368543/1/../bin/lava-test-case
11093 01:26:19.636752 <8>[ 18.189544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11094 01:26:19.637046 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11096 01:26:19.646139 /lava-11368543/1/../bin/lava-test-case
11097 01:26:19.652432 <8>[ 18.204960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11098 01:26:19.652730 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11100 01:26:19.662625 /lava-11368543/1/../bin/lava-test-case
11101 01:26:19.669798 <8>[ 18.221700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11102 01:26:19.670090 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11104 01:26:19.680157 /lava-11368543/1/../bin/lava-test-case
11105 01:26:19.686739 <8>[ 18.239310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11106 01:26:19.687039 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11108 01:26:19.696537 /lava-11368543/1/../bin/lava-test-case
11109 01:26:19.702908 <8>[ 18.255500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11110 01:26:19.703171 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11112 01:26:19.713638 /lava-11368543/1/../bin/lava-test-case
11113 01:26:19.720322 <8>[ 18.272925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11114 01:26:19.720582 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11116 01:26:19.731052 /lava-11368543/1/../bin/lava-test-case
11117 01:26:19.738022 <8>[ 18.290673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11118 01:26:19.738283 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11120 01:26:19.746408 /lava-11368543/1/../bin/lava-test-case
11121 01:26:19.752580 <8>[ 18.305968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11122 01:26:19.752831 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11124 01:26:19.764695 /lava-11368543/1/../bin/lava-test-case
11125 01:26:19.771448 <8>[ 18.323751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11126 01:26:19.771741 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11128 01:26:19.781933 /lava-11368543/1/../bin/lava-test-case
11129 01:26:19.788169 <8>[ 18.340079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11130 01:26:19.788457 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11132 01:26:19.805294 /lava-11368543/1/../bin/lava-tes<8>[ 18.356884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11133 01:26:19.805418 t-case
11134 01:26:19.805692 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11136 01:26:19.822133 /lava-11368543/1/../bin/lava-tes<8>[ 18.373940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11137 01:26:19.822248 t-case
11138 01:26:19.822522 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11140 01:26:19.832786 /lava-11368543/1/../bin/lava-test-case
11141 01:26:19.842279 <8>[ 18.393472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11142 01:26:19.842585 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11144 01:26:19.852033 /lava-11368543/1/../bin/lava-test-case
11145 01:26:19.858091 <8>[ 18.410762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11146 01:26:19.858349 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11148 01:26:19.867589 /lava-11368543/1/../bin/lava-test-case
11149 01:26:19.874549 <8>[ 18.426540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11150 01:26:19.874832 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11152 01:26:19.884802 /lava-11368543/1/../bin/lava-test-case
11153 01:26:19.891337 <8>[ 18.444222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11154 01:26:19.891618 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11156 01:26:19.902967 /lava-11368543/1/../bin/lava-test-case
11157 01:26:19.909599 <8>[ 18.461744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11158 01:26:19.909899 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11160 01:26:19.919252 /lava-11368543/1/../bin/lava-test-case
11161 01:26:19.926350 <8>[ 18.478811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11162 01:26:19.926640 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11164 01:26:19.937220 /lava-11368543/1/../bin/lava-test-case
11165 01:26:19.943890 <8>[ 18.496288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11166 01:26:19.944187 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11168 01:26:19.954064 /lava-11368543/1/../bin/lava-test-case
11169 01:26:19.960538 <8>[ 18.513105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11170 01:26:19.960841 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11172 01:26:19.972050 /lava-11368543/1/../bin/lava-test-case
11173 01:26:19.978591 <8>[ 18.530681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11174 01:26:19.978850 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11176 01:26:19.988208 /lava-11368543/1/../bin/lava-test-case
11177 01:26:19.994676 <8>[ 18.547463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11178 01:26:19.994954 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11180 01:26:20.013169 /lava-11368543/1/../bin/lava-tes<8>[ 18.564885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11181 01:26:20.013295 t-case
11182 01:26:20.013571 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11184 01:26:20.022196 /lava-11368543/1/../bin/lava-test-case
11185 01:26:20.029075 <8>[ 18.582114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11186 01:26:20.029369 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11188 01:26:20.040640 /lava-11368543/1/../bin/lava-test-case
11189 01:26:20.047269 <8>[ 18.599800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11190 01:26:20.047577 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11192 01:26:20.062158 /lava-11368543/1/../bin/lava-test-case
11193 01:26:20.068993 <8>[ 18.621233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11194 01:26:20.069287 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11196 01:26:20.082547 /lava-11368543/1/../bin/lava-test-case
11197 01:26:20.088681 <8>[ 18.640820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11198 01:26:20.088975 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11200 01:26:20.101375 /lava-11368543/1/../bin/lava-test-case
11201 01:26:20.107561 <8>[ 18.660336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11202 01:26:20.107855 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11204 01:26:20.118472 /lava-11368543/1/../bin/lava-test-case
11205 01:26:20.124972 <8>[ 18.676635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11206 01:26:20.125268 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11208 01:26:20.138348 /lava-11368543/1/../bin/lava-test-case
11209 01:26:20.144825 <8>[ 18.696935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11210 01:26:20.145128 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11212 01:26:20.152906 /lava-11368543/1/../bin/lava-test-case
11213 01:26:20.159556 <8>[ 18.712086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11214 01:26:20.159848 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11216 01:26:20.172922 /lava-11368543/1/../bin/lava-test-case
11217 01:26:20.179486 <8>[ 18.731560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11218 01:26:20.179785 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11220 01:26:20.194115 /lava-11368543/1/../bin/lava-tes<8>[ 18.745473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11221 01:26:20.194238 t-case
11222 01:26:20.194512 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11224 01:26:20.206162 /lava-11368543/1/../bin/lava-test-case
11225 01:26:20.212654 <8>[ 18.766777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11226 01:26:20.212950 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11228 01:26:20.222481 /lava-11368543/1/../bin/lava-test-case
11229 01:26:20.228884 <8>[ 18.781037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11230 01:26:20.229184 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11232 01:26:20.240857 /lava-11368543/1/../bin/lava-test-case
11233 01:26:20.247744 <8>[ 18.799771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11234 01:26:20.248037 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11236 01:26:20.258171 /lava-11368543/1/../bin/lava-test-case
11237 01:26:20.264543 <8>[ 18.817847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11238 01:26:20.264842 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11240 01:26:20.284286 /lava-11368543/1/../bin/lava-tes<8>[ 18.835840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11241 01:26:20.284403 t-case
11242 01:26:20.284678 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11244 01:26:20.292014 /lava-11368543/1/../bin/lava-test-case
11245 01:26:20.298434 <8>[ 18.851006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11246 01:26:20.298725 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11248 01:26:20.312087 /lava-11368543/1/../bin/lava-test-case
11249 01:26:20.318705 <8>[ 18.870972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11250 01:26:20.319006 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11252 01:26:20.328688 /lava-11368543/1/../bin/lava-test-case
11253 01:26:20.334954 <8>[ 18.888554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11254 01:26:20.335247 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11256 01:26:20.348369 /lava-11368543/1/../bin/lava-test-case
11257 01:26:20.355245 <8>[ 18.908056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11258 01:26:20.355536 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11260 01:26:20.369470 /lava-11368543/1/../bin/lava-test-case
11261 01:26:20.375953 <8>[ 18.929533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11262 01:26:20.376253 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11264 01:26:20.386376 /lava-11368543/1/../bin/lava-test-case
11265 01:26:20.393388 <8>[ 18.945660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11266 01:26:20.393683 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11268 01:26:20.404940 /lava-11368543/1/../bin/lava-test-case
11269 01:26:20.411401 <8>[ 18.964073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11270 01:26:20.411698 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11272 01:26:20.420584 /lava-11368543/1/../bin/lava-test-case
11273 01:26:20.427460 <8>[ 18.979551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11274 01:26:20.427747 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11276 01:26:20.441154 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11278 01:26:20.444670 /lava-11368543/1/../bin/lava-tes<8>[ 18.996185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11279 01:26:20.444778 t-case
11280 01:26:20.453105 /lava-11368543/1/../bin/lava-test-case
11281 01:26:20.459543 <8>[ 19.012564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11282 01:26:20.459837 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11284 01:26:21.473154 /lava-11368543/1/../bin/lava-test-case
11285 01:26:21.479517 <8>[ 20.032553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11286 01:26:21.479880 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11288 01:26:21.489237 /lava-11368543/1/../bin/lava-test-case
11289 01:26:21.495775 <8>[ 20.048555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11290 01:26:21.496031 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11292 01:26:22.507836 /lava-11368543/1/../bin/lava-test-case
11293 01:26:22.514422 <8>[ 21.067295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11294 01:26:22.514689 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11296 01:26:22.524542 /lava-11368543/1/../bin/lava-test-case
11297 01:26:22.531000 <8>[ 21.084490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11298 01:26:22.531277 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11300 01:26:23.545291 /lava-11368543/1/../bin/lava-test-case
11301 01:26:23.551433 <8>[ 22.104603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11302 01:26:23.551742 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11304 01:26:23.569417 /lava-11368543/1/../bin/lava-tes<8>[ 22.121194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11305 01:26:23.569519 t-case
11306 01:26:23.569762 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11308 01:26:24.586945 /lava-11368543/1/../bin/lava-test-case
11309 01:26:24.593453 <8>[ 23.148355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11310 01:26:24.593714 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11312 01:26:24.603781 /lava-11368543/1/../bin/lava-test-case
11313 01:26:24.610947 <8>[ 23.163316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11314 01:26:24.611261 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11316 01:26:25.624723 /lava-11368543/1/../bin/lava-test-case
11317 01:26:25.631282 <8>[ 24.184406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11318 01:26:25.631617 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11320 01:26:25.640554 /lava-11368543/1/../bin/lava-test-case
11321 01:26:25.647202 <8>[ 24.200924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11322 01:26:25.647533 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11324 01:26:26.661449 /lava-11368543/1/../bin/lava-test-case
11325 01:26:26.668033 <8>[ 25.221066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11326 01:26:26.668368 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11328 01:26:26.684808 /lava-11368543/1/../bin/lava-tes<8>[ 25.236855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11329 01:26:26.684985 t-case
11330 01:26:26.685275 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11332 01:26:27.699421 /lava-11368543/1/../bin/lava-test-case
11333 01:26:27.705975 <8>[ 26.259167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11334 01:26:27.706279 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11336 01:26:27.716767 /lava-11368543/1/../bin/lava-test-case
11337 01:26:27.726657 <8>[ 26.278894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11338 01:26:27.726975 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11340 01:26:27.734150 /lava-11368543/1/../bin/lava-test-case
11341 01:26:27.740767 <8>[ 26.294838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11342 01:26:27.741074 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11344 01:26:28.756188 /lava-11368543/1/../bin/lava-test-case
11345 01:26:28.763132 <8>[ 27.316447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11346 01:26:28.763425 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11348 01:26:28.772362 /lava-11368543/1/../bin/lava-test-case
11349 01:26:28.778908 <8>[ 27.333154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11350 01:26:28.779199 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11352 01:26:28.791984 /lava-11368543/1/../bin/lava-test-case
11353 01:26:28.798005 <8>[ 27.351477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11354 01:26:28.798298 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11356 01:26:28.813074 /lava-11368543/1/../bin/lava-tes<8>[ 27.365775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11357 01:26:28.813213 t-case
11358 01:26:28.813460 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11360 01:26:28.833207 /lava-11368543/1/../bin/lava-tes<8>[ 27.385859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11361 01:26:28.833353 t-case
11362 01:26:28.833599 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11364 01:26:28.842676 /lava-11368543/1/../bin/lava-test-case
11365 01:26:28.853004 <8>[ 27.405019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11366 01:26:28.853316 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11368 01:26:28.863114 /lava-11368543/1/../bin/lava-test-case
11369 01:26:28.870040 <8>[ 27.422921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11370 01:26:28.870343 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11372 01:26:28.886156 /lava-11368543/1/../bin/lava-tes<8>[ 27.438689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11373 01:26:28.886293 t-case
11374 01:26:28.886535 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11376 01:26:28.900079 /lava-11368543/1/../bin/lava-test-case
11377 01:26:28.906157 <8>[ 27.459941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11378 01:26:28.906490 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11380 01:26:28.918443 /lava-11368543/1/../bin/lava-test-case
11381 01:26:28.924995 <8>[ 27.478330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11382 01:26:28.925291 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11384 01:26:28.933611 /lava-11368543/1/../bin/lava-test-case
11385 01:26:28.940424 <8>[ 27.494567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11386 01:26:28.940714 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11388 01:26:28.953447 /lava-11368543/1/../bin/lava-test-case
11389 01:26:28.959959 <8>[ 27.513450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11390 01:26:28.960286 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11392 01:26:28.969453 /lava-11368543/1/../bin/lava-test-case
11393 01:26:28.979066 <8>[ 27.530682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11394 01:26:28.979405 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11396 01:26:28.990057 /lava-11368543/1/../bin/lava-test-case
11397 01:26:28.996644 <8>[ 27.549986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11398 01:26:28.996942 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11400 01:26:29.011852 /lava-11368543/1/../bin/lava-tes<8>[ 27.564624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11401 01:26:29.011997 t-case
11402 01:26:29.012242 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11404 01:26:29.025901 /lava-11368543/1/../bin/lava-test-case
11405 01:26:29.032010 <8>[ 27.585015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11406 01:26:29.032305 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11408 01:26:29.040682 /lava-11368543/1/../bin/lava-test-case
11409 01:26:29.050944 <8>[ 27.602439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11410 01:26:29.051255 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11412 01:26:29.061442 /lava-11368543/1/../bin/lava-test-case
11413 01:26:29.068023 <8>[ 27.621516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11414 01:26:29.068318 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11416 01:26:29.077027 /lava-11368543/1/../bin/lava-test-case
11417 01:26:29.083515 <8>[ 27.637249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11418 01:26:29.083827 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11420 01:26:29.101965 /lava-11368543/1/../bin/lava-tes<8>[ 27.654877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11421 01:26:29.102110 t-case
11422 01:26:29.102361 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11424 01:26:29.109439 /lava-11368543/1/../bin/lava-test-case
11425 01:26:29.115817 <8>[ 27.670104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11426 01:26:29.116116 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11428 01:26:30.130123 /lava-11368543/1/../bin/lava-test-case
11429 01:26:30.136823 <8>[ 28.690639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11430 01:26:30.137123 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11432 01:26:31.152595 /lava-11368543/1/../bin/lava-test-case
11433 01:26:31.158922 <8>[ 29.713357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11434 01:26:31.159225 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11436 01:26:31.176660 /lava-11368543/1/../bin/lava-tes<8>[ 29.729884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11437 01:26:31.176793 t-case
11438 01:26:31.177037 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11440 01:26:31.187585 /lava-11368543/1/../bin/lava-test-case
11441 01:26:31.194203 <8>[ 29.747916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11442 01:26:31.194535 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11444 01:26:31.203716 /lava-11368543/1/../bin/lava-test-case
11445 01:26:31.209794 <8>[ 29.763402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11446 01:26:31.210075 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11448 01:26:31.229211 /lava-11368543/1/../bin/lava-tes<8>[ 29.781949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11449 01:26:31.229348 t-case
11450 01:26:31.229611 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11452 01:26:31.244495 /lava-11368543/1/../bin/lava-tes<8>[ 29.797584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11453 01:26:31.244640 t-case
11454 01:26:31.244887 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11456 01:26:31.255324 /lava-11368543/1/../bin/lava-test-case
11457 01:26:31.261978 <8>[ 29.815250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11458 01:26:31.262280 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11460 01:26:31.269426 /lava-11368543/1/../bin/lava-test-case
11461 01:26:31.275929 <8>[ 29.830062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11462 01:26:31.276227 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11464 01:26:31.288197 /lava-11368543/1/../bin/lava-test-case
11465 01:26:31.294799 <8>[ 29.848154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11466 01:26:31.295100 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11468 01:26:31.302700 /lava-11368543/1/../bin/lava-test-case
11469 01:26:31.309292 <8>[ 29.863386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11470 01:26:31.309589 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11472 01:26:31.319738 /lava-11368543/1/../bin/lava-test-case
11473 01:26:31.326314 <8>[ 29.881664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11474 01:26:31.326606 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11476 01:26:31.344102 /lava-11368543/1/../bin/lava-tes<8>[ 29.897082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11477 01:26:31.344242 t-case
11478 01:26:31.344487 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11480 01:26:31.359718 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11482 01:26:31.362273 /lava-11368543/1/../bin/lava-tes<8>[ 29.915409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11483 01:26:31.362366 t-case
11484 01:26:31.369735 /lava-11368543/1/../bin/lava-test-case
11485 01:26:31.376567 <8>[ 29.931108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11486 01:26:31.376864 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11488 01:26:31.389497 /lava-11368543/1/../bin/lava-test-case
11489 01:26:31.396231 <8>[ 29.949757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11490 01:26:31.396528 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11492 01:26:31.404261 /lava-11368543/1/../bin/lava-test-case
11493 01:26:31.410382 <8>[ 29.963659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11494 01:26:31.410674 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11496 01:26:31.422259 /lava-11368543/1/../bin/lava-test-case
11497 01:26:31.428922 <8>[ 29.982102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11498 01:26:31.429221 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11500 01:26:31.436800 /lava-11368543/1/../bin/lava-test-case
11501 01:26:31.442906 <8>[ 29.996153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11502 01:26:31.443225 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11504 01:26:31.456573 /lava-11368543/1/../bin/lava-test-case
11505 01:26:31.463388 <8>[ 30.017912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11506 01:26:31.463723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11508 01:26:31.472473 /lava-11368543/1/../bin/lava-test-case
11509 01:26:31.478780 <8>[ 30.033360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11510 01:26:31.479079 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11512 01:26:31.492000 /lava-11368543/1/../bin/lava-test-case
11513 01:26:31.498175 <8>[ 30.052128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11514 01:26:31.498483 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11516 01:26:32.510478 /lava-11368543/1/../bin/lava-test-case
11517 01:26:32.516971 <8>[ 31.072132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11518 01:26:32.517338 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11520 01:26:33.530691 /lava-11368543/1/../bin/lava-test-case
11521 01:26:33.537161 <8>[ 32.091265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11522 01:26:33.537453 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11523 01:26:33.537555 Bad test result: blocked
11524 01:26:33.546047 /lava-11368543/1/../bin/lava-test-case
11525 01:26:33.556139 <8>[ 32.110138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11526 01:26:33.556438 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11528 01:26:34.569303 /lava-11368543/1/../bin/lava-test-case
11529 01:26:34.576310 <8>[ 33.129832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11530 01:26:34.576592 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11532 01:26:34.583946 /lava-11368543/1/../bin/lava-test-case
11533 01:26:34.590464 <8>[ 33.145203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11534 01:26:34.590728 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11536 01:26:34.604407 /lava-11368543/1/../bin/lava-test-case
11537 01:26:34.610996 <8>[ 33.165179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11538 01:26:34.611258 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11540 01:26:34.620598 /lava-11368543/1/../bin/lava-test-case
11541 01:26:34.627315 <8>[ 33.182497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11542 01:26:34.627572 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11544 01:26:34.638997 /lava-11368543/1/../bin/lava-test-case
11545 01:26:34.645578 <8>[ 33.199561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11546 01:26:34.645837 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11548 01:26:34.656457 /lava-11368543/1/../bin/lava-test-case
11549 01:26:34.663245 <8>[ 33.217536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11550 01:26:34.663506 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11552 01:26:34.672457 /lava-11368543/1/../bin/lava-test-case
11553 01:26:34.679064 <8>[ 33.233040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11554 01:26:34.679331 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11556 01:26:35.692351 /lava-11368543/1/../bin/lava-test-case
11557 01:26:35.698951 <8>[ 34.252925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11558 01:26:35.699261 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11560 01:26:35.715780 /lava-11368543/1/../bin/lava-tes<8>[ 34.269177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11561 01:26:35.715947 t-case
11562 01:26:35.716196 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11564 01:26:36.728024 /lava-11368543/1/../bin/lava-test-case
11565 01:26:36.734477 <8>[ 35.290668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11566 01:26:36.734747 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11568 01:26:36.745099 /lava-11368543/1/../bin/lava-test-case
11569 01:26:36.751744 <8>[ 35.305864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11570 01:26:36.752013 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11572 01:26:37.765403 /lava-11368543/1/../bin/lava-test-case
11573 01:26:37.771872 <8>[ 36.326458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11574 01:26:37.772154 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11576 01:26:37.782665 /lava-11368543/1/../bin/lava-test-case
11577 01:26:37.789161 <8>[ 36.344675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11578 01:26:37.789427 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11580 01:26:38.803333 /lava-11368543/1/../bin/lava-test-case
11581 01:26:38.809887 <8>[ 37.363887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11582 01:26:38.810647 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11584 01:26:38.819363 /lava-11368543/1/../bin/lava-test-case
11585 01:26:38.826213 <8>[ 37.381046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11586 01:26:38.826920 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11588 01:26:38.837189 /lava-11368543/1/../bin/lava-test-case
11589 01:26:38.843974 <8>[ 37.398022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11590 01:26:38.844780 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11592 01:26:38.854419 /lava-11368543/1/../bin/lava-test-case
11593 01:26:38.861016 <8>[ 37.414706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11594 01:26:38.861768 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11596 01:26:38.877564 /lava-11368543/1/../bin/lava-tes<8>[ 37.431214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11597 01:26:38.877652 t-case
11598 01:26:38.877901 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11600 01:26:38.888072 /lava-11368543/1/../bin/lava-test-case
11601 01:26:38.895124 <8>[ 37.450002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11602 01:26:38.895382 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11604 01:26:38.903014 /lava-11368543/1/../bin/lava-test-case
11605 01:26:38.909637 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11607 01:26:38.912861 <8>[ 37.465562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11608 01:26:38.923314 /lava-11368543/1/../bin/lava-test-case
11609 01:26:38.929722 <8>[ 37.484550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11610 01:26:38.929970 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11612 01:26:38.938384 /lava-11368543/1/../bin/lava-test-case
11613 01:26:38.945214 <8>[ 37.499714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11614 01:26:38.945463 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11616 01:26:38.959409 /lava-11368543/1/../bin/lava-test-case
11617 01:26:38.965505 <8>[ 37.520397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11618 01:26:38.965767 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11620 01:26:38.969736 + set +x
11621 01:26:38.973131 Received signal: <ENDRUN> 1_bootrr 11368543_1.5.2.3.5
11622 01:26:38.973214 Ending use of test pattern.
11623 01:26:38.973291 Ending test lava.1_bootrr (11368543_1.5.2.3.5), duration 20.32
11625 01:26:38.975845 <8>[ 37.530487] <LAVA_SIGNAL_ENDRUN 1_bootrr 11368543_1.5.2.3.5>
11626 01:26:38.979314 <LAVA_TEST_RUNNER EXIT>
11627 01:26:38.979564 ok: lava_test_shell seems to have completed
11628 01:26:38.980738 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11629 01:26:38.980902 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11630 01:26:38.981013 end: 4 lava-test-retry (duration 00:00:21) [common]
11631 01:26:38.981140 start: 5 finalize (timeout 00:07:59) [common]
11632 01:26:38.981279 start: 5.1 power-off (timeout 00:00:30) [common]
11633 01:26:38.981559 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11634 01:26:39.059268 >> Command sent successfully.
11635 01:26:39.064684 Returned 0 in 0 seconds
11636 01:26:39.165798 end: 5.1 power-off (duration 00:00:00) [common]
11638 01:26:39.167538 start: 5.2 read-feedback (timeout 00:07:59) [common]
11639 01:26:39.169106 Listened to connection for namespace 'common' for up to 1s
11640 01:26:40.169621 Finalising connection for namespace 'common'
11641 01:26:40.170243 Disconnecting from shell: Finalise
11642 01:26:40.170661 / #
11643 01:26:40.271534 end: 5.2 read-feedback (duration 00:00:01) [common]
11644 01:26:40.272452 end: 5 finalize (duration 00:00:01) [common]
11645 01:26:40.273070 Cleaning after the job
11646 01:26:40.273632 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/ramdisk
11647 01:26:40.288884 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/kernel
11648 01:26:40.310877 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/dtb
11649 01:26:40.311218 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368543/tftp-deploy-5parntst/modules
11650 01:26:40.321973 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11368543
11651 01:26:40.370724 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11368543
11652 01:26:40.370893 Job finished correctly