Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Errors: 1
- Kernel Warnings: 27
1 01:23:22.201651 lava-dispatcher, installed at version: 2023.06
2 01:23:22.201868 start: 0 validate
3 01:23:22.202002 Start time: 2023-08-28 01:23:22.201995+00:00 (UTC)
4 01:23:22.202131 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:23:22.202273 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 01:23:22.473083 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:23:22.473871 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:23:43.977718 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:23:43.978470 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:23:44.250002 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:23:44.250701 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:23:44.517115 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:23:44.517786 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:23:48.027370 validate duration: 25.83
16 01:23:48.027631 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:23:48.027732 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:23:48.027824 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:23:48.027960 Not decompressing ramdisk as can be used compressed.
20 01:23:48.028046 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 01:23:48.028110 saving as /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/ramdisk/initrd.cpio.gz
22 01:23:48.028172 total size: 4665412 (4 MB)
23 01:23:48.294151 progress 0 % (0 MB)
24 01:23:48.295701 progress 5 % (0 MB)
25 01:23:48.297111 progress 10 % (0 MB)
26 01:23:48.298377 progress 15 % (0 MB)
27 01:23:48.299680 progress 20 % (0 MB)
28 01:23:48.300959 progress 25 % (1 MB)
29 01:23:48.302211 progress 30 % (1 MB)
30 01:23:48.303441 progress 35 % (1 MB)
31 01:23:48.304742 progress 40 % (1 MB)
32 01:23:48.306134 progress 45 % (2 MB)
33 01:23:48.307414 progress 50 % (2 MB)
34 01:23:48.308757 progress 55 % (2 MB)
35 01:23:48.309992 progress 60 % (2 MB)
36 01:23:48.311225 progress 65 % (2 MB)
37 01:23:48.312501 progress 70 % (3 MB)
38 01:23:48.313729 progress 75 % (3 MB)
39 01:23:48.314946 progress 80 % (3 MB)
40 01:23:48.316397 progress 85 % (3 MB)
41 01:23:48.317696 progress 90 % (4 MB)
42 01:23:48.318919 progress 95 % (4 MB)
43 01:23:48.320241 progress 100 % (4 MB)
44 01:23:48.320397 4 MB downloaded in 0.29 s (15.23 MB/s)
45 01:23:48.320555 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:23:48.320790 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:23:48.320874 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:23:48.320956 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:23:48.321091 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:23:48.321158 saving as /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/kernel/Image
52 01:23:48.321218 total size: 49220096 (46 MB)
53 01:23:48.321277 No compression specified
54 01:23:48.322370 progress 0 % (0 MB)
55 01:23:48.335250 progress 5 % (2 MB)
56 01:23:48.347995 progress 10 % (4 MB)
57 01:23:48.360795 progress 15 % (7 MB)
58 01:23:48.373586 progress 20 % (9 MB)
59 01:23:48.386266 progress 25 % (11 MB)
60 01:23:48.399097 progress 30 % (14 MB)
61 01:23:48.412048 progress 35 % (16 MB)
62 01:23:48.424869 progress 40 % (18 MB)
63 01:23:48.437632 progress 45 % (21 MB)
64 01:23:48.450550 progress 50 % (23 MB)
65 01:23:48.463287 progress 55 % (25 MB)
66 01:23:48.476122 progress 60 % (28 MB)
67 01:23:48.489041 progress 65 % (30 MB)
68 01:23:48.501842 progress 70 % (32 MB)
69 01:23:48.514731 progress 75 % (35 MB)
70 01:23:48.527676 progress 80 % (37 MB)
71 01:23:48.540602 progress 85 % (39 MB)
72 01:23:48.553322 progress 90 % (42 MB)
73 01:23:48.565895 progress 95 % (44 MB)
74 01:23:48.578558 progress 100 % (46 MB)
75 01:23:48.578729 46 MB downloaded in 0.26 s (182.29 MB/s)
76 01:23:48.578883 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:23:48.579141 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:23:48.579257 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:23:48.579358 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:23:48.579499 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:23:48.579570 saving as /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/dtb/mt8192-asurada-spherion-r0.dtb
83 01:23:48.579630 total size: 47278 (0 MB)
84 01:23:48.579690 No compression specified
85 01:23:48.580846 progress 69 % (0 MB)
86 01:23:48.581124 progress 100 % (0 MB)
87 01:23:48.581277 0 MB downloaded in 0.00 s (27.42 MB/s)
88 01:23:48.581399 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:23:48.581615 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:23:48.581696 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:23:48.581777 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:23:48.581892 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 01:23:48.581959 saving as /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/nfsrootfs/full.rootfs.tar
95 01:23:48.582018 total size: 125290964 (119 MB)
96 01:23:48.582077 Using unxz to decompress xz
97 01:23:48.586264 progress 0 % (0 MB)
98 01:23:48.911256 progress 5 % (6 MB)
99 01:23:49.242993 progress 10 % (11 MB)
100 01:23:49.572045 progress 15 % (17 MB)
101 01:23:49.757137 progress 20 % (23 MB)
102 01:23:49.937043 progress 25 % (29 MB)
103 01:23:50.287526 progress 30 % (35 MB)
104 01:23:50.640394 progress 35 % (41 MB)
105 01:23:51.023521 progress 40 % (47 MB)
106 01:23:51.398473 progress 45 % (53 MB)
107 01:23:51.786274 progress 50 % (59 MB)
108 01:23:52.139787 progress 55 % (65 MB)
109 01:23:52.502483 progress 60 % (71 MB)
110 01:23:52.839133 progress 65 % (77 MB)
111 01:23:53.204357 progress 70 % (83 MB)
112 01:23:53.582980 progress 75 % (89 MB)
113 01:23:53.998868 progress 80 % (95 MB)
114 01:23:54.413023 progress 85 % (101 MB)
115 01:23:54.658894 progress 90 % (107 MB)
116 01:23:54.999103 progress 95 % (113 MB)
117 01:23:55.373593 progress 100 % (119 MB)
118 01:23:55.379284 119 MB downloaded in 6.80 s (17.58 MB/s)
119 01:23:55.379599 end: 1.4.1 http-download (duration 00:00:07) [common]
121 01:23:55.379871 end: 1.4 download-retry (duration 00:00:07) [common]
122 01:23:55.380001 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:23:55.380090 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:23:55.380247 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:23:55.380317 saving as /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/modules/modules.tar
126 01:23:55.380377 total size: 8616896 (8 MB)
127 01:23:55.380441 Using unxz to decompress xz
128 01:23:55.650089 progress 0 % (0 MB)
129 01:23:55.672464 progress 5 % (0 MB)
130 01:23:55.698879 progress 10 % (0 MB)
131 01:23:55.728981 progress 15 % (1 MB)
132 01:23:55.757794 progress 20 % (1 MB)
133 01:23:55.781772 progress 25 % (2 MB)
134 01:23:55.805929 progress 30 % (2 MB)
135 01:23:55.833322 progress 35 % (2 MB)
136 01:23:55.858300 progress 40 % (3 MB)
137 01:23:55.884700 progress 45 % (3 MB)
138 01:23:55.910691 progress 50 % (4 MB)
139 01:23:55.936769 progress 55 % (4 MB)
140 01:23:55.962259 progress 60 % (4 MB)
141 01:23:55.986821 progress 65 % (5 MB)
142 01:23:56.012596 progress 70 % (5 MB)
143 01:23:56.038698 progress 75 % (6 MB)
144 01:23:56.063335 progress 80 % (6 MB)
145 01:23:56.089178 progress 85 % (7 MB)
146 01:23:56.114297 progress 90 % (7 MB)
147 01:23:56.138897 progress 95 % (7 MB)
148 01:23:56.165784 progress 100 % (8 MB)
149 01:23:56.172152 8 MB downloaded in 0.79 s (10.38 MB/s)
150 01:23:56.172442 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:23:56.172724 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:23:56.172819 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 01:23:56.172913 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 01:23:58.353713 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf
156 01:23:58.353899 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 01:23:58.354002 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 01:23:58.354158 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6
159 01:23:58.354289 makedir: /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin
160 01:23:58.354391 makedir: /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/tests
161 01:23:58.354489 makedir: /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/results
162 01:23:58.354591 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-add-keys
163 01:23:58.354731 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-add-sources
164 01:23:58.354858 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-background-process-start
165 01:23:58.354985 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-background-process-stop
166 01:23:58.355111 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-common-functions
167 01:23:58.355235 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-echo-ipv4
168 01:23:58.355360 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-install-packages
169 01:23:58.355507 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-installed-packages
170 01:23:58.355648 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-os-build
171 01:23:58.355772 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-probe-channel
172 01:23:58.355895 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-probe-ip
173 01:23:58.356056 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-target-ip
174 01:23:58.356180 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-target-mac
175 01:23:58.356302 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-target-storage
176 01:23:58.356428 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-case
177 01:23:58.356554 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-event
178 01:23:58.356677 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-feedback
179 01:23:58.356800 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-raise
180 01:23:58.356923 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-reference
181 01:23:58.357046 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-runner
182 01:23:58.357170 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-set
183 01:23:58.357294 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-test-shell
184 01:23:58.357421 Updating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-install-packages (oe)
185 01:23:58.357567 Updating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/bin/lava-installed-packages (oe)
186 01:23:58.357692 Creating /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/environment
187 01:23:58.357790 LAVA metadata
188 01:23:58.357861 - LAVA_JOB_ID=11368520
189 01:23:58.357925 - LAVA_DISPATCHER_IP=192.168.201.1
190 01:23:58.358030 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 01:23:58.358098 skipped lava-vland-overlay
192 01:23:58.358172 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 01:23:58.358250 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 01:23:58.358326 skipped lava-multinode-overlay
195 01:23:58.358401 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 01:23:58.358478 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 01:23:58.358552 Loading test definitions
198 01:23:58.358641 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 01:23:58.358713 Using /lava-11368520 at stage 0
200 01:23:58.359017 uuid=11368520_1.6.2.3.1 testdef=None
201 01:23:58.359105 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 01:23:58.359191 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 01:23:58.359700 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 01:23:58.360137 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 01:23:58.360791 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 01:23:58.361023 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 01:23:58.361646 runner path: /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/0/tests/0_dmesg test_uuid 11368520_1.6.2.3.1
210 01:23:58.361805 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 01:23:58.362025 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 01:23:58.362097 Using /lava-11368520 at stage 1
214 01:23:58.362398 uuid=11368520_1.6.2.3.5 testdef=None
215 01:23:58.362486 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 01:23:58.362571 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 01:23:58.363044 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 01:23:58.363260 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 01:23:58.364021 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 01:23:58.364250 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 01:23:58.364883 runner path: /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/1/tests/1_bootrr test_uuid 11368520_1.6.2.3.5
224 01:23:58.365038 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 01:23:58.365240 Creating lava-test-runner.conf files
227 01:23:58.365301 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/0 for stage 0
228 01:23:58.365391 - 0_dmesg
229 01:23:58.365471 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11368520/lava-overlay-0qkqe2w6/lava-11368520/1 for stage 1
230 01:23:58.365562 - 1_bootrr
231 01:23:58.365658 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 01:23:58.365742 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 01:23:58.373004 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 01:23:58.373137 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 01:23:58.373230 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 01:23:58.373317 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 01:23:58.373401 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 01:23:58.494832 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 01:23:58.495227 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 01:23:58.495346 extracting modules file /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf
241 01:23:58.718793 extracting modules file /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11368520/extract-overlay-ramdisk-3iz3de09/ramdisk
242 01:23:58.948309 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 01:23:58.948469 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 01:23:58.948565 [common] Applying overlay to NFS
245 01:23:58.948638 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368520/compress-overlay-s35uy43d/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf
246 01:23:58.956828 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 01:23:58.956988 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 01:23:58.957082 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 01:23:58.957169 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 01:23:58.957248 Building ramdisk /var/lib/lava/dispatcher/tmp/11368520/extract-overlay-ramdisk-3iz3de09/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11368520/extract-overlay-ramdisk-3iz3de09/ramdisk
251 01:23:59.333025 >> 119219 blocks
252 01:24:01.241207 rename /var/lib/lava/dispatcher/tmp/11368520/extract-overlay-ramdisk-3iz3de09/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/ramdisk/ramdisk.cpio.gz
253 01:24:01.241650 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 01:24:01.241783 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 01:24:01.241885 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 01:24:01.241995 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/kernel/Image'
257 01:24:14.103843 Returned 0 in 12 seconds
258 01:24:14.204658 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/kernel/image.itb
259 01:24:14.569015 output: FIT description: Kernel Image image with one or more FDT blobs
260 01:24:14.569378 output: Created: Mon Aug 28 02:24:14 2023
261 01:24:14.569456 output: Image 0 (kernel-1)
262 01:24:14.569522 output: Description:
263 01:24:14.569615 output: Created: Mon Aug 28 02:24:14 2023
264 01:24:14.569711 output: Type: Kernel Image
265 01:24:14.569805 output: Compression: lzma compressed
266 01:24:14.569894 output: Data Size: 11038667 Bytes = 10779.95 KiB = 10.53 MiB
267 01:24:14.569988 output: Architecture: AArch64
268 01:24:14.570079 output: OS: Linux
269 01:24:14.570170 output: Load Address: 0x00000000
270 01:24:14.570251 output: Entry Point: 0x00000000
271 01:24:14.570332 output: Hash algo: crc32
272 01:24:14.570418 output: Hash value: 3affb6e1
273 01:24:14.570502 output: Image 1 (fdt-1)
274 01:24:14.570586 output: Description: mt8192-asurada-spherion-r0
275 01:24:14.570667 output: Created: Mon Aug 28 02:24:14 2023
276 01:24:14.570753 output: Type: Flat Device Tree
277 01:24:14.570838 output: Compression: uncompressed
278 01:24:14.570925 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 01:24:14.570981 output: Architecture: AArch64
280 01:24:14.571037 output: Hash algo: crc32
281 01:24:14.571090 output: Hash value: cc4352de
282 01:24:14.571142 output: Image 2 (ramdisk-1)
283 01:24:14.571208 output: Description: unavailable
284 01:24:14.571273 output: Created: Mon Aug 28 02:24:14 2023
285 01:24:14.571358 output: Type: RAMDisk Image
286 01:24:14.571439 output: Compression: Unknown Compression
287 01:24:14.571525 output: Data Size: 17766234 Bytes = 17349.84 KiB = 16.94 MiB
288 01:24:14.571609 output: Architecture: AArch64
289 01:24:14.571691 output: OS: Linux
290 01:24:14.571771 output: Load Address: unavailable
291 01:24:14.571857 output: Entry Point: unavailable
292 01:24:14.571974 output: Hash algo: crc32
293 01:24:14.572056 output: Hash value: 411ed951
294 01:24:14.572137 output: Default Configuration: 'conf-1'
295 01:24:14.572222 output: Configuration 0 (conf-1)
296 01:24:14.572304 output: Description: mt8192-asurada-spherion-r0
297 01:24:14.572387 output: Kernel: kernel-1
298 01:24:14.572473 output: Init Ramdisk: ramdisk-1
299 01:24:14.572557 output: FDT: fdt-1
300 01:24:14.572638 output: Loadables: kernel-1
301 01:24:14.572738 output:
302 01:24:14.573062 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 01:24:14.573201 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 01:24:14.573332 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 01:24:14.573461 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 01:24:14.573563 No LXC device requested
307 01:24:14.573674 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 01:24:14.573790 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 01:24:14.573897 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 01:24:14.573991 Checking files for TFTP limit of 4294967296 bytes.
311 01:24:14.574661 end: 1 tftp-deploy (duration 00:00:27) [common]
312 01:24:14.574792 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 01:24:14.574910 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 01:24:14.575073 substitutions:
315 01:24:14.575166 - {DTB}: 11368520/tftp-deploy-fcn7bodx/dtb/mt8192-asurada-spherion-r0.dtb
316 01:24:14.575232 - {INITRD}: 11368520/tftp-deploy-fcn7bodx/ramdisk/ramdisk.cpio.gz
317 01:24:14.575291 - {KERNEL}: 11368520/tftp-deploy-fcn7bodx/kernel/Image
318 01:24:14.575392 - {LAVA_MAC}: None
319 01:24:14.575462 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf
320 01:24:14.575518 - {NFS_SERVER_IP}: 192.168.201.1
321 01:24:14.575571 - {PRESEED_CONFIG}: None
322 01:24:14.575625 - {PRESEED_LOCAL}: None
323 01:24:14.575677 - {RAMDISK}: 11368520/tftp-deploy-fcn7bodx/ramdisk/ramdisk.cpio.gz
324 01:24:14.575754 - {ROOT_PART}: None
325 01:24:14.575856 - {ROOT}: None
326 01:24:14.575964 - {SERVER_IP}: 192.168.201.1
327 01:24:14.576047 - {TEE}: None
328 01:24:14.576129 Parsed boot commands:
329 01:24:14.576215 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 01:24:14.576451 Parsed boot commands: tftpboot 192.168.201.1 11368520/tftp-deploy-fcn7bodx/kernel/image.itb 11368520/tftp-deploy-fcn7bodx/kernel/cmdline
331 01:24:14.576594 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 01:24:14.576706 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 01:24:14.576829 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 01:24:14.576946 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 01:24:14.577047 Not connected, no need to disconnect.
336 01:24:14.577221 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 01:24:14.577340 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 01:24:14.577438 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
339 01:24:14.581815 Setting prompt string to ['lava-test: # ']
340 01:24:14.582227 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 01:24:14.582375 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 01:24:14.582502 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 01:24:14.582627 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 01:24:14.582956 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 01:24:19.730869 >> Command sent successfully.
346 01:24:19.741521 Returned 0 in 5 seconds
347 01:24:19.842766 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 01:24:19.843869 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 01:24:19.844308 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 01:24:19.844575 Setting prompt string to 'Starting depthcharge on Spherion...'
352 01:24:19.844793 Changing prompt to 'Starting depthcharge on Spherion...'
353 01:24:19.845013 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 01:24:19.845807 [Enter `^Ec?' for help]
355 01:24:20.008277
356 01:24:20.008411
357 01:24:20.008479 F0: 102B 0000
358 01:24:20.008542
359 01:24:20.008600 F3: 1001 0000 [0200]
360 01:24:20.010954
361 01:24:20.011065 F3: 1001 0000
362 01:24:20.011164
363 01:24:20.011241 F7: 102D 0000
364 01:24:20.011302
365 01:24:20.014081 F1: 0000 0000
366 01:24:20.014163
367 01:24:20.014229 V0: 0000 0000 [0001]
368 01:24:20.014294
369 01:24:20.017560 00: 0007 8000
370 01:24:20.017646
371 01:24:20.017712 01: 0000 0000
372 01:24:20.017774
373 01:24:20.021065 BP: 0C00 0209 [0000]
374 01:24:20.021148
375 01:24:20.021213 G0: 1182 0000
376 01:24:20.021273
377 01:24:20.024496 EC: 0000 0021 [4000]
378 01:24:20.024579
379 01:24:20.024645 S7: 0000 0000 [0000]
380 01:24:20.024705
381 01:24:20.028712 CC: 0000 0000 [0001]
382 01:24:20.028795
383 01:24:20.028860 T0: 0000 0040 [010F]
384 01:24:20.028921
385 01:24:20.028979 Jump to BL
386 01:24:20.031718
387 01:24:20.054552
388 01:24:20.054655
389 01:24:20.054723
390 01:24:20.062289 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 01:24:20.066164 ARM64: Exception handlers installed.
392 01:24:20.069663 ARM64: Testing exception
393 01:24:20.073038 ARM64: Done test exception
394 01:24:20.079327 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 01:24:20.089860 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 01:24:20.096439 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 01:24:20.106580 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 01:24:20.113115 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 01:24:20.119900 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 01:24:20.131715 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 01:24:20.138204 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 01:24:20.157717 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 01:24:20.161054 WDT: Last reset was cold boot
404 01:24:20.164376 SPI1(PAD0) initialized at 2873684 Hz
405 01:24:20.167459 SPI5(PAD0) initialized at 992727 Hz
406 01:24:20.171303 VBOOT: Loading verstage.
407 01:24:20.177441 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 01:24:20.180664 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 01:24:20.184116 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 01:24:20.187447 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 01:24:20.194678 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 01:24:20.201761 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 01:24:20.212783 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 01:24:20.212867
415 01:24:20.212931
416 01:24:20.222621 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 01:24:20.225846 ARM64: Exception handlers installed.
418 01:24:20.229064 ARM64: Testing exception
419 01:24:20.229145 ARM64: Done test exception
420 01:24:20.237124 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 01:24:20.239634 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:24:20.253769 Probing TPM: . done!
423 01:24:20.253852 TPM ready after 0 ms
424 01:24:20.261556 Connected to device vid:did:rid of 1ae0:0028:00
425 01:24:20.269477 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 01:24:20.326518 Initialized TPM device CR50 revision 0
427 01:24:20.337445 tlcl_send_startup: Startup return code is 0
428 01:24:20.337538 TPM: setup succeeded
429 01:24:20.348977 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 01:24:20.358129 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 01:24:20.370068 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 01:24:20.380660 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 01:24:20.383493 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 01:24:20.388117 in-header: 03 07 00 00 08 00 00 00
435 01:24:20.392579 in-data: aa e4 47 04 13 02 00 00
436 01:24:20.395761 Chrome EC: UHEPI supported
437 01:24:20.403176 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 01:24:20.407395 in-header: 03 95 00 00 08 00 00 00
439 01:24:20.410422 in-data: 18 20 20 08 00 00 00 00
440 01:24:20.410504 Phase 1
441 01:24:20.413994 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 01:24:20.421242 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 01:24:20.425626 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 01:24:20.429366 Recovery requested (1009000e)
445 01:24:20.437185 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 01:24:20.443077 tlcl_extend: response is 0
447 01:24:20.452235 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 01:24:20.457813 tlcl_extend: response is 0
449 01:24:20.464576 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 01:24:20.485000 read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps
451 01:24:20.491362 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 01:24:20.491446
453 01:24:20.491511
454 01:24:20.500911 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 01:24:20.504391 ARM64: Exception handlers installed.
456 01:24:20.507873 ARM64: Testing exception
457 01:24:20.507977 ARM64: Done test exception
458 01:24:20.529925 pmic_efuse_setting: Set efuses in 11 msecs
459 01:24:20.533578 pmwrap_interface_init: Select PMIF_VLD_RDY
460 01:24:20.539808 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 01:24:20.543151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 01:24:20.550601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 01:24:20.554320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 01:24:20.558073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 01:24:20.564633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 01:24:20.569022 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 01:24:20.572308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 01:24:20.576093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 01:24:20.583355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 01:24:20.586634 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 01:24:20.590935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 01:24:20.594405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 01:24:20.602298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 01:24:20.609632 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 01:24:20.612593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 01:24:20.620465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 01:24:20.624097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 01:24:20.631818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 01:24:20.635624 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 01:24:20.642980 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 01:24:20.646420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 01:24:20.654017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 01:24:20.658088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 01:24:20.665065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 01:24:20.668818 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 01:24:20.675735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 01:24:20.679454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 01:24:20.683088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 01:24:20.690198 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 01:24:20.694009 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 01:24:20.697157 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 01:24:20.705011 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 01:24:20.708558 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 01:24:20.715805 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 01:24:20.719407 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 01:24:20.723245 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 01:24:20.731135 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 01:24:20.734928 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 01:24:20.738606 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 01:24:20.741855 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 01:24:20.745915 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 01:24:20.752599 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 01:24:20.756380 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 01:24:20.760667 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 01:24:20.764096 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 01:24:20.767735 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 01:24:20.771319 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 01:24:20.778573 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 01:24:20.782212 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 01:24:20.785983 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 01:24:20.793593 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 01:24:20.800473 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 01:24:20.807877 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 01:24:20.815275 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 01:24:20.822335 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 01:24:20.825674 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 01:24:20.833598 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 01:24:20.836845 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 01:24:20.843978 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x5
520 01:24:20.847455 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 01:24:20.855028 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 01:24:20.857984 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 01:24:20.867468 [RTC]rtc_get_frequency_meter,154: input=15, output=852
524 01:24:20.877029 [RTC]rtc_get_frequency_meter,154: input=7, output=724
525 01:24:20.886749 [RTC]rtc_get_frequency_meter,154: input=11, output=789
526 01:24:20.895649 [RTC]rtc_get_frequency_meter,154: input=13, output=821
527 01:24:20.905848 [RTC]rtc_get_frequency_meter,154: input=12, output=805
528 01:24:20.915052 [RTC]rtc_get_frequency_meter,154: input=11, output=788
529 01:24:20.925288 [RTC]rtc_get_frequency_meter,154: input=12, output=805
530 01:24:20.929359 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 01:24:20.932727 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 01:24:20.936287 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 01:24:20.943754 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
534 01:24:20.947311 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 01:24:20.951006 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 01:24:20.954999 ADC[4]: Raw value=904433 ID=7
537 01:24:20.955085 ADC[3]: Raw value=213546 ID=1
538 01:24:20.958423 RAM Code: 0x71
539 01:24:20.961916 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 01:24:20.966186 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 01:24:20.976537 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 01:24:20.984384 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 01:24:20.984469 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 01:24:20.988457 in-header: 03 07 00 00 08 00 00 00
545 01:24:20.991655 in-data: aa e4 47 04 13 02 00 00
546 01:24:20.995585 Chrome EC: UHEPI supported
547 01:24:21.002577 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 01:24:21.006481 in-header: 03 95 00 00 08 00 00 00
549 01:24:21.006561 in-data: 18 20 20 08 00 00 00 00
550 01:24:21.010582 MRC: failed to locate region type 0.
551 01:24:21.017483 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 01:24:21.021668 DRAM-K: Running full calibration
553 01:24:21.028700 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 01:24:21.028779 header.status = 0x0
555 01:24:21.032057 header.version = 0x6 (expected: 0x6)
556 01:24:21.035765 header.size = 0xd00 (expected: 0xd00)
557 01:24:21.035841 header.flags = 0x0
558 01:24:21.043208 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 01:24:21.062085 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 01:24:21.068867 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 01:24:21.072563 dram_init: ddr_geometry: 2
562 01:24:21.072640 [EMI] MDL number = 2
563 01:24:21.076313 [EMI] Get MDL freq = 0
564 01:24:21.076397 dram_init: ddr_type: 0
565 01:24:21.080201 is_discrete_lpddr4: 1
566 01:24:21.084105 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 01:24:21.084180
568 01:24:21.084245
569 01:24:21.084303 [Bian_co] ETT version 0.0.0.1
570 01:24:21.091199 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 01:24:21.091277
572 01:24:21.095007 dramc_set_vcore_voltage set vcore to 650000
573 01:24:21.095080 Read voltage for 800, 4
574 01:24:21.098661 Vio18 = 0
575 01:24:21.098736 Vcore = 650000
576 01:24:21.098798 Vdram = 0
577 01:24:21.098856 Vddq = 0
578 01:24:21.102467 Vmddr = 0
579 01:24:21.102537 dram_init: config_dvfs: 1
580 01:24:21.109139 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 01:24:21.112308 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 01:24:21.119000 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 01:24:21.122430 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 01:24:21.126027 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 01:24:21.129654 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 01:24:21.133233 MEM_TYPE=3, freq_sel=18
587 01:24:21.133379 sv_algorithm_assistance_LP4_1600
588 01:24:21.136998 ============ PULL DRAM RESETB DOWN ============
589 01:24:21.144717 ========== PULL DRAM RESETB DOWN end =========
590 01:24:21.147827 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 01:24:21.150947 ===================================
592 01:24:21.151026 LPDDR4 DRAM CONFIGURATION
593 01:24:21.154345 ===================================
594 01:24:21.158168 EX_ROW_EN[0] = 0x0
595 01:24:21.161122 EX_ROW_EN[1] = 0x0
596 01:24:21.161200 LP4Y_EN = 0x0
597 01:24:21.164851 WORK_FSP = 0x0
598 01:24:21.164924 WL = 0x2
599 01:24:21.168119 RL = 0x2
600 01:24:21.168196 BL = 0x2
601 01:24:21.171383 RPST = 0x0
602 01:24:21.171460 RD_PRE = 0x0
603 01:24:21.174589 WR_PRE = 0x1
604 01:24:21.174663 WR_PST = 0x0
605 01:24:21.177856 DBI_WR = 0x0
606 01:24:21.177931 DBI_RD = 0x0
607 01:24:21.181297 OTF = 0x1
608 01:24:21.184164 ===================================
609 01:24:21.187130 ===================================
610 01:24:21.187203 ANA top config
611 01:24:21.190679 ===================================
612 01:24:21.194108 DLL_ASYNC_EN = 0
613 01:24:21.197360 ALL_SLAVE_EN = 1
614 01:24:21.200500 NEW_RANK_MODE = 1
615 01:24:21.200580 DLL_IDLE_MODE = 1
616 01:24:21.204749 LP45_APHY_COMB_EN = 1
617 01:24:21.207297 TX_ODT_DIS = 1
618 01:24:21.210379 NEW_8X_MODE = 1
619 01:24:21.213948 ===================================
620 01:24:21.216984 ===================================
621 01:24:21.220568 data_rate = 1600
622 01:24:21.223699 CKR = 1
623 01:24:21.223773 DQ_P2S_RATIO = 8
624 01:24:21.227122 ===================================
625 01:24:21.230575 CA_P2S_RATIO = 8
626 01:24:21.234215 DQ_CA_OPEN = 0
627 01:24:21.237829 DQ_SEMI_OPEN = 0
628 01:24:21.237908 CA_SEMI_OPEN = 0
629 01:24:21.241047 CA_FULL_RATE = 0
630 01:24:21.244599 DQ_CKDIV4_EN = 1
631 01:24:21.248096 CA_CKDIV4_EN = 1
632 01:24:21.250833 CA_PREDIV_EN = 0
633 01:24:21.254428 PH8_DLY = 0
634 01:24:21.254511 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 01:24:21.257794 DQ_AAMCK_DIV = 4
636 01:24:21.261208 CA_AAMCK_DIV = 4
637 01:24:21.264144 CA_ADMCK_DIV = 4
638 01:24:21.267622 DQ_TRACK_CA_EN = 0
639 01:24:21.270795 CA_PICK = 800
640 01:24:21.274491 CA_MCKIO = 800
641 01:24:21.274571 MCKIO_SEMI = 0
642 01:24:21.278168 PLL_FREQ = 3068
643 01:24:21.281562 DQ_UI_PI_RATIO = 32
644 01:24:21.285407 CA_UI_PI_RATIO = 0
645 01:24:21.288735 ===================================
646 01:24:21.292655 ===================================
647 01:24:21.292735 memory_type:LPDDR4
648 01:24:21.296565 GP_NUM : 10
649 01:24:21.296640 SRAM_EN : 1
650 01:24:21.299940 MD32_EN : 0
651 01:24:21.304123 ===================================
652 01:24:21.304198 [ANA_INIT] >>>>>>>>>>>>>>
653 01:24:21.308107 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 01:24:21.311805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 01:24:21.314982 ===================================
656 01:24:21.318458 data_rate = 1600,PCW = 0X7600
657 01:24:21.321700 ===================================
658 01:24:21.325408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 01:24:21.328210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 01:24:21.335162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 01:24:21.338406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 01:24:21.341319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 01:24:21.347851 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 01:24:21.347946 [ANA_INIT] flow start
665 01:24:21.351307 [ANA_INIT] PLL >>>>>>>>
666 01:24:21.351378 [ANA_INIT] PLL <<<<<<<<
667 01:24:21.354816 [ANA_INIT] MIDPI >>>>>>>>
668 01:24:21.358043 [ANA_INIT] MIDPI <<<<<<<<
669 01:24:21.361364 [ANA_INIT] DLL >>>>>>>>
670 01:24:21.361436 [ANA_INIT] flow end
671 01:24:21.364702 ============ LP4 DIFF to SE enter ============
672 01:24:21.372196 ============ LP4 DIFF to SE exit ============
673 01:24:21.372280 [ANA_INIT] <<<<<<<<<<<<<
674 01:24:21.374583 [Flow] Enable top DCM control >>>>>
675 01:24:21.377910 [Flow] Enable top DCM control <<<<<
676 01:24:21.381712 Enable DLL master slave shuffle
677 01:24:21.388694 ==============================================================
678 01:24:21.388773 Gating Mode config
679 01:24:21.395233 ==============================================================
680 01:24:21.398053 Config description:
681 01:24:21.407806 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 01:24:21.414953 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 01:24:21.418005 SELPH_MODE 0: By rank 1: By Phase
684 01:24:21.424897 ==============================================================
685 01:24:21.427972 GAT_TRACK_EN = 1
686 01:24:21.428049 RX_GATING_MODE = 2
687 01:24:21.431515 RX_GATING_TRACK_MODE = 2
688 01:24:21.434733 SELPH_MODE = 1
689 01:24:21.437997 PICG_EARLY_EN = 1
690 01:24:21.441547 VALID_LAT_VALUE = 1
691 01:24:21.448269 ==============================================================
692 01:24:21.451046 Enter into Gating configuration >>>>
693 01:24:21.454179 Exit from Gating configuration <<<<
694 01:24:21.457682 Enter into DVFS_PRE_config >>>>>
695 01:24:21.467686 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 01:24:21.471170 Exit from DVFS_PRE_config <<<<<
697 01:24:21.474472 Enter into PICG configuration >>>>
698 01:24:21.478305 Exit from PICG configuration <<<<
699 01:24:21.481315 [RX_INPUT] configuration >>>>>
700 01:24:21.484196 [RX_INPUT] configuration <<<<<
701 01:24:21.487814 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 01:24:21.494235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 01:24:21.501062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 01:24:21.507447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 01:24:21.510966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 01:24:21.517393 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 01:24:21.520592 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 01:24:21.527171 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 01:24:21.530479 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 01:24:21.534254 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 01:24:21.537152 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 01:24:21.544457 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 01:24:21.547128 ===================================
714 01:24:21.547215 LPDDR4 DRAM CONFIGURATION
715 01:24:21.550710 ===================================
716 01:24:21.554357 EX_ROW_EN[0] = 0x0
717 01:24:21.557513 EX_ROW_EN[1] = 0x0
718 01:24:21.557589 LP4Y_EN = 0x0
719 01:24:21.560424 WORK_FSP = 0x0
720 01:24:21.560492 WL = 0x2
721 01:24:21.563907 RL = 0x2
722 01:24:21.563992 BL = 0x2
723 01:24:21.567257 RPST = 0x0
724 01:24:21.567323 RD_PRE = 0x0
725 01:24:21.570929 WR_PRE = 0x1
726 01:24:21.571005 WR_PST = 0x0
727 01:24:21.574029 DBI_WR = 0x0
728 01:24:21.574105 DBI_RD = 0x0
729 01:24:21.576888 OTF = 0x1
730 01:24:21.580444 ===================================
731 01:24:21.583780 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 01:24:21.587415 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 01:24:21.593462 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 01:24:21.597409 ===================================
735 01:24:21.597481 LPDDR4 DRAM CONFIGURATION
736 01:24:21.600237 ===================================
737 01:24:21.603643 EX_ROW_EN[0] = 0x10
738 01:24:21.607558 EX_ROW_EN[1] = 0x0
739 01:24:21.607639 LP4Y_EN = 0x0
740 01:24:21.610153 WORK_FSP = 0x0
741 01:24:21.610235 WL = 0x2
742 01:24:21.613672 RL = 0x2
743 01:24:21.613754 BL = 0x2
744 01:24:21.617083 RPST = 0x0
745 01:24:21.617164 RD_PRE = 0x0
746 01:24:21.620547 WR_PRE = 0x1
747 01:24:21.620628 WR_PST = 0x0
748 01:24:21.623409 DBI_WR = 0x0
749 01:24:21.623489 DBI_RD = 0x0
750 01:24:21.626967 OTF = 0x1
751 01:24:21.630238 ===================================
752 01:24:21.636961 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 01:24:21.639918 nWR fixed to 40
754 01:24:21.640018 [ModeRegInit_LP4] CH0 RK0
755 01:24:21.643805 [ModeRegInit_LP4] CH0 RK1
756 01:24:21.646878 [ModeRegInit_LP4] CH1 RK0
757 01:24:21.650323 [ModeRegInit_LP4] CH1 RK1
758 01:24:21.650404 match AC timing 13
759 01:24:21.653341 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 01:24:21.660240 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 01:24:21.663538 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 01:24:21.669731 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 01:24:21.673464 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 01:24:21.673549 [EMI DOE] emi_dcm 0
765 01:24:21.679707 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 01:24:21.679816 ==
767 01:24:21.683155 Dram Type= 6, Freq= 0, CH_0, rank 0
768 01:24:21.686761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 01:24:21.686842 ==
770 01:24:21.693102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 01:24:21.696385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 01:24:21.707727 [CA 0] Center 37 (7~68) winsize 62
773 01:24:21.710429 [CA 1] Center 37 (7~68) winsize 62
774 01:24:21.713952 [CA 2] Center 34 (4~65) winsize 62
775 01:24:21.716796 [CA 3] Center 35 (4~66) winsize 63
776 01:24:21.720211 [CA 4] Center 33 (3~64) winsize 62
777 01:24:21.723736 [CA 5] Center 33 (3~64) winsize 62
778 01:24:21.723841
779 01:24:21.726944 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 01:24:21.727030
781 01:24:21.730232 [CATrainingPosCal] consider 1 rank data
782 01:24:21.733270 u2DelayCellTimex100 = 270/100 ps
783 01:24:21.736553 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 01:24:21.743346 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 01:24:21.746671 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 01:24:21.750342 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 01:24:21.753332 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 01:24:21.756598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 01:24:21.756671
790 01:24:21.760264 CA PerBit enable=1, Macro0, CA PI delay=33
791 01:24:21.760354
792 01:24:21.763854 [CBTSetCACLKResult] CA Dly = 33
793 01:24:21.763968 CS Dly: 6 (0~37)
794 01:24:21.764031 ==
795 01:24:21.767123 Dram Type= 6, Freq= 0, CH_0, rank 1
796 01:24:21.774011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 01:24:21.774088 ==
798 01:24:21.777767 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 01:24:21.783237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 01:24:21.793341 [CA 0] Center 38 (7~69) winsize 63
801 01:24:21.796406 [CA 1] Center 37 (7~68) winsize 62
802 01:24:21.800162 [CA 2] Center 34 (4~65) winsize 62
803 01:24:21.803171 [CA 3] Center 35 (4~66) winsize 63
804 01:24:21.806461 [CA 4] Center 34 (3~65) winsize 63
805 01:24:21.810021 [CA 5] Center 33 (3~64) winsize 62
806 01:24:21.810092
807 01:24:21.813094 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 01:24:21.813164
809 01:24:21.816423 [CATrainingPosCal] consider 2 rank data
810 01:24:21.819895 u2DelayCellTimex100 = 270/100 ps
811 01:24:21.823066 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 01:24:21.827164 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 01:24:21.833983 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 01:24:21.836288 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
815 01:24:21.839534 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 01:24:21.843345 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 01:24:21.843420
818 01:24:21.846173 CA PerBit enable=1, Macro0, CA PI delay=33
819 01:24:21.846243
820 01:24:21.849919 [CBTSetCACLKResult] CA Dly = 33
821 01:24:21.849988 CS Dly: 6 (0~38)
822 01:24:21.850048
823 01:24:21.856705 ----->DramcWriteLeveling(PI) begin...
824 01:24:21.856780 ==
825 01:24:21.856846 Dram Type= 6, Freq= 0, CH_0, rank 0
826 01:24:21.863743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 01:24:21.863874 ==
828 01:24:21.867838 Write leveling (Byte 0): 32 => 32
829 01:24:21.867965 Write leveling (Byte 1): 27 => 27
830 01:24:21.871056 DramcWriteLeveling(PI) end<-----
831 01:24:21.871136
832 01:24:21.871200 ==
833 01:24:21.875082 Dram Type= 6, Freq= 0, CH_0, rank 0
834 01:24:21.878669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 01:24:21.881369 ==
836 01:24:21.881447 [Gating] SW mode calibration
837 01:24:21.888701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 01:24:21.895138 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 01:24:21.899119 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 01:24:21.901863 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 01:24:21.908668 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 01:24:21.911895 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 01:24:21.915285 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 01:24:21.921939 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 01:24:21.925116 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 01:24:21.928355 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 01:24:21.935685 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 01:24:21.938555 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 01:24:21.942099 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 01:24:21.948563 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 01:24:21.951762 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 01:24:21.955199 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 01:24:21.961872 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 01:24:21.965373 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 01:24:21.969382 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 01:24:21.975471 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 01:24:21.978861 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 01:24:21.981618 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:24:21.988885 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:24:21.991857 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:24:21.995531 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:24:22.001551 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:24:22.005158 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:24:22.008258 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:24:22.015006 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (1 1) (0 0)
866 01:24:22.018057 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
867 01:24:22.021596 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 01:24:22.027825 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 01:24:22.031513 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 01:24:22.034652 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 01:24:22.041363 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 01:24:22.044915 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
873 01:24:22.047821 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
874 01:24:22.051096 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
875 01:24:22.057742 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:24:22.061948 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:24:22.064986 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 01:24:22.071372 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 01:24:22.074830 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 01:24:22.077999 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
881 01:24:22.084372 0 11 8 | B1->B0 | 2a2a 3f3f | 1 0 | (0 0) (0 0)
882 01:24:22.088024 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
883 01:24:22.091824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 01:24:22.097922 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 01:24:22.100946 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 01:24:22.104635 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 01:24:22.111497 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 01:24:22.114566 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 01:24:22.117765 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
890 01:24:22.124678 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 01:24:22.127729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 01:24:22.131297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 01:24:22.138465 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 01:24:22.140849 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 01:24:22.144324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 01:24:22.151087 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 01:24:22.154622 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 01:24:22.157659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 01:24:22.164404 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 01:24:22.167372 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 01:24:22.171667 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 01:24:22.177794 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 01:24:22.181139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 01:24:22.183866 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 01:24:22.190897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 01:24:22.190980 Total UI for P1: 0, mck2ui 16
907 01:24:22.194143 best dqsien dly found for B0: ( 0, 14, 4)
908 01:24:22.200977 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
909 01:24:22.204077 Total UI for P1: 0, mck2ui 16
910 01:24:22.207678 best dqsien dly found for B1: ( 0, 14, 8)
911 01:24:22.210788 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
912 01:24:22.214280 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 01:24:22.214363
914 01:24:22.217279 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
915 01:24:22.220548 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 01:24:22.224058 [Gating] SW calibration Done
917 01:24:22.224142 ==
918 01:24:22.227742 Dram Type= 6, Freq= 0, CH_0, rank 0
919 01:24:22.230839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 01:24:22.230937 ==
921 01:24:22.234533 RX Vref Scan: 0
922 01:24:22.234616
923 01:24:22.234681 RX Vref 0 -> 0, step: 1
924 01:24:22.234742
925 01:24:22.238050 RX Delay -130 -> 252, step: 16
926 01:24:22.241302 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 01:24:22.244891 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 01:24:22.251882 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 01:24:22.254723 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 01:24:22.258115 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
931 01:24:22.261404 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 01:24:22.264724 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
933 01:24:22.271382 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
934 01:24:22.274984 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
935 01:24:22.278141 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
936 01:24:22.281511 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
937 01:24:22.284717 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 01:24:22.291377 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
939 01:24:22.294932 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 01:24:22.298350 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 01:24:22.301562 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 01:24:22.301636 ==
943 01:24:22.304740 Dram Type= 6, Freq= 0, CH_0, rank 0
944 01:24:22.311471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 01:24:22.311549 ==
946 01:24:22.311616 DQS Delay:
947 01:24:22.314530 DQS0 = 0, DQS1 = 0
948 01:24:22.314600 DQM Delay:
949 01:24:22.314661 DQM0 = 88, DQM1 = 76
950 01:24:22.318513 DQ Delay:
951 01:24:22.321240 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 01:24:22.324774 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
953 01:24:22.328627 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
954 01:24:22.331478 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 01:24:22.331547
956 01:24:22.331606
957 01:24:22.331666 ==
958 01:24:22.334749 Dram Type= 6, Freq= 0, CH_0, rank 0
959 01:24:22.338201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 01:24:22.338275 ==
961 01:24:22.338335
962 01:24:22.338391
963 01:24:22.341352 TX Vref Scan disable
964 01:24:22.344586 == TX Byte 0 ==
965 01:24:22.347760 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
966 01:24:22.351338 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
967 01:24:22.354547 == TX Byte 1 ==
968 01:24:22.358727 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
969 01:24:22.361793 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
970 01:24:22.361868 ==
971 01:24:22.364415 Dram Type= 6, Freq= 0, CH_0, rank 0
972 01:24:22.367946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 01:24:22.368029 ==
974 01:24:22.382558 TX Vref=22, minBit 4, minWin=26, winSum=437
975 01:24:22.385913 TX Vref=24, minBit 0, minWin=27, winSum=440
976 01:24:22.389184 TX Vref=26, minBit 6, minWin=27, winSum=449
977 01:24:22.392566 TX Vref=28, minBit 1, minWin=27, winSum=449
978 01:24:22.396096 TX Vref=30, minBit 0, minWin=28, winSum=454
979 01:24:22.398938 TX Vref=32, minBit 8, minWin=27, winSum=449
980 01:24:22.406608 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
981 01:24:22.406682
982 01:24:22.409251 Final TX Range 1 Vref 30
983 01:24:22.409324
984 01:24:22.409384 ==
985 01:24:22.413221 Dram Type= 6, Freq= 0, CH_0, rank 0
986 01:24:22.416088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 01:24:22.416163 ==
988 01:24:22.419051
989 01:24:22.419134
990 01:24:22.419200 TX Vref Scan disable
991 01:24:22.422758 == TX Byte 0 ==
992 01:24:22.426318 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
993 01:24:22.432299 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
994 01:24:22.432381 == TX Byte 1 ==
995 01:24:22.436178 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
996 01:24:22.442380 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
997 01:24:22.442466
998 01:24:22.442531 [DATLAT]
999 01:24:22.442592 Freq=800, CH0 RK0
1000 01:24:22.442651
1001 01:24:22.445585 DATLAT Default: 0xa
1002 01:24:22.445666 0, 0xFFFF, sum = 0
1003 01:24:22.449101 1, 0xFFFF, sum = 0
1004 01:24:22.449184 2, 0xFFFF, sum = 0
1005 01:24:22.452315 3, 0xFFFF, sum = 0
1006 01:24:22.455764 4, 0xFFFF, sum = 0
1007 01:24:22.455848 5, 0xFFFF, sum = 0
1008 01:24:22.458719 6, 0xFFFF, sum = 0
1009 01:24:22.458803 7, 0xFFFF, sum = 0
1010 01:24:22.462722 8, 0xFFFF, sum = 0
1011 01:24:22.462807 9, 0x0, sum = 1
1012 01:24:22.462877 10, 0x0, sum = 2
1013 01:24:22.465718 11, 0x0, sum = 3
1014 01:24:22.465802 12, 0x0, sum = 4
1015 01:24:22.468876 best_step = 10
1016 01:24:22.468958
1017 01:24:22.469023 ==
1018 01:24:22.472759 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 01:24:22.475643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 01:24:22.475726 ==
1021 01:24:22.478839 RX Vref Scan: 1
1022 01:24:22.478922
1023 01:24:22.478987 Set Vref Range= 32 -> 127
1024 01:24:22.482914
1025 01:24:22.483000 RX Vref 32 -> 127, step: 1
1026 01:24:22.483067
1027 01:24:22.485741 RX Delay -111 -> 252, step: 8
1028 01:24:22.485823
1029 01:24:22.488963 Set Vref, RX VrefLevel [Byte0]: 32
1030 01:24:22.492854 [Byte1]: 32
1031 01:24:22.492936
1032 01:24:22.495499 Set Vref, RX VrefLevel [Byte0]: 33
1033 01:24:22.498884 [Byte1]: 33
1034 01:24:22.503129
1035 01:24:22.503210 Set Vref, RX VrefLevel [Byte0]: 34
1036 01:24:22.506571 [Byte1]: 34
1037 01:24:22.510938
1038 01:24:22.511020 Set Vref, RX VrefLevel [Byte0]: 35
1039 01:24:22.514392 [Byte1]: 35
1040 01:24:22.518439
1041 01:24:22.518521 Set Vref, RX VrefLevel [Byte0]: 36
1042 01:24:22.521856 [Byte1]: 36
1043 01:24:22.526262
1044 01:24:22.526343 Set Vref, RX VrefLevel [Byte0]: 37
1045 01:24:22.529700 [Byte1]: 37
1046 01:24:22.534550
1047 01:24:22.534632 Set Vref, RX VrefLevel [Byte0]: 38
1048 01:24:22.537352 [Byte1]: 38
1049 01:24:22.541490
1050 01:24:22.541572 Set Vref, RX VrefLevel [Byte0]: 39
1051 01:24:22.545136 [Byte1]: 39
1052 01:24:22.549195
1053 01:24:22.549276 Set Vref, RX VrefLevel [Byte0]: 40
1054 01:24:22.552880 [Byte1]: 40
1055 01:24:22.557011
1056 01:24:22.557092 Set Vref, RX VrefLevel [Byte0]: 41
1057 01:24:22.560572 [Byte1]: 41
1058 01:24:22.564233
1059 01:24:22.564314 Set Vref, RX VrefLevel [Byte0]: 42
1060 01:24:22.567394 [Byte1]: 42
1061 01:24:22.571910
1062 01:24:22.571993 Set Vref, RX VrefLevel [Byte0]: 43
1063 01:24:22.574881 [Byte1]: 43
1064 01:24:22.579727
1065 01:24:22.579808 Set Vref, RX VrefLevel [Byte0]: 44
1066 01:24:22.582709 [Byte1]: 44
1067 01:24:22.587226
1068 01:24:22.587308 Set Vref, RX VrefLevel [Byte0]: 45
1069 01:24:22.590472 [Byte1]: 45
1070 01:24:22.594948
1071 01:24:22.595030 Set Vref, RX VrefLevel [Byte0]: 46
1072 01:24:22.597881 [Byte1]: 46
1073 01:24:22.602548
1074 01:24:22.602630 Set Vref, RX VrefLevel [Byte0]: 47
1075 01:24:22.605766 [Byte1]: 47
1076 01:24:22.610435
1077 01:24:22.610516 Set Vref, RX VrefLevel [Byte0]: 48
1078 01:24:22.613376 [Byte1]: 48
1079 01:24:22.618234
1080 01:24:22.618315 Set Vref, RX VrefLevel [Byte0]: 49
1081 01:24:22.620869 [Byte1]: 49
1082 01:24:22.625327
1083 01:24:22.625408 Set Vref, RX VrefLevel [Byte0]: 50
1084 01:24:22.629109 [Byte1]: 50
1085 01:24:22.632787
1086 01:24:22.632868 Set Vref, RX VrefLevel [Byte0]: 51
1087 01:24:22.636645 [Byte1]: 51
1088 01:24:22.640796
1089 01:24:22.640876 Set Vref, RX VrefLevel [Byte0]: 52
1090 01:24:22.643757 [Byte1]: 52
1091 01:24:22.648437
1092 01:24:22.648518 Set Vref, RX VrefLevel [Byte0]: 53
1093 01:24:22.651371 [Byte1]: 53
1094 01:24:22.656292
1095 01:24:22.656373 Set Vref, RX VrefLevel [Byte0]: 54
1096 01:24:22.659168 [Byte1]: 54
1097 01:24:22.664013
1098 01:24:22.664095 Set Vref, RX VrefLevel [Byte0]: 55
1099 01:24:22.666955 [Byte1]: 55
1100 01:24:22.671236
1101 01:24:22.671317 Set Vref, RX VrefLevel [Byte0]: 56
1102 01:24:22.674622 [Byte1]: 56
1103 01:24:22.679045
1104 01:24:22.679126 Set Vref, RX VrefLevel [Byte0]: 57
1105 01:24:22.682558 [Byte1]: 57
1106 01:24:22.686657
1107 01:24:22.686738 Set Vref, RX VrefLevel [Byte0]: 58
1108 01:24:22.690393 [Byte1]: 58
1109 01:24:22.694202
1110 01:24:22.694283 Set Vref, RX VrefLevel [Byte0]: 59
1111 01:24:22.697289 [Byte1]: 59
1112 01:24:22.701561
1113 01:24:22.701642 Set Vref, RX VrefLevel [Byte0]: 60
1114 01:24:22.704934 [Byte1]: 60
1115 01:24:22.709501
1116 01:24:22.709579 Set Vref, RX VrefLevel [Byte0]: 61
1117 01:24:22.712719 [Byte1]: 61
1118 01:24:22.716957
1119 01:24:22.717030 Set Vref, RX VrefLevel [Byte0]: 62
1120 01:24:22.720275 [Byte1]: 62
1121 01:24:22.724912
1122 01:24:22.724987 Set Vref, RX VrefLevel [Byte0]: 63
1123 01:24:22.727887 [Byte1]: 63
1124 01:24:22.732585
1125 01:24:22.732658 Set Vref, RX VrefLevel [Byte0]: 64
1126 01:24:22.736021 [Byte1]: 64
1127 01:24:22.739933
1128 01:24:22.740024 Set Vref, RX VrefLevel [Byte0]: 65
1129 01:24:22.743819 [Byte1]: 65
1130 01:24:22.747749
1131 01:24:22.747820 Set Vref, RX VrefLevel [Byte0]: 66
1132 01:24:22.750818 [Byte1]: 66
1133 01:24:22.755545
1134 01:24:22.755619 Set Vref, RX VrefLevel [Byte0]: 67
1135 01:24:22.758606 [Byte1]: 67
1136 01:24:22.762917
1137 01:24:22.762988 Set Vref, RX VrefLevel [Byte0]: 68
1138 01:24:22.766173 [Byte1]: 68
1139 01:24:22.770569
1140 01:24:22.770647 Set Vref, RX VrefLevel [Byte0]: 69
1141 01:24:22.773786 [Byte1]: 69
1142 01:24:22.778301
1143 01:24:22.778374 Set Vref, RX VrefLevel [Byte0]: 70
1144 01:24:22.781347 [Byte1]: 70
1145 01:24:22.786222
1146 01:24:22.786295 Set Vref, RX VrefLevel [Byte0]: 71
1147 01:24:22.789559 [Byte1]: 71
1148 01:24:22.793936
1149 01:24:22.794009 Set Vref, RX VrefLevel [Byte0]: 72
1150 01:24:22.796697 [Byte1]: 72
1151 01:24:22.800947
1152 01:24:22.801018 Set Vref, RX VrefLevel [Byte0]: 73
1153 01:24:22.804789 [Byte1]: 73
1154 01:24:22.808946
1155 01:24:22.809026 Set Vref, RX VrefLevel [Byte0]: 74
1156 01:24:22.812038 [Byte1]: 74
1157 01:24:22.816203
1158 01:24:22.816277 Final RX Vref Byte 0 = 57 to rank0
1159 01:24:22.819886 Final RX Vref Byte 1 = 61 to rank0
1160 01:24:22.822928 Final RX Vref Byte 0 = 57 to rank1
1161 01:24:22.826395 Final RX Vref Byte 1 = 61 to rank1==
1162 01:24:22.829847 Dram Type= 6, Freq= 0, CH_0, rank 0
1163 01:24:22.836181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 01:24:22.836258 ==
1165 01:24:22.836321 DQS Delay:
1166 01:24:22.839579 DQS0 = 0, DQS1 = 0
1167 01:24:22.839645 DQM Delay:
1168 01:24:22.839703 DQM0 = 88, DQM1 = 76
1169 01:24:22.842783 DQ Delay:
1170 01:24:22.846292 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1171 01:24:22.849655 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1172 01:24:22.853015 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
1173 01:24:22.856345 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1174 01:24:22.856420
1175 01:24:22.856482
1176 01:24:22.862902 [DQSOSCAuto] RK0, (LSB)MR18= 0x342d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1177 01:24:22.866366 CH0 RK0: MR19=606, MR18=342D
1178 01:24:22.873272 CH0_RK0: MR19=0x606, MR18=0x342D, DQSOSC=396, MR23=63, INC=94, DEC=62
1179 01:24:22.873355
1180 01:24:22.876056 ----->DramcWriteLeveling(PI) begin...
1181 01:24:22.876138 ==
1182 01:24:22.879529 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 01:24:22.882871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 01:24:22.882953 ==
1185 01:24:22.886354 Write leveling (Byte 0): 32 => 32
1186 01:24:22.889879 Write leveling (Byte 1): 27 => 27
1187 01:24:22.892904 DramcWriteLeveling(PI) end<-----
1188 01:24:22.892987
1189 01:24:22.893052 ==
1190 01:24:22.896716 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 01:24:22.899632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 01:24:22.899717 ==
1193 01:24:22.902571 [Gating] SW mode calibration
1194 01:24:22.909321 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1195 01:24:22.916225 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1196 01:24:22.919124 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1197 01:24:22.967065 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1198 01:24:22.967164 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1199 01:24:22.967276 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 01:24:22.967538 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 01:24:22.967612 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 01:24:22.967673 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 01:24:22.967923 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 01:24:22.968415 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 01:24:22.969146 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 01:24:22.969242 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 01:24:22.969307 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 01:24:22.972639 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 01:24:22.976045 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 01:24:22.982346 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 01:24:22.985769 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 01:24:22.989329 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 01:24:22.995501 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1214 01:24:22.999074 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1215 01:24:23.002657 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 01:24:23.008922 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 01:24:23.012417 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 01:24:23.015441 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 01:24:23.022140 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 01:24:23.025585 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 01:24:23.028745 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1222 01:24:23.035495 0 9 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
1223 01:24:23.038786 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 01:24:23.041874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 01:24:23.048626 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 01:24:23.051925 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 01:24:23.055322 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 01:24:23.061961 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 01:24:23.065063 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
1230 01:24:23.068117 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
1231 01:24:23.075019 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1232 01:24:23.078875 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 01:24:23.081440 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 01:24:23.089291 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 01:24:23.091694 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 01:24:23.095103 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 01:24:23.098335 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
1238 01:24:23.105453 0 11 8 | B1->B0 | 3131 4444 | 0 0 | (1 1) (0 0)
1239 01:24:23.109322 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 01:24:23.112666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 01:24:23.116076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 01:24:23.123338 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 01:24:23.126814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 01:24:23.130281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 01:24:23.133695 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1246 01:24:23.140518 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1247 01:24:23.144214 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 01:24:23.146952 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 01:24:23.153805 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 01:24:23.157377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 01:24:23.160858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 01:24:23.166831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 01:24:23.170311 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 01:24:23.173557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 01:24:23.180288 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 01:24:23.183716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 01:24:23.186945 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 01:24:23.193584 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 01:24:23.196666 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 01:24:23.201172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1261 01:24:23.206722 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1262 01:24:23.209782 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 01:24:23.213925 Total UI for P1: 0, mck2ui 16
1264 01:24:23.216736 best dqsien dly found for B0: ( 0, 14, 2)
1265 01:24:23.220035 Total UI for P1: 0, mck2ui 16
1266 01:24:23.223283 best dqsien dly found for B1: ( 0, 14, 4)
1267 01:24:23.226882 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1268 01:24:23.229721 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1269 01:24:23.229795
1270 01:24:23.233129 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1271 01:24:23.236169 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1272 01:24:23.240674 [Gating] SW calibration Done
1273 01:24:23.240741 ==
1274 01:24:23.243382 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 01:24:23.246620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 01:24:23.246688 ==
1277 01:24:23.249897 RX Vref Scan: 0
1278 01:24:23.249965
1279 01:24:23.252848 RX Vref 0 -> 0, step: 1
1280 01:24:23.252914
1281 01:24:23.256313 RX Delay -130 -> 252, step: 16
1282 01:24:23.260292 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1283 01:24:23.262933 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1284 01:24:23.266349 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1285 01:24:23.269699 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1286 01:24:23.277044 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1287 01:24:23.279623 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1288 01:24:23.282872 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1289 01:24:23.286244 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1290 01:24:23.289646 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1291 01:24:23.293214 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1292 01:24:23.300067 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1293 01:24:23.303274 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1294 01:24:23.306869 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1295 01:24:23.310040 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1296 01:24:23.316321 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1297 01:24:23.319573 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1298 01:24:23.319656 ==
1299 01:24:23.323022 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 01:24:23.326237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 01:24:23.326319 ==
1302 01:24:23.326385 DQS Delay:
1303 01:24:23.329466 DQS0 = 0, DQS1 = 0
1304 01:24:23.329547 DQM Delay:
1305 01:24:23.333190 DQM0 = 86, DQM1 = 78
1306 01:24:23.333272 DQ Delay:
1307 01:24:23.336108 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1308 01:24:23.339530 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1309 01:24:23.343418 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1310 01:24:23.346253 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1311 01:24:23.346350
1312 01:24:23.346415
1313 01:24:23.346475 ==
1314 01:24:23.350086 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 01:24:23.352435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 01:24:23.355712 ==
1317 01:24:23.355819
1318 01:24:23.355935
1319 01:24:23.356013 TX Vref Scan disable
1320 01:24:23.359189 == TX Byte 0 ==
1321 01:24:23.362564 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1322 01:24:23.369092 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1323 01:24:23.369176 == TX Byte 1 ==
1324 01:24:23.372654 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1325 01:24:23.375976 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1326 01:24:23.379104 ==
1327 01:24:23.382502 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 01:24:23.385999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 01:24:23.386084 ==
1330 01:24:23.398541 TX Vref=22, minBit 0, minWin=27, winSum=441
1331 01:24:23.401918 TX Vref=24, minBit 1, minWin=27, winSum=443
1332 01:24:23.405756 TX Vref=26, minBit 1, minWin=27, winSum=445
1333 01:24:23.408572 TX Vref=28, minBit 9, minWin=27, winSum=449
1334 01:24:23.412038 TX Vref=30, minBit 1, minWin=27, winSum=451
1335 01:24:23.418561 TX Vref=32, minBit 0, minWin=28, winSum=451
1336 01:24:23.422057 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1337 01:24:23.422140
1338 01:24:23.425446 Final TX Range 1 Vref 32
1339 01:24:23.425529
1340 01:24:23.425595 ==
1341 01:24:23.428748 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 01:24:23.431893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 01:24:23.432003 ==
1344 01:24:23.435014
1345 01:24:23.435121
1346 01:24:23.435215 TX Vref Scan disable
1347 01:24:23.438585 == TX Byte 0 ==
1348 01:24:23.442259 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1349 01:24:23.448983 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1350 01:24:23.449069 == TX Byte 1 ==
1351 01:24:23.452033 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1352 01:24:23.459084 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1353 01:24:23.459167
1354 01:24:23.459232 [DATLAT]
1355 01:24:23.459292 Freq=800, CH0 RK1
1356 01:24:23.459351
1357 01:24:23.461788 DATLAT Default: 0xa
1358 01:24:23.461869 0, 0xFFFF, sum = 0
1359 01:24:23.465517 1, 0xFFFF, sum = 0
1360 01:24:23.468393 2, 0xFFFF, sum = 0
1361 01:24:23.468475 3, 0xFFFF, sum = 0
1362 01:24:23.471765 4, 0xFFFF, sum = 0
1363 01:24:23.471876 5, 0xFFFF, sum = 0
1364 01:24:23.475332 6, 0xFFFF, sum = 0
1365 01:24:23.475414 7, 0xFFFF, sum = 0
1366 01:24:23.478224 8, 0xFFFF, sum = 0
1367 01:24:23.478323 9, 0x0, sum = 1
1368 01:24:23.482088 10, 0x0, sum = 2
1369 01:24:23.482166 11, 0x0, sum = 3
1370 01:24:23.482229 12, 0x0, sum = 4
1371 01:24:23.485029 best_step = 10
1372 01:24:23.485101
1373 01:24:23.485161 ==
1374 01:24:23.488582 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 01:24:23.491647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 01:24:23.491751 ==
1377 01:24:23.495779 RX Vref Scan: 0
1378 01:24:23.495869
1379 01:24:23.495969 RX Vref 0 -> 0, step: 1
1380 01:24:23.498783
1381 01:24:23.498854 RX Delay -95 -> 252, step: 8
1382 01:24:23.505562 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1383 01:24:23.508478 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1384 01:24:23.511817 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1385 01:24:23.515460 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1386 01:24:23.518795 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1387 01:24:23.525463 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1388 01:24:23.529002 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1389 01:24:23.531998 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1390 01:24:23.535066 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1391 01:24:23.538511 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1392 01:24:23.545156 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1393 01:24:23.548533 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1394 01:24:23.552177 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1395 01:24:23.555350 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1396 01:24:23.562090 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1397 01:24:23.565028 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1398 01:24:23.565131 ==
1399 01:24:23.568431 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 01:24:23.571835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 01:24:23.571969 ==
1402 01:24:23.572033 DQS Delay:
1403 01:24:23.575382 DQS0 = 0, DQS1 = 0
1404 01:24:23.575481 DQM Delay:
1405 01:24:23.578611 DQM0 = 86, DQM1 = 77
1406 01:24:23.578709 DQ Delay:
1407 01:24:23.581921 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1408 01:24:23.585265 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1409 01:24:23.588500 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1410 01:24:23.591496 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1411 01:24:23.591594
1412 01:24:23.591696
1413 01:24:23.601670 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1414 01:24:23.601772 CH0 RK1: MR19=606, MR18=2E2A
1415 01:24:23.608142 CH0_RK1: MR19=0x606, MR18=0x2E2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1416 01:24:23.611651 [RxdqsGatingPostProcess] freq 800
1417 01:24:23.619278 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1418 01:24:23.622019 Pre-setting of DQS Precalculation
1419 01:24:23.624903 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1420 01:24:23.624975 ==
1421 01:24:23.628185 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 01:24:23.634453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 01:24:23.634561 ==
1424 01:24:23.637924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 01:24:23.644302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 01:24:23.653589 [CA 0] Center 36 (6~67) winsize 62
1427 01:24:23.657119 [CA 1] Center 37 (6~68) winsize 63
1428 01:24:23.660378 [CA 2] Center 35 (5~65) winsize 61
1429 01:24:23.663728 [CA 3] Center 34 (4~65) winsize 62
1430 01:24:23.666950 [CA 4] Center 34 (4~65) winsize 62
1431 01:24:23.670537 [CA 5] Center 34 (3~65) winsize 63
1432 01:24:23.670644
1433 01:24:23.673588 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1434 01:24:23.673663
1435 01:24:23.677148 [CATrainingPosCal] consider 1 rank data
1436 01:24:23.680188 u2DelayCellTimex100 = 270/100 ps
1437 01:24:23.683880 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1438 01:24:23.690726 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1439 01:24:23.693631 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1440 01:24:23.696967 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1441 01:24:23.700812 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 01:24:23.703706 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1443 01:24:23.703803
1444 01:24:23.706762 CA PerBit enable=1, Macro0, CA PI delay=34
1445 01:24:23.706843
1446 01:24:23.710243 [CBTSetCACLKResult] CA Dly = 34
1447 01:24:23.710324 CS Dly: 4 (0~35)
1448 01:24:23.713867 ==
1449 01:24:23.713949 Dram Type= 6, Freq= 0, CH_1, rank 1
1450 01:24:23.720219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 01:24:23.720302 ==
1452 01:24:23.723609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 01:24:23.729997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 01:24:23.739918 [CA 0] Center 36 (6~67) winsize 62
1455 01:24:23.743469 [CA 1] Center 37 (6~68) winsize 63
1456 01:24:23.746827 [CA 2] Center 34 (4~65) winsize 62
1457 01:24:23.749856 [CA 3] Center 33 (3~64) winsize 62
1458 01:24:23.753619 [CA 4] Center 34 (3~65) winsize 63
1459 01:24:23.756244 [CA 5] Center 34 (3~65) winsize 63
1460 01:24:23.756327
1461 01:24:23.760091 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 01:24:23.760173
1463 01:24:23.762754 [CATrainingPosCal] consider 2 rank data
1464 01:24:23.766021 u2DelayCellTimex100 = 270/100 ps
1465 01:24:23.769336 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 01:24:23.773662 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1467 01:24:23.776529 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1468 01:24:23.780742 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1469 01:24:23.784099 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 01:24:23.788232 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1471 01:24:23.788315
1472 01:24:23.795283 CA PerBit enable=1, Macro0, CA PI delay=34
1473 01:24:23.795391
1474 01:24:23.795485 [CBTSetCACLKResult] CA Dly = 34
1475 01:24:23.798528 CS Dly: 5 (0~37)
1476 01:24:23.798610
1477 01:24:23.802190 ----->DramcWriteLeveling(PI) begin...
1478 01:24:23.802273 ==
1479 01:24:23.806212 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 01:24:23.809455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1481 01:24:23.809538 ==
1482 01:24:23.812433 Write leveling (Byte 0): 26 => 26
1483 01:24:23.816053 Write leveling (Byte 1): 27 => 27
1484 01:24:23.819741 DramcWriteLeveling(PI) end<-----
1485 01:24:23.819848
1486 01:24:23.819975 ==
1487 01:24:23.823005 Dram Type= 6, Freq= 0, CH_1, rank 0
1488 01:24:23.826098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1489 01:24:23.826191 ==
1490 01:24:23.829393 [Gating] SW mode calibration
1491 01:24:23.835679 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1492 01:24:23.842300 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1493 01:24:23.845744 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1494 01:24:23.848941 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1495 01:24:23.855833 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1496 01:24:23.858985 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 01:24:23.862448 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 01:24:23.869249 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 01:24:23.872178 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 01:24:23.875440 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 01:24:23.882285 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 01:24:23.885311 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 01:24:23.888892 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 01:24:23.895739 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 01:24:23.898878 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 01:24:23.901962 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 01:24:23.909029 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 01:24:23.912058 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1509 01:24:23.915601 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 01:24:23.919098 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1511 01:24:23.925456 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 01:24:23.929190 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 01:24:23.932161 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 01:24:23.939301 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 01:24:23.941834 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 01:24:23.945761 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 01:24:23.951818 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 01:24:23.955603 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 01:24:23.958964 0 9 8 | B1->B0 | 3131 3232 | 0 1 | (0 0) (1 1)
1520 01:24:23.965335 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 01:24:23.969176 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 01:24:23.971949 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 01:24:23.978305 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 01:24:23.982072 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 01:24:23.985081 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 01:24:23.991423 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
1527 01:24:23.995208 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1528 01:24:23.998237 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:24:24.004826 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:24:24.008053 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:24:24.011652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 01:24:24.018012 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:24:24.021319 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 01:24:24.024876 0 11 4 | B1->B0 | 2626 3030 | 0 1 | (0 0) (0 0)
1535 01:24:24.031490 0 11 8 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
1536 01:24:24.035420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 01:24:24.038292 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 01:24:24.045115 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 01:24:24.048289 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 01:24:24.051462 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 01:24:24.057829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 01:24:24.061145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1543 01:24:24.064706 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 01:24:24.073888 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 01:24:24.074403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 01:24:24.078249 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 01:24:24.084528 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 01:24:24.088427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 01:24:24.091243 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 01:24:24.094523 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 01:24:24.100983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 01:24:24.104337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 01:24:24.108493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 01:24:24.114666 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 01:24:24.118550 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 01:24:24.122061 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 01:24:24.127728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 01:24:24.130918 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1559 01:24:24.134393 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 01:24:24.137375 Total UI for P1: 0, mck2ui 16
1561 01:24:24.140773 best dqsien dly found for B0: ( 0, 14, 4)
1562 01:24:24.144518 Total UI for P1: 0, mck2ui 16
1563 01:24:24.147425 best dqsien dly found for B1: ( 0, 14, 6)
1564 01:24:24.150897 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1565 01:24:24.154342 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1566 01:24:24.154440
1567 01:24:24.160873 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1568 01:24:24.164984 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1569 01:24:24.165065 [Gating] SW calibration Done
1570 01:24:24.168145 ==
1571 01:24:24.170911 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 01:24:24.173979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 01:24:24.174054 ==
1574 01:24:24.174135 RX Vref Scan: 0
1575 01:24:24.174215
1576 01:24:24.177378 RX Vref 0 -> 0, step: 1
1577 01:24:24.177452
1578 01:24:24.180768 RX Delay -130 -> 252, step: 16
1579 01:24:24.184343 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1580 01:24:24.187221 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1581 01:24:24.194367 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1582 01:24:24.197524 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1583 01:24:24.201011 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1584 01:24:24.203893 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1585 01:24:24.207499 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1586 01:24:24.213935 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1587 01:24:24.217145 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1588 01:24:24.220485 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1589 01:24:24.223823 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1590 01:24:24.227003 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1591 01:24:24.233964 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1592 01:24:24.236970 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1593 01:24:24.240865 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1594 01:24:24.243621 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1595 01:24:24.243703 ==
1596 01:24:24.247043 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 01:24:24.253803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 01:24:24.253883 ==
1599 01:24:24.253969 DQS Delay:
1600 01:24:24.256724 DQS0 = 0, DQS1 = 0
1601 01:24:24.256806 DQM Delay:
1602 01:24:24.256891 DQM0 = 85, DQM1 = 78
1603 01:24:24.260456 DQ Delay:
1604 01:24:24.263596 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1605 01:24:24.267415 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =77
1606 01:24:24.269809 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1607 01:24:24.273709 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1608 01:24:24.273795
1609 01:24:24.273877
1610 01:24:24.273954 ==
1611 01:24:24.276711 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 01:24:24.279837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 01:24:24.279973 ==
1614 01:24:24.280061
1615 01:24:24.280140
1616 01:24:24.283403 TX Vref Scan disable
1617 01:24:24.286631 == TX Byte 0 ==
1618 01:24:24.290489 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 01:24:24.293299 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 01:24:24.296471 == TX Byte 1 ==
1621 01:24:24.299958 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1622 01:24:24.303124 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1623 01:24:24.303202 ==
1624 01:24:24.306465 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 01:24:24.310206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 01:24:24.313064 ==
1627 01:24:24.324465 TX Vref=22, minBit 2, minWin=26, winSum=442
1628 01:24:24.327719 TX Vref=24, minBit 1, minWin=27, winSum=447
1629 01:24:24.330854 TX Vref=26, minBit 4, minWin=27, winSum=452
1630 01:24:24.334256 TX Vref=28, minBit 4, minWin=27, winSum=453
1631 01:24:24.338046 TX Vref=30, minBit 0, minWin=28, winSum=456
1632 01:24:24.340994 TX Vref=32, minBit 5, minWin=27, winSum=454
1633 01:24:24.347704 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1634 01:24:24.347809
1635 01:24:24.351460 Final TX Range 1 Vref 30
1636 01:24:24.351559
1637 01:24:24.351652 ==
1638 01:24:24.355457 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 01:24:24.358427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 01:24:24.358531 ==
1641 01:24:24.358623
1642 01:24:24.358714
1643 01:24:24.361695 TX Vref Scan disable
1644 01:24:24.364999 == TX Byte 0 ==
1645 01:24:24.368483 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1646 01:24:24.372230 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1647 01:24:24.375322 == TX Byte 1 ==
1648 01:24:24.378108 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1649 01:24:24.381583 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1650 01:24:24.381683
1651 01:24:24.384934 [DATLAT]
1652 01:24:24.385025 Freq=800, CH1 RK0
1653 01:24:24.385088
1654 01:24:24.388492 DATLAT Default: 0xa
1655 01:24:24.388565 0, 0xFFFF, sum = 0
1656 01:24:24.391577 1, 0xFFFF, sum = 0
1657 01:24:24.391681 2, 0xFFFF, sum = 0
1658 01:24:24.394893 3, 0xFFFF, sum = 0
1659 01:24:24.394995 4, 0xFFFF, sum = 0
1660 01:24:24.398080 5, 0xFFFF, sum = 0
1661 01:24:24.398197 6, 0xFFFF, sum = 0
1662 01:24:24.401542 7, 0xFFFF, sum = 0
1663 01:24:24.401635 8, 0xFFFF, sum = 0
1664 01:24:24.405140 9, 0x0, sum = 1
1665 01:24:24.405213 10, 0x0, sum = 2
1666 01:24:24.408220 11, 0x0, sum = 3
1667 01:24:24.408297 12, 0x0, sum = 4
1668 01:24:24.411835 best_step = 10
1669 01:24:24.411955
1670 01:24:24.412043 ==
1671 01:24:24.415077 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 01:24:24.417965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1673 01:24:24.418040 ==
1674 01:24:24.421700 RX Vref Scan: 1
1675 01:24:24.421799
1676 01:24:24.421887 Set Vref Range= 32 -> 127
1677 01:24:24.421974
1678 01:24:24.425051 RX Vref 32 -> 127, step: 1
1679 01:24:24.425129
1680 01:24:24.428159 RX Delay -95 -> 252, step: 8
1681 01:24:24.428235
1682 01:24:24.431497 Set Vref, RX VrefLevel [Byte0]: 32
1683 01:24:24.434676 [Byte1]: 32
1684 01:24:24.434774
1685 01:24:24.438235 Set Vref, RX VrefLevel [Byte0]: 33
1686 01:24:24.441451 [Byte1]: 33
1687 01:24:24.441550
1688 01:24:24.444707 Set Vref, RX VrefLevel [Byte0]: 34
1689 01:24:24.448122 [Byte1]: 34
1690 01:24:24.452201
1691 01:24:24.452294 Set Vref, RX VrefLevel [Byte0]: 35
1692 01:24:24.455843 [Byte1]: 35
1693 01:24:24.459727
1694 01:24:24.459825 Set Vref, RX VrefLevel [Byte0]: 36
1695 01:24:24.463218 [Byte1]: 36
1696 01:24:24.467416
1697 01:24:24.467516 Set Vref, RX VrefLevel [Byte0]: 37
1698 01:24:24.470979 [Byte1]: 37
1699 01:24:24.474910
1700 01:24:24.474985 Set Vref, RX VrefLevel [Byte0]: 38
1701 01:24:24.478324 [Byte1]: 38
1702 01:24:24.482342
1703 01:24:24.482445 Set Vref, RX VrefLevel [Byte0]: 39
1704 01:24:24.486245 [Byte1]: 39
1705 01:24:24.490255
1706 01:24:24.490328 Set Vref, RX VrefLevel [Byte0]: 40
1707 01:24:24.493704 [Byte1]: 40
1708 01:24:24.497886
1709 01:24:24.497963 Set Vref, RX VrefLevel [Byte0]: 41
1710 01:24:24.501182 [Byte1]: 41
1711 01:24:24.505949
1712 01:24:24.506024 Set Vref, RX VrefLevel [Byte0]: 42
1713 01:24:24.508797 [Byte1]: 42
1714 01:24:24.512788
1715 01:24:24.512860 Set Vref, RX VrefLevel [Byte0]: 43
1716 01:24:24.516527 [Byte1]: 43
1717 01:24:24.521219
1718 01:24:24.524228 Set Vref, RX VrefLevel [Byte0]: 44
1719 01:24:24.527167 [Byte1]: 44
1720 01:24:24.527239
1721 01:24:24.530555 Set Vref, RX VrefLevel [Byte0]: 45
1722 01:24:24.533693 [Byte1]: 45
1723 01:24:24.533793
1724 01:24:24.537254 Set Vref, RX VrefLevel [Byte0]: 46
1725 01:24:24.540923 [Byte1]: 46
1726 01:24:24.540997
1727 01:24:24.543614 Set Vref, RX VrefLevel [Byte0]: 47
1728 01:24:24.547160 [Byte1]: 47
1729 01:24:24.551276
1730 01:24:24.551375 Set Vref, RX VrefLevel [Byte0]: 48
1731 01:24:24.554189 [Byte1]: 48
1732 01:24:24.558656
1733 01:24:24.558733 Set Vref, RX VrefLevel [Byte0]: 49
1734 01:24:24.561618 [Byte1]: 49
1735 01:24:24.566105
1736 01:24:24.566182 Set Vref, RX VrefLevel [Byte0]: 50
1737 01:24:24.569419 [Byte1]: 50
1738 01:24:24.573808
1739 01:24:24.573906 Set Vref, RX VrefLevel [Byte0]: 51
1740 01:24:24.576989 [Byte1]: 51
1741 01:24:24.581575
1742 01:24:24.581670 Set Vref, RX VrefLevel [Byte0]: 52
1743 01:24:24.584827 [Byte1]: 52
1744 01:24:24.588937
1745 01:24:24.589038 Set Vref, RX VrefLevel [Byte0]: 53
1746 01:24:24.592244 [Byte1]: 53
1747 01:24:24.596494
1748 01:24:24.596567 Set Vref, RX VrefLevel [Byte0]: 54
1749 01:24:24.599703 [Byte1]: 54
1750 01:24:24.604153
1751 01:24:24.604229 Set Vref, RX VrefLevel [Byte0]: 55
1752 01:24:24.607692 [Byte1]: 55
1753 01:24:24.611720
1754 01:24:24.611814 Set Vref, RX VrefLevel [Byte0]: 56
1755 01:24:24.614726 [Byte1]: 56
1756 01:24:24.619098
1757 01:24:24.622400 Set Vref, RX VrefLevel [Byte0]: 57
1758 01:24:24.625813 [Byte1]: 57
1759 01:24:24.625901
1760 01:24:24.628866 Set Vref, RX VrefLevel [Byte0]: 58
1761 01:24:24.632172 [Byte1]: 58
1762 01:24:24.632244
1763 01:24:24.635418 Set Vref, RX VrefLevel [Byte0]: 59
1764 01:24:24.639070 [Byte1]: 59
1765 01:24:24.639142
1766 01:24:24.642535 Set Vref, RX VrefLevel [Byte0]: 60
1767 01:24:24.645614 [Byte1]: 60
1768 01:24:24.649898
1769 01:24:24.649967 Set Vref, RX VrefLevel [Byte0]: 61
1770 01:24:24.652763 [Byte1]: 61
1771 01:24:24.657547
1772 01:24:24.657647 Set Vref, RX VrefLevel [Byte0]: 62
1773 01:24:24.660663 [Byte1]: 62
1774 01:24:24.664902
1775 01:24:24.664974 Set Vref, RX VrefLevel [Byte0]: 63
1776 01:24:24.668886 [Byte1]: 63
1777 01:24:24.672313
1778 01:24:24.672396 Set Vref, RX VrefLevel [Byte0]: 64
1779 01:24:24.675515 [Byte1]: 64
1780 01:24:24.680126
1781 01:24:24.680206 Set Vref, RX VrefLevel [Byte0]: 65
1782 01:24:24.683472 [Byte1]: 65
1783 01:24:24.687446
1784 01:24:24.687524 Set Vref, RX VrefLevel [Byte0]: 66
1785 01:24:24.690935 [Byte1]: 66
1786 01:24:24.695239
1787 01:24:24.695318 Set Vref, RX VrefLevel [Byte0]: 67
1788 01:24:24.698645 [Byte1]: 67
1789 01:24:24.702803
1790 01:24:24.702888 Set Vref, RX VrefLevel [Byte0]: 68
1791 01:24:24.706053 [Byte1]: 68
1792 01:24:24.710627
1793 01:24:24.710707 Set Vref, RX VrefLevel [Byte0]: 69
1794 01:24:24.713556 [Byte1]: 69
1795 01:24:24.718113
1796 01:24:24.721343 Set Vref, RX VrefLevel [Byte0]: 70
1797 01:24:24.724478 [Byte1]: 70
1798 01:24:24.724558
1799 01:24:24.727555 Set Vref, RX VrefLevel [Byte0]: 71
1800 01:24:24.731106 [Byte1]: 71
1801 01:24:24.731187
1802 01:24:24.734248 Set Vref, RX VrefLevel [Byte0]: 72
1803 01:24:24.738585 [Byte1]: 72
1804 01:24:24.738701
1805 01:24:24.741383 Set Vref, RX VrefLevel [Byte0]: 73
1806 01:24:24.744334 [Byte1]: 73
1807 01:24:24.748385
1808 01:24:24.748460 Set Vref, RX VrefLevel [Byte0]: 74
1809 01:24:24.751960 [Byte1]: 74
1810 01:24:24.755885
1811 01:24:24.756030 Set Vref, RX VrefLevel [Byte0]: 75
1812 01:24:24.759423 [Byte1]: 75
1813 01:24:24.763594
1814 01:24:24.763667 Final RX Vref Byte 0 = 56 to rank0
1815 01:24:24.766915 Final RX Vref Byte 1 = 57 to rank0
1816 01:24:24.770368 Final RX Vref Byte 0 = 56 to rank1
1817 01:24:24.773428 Final RX Vref Byte 1 = 57 to rank1==
1818 01:24:24.777792 Dram Type= 6, Freq= 0, CH_1, rank 0
1819 01:24:24.783725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 01:24:24.783828 ==
1821 01:24:24.783955 DQS Delay:
1822 01:24:24.784044 DQS0 = 0, DQS1 = 0
1823 01:24:24.787227 DQM Delay:
1824 01:24:24.787297 DQM0 = 86, DQM1 = 80
1825 01:24:24.790323 DQ Delay:
1826 01:24:24.793358 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1827 01:24:24.796976 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =84
1828 01:24:24.797076 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1829 01:24:24.803329 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1830 01:24:24.803403
1831 01:24:24.803465
1832 01:24:24.810619 [DQSOSCAuto] RK0, (LSB)MR18= 0x172a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1833 01:24:24.813838 CH1 RK0: MR19=606, MR18=172A
1834 01:24:24.820102 CH1_RK0: MR19=0x606, MR18=0x172A, DQSOSC=399, MR23=63, INC=92, DEC=61
1835 01:24:24.820179
1836 01:24:24.823323 ----->DramcWriteLeveling(PI) begin...
1837 01:24:24.823400 ==
1838 01:24:24.826964 Dram Type= 6, Freq= 0, CH_1, rank 1
1839 01:24:24.829804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 01:24:24.829876 ==
1841 01:24:24.833123 Write leveling (Byte 0): 26 => 26
1842 01:24:24.836803 Write leveling (Byte 1): 30 => 30
1843 01:24:24.839988 DramcWriteLeveling(PI) end<-----
1844 01:24:24.840061
1845 01:24:24.840128 ==
1846 01:24:24.843225 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 01:24:24.846401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 01:24:24.846482 ==
1849 01:24:24.850009 [Gating] SW mode calibration
1850 01:24:24.856345 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1851 01:24:24.862881 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1852 01:24:24.866432 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1853 01:24:24.873149 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 01:24:24.876272 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 01:24:24.879682 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 01:24:24.886565 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 01:24:24.889568 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 01:24:24.892583 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 01:24:24.896635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 01:24:24.902950 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 01:24:24.906308 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 01:24:24.909377 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 01:24:24.916089 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 01:24:24.919203 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 01:24:24.922707 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 01:24:24.929521 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 01:24:24.932654 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 01:24:24.936772 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1869 01:24:24.942848 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1870 01:24:24.946110 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 01:24:24.949835 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 01:24:24.956183 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 01:24:24.959435 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 01:24:24.962463 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 01:24:24.969495 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 01:24:24.972794 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 01:24:24.975915 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1878 01:24:24.982676 0 9 8 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
1879 01:24:24.985730 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 01:24:24.989343 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 01:24:24.995885 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 01:24:24.999289 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 01:24:25.002292 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 01:24:25.009150 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1885 01:24:25.012152 0 10 4 | B1->B0 | 3030 2626 | 1 0 | (1 1) (0 0)
1886 01:24:25.015807 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1887 01:24:25.019131 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 01:24:25.025992 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 01:24:25.029092 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 01:24:25.032562 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 01:24:25.038881 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 01:24:25.042158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 01:24:25.045374 0 11 4 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
1894 01:24:25.052501 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1895 01:24:25.055831 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 01:24:25.058608 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 01:24:25.066060 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 01:24:25.069133 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 01:24:25.071847 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 01:24:25.079097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1901 01:24:25.082234 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1902 01:24:25.085574 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1903 01:24:25.092032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 01:24:25.095413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 01:24:25.098586 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 01:24:25.105208 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 01:24:25.108452 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 01:24:25.111752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 01:24:25.118606 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 01:24:25.121535 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 01:24:25.125255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 01:24:25.132086 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 01:24:25.135200 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 01:24:25.138513 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 01:24:25.144849 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 01:24:25.148362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1917 01:24:25.151764 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1918 01:24:25.158222 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 01:24:25.158327 Total UI for P1: 0, mck2ui 16
1920 01:24:25.164944 best dqsien dly found for B0: ( 0, 14, 2)
1921 01:24:25.165027 Total UI for P1: 0, mck2ui 16
1922 01:24:25.168159 best dqsien dly found for B1: ( 0, 14, 6)
1923 01:24:25.174946 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1924 01:24:25.178217 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1925 01:24:25.178309
1926 01:24:25.181799 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1927 01:24:25.184948 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1928 01:24:25.188238 [Gating] SW calibration Done
1929 01:24:25.188311 ==
1930 01:24:25.191487 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 01:24:25.195229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 01:24:25.195305 ==
1933 01:24:25.198377 RX Vref Scan: 0
1934 01:24:25.198511
1935 01:24:25.198600 RX Vref 0 -> 0, step: 1
1936 01:24:25.198689
1937 01:24:25.201449 RX Delay -130 -> 252, step: 16
1938 01:24:25.205060 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1939 01:24:25.211189 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1940 01:24:25.214654 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1941 01:24:25.218040 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1942 01:24:25.221270 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1943 01:24:25.225188 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1944 01:24:25.231570 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1945 01:24:25.234750 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1946 01:24:25.237923 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1947 01:24:25.241767 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1948 01:24:25.244777 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1949 01:24:25.251149 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1950 01:24:25.254312 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1951 01:24:25.257797 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1952 01:24:25.260997 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1953 01:24:25.264423 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1954 01:24:25.268367 ==
1955 01:24:25.268449 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 01:24:25.274486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 01:24:25.274568 ==
1958 01:24:25.274664 DQS Delay:
1959 01:24:25.277773 DQS0 = 0, DQS1 = 0
1960 01:24:25.277853 DQM Delay:
1961 01:24:25.281098 DQM0 = 84, DQM1 = 82
1962 01:24:25.281212 DQ Delay:
1963 01:24:25.284839 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1964 01:24:25.287968 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1965 01:24:25.292438 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1966 01:24:25.294544 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1967 01:24:25.294644
1968 01:24:25.294735
1969 01:24:25.294826 ==
1970 01:24:25.298116 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 01:24:25.301167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 01:24:25.301246 ==
1973 01:24:25.301309
1974 01:24:25.301373
1975 01:24:25.304454 TX Vref Scan disable
1976 01:24:25.307771 == TX Byte 0 ==
1977 01:24:25.311441 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1978 01:24:25.314253 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1979 01:24:25.317529 == TX Byte 1 ==
1980 01:24:25.321529 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1981 01:24:25.324771 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1982 01:24:25.324846 ==
1983 01:24:25.327429 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 01:24:25.331168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 01:24:25.334005 ==
1986 01:24:25.345763 TX Vref=22, minBit 1, minWin=27, winSum=444
1987 01:24:25.349083 TX Vref=24, minBit 1, minWin=27, winSum=449
1988 01:24:25.352494 TX Vref=26, minBit 1, minWin=27, winSum=449
1989 01:24:25.355524 TX Vref=28, minBit 0, minWin=28, winSum=456
1990 01:24:25.359991 TX Vref=30, minBit 5, minWin=27, winSum=454
1991 01:24:25.362677 TX Vref=32, minBit 5, minWin=27, winSum=455
1992 01:24:25.369430 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1993 01:24:25.369537
1994 01:24:25.372875 Final TX Range 1 Vref 28
1995 01:24:25.372968
1996 01:24:25.373032 ==
1997 01:24:25.376379 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 01:24:25.379126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 01:24:25.379229 ==
2000 01:24:25.379321
2001 01:24:25.382693
2002 01:24:25.382827 TX Vref Scan disable
2003 01:24:25.385887 == TX Byte 0 ==
2004 01:24:25.389283 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2005 01:24:25.395424 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2006 01:24:25.395504 == TX Byte 1 ==
2007 01:24:25.399646 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2008 01:24:25.405469 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2009 01:24:25.405546
2010 01:24:25.405613 [DATLAT]
2011 01:24:25.405672 Freq=800, CH1 RK1
2012 01:24:25.405730
2013 01:24:25.409098 DATLAT Default: 0xa
2014 01:24:25.409165 0, 0xFFFF, sum = 0
2015 01:24:25.412709 1, 0xFFFF, sum = 0
2016 01:24:25.415334 2, 0xFFFF, sum = 0
2017 01:24:25.415417 3, 0xFFFF, sum = 0
2018 01:24:25.418978 4, 0xFFFF, sum = 0
2019 01:24:25.419051 5, 0xFFFF, sum = 0
2020 01:24:25.422240 6, 0xFFFF, sum = 0
2021 01:24:25.422309 7, 0xFFFF, sum = 0
2022 01:24:25.425463 8, 0xFFFF, sum = 0
2023 01:24:25.425541 9, 0x0, sum = 1
2024 01:24:25.428619 10, 0x0, sum = 2
2025 01:24:25.428695 11, 0x0, sum = 3
2026 01:24:25.428756 12, 0x0, sum = 4
2027 01:24:25.432087 best_step = 10
2028 01:24:25.432177
2029 01:24:25.432265 ==
2030 01:24:25.435284 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 01:24:25.438684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 01:24:25.438757 ==
2033 01:24:25.441972 RX Vref Scan: 0
2034 01:24:25.442045
2035 01:24:25.442105 RX Vref 0 -> 0, step: 1
2036 01:24:25.445124
2037 01:24:25.445194 RX Delay -95 -> 252, step: 8
2038 01:24:25.452212 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2039 01:24:25.456083 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2040 01:24:25.459525 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2041 01:24:25.462237 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2042 01:24:25.466285 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2043 01:24:25.472607 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2044 01:24:25.476193 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2045 01:24:25.478892 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2046 01:24:25.482447 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2047 01:24:25.485399 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2048 01:24:25.491860 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2049 01:24:25.495358 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2050 01:24:25.498572 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2051 01:24:25.502200 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2052 01:24:25.508361 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2053 01:24:25.511818 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2054 01:24:25.511895 ==
2055 01:24:25.515409 Dram Type= 6, Freq= 0, CH_1, rank 1
2056 01:24:25.518458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2057 01:24:25.518536 ==
2058 01:24:25.521642 DQS Delay:
2059 01:24:25.521724 DQS0 = 0, DQS1 = 0
2060 01:24:25.521809 DQM Delay:
2061 01:24:25.525409 DQM0 = 87, DQM1 = 82
2062 01:24:25.525484 DQ Delay:
2063 01:24:25.528616 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2064 01:24:25.531819 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2065 01:24:25.535288 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2066 01:24:25.538694 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2067 01:24:25.538768
2068 01:24:25.538833
2069 01:24:25.548336 [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2070 01:24:25.548415 CH1 RK1: MR19=606, MR18=203C
2071 01:24:25.555078 CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63
2072 01:24:25.558288 [RxdqsGatingPostProcess] freq 800
2073 01:24:25.565013 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2074 01:24:25.568235 Pre-setting of DQS Precalculation
2075 01:24:25.571262 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2076 01:24:25.578551 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2077 01:24:25.588628 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2078 01:24:25.588706
2079 01:24:25.588772
2080 01:24:25.591998 [Calibration Summary] 1600 Mbps
2081 01:24:25.592071 CH 0, Rank 0
2082 01:24:25.594936 SW Impedance : PASS
2083 01:24:25.595011 DUTY Scan : NO K
2084 01:24:25.598368 ZQ Calibration : PASS
2085 01:24:25.601884 Jitter Meter : NO K
2086 01:24:25.601988 CBT Training : PASS
2087 01:24:25.605342 Write leveling : PASS
2088 01:24:25.605411 RX DQS gating : PASS
2089 01:24:25.608149 RX DQ/DQS(RDDQC) : PASS
2090 01:24:25.611690 TX DQ/DQS : PASS
2091 01:24:25.611763 RX DATLAT : PASS
2092 01:24:25.615152 RX DQ/DQS(Engine): PASS
2093 01:24:25.618118 TX OE : NO K
2094 01:24:25.618194 All Pass.
2095 01:24:25.618255
2096 01:24:25.618316 CH 0, Rank 1
2097 01:24:25.621259 SW Impedance : PASS
2098 01:24:25.624580 DUTY Scan : NO K
2099 01:24:25.624655 ZQ Calibration : PASS
2100 01:24:25.628740 Jitter Meter : NO K
2101 01:24:25.631250 CBT Training : PASS
2102 01:24:25.631326 Write leveling : PASS
2103 01:24:25.635208 RX DQS gating : PASS
2104 01:24:25.638066 RX DQ/DQS(RDDQC) : PASS
2105 01:24:25.638133 TX DQ/DQS : PASS
2106 01:24:25.641374 RX DATLAT : PASS
2107 01:24:25.645017 RX DQ/DQS(Engine): PASS
2108 01:24:25.645088 TX OE : NO K
2109 01:24:25.647632 All Pass.
2110 01:24:25.647697
2111 01:24:25.647758 CH 1, Rank 0
2112 01:24:25.651146 SW Impedance : PASS
2113 01:24:25.651214 DUTY Scan : NO K
2114 01:24:25.655507 ZQ Calibration : PASS
2115 01:24:25.658029 Jitter Meter : NO K
2116 01:24:25.658100 CBT Training : PASS
2117 01:24:25.660949 Write leveling : PASS
2118 01:24:25.661015 RX DQS gating : PASS
2119 01:24:25.664176 RX DQ/DQS(RDDQC) : PASS
2120 01:24:25.667705 TX DQ/DQS : PASS
2121 01:24:25.667780 RX DATLAT : PASS
2122 01:24:25.671031 RX DQ/DQS(Engine): PASS
2123 01:24:25.674477 TX OE : NO K
2124 01:24:25.674552 All Pass.
2125 01:24:25.674611
2126 01:24:25.674671 CH 1, Rank 1
2127 01:24:25.678180 SW Impedance : PASS
2128 01:24:25.681216 DUTY Scan : NO K
2129 01:24:25.681288 ZQ Calibration : PASS
2130 01:24:25.684209 Jitter Meter : NO K
2131 01:24:25.687705 CBT Training : PASS
2132 01:24:25.687775 Write leveling : PASS
2133 01:24:25.690777 RX DQS gating : PASS
2134 01:24:25.694102 RX DQ/DQS(RDDQC) : PASS
2135 01:24:25.694168 TX DQ/DQS : PASS
2136 01:24:25.697861 RX DATLAT : PASS
2137 01:24:25.701316 RX DQ/DQS(Engine): PASS
2138 01:24:25.701384 TX OE : NO K
2139 01:24:25.704291 All Pass.
2140 01:24:25.704357
2141 01:24:25.704418 DramC Write-DBI off
2142 01:24:25.707416 PER_BANK_REFRESH: Hybrid Mode
2143 01:24:25.707480 TX_TRACKING: ON
2144 01:24:25.710651 [GetDramInforAfterCalByMRR] Vendor 6.
2145 01:24:25.717438 [GetDramInforAfterCalByMRR] Revision 606.
2146 01:24:25.720894 [GetDramInforAfterCalByMRR] Revision 2 0.
2147 01:24:25.720964 MR0 0x3b3b
2148 01:24:25.721028 MR8 0x5151
2149 01:24:25.724578 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2150 01:24:25.724653
2151 01:24:25.727333 MR0 0x3b3b
2152 01:24:25.727399 MR8 0x5151
2153 01:24:25.730995 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2154 01:24:25.731064
2155 01:24:25.740443 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2156 01:24:25.744038 [FAST_K] Save calibration result to emmc
2157 01:24:25.747360 [FAST_K] Save calibration result to emmc
2158 01:24:25.750947 dram_init: config_dvfs: 1
2159 01:24:25.753670 dramc_set_vcore_voltage set vcore to 662500
2160 01:24:25.758030 Read voltage for 1200, 2
2161 01:24:25.758105 Vio18 = 0
2162 01:24:25.758171 Vcore = 662500
2163 01:24:25.760415 Vdram = 0
2164 01:24:25.760481 Vddq = 0
2165 01:24:25.760540 Vmddr = 0
2166 01:24:25.767002 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2167 01:24:25.770367 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2168 01:24:25.774656 MEM_TYPE=3, freq_sel=15
2169 01:24:25.777151 sv_algorithm_assistance_LP4_1600
2170 01:24:25.780313 ============ PULL DRAM RESETB DOWN ============
2171 01:24:25.783803 ========== PULL DRAM RESETB DOWN end =========
2172 01:24:25.790633 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2173 01:24:25.794248 ===================================
2174 01:24:25.794319 LPDDR4 DRAM CONFIGURATION
2175 01:24:25.797227 ===================================
2176 01:24:25.800874 EX_ROW_EN[0] = 0x0
2177 01:24:25.803606 EX_ROW_EN[1] = 0x0
2178 01:24:25.803675 LP4Y_EN = 0x0
2179 01:24:25.806768 WORK_FSP = 0x0
2180 01:24:25.806835 WL = 0x4
2181 01:24:25.810143 RL = 0x4
2182 01:24:25.810209 BL = 0x2
2183 01:24:25.813873 RPST = 0x0
2184 01:24:25.813943 RD_PRE = 0x0
2185 01:24:25.816871 WR_PRE = 0x1
2186 01:24:25.816943 WR_PST = 0x0
2187 01:24:25.821394 DBI_WR = 0x0
2188 01:24:25.821465 DBI_RD = 0x0
2189 01:24:25.823885 OTF = 0x1
2190 01:24:25.826921 ===================================
2191 01:24:25.830604 ===================================
2192 01:24:25.830671 ANA top config
2193 01:24:25.833485 ===================================
2194 01:24:25.836486 DLL_ASYNC_EN = 0
2195 01:24:25.840156 ALL_SLAVE_EN = 0
2196 01:24:25.843322 NEW_RANK_MODE = 1
2197 01:24:25.843387 DLL_IDLE_MODE = 1
2198 01:24:25.846848 LP45_APHY_COMB_EN = 1
2199 01:24:25.850385 TX_ODT_DIS = 1
2200 01:24:25.853428 NEW_8X_MODE = 1
2201 01:24:25.856800 ===================================
2202 01:24:25.860097 ===================================
2203 01:24:25.863168 data_rate = 2400
2204 01:24:25.863244 CKR = 1
2205 01:24:25.867236 DQ_P2S_RATIO = 8
2206 01:24:25.870067 ===================================
2207 01:24:25.873882 CA_P2S_RATIO = 8
2208 01:24:25.876863 DQ_CA_OPEN = 0
2209 01:24:25.879820 DQ_SEMI_OPEN = 0
2210 01:24:25.883122 CA_SEMI_OPEN = 0
2211 01:24:25.883197 CA_FULL_RATE = 0
2212 01:24:25.886651 DQ_CKDIV4_EN = 0
2213 01:24:25.890135 CA_CKDIV4_EN = 0
2214 01:24:25.893144 CA_PREDIV_EN = 0
2215 01:24:25.896891 PH8_DLY = 17
2216 01:24:25.899803 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2217 01:24:25.899908 DQ_AAMCK_DIV = 4
2218 01:24:25.903252 CA_AAMCK_DIV = 4
2219 01:24:25.906667 CA_ADMCK_DIV = 4
2220 01:24:25.910271 DQ_TRACK_CA_EN = 0
2221 01:24:25.913945 CA_PICK = 1200
2222 01:24:25.916510 CA_MCKIO = 1200
2223 01:24:25.920136 MCKIO_SEMI = 0
2224 01:24:25.920209 PLL_FREQ = 2366
2225 01:24:25.923377 DQ_UI_PI_RATIO = 32
2226 01:24:25.926598 CA_UI_PI_RATIO = 0
2227 01:24:25.930071 ===================================
2228 01:24:25.933461 ===================================
2229 01:24:25.936494 memory_type:LPDDR4
2230 01:24:25.936591 GP_NUM : 10
2231 01:24:25.940245 SRAM_EN : 1
2232 01:24:25.942800 MD32_EN : 0
2233 01:24:25.946398 ===================================
2234 01:24:25.946469 [ANA_INIT] >>>>>>>>>>>>>>
2235 01:24:25.949934 <<<<<< [CONFIGURE PHASE]: ANA_TX
2236 01:24:25.952865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2237 01:24:25.956048 ===================================
2238 01:24:25.959312 data_rate = 2400,PCW = 0X5b00
2239 01:24:25.963049 ===================================
2240 01:24:25.966136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2241 01:24:25.973060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2242 01:24:25.976278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 01:24:25.982714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2244 01:24:25.985952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2245 01:24:25.989406 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2246 01:24:25.993368 [ANA_INIT] flow start
2247 01:24:25.993493 [ANA_INIT] PLL >>>>>>>>
2248 01:24:25.995746 [ANA_INIT] PLL <<<<<<<<
2249 01:24:25.999157 [ANA_INIT] MIDPI >>>>>>>>
2250 01:24:25.999232 [ANA_INIT] MIDPI <<<<<<<<
2251 01:24:26.002635 [ANA_INIT] DLL >>>>>>>>
2252 01:24:26.005730 [ANA_INIT] DLL <<<<<<<<
2253 01:24:26.005800 [ANA_INIT] flow end
2254 01:24:26.012657 ============ LP4 DIFF to SE enter ============
2255 01:24:26.015806 ============ LP4 DIFF to SE exit ============
2256 01:24:26.015931 [ANA_INIT] <<<<<<<<<<<<<
2257 01:24:26.019068 [Flow] Enable top DCM control >>>>>
2258 01:24:26.022472 [Flow] Enable top DCM control <<<<<
2259 01:24:26.026153 Enable DLL master slave shuffle
2260 01:24:26.033393 ==============================================================
2261 01:24:26.035515 Gating Mode config
2262 01:24:26.038895 ==============================================================
2263 01:24:26.042415 Config description:
2264 01:24:26.052257 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2265 01:24:26.058865 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2266 01:24:26.062780 SELPH_MODE 0: By rank 1: By Phase
2267 01:24:26.069001 ==============================================================
2268 01:24:26.072741 GAT_TRACK_EN = 1
2269 01:24:26.075727 RX_GATING_MODE = 2
2270 01:24:26.079044 RX_GATING_TRACK_MODE = 2
2271 01:24:26.079117 SELPH_MODE = 1
2272 01:24:26.082094 PICG_EARLY_EN = 1
2273 01:24:26.085845 VALID_LAT_VALUE = 1
2274 01:24:26.092244 ==============================================================
2275 01:24:26.095612 Enter into Gating configuration >>>>
2276 01:24:26.098990 Exit from Gating configuration <<<<
2277 01:24:26.102029 Enter into DVFS_PRE_config >>>>>
2278 01:24:26.112689 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2279 01:24:26.115678 Exit from DVFS_PRE_config <<<<<
2280 01:24:26.118616 Enter into PICG configuration >>>>
2281 01:24:26.121784 Exit from PICG configuration <<<<
2282 01:24:26.125049 [RX_INPUT] configuration >>>>>
2283 01:24:26.128709 [RX_INPUT] configuration <<<<<
2284 01:24:26.131987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2285 01:24:26.138592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2286 01:24:26.144838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2287 01:24:26.151747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2288 01:24:26.158343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2289 01:24:26.161621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2290 01:24:26.168292 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2291 01:24:26.171689 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2292 01:24:26.175290 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2293 01:24:26.178297 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2294 01:24:26.184788 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2295 01:24:26.188366 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 01:24:26.191316 ===================================
2297 01:24:26.194791 LPDDR4 DRAM CONFIGURATION
2298 01:24:26.198094 ===================================
2299 01:24:26.198177 EX_ROW_EN[0] = 0x0
2300 01:24:26.202066 EX_ROW_EN[1] = 0x0
2301 01:24:26.202149 LP4Y_EN = 0x0
2302 01:24:26.205118 WORK_FSP = 0x0
2303 01:24:26.205202 WL = 0x4
2304 01:24:26.208219 RL = 0x4
2305 01:24:26.208313 BL = 0x2
2306 01:24:26.211608 RPST = 0x0
2307 01:24:26.211681 RD_PRE = 0x0
2308 01:24:26.214850 WR_PRE = 0x1
2309 01:24:26.214923 WR_PST = 0x0
2310 01:24:26.217946 DBI_WR = 0x0
2311 01:24:26.218021 DBI_RD = 0x0
2312 01:24:26.221458 OTF = 0x1
2313 01:24:26.224863 ===================================
2314 01:24:26.228113 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2315 01:24:26.231346 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2316 01:24:26.237672 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2317 01:24:26.241030 ===================================
2318 01:24:26.244752 LPDDR4 DRAM CONFIGURATION
2319 01:24:26.247879 ===================================
2320 01:24:26.247999 EX_ROW_EN[0] = 0x10
2321 01:24:26.250920 EX_ROW_EN[1] = 0x0
2322 01:24:26.250991 LP4Y_EN = 0x0
2323 01:24:26.254952 WORK_FSP = 0x0
2324 01:24:26.255024 WL = 0x4
2325 01:24:26.257636 RL = 0x4
2326 01:24:26.257763 BL = 0x2
2327 01:24:26.261232 RPST = 0x0
2328 01:24:26.261305 RD_PRE = 0x0
2329 01:24:26.264455 WR_PRE = 0x1
2330 01:24:26.264533 WR_PST = 0x0
2331 01:24:26.267477 DBI_WR = 0x0
2332 01:24:26.271173 DBI_RD = 0x0
2333 01:24:26.271241 OTF = 0x1
2334 01:24:26.274346 ===================================
2335 01:24:26.280694 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2336 01:24:26.280772 ==
2337 01:24:26.284493 Dram Type= 6, Freq= 0, CH_0, rank 0
2338 01:24:26.288086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2339 01:24:26.288161 ==
2340 01:24:26.291244 [Duty_Offset_Calibration]
2341 01:24:26.291310 B0:2 B1:0 CA:4
2342 01:24:26.291370
2343 01:24:26.294332 [DutyScan_Calibration_Flow] k_type=0
2344 01:24:26.304120
2345 01:24:26.304217 ==CLK 0==
2346 01:24:26.307391 Final CLK duty delay cell = -4
2347 01:24:26.310881 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2348 01:24:26.314502 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2349 01:24:26.317461 [-4] AVG Duty = 4937%(X100)
2350 01:24:26.317548
2351 01:24:26.320801 CH0 CLK Duty spec in!! Max-Min= 187%
2352 01:24:26.324351 [DutyScan_Calibration_Flow] ====Done====
2353 01:24:26.324465
2354 01:24:26.327590 [DutyScan_Calibration_Flow] k_type=1
2355 01:24:26.343214
2356 01:24:26.343305 ==DQS 0 ==
2357 01:24:26.346480 Final DQS duty delay cell = -4
2358 01:24:26.349757 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2359 01:24:26.352888 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2360 01:24:26.356822 [-4] AVG Duty = 4922%(X100)
2361 01:24:26.356903
2362 01:24:26.356967 ==DQS 1 ==
2363 01:24:26.360051 Final DQS duty delay cell = 0
2364 01:24:26.363186 [0] MAX Duty = 5125%(X100), DQS PI = 50
2365 01:24:26.366093 [0] MIN Duty = 5000%(X100), DQS PI = 0
2366 01:24:26.369331 [0] AVG Duty = 5062%(X100)
2367 01:24:26.369411
2368 01:24:26.372804 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2369 01:24:26.372885
2370 01:24:26.376025 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2371 01:24:26.379121 [DutyScan_Calibration_Flow] ====Done====
2372 01:24:26.379229
2373 01:24:26.383259 [DutyScan_Calibration_Flow] k_type=3
2374 01:24:26.400482
2375 01:24:26.400563 ==DQM 0 ==
2376 01:24:26.403350 Final DQM duty delay cell = 0
2377 01:24:26.406269 [0] MAX Duty = 5125%(X100), DQS PI = 20
2378 01:24:26.409512 [0] MIN Duty = 4844%(X100), DQS PI = 50
2379 01:24:26.413053 [0] AVG Duty = 4984%(X100)
2380 01:24:26.413134
2381 01:24:26.413197 ==DQM 1 ==
2382 01:24:26.416344 Final DQM duty delay cell = 0
2383 01:24:26.419787 [0] MAX Duty = 4969%(X100), DQS PI = 0
2384 01:24:26.423054 [0] MIN Duty = 4907%(X100), DQS PI = 12
2385 01:24:26.426820 [0] AVG Duty = 4938%(X100)
2386 01:24:26.426901
2387 01:24:26.429370 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2388 01:24:26.429457
2389 01:24:26.432958 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2390 01:24:26.436175 [DutyScan_Calibration_Flow] ====Done====
2391 01:24:26.436256
2392 01:24:26.440071 [DutyScan_Calibration_Flow] k_type=2
2393 01:24:26.456034
2394 01:24:26.456114 ==DQ 0 ==
2395 01:24:26.459849 Final DQ duty delay cell = 0
2396 01:24:26.463031 [0] MAX Duty = 5125%(X100), DQS PI = 18
2397 01:24:26.466055 [0] MIN Duty = 4938%(X100), DQS PI = 58
2398 01:24:26.466136 [0] AVG Duty = 5031%(X100)
2399 01:24:26.466200
2400 01:24:26.469513 ==DQ 1 ==
2401 01:24:26.472857 Final DQ duty delay cell = 0
2402 01:24:26.476221 [0] MAX Duty = 5125%(X100), DQS PI = 6
2403 01:24:26.479234 [0] MIN Duty = 4938%(X100), DQS PI = 14
2404 01:24:26.479314 [0] AVG Duty = 5031%(X100)
2405 01:24:26.479378
2406 01:24:26.482797 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2407 01:24:26.486543
2408 01:24:26.486623 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2409 01:24:26.492789 [DutyScan_Calibration_Flow] ====Done====
2410 01:24:26.492870 ==
2411 01:24:26.496176 Dram Type= 6, Freq= 0, CH_1, rank 0
2412 01:24:26.499295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2413 01:24:26.499375 ==
2414 01:24:26.503163 [Duty_Offset_Calibration]
2415 01:24:26.503237 B0:0 B1:-1 CA:3
2416 01:24:26.503297
2417 01:24:26.506790 [DutyScan_Calibration_Flow] k_type=0
2418 01:24:26.515353
2419 01:24:26.515432 ==CLK 0==
2420 01:24:26.519121 Final CLK duty delay cell = -4
2421 01:24:26.521799 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2422 01:24:26.525142 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2423 01:24:26.528679 [-4] AVG Duty = 4938%(X100)
2424 01:24:26.528756
2425 01:24:26.531680 CH1 CLK Duty spec in!! Max-Min= 124%
2426 01:24:26.535265 [DutyScan_Calibration_Flow] ====Done====
2427 01:24:26.535342
2428 01:24:26.538177 [DutyScan_Calibration_Flow] k_type=1
2429 01:24:26.553966
2430 01:24:26.554050 ==DQS 0 ==
2431 01:24:26.557310 Final DQS duty delay cell = 0
2432 01:24:26.560599 [0] MAX Duty = 5187%(X100), DQS PI = 18
2433 01:24:26.564018 [0] MIN Duty = 4907%(X100), DQS PI = 38
2434 01:24:26.567521 [0] AVG Duty = 5047%(X100)
2435 01:24:26.567628
2436 01:24:26.567725 ==DQS 1 ==
2437 01:24:26.570541 Final DQS duty delay cell = -4
2438 01:24:26.573926 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2439 01:24:26.576998 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2440 01:24:26.580980 [-4] AVG Duty = 4937%(X100)
2441 01:24:26.581064
2442 01:24:26.583772 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2443 01:24:26.583877
2444 01:24:26.587016 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2445 01:24:26.590631 [DutyScan_Calibration_Flow] ====Done====
2446 01:24:26.590720
2447 01:24:26.593666 [DutyScan_Calibration_Flow] k_type=3
2448 01:24:26.610901
2449 01:24:26.610983 ==DQM 0 ==
2450 01:24:26.614052 Final DQM duty delay cell = 0
2451 01:24:26.617597 [0] MAX Duty = 5031%(X100), DQS PI = 28
2452 01:24:26.621315 [0] MIN Duty = 4813%(X100), DQS PI = 36
2453 01:24:26.624294 [0] AVG Duty = 4922%(X100)
2454 01:24:26.624394
2455 01:24:26.624488 ==DQM 1 ==
2456 01:24:26.627359 Final DQM duty delay cell = 0
2457 01:24:26.630702 [0] MAX Duty = 5000%(X100), DQS PI = 34
2458 01:24:26.634038 [0] MIN Duty = 4844%(X100), DQS PI = 0
2459 01:24:26.634134 [0] AVG Duty = 4922%(X100)
2460 01:24:26.637482
2461 01:24:26.640745 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2462 01:24:26.640824
2463 01:24:26.644340 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2464 01:24:26.647672 [DutyScan_Calibration_Flow] ====Done====
2465 01:24:26.647768
2466 01:24:26.650627 [DutyScan_Calibration_Flow] k_type=2
2467 01:24:26.667855
2468 01:24:26.667981 ==DQ 0 ==
2469 01:24:26.670609 Final DQ duty delay cell = -4
2470 01:24:26.674426 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2471 01:24:26.677149 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2472 01:24:26.680662 [-4] AVG Duty = 4922%(X100)
2473 01:24:26.680752
2474 01:24:26.680817 ==DQ 1 ==
2475 01:24:26.684128 Final DQ duty delay cell = 4
2476 01:24:26.687464 [4] MAX Duty = 5156%(X100), DQS PI = 26
2477 01:24:26.691091 [4] MIN Duty = 5031%(X100), DQS PI = 62
2478 01:24:26.694052 [4] AVG Duty = 5093%(X100)
2479 01:24:26.694124
2480 01:24:26.697337 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2481 01:24:26.697417
2482 01:24:26.700523 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2483 01:24:26.703632 [DutyScan_Calibration_Flow] ====Done====
2484 01:24:26.707194 nWR fixed to 30
2485 01:24:26.710502 [ModeRegInit_LP4] CH0 RK0
2486 01:24:26.710586 [ModeRegInit_LP4] CH0 RK1
2487 01:24:26.714081 [ModeRegInit_LP4] CH1 RK0
2488 01:24:26.717361 [ModeRegInit_LP4] CH1 RK1
2489 01:24:26.717441 match AC timing 7
2490 01:24:26.723645 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2491 01:24:26.727163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2492 01:24:26.730590 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2493 01:24:26.737363 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2494 01:24:26.740537 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2495 01:24:26.740621 ==
2496 01:24:26.743469 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 01:24:26.747165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 01:24:26.747249 ==
2499 01:24:26.753472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 01:24:26.760018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2501 01:24:26.768059 [CA 0] Center 39 (9~70) winsize 62
2502 01:24:26.771049 [CA 1] Center 39 (9~70) winsize 62
2503 01:24:26.774464 [CA 2] Center 35 (5~66) winsize 62
2504 01:24:26.777543 [CA 3] Center 35 (5~66) winsize 62
2505 01:24:26.781418 [CA 4] Center 33 (3~64) winsize 62
2506 01:24:26.784420 [CA 5] Center 33 (3~63) winsize 61
2507 01:24:26.784505
2508 01:24:26.787413 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 01:24:26.787492
2510 01:24:26.790901 [CATrainingPosCal] consider 1 rank data
2511 01:24:26.794417 u2DelayCellTimex100 = 270/100 ps
2512 01:24:26.797459 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2513 01:24:26.804477 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2514 01:24:26.807185 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 01:24:26.810892 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 01:24:26.814249 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2517 01:24:26.817768 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2518 01:24:26.817849
2519 01:24:26.821166 CA PerBit enable=1, Macro0, CA PI delay=33
2520 01:24:26.821247
2521 01:24:26.824066 [CBTSetCACLKResult] CA Dly = 33
2522 01:24:26.824146 CS Dly: 7 (0~38)
2523 01:24:26.827432 ==
2524 01:24:26.827511 Dram Type= 6, Freq= 0, CH_0, rank 1
2525 01:24:26.833961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 01:24:26.834043 ==
2527 01:24:26.837092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 01:24:26.843845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 01:24:26.853711 [CA 0] Center 39 (9~70) winsize 62
2530 01:24:26.856609 [CA 1] Center 39 (9~70) winsize 62
2531 01:24:26.859908 [CA 2] Center 35 (5~66) winsize 62
2532 01:24:26.863323 [CA 3] Center 35 (5~66) winsize 62
2533 01:24:26.866437 [CA 4] Center 34 (4~65) winsize 62
2534 01:24:26.870300 [CA 5] Center 33 (3~64) winsize 62
2535 01:24:26.870398
2536 01:24:26.873312 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2537 01:24:26.873392
2538 01:24:26.876304 [CATrainingPosCal] consider 2 rank data
2539 01:24:26.880093 u2DelayCellTimex100 = 270/100 ps
2540 01:24:26.883022 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2541 01:24:26.889798 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2542 01:24:26.893118 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2543 01:24:26.896758 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 01:24:26.899533 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2545 01:24:26.903707 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2546 01:24:26.903779
2547 01:24:26.906359 CA PerBit enable=1, Macro0, CA PI delay=33
2548 01:24:26.906431
2549 01:24:26.909640 [CBTSetCACLKResult] CA Dly = 33
2550 01:24:26.909720 CS Dly: 8 (0~41)
2551 01:24:26.912846
2552 01:24:26.916295 ----->DramcWriteLeveling(PI) begin...
2553 01:24:26.916373 ==
2554 01:24:26.920132 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 01:24:26.923493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 01:24:26.923570 ==
2557 01:24:26.926496 Write leveling (Byte 0): 33 => 33
2558 01:24:26.929632 Write leveling (Byte 1): 27 => 27
2559 01:24:26.932840 DramcWriteLeveling(PI) end<-----
2560 01:24:26.932925
2561 01:24:26.932992 ==
2562 01:24:26.936014 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 01:24:26.939758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 01:24:26.939876 ==
2565 01:24:26.942792 [Gating] SW mode calibration
2566 01:24:26.949448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2567 01:24:26.956033 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2568 01:24:26.959427 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2569 01:24:26.962937 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2570 01:24:26.969402 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 01:24:26.972997 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 01:24:26.976104 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 01:24:26.982610 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 01:24:26.986281 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 01:24:26.989656 0 15 28 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
2576 01:24:26.996262 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2577 01:24:26.999407 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2578 01:24:27.002685 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 01:24:27.005842 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 01:24:27.012662 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 01:24:27.016009 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 01:24:27.019822 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2583 01:24:27.026511 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2584 01:24:27.029969 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
2585 01:24:27.033080 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2586 01:24:27.039092 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 01:24:27.042639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 01:24:27.045919 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 01:24:27.052285 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 01:24:27.056090 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 01:24:27.059004 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2592 01:24:27.065538 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2593 01:24:27.069300 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2594 01:24:27.072228 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 01:24:27.078602 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 01:24:27.082280 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 01:24:27.085887 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 01:24:27.092155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 01:24:27.095255 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 01:24:27.098718 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 01:24:27.105519 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 01:24:27.108777 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 01:24:27.112437 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 01:24:27.118752 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 01:24:27.121867 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 01:24:27.125171 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2607 01:24:27.131886 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2608 01:24:27.135509 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2609 01:24:27.138868 Total UI for P1: 0, mck2ui 16
2610 01:24:27.142293 best dqsien dly found for B0: ( 1, 3, 26)
2611 01:24:27.145080 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2612 01:24:27.151922 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 01:24:27.152005 Total UI for P1: 0, mck2ui 16
2614 01:24:27.155356 best dqsien dly found for B1: ( 1, 4, 2)
2615 01:24:27.161770 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2616 01:24:27.165105 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2617 01:24:27.165184
2618 01:24:27.168401 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2619 01:24:27.171552 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2620 01:24:27.175295 [Gating] SW calibration Done
2621 01:24:27.175375 ==
2622 01:24:27.178244 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 01:24:27.181823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 01:24:27.181906 ==
2625 01:24:27.185265 RX Vref Scan: 0
2626 01:24:27.185339
2627 01:24:27.185400 RX Vref 0 -> 0, step: 1
2628 01:24:27.185459
2629 01:24:27.188791 RX Delay -40 -> 252, step: 8
2630 01:24:27.192253 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2631 01:24:27.194831 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2632 01:24:27.201478 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2633 01:24:27.204769 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2634 01:24:27.208688 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2635 01:24:27.212220 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2636 01:24:27.215572 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2637 01:24:27.221228 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2638 01:24:27.224544 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2639 01:24:27.227733 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2640 01:24:27.231759 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2641 01:24:27.234586 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2642 01:24:27.241011 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2643 01:24:27.245062 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2644 01:24:27.247815 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2645 01:24:27.252312 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2646 01:24:27.252416 ==
2647 01:24:27.254463 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 01:24:27.261455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 01:24:27.261533 ==
2650 01:24:27.261600 DQS Delay:
2651 01:24:27.264303 DQS0 = 0, DQS1 = 0
2652 01:24:27.264402 DQM Delay:
2653 01:24:27.267591 DQM0 = 118, DQM1 = 108
2654 01:24:27.267689 DQ Delay:
2655 01:24:27.271634 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2656 01:24:27.274173 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2657 01:24:27.277920 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2658 01:24:27.281469 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2659 01:24:27.281571
2660 01:24:27.281680
2661 01:24:27.281777 ==
2662 01:24:27.284287 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 01:24:27.290838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 01:24:27.290944 ==
2665 01:24:27.291012
2666 01:24:27.291073
2667 01:24:27.291131 TX Vref Scan disable
2668 01:24:27.294495 == TX Byte 0 ==
2669 01:24:27.297432 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2670 01:24:27.304051 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2671 01:24:27.304129 == TX Byte 1 ==
2672 01:24:27.307339 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2673 01:24:27.314056 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2674 01:24:27.314158 ==
2675 01:24:27.317482 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 01:24:27.320612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 01:24:27.320691 ==
2678 01:24:27.332372 TX Vref=22, minBit 4, minWin=24, winSum=409
2679 01:24:27.335881 TX Vref=24, minBit 14, minWin=25, winSum=418
2680 01:24:27.339269 TX Vref=26, minBit 10, minWin=25, winSum=421
2681 01:24:27.342302 TX Vref=28, minBit 4, minWin=25, winSum=428
2682 01:24:27.345439 TX Vref=30, minBit 8, minWin=26, winSum=429
2683 01:24:27.352745 TX Vref=32, minBit 1, minWin=26, winSum=427
2684 01:24:27.355955 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
2685 01:24:27.356068
2686 01:24:27.359121 Final TX Range 1 Vref 30
2687 01:24:27.359230
2688 01:24:27.359322 ==
2689 01:24:27.362513 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 01:24:27.365665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 01:24:27.369204 ==
2692 01:24:27.369294
2693 01:24:27.369358
2694 01:24:27.369418 TX Vref Scan disable
2695 01:24:27.372324 == TX Byte 0 ==
2696 01:24:27.375538 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2697 01:24:27.382500 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2698 01:24:27.382611 == TX Byte 1 ==
2699 01:24:27.385629 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2700 01:24:27.389013 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2701 01:24:27.392467
2702 01:24:27.392573 [DATLAT]
2703 01:24:27.392665 Freq=1200, CH0 RK0
2704 01:24:27.392754
2705 01:24:27.396079 DATLAT Default: 0xd
2706 01:24:27.396181 0, 0xFFFF, sum = 0
2707 01:24:27.399408 1, 0xFFFF, sum = 0
2708 01:24:27.399515 2, 0xFFFF, sum = 0
2709 01:24:27.402298 3, 0xFFFF, sum = 0
2710 01:24:27.405540 4, 0xFFFF, sum = 0
2711 01:24:27.405632 5, 0xFFFF, sum = 0
2712 01:24:27.409389 6, 0xFFFF, sum = 0
2713 01:24:27.409464 7, 0xFFFF, sum = 0
2714 01:24:27.412371 8, 0xFFFF, sum = 0
2715 01:24:27.412458 9, 0xFFFF, sum = 0
2716 01:24:27.415552 10, 0xFFFF, sum = 0
2717 01:24:27.415649 11, 0xFFFF, sum = 0
2718 01:24:27.419167 12, 0x0, sum = 1
2719 01:24:27.419265 13, 0x0, sum = 2
2720 01:24:27.422305 14, 0x0, sum = 3
2721 01:24:27.422408 15, 0x0, sum = 4
2722 01:24:27.425653 best_step = 13
2723 01:24:27.425753
2724 01:24:27.425846 ==
2725 01:24:27.429356 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 01:24:27.432002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 01:24:27.432100 ==
2728 01:24:27.432169 RX Vref Scan: 1
2729 01:24:27.432257
2730 01:24:27.436132 Set Vref Range= 32 -> 127
2731 01:24:27.436228
2732 01:24:27.438602 RX Vref 32 -> 127, step: 1
2733 01:24:27.438695
2734 01:24:27.442794 RX Delay -21 -> 252, step: 4
2735 01:24:27.442894
2736 01:24:27.445545 Set Vref, RX VrefLevel [Byte0]: 32
2737 01:24:27.448364 [Byte1]: 32
2738 01:24:27.448464
2739 01:24:27.451654 Set Vref, RX VrefLevel [Byte0]: 33
2740 01:24:27.454815 [Byte1]: 33
2741 01:24:27.458864
2742 01:24:27.458965 Set Vref, RX VrefLevel [Byte0]: 34
2743 01:24:27.462153 [Byte1]: 34
2744 01:24:27.466735
2745 01:24:27.466836 Set Vref, RX VrefLevel [Byte0]: 35
2746 01:24:27.470359 [Byte1]: 35
2747 01:24:27.474897
2748 01:24:27.475002 Set Vref, RX VrefLevel [Byte0]: 36
2749 01:24:27.478057 [Byte1]: 36
2750 01:24:27.483238
2751 01:24:27.483344 Set Vref, RX VrefLevel [Byte0]: 37
2752 01:24:27.486201 [Byte1]: 37
2753 01:24:27.491075
2754 01:24:27.491150 Set Vref, RX VrefLevel [Byte0]: 38
2755 01:24:27.494288 [Byte1]: 38
2756 01:24:27.498489
2757 01:24:27.498591 Set Vref, RX VrefLevel [Byte0]: 39
2758 01:24:27.501848 [Byte1]: 39
2759 01:24:27.506428
2760 01:24:27.506543 Set Vref, RX VrefLevel [Byte0]: 40
2761 01:24:27.510156 [Byte1]: 40
2762 01:24:27.514587
2763 01:24:27.518378 Set Vref, RX VrefLevel [Byte0]: 41
2764 01:24:27.518489 [Byte1]: 41
2765 01:24:27.522493
2766 01:24:27.522573 Set Vref, RX VrefLevel [Byte0]: 42
2767 01:24:27.525472 [Byte1]: 42
2768 01:24:27.530125
2769 01:24:27.530235 Set Vref, RX VrefLevel [Byte0]: 43
2770 01:24:27.533914 [Byte1]: 43
2771 01:24:27.538178
2772 01:24:27.538259 Set Vref, RX VrefLevel [Byte0]: 44
2773 01:24:27.541408 [Byte1]: 44
2774 01:24:27.546361
2775 01:24:27.546442 Set Vref, RX VrefLevel [Byte0]: 45
2776 01:24:27.549541 [Byte1]: 45
2777 01:24:27.554024
2778 01:24:27.554121 Set Vref, RX VrefLevel [Byte0]: 46
2779 01:24:27.557320 [Byte1]: 46
2780 01:24:27.562740
2781 01:24:27.562821 Set Vref, RX VrefLevel [Byte0]: 47
2782 01:24:27.565383 [Byte1]: 47
2783 01:24:27.570176
2784 01:24:27.570255 Set Vref, RX VrefLevel [Byte0]: 48
2785 01:24:27.573183 [Byte1]: 48
2786 01:24:27.577811
2787 01:24:27.577911 Set Vref, RX VrefLevel [Byte0]: 49
2788 01:24:27.581330 [Byte1]: 49
2789 01:24:27.585736
2790 01:24:27.585818 Set Vref, RX VrefLevel [Byte0]: 50
2791 01:24:27.589255 [Byte1]: 50
2792 01:24:27.593624
2793 01:24:27.593701 Set Vref, RX VrefLevel [Byte0]: 51
2794 01:24:27.597356 [Byte1]: 51
2795 01:24:27.601795
2796 01:24:27.601868 Set Vref, RX VrefLevel [Byte0]: 52
2797 01:24:27.604831 [Byte1]: 52
2798 01:24:27.609480
2799 01:24:27.609550 Set Vref, RX VrefLevel [Byte0]: 53
2800 01:24:27.612848 [Byte1]: 53
2801 01:24:27.617671
2802 01:24:27.617750 Set Vref, RX VrefLevel [Byte0]: 54
2803 01:24:27.620910 [Byte1]: 54
2804 01:24:27.625819
2805 01:24:27.625891 Set Vref, RX VrefLevel [Byte0]: 55
2806 01:24:27.628866 [Byte1]: 55
2807 01:24:27.633980
2808 01:24:27.634051 Set Vref, RX VrefLevel [Byte0]: 56
2809 01:24:27.636428 [Byte1]: 56
2810 01:24:27.641275
2811 01:24:27.641347 Set Vref, RX VrefLevel [Byte0]: 57
2812 01:24:27.644400 [Byte1]: 57
2813 01:24:27.649469
2814 01:24:27.649547 Set Vref, RX VrefLevel [Byte0]: 58
2815 01:24:27.652707 [Byte1]: 58
2816 01:24:27.656933
2817 01:24:27.657006 Set Vref, RX VrefLevel [Byte0]: 59
2818 01:24:27.660199 [Byte1]: 59
2819 01:24:27.665133
2820 01:24:27.665208 Set Vref, RX VrefLevel [Byte0]: 60
2821 01:24:27.668356 [Byte1]: 60
2822 01:24:27.673021
2823 01:24:27.673093 Set Vref, RX VrefLevel [Byte0]: 61
2824 01:24:27.676509 [Byte1]: 61
2825 01:24:27.680957
2826 01:24:27.681030 Set Vref, RX VrefLevel [Byte0]: 62
2827 01:24:27.684229 [Byte1]: 62
2828 01:24:27.688831
2829 01:24:27.688906 Set Vref, RX VrefLevel [Byte0]: 63
2830 01:24:27.692554 [Byte1]: 63
2831 01:24:27.696866
2832 01:24:27.696940 Set Vref, RX VrefLevel [Byte0]: 64
2833 01:24:27.699981 [Byte1]: 64
2834 01:24:27.704794
2835 01:24:27.704868 Set Vref, RX VrefLevel [Byte0]: 65
2836 01:24:27.708922 [Byte1]: 65
2837 01:24:27.712614
2838 01:24:27.712699 Set Vref, RX VrefLevel [Byte0]: 66
2839 01:24:27.715854 [Byte1]: 66
2840 01:24:27.720419
2841 01:24:27.720491 Set Vref, RX VrefLevel [Byte0]: 67
2842 01:24:27.724227 [Byte1]: 67
2843 01:24:27.728341
2844 01:24:27.728411 Set Vref, RX VrefLevel [Byte0]: 68
2845 01:24:27.731999 [Byte1]: 68
2846 01:24:27.736444
2847 01:24:27.736524 Set Vref, RX VrefLevel [Byte0]: 69
2848 01:24:27.739853 [Byte1]: 69
2849 01:24:27.744362
2850 01:24:27.744449 Final RX Vref Byte 0 = 51 to rank0
2851 01:24:27.748152 Final RX Vref Byte 1 = 59 to rank0
2852 01:24:27.751184 Final RX Vref Byte 0 = 51 to rank1
2853 01:24:27.754228 Final RX Vref Byte 1 = 59 to rank1==
2854 01:24:27.757825 Dram Type= 6, Freq= 0, CH_0, rank 0
2855 01:24:27.763985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 01:24:27.764063 ==
2857 01:24:27.764135 DQS Delay:
2858 01:24:27.764195 DQS0 = 0, DQS1 = 0
2859 01:24:27.767870 DQM Delay:
2860 01:24:27.767981 DQM0 = 117, DQM1 = 105
2861 01:24:27.770725 DQ Delay:
2862 01:24:27.774483 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =112
2863 01:24:27.777680 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2864 01:24:27.781355 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2865 01:24:27.784876 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =110
2866 01:24:27.784953
2867 01:24:27.785024
2868 01:24:27.790708 [DQSOSCAuto] RK0, (LSB)MR18= 0x2fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2869 01:24:27.794202 CH0 RK0: MR19=403, MR18=2FD
2870 01:24:27.801014 CH0_RK0: MR19=0x403, MR18=0x2FD, DQSOSC=409, MR23=63, INC=39, DEC=26
2871 01:24:27.801091
2872 01:24:27.804068 ----->DramcWriteLeveling(PI) begin...
2873 01:24:27.804163 ==
2874 01:24:27.807882 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 01:24:27.811102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 01:24:27.811178 ==
2877 01:24:27.814426 Write leveling (Byte 0): 33 => 33
2878 01:24:27.818008 Write leveling (Byte 1): 26 => 26
2879 01:24:27.822008 DramcWriteLeveling(PI) end<-----
2880 01:24:27.822083
2881 01:24:27.822146 ==
2882 01:24:27.824093 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 01:24:27.830774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 01:24:27.830853 ==
2885 01:24:27.830916 [Gating] SW mode calibration
2886 01:24:27.840483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2887 01:24:27.843634 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2888 01:24:27.850412 0 15 0 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
2889 01:24:27.854088 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2890 01:24:27.857848 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 01:24:27.860682 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 01:24:27.866791 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 01:24:27.870708 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 01:24:27.873480 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2895 01:24:27.880717 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2896 01:24:27.883750 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2897 01:24:27.887227 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 01:24:27.893697 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 01:24:27.896634 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 01:24:27.900044 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 01:24:27.907068 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 01:24:27.909906 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2903 01:24:27.913427 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2904 01:24:27.920022 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2905 01:24:27.923345 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 01:24:27.927245 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 01:24:27.933530 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 01:24:27.936392 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 01:24:27.940143 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 01:24:27.946392 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2911 01:24:27.949381 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2912 01:24:27.952734 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2913 01:24:27.959844 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 01:24:27.963432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 01:24:27.966362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 01:24:27.972975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 01:24:27.976630 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 01:24:27.979617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 01:24:27.986210 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 01:24:27.989311 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 01:24:27.992843 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 01:24:27.999594 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 01:24:28.002678 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 01:24:28.005903 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 01:24:28.012818 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 01:24:28.016779 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2927 01:24:28.019295 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2928 01:24:28.022554 Total UI for P1: 0, mck2ui 16
2929 01:24:28.026323 best dqsien dly found for B0: ( 1, 3, 24)
2930 01:24:28.029736 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2931 01:24:28.036022 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 01:24:28.039285 Total UI for P1: 0, mck2ui 16
2933 01:24:28.043333 best dqsien dly found for B1: ( 1, 4, 0)
2934 01:24:28.045742 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2935 01:24:28.049662 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2936 01:24:28.049737
2937 01:24:28.052938 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2938 01:24:28.055596 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2939 01:24:28.059844 [Gating] SW calibration Done
2940 01:24:28.059968 ==
2941 01:24:28.062458 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 01:24:28.065887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 01:24:28.065970 ==
2944 01:24:28.069106 RX Vref Scan: 0
2945 01:24:28.069175
2946 01:24:28.072286 RX Vref 0 -> 0, step: 1
2947 01:24:28.072352
2948 01:24:28.072419 RX Delay -40 -> 252, step: 8
2949 01:24:28.078997 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2950 01:24:28.082472 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2951 01:24:28.085627 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2952 01:24:28.089050 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2953 01:24:28.092363 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2954 01:24:28.099375 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2955 01:24:28.102281 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2956 01:24:28.106235 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2957 01:24:28.109170 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2958 01:24:28.112448 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2959 01:24:28.115738 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2960 01:24:28.122181 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2961 01:24:28.126157 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2962 01:24:28.129551 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2963 01:24:28.132658 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2964 01:24:28.138766 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2965 01:24:28.138847 ==
2966 01:24:28.142414 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 01:24:28.145780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 01:24:28.145853 ==
2969 01:24:28.145939 DQS Delay:
2970 01:24:28.148982 DQS0 = 0, DQS1 = 0
2971 01:24:28.149052 DQM Delay:
2972 01:24:28.152040 DQM0 = 115, DQM1 = 108
2973 01:24:28.152111 DQ Delay:
2974 01:24:28.155754 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2975 01:24:28.158982 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2976 01:24:28.162290 DQ8 =99, DQ9 =91, DQ10 =107, DQ11 =103
2977 01:24:28.165710 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2978 01:24:28.165789
2979 01:24:28.165852
2980 01:24:28.169246 ==
2981 01:24:28.169321 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 01:24:28.175495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 01:24:28.175589 ==
2984 01:24:28.175689
2985 01:24:28.175762
2986 01:24:28.179007 TX Vref Scan disable
2987 01:24:28.179086 == TX Byte 0 ==
2988 01:24:28.182204 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2989 01:24:28.189146 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2990 01:24:28.189234 == TX Byte 1 ==
2991 01:24:28.192300 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2992 01:24:28.198982 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2993 01:24:28.199058 ==
2994 01:24:28.202021 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 01:24:28.205240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 01:24:28.205312 ==
2997 01:24:28.218394 TX Vref=22, minBit 4, minWin=25, winSum=418
2998 01:24:28.221307 TX Vref=24, minBit 14, minWin=25, winSum=421
2999 01:24:28.224973 TX Vref=26, minBit 13, minWin=25, winSum=425
3000 01:24:28.228372 TX Vref=28, minBit 4, minWin=26, winSum=429
3001 01:24:28.231381 TX Vref=30, minBit 10, minWin=26, winSum=428
3002 01:24:28.237669 TX Vref=32, minBit 4, minWin=26, winSum=427
3003 01:24:28.241415 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 28
3004 01:24:28.241503
3005 01:24:28.245070 Final TX Range 1 Vref 28
3006 01:24:28.245143
3007 01:24:28.245204 ==
3008 01:24:28.247848 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 01:24:28.251516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 01:24:28.254984 ==
3011 01:24:28.255056
3012 01:24:28.255124
3013 01:24:28.255184 TX Vref Scan disable
3014 01:24:28.257982 == TX Byte 0 ==
3015 01:24:28.261265 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3016 01:24:28.267778 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3017 01:24:28.267868 == TX Byte 1 ==
3018 01:24:28.271148 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3019 01:24:28.277860 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3020 01:24:28.277935
3021 01:24:28.278018 [DATLAT]
3022 01:24:28.278092 Freq=1200, CH0 RK1
3023 01:24:28.278149
3024 01:24:28.281698 DATLAT Default: 0xd
3025 01:24:28.281763 0, 0xFFFF, sum = 0
3026 01:24:28.284612 1, 0xFFFF, sum = 0
3027 01:24:28.288433 2, 0xFFFF, sum = 0
3028 01:24:28.288521 3, 0xFFFF, sum = 0
3029 01:24:28.291123 4, 0xFFFF, sum = 0
3030 01:24:28.291195 5, 0xFFFF, sum = 0
3031 01:24:28.294411 6, 0xFFFF, sum = 0
3032 01:24:28.294484 7, 0xFFFF, sum = 0
3033 01:24:28.297910 8, 0xFFFF, sum = 0
3034 01:24:28.297984 9, 0xFFFF, sum = 0
3035 01:24:28.300903 10, 0xFFFF, sum = 0
3036 01:24:28.300982 11, 0xFFFF, sum = 0
3037 01:24:28.304363 12, 0x0, sum = 1
3038 01:24:28.304431 13, 0x0, sum = 2
3039 01:24:28.307637 14, 0x0, sum = 3
3040 01:24:28.307716 15, 0x0, sum = 4
3041 01:24:28.310905 best_step = 13
3042 01:24:28.310991
3043 01:24:28.311052 ==
3044 01:24:28.314524 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 01:24:28.317873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 01:24:28.317946 ==
3047 01:24:28.318012 RX Vref Scan: 0
3048 01:24:28.318072
3049 01:24:28.321548 RX Vref 0 -> 0, step: 1
3050 01:24:28.321621
3051 01:24:28.324316 RX Delay -21 -> 252, step: 4
3052 01:24:28.327985 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3053 01:24:28.334893 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3054 01:24:28.337795 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3055 01:24:28.341125 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3056 01:24:28.344128 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3057 01:24:28.347842 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3058 01:24:28.354222 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3059 01:24:28.357614 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3060 01:24:28.361125 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3061 01:24:28.364820 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3062 01:24:28.367720 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3063 01:24:28.374566 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3064 01:24:28.377586 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3065 01:24:28.380989 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3066 01:24:28.384434 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3067 01:24:28.387419 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3068 01:24:28.390652 ==
3069 01:24:28.390727 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 01:24:28.397529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 01:24:28.397618 ==
3072 01:24:28.397717 DQS Delay:
3073 01:24:28.400617 DQS0 = 0, DQS1 = 0
3074 01:24:28.400690 DQM Delay:
3075 01:24:28.403948 DQM0 = 116, DQM1 = 107
3076 01:24:28.404031 DQ Delay:
3077 01:24:28.407408 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3078 01:24:28.411200 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3079 01:24:28.413869 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3080 01:24:28.417243 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
3081 01:24:28.417310
3082 01:24:28.417370
3083 01:24:28.427389 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
3084 01:24:28.427474 CH0 RK1: MR19=303, MR18=FEFB
3085 01:24:28.433999 CH0_RK1: MR19=0x303, MR18=0xFEFB, DQSOSC=410, MR23=63, INC=39, DEC=26
3086 01:24:28.437060 [RxdqsGatingPostProcess] freq 1200
3087 01:24:28.443775 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3088 01:24:28.447370 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 01:24:28.450787 best DQS1 dly(2T, 0.5T) = (0, 12)
3090 01:24:28.453739 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 01:24:28.457539 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3092 01:24:28.460770 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 01:24:28.464319 best DQS1 dly(2T, 0.5T) = (0, 12)
3094 01:24:28.464415 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 01:24:28.467307 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3096 01:24:28.470569 Pre-setting of DQS Precalculation
3097 01:24:28.477274 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3098 01:24:28.477386 ==
3099 01:24:28.481071 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 01:24:28.484035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 01:24:28.484133 ==
3102 01:24:28.490756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 01:24:28.497128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3104 01:24:28.504616 [CA 0] Center 38 (8~68) winsize 61
3105 01:24:28.507421 [CA 1] Center 37 (7~68) winsize 62
3106 01:24:28.511007 [CA 2] Center 35 (5~65) winsize 61
3107 01:24:28.514567 [CA 3] Center 34 (4~64) winsize 61
3108 01:24:28.517824 [CA 4] Center 35 (5~65) winsize 61
3109 01:24:28.520994 [CA 5] Center 33 (3~63) winsize 61
3110 01:24:28.521067
3111 01:24:28.524353 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 01:24:28.524423
3113 01:24:28.527515 [CATrainingPosCal] consider 1 rank data
3114 01:24:28.530935 u2DelayCellTimex100 = 270/100 ps
3115 01:24:28.534143 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 01:24:28.541023 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3117 01:24:28.544050 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3118 01:24:28.547852 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 01:24:28.550429 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3120 01:24:28.553943 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3121 01:24:28.554018
3122 01:24:28.557528 CA PerBit enable=1, Macro0, CA PI delay=33
3123 01:24:28.557601
3124 01:24:28.560603 [CBTSetCACLKResult] CA Dly = 33
3125 01:24:28.560689 CS Dly: 4 (0~35)
3126 01:24:28.564369 ==
3127 01:24:28.567571 Dram Type= 6, Freq= 0, CH_1, rank 1
3128 01:24:28.570480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 01:24:28.570580 ==
3130 01:24:28.577306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 01:24:28.580268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3132 01:24:28.590047 [CA 0] Center 37 (7~68) winsize 62
3133 01:24:28.593972 [CA 1] Center 38 (8~68) winsize 61
3134 01:24:28.597145 [CA 2] Center 34 (4~65) winsize 62
3135 01:24:28.599822 [CA 3] Center 33 (3~64) winsize 62
3136 01:24:28.603514 [CA 4] Center 34 (4~64) winsize 61
3137 01:24:28.606787 [CA 5] Center 33 (3~63) winsize 61
3138 01:24:28.606857
3139 01:24:28.609693 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3140 01:24:28.609767
3141 01:24:28.613328 [CATrainingPosCal] consider 2 rank data
3142 01:24:28.616324 u2DelayCellTimex100 = 270/100 ps
3143 01:24:28.619721 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3144 01:24:28.626744 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3145 01:24:28.630434 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3146 01:24:28.632923 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 01:24:28.636440 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3148 01:24:28.640044 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3149 01:24:28.640130
3150 01:24:28.643001 CA PerBit enable=1, Macro0, CA PI delay=33
3151 01:24:28.643077
3152 01:24:28.646344 [CBTSetCACLKResult] CA Dly = 33
3153 01:24:28.646415 CS Dly: 6 (0~39)
3154 01:24:28.650189
3155 01:24:28.653023 ----->DramcWriteLeveling(PI) begin...
3156 01:24:28.653096 ==
3157 01:24:28.656351 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 01:24:28.659511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 01:24:28.659584 ==
3160 01:24:28.662894 Write leveling (Byte 0): 26 => 26
3161 01:24:28.666019 Write leveling (Byte 1): 27 => 27
3162 01:24:28.669613 DramcWriteLeveling(PI) end<-----
3163 01:24:28.669692
3164 01:24:28.669754 ==
3165 01:24:28.673228 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 01:24:28.676305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 01:24:28.676414 ==
3168 01:24:28.679390 [Gating] SW mode calibration
3169 01:24:28.686728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3170 01:24:28.693022 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3171 01:24:28.696137 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 01:24:28.699284 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 01:24:28.706282 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 01:24:28.709302 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 01:24:28.713050 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 01:24:28.719373 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 01:24:28.723093 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3178 01:24:28.726938 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3179 01:24:28.729442 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 01:24:28.736142 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 01:24:28.739474 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 01:24:28.743134 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 01:24:28.749196 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 01:24:28.752609 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 01:24:28.756213 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3186 01:24:28.762469 1 0 28 | B1->B0 | 3b3b 4545 | 0 1 | (0 0) (0 0)
3187 01:24:28.765649 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 01:24:28.769500 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 01:24:28.776310 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 01:24:28.779185 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 01:24:28.782550 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 01:24:28.788988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 01:24:28.792117 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3194 01:24:28.795466 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3195 01:24:28.802423 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3196 01:24:28.805574 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 01:24:28.808786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 01:24:28.815266 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 01:24:28.819026 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 01:24:28.822320 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 01:24:28.828572 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 01:24:28.832700 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 01:24:28.835218 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 01:24:28.841799 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 01:24:28.845390 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 01:24:28.848899 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 01:24:28.855489 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 01:24:28.859134 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 01:24:28.861838 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 01:24:28.868828 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 01:24:28.872263 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 01:24:28.875468 Total UI for P1: 0, mck2ui 16
3213 01:24:28.878412 best dqsien dly found for B0: ( 1, 3, 28)
3214 01:24:28.881994 Total UI for P1: 0, mck2ui 16
3215 01:24:28.885491 best dqsien dly found for B1: ( 1, 3, 28)
3216 01:24:28.888927 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3217 01:24:28.892100 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3218 01:24:28.892176
3219 01:24:28.895164 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3220 01:24:28.898435 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3221 01:24:28.901837 [Gating] SW calibration Done
3222 01:24:28.901945 ==
3223 01:24:28.904998 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 01:24:28.908422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 01:24:28.908500 ==
3226 01:24:28.912120 RX Vref Scan: 0
3227 01:24:28.912201
3228 01:24:28.914934 RX Vref 0 -> 0, step: 1
3229 01:24:28.915016
3230 01:24:28.915079 RX Delay -40 -> 252, step: 8
3231 01:24:28.921656 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3232 01:24:28.925058 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3233 01:24:28.928602 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3234 01:24:28.931445 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3235 01:24:28.935000 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3236 01:24:28.941514 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3237 01:24:28.944914 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3238 01:24:28.948441 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3239 01:24:28.951428 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3240 01:24:28.955023 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3241 01:24:28.961724 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3242 01:24:28.964547 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3243 01:24:28.968029 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3244 01:24:28.971016 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3245 01:24:28.977626 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3246 01:24:28.981230 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3247 01:24:28.981326 ==
3248 01:24:28.985218 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 01:24:28.987855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 01:24:28.987990 ==
3251 01:24:28.991125 DQS Delay:
3252 01:24:28.991203 DQS0 = 0, DQS1 = 0
3253 01:24:28.991273 DQM Delay:
3254 01:24:28.994348 DQM0 = 115, DQM1 = 112
3255 01:24:28.994419 DQ Delay:
3256 01:24:28.997525 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3257 01:24:29.001160 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3258 01:24:29.004497 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3259 01:24:29.010901 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3260 01:24:29.010988
3261 01:24:29.011054
3262 01:24:29.011114 ==
3263 01:24:29.014231 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 01:24:29.017848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 01:24:29.017929 ==
3266 01:24:29.018029
3267 01:24:29.018088
3268 01:24:29.020836 TX Vref Scan disable
3269 01:24:29.020923 == TX Byte 0 ==
3270 01:24:29.027451 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 01:24:29.030783 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 01:24:29.030867 == TX Byte 1 ==
3273 01:24:29.037394 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3274 01:24:29.040601 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3275 01:24:29.040713 ==
3276 01:24:29.043815 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 01:24:29.047352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 01:24:29.047450 ==
3279 01:24:29.060626 TX Vref=22, minBit 9, minWin=24, winSum=403
3280 01:24:29.063056 TX Vref=24, minBit 3, minWin=25, winSum=414
3281 01:24:29.067124 TX Vref=26, minBit 11, minWin=24, winSum=419
3282 01:24:29.070245 TX Vref=28, minBit 9, minWin=25, winSum=424
3283 01:24:29.073153 TX Vref=30, minBit 9, minWin=25, winSum=426
3284 01:24:29.080168 TX Vref=32, minBit 4, minWin=26, winSum=426
3285 01:24:29.083433 [TxChooseVref] Worse bit 4, Min win 26, Win sum 426, Final Vref 32
3286 01:24:29.083552
3287 01:24:29.086981 Final TX Range 1 Vref 32
3288 01:24:29.087080
3289 01:24:29.087144 ==
3290 01:24:29.090013 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 01:24:29.093415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 01:24:29.093498 ==
3293 01:24:29.096241
3294 01:24:29.096351
3295 01:24:29.096443 TX Vref Scan disable
3296 01:24:29.099513 == TX Byte 0 ==
3297 01:24:29.103028 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3298 01:24:29.109761 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3299 01:24:29.109843 == TX Byte 1 ==
3300 01:24:29.113105 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3301 01:24:29.119646 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3302 01:24:29.119731
3303 01:24:29.119797 [DATLAT]
3304 01:24:29.119859 Freq=1200, CH1 RK0
3305 01:24:29.119930
3306 01:24:29.122915 DATLAT Default: 0xd
3307 01:24:29.122999 0, 0xFFFF, sum = 0
3308 01:24:29.126585 1, 0xFFFF, sum = 0
3309 01:24:29.129910 2, 0xFFFF, sum = 0
3310 01:24:29.129995 3, 0xFFFF, sum = 0
3311 01:24:29.132756 4, 0xFFFF, sum = 0
3312 01:24:29.132841 5, 0xFFFF, sum = 0
3313 01:24:29.136177 6, 0xFFFF, sum = 0
3314 01:24:29.136261 7, 0xFFFF, sum = 0
3315 01:24:29.139198 8, 0xFFFF, sum = 0
3316 01:24:29.139283 9, 0xFFFF, sum = 0
3317 01:24:29.142739 10, 0xFFFF, sum = 0
3318 01:24:29.142831 11, 0xFFFF, sum = 0
3319 01:24:29.146168 12, 0x0, sum = 1
3320 01:24:29.146253 13, 0x0, sum = 2
3321 01:24:29.149324 14, 0x0, sum = 3
3322 01:24:29.149409 15, 0x0, sum = 4
3323 01:24:29.152387 best_step = 13
3324 01:24:29.152470
3325 01:24:29.152535 ==
3326 01:24:29.156248 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 01:24:29.159503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 01:24:29.159587 ==
3329 01:24:29.159653 RX Vref Scan: 1
3330 01:24:29.159715
3331 01:24:29.162603 Set Vref Range= 32 -> 127
3332 01:24:29.162686
3333 01:24:29.165894 RX Vref 32 -> 127, step: 1
3334 01:24:29.165978
3335 01:24:29.169458 RX Delay -13 -> 252, step: 4
3336 01:24:29.169542
3337 01:24:29.172739 Set Vref, RX VrefLevel [Byte0]: 32
3338 01:24:29.176248 [Byte1]: 32
3339 01:24:29.176331
3340 01:24:29.179036 Set Vref, RX VrefLevel [Byte0]: 33
3341 01:24:29.182831 [Byte1]: 33
3342 01:24:29.185938
3343 01:24:29.186023 Set Vref, RX VrefLevel [Byte0]: 34
3344 01:24:29.189687 [Byte1]: 34
3345 01:24:29.193936
3346 01:24:29.194020 Set Vref, RX VrefLevel [Byte0]: 35
3347 01:24:29.197451 [Byte1]: 35
3348 01:24:29.201945
3349 01:24:29.202031 Set Vref, RX VrefLevel [Byte0]: 36
3350 01:24:29.204918 [Byte1]: 36
3351 01:24:29.209960
3352 01:24:29.210077 Set Vref, RX VrefLevel [Byte0]: 37
3353 01:24:29.212895 [Byte1]: 37
3354 01:24:29.217586
3355 01:24:29.217661 Set Vref, RX VrefLevel [Byte0]: 38
3356 01:24:29.221231 [Byte1]: 38
3357 01:24:29.225643
3358 01:24:29.228948 Set Vref, RX VrefLevel [Byte0]: 39
3359 01:24:29.229056 [Byte1]: 39
3360 01:24:29.233942
3361 01:24:29.234045 Set Vref, RX VrefLevel [Byte0]: 40
3362 01:24:29.236987 [Byte1]: 40
3363 01:24:29.241423
3364 01:24:29.241501 Set Vref, RX VrefLevel [Byte0]: 41
3365 01:24:29.244513 [Byte1]: 41
3366 01:24:29.248901
3367 01:24:29.249005 Set Vref, RX VrefLevel [Byte0]: 42
3368 01:24:29.252633 [Byte1]: 42
3369 01:24:29.256882
3370 01:24:29.256993 Set Vref, RX VrefLevel [Byte0]: 43
3371 01:24:29.260757 [Byte1]: 43
3372 01:24:29.265028
3373 01:24:29.265111 Set Vref, RX VrefLevel [Byte0]: 44
3374 01:24:29.268506 [Byte1]: 44
3375 01:24:29.273591
3376 01:24:29.273673 Set Vref, RX VrefLevel [Byte0]: 45
3377 01:24:29.275952 [Byte1]: 45
3378 01:24:29.280811
3379 01:24:29.280896 Set Vref, RX VrefLevel [Byte0]: 46
3380 01:24:29.284043 [Byte1]: 46
3381 01:24:29.288609
3382 01:24:29.288693 Set Vref, RX VrefLevel [Byte0]: 47
3383 01:24:29.291984 [Byte1]: 47
3384 01:24:29.296232
3385 01:24:29.296344 Set Vref, RX VrefLevel [Byte0]: 48
3386 01:24:29.299681 [Byte1]: 48
3387 01:24:29.304435
3388 01:24:29.304517 Set Vref, RX VrefLevel [Byte0]: 49
3389 01:24:29.307647 [Byte1]: 49
3390 01:24:29.311997
3391 01:24:29.312117 Set Vref, RX VrefLevel [Byte0]: 50
3392 01:24:29.316109 [Byte1]: 50
3393 01:24:29.319880
3394 01:24:29.320016 Set Vref, RX VrefLevel [Byte0]: 51
3395 01:24:29.323493 [Byte1]: 51
3396 01:24:29.328293
3397 01:24:29.328399 Set Vref, RX VrefLevel [Byte0]: 52
3398 01:24:29.331017 [Byte1]: 52
3399 01:24:29.335598
3400 01:24:29.335722 Set Vref, RX VrefLevel [Byte0]: 53
3401 01:24:29.339494 [Byte1]: 53
3402 01:24:29.343979
3403 01:24:29.344063 Set Vref, RX VrefLevel [Byte0]: 54
3404 01:24:29.347231 [Byte1]: 54
3405 01:24:29.351534
3406 01:24:29.351669 Set Vref, RX VrefLevel [Byte0]: 55
3407 01:24:29.355065 [Byte1]: 55
3408 01:24:29.359437
3409 01:24:29.359572 Set Vref, RX VrefLevel [Byte0]: 56
3410 01:24:29.362965 [Byte1]: 56
3411 01:24:29.367277
3412 01:24:29.367386 Set Vref, RX VrefLevel [Byte0]: 57
3413 01:24:29.371045 [Byte1]: 57
3414 01:24:29.375349
3415 01:24:29.375447 Set Vref, RX VrefLevel [Byte0]: 58
3416 01:24:29.378723 [Byte1]: 58
3417 01:24:29.383149
3418 01:24:29.383222 Set Vref, RX VrefLevel [Byte0]: 59
3419 01:24:29.386262 [Byte1]: 59
3420 01:24:29.391269
3421 01:24:29.391350 Set Vref, RX VrefLevel [Byte0]: 60
3422 01:24:29.394209 [Byte1]: 60
3423 01:24:29.399133
3424 01:24:29.399245 Set Vref, RX VrefLevel [Byte0]: 61
3425 01:24:29.402030 [Byte1]: 61
3426 01:24:29.406512
3427 01:24:29.406617 Set Vref, RX VrefLevel [Byte0]: 62
3428 01:24:29.410135 [Byte1]: 62
3429 01:24:29.414762
3430 01:24:29.414884 Set Vref, RX VrefLevel [Byte0]: 63
3431 01:24:29.417837 [Byte1]: 63
3432 01:24:29.422473
3433 01:24:29.422583 Set Vref, RX VrefLevel [Byte0]: 64
3434 01:24:29.425871 [Byte1]: 64
3435 01:24:29.430559
3436 01:24:29.430645 Set Vref, RX VrefLevel [Byte0]: 65
3437 01:24:29.433662 [Byte1]: 65
3438 01:24:29.438764
3439 01:24:29.438898 Set Vref, RX VrefLevel [Byte0]: 66
3440 01:24:29.441411 [Byte1]: 66
3441 01:24:29.446134
3442 01:24:29.446216 Final RX Vref Byte 0 = 50 to rank0
3443 01:24:29.449371 Final RX Vref Byte 1 = 52 to rank0
3444 01:24:29.452720 Final RX Vref Byte 0 = 50 to rank1
3445 01:24:29.456347 Final RX Vref Byte 1 = 52 to rank1==
3446 01:24:29.459315 Dram Type= 6, Freq= 0, CH_1, rank 0
3447 01:24:29.466094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 01:24:29.466206 ==
3449 01:24:29.466274 DQS Delay:
3450 01:24:29.466336 DQS0 = 0, DQS1 = 0
3451 01:24:29.469282 DQM Delay:
3452 01:24:29.469370 DQM0 = 115, DQM1 = 113
3453 01:24:29.472764 DQ Delay:
3454 01:24:29.476277 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3455 01:24:29.480063 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3456 01:24:29.482939 DQ8 =98, DQ9 =102, DQ10 =116, DQ11 =106
3457 01:24:29.486142 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3458 01:24:29.486225
3459 01:24:29.486292
3460 01:24:29.492927 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3461 01:24:29.496789 CH1 RK0: MR19=303, MR18=F2FF
3462 01:24:29.502510 CH1_RK0: MR19=0x303, MR18=0xF2FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3463 01:24:29.502601
3464 01:24:29.506495 ----->DramcWriteLeveling(PI) begin...
3465 01:24:29.506580 ==
3466 01:24:29.509046 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 01:24:29.515843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3468 01:24:29.516001 ==
3469 01:24:29.519059 Write leveling (Byte 0): 26 => 26
3470 01:24:29.519204 Write leveling (Byte 1): 30 => 30
3471 01:24:29.522501 DramcWriteLeveling(PI) end<-----
3472 01:24:29.522614
3473 01:24:29.522707 ==
3474 01:24:29.525706 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 01:24:29.532682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 01:24:29.532763 ==
3477 01:24:29.535916 [Gating] SW mode calibration
3478 01:24:29.542647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3479 01:24:29.545609 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3480 01:24:29.552705 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3481 01:24:29.555484 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 01:24:29.559289 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 01:24:29.565455 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 01:24:29.568883 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 01:24:29.572064 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3486 01:24:29.578992 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
3487 01:24:29.581845 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3488 01:24:29.586247 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 01:24:29.592279 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 01:24:29.595481 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 01:24:29.598711 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 01:24:29.605822 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 01:24:29.608733 1 0 20 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
3494 01:24:29.612080 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3495 01:24:29.618144 1 0 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
3496 01:24:29.621604 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 01:24:29.625139 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 01:24:29.631785 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 01:24:29.634811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 01:24:29.638045 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 01:24:29.645084 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 01:24:29.647857 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3503 01:24:29.651470 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3504 01:24:29.658071 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 01:24:29.661243 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 01:24:29.664822 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 01:24:29.671660 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 01:24:29.674372 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 01:24:29.677848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 01:24:29.684295 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 01:24:29.688120 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 01:24:29.691133 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 01:24:29.697331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 01:24:29.701020 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 01:24:29.703935 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 01:24:29.710986 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 01:24:29.714352 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3518 01:24:29.717184 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3519 01:24:29.720451 Total UI for P1: 0, mck2ui 16
3520 01:24:29.723978 best dqsien dly found for B0: ( 1, 3, 20)
3521 01:24:29.727160 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3522 01:24:29.734165 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 01:24:29.737329 Total UI for P1: 0, mck2ui 16
3524 01:24:29.740585 best dqsien dly found for B1: ( 1, 3, 26)
3525 01:24:29.743958 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3526 01:24:29.747385 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3527 01:24:29.747470
3528 01:24:29.750858 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3529 01:24:29.753559 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3530 01:24:29.756862 [Gating] SW calibration Done
3531 01:24:29.756947 ==
3532 01:24:29.760174 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 01:24:29.763981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 01:24:29.764076 ==
3535 01:24:29.766584 RX Vref Scan: 0
3536 01:24:29.766684
3537 01:24:29.770192 RX Vref 0 -> 0, step: 1
3538 01:24:29.770294
3539 01:24:29.770385 RX Delay -40 -> 252, step: 8
3540 01:24:29.776860 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3541 01:24:29.779819 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3542 01:24:29.783537 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3543 01:24:29.786789 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3544 01:24:29.793008 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3545 01:24:29.796508 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3546 01:24:29.799978 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3547 01:24:29.803697 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3548 01:24:29.806478 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3549 01:24:29.809913 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3550 01:24:29.816710 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3551 01:24:29.819759 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3552 01:24:29.823301 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3553 01:24:29.825930 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3554 01:24:29.833279 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3555 01:24:29.836133 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3556 01:24:29.836211 ==
3557 01:24:29.839414 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 01:24:29.842812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 01:24:29.842914 ==
3560 01:24:29.846395 DQS Delay:
3561 01:24:29.846496 DQS0 = 0, DQS1 = 0
3562 01:24:29.846594 DQM Delay:
3563 01:24:29.849257 DQM0 = 115, DQM1 = 111
3564 01:24:29.849340 DQ Delay:
3565 01:24:29.852518 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3566 01:24:29.856213 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =111
3567 01:24:29.859294 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3568 01:24:29.865841 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3569 01:24:29.865949
3570 01:24:29.866041
3571 01:24:29.866133 ==
3572 01:24:29.869412 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 01:24:29.872387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 01:24:29.872491 ==
3575 01:24:29.872587
3576 01:24:29.872676
3577 01:24:29.875749 TX Vref Scan disable
3578 01:24:29.875849 == TX Byte 0 ==
3579 01:24:29.881919 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3580 01:24:29.885766 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3581 01:24:29.888910 == TX Byte 1 ==
3582 01:24:29.891863 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3583 01:24:29.895169 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3584 01:24:29.895271 ==
3585 01:24:29.898433 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 01:24:29.902004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 01:24:29.905029 ==
3588 01:24:29.915126 TX Vref=22, minBit 10, minWin=25, winSum=417
3589 01:24:29.918549 TX Vref=24, minBit 10, minWin=25, winSum=419
3590 01:24:29.922218 TX Vref=26, minBit 10, minWin=25, winSum=420
3591 01:24:29.925288 TX Vref=28, minBit 3, minWin=26, winSum=426
3592 01:24:29.928354 TX Vref=30, minBit 1, minWin=26, winSum=425
3593 01:24:29.934748 TX Vref=32, minBit 1, minWin=26, winSum=426
3594 01:24:29.938400 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 28
3595 01:24:29.941819
3596 01:24:29.941899 Final TX Range 1 Vref 28
3597 01:24:29.941963
3598 01:24:29.942036 ==
3599 01:24:29.944954 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 01:24:29.951337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 01:24:29.951417 ==
3602 01:24:29.951518
3603 01:24:29.951578
3604 01:24:29.951635 TX Vref Scan disable
3605 01:24:29.955217 == TX Byte 0 ==
3606 01:24:29.958475 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3607 01:24:29.965340 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3608 01:24:29.965446 == TX Byte 1 ==
3609 01:24:29.968598 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3610 01:24:29.975273 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3611 01:24:29.975377
3612 01:24:29.975467 [DATLAT]
3613 01:24:29.975556 Freq=1200, CH1 RK1
3614 01:24:29.975643
3615 01:24:29.978015 DATLAT Default: 0xd
3616 01:24:29.981331 0, 0xFFFF, sum = 0
3617 01:24:29.981435 1, 0xFFFF, sum = 0
3618 01:24:29.984785 2, 0xFFFF, sum = 0
3619 01:24:29.984887 3, 0xFFFF, sum = 0
3620 01:24:29.987955 4, 0xFFFF, sum = 0
3621 01:24:29.988057 5, 0xFFFF, sum = 0
3622 01:24:29.991686 6, 0xFFFF, sum = 0
3623 01:24:29.991788 7, 0xFFFF, sum = 0
3624 01:24:29.994447 8, 0xFFFF, sum = 0
3625 01:24:29.994543 9, 0xFFFF, sum = 0
3626 01:24:29.997800 10, 0xFFFF, sum = 0
3627 01:24:29.997899 11, 0xFFFF, sum = 0
3628 01:24:30.001087 12, 0x0, sum = 1
3629 01:24:30.001188 13, 0x0, sum = 2
3630 01:24:30.004556 14, 0x0, sum = 3
3631 01:24:30.004656 15, 0x0, sum = 4
3632 01:24:30.007460 best_step = 13
3633 01:24:30.007559
3634 01:24:30.007649 ==
3635 01:24:30.010765 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 01:24:30.014255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 01:24:30.014352 ==
3638 01:24:30.017662 RX Vref Scan: 0
3639 01:24:30.017757
3640 01:24:30.017846 RX Vref 0 -> 0, step: 1
3641 01:24:30.017934
3642 01:24:30.021180 RX Delay -13 -> 252, step: 4
3643 01:24:30.028144 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3644 01:24:30.030762 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3645 01:24:30.034398 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3646 01:24:30.037405 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3647 01:24:30.043941 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3648 01:24:30.047286 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3649 01:24:30.050530 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3650 01:24:30.053836 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3651 01:24:30.057464 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3652 01:24:30.063630 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3653 01:24:30.066923 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3654 01:24:30.070310 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3655 01:24:30.073393 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3656 01:24:30.076712 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3657 01:24:30.084009 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3658 01:24:30.086932 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3659 01:24:30.087014 ==
3660 01:24:30.090619 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 01:24:30.093597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 01:24:30.093681 ==
3663 01:24:30.097306 DQS Delay:
3664 01:24:30.097389 DQS0 = 0, DQS1 = 0
3665 01:24:30.097475 DQM Delay:
3666 01:24:30.100294 DQM0 = 114, DQM1 = 112
3667 01:24:30.100377 DQ Delay:
3668 01:24:30.103467 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3669 01:24:30.106951 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3670 01:24:30.114004 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3671 01:24:30.116950 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3672 01:24:30.117033
3673 01:24:30.117117
3674 01:24:30.123463 [DQSOSCAuto] RK1, (LSB)MR18= 0xf608, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3675 01:24:30.126243 CH1 RK1: MR19=304, MR18=F608
3676 01:24:30.133326 CH1_RK1: MR19=0x304, MR18=0xF608, DQSOSC=406, MR23=63, INC=39, DEC=26
3677 01:24:30.136722 [RxdqsGatingPostProcess] freq 1200
3678 01:24:30.143106 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3679 01:24:30.143203 best DQS0 dly(2T, 0.5T) = (0, 11)
3680 01:24:30.146441 best DQS1 dly(2T, 0.5T) = (0, 11)
3681 01:24:30.149364 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3682 01:24:30.152866 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3683 01:24:30.155869 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 01:24:30.159395 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 01:24:30.162764 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 01:24:30.166233 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 01:24:30.169104 Pre-setting of DQS Precalculation
3688 01:24:30.175735 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3689 01:24:30.182226 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3690 01:24:30.188790 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3691 01:24:30.188874
3692 01:24:30.188958
3693 01:24:30.192820 [Calibration Summary] 2400 Mbps
3694 01:24:30.192904 CH 0, Rank 0
3695 01:24:30.195550 SW Impedance : PASS
3696 01:24:30.198602 DUTY Scan : NO K
3697 01:24:30.198700 ZQ Calibration : PASS
3698 01:24:30.201851 Jitter Meter : NO K
3699 01:24:30.205667 CBT Training : PASS
3700 01:24:30.205775 Write leveling : PASS
3701 01:24:30.208673 RX DQS gating : PASS
3702 01:24:30.212115 RX DQ/DQS(RDDQC) : PASS
3703 01:24:30.212190 TX DQ/DQS : PASS
3704 01:24:30.215758 RX DATLAT : PASS
3705 01:24:30.218622 RX DQ/DQS(Engine): PASS
3706 01:24:30.218725 TX OE : NO K
3707 01:24:30.218816 All Pass.
3708 01:24:30.222092
3709 01:24:30.222186 CH 0, Rank 1
3710 01:24:30.225395 SW Impedance : PASS
3711 01:24:30.225470 DUTY Scan : NO K
3712 01:24:30.228397 ZQ Calibration : PASS
3713 01:24:30.231807 Jitter Meter : NO K
3714 01:24:30.231934 CBT Training : PASS
3715 01:24:30.235318 Write leveling : PASS
3716 01:24:30.235414 RX DQS gating : PASS
3717 01:24:30.238663 RX DQ/DQS(RDDQC) : PASS
3718 01:24:30.242051 TX DQ/DQS : PASS
3719 01:24:30.242147 RX DATLAT : PASS
3720 01:24:30.245423 RX DQ/DQS(Engine): PASS
3721 01:24:30.248356 TX OE : NO K
3722 01:24:30.248472 All Pass.
3723 01:24:30.248610
3724 01:24:30.248701 CH 1, Rank 0
3725 01:24:30.251772 SW Impedance : PASS
3726 01:24:30.254849 DUTY Scan : NO K
3727 01:24:30.254929 ZQ Calibration : PASS
3728 01:24:30.258434 Jitter Meter : NO K
3729 01:24:30.261817 CBT Training : PASS
3730 01:24:30.261911 Write leveling : PASS
3731 01:24:30.264869 RX DQS gating : PASS
3732 01:24:30.267834 RX DQ/DQS(RDDQC) : PASS
3733 01:24:30.267924 TX DQ/DQS : PASS
3734 01:24:30.271325 RX DATLAT : PASS
3735 01:24:30.274657 RX DQ/DQS(Engine): PASS
3736 01:24:30.274766 TX OE : NO K
3737 01:24:30.278007 All Pass.
3738 01:24:30.278103
3739 01:24:30.278197 CH 1, Rank 1
3740 01:24:30.281231 SW Impedance : PASS
3741 01:24:30.281337 DUTY Scan : NO K
3742 01:24:30.284272 ZQ Calibration : PASS
3743 01:24:30.287632 Jitter Meter : NO K
3744 01:24:30.287734 CBT Training : PASS
3745 01:24:30.290809 Write leveling : PASS
3746 01:24:30.294441 RX DQS gating : PASS
3747 01:24:30.294543 RX DQ/DQS(RDDQC) : PASS
3748 01:24:30.297571 TX DQ/DQS : PASS
3749 01:24:30.300777 RX DATLAT : PASS
3750 01:24:30.300924 RX DQ/DQS(Engine): PASS
3751 01:24:30.303778 TX OE : NO K
3752 01:24:30.303880 All Pass.
3753 01:24:30.303996
3754 01:24:30.307235 DramC Write-DBI off
3755 01:24:30.310565 PER_BANK_REFRESH: Hybrid Mode
3756 01:24:30.310666 TX_TRACKING: ON
3757 01:24:30.320686 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3758 01:24:30.323702 [FAST_K] Save calibration result to emmc
3759 01:24:30.327663 dramc_set_vcore_voltage set vcore to 650000
3760 01:24:30.331236 Read voltage for 600, 5
3761 01:24:30.331336 Vio18 = 0
3762 01:24:30.331437 Vcore = 650000
3763 01:24:30.333750 Vdram = 0
3764 01:24:30.333849 Vddq = 0
3765 01:24:30.333936 Vmddr = 0
3766 01:24:30.340541 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3767 01:24:30.343872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3768 01:24:30.347207 MEM_TYPE=3, freq_sel=19
3769 01:24:30.350371 sv_algorithm_assistance_LP4_1600
3770 01:24:30.353596 ============ PULL DRAM RESETB DOWN ============
3771 01:24:30.360244 ========== PULL DRAM RESETB DOWN end =========
3772 01:24:30.363254 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3773 01:24:30.366913 ===================================
3774 01:24:30.369816 LPDDR4 DRAM CONFIGURATION
3775 01:24:30.373248 ===================================
3776 01:24:30.373348 EX_ROW_EN[0] = 0x0
3777 01:24:30.376904 EX_ROW_EN[1] = 0x0
3778 01:24:30.377006 LP4Y_EN = 0x0
3779 01:24:30.380088 WORK_FSP = 0x0
3780 01:24:30.380165 WL = 0x2
3781 01:24:30.383467 RL = 0x2
3782 01:24:30.383567 BL = 0x2
3783 01:24:30.386984 RPST = 0x0
3784 01:24:30.387084 RD_PRE = 0x0
3785 01:24:30.389397 WR_PRE = 0x1
3786 01:24:30.393063 WR_PST = 0x0
3787 01:24:30.393168 DBI_WR = 0x0
3788 01:24:30.396337 DBI_RD = 0x0
3789 01:24:30.396438 OTF = 0x1
3790 01:24:30.400001 ===================================
3791 01:24:30.402622 ===================================
3792 01:24:30.406594 ANA top config
3793 01:24:30.409674 ===================================
3794 01:24:30.409773 DLL_ASYNC_EN = 0
3795 01:24:30.412772 ALL_SLAVE_EN = 1
3796 01:24:30.416024 NEW_RANK_MODE = 1
3797 01:24:30.419380 DLL_IDLE_MODE = 1
3798 01:24:30.419480 LP45_APHY_COMB_EN = 1
3799 01:24:30.423134 TX_ODT_DIS = 1
3800 01:24:30.426307 NEW_8X_MODE = 1
3801 01:24:30.429143 ===================================
3802 01:24:30.432509 ===================================
3803 01:24:30.435923 data_rate = 1200
3804 01:24:30.439444 CKR = 1
3805 01:24:30.442478 DQ_P2S_RATIO = 8
3806 01:24:30.445531 ===================================
3807 01:24:30.445653 CA_P2S_RATIO = 8
3808 01:24:30.449016 DQ_CA_OPEN = 0
3809 01:24:30.452434 DQ_SEMI_OPEN = 0
3810 01:24:30.456055 CA_SEMI_OPEN = 0
3811 01:24:30.458979 CA_FULL_RATE = 0
3812 01:24:30.462137 DQ_CKDIV4_EN = 1
3813 01:24:30.462234 CA_CKDIV4_EN = 1
3814 01:24:30.465748 CA_PREDIV_EN = 0
3815 01:24:30.469929 PH8_DLY = 0
3816 01:24:30.472164 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3817 01:24:30.475514 DQ_AAMCK_DIV = 4
3818 01:24:30.479020 CA_AAMCK_DIV = 4
3819 01:24:30.479110 CA_ADMCK_DIV = 4
3820 01:24:30.482199 DQ_TRACK_CA_EN = 0
3821 01:24:30.485391 CA_PICK = 600
3822 01:24:30.488385 CA_MCKIO = 600
3823 01:24:30.491829 MCKIO_SEMI = 0
3824 01:24:30.495279 PLL_FREQ = 2288
3825 01:24:30.498739 DQ_UI_PI_RATIO = 32
3826 01:24:30.498858 CA_UI_PI_RATIO = 0
3827 01:24:30.501853 ===================================
3828 01:24:30.505354 ===================================
3829 01:24:30.508433 memory_type:LPDDR4
3830 01:24:30.511951 GP_NUM : 10
3831 01:24:30.512050 SRAM_EN : 1
3832 01:24:30.514746 MD32_EN : 0
3833 01:24:30.518142 ===================================
3834 01:24:30.521378 [ANA_INIT] >>>>>>>>>>>>>>
3835 01:24:30.524985 <<<<<< [CONFIGURE PHASE]: ANA_TX
3836 01:24:30.528338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3837 01:24:30.531377 ===================================
3838 01:24:30.535125 data_rate = 1200,PCW = 0X5800
3839 01:24:30.538039 ===================================
3840 01:24:30.541619 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3841 01:24:30.545596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 01:24:30.551489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 01:24:30.554684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3844 01:24:30.557736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3845 01:24:30.561237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3846 01:24:30.564095 [ANA_INIT] flow start
3847 01:24:30.567401 [ANA_INIT] PLL >>>>>>>>
3848 01:24:30.567477 [ANA_INIT] PLL <<<<<<<<
3849 01:24:30.570814 [ANA_INIT] MIDPI >>>>>>>>
3850 01:24:30.574032 [ANA_INIT] MIDPI <<<<<<<<
3851 01:24:30.577264 [ANA_INIT] DLL >>>>>>>>
3852 01:24:30.577337 [ANA_INIT] flow end
3853 01:24:30.580864 ============ LP4 DIFF to SE enter ============
3854 01:24:30.587153 ============ LP4 DIFF to SE exit ============
3855 01:24:30.587231 [ANA_INIT] <<<<<<<<<<<<<
3856 01:24:30.590511 [Flow] Enable top DCM control >>>>>
3857 01:24:30.594053 [Flow] Enable top DCM control <<<<<
3858 01:24:30.596896 Enable DLL master slave shuffle
3859 01:24:30.603891 ==============================================================
3860 01:24:30.604030 Gating Mode config
3861 01:24:30.610698 ==============================================================
3862 01:24:30.613796 Config description:
3863 01:24:30.623248 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3864 01:24:30.629839 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3865 01:24:30.633550 SELPH_MODE 0: By rank 1: By Phase
3866 01:24:30.639716 ==============================================================
3867 01:24:30.642995 GAT_TRACK_EN = 1
3868 01:24:30.646171 RX_GATING_MODE = 2
3869 01:24:30.649662 RX_GATING_TRACK_MODE = 2
3870 01:24:30.653236 SELPH_MODE = 1
3871 01:24:30.653308 PICG_EARLY_EN = 1
3872 01:24:30.656514 VALID_LAT_VALUE = 1
3873 01:24:30.663066 ==============================================================
3874 01:24:30.666476 Enter into Gating configuration >>>>
3875 01:24:30.669461 Exit from Gating configuration <<<<
3876 01:24:30.673096 Enter into DVFS_PRE_config >>>>>
3877 01:24:30.683251 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3878 01:24:30.685885 Exit from DVFS_PRE_config <<<<<
3879 01:24:30.689282 Enter into PICG configuration >>>>
3880 01:24:30.692789 Exit from PICG configuration <<<<
3881 01:24:30.696045 [RX_INPUT] configuration >>>>>
3882 01:24:30.699586 [RX_INPUT] configuration <<<<<
3883 01:24:30.705553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3884 01:24:30.708873 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3885 01:24:30.715577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3886 01:24:30.722379 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3887 01:24:30.728483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3888 01:24:30.735526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3889 01:24:30.738578 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3890 01:24:30.742053 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3891 01:24:30.744890 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3892 01:24:30.752085 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3893 01:24:30.755217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3894 01:24:30.758209 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 01:24:30.761542 ===================================
3896 01:24:30.765091 LPDDR4 DRAM CONFIGURATION
3897 01:24:30.768151 ===================================
3898 01:24:30.771580 EX_ROW_EN[0] = 0x0
3899 01:24:30.771679 EX_ROW_EN[1] = 0x0
3900 01:24:30.774807 LP4Y_EN = 0x0
3901 01:24:30.774900 WORK_FSP = 0x0
3902 01:24:30.777953 WL = 0x2
3903 01:24:30.778051 RL = 0x2
3904 01:24:30.781521 BL = 0x2
3905 01:24:30.781594 RPST = 0x0
3906 01:24:30.784542 RD_PRE = 0x0
3907 01:24:30.784653 WR_PRE = 0x1
3908 01:24:30.788089 WR_PST = 0x0
3909 01:24:30.788205 DBI_WR = 0x0
3910 01:24:30.791400 DBI_RD = 0x0
3911 01:24:30.791521 OTF = 0x1
3912 01:24:30.794752 ===================================
3913 01:24:30.800934 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3914 01:24:30.804468 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3915 01:24:30.807679 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 01:24:30.811238 ===================================
3917 01:24:30.814869 LPDDR4 DRAM CONFIGURATION
3918 01:24:30.817409 ===================================
3919 01:24:30.820781 EX_ROW_EN[0] = 0x10
3920 01:24:30.820864 EX_ROW_EN[1] = 0x0
3921 01:24:30.824723 LP4Y_EN = 0x0
3922 01:24:30.824824 WORK_FSP = 0x0
3923 01:24:30.827541 WL = 0x2
3924 01:24:30.827650 RL = 0x2
3925 01:24:30.831113 BL = 0x2
3926 01:24:30.831212 RPST = 0x0
3927 01:24:30.834020 RD_PRE = 0x0
3928 01:24:30.834124 WR_PRE = 0x1
3929 01:24:30.837135 WR_PST = 0x0
3930 01:24:30.837212 DBI_WR = 0x0
3931 01:24:30.840472 DBI_RD = 0x0
3932 01:24:30.840544 OTF = 0x1
3933 01:24:30.844196 ===================================
3934 01:24:30.850959 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3935 01:24:30.855688 nWR fixed to 30
3936 01:24:30.858596 [ModeRegInit_LP4] CH0 RK0
3937 01:24:30.858714 [ModeRegInit_LP4] CH0 RK1
3938 01:24:30.862215 [ModeRegInit_LP4] CH1 RK0
3939 01:24:30.865274 [ModeRegInit_LP4] CH1 RK1
3940 01:24:30.865390 match AC timing 17
3941 01:24:30.872206 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3942 01:24:30.875033 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3943 01:24:30.878365 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3944 01:24:30.884996 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3945 01:24:30.888859 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3946 01:24:30.888977 ==
3947 01:24:30.891506 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 01:24:30.894894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 01:24:30.895013 ==
3950 01:24:30.901724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 01:24:30.907965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3952 01:24:30.911330 [CA 0] Center 36 (5~67) winsize 63
3953 01:24:30.914943 [CA 1] Center 35 (5~66) winsize 62
3954 01:24:30.917851 [CA 2] Center 34 (4~65) winsize 62
3955 01:24:30.921468 [CA 3] Center 34 (4~65) winsize 62
3956 01:24:30.924987 [CA 4] Center 33 (3~64) winsize 62
3957 01:24:30.928058 [CA 5] Center 33 (2~64) winsize 63
3958 01:24:30.928157
3959 01:24:30.931235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3960 01:24:30.931333
3961 01:24:30.934956 [CATrainingPosCal] consider 1 rank data
3962 01:24:30.937550 u2DelayCellTimex100 = 270/100 ps
3963 01:24:30.941230 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3964 01:24:30.944322 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3965 01:24:30.947715 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 01:24:30.954260 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 01:24:30.957697 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 01:24:30.960620 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3969 01:24:30.960720
3970 01:24:30.964132 CA PerBit enable=1, Macro0, CA PI delay=33
3971 01:24:30.964231
3972 01:24:30.967673 [CBTSetCACLKResult] CA Dly = 33
3973 01:24:30.967793 CS Dly: 5 (0~36)
3974 01:24:30.967886 ==
3975 01:24:30.970736 Dram Type= 6, Freq= 0, CH_0, rank 1
3976 01:24:30.977204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 01:24:30.977307 ==
3978 01:24:30.981293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3979 01:24:30.987191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3980 01:24:30.990791 [CA 0] Center 36 (6~67) winsize 62
3981 01:24:30.994450 [CA 1] Center 36 (6~67) winsize 62
3982 01:24:30.997495 [CA 2] Center 34 (4~65) winsize 62
3983 01:24:31.000850 [CA 3] Center 34 (4~65) winsize 62
3984 01:24:31.004031 [CA 4] Center 34 (3~65) winsize 63
3985 01:24:31.007277 [CA 5] Center 33 (3~64) winsize 62
3986 01:24:31.007390
3987 01:24:31.010353 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3988 01:24:31.010465
3989 01:24:31.013942 [CATrainingPosCal] consider 2 rank data
3990 01:24:31.016991 u2DelayCellTimex100 = 270/100 ps
3991 01:24:31.020229 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3992 01:24:31.026744 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3993 01:24:31.030364 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 01:24:31.033695 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 01:24:31.036653 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 01:24:31.040075 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 01:24:31.040190
3998 01:24:31.043403 CA PerBit enable=1, Macro0, CA PI delay=33
3999 01:24:31.043496
4000 01:24:31.047040 [CBTSetCACLKResult] CA Dly = 33
4001 01:24:31.050124 CS Dly: 5 (0~37)
4002 01:24:31.050226
4003 01:24:31.053595 ----->DramcWriteLeveling(PI) begin...
4004 01:24:31.053694 ==
4005 01:24:31.056719 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 01:24:31.060272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 01:24:31.060370 ==
4008 01:24:31.063455 Write leveling (Byte 0): 34 => 34
4009 01:24:31.066912 Write leveling (Byte 1): 30 => 30
4010 01:24:31.070089 DramcWriteLeveling(PI) end<-----
4011 01:24:31.070187
4012 01:24:31.070277 ==
4013 01:24:31.073760 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 01:24:31.076951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 01:24:31.077079 ==
4016 01:24:31.079774 [Gating] SW mode calibration
4017 01:24:31.086420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4018 01:24:31.093271 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4019 01:24:31.096355 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 01:24:31.099939 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 01:24:31.106671 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4022 01:24:31.109633 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4023 01:24:31.113681 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
4024 01:24:31.119514 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 01:24:31.123604 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 01:24:31.125824 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 01:24:31.132358 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 01:24:31.136639 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 01:24:31.139733 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 01:24:31.145740 0 10 12 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
4031 01:24:31.149115 0 10 16 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
4032 01:24:31.152221 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 01:24:31.159056 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 01:24:31.162635 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 01:24:31.165477 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 01:24:31.172110 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 01:24:31.175331 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4038 01:24:31.178695 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 01:24:31.185186 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4040 01:24:31.189022 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 01:24:31.192266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 01:24:31.198849 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 01:24:31.201850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 01:24:31.205324 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 01:24:31.211767 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 01:24:31.215165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 01:24:31.218194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 01:24:31.225148 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 01:24:31.228188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 01:24:31.232019 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 01:24:31.238192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 01:24:31.241465 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 01:24:31.244713 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 01:24:31.251471 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4055 01:24:31.255041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4056 01:24:31.257932 Total UI for P1: 0, mck2ui 16
4057 01:24:31.261734 best dqsien dly found for B0: ( 0, 13, 12)
4058 01:24:31.265167 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 01:24:31.267703 Total UI for P1: 0, mck2ui 16
4060 01:24:31.271574 best dqsien dly found for B1: ( 0, 13, 16)
4061 01:24:31.274965 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4062 01:24:31.277889 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4063 01:24:31.277981
4064 01:24:31.284561 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4065 01:24:31.288167 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4066 01:24:31.291041 [Gating] SW calibration Done
4067 01:24:31.291144 ==
4068 01:24:31.294157 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 01:24:31.297541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 01:24:31.297640 ==
4071 01:24:31.297729 RX Vref Scan: 0
4072 01:24:31.300784
4073 01:24:31.300871 RX Vref 0 -> 0, step: 1
4074 01:24:31.300967
4075 01:24:31.304578 RX Delay -230 -> 252, step: 16
4076 01:24:31.307473 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4077 01:24:31.314887 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4078 01:24:31.318436 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4079 01:24:31.320712 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4080 01:24:31.324236 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4081 01:24:31.327432 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4082 01:24:31.333870 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4083 01:24:31.337493 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4084 01:24:31.340347 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4085 01:24:31.343765 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4086 01:24:31.350234 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4087 01:24:31.353654 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4088 01:24:31.356987 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4089 01:24:31.360216 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4090 01:24:31.366925 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4091 01:24:31.369850 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4092 01:24:31.369930 ==
4093 01:24:31.373582 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 01:24:31.376509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 01:24:31.376581 ==
4096 01:24:31.379837 DQS Delay:
4097 01:24:31.379951 DQS0 = 0, DQS1 = 0
4098 01:24:31.383003 DQM Delay:
4099 01:24:31.383107 DQM0 = 46, DQM1 = 36
4100 01:24:31.383195 DQ Delay:
4101 01:24:31.386255 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4102 01:24:31.390063 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4103 01:24:31.392831 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4104 01:24:31.396514 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4105 01:24:31.396586
4106 01:24:31.396647
4107 01:24:31.400016 ==
4108 01:24:31.400087 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 01:24:31.406500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 01:24:31.406600 ==
4111 01:24:31.406690
4112 01:24:31.406774
4113 01:24:31.409565 TX Vref Scan disable
4114 01:24:31.409636 == TX Byte 0 ==
4115 01:24:31.415807 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4116 01:24:31.419367 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4117 01:24:31.419463 == TX Byte 1 ==
4118 01:24:31.426218 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4119 01:24:31.429984 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4120 01:24:31.430078 ==
4121 01:24:31.433366 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 01:24:31.435670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 01:24:31.435764 ==
4124 01:24:31.435852
4125 01:24:31.435973
4126 01:24:31.439106 TX Vref Scan disable
4127 01:24:31.442807 == TX Byte 0 ==
4128 01:24:31.445510 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4129 01:24:31.449063 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4130 01:24:31.452749 == TX Byte 1 ==
4131 01:24:31.455575 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4132 01:24:31.459524 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4133 01:24:31.462652
4134 01:24:31.462750 [DATLAT]
4135 01:24:31.462839 Freq=600, CH0 RK0
4136 01:24:31.462929
4137 01:24:31.465516 DATLAT Default: 0x9
4138 01:24:31.465613 0, 0xFFFF, sum = 0
4139 01:24:31.468726 1, 0xFFFF, sum = 0
4140 01:24:31.468800 2, 0xFFFF, sum = 0
4141 01:24:31.472246 3, 0xFFFF, sum = 0
4142 01:24:31.472316 4, 0xFFFF, sum = 0
4143 01:24:31.475525 5, 0xFFFF, sum = 0
4144 01:24:31.478595 6, 0xFFFF, sum = 0
4145 01:24:31.478706 7, 0xFFFF, sum = 0
4146 01:24:31.482195 8, 0x0, sum = 1
4147 01:24:31.482300 9, 0x0, sum = 2
4148 01:24:31.482391 10, 0x0, sum = 3
4149 01:24:31.486092 11, 0x0, sum = 4
4150 01:24:31.486189 best_step = 9
4151 01:24:31.486276
4152 01:24:31.486362 ==
4153 01:24:31.488497 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 01:24:31.495245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 01:24:31.495347 ==
4156 01:24:31.495441 RX Vref Scan: 1
4157 01:24:31.495528
4158 01:24:31.498758 RX Vref 0 -> 0, step: 1
4159 01:24:31.498862
4160 01:24:31.502188 RX Delay -179 -> 252, step: 8
4161 01:24:31.502282
4162 01:24:31.504963 Set Vref, RX VrefLevel [Byte0]: 51
4163 01:24:31.508267 [Byte1]: 59
4164 01:24:31.508362
4165 01:24:31.511713 Final RX Vref Byte 0 = 51 to rank0
4166 01:24:31.514609 Final RX Vref Byte 1 = 59 to rank0
4167 01:24:31.518042 Final RX Vref Byte 0 = 51 to rank1
4168 01:24:31.521680 Final RX Vref Byte 1 = 59 to rank1==
4169 01:24:31.525021 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 01:24:31.528287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 01:24:31.528360 ==
4172 01:24:31.531550 DQS Delay:
4173 01:24:31.531648 DQS0 = 0, DQS1 = 0
4174 01:24:31.535504 DQM Delay:
4175 01:24:31.535610 DQM0 = 41, DQM1 = 33
4176 01:24:31.535701 DQ Delay:
4177 01:24:31.538534 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4178 01:24:31.541708 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4179 01:24:31.544910 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4180 01:24:31.548072 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4181 01:24:31.548144
4182 01:24:31.548218
4183 01:24:31.557808 [DQSOSCAuto] RK0, (LSB)MR18= 0x5249, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4184 01:24:31.561434 CH0 RK0: MR19=808, MR18=5249
4185 01:24:31.567792 CH0_RK0: MR19=0x808, MR18=0x5249, DQSOSC=394, MR23=63, INC=168, DEC=112
4186 01:24:31.567894
4187 01:24:31.571052 ----->DramcWriteLeveling(PI) begin...
4188 01:24:31.571153 ==
4189 01:24:31.574372 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 01:24:31.578138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 01:24:31.578245 ==
4192 01:24:31.581094 Write leveling (Byte 0): 34 => 34
4193 01:24:31.584474 Write leveling (Byte 1): 29 => 29
4194 01:24:31.587497 DramcWriteLeveling(PI) end<-----
4195 01:24:31.587595
4196 01:24:31.587695 ==
4197 01:24:31.591671 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 01:24:31.594180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 01:24:31.594262 ==
4200 01:24:31.597635 [Gating] SW mode calibration
4201 01:24:31.604130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4202 01:24:31.610743 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4203 01:24:31.614475 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 01:24:31.617438 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 01:24:31.624227 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 01:24:31.627100 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (0 1) (0 0)
4207 01:24:31.630243 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
4208 01:24:31.637124 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 01:24:31.640475 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 01:24:31.643681 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 01:24:31.650679 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 01:24:31.653988 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 01:24:31.656761 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 01:24:31.663447 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4215 01:24:31.666479 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4216 01:24:31.670124 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 01:24:31.676602 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 01:24:31.679862 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 01:24:31.683015 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 01:24:31.689618 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 01:24:31.693062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 01:24:31.696808 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4223 01:24:31.702998 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 01:24:31.706203 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 01:24:31.709812 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 01:24:31.716330 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 01:24:31.719572 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 01:24:31.723081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 01:24:31.729373 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 01:24:31.732616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 01:24:31.736108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 01:24:31.742582 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 01:24:31.746302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 01:24:31.749210 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 01:24:31.756558 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 01:24:31.759066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 01:24:31.762815 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 01:24:31.769091 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4239 01:24:31.772580 Total UI for P1: 0, mck2ui 16
4240 01:24:31.775677 best dqsien dly found for B0: ( 0, 13, 10)
4241 01:24:31.778894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4242 01:24:31.782018 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 01:24:31.785863 Total UI for P1: 0, mck2ui 16
4244 01:24:31.788591 best dqsien dly found for B1: ( 0, 13, 14)
4245 01:24:31.792438 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4246 01:24:31.798602 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4247 01:24:31.798683
4248 01:24:31.802022 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4249 01:24:31.804987 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4250 01:24:31.808727 [Gating] SW calibration Done
4251 01:24:31.808821 ==
4252 01:24:31.811741 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 01:24:31.815093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 01:24:31.815174 ==
4255 01:24:31.818671 RX Vref Scan: 0
4256 01:24:31.818751
4257 01:24:31.818815 RX Vref 0 -> 0, step: 1
4258 01:24:31.818875
4259 01:24:31.821771 RX Delay -230 -> 252, step: 16
4260 01:24:31.825028 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4261 01:24:31.831635 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4262 01:24:31.835061 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4263 01:24:31.838210 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4264 01:24:31.841436 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4265 01:24:31.847801 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4266 01:24:31.851214 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4267 01:24:31.854292 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4268 01:24:31.857762 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4269 01:24:31.864389 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4270 01:24:31.867666 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4271 01:24:31.871173 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4272 01:24:31.874816 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4273 01:24:31.880799 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4274 01:24:31.884251 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4275 01:24:31.887685 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4276 01:24:31.887765 ==
4277 01:24:31.890912 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 01:24:31.894237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 01:24:31.894318 ==
4280 01:24:31.897433 DQS Delay:
4281 01:24:31.897513 DQS0 = 0, DQS1 = 0
4282 01:24:31.900767 DQM Delay:
4283 01:24:31.900847 DQM0 = 41, DQM1 = 32
4284 01:24:31.903945 DQ Delay:
4285 01:24:31.904055 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4286 01:24:31.907250 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4287 01:24:31.910814 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4288 01:24:31.913682 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4289 01:24:31.913779
4290 01:24:31.917001
4291 01:24:31.917081 ==
4292 01:24:31.920630 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 01:24:31.923885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 01:24:31.924004 ==
4295 01:24:31.924083
4296 01:24:31.924142
4297 01:24:31.927474 TX Vref Scan disable
4298 01:24:31.927554 == TX Byte 0 ==
4299 01:24:31.933618 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4300 01:24:31.936553 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4301 01:24:31.936671 == TX Byte 1 ==
4302 01:24:31.943388 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4303 01:24:31.946851 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4304 01:24:31.946950 ==
4305 01:24:31.949892 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 01:24:31.953445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 01:24:31.953545 ==
4308 01:24:31.953634
4309 01:24:31.956783
4310 01:24:31.956880 TX Vref Scan disable
4311 01:24:31.960372 == TX Byte 0 ==
4312 01:24:31.963911 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4313 01:24:31.970093 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4314 01:24:31.970194 == TX Byte 1 ==
4315 01:24:31.973955 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4316 01:24:31.980310 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4317 01:24:31.980383
4318 01:24:31.980444 [DATLAT]
4319 01:24:31.980505 Freq=600, CH0 RK1
4320 01:24:31.980566
4321 01:24:31.983444 DATLAT Default: 0x9
4322 01:24:31.986595 0, 0xFFFF, sum = 0
4323 01:24:31.986696 1, 0xFFFF, sum = 0
4324 01:24:31.989750 2, 0xFFFF, sum = 0
4325 01:24:31.989857 3, 0xFFFF, sum = 0
4326 01:24:31.993282 4, 0xFFFF, sum = 0
4327 01:24:31.993380 5, 0xFFFF, sum = 0
4328 01:24:31.996629 6, 0xFFFF, sum = 0
4329 01:24:31.996703 7, 0xFFFF, sum = 0
4330 01:24:31.999676 8, 0x0, sum = 1
4331 01:24:31.999787 9, 0x0, sum = 2
4332 01:24:32.002746 10, 0x0, sum = 3
4333 01:24:32.002847 11, 0x0, sum = 4
4334 01:24:32.002936 best_step = 9
4335 01:24:32.003031
4336 01:24:32.006350 ==
4337 01:24:32.009531 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 01:24:32.012922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 01:24:32.013022 ==
4340 01:24:32.013110 RX Vref Scan: 0
4341 01:24:32.013204
4342 01:24:32.016229 RX Vref 0 -> 0, step: 1
4343 01:24:32.016307
4344 01:24:32.019130 RX Delay -195 -> 252, step: 8
4345 01:24:32.025859 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4346 01:24:32.029243 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4347 01:24:32.032475 iDelay=197, Bit 2, Center 40 (-107 ~ 188) 296
4348 01:24:32.036264 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4349 01:24:32.039128 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4350 01:24:32.046291 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4351 01:24:32.049558 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4352 01:24:32.052629 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4353 01:24:32.055822 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4354 01:24:32.062700 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4355 01:24:32.065664 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4356 01:24:32.069010 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4357 01:24:32.072300 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4358 01:24:32.078888 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4359 01:24:32.082437 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4360 01:24:32.085173 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4361 01:24:32.085271 ==
4362 01:24:32.088712 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 01:24:32.091938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 01:24:32.095680 ==
4365 01:24:32.095760 DQS Delay:
4366 01:24:32.095823 DQS0 = 0, DQS1 = 0
4367 01:24:32.098698 DQM Delay:
4368 01:24:32.098776 DQM0 = 41, DQM1 = 33
4369 01:24:32.102260 DQ Delay:
4370 01:24:32.102339 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4371 01:24:32.104932 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4372 01:24:32.108910 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4373 01:24:32.111589 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4374 01:24:32.114894
4375 01:24:32.114974
4376 01:24:32.121366 [DQSOSCAuto] RK1, (LSB)MR18= 0x433e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4377 01:24:32.125111 CH0 RK1: MR19=808, MR18=433E
4378 01:24:32.131426 CH0_RK1: MR19=0x808, MR18=0x433E, DQSOSC=397, MR23=63, INC=166, DEC=110
4379 01:24:32.135074 [RxdqsGatingPostProcess] freq 600
4380 01:24:32.138107 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 01:24:32.141376 Pre-setting of DQS Precalculation
4382 01:24:32.147887 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 01:24:32.147993 ==
4384 01:24:32.150916 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 01:24:32.154269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 01:24:32.154351 ==
4387 01:24:32.160807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 01:24:32.167342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4389 01:24:32.170781 [CA 0] Center 35 (5~66) winsize 62
4390 01:24:32.174111 [CA 1] Center 35 (5~66) winsize 62
4391 01:24:32.177404 [CA 2] Center 35 (5~65) winsize 61
4392 01:24:32.180604 [CA 3] Center 34 (3~65) winsize 63
4393 01:24:32.184276 [CA 4] Center 34 (4~65) winsize 62
4394 01:24:32.187661 [CA 5] Center 34 (3~65) winsize 63
4395 01:24:32.187741
4396 01:24:32.191149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4397 01:24:32.191230
4398 01:24:32.194113 [CATrainingPosCal] consider 1 rank data
4399 01:24:32.197202 u2DelayCellTimex100 = 270/100 ps
4400 01:24:32.200749 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4401 01:24:32.204074 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4402 01:24:32.207256 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4403 01:24:32.210602 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4404 01:24:32.213821 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 01:24:32.217526 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4406 01:24:32.217624
4407 01:24:32.221345 CA PerBit enable=1, Macro0, CA PI delay=34
4408 01:24:32.223684
4409 01:24:32.223765 [CBTSetCACLKResult] CA Dly = 34
4410 01:24:32.227226 CS Dly: 4 (0~35)
4411 01:24:32.227307 ==
4412 01:24:32.230236 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 01:24:32.234105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 01:24:32.234187 ==
4415 01:24:32.240221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 01:24:32.246879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4417 01:24:32.250650 [CA 0] Center 36 (6~66) winsize 61
4418 01:24:32.253709 [CA 1] Center 35 (5~66) winsize 62
4419 01:24:32.257146 [CA 2] Center 34 (4~65) winsize 62
4420 01:24:32.260130 [CA 3] Center 34 (3~65) winsize 63
4421 01:24:32.263372 [CA 4] Center 34 (3~65) winsize 63
4422 01:24:32.267013 [CA 5] Center 33 (3~64) winsize 62
4423 01:24:32.267094
4424 01:24:32.269944 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4425 01:24:32.270024
4426 01:24:32.273219 [CATrainingPosCal] consider 2 rank data
4427 01:24:32.276866 u2DelayCellTimex100 = 270/100 ps
4428 01:24:32.280082 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4429 01:24:32.283045 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 01:24:32.286835 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4431 01:24:32.289807 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4432 01:24:32.293165 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 01:24:32.300072 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 01:24:32.300153
4435 01:24:32.303213 CA PerBit enable=1, Macro0, CA PI delay=33
4436 01:24:32.303294
4437 01:24:32.306384 [CBTSetCACLKResult] CA Dly = 33
4438 01:24:32.306465 CS Dly: 5 (0~37)
4439 01:24:32.306530
4440 01:24:32.309883 ----->DramcWriteLeveling(PI) begin...
4441 01:24:32.309966 ==
4442 01:24:32.313034 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 01:24:32.319413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 01:24:32.319496 ==
4445 01:24:32.322959 Write leveling (Byte 0): 31 => 31
4446 01:24:32.326203 Write leveling (Byte 1): 28 => 28
4447 01:24:32.326299 DramcWriteLeveling(PI) end<-----
4448 01:24:32.326365
4449 01:24:32.329239 ==
4450 01:24:32.332970 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 01:24:32.335854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 01:24:32.335962 ==
4453 01:24:32.339692 [Gating] SW mode calibration
4454 01:24:32.345879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 01:24:32.349455 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 01:24:32.356099 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 01:24:32.358949 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 01:24:32.362122 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 01:24:32.368605 0 9 12 | B1->B0 | 3131 2f2f | 0 1 | (1 0) (1 1)
4460 01:24:32.372426 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 01:24:32.375307 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 01:24:32.382487 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 01:24:32.385084 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 01:24:32.388475 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 01:24:32.395284 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 01:24:32.398586 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4467 01:24:32.401639 0 10 12 | B1->B0 | 3030 3636 | 0 1 | (0 0) (0 0)
4468 01:24:32.408178 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 01:24:32.412050 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 01:24:32.415054 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 01:24:32.421751 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 01:24:32.425488 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 01:24:32.428554 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 01:24:32.435281 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 01:24:32.438449 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4476 01:24:32.441433 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 01:24:32.448292 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 01:24:32.451350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 01:24:32.454494 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 01:24:32.460958 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 01:24:32.464104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 01:24:32.467759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 01:24:32.474490 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 01:24:32.477590 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 01:24:32.480879 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 01:24:32.487308 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 01:24:32.490751 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 01:24:32.494157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 01:24:32.501080 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 01:24:32.503946 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 01:24:32.507895 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 01:24:32.514422 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 01:24:32.517392 Total UI for P1: 0, mck2ui 16
4494 01:24:32.520606 best dqsien dly found for B0: ( 0, 13, 14)
4495 01:24:32.520680 Total UI for P1: 0, mck2ui 16
4496 01:24:32.526962 best dqsien dly found for B1: ( 0, 13, 14)
4497 01:24:32.530378 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4498 01:24:32.533587 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4499 01:24:32.533670
4500 01:24:32.537569 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4501 01:24:32.540484 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4502 01:24:32.544048 [Gating] SW calibration Done
4503 01:24:32.544124 ==
4504 01:24:32.546868 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 01:24:32.550478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 01:24:32.550555 ==
4507 01:24:32.553366 RX Vref Scan: 0
4508 01:24:32.553437
4509 01:24:32.556974 RX Vref 0 -> 0, step: 1
4510 01:24:32.557042
4511 01:24:32.557101 RX Delay -230 -> 252, step: 16
4512 01:24:32.563512 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4513 01:24:32.567093 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4514 01:24:32.570164 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4515 01:24:32.573308 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 01:24:32.580110 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 01:24:32.582836 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4518 01:24:32.586531 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4519 01:24:32.589616 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 01:24:32.596585 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4521 01:24:32.599539 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4522 01:24:32.602554 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4523 01:24:32.605991 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4524 01:24:32.612970 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4525 01:24:32.616013 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 01:24:32.619622 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4527 01:24:32.622856 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 01:24:32.622931 ==
4529 01:24:32.626045 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 01:24:32.632202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 01:24:32.632280 ==
4532 01:24:32.632346 DQS Delay:
4533 01:24:32.635693 DQS0 = 0, DQS1 = 0
4534 01:24:32.635762 DQM Delay:
4535 01:24:32.638737 DQM0 = 45, DQM1 = 40
4536 01:24:32.638808 DQ Delay:
4537 01:24:32.642007 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4538 01:24:32.647696 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4539 01:24:32.648515 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4540 01:24:32.652093 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =41
4541 01:24:32.652161
4542 01:24:32.652223
4543 01:24:32.652283 ==
4544 01:24:32.655676 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 01:24:32.658455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 01:24:32.658528 ==
4547 01:24:32.658592
4548 01:24:32.658652
4549 01:24:32.662102 TX Vref Scan disable
4550 01:24:32.664849 == TX Byte 0 ==
4551 01:24:32.668605 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4552 01:24:32.671754 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4553 01:24:32.675049 == TX Byte 1 ==
4554 01:24:32.678284 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4555 01:24:32.681445 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4556 01:24:32.681516 ==
4557 01:24:32.685172 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 01:24:32.691574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 01:24:32.691653 ==
4560 01:24:32.691714
4561 01:24:32.691771
4562 01:24:32.691829 TX Vref Scan disable
4563 01:24:32.696006 == TX Byte 0 ==
4564 01:24:32.699049 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4565 01:24:32.705831 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4566 01:24:32.705906 == TX Byte 1 ==
4567 01:24:32.708993 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4568 01:24:32.715652 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4569 01:24:32.715728
4570 01:24:32.715788 [DATLAT]
4571 01:24:32.715844 Freq=600, CH1 RK0
4572 01:24:32.715909
4573 01:24:32.719265 DATLAT Default: 0x9
4574 01:24:32.722432 0, 0xFFFF, sum = 0
4575 01:24:32.722535 1, 0xFFFF, sum = 0
4576 01:24:32.725567 2, 0xFFFF, sum = 0
4577 01:24:32.725636 3, 0xFFFF, sum = 0
4578 01:24:32.728783 4, 0xFFFF, sum = 0
4579 01:24:32.728857 5, 0xFFFF, sum = 0
4580 01:24:32.732908 6, 0xFFFF, sum = 0
4581 01:24:32.732999 7, 0xFFFF, sum = 0
4582 01:24:32.735769 8, 0x0, sum = 1
4583 01:24:32.735846 9, 0x0, sum = 2
4584 01:24:32.738755 10, 0x0, sum = 3
4585 01:24:32.738828 11, 0x0, sum = 4
4586 01:24:32.738915 best_step = 9
4587 01:24:32.738991
4588 01:24:32.741945 ==
4589 01:24:32.745316 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 01:24:32.748521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 01:24:32.748597 ==
4592 01:24:32.748685 RX Vref Scan: 1
4593 01:24:32.748762
4594 01:24:32.751883 RX Vref 0 -> 0, step: 1
4595 01:24:32.751995
4596 01:24:32.755380 RX Delay -179 -> 252, step: 8
4597 01:24:32.755455
4598 01:24:32.758819 Set Vref, RX VrefLevel [Byte0]: 50
4599 01:24:32.761731 [Byte1]: 52
4600 01:24:32.761805
4601 01:24:32.765992 Final RX Vref Byte 0 = 50 to rank0
4602 01:24:32.768731 Final RX Vref Byte 1 = 52 to rank0
4603 01:24:32.771759 Final RX Vref Byte 0 = 50 to rank1
4604 01:24:32.775158 Final RX Vref Byte 1 = 52 to rank1==
4605 01:24:32.778200 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 01:24:32.782082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 01:24:32.785007 ==
4608 01:24:32.785078 DQS Delay:
4609 01:24:32.785140 DQS0 = 0, DQS1 = 0
4610 01:24:32.788379 DQM Delay:
4611 01:24:32.788446 DQM0 = 41, DQM1 = 35
4612 01:24:32.791604 DQ Delay:
4613 01:24:32.794919 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4614 01:24:32.795003 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4615 01:24:32.798116 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4616 01:24:32.804666 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4617 01:24:32.804741
4618 01:24:32.804807
4619 01:24:32.811217 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4620 01:24:32.814705 CH1 RK0: MR19=808, MR18=2B45
4621 01:24:32.821316 CH1_RK0: MR19=0x808, MR18=0x2B45, DQSOSC=396, MR23=63, INC=167, DEC=111
4622 01:24:32.821395
4623 01:24:32.824397 ----->DramcWriteLeveling(PI) begin...
4624 01:24:32.824473 ==
4625 01:24:32.828391 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 01:24:32.831560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 01:24:32.831631 ==
4628 01:24:32.834503 Write leveling (Byte 0): 28 => 28
4629 01:24:32.838466 Write leveling (Byte 1): 28 => 28
4630 01:24:32.841532 DramcWriteLeveling(PI) end<-----
4631 01:24:32.841604
4632 01:24:32.841686 ==
4633 01:24:32.844391 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 01:24:32.848226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 01:24:32.848297 ==
4636 01:24:32.851029 [Gating] SW mode calibration
4637 01:24:32.857340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 01:24:32.864064 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 01:24:32.868094 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 01:24:32.873823 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 01:24:32.877008 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 01:24:32.880300 0 9 12 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 0)
4643 01:24:32.887120 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 01:24:32.890566 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 01:24:32.893716 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 01:24:32.899799 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 01:24:32.903369 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 01:24:32.906351 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 01:24:32.913542 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4650 01:24:32.916667 0 10 12 | B1->B0 | 3232 4242 | 0 0 | (1 1) (0 0)
4651 01:24:32.919843 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 01:24:32.926048 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 01:24:32.929922 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 01:24:32.932791 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 01:24:32.939423 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 01:24:32.942902 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 01:24:32.945903 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4658 01:24:32.952735 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 01:24:32.956553 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 01:24:32.959562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 01:24:32.966072 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 01:24:32.969314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 01:24:32.972461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 01:24:32.979180 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 01:24:32.982525 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 01:24:32.985963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 01:24:32.992268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 01:24:32.995807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 01:24:32.998863 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 01:24:33.005823 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 01:24:33.009551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 01:24:33.011798 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 01:24:33.018781 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 01:24:33.021775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4675 01:24:33.025175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 01:24:33.028554 Total UI for P1: 0, mck2ui 16
4677 01:24:33.031752 best dqsien dly found for B0: ( 0, 13, 12)
4678 01:24:33.035218 Total UI for P1: 0, mck2ui 16
4679 01:24:33.038403 best dqsien dly found for B1: ( 0, 13, 14)
4680 01:24:33.041632 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4681 01:24:33.048325 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4682 01:24:33.048414
4683 01:24:33.051751 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4684 01:24:33.055339 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4685 01:24:33.058064 [Gating] SW calibration Done
4686 01:24:33.058163 ==
4687 01:24:33.061501 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 01:24:33.064817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 01:24:33.064892 ==
4690 01:24:33.068093 RX Vref Scan: 0
4691 01:24:33.068200
4692 01:24:33.068272 RX Vref 0 -> 0, step: 1
4693 01:24:33.068332
4694 01:24:33.071031 RX Delay -230 -> 252, step: 16
4695 01:24:33.074248 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4696 01:24:33.081111 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4697 01:24:33.084589 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4698 01:24:33.087573 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4699 01:24:33.091517 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4700 01:24:33.097371 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4701 01:24:33.100758 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4702 01:24:33.104164 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4703 01:24:33.107861 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4704 01:24:33.113838 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4705 01:24:33.116874 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4706 01:24:33.120694 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4707 01:24:33.123587 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4708 01:24:33.130380 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4709 01:24:33.133896 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4710 01:24:33.136938 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4711 01:24:33.137011 ==
4712 01:24:33.140320 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 01:24:33.143514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 01:24:33.146841 ==
4715 01:24:33.146912 DQS Delay:
4716 01:24:33.146972 DQS0 = 0, DQS1 = 0
4717 01:24:33.150241 DQM Delay:
4718 01:24:33.150314 DQM0 = 40, DQM1 = 42
4719 01:24:33.153683 DQ Delay:
4720 01:24:33.153754 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4721 01:24:33.156678 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4722 01:24:33.160183 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4723 01:24:33.163223 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4724 01:24:33.166310
4725 01:24:33.166387
4726 01:24:33.166451 ==
4727 01:24:33.169681 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 01:24:33.173366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 01:24:33.173442 ==
4730 01:24:33.173506
4731 01:24:33.173563
4732 01:24:33.176210 TX Vref Scan disable
4733 01:24:33.176278 == TX Byte 0 ==
4734 01:24:33.182789 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4735 01:24:33.185992 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4736 01:24:33.186068 == TX Byte 1 ==
4737 01:24:33.192725 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4738 01:24:33.196197 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4739 01:24:33.196289 ==
4740 01:24:33.199620 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 01:24:33.203629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 01:24:33.203759 ==
4743 01:24:33.203868
4744 01:24:33.205787
4745 01:24:33.205880 TX Vref Scan disable
4746 01:24:33.209253 == TX Byte 0 ==
4747 01:24:33.212757 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4748 01:24:33.219403 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4749 01:24:33.219481 == TX Byte 1 ==
4750 01:24:33.222790 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4751 01:24:33.229238 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4752 01:24:33.229312
4753 01:24:33.229373 [DATLAT]
4754 01:24:33.229439 Freq=600, CH1 RK1
4755 01:24:33.229497
4756 01:24:33.232617 DATLAT Default: 0x9
4757 01:24:33.232693 0, 0xFFFF, sum = 0
4758 01:24:33.235507 1, 0xFFFF, sum = 0
4759 01:24:33.238901 2, 0xFFFF, sum = 0
4760 01:24:33.239005 3, 0xFFFF, sum = 0
4761 01:24:33.242491 4, 0xFFFF, sum = 0
4762 01:24:33.242572 5, 0xFFFF, sum = 0
4763 01:24:33.245495 6, 0xFFFF, sum = 0
4764 01:24:33.245564 7, 0xFFFF, sum = 0
4765 01:24:33.248758 8, 0x0, sum = 1
4766 01:24:33.248833 9, 0x0, sum = 2
4767 01:24:33.252463 10, 0x0, sum = 3
4768 01:24:33.252544 11, 0x0, sum = 4
4769 01:24:33.252606 best_step = 9
4770 01:24:33.252664
4771 01:24:33.255326 ==
4772 01:24:33.258730 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 01:24:33.262041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 01:24:33.262130 ==
4775 01:24:33.262211 RX Vref Scan: 0
4776 01:24:33.262269
4777 01:24:33.265488 RX Vref 0 -> 0, step: 1
4778 01:24:33.265580
4779 01:24:33.268926 RX Delay -179 -> 252, step: 8
4780 01:24:33.275183 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4781 01:24:33.278751 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4782 01:24:33.281728 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4783 01:24:33.284857 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4784 01:24:33.288251 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4785 01:24:33.295002 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4786 01:24:33.298340 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4787 01:24:33.301922 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4788 01:24:33.305543 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4789 01:24:33.312417 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4790 01:24:33.314928 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4791 01:24:33.317869 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4792 01:24:33.321840 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4793 01:24:33.327870 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4794 01:24:33.331188 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4795 01:24:33.334873 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4796 01:24:33.334949 ==
4797 01:24:33.337839 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 01:24:33.341936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 01:24:33.344534 ==
4800 01:24:33.344605 DQS Delay:
4801 01:24:33.344664 DQS0 = 0, DQS1 = 0
4802 01:24:33.347989 DQM Delay:
4803 01:24:33.348055 DQM0 = 37, DQM1 = 35
4804 01:24:33.350808 DQ Delay:
4805 01:24:33.354329 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4806 01:24:33.354400 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4807 01:24:33.357604 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4808 01:24:33.364262 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4809 01:24:33.364336
4810 01:24:33.364397
4811 01:24:33.370911 [DQSOSCAuto] RK1, (LSB)MR18= 0x375c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4812 01:24:33.373822 CH1 RK1: MR19=808, MR18=375C
4813 01:24:33.380580 CH1_RK1: MR19=0x808, MR18=0x375C, DQSOSC=392, MR23=63, INC=170, DEC=113
4814 01:24:33.383723 [RxdqsGatingPostProcess] freq 600
4815 01:24:33.387805 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 01:24:33.390604 Pre-setting of DQS Precalculation
4817 01:24:33.397691 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 01:24:33.403629 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 01:24:33.410167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 01:24:33.410244
4821 01:24:33.410306
4822 01:24:33.413481 [Calibration Summary] 1200 Mbps
4823 01:24:33.413569 CH 0, Rank 0
4824 01:24:33.416749 SW Impedance : PASS
4825 01:24:33.421031 DUTY Scan : NO K
4826 01:24:33.421108 ZQ Calibration : PASS
4827 01:24:33.424161 Jitter Meter : NO K
4828 01:24:33.426629 CBT Training : PASS
4829 01:24:33.426700 Write leveling : PASS
4830 01:24:33.430053 RX DQS gating : PASS
4831 01:24:33.433385 RX DQ/DQS(RDDQC) : PASS
4832 01:24:33.433455 TX DQ/DQS : PASS
4833 01:24:33.436422 RX DATLAT : PASS
4834 01:24:33.439997 RX DQ/DQS(Engine): PASS
4835 01:24:33.440105 TX OE : NO K
4836 01:24:33.443231 All Pass.
4837 01:24:33.443298
4838 01:24:33.443378 CH 0, Rank 1
4839 01:24:33.446764 SW Impedance : PASS
4840 01:24:33.446835 DUTY Scan : NO K
4841 01:24:33.450062 ZQ Calibration : PASS
4842 01:24:33.452867 Jitter Meter : NO K
4843 01:24:33.452936 CBT Training : PASS
4844 01:24:33.456207 Write leveling : PASS
4845 01:24:33.459370 RX DQS gating : PASS
4846 01:24:33.459453 RX DQ/DQS(RDDQC) : PASS
4847 01:24:33.463046 TX DQ/DQS : PASS
4848 01:24:33.465941 RX DATLAT : PASS
4849 01:24:33.466022 RX DQ/DQS(Engine): PASS
4850 01:24:33.469649 TX OE : NO K
4851 01:24:33.469722 All Pass.
4852 01:24:33.469781
4853 01:24:33.472900 CH 1, Rank 0
4854 01:24:33.472970 SW Impedance : PASS
4855 01:24:33.476468 DUTY Scan : NO K
4856 01:24:33.479198 ZQ Calibration : PASS
4857 01:24:33.479283 Jitter Meter : NO K
4858 01:24:33.482668 CBT Training : PASS
4859 01:24:33.482773 Write leveling : PASS
4860 01:24:33.485927 RX DQS gating : PASS
4861 01:24:33.489381 RX DQ/DQS(RDDQC) : PASS
4862 01:24:33.489450 TX DQ/DQS : PASS
4863 01:24:33.492734 RX DATLAT : PASS
4864 01:24:33.495889 RX DQ/DQS(Engine): PASS
4865 01:24:33.495988 TX OE : NO K
4866 01:24:33.499251 All Pass.
4867 01:24:33.499322
4868 01:24:33.499381 CH 1, Rank 1
4869 01:24:33.502713 SW Impedance : PASS
4870 01:24:33.502784 DUTY Scan : NO K
4871 01:24:33.505834 ZQ Calibration : PASS
4872 01:24:33.509914 Jitter Meter : NO K
4873 01:24:33.510003 CBT Training : PASS
4874 01:24:33.512634 Write leveling : PASS
4875 01:24:33.515826 RX DQS gating : PASS
4876 01:24:33.515955 RX DQ/DQS(RDDQC) : PASS
4877 01:24:33.518742 TX DQ/DQS : PASS
4878 01:24:33.522573 RX DATLAT : PASS
4879 01:24:33.522645 RX DQ/DQS(Engine): PASS
4880 01:24:33.525739 TX OE : NO K
4881 01:24:33.525810 All Pass.
4882 01:24:33.525869
4883 01:24:33.528769 DramC Write-DBI off
4884 01:24:33.532397 PER_BANK_REFRESH: Hybrid Mode
4885 01:24:33.532483 TX_TRACKING: ON
4886 01:24:33.542101 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 01:24:33.545963 [FAST_K] Save calibration result to emmc
4888 01:24:33.548867 dramc_set_vcore_voltage set vcore to 662500
4889 01:24:33.552423 Read voltage for 933, 3
4890 01:24:33.552494 Vio18 = 0
4891 01:24:33.552557 Vcore = 662500
4892 01:24:33.555184 Vdram = 0
4893 01:24:33.555254 Vddq = 0
4894 01:24:33.555315 Vmddr = 0
4895 01:24:33.561804 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 01:24:33.565250 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 01:24:33.568871 MEM_TYPE=3, freq_sel=17
4898 01:24:33.572101 sv_algorithm_assistance_LP4_1600
4899 01:24:33.575147 ============ PULL DRAM RESETB DOWN ============
4900 01:24:33.578215 ========== PULL DRAM RESETB DOWN end =========
4901 01:24:33.584909 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 01:24:33.588285 ===================================
4903 01:24:33.591489 LPDDR4 DRAM CONFIGURATION
4904 01:24:33.594950 ===================================
4905 01:24:33.595028 EX_ROW_EN[0] = 0x0
4906 01:24:33.598220 EX_ROW_EN[1] = 0x0
4907 01:24:33.598303 LP4Y_EN = 0x0
4908 01:24:33.601791 WORK_FSP = 0x0
4909 01:24:33.601882 WL = 0x3
4910 01:24:33.604967 RL = 0x3
4911 01:24:33.605041 BL = 0x2
4912 01:24:33.608000 RPST = 0x0
4913 01:24:33.608075 RD_PRE = 0x0
4914 01:24:33.611236 WR_PRE = 0x1
4915 01:24:33.611314 WR_PST = 0x0
4916 01:24:33.614681 DBI_WR = 0x0
4917 01:24:33.617728 DBI_RD = 0x0
4918 01:24:33.617803 OTF = 0x1
4919 01:24:33.621092 ===================================
4920 01:24:33.624303 ===================================
4921 01:24:33.624395 ANA top config
4922 01:24:33.628169 ===================================
4923 01:24:33.631131 DLL_ASYNC_EN = 0
4924 01:24:33.634178 ALL_SLAVE_EN = 1
4925 01:24:33.637414 NEW_RANK_MODE = 1
4926 01:24:33.641313 DLL_IDLE_MODE = 1
4927 01:24:33.641388 LP45_APHY_COMB_EN = 1
4928 01:24:33.644270 TX_ODT_DIS = 1
4929 01:24:33.647175 NEW_8X_MODE = 1
4930 01:24:33.650798 ===================================
4931 01:24:33.654458 ===================================
4932 01:24:33.657314 data_rate = 1866
4933 01:24:33.660464 CKR = 1
4934 01:24:33.664143 DQ_P2S_RATIO = 8
4935 01:24:33.667542 ===================================
4936 01:24:33.667618 CA_P2S_RATIO = 8
4937 01:24:33.670290 DQ_CA_OPEN = 0
4938 01:24:33.673541 DQ_SEMI_OPEN = 0
4939 01:24:33.677255 CA_SEMI_OPEN = 0
4940 01:24:33.680932 CA_FULL_RATE = 0
4941 01:24:33.683817 DQ_CKDIV4_EN = 1
4942 01:24:33.683958 CA_CKDIV4_EN = 1
4943 01:24:33.686832 CA_PREDIV_EN = 0
4944 01:24:33.690992 PH8_DLY = 0
4945 01:24:33.693595 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 01:24:33.696875 DQ_AAMCK_DIV = 4
4947 01:24:33.700195 CA_AAMCK_DIV = 4
4948 01:24:33.700274 CA_ADMCK_DIV = 4
4949 01:24:33.703221 DQ_TRACK_CA_EN = 0
4950 01:24:33.706931 CA_PICK = 933
4951 01:24:33.709989 CA_MCKIO = 933
4952 01:24:33.713565 MCKIO_SEMI = 0
4953 01:24:33.717207 PLL_FREQ = 3732
4954 01:24:33.719986 DQ_UI_PI_RATIO = 32
4955 01:24:33.720060 CA_UI_PI_RATIO = 0
4956 01:24:33.723590 ===================================
4957 01:24:33.726251 ===================================
4958 01:24:33.729952 memory_type:LPDDR4
4959 01:24:33.733380 GP_NUM : 10
4960 01:24:33.733452 SRAM_EN : 1
4961 01:24:33.736611 MD32_EN : 0
4962 01:24:33.740004 ===================================
4963 01:24:33.742932 [ANA_INIT] >>>>>>>>>>>>>>
4964 01:24:33.746206 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 01:24:33.749559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 01:24:33.753024 ===================================
4967 01:24:33.756125 data_rate = 1866,PCW = 0X8f00
4968 01:24:33.759348 ===================================
4969 01:24:33.762493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 01:24:33.766022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 01:24:33.772266 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 01:24:33.776194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 01:24:33.779404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 01:24:33.782510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 01:24:33.785700 [ANA_INIT] flow start
4976 01:24:33.788961 [ANA_INIT] PLL >>>>>>>>
4977 01:24:33.789036 [ANA_INIT] PLL <<<<<<<<
4978 01:24:33.792543 [ANA_INIT] MIDPI >>>>>>>>
4979 01:24:33.795487 [ANA_INIT] MIDPI <<<<<<<<
4980 01:24:33.798869 [ANA_INIT] DLL >>>>>>>>
4981 01:24:33.798951 [ANA_INIT] flow end
4982 01:24:33.802092 ============ LP4 DIFF to SE enter ============
4983 01:24:33.809305 ============ LP4 DIFF to SE exit ============
4984 01:24:33.809394 [ANA_INIT] <<<<<<<<<<<<<
4985 01:24:33.812030 [Flow] Enable top DCM control >>>>>
4986 01:24:33.815837 [Flow] Enable top DCM control <<<<<
4987 01:24:33.819255 Enable DLL master slave shuffle
4988 01:24:33.825194 ==============================================================
4989 01:24:33.825275 Gating Mode config
4990 01:24:33.832324 ==============================================================
4991 01:24:33.835226 Config description:
4992 01:24:33.845136 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 01:24:33.851596 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 01:24:33.854898 SELPH_MODE 0: By rank 1: By Phase
4995 01:24:33.861823 ==============================================================
4996 01:24:33.864812 GAT_TRACK_EN = 1
4997 01:24:33.868644 RX_GATING_MODE = 2
4998 01:24:33.871253 RX_GATING_TRACK_MODE = 2
4999 01:24:33.871333 SELPH_MODE = 1
5000 01:24:33.874863 PICG_EARLY_EN = 1
5001 01:24:33.878348 VALID_LAT_VALUE = 1
5002 01:24:33.884949 ==============================================================
5003 01:24:33.888360 Enter into Gating configuration >>>>
5004 01:24:33.891353 Exit from Gating configuration <<<<
5005 01:24:33.894401 Enter into DVFS_PRE_config >>>>>
5006 01:24:33.904719 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 01:24:33.908279 Exit from DVFS_PRE_config <<<<<
5008 01:24:33.911031 Enter into PICG configuration >>>>
5009 01:24:33.914520 Exit from PICG configuration <<<<
5010 01:24:33.917748 [RX_INPUT] configuration >>>>>
5011 01:24:33.920896 [RX_INPUT] configuration <<<<<
5012 01:24:33.924394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 01:24:33.930624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 01:24:33.937340 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 01:24:33.943768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 01:24:33.950366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 01:24:33.958263 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 01:24:33.960301 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 01:24:33.963290 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 01:24:33.966805 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 01:24:33.973374 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 01:24:33.976499 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 01:24:33.980039 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 01:24:33.983063 ===================================
5025 01:24:33.986799 LPDDR4 DRAM CONFIGURATION
5026 01:24:33.989921 ===================================
5027 01:24:33.989990 EX_ROW_EN[0] = 0x0
5028 01:24:33.993286 EX_ROW_EN[1] = 0x0
5029 01:24:33.996325 LP4Y_EN = 0x0
5030 01:24:33.996434 WORK_FSP = 0x0
5031 01:24:33.999453 WL = 0x3
5032 01:24:33.999522 RL = 0x3
5033 01:24:34.003254 BL = 0x2
5034 01:24:34.003321 RPST = 0x0
5035 01:24:34.006267 RD_PRE = 0x0
5036 01:24:34.006340 WR_PRE = 0x1
5037 01:24:34.009516 WR_PST = 0x0
5038 01:24:34.009594 DBI_WR = 0x0
5039 01:24:34.012742 DBI_RD = 0x0
5040 01:24:34.012810 OTF = 0x1
5041 01:24:34.016078 ===================================
5042 01:24:34.019445 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 01:24:34.025990 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 01:24:34.029400 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 01:24:34.033408 ===================================
5046 01:24:34.035729 LPDDR4 DRAM CONFIGURATION
5047 01:24:34.039471 ===================================
5048 01:24:34.039570 EX_ROW_EN[0] = 0x10
5049 01:24:34.042213 EX_ROW_EN[1] = 0x0
5050 01:24:34.045680 LP4Y_EN = 0x0
5051 01:24:34.045753 WORK_FSP = 0x0
5052 01:24:34.048933 WL = 0x3
5053 01:24:34.049000 RL = 0x3
5054 01:24:34.052717 BL = 0x2
5055 01:24:34.052788 RPST = 0x0
5056 01:24:34.055661 RD_PRE = 0x0
5057 01:24:34.055727 WR_PRE = 0x1
5058 01:24:34.059174 WR_PST = 0x0
5059 01:24:34.059244 DBI_WR = 0x0
5060 01:24:34.062252 DBI_RD = 0x0
5061 01:24:34.062318 OTF = 0x1
5062 01:24:34.065576 ===================================
5063 01:24:34.073619 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 01:24:34.077035 nWR fixed to 30
5065 01:24:34.080055 [ModeRegInit_LP4] CH0 RK0
5066 01:24:34.080133 [ModeRegInit_LP4] CH0 RK1
5067 01:24:34.083273 [ModeRegInit_LP4] CH1 RK0
5068 01:24:34.086851 [ModeRegInit_LP4] CH1 RK1
5069 01:24:34.086924 match AC timing 9
5070 01:24:34.093444 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 01:24:34.096426 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 01:24:34.100137 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 01:24:34.106532 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 01:24:34.109790 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 01:24:34.109872 ==
5076 01:24:34.113222 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 01:24:34.116494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 01:24:34.116575 ==
5079 01:24:34.122833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 01:24:34.130206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5081 01:24:34.132763 [CA 0] Center 37 (7~68) winsize 62
5082 01:24:34.136500 [CA 1] Center 37 (7~68) winsize 62
5083 01:24:34.139813 [CA 2] Center 34 (4~64) winsize 61
5084 01:24:34.142707 [CA 3] Center 34 (4~65) winsize 62
5085 01:24:34.146035 [CA 4] Center 32 (2~63) winsize 62
5086 01:24:34.149462 [CA 5] Center 32 (2~63) winsize 62
5087 01:24:34.149550
5088 01:24:34.152839 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5089 01:24:34.152919
5090 01:24:34.156040 [CATrainingPosCal] consider 1 rank data
5091 01:24:34.159547 u2DelayCellTimex100 = 270/100 ps
5092 01:24:34.163063 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5093 01:24:34.165926 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5094 01:24:34.169509 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5095 01:24:34.172637 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5096 01:24:34.179776 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5097 01:24:34.182519 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5098 01:24:34.182600
5099 01:24:34.185849 CA PerBit enable=1, Macro0, CA PI delay=32
5100 01:24:34.185930
5101 01:24:34.189516 [CBTSetCACLKResult] CA Dly = 32
5102 01:24:34.189596 CS Dly: 5 (0~36)
5103 01:24:34.189660 ==
5104 01:24:34.192616 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 01:24:34.198830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 01:24:34.198946 ==
5107 01:24:34.202236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 01:24:34.208650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5109 01:24:34.212069 [CA 0] Center 38 (8~68) winsize 61
5110 01:24:34.216026 [CA 1] Center 37 (7~68) winsize 62
5111 01:24:34.218827 [CA 2] Center 34 (4~65) winsize 62
5112 01:24:34.221980 [CA 3] Center 34 (4~65) winsize 62
5113 01:24:34.225478 [CA 4] Center 33 (3~64) winsize 62
5114 01:24:34.228608 [CA 5] Center 32 (2~63) winsize 62
5115 01:24:34.228682
5116 01:24:34.231807 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5117 01:24:34.231894
5118 01:24:34.235893 [CATrainingPosCal] consider 2 rank data
5119 01:24:34.238550 u2DelayCellTimex100 = 270/100 ps
5120 01:24:34.241855 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5121 01:24:34.248334 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5122 01:24:34.252020 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5123 01:24:34.255559 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5124 01:24:34.258471 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5125 01:24:34.261323 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5126 01:24:34.261396
5127 01:24:34.265219 CA PerBit enable=1, Macro0, CA PI delay=32
5128 01:24:34.265291
5129 01:24:34.268207 [CBTSetCACLKResult] CA Dly = 32
5130 01:24:34.271767 CS Dly: 6 (0~39)
5131 01:24:34.271856
5132 01:24:34.275285 ----->DramcWriteLeveling(PI) begin...
5133 01:24:34.275363 ==
5134 01:24:34.278155 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 01:24:34.281741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 01:24:34.281815 ==
5137 01:24:34.284516 Write leveling (Byte 0): 33 => 33
5138 01:24:34.288390 Write leveling (Byte 1): 28 => 28
5139 01:24:34.291528 DramcWriteLeveling(PI) end<-----
5140 01:24:34.291600
5141 01:24:34.291660 ==
5142 01:24:34.294961 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 01:24:34.298014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 01:24:34.298106 ==
5145 01:24:34.301207 [Gating] SW mode calibration
5146 01:24:34.307794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 01:24:34.314634 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 01:24:34.317570 0 14 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5149 01:24:34.320862 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5150 01:24:34.327628 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 01:24:34.331055 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 01:24:34.334412 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 01:24:34.341166 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 01:24:34.344651 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 01:24:34.347576 0 14 28 | B1->B0 | 3434 2d2d | 0 1 | (0 0) (0 0)
5156 01:24:34.354136 0 15 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
5157 01:24:34.357907 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5158 01:24:34.360996 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 01:24:34.367557 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 01:24:34.370538 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 01:24:34.374180 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 01:24:34.380368 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5163 01:24:34.383769 0 15 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5164 01:24:34.387072 1 0 0 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
5165 01:24:34.393532 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 01:24:34.397127 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 01:24:34.400162 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 01:24:34.406842 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 01:24:34.410092 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 01:24:34.413334 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5171 01:24:34.419849 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5172 01:24:34.423339 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5173 01:24:34.426330 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5174 01:24:34.433565 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 01:24:34.436664 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 01:24:34.439457 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 01:24:34.446099 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 01:24:34.449582 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 01:24:34.453710 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 01:24:34.459546 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 01:24:34.463102 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 01:24:34.466028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 01:24:34.472749 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 01:24:34.476143 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 01:24:34.478894 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 01:24:34.485769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 01:24:34.488864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5188 01:24:34.492367 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5189 01:24:34.496060 Total UI for P1: 0, mck2ui 16
5190 01:24:34.498644 best dqsien dly found for B0: ( 1, 2, 26)
5191 01:24:34.505146 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 01:24:34.508489 Total UI for P1: 0, mck2ui 16
5193 01:24:34.511715 best dqsien dly found for B1: ( 1, 3, 0)
5194 01:24:34.515358 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5195 01:24:34.518637 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5196 01:24:34.518720
5197 01:24:34.521348 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5198 01:24:34.524859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5199 01:24:34.528460 [Gating] SW calibration Done
5200 01:24:34.528545 ==
5201 01:24:34.531577 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 01:24:34.534973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 01:24:34.535077 ==
5204 01:24:34.538225 RX Vref Scan: 0
5205 01:24:34.538350
5206 01:24:34.541227 RX Vref 0 -> 0, step: 1
5207 01:24:34.541308
5208 01:24:34.541371 RX Delay -80 -> 252, step: 8
5209 01:24:34.548271 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5210 01:24:34.551645 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5211 01:24:34.555090 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5212 01:24:34.558428 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5213 01:24:34.561460 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5214 01:24:34.564521 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5215 01:24:34.571419 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5216 01:24:34.574675 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5217 01:24:34.578055 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5218 01:24:34.581125 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5219 01:24:34.584310 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5220 01:24:34.590830 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5221 01:24:34.594123 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5222 01:24:34.597945 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5223 01:24:34.601172 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5224 01:24:34.604343 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5225 01:24:34.604424 ==
5226 01:24:34.607310 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 01:24:34.613762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 01:24:34.613843 ==
5229 01:24:34.613907 DQS Delay:
5230 01:24:34.617220 DQS0 = 0, DQS1 = 0
5231 01:24:34.617337 DQM Delay:
5232 01:24:34.620620 DQM0 = 100, DQM1 = 89
5233 01:24:34.620700 DQ Delay:
5234 01:24:34.624740 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5235 01:24:34.626986 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5236 01:24:34.630333 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5237 01:24:34.634209 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5238 01:24:34.634290
5239 01:24:34.634353
5240 01:24:34.634411 ==
5241 01:24:34.637411 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 01:24:34.640441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 01:24:34.640540 ==
5244 01:24:34.640635
5245 01:24:34.640708
5246 01:24:34.643446 TX Vref Scan disable
5247 01:24:34.647372 == TX Byte 0 ==
5248 01:24:34.650345 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5249 01:24:34.653592 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5250 01:24:34.656639 == TX Byte 1 ==
5251 01:24:34.660072 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5252 01:24:34.663551 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5253 01:24:34.663631 ==
5254 01:24:34.667241 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 01:24:34.673170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 01:24:34.673251 ==
5257 01:24:34.673315
5258 01:24:34.673373
5259 01:24:34.673428 TX Vref Scan disable
5260 01:24:34.677797 == TX Byte 0 ==
5261 01:24:34.680695 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5262 01:24:34.687117 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5263 01:24:34.687219 == TX Byte 1 ==
5264 01:24:34.690782 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5265 01:24:34.697774 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5266 01:24:34.697856
5267 01:24:34.697918 [DATLAT]
5268 01:24:34.697977 Freq=933, CH0 RK0
5269 01:24:34.698036
5270 01:24:34.700555 DATLAT Default: 0xd
5271 01:24:34.700635 0, 0xFFFF, sum = 0
5272 01:24:34.703619 1, 0xFFFF, sum = 0
5273 01:24:34.707831 2, 0xFFFF, sum = 0
5274 01:24:34.707959 3, 0xFFFF, sum = 0
5275 01:24:34.710601 4, 0xFFFF, sum = 0
5276 01:24:34.710683 5, 0xFFFF, sum = 0
5277 01:24:34.713596 6, 0xFFFF, sum = 0
5278 01:24:34.713694 7, 0xFFFF, sum = 0
5279 01:24:34.717589 8, 0xFFFF, sum = 0
5280 01:24:34.717671 9, 0xFFFF, sum = 0
5281 01:24:34.720239 10, 0x0, sum = 1
5282 01:24:34.720320 11, 0x0, sum = 2
5283 01:24:34.723831 12, 0x0, sum = 3
5284 01:24:34.723958 13, 0x0, sum = 4
5285 01:24:34.727055 best_step = 11
5286 01:24:34.727135
5287 01:24:34.727199 ==
5288 01:24:34.730348 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 01:24:34.733897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 01:24:34.733978 ==
5291 01:24:34.734041 RX Vref Scan: 1
5292 01:24:34.734101
5293 01:24:34.737532 RX Vref 0 -> 0, step: 1
5294 01:24:34.737612
5295 01:24:34.739854 RX Delay -61 -> 252, step: 4
5296 01:24:34.739975
5297 01:24:34.743830 Set Vref, RX VrefLevel [Byte0]: 51
5298 01:24:34.746357 [Byte1]: 59
5299 01:24:34.749873
5300 01:24:34.749967 Final RX Vref Byte 0 = 51 to rank0
5301 01:24:34.753101 Final RX Vref Byte 1 = 59 to rank0
5302 01:24:34.756324 Final RX Vref Byte 0 = 51 to rank1
5303 01:24:34.759892 Final RX Vref Byte 1 = 59 to rank1==
5304 01:24:34.763536 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 01:24:34.770014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 01:24:34.770113 ==
5307 01:24:34.770208 DQS Delay:
5308 01:24:34.773280 DQS0 = 0, DQS1 = 0
5309 01:24:34.773361 DQM Delay:
5310 01:24:34.773423 DQM0 = 99, DQM1 = 88
5311 01:24:34.776286 DQ Delay:
5312 01:24:34.779677 DQ0 =100, DQ1 =100, DQ2 =96, DQ3 =96
5313 01:24:34.783315 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5314 01:24:34.786540 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5315 01:24:34.789505 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5316 01:24:34.789586
5317 01:24:34.789649
5318 01:24:34.796344 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5319 01:24:34.799462 CH0 RK0: MR19=505, MR18=1A14
5320 01:24:34.806210 CH0_RK0: MR19=0x505, MR18=0x1A14, DQSOSC=413, MR23=63, INC=63, DEC=42
5321 01:24:34.806291
5322 01:24:34.809420 ----->DramcWriteLeveling(PI) begin...
5323 01:24:34.809502 ==
5324 01:24:34.812641 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 01:24:34.815810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 01:24:34.818963 ==
5327 01:24:34.819045 Write leveling (Byte 0): 34 => 34
5328 01:24:34.822179 Write leveling (Byte 1): 30 => 30
5329 01:24:34.825757 DramcWriteLeveling(PI) end<-----
5330 01:24:34.825837
5331 01:24:34.825900 ==
5332 01:24:34.829343 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 01:24:34.835735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 01:24:34.835843 ==
5335 01:24:34.838803 [Gating] SW mode calibration
5336 01:24:34.845475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5337 01:24:34.849519 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5338 01:24:34.854997 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5339 01:24:34.858211 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 01:24:34.861529 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 01:24:34.868104 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 01:24:34.871489 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 01:24:34.874878 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 01:24:34.881414 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5345 01:24:34.884573 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
5346 01:24:34.888062 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5347 01:24:34.894589 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 01:24:34.897756 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 01:24:34.901540 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 01:24:34.908274 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 01:24:34.910959 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 01:24:34.914748 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5353 01:24:34.921166 0 15 28 | B1->B0 | 2828 4141 | 0 1 | (0 0) (0 0)
5354 01:24:34.924489 1 0 0 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5355 01:24:34.927484 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 01:24:34.934568 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 01:24:34.937325 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 01:24:34.940803 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 01:24:34.947873 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 01:24:34.950962 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5361 01:24:34.954465 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5362 01:24:34.960894 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5363 01:24:34.964142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 01:24:34.967452 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 01:24:34.973530 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 01:24:34.977442 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 01:24:34.980544 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 01:24:34.987255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 01:24:34.990314 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 01:24:34.994152 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 01:24:35.000271 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 01:24:35.003255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 01:24:35.006614 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 01:24:35.013166 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 01:24:35.016730 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 01:24:35.019709 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 01:24:35.026997 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5378 01:24:35.027082 Total UI for P1: 0, mck2ui 16
5379 01:24:35.032847 best dqsien dly found for B0: ( 1, 2, 26)
5380 01:24:35.036687 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 01:24:35.039748 Total UI for P1: 0, mck2ui 16
5382 01:24:35.042958 best dqsien dly found for B1: ( 1, 2, 30)
5383 01:24:35.046937 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5384 01:24:35.049601 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5385 01:24:35.049681
5386 01:24:35.053196 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5387 01:24:35.056215 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5388 01:24:35.059712 [Gating] SW calibration Done
5389 01:24:35.059825 ==
5390 01:24:35.062894 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 01:24:35.065949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 01:24:35.069475 ==
5393 01:24:35.069555 RX Vref Scan: 0
5394 01:24:35.069635
5395 01:24:35.072792 RX Vref 0 -> 0, step: 1
5396 01:24:35.072873
5397 01:24:35.075825 RX Delay -80 -> 252, step: 8
5398 01:24:35.079511 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5399 01:24:35.082638 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5400 01:24:35.085932 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5401 01:24:35.089382 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5402 01:24:35.092654 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5403 01:24:35.098917 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5404 01:24:35.102600 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5405 01:24:35.106037 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5406 01:24:35.108933 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5407 01:24:35.112252 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5408 01:24:35.118759 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5409 01:24:35.122486 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5410 01:24:35.125594 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5411 01:24:35.128885 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5412 01:24:35.132023 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5413 01:24:35.134969 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5414 01:24:35.138835 ==
5415 01:24:35.138915 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 01:24:35.145329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 01:24:35.145410 ==
5418 01:24:35.145474 DQS Delay:
5419 01:24:35.148128 DQS0 = 0, DQS1 = 0
5420 01:24:35.148207 DQM Delay:
5421 01:24:35.151692 DQM0 = 97, DQM1 = 90
5422 01:24:35.151772 DQ Delay:
5423 01:24:35.154727 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =95
5424 01:24:35.158585 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5425 01:24:35.161608 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5426 01:24:35.165820 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5427 01:24:35.165901
5428 01:24:35.165964
5429 01:24:35.166022 ==
5430 01:24:35.168295 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 01:24:35.171524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 01:24:35.171631 ==
5433 01:24:35.171721
5434 01:24:35.171832
5435 01:24:35.174555 TX Vref Scan disable
5436 01:24:35.178215 == TX Byte 0 ==
5437 01:24:35.181437 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5438 01:24:35.184696 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5439 01:24:35.187761 == TX Byte 1 ==
5440 01:24:35.191352 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5441 01:24:35.194692 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5442 01:24:35.194773 ==
5443 01:24:35.197964 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 01:24:35.204408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 01:24:35.204506 ==
5446 01:24:35.204578
5447 01:24:35.204638
5448 01:24:35.204696 TX Vref Scan disable
5449 01:24:35.209072 == TX Byte 0 ==
5450 01:24:35.212216 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5451 01:24:35.215751 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5452 01:24:35.218620 == TX Byte 1 ==
5453 01:24:35.221842 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5454 01:24:35.228656 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5455 01:24:35.228773
5456 01:24:35.228837 [DATLAT]
5457 01:24:35.228897 Freq=933, CH0 RK1
5458 01:24:35.228955
5459 01:24:35.231770 DATLAT Default: 0xb
5460 01:24:35.231875 0, 0xFFFF, sum = 0
5461 01:24:35.235109 1, 0xFFFF, sum = 0
5462 01:24:35.238608 2, 0xFFFF, sum = 0
5463 01:24:35.238689 3, 0xFFFF, sum = 0
5464 01:24:35.242315 4, 0xFFFF, sum = 0
5465 01:24:35.242397 5, 0xFFFF, sum = 0
5466 01:24:35.245042 6, 0xFFFF, sum = 0
5467 01:24:35.245123 7, 0xFFFF, sum = 0
5468 01:24:35.248918 8, 0xFFFF, sum = 0
5469 01:24:35.248999 9, 0xFFFF, sum = 0
5470 01:24:35.251750 10, 0x0, sum = 1
5471 01:24:35.251831 11, 0x0, sum = 2
5472 01:24:35.254992 12, 0x0, sum = 3
5473 01:24:35.255074 13, 0x0, sum = 4
5474 01:24:35.255139 best_step = 11
5475 01:24:35.258381
5476 01:24:35.258521 ==
5477 01:24:35.261694 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 01:24:35.265500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 01:24:35.265582 ==
5480 01:24:35.265645 RX Vref Scan: 0
5481 01:24:35.265704
5482 01:24:35.268121 RX Vref 0 -> 0, step: 1
5483 01:24:35.268217
5484 01:24:35.272217 RX Delay -53 -> 252, step: 4
5485 01:24:35.277845 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5486 01:24:35.281191 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5487 01:24:35.284637 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5488 01:24:35.287897 iDelay=195, Bit 3, Center 92 (3 ~ 182) 180
5489 01:24:35.291374 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5490 01:24:35.294307 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5491 01:24:35.301159 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5492 01:24:35.304857 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5493 01:24:35.307521 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5494 01:24:35.311169 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5495 01:24:35.314320 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5496 01:24:35.317659 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5497 01:24:35.323964 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5498 01:24:35.327466 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5499 01:24:35.330749 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5500 01:24:35.334614 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5501 01:24:35.334695 ==
5502 01:24:35.337634 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 01:24:35.343863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 01:24:35.343966 ==
5505 01:24:35.344030 DQS Delay:
5506 01:24:35.347221 DQS0 = 0, DQS1 = 0
5507 01:24:35.347301 DQM Delay:
5508 01:24:35.347363 DQM0 = 96, DQM1 = 89
5509 01:24:35.350526 DQ Delay:
5510 01:24:35.354230 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5511 01:24:35.357101 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5512 01:24:35.361090 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5513 01:24:35.364196 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5514 01:24:35.364276
5515 01:24:35.364339
5516 01:24:35.370439 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5517 01:24:35.373616 CH0 RK1: MR19=505, MR18=1A17
5518 01:24:35.380370 CH0_RK1: MR19=0x505, MR18=0x1A17, DQSOSC=413, MR23=63, INC=63, DEC=42
5519 01:24:35.383757 [RxdqsGatingPostProcess] freq 933
5520 01:24:35.390271 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5521 01:24:35.390356 best DQS0 dly(2T, 0.5T) = (0, 10)
5522 01:24:35.393207 best DQS1 dly(2T, 0.5T) = (0, 11)
5523 01:24:35.396690 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5524 01:24:35.399966 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5525 01:24:35.403346 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 01:24:35.406391 best DQS1 dly(2T, 0.5T) = (0, 10)
5527 01:24:35.409880 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 01:24:35.412857 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5529 01:24:35.416601 Pre-setting of DQS Precalculation
5530 01:24:35.422714 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5531 01:24:35.422794 ==
5532 01:24:35.426086 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 01:24:35.429841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 01:24:35.429936 ==
5535 01:24:35.436264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5536 01:24:35.439574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5537 01:24:35.443624 [CA 0] Center 36 (6~67) winsize 62
5538 01:24:35.446839 [CA 1] Center 36 (6~67) winsize 62
5539 01:24:35.450248 [CA 2] Center 34 (4~65) winsize 62
5540 01:24:35.453698 [CA 3] Center 34 (4~64) winsize 61
5541 01:24:35.456947 [CA 4] Center 34 (4~65) winsize 62
5542 01:24:35.459844 [CA 5] Center 33 (3~64) winsize 62
5543 01:24:35.459949
5544 01:24:35.463498 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5545 01:24:35.463626
5546 01:24:35.466530 [CATrainingPosCal] consider 1 rank data
5547 01:24:35.469575 u2DelayCellTimex100 = 270/100 ps
5548 01:24:35.476481 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5549 01:24:35.480226 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 01:24:35.482832 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 01:24:35.486434 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 01:24:35.489301 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5553 01:24:35.493180 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 01:24:35.493260
5555 01:24:35.496237 CA PerBit enable=1, Macro0, CA PI delay=33
5556 01:24:35.496317
5557 01:24:35.499219 [CBTSetCACLKResult] CA Dly = 33
5558 01:24:35.502798 CS Dly: 5 (0~36)
5559 01:24:35.502878 ==
5560 01:24:35.505888 Dram Type= 6, Freq= 0, CH_1, rank 1
5561 01:24:35.509519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 01:24:35.509600 ==
5563 01:24:35.515911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 01:24:35.522492 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5565 01:24:35.525657 [CA 0] Center 36 (6~67) winsize 62
5566 01:24:35.529027 [CA 1] Center 36 (6~67) winsize 62
5567 01:24:35.532382 [CA 2] Center 34 (4~65) winsize 62
5568 01:24:35.535534 [CA 3] Center 33 (3~64) winsize 62
5569 01:24:35.539146 [CA 4] Center 33 (3~64) winsize 62
5570 01:24:35.542044 [CA 5] Center 33 (3~64) winsize 62
5571 01:24:35.542125
5572 01:24:35.545237 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5573 01:24:35.545317
5574 01:24:35.549509 [CATrainingPosCal] consider 2 rank data
5575 01:24:35.552246 u2DelayCellTimex100 = 270/100 ps
5576 01:24:35.555460 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5577 01:24:35.558412 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5578 01:24:35.562340 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5579 01:24:35.565132 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5580 01:24:35.568504 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 01:24:35.571853 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 01:24:35.571958
5583 01:24:35.575786 CA PerBit enable=1, Macro0, CA PI delay=33
5584 01:24:35.578498
5585 01:24:35.578577 [CBTSetCACLKResult] CA Dly = 33
5586 01:24:35.581695 CS Dly: 6 (0~38)
5587 01:24:35.581774
5588 01:24:35.585050 ----->DramcWriteLeveling(PI) begin...
5589 01:24:35.585132 ==
5590 01:24:35.588360 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 01:24:35.591768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 01:24:35.591848 ==
5593 01:24:35.595147 Write leveling (Byte 0): 26 => 26
5594 01:24:35.598922 Write leveling (Byte 1): 27 => 27
5595 01:24:35.602349 DramcWriteLeveling(PI) end<-----
5596 01:24:35.602429
5597 01:24:35.602492 ==
5598 01:24:35.604849 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 01:24:35.608383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 01:24:35.611501 ==
5601 01:24:35.611581 [Gating] SW mode calibration
5602 01:24:35.621448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5603 01:24:35.624806 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5604 01:24:35.627914 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 01:24:35.634324 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 01:24:35.637813 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 01:24:35.641037 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 01:24:35.647490 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 01:24:35.650859 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 01:24:35.654078 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
5611 01:24:35.660998 0 14 28 | B1->B0 | 2a2a 2626 | 1 0 | (1 0) (0 0)
5612 01:24:35.664287 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 01:24:35.667692 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 01:24:35.674101 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 01:24:35.678083 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 01:24:35.680394 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 01:24:35.686981 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 01:24:35.690823 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5619 01:24:35.693864 0 15 28 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
5620 01:24:35.700125 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 01:24:35.703834 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 01:24:35.710876 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 01:24:35.713598 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 01:24:35.716945 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 01:24:35.723388 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 01:24:35.726957 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5627 01:24:35.729920 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5628 01:24:35.736816 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 01:24:35.739590 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 01:24:35.743050 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 01:24:35.749486 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 01:24:35.752827 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 01:24:35.756121 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 01:24:35.763660 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 01:24:35.766177 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 01:24:35.769654 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 01:24:35.776169 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 01:24:35.779393 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 01:24:35.782457 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 01:24:35.789053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 01:24:35.792614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 01:24:35.795771 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5643 01:24:35.802220 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5644 01:24:35.805608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 01:24:35.809115 Total UI for P1: 0, mck2ui 16
5646 01:24:35.812737 best dqsien dly found for B0: ( 1, 2, 26)
5647 01:24:35.815884 Total UI for P1: 0, mck2ui 16
5648 01:24:35.819461 best dqsien dly found for B1: ( 1, 2, 26)
5649 01:24:35.822117 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5650 01:24:35.825535 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5651 01:24:35.825609
5652 01:24:35.829025 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5653 01:24:35.832274 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5654 01:24:35.835181 [Gating] SW calibration Done
5655 01:24:35.835283 ==
5656 01:24:35.838893 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 01:24:35.842043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 01:24:35.842145 ==
5659 01:24:35.845272 RX Vref Scan: 0
5660 01:24:35.845349
5661 01:24:35.848663 RX Vref 0 -> 0, step: 1
5662 01:24:35.848740
5663 01:24:35.848803 RX Delay -80 -> 252, step: 8
5664 01:24:35.855456 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5665 01:24:35.858523 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5666 01:24:35.861929 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5667 01:24:35.865148 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5668 01:24:35.868534 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5669 01:24:35.875105 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5670 01:24:35.878166 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5671 01:24:35.881485 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5672 01:24:35.884894 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5673 01:24:35.888607 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5674 01:24:35.891344 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5675 01:24:35.897917 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5676 01:24:35.901603 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5677 01:24:35.904770 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5678 01:24:35.907811 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5679 01:24:35.911637 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5680 01:24:35.911716 ==
5681 01:24:35.914768 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 01:24:35.921220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 01:24:35.921300 ==
5684 01:24:35.921364 DQS Delay:
5685 01:24:35.925004 DQS0 = 0, DQS1 = 0
5686 01:24:35.925084 DQM Delay:
5687 01:24:35.928161 DQM0 = 99, DQM1 = 95
5688 01:24:35.928241 DQ Delay:
5689 01:24:35.930831 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5690 01:24:35.934698 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5691 01:24:35.937673 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5692 01:24:35.941216 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5693 01:24:35.941297
5694 01:24:35.941360
5695 01:24:35.941417 ==
5696 01:24:35.944193 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 01:24:35.947594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 01:24:35.951112 ==
5699 01:24:35.951193
5700 01:24:35.951256
5701 01:24:35.951315 TX Vref Scan disable
5702 01:24:35.954534 == TX Byte 0 ==
5703 01:24:35.958091 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5704 01:24:35.960698 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5705 01:24:35.964672 == TX Byte 1 ==
5706 01:24:35.967391 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5707 01:24:35.970551 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5708 01:24:35.970634 ==
5709 01:24:35.974168 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 01:24:35.980419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 01:24:35.980500 ==
5712 01:24:35.980564
5713 01:24:35.980623
5714 01:24:35.983836 TX Vref Scan disable
5715 01:24:35.983941 == TX Byte 0 ==
5716 01:24:35.990797 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5717 01:24:35.993710 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5718 01:24:35.993804 == TX Byte 1 ==
5719 01:24:36.000263 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5720 01:24:36.003768 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5721 01:24:36.003851
5722 01:24:36.003926 [DATLAT]
5723 01:24:36.006762 Freq=933, CH1 RK0
5724 01:24:36.006843
5725 01:24:36.006905 DATLAT Default: 0xd
5726 01:24:36.010338 0, 0xFFFF, sum = 0
5727 01:24:36.010422 1, 0xFFFF, sum = 0
5728 01:24:36.013438 2, 0xFFFF, sum = 0
5729 01:24:36.013519 3, 0xFFFF, sum = 0
5730 01:24:36.016603 4, 0xFFFF, sum = 0
5731 01:24:36.016684 5, 0xFFFF, sum = 0
5732 01:24:36.020214 6, 0xFFFF, sum = 0
5733 01:24:36.023445 7, 0xFFFF, sum = 0
5734 01:24:36.023529 8, 0xFFFF, sum = 0
5735 01:24:36.026657 9, 0xFFFF, sum = 0
5736 01:24:36.026738 10, 0x0, sum = 1
5737 01:24:36.026803 11, 0x0, sum = 2
5738 01:24:36.030060 12, 0x0, sum = 3
5739 01:24:36.030142 13, 0x0, sum = 4
5740 01:24:36.033698 best_step = 11
5741 01:24:36.033778
5742 01:24:36.033841 ==
5743 01:24:36.036706 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 01:24:36.040278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 01:24:36.040376 ==
5746 01:24:36.043241 RX Vref Scan: 1
5747 01:24:36.043322
5748 01:24:36.046568 RX Vref 0 -> 0, step: 1
5749 01:24:36.046648
5750 01:24:36.046711 RX Delay -53 -> 252, step: 4
5751 01:24:36.046770
5752 01:24:36.049436 Set Vref, RX VrefLevel [Byte0]: 50
5753 01:24:36.052890 [Byte1]: 52
5754 01:24:36.057681
5755 01:24:36.057760 Final RX Vref Byte 0 = 50 to rank0
5756 01:24:36.060889 Final RX Vref Byte 1 = 52 to rank0
5757 01:24:36.064324 Final RX Vref Byte 0 = 50 to rank1
5758 01:24:36.067621 Final RX Vref Byte 1 = 52 to rank1==
5759 01:24:36.070801 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 01:24:36.076910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 01:24:36.076992 ==
5762 01:24:36.077056 DQS Delay:
5763 01:24:36.080710 DQS0 = 0, DQS1 = 0
5764 01:24:36.080790 DQM Delay:
5765 01:24:36.080854 DQM0 = 98, DQM1 = 94
5766 01:24:36.083865 DQ Delay:
5767 01:24:36.086822 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =98
5768 01:24:36.090327 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5769 01:24:36.093567 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5770 01:24:36.096945 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5771 01:24:36.097050
5772 01:24:36.097141
5773 01:24:36.103611 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5774 01:24:36.106877 CH1 RK0: MR19=505, MR18=717
5775 01:24:36.113572 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5776 01:24:36.113653
5777 01:24:36.116498 ----->DramcWriteLeveling(PI) begin...
5778 01:24:36.116580 ==
5779 01:24:36.119841 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 01:24:36.123571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 01:24:36.123652 ==
5782 01:24:36.126775 Write leveling (Byte 0): 24 => 24
5783 01:24:36.130128 Write leveling (Byte 1): 28 => 28
5784 01:24:36.133081 DramcWriteLeveling(PI) end<-----
5785 01:24:36.133161
5786 01:24:36.133224 ==
5787 01:24:36.136607 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 01:24:36.143024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 01:24:36.143104 ==
5790 01:24:36.143199 [Gating] SW mode calibration
5791 01:24:36.152873 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5792 01:24:36.156344 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5793 01:24:36.162905 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 01:24:36.166133 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 01:24:36.169550 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 01:24:36.172997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 01:24:36.179584 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 01:24:36.182719 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 01:24:36.185936 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5800 01:24:36.192826 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
5801 01:24:36.196147 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 01:24:36.199096 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 01:24:36.205879 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 01:24:36.209261 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 01:24:36.212208 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 01:24:36.219224 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 01:24:36.222147 0 15 24 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5808 01:24:36.225476 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5809 01:24:36.232140 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 01:24:36.235262 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 01:24:36.239219 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 01:24:36.246141 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 01:24:36.249155 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 01:24:36.252107 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 01:24:36.258717 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5816 01:24:36.261727 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5817 01:24:36.268367 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5818 01:24:36.271432 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 01:24:36.275143 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 01:24:36.278430 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 01:24:36.285225 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 01:24:36.288258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 01:24:36.291170 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 01:24:36.298541 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 01:24:36.301182 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 01:24:36.307530 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 01:24:36.311515 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 01:24:36.314953 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 01:24:36.321218 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 01:24:36.324116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 01:24:36.328028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5832 01:24:36.334092 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5833 01:24:36.334173 Total UI for P1: 0, mck2ui 16
5834 01:24:36.340886 best dqsien dly found for B0: ( 1, 2, 24)
5835 01:24:36.343840 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 01:24:36.347165 Total UI for P1: 0, mck2ui 16
5837 01:24:36.351070 best dqsien dly found for B1: ( 1, 2, 26)
5838 01:24:36.354246 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5839 01:24:36.357170 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5840 01:24:36.357250
5841 01:24:36.360786 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5842 01:24:36.363759 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5843 01:24:36.367043 [Gating] SW calibration Done
5844 01:24:36.367123 ==
5845 01:24:36.370455 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 01:24:36.373745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 01:24:36.376814 ==
5848 01:24:36.376894 RX Vref Scan: 0
5849 01:24:36.376958
5850 01:24:36.380726 RX Vref 0 -> 0, step: 1
5851 01:24:36.380807
5852 01:24:36.383305 RX Delay -80 -> 252, step: 8
5853 01:24:36.387321 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5854 01:24:36.390024 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5855 01:24:36.393752 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5856 01:24:36.396873 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5857 01:24:36.400019 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5858 01:24:36.406516 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5859 01:24:36.409595 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5860 01:24:36.413026 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5861 01:24:36.416740 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5862 01:24:36.419819 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5863 01:24:36.422833 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5864 01:24:36.429577 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5865 01:24:36.433110 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5866 01:24:36.436112 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5867 01:24:36.439211 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5868 01:24:36.442679 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5869 01:24:36.446342 ==
5870 01:24:36.449418 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 01:24:36.453175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 01:24:36.453285 ==
5873 01:24:36.453357 DQS Delay:
5874 01:24:36.455991 DQS0 = 0, DQS1 = 0
5875 01:24:36.456071 DQM Delay:
5876 01:24:36.459553 DQM0 = 97, DQM1 = 94
5877 01:24:36.459633 DQ Delay:
5878 01:24:36.462564 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5879 01:24:36.466289 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5880 01:24:36.468947 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5881 01:24:36.472435 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5882 01:24:36.472516
5883 01:24:36.472579
5884 01:24:36.472637 ==
5885 01:24:36.475718 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 01:24:36.478791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 01:24:36.482425 ==
5888 01:24:36.482505
5889 01:24:36.482568
5890 01:24:36.482627 TX Vref Scan disable
5891 01:24:36.485498 == TX Byte 0 ==
5892 01:24:36.488868 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5893 01:24:36.492089 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5894 01:24:36.495634 == TX Byte 1 ==
5895 01:24:36.498942 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5896 01:24:36.502352 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5897 01:24:36.505240 ==
5898 01:24:36.509354 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 01:24:36.511848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 01:24:36.511969 ==
5901 01:24:36.512034
5902 01:24:36.512093
5903 01:24:36.515661 TX Vref Scan disable
5904 01:24:36.515741 == TX Byte 0 ==
5905 01:24:36.521922 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5906 01:24:36.525161 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5907 01:24:36.525241 == TX Byte 1 ==
5908 01:24:36.531822 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5909 01:24:36.535351 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5910 01:24:36.535432
5911 01:24:36.535495 [DATLAT]
5912 01:24:36.538946 Freq=933, CH1 RK1
5913 01:24:36.539027
5914 01:24:36.539091 DATLAT Default: 0xb
5915 01:24:36.541649 0, 0xFFFF, sum = 0
5916 01:24:36.541730 1, 0xFFFF, sum = 0
5917 01:24:36.544804 2, 0xFFFF, sum = 0
5918 01:24:36.548145 3, 0xFFFF, sum = 0
5919 01:24:36.548226 4, 0xFFFF, sum = 0
5920 01:24:36.551239 5, 0xFFFF, sum = 0
5921 01:24:36.551320 6, 0xFFFF, sum = 0
5922 01:24:36.554861 7, 0xFFFF, sum = 0
5923 01:24:36.554943 8, 0xFFFF, sum = 0
5924 01:24:36.558310 9, 0xFFFF, sum = 0
5925 01:24:36.558391 10, 0x0, sum = 1
5926 01:24:36.561750 11, 0x0, sum = 2
5927 01:24:36.561831 12, 0x0, sum = 3
5928 01:24:36.564688 13, 0x0, sum = 4
5929 01:24:36.564769 best_step = 11
5930 01:24:36.564833
5931 01:24:36.564891 ==
5932 01:24:36.567883 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 01:24:36.570942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 01:24:36.571023 ==
5935 01:24:36.574686 RX Vref Scan: 0
5936 01:24:36.574788
5937 01:24:36.577778 RX Vref 0 -> 0, step: 1
5938 01:24:36.577859
5939 01:24:36.577922 RX Delay -53 -> 252, step: 4
5940 01:24:36.585347 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5941 01:24:36.589067 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5942 01:24:36.592152 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5943 01:24:36.595803 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5944 01:24:36.599005 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5945 01:24:36.605710 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5946 01:24:36.608657 iDelay=203, Bit 6, Center 102 (11 ~ 194) 184
5947 01:24:36.612587 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5948 01:24:36.616382 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5949 01:24:36.618673 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5950 01:24:36.622103 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5951 01:24:36.628658 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5952 01:24:36.631850 iDelay=203, Bit 12, Center 100 (7 ~ 194) 188
5953 01:24:36.634925 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5954 01:24:36.638062 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5955 01:24:36.645083 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5956 01:24:36.645165 ==
5957 01:24:36.648384 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 01:24:36.651620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 01:24:36.651704 ==
5960 01:24:36.651769 DQS Delay:
5961 01:24:36.654994 DQS0 = 0, DQS1 = 0
5962 01:24:36.655076 DQM Delay:
5963 01:24:36.658252 DQM0 = 96, DQM1 = 92
5964 01:24:36.658334 DQ Delay:
5965 01:24:36.661287 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5966 01:24:36.665138 DQ4 =96, DQ5 =108, DQ6 =102, DQ7 =92
5967 01:24:36.668468 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5968 01:24:36.671446 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5969 01:24:36.671528
5970 01:24:36.671592
5971 01:24:36.681144 [DQSOSCAuto] RK1, (LSB)MR18= 0x1128, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5972 01:24:36.681228 CH1 RK1: MR19=505, MR18=1128
5973 01:24:36.688040 CH1_RK1: MR19=0x505, MR18=0x1128, DQSOSC=409, MR23=63, INC=64, DEC=43
5974 01:24:36.690750 [RxdqsGatingPostProcess] freq 933
5975 01:24:36.697671 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5976 01:24:36.701192 best DQS0 dly(2T, 0.5T) = (0, 10)
5977 01:24:36.704142 best DQS1 dly(2T, 0.5T) = (0, 10)
5978 01:24:36.707712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5979 01:24:36.710716 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5980 01:24:36.714100 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 01:24:36.714181 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 01:24:36.717440 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 01:24:36.721001 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 01:24:36.723901 Pre-setting of DQS Precalculation
5985 01:24:36.730732 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5986 01:24:36.737108 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5987 01:24:36.743498 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5988 01:24:36.743579
5989 01:24:36.743642
5990 01:24:36.747150 [Calibration Summary] 1866 Mbps
5991 01:24:36.751354 CH 0, Rank 0
5992 01:24:36.751434 SW Impedance : PASS
5993 01:24:36.753544 DUTY Scan : NO K
5994 01:24:36.756805 ZQ Calibration : PASS
5995 01:24:36.756886 Jitter Meter : NO K
5996 01:24:36.760125 CBT Training : PASS
5997 01:24:36.763416 Write leveling : PASS
5998 01:24:36.763496 RX DQS gating : PASS
5999 01:24:36.767425 RX DQ/DQS(RDDQC) : PASS
6000 01:24:36.767539 TX DQ/DQS : PASS
6001 01:24:36.770221 RX DATLAT : PASS
6002 01:24:36.774170 RX DQ/DQS(Engine): PASS
6003 01:24:36.774251 TX OE : NO K
6004 01:24:36.776487 All Pass.
6005 01:24:36.776566
6006 01:24:36.776630 CH 0, Rank 1
6007 01:24:36.780398 SW Impedance : PASS
6008 01:24:36.780478 DUTY Scan : NO K
6009 01:24:36.782945 ZQ Calibration : PASS
6010 01:24:36.787004 Jitter Meter : NO K
6011 01:24:36.787084 CBT Training : PASS
6012 01:24:36.789974 Write leveling : PASS
6013 01:24:36.792849 RX DQS gating : PASS
6014 01:24:36.792930 RX DQ/DQS(RDDQC) : PASS
6015 01:24:36.796092 TX DQ/DQS : PASS
6016 01:24:36.799797 RX DATLAT : PASS
6017 01:24:36.799877 RX DQ/DQS(Engine): PASS
6018 01:24:36.803138 TX OE : NO K
6019 01:24:36.803219 All Pass.
6020 01:24:36.803282
6021 01:24:36.806163 CH 1, Rank 0
6022 01:24:36.806244 SW Impedance : PASS
6023 01:24:36.809371 DUTY Scan : NO K
6024 01:24:36.812740 ZQ Calibration : PASS
6025 01:24:36.812820 Jitter Meter : NO K
6026 01:24:36.815730 CBT Training : PASS
6027 01:24:36.819246 Write leveling : PASS
6028 01:24:36.819326 RX DQS gating : PASS
6029 01:24:36.822930 RX DQ/DQS(RDDQC) : PASS
6030 01:24:36.825963 TX DQ/DQS : PASS
6031 01:24:36.826044 RX DATLAT : PASS
6032 01:24:36.828971 RX DQ/DQS(Engine): PASS
6033 01:24:36.832322 TX OE : NO K
6034 01:24:36.832402 All Pass.
6035 01:24:36.832465
6036 01:24:36.832524 CH 1, Rank 1
6037 01:24:36.835886 SW Impedance : PASS
6038 01:24:36.839373 DUTY Scan : NO K
6039 01:24:36.839454 ZQ Calibration : PASS
6040 01:24:36.842679 Jitter Meter : NO K
6041 01:24:36.845722 CBT Training : PASS
6042 01:24:36.845802 Write leveling : PASS
6043 01:24:36.849254 RX DQS gating : PASS
6044 01:24:36.852185 RX DQ/DQS(RDDQC) : PASS
6045 01:24:36.852264 TX DQ/DQS : PASS
6046 01:24:36.855339 RX DATLAT : PASS
6047 01:24:36.858988 RX DQ/DQS(Engine): PASS
6048 01:24:36.859068 TX OE : NO K
6049 01:24:36.859132 All Pass.
6050 01:24:36.861825
6051 01:24:36.861905 DramC Write-DBI off
6052 01:24:36.865192 PER_BANK_REFRESH: Hybrid Mode
6053 01:24:36.865272 TX_TRACKING: ON
6054 01:24:36.875506 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6055 01:24:36.878842 [FAST_K] Save calibration result to emmc
6056 01:24:36.882012 dramc_set_vcore_voltage set vcore to 650000
6057 01:24:36.885155 Read voltage for 400, 6
6058 01:24:36.885260 Vio18 = 0
6059 01:24:36.888482 Vcore = 650000
6060 01:24:36.888564 Vdram = 0
6061 01:24:36.888629 Vddq = 0
6062 01:24:36.892039 Vmddr = 0
6063 01:24:36.894790 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6064 01:24:36.901973 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6065 01:24:36.902054 MEM_TYPE=3, freq_sel=20
6066 01:24:36.905032 sv_algorithm_assistance_LP4_800
6067 01:24:36.908342 ============ PULL DRAM RESETB DOWN ============
6068 01:24:36.914825 ========== PULL DRAM RESETB DOWN end =========
6069 01:24:36.917851 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6070 01:24:36.921567 ===================================
6071 01:24:36.924433 LPDDR4 DRAM CONFIGURATION
6072 01:24:36.927878 ===================================
6073 01:24:36.928007 EX_ROW_EN[0] = 0x0
6074 01:24:36.931059 EX_ROW_EN[1] = 0x0
6075 01:24:36.934375 LP4Y_EN = 0x0
6076 01:24:36.934479 WORK_FSP = 0x0
6077 01:24:36.937790 WL = 0x2
6078 01:24:36.937870 RL = 0x2
6079 01:24:36.941410 BL = 0x2
6080 01:24:36.941494 RPST = 0x0
6081 01:24:36.944544 RD_PRE = 0x0
6082 01:24:36.944624 WR_PRE = 0x1
6083 01:24:36.947859 WR_PST = 0x0
6084 01:24:36.947959 DBI_WR = 0x0
6085 01:24:36.951482 DBI_RD = 0x0
6086 01:24:36.951562 OTF = 0x1
6087 01:24:36.954301 ===================================
6088 01:24:36.957638 ===================================
6089 01:24:36.961014 ANA top config
6090 01:24:36.964279 ===================================
6091 01:24:36.964363 DLL_ASYNC_EN = 0
6092 01:24:36.967514 ALL_SLAVE_EN = 1
6093 01:24:36.970828 NEW_RANK_MODE = 1
6094 01:24:36.974247 DLL_IDLE_MODE = 1
6095 01:24:36.977412 LP45_APHY_COMB_EN = 1
6096 01:24:36.977493 TX_ODT_DIS = 1
6097 01:24:36.980840 NEW_8X_MODE = 1
6098 01:24:36.984153 ===================================
6099 01:24:36.987252 ===================================
6100 01:24:36.990380 data_rate = 800
6101 01:24:36.994302 CKR = 1
6102 01:24:36.997568 DQ_P2S_RATIO = 4
6103 01:24:37.000475 ===================================
6104 01:24:37.003520 CA_P2S_RATIO = 4
6105 01:24:37.003601 DQ_CA_OPEN = 0
6106 01:24:37.007370 DQ_SEMI_OPEN = 1
6107 01:24:37.010223 CA_SEMI_OPEN = 1
6108 01:24:37.013748 CA_FULL_RATE = 0
6109 01:24:37.017458 DQ_CKDIV4_EN = 0
6110 01:24:37.020434 CA_CKDIV4_EN = 1
6111 01:24:37.020546 CA_PREDIV_EN = 0
6112 01:24:37.023322 PH8_DLY = 0
6113 01:24:37.026929 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6114 01:24:37.030450 DQ_AAMCK_DIV = 0
6115 01:24:37.033827 CA_AAMCK_DIV = 0
6116 01:24:37.036271 CA_ADMCK_DIV = 4
6117 01:24:37.039871 DQ_TRACK_CA_EN = 0
6118 01:24:37.039961 CA_PICK = 800
6119 01:24:37.043405 CA_MCKIO = 400
6120 01:24:37.046316 MCKIO_SEMI = 400
6121 01:24:37.049722 PLL_FREQ = 3016
6122 01:24:37.052839 DQ_UI_PI_RATIO = 32
6123 01:24:37.056150 CA_UI_PI_RATIO = 32
6124 01:24:37.059683 ===================================
6125 01:24:37.062825 ===================================
6126 01:24:37.066006 memory_type:LPDDR4
6127 01:24:37.066087 GP_NUM : 10
6128 01:24:37.069714 SRAM_EN : 1
6129 01:24:37.069821 MD32_EN : 0
6130 01:24:37.072997 ===================================
6131 01:24:37.076399 [ANA_INIT] >>>>>>>>>>>>>>
6132 01:24:37.079711 <<<<<< [CONFIGURE PHASE]: ANA_TX
6133 01:24:37.082875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6134 01:24:37.086318 ===================================
6135 01:24:37.089366 data_rate = 800,PCW = 0X7400
6136 01:24:37.092832 ===================================
6137 01:24:37.095802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6138 01:24:37.102565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 01:24:37.112474 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6140 01:24:37.116162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6141 01:24:37.118988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6142 01:24:37.125564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6143 01:24:37.125647 [ANA_INIT] flow start
6144 01:24:37.128641 [ANA_INIT] PLL >>>>>>>>
6145 01:24:37.128722 [ANA_INIT] PLL <<<<<<<<
6146 01:24:37.132286 [ANA_INIT] MIDPI >>>>>>>>
6147 01:24:37.135462 [ANA_INIT] MIDPI <<<<<<<<
6148 01:24:37.138685 [ANA_INIT] DLL >>>>>>>>
6149 01:24:37.138765 [ANA_INIT] flow end
6150 01:24:37.142437 ============ LP4 DIFF to SE enter ============
6151 01:24:37.148989 ============ LP4 DIFF to SE exit ============
6152 01:24:37.149071 [ANA_INIT] <<<<<<<<<<<<<
6153 01:24:37.152167 [Flow] Enable top DCM control >>>>>
6154 01:24:37.155445 [Flow] Enable top DCM control <<<<<
6155 01:24:37.158649 Enable DLL master slave shuffle
6156 01:24:37.165099 ==============================================================
6157 01:24:37.168630 Gating Mode config
6158 01:24:37.171491 ==============================================================
6159 01:24:37.174962 Config description:
6160 01:24:37.184642 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6161 01:24:37.191832 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6162 01:24:37.194678 SELPH_MODE 0: By rank 1: By Phase
6163 01:24:37.201217 ==============================================================
6164 01:24:37.204814 GAT_TRACK_EN = 0
6165 01:24:37.207793 RX_GATING_MODE = 2
6166 01:24:37.210981 RX_GATING_TRACK_MODE = 2
6167 01:24:37.214553 SELPH_MODE = 1
6168 01:24:37.214660 PICG_EARLY_EN = 1
6169 01:24:37.217994 VALID_LAT_VALUE = 1
6170 01:24:37.224299 ==============================================================
6171 01:24:37.228419 Enter into Gating configuration >>>>
6172 01:24:37.231013 Exit from Gating configuration <<<<
6173 01:24:37.234617 Enter into DVFS_PRE_config >>>>>
6174 01:24:37.243878 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6175 01:24:37.247348 Exit from DVFS_PRE_config <<<<<
6176 01:24:37.250964 Enter into PICG configuration >>>>
6177 01:24:37.253955 Exit from PICG configuration <<<<
6178 01:24:37.257674 [RX_INPUT] configuration >>>>>
6179 01:24:37.260957 [RX_INPUT] configuration <<<<<
6180 01:24:37.264199 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6181 01:24:37.270594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6182 01:24:37.276896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 01:24:37.283630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 01:24:37.290159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 01:24:37.296841 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 01:24:37.300239 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6187 01:24:37.303413 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6188 01:24:37.307110 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6189 01:24:37.313735 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6190 01:24:37.317262 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6191 01:24:37.319891 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 01:24:37.323544 ===================================
6193 01:24:37.326405 LPDDR4 DRAM CONFIGURATION
6194 01:24:37.330088 ===================================
6195 01:24:37.333292 EX_ROW_EN[0] = 0x0
6196 01:24:37.333373 EX_ROW_EN[1] = 0x0
6197 01:24:37.336082 LP4Y_EN = 0x0
6198 01:24:37.336162 WORK_FSP = 0x0
6199 01:24:37.339659 WL = 0x2
6200 01:24:37.339739 RL = 0x2
6201 01:24:37.342846 BL = 0x2
6202 01:24:37.342926 RPST = 0x0
6203 01:24:37.346466 RD_PRE = 0x0
6204 01:24:37.346584 WR_PRE = 0x1
6205 01:24:37.349454 WR_PST = 0x0
6206 01:24:37.349537 DBI_WR = 0x0
6207 01:24:37.353257 DBI_RD = 0x0
6208 01:24:37.353338 OTF = 0x1
6209 01:24:37.355892 ===================================
6210 01:24:37.362787 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6211 01:24:37.365875 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6212 01:24:37.369641 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6213 01:24:37.372333 ===================================
6214 01:24:37.375771 LPDDR4 DRAM CONFIGURATION
6215 01:24:37.379607 ===================================
6216 01:24:37.382356 EX_ROW_EN[0] = 0x10
6217 01:24:37.382437 EX_ROW_EN[1] = 0x0
6218 01:24:37.386156 LP4Y_EN = 0x0
6219 01:24:37.386237 WORK_FSP = 0x0
6220 01:24:37.388820 WL = 0x2
6221 01:24:37.388943 RL = 0x2
6222 01:24:37.392107 BL = 0x2
6223 01:24:37.392205 RPST = 0x0
6224 01:24:37.396392 RD_PRE = 0x0
6225 01:24:37.396488 WR_PRE = 0x1
6226 01:24:37.399223 WR_PST = 0x0
6227 01:24:37.399304 DBI_WR = 0x0
6228 01:24:37.402648 DBI_RD = 0x0
6229 01:24:37.402729 OTF = 0x1
6230 01:24:37.405785 ===================================
6231 01:24:37.412324 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6232 01:24:37.416972 nWR fixed to 30
6233 01:24:37.419822 [ModeRegInit_LP4] CH0 RK0
6234 01:24:37.419937 [ModeRegInit_LP4] CH0 RK1
6235 01:24:37.423382 [ModeRegInit_LP4] CH1 RK0
6236 01:24:37.426518 [ModeRegInit_LP4] CH1 RK1
6237 01:24:37.426599 match AC timing 19
6238 01:24:37.433034 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6239 01:24:37.436395 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6240 01:24:37.439597 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6241 01:24:37.446547 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6242 01:24:37.449396 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6243 01:24:37.449477 ==
6244 01:24:37.453268 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 01:24:37.456094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 01:24:37.459342 ==
6247 01:24:37.462815 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 01:24:37.469345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6249 01:24:37.472733 [CA 0] Center 36 (8~64) winsize 57
6250 01:24:37.475835 [CA 1] Center 36 (8~64) winsize 57
6251 01:24:37.479683 [CA 2] Center 36 (8~64) winsize 57
6252 01:24:37.482562 [CA 3] Center 36 (8~64) winsize 57
6253 01:24:37.485667 [CA 4] Center 36 (8~64) winsize 57
6254 01:24:37.488879 [CA 5] Center 36 (8~64) winsize 57
6255 01:24:37.488985
6256 01:24:37.492317 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6257 01:24:37.492399
6258 01:24:37.495489 [CATrainingPosCal] consider 1 rank data
6259 01:24:37.499204 u2DelayCellTimex100 = 270/100 ps
6260 01:24:37.502031 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 01:24:37.505287 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 01:24:37.508604 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 01:24:37.512412 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 01:24:37.515118 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 01:24:37.518746 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 01:24:37.518827
6267 01:24:37.525440 CA PerBit enable=1, Macro0, CA PI delay=36
6268 01:24:37.525522
6269 01:24:37.528476 [CBTSetCACLKResult] CA Dly = 36
6270 01:24:37.528557 CS Dly: 1 (0~32)
6271 01:24:37.528621 ==
6272 01:24:37.531507 Dram Type= 6, Freq= 0, CH_0, rank 1
6273 01:24:37.535015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 01:24:37.535095 ==
6275 01:24:37.541679 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 01:24:37.548147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6277 01:24:37.551857 [CA 0] Center 36 (8~64) winsize 57
6278 01:24:37.555188 [CA 1] Center 36 (8~64) winsize 57
6279 01:24:37.558420 [CA 2] Center 36 (8~64) winsize 57
6280 01:24:37.561623 [CA 3] Center 36 (8~64) winsize 57
6281 01:24:37.564768 [CA 4] Center 36 (8~64) winsize 57
6282 01:24:37.567815 [CA 5] Center 36 (8~64) winsize 57
6283 01:24:37.567950
6284 01:24:37.570889 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6285 01:24:37.571000
6286 01:24:37.574533 [CATrainingPosCal] consider 2 rank data
6287 01:24:37.577800 u2DelayCellTimex100 = 270/100 ps
6288 01:24:37.581315 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 01:24:37.585396 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 01:24:37.587721 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 01:24:37.590823 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 01:24:37.594523 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 01:24:37.597829 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 01:24:37.597940
6295 01:24:37.604402 CA PerBit enable=1, Macro0, CA PI delay=36
6296 01:24:37.604484
6297 01:24:37.604548 [CBTSetCACLKResult] CA Dly = 36
6298 01:24:37.607424 CS Dly: 1 (0~32)
6299 01:24:37.607505
6300 01:24:37.610931 ----->DramcWriteLeveling(PI) begin...
6301 01:24:37.611013 ==
6302 01:24:37.613819 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 01:24:37.617434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 01:24:37.617516 ==
6305 01:24:37.620385 Write leveling (Byte 0): 40 => 8
6306 01:24:37.624260 Write leveling (Byte 1): 40 => 8
6307 01:24:37.627275 DramcWriteLeveling(PI) end<-----
6308 01:24:37.627371
6309 01:24:37.627466 ==
6310 01:24:37.630728 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 01:24:37.637626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 01:24:37.637732 ==
6313 01:24:37.637814 [Gating] SW mode calibration
6314 01:24:37.647166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6315 01:24:37.650060 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6316 01:24:37.653662 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 01:24:37.660684 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6318 01:24:37.663653 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 01:24:37.666508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 01:24:37.673369 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 01:24:37.677020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 01:24:37.683528 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 01:24:37.686563 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 01:24:37.689628 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 01:24:37.692990 Total UI for P1: 0, mck2ui 16
6326 01:24:37.696157 best dqsien dly found for B0: ( 0, 14, 24)
6327 01:24:37.699878 Total UI for P1: 0, mck2ui 16
6328 01:24:37.702861 best dqsien dly found for B1: ( 0, 14, 24)
6329 01:24:37.707195 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6330 01:24:37.709915 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6331 01:24:37.709996
6332 01:24:37.715718 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 01:24:37.720292 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6334 01:24:37.720373 [Gating] SW calibration Done
6335 01:24:37.722797 ==
6336 01:24:37.725692 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 01:24:37.729054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 01:24:37.729136 ==
6339 01:24:37.729201 RX Vref Scan: 0
6340 01:24:37.729261
6341 01:24:37.732303 RX Vref 0 -> 0, step: 1
6342 01:24:37.732383
6343 01:24:37.736494 RX Delay -410 -> 252, step: 16
6344 01:24:37.739556 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6345 01:24:37.742420 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6346 01:24:37.748858 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6347 01:24:37.752750 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6348 01:24:37.755455 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6349 01:24:37.762164 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6350 01:24:37.765686 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6351 01:24:37.769504 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6352 01:24:37.771932 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6353 01:24:37.778733 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6354 01:24:37.781997 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6355 01:24:37.784922 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6356 01:24:37.788276 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6357 01:24:37.794750 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6358 01:24:37.798029 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6359 01:24:37.801715 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6360 01:24:37.801796 ==
6361 01:24:37.804701 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 01:24:37.811157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 01:24:37.811237 ==
6364 01:24:37.811308 DQS Delay:
6365 01:24:37.814884 DQS0 = 35, DQS1 = 51
6366 01:24:37.814964 DQM Delay:
6367 01:24:37.815026 DQM0 = 5, DQM1 = 11
6368 01:24:37.817978 DQ Delay:
6369 01:24:37.820888 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6370 01:24:37.824273 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6371 01:24:37.824352 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6372 01:24:37.827512 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6373 01:24:37.831084
6374 01:24:37.831164
6375 01:24:37.831226 ==
6376 01:24:37.834789 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 01:24:37.837592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 01:24:37.837672 ==
6379 01:24:37.837734
6380 01:24:37.837792
6381 01:24:37.841581 TX Vref Scan disable
6382 01:24:37.841660 == TX Byte 0 ==
6383 01:24:37.844685 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 01:24:37.851041 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 01:24:37.851121 == TX Byte 1 ==
6386 01:24:37.854681 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 01:24:37.861037 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 01:24:37.861117 ==
6389 01:24:37.864426 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 01:24:37.867813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 01:24:37.867917 ==
6392 01:24:37.867998
6393 01:24:37.868057
6394 01:24:37.870911 TX Vref Scan disable
6395 01:24:37.870990 == TX Byte 0 ==
6396 01:24:37.877249 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 01:24:37.880332 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 01:24:37.880412 == TX Byte 1 ==
6399 01:24:37.887732 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 01:24:37.890530 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 01:24:37.890610
6402 01:24:37.890674 [DATLAT]
6403 01:24:37.893541 Freq=400, CH0 RK0
6404 01:24:37.893621
6405 01:24:37.893684 DATLAT Default: 0xf
6406 01:24:37.897268 0, 0xFFFF, sum = 0
6407 01:24:37.897349 1, 0xFFFF, sum = 0
6408 01:24:37.900260 2, 0xFFFF, sum = 0
6409 01:24:37.900373 3, 0xFFFF, sum = 0
6410 01:24:37.903785 4, 0xFFFF, sum = 0
6411 01:24:37.903868 5, 0xFFFF, sum = 0
6412 01:24:37.906739 6, 0xFFFF, sum = 0
6413 01:24:37.906854 7, 0xFFFF, sum = 0
6414 01:24:37.909940 8, 0xFFFF, sum = 0
6415 01:24:37.910021 9, 0xFFFF, sum = 0
6416 01:24:37.913382 10, 0xFFFF, sum = 0
6417 01:24:37.916677 11, 0xFFFF, sum = 0
6418 01:24:37.916758 12, 0xFFFF, sum = 0
6419 01:24:37.919671 13, 0x0, sum = 1
6420 01:24:37.919752 14, 0x0, sum = 2
6421 01:24:37.922986 15, 0x0, sum = 3
6422 01:24:37.923067 16, 0x0, sum = 4
6423 01:24:37.923131 best_step = 14
6424 01:24:37.926382
6425 01:24:37.926461 ==
6426 01:24:37.929947 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 01:24:37.932769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 01:24:37.932849 ==
6429 01:24:37.932913 RX Vref Scan: 1
6430 01:24:37.932972
6431 01:24:37.936568 RX Vref 0 -> 0, step: 1
6432 01:24:37.936648
6433 01:24:37.939779 RX Delay -343 -> 252, step: 8
6434 01:24:37.939861
6435 01:24:37.943378 Set Vref, RX VrefLevel [Byte0]: 51
6436 01:24:37.946078 [Byte1]: 59
6437 01:24:37.950167
6438 01:24:37.950263 Final RX Vref Byte 0 = 51 to rank0
6439 01:24:37.953593 Final RX Vref Byte 1 = 59 to rank0
6440 01:24:37.956966 Final RX Vref Byte 0 = 51 to rank1
6441 01:24:37.960428 Final RX Vref Byte 1 = 59 to rank1==
6442 01:24:37.963550 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 01:24:37.970061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 01:24:37.970141 ==
6445 01:24:37.970205 DQS Delay:
6446 01:24:37.973232 DQS0 = 40, DQS1 = 60
6447 01:24:37.973361 DQM Delay:
6448 01:24:37.973454 DQM0 = 6, DQM1 = 15
6449 01:24:37.976765 DQ Delay:
6450 01:24:37.979864 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6451 01:24:37.979968 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6452 01:24:37.983183 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6453 01:24:37.986278 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6454 01:24:37.986358
6455 01:24:37.989964
6456 01:24:37.996141 [DQSOSCAuto] RK0, (LSB)MR18= 0x9387, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6457 01:24:37.999557 CH0 RK0: MR19=C0C, MR18=9387
6458 01:24:38.006061 CH0_RK0: MR19=0xC0C, MR18=0x9387, DQSOSC=391, MR23=63, INC=386, DEC=257
6459 01:24:38.006142 ==
6460 01:24:38.009438 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 01:24:38.013125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 01:24:38.013206 ==
6463 01:24:38.016347 [Gating] SW mode calibration
6464 01:24:38.023026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6465 01:24:38.029039 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6466 01:24:38.032388 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 01:24:38.035561 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6468 01:24:38.042476 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 01:24:38.045413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 01:24:38.048901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 01:24:38.055662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 01:24:38.058745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 01:24:38.061923 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 01:24:38.068779 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 01:24:38.068860 Total UI for P1: 0, mck2ui 16
6476 01:24:38.075848 best dqsien dly found for B0: ( 0, 14, 24)
6477 01:24:38.075955 Total UI for P1: 0, mck2ui 16
6478 01:24:38.081684 best dqsien dly found for B1: ( 0, 14, 24)
6479 01:24:38.085302 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6480 01:24:38.088082 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6481 01:24:38.088163
6482 01:24:38.091347 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 01:24:38.095355 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6484 01:24:38.098355 [Gating] SW calibration Done
6485 01:24:38.098434 ==
6486 01:24:38.101714 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 01:24:38.104595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 01:24:38.104676 ==
6489 01:24:38.108060 RX Vref Scan: 0
6490 01:24:38.108140
6491 01:24:38.111179 RX Vref 0 -> 0, step: 1
6492 01:24:38.111259
6493 01:24:38.111322 RX Delay -410 -> 252, step: 16
6494 01:24:38.118314 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6495 01:24:38.121375 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6496 01:24:38.124683 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6497 01:24:38.131002 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6498 01:24:38.134338 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6499 01:24:38.138203 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6500 01:24:38.140830 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6501 01:24:38.147728 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6502 01:24:38.150641 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6503 01:24:38.153970 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6504 01:24:38.157834 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6505 01:24:38.164058 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6506 01:24:38.167314 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6507 01:24:38.170598 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6508 01:24:38.177224 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6509 01:24:38.180522 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6510 01:24:38.180603 ==
6511 01:24:38.183847 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 01:24:38.187549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 01:24:38.187630 ==
6514 01:24:38.190105 DQS Delay:
6515 01:24:38.190185 DQS0 = 35, DQS1 = 59
6516 01:24:38.190248 DQM Delay:
6517 01:24:38.193921 DQM0 = 6, DQM1 = 16
6518 01:24:38.194001 DQ Delay:
6519 01:24:38.196788 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6520 01:24:38.200254 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6521 01:24:38.203668 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6522 01:24:38.206819 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6523 01:24:38.206900
6524 01:24:38.206963
6525 01:24:38.207021 ==
6526 01:24:38.210337 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 01:24:38.213530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 01:24:38.216936 ==
6529 01:24:38.217016
6530 01:24:38.217079
6531 01:24:38.217138 TX Vref Scan disable
6532 01:24:38.219893 == TX Byte 0 ==
6533 01:24:38.223016 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6534 01:24:38.226433 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6535 01:24:38.230391 == TX Byte 1 ==
6536 01:24:38.233722 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6537 01:24:38.236607 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6538 01:24:38.236687 ==
6539 01:24:38.239782 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 01:24:38.246758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 01:24:38.246838 ==
6542 01:24:38.246901
6543 01:24:38.246959
6544 01:24:38.247029 TX Vref Scan disable
6545 01:24:38.249183 == TX Byte 0 ==
6546 01:24:38.252450 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6547 01:24:38.255990 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6548 01:24:38.260067 == TX Byte 1 ==
6549 01:24:38.262691 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6550 01:24:38.265712 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6551 01:24:38.265793
6552 01:24:38.268828 [DATLAT]
6553 01:24:38.268908 Freq=400, CH0 RK1
6554 01:24:38.268971
6555 01:24:38.272683 DATLAT Default: 0xe
6556 01:24:38.272763 0, 0xFFFF, sum = 0
6557 01:24:38.275800 1, 0xFFFF, sum = 0
6558 01:24:38.275882 2, 0xFFFF, sum = 0
6559 01:24:38.278749 3, 0xFFFF, sum = 0
6560 01:24:38.278831 4, 0xFFFF, sum = 0
6561 01:24:38.282407 5, 0xFFFF, sum = 0
6562 01:24:38.282490 6, 0xFFFF, sum = 0
6563 01:24:38.285604 7, 0xFFFF, sum = 0
6564 01:24:38.285685 8, 0xFFFF, sum = 0
6565 01:24:38.288832 9, 0xFFFF, sum = 0
6566 01:24:38.292179 10, 0xFFFF, sum = 0
6567 01:24:38.292261 11, 0xFFFF, sum = 0
6568 01:24:38.295449 12, 0xFFFF, sum = 0
6569 01:24:38.295530 13, 0x0, sum = 1
6570 01:24:38.299029 14, 0x0, sum = 2
6571 01:24:38.299109 15, 0x0, sum = 3
6572 01:24:38.299174 16, 0x0, sum = 4
6573 01:24:38.302356 best_step = 14
6574 01:24:38.302435
6575 01:24:38.302499 ==
6576 01:24:38.305425 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 01:24:38.308602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 01:24:38.308683 ==
6579 01:24:38.312209 RX Vref Scan: 0
6580 01:24:38.312317
6581 01:24:38.315437 RX Vref 0 -> 0, step: 1
6582 01:24:38.315517
6583 01:24:38.315581 RX Delay -359 -> 252, step: 8
6584 01:24:38.324029 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6585 01:24:38.327166 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6586 01:24:38.330654 iDelay=209, Bit 2, Center -36 (-271 ~ 200) 472
6587 01:24:38.337762 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6588 01:24:38.340513 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6589 01:24:38.344056 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6590 01:24:38.346927 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6591 01:24:38.353422 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6592 01:24:38.356907 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6593 01:24:38.360718 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6594 01:24:38.363746 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6595 01:24:38.369793 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6596 01:24:38.373506 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6597 01:24:38.376285 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6598 01:24:38.380485 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6599 01:24:38.386542 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6600 01:24:38.386649 ==
6601 01:24:38.389745 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 01:24:38.394200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 01:24:38.394281 ==
6604 01:24:38.396786 DQS Delay:
6605 01:24:38.396865 DQS0 = 44, DQS1 = 60
6606 01:24:38.396929 DQM Delay:
6607 01:24:38.399843 DQM0 = 10, DQM1 = 14
6608 01:24:38.399975 DQ Delay:
6609 01:24:38.403383 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6610 01:24:38.406249 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6611 01:24:38.409703 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6612 01:24:38.412832 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6613 01:24:38.412912
6614 01:24:38.412975
6615 01:24:38.423139 [DQSOSCAuto] RK1, (LSB)MR18= 0x918a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6616 01:24:38.423220 CH0 RK1: MR19=C0C, MR18=918A
6617 01:24:38.429952 CH0_RK1: MR19=0xC0C, MR18=0x918A, DQSOSC=391, MR23=63, INC=386, DEC=257
6618 01:24:38.432821 [RxdqsGatingPostProcess] freq 400
6619 01:24:38.439507 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6620 01:24:38.442430 best DQS0 dly(2T, 0.5T) = (0, 10)
6621 01:24:38.447026 best DQS1 dly(2T, 0.5T) = (0, 10)
6622 01:24:38.449179 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6623 01:24:38.452677 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6624 01:24:38.455736 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 01:24:38.455817 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 01:24:38.459477 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 01:24:38.462697 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 01:24:38.465917 Pre-setting of DQS Precalculation
6629 01:24:38.472058 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6630 01:24:38.472138 ==
6631 01:24:38.475438 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 01:24:38.478537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 01:24:38.478618 ==
6634 01:24:38.485396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 01:24:38.491932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6636 01:24:38.494989 [CA 0] Center 36 (8~64) winsize 57
6637 01:24:38.498143 [CA 1] Center 36 (8~64) winsize 57
6638 01:24:38.501678 [CA 2] Center 36 (8~64) winsize 57
6639 01:24:38.505337 [CA 3] Center 36 (8~64) winsize 57
6640 01:24:38.508160 [CA 4] Center 36 (8~64) winsize 57
6641 01:24:38.511621 [CA 5] Center 36 (8~64) winsize 57
6642 01:24:38.511700
6643 01:24:38.514813 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6644 01:24:38.514897
6645 01:24:38.517985 [CATrainingPosCal] consider 1 rank data
6646 01:24:38.521643 u2DelayCellTimex100 = 270/100 ps
6647 01:24:38.524442 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 01:24:38.527801 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 01:24:38.531330 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 01:24:38.535123 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 01:24:38.537797 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 01:24:38.540843 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 01:24:38.540923
6654 01:24:38.547576 CA PerBit enable=1, Macro0, CA PI delay=36
6655 01:24:38.547656
6656 01:24:38.547720 [CBTSetCACLKResult] CA Dly = 36
6657 01:24:38.551167 CS Dly: 1 (0~32)
6658 01:24:38.551247 ==
6659 01:24:38.554261 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 01:24:38.557367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 01:24:38.557448 ==
6662 01:24:38.564273 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 01:24:38.570679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6664 01:24:38.574633 [CA 0] Center 36 (8~64) winsize 57
6665 01:24:38.577770 [CA 1] Center 36 (8~64) winsize 57
6666 01:24:38.581099 [CA 2] Center 36 (8~64) winsize 57
6667 01:24:38.581179 [CA 3] Center 36 (8~64) winsize 57
6668 01:24:38.583871 [CA 4] Center 36 (8~64) winsize 57
6669 01:24:38.587378 [CA 5] Center 36 (8~64) winsize 57
6670 01:24:38.587458
6671 01:24:38.594468 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6672 01:24:38.594549
6673 01:24:38.598095 [CATrainingPosCal] consider 2 rank data
6674 01:24:38.600711 u2DelayCellTimex100 = 270/100 ps
6675 01:24:38.604713 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 01:24:38.607660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 01:24:38.610836 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 01:24:38.613489 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 01:24:38.617305 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 01:24:38.620253 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 01:24:38.620333
6682 01:24:38.623698 CA PerBit enable=1, Macro0, CA PI delay=36
6683 01:24:38.623778
6684 01:24:38.626764 [CBTSetCACLKResult] CA Dly = 36
6685 01:24:38.630149 CS Dly: 1 (0~32)
6686 01:24:38.630229
6687 01:24:38.633241 ----->DramcWriteLeveling(PI) begin...
6688 01:24:38.633323 ==
6689 01:24:38.637355 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 01:24:38.640346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 01:24:38.640427 ==
6692 01:24:38.643470 Write leveling (Byte 0): 40 => 8
6693 01:24:38.646757 Write leveling (Byte 1): 40 => 8
6694 01:24:38.649775 DramcWriteLeveling(PI) end<-----
6695 01:24:38.649855
6696 01:24:38.649919 ==
6697 01:24:38.652966 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 01:24:38.656589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 01:24:38.656670 ==
6700 01:24:38.660022 [Gating] SW mode calibration
6701 01:24:38.666636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6702 01:24:38.673070 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6703 01:24:38.676058 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 01:24:38.683336 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6705 01:24:38.686181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 01:24:38.689591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 01:24:38.696054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 01:24:38.699700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 01:24:38.703213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 01:24:38.709939 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 01:24:38.712355 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 01:24:38.715956 Total UI for P1: 0, mck2ui 16
6713 01:24:38.719396 best dqsien dly found for B0: ( 0, 14, 24)
6714 01:24:38.722540 Total UI for P1: 0, mck2ui 16
6715 01:24:38.725479 best dqsien dly found for B1: ( 0, 14, 24)
6716 01:24:38.729269 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6717 01:24:38.732139 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6718 01:24:38.732219
6719 01:24:38.736149 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 01:24:38.738898 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6721 01:24:38.741833 [Gating] SW calibration Done
6722 01:24:38.741914 ==
6723 01:24:38.745226 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 01:24:38.751955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 01:24:38.752037 ==
6726 01:24:38.752102 RX Vref Scan: 0
6727 01:24:38.752162
6728 01:24:38.755108 RX Vref 0 -> 0, step: 1
6729 01:24:38.755193
6730 01:24:38.758771 RX Delay -410 -> 252, step: 16
6731 01:24:38.761729 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6732 01:24:38.764885 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6733 01:24:38.771600 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6734 01:24:38.775498 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6735 01:24:38.778150 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6736 01:24:38.781570 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6737 01:24:38.787836 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6738 01:24:38.791174 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6739 01:24:38.794587 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6740 01:24:38.797864 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6741 01:24:38.804710 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6742 01:24:38.807882 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6743 01:24:38.811535 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6744 01:24:38.817566 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6745 01:24:38.821001 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6746 01:24:38.824207 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6747 01:24:38.824287 ==
6748 01:24:38.827541 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 01:24:38.830530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 01:24:38.834330 ==
6751 01:24:38.834410 DQS Delay:
6752 01:24:38.834474 DQS0 = 43, DQS1 = 51
6753 01:24:38.837783 DQM Delay:
6754 01:24:38.837863 DQM0 = 13, DQM1 = 13
6755 01:24:38.840694 DQ Delay:
6756 01:24:38.840775 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6757 01:24:38.843887 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6758 01:24:38.847740 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6759 01:24:38.850489 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6760 01:24:38.850569
6761 01:24:38.850632
6762 01:24:38.853906 ==
6763 01:24:38.853987 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 01:24:38.860387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 01:24:38.860469 ==
6766 01:24:38.860533
6767 01:24:38.860592
6768 01:24:38.863864 TX Vref Scan disable
6769 01:24:38.863965 == TX Byte 0 ==
6770 01:24:38.867052 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 01:24:38.874169 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 01:24:38.874250 == TX Byte 1 ==
6773 01:24:38.877072 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 01:24:38.883422 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 01:24:38.883503 ==
6776 01:24:38.886794 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 01:24:38.890273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 01:24:38.890363 ==
6779 01:24:38.890465
6780 01:24:38.890528
6781 01:24:38.893594 TX Vref Scan disable
6782 01:24:38.893675 == TX Byte 0 ==
6783 01:24:38.896914 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 01:24:38.903235 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 01:24:38.903317 == TX Byte 1 ==
6786 01:24:38.907156 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 01:24:38.913449 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 01:24:38.913530
6789 01:24:38.913642 [DATLAT]
6790 01:24:38.913733 Freq=400, CH1 RK0
6791 01:24:38.913794
6792 01:24:38.916809 DATLAT Default: 0xf
6793 01:24:38.919954 0, 0xFFFF, sum = 0
6794 01:24:38.920037 1, 0xFFFF, sum = 0
6795 01:24:38.923448 2, 0xFFFF, sum = 0
6796 01:24:38.923530 3, 0xFFFF, sum = 0
6797 01:24:38.926455 4, 0xFFFF, sum = 0
6798 01:24:38.926537 5, 0xFFFF, sum = 0
6799 01:24:38.930234 6, 0xFFFF, sum = 0
6800 01:24:38.930316 7, 0xFFFF, sum = 0
6801 01:24:38.933507 8, 0xFFFF, sum = 0
6802 01:24:38.933625 9, 0xFFFF, sum = 0
6803 01:24:38.936119 10, 0xFFFF, sum = 0
6804 01:24:38.936200 11, 0xFFFF, sum = 0
6805 01:24:38.939478 12, 0xFFFF, sum = 0
6806 01:24:38.939560 13, 0x0, sum = 1
6807 01:24:38.942578 14, 0x0, sum = 2
6808 01:24:38.942660 15, 0x0, sum = 3
6809 01:24:38.946521 16, 0x0, sum = 4
6810 01:24:38.946603 best_step = 14
6811 01:24:38.946666
6812 01:24:38.946725 ==
6813 01:24:38.949641 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 01:24:38.955844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 01:24:38.955964 ==
6816 01:24:38.956031 RX Vref Scan: 1
6817 01:24:38.956092
6818 01:24:38.959309 RX Vref 0 -> 0, step: 1
6819 01:24:38.959389
6820 01:24:38.962877 RX Delay -343 -> 252, step: 8
6821 01:24:38.962958
6822 01:24:38.965989 Set Vref, RX VrefLevel [Byte0]: 50
6823 01:24:38.969432 [Byte1]: 52
6824 01:24:38.972285
6825 01:24:38.972365 Final RX Vref Byte 0 = 50 to rank0
6826 01:24:38.975472 Final RX Vref Byte 1 = 52 to rank0
6827 01:24:38.979049 Final RX Vref Byte 0 = 50 to rank1
6828 01:24:38.982145 Final RX Vref Byte 1 = 52 to rank1==
6829 01:24:38.985920 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 01:24:38.991817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 01:24:38.991898 ==
6832 01:24:38.991968 DQS Delay:
6833 01:24:38.995386 DQS0 = 44, DQS1 = 52
6834 01:24:38.995466 DQM Delay:
6835 01:24:38.995530 DQM0 = 10, DQM1 = 10
6836 01:24:38.999045 DQ Delay:
6837 01:24:39.002071 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6838 01:24:39.005103 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6839 01:24:39.005188 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6840 01:24:39.008523 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6841 01:24:39.012065
6842 01:24:39.012164
6843 01:24:39.018457 [DQSOSCAuto] RK0, (LSB)MR18= 0x668d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6844 01:24:39.021487 CH1 RK0: MR19=C0C, MR18=668D
6845 01:24:39.028183 CH1_RK0: MR19=0xC0C, MR18=0x668D, DQSOSC=392, MR23=63, INC=384, DEC=256
6846 01:24:39.028265 ==
6847 01:24:39.031483 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 01:24:39.035005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 01:24:39.035087 ==
6850 01:24:39.038087 [Gating] SW mode calibration
6851 01:24:39.044567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6852 01:24:39.051422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6853 01:24:39.055110 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 01:24:39.058111 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6855 01:24:39.064488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 01:24:39.067765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 01:24:39.072620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 01:24:39.078143 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 01:24:39.081136 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 01:24:39.084314 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 01:24:39.091174 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 01:24:39.091256 Total UI for P1: 0, mck2ui 16
6863 01:24:39.097567 best dqsien dly found for B0: ( 0, 14, 24)
6864 01:24:39.097649 Total UI for P1: 0, mck2ui 16
6865 01:24:39.105568 best dqsien dly found for B1: ( 0, 14, 24)
6866 01:24:39.107298 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6867 01:24:39.110528 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6868 01:24:39.110609
6869 01:24:39.113873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 01:24:39.117502 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6871 01:24:39.120471 [Gating] SW calibration Done
6872 01:24:39.120552 ==
6873 01:24:39.123631 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 01:24:39.127036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 01:24:39.127118 ==
6876 01:24:39.130169 RX Vref Scan: 0
6877 01:24:39.130250
6878 01:24:39.133606 RX Vref 0 -> 0, step: 1
6879 01:24:39.133687
6880 01:24:39.133751 RX Delay -410 -> 252, step: 16
6881 01:24:39.140095 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6882 01:24:39.143995 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6883 01:24:39.147183 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6884 01:24:39.153848 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6885 01:24:39.156669 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6886 01:24:39.160168 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6887 01:24:39.163567 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6888 01:24:39.170064 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6889 01:24:39.173535 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6890 01:24:39.176833 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6891 01:24:39.180445 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6892 01:24:39.186449 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6893 01:24:39.189822 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6894 01:24:39.192903 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6895 01:24:39.196267 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6896 01:24:39.203007 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6897 01:24:39.203088 ==
6898 01:24:39.206463 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 01:24:39.209161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 01:24:39.209242 ==
6901 01:24:39.213245 DQS Delay:
6902 01:24:39.213326 DQS0 = 43, DQS1 = 51
6903 01:24:39.213390 DQM Delay:
6904 01:24:39.216085 DQM0 = 9, DQM1 = 14
6905 01:24:39.216166 DQ Delay:
6906 01:24:39.219204 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6907 01:24:39.222343 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6908 01:24:39.225914 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6909 01:24:39.229093 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6910 01:24:39.229173
6911 01:24:39.229237
6912 01:24:39.229296 ==
6913 01:24:39.232464 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 01:24:39.235737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 01:24:39.235818 ==
6916 01:24:39.239144
6917 01:24:39.239224
6918 01:24:39.239287 TX Vref Scan disable
6919 01:24:39.242271 == TX Byte 0 ==
6920 01:24:39.245375 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6921 01:24:39.249147 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6922 01:24:39.252168 == TX Byte 1 ==
6923 01:24:39.255244 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6924 01:24:39.258740 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6925 01:24:39.258821 ==
6926 01:24:39.262291 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 01:24:39.268372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 01:24:39.268453 ==
6929 01:24:39.268517
6930 01:24:39.268576
6931 01:24:39.268633 TX Vref Scan disable
6932 01:24:39.271543 == TX Byte 0 ==
6933 01:24:39.275012 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6934 01:24:39.278123 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6935 01:24:39.281761 == TX Byte 1 ==
6936 01:24:39.285227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6937 01:24:39.288157 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6938 01:24:39.288241
6939 01:24:39.291545 [DATLAT]
6940 01:24:39.291626 Freq=400, CH1 RK1
6941 01:24:39.291690
6942 01:24:39.294612 DATLAT Default: 0xe
6943 01:24:39.294692 0, 0xFFFF, sum = 0
6944 01:24:39.297990 1, 0xFFFF, sum = 0
6945 01:24:39.298072 2, 0xFFFF, sum = 0
6946 01:24:39.301809 3, 0xFFFF, sum = 0
6947 01:24:39.301891 4, 0xFFFF, sum = 0
6948 01:24:39.304908 5, 0xFFFF, sum = 0
6949 01:24:39.304990 6, 0xFFFF, sum = 0
6950 01:24:39.307874 7, 0xFFFF, sum = 0
6951 01:24:39.307965 8, 0xFFFF, sum = 0
6952 01:24:39.311496 9, 0xFFFF, sum = 0
6953 01:24:39.311578 10, 0xFFFF, sum = 0
6954 01:24:39.314782 11, 0xFFFF, sum = 0
6955 01:24:39.318025 12, 0xFFFF, sum = 0
6956 01:24:39.318108 13, 0x0, sum = 1
6957 01:24:39.321092 14, 0x0, sum = 2
6958 01:24:39.321174 15, 0x0, sum = 3
6959 01:24:39.321239 16, 0x0, sum = 4
6960 01:24:39.324296 best_step = 14
6961 01:24:39.324377
6962 01:24:39.324441 ==
6963 01:24:39.327698 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 01:24:39.331300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 01:24:39.331381 ==
6966 01:24:39.334308 RX Vref Scan: 0
6967 01:24:39.334389
6968 01:24:39.337476 RX Vref 0 -> 0, step: 1
6969 01:24:39.337557
6970 01:24:39.337619 RX Delay -343 -> 252, step: 8
6971 01:24:39.346147 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6972 01:24:39.349849 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6973 01:24:39.353208 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6974 01:24:39.356469 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6975 01:24:39.363130 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6976 01:24:39.366178 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6977 01:24:39.369347 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6978 01:24:39.376244 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6979 01:24:39.379406 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6980 01:24:39.382216 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6981 01:24:39.385779 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6982 01:24:39.392224 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6983 01:24:39.395323 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6984 01:24:39.398681 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6985 01:24:39.405655 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6986 01:24:39.408686 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6987 01:24:39.408767 ==
6988 01:24:39.412201 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 01:24:39.415385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 01:24:39.415467 ==
6991 01:24:39.418875 DQS Delay:
6992 01:24:39.418955 DQS0 = 48, DQS1 = 52
6993 01:24:39.419020 DQM Delay:
6994 01:24:39.421676 DQM0 = 11, DQM1 = 10
6995 01:24:39.421757 DQ Delay:
6996 01:24:39.424942 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6997 01:24:39.428510 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6998 01:24:39.432043 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6999 01:24:39.435115 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7000 01:24:39.435196
7001 01:24:39.435259
7002 01:24:39.445264 [DQSOSCAuto] RK1, (LSB)MR18= 0x76af, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7003 01:24:39.445346 CH1 RK1: MR19=C0C, MR18=76AF
7004 01:24:39.452203 CH1_RK1: MR19=0xC0C, MR18=0x76AF, DQSOSC=388, MR23=63, INC=392, DEC=261
7005 01:24:39.454931 [RxdqsGatingPostProcess] freq 400
7006 01:24:39.461291 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7007 01:24:39.465214 best DQS0 dly(2T, 0.5T) = (0, 10)
7008 01:24:39.469091 best DQS1 dly(2T, 0.5T) = (0, 10)
7009 01:24:39.471471 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7010 01:24:39.474705 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7011 01:24:39.477802 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 01:24:39.481188 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 01:24:39.484355 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 01:24:39.488308 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 01:24:39.488389 Pre-setting of DQS Precalculation
7016 01:24:39.494686 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7017 01:24:39.501207 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7018 01:24:39.507831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7019 01:24:39.507947
7020 01:24:39.508012
7021 01:24:39.510768 [Calibration Summary] 800 Mbps
7022 01:24:39.514183 CH 0, Rank 0
7023 01:24:39.514263 SW Impedance : PASS
7024 01:24:39.517182 DUTY Scan : NO K
7025 01:24:39.520744 ZQ Calibration : PASS
7026 01:24:39.520825 Jitter Meter : NO K
7027 01:24:39.524017 CBT Training : PASS
7028 01:24:39.527466 Write leveling : PASS
7029 01:24:39.527547 RX DQS gating : PASS
7030 01:24:39.530604 RX DQ/DQS(RDDQC) : PASS
7031 01:24:39.533607 TX DQ/DQS : PASS
7032 01:24:39.533689 RX DATLAT : PASS
7033 01:24:39.537090 RX DQ/DQS(Engine): PASS
7034 01:24:39.540534 TX OE : NO K
7035 01:24:39.540615 All Pass.
7036 01:24:39.540679
7037 01:24:39.540737 CH 0, Rank 1
7038 01:24:39.543752 SW Impedance : PASS
7039 01:24:39.547252 DUTY Scan : NO K
7040 01:24:39.547333 ZQ Calibration : PASS
7041 01:24:39.550215 Jitter Meter : NO K
7042 01:24:39.553298 CBT Training : PASS
7043 01:24:39.553379 Write leveling : NO K
7044 01:24:39.557204 RX DQS gating : PASS
7045 01:24:39.557285 RX DQ/DQS(RDDQC) : PASS
7046 01:24:39.560629 TX DQ/DQS : PASS
7047 01:24:39.563761 RX DATLAT : PASS
7048 01:24:39.563842 RX DQ/DQS(Engine): PASS
7049 01:24:39.566655 TX OE : NO K
7050 01:24:39.566735 All Pass.
7051 01:24:39.566800
7052 01:24:39.569788 CH 1, Rank 0
7053 01:24:39.569869 SW Impedance : PASS
7054 01:24:39.573160 DUTY Scan : NO K
7055 01:24:39.576163 ZQ Calibration : PASS
7056 01:24:39.576263 Jitter Meter : NO K
7057 01:24:39.579890 CBT Training : PASS
7058 01:24:39.583104 Write leveling : PASS
7059 01:24:39.583184 RX DQS gating : PASS
7060 01:24:39.586219 RX DQ/DQS(RDDQC) : PASS
7061 01:24:39.589868 TX DQ/DQS : PASS
7062 01:24:39.589949 RX DATLAT : PASS
7063 01:24:39.593273 RX DQ/DQS(Engine): PASS
7064 01:24:39.596155 TX OE : NO K
7065 01:24:39.596236 All Pass.
7066 01:24:39.596300
7067 01:24:39.596359 CH 1, Rank 1
7068 01:24:39.600125 SW Impedance : PASS
7069 01:24:39.602973 DUTY Scan : NO K
7070 01:24:39.603053 ZQ Calibration : PASS
7071 01:24:39.606009 Jitter Meter : NO K
7072 01:24:39.609447 CBT Training : PASS
7073 01:24:39.609527 Write leveling : NO K
7074 01:24:39.612510 RX DQS gating : PASS
7075 01:24:39.616104 RX DQ/DQS(RDDQC) : PASS
7076 01:24:39.616186 TX DQ/DQS : PASS
7077 01:24:39.619128 RX DATLAT : PASS
7078 01:24:39.622352 RX DQ/DQS(Engine): PASS
7079 01:24:39.622432 TX OE : NO K
7080 01:24:39.625467 All Pass.
7081 01:24:39.625547
7082 01:24:39.625611 DramC Write-DBI off
7083 01:24:39.628905 PER_BANK_REFRESH: Hybrid Mode
7084 01:24:39.628986 TX_TRACKING: ON
7085 01:24:39.638797 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7086 01:24:39.641970 [FAST_K] Save calibration result to emmc
7087 01:24:39.646191 dramc_set_vcore_voltage set vcore to 725000
7088 01:24:39.649169 Read voltage for 1600, 0
7089 01:24:39.649250 Vio18 = 0
7090 01:24:39.652172 Vcore = 725000
7091 01:24:39.652253 Vdram = 0
7092 01:24:39.652316 Vddq = 0
7093 01:24:39.655291 Vmddr = 0
7094 01:24:39.659005 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7095 01:24:39.665574 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7096 01:24:39.665656 MEM_TYPE=3, freq_sel=13
7097 01:24:39.668583 sv_algorithm_assistance_LP4_3733
7098 01:24:39.675310 ============ PULL DRAM RESETB DOWN ============
7099 01:24:39.678614 ========== PULL DRAM RESETB DOWN end =========
7100 01:24:39.682109 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7101 01:24:39.685042 ===================================
7102 01:24:39.688610 LPDDR4 DRAM CONFIGURATION
7103 01:24:39.691516 ===================================
7104 01:24:39.695145 EX_ROW_EN[0] = 0x0
7105 01:24:39.695226 EX_ROW_EN[1] = 0x0
7106 01:24:39.698299 LP4Y_EN = 0x0
7107 01:24:39.698380 WORK_FSP = 0x1
7108 01:24:39.701594 WL = 0x5
7109 01:24:39.701675 RL = 0x5
7110 01:24:39.704876 BL = 0x2
7111 01:24:39.704957 RPST = 0x0
7112 01:24:39.708587 RD_PRE = 0x0
7113 01:24:39.708667 WR_PRE = 0x1
7114 01:24:39.711544 WR_PST = 0x1
7115 01:24:39.711625 DBI_WR = 0x0
7116 01:24:39.714587 DBI_RD = 0x0
7117 01:24:39.714667 OTF = 0x1
7118 01:24:39.717916 ===================================
7119 01:24:39.721664 ===================================
7120 01:24:39.724484 ANA top config
7121 01:24:39.728105 ===================================
7122 01:24:39.731341 DLL_ASYNC_EN = 0
7123 01:24:39.731421 ALL_SLAVE_EN = 0
7124 01:24:39.734557 NEW_RANK_MODE = 1
7125 01:24:39.738052 DLL_IDLE_MODE = 1
7126 01:24:39.741106 LP45_APHY_COMB_EN = 1
7127 01:24:39.744636 TX_ODT_DIS = 0
7128 01:24:39.744717 NEW_8X_MODE = 1
7129 01:24:39.747871 ===================================
7130 01:24:39.751046 ===================================
7131 01:24:39.753997 data_rate = 3200
7132 01:24:39.757466 CKR = 1
7133 01:24:39.760790 DQ_P2S_RATIO = 8
7134 01:24:39.763982 ===================================
7135 01:24:39.767580 CA_P2S_RATIO = 8
7136 01:24:39.770524 DQ_CA_OPEN = 0
7137 01:24:39.770604 DQ_SEMI_OPEN = 0
7138 01:24:39.774311 CA_SEMI_OPEN = 0
7139 01:24:39.777891 CA_FULL_RATE = 0
7140 01:24:39.780606 DQ_CKDIV4_EN = 0
7141 01:24:39.784045 CA_CKDIV4_EN = 0
7142 01:24:39.786896 CA_PREDIV_EN = 0
7143 01:24:39.786976 PH8_DLY = 12
7144 01:24:39.790365 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7145 01:24:39.793779 DQ_AAMCK_DIV = 4
7146 01:24:39.797122 CA_AAMCK_DIV = 4
7147 01:24:39.800085 CA_ADMCK_DIV = 4
7148 01:24:39.805555 DQ_TRACK_CA_EN = 0
7149 01:24:39.807122 CA_PICK = 1600
7150 01:24:39.810038 CA_MCKIO = 1600
7151 01:24:39.810118 MCKIO_SEMI = 0
7152 01:24:39.813190 PLL_FREQ = 3068
7153 01:24:39.817047 DQ_UI_PI_RATIO = 32
7154 01:24:39.819785 CA_UI_PI_RATIO = 0
7155 01:24:39.823557 ===================================
7156 01:24:39.826838 ===================================
7157 01:24:39.829805 memory_type:LPDDR4
7158 01:24:39.829885 GP_NUM : 10
7159 01:24:39.833086 SRAM_EN : 1
7160 01:24:39.836466 MD32_EN : 0
7161 01:24:39.839558 ===================================
7162 01:24:39.839637 [ANA_INIT] >>>>>>>>>>>>>>
7163 01:24:39.843097 <<<<<< [CONFIGURE PHASE]: ANA_TX
7164 01:24:39.846354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7165 01:24:39.849410 ===================================
7166 01:24:39.853125 data_rate = 3200,PCW = 0X7600
7167 01:24:39.856198 ===================================
7168 01:24:39.859643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7169 01:24:39.866008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 01:24:39.869180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7171 01:24:39.876494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7172 01:24:39.879770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7173 01:24:39.883126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7174 01:24:39.883206 [ANA_INIT] flow start
7175 01:24:39.885897 [ANA_INIT] PLL >>>>>>>>
7176 01:24:39.889955 [ANA_INIT] PLL <<<<<<<<
7177 01:24:39.892660 [ANA_INIT] MIDPI >>>>>>>>
7178 01:24:39.892740 [ANA_INIT] MIDPI <<<<<<<<
7179 01:24:39.895802 [ANA_INIT] DLL >>>>>>>>
7180 01:24:39.899197 [ANA_INIT] DLL <<<<<<<<
7181 01:24:39.899277 [ANA_INIT] flow end
7182 01:24:39.905732 ============ LP4 DIFF to SE enter ============
7183 01:24:39.909217 ============ LP4 DIFF to SE exit ============
7184 01:24:39.909297 [ANA_INIT] <<<<<<<<<<<<<
7185 01:24:39.912063 [Flow] Enable top DCM control >>>>>
7186 01:24:39.915641 [Flow] Enable top DCM control <<<<<
7187 01:24:39.918857 Enable DLL master slave shuffle
7188 01:24:39.925550 ==============================================================
7189 01:24:39.928998 Gating Mode config
7190 01:24:39.931804 ==============================================================
7191 01:24:39.935430 Config description:
7192 01:24:39.945435 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7193 01:24:39.951663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7194 01:24:39.954822 SELPH_MODE 0: By rank 1: By Phase
7195 01:24:39.961574 ==============================================================
7196 01:24:39.965070 GAT_TRACK_EN = 1
7197 01:24:39.968433 RX_GATING_MODE = 2
7198 01:24:39.971586 RX_GATING_TRACK_MODE = 2
7199 01:24:39.975094 SELPH_MODE = 1
7200 01:24:39.977922 PICG_EARLY_EN = 1
7201 01:24:39.978002 VALID_LAT_VALUE = 1
7202 01:24:39.984673 ==============================================================
7203 01:24:39.987887 Enter into Gating configuration >>>>
7204 01:24:39.991131 Exit from Gating configuration <<<<
7205 01:24:39.994436 Enter into DVFS_PRE_config >>>>>
7206 01:24:40.004322 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7207 01:24:40.007795 Exit from DVFS_PRE_config <<<<<
7208 01:24:40.010825 Enter into PICG configuration >>>>
7209 01:24:40.014452 Exit from PICG configuration <<<<
7210 01:24:40.017275 [RX_INPUT] configuration >>>>>
7211 01:24:40.021017 [RX_INPUT] configuration <<<<<
7212 01:24:40.027355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7213 01:24:40.030970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7214 01:24:40.037485 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 01:24:40.043977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 01:24:40.050620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 01:24:40.056900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 01:24:40.060085 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7219 01:24:40.063598 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7220 01:24:40.066725 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7221 01:24:40.073662 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7222 01:24:40.077438 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7223 01:24:40.080072 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 01:24:40.083437 ===================================
7225 01:24:40.086537 LPDDR4 DRAM CONFIGURATION
7226 01:24:40.090233 ===================================
7227 01:24:40.093461 EX_ROW_EN[0] = 0x0
7228 01:24:40.093541 EX_ROW_EN[1] = 0x0
7229 01:24:40.096542 LP4Y_EN = 0x0
7230 01:24:40.096669 WORK_FSP = 0x1
7231 01:24:40.100172 WL = 0x5
7232 01:24:40.100252 RL = 0x5
7233 01:24:40.103383 BL = 0x2
7234 01:24:40.103489 RPST = 0x0
7235 01:24:40.106286 RD_PRE = 0x0
7236 01:24:40.106388 WR_PRE = 0x1
7237 01:24:40.109534 WR_PST = 0x1
7238 01:24:40.109635 DBI_WR = 0x0
7239 01:24:40.112878 DBI_RD = 0x0
7240 01:24:40.116259 OTF = 0x1
7241 01:24:40.119497 ===================================
7242 01:24:40.122581 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7243 01:24:40.126190 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7244 01:24:40.129501 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7245 01:24:40.132576 ===================================
7246 01:24:40.136233 LPDDR4 DRAM CONFIGURATION
7247 01:24:40.139525 ===================================
7248 01:24:40.142686 EX_ROW_EN[0] = 0x10
7249 01:24:40.142767 EX_ROW_EN[1] = 0x0
7250 01:24:40.145824 LP4Y_EN = 0x0
7251 01:24:40.145903 WORK_FSP = 0x1
7252 01:24:40.149374 WL = 0x5
7253 01:24:40.149454 RL = 0x5
7254 01:24:40.152799 BL = 0x2
7255 01:24:40.152879 RPST = 0x0
7256 01:24:40.156308 RD_PRE = 0x0
7257 01:24:40.156388 WR_PRE = 0x1
7258 01:24:40.159480 WR_PST = 0x1
7259 01:24:40.162284 DBI_WR = 0x0
7260 01:24:40.162367 DBI_RD = 0x0
7261 01:24:40.165686 OTF = 0x1
7262 01:24:40.168964 ===================================
7263 01:24:40.172524 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7264 01:24:40.172607 ==
7265 01:24:40.175752 Dram Type= 6, Freq= 0, CH_0, rank 0
7266 01:24:40.182450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7267 01:24:40.182531 ==
7268 01:24:40.185839 [Duty_Offset_Calibration]
7269 01:24:40.185918 B0:2 B1:0 CA:4
7270 01:24:40.185981
7271 01:24:40.188859 [DutyScan_Calibration_Flow] k_type=0
7272 01:24:40.197551
7273 01:24:40.197635 ==CLK 0==
7274 01:24:40.200943 Final CLK duty delay cell = -4
7275 01:24:40.204823 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7276 01:24:40.208090 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7277 01:24:40.210598 [-4] AVG Duty = 4937%(X100)
7278 01:24:40.210678
7279 01:24:40.214103 CH0 CLK Duty spec in!! Max-Min= 187%
7280 01:24:40.217403 [DutyScan_Calibration_Flow] ====Done====
7281 01:24:40.217483
7282 01:24:40.220792 [DutyScan_Calibration_Flow] k_type=1
7283 01:24:40.238395
7284 01:24:40.238477 ==DQS 0 ==
7285 01:24:40.241332 Final DQS duty delay cell = 0
7286 01:24:40.244613 [0] MAX Duty = 5249%(X100), DQS PI = 38
7287 01:24:40.247846 [0] MIN Duty = 5093%(X100), DQS PI = 12
7288 01:24:40.251637 [0] AVG Duty = 5171%(X100)
7289 01:24:40.251758
7290 01:24:40.251849 ==DQS 1 ==
7291 01:24:40.254827 Final DQS duty delay cell = 0
7292 01:24:40.257916 [0] MAX Duty = 5187%(X100), DQS PI = 0
7293 01:24:40.261385 [0] MIN Duty = 4969%(X100), DQS PI = 12
7294 01:24:40.264716 [0] AVG Duty = 5078%(X100)
7295 01:24:40.264797
7296 01:24:40.267594 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7297 01:24:40.267675
7298 01:24:40.271661 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7299 01:24:40.274522 [DutyScan_Calibration_Flow] ====Done====
7300 01:24:40.274603
7301 01:24:40.277471 [DutyScan_Calibration_Flow] k_type=3
7302 01:24:40.295272
7303 01:24:40.295353 ==DQM 0 ==
7304 01:24:40.298794 Final DQM duty delay cell = 0
7305 01:24:40.301772 [0] MAX Duty = 5124%(X100), DQS PI = 20
7306 01:24:40.305004 [0] MIN Duty = 4875%(X100), DQS PI = 54
7307 01:24:40.309129 [0] AVG Duty = 4999%(X100)
7308 01:24:40.309211
7309 01:24:40.309276 ==DQM 1 ==
7310 01:24:40.311646 Final DQM duty delay cell = 0
7311 01:24:40.315407 [0] MAX Duty = 4969%(X100), DQS PI = 0
7312 01:24:40.318253 [0] MIN Duty = 4844%(X100), DQS PI = 16
7313 01:24:40.321574 [0] AVG Duty = 4906%(X100)
7314 01:24:40.321654
7315 01:24:40.325184 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7316 01:24:40.325273
7317 01:24:40.328076 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7318 01:24:40.332037 [DutyScan_Calibration_Flow] ====Done====
7319 01:24:40.332118
7320 01:24:40.334683 [DutyScan_Calibration_Flow] k_type=2
7321 01:24:40.352187
7322 01:24:40.352269 ==DQ 0 ==
7323 01:24:40.355875 Final DQ duty delay cell = 0
7324 01:24:40.359098 [0] MAX Duty = 5156%(X100), DQS PI = 26
7325 01:24:40.362071 [0] MIN Duty = 4938%(X100), DQS PI = 12
7326 01:24:40.365253 [0] AVG Duty = 5047%(X100)
7327 01:24:40.365334
7328 01:24:40.365398 ==DQ 1 ==
7329 01:24:40.368774 Final DQ duty delay cell = 0
7330 01:24:40.372093 [0] MAX Duty = 5187%(X100), DQS PI = 2
7331 01:24:40.375654 [0] MIN Duty = 4938%(X100), DQS PI = 12
7332 01:24:40.375735 [0] AVG Duty = 5062%(X100)
7333 01:24:40.378718
7334 01:24:40.382134 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7335 01:24:40.382214
7336 01:24:40.385716 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7337 01:24:40.388708 [DutyScan_Calibration_Flow] ====Done====
7338 01:24:40.388789 ==
7339 01:24:40.391825 Dram Type= 6, Freq= 0, CH_1, rank 0
7340 01:24:40.395036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 01:24:40.395117 ==
7342 01:24:40.398507 [Duty_Offset_Calibration]
7343 01:24:40.398587 B0:0 B1:-1 CA:3
7344 01:24:40.398651
7345 01:24:40.401539 [DutyScan_Calibration_Flow] k_type=0
7346 01:24:40.411611
7347 01:24:40.411693 ==CLK 0==
7348 01:24:40.415416 Final CLK duty delay cell = -4
7349 01:24:40.418655 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7350 01:24:40.421623 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7351 01:24:40.425411 [-4] AVG Duty = 4937%(X100)
7352 01:24:40.425491
7353 01:24:40.427986 CH1 CLK Duty spec in!! Max-Min= 125%
7354 01:24:40.431745 [DutyScan_Calibration_Flow] ====Done====
7355 01:24:40.431825
7356 01:24:40.435225 [DutyScan_Calibration_Flow] k_type=1
7357 01:24:40.451255
7358 01:24:40.451335 ==DQS 0 ==
7359 01:24:40.454022 Final DQS duty delay cell = 0
7360 01:24:40.457563 [0] MAX Duty = 5250%(X100), DQS PI = 28
7361 01:24:40.460593 [0] MIN Duty = 4938%(X100), DQS PI = 56
7362 01:24:40.464331 [0] AVG Duty = 5094%(X100)
7363 01:24:40.464411
7364 01:24:40.464475 ==DQS 1 ==
7365 01:24:40.467003 Final DQS duty delay cell = -4
7366 01:24:40.471663 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7367 01:24:40.473929 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7368 01:24:40.476931 [-4] AVG Duty = 4906%(X100)
7369 01:24:40.477012
7370 01:24:40.480835 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7371 01:24:40.480916
7372 01:24:40.483603 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7373 01:24:40.486917 [DutyScan_Calibration_Flow] ====Done====
7374 01:24:40.486997
7375 01:24:40.491131 [DutyScan_Calibration_Flow] k_type=3
7376 01:24:40.508000
7377 01:24:40.508082 ==DQM 0 ==
7378 01:24:40.511431 Final DQM duty delay cell = 0
7379 01:24:40.514894 [0] MAX Duty = 5062%(X100), DQS PI = 30
7380 01:24:40.517924 [0] MIN Duty = 4750%(X100), DQS PI = 40
7381 01:24:40.521174 [0] AVG Duty = 4906%(X100)
7382 01:24:40.521253
7383 01:24:40.521316 ==DQM 1 ==
7384 01:24:40.524942 Final DQM duty delay cell = 0
7385 01:24:40.528504 [0] MAX Duty = 5000%(X100), DQS PI = 30
7386 01:24:40.531444 [0] MIN Duty = 4813%(X100), DQS PI = 0
7387 01:24:40.534526 [0] AVG Duty = 4906%(X100)
7388 01:24:40.534608
7389 01:24:40.537568 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7390 01:24:40.537648
7391 01:24:40.541447 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7392 01:24:40.545030 [DutyScan_Calibration_Flow] ====Done====
7393 01:24:40.545111
7394 01:24:40.547692 [DutyScan_Calibration_Flow] k_type=2
7395 01:24:40.564042
7396 01:24:40.564123 ==DQ 0 ==
7397 01:24:40.567876 Final DQ duty delay cell = -4
7398 01:24:40.570826 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7399 01:24:40.574072 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7400 01:24:40.577639 [-4] AVG Duty = 4891%(X100)
7401 01:24:40.577720
7402 01:24:40.577783 ==DQ 1 ==
7403 01:24:40.581152 Final DQ duty delay cell = 0
7404 01:24:40.584189 [0] MAX Duty = 5062%(X100), DQS PI = 32
7405 01:24:40.587430 [0] MIN Duty = 4875%(X100), DQS PI = 58
7406 01:24:40.590333 [0] AVG Duty = 4968%(X100)
7407 01:24:40.590427
7408 01:24:40.594263 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7409 01:24:40.594343
7410 01:24:40.597121 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7411 01:24:40.600368 [DutyScan_Calibration_Flow] ====Done====
7412 01:24:40.603820 nWR fixed to 30
7413 01:24:40.606844 [ModeRegInit_LP4] CH0 RK0
7414 01:24:40.606924 [ModeRegInit_LP4] CH0 RK1
7415 01:24:40.610352 [ModeRegInit_LP4] CH1 RK0
7416 01:24:40.614031 [ModeRegInit_LP4] CH1 RK1
7417 01:24:40.614137 match AC timing 5
7418 01:24:40.620103 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7419 01:24:40.623563 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7420 01:24:40.626856 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7421 01:24:40.633096 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7422 01:24:40.636802 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7423 01:24:40.636883 [MiockJmeterHQA]
7424 01:24:40.640044
7425 01:24:40.643544 [DramcMiockJmeter] u1RxGatingPI = 0
7426 01:24:40.643624 0 : 4363, 4137
7427 01:24:40.643720 4 : 4255, 4029
7428 01:24:40.646330 8 : 4253, 4027
7429 01:24:40.646411 12 : 4255, 4030
7430 01:24:40.650000 16 : 4368, 4142
7431 01:24:40.650110 20 : 4363, 4137
7432 01:24:40.653397 24 : 4363, 4138
7433 01:24:40.653478 28 : 4249, 4027
7434 01:24:40.653549 32 : 4365, 4140
7435 01:24:40.656777 36 : 4250, 4027
7436 01:24:40.656858 40 : 4253, 4026
7437 01:24:40.659747 44 : 4252, 4027
7438 01:24:40.659855 48 : 4253, 4027
7439 01:24:40.662766 52 : 4250, 4027
7440 01:24:40.662868 56 : 4255, 4029
7441 01:24:40.666228 60 : 4253, 4027
7442 01:24:40.666309 64 : 4249, 4027
7443 01:24:40.666374 68 : 4365, 4140
7444 01:24:40.669975 72 : 4252, 4029
7445 01:24:40.670057 76 : 4252, 4030
7446 01:24:40.673115 80 : 4250, 4027
7447 01:24:40.673196 84 : 4361, 4137
7448 01:24:40.676325 88 : 4250, 4027
7449 01:24:40.676406 92 : 4250, 4027
7450 01:24:40.679444 96 : 4252, 3568
7451 01:24:40.679524 100 : 4250, 0
7452 01:24:40.679589 104 : 4360, 0
7453 01:24:40.682721 108 : 4252, 0
7454 01:24:40.682803 112 : 4252, 0
7455 01:24:40.686448 116 : 4250, 0
7456 01:24:40.686529 120 : 4255, 0
7457 01:24:40.686593 124 : 4250, 0
7458 01:24:40.690369 128 : 4363, 0
7459 01:24:40.690453 132 : 4250, 0
7460 01:24:40.690519 136 : 4250, 0
7461 01:24:40.692547 140 : 4250, 0
7462 01:24:40.692629 144 : 4252, 0
7463 01:24:40.696081 148 : 4361, 0
7464 01:24:40.696162 152 : 4360, 0
7465 01:24:40.696227 156 : 4363, 0
7466 01:24:40.699444 160 : 4250, 0
7467 01:24:40.699526 164 : 4250, 0
7468 01:24:40.702715 168 : 4255, 0
7469 01:24:40.702796 172 : 4250, 0
7470 01:24:40.702861 176 : 4363, 0
7471 01:24:40.705462 180 : 4255, 0
7472 01:24:40.705544 184 : 4250, 0
7473 01:24:40.708796 188 : 4252, 0
7474 01:24:40.708877 192 : 4250, 0
7475 01:24:40.708943 196 : 4249, 0
7476 01:24:40.712522 200 : 4250, 0
7477 01:24:40.712603 204 : 4252, 0
7478 01:24:40.715424 208 : 4363, 0
7479 01:24:40.715505 212 : 4255, 0
7480 01:24:40.715570 216 : 4361, 0
7481 01:24:40.718803 220 : 4250, 295
7482 01:24:40.718884 224 : 4361, 3862
7483 01:24:40.722158 228 : 4253, 4029
7484 01:24:40.722240 232 : 4250, 4027
7485 01:24:40.726143 236 : 4252, 4029
7486 01:24:40.726225 240 : 4250, 4027
7487 01:24:40.728671 244 : 4361, 4137
7488 01:24:40.728752 248 : 4250, 4027
7489 01:24:40.732108 252 : 4250, 4027
7490 01:24:40.732189 256 : 4250, 4027
7491 01:24:40.735293 260 : 4250, 4027
7492 01:24:40.735375 264 : 4361, 4137
7493 01:24:40.735439 268 : 4250, 4027
7494 01:24:40.738811 272 : 4360, 4138
7495 01:24:40.738892 276 : 4250, 4027
7496 01:24:40.741813 280 : 4250, 4026
7497 01:24:40.741894 284 : 4250, 4027
7498 01:24:40.745065 288 : 4250, 4027
7499 01:24:40.745146 292 : 4254, 4030
7500 01:24:40.749097 296 : 4361, 4137
7501 01:24:40.749178 300 : 4250, 4026
7502 01:24:40.751802 304 : 4250, 4027
7503 01:24:40.751883 308 : 4255, 4030
7504 01:24:40.755297 312 : 4250, 4027
7505 01:24:40.755378 316 : 4363, 4137
7506 01:24:40.758331 320 : 4250, 4027
7507 01:24:40.758412 324 : 4363, 4138
7508 01:24:40.761767 328 : 4250, 4027
7509 01:24:40.761848 332 : 4250, 4023
7510 01:24:40.761912 336 : 4252, 2368
7511 01:24:40.764934 340 : 4250, 30
7512 01:24:40.765015
7513 01:24:40.768145 MIOCK jitter meter ch=0
7514 01:24:40.768225
7515 01:24:40.771518 1T = (340-100) = 240 dly cells
7516 01:24:40.774592 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7517 01:24:40.774673 ==
7518 01:24:40.778271 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 01:24:40.784969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 01:24:40.785076 ==
7521 01:24:40.788278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7522 01:24:40.794474 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7523 01:24:40.797989 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7524 01:24:40.804136 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7525 01:24:40.811937 [CA 0] Center 44 (14~74) winsize 61
7526 01:24:40.815462 [CA 1] Center 43 (13~74) winsize 62
7527 01:24:40.818780 [CA 2] Center 39 (10~68) winsize 59
7528 01:24:40.822014 [CA 3] Center 38 (9~68) winsize 60
7529 01:24:40.825751 [CA 4] Center 36 (7~66) winsize 60
7530 01:24:40.828579 [CA 5] Center 36 (6~66) winsize 61
7531 01:24:40.828659
7532 01:24:40.832383 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7533 01:24:40.832528
7534 01:24:40.838786 [CATrainingPosCal] consider 1 rank data
7535 01:24:40.838866 u2DelayCellTimex100 = 271/100 ps
7536 01:24:40.845192 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7537 01:24:40.848423 CA1 delay=43 (13~74),Diff = 7 PI (25 cell)
7538 01:24:40.851464 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7539 01:24:40.855322 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7540 01:24:40.858103 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7541 01:24:40.861660 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7542 01:24:40.861741
7543 01:24:40.864833 CA PerBit enable=1, Macro0, CA PI delay=36
7544 01:24:40.864914
7545 01:24:40.868387 [CBTSetCACLKResult] CA Dly = 36
7546 01:24:40.871473 CS Dly: 10 (0~41)
7547 01:24:40.875141 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7548 01:24:40.878237 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7549 01:24:40.878318 ==
7550 01:24:40.881264 Dram Type= 6, Freq= 0, CH_0, rank 1
7551 01:24:40.887750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 01:24:40.887834 ==
7553 01:24:40.891060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 01:24:40.897852 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 01:24:40.900845 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 01:24:40.907736 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 01:24:40.915614 [CA 0] Center 43 (13~74) winsize 62
7558 01:24:40.918914 [CA 1] Center 43 (13~73) winsize 61
7559 01:24:40.923310 [CA 2] Center 38 (9~68) winsize 60
7560 01:24:40.925751 [CA 3] Center 38 (9~68) winsize 60
7561 01:24:40.928827 [CA 4] Center 36 (6~66) winsize 61
7562 01:24:40.932128 [CA 5] Center 36 (6~66) winsize 61
7563 01:24:40.932209
7564 01:24:40.935351 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7565 01:24:40.935431
7566 01:24:40.938951 [CATrainingPosCal] consider 2 rank data
7567 01:24:40.942533 u2DelayCellTimex100 = 271/100 ps
7568 01:24:40.948686 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7569 01:24:40.952013 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7570 01:24:40.955517 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7571 01:24:40.958494 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7572 01:24:40.962013 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7573 01:24:40.965137 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7574 01:24:40.965218
7575 01:24:40.968611 CA PerBit enable=1, Macro0, CA PI delay=36
7576 01:24:40.968717
7577 01:24:40.971860 [CBTSetCACLKResult] CA Dly = 36
7578 01:24:40.975132 CS Dly: 11 (0~43)
7579 01:24:40.978287 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 01:24:40.981840 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 01:24:40.981920
7582 01:24:40.985062 ----->DramcWriteLeveling(PI) begin...
7583 01:24:40.988134 ==
7584 01:24:40.991382 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 01:24:40.995104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 01:24:40.995185 ==
7587 01:24:40.998186 Write leveling (Byte 0): 34 => 34
7588 01:24:41.001183 Write leveling (Byte 1): 28 => 28
7589 01:24:41.004619 DramcWriteLeveling(PI) end<-----
7590 01:24:41.004700
7591 01:24:41.004763 ==
7592 01:24:41.008160 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 01:24:41.011045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 01:24:41.011126 ==
7595 01:24:41.014783 [Gating] SW mode calibration
7596 01:24:41.021002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7597 01:24:41.027721 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7598 01:24:41.031132 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 01:24:41.034322 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 01:24:41.041635 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 01:24:41.044630 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7602 01:24:41.047634 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7603 01:24:41.051017 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7604 01:24:41.057786 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 01:24:41.060953 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 01:24:41.064474 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 01:24:41.071086 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 01:24:41.074298 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7609 01:24:41.080781 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7610 01:24:41.084150 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7611 01:24:41.087663 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
7612 01:24:41.093902 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7613 01:24:41.096896 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 01:24:41.100409 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 01:24:41.106938 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 01:24:41.110489 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7617 01:24:41.113805 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7618 01:24:41.117393 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7619 01:24:41.123436 1 6 20 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
7620 01:24:41.127310 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 01:24:41.130489 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 01:24:41.137242 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 01:24:41.140321 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 01:24:41.146358 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 01:24:41.150322 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 01:24:41.153406 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7627 01:24:41.160079 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7628 01:24:41.163378 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7629 01:24:41.166518 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 01:24:41.173458 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 01:24:41.176487 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 01:24:41.179404 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 01:24:41.183243 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 01:24:41.189606 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 01:24:41.192628 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 01:24:41.195854 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 01:24:41.202808 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 01:24:41.205912 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 01:24:41.209150 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 01:24:41.216250 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 01:24:41.219196 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7642 01:24:41.222724 Total UI for P1: 0, mck2ui 16
7643 01:24:41.226030 best dqsien dly found for B0: ( 1, 9, 8)
7644 01:24:41.229601 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7645 01:24:41.235700 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7646 01:24:41.239469 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 01:24:41.242966 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 01:24:41.245424 Total UI for P1: 0, mck2ui 16
7649 01:24:41.248715 best dqsien dly found for B1: ( 1, 9, 22)
7650 01:24:41.252798 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7651 01:24:41.258895 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7652 01:24:41.258976
7653 01:24:41.261872 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7654 01:24:41.265298 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7655 01:24:41.268698 [Gating] SW calibration Done
7656 01:24:41.268779 ==
7657 01:24:41.271763 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 01:24:41.275284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 01:24:41.275365 ==
7660 01:24:41.278501 RX Vref Scan: 0
7661 01:24:41.278582
7662 01:24:41.278645 RX Vref 0 -> 0, step: 1
7663 01:24:41.278704
7664 01:24:41.281655 RX Delay 0 -> 252, step: 8
7665 01:24:41.285301 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7666 01:24:41.292175 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7667 01:24:41.295498 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7668 01:24:41.298346 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7669 01:24:41.301664 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7670 01:24:41.305019 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7671 01:24:41.311548 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7672 01:24:41.315125 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7673 01:24:41.318191 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7674 01:24:41.321105 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7675 01:24:41.324609 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7676 01:24:41.330965 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7677 01:24:41.334477 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7678 01:24:41.337841 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7679 01:24:41.341027 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7680 01:24:41.344028 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7681 01:24:41.347801 ==
7682 01:24:41.351071 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 01:24:41.354388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 01:24:41.354468 ==
7685 01:24:41.354531 DQS Delay:
7686 01:24:41.357868 DQS0 = 0, DQS1 = 0
7687 01:24:41.357948 DQM Delay:
7688 01:24:41.360907 DQM0 = 131, DQM1 = 125
7689 01:24:41.361012 DQ Delay:
7690 01:24:41.364031 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7691 01:24:41.367502 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7692 01:24:41.370647 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7693 01:24:41.374127 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7694 01:24:41.374207
7695 01:24:41.374269
7696 01:24:41.377936 ==
7697 01:24:41.378017 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 01:24:41.384247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 01:24:41.384328 ==
7700 01:24:41.384392
7701 01:24:41.384450
7702 01:24:41.387281 TX Vref Scan disable
7703 01:24:41.387362 == TX Byte 0 ==
7704 01:24:41.390580 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7705 01:24:41.397080 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7706 01:24:41.397161 == TX Byte 1 ==
7707 01:24:41.400573 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7708 01:24:41.406798 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7709 01:24:41.406880 ==
7710 01:24:41.410565 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 01:24:41.413278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 01:24:41.413360 ==
7713 01:24:41.427268
7714 01:24:41.430591 TX Vref early break, caculate TX vref
7715 01:24:41.433865 TX Vref=16, minBit 1, minWin=22, winSum=369
7716 01:24:41.437025 TX Vref=18, minBit 8, minWin=22, winSum=382
7717 01:24:41.440296 TX Vref=20, minBit 1, minWin=24, winSum=392
7718 01:24:41.443539 TX Vref=22, minBit 7, minWin=24, winSum=401
7719 01:24:41.447075 TX Vref=24, minBit 0, minWin=25, winSum=412
7720 01:24:41.453687 TX Vref=26, minBit 1, minWin=25, winSum=422
7721 01:24:41.456987 TX Vref=28, minBit 2, minWin=25, winSum=424
7722 01:24:41.460347 TX Vref=30, minBit 0, minWin=25, winSum=419
7723 01:24:41.463433 TX Vref=32, minBit 2, minWin=25, winSum=411
7724 01:24:41.466539 TX Vref=34, minBit 0, minWin=24, winSum=397
7725 01:24:41.473098 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 28
7726 01:24:41.473180
7727 01:24:41.476565 Final TX Range 0 Vref 28
7728 01:24:41.476646
7729 01:24:41.476709 ==
7730 01:24:41.479831 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 01:24:41.483355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 01:24:41.483436 ==
7733 01:24:41.483500
7734 01:24:41.483559
7735 01:24:41.486413 TX Vref Scan disable
7736 01:24:41.492716 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7737 01:24:41.492797 == TX Byte 0 ==
7738 01:24:41.496497 u2DelayCellOfst[0]=10 cells (3 PI)
7739 01:24:41.499869 u2DelayCellOfst[1]=14 cells (4 PI)
7740 01:24:41.503402 u2DelayCellOfst[2]=10 cells (3 PI)
7741 01:24:41.506469 u2DelayCellOfst[3]=10 cells (3 PI)
7742 01:24:41.510308 u2DelayCellOfst[4]=7 cells (2 PI)
7743 01:24:41.513026 u2DelayCellOfst[5]=0 cells (0 PI)
7744 01:24:41.516103 u2DelayCellOfst[6]=14 cells (4 PI)
7745 01:24:41.519396 u2DelayCellOfst[7]=14 cells (4 PI)
7746 01:24:41.522833 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7747 01:24:41.525934 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7748 01:24:41.529480 == TX Byte 1 ==
7749 01:24:41.532573 u2DelayCellOfst[8]=0 cells (0 PI)
7750 01:24:41.535846 u2DelayCellOfst[9]=0 cells (0 PI)
7751 01:24:41.539184 u2DelayCellOfst[10]=7 cells (2 PI)
7752 01:24:41.542283 u2DelayCellOfst[11]=3 cells (1 PI)
7753 01:24:41.545690 u2DelayCellOfst[12]=10 cells (3 PI)
7754 01:24:41.545769 u2DelayCellOfst[13]=10 cells (3 PI)
7755 01:24:41.549034 u2DelayCellOfst[14]=14 cells (4 PI)
7756 01:24:41.553196 u2DelayCellOfst[15]=10 cells (3 PI)
7757 01:24:41.558628 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7758 01:24:41.562378 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7759 01:24:41.565986 DramC Write-DBI on
7760 01:24:41.566066 ==
7761 01:24:41.569025 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 01:24:41.572217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 01:24:41.572299 ==
7764 01:24:41.572362
7765 01:24:41.572421
7766 01:24:41.575224 TX Vref Scan disable
7767 01:24:41.575304 == TX Byte 0 ==
7768 01:24:41.581772 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7769 01:24:41.581853 == TX Byte 1 ==
7770 01:24:41.585412 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7771 01:24:41.588307 DramC Write-DBI off
7772 01:24:41.588387
7773 01:24:41.588459 [DATLAT]
7774 01:24:41.591624 Freq=1600, CH0 RK0
7775 01:24:41.591709
7776 01:24:41.591773 DATLAT Default: 0xf
7777 01:24:41.595190 0, 0xFFFF, sum = 0
7778 01:24:41.595272 1, 0xFFFF, sum = 0
7779 01:24:41.598539 2, 0xFFFF, sum = 0
7780 01:24:41.602029 3, 0xFFFF, sum = 0
7781 01:24:41.602111 4, 0xFFFF, sum = 0
7782 01:24:41.605094 5, 0xFFFF, sum = 0
7783 01:24:41.605177 6, 0xFFFF, sum = 0
7784 01:24:41.608281 7, 0xFFFF, sum = 0
7785 01:24:41.608362 8, 0xFFFF, sum = 0
7786 01:24:41.611236 9, 0xFFFF, sum = 0
7787 01:24:41.611318 10, 0xFFFF, sum = 0
7788 01:24:41.614646 11, 0xFFFF, sum = 0
7789 01:24:41.614727 12, 0xFFFF, sum = 0
7790 01:24:41.618121 13, 0xFFFF, sum = 0
7791 01:24:41.618201 14, 0x0, sum = 1
7792 01:24:41.621960 15, 0x0, sum = 2
7793 01:24:41.622042 16, 0x0, sum = 3
7794 01:24:41.624497 17, 0x0, sum = 4
7795 01:24:41.624578 best_step = 15
7796 01:24:41.624642
7797 01:24:41.624701 ==
7798 01:24:41.628476 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 01:24:41.634239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 01:24:41.634325 ==
7801 01:24:41.634391 RX Vref Scan: 1
7802 01:24:41.634451
7803 01:24:41.637551 Set Vref Range= 24 -> 127
7804 01:24:41.637658
7805 01:24:41.641893 RX Vref 24 -> 127, step: 1
7806 01:24:41.641974
7807 01:24:41.642038 RX Delay 11 -> 252, step: 4
7808 01:24:41.644755
7809 01:24:41.644835 Set Vref, RX VrefLevel [Byte0]: 24
7810 01:24:41.647449 [Byte1]: 24
7811 01:24:41.652206
7812 01:24:41.652287 Set Vref, RX VrefLevel [Byte0]: 25
7813 01:24:41.654967 [Byte1]: 25
7814 01:24:41.659527
7815 01:24:41.659607 Set Vref, RX VrefLevel [Byte0]: 26
7816 01:24:41.662824 [Byte1]: 26
7817 01:24:41.667372
7818 01:24:41.667453 Set Vref, RX VrefLevel [Byte0]: 27
7819 01:24:41.670368 [Byte1]: 27
7820 01:24:41.674889
7821 01:24:41.674969 Set Vref, RX VrefLevel [Byte0]: 28
7822 01:24:41.677856 [Byte1]: 28
7823 01:24:41.682525
7824 01:24:41.682606 Set Vref, RX VrefLevel [Byte0]: 29
7825 01:24:41.685410 [Byte1]: 29
7826 01:24:41.690394
7827 01:24:41.690474 Set Vref, RX VrefLevel [Byte0]: 30
7828 01:24:41.693573 [Byte1]: 30
7829 01:24:41.697313
7830 01:24:41.697393 Set Vref, RX VrefLevel [Byte0]: 31
7831 01:24:41.701120 [Byte1]: 31
7832 01:24:41.705155
7833 01:24:41.705236 Set Vref, RX VrefLevel [Byte0]: 32
7834 01:24:41.708285 [Byte1]: 32
7835 01:24:41.712808
7836 01:24:41.712887 Set Vref, RX VrefLevel [Byte0]: 33
7837 01:24:41.716646 [Byte1]: 33
7838 01:24:41.720591
7839 01:24:41.720671 Set Vref, RX VrefLevel [Byte0]: 34
7840 01:24:41.723855 [Byte1]: 34
7841 01:24:41.727852
7842 01:24:41.727984 Set Vref, RX VrefLevel [Byte0]: 35
7843 01:24:41.731639 [Byte1]: 35
7844 01:24:41.735573
7845 01:24:41.735654 Set Vref, RX VrefLevel [Byte0]: 36
7846 01:24:41.738793 [Byte1]: 36
7847 01:24:41.743526
7848 01:24:41.743607 Set Vref, RX VrefLevel [Byte0]: 37
7849 01:24:41.746439 [Byte1]: 37
7850 01:24:41.750980
7851 01:24:41.751062 Set Vref, RX VrefLevel [Byte0]: 38
7852 01:24:41.753899 [Byte1]: 38
7853 01:24:41.758615
7854 01:24:41.761386 Set Vref, RX VrefLevel [Byte0]: 39
7855 01:24:41.765047 [Byte1]: 39
7856 01:24:41.765128
7857 01:24:41.768069 Set Vref, RX VrefLevel [Byte0]: 40
7858 01:24:41.771426 [Byte1]: 40
7859 01:24:41.771506
7860 01:24:41.775011 Set Vref, RX VrefLevel [Byte0]: 41
7861 01:24:41.778061 [Byte1]: 41
7862 01:24:41.781470
7863 01:24:41.781551 Set Vref, RX VrefLevel [Byte0]: 42
7864 01:24:41.784562 [Byte1]: 42
7865 01:24:41.789163
7866 01:24:41.789243 Set Vref, RX VrefLevel [Byte0]: 43
7867 01:24:41.792570 [Byte1]: 43
7868 01:24:41.796989
7869 01:24:41.797069 Set Vref, RX VrefLevel [Byte0]: 44
7870 01:24:41.800198 [Byte1]: 44
7871 01:24:41.804081
7872 01:24:41.804188 Set Vref, RX VrefLevel [Byte0]: 45
7873 01:24:41.807610 [Byte1]: 45
7874 01:24:41.811845
7875 01:24:41.811980 Set Vref, RX VrefLevel [Byte0]: 46
7876 01:24:41.815114 [Byte1]: 46
7877 01:24:41.819454
7878 01:24:41.819539 Set Vref, RX VrefLevel [Byte0]: 47
7879 01:24:41.823505 [Byte1]: 47
7880 01:24:41.826868
7881 01:24:41.826948 Set Vref, RX VrefLevel [Byte0]: 48
7882 01:24:41.830138 [Byte1]: 48
7883 01:24:41.835323
7884 01:24:41.835404 Set Vref, RX VrefLevel [Byte0]: 49
7885 01:24:41.838057 [Byte1]: 49
7886 01:24:41.842191
7887 01:24:41.842272 Set Vref, RX VrefLevel [Byte0]: 50
7888 01:24:41.845731 [Byte1]: 50
7889 01:24:41.849564
7890 01:24:41.849670 Set Vref, RX VrefLevel [Byte0]: 51
7891 01:24:41.852709 [Byte1]: 51
7892 01:24:41.857673
7893 01:24:41.857754 Set Vref, RX VrefLevel [Byte0]: 52
7894 01:24:41.860960 [Byte1]: 52
7895 01:24:41.865123
7896 01:24:41.865203 Set Vref, RX VrefLevel [Byte0]: 53
7897 01:24:41.868067 [Byte1]: 53
7898 01:24:41.872469
7899 01:24:41.872551 Set Vref, RX VrefLevel [Byte0]: 54
7900 01:24:41.876014 [Byte1]: 54
7901 01:24:41.880138
7902 01:24:41.880219 Set Vref, RX VrefLevel [Byte0]: 55
7903 01:24:41.883513 [Byte1]: 55
7904 01:24:41.887665
7905 01:24:41.887744 Set Vref, RX VrefLevel [Byte0]: 56
7906 01:24:41.890892 [Byte1]: 56
7907 01:24:41.895686
7908 01:24:41.895766 Set Vref, RX VrefLevel [Byte0]: 57
7909 01:24:41.898939 [Byte1]: 57
7910 01:24:41.902965
7911 01:24:41.903046 Set Vref, RX VrefLevel [Byte0]: 58
7912 01:24:41.906127 [Byte1]: 58
7913 01:24:41.910679
7914 01:24:41.910760 Set Vref, RX VrefLevel [Byte0]: 59
7915 01:24:41.914270 [Byte1]: 59
7916 01:24:41.918243
7917 01:24:41.918322 Set Vref, RX VrefLevel [Byte0]: 60
7918 01:24:41.921647 [Byte1]: 60
7919 01:24:41.926058
7920 01:24:41.926138 Set Vref, RX VrefLevel [Byte0]: 61
7921 01:24:41.929634 [Byte1]: 61
7922 01:24:41.933743
7923 01:24:41.933823 Set Vref, RX VrefLevel [Byte0]: 62
7924 01:24:41.936972 [Byte1]: 62
7925 01:24:41.941138
7926 01:24:41.941218 Set Vref, RX VrefLevel [Byte0]: 63
7927 01:24:41.944229 [Byte1]: 63
7928 01:24:41.948557
7929 01:24:41.948639 Set Vref, RX VrefLevel [Byte0]: 64
7930 01:24:41.952505 [Byte1]: 64
7931 01:24:41.956208
7932 01:24:41.956313 Set Vref, RX VrefLevel [Byte0]: 65
7933 01:24:41.959484 [Byte1]: 65
7934 01:24:41.964638
7935 01:24:41.964717 Set Vref, RX VrefLevel [Byte0]: 66
7936 01:24:41.967495 [Byte1]: 66
7937 01:24:41.972087
7938 01:24:41.972167 Set Vref, RX VrefLevel [Byte0]: 67
7939 01:24:41.974926 [Byte1]: 67
7940 01:24:41.978987
7941 01:24:41.979093 Set Vref, RX VrefLevel [Byte0]: 68
7942 01:24:41.982505 [Byte1]: 68
7943 01:24:41.986985
7944 01:24:41.987064 Set Vref, RX VrefLevel [Byte0]: 69
7945 01:24:41.989935 [Byte1]: 69
7946 01:24:41.994883
7947 01:24:41.994962 Set Vref, RX VrefLevel [Byte0]: 70
7948 01:24:41.997792 [Byte1]: 70
7949 01:24:42.002500
7950 01:24:42.002579 Set Vref, RX VrefLevel [Byte0]: 71
7951 01:24:42.005060 [Byte1]: 71
7952 01:24:42.009668
7953 01:24:42.009748 Set Vref, RX VrefLevel [Byte0]: 72
7954 01:24:42.012951 [Byte1]: 72
7955 01:24:42.017386
7956 01:24:42.017465 Set Vref, RX VrefLevel [Byte0]: 73
7957 01:24:42.020261 [Byte1]: 73
7958 01:24:42.024861
7959 01:24:42.024940 Set Vref, RX VrefLevel [Byte0]: 74
7960 01:24:42.028435 [Byte1]: 74
7961 01:24:42.032672
7962 01:24:42.032752 Final RX Vref Byte 0 = 54 to rank0
7963 01:24:42.035834 Final RX Vref Byte 1 = 57 to rank0
7964 01:24:42.039416 Final RX Vref Byte 0 = 54 to rank1
7965 01:24:42.042238 Final RX Vref Byte 1 = 57 to rank1==
7966 01:24:42.045592 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 01:24:42.052647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 01:24:42.052728 ==
7969 01:24:42.052792 DQS Delay:
7970 01:24:42.055427 DQS0 = 0, DQS1 = 0
7971 01:24:42.055507 DQM Delay:
7972 01:24:42.055570 DQM0 = 128, DQM1 = 124
7973 01:24:42.058913 DQ Delay:
7974 01:24:42.062384 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7975 01:24:42.065616 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7976 01:24:42.068798 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7977 01:24:42.071877 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =132
7978 01:24:42.071995
7979 01:24:42.072059
7980 01:24:42.072117
7981 01:24:42.075925 [DramC_TX_OE_Calibration] TA2
7982 01:24:42.078516 Original DQ_B0 (3 6) =30, OEN = 27
7983 01:24:42.081895 Original DQ_B1 (3 6) =30, OEN = 27
7984 01:24:42.085374 24, 0x0, End_B0=24 End_B1=24
7985 01:24:42.088440 25, 0x0, End_B0=25 End_B1=25
7986 01:24:42.088521 26, 0x0, End_B0=26 End_B1=26
7987 01:24:42.091625 27, 0x0, End_B0=27 End_B1=27
7988 01:24:42.095309 28, 0x0, End_B0=28 End_B1=28
7989 01:24:42.098120 29, 0x0, End_B0=29 End_B1=29
7990 01:24:42.098202 30, 0x0, End_B0=30 End_B1=30
7991 01:24:42.102018 31, 0x4545, End_B0=30 End_B1=30
7992 01:24:42.104847 Byte0 end_step=30 best_step=27
7993 01:24:42.108168 Byte1 end_step=30 best_step=27
7994 01:24:42.111305 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 01:24:42.114912 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 01:24:42.114993
7997 01:24:42.115055
7998 01:24:42.121405 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7999 01:24:42.124739 CH0 RK0: MR19=303, MR18=1A17
8000 01:24:42.131493 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
8001 01:24:42.131574
8002 01:24:42.134970 ----->DramcWriteLeveling(PI) begin...
8003 01:24:42.135052 ==
8004 01:24:42.137601 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 01:24:42.141336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 01:24:42.141417 ==
8007 01:24:42.144393 Write leveling (Byte 0): 35 => 35
8008 01:24:42.147668 Write leveling (Byte 1): 29 => 29
8009 01:24:42.151079 DramcWriteLeveling(PI) end<-----
8010 01:24:42.151159
8011 01:24:42.151223 ==
8012 01:24:42.154711 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 01:24:42.160910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 01:24:42.160991 ==
8015 01:24:42.161059 [Gating] SW mode calibration
8016 01:24:42.171040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 01:24:42.174279 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 01:24:42.180369 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 01:24:42.184646 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 01:24:42.188303 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8021 01:24:42.193541 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8022 01:24:42.197077 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8023 01:24:42.200536 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8024 01:24:42.206949 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 01:24:42.210116 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 01:24:42.213815 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 01:24:42.219913 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8028 01:24:42.223566 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8029 01:24:42.226675 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8030 01:24:42.233266 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8031 01:24:42.236832 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8032 01:24:42.240434 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 01:24:42.246313 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 01:24:42.249683 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 01:24:42.253473 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8036 01:24:42.259787 1 6 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
8037 01:24:42.262951 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8038 01:24:42.266581 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8039 01:24:42.272778 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8040 01:24:42.275929 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 01:24:42.279101 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 01:24:42.285992 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 01:24:42.289520 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8044 01:24:42.292301 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 01:24:42.299247 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 01:24:42.302515 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 01:24:42.305439 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 01:24:42.312510 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 01:24:42.315511 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 01:24:42.318818 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 01:24:42.325208 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 01:24:42.328522 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 01:24:42.332174 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 01:24:42.338601 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 01:24:42.341605 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 01:24:42.344785 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 01:24:42.351607 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 01:24:42.354585 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 01:24:42.357932 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 01:24:42.364988 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 01:24:42.368424 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8062 01:24:42.371381 Total UI for P1: 0, mck2ui 16
8063 01:24:42.374629 best dqsien dly found for B0: ( 1, 9, 8)
8064 01:24:42.377932 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 01:24:42.384485 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 01:24:42.387847 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 01:24:42.391150 Total UI for P1: 0, mck2ui 16
8068 01:24:42.394571 best dqsien dly found for B1: ( 1, 9, 18)
8069 01:24:42.397806 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8070 01:24:42.400928 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8071 01:24:42.401007
8072 01:24:42.404379 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8073 01:24:42.407455 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8074 01:24:42.410726 [Gating] SW calibration Done
8075 01:24:42.410807 ==
8076 01:24:42.414095 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 01:24:42.418123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 01:24:42.420792 ==
8079 01:24:42.420873 RX Vref Scan: 0
8080 01:24:42.420937
8081 01:24:42.423940 RX Vref 0 -> 0, step: 1
8082 01:24:42.424040
8083 01:24:42.424104 RX Delay 0 -> 252, step: 8
8084 01:24:42.430848 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8085 01:24:42.434371 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8086 01:24:42.437300 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8087 01:24:42.441293 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8088 01:24:42.447568 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8089 01:24:42.450816 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8090 01:24:42.454155 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8091 01:24:42.457395 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8092 01:24:42.460592 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8093 01:24:42.464177 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8094 01:24:42.470451 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8095 01:24:42.473814 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8096 01:24:42.477239 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8097 01:24:42.480575 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8098 01:24:42.487420 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8099 01:24:42.490450 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8100 01:24:42.490531 ==
8101 01:24:42.493521 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 01:24:42.497300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 01:24:42.497382 ==
8104 01:24:42.500460 DQS Delay:
8105 01:24:42.500541 DQS0 = 0, DQS1 = 0
8106 01:24:42.500604 DQM Delay:
8107 01:24:42.503510 DQM0 = 132, DQM1 = 125
8108 01:24:42.503591 DQ Delay:
8109 01:24:42.506909 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8110 01:24:42.510064 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
8111 01:24:42.517053 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8112 01:24:42.520649 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8113 01:24:42.520730
8114 01:24:42.520794
8115 01:24:42.520854 ==
8116 01:24:42.523070 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 01:24:42.526733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 01:24:42.526814 ==
8119 01:24:42.526878
8120 01:24:42.526936
8121 01:24:42.529692 TX Vref Scan disable
8122 01:24:42.533604 == TX Byte 0 ==
8123 01:24:42.536398 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8124 01:24:42.539654 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8125 01:24:42.542978 == TX Byte 1 ==
8126 01:24:42.546753 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8127 01:24:42.549383 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8128 01:24:42.549464 ==
8129 01:24:42.552609 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 01:24:42.559209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 01:24:42.559290 ==
8132 01:24:42.571251
8133 01:24:42.574892 TX Vref early break, caculate TX vref
8134 01:24:42.578347 TX Vref=16, minBit 2, minWin=23, winSum=383
8135 01:24:42.581361 TX Vref=18, minBit 0, minWin=24, winSum=390
8136 01:24:42.584632 TX Vref=20, minBit 2, minWin=24, winSum=399
8137 01:24:42.587908 TX Vref=22, minBit 0, minWin=25, winSum=408
8138 01:24:42.591198 TX Vref=24, minBit 1, minWin=25, winSum=416
8139 01:24:42.597626 TX Vref=26, minBit 1, minWin=25, winSum=417
8140 01:24:42.600800 TX Vref=28, minBit 4, minWin=25, winSum=422
8141 01:24:42.604228 TX Vref=30, minBit 1, minWin=25, winSum=421
8142 01:24:42.607535 TX Vref=32, minBit 1, minWin=25, winSum=410
8143 01:24:42.610835 TX Vref=34, minBit 0, minWin=24, winSum=399
8144 01:24:42.617373 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8145 01:24:42.617455
8146 01:24:42.620617 Final TX Range 0 Vref 28
8147 01:24:42.620698
8148 01:24:42.620762 ==
8149 01:24:42.624099 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 01:24:42.627564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 01:24:42.627645 ==
8152 01:24:42.627709
8153 01:24:42.627769
8154 01:24:42.630471 TX Vref Scan disable
8155 01:24:42.637478 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8156 01:24:42.637560 == TX Byte 0 ==
8157 01:24:42.640627 u2DelayCellOfst[0]=10 cells (3 PI)
8158 01:24:42.643569 u2DelayCellOfst[1]=14 cells (4 PI)
8159 01:24:42.647052 u2DelayCellOfst[2]=7 cells (2 PI)
8160 01:24:42.650984 u2DelayCellOfst[3]=10 cells (3 PI)
8161 01:24:42.653606 u2DelayCellOfst[4]=7 cells (2 PI)
8162 01:24:42.657179 u2DelayCellOfst[5]=0 cells (0 PI)
8163 01:24:42.660217 u2DelayCellOfst[6]=14 cells (4 PI)
8164 01:24:42.663534 u2DelayCellOfst[7]=14 cells (4 PI)
8165 01:24:42.666754 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8166 01:24:42.670705 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8167 01:24:42.673525 == TX Byte 1 ==
8168 01:24:42.676867 u2DelayCellOfst[8]=0 cells (0 PI)
8169 01:24:42.679752 u2DelayCellOfst[9]=0 cells (0 PI)
8170 01:24:42.683264 u2DelayCellOfst[10]=7 cells (2 PI)
8171 01:24:42.683344 u2DelayCellOfst[11]=3 cells (1 PI)
8172 01:24:42.686404 u2DelayCellOfst[12]=10 cells (3 PI)
8173 01:24:42.689894 u2DelayCellOfst[13]=10 cells (3 PI)
8174 01:24:42.693197 u2DelayCellOfst[14]=18 cells (5 PI)
8175 01:24:42.696431 u2DelayCellOfst[15]=10 cells (3 PI)
8176 01:24:42.703476 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8177 01:24:42.706096 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8178 01:24:42.706177 DramC Write-DBI on
8179 01:24:42.709301 ==
8180 01:24:42.709381 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 01:24:42.716167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 01:24:42.716249 ==
8183 01:24:42.716313
8184 01:24:42.716372
8185 01:24:42.719821 TX Vref Scan disable
8186 01:24:42.719925 == TX Byte 0 ==
8187 01:24:42.726115 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8188 01:24:42.726196 == TX Byte 1 ==
8189 01:24:42.729355 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8190 01:24:42.732708 DramC Write-DBI off
8191 01:24:42.732791
8192 01:24:42.732856 [DATLAT]
8193 01:24:42.735711 Freq=1600, CH0 RK1
8194 01:24:42.735793
8195 01:24:42.735857 DATLAT Default: 0xf
8196 01:24:42.738998 0, 0xFFFF, sum = 0
8197 01:24:42.739081 1, 0xFFFF, sum = 0
8198 01:24:42.742481 2, 0xFFFF, sum = 0
8199 01:24:42.742564 3, 0xFFFF, sum = 0
8200 01:24:42.745573 4, 0xFFFF, sum = 0
8201 01:24:42.749086 5, 0xFFFF, sum = 0
8202 01:24:42.749169 6, 0xFFFF, sum = 0
8203 01:24:42.752066 7, 0xFFFF, sum = 0
8204 01:24:42.752149 8, 0xFFFF, sum = 0
8205 01:24:42.755797 9, 0xFFFF, sum = 0
8206 01:24:42.755879 10, 0xFFFF, sum = 0
8207 01:24:42.758554 11, 0xFFFF, sum = 0
8208 01:24:42.758636 12, 0xFFFF, sum = 0
8209 01:24:42.762084 13, 0xFFFF, sum = 0
8210 01:24:42.762166 14, 0x0, sum = 1
8211 01:24:42.765958 15, 0x0, sum = 2
8212 01:24:42.766040 16, 0x0, sum = 3
8213 01:24:42.768876 17, 0x0, sum = 4
8214 01:24:42.768958 best_step = 15
8215 01:24:42.769021
8216 01:24:42.769081 ==
8217 01:24:42.771924 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 01:24:42.775229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 01:24:42.779046 ==
8220 01:24:42.779127 RX Vref Scan: 0
8221 01:24:42.779192
8222 01:24:42.781818 RX Vref 0 -> 0, step: 1
8223 01:24:42.781899
8224 01:24:42.786344 RX Delay 11 -> 252, step: 4
8225 01:24:42.789088 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8226 01:24:42.791839 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8227 01:24:42.795213 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8228 01:24:42.801541 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8229 01:24:42.804992 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8230 01:24:42.808431 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8231 01:24:42.811220 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8232 01:24:42.814948 iDelay=191, Bit 7, Center 136 (87 ~ 186) 100
8233 01:24:42.821406 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8234 01:24:42.824336 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8235 01:24:42.827763 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8236 01:24:42.831286 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8237 01:24:42.837842 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8238 01:24:42.841056 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8239 01:24:42.844663 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8240 01:24:42.847417 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8241 01:24:42.847500 ==
8242 01:24:42.850834 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 01:24:42.857413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 01:24:42.857494 ==
8245 01:24:42.857559 DQS Delay:
8246 01:24:42.857619 DQS0 = 0, DQS1 = 0
8247 01:24:42.860546 DQM Delay:
8248 01:24:42.860627 DQM0 = 129, DQM1 = 124
8249 01:24:42.864020 DQ Delay:
8250 01:24:42.867296 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8251 01:24:42.870429 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
8252 01:24:42.873599 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8253 01:24:42.877220 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =130
8254 01:24:42.877301
8255 01:24:42.877365
8256 01:24:42.877424
8257 01:24:42.880298 [DramC_TX_OE_Calibration] TA2
8258 01:24:42.883847 Original DQ_B0 (3 6) =30, OEN = 27
8259 01:24:42.886969 Original DQ_B1 (3 6) =30, OEN = 27
8260 01:24:42.890548 24, 0x0, End_B0=24 End_B1=24
8261 01:24:42.890630 25, 0x0, End_B0=25 End_B1=25
8262 01:24:42.893799 26, 0x0, End_B0=26 End_B1=26
8263 01:24:42.896797 27, 0x0, End_B0=27 End_B1=27
8264 01:24:42.900353 28, 0x0, End_B0=28 End_B1=28
8265 01:24:42.903218 29, 0x0, End_B0=29 End_B1=29
8266 01:24:42.903301 30, 0x0, End_B0=30 End_B1=30
8267 01:24:42.906755 31, 0x5151, End_B0=30 End_B1=30
8268 01:24:42.910002 Byte0 end_step=30 best_step=27
8269 01:24:42.913395 Byte1 end_step=30 best_step=27
8270 01:24:42.916922 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 01:24:42.920106 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 01:24:42.920187
8273 01:24:42.920250
8274 01:24:42.926712 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8275 01:24:42.929786 CH0 RK1: MR19=303, MR18=1412
8276 01:24:42.936468 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8277 01:24:42.939869 [RxdqsGatingPostProcess] freq 1600
8278 01:24:42.946235 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 01:24:42.946317 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 01:24:42.949552 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 01:24:42.952995 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 01:24:42.956100 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 01:24:42.959602 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 01:24:42.962554 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 01:24:42.965650 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 01:24:42.969265 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 01:24:42.972362 Pre-setting of DQS Precalculation
8288 01:24:42.975796 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 01:24:42.975877 ==
8290 01:24:42.979242 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 01:24:42.985687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 01:24:42.985768 ==
8293 01:24:42.988918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 01:24:42.995601 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 01:24:42.998647 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 01:24:43.005388 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 01:24:43.014101 [CA 0] Center 41 (11~72) winsize 62
8298 01:24:43.016669 [CA 1] Center 42 (12~72) winsize 61
8299 01:24:43.020108 [CA 2] Center 38 (9~67) winsize 59
8300 01:24:43.023155 [CA 3] Center 37 (8~66) winsize 59
8301 01:24:43.026595 [CA 4] Center 37 (8~67) winsize 60
8302 01:24:43.030252 [CA 5] Center 36 (7~66) winsize 60
8303 01:24:43.030332
8304 01:24:43.033220 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 01:24:43.033301
8306 01:24:43.036851 [CATrainingPosCal] consider 1 rank data
8307 01:24:43.039826 u2DelayCellTimex100 = 271/100 ps
8308 01:24:43.046697 CA0 delay=41 (11~72),Diff = 5 PI (18 cell)
8309 01:24:43.049847 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8310 01:24:43.053467 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8311 01:24:43.056389 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 01:24:43.059550 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8313 01:24:43.063045 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 01:24:43.063126
8315 01:24:43.066454 CA PerBit enable=1, Macro0, CA PI delay=36
8316 01:24:43.066536
8317 01:24:43.069511 [CBTSetCACLKResult] CA Dly = 36
8318 01:24:43.072650 CS Dly: 8 (0~39)
8319 01:24:43.075896 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 01:24:43.079075 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 01:24:43.079156 ==
8322 01:24:43.082470 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 01:24:43.089263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 01:24:43.089345 ==
8325 01:24:43.092660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 01:24:43.099048 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 01:24:43.102878 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 01:24:43.108952 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 01:24:43.116467 [CA 0] Center 41 (11~71) winsize 61
8330 01:24:43.119950 [CA 1] Center 41 (12~71) winsize 60
8331 01:24:43.123150 [CA 2] Center 37 (8~67) winsize 60
8332 01:24:43.126548 [CA 3] Center 36 (7~66) winsize 60
8333 01:24:43.129910 [CA 4] Center 37 (8~66) winsize 59
8334 01:24:43.133013 [CA 5] Center 36 (6~66) winsize 61
8335 01:24:43.133093
8336 01:24:43.136806 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 01:24:43.136887
8338 01:24:43.143104 [CATrainingPosCal] consider 2 rank data
8339 01:24:43.143185 u2DelayCellTimex100 = 271/100 ps
8340 01:24:43.149913 CA0 delay=41 (11~71),Diff = 5 PI (18 cell)
8341 01:24:43.152895 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8342 01:24:43.156106 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8343 01:24:43.159165 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8344 01:24:43.163582 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8345 01:24:43.165807 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8346 01:24:43.165888
8347 01:24:43.169345 CA PerBit enable=1, Macro0, CA PI delay=36
8348 01:24:43.169428
8349 01:24:43.173170 [CBTSetCACLKResult] CA Dly = 36
8350 01:24:43.176040 CS Dly: 10 (0~43)
8351 01:24:43.179027 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 01:24:43.182327 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 01:24:43.182408
8354 01:24:43.186007 ----->DramcWriteLeveling(PI) begin...
8355 01:24:43.186089 ==
8356 01:24:43.188907 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 01:24:43.195547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 01:24:43.195654 ==
8359 01:24:43.199114 Write leveling (Byte 0): 23 => 23
8360 01:24:43.202078 Write leveling (Byte 1): 26 => 26
8361 01:24:43.205371 DramcWriteLeveling(PI) end<-----
8362 01:24:43.205451
8363 01:24:43.205514 ==
8364 01:24:43.208950 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 01:24:43.211868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 01:24:43.211989 ==
8367 01:24:43.215203 [Gating] SW mode calibration
8368 01:24:43.222008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 01:24:43.225418 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 01:24:43.232035 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 01:24:43.235187 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 01:24:43.238896 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 01:24:43.245445 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8374 01:24:43.249116 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8375 01:24:43.251799 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 01:24:43.258279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 01:24:43.261806 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 01:24:43.264782 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 01:24:43.271620 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 01:24:43.274797 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8381 01:24:43.278226 1 5 12 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
8382 01:24:43.285080 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 01:24:43.287898 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 01:24:43.291287 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 01:24:43.297847 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 01:24:43.301321 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 01:24:43.304420 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 01:24:43.310906 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8389 01:24:43.314755 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8390 01:24:43.317762 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 01:24:43.324685 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 01:24:43.327472 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 01:24:43.330789 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 01:24:43.337310 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 01:24:43.341454 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 01:24:43.343926 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 01:24:43.350929 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 01:24:43.354059 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8399 01:24:43.357684 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 01:24:43.364241 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 01:24:43.366920 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 01:24:43.373403 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 01:24:43.376721 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 01:24:43.380424 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 01:24:43.386623 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 01:24:43.390238 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 01:24:43.393354 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 01:24:43.400481 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 01:24:43.403298 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 01:24:43.406425 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 01:24:43.412982 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 01:24:43.416039 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8413 01:24:43.419790 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8414 01:24:43.422962 Total UI for P1: 0, mck2ui 16
8415 01:24:43.426198 best dqsien dly found for B0: ( 1, 9, 8)
8416 01:24:43.432676 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 01:24:43.432757 Total UI for P1: 0, mck2ui 16
8418 01:24:43.436223 best dqsien dly found for B1: ( 1, 9, 12)
8419 01:24:43.439426 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8420 01:24:43.446020 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8421 01:24:43.446101
8422 01:24:43.449216 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8423 01:24:43.452669 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8424 01:24:43.455639 [Gating] SW calibration Done
8425 01:24:43.455745 ==
8426 01:24:43.458971 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 01:24:43.462794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 01:24:43.462877 ==
8429 01:24:43.466200 RX Vref Scan: 0
8430 01:24:43.466280
8431 01:24:43.466344 RX Vref 0 -> 0, step: 1
8432 01:24:43.466404
8433 01:24:43.469167 RX Delay 0 -> 252, step: 8
8434 01:24:43.472596 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8435 01:24:43.478810 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8436 01:24:43.481953 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8437 01:24:43.485712 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8438 01:24:43.489005 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8439 01:24:43.492083 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8440 01:24:43.498611 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8441 01:24:43.501826 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8442 01:24:43.505667 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8443 01:24:43.508390 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8444 01:24:43.512397 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8445 01:24:43.518123 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8446 01:24:43.521897 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8447 01:24:43.525006 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8448 01:24:43.528433 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8449 01:24:43.534689 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8450 01:24:43.534770 ==
8451 01:24:43.537952 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 01:24:43.541334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 01:24:43.541416 ==
8454 01:24:43.541481 DQS Delay:
8455 01:24:43.545039 DQS0 = 0, DQS1 = 0
8456 01:24:43.545119 DQM Delay:
8457 01:24:43.547981 DQM0 = 135, DQM1 = 130
8458 01:24:43.548062 DQ Delay:
8459 01:24:43.551113 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8460 01:24:43.555152 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8461 01:24:43.557942 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =127
8462 01:24:43.561548 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8463 01:24:43.561629
8464 01:24:43.564265
8465 01:24:43.564346 ==
8466 01:24:43.567636 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 01:24:43.571681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 01:24:43.571762 ==
8469 01:24:43.571826
8470 01:24:43.571886
8471 01:24:43.574232 TX Vref Scan disable
8472 01:24:43.574313 == TX Byte 0 ==
8473 01:24:43.581353 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8474 01:24:43.584169 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8475 01:24:43.584250 == TX Byte 1 ==
8476 01:24:43.591736 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8477 01:24:43.594273 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8478 01:24:43.594355 ==
8479 01:24:43.597548 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 01:24:43.600416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 01:24:43.600497 ==
8482 01:24:43.614283
8483 01:24:43.617973 TX Vref early break, caculate TX vref
8484 01:24:43.620887 TX Vref=16, minBit 8, minWin=22, winSum=370
8485 01:24:43.624374 TX Vref=18, minBit 8, minWin=22, winSum=376
8486 01:24:43.627649 TX Vref=20, minBit 6, minWin=23, winSum=386
8487 01:24:43.630648 TX Vref=22, minBit 1, minWin=24, winSum=396
8488 01:24:43.637454 TX Vref=24, minBit 9, minWin=23, winSum=403
8489 01:24:43.640423 TX Vref=26, minBit 2, minWin=25, winSum=411
8490 01:24:43.643715 TX Vref=28, minBit 9, minWin=25, winSum=419
8491 01:24:43.646826 TX Vref=30, minBit 0, minWin=24, winSum=412
8492 01:24:43.650134 TX Vref=32, minBit 9, minWin=23, winSum=403
8493 01:24:43.653866 TX Vref=34, minBit 0, minWin=23, winSum=397
8494 01:24:43.660354 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8495 01:24:43.660480
8496 01:24:43.663682 Final TX Range 0 Vref 28
8497 01:24:43.663832
8498 01:24:43.663987 ==
8499 01:24:43.667035 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 01:24:43.670100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 01:24:43.670222 ==
8502 01:24:43.670319
8503 01:24:43.670408
8504 01:24:43.673324 TX Vref Scan disable
8505 01:24:43.680120 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8506 01:24:43.680242 == TX Byte 0 ==
8507 01:24:43.683235 u2DelayCellOfst[0]=14 cells (4 PI)
8508 01:24:43.686724 u2DelayCellOfst[1]=10 cells (3 PI)
8509 01:24:43.690001 u2DelayCellOfst[2]=0 cells (0 PI)
8510 01:24:43.693725 u2DelayCellOfst[3]=7 cells (2 PI)
8511 01:24:43.697023 u2DelayCellOfst[4]=10 cells (3 PI)
8512 01:24:43.700234 u2DelayCellOfst[5]=18 cells (5 PI)
8513 01:24:43.703354 u2DelayCellOfst[6]=18 cells (5 PI)
8514 01:24:43.706917 u2DelayCellOfst[7]=7 cells (2 PI)
8515 01:24:43.710298 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8516 01:24:43.713148 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8517 01:24:43.716440 == TX Byte 1 ==
8518 01:24:43.719987 u2DelayCellOfst[8]=0 cells (0 PI)
8519 01:24:43.723575 u2DelayCellOfst[9]=7 cells (2 PI)
8520 01:24:43.726685 u2DelayCellOfst[10]=10 cells (3 PI)
8521 01:24:43.730005 u2DelayCellOfst[11]=3 cells (1 PI)
8522 01:24:43.732824 u2DelayCellOfst[12]=14 cells (4 PI)
8523 01:24:43.733211 u2DelayCellOfst[13]=14 cells (4 PI)
8524 01:24:43.736565 u2DelayCellOfst[14]=18 cells (5 PI)
8525 01:24:43.739860 u2DelayCellOfst[15]=18 cells (5 PI)
8526 01:24:43.746620 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8527 01:24:43.749732 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8528 01:24:43.750292 DramC Write-DBI on
8529 01:24:43.753213 ==
8530 01:24:43.756478 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 01:24:43.759830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 01:24:43.760453 ==
8533 01:24:43.760825
8534 01:24:43.761165
8535 01:24:43.763042 TX Vref Scan disable
8536 01:24:43.763502 == TX Byte 0 ==
8537 01:24:43.769266 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8538 01:24:43.769727 == TX Byte 1 ==
8539 01:24:43.772486 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8540 01:24:43.776699 DramC Write-DBI off
8541 01:24:43.777121
8542 01:24:43.777451 [DATLAT]
8543 01:24:43.779505 Freq=1600, CH1 RK0
8544 01:24:43.779968
8545 01:24:43.780315 DATLAT Default: 0xf
8546 01:24:43.782722 0, 0xFFFF, sum = 0
8547 01:24:43.783147 1, 0xFFFF, sum = 0
8548 01:24:43.786563 2, 0xFFFF, sum = 0
8549 01:24:43.786988 3, 0xFFFF, sum = 0
8550 01:24:43.789832 4, 0xFFFF, sum = 0
8551 01:24:43.792465 5, 0xFFFF, sum = 0
8552 01:24:43.792910 6, 0xFFFF, sum = 0
8553 01:24:43.795966 7, 0xFFFF, sum = 0
8554 01:24:43.796394 8, 0xFFFF, sum = 0
8555 01:24:43.799037 9, 0xFFFF, sum = 0
8556 01:24:43.799462 10, 0xFFFF, sum = 0
8557 01:24:43.802697 11, 0xFFFF, sum = 0
8558 01:24:43.803221 12, 0xFFFF, sum = 0
8559 01:24:43.805777 13, 0xFFFF, sum = 0
8560 01:24:43.806272 14, 0x0, sum = 1
8561 01:24:43.808706 15, 0x0, sum = 2
8562 01:24:43.809133 16, 0x0, sum = 3
8563 01:24:43.812190 17, 0x0, sum = 4
8564 01:24:43.812611 best_step = 15
8565 01:24:43.812944
8566 01:24:43.813251 ==
8567 01:24:43.815274 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 01:24:43.819083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 01:24:43.822012 ==
8570 01:24:43.822507 RX Vref Scan: 1
8571 01:24:43.822847
8572 01:24:43.825418 Set Vref Range= 24 -> 127
8573 01:24:43.825848
8574 01:24:43.829108 RX Vref 24 -> 127, step: 1
8575 01:24:43.829633
8576 01:24:43.829968 RX Delay 11 -> 252, step: 4
8577 01:24:43.830275
8578 01:24:43.832005 Set Vref, RX VrefLevel [Byte0]: 24
8579 01:24:43.835561 [Byte1]: 24
8580 01:24:43.839387
8581 01:24:43.839960 Set Vref, RX VrefLevel [Byte0]: 25
8582 01:24:43.843133 [Byte1]: 25
8583 01:24:43.847853
8584 01:24:43.848457 Set Vref, RX VrefLevel [Byte0]: 26
8585 01:24:43.850401 [Byte1]: 26
8586 01:24:43.855084
8587 01:24:43.855664 Set Vref, RX VrefLevel [Byte0]: 27
8588 01:24:43.858428 [Byte1]: 27
8589 01:24:43.862384
8590 01:24:43.862942 Set Vref, RX VrefLevel [Byte0]: 28
8591 01:24:43.865672 [Byte1]: 28
8592 01:24:43.869914
8593 01:24:43.870480 Set Vref, RX VrefLevel [Byte0]: 29
8594 01:24:43.872922 [Byte1]: 29
8595 01:24:43.877298
8596 01:24:43.877862 Set Vref, RX VrefLevel [Byte0]: 30
8597 01:24:43.880884 [Byte1]: 30
8598 01:24:43.884878
8599 01:24:43.885335 Set Vref, RX VrefLevel [Byte0]: 31
8600 01:24:43.888306 [Byte1]: 31
8601 01:24:43.892831
8602 01:24:43.893406 Set Vref, RX VrefLevel [Byte0]: 32
8603 01:24:43.895723 [Byte1]: 32
8604 01:24:43.900509
8605 01:24:43.901069 Set Vref, RX VrefLevel [Byte0]: 33
8606 01:24:43.903313 [Byte1]: 33
8607 01:24:43.907750
8608 01:24:43.908251 Set Vref, RX VrefLevel [Byte0]: 34
8609 01:24:43.911096 [Byte1]: 34
8610 01:24:43.915440
8611 01:24:43.916000 Set Vref, RX VrefLevel [Byte0]: 35
8612 01:24:43.918932 [Byte1]: 35
8613 01:24:43.923438
8614 01:24:43.923983 Set Vref, RX VrefLevel [Byte0]: 36
8615 01:24:43.926490 [Byte1]: 36
8616 01:24:43.930948
8617 01:24:43.931486 Set Vref, RX VrefLevel [Byte0]: 37
8618 01:24:43.934116 [Byte1]: 37
8619 01:24:43.938432
8620 01:24:43.938947 Set Vref, RX VrefLevel [Byte0]: 38
8621 01:24:43.941173 [Byte1]: 38
8622 01:24:43.945993
8623 01:24:43.946413 Set Vref, RX VrefLevel [Byte0]: 39
8624 01:24:43.949664 [Byte1]: 39
8625 01:24:43.954041
8626 01:24:43.954679 Set Vref, RX VrefLevel [Byte0]: 40
8627 01:24:43.957292 [Byte1]: 40
8628 01:24:43.961655
8629 01:24:43.962215 Set Vref, RX VrefLevel [Byte0]: 41
8630 01:24:43.964450 [Byte1]: 41
8631 01:24:43.969226
8632 01:24:43.969786 Set Vref, RX VrefLevel [Byte0]: 42
8633 01:24:43.972005 [Byte1]: 42
8634 01:24:43.976489
8635 01:24:43.977054 Set Vref, RX VrefLevel [Byte0]: 43
8636 01:24:43.979656 [Byte1]: 43
8637 01:24:43.984223
8638 01:24:43.984699 Set Vref, RX VrefLevel [Byte0]: 44
8639 01:24:43.987553 [Byte1]: 44
8640 01:24:43.991687
8641 01:24:43.992299 Set Vref, RX VrefLevel [Byte0]: 45
8642 01:24:43.994898 [Byte1]: 45
8643 01:24:43.999033
8644 01:24:43.999492 Set Vref, RX VrefLevel [Byte0]: 46
8645 01:24:44.002529 [Byte1]: 46
8646 01:24:44.007002
8647 01:24:44.007463 Set Vref, RX VrefLevel [Byte0]: 47
8648 01:24:44.009959 [Byte1]: 47
8649 01:24:44.014898
8650 01:24:44.015456 Set Vref, RX VrefLevel [Byte0]: 48
8651 01:24:44.018265 [Byte1]: 48
8652 01:24:44.022405
8653 01:24:44.023044 Set Vref, RX VrefLevel [Byte0]: 49
8654 01:24:44.025137 [Byte1]: 49
8655 01:24:44.030015
8656 01:24:44.030579 Set Vref, RX VrefLevel [Byte0]: 50
8657 01:24:44.033426 [Byte1]: 50
8658 01:24:44.036952
8659 01:24:44.037412 Set Vref, RX VrefLevel [Byte0]: 51
8660 01:24:44.040645 [Byte1]: 51
8661 01:24:44.045038
8662 01:24:44.045610 Set Vref, RX VrefLevel [Byte0]: 52
8663 01:24:44.048618 [Byte1]: 52
8664 01:24:44.052258
8665 01:24:44.052724 Set Vref, RX VrefLevel [Byte0]: 53
8666 01:24:44.056159 [Byte1]: 53
8667 01:24:44.060261
8668 01:24:44.060823 Set Vref, RX VrefLevel [Byte0]: 54
8669 01:24:44.063170 [Byte1]: 54
8670 01:24:44.067974
8671 01:24:44.068393 Set Vref, RX VrefLevel [Byte0]: 55
8672 01:24:44.070933 [Byte1]: 55
8673 01:24:44.075494
8674 01:24:44.075929 Set Vref, RX VrefLevel [Byte0]: 56
8675 01:24:44.078421 [Byte1]: 56
8676 01:24:44.082852
8677 01:24:44.083377 Set Vref, RX VrefLevel [Byte0]: 57
8678 01:24:44.086028 [Byte1]: 57
8679 01:24:44.090512
8680 01:24:44.091001 Set Vref, RX VrefLevel [Byte0]: 58
8681 01:24:44.094028 [Byte1]: 58
8682 01:24:44.097818
8683 01:24:44.098235 Set Vref, RX VrefLevel [Byte0]: 59
8684 01:24:44.102185 [Byte1]: 59
8685 01:24:44.106379
8686 01:24:44.107008 Set Vref, RX VrefLevel [Byte0]: 60
8687 01:24:44.108995 [Byte1]: 60
8688 01:24:44.113170
8689 01:24:44.113646 Set Vref, RX VrefLevel [Byte0]: 61
8690 01:24:44.116709 [Byte1]: 61
8691 01:24:44.120712
8692 01:24:44.121127 Set Vref, RX VrefLevel [Byte0]: 62
8693 01:24:44.124310 [Byte1]: 62
8694 01:24:44.128502
8695 01:24:44.128916 Set Vref, RX VrefLevel [Byte0]: 63
8696 01:24:44.131818 [Byte1]: 63
8697 01:24:44.136110
8698 01:24:44.136640 Set Vref, RX VrefLevel [Byte0]: 64
8699 01:24:44.139377 [Byte1]: 64
8700 01:24:44.143718
8701 01:24:44.144301 Set Vref, RX VrefLevel [Byte0]: 65
8702 01:24:44.147753 [Byte1]: 65
8703 01:24:44.151712
8704 01:24:44.152293 Set Vref, RX VrefLevel [Byte0]: 66
8705 01:24:44.154783 [Byte1]: 66
8706 01:24:44.159357
8707 01:24:44.159880 Set Vref, RX VrefLevel [Byte0]: 67
8708 01:24:44.163058 [Byte1]: 67
8709 01:24:44.166385
8710 01:24:44.167010 Set Vref, RX VrefLevel [Byte0]: 68
8711 01:24:44.169933 [Byte1]: 68
8712 01:24:44.173950
8713 01:24:44.174366 Set Vref, RX VrefLevel [Byte0]: 69
8714 01:24:44.177528 [Byte1]: 69
8715 01:24:44.181940
8716 01:24:44.182461 Set Vref, RX VrefLevel [Byte0]: 70
8717 01:24:44.185429 [Byte1]: 70
8718 01:24:44.189572
8719 01:24:44.190092 Set Vref, RX VrefLevel [Byte0]: 71
8720 01:24:44.192597 [Byte1]: 71
8721 01:24:44.197541
8722 01:24:44.198112 Final RX Vref Byte 0 = 52 to rank0
8723 01:24:44.200797 Final RX Vref Byte 1 = 62 to rank0
8724 01:24:44.204001 Final RX Vref Byte 0 = 52 to rank1
8725 01:24:44.206802 Final RX Vref Byte 1 = 62 to rank1==
8726 01:24:44.210786 Dram Type= 6, Freq= 0, CH_1, rank 0
8727 01:24:44.216875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 01:24:44.217387 ==
8729 01:24:44.217717 DQS Delay:
8730 01:24:44.220483 DQS0 = 0, DQS1 = 0
8731 01:24:44.220952 DQM Delay:
8732 01:24:44.223071 DQM0 = 132, DQM1 = 128
8733 01:24:44.223525 DQ Delay:
8734 01:24:44.226287 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8735 01:24:44.230934 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =126
8736 01:24:44.233096 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8737 01:24:44.236758 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8738 01:24:44.237233
8739 01:24:44.237590
8740 01:24:44.237917
8741 01:24:44.240105 [DramC_TX_OE_Calibration] TA2
8742 01:24:44.242978 Original DQ_B0 (3 6) =30, OEN = 27
8743 01:24:44.246504 Original DQ_B1 (3 6) =30, OEN = 27
8744 01:24:44.249827 24, 0x0, End_B0=24 End_B1=24
8745 01:24:44.252606 25, 0x0, End_B0=25 End_B1=25
8746 01:24:44.253032 26, 0x0, End_B0=26 End_B1=26
8747 01:24:44.255849 27, 0x0, End_B0=27 End_B1=27
8748 01:24:44.259641 28, 0x0, End_B0=28 End_B1=28
8749 01:24:44.262826 29, 0x0, End_B0=29 End_B1=29
8750 01:24:44.263347 30, 0x0, End_B0=30 End_B1=30
8751 01:24:44.266078 31, 0x4141, End_B0=30 End_B1=30
8752 01:24:44.269392 Byte0 end_step=30 best_step=27
8753 01:24:44.273031 Byte1 end_step=30 best_step=27
8754 01:24:44.276037 Byte0 TX OE(2T, 0.5T) = (3, 3)
8755 01:24:44.279517 Byte1 TX OE(2T, 0.5T) = (3, 3)
8756 01:24:44.280038
8757 01:24:44.280409
8758 01:24:44.285467 [DQSOSCAuto] RK0, (LSB)MR18= 0xb15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8759 01:24:44.289215 CH1 RK0: MR19=303, MR18=B15
8760 01:24:44.295448 CH1_RK0: MR19=0x303, MR18=0xB15, DQSOSC=399, MR23=63, INC=23, DEC=15
8761 01:24:44.296058
8762 01:24:44.299260 ----->DramcWriteLeveling(PI) begin...
8763 01:24:44.299816 ==
8764 01:24:44.302565 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 01:24:44.305272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 01:24:44.305737 ==
8767 01:24:44.308919 Write leveling (Byte 0): 24 => 24
8768 01:24:44.312018 Write leveling (Byte 1): 26 => 26
8769 01:24:44.314912 DramcWriteLeveling(PI) end<-----
8770 01:24:44.315372
8771 01:24:44.315734 ==
8772 01:24:44.318549 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 01:24:44.325130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 01:24:44.325690 ==
8775 01:24:44.326286 [Gating] SW mode calibration
8776 01:24:44.335241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8777 01:24:44.338509 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8778 01:24:44.344659 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 01:24:44.348139 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 01:24:44.351261 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8781 01:24:44.358233 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8782 01:24:44.360897 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 01:24:44.364753 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 01:24:44.371009 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 01:24:44.374676 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 01:24:44.377511 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 01:24:44.384278 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8788 01:24:44.387078 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8789 01:24:44.391217 1 5 12 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8790 01:24:44.397507 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8791 01:24:44.400234 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 01:24:44.403853 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 01:24:44.410519 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 01:24:44.413447 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 01:24:44.417177 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8796 01:24:44.424076 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8797 01:24:44.427341 1 6 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8798 01:24:44.430130 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 01:24:44.436853 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 01:24:44.440021 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 01:24:44.443740 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 01:24:44.450153 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 01:24:44.453197 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 01:24:44.456751 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8805 01:24:44.463260 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8806 01:24:44.467100 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8807 01:24:44.470006 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 01:24:44.476605 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 01:24:44.479302 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 01:24:44.482564 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 01:24:44.489908 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 01:24:44.492678 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 01:24:44.496144 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 01:24:44.502342 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 01:24:44.506315 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 01:24:44.508853 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 01:24:44.515304 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 01:24:44.519068 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 01:24:44.522244 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8820 01:24:44.528564 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8821 01:24:44.532183 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 01:24:44.535715 Total UI for P1: 0, mck2ui 16
8823 01:24:44.538558 best dqsien dly found for B0: ( 1, 9, 6)
8824 01:24:44.542311 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 01:24:44.545495 Total UI for P1: 0, mck2ui 16
8826 01:24:44.549158 best dqsien dly found for B1: ( 1, 9, 12)
8827 01:24:44.552294 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8828 01:24:44.555000 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8829 01:24:44.555459
8830 01:24:44.562586 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8831 01:24:44.565462 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8832 01:24:44.569278 [Gating] SW calibration Done
8833 01:24:44.569829 ==
8834 01:24:44.571534 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 01:24:44.575723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 01:24:44.576328 ==
8837 01:24:44.578207 RX Vref Scan: 0
8838 01:24:44.578755
8839 01:24:44.579121 RX Vref 0 -> 0, step: 1
8840 01:24:44.579558
8841 01:24:44.581180 RX Delay 0 -> 252, step: 8
8842 01:24:44.584442 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8843 01:24:44.588530 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8844 01:24:44.595043 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8845 01:24:44.598154 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8846 01:24:44.601369 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8847 01:24:44.604854 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8848 01:24:44.608077 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8849 01:24:44.614500 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8850 01:24:44.617462 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8851 01:24:44.621040 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8852 01:24:44.625217 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8853 01:24:44.628095 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8854 01:24:44.634284 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8855 01:24:44.638108 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8856 01:24:44.641069 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8857 01:24:44.644094 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8858 01:24:44.644666 ==
8859 01:24:44.647978 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 01:24:44.654232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 01:24:44.654794 ==
8862 01:24:44.655163 DQS Delay:
8863 01:24:44.657304 DQS0 = 0, DQS1 = 0
8864 01:24:44.657814 DQM Delay:
8865 01:24:44.660836 DQM0 = 133, DQM1 = 130
8866 01:24:44.661391 DQ Delay:
8867 01:24:44.664504 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8868 01:24:44.667095 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8869 01:24:44.670510 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8870 01:24:44.674385 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8871 01:24:44.674938
8872 01:24:44.675302
8873 01:24:44.675638 ==
8874 01:24:44.676755 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 01:24:44.683745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 01:24:44.684358 ==
8877 01:24:44.684734
8878 01:24:44.685072
8879 01:24:44.687155 TX Vref Scan disable
8880 01:24:44.687608 == TX Byte 0 ==
8881 01:24:44.690204 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8882 01:24:44.696715 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8883 01:24:44.697253 == TX Byte 1 ==
8884 01:24:44.700117 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8885 01:24:44.707146 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8886 01:24:44.707704 ==
8887 01:24:44.710140 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 01:24:44.713459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 01:24:44.714014 ==
8890 01:24:44.728209
8891 01:24:44.730944 TX Vref early break, caculate TX vref
8892 01:24:44.733895 TX Vref=16, minBit 9, minWin=22, winSum=378
8893 01:24:44.737334 TX Vref=18, minBit 9, minWin=22, winSum=386
8894 01:24:44.740577 TX Vref=20, minBit 9, minWin=22, winSum=393
8895 01:24:44.744076 TX Vref=22, minBit 9, minWin=22, winSum=402
8896 01:24:44.747227 TX Vref=24, minBit 8, minWin=24, winSum=411
8897 01:24:44.753846 TX Vref=26, minBit 1, minWin=25, winSum=417
8898 01:24:44.757280 TX Vref=28, minBit 9, minWin=24, winSum=419
8899 01:24:44.760073 TX Vref=30, minBit 8, minWin=25, winSum=416
8900 01:24:44.764088 TX Vref=32, minBit 8, minWin=24, winSum=407
8901 01:24:44.766915 TX Vref=34, minBit 9, minWin=23, winSum=399
8902 01:24:44.773864 TX Vref=36, minBit 8, minWin=22, winSum=396
8903 01:24:44.776546 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 26
8904 01:24:44.777007
8905 01:24:44.779858 Final TX Range 0 Vref 26
8906 01:24:44.780357
8907 01:24:44.780718 ==
8908 01:24:44.783768 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 01:24:44.787142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 01:24:44.789582 ==
8911 01:24:44.790137
8912 01:24:44.790501
8913 01:24:44.790840 TX Vref Scan disable
8914 01:24:44.796669 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8915 01:24:44.797263 == TX Byte 0 ==
8916 01:24:44.799890 u2DelayCellOfst[0]=14 cells (4 PI)
8917 01:24:44.803171 u2DelayCellOfst[1]=10 cells (3 PI)
8918 01:24:44.806346 u2DelayCellOfst[2]=0 cells (0 PI)
8919 01:24:44.809462 u2DelayCellOfst[3]=3 cells (1 PI)
8920 01:24:44.813197 u2DelayCellOfst[4]=7 cells (2 PI)
8921 01:24:44.815773 u2DelayCellOfst[5]=14 cells (4 PI)
8922 01:24:44.819256 u2DelayCellOfst[6]=14 cells (4 PI)
8923 01:24:44.822536 u2DelayCellOfst[7]=3 cells (1 PI)
8924 01:24:44.826008 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8925 01:24:44.829057 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8926 01:24:44.832341 == TX Byte 1 ==
8927 01:24:44.835977 u2DelayCellOfst[8]=0 cells (0 PI)
8928 01:24:44.839415 u2DelayCellOfst[9]=3 cells (1 PI)
8929 01:24:44.842805 u2DelayCellOfst[10]=14 cells (4 PI)
8930 01:24:44.845934 u2DelayCellOfst[11]=7 cells (2 PI)
8931 01:24:44.849043 u2DelayCellOfst[12]=18 cells (5 PI)
8932 01:24:44.852604 u2DelayCellOfst[13]=18 cells (5 PI)
8933 01:24:44.853118 u2DelayCellOfst[14]=21 cells (6 PI)
8934 01:24:44.855782 u2DelayCellOfst[15]=21 cells (6 PI)
8935 01:24:44.862347 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8936 01:24:44.866883 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8937 01:24:44.869014 DramC Write-DBI on
8938 01:24:44.869433 ==
8939 01:24:44.872692 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 01:24:44.875557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 01:24:44.876166 ==
8942 01:24:44.876519
8943 01:24:44.876831
8944 01:24:44.878714 TX Vref Scan disable
8945 01:24:44.879130 == TX Byte 0 ==
8946 01:24:44.885537 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8947 01:24:44.886049 == TX Byte 1 ==
8948 01:24:44.888963 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8949 01:24:44.892396 DramC Write-DBI off
8950 01:24:44.892905
8951 01:24:44.893236 [DATLAT]
8952 01:24:44.895382 Freq=1600, CH1 RK1
8953 01:24:44.895796
8954 01:24:44.896175 DATLAT Default: 0xf
8955 01:24:44.898714 0, 0xFFFF, sum = 0
8956 01:24:44.899134 1, 0xFFFF, sum = 0
8957 01:24:44.902079 2, 0xFFFF, sum = 0
8958 01:24:44.902598 3, 0xFFFF, sum = 0
8959 01:24:44.905746 4, 0xFFFF, sum = 0
8960 01:24:44.908823 5, 0xFFFF, sum = 0
8961 01:24:44.909345 6, 0xFFFF, sum = 0
8962 01:24:44.912238 7, 0xFFFF, sum = 0
8963 01:24:44.912660 8, 0xFFFF, sum = 0
8964 01:24:44.915217 9, 0xFFFF, sum = 0
8965 01:24:44.915636 10, 0xFFFF, sum = 0
8966 01:24:44.918580 11, 0xFFFF, sum = 0
8967 01:24:44.918999 12, 0xFFFF, sum = 0
8968 01:24:44.921493 13, 0xFFFF, sum = 0
8969 01:24:44.921961 14, 0x0, sum = 1
8970 01:24:44.925167 15, 0x0, sum = 2
8971 01:24:44.925586 16, 0x0, sum = 3
8972 01:24:44.928795 17, 0x0, sum = 4
8973 01:24:44.929219 best_step = 15
8974 01:24:44.929547
8975 01:24:44.929848 ==
8976 01:24:44.931620 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 01:24:44.938463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 01:24:44.938979 ==
8979 01:24:44.939314 RX Vref Scan: 0
8980 01:24:44.939623
8981 01:24:44.941675 RX Vref 0 -> 0, step: 1
8982 01:24:44.942089
8983 01:24:44.945389 RX Delay 19 -> 252, step: 4
8984 01:24:44.948426 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8985 01:24:44.951542 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8986 01:24:44.954652 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8987 01:24:44.961275 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8988 01:24:44.964844 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8989 01:24:44.968752 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8990 01:24:44.970945 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8991 01:24:44.974540 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8992 01:24:44.981104 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8993 01:24:44.984365 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8994 01:24:44.987529 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8995 01:24:44.991288 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8996 01:24:44.997197 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8997 01:24:45.000909 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8998 01:24:45.004015 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8999 01:24:45.007288 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9000 01:24:45.007865 ==
9001 01:24:45.010687 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 01:24:45.017509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 01:24:45.018039 ==
9004 01:24:45.018376 DQS Delay:
9005 01:24:45.020222 DQS0 = 0, DQS1 = 0
9006 01:24:45.020637 DQM Delay:
9007 01:24:45.020964 DQM0 = 131, DQM1 = 128
9008 01:24:45.023525 DQ Delay:
9009 01:24:45.027063 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =128
9010 01:24:45.030301 DQ4 =132, DQ5 =142, DQ6 =140, DQ7 =128
9011 01:24:45.033672 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9012 01:24:45.037225 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9013 01:24:45.037738
9014 01:24:45.038066
9015 01:24:45.038369
9016 01:24:45.040252 [DramC_TX_OE_Calibration] TA2
9017 01:24:45.044203 Original DQ_B0 (3 6) =30, OEN = 27
9018 01:24:45.047020 Original DQ_B1 (3 6) =30, OEN = 27
9019 01:24:45.050317 24, 0x0, End_B0=24 End_B1=24
9020 01:24:45.053922 25, 0x0, End_B0=25 End_B1=25
9021 01:24:45.054439 26, 0x0, End_B0=26 End_B1=26
9022 01:24:45.056616 27, 0x0, End_B0=27 End_B1=27
9023 01:24:45.060494 28, 0x0, End_B0=28 End_B1=28
9024 01:24:45.063836 29, 0x0, End_B0=29 End_B1=29
9025 01:24:45.064394 30, 0x0, End_B0=30 End_B1=30
9026 01:24:45.067074 31, 0x4141, End_B0=30 End_B1=30
9027 01:24:45.069579 Byte0 end_step=30 best_step=27
9028 01:24:45.073925 Byte1 end_step=30 best_step=27
9029 01:24:45.076462 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 01:24:45.080090 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 01:24:45.080593
9032 01:24:45.080924
9033 01:24:45.087145 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9034 01:24:45.089947 CH1 RK1: MR19=303, MR18=E1C
9035 01:24:45.096519 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9036 01:24:45.099769 [RxdqsGatingPostProcess] freq 1600
9037 01:24:45.103146 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 01:24:45.106487 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 01:24:45.109227 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 01:24:45.112894 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 01:24:45.115972 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 01:24:45.119337 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 01:24:45.122422 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 01:24:45.125984 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 01:24:45.129112 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 01:24:45.132586 Pre-setting of DQS Precalculation
9047 01:24:45.135438 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 01:24:45.146174 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 01:24:45.152917 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 01:24:45.153466
9051 01:24:45.153829
9052 01:24:45.155995 [Calibration Summary] 3200 Mbps
9053 01:24:45.156461 CH 0, Rank 0
9054 01:24:45.159136 SW Impedance : PASS
9055 01:24:45.159834 DUTY Scan : NO K
9056 01:24:45.162611 ZQ Calibration : PASS
9057 01:24:45.165456 Jitter Meter : NO K
9058 01:24:45.166002 CBT Training : PASS
9059 01:24:45.168849 Write leveling : PASS
9060 01:24:45.172438 RX DQS gating : PASS
9061 01:24:45.172986 RX DQ/DQS(RDDQC) : PASS
9062 01:24:45.175736 TX DQ/DQS : PASS
9063 01:24:45.178688 RX DATLAT : PASS
9064 01:24:45.179234 RX DQ/DQS(Engine): PASS
9065 01:24:45.181944 TX OE : PASS
9066 01:24:45.182409 All Pass.
9067 01:24:45.182775
9068 01:24:45.185518 CH 0, Rank 1
9069 01:24:45.185979 SW Impedance : PASS
9070 01:24:45.188524 DUTY Scan : NO K
9071 01:24:45.192493 ZQ Calibration : PASS
9072 01:24:45.193041 Jitter Meter : NO K
9073 01:24:45.195297 CBT Training : PASS
9074 01:24:45.198385 Write leveling : PASS
9075 01:24:45.198848 RX DQS gating : PASS
9076 01:24:45.202180 RX DQ/DQS(RDDQC) : PASS
9077 01:24:45.202733 TX DQ/DQS : PASS
9078 01:24:45.204871 RX DATLAT : PASS
9079 01:24:45.208655 RX DQ/DQS(Engine): PASS
9080 01:24:45.209217 TX OE : PASS
9081 01:24:45.211673 All Pass.
9082 01:24:45.212276
9083 01:24:45.212647 CH 1, Rank 0
9084 01:24:45.214839 SW Impedance : PASS
9085 01:24:45.215293 DUTY Scan : NO K
9086 01:24:45.218052 ZQ Calibration : PASS
9087 01:24:45.222048 Jitter Meter : NO K
9088 01:24:45.222498 CBT Training : PASS
9089 01:24:45.224654 Write leveling : PASS
9090 01:24:45.228123 RX DQS gating : PASS
9091 01:24:45.228536 RX DQ/DQS(RDDQC) : PASS
9092 01:24:45.231208 TX DQ/DQS : PASS
9093 01:24:45.234577 RX DATLAT : PASS
9094 01:24:45.235009 RX DQ/DQS(Engine): PASS
9095 01:24:45.237731 TX OE : PASS
9096 01:24:45.238152 All Pass.
9097 01:24:45.238481
9098 01:24:45.240952 CH 1, Rank 1
9099 01:24:45.241368 SW Impedance : PASS
9100 01:24:45.244496 DUTY Scan : NO K
9101 01:24:45.247626 ZQ Calibration : PASS
9102 01:24:45.248085 Jitter Meter : NO K
9103 01:24:45.250681 CBT Training : PASS
9104 01:24:45.254522 Write leveling : PASS
9105 01:24:45.254956 RX DQS gating : PASS
9106 01:24:45.257717 RX DQ/DQS(RDDQC) : PASS
9107 01:24:45.260596 TX DQ/DQS : PASS
9108 01:24:45.261024 RX DATLAT : PASS
9109 01:24:45.264028 RX DQ/DQS(Engine): PASS
9110 01:24:45.267114 TX OE : PASS
9111 01:24:45.267414 All Pass.
9112 01:24:45.267649
9113 01:24:45.267869 DramC Write-DBI on
9114 01:24:45.270663 PER_BANK_REFRESH: Hybrid Mode
9115 01:24:45.274101 TX_TRACKING: ON
9116 01:24:45.281048 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 01:24:45.290461 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 01:24:45.296972 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 01:24:45.300620 [FAST_K] Save calibration result to emmc
9120 01:24:45.304163 sync common calibartion params.
9121 01:24:45.307203 sync cbt_mode0:1, 1:1
9122 01:24:45.307715 dram_init: ddr_geometry: 2
9123 01:24:45.310821 dram_init: ddr_geometry: 2
9124 01:24:45.313810 dram_init: ddr_geometry: 2
9125 01:24:45.314376 0:dram_rank_size:100000000
9126 01:24:45.316994 1:dram_rank_size:100000000
9127 01:24:45.323410 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 01:24:45.327169 DFS_SHUFFLE_HW_MODE: ON
9129 01:24:45.330460 dramc_set_vcore_voltage set vcore to 725000
9130 01:24:45.330882 Read voltage for 1600, 0
9131 01:24:45.333883 Vio18 = 0
9132 01:24:45.334395 Vcore = 725000
9133 01:24:45.334731 Vdram = 0
9134 01:24:45.336676 Vddq = 0
9135 01:24:45.337093 Vmddr = 0
9136 01:24:45.340235 switch to 3200 Mbps bootup
9137 01:24:45.340653 [DramcRunTimeConfig]
9138 01:24:45.340983 PHYPLL
9139 01:24:45.343719 DPM_CONTROL_AFTERK: ON
9140 01:24:45.346924 PER_BANK_REFRESH: ON
9141 01:24:45.347340 REFRESH_OVERHEAD_REDUCTION: ON
9142 01:24:45.350343 CMD_PICG_NEW_MODE: OFF
9143 01:24:45.353617 XRTWTW_NEW_MODE: ON
9144 01:24:45.354130 XRTRTR_NEW_MODE: ON
9145 01:24:45.356612 TX_TRACKING: ON
9146 01:24:45.357031 RDSEL_TRACKING: OFF
9147 01:24:45.360017 DQS Precalculation for DVFS: ON
9148 01:24:45.363816 RX_TRACKING: OFF
9149 01:24:45.364380 HW_GATING DBG: ON
9150 01:24:45.367614 ZQCS_ENABLE_LP4: ON
9151 01:24:45.368181 RX_PICG_NEW_MODE: ON
9152 01:24:45.369937 TX_PICG_NEW_MODE: ON
9153 01:24:45.370355 ENABLE_RX_DCM_DPHY: ON
9154 01:24:45.373004 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 01:24:45.376672 DUMMY_READ_FOR_TRACKING: OFF
9156 01:24:45.380638 !!! SPM_CONTROL_AFTERK: OFF
9157 01:24:45.383015 !!! SPM could not control APHY
9158 01:24:45.383435 IMPEDANCE_TRACKING: ON
9159 01:24:45.386222 TEMP_SENSOR: ON
9160 01:24:45.386641 HW_SAVE_FOR_SR: OFF
9161 01:24:45.390012 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 01:24:45.393524 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 01:24:45.396150 Read ODT Tracking: ON
9164 01:24:45.399592 Refresh Rate DeBounce: ON
9165 01:24:45.400042 DFS_NO_QUEUE_FLUSH: ON
9166 01:24:45.403151 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 01:24:45.406803 ENABLE_DFS_RUNTIME_MRW: OFF
9168 01:24:45.409395 DDR_RESERVE_NEW_MODE: ON
9169 01:24:45.409907 MR_CBT_SWITCH_FREQ: ON
9170 01:24:45.412650 =========================
9171 01:24:45.431700 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 01:24:45.435683 dram_init: ddr_geometry: 2
9173 01:24:45.453241 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 01:24:45.456867 dram_init: dram init end (result: 0)
9175 01:24:45.463436 DRAM-K: Full calibration passed in 24429 msecs
9176 01:24:45.466351 MRC: failed to locate region type 0.
9177 01:24:45.466919 DRAM rank0 size:0x100000000,
9178 01:24:45.469407 DRAM rank1 size=0x100000000
9179 01:24:45.480164 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 01:24:45.486242 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 01:24:45.492834 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 01:24:45.499383 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 01:24:45.503182 DRAM rank0 size:0x100000000,
9184 01:24:45.506090 DRAM rank1 size=0x100000000
9185 01:24:45.506652 CBMEM:
9186 01:24:45.509151 IMD: root @ 0xfffff000 254 entries.
9187 01:24:45.512722 IMD: root @ 0xffffec00 62 entries.
9188 01:24:45.515801 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 01:24:45.522949 WARNING: RO_VPD is uninitialized or empty.
9190 01:24:45.525664 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 01:24:45.533410 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 01:24:45.545944 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9193 01:24:45.557624 BS: romstage times (exec / console): total (unknown) / 23956 ms
9194 01:24:45.558181
9195 01:24:45.558545
9196 01:24:45.567324 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 01:24:45.570627 ARM64: Exception handlers installed.
9198 01:24:45.573779 ARM64: Testing exception
9199 01:24:45.577271 ARM64: Done test exception
9200 01:24:45.577826 Enumerating buses...
9201 01:24:45.580308 Show all devs... Before device enumeration.
9202 01:24:45.583462 Root Device: enabled 1
9203 01:24:45.586844 CPU_CLUSTER: 0: enabled 1
9204 01:24:45.587324 CPU: 00: enabled 1
9205 01:24:45.590501 Compare with tree...
9206 01:24:45.591052 Root Device: enabled 1
9207 01:24:45.594083 CPU_CLUSTER: 0: enabled 1
9208 01:24:45.597162 CPU: 00: enabled 1
9209 01:24:45.597624 Root Device scanning...
9210 01:24:45.600604 scan_static_bus for Root Device
9211 01:24:45.604080 CPU_CLUSTER: 0 enabled
9212 01:24:45.606457 scan_static_bus for Root Device done
9213 01:24:45.610194 scan_bus: bus Root Device finished in 8 msecs
9214 01:24:45.610828 done
9215 01:24:45.616992 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 01:24:45.620194 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 01:24:45.626787 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 01:24:45.630058 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 01:24:45.633547 Allocating resources...
9220 01:24:45.636249 Reading resources...
9221 01:24:45.639970 Root Device read_resources bus 0 link: 0
9222 01:24:45.643181 DRAM rank0 size:0x100000000,
9223 01:24:45.643734 DRAM rank1 size=0x100000000
9224 01:24:45.649857 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 01:24:45.650411 CPU: 00 missing read_resources
9226 01:24:45.656904 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 01:24:45.660160 Root Device read_resources bus 0 link: 0 done
9228 01:24:45.662606 Done reading resources.
9229 01:24:45.667022 Show resources in subtree (Root Device)...After reading.
9230 01:24:45.669637 Root Device child on link 0 CPU_CLUSTER: 0
9231 01:24:45.672439 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 01:24:45.682531 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 01:24:45.683068 CPU: 00
9234 01:24:45.688769 Root Device assign_resources, bus 0 link: 0
9235 01:24:45.692297 CPU_CLUSTER: 0 missing set_resources
9236 01:24:45.695443 Root Device assign_resources, bus 0 link: 0 done
9237 01:24:45.696021 Done setting resources.
9238 01:24:45.701855 Show resources in subtree (Root Device)...After assigning values.
9239 01:24:45.705202 Root Device child on link 0 CPU_CLUSTER: 0
9240 01:24:45.712055 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 01:24:45.718699 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 01:24:45.721893 CPU: 00
9243 01:24:45.722502 Done allocating resources.
9244 01:24:45.728567 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 01:24:45.728957 Enabling resources...
9246 01:24:45.731880 done.
9247 01:24:45.734659 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 01:24:45.738347 Initializing devices...
9249 01:24:45.738743 Root Device init
9250 01:24:45.741398 init hardware done!
9251 01:24:45.741796 0x00000018: ctrlr->caps
9252 01:24:45.744447 52.000 MHz: ctrlr->f_max
9253 01:24:45.748399 0.400 MHz: ctrlr->f_min
9254 01:24:45.751196 0x40ff8080: ctrlr->voltages
9255 01:24:45.751767 sclk: 390625
9256 01:24:45.752323 Bus Width = 1
9257 01:24:45.754480 sclk: 390625
9258 01:24:45.754896 Bus Width = 1
9259 01:24:45.757703 Early init status = 3
9260 01:24:45.760872 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 01:24:45.765163 in-header: 03 fc 00 00 01 00 00 00
9262 01:24:45.768411 in-data: 00
9263 01:24:45.772186 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 01:24:45.776805 in-header: 03 fd 00 00 00 00 00 00
9265 01:24:45.780366 in-data:
9266 01:24:45.783845 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 01:24:45.787723 in-header: 03 fc 00 00 01 00 00 00
9268 01:24:45.791666 in-data: 00
9269 01:24:45.794419 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 01:24:45.799975 in-header: 03 fd 00 00 00 00 00 00
9271 01:24:45.803314 in-data:
9272 01:24:45.806716 [SSUSB] Setting up USB HOST controller...
9273 01:24:45.810730 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 01:24:45.813525 [SSUSB] phy power-on done.
9275 01:24:45.816737 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 01:24:45.823214 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 01:24:45.827046 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 01:24:45.832848 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 01:24:45.839689 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 01:24:45.845987 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 01:24:45.853096 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 01:24:45.859268 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9283 01:24:45.862775 SPM: binary array size = 0x9dc
9284 01:24:45.865762 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 01:24:45.872665 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 01:24:45.878978 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 01:24:45.886094 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 01:24:45.888800 configure_display: Starting display init
9289 01:24:45.923368 anx7625_power_on_init: Init interface.
9290 01:24:45.926700 anx7625_disable_pd_protocol: Disabled PD feature.
9291 01:24:45.929980 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 01:24:45.957344 anx7625_start_dp_work: Secure OCM version=00
9293 01:24:45.960316 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 01:24:45.976000 sp_tx_get_edid_block: EDID Block = 1
9295 01:24:46.078415 Extracted contents:
9296 01:24:46.081551 header: 00 ff ff ff ff ff ff 00
9297 01:24:46.085025 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 01:24:46.088931 version: 01 04
9299 01:24:46.091555 basic params: 95 1f 11 78 0a
9300 01:24:46.094912 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 01:24:46.098084 established: 00 00 00
9302 01:24:46.104637 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 01:24:46.108300 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 01:24:46.114764 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 01:24:46.121124 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 01:24:46.128682 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 01:24:46.131877 extensions: 00
9308 01:24:46.132300 checksum: fb
9309 01:24:46.132548
9310 01:24:46.134762 Manufacturer: IVO Model 57d Serial Number 0
9311 01:24:46.138061 Made week 0 of 2020
9312 01:24:46.138445 EDID version: 1.4
9313 01:24:46.141795 Digital display
9314 01:24:46.144623 6 bits per primary color channel
9315 01:24:46.144932 DisplayPort interface
9316 01:24:46.148041 Maximum image size: 31 cm x 17 cm
9317 01:24:46.151464 Gamma: 220%
9318 01:24:46.151987 Check DPMS levels
9319 01:24:46.154852 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 01:24:46.161845 First detailed timing is preferred timing
9321 01:24:46.162380 Established timings supported:
9322 01:24:46.164196 Standard timings supported:
9323 01:24:46.167667 Detailed timings
9324 01:24:46.170819 Hex of detail: 383680a07038204018303c0035ae10000019
9325 01:24:46.177824 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 01:24:46.181252 0780 0798 07c8 0820 hborder 0
9327 01:24:46.184694 0438 043b 0447 0458 vborder 0
9328 01:24:46.187512 -hsync -vsync
9329 01:24:46.187998 Did detailed timing
9330 01:24:46.194290 Hex of detail: 000000000000000000000000000000000000
9331 01:24:46.197091 Manufacturer-specified data, tag 0
9332 01:24:46.200581 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 01:24:46.203997 ASCII string: InfoVision
9334 01:24:46.207834 Hex of detail: 000000fe00523134304e574635205248200a
9335 01:24:46.211011 ASCII string: R140NWF5 RH
9336 01:24:46.211427 Checksum
9337 01:24:46.214406 Checksum: 0xfb (valid)
9338 01:24:46.217565 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 01:24:46.220397 DSI data_rate: 832800000 bps
9340 01:24:46.227393 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 01:24:46.230112 anx7625_parse_edid: pixelclock(138800).
9342 01:24:46.233318 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 01:24:46.236842 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 01:24:46.240536 anx7625_dsi_config: config dsi.
9345 01:24:46.246734 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 01:24:46.260344 anx7625_dsi_config: success to config DSI
9347 01:24:46.263589 anx7625_dp_start: MIPI phy setup OK.
9348 01:24:46.267921 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 01:24:46.269790 mtk_ddp_mode_set invalid vrefresh 60
9350 01:24:46.273283 main_disp_path_setup
9351 01:24:46.273363 ovl_layer_smi_id_en
9352 01:24:46.276768 ovl_layer_smi_id_en
9353 01:24:46.276849 ccorr_config
9354 01:24:46.276913 aal_config
9355 01:24:46.279852 gamma_config
9356 01:24:46.279980 postmask_config
9357 01:24:46.283124 dither_config
9358 01:24:46.286114 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 01:24:46.292604 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 01:24:46.296086 Root Device init finished in 554 msecs
9361 01:24:46.299196 CPU_CLUSTER: 0 init
9362 01:24:46.306166 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 01:24:46.312418 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 01:24:46.312502 APU_MBOX 0x190000b0 = 0x10001
9365 01:24:46.315883 APU_MBOX 0x190001b0 = 0x10001
9366 01:24:46.318991 APU_MBOX 0x190005b0 = 0x10001
9367 01:24:46.323340 APU_MBOX 0x190006b0 = 0x10001
9368 01:24:46.328854 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 01:24:46.339125 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9370 01:24:46.351219 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 01:24:46.358115 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 01:24:46.369514 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9373 01:24:46.378925 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 01:24:46.382262 CPU_CLUSTER: 0 init finished in 81 msecs
9375 01:24:46.385563 Devices initialized
9376 01:24:46.388600 Show all devs... After init.
9377 01:24:46.388680 Root Device: enabled 1
9378 01:24:46.391694 CPU_CLUSTER: 0: enabled 1
9379 01:24:46.395464 CPU: 00: enabled 1
9380 01:24:46.398393 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9381 01:24:46.401589 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 01:24:46.405368 ELOG: NV offset 0x57f000 size 0x1000
9383 01:24:46.411874 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9384 01:24:46.419361 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 01:24:46.422072 ELOG: Event(17) added with size 13 at 2023-08-28 01:24:47 UTC
9386 01:24:46.428874 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 01:24:46.431762 in-header: 03 2a 00 00 2c 00 00 00
9388 01:24:46.441970 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9389 01:24:46.447960 ELOG: Event(A1) added with size 10 at 2023-08-28 01:24:47 UTC
9390 01:24:46.455029 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9391 01:24:46.461392 ELOG: Event(A0) added with size 9 at 2023-08-28 01:24:47 UTC
9392 01:24:46.464712 elog_add_boot_reason: Logged dev mode boot
9393 01:24:46.471625 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9394 01:24:46.471747 Finalize devices...
9395 01:24:46.475192 Devices finalized
9396 01:24:46.477939 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 01:24:46.481682 Writing coreboot table at 0xffe64000
9398 01:24:46.484711 0. 000000000010a000-0000000000113fff: RAMSTAGE
9399 01:24:46.491638 1. 0000000040000000-00000000400fffff: RAM
9400 01:24:46.495076 2. 0000000040100000-000000004032afff: RAMSTAGE
9401 01:24:46.498058 3. 000000004032b000-00000000545fffff: RAM
9402 01:24:46.500867 4. 0000000054600000-000000005465ffff: BL31
9403 01:24:46.505048 5. 0000000054660000-00000000ffe63fff: RAM
9404 01:24:46.511021 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9405 01:24:46.514600 7. 0000000100000000-000000023fffffff: RAM
9406 01:24:46.517817 Passing 5 GPIOs to payload:
9407 01:24:46.521290 NAME | PORT | POLARITY | VALUE
9408 01:24:46.527739 EC in RW | 0x000000aa | low | undefined
9409 01:24:46.530908 EC interrupt | 0x00000005 | low | undefined
9410 01:24:46.534664 TPM interrupt | 0x000000ab | high | undefined
9411 01:24:46.541121 SD card detect | 0x00000011 | high | undefined
9412 01:24:46.544101 speaker enable | 0x00000093 | high | undefined
9413 01:24:46.547351 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9414 01:24:46.551551 in-header: 03 f9 00 00 02 00 00 00
9415 01:24:46.554390 in-data: 02 00
9416 01:24:46.558091 ADC[4]: Raw value=903325 ID=7
9417 01:24:46.561053 ADC[3]: Raw value=213916 ID=1
9418 01:24:46.561276 RAM Code: 0x71
9419 01:24:46.564793 ADC[6]: Raw value=75000 ID=0
9420 01:24:46.567788 ADC[5]: Raw value=213916 ID=1
9421 01:24:46.568016 SKU Code: 0x1
9422 01:24:46.574429 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 955a
9423 01:24:46.574676 coreboot table: 964 bytes.
9424 01:24:46.577566 IMD ROOT 0. 0xfffff000 0x00001000
9425 01:24:46.580949 IMD SMALL 1. 0xffffe000 0x00001000
9426 01:24:46.583867 RO MCACHE 2. 0xffffc000 0x00001104
9427 01:24:46.587663 CONSOLE 3. 0xfff7c000 0x00080000
9428 01:24:46.590504 FMAP 4. 0xfff7b000 0x00000452
9429 01:24:46.593942 TIME STAMP 5. 0xfff7a000 0x00000910
9430 01:24:46.597142 VBOOT WORK 6. 0xfff66000 0x00014000
9431 01:24:46.600397 RAMOOPS 7. 0xffe66000 0x00100000
9432 01:24:46.603596 COREBOOT 8. 0xffe64000 0x00002000
9433 01:24:46.606806 IMD small region:
9434 01:24:46.610486 IMD ROOT 0. 0xffffec00 0x00000400
9435 01:24:46.613995 VPD 1. 0xffffeb80 0x0000006c
9436 01:24:46.616697 MMC STATUS 2. 0xffffeb60 0x00000004
9437 01:24:46.623696 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9438 01:24:46.623956 Probing TPM: done!
9439 01:24:46.630245 Connected to device vid:did:rid of 1ae0:0028:00
9440 01:24:46.636551 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9441 01:24:46.640501 Initialized TPM device CR50 revision 0
9442 01:24:46.644451 Checking cr50 for pending updates
9443 01:24:46.649662 Reading cr50 TPM mode
9444 01:24:46.657931 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9445 01:24:46.665034 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9446 01:24:46.704767 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9447 01:24:46.708231 Checking segment from ROM address 0x40100000
9448 01:24:46.711637 Checking segment from ROM address 0x4010001c
9449 01:24:46.718325 Loading segment from ROM address 0x40100000
9450 01:24:46.718659 code (compression=0)
9451 01:24:46.727686 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9452 01:24:46.734423 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9453 01:24:46.734751 it's not compressed!
9454 01:24:46.740976 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9455 01:24:46.748187 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9456 01:24:46.765503 Loading segment from ROM address 0x4010001c
9457 01:24:46.765836 Entry Point 0x80000000
9458 01:24:46.768481 Loaded segments
9459 01:24:46.771801 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9460 01:24:46.778246 Jumping to boot code at 0x80000000(0xffe64000)
9461 01:24:46.785045 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9462 01:24:46.791589 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9463 01:24:46.800217 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9464 01:24:46.803235 Checking segment from ROM address 0x40100000
9465 01:24:46.806352 Checking segment from ROM address 0x4010001c
9466 01:24:46.812898 Loading segment from ROM address 0x40100000
9467 01:24:46.813227 code (compression=1)
9468 01:24:46.819396 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9469 01:24:46.829657 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9470 01:24:46.830000 using LZMA
9471 01:24:46.838257 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9472 01:24:46.844789 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9473 01:24:46.848439 Loading segment from ROM address 0x4010001c
9474 01:24:46.848682 Entry Point 0x54601000
9475 01:24:46.851640 Loaded segments
9476 01:24:46.854651 NOTICE: MT8192 bl31_setup
9477 01:24:46.861885 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9478 01:24:46.865066 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9479 01:24:46.868162 WARNING: region 0:
9480 01:24:46.871611 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 01:24:46.871950 WARNING: region 1:
9482 01:24:46.877953 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9483 01:24:46.881490 WARNING: region 2:
9484 01:24:46.885367 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9485 01:24:46.888730 WARNING: region 3:
9486 01:24:46.891987 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 01:24:46.895361 WARNING: region 4:
9488 01:24:46.901201 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 01:24:46.901530 WARNING: region 5:
9490 01:24:46.904597 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 01:24:46.908232 WARNING: region 6:
9492 01:24:46.911259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 01:24:46.914358 WARNING: region 7:
9494 01:24:46.917597 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 01:24:46.924344 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9496 01:24:46.928246 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9497 01:24:46.931227 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9498 01:24:46.937478 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9499 01:24:46.941142 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9500 01:24:46.947539 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9501 01:24:46.951513 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9502 01:24:46.955087 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9503 01:24:46.960899 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9504 01:24:46.964681 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9505 01:24:46.967844 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9506 01:24:46.974537 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9507 01:24:46.978160 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9508 01:24:46.984731 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9509 01:24:46.987768 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9510 01:24:46.991196 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9511 01:24:46.997980 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9512 01:24:47.001573 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9513 01:24:47.007839 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9514 01:24:47.011152 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9515 01:24:47.014312 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9516 01:24:47.021150 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9517 01:24:47.024292 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9518 01:24:47.027342 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9519 01:24:47.034103 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9520 01:24:47.037382 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9521 01:24:47.044618 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9522 01:24:47.047363 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9523 01:24:47.054236 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9524 01:24:47.057378 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9525 01:24:47.060981 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9526 01:24:47.067642 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9527 01:24:47.071141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9528 01:24:47.074202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9529 01:24:47.077329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9530 01:24:47.083897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9531 01:24:47.087228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9532 01:24:47.090487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9533 01:24:47.093835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9534 01:24:47.100537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9535 01:24:47.104129 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9536 01:24:47.107206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9537 01:24:47.110477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9538 01:24:47.117521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9539 01:24:47.120707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9540 01:24:47.123798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9541 01:24:47.127013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9542 01:24:47.134336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9543 01:24:47.137331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9544 01:24:47.143897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9545 01:24:47.147136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9546 01:24:47.150507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9547 01:24:47.157158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9548 01:24:47.160422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9549 01:24:47.167272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9550 01:24:47.170376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9551 01:24:47.177086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9552 01:24:47.180007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9553 01:24:47.183804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9554 01:24:47.190466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9555 01:24:47.193396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9556 01:24:47.200510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9557 01:24:47.203299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9558 01:24:47.210467 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9559 01:24:47.213520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9560 01:24:47.220091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9561 01:24:47.223991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9562 01:24:47.226451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9563 01:24:47.233562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9564 01:24:47.236490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9565 01:24:47.243315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9566 01:24:47.247043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9567 01:24:47.253413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9568 01:24:47.256474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9569 01:24:47.259596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9570 01:24:47.266688 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9571 01:24:47.270265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9572 01:24:47.276485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9573 01:24:47.280075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9574 01:24:47.288401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9575 01:24:47.290080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9576 01:24:47.297141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9577 01:24:47.300171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9578 01:24:47.303762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9579 01:24:47.310395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9580 01:24:47.313770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9581 01:24:47.320800 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9582 01:24:47.323312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9583 01:24:47.326640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9584 01:24:47.333657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9585 01:24:47.336665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9586 01:24:47.344027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9587 01:24:47.347194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9588 01:24:47.353829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9589 01:24:47.356545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9590 01:24:47.363410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9591 01:24:47.366939 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9592 01:24:47.370147 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9593 01:24:47.372858 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9594 01:24:47.380488 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9595 01:24:47.383177 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9596 01:24:47.386631 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9597 01:24:47.393090 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9598 01:24:47.396390 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9599 01:24:47.403126 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9600 01:24:47.406512 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9601 01:24:47.410006 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9602 01:24:47.416184 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9603 01:24:47.420069 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9604 01:24:47.425914 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9605 01:24:47.429534 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9606 01:24:47.433353 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9607 01:24:47.439581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9608 01:24:47.442659 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9609 01:24:47.449199 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9610 01:24:47.452645 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9611 01:24:47.456583 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9612 01:24:47.462698 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9613 01:24:47.466322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9614 01:24:47.469624 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9615 01:24:47.472640 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9616 01:24:47.479427 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9617 01:24:47.482639 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9618 01:24:47.485928 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9619 01:24:47.492299 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9620 01:24:47.496335 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9621 01:24:47.499729 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9622 01:24:47.505560 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9623 01:24:47.509611 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9624 01:24:47.516856 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9625 01:24:47.519090 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9626 01:24:47.522968 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9627 01:24:47.528890 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9628 01:24:47.532602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9629 01:24:47.535801 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9630 01:24:47.542815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9631 01:24:47.545920 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9632 01:24:47.553365 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9633 01:24:47.555332 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9634 01:24:47.558961 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9635 01:24:47.565807 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9636 01:24:47.569011 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9637 01:24:47.575947 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9638 01:24:47.578539 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9639 01:24:47.582216 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9640 01:24:47.588756 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9641 01:24:47.592457 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9642 01:24:47.595314 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9643 01:24:47.602026 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9644 01:24:47.605680 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9645 01:24:47.612147 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9646 01:24:47.615446 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9647 01:24:47.618957 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9648 01:24:47.625596 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9649 01:24:47.628900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9650 01:24:47.635576 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9651 01:24:47.638560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9652 01:24:47.642447 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9653 01:24:47.648392 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9654 01:24:47.651700 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9655 01:24:47.658391 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9656 01:24:47.661830 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9657 01:24:47.665627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9658 01:24:47.671991 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9659 01:24:47.675177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9660 01:24:47.681775 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9661 01:24:47.685796 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9662 01:24:47.688750 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9663 01:24:47.695739 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9664 01:24:47.698907 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9665 01:24:47.704992 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9666 01:24:47.708542 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9667 01:24:47.711354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9668 01:24:47.717802 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9669 01:24:47.721509 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9670 01:24:47.728163 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9671 01:24:47.732116 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9672 01:24:47.735160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9673 01:24:47.741079 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9674 01:24:47.744453 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9675 01:24:47.748108 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9676 01:24:47.754523 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9677 01:24:47.757892 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9678 01:24:47.764577 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9679 01:24:47.767889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9680 01:24:47.771717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9681 01:24:47.778427 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9682 01:24:47.781398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9683 01:24:47.787795 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9684 01:24:47.791217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9685 01:24:47.798046 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9686 01:24:47.801320 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9687 01:24:47.804240 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9688 01:24:47.810827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9689 01:24:47.814465 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9690 01:24:47.821169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9691 01:24:47.823791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9692 01:24:47.830321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9693 01:24:47.834144 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9694 01:24:47.836816 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9695 01:24:47.844078 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9696 01:24:47.846972 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9697 01:24:47.854271 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9698 01:24:47.857029 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9699 01:24:47.863361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9700 01:24:47.867184 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9701 01:24:47.869970 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9702 01:24:47.876575 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9703 01:24:47.879575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9704 01:24:47.886256 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9705 01:24:47.889289 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9706 01:24:47.895789 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9707 01:24:47.899305 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9708 01:24:47.902658 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9709 01:24:47.909717 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9710 01:24:47.912603 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9711 01:24:47.919413 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9712 01:24:47.922365 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9713 01:24:47.929217 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9714 01:24:47.932300 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9715 01:24:47.935760 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9716 01:24:47.942622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9717 01:24:47.945243 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9718 01:24:47.951980 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9719 01:24:47.954982 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9720 01:24:47.962344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9721 01:24:47.965232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9722 01:24:47.968844 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9723 01:24:47.975233 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9724 01:24:47.978926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9725 01:24:47.981964 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9726 01:24:47.988311 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9727 01:24:47.991841 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9728 01:24:47.994829 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9729 01:24:47.998224 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9730 01:24:48.004742 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9731 01:24:48.008339 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9732 01:24:48.014699 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9733 01:24:48.017866 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9734 01:24:48.021479 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9735 01:24:48.028145 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9736 01:24:48.030831 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9737 01:24:48.038156 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9738 01:24:48.041352 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9739 01:24:48.044212 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9740 01:24:48.051236 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9741 01:24:48.054165 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9742 01:24:48.057569 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9743 01:24:48.063855 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9744 01:24:48.066953 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9745 01:24:48.070571 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9746 01:24:48.076968 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9747 01:24:48.080958 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9748 01:24:48.083523 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9749 01:24:48.090384 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9750 01:24:48.093792 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9751 01:24:48.100766 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9752 01:24:48.103141 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9753 01:24:48.106596 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9754 01:24:48.113504 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9755 01:24:48.116572 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9756 01:24:48.122984 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9757 01:24:48.126046 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9758 01:24:48.129405 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9759 01:24:48.136218 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9760 01:24:48.139618 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9761 01:24:48.142717 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9762 01:24:48.149263 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9763 01:24:48.152828 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9764 01:24:48.156339 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9765 01:24:48.162491 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9766 01:24:48.165856 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9767 01:24:48.169468 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9768 01:24:48.172380 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9769 01:24:48.175763 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9770 01:24:48.182641 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9771 01:24:48.185497 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9772 01:24:48.189341 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9773 01:24:48.195403 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9774 01:24:48.198819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9775 01:24:48.202301 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9776 01:24:48.205775 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9777 01:24:48.212281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9778 01:24:48.215327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9779 01:24:48.222218 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9780 01:24:48.225733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9781 01:24:48.232041 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9782 01:24:48.235425 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9783 01:24:48.238988 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9784 01:24:48.245305 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9785 01:24:48.248666 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9786 01:24:48.255744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9787 01:24:48.258889 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9788 01:24:48.264777 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9789 01:24:48.268087 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9790 01:24:48.271375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9791 01:24:48.278977 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9792 01:24:48.281765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9793 01:24:48.288713 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9794 01:24:48.291260 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9795 01:24:48.294910 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9796 01:24:48.302249 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9797 01:24:48.304698 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9798 01:24:48.311134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9799 01:24:48.314969 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9800 01:24:48.317677 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9801 01:24:48.324177 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9802 01:24:48.327851 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9803 01:24:48.334025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9804 01:24:48.337486 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9805 01:24:48.343955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9806 01:24:48.347253 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9807 01:24:48.353918 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9808 01:24:48.357196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9809 01:24:48.360917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9810 01:24:48.367126 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9811 01:24:48.370227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9812 01:24:48.377554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9813 01:24:48.380511 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9814 01:24:48.383501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9815 01:24:48.390507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9816 01:24:48.393464 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9817 01:24:48.400366 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9818 01:24:48.403538 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9819 01:24:48.406252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9820 01:24:48.412862 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9821 01:24:48.416481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9822 01:24:48.423027 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9823 01:24:48.426296 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9824 01:24:48.429507 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9825 01:24:48.436565 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9826 01:24:48.439781 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9827 01:24:48.445825 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9828 01:24:48.449332 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9829 01:24:48.456254 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9830 01:24:48.459372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9831 01:24:48.465946 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9832 01:24:48.469415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9833 01:24:48.473038 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9834 01:24:48.479862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9835 01:24:48.482873 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9836 01:24:48.489466 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9837 01:24:48.492819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9838 01:24:48.495734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9839 01:24:48.502323 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9840 01:24:48.505905 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9841 01:24:48.512550 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9842 01:24:48.515669 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9843 01:24:48.519571 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9844 01:24:48.525714 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9845 01:24:48.528842 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9846 01:24:48.535340 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9847 01:24:48.538655 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9848 01:24:48.545198 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9849 01:24:48.549109 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9850 01:24:48.552016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9851 01:24:48.558153 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9852 01:24:48.561819 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9853 01:24:48.568280 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9854 01:24:48.571672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9855 01:24:48.578454 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9856 01:24:48.582292 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9857 01:24:48.587836 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9858 01:24:48.591252 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9859 01:24:48.594481 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9860 01:24:48.601001 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9861 01:24:48.604272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9862 01:24:48.610988 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9863 01:24:48.614340 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9864 01:24:48.620979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9865 01:24:48.624017 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9866 01:24:48.631125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9867 01:24:48.634030 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9868 01:24:48.637604 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9869 01:24:48.644557 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9870 01:24:48.647635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9871 01:24:48.654139 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9872 01:24:48.657470 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9873 01:24:48.664385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9874 01:24:48.667497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9875 01:24:48.674394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9876 01:24:48.677226 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9877 01:24:48.681154 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9878 01:24:48.687998 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9879 01:24:48.690802 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9880 01:24:48.697461 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9881 01:24:48.700931 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9882 01:24:48.706972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9883 01:24:48.710527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9884 01:24:48.717662 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9885 01:24:48.720217 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9886 01:24:48.724053 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9887 01:24:48.730297 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9888 01:24:48.733804 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9889 01:24:48.740413 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9890 01:24:48.743880 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9891 01:24:48.750812 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9892 01:24:48.753959 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9893 01:24:48.756692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9894 01:24:48.763405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9895 01:24:48.767374 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9896 01:24:48.773604 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9897 01:24:48.776905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9898 01:24:48.780137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9899 01:24:48.786541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9900 01:24:48.790099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9901 01:24:48.797129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9902 01:24:48.799672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9903 01:24:48.806721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9904 01:24:48.810392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9905 01:24:48.816600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9906 01:24:48.819564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9907 01:24:48.826405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9908 01:24:48.829597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9909 01:24:48.836775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9910 01:24:48.839777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9911 01:24:48.846282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9912 01:24:48.849548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9913 01:24:48.856303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9914 01:24:48.859143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9915 01:24:48.866665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9916 01:24:48.869643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9917 01:24:48.876278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9918 01:24:48.879315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9919 01:24:48.886224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9920 01:24:48.888850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9921 01:24:48.895434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9922 01:24:48.898696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9923 01:24:48.905689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9924 01:24:48.909277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9925 01:24:48.916073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9926 01:24:48.918744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9927 01:24:48.925192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9928 01:24:48.929080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9929 01:24:48.935309 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9930 01:24:48.935882 INFO: [APUAPC] vio 0
9931 01:24:48.942283 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9932 01:24:48.945514 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9933 01:24:48.948218 INFO: [APUAPC] D0_APC_0: 0x400510
9934 01:24:48.951867 INFO: [APUAPC] D0_APC_1: 0x0
9935 01:24:48.955119 INFO: [APUAPC] D0_APC_2: 0x1540
9936 01:24:48.958561 INFO: [APUAPC] D0_APC_3: 0x0
9937 01:24:48.961905 INFO: [APUAPC] D1_APC_0: 0xffffffff
9938 01:24:48.964695 INFO: [APUAPC] D1_APC_1: 0xffffffff
9939 01:24:48.968159 INFO: [APUAPC] D1_APC_2: 0x3fffff
9940 01:24:48.971596 INFO: [APUAPC] D1_APC_3: 0x0
9941 01:24:48.974793 INFO: [APUAPC] D2_APC_0: 0xffffffff
9942 01:24:48.978227 INFO: [APUAPC] D2_APC_1: 0xffffffff
9943 01:24:48.981863 INFO: [APUAPC] D2_APC_2: 0x3fffff
9944 01:24:48.984838 INFO: [APUAPC] D2_APC_3: 0x0
9945 01:24:48.987793 INFO: [APUAPC] D3_APC_0: 0xffffffff
9946 01:24:48.991757 INFO: [APUAPC] D3_APC_1: 0xffffffff
9947 01:24:48.995375 INFO: [APUAPC] D3_APC_2: 0x3fffff
9948 01:24:48.998181 INFO: [APUAPC] D3_APC_3: 0x0
9949 01:24:49.001299 INFO: [APUAPC] D4_APC_0: 0xffffffff
9950 01:24:49.004348 INFO: [APUAPC] D4_APC_1: 0xffffffff
9951 01:24:49.007739 INFO: [APUAPC] D4_APC_2: 0x3fffff
9952 01:24:49.010936 INFO: [APUAPC] D4_APC_3: 0x0
9953 01:24:49.014503 INFO: [APUAPC] D5_APC_0: 0xffffffff
9954 01:24:49.017884 INFO: [APUAPC] D5_APC_1: 0xffffffff
9955 01:24:49.021225 INFO: [APUAPC] D5_APC_2: 0x3fffff
9956 01:24:49.024412 INFO: [APUAPC] D5_APC_3: 0x0
9957 01:24:49.027350 INFO: [APUAPC] D6_APC_0: 0xffffffff
9958 01:24:49.030581 INFO: [APUAPC] D6_APC_1: 0xffffffff
9959 01:24:49.034068 INFO: [APUAPC] D6_APC_2: 0x3fffff
9960 01:24:49.034499 INFO: [APUAPC] D6_APC_3: 0x0
9961 01:24:49.040651 INFO: [APUAPC] D7_APC_0: 0xffffffff
9962 01:24:49.044238 INFO: [APUAPC] D7_APC_1: 0xffffffff
9963 01:24:49.047488 INFO: [APUAPC] D7_APC_2: 0x3fffff
9964 01:24:49.047927 INFO: [APUAPC] D7_APC_3: 0x0
9965 01:24:49.050924 INFO: [APUAPC] D8_APC_0: 0xffffffff
9966 01:24:49.057703 INFO: [APUAPC] D8_APC_1: 0xffffffff
9967 01:24:49.057997 INFO: [APUAPC] D8_APC_2: 0x3fffff
9968 01:24:49.060221 INFO: [APUAPC] D8_APC_3: 0x0
9969 01:24:49.063642 INFO: [APUAPC] D9_APC_0: 0xffffffff
9970 01:24:49.066849 INFO: [APUAPC] D9_APC_1: 0xffffffff
9971 01:24:49.070137 INFO: [APUAPC] D9_APC_2: 0x3fffff
9972 01:24:49.074180 INFO: [APUAPC] D9_APC_3: 0x0
9973 01:24:49.077106 INFO: [APUAPC] D10_APC_0: 0xffffffff
9974 01:24:49.079892 INFO: [APUAPC] D10_APC_1: 0xffffffff
9975 01:24:49.083039 INFO: [APUAPC] D10_APC_2: 0x3fffff
9976 01:24:49.086268 INFO: [APUAPC] D10_APC_3: 0x0
9977 01:24:49.089537 INFO: [APUAPC] D11_APC_0: 0xffffffff
9978 01:24:49.096313 INFO: [APUAPC] D11_APC_1: 0xffffffff
9979 01:24:49.099360 INFO: [APUAPC] D11_APC_2: 0x3fffff
9980 01:24:49.102799 INFO: [APUAPC] D11_APC_3: 0x0
9981 01:24:49.106052 INFO: [APUAPC] D12_APC_0: 0xffffffff
9982 01:24:49.109280 INFO: [APUAPC] D12_APC_1: 0xffffffff
9983 01:24:49.113155 INFO: [APUAPC] D12_APC_2: 0x3fffff
9984 01:24:49.115881 INFO: [APUAPC] D12_APC_3: 0x0
9985 01:24:49.120166 INFO: [APUAPC] D13_APC_0: 0xffffffff
9986 01:24:49.122127 INFO: [APUAPC] D13_APC_1: 0xffffffff
9987 01:24:49.125826 INFO: [APUAPC] D13_APC_2: 0x3fffff
9988 01:24:49.129005 INFO: [APUAPC] D13_APC_3: 0x0
9989 01:24:49.132699 INFO: [APUAPC] D14_APC_0: 0xffffffff
9990 01:24:49.135973 INFO: [APUAPC] D14_APC_1: 0xffffffff
9991 01:24:49.138866 INFO: [APUAPC] D14_APC_2: 0x3fffff
9992 01:24:49.142760 INFO: [APUAPC] D14_APC_3: 0x0
9993 01:24:49.145763 INFO: [APUAPC] D15_APC_0: 0xffffffff
9994 01:24:49.149079 INFO: [APUAPC] D15_APC_1: 0xffffffff
9995 01:24:49.152391 INFO: [APUAPC] D15_APC_2: 0x3fffff
9996 01:24:49.155425 INFO: [APUAPC] D15_APC_3: 0x0
9997 01:24:49.159111 INFO: [APUAPC] APC_CON: 0x4
9998 01:24:49.159318 INFO: [NOCDAPC] D0_APC_0: 0x0
9999 01:24:49.161971 INFO: [NOCDAPC] D0_APC_1: 0x0
10000 01:24:49.165407 INFO: [NOCDAPC] D1_APC_0: 0x0
10001 01:24:49.168548 INFO: [NOCDAPC] D1_APC_1: 0xfff
10002 01:24:49.171718 INFO: [NOCDAPC] D2_APC_0: 0x0
10003 01:24:49.175252 INFO: [NOCDAPC] D2_APC_1: 0xfff
10004 01:24:49.178338 INFO: [NOCDAPC] D3_APC_0: 0x0
10005 01:24:49.182169 INFO: [NOCDAPC] D3_APC_1: 0xfff
10006 01:24:49.185011 INFO: [NOCDAPC] D4_APC_0: 0x0
10007 01:24:49.188453 INFO: [NOCDAPC] D4_APC_1: 0xfff
10008 01:24:49.191772 INFO: [NOCDAPC] D5_APC_0: 0x0
10009 01:24:49.194984 INFO: [NOCDAPC] D5_APC_1: 0xfff
10010 01:24:49.195067 INFO: [NOCDAPC] D6_APC_0: 0x0
10011 01:24:49.198326 INFO: [NOCDAPC] D6_APC_1: 0xfff
10012 01:24:49.201655 INFO: [NOCDAPC] D7_APC_0: 0x0
10013 01:24:49.204870 INFO: [NOCDAPC] D7_APC_1: 0xfff
10014 01:24:49.208164 INFO: [NOCDAPC] D8_APC_0: 0x0
10015 01:24:49.211138 INFO: [NOCDAPC] D8_APC_1: 0xfff
10016 01:24:49.214761 INFO: [NOCDAPC] D9_APC_0: 0x0
10017 01:24:49.217988 INFO: [NOCDAPC] D9_APC_1: 0xfff
10018 01:24:49.221107 INFO: [NOCDAPC] D10_APC_0: 0x0
10019 01:24:49.224595 INFO: [NOCDAPC] D10_APC_1: 0xfff
10020 01:24:49.228073 INFO: [NOCDAPC] D11_APC_0: 0x0
10021 01:24:49.231105 INFO: [NOCDAPC] D11_APC_1: 0xfff
10022 01:24:49.234343 INFO: [NOCDAPC] D12_APC_0: 0x0
10023 01:24:49.234434 INFO: [NOCDAPC] D12_APC_1: 0xfff
10024 01:24:49.237547 INFO: [NOCDAPC] D13_APC_0: 0x0
10025 01:24:49.241139 INFO: [NOCDAPC] D13_APC_1: 0xfff
10026 01:24:49.244048 INFO: [NOCDAPC] D14_APC_0: 0x0
10027 01:24:49.247704 INFO: [NOCDAPC] D14_APC_1: 0xfff
10028 01:24:49.251355 INFO: [NOCDAPC] D15_APC_0: 0x0
10029 01:24:49.254796 INFO: [NOCDAPC] D15_APC_1: 0xfff
10030 01:24:49.257268 INFO: [NOCDAPC] APC_CON: 0x4
10031 01:24:49.260606 INFO: [APUAPC] set_apusys_apc done
10032 01:24:49.264185 INFO: [DEVAPC] devapc_init done
10033 01:24:49.267726 INFO: GICv3 without legacy support detected.
10034 01:24:49.270987 INFO: ARM GICv3 driver initialized in EL3
10035 01:24:49.277996 INFO: Maximum SPI INTID supported: 639
10036 01:24:49.281352 INFO: BL31: Initializing runtime services
10037 01:24:49.287533 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10038 01:24:49.288060 INFO: SPM: enable CPC mode
10039 01:24:49.294625 INFO: mcdi ready for mcusys-off-idle and system suspend
10040 01:24:49.297589 INFO: BL31: Preparing for EL3 exit to normal world
10041 01:24:49.304258 INFO: Entry point address = 0x80000000
10042 01:24:49.304675 INFO: SPSR = 0x8
10043 01:24:49.310195
10044 01:24:49.310705
10045 01:24:49.311114
10046 01:24:49.313473 Starting depthcharge on Spherion...
10047 01:24:49.313885
10048 01:24:49.314211 Wipe memory regions:
10049 01:24:49.314516
10050 01:24:49.317028 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10051 01:24:49.317607 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10052 01:24:49.319138 Setting prompt string to ['asurada:']
10053 01:24:49.319627 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10054 01:24:49.320435 [0x00000040000000, 0x00000054600000)
10055 01:24:49.438421
10056 01:24:49.438661 [0x00000054660000, 0x00000080000000)
10057 01:24:49.699674
10058 01:24:49.700278 [0x000000821a7280, 0x000000ffe64000)
10059 01:24:50.444757
10060 01:24:50.445347 [0x00000100000000, 0x00000240000000)
10061 01:24:52.335654
10062 01:24:52.337999 Initializing XHCI USB controller at 0x11200000.
10063 01:24:53.376274
10064 01:24:53.379187 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10065 01:24:53.379675
10066 01:24:53.380119
10067 01:24:53.380470
10068 01:24:53.381271 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 01:24:53.482522 asurada: tftpboot 192.168.201.1 11368520/tftp-deploy-fcn7bodx/kernel/image.itb 11368520/tftp-deploy-fcn7bodx/kernel/cmdline
10071 01:24:53.483166 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 01:24:53.483697 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10073 01:24:53.488464 tftpboot 192.168.201.1 11368520/tftp-deploy-fcn7bodx/kernel/image.ittp-deploy-fcn7bodx/kernel/cmdline
10074 01:24:53.488924
10075 01:24:53.489281 Waiting for link
10076 01:24:53.648849
10077 01:24:53.649402 R8152: Initializing
10078 01:24:53.649764
10079 01:24:53.652217 Version 6 (ocp_data = 5c30)
10080 01:24:53.652766
10081 01:24:53.656282 R8152: Done initializing
10082 01:24:53.656830
10083 01:24:53.657191 Adding net device
10084 01:24:55.522965
10085 01:24:55.523331 done.
10086 01:24:55.523559
10087 01:24:55.523760 MAC: 00:24:32:30:7c:7b
10088 01:24:55.523981
10089 01:24:55.526918 Sending DHCP discover... done.
10090 01:24:55.527372
10091 01:24:58.614938 Waiting for reply... done.
10092 01:24:58.615577
10093 01:24:58.618230 Sending DHCP request... done.
10094 01:24:58.618680
10095 01:24:58.619033 Waiting for reply... done.
10096 01:24:58.619390
10097 01:24:58.621691 My ip is 192.168.201.14
10098 01:24:58.622249
10099 01:24:58.624265 The DHCP server ip is 192.168.201.1
10100 01:24:58.624723
10101 01:24:58.628117 TFTP server IP predefined by user: 192.168.201.1
10102 01:24:58.628613
10103 01:24:58.634651 Bootfile predefined by user: 11368520/tftp-deploy-fcn7bodx/kernel/image.itb
10104 01:24:58.635213
10105 01:24:58.638214 Sending tftp read request... done.
10106 01:24:58.638782
10107 01:24:58.647156 Waiting for the transfer...
10108 01:24:58.647717
10109 01:24:59.299585 00000000 ################################################################
10110 01:24:59.299777
10111 01:24:59.889335 00080000 ################################################################
10112 01:24:59.889482
10113 01:25:00.450621 00100000 ################################################################
10114 01:25:00.450760
10115 01:25:01.016162 00180000 ################################################################
10116 01:25:01.016313
10117 01:25:01.590414 00200000 ################################################################
10118 01:25:01.590547
10119 01:25:02.209066 00280000 ################################################################
10120 01:25:02.209201
10121 01:25:02.828637 00300000 ################################################################
10122 01:25:02.828772
10123 01:25:03.378173 00380000 ################################################################
10124 01:25:03.378311
10125 01:25:03.917542 00400000 ################################################################
10126 01:25:03.917697
10127 01:25:04.461329 00480000 ################################################################
10128 01:25:04.461483
10129 01:25:04.996314 00500000 ################################################################
10130 01:25:04.996467
10131 01:25:05.539869 00580000 ################################################################
10132 01:25:05.540044
10133 01:25:06.162724 00600000 ################################################################
10134 01:25:06.162855
10135 01:25:06.749631 00680000 ################################################################
10136 01:25:06.749765
10137 01:25:07.316942 00700000 ################################################################
10138 01:25:07.317078
10139 01:25:07.872745 00780000 ################################################################
10140 01:25:07.872874
10141 01:25:08.422876 00800000 ################################################################
10142 01:25:08.423004
10143 01:25:09.021976 00880000 ################################################################
10144 01:25:09.022108
10145 01:25:09.575163 00900000 ################################################################
10146 01:25:09.575296
10147 01:25:10.149522 00980000 ################################################################
10148 01:25:10.149655
10149 01:25:10.731541 00a00000 ################################################################
10150 01:25:10.731674
10151 01:25:11.306964 00a80000 ################################################################
10152 01:25:11.307097
10153 01:25:11.871104 00b00000 ################################################################
10154 01:25:11.871236
10155 01:25:12.458148 00b80000 ################################################################
10156 01:25:12.458281
10157 01:25:13.029003 00c00000 ################################################################
10158 01:25:13.029160
10159 01:25:13.606049 00c80000 ################################################################
10160 01:25:13.606181
10161 01:25:14.160620 00d00000 ################################################################
10162 01:25:14.160753
10163 01:25:14.733455 00d80000 ################################################################
10164 01:25:14.733589
10165 01:25:15.306854 00e00000 ################################################################
10166 01:25:15.306987
10167 01:25:15.895755 00e80000 ################################################################
10168 01:25:15.895888
10169 01:25:16.481982 00f00000 ################################################################
10170 01:25:16.482115
10171 01:25:17.086662 00f80000 ################################################################
10172 01:25:17.086793
10173 01:25:17.715981 01000000 ################################################################
10174 01:25:17.716108
10175 01:25:18.339653 01080000 ################################################################
10176 01:25:18.339790
10177 01:25:18.956704 01100000 ################################################################
10178 01:25:18.956838
10179 01:25:19.566710 01180000 ################################################################
10180 01:25:19.566841
10181 01:25:20.163377 01200000 ################################################################
10182 01:25:20.163514
10183 01:25:20.804148 01280000 ################################################################
10184 01:25:20.804280
10185 01:25:21.436153 01300000 ################################################################
10186 01:25:21.436316
10187 01:25:22.032077 01380000 ################################################################
10188 01:25:22.032209
10189 01:25:22.655801 01400000 ################################################################
10190 01:25:22.656339
10191 01:25:23.344571 01480000 ################################################################
10192 01:25:23.345073
10193 01:25:23.953220 01500000 ################################################################
10194 01:25:23.953368
10195 01:25:24.610764 01580000 ################################################################
10196 01:25:24.611276
10197 01:25:25.278889 01600000 ################################################################
10198 01:25:25.279401
10199 01:25:25.968723 01680000 ################################################################
10200 01:25:25.969253
10201 01:25:26.657764 01700000 ################################################################
10202 01:25:26.658334
10203 01:25:27.347105 01780000 ################################################################
10204 01:25:27.347611
10205 01:25:28.030629 01800000 ################################################################
10206 01:25:28.031138
10207 01:25:28.719218 01880000 ################################################################
10208 01:25:28.719733
10209 01:25:29.396416 01900000 ################################################################
10210 01:25:29.396925
10211 01:25:30.084642 01980000 ################################################################
10212 01:25:30.085144
10213 01:25:30.766064 01a00000 ################################################################
10214 01:25:30.766563
10215 01:25:31.439271 01a80000 ################################################################
10216 01:25:31.439773
10217 01:25:32.128461 01b00000 ################################################################
10218 01:25:32.129110
10219 01:25:32.151395 01b80000 ### done.
10220 01:25:32.151817
10221 01:25:32.154484 The bootfile was 28854214 bytes long.
10222 01:25:32.154897
10223 01:25:32.157710 Sending tftp read request... done.
10224 01:25:32.158121
10225 01:25:32.160944 Waiting for the transfer...
10226 01:25:32.161361
10227 01:25:32.164647 00000000 # done.
10228 01:25:32.165069
10229 01:25:32.170931 Command line loaded dynamically from TFTP file: 11368520/tftp-deploy-fcn7bodx/kernel/cmdline
10230 01:25:32.171449
10231 01:25:32.194411 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10232 01:25:32.194954
10233 01:25:32.195293 Loading FIT.
10234 01:25:32.195604
10235 01:25:32.197788 Image ramdisk-1 has 17766234 bytes.
10236 01:25:32.198306
10237 01:25:32.201042 Image fdt-1 has 47278 bytes.
10238 01:25:32.201457
10239 01:25:32.204017 Image kernel-1 has 11038667 bytes.
10240 01:25:32.204539
10241 01:25:32.213719 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10242 01:25:32.214217
10243 01:25:32.230378 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10244 01:25:32.230901
10245 01:25:32.237207 Choosing best match conf-1 for compat google,spherion-rev2.
10246 01:25:32.237768
10247 01:25:32.244536 Connected to device vid:did:rid of 1ae0:0028:00
10248 01:25:32.252884
10249 01:25:32.255578 tpm_get_response: command 0x17b, return code 0x0
10250 01:25:32.256039
10251 01:25:32.262344 ec_init: CrosEC protocol v3 supported (256, 248)
10252 01:25:32.262758
10253 01:25:32.266598 tpm_cleanup: add release locality here.
10254 01:25:32.267117
10255 01:25:32.268822 Shutting down all USB controllers.
10256 01:25:32.269236
10257 01:25:32.272244 Removing current net device
10258 01:25:32.272658
10259 01:25:32.275575 Exiting depthcharge with code 4 at timestamp: 72219262
10260 01:25:32.276030
10261 01:25:32.279284 LZMA decompressing kernel-1 to 0x821a6718
10262 01:25:32.282825
10263 01:25:32.285579 LZMA decompressing kernel-1 to 0x40000000
10264 01:25:33.673359
10265 01:25:33.673916 jumping to kernel
10266 01:25:33.675369 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10267 01:25:33.675889 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10268 01:25:33.676343 Setting prompt string to ['Linux version [0-9]']
10269 01:25:33.676716 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10270 01:25:33.677083 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10271 01:25:33.753754
10272 01:25:33.757259 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10273 01:25:33.762153 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10274 01:25:33.762724 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10275 01:25:33.763118 Setting prompt string to []
10276 01:25:33.763529 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10277 01:25:33.764020 Using line separator: #'\n'#
10278 01:25:33.764368 No login prompt set.
10279 01:25:33.764714 Parsing kernel messages
10280 01:25:33.765026 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10281 01:25:33.765573 [login-action] Waiting for messages, (timeout 00:03:41)
10282 01:25:33.780102 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j24548-arm64-gcc-10-defconfig-arm64-chromebook-xnj4p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023
10283 01:25:33.783458 [ 0.000000] random: crng init done
10284 01:25:33.789724 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10285 01:25:33.793878 [ 0.000000] efi: UEFI not found.
10286 01:25:33.799825 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10287 01:25:33.807184 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10288 01:25:33.816188 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10289 01:25:33.826480 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10290 01:25:33.833053 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10291 01:25:33.839943 [ 0.000000] printk: bootconsole [mtk8250] enabled
10292 01:25:33.846480 [ 0.000000] NUMA: No NUMA configuration found
10293 01:25:33.852543 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10294 01:25:33.856603 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10295 01:25:33.859885 [ 0.000000] Zone ranges:
10296 01:25:33.865743 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10297 01:25:33.869802 [ 0.000000] DMA32 empty
10298 01:25:33.875822 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10299 01:25:33.879218 [ 0.000000] Movable zone start for each node
10300 01:25:33.882281 [ 0.000000] Early memory node ranges
10301 01:25:33.888586 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10302 01:25:33.896012 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10303 01:25:33.902412 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10304 01:25:33.908534 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10305 01:25:33.915414 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10306 01:25:33.922110 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10307 01:25:33.978585 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10308 01:25:33.984636 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10309 01:25:33.991347 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10310 01:25:33.994778 [ 0.000000] psci: probing for conduit method from DT.
10311 01:25:34.001201 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10312 01:25:34.004839 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10313 01:25:34.011287 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10314 01:25:34.014664 [ 0.000000] psci: SMC Calling Convention v1.2
10315 01:25:34.021261 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10316 01:25:34.024557 [ 0.000000] Detected VIPT I-cache on CPU0
10317 01:25:34.031162 [ 0.000000] CPU features: detected: GIC system register CPU interface
10318 01:25:34.037545 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10319 01:25:34.044392 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10320 01:25:34.050666 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10321 01:25:34.060718 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10322 01:25:34.067595 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10323 01:25:34.071831 [ 0.000000] alternatives: applying boot alternatives
10324 01:25:34.077116 [ 0.000000] Fallback order for Node 0: 0
10325 01:25:34.084115 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10326 01:25:34.089099 [ 0.000000] Policy zone: Normal
10327 01:25:34.110108 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10328 01:25:34.120073 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10329 01:25:34.131414 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10330 01:25:34.141004 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10331 01:25:34.148756 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10332 01:25:34.150595 <6>[ 0.000000] software IO TLB: area num 8.
10333 01:25:34.207486 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10334 01:25:34.357273 <6>[ 0.000000] Memory: 7952204K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 400564K reserved, 32768K cma-reserved)
10335 01:25:34.363782 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10336 01:25:34.370298 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10337 01:25:34.373678 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10338 01:25:34.380154 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10339 01:25:34.386487 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10340 01:25:34.389496 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10341 01:25:34.399621 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10342 01:25:34.406450 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10343 01:25:34.413180 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10344 01:25:34.419703 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10345 01:25:34.423175 <6>[ 0.000000] GICv3: 608 SPIs implemented
10346 01:25:34.425825 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10347 01:25:34.432680 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10348 01:25:34.436103 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10349 01:25:34.442516 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10350 01:25:34.456188 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10351 01:25:34.469335 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10352 01:25:34.475957 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10353 01:25:34.483620 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10354 01:25:34.496909 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10355 01:25:34.504087 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10356 01:25:34.510724 <6>[ 0.009185] Console: colour dummy device 80x25
10357 01:25:34.519575 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10358 01:25:34.527702 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10359 01:25:34.530813 <6>[ 0.029226] LSM: Security Framework initializing
10360 01:25:34.536067 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10361 01:25:34.546427 <6>[ 0.041976] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10362 01:25:34.556788 <6>[ 0.051403] cblist_init_generic: Setting adjustable number of callback queues.
10363 01:25:34.559114 <6>[ 0.058895] cblist_init_generic: Setting shift to 3 and lim to 1.
10364 01:25:34.570124 <6>[ 0.065234] cblist_init_generic: Setting adjustable number of callback queues.
10365 01:25:34.575720 <6>[ 0.072659] cblist_init_generic: Setting shift to 3 and lim to 1.
10366 01:25:34.580110 <6>[ 0.079058] rcu: Hierarchical SRCU implementation.
10367 01:25:34.586217 <6>[ 0.084102] rcu: Max phase no-delay instances is 1000.
10368 01:25:34.592711 <6>[ 0.091137] EFI services will not be available.
10369 01:25:34.595691 <6>[ 0.096141] smp: Bringing up secondary CPUs ...
10370 01:25:34.604751 <6>[ 0.101194] Detected VIPT I-cache on CPU1
10371 01:25:34.611272 <6>[ 0.101264] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10372 01:25:34.617409 <6>[ 0.101295] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10373 01:25:34.620839 <6>[ 0.101641] Detected VIPT I-cache on CPU2
10374 01:25:34.628000 <6>[ 0.101693] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10375 01:25:34.637546 <6>[ 0.101711] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10376 01:25:34.641089 <6>[ 0.101975] Detected VIPT I-cache on CPU3
10377 01:25:34.647755 <6>[ 0.102020] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10378 01:25:34.653933 <6>[ 0.102034] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10379 01:25:34.656704 <6>[ 0.102341] CPU features: detected: Spectre-v4
10380 01:25:34.664241 <6>[ 0.102348] CPU features: detected: Spectre-BHB
10381 01:25:34.666753 <6>[ 0.102352] Detected PIPT I-cache on CPU4
10382 01:25:34.674574 <6>[ 0.102402] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10383 01:25:34.680171 <6>[ 0.102418] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10384 01:25:34.686547 <6>[ 0.102696] Detected PIPT I-cache on CPU5
10385 01:25:34.693725 <6>[ 0.102751] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10386 01:25:34.700341 <6>[ 0.102767] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10387 01:25:34.703345 <6>[ 0.103049] Detected PIPT I-cache on CPU6
10388 01:25:34.709983 <6>[ 0.103112] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10389 01:25:34.716672 <6>[ 0.103129] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10390 01:25:34.724061 <6>[ 0.103431] Detected PIPT I-cache on CPU7
10391 01:25:34.729822 <6>[ 0.103496] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10392 01:25:34.736261 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10393 01:25:34.739699 <6>[ 0.103561] smp: Brought up 1 node, 8 CPUs
10394 01:25:34.745969 <6>[ 0.244789] SMP: Total of 8 processors activated.
10395 01:25:34.749805 <6>[ 0.249710] CPU features: detected: 32-bit EL0 Support
10396 01:25:34.759646 <6>[ 0.255073] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10397 01:25:34.765469 <6>[ 0.263927] CPU features: detected: Common not Private translations
10398 01:25:34.773019 <6>[ 0.270402] CPU features: detected: CRC32 instructions
10399 01:25:34.779102 <6>[ 0.275754] CPU features: detected: RCpc load-acquire (LDAPR)
10400 01:25:34.782198 <6>[ 0.281713] CPU features: detected: LSE atomic instructions
10401 01:25:34.788676 <6>[ 0.287530] CPU features: detected: Privileged Access Never
10402 01:25:34.795172 <6>[ 0.293309] CPU features: detected: RAS Extension Support
10403 01:25:34.803224 <6>[ 0.298918] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10404 01:25:34.805651 <6>[ 0.306141] CPU: All CPU(s) started at EL2
10405 01:25:34.812219 <6>[ 0.310457] alternatives: applying system-wide alternatives
10406 01:25:34.822692 <6>[ 0.321168] devtmpfs: initialized
10407 01:25:34.837892 <6>[ 0.330166] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10408 01:25:34.844691 <6>[ 0.340128] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10409 01:25:34.851535 <6>[ 0.348140] pinctrl core: initialized pinctrl subsystem
10410 01:25:34.853787 <6>[ 0.354771] DMI not present or invalid.
10411 01:25:34.860149 <6>[ 0.359184] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10412 01:25:34.869903 <6>[ 0.366046] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10413 01:25:34.876914 <6>[ 0.373630] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10414 01:25:34.886986 <6>[ 0.381842] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10415 01:25:34.890303 <6>[ 0.390086] audit: initializing netlink subsys (disabled)
10416 01:25:34.900672 <5>[ 0.395781] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10417 01:25:34.906591 <6>[ 0.396479] thermal_sys: Registered thermal governor 'step_wise'
10418 01:25:34.914295 <6>[ 0.403749] thermal_sys: Registered thermal governor 'power_allocator'
10419 01:25:34.916612 <6>[ 0.410005] cpuidle: using governor menu
10420 01:25:34.923511 <6>[ 0.420964] NET: Registered PF_QIPCRTR protocol family
10421 01:25:34.929645 <6>[ 0.426455] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10422 01:25:34.935939 <6>[ 0.433560] ASID allocator initialised with 32768 entries
10423 01:25:34.939607 <6>[ 0.440128] Serial: AMBA PL011 UART driver
10424 01:25:34.949763 <4>[ 0.448846] Trying to register duplicate clock ID: 134
10425 01:25:35.004202 <6>[ 0.506278] KASLR enabled
10426 01:25:35.017913 <6>[ 0.514045] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10427 01:25:35.024822 <6>[ 0.521060] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10428 01:25:35.031154 <6>[ 0.527550] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10429 01:25:35.037900 <6>[ 0.534554] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10430 01:25:35.044625 <6>[ 0.541043] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10431 01:25:35.051198 <6>[ 0.548045] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10432 01:25:35.057655 <6>[ 0.554530] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10433 01:25:35.064071 <6>[ 0.561536] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10434 01:25:35.067155 <6>[ 0.569033] ACPI: Interpreter disabled.
10435 01:25:35.076247 <6>[ 0.575441] iommu: Default domain type: Translated
10436 01:25:35.082770 <6>[ 0.580552] iommu: DMA domain TLB invalidation policy: strict mode
10437 01:25:35.085667 <5>[ 0.587205] SCSI subsystem initialized
10438 01:25:35.092324 <6>[ 0.591370] usbcore: registered new interface driver usbfs
10439 01:25:35.098874 <6>[ 0.597103] usbcore: registered new interface driver hub
10440 01:25:35.103420 <6>[ 0.602654] usbcore: registered new device driver usb
10441 01:25:35.109083 <6>[ 0.608742] pps_core: LinuxPPS API ver. 1 registered
10442 01:25:35.119272 <6>[ 0.613938] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10443 01:25:35.122291 <6>[ 0.623286] PTP clock support registered
10444 01:25:35.125632 <6>[ 0.627530] EDAC MC: Ver: 3.0.0
10445 01:25:35.133359 <6>[ 0.632680] FPGA manager framework
10446 01:25:35.140152 <6>[ 0.636360] Advanced Linux Sound Architecture Driver Initialized.
10447 01:25:35.143832 <6>[ 0.643133] vgaarb: loaded
10448 01:25:35.149898 <6>[ 0.646316] clocksource: Switched to clocksource arch_sys_counter
10449 01:25:35.152921 <5>[ 0.652756] VFS: Disk quotas dquot_6.6.0
10450 01:25:35.159530 <6>[ 0.656948] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10451 01:25:35.162860 <6>[ 0.664132] pnp: PnP ACPI: disabled
10452 01:25:35.171354 <6>[ 0.670865] NET: Registered PF_INET protocol family
10453 01:25:35.181607 <6>[ 0.676473] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10454 01:25:35.193290 <6>[ 0.688778] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10455 01:25:35.202389 <6>[ 0.697594] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10456 01:25:35.208832 <6>[ 0.705567] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10457 01:25:35.218984 <6>[ 0.714268] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10458 01:25:35.226067 <6>[ 0.723983] TCP: Hash tables configured (established 65536 bind 65536)
10459 01:25:35.232308 <6>[ 0.730844] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10460 01:25:35.241913 <6>[ 0.738043] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10461 01:25:35.248715 <6>[ 0.745748] NET: Registered PF_UNIX/PF_LOCAL protocol family
10462 01:25:35.255473 <6>[ 0.751901] RPC: Registered named UNIX socket transport module.
10463 01:25:35.258754 <6>[ 0.758057] RPC: Registered udp transport module.
10464 01:25:35.265442 <6>[ 0.762988] RPC: Registered tcp transport module.
10465 01:25:35.271781 <6>[ 0.767920] RPC: Registered tcp NFSv4.1 backchannel transport module.
10466 01:25:35.275295 <6>[ 0.774583] PCI: CLS 0 bytes, default 64
10467 01:25:35.278640 <6>[ 0.778944] Unpacking initramfs...
10468 01:25:35.288313 <6>[ 0.783041] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10469 01:25:35.295175 <6>[ 0.791681] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10470 01:25:35.301460 <6>[ 0.800522] kvm [1]: IPA Size Limit: 40 bits
10471 01:25:35.304978 <6>[ 0.805051] kvm [1]: GICv3: no GICV resource entry
10472 01:25:35.311754 <6>[ 0.810072] kvm [1]: disabling GICv2 emulation
10473 01:25:35.317923 <6>[ 0.814757] kvm [1]: GIC system register CPU interface enabled
10474 01:25:35.320969 <6>[ 0.820937] kvm [1]: vgic interrupt IRQ18
10475 01:25:35.328239 <6>[ 0.826378] kvm [1]: VHE mode initialized successfully
10476 01:25:35.334937 <5>[ 0.832774] Initialise system trusted keyrings
10477 01:25:35.341226 <6>[ 0.837592] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10478 01:25:35.348348 <6>[ 0.847676] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10479 01:25:35.354823 <5>[ 0.854075] NFS: Registering the id_resolver key type
10480 01:25:35.358137 <5>[ 0.859383] Key type id_resolver registered
10481 01:25:35.364643 <5>[ 0.863797] Key type id_legacy registered
10482 01:25:35.371156 <6>[ 0.868076] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10483 01:25:35.377752 <6>[ 0.874999] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10484 01:25:35.384531 <6>[ 0.882717] 9p: Installing v9fs 9p2000 file system support
10485 01:25:35.420944 <5>[ 0.920253] Key type asymmetric registered
10486 01:25:35.423953 <5>[ 0.924586] Asymmetric key parser 'x509' registered
10487 01:25:35.433890 <6>[ 0.929731] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10488 01:25:35.437328 <6>[ 0.937346] io scheduler mq-deadline registered
10489 01:25:35.441183 <6>[ 0.942105] io scheduler kyber registered
10490 01:25:35.460893 <6>[ 0.959119] EINJ: ACPI disabled.
10491 01:25:35.491656 <4>[ 0.984613] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10492 01:25:35.501440 <4>[ 0.995240] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10493 01:25:35.517545 <6>[ 1.016374] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10494 01:25:35.525258 <6>[ 1.024328] printk: console [ttyS0] disabled
10495 01:25:35.553126 <6>[ 1.048973] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10496 01:25:35.559590 <6>[ 1.058467] printk: console [ttyS0] enabled
10497 01:25:35.562797 <6>[ 1.058467] printk: console [ttyS0] enabled
10498 01:25:35.569315 <6>[ 1.067362] printk: bootconsole [mtk8250] disabled
10499 01:25:35.572764 <6>[ 1.067362] printk: bootconsole [mtk8250] disabled
10500 01:25:35.579525 <6>[ 1.078623] SuperH (H)SCI(F) driver initialized
10501 01:25:35.582679 <6>[ 1.083892] msm_serial: driver initialized
10502 01:25:35.596706 <6>[ 1.092912] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10503 01:25:35.607120 <6>[ 1.101462] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10504 01:25:35.613981 <6>[ 1.110005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10505 01:25:35.623012 <6>[ 1.118636] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10506 01:25:35.633274 <6>[ 1.127342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10507 01:25:35.639891 <6>[ 1.136056] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10508 01:25:35.649624 <6>[ 1.144603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10509 01:25:35.656495 <6>[ 1.153413] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10510 01:25:35.666099 <6>[ 1.161958] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10511 01:25:35.678698 <6>[ 1.177608] loop: module loaded
10512 01:25:35.684549 <6>[ 1.183585] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10513 01:25:35.707653 <4>[ 1.207106] mtk-pmic-keys: Failed to locate of_node [id: -1]
10514 01:25:35.715339 <6>[ 1.214109] megasas: 07.719.03.00-rc1
10515 01:25:35.724331 <6>[ 1.223768] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10516 01:25:35.734374 <6>[ 1.233699] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10517 01:25:35.751164 <6>[ 1.250372] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10518 01:25:35.807587 <6>[ 1.300445] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10519 01:25:36.022984 <6>[ 1.522254] Freeing initrd memory: 17348K
10520 01:25:36.033610 <6>[ 1.532691] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10521 01:25:36.044284 <6>[ 1.543820] tun: Universal TUN/TAP device driver, 1.6
10522 01:25:36.048730 <6>[ 1.549900] thunder_xcv, ver 1.0
10523 01:25:36.050704 <6>[ 1.553404] thunder_bgx, ver 1.0
10524 01:25:36.054341 <6>[ 1.556899] nicpf, ver 1.0
10525 01:25:36.065051 <6>[ 1.560912] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10526 01:25:36.068007 <6>[ 1.568388] hns3: Copyright (c) 2017 Huawei Corporation.
10527 01:25:36.075122 <6>[ 1.573981] hclge is initializing
10528 01:25:36.078112 <6>[ 1.577559] e1000: Intel(R) PRO/1000 Network Driver
10529 01:25:36.084630 <6>[ 1.582689] e1000: Copyright (c) 1999-2006 Intel Corporation.
10530 01:25:36.088078 <6>[ 1.588702] e1000e: Intel(R) PRO/1000 Network Driver
10531 01:25:36.094661 <6>[ 1.593917] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10532 01:25:36.102345 <6>[ 1.600105] igb: Intel(R) Gigabit Ethernet Network Driver
10533 01:25:36.107990 <6>[ 1.605754] igb: Copyright (c) 2007-2014 Intel Corporation.
10534 01:25:36.114563 <6>[ 1.611591] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10535 01:25:36.121295 <6>[ 1.618108] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10536 01:25:36.124284 <6>[ 1.624573] sky2: driver version 1.30
10537 01:25:36.130724 <6>[ 1.629567] VFIO - User Level meta-driver version: 0.3
10538 01:25:36.138330 <6>[ 1.637824] usbcore: registered new interface driver usb-storage
10539 01:25:36.145105 <6>[ 1.644273] usbcore: registered new device driver onboard-usb-hub
10540 01:25:36.153878 <6>[ 1.653402] mt6397-rtc mt6359-rtc: registered as rtc0
10541 01:25:36.164500 <6>[ 1.658869] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T01:25:36 UTC (1693185936)
10542 01:25:36.166809 <6>[ 1.668436] i2c_dev: i2c /dev entries driver
10543 01:25:36.184147 <6>[ 1.680281] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10544 01:25:36.203685 <6>[ 1.703292] cpu cpu0: EM: created perf domain
10545 01:25:36.207571 <6>[ 1.708390] cpu cpu4: EM: created perf domain
10546 01:25:36.214155 <6>[ 1.714050] sdhci: Secure Digital Host Controller Interface driver
10547 01:25:36.221003 <6>[ 1.720483] sdhci: Copyright(c) Pierre Ossman
10548 01:25:36.227635 <6>[ 1.725441] Synopsys Designware Multimedia Card Interface Driver
10549 01:25:36.234129 <6>[ 1.732076] sdhci-pltfm: SDHCI platform and OF driver helper
10550 01:25:36.237446 <6>[ 1.732159] mmc0: CQHCI version 5.10
10551 01:25:36.244018 <6>[ 1.742451] ledtrig-cpu: registered to indicate activity on CPUs
10552 01:25:36.251251 <6>[ 1.749509] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10553 01:25:36.257758 <6>[ 1.756565] usbcore: registered new interface driver usbhid
10554 01:25:36.260878 <6>[ 1.762387] usbhid: USB HID core driver
10555 01:25:36.267278 <6>[ 1.766590] spi_master spi0: will run message pump with realtime priority
10556 01:25:36.310537 <6>[ 1.803253] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10557 01:25:36.330006 <6>[ 1.819052] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10558 01:25:36.332383 <6>[ 1.833847] mmc0: Command Queue Engine enabled
10559 01:25:36.339611 <6>[ 1.838602] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10560 01:25:36.346292 <6>[ 1.845337] cros-ec-spi spi0.0: Chrome EC device registered
10561 01:25:36.352573 <6>[ 1.845637] mmcblk0: mmc0:0001 DA4128 116 GiB
10562 01:25:36.360126 <6>[ 1.859774] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10563 01:25:36.368265 <6>[ 1.867044] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10564 01:25:36.374420 <6>[ 1.872912] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10565 01:25:36.380561 <6>[ 1.878842] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10566 01:25:36.396645 <6>[ 1.892771] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10567 01:25:36.404451 <6>[ 1.903495] NET: Registered PF_PACKET protocol family
10568 01:25:36.407893 <6>[ 1.908897] 9pnet: Installing 9P2000 support
10569 01:25:36.414056 <5>[ 1.913466] Key type dns_resolver registered
10570 01:25:36.417192 <6>[ 1.918479] registered taskstats version 1
10571 01:25:36.423977 <5>[ 1.922867] Loading compiled-in X.509 certificates
10572 01:25:36.454006 <4>[ 1.946754] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 01:25:36.463843 <4>[ 1.957604] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 01:25:36.470803 <3>[ 1.968141] debugfs: File 'uA_load' in directory '/' already present!
10575 01:25:36.477724 <3>[ 1.974848] debugfs: File 'min_uV' in directory '/' already present!
10576 01:25:36.483818 <3>[ 1.981457] debugfs: File 'max_uV' in directory '/' already present!
10577 01:25:36.489975 <3>[ 1.988064] debugfs: File 'constraint_flags' in directory '/' already present!
10578 01:25:36.501638 <3>[ 1.997772] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10579 01:25:36.515366 <6>[ 2.014851] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10580 01:25:36.522476 <6>[ 2.021699] xhci-mtk 11200000.usb: xHCI Host Controller
10581 01:25:36.528650 <6>[ 2.027234] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10582 01:25:36.539010 <6>[ 2.035113] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10583 01:25:36.545590 <6>[ 2.044552] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10584 01:25:36.552424 <6>[ 2.050657] xhci-mtk 11200000.usb: xHCI Host Controller
10585 01:25:36.559049 <6>[ 2.056145] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10586 01:25:36.565452 <6>[ 2.063799] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10587 01:25:36.572738 <6>[ 2.071732] hub 1-0:1.0: USB hub found
10588 01:25:36.575476 <6>[ 2.075757] hub 1-0:1.0: 1 port detected
10589 01:25:36.585277 <6>[ 2.080053] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10590 01:25:36.588829 <6>[ 2.088865] hub 2-0:1.0: USB hub found
10591 01:25:36.591737 <6>[ 2.092894] hub 2-0:1.0: 1 port detected
10592 01:25:36.601930 <6>[ 2.101023] mtk-msdc 11f70000.mmc: Got CD GPIO
10593 01:25:36.613500 <6>[ 2.109410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10594 01:25:36.619853 <6>[ 2.117446] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10595 01:25:36.630353 <4>[ 2.125368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10596 01:25:36.639996 <6>[ 2.134927] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10597 01:25:36.646194 <6>[ 2.143005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10598 01:25:36.653134 <6>[ 2.151020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10599 01:25:36.662958 <6>[ 2.158940] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10600 01:25:36.670032 <6>[ 2.166757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10601 01:25:36.679182 <6>[ 2.174574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10602 01:25:36.688936 <6>[ 2.184981] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10603 01:25:36.696052 <6>[ 2.193349] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10604 01:25:36.705688 <6>[ 2.201693] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10605 01:25:36.712898 <6>[ 2.210031] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10606 01:25:36.722675 <6>[ 2.218369] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10607 01:25:36.728650 <6>[ 2.226713] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10608 01:25:36.738740 <6>[ 2.235052] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10609 01:25:36.748907 <6>[ 2.243390] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10610 01:25:36.755316 <6>[ 2.251737] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10611 01:25:36.765086 <6>[ 2.260076] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10612 01:25:36.771630 <6>[ 2.268413] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10613 01:25:36.781776 <6>[ 2.276751] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10614 01:25:36.788648 <6>[ 2.285089] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10615 01:25:36.798334 <6>[ 2.293427] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10616 01:25:36.805084 <6>[ 2.301765] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10617 01:25:36.811782 <6>[ 2.310566] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10618 01:25:36.818471 <6>[ 2.317748] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10619 01:25:36.825808 <6>[ 2.324510] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10620 01:25:36.834764 <6>[ 2.331267] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10621 01:25:36.841459 <6>[ 2.338203] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10622 01:25:36.847940 <6>[ 2.345075] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10623 01:25:36.858333 <6>[ 2.354213] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10624 01:25:36.868337 <6>[ 2.363332] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10625 01:25:36.877754 <6>[ 2.372625] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10626 01:25:36.887247 <6>[ 2.382093] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10627 01:25:36.895300 <6>[ 2.391561] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10628 01:25:36.904523 <6>[ 2.400682] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10629 01:25:36.914023 <6>[ 2.410151] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10630 01:25:36.924023 <6>[ 2.419270] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10631 01:25:36.934993 <6>[ 2.428566] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10632 01:25:36.944522 <6>[ 2.438726] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10633 01:25:36.954031 <6>[ 2.450247] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10634 01:25:36.960713 <6>[ 2.460113] Trying to probe devices needed for running init ...
10635 01:25:36.984184 <6>[ 2.478822] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10636 01:25:37.010681 <6>[ 2.509961] hub 2-1:1.0: USB hub found
10637 01:25:37.013571 <6>[ 2.514424] hub 2-1:1.0: 3 ports detected
10638 01:25:37.134128 <6>[ 2.630583] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10639 01:25:37.289338 <6>[ 2.788701] hub 1-1:1.0: USB hub found
10640 01:25:37.292680 <6>[ 2.793179] hub 1-1:1.0: 4 ports detected
10641 01:25:37.367198 <6>[ 2.862892] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10642 01:25:37.614295 <6>[ 3.110637] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10643 01:25:37.747379 <6>[ 3.246650] hub 1-1.4:1.0: USB hub found
10644 01:25:37.751395 <6>[ 3.251322] hub 1-1.4:1.0: 2 ports detected
10645 01:25:38.046142 <6>[ 3.542577] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10646 01:25:38.237936 <6>[ 3.734637] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10647 01:25:49.263587 <6>[ 14.767583] ALSA device list:
10648 01:25:49.269731 <6>[ 14.770876] No soundcards found.
10649 01:25:49.278128 <6>[ 14.778832] Freeing unused kernel memory: 8384K
10650 01:25:49.281052 <6>[ 14.783892] Run /init as init process
10651 01:25:49.291980 Loading, please wait...
10652 01:25:49.313607 Starting version 247.3-7+deb11u2
10653 01:25:49.513810 <6>[ 15.011782] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10654 01:25:49.532447 <6>[ 15.033128] remoteproc remoteproc0: scp is available
10655 01:25:49.540095 <6>[ 15.040304] remoteproc remoteproc0: powering up scp
10656 01:25:49.549515 <6>[ 15.045639] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10657 01:25:49.553362 <6>[ 15.054096] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10658 01:25:49.562398 <6>[ 15.057526] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10659 01:25:49.569656 <6>[ 15.067443] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10660 01:25:49.579644 <6>[ 15.076265] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10661 01:25:49.589249 <3>[ 15.085756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 01:25:49.596014 <3>[ 15.094431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 01:25:49.605058 <3>[ 15.102555] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 01:25:49.619284 <3>[ 15.116975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 01:25:49.622882 <6>[ 15.119120] mc: Linux media interface: v0.10
10666 01:25:49.633063 <3>[ 15.125157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 01:25:49.639860 <4>[ 15.125403] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10668 01:25:49.645632 <4>[ 15.125729] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10669 01:25:49.656010 <6>[ 15.151379] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10670 01:25:49.662046 <3>[ 15.153690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 01:25:49.669406 <6>[ 15.156468] usbcore: registered new interface driver r8152
10672 01:25:49.675460 <6>[ 15.157588] videodev: Linux video capture interface: v2.00
10673 01:25:49.682153 <3>[ 15.180511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 01:25:49.692215 <4>[ 15.180526] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10675 01:25:49.695431 <4>[ 15.180526] Fallback method does not support PEC.
10676 01:25:49.702173 <6>[ 15.185077] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10677 01:25:49.712237 <6>[ 15.188609] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10678 01:25:49.718214 <3>[ 15.189738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 01:25:49.728853 <3>[ 15.189807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 01:25:49.735642 <3>[ 15.189857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 01:25:49.745701 <3>[ 15.189865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 01:25:49.752269 <3>[ 15.189872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 01:25:49.760190 <3>[ 15.189938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 01:25:49.769377 <3>[ 15.189947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 01:25:49.775871 <3>[ 15.189954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 01:25:49.786320 <3>[ 15.189961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 01:25:49.792178 <3>[ 15.189968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 01:25:49.802493 <3>[ 15.190004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 01:25:49.808613 <6>[ 15.207688] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10690 01:25:49.815020 <6>[ 15.209337] remoteproc remoteproc0: remote processor scp is now up
10691 01:25:49.822061 <6>[ 15.210885] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10692 01:25:49.832013 <6>[ 15.213408] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10693 01:25:49.835595 <6>[ 15.217988] pci_bus 0000:00: root bus resource [bus 00-ff]
10694 01:25:49.845038 <6>[ 15.238565] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10695 01:25:49.851367 <3>[ 15.240375] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10696 01:25:49.857993 <6>[ 15.242255] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10697 01:25:49.868003 <6>[ 15.243084] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10698 01:25:49.878220 <3>[ 15.263352] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 01:25:49.889022 <6>[ 15.267846] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10700 01:25:49.898096 <4>[ 15.269979] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10701 01:25:49.904638 <4>[ 15.269988] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10702 01:25:49.915217 <6>[ 15.274480] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10703 01:25:49.921249 <6>[ 15.274523] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10704 01:25:49.927964 <6>[ 15.274537] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10705 01:25:49.937433 <6>[ 15.282946] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10706 01:25:49.940724 <6>[ 15.290755] pci 0000:00:00.0: supports D1 D2
10707 01:25:49.947439 <6>[ 15.328469] r8152 2-1.3:1.0 eth0: v1.12.13
10708 01:25:49.950676 <6>[ 15.328732] usbcore: registered new interface driver cdc_ether
10709 01:25:49.960754 <6>[ 15.336663] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10710 01:25:49.964565 <6>[ 15.336970] usbcore: registered new interface driver r8153_ecm
10711 01:25:49.973967 <6>[ 15.337733] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10712 01:25:49.980705 <6>[ 15.337836] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10713 01:25:49.987544 <6>[ 15.337862] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10714 01:25:49.993713 <6>[ 15.337878] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10715 01:25:50.003349 <6>[ 15.337893] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10716 01:25:50.007089 <6>[ 15.338011] pci 0000:01:00.0: supports D1 D2
10717 01:25:50.014793 <6>[ 15.338016] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10718 01:25:50.020055 <6>[ 15.350423] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10719 01:25:50.024556 <6>[ 15.359312] Bluetooth: Core ver 2.22
10720 01:25:50.030352 <6>[ 15.360302] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10721 01:25:50.043084 <6>[ 15.361430] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10722 01:25:50.049517 <6>[ 15.361542] usbcore: registered new interface driver uvcvideo
10723 01:25:50.056128 <6>[ 15.365483] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10724 01:25:50.062790 <6>[ 15.369805] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10725 01:25:50.069924 <6>[ 15.374819] NET: Registered PF_BLUETOOTH protocol family
10726 01:25:50.076618 <6>[ 15.383517] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10727 01:25:50.082769 <6>[ 15.393592] Bluetooth: HCI device and connection manager initialized
10728 01:25:50.092538 <6>[ 15.402630] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10729 01:25:50.099789 <6>[ 15.403191] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10730 01:25:50.102947 <6>[ 15.410709] Bluetooth: HCI socket layer initialized
10731 01:25:50.112559 <6>[ 15.420609] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10732 01:25:50.115745 <6>[ 15.426854] Bluetooth: L2CAP socket layer initialized
10733 01:25:50.125602 <6>[ 15.434330] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10734 01:25:50.129611 <6>[ 15.443356] Bluetooth: SCO socket layer initialized
10735 01:25:50.135291 <6>[ 15.447878] pci 0000:00:00.0: PCI bridge to [bus 01]
10736 01:25:50.142182 <6>[ 15.508641] usbcore: registered new interface driver btusb
10737 01:25:50.151888 <4>[ 15.509404] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10738 01:25:50.158789 <3>[ 15.509410] Bluetooth: hci0: Failed to load firmware file (-2)
10739 01:25:50.161477 <3>[ 15.509412] Bluetooth: hci0: Failed to set up firmware (-2)
10740 01:25:50.175266 <4>[ 15.509414] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10741 01:25:50.181729 <6>[ 15.512668] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10742 01:25:50.188016 <6>[ 15.512800] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10743 01:25:50.194991 <6>[ 15.694621] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10744 01:25:50.201562 <6>[ 15.701157] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10745 01:25:50.217086 <5>[ 15.715002] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10746 01:25:50.235842 <5>[ 15.733557] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10747 01:25:50.242504 <4>[ 15.740490] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10748 01:25:50.248921 <6>[ 15.749388] cfg80211: failed to load regulatory.db
10749 01:25:50.297862 <6>[ 15.795054] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10750 01:25:50.303703 <6>[ 15.802567] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10751 01:25:50.325972 <6>[ 15.826537] mt7921e 0000:01:00.0: ASIC revision: 79610010
10752 01:25:50.431782 <4>[ 15.926401] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10753 01:25:50.451842 Begin: Loading essential drivers ... done.
10754 01:25:50.455512 Begin: Running /scripts/init-premount ... done.
10755 01:25:50.461980 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10756 01:25:50.472031 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10757 01:25:50.475034 Device /sys/class/net/enx002432307c7b found
10758 01:25:50.475589 done.
10759 01:25:50.512790 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10760 01:25:50.553553 <4>[ 16.046935] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 01:25:50.672059 <4>[ 16.166218] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10762 01:25:50.791961 <4>[ 16.286042] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 01:25:50.911541 <4>[ 16.406181] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10764 01:25:51.031587 <4>[ 16.526070] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10765 01:25:51.152151 <4>[ 16.646087] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 01:25:51.271535 <4>[ 16.765992] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 01:25:51.391633 <4>[ 16.886063] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 01:25:51.512564 <4>[ 17.005965] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 01:25:51.532936 <6>[ 17.034422] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10770 01:25:51.623058 <3>[ 17.123803] mt7921e 0000:01:00.0: hardware init failed
10771 01:25:51.658394 IP-Config: no response after 2 secs - giving up
10772 01:25:51.692621 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10773 01:25:51.699189 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10774 01:25:51.706412 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10775 01:25:51.712703 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10776 01:25:51.719292 host : mt8192-asurada-spherion-r0-cbg-2
10777 01:25:51.725609 domain : lava-rack
10778 01:25:51.728836 rootserver: 192.168.201.1 rootpath:
10779 01:25:51.729393 filename :
10780 01:25:51.807945 done.
10781 01:25:51.817487 Begin: Running /scripts/nfs-bottom ... done.
10782 01:25:51.840312 Begin: Running /scripts/init-bottom ... done.
10783 01:25:53.104590 <6>[ 18.606388] NET: Registered PF_INET6 protocol family
10784 01:25:53.112076 <6>[ 18.613747] Segment Routing with IPv6
10785 01:25:53.115637 <6>[ 18.617757] In-situ OAM (IOAM) with IPv6
10786 01:25:53.245348 <30>[ 18.727002] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10787 01:25:53.251612 <30>[ 18.751415] systemd[1]: Detected architecture arm64.
10788 01:25:53.273174
10789 01:25:53.276343 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10790 01:25:53.276806
10791 01:25:53.293032 <30>[ 18.794373] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10792 01:25:54.286625 <30>[ 19.784736] systemd[1]: Queued start job for default target Graphical Interface.
10793 01:25:54.319512 <30>[ 19.820914] systemd[1]: Created slice system-getty.slice.
10794 01:25:54.325656 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10795 01:25:54.342034 <30>[ 19.843948] systemd[1]: Created slice system-modprobe.slice.
10796 01:25:54.348533 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10797 01:25:54.366502 <30>[ 19.867839] systemd[1]: Created slice system-serial\x2dgetty.slice.
10798 01:25:54.376589 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10799 01:25:54.390711 <30>[ 19.891641] systemd[1]: Created slice User and Session Slice.
10800 01:25:54.396798 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10801 01:25:54.417896 <30>[ 19.915339] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10802 01:25:54.427431 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10803 01:25:54.445029 <30>[ 19.943345] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10804 01:25:54.452331 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10805 01:25:54.475678 <30>[ 19.970763] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10806 01:25:54.482416 <30>[ 19.982970] systemd[1]: Reached target Local Encrypted Volumes.
10807 01:25:54.488878 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10808 01:25:54.505834 <30>[ 20.007176] systemd[1]: Reached target Paths.
10809 01:25:54.512147 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10810 01:25:54.525093 <30>[ 20.026601] systemd[1]: Reached target Remote File Systems.
10811 01:25:54.531310 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10812 01:25:54.549383 <30>[ 20.050612] systemd[1]: Reached target Slices.
10813 01:25:54.552179 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10814 01:25:54.569133 <30>[ 20.070844] systemd[1]: Reached target Swap.
10815 01:25:54.572907 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10816 01:25:54.593447 <30>[ 20.091138] systemd[1]: Listening on initctl Compatibility Named Pipe.
10817 01:25:54.600326 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10818 01:25:54.606178 <30>[ 20.107584] systemd[1]: Listening on Journal Audit Socket.
10819 01:25:54.612823 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10820 01:25:54.630438 <30>[ 20.132146] systemd[1]: Listening on Journal Socket (/dev/log).
10821 01:25:54.637114 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10822 01:25:54.653734 <30>[ 20.155156] systemd[1]: Listening on Journal Socket.
10823 01:25:54.660299 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10824 01:25:54.678342 <30>[ 20.176378] systemd[1]: Listening on Network Service Netlink Socket.
10825 01:25:54.684987 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10826 01:25:54.701274 <30>[ 20.202283] systemd[1]: Listening on udev Control Socket.
10827 01:25:54.707178 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10828 01:25:54.721554 <30>[ 20.223030] systemd[1]: Listening on udev Kernel Socket.
10829 01:25:54.727802 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10830 01:25:54.785311 <30>[ 20.286778] systemd[1]: Mounting Huge Pages File System...
10831 01:25:54.791387 Mounting [0;1;39mHuge Pages File System[0m...
10832 01:25:54.809167 <30>[ 20.311036] systemd[1]: Mounting POSIX Message Queue File System...
10833 01:25:54.816140 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10834 01:25:54.838228 <30>[ 20.339789] systemd[1]: Mounting Kernel Debug File System...
10835 01:25:54.844414 Mounting [0;1;39mKernel Debug File System[0m...
10836 01:25:54.864436 <30>[ 20.363006] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10837 01:25:54.880000 <30>[ 20.378220] systemd[1]: Starting Create list of static device nodes for the current kernel...
10838 01:25:54.889393 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10839 01:25:54.910106 <30>[ 20.411843] systemd[1]: Starting Load Kernel Module configfs...
10840 01:25:54.916491 Starting [0;1;39mLoad Kernel Module configfs[0m...
10841 01:25:54.938270 <30>[ 20.439344] systemd[1]: Starting Load Kernel Module drm...
10842 01:25:54.944224 Starting [0;1;39mLoad Kernel Module drm[0m...
10843 01:25:54.962057 <30>[ 20.463961] systemd[1]: Starting Load Kernel Module fuse...
10844 01:25:54.968867 Starting [0;1;39mLoad Kernel Module fuse[0m...
10845 01:25:54.994628 <30>[ 20.493008] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10846 01:25:55.010205 <30>[ 20.512252] systemd[1]: Starting Journal Service...
10847 01:25:55.017875 Starting [0;1;39mJournal Service[0m...
10848 01:25:55.023820 <6>[ 20.525405] fuse: init (API version 7.37)
10849 01:25:55.036972 <30>[ 20.539011] systemd[1]: Starting Load Kernel Modules...
10850 01:25:55.043968 Starting [0;1;39mLoad Kernel Modules[0m...
10851 01:25:55.065518 <30>[ 20.563863] systemd[1]: Starting Remount Root and Kernel File Systems...
10852 01:25:55.071898 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10853 01:25:55.091314 <30>[ 20.593336] systemd[1]: Starting Coldplug All udev Devices...
10854 01:25:55.098351 Starting [0;1;39mColdplug All udev Devices[0m...
10855 01:25:55.118804 <30>[ 20.620300] systemd[1]: Mounted Huge Pages File System.
10856 01:25:55.124767 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10857 01:25:55.141877 <30>[ 20.643454] systemd[1]: Mounted POSIX Message Queue File System.
10858 01:25:55.148592 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10859 01:25:55.167577 <3>[ 20.665338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 01:25:55.173974 <30>[ 20.674807] systemd[1]: Mounted Kernel Debug File System.
10861 01:25:55.180226 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10862 01:25:55.196569 <3>[ 20.694806] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 01:25:55.206481 <30>[ 20.696033] systemd[1]: Finished Create list of static device nodes for the current kernel.
10864 01:25:55.213160 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10865 01:25:55.229510 <30>[ 20.731309] systemd[1]: modprobe@configfs.service: Succeeded.
10866 01:25:55.236379 <30>[ 20.737986] systemd[1]: Finished Load Kernel Module configfs.
10867 01:25:55.250778 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 20.747524] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 01:25:55.253545 l Module configfs[0m.
10869 01:25:55.270682 <30>[ 20.771444] systemd[1]: modprobe@drm.service: Succeeded.
10870 01:25:55.280476 <3>[ 20.777049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 01:25:55.284319 <30>[ 20.777914] systemd[1]: Finished Load Kernel Module drm.
10872 01:25:55.290564 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10873 01:25:55.305692 <30>[ 20.807184] systemd[1]: modprobe@fuse.service: Succeeded.
10874 01:25:55.315401 <3>[ 20.807604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 01:25:55.323067 <30>[ 20.813557] systemd[1]: Finished Load Kernel Module fuse.
10876 01:25:55.325429 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10877 01:25:55.343586 <3>[ 20.842057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 01:25:55.351155 <30>[ 20.852676] systemd[1]: Finished Load Kernel Modules.
10879 01:25:55.358255 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10880 01:25:55.376577 <3>[ 20.874790] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 01:25:55.383148 <30>[ 20.876185] systemd[1]: Finished Remount Root and Kernel File Systems.
10882 01:25:55.392847 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10883 01:25:55.408323 <3>[ 20.906494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 01:25:55.443446 <3>[ 20.942052] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 01:25:55.449781 <30>[ 20.942822] systemd[1]: Mounting FUSE Control File System...
10886 01:25:55.457225 Mounting [0;1;39mFUSE Control File System[0m...
10887 01:25:55.473523 <3>[ 20.971448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 01:25:55.479664 <30>[ 20.973429] systemd[1]: Mounting Kernel Configuration File System...
10889 01:25:55.485968 Mounting [0;1;39mKernel Configuration File System[0m...
10890 01:25:55.510881 <30>[ 21.009041] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10891 01:25:55.521872 <30>[ 21.018109] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10892 01:25:55.529998 <30>[ 21.031766] systemd[1]: Starting Load/Save Random Seed...
10893 01:25:55.536595 Starting [0;1;39mLoad/Save Random Seed[0m...
10894 01:25:55.552261 <30>[ 21.054303] systemd[1]: Starting Apply Kernel Variables...
10895 01:25:55.558817 Starting [0;1;39mApply Kernel Variables[0m...
10896 01:25:55.577256 <30>[ 21.079025] systemd[1]: Starting Create System Users...
10897 01:25:55.584793 Starting [0;1;39mCreate System Users[0m...
10898 01:25:55.601184 <4>[ 21.090602] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10899 01:25:55.607349 <3>[ 21.106281] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10900 01:25:55.610875 <30>[ 21.108186] systemd[1]: Started Journal Service.
10901 01:25:55.617387 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10902 01:25:55.646004 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10903 01:25:55.657585 See 'systemctl status systemd-udev-trigger.service' for details.
10904 01:25:55.673602 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10905 01:25:55.693558 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10906 01:25:55.714201 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10907 01:25:55.730096 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10908 01:25:55.746405 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10909 01:25:55.789984 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10910 01:25:55.807985 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10911 01:25:55.853561 <46>[ 21.351847] systemd-journald[290]: Received client request to flush runtime journal.
10912 01:25:56.905906 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10913 01:25:56.920957 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10914 01:25:56.936579 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10915 01:25:56.997109 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10916 01:25:57.277388 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10917 01:25:57.310108 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10918 01:25:57.435221 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10919 01:25:57.474035 Starting [0;1;39mNetwork Service[0m...
10920 01:25:57.761477 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10921 01:25:57.786954 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10922 01:25:57.833091 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10923 01:25:58.119019 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10924 01:25:58.136058 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10925 01:25:58.181965 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10926 01:25:58.218440 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10927 01:25:58.237440 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10928 01:25:58.253398 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10929 01:25:58.268663 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10930 01:25:58.329663 Starting [0;1;39mNetwork Name Resolution[0m...
10931 01:25:58.360797 Starting [0;1;39mNetwork Time Synchronization[0m...
10932 01:25:58.378398 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10933 01:25:58.446321 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10934 01:25:58.599133 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10935 01:25:58.616558 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10936 01:25:58.635415 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10937 01:25:58.648135 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10938 01:25:58.664119 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10939 01:25:58.809170 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10940 01:25:58.841051 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10941 01:25:58.865495 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10942 01:25:58.891814 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10943 01:25:58.903857 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10944 01:25:58.925984 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10945 01:25:58.944874 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10946 01:25:58.960749 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10947 01:25:59.016969 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10948 01:25:59.062836 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10949 01:25:59.161793 Starting [0;1;39mUser Login Management[0m...
10950 01:25:59.182096 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10951 01:25:59.201981 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10952 01:25:59.220419 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10953 01:25:59.265590 Starting [0;1;39mPermit User Sessions[0m...
10954 01:25:59.380216 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10955 01:25:59.429155 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10956 01:25:59.447772 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10957 01:25:59.465279 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10958 01:25:59.486129 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10959 01:25:59.503270 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10960 01:25:59.522765 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10961 01:25:59.541332 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10962 01:25:59.586111 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10963 01:25:59.640537 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10964 01:25:59.725931
10965 01:25:59.726438
10966 01:25:59.729228 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10967 01:25:59.729647
10968 01:25:59.732445 debian-bullseye-arm64 login: root (automatic login)
10969 01:25:59.732866
10970 01:25:59.733195
10971 01:26:00.088518 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023 aarch64
10972 01:26:00.089006
10973 01:26:00.094538 The programs included with the Debian GNU/Linux system are free software;
10974 01:26:00.101022 the exact distribution terms for each program are described in the
10975 01:26:00.104883 individual files in /usr/share/doc/*/copyright.
10976 01:26:00.105302
10977 01:26:00.110998 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10978 01:26:00.114903 permitted by applicable law.
10979 01:26:00.238600 Matched prompt #10: / #
10981 01:26:00.239700 Setting prompt string to ['/ #']
10982 01:26:00.240153 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10984 01:26:00.241121 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10985 01:26:00.241552 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
10986 01:26:00.241908 Setting prompt string to ['/ #']
10987 01:26:00.242210 Forcing a shell prompt, looking for ['/ #']
10989 01:26:00.293140 / #
10990 01:26:00.293871 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10991 01:26:00.294335 Waiting using forced prompt support (timeout 00:02:30)
10992 01:26:00.299770
10993 01:26:00.300739 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10994 01:26:00.301276 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
10996 01:26:00.402604 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf'
10997 01:26:00.408968 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11368520/extract-nfsrootfs-k0fcp9kf'
10999 01:26:00.510780 / # export NFS_SERVER_IP='192.168.201.1'
11000 01:26:00.517814 export NFS_SERVER_IP='192.168.201.1'
11001 01:26:00.518755 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11002 01:26:00.519293 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11003 01:26:00.519770 end: 2 depthcharge-action (duration 00:01:46) [common]
11004 01:26:00.520306 start: 3 lava-test-retry (timeout 00:01:00) [common]
11005 01:26:00.520778 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11006 01:26:00.521180 Using namespace: common
11008 01:26:00.622575 / # #
11009 01:26:00.623210 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11010 01:26:00.629728 #
11011 01:26:00.630495 Using /lava-11368520
11013 01:26:00.731952 / # export SHELL=/bin/sh
11014 01:26:00.739065 export SHELL=/bin/sh
11016 01:26:00.840778 / # . /lava-11368520/environment
11017 01:26:00.848351 . /lava-11368520/environment
11019 01:26:00.956873 / # /lava-11368520/bin/lava-test-runner /lava-11368520/0
11020 01:26:00.957510 Test shell timeout: 10s (minimum of the action and connection timeout)
11021 01:26:00.963581 /lava-11368520/bin/lava-test-runner /lava-11368520/0
11022 01:26:01.266326 + export TESTRUN_ID=0_dmesg
11023 01:26:01.269775 + cd /lava-11368520/0/tests/0_dmesg
11024 01:26:01.272867 + cat uuid
11025 01:26:01.292904 + UUID=11368520_<8>[ 26.792022] <LAVA_SIGNAL_STARTRUN 0_dmesg 11368520_1.6.2.3.1>
11026 01:26:01.293465 1.6.2.3.1
11027 01:26:01.293828 + set +x
11028 01:26:01.294420 Received signal: <STARTRUN> 0_dmesg 11368520_1.6.2.3.1
11029 01:26:01.294781 Starting test lava.0_dmesg (11368520_1.6.2.3.1)
11030 01:26:01.295190 Skipping test definition patterns.
11031 01:26:01.298955 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11032 01:26:01.433261 <8>[ 26.931819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11033 01:26:01.434053 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11035 01:26:01.533425 <8>[ 27.032044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11036 01:26:01.534227 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11038 01:26:01.637158 <8>[ 27.135190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11039 01:26:01.637904 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11041 01:26:01.639207 + set +x
11042 01:26:01.642594 <8>[ 27.144532] <LAVA_SIGNAL_ENDRUN 0_dmesg 11368520_1.6.2.3.1>
11043 01:26:01.643268 Received signal: <ENDRUN> 0_dmesg 11368520_1.6.2.3.1
11044 01:26:01.643668 Ending use of test pattern.
11045 01:26:01.644028 Ending test lava.0_dmesg (11368520_1.6.2.3.1), duration 0.35
11047 01:26:01.650218 <LAVA_TEST_RUNNER EXIT>
11048 01:26:01.650883 ok: lava_test_shell seems to have completed
11049 01:26:01.651400 alert: pass
crit: pass
emerg: pass
11050 01:26:01.651801 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11051 01:26:01.652283 end: 3 lava-test-retry (duration 00:00:01) [common]
11052 01:26:01.652706 start: 4 lava-test-retry (timeout 00:01:00) [common]
11053 01:26:01.653107 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11054 01:26:01.653425 Using namespace: common
11056 01:26:01.754493 / # #
11057 01:26:01.755128 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11058 01:26:01.755692 Using /lava-11368520
11060 01:26:01.857086 export SHELL=/bin/sh
11061 01:26:01.857864 #
11063 01:26:01.959598 / # export SHELL=/bin/sh. /lava-11368520/environment
11064 01:26:01.960424
11066 01:26:02.062101 / # . /lava-11368520/environment/lava-11368520/bin/lava-test-runner /lava-11368520/1
11067 01:26:02.062724 Test shell timeout: 10s (minimum of the action and connection timeout)
11068 01:26:02.063334
11069 01:26:02.068912 / # /lava-11368520/bin/lava-test-runner /lava-11368520/1
11070 01:26:02.251129 + export TESTRUN_ID=1_bootrr
11071 01:26:02.253680 + cd /lava-11368520/1/tests/1_bootrr
11072 01:26:02.256778 + cat uuid
11073 01:26:02.277779 + UUID=11368520_<8>[ 27.777186] <LAVA_SIGNAL_STARTRUN 1_bootrr 11368520_1.6.2.3.5>
11074 01:26:02.278295 1.6.2.3.5
11075 01:26:02.278634 + set +x
11076 01:26:02.279216 Received signal: <STARTRUN> 1_bootrr 11368520_1.6.2.3.5
11077 01:26:02.279563 Starting test lava.1_bootrr (11368520_1.6.2.3.5)
11078 01:26:02.279975 Skipping test definition patterns.
11079 01:26:02.291620 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11368520/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11080 01:26:02.294141 + cd /opt/bootrr/libexec/bootrr
11081 01:26:02.294784 + sh helpers/bootrr-auto
11082 01:26:02.394425 /lava-11368520/1/../bin/lava-test-case
11083 01:26:02.439575 <8>[ 27.938948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11084 01:26:02.440405 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11086 01:26:02.504050 /lava-11368520/1/../bin/lava-test-case
11087 01:26:02.539689 <8>[ 28.038799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11088 01:26:02.540418 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11090 01:26:02.576680 /lava-11368520/1/../bin/lava-test-case
11091 01:26:02.616919 <8>[ 28.116434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11092 01:26:02.617735 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11094 01:26:02.688862 /lava-11368520/1/../bin/lava-test-case
11095 01:26:02.726693 <8>[ 28.226293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11096 01:26:02.727457 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11098 01:26:02.776346 /lava-11368520/1/../bin/lava-test-case
11099 01:26:02.817115 <8>[ 28.316122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11100 01:26:02.817907 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11102 01:26:02.862928 /lava-11368520/1/../bin/lava-test-case
11103 01:26:02.903998 <8>[ 28.403259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11104 01:26:02.904792 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11106 01:26:02.956021 /lava-11368520/1/../bin/lava-test-case
11107 01:26:02.997872 <8>[ 28.496893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11108 01:26:02.998687 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11110 01:26:03.043582 /lava-11368520/1/../bin/lava-test-case
11111 01:26:03.082161 <8>[ 28.581827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11112 01:26:03.082928 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11114 01:26:03.111091 /lava-11368520/1/../bin/lava-test-case
11115 01:26:03.148625 <8>[ 28.647931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11116 01:26:03.149412 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11118 01:26:03.195383 /lava-11368520/1/../bin/lava-test-case
11119 01:26:03.234575 <8>[ 28.734277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11120 01:26:03.235282 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11122 01:26:03.263733 /lava-11368520/1/../bin/lava-test-case
11123 01:26:03.303383 <8>[ 28.802727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11124 01:26:03.304220 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11126 01:26:03.356299 /lava-11368520/1/../bin/lava-test-case
11127 01:26:03.393150 <8>[ 28.892206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11128 01:26:03.393941 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11130 01:26:03.435537 /lava-11368520/1/../bin/lava-test-case
11131 01:26:03.472601 <8>[ 28.971853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11132 01:26:03.473387 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11134 01:26:03.520209 /lava-11368520/1/../bin/lava-test-case
11135 01:26:03.559891 <8>[ 29.059496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11136 01:26:03.560640 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11138 01:26:03.603283 /lava-11368520/1/../bin/lava-test-case
11139 01:26:03.641927 <8>[ 29.141455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11140 01:26:03.642773 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11142 01:26:03.671854 /lava-11368520/1/../bin/lava-test-case
11143 01:26:03.711329 <8>[ 29.210780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11144 01:26:03.712134 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11146 01:26:03.769090 /lava-11368520/1/../bin/lava-test-case
11147 01:26:03.807656 <8>[ 29.306986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11148 01:26:03.808460 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11150 01:26:03.838627 /lava-11368520/1/../bin/lava-test-case
11151 01:26:03.877244 <8>[ 29.376603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11152 01:26:03.878033 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11154 01:26:03.922891 /lava-11368520/1/../bin/lava-test-case
11155 01:26:03.965247 <8>[ 29.464792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11156 01:26:03.966045 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11158 01:26:03.993646 /lava-11368520/1/../bin/lava-test-case
11159 01:26:04.033128 <8>[ 29.532529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11160 01:26:04.033903 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11162 01:26:04.081561 /lava-11368520/1/../bin/lava-test-case
11163 01:26:04.119568 <8>[ 29.618696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11164 01:26:04.120397 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11166 01:26:04.153222 /lava-11368520/1/../bin/lava-test-case
11167 01:26:04.194074 <8>[ 29.693726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11168 01:26:04.194876 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11170 01:26:04.243293 /lava-11368520/1/../bin/lava-test-case
11171 01:26:04.284140 <8>[ 29.783716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11172 01:26:04.284946 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11174 01:26:04.313970 /lava-11368520/1/../bin/lava-test-case
11175 01:26:04.354601 <8>[ 29.853944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11176 01:26:04.355386 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11178 01:26:04.402521 /lava-11368520/1/../bin/lava-test-case
11179 01:26:04.443370 <8>[ 29.943303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11180 01:26:04.444065 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11182 01:26:04.485179 /lava-11368520/1/../bin/lava-test-case
11183 01:26:04.525161 <8>[ 30.024617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11184 01:26:04.526063 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11186 01:26:04.561838 /lava-11368520/1/../bin/lava-test-case
11187 01:26:04.599515 <8>[ 30.099094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11188 01:26:04.600255 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11190 01:26:04.644354 /lava-11368520/1/../bin/lava-test-case
11191 01:26:04.684470 <8>[ 30.183912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11192 01:26:04.685254 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11194 01:26:04.714522 /lava-11368520/1/../bin/lava-test-case
11195 01:26:04.754012 <8>[ 30.253322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11196 01:26:04.754808 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11198 01:26:04.797665 /lava-11368520/1/../bin/lava-test-case
11199 01:26:04.838468 <8>[ 30.338008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11200 01:26:04.839259 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11202 01:26:04.884225 /lava-11368520/1/../bin/lava-test-case
11203 01:26:04.924381 <8>[ 30.424031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11204 01:26:04.925176 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11206 01:26:04.979714 /lava-11368520/1/../bin/lava-test-case
11207 01:26:05.018359 <8>[ 30.517899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11208 01:26:05.019147 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11210 01:26:05.068110 /lava-11368520/1/../bin/lava-test-case
11211 01:26:05.106426 <8>[ 30.605445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11212 01:26:05.107220 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11214 01:26:05.134641 /lava-11368520/1/../bin/lava-test-case
11215 01:26:05.171853 <8>[ 30.671290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11216 01:26:05.172741 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11218 01:26:05.215733 /lava-11368520/1/../bin/lava-test-case
11219 01:26:05.255246 <8>[ 30.753575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11220 01:26:05.256058 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11222 01:26:05.301024 /lava-11368520/1/../bin/lava-test-case
11223 01:26:05.338937 <8>[ 30.837879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11224 01:26:05.339754 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11226 01:26:05.374595 /lava-11368520/1/../bin/lava-test-case
11227 01:26:05.411963 <8>[ 30.911523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11228 01:26:05.412767 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11230 01:26:05.460826 /lava-11368520/1/../bin/lava-test-case
11231 01:26:05.503144 <8>[ 31.002701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11232 01:26:05.504007 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11234 01:26:05.532799 /lava-11368520/1/../bin/lava-test-case
11235 01:26:05.572687 <8>[ 31.072235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11236 01:26:05.573518 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11238 01:26:05.619220 /lava-11368520/1/../bin/lava-test-case
11239 01:26:05.660132 <8>[ 31.159588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11240 01:26:05.660932 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11242 01:26:05.688034 /lava-11368520/1/../bin/lava-test-case
11243 01:26:05.726365 <8>[ 31.225911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11244 01:26:05.727204 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11246 01:26:05.777205 /lava-11368520/1/../bin/lava-test-case
11247 01:26:05.815412 <8>[ 31.314526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11248 01:26:05.816284 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11250 01:26:05.844548 /lava-11368520/1/../bin/lava-test-case
11251 01:26:05.884097 <8>[ 31.383657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11252 01:26:05.884902 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11254 01:26:05.934970 /lava-11368520/1/../bin/lava-test-case
11255 01:26:05.977224 <8>[ 31.476422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11256 01:26:05.978046 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11258 01:26:06.006169 /lava-11368520/1/../bin/lava-test-case
11259 01:26:06.044291 <8>[ 31.543930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11260 01:26:06.045110 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11262 01:26:06.090301 /lava-11368520/1/../bin/lava-test-case
11263 01:26:06.130324 <8>[ 31.630079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11264 01:26:06.131104 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11266 01:26:06.166392 /lava-11368520/1/../bin/lava-test-case
11267 01:26:06.205522 <8>[ 31.705121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11268 01:26:06.206317 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11270 01:26:06.249531 /lava-11368520/1/../bin/lava-test-case
11271 01:26:06.289675 <8>[ 31.788993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11272 01:26:06.290555 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11274 01:26:06.318038 /lava-11368520/1/../bin/lava-test-case
11275 01:26:06.358523 <8>[ 31.858592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11276 01:26:06.359276 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11278 01:26:06.404409 /lava-11368520/1/../bin/lava-test-case
11279 01:26:06.444758 <8>[ 31.944938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11280 01:26:06.445118 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11282 01:26:06.489659 /lava-11368520/1/../bin/lava-test-case
11283 01:26:06.531502 <8>[ 32.031335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11284 01:26:06.532360 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11286 01:26:06.567772 /lava-11368520/1/../bin/lava-test-case
11287 01:26:06.604879 <8>[ 32.104789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11288 01:26:06.605230 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11290 01:26:06.651777 /lava-11368520/1/../bin/lava-test-case
11291 01:26:06.694570 <8>[ 32.193944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11292 01:26:06.695360 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11294 01:26:06.724149 /lava-11368520/1/../bin/lava-test-case
11295 01:26:06.765070 <8>[ 32.264846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11296 01:26:06.765766 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11298 01:26:06.811253 /lava-11368520/1/../bin/lava-test-case
11299 01:26:06.849240 <8>[ 32.348854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11300 01:26:06.850130 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11302 01:26:06.894518 /lava-11368520/1/../bin/lava-test-case
11303 01:26:06.929983 <8>[ 32.429841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11304 01:26:06.930868 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11306 01:26:06.983805 /lava-11368520/1/../bin/lava-test-case
11307 01:26:07.027984 <8>[ 32.527193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11308 01:26:07.028853 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11310 01:26:07.074828 /lava-11368520/1/../bin/lava-test-case
11311 01:26:07.115813 <8>[ 32.615868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11312 01:26:07.116589 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11314 01:26:07.162430 /lava-11368520/1/../bin/lava-test-case
11315 01:26:07.201021 <8>[ 32.700699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11316 01:26:07.201821 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11318 01:26:07.229007 /lava-11368520/1/../bin/lava-test-case
11319 01:26:07.270757 <8>[ 32.769555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11320 01:26:07.271559 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11322 01:26:07.316359 /lava-11368520/1/../bin/lava-test-case
11323 01:26:07.350960 <8>[ 32.851089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11324 01:26:07.351742 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11326 01:26:07.401941 /lava-11368520/1/../bin/lava-test-case
11327 01:26:07.442069 <8>[ 32.942024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11328 01:26:07.442847 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11330 01:26:07.473005 /lava-11368520/1/../bin/lava-test-case
11331 01:26:07.512506 <8>[ 33.012067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11332 01:26:07.513381 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11334 01:26:07.557578 /lava-11368520/1/../bin/lava-test-case
11335 01:26:07.596724 <8>[ 33.096768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11336 01:26:07.597540 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11338 01:26:07.623693 /lava-11368520/1/../bin/lava-test-case
11339 01:26:07.662133 <8>[ 33.162031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11340 01:26:07.662837 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11342 01:26:07.712241 /lava-11368520/1/../bin/lava-test-case
11343 01:26:07.755757 <8>[ 33.255769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11344 01:26:07.756539 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11346 01:26:07.792974 /lava-11368520/1/../bin/lava-test-case
11347 01:26:07.834000 <8>[ 33.333972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11348 01:26:07.834784 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11350 01:26:07.884994 /lava-11368520/1/../bin/lava-test-case
11351 01:26:07.928434 <8>[ 33.428293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11352 01:26:07.929238 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11354 01:26:07.975580 /lava-11368520/1/../bin/lava-test-case
11355 01:26:08.012548 <8>[ 33.512762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11356 01:26:08.013287 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11358 01:26:08.059443 /lava-11368520/1/../bin/lava-test-case
11359 01:26:08.098162 <8>[ 33.598546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11360 01:26:08.098551 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11362 01:26:08.144996 /lava-11368520/1/../bin/lava-test-case
11363 01:26:08.184826 <8>[ 33.684474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11364 01:26:08.185631 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11366 01:26:08.231883 /lava-11368520/1/../bin/lava-test-case
11367 01:26:08.270629 <8>[ 33.769929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11368 01:26:08.271436 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11370 01:26:08.314265 /lava-11368520/1/../bin/lava-test-case
11371 01:26:08.352613 <8>[ 33.853049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11372 01:26:08.352894 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11374 01:26:08.396024 /lava-11368520/1/../bin/lava-test-case
11375 01:26:08.437372 <8>[ 33.937339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11376 01:26:08.438177 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11378 01:26:08.479348 /lava-11368520/1/../bin/lava-test-case
11379 01:26:08.513211 <8>[ 34.013155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11380 01:26:08.513486 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11382 01:26:08.562581 /lava-11368520/1/../bin/lava-test-case
11383 01:26:08.603735 <8>[ 34.103972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11384 01:26:08.604568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11386 01:26:08.646890 /lava-11368520/1/../bin/lava-test-case
11387 01:26:08.685452 <8>[ 34.185196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11388 01:26:08.685814 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11390 01:26:08.727359 /lava-11368520/1/../bin/lava-test-case
11391 01:26:08.770704 <8>[ 34.270590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11392 01:26:08.771396 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11394 01:26:08.816480 /lava-11368520/1/../bin/lava-test-case
11395 01:26:08.856770 <8>[ 34.356141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11396 01:26:08.857457 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11398 01:26:08.907212 /lava-11368520/1/../bin/lava-test-case
11399 01:26:08.947468 <8>[ 34.447742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11400 01:26:08.948315 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11402 01:26:08.998556 /lava-11368520/1/../bin/lava-test-case
11403 01:26:09.038742 <8>[ 34.539069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11404 01:26:09.039548 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11406 01:26:09.087518 /lava-11368520/1/../bin/lava-test-case
11407 01:26:09.130412 <8>[ 34.630122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11408 01:26:09.131207 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11410 01:26:09.161568 /lava-11368520/1/../bin/lava-test-case
11411 01:26:09.201279 <8>[ 34.701377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11412 01:26:09.202086 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11414 01:26:09.247717 /lava-11368520/1/../bin/lava-test-case
11415 01:26:09.289380 <8>[ 34.789751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11416 01:26:09.290256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11418 01:26:09.319900 /lava-11368520/1/../bin/lava-test-case
11419 01:26:09.358225 <8>[ 34.857475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11420 01:26:09.358919 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11422 01:26:09.408884 /lava-11368520/1/../bin/lava-test-case
11423 01:26:09.451941 <8>[ 34.952084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11424 01:26:09.452730 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11426 01:26:09.481869 /lava-11368520/1/../bin/lava-test-case
11427 01:26:09.520659 <8>[ 35.020641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11428 01:26:09.521450 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11430 01:26:09.568305 /lava-11368520/1/../bin/lava-test-case
11431 01:26:09.609604 <8>[ 35.109920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11432 01:26:09.610373 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11434 01:26:09.639657 /lava-11368520/1/../bin/lava-test-case
11435 01:26:09.680965 <8>[ 35.181199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11436 01:26:09.681707 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11438 01:26:09.728355 /lava-11368520/1/../bin/lava-test-case
11439 01:26:09.768026 <8>[ 35.268412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11440 01:26:09.768782 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11442 01:26:09.802917 /lava-11368520/1/../bin/lava-test-case
11443 01:26:09.841328 <8>[ 35.341794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11444 01:26:09.842201 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11446 01:26:09.890497 /lava-11368520/1/../bin/lava-test-case
11447 01:26:09.929745 <8>[ 35.430047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11448 01:26:09.930546 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11450 01:26:09.957820 /lava-11368520/1/../bin/lava-test-case
11451 01:26:09.998820 <8>[ 35.499088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11452 01:26:09.999606 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11454 01:26:10.045706 /lava-11368520/1/../bin/lava-test-case
11455 01:26:10.083094 <8>[ 35.583189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11456 01:26:10.083882 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11458 01:26:10.127096 /lava-11368520/1/../bin/lava-test-case
11459 01:26:10.166316 <8>[ 35.666144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11460 01:26:10.167008 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11462 01:26:10.201301 /lava-11368520/1/../bin/lava-test-case
11463 01:26:10.242181 <8>[ 35.741914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11464 01:26:10.242974 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11466 01:26:10.287795 /lava-11368520/1/../bin/lava-test-case
11467 01:26:10.328519 <8>[ 35.829090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11468 01:26:10.329208 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11470 01:26:10.356188 /lava-11368520/1/../bin/lava-test-case
11471 01:26:10.392668 <8>[ 35.893069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11472 01:26:10.393031 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11474 01:26:10.437133 /lava-11368520/1/../bin/lava-test-case
11475 01:26:10.476751 <8>[ 35.976492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11476 01:26:10.477129 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11478 01:26:10.502293 /lava-11368520/1/../bin/lava-test-case
11479 01:26:10.536057 <8>[ 36.036466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11480 01:26:10.536840 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11482 01:26:11.629640 /lava-11368520/1/../bin/lava-test-case
11483 01:26:11.675378 <8>[ 37.175929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11484 01:26:11.676270 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11486 01:26:11.703708 /lava-11368520/1/../bin/lava-test-case
11487 01:26:11.739440 <8>[ 37.240050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11488 01:26:11.740136 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11490 01:26:12.812299 /lava-11368520/1/../bin/lava-test-case
11491 01:26:12.855356 <8>[ 38.355514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11492 01:26:12.856145 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11494 01:26:12.882668 /lava-11368520/1/../bin/lava-test-case
11495 01:26:12.921708 <8>[ 38.422545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11496 01:26:12.922478 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11498 01:26:13.989755 /lava-11368520/1/../bin/lava-test-case
11499 01:26:14.034504 <8>[ 39.535277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11500 01:26:14.035271 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11502 01:26:14.064607 /lava-11368520/1/../bin/lava-test-case
11503 01:26:14.101686 <8>[ 39.602116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11504 01:26:14.102044 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11506 01:26:15.170904 /lava-11368520/1/../bin/lava-test-case
11507 01:26:15.210904 <8>[ 40.712073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11508 01:26:15.211267 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11510 01:26:15.237120 /lava-11368520/1/../bin/lava-test-case
11511 01:26:15.272026 <8>[ 40.772893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11512 01:26:15.272777 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11514 01:26:16.337093 /lava-11368520/1/../bin/lava-test-case
11515 01:26:16.376245 <8>[ 41.876751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11516 01:26:16.377065 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11518 01:26:16.404376 /lava-11368520/1/../bin/lava-test-case
11519 01:26:16.441056 <8>[ 41.941677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11520 01:26:16.441843 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11522 01:26:17.506665 /lava-11368520/1/../bin/lava-test-case
11523 01:26:17.548025 <8>[ 43.049011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11524 01:26:17.548819 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11526 01:26:17.578227 /lava-11368520/1/../bin/lava-test-case
11527 01:26:17.617260 <8>[ 43.118429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11528 01:26:17.618074 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11530 01:26:18.684009 /lava-11368520/1/../bin/lava-test-case
11531 01:26:18.722031 <8>[ 44.222633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11532 01:26:18.722826 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11534 01:26:18.749267 /lava-11368520/1/../bin/lava-test-case
11535 01:26:18.785889 <8>[ 44.286976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11536 01:26:18.786688 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11538 01:26:18.814949 /lava-11368520/1/../bin/lava-test-case
11539 01:26:18.851800 <8>[ 44.352897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11540 01:26:18.852650 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11542 01:26:19.919694 /lava-11368520/1/../bin/lava-test-case
11543 01:26:19.961325 <8>[ 45.462882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11544 01:26:19.962112 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11546 01:26:19.991115 /lava-11368520/1/../bin/lava-test-case
11547 01:26:20.031232 <8>[ 45.532189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11548 01:26:20.032019 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11550 01:26:20.073744 /lava-11368520/1/../bin/lava-test-case
11551 01:26:20.110498 <8>[ 45.611283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11552 01:26:20.111295 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11554 01:26:20.143956 /lava-11368520/1/../bin/lava-test-case
11555 01:26:20.179939 <8>[ 45.681393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11556 01:26:20.180639 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11558 01:26:20.227149 /lava-11368520/1/../bin/lava-test-case
11559 01:26:20.266165 <8>[ 45.767304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11560 01:26:20.266951 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11562 01:26:20.321921 /lava-11368520/1/../bin/lava-test-case
11563 01:26:20.361599 <8>[ 45.862054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11564 01:26:20.362334 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11566 01:26:20.406757 /lava-11368520/1/../bin/lava-test-case
11567 01:26:20.446753 <8>[ 45.948259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11568 01:26:20.447614 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11570 01:26:20.478314 /lava-11368520/1/../bin/lava-test-case
11571 01:26:20.518116 <8>[ 46.018750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11572 01:26:20.518906 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11574 01:26:20.566319 /lava-11368520/1/../bin/lava-test-case
11575 01:26:20.605818 <8>[ 46.107279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11576 01:26:20.606597 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11578 01:26:20.653820 /lava-11368520/1/../bin/lava-test-case
11579 01:26:20.690726 <8>[ 46.192330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11580 01:26:20.691483 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11582 01:26:20.726328 /lava-11368520/1/../bin/lava-test-case
11583 01:26:20.764993 <8>[ 46.266443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11584 01:26:20.765781 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11586 01:26:20.813238 /lava-11368520/1/../bin/lava-test-case
11587 01:26:20.852281 <8>[ 46.353104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11588 01:26:20.852993 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11590 01:26:20.880784 /lava-11368520/1/../bin/lava-test-case
11591 01:26:20.921885 <8>[ 46.422748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11592 01:26:20.922726 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11594 01:26:20.969798 /lava-11368520/1/../bin/lava-test-case
11595 01:26:20.993260 <6>[ 46.501585] vpu: disabling
11596 01:26:20.996625 <6>[ 46.504690] vproc2: disabling
11597 01:26:21.000292 <6>[ 46.508011] vproc1: disabling
11598 01:26:21.003318 <6>[ 46.511359] vaud18: disabling
11599 01:26:21.010517 <6>[ 46.514827] vsram_others: disabling
11600 01:26:21.013363 <6>[ 46.518780] va09: disabling
11601 01:26:21.020068 <8>[ 46.519375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11602 01:26:21.020835 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11604 01:26:21.023701 <6>[ 46.521952] vsram_md: disabling
11605 01:26:21.026685 <6>[ 46.533580] Vgpu: disabling
11606 01:26:21.064770 /lava-11368520/1/../bin/lava-test-case
11607 01:26:21.104090 <8>[ 46.605366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11608 01:26:21.104902 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11610 01:26:21.151024 /lava-11368520/1/../bin/lava-test-case
11611 01:26:21.192532 <8>[ 46.693739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11612 01:26:21.193297 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11614 01:26:21.224348 /lava-11368520/1/../bin/lava-test-case
11615 01:26:21.262011 <8>[ 46.763706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11616 01:26:21.262701 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11618 01:26:21.313092 /lava-11368520/1/../bin/lava-test-case
11619 01:26:21.350810 <8>[ 46.852372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11620 01:26:21.351573 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11622 01:26:21.380871 /lava-11368520/1/../bin/lava-test-case
11623 01:26:21.419345 <8>[ 46.920886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11624 01:26:21.420109 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11626 01:26:21.473107 /lava-11368520/1/../bin/lava-test-case
11627 01:26:21.511365 <8>[ 47.012795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11628 01:26:21.512157 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11630 01:26:21.541418 /lava-11368520/1/../bin/lava-test-case
11631 01:26:21.577793 <8>[ 47.079319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11632 01:26:21.578581 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11634 01:26:22.644473 /lava-11368520/1/../bin/lava-test-case
11635 01:26:22.683633 <8>[ 48.185260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11636 01:26:22.684351 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11638 01:26:23.742943 /lava-11368520/1/../bin/lava-test-case
11639 01:26:23.775772 <8>[ 49.277973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11640 01:26:23.776073 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11642 01:26:23.801356 /lava-11368520/1/../bin/lava-test-case
11643 01:26:23.835709 <8>[ 49.338203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11644 01:26:23.836024 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11646 01:26:23.875446 /lava-11368520/1/../bin/lava-test-case
11647 01:26:23.907362 <8>[ 49.409596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11648 01:26:23.907669 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11650 01:26:23.931278 /lava-11368520/1/../bin/lava-test-case
11651 01:26:23.960814 <8>[ 49.463299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11652 01:26:23.961111 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11654 01:26:24.001389 /lava-11368520/1/../bin/lava-test-case
11655 01:26:24.033236 <8>[ 49.535814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11656 01:26:24.033543 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11658 01:26:24.063840 /lava-11368520/1/../bin/lava-test-case
11659 01:26:24.091867 <8>[ 49.593953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11660 01:26:24.092193 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11662 01:26:24.128602 /lava-11368520/1/../bin/lava-test-case
11663 01:26:24.163206 <8>[ 49.665411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11664 01:26:24.163519 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11666 01:26:24.187212 /lava-11368520/1/../bin/lava-test-case
11667 01:26:24.218139 <8>[ 49.720493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11668 01:26:24.218460 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11670 01:26:24.257667 /lava-11368520/1/../bin/lava-test-case
11671 01:26:24.290450 <8>[ 49.792658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11672 01:26:24.290747 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11674 01:26:24.315414 /lava-11368520/1/../bin/lava-test-case
11675 01:26:24.345954 <8>[ 49.848306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11676 01:26:24.346239 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11678 01:26:24.389132 /lava-11368520/1/../bin/lava-test-case
11679 01:26:24.422176 <8>[ 49.924542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11680 01:26:24.422483 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11682 01:26:24.447603 /lava-11368520/1/../bin/lava-test-case
11683 01:26:24.481494 <8>[ 49.983790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11684 01:26:24.481788 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11686 01:26:24.523287 /lava-11368520/1/../bin/lava-test-case
11687 01:26:24.558526 <8>[ 50.060472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11688 01:26:24.558846 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11690 01:26:24.582937 /lava-11368520/1/../bin/lava-test-case
11691 01:26:24.616798 <8>[ 50.119199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11692 01:26:24.617112 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11694 01:26:24.657979 /lava-11368520/1/../bin/lava-test-case
11695 01:26:24.692911 <8>[ 50.195435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11696 01:26:24.693223 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11698 01:26:24.724393 /lava-11368520/1/../bin/lava-test-case
11699 01:26:24.751879 <8>[ 50.254011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11700 01:26:24.752216 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11702 01:26:24.790295 /lava-11368520/1/../bin/lava-test-case
11703 01:26:24.823554 <8>[ 50.326183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11704 01:26:24.823869 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11706 01:26:24.850351 /lava-11368520/1/../bin/lava-test-case
11707 01:26:24.884108 <8>[ 50.386382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11708 01:26:24.884406 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11710 01:26:24.923207 /lava-11368520/1/../bin/lava-test-case
11711 01:26:24.957321 <8>[ 50.459172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11712 01:26:24.957590 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11714 01:26:24.981758 /lava-11368520/1/../bin/lava-test-case
11715 01:26:25.013840 <8>[ 50.516153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11716 01:26:25.014164 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11718 01:26:25.061921 /lava-11368520/1/../bin/lava-test-case
11719 01:26:25.094641 <8>[ 50.597177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11720 01:26:25.094948 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11722 01:26:26.135238 /lava-11368520/1/../bin/lava-test-case
11723 01:26:26.171754 <8>[ 51.673641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11724 01:26:26.172058 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11726 01:26:27.212951 /lava-11368520/1/../bin/lava-test-case
11727 01:26:27.249372 <8>[ 52.751379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11728 01:26:27.249640 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11729 01:26:27.249728 Bad test result: blocked
11730 01:26:27.275415 /lava-11368520/1/../bin/lava-test-case
11731 01:26:27.307106 <8>[ 52.809449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11732 01:26:27.307377 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11734 01:26:28.364586 /lava-11368520/1/../bin/lava-test-case
11735 01:26:28.397584 <8>[ 53.900485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11736 01:26:28.397860 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11738 01:26:28.423829 /lava-11368520/1/../bin/lava-test-case
11739 01:26:28.455773 <8>[ 53.958408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11740 01:26:28.456032 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11742 01:26:28.492629 /lava-11368520/1/../bin/lava-test-case
11743 01:26:28.522253 <8>[ 54.025107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11744 01:26:28.522514 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11746 01:26:28.560645 /lava-11368520/1/../bin/lava-test-case
11747 01:26:28.593963 <8>[ 54.096672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11748 01:26:28.594223 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11750 01:26:28.617947 /lava-11368520/1/../bin/lava-test-case
11751 01:26:28.652320 <8>[ 54.154863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11752 01:26:28.652576 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11754 01:26:28.698691 /lava-11368520/1/../bin/lava-test-case
11755 01:26:28.731876 <8>[ 54.234794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11756 01:26:28.732188 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11758 01:26:28.758287 /lava-11368520/1/../bin/lava-test-case
11759 01:26:28.790900 <8>[ 54.293478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11760 01:26:28.791159 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11762 01:26:29.851423 /lava-11368520/1/../bin/lava-test-case
11763 01:26:29.884263 <8>[ 55.387327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11764 01:26:29.884584 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11766 01:26:29.909753 /lava-11368520/1/../bin/lava-test-case
11767 01:26:29.944754 <8>[ 55.446825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11768 01:26:29.945080 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11770 01:26:30.998196 /lava-11368520/1/../bin/lava-test-case
11771 01:26:31.037993 <8>[ 56.541162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11772 01:26:31.038320 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11774 01:26:31.059427 /lava-11368520/1/../bin/lava-test-case
11775 01:26:31.089139 <8>[ 56.592311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11776 01:26:31.089462 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11778 01:26:32.138979 /lava-11368520/1/../bin/lava-test-case
11779 01:26:32.175845 <8>[ 57.679063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11780 01:26:32.176230 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11782 01:26:32.201375 /lava-11368520/1/../bin/lava-test-case
11783 01:26:32.234607 <8>[ 57.736898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11784 01:26:32.234939 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11786 01:26:33.287448 /lava-11368520/1/../bin/lava-test-case
11787 01:26:33.315749 <8>[ 58.819013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11788 01:26:33.316076 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11790 01:26:33.340876 /lava-11368520/1/../bin/lava-test-case
11791 01:26:33.373342 <8>[ 58.876901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11792 01:26:33.373668 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11794 01:26:33.414190 /lava-11368520/1/../bin/lava-test-case
11795 01:26:33.446004 <8>[ 58.949319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11796 01:26:33.446331 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11798 01:26:33.486700 /lava-11368520/1/../bin/lava-test-case
11799 01:26:33.519386 <8>[ 59.022328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11800 01:26:33.519713 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11802 01:26:33.543092 /lava-11368520/1/../bin/lava-test-case
11803 01:26:33.575194 <8>[ 59.078151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11804 01:26:33.575525 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11806 01:26:33.622774 /lava-11368520/1/../bin/lava-test-case
11807 01:26:33.656495 <8>[ 59.159946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11808 01:26:33.656823 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11810 01:26:33.681690 /lava-11368520/1/../bin/lava-test-case
11811 01:26:33.711795 <8>[ 59.215427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11812 01:26:33.712180 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11814 01:26:33.751598 /lava-11368520/1/../bin/lava-test-case
11815 01:26:33.785794 <8>[ 59.289249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11816 01:26:33.786169 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11818 01:26:33.811495 /lava-11368520/1/../bin/lava-test-case
11819 01:26:33.844618 <8>[ 59.347790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11820 01:26:33.844946 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11822 01:26:33.889693 /lava-11368520/1/../bin/lava-test-case
11823 01:26:33.924036 <8>[ 59.427542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11824 01:26:33.924365 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11826 01:26:33.936624 + set +x
11827 01:26:33.939884 Received signal: <ENDRUN> 1_bootrr 11368520_1.6.2.3.5
11828 01:26:33.940028 Ending use of test pattern.
11829 01:26:33.940094 Ending test lava.1_bootrr (11368520_1.6.2.3.5), duration 31.66
11831 01:26:33.943001 <8>[ 59.446527] <LAVA_SIGNAL_ENDRUN 1_bootrr 11368520_1.6.2.3.5>
11832 01:26:33.947503 <LAVA_TEST_RUNNER EXIT>
11833 01:26:33.947763 ok: lava_test_shell seems to have completed
11834 01:26:33.948788 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11835 01:26:33.948954 end: 4.1 lava-test-shell (duration 00:00:32) [common]
11836 01:26:33.949042 end: 4 lava-test-retry (duration 00:00:32) [common]
11837 01:26:33.949130 start: 5 finalize (timeout 00:07:14) [common]
11838 01:26:33.949217 start: 5.1 power-off (timeout 00:00:30) [common]
11839 01:26:33.949369 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11840 01:26:34.026767 >> Command sent successfully.
11841 01:26:34.029283 Returned 0 in 0 seconds
11842 01:26:34.129685 end: 5.1 power-off (duration 00:00:00) [common]
11844 01:26:34.130030 start: 5.2 read-feedback (timeout 00:07:14) [common]
11845 01:26:34.130293 Listened to connection for namespace 'common' for up to 1s
11846 01:26:35.131261 Finalising connection for namespace 'common'
11847 01:26:35.131449 Disconnecting from shell: Finalise
11848 01:26:35.131532 / #
11849 01:26:35.231891 end: 5.2 read-feedback (duration 00:00:01) [common]
11850 01:26:35.232117 end: 5 finalize (duration 00:00:01) [common]
11851 01:26:35.232238 Cleaning after the job
11852 01:26:35.232340 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/ramdisk
11853 01:26:35.235065 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/kernel
11854 01:26:35.247371 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/dtb
11855 01:26:35.247609 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/nfsrootfs
11856 01:26:35.321800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368520/tftp-deploy-fcn7bodx/modules
11857 01:26:35.329092 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11368520
11858 01:26:35.710601 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11368520
11859 01:26:35.710785 Job finished correctly