Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 136
- Boot result: PASS
- Warnings: 1
- Errors: 0
- Kernel Warnings: 25
1 01:23:06.911287 lava-dispatcher, installed at version: 2023.06
2 01:23:06.911510 start: 0 validate
3 01:23:06.911651 Start time: 2023-08-28 01:23:06.911643+00:00 (UTC)
4 01:23:06.911793 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:23:06.911943 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 01:23:07.174850 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:23:07.175643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:23:07.446724 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:23:07.447494 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:23:23.426380 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:23:23.427063 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.46-cip4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:23:23.965139 validate duration: 17.05
14 01:23:23.966412 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:23:23.966953 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:23:23.967445 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:23:23.968187 Not decompressing ramdisk as can be used compressed.
18 01:23:23.968715 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 01:23:23.969094 saving as /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/ramdisk/rootfs.cpio.gz
20 01:23:23.969456 total size: 84918747 (80 MB)
21 01:23:26.587402 progress 0 % (0 MB)
22 01:23:26.648807 progress 5 % (4 MB)
23 01:23:26.671703 progress 10 % (8 MB)
24 01:23:26.693527 progress 15 % (12 MB)
25 01:23:26.715491 progress 20 % (16 MB)
26 01:23:26.737646 progress 25 % (20 MB)
27 01:23:26.759746 progress 30 % (24 MB)
28 01:23:26.781473 progress 35 % (28 MB)
29 01:23:26.802882 progress 40 % (32 MB)
30 01:23:26.824814 progress 45 % (36 MB)
31 01:23:26.847060 progress 50 % (40 MB)
32 01:23:26.869433 progress 55 % (44 MB)
33 01:23:26.891017 progress 60 % (48 MB)
34 01:23:26.914226 progress 65 % (52 MB)
35 01:23:26.936181 progress 70 % (56 MB)
36 01:23:26.958185 progress 75 % (60 MB)
37 01:23:26.980563 progress 80 % (64 MB)
38 01:23:27.002326 progress 85 % (68 MB)
39 01:23:27.024037 progress 90 % (72 MB)
40 01:23:27.045981 progress 95 % (76 MB)
41 01:23:27.067599 progress 100 % (80 MB)
42 01:23:27.067824 80 MB downloaded in 3.10 s (26.14 MB/s)
43 01:23:27.067996 end: 1.1.1 http-download (duration 00:00:03) [common]
45 01:23:27.068235 end: 1.1 download-retry (duration 00:00:03) [common]
46 01:23:27.068321 start: 1.2 download-retry (timeout 00:09:57) [common]
47 01:23:27.068403 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 01:23:27.068543 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:23:27.068612 saving as /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/kernel/Image
50 01:23:27.068679 total size: 49220096 (46 MB)
51 01:23:27.068740 No compression specified
52 01:23:27.069854 progress 0 % (0 MB)
53 01:23:27.082765 progress 5 % (2 MB)
54 01:23:27.095478 progress 10 % (4 MB)
55 01:23:27.108193 progress 15 % (7 MB)
56 01:23:27.120766 progress 20 % (9 MB)
57 01:23:27.133519 progress 25 % (11 MB)
58 01:23:27.146324 progress 30 % (14 MB)
59 01:23:27.158990 progress 35 % (16 MB)
60 01:23:27.171768 progress 40 % (18 MB)
61 01:23:27.184874 progress 45 % (21 MB)
62 01:23:27.197675 progress 50 % (23 MB)
63 01:23:27.210438 progress 55 % (25 MB)
64 01:23:27.223454 progress 60 % (28 MB)
65 01:23:27.236212 progress 65 % (30 MB)
66 01:23:27.249389 progress 70 % (32 MB)
67 01:23:27.262170 progress 75 % (35 MB)
68 01:23:27.274884 progress 80 % (37 MB)
69 01:23:27.288028 progress 85 % (39 MB)
70 01:23:27.301082 progress 90 % (42 MB)
71 01:23:27.313632 progress 95 % (44 MB)
72 01:23:27.326485 progress 100 % (46 MB)
73 01:23:27.326638 46 MB downloaded in 0.26 s (181.97 MB/s)
74 01:23:27.326790 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:23:27.327020 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:23:27.327106 start: 1.3 download-retry (timeout 00:09:57) [common]
78 01:23:27.327199 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 01:23:27.327341 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:23:27.327414 saving as /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/dtb/mt8192-asurada-spherion-r0.dtb
81 01:23:27.327474 total size: 47278 (0 MB)
82 01:23:27.327535 No compression specified
83 01:23:27.328645 progress 69 % (0 MB)
84 01:23:27.328964 progress 100 % (0 MB)
85 01:23:27.329119 0 MB downloaded in 0.00 s (27.45 MB/s)
86 01:23:27.329257 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:23:27.329530 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:23:27.329614 start: 1.4 download-retry (timeout 00:09:57) [common]
90 01:23:27.329700 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 01:23:27.329814 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.46-cip4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:23:27.329882 saving as /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/modules/modules.tar
93 01:23:27.329941 total size: 8616896 (8 MB)
94 01:23:27.330001 Using unxz to decompress xz
95 01:23:27.334553 progress 0 % (0 MB)
96 01:23:27.355573 progress 5 % (0 MB)
97 01:23:27.379431 progress 10 % (0 MB)
98 01:23:27.408880 progress 15 % (1 MB)
99 01:23:27.437308 progress 20 % (1 MB)
100 01:23:27.460986 progress 25 % (2 MB)
101 01:23:27.484533 progress 30 % (2 MB)
102 01:23:27.511007 progress 35 % (2 MB)
103 01:23:27.535778 progress 40 % (3 MB)
104 01:23:27.561948 progress 45 % (3 MB)
105 01:23:27.587366 progress 50 % (4 MB)
106 01:23:27.612109 progress 55 % (4 MB)
107 01:23:27.637323 progress 60 % (4 MB)
108 01:23:27.661845 progress 65 % (5 MB)
109 01:23:27.687499 progress 70 % (5 MB)
110 01:23:27.712566 progress 75 % (6 MB)
111 01:23:27.736600 progress 80 % (6 MB)
112 01:23:27.762690 progress 85 % (7 MB)
113 01:23:27.788311 progress 90 % (7 MB)
114 01:23:27.812027 progress 95 % (7 MB)
115 01:23:27.838472 progress 100 % (8 MB)
116 01:23:27.844744 8 MB downloaded in 0.51 s (15.96 MB/s)
117 01:23:27.844987 end: 1.4.1 http-download (duration 00:00:01) [common]
119 01:23:27.845243 end: 1.4 download-retry (duration 00:00:01) [common]
120 01:23:27.845335 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 01:23:27.845429 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 01:23:27.845509 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:23:27.845600 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 01:23:27.845829 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi
125 01:23:27.845965 makedir: /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin
126 01:23:27.846069 makedir: /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/tests
127 01:23:27.846167 makedir: /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/results
128 01:23:27.846285 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-add-keys
129 01:23:27.846430 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-add-sources
130 01:23:27.846561 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-background-process-start
131 01:23:27.846688 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-background-process-stop
132 01:23:27.846813 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-common-functions
133 01:23:27.846936 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-echo-ipv4
134 01:23:27.847060 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-install-packages
135 01:23:27.847185 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-installed-packages
136 01:23:27.847308 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-os-build
137 01:23:27.847434 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-probe-channel
138 01:23:27.847557 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-probe-ip
139 01:23:27.847680 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-target-ip
140 01:23:27.847803 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-target-mac
141 01:23:27.847926 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-target-storage
142 01:23:27.848055 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-case
143 01:23:27.848181 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-event
144 01:23:27.848302 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-feedback
145 01:23:27.848426 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-raise
146 01:23:27.848550 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-reference
147 01:23:27.848678 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-runner
148 01:23:27.848838 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-set
149 01:23:27.848964 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-test-shell
150 01:23:27.849090 Updating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-install-packages (oe)
151 01:23:27.849243 Updating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/bin/lava-installed-packages (oe)
152 01:23:27.849368 Creating /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/environment
153 01:23:27.849466 LAVA metadata
154 01:23:27.849547 - LAVA_JOB_ID=11368532
155 01:23:27.849610 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:23:27.849710 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 01:23:27.849775 skipped lava-vland-overlay
158 01:23:27.849847 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:23:27.849929 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 01:23:27.849990 skipped lava-multinode-overlay
161 01:23:27.850063 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:23:27.850144 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 01:23:27.850215 Loading test definitions
164 01:23:27.850301 start: 1.5.2.3.1 git-repo-action (timeout 00:09:56) [common]
165 01:23:27.850373 Using /lava-11368532 at stage 0
166 01:23:27.850467 Fetching tests from https://github.com/kernelci/kernelci-core
167 01:23:27.850545 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/0/tests/0_sleep'
168 01:23:28.530983 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/0/tests/0_sleep
169 01:23:28.532317 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 01:23:28.532763 uuid=11368532_1.5.2.3.1 testdef=None
171 01:23:28.532910 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 01:23:28.533157 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
174 01:23:28.533717 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 01:23:28.533935 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
177 01:23:28.534620 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 01:23:28.534849 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
180 01:23:28.535503 runner path: /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/0/tests/0_sleep test_uuid 11368532_1.5.2.3.1
181 01:23:28.535586 sleep_params='mem freeze'
182 01:23:28.535726 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 01:23:28.535936 Creating lava-test-runner.conf files
185 01:23:28.535997 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11368532/lava-overlay-rg6x4nxi/lava-11368532/0 for stage 0
186 01:23:28.536086 - 0_sleep
187 01:23:28.536192 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 01:23:28.536277 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
189 01:23:28.659886 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 01:23:28.660044 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
191 01:23:28.660134 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 01:23:28.660229 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 01:23:28.660315 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
194 01:23:31.114619 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 01:23:31.115019 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
196 01:23:31.115138 extracting modules file /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11368532/extract-overlay-ramdisk-7clksxjz/ramdisk
197 01:23:31.340339 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 01:23:31.340517 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
199 01:23:31.340616 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368532/compress-overlay-rjpigrll/overlay-1.5.2.4.tar.gz to ramdisk
200 01:23:31.340802 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11368532/compress-overlay-rjpigrll/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11368532/extract-overlay-ramdisk-7clksxjz/ramdisk
201 01:23:31.433334 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 01:23:31.433490 start: 1.5.6 configure-preseed-file (timeout 00:09:53) [common]
203 01:23:31.433587 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 01:23:31.433673 start: 1.5.7 compress-ramdisk (timeout 00:09:53) [common]
205 01:23:31.433754 Building ramdisk /var/lib/lava/dispatcher/tmp/11368532/extract-overlay-ramdisk-7clksxjz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11368532/extract-overlay-ramdisk-7clksxjz/ramdisk
206 01:23:32.946662 >> 563307 blocks
207 01:23:42.408834 rename /var/lib/lava/dispatcher/tmp/11368532/extract-overlay-ramdisk-7clksxjz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/ramdisk/ramdisk.cpio.gz
208 01:23:42.409279 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 01:23:42.409401 start: 1.5.8 prepare-kernel (timeout 00:09:42) [common]
210 01:23:42.409507 start: 1.5.8.1 prepare-fit (timeout 00:09:42) [common]
211 01:23:42.409620 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/kernel/Image'
212 01:23:54.734631 Returned 0 in 12 seconds
213 01:23:54.835903 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/kernel/image.itb
214 01:23:56.193829 output: FIT description: Kernel Image image with one or more FDT blobs
215 01:23:56.194194 output: Created: Mon Aug 28 02:23:55 2023
216 01:23:56.194271 output: Image 0 (kernel-1)
217 01:23:56.194334 output: Description:
218 01:23:56.194396 output: Created: Mon Aug 28 02:23:55 2023
219 01:23:56.194456 output: Type: Kernel Image
220 01:23:56.194518 output: Compression: lzma compressed
221 01:23:56.194576 output: Data Size: 11038667 Bytes = 10779.95 KiB = 10.53 MiB
222 01:23:56.194635 output: Architecture: AArch64
223 01:23:56.194694 output: OS: Linux
224 01:23:56.194750 output: Load Address: 0x00000000
225 01:23:56.194802 output: Entry Point: 0x00000000
226 01:23:56.194854 output: Hash algo: crc32
227 01:23:56.194905 output: Hash value: 3affb6e1
228 01:23:56.194957 output: Image 1 (fdt-1)
229 01:23:56.195008 output: Description: mt8192-asurada-spherion-r0
230 01:23:56.195059 output: Created: Mon Aug 28 02:23:55 2023
231 01:23:56.195111 output: Type: Flat Device Tree
232 01:23:56.195162 output: Compression: uncompressed
233 01:23:56.195213 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 01:23:56.195265 output: Architecture: AArch64
235 01:23:56.195315 output: Hash algo: crc32
236 01:23:56.195365 output: Hash value: cc4352de
237 01:23:56.195416 output: Image 2 (ramdisk-1)
238 01:23:56.195466 output: Description: unavailable
239 01:23:56.195516 output: Created: Mon Aug 28 02:23:55 2023
240 01:23:56.195567 output: Type: RAMDisk Image
241 01:23:56.195618 output: Compression: Unknown Compression
242 01:23:56.195668 output: Data Size: 98317070 Bytes = 96012.76 KiB = 93.76 MiB
243 01:23:56.195720 output: Architecture: AArch64
244 01:23:56.195770 output: OS: Linux
245 01:23:56.195821 output: Load Address: unavailable
246 01:23:56.195871 output: Entry Point: unavailable
247 01:23:56.195922 output: Hash algo: crc32
248 01:23:56.195972 output: Hash value: 669143a7
249 01:23:56.196023 output: Default Configuration: 'conf-1'
250 01:23:56.196074 output: Configuration 0 (conf-1)
251 01:23:56.196124 output: Description: mt8192-asurada-spherion-r0
252 01:23:56.196175 output: Kernel: kernel-1
253 01:23:56.196225 output: Init Ramdisk: ramdisk-1
254 01:23:56.196276 output: FDT: fdt-1
255 01:23:56.196326 output: Loadables: kernel-1
256 01:23:56.196377 output:
257 01:23:56.196577 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 01:23:56.196679 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 01:23:56.196825 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 01:23:56.196921 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:28) [common]
261 01:23:56.196998 No LXC device requested
262 01:23:56.197076 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 01:23:56.197159 start: 1.7 deploy-device-env (timeout 00:09:28) [common]
264 01:23:56.197236 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 01:23:56.197304 Checking files for TFTP limit of 4294967296 bytes.
266 01:23:56.197805 end: 1 tftp-deploy (duration 00:00:32) [common]
267 01:23:56.197914 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 01:23:56.198000 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 01:23:56.198121 substitutions:
270 01:23:56.198188 - {DTB}: 11368532/tftp-deploy-oxmtxrpo/dtb/mt8192-asurada-spherion-r0.dtb
271 01:23:56.198251 - {INITRD}: 11368532/tftp-deploy-oxmtxrpo/ramdisk/ramdisk.cpio.gz
272 01:23:56.198309 - {KERNEL}: 11368532/tftp-deploy-oxmtxrpo/kernel/Image
273 01:23:56.198364 - {LAVA_MAC}: None
274 01:23:56.198418 - {PRESEED_CONFIG}: None
275 01:23:56.198472 - {PRESEED_LOCAL}: None
276 01:23:56.198525 - {RAMDISK}: 11368532/tftp-deploy-oxmtxrpo/ramdisk/ramdisk.cpio.gz
277 01:23:56.198578 - {ROOT_PART}: None
278 01:23:56.198631 - {ROOT}: None
279 01:23:56.198683 - {SERVER_IP}: 192.168.201.1
280 01:23:56.198735 - {TEE}: None
281 01:23:56.198787 Parsed boot commands:
282 01:23:56.198838 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 01:23:56.199016 Parsed boot commands: tftpboot 192.168.201.1 11368532/tftp-deploy-oxmtxrpo/kernel/image.itb 11368532/tftp-deploy-oxmtxrpo/kernel/cmdline
284 01:23:56.199108 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 01:23:56.199189 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 01:23:56.199283 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 01:23:56.199369 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 01:23:56.199438 Not connected, no need to disconnect.
289 01:23:56.199510 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 01:23:56.199589 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 01:23:56.199654 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
292 01:23:56.203711 Setting prompt string to ['lava-test: # ']
293 01:23:56.204073 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 01:23:56.204178 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 01:23:56.204280 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 01:23:56.204373 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 01:23:56.204604 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 01:24:01.340588 >> Command sent successfully.
299 01:24:01.343039 Returned 0 in 5 seconds
300 01:24:01.443780 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 01:24:01.445253 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 01:24:01.445868 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 01:24:01.446424 Setting prompt string to 'Starting depthcharge on Spherion...'
305 01:24:01.446771 Changing prompt to 'Starting depthcharge on Spherion...'
306 01:24:01.447134 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 01:24:01.448300 [Enter `^Ec?' for help]
308 01:24:01.618054
309 01:24:01.618636
310 01:24:01.618740 F0: 102B 0000
311 01:24:01.618809
312 01:24:01.618869 F3: 1001 0000 [0200]
313 01:24:01.618927
314 01:24:01.621305 F3: 1001 0000
315 01:24:01.621387
316 01:24:01.621452 F7: 102D 0000
317 01:24:01.621512
318 01:24:01.624161 F1: 0000 0000
319 01:24:01.624243
320 01:24:01.624307 V0: 0000 0000 [0001]
321 01:24:01.624367
322 01:24:01.627590 00: 0007 8000
323 01:24:01.627677
324 01:24:01.627752 01: 0000 0000
325 01:24:01.627815
326 01:24:01.631058 BP: 0C00 0209 [0000]
327 01:24:01.631140
328 01:24:01.631204 G0: 1182 0000
329 01:24:01.631264
330 01:24:01.631321 EC: 0000 0021 [4000]
331 01:24:01.634738
332 01:24:01.634819 S7: 0000 0000 [0000]
333 01:24:01.634883
334 01:24:01.637565 CC: 0000 0000 [0001]
335 01:24:01.637699
336 01:24:01.637812 T0: 0000 0040 [010F]
337 01:24:01.637900
338 01:24:01.637986 Jump to BL
339 01:24:01.641077
340 01:24:01.664542
341 01:24:01.664657
342 01:24:01.664749
343 01:24:01.671956 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 01:24:01.675634 ARM64: Exception handlers installed.
345 01:24:01.679326 ARM64: Testing exception
346 01:24:01.682651 ARM64: Done test exception
347 01:24:01.689475 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 01:24:01.700059 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 01:24:01.707214 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 01:24:01.717146 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 01:24:01.723823 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 01:24:01.730696 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 01:24:01.741266 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 01:24:01.748291 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 01:24:01.767313 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 01:24:01.770524 WDT: Last reset was cold boot
357 01:24:01.774239 SPI1(PAD0) initialized at 2873684 Hz
358 01:24:01.777377 SPI5(PAD0) initialized at 992727 Hz
359 01:24:01.780462 VBOOT: Loading verstage.
360 01:24:01.787280 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 01:24:01.791066 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 01:24:01.793925 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 01:24:01.797246 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 01:24:01.804657 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 01:24:01.811576 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 01:24:01.822292 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 01:24:01.822401
368 01:24:01.822471
369 01:24:01.832323 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 01:24:01.835945 ARM64: Exception handlers installed.
371 01:24:01.839688 ARM64: Testing exception
372 01:24:01.839770 ARM64: Done test exception
373 01:24:01.845808 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 01:24:01.849290 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 01:24:01.862984 Probing TPM: . done!
376 01:24:01.863067 TPM ready after 0 ms
377 01:24:01.868325 Connected to device vid:did:rid of 1ae0:0028:00
378 01:24:01.879124 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 01:24:01.935060 Initialized TPM device CR50 revision 0
380 01:24:01.946703 tlcl_send_startup: Startup return code is 0
381 01:24:01.946797 TPM: setup succeeded
382 01:24:01.957968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 01:24:01.966896 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 01:24:01.978244 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 01:24:01.987673 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 01:24:01.991258 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 01:24:01.998950 in-header: 03 07 00 00 08 00 00 00
388 01:24:02.002041 in-data: aa e4 47 04 13 02 00 00
389 01:24:02.005885 Chrome EC: UHEPI supported
390 01:24:02.013324 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 01:24:02.017277 in-header: 03 ad 00 00 08 00 00 00
392 01:24:02.020568 in-data: 00 20 20 08 00 00 00 00
393 01:24:02.020651 Phase 1
394 01:24:02.024287 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 01:24:02.031854 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 01:24:02.036081 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 01:24:02.039096 Recovery requested (1009000e)
398 01:24:02.047069 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 01:24:02.052776 tlcl_extend: response is 0
400 01:24:02.062103 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 01:24:02.067746 tlcl_extend: response is 0
402 01:24:02.074820 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 01:24:02.094664 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 01:24:02.101081 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 01:24:02.101164
406 01:24:02.101228
407 01:24:02.112187 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 01:24:02.115438 ARM64: Exception handlers installed.
409 01:24:02.115521 ARM64: Testing exception
410 01:24:02.118809 ARM64: Done test exception
411 01:24:02.139947 pmic_efuse_setting: Set efuses in 11 msecs
412 01:24:02.143571 pmwrap_interface_init: Select PMIF_VLD_RDY
413 01:24:02.150364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 01:24:02.153640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 01:24:02.160384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 01:24:02.164045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 01:24:02.167779 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 01:24:02.175235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 01:24:02.177867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 01:24:02.181522 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 01:24:02.188695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 01:24:02.192813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 01:24:02.195962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 01:24:02.199720 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 01:24:02.207247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 01:24:02.211328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 01:24:02.218119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 01:24:02.226038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 01:24:02.229245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 01:24:02.236919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 01:24:02.240381 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 01:24:02.247875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 01:24:02.251464 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 01:24:02.258691 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 01:24:02.262549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 01:24:02.269628 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 01:24:02.273765 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 01:24:02.280964 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 01:24:02.284449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 01:24:02.288035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 01:24:02.295530 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 01:24:02.299134 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 01:24:02.302899 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 01:24:02.310202 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 01:24:02.313792 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 01:24:02.317545 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 01:24:02.324918 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 01:24:02.328528 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 01:24:02.336370 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 01:24:02.339706 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 01:24:02.343536 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 01:24:02.347226 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 01:24:02.350497 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 01:24:02.358571 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 01:24:02.361578 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 01:24:02.365579 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 01:24:02.369613 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 01:24:02.373038 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 01:24:02.377070 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 01:24:02.381165 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 01:24:02.388341 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 01:24:02.391626 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 01:24:02.395304 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 01:24:02.402926 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 01:24:02.410118 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 01:24:02.417099 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 01:24:02.424274 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 01:24:02.431120 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 01:24:02.438505 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 01:24:02.442500 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 01:24:02.446649 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 01:24:02.453274 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x3a
473 01:24:02.456945 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 01:24:02.464849 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 01:24:02.468048 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 01:24:02.477841 [RTC]rtc_get_frequency_meter,154: input=15, output=791
477 01:24:02.487409 [RTC]rtc_get_frequency_meter,154: input=23, output=979
478 01:24:02.496567 [RTC]rtc_get_frequency_meter,154: input=19, output=884
479 01:24:02.506407 [RTC]rtc_get_frequency_meter,154: input=17, output=837
480 01:24:02.515845 [RTC]rtc_get_frequency_meter,154: input=16, output=813
481 01:24:02.525104 [RTC]rtc_get_frequency_meter,154: input=15, output=791
482 01:24:02.534728 [RTC]rtc_get_frequency_meter,154: input=16, output=814
483 01:24:02.537984 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 01:24:02.545181 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 01:24:02.549306 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 01:24:02.552979 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 01:24:02.556632 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 01:24:02.560618 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 01:24:02.564093 ADC[4]: Raw value=901697 ID=7
490 01:24:02.567797 ADC[3]: Raw value=213336 ID=1
491 01:24:02.567872 RAM Code: 0x71
492 01:24:02.572175 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 01:24:02.578685 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 01:24:02.586277 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 01:24:02.593557 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 01:24:02.597205 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 01:24:02.600672 in-header: 03 07 00 00 08 00 00 00
498 01:24:02.600796 in-data: aa e4 47 04 13 02 00 00
499 01:24:02.604495 Chrome EC: UHEPI supported
500 01:24:02.611949 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 01:24:02.615811 in-header: 03 ed 00 00 08 00 00 00
502 01:24:02.619359 in-data: 80 20 60 08 00 00 00 00
503 01:24:02.622978 MRC: failed to locate region type 0.
504 01:24:02.626962 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 01:24:02.630392 DRAM-K: Running full calibration
506 01:24:02.638173 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 01:24:02.638257 header.status = 0x0
508 01:24:02.641438 header.version = 0x6 (expected: 0x6)
509 01:24:02.645883 header.size = 0xd00 (expected: 0xd00)
510 01:24:02.649102 header.flags = 0x0
511 01:24:02.652286 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 01:24:02.672265 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
513 01:24:02.679497 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 01:24:02.682846 dram_init: ddr_geometry: 2
515 01:24:02.682928 [EMI] MDL number = 2
516 01:24:02.686801 [EMI] Get MDL freq = 0
517 01:24:02.686883 dram_init: ddr_type: 0
518 01:24:02.690393 is_discrete_lpddr4: 1
519 01:24:02.694093 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 01:24:02.694176
521 01:24:02.694239
522 01:24:02.694298 [Bian_co] ETT version 0.0.0.1
523 01:24:02.701740 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 01:24:02.701823
525 01:24:02.705790 dramc_set_vcore_voltage set vcore to 650000
526 01:24:02.705872 Read voltage for 800, 4
527 01:24:02.705936 Vio18 = 0
528 01:24:02.709160 Vcore = 650000
529 01:24:02.709242 Vdram = 0
530 01:24:02.709307 Vddq = 0
531 01:24:02.712956 Vmddr = 0
532 01:24:02.713052 dram_init: config_dvfs: 1
533 01:24:02.720508 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 01:24:02.724723 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 01:24:02.728435 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 01:24:02.731680 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 01:24:02.734836 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 01:24:02.738444 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 01:24:02.741462 MEM_TYPE=3, freq_sel=18
540 01:24:02.744753 sv_algorithm_assistance_LP4_1600
541 01:24:02.748637 ============ PULL DRAM RESETB DOWN ============
542 01:24:02.751463 ========== PULL DRAM RESETB DOWN end =========
543 01:24:02.758585 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 01:24:02.761951 ===================================
545 01:24:02.762035 LPDDR4 DRAM CONFIGURATION
546 01:24:02.764923 ===================================
547 01:24:02.768277 EX_ROW_EN[0] = 0x0
548 01:24:02.771883 EX_ROW_EN[1] = 0x0
549 01:24:02.771967 LP4Y_EN = 0x0
550 01:24:02.774968 WORK_FSP = 0x0
551 01:24:02.775051 WL = 0x2
552 01:24:02.778483 RL = 0x2
553 01:24:02.778566 BL = 0x2
554 01:24:02.781946 RPST = 0x0
555 01:24:02.782029 RD_PRE = 0x0
556 01:24:02.785001 WR_PRE = 0x1
557 01:24:02.785084 WR_PST = 0x0
558 01:24:02.788636 DBI_WR = 0x0
559 01:24:02.788726 DBI_RD = 0x0
560 01:24:02.791778 OTF = 0x1
561 01:24:02.795301 ===================================
562 01:24:02.798532 ===================================
563 01:24:02.798615 ANA top config
564 01:24:02.802486 ===================================
565 01:24:02.805339 DLL_ASYNC_EN = 0
566 01:24:02.808871 ALL_SLAVE_EN = 1
567 01:24:02.808954 NEW_RANK_MODE = 1
568 01:24:02.812291 DLL_IDLE_MODE = 1
569 01:24:02.815556 LP45_APHY_COMB_EN = 1
570 01:24:02.818810 TX_ODT_DIS = 1
571 01:24:02.818894 NEW_8X_MODE = 1
572 01:24:02.822201 ===================================
573 01:24:02.825455 ===================================
574 01:24:02.828658 data_rate = 1600
575 01:24:02.832253 CKR = 1
576 01:24:02.835889 DQ_P2S_RATIO = 8
577 01:24:02.838894 ===================================
578 01:24:02.842610 CA_P2S_RATIO = 8
579 01:24:02.845705 DQ_CA_OPEN = 0
580 01:24:02.845788 DQ_SEMI_OPEN = 0
581 01:24:02.849307 CA_SEMI_OPEN = 0
582 01:24:02.852501 CA_FULL_RATE = 0
583 01:24:02.855752 DQ_CKDIV4_EN = 1
584 01:24:02.859476 CA_CKDIV4_EN = 1
585 01:24:02.859559 CA_PREDIV_EN = 0
586 01:24:02.862525 PH8_DLY = 0
587 01:24:02.866143 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 01:24:02.869194 DQ_AAMCK_DIV = 4
589 01:24:02.872878 CA_AAMCK_DIV = 4
590 01:24:02.876327 CA_ADMCK_DIV = 4
591 01:24:02.876410 DQ_TRACK_CA_EN = 0
592 01:24:02.879255 CA_PICK = 800
593 01:24:02.883019 CA_MCKIO = 800
594 01:24:02.886236 MCKIO_SEMI = 0
595 01:24:02.889986 PLL_FREQ = 3068
596 01:24:02.893611 DQ_UI_PI_RATIO = 32
597 01:24:02.893695 CA_UI_PI_RATIO = 0
598 01:24:02.897639 ===================================
599 01:24:02.901273 ===================================
600 01:24:02.905069 memory_type:LPDDR4
601 01:24:02.905152 GP_NUM : 10
602 01:24:02.908430 SRAM_EN : 1
603 01:24:02.908513 MD32_EN : 0
604 01:24:02.912284 ===================================
605 01:24:02.915552 [ANA_INIT] >>>>>>>>>>>>>>
606 01:24:02.919151 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 01:24:02.922360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 01:24:02.926342 ===================================
609 01:24:02.926426 data_rate = 1600,PCW = 0X7600
610 01:24:02.929777 ===================================
611 01:24:02.932935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 01:24:02.940192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 01:24:02.946331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 01:24:02.950185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 01:24:02.953025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 01:24:02.956353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 01:24:02.959773 [ANA_INIT] flow start
618 01:24:02.959857 [ANA_INIT] PLL >>>>>>>>
619 01:24:02.963312 [ANA_INIT] PLL <<<<<<<<
620 01:24:02.966599 [ANA_INIT] MIDPI >>>>>>>>
621 01:24:02.966682 [ANA_INIT] MIDPI <<<<<<<<
622 01:24:02.969886 [ANA_INIT] DLL >>>>>>>>
623 01:24:02.973133 [ANA_INIT] flow end
624 01:24:02.976697 ============ LP4 DIFF to SE enter ============
625 01:24:02.980254 ============ LP4 DIFF to SE exit ============
626 01:24:02.983305 [ANA_INIT] <<<<<<<<<<<<<
627 01:24:02.987117 [Flow] Enable top DCM control >>>>>
628 01:24:02.990243 [Flow] Enable top DCM control <<<<<
629 01:24:02.993501 Enable DLL master slave shuffle
630 01:24:02.996775 ==============================================================
631 01:24:02.999932 Gating Mode config
632 01:24:03.006794 ==============================================================
633 01:24:03.006877 Config description:
634 01:24:03.016838 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 01:24:03.023670 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 01:24:03.026865 SELPH_MODE 0: By rank 1: By Phase
637 01:24:03.033535 ==============================================================
638 01:24:03.037124 GAT_TRACK_EN = 1
639 01:24:03.040477 RX_GATING_MODE = 2
640 01:24:03.043599 RX_GATING_TRACK_MODE = 2
641 01:24:03.046917 SELPH_MODE = 1
642 01:24:03.047000 PICG_EARLY_EN = 1
643 01:24:03.050507 VALID_LAT_VALUE = 1
644 01:24:03.057432 ==============================================================
645 01:24:03.060482 Enter into Gating configuration >>>>
646 01:24:03.064439 Exit from Gating configuration <<<<
647 01:24:03.067696 Enter into DVFS_PRE_config >>>>>
648 01:24:03.077434 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 01:24:03.080671 Exit from DVFS_PRE_config <<<<<
650 01:24:03.084034 Enter into PICG configuration >>>>
651 01:24:03.087578 Exit from PICG configuration <<<<
652 01:24:03.090683 [RX_INPUT] configuration >>>>>
653 01:24:03.094166 [RX_INPUT] configuration <<<<<
654 01:24:03.097489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 01:24:03.104639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 01:24:03.108540 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 01:24:03.115843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 01:24:03.122163 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 01:24:03.128795 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 01:24:03.132281 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 01:24:03.135521 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 01:24:03.138938 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 01:24:03.145954 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 01:24:03.148971 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 01:24:03.152276 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 01:24:03.155915 ===================================
667 01:24:03.159129 LPDDR4 DRAM CONFIGURATION
668 01:24:03.162495 ===================================
669 01:24:03.165816 EX_ROW_EN[0] = 0x0
670 01:24:03.165900 EX_ROW_EN[1] = 0x0
671 01:24:03.169082 LP4Y_EN = 0x0
672 01:24:03.169165 WORK_FSP = 0x0
673 01:24:03.172431 WL = 0x2
674 01:24:03.172513 RL = 0x2
675 01:24:03.175816 BL = 0x2
676 01:24:03.175899 RPST = 0x0
677 01:24:03.179103 RD_PRE = 0x0
678 01:24:03.179187 WR_PRE = 0x1
679 01:24:03.182543 WR_PST = 0x0
680 01:24:03.182627 DBI_WR = 0x0
681 01:24:03.186064 DBI_RD = 0x0
682 01:24:03.186147 OTF = 0x1
683 01:24:03.189299 ===================================
684 01:24:03.192539 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 01:24:03.199589 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 01:24:03.203164 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 01:24:03.206540 ===================================
688 01:24:03.209633 LPDDR4 DRAM CONFIGURATION
689 01:24:03.213206 ===================================
690 01:24:03.213290 EX_ROW_EN[0] = 0x10
691 01:24:03.215988 EX_ROW_EN[1] = 0x0
692 01:24:03.216102 LP4Y_EN = 0x0
693 01:24:03.219280 WORK_FSP = 0x0
694 01:24:03.219363 WL = 0x2
695 01:24:03.223114 RL = 0x2
696 01:24:03.223197 BL = 0x2
697 01:24:03.226365 RPST = 0x0
698 01:24:03.226448 RD_PRE = 0x0
699 01:24:03.229366 WR_PRE = 0x1
700 01:24:03.232955 WR_PST = 0x0
701 01:24:03.233037 DBI_WR = 0x0
702 01:24:03.236724 DBI_RD = 0x0
703 01:24:03.236807 OTF = 0x1
704 01:24:03.239418 ===================================
705 01:24:03.246382 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 01:24:03.249787 nWR fixed to 40
707 01:24:03.252896 [ModeRegInit_LP4] CH0 RK0
708 01:24:03.253007 [ModeRegInit_LP4] CH0 RK1
709 01:24:03.256331 [ModeRegInit_LP4] CH1 RK0
710 01:24:03.259774 [ModeRegInit_LP4] CH1 RK1
711 01:24:03.259857 match AC timing 13
712 01:24:03.266469 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 01:24:03.269952 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 01:24:03.273158 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 01:24:03.280328 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 01:24:03.283290 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 01:24:03.283374 [EMI DOE] emi_dcm 0
718 01:24:03.289996 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 01:24:03.290079 ==
720 01:24:03.293432 Dram Type= 6, Freq= 0, CH_0, rank 0
721 01:24:03.296955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 01:24:03.297039 ==
723 01:24:03.303283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 01:24:03.306807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 01:24:03.317024 [CA 0] Center 37 (7~68) winsize 62
726 01:24:03.320708 [CA 1] Center 37 (6~68) winsize 63
727 01:24:03.323723 [CA 2] Center 35 (5~66) winsize 62
728 01:24:03.327220 [CA 3] Center 34 (4~65) winsize 62
729 01:24:03.330674 [CA 4] Center 34 (3~65) winsize 63
730 01:24:03.333879 [CA 5] Center 34 (4~64) winsize 61
731 01:24:03.333963
732 01:24:03.337526 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 01:24:03.337610
734 01:24:03.340507 [CATrainingPosCal] consider 1 rank data
735 01:24:03.343908 u2DelayCellTimex100 = 270/100 ps
736 01:24:03.347460 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
737 01:24:03.350727 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
738 01:24:03.353951 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
739 01:24:03.361249 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
740 01:24:03.364227 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
741 01:24:03.367793 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
742 01:24:03.367877
743 01:24:03.370823 CA PerBit enable=1, Macro0, CA PI delay=34
744 01:24:03.370907
745 01:24:03.374483 [CBTSetCACLKResult] CA Dly = 34
746 01:24:03.374568 CS Dly: 4 (0~35)
747 01:24:03.374669 ==
748 01:24:03.377715 Dram Type= 6, Freq= 0, CH_0, rank 1
749 01:24:03.381460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 01:24:03.384397 ==
751 01:24:03.388400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 01:24:03.394407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 01:24:03.403742 [CA 0] Center 37 (6~68) winsize 63
754 01:24:03.406839 [CA 1] Center 37 (7~68) winsize 62
755 01:24:03.410171 [CA 2] Center 35 (5~66) winsize 62
756 01:24:03.413568 [CA 3] Center 35 (5~65) winsize 61
757 01:24:03.417106 [CA 4] Center 33 (3~64) winsize 62
758 01:24:03.420241 [CA 5] Center 33 (3~64) winsize 62
759 01:24:03.420324
760 01:24:03.423407 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 01:24:03.423491
762 01:24:03.426634 [CATrainingPosCal] consider 2 rank data
763 01:24:03.430010 u2DelayCellTimex100 = 270/100 ps
764 01:24:03.433482 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 01:24:03.437010 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 01:24:03.440481 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 01:24:03.446865 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
768 01:24:03.450576 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 01:24:03.453674 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
770 01:24:03.453758
771 01:24:03.457105 CA PerBit enable=1, Macro0, CA PI delay=33
772 01:24:03.457189
773 01:24:03.460209 [CBTSetCACLKResult] CA Dly = 33
774 01:24:03.460293 CS Dly: 5 (0~37)
775 01:24:03.460358
776 01:24:03.463905 ----->DramcWriteLeveling(PI) begin...
777 01:24:03.463992 ==
778 01:24:03.466958 Dram Type= 6, Freq= 0, CH_0, rank 0
779 01:24:03.474372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 01:24:03.474456 ==
781 01:24:03.474522 Write leveling (Byte 0): 28 => 28
782 01:24:03.477954 Write leveling (Byte 1): 32 => 32
783 01:24:03.481815 DramcWriteLeveling(PI) end<-----
784 01:24:03.481897
785 01:24:03.481962 ==
786 01:24:03.485668 Dram Type= 6, Freq= 0, CH_0, rank 0
787 01:24:03.489098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 01:24:03.489182 ==
789 01:24:03.492702 [Gating] SW mode calibration
790 01:24:03.499089 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 01:24:03.506892 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 01:24:03.510324 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 01:24:03.513861 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 01:24:03.516601 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 01:24:03.523434 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:24:03.526909 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:24:03.530022 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:24:03.537022 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:24:03.540558 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:24:03.543949 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:24:03.550680 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:24:03.554327 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 01:24:03.557457 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 01:24:03.560570 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 01:24:03.567447 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:24:03.571013 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:24:03.574058 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:24:03.580798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:24:03.583945 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:24:03.587422 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 01:24:03.594574 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
812 01:24:03.597379 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 01:24:03.600861 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 01:24:03.607515 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 01:24:03.611004 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 01:24:03.614308 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 01:24:03.617801 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 01:24:03.624441 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 01:24:03.627831 0 9 12 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
820 01:24:03.631441 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 01:24:03.638096 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 01:24:03.641239 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 01:24:03.644884 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 01:24:03.651297 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 01:24:03.654743 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
826 01:24:03.658242 0 10 8 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
827 01:24:03.661417 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
828 01:24:03.667956 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 01:24:03.671434 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 01:24:03.674610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 01:24:03.681436 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 01:24:03.684647 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 01:24:03.688228 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 01:24:03.695051 0 11 8 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
835 01:24:03.698020 0 11 12 | B1->B0 | 3636 4444 | 0 0 | (1 1) (0 0)
836 01:24:03.701567 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 01:24:03.708123 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 01:24:03.711597 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 01:24:03.714953 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 01:24:03.721512 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 01:24:03.725109 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 01:24:03.728566 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 01:24:03.732115 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:24:03.738524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:24:03.742084 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:24:03.745407 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:24:03.751939 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:24:03.755607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:24:03.758572 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:24:03.765242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:24:03.768552 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 01:24:03.772416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 01:24:03.779191 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 01:24:03.782303 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 01:24:03.785269 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 01:24:03.792111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 01:24:03.795673 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 01:24:03.798551 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 01:24:03.802242 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 01:24:03.805649 Total UI for P1: 0, mck2ui 16
861 01:24:03.809020 best dqsien dly found for B0: ( 0, 14, 8)
862 01:24:03.812039 Total UI for P1: 0, mck2ui 16
863 01:24:03.815739 best dqsien dly found for B1: ( 0, 14, 8)
864 01:24:03.819284 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 01:24:03.822648 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 01:24:03.822733
867 01:24:03.828946 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 01:24:03.832222 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 01:24:03.832307 [Gating] SW calibration Done
870 01:24:03.836167 ==
871 01:24:03.836252 Dram Type= 6, Freq= 0, CH_0, rank 0
872 01:24:03.842398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 01:24:03.842485 ==
874 01:24:03.842571 RX Vref Scan: 0
875 01:24:03.842652
876 01:24:03.846195 RX Vref 0 -> 0, step: 1
877 01:24:03.846280
878 01:24:03.849054 RX Delay -130 -> 252, step: 16
879 01:24:03.852338 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 01:24:03.856242 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 01:24:03.859508 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 01:24:03.866534 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 01:24:03.869094 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
884 01:24:03.872787 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 01:24:03.875953 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
886 01:24:03.879294 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
887 01:24:03.882609 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
888 01:24:03.889684 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 01:24:03.893399 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 01:24:03.896421 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 01:24:03.899713 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 01:24:03.903130 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 01:24:03.909779 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 01:24:03.913573 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 01:24:03.913656 ==
896 01:24:03.917101 Dram Type= 6, Freq= 0, CH_0, rank 0
897 01:24:03.919922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 01:24:03.920030 ==
899 01:24:03.920097 DQS Delay:
900 01:24:03.923227 DQS0 = 0, DQS1 = 0
901 01:24:03.923310 DQM Delay:
902 01:24:03.926497 DQM0 = 84, DQM1 = 77
903 01:24:03.926580 DQ Delay:
904 01:24:03.930263 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 01:24:03.933456 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
906 01:24:03.936785 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
907 01:24:03.940242 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
908 01:24:03.940326
909 01:24:03.940393
910 01:24:03.940480 ==
911 01:24:03.943523 Dram Type= 6, Freq= 0, CH_0, rank 0
912 01:24:03.946771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 01:24:03.946855 ==
914 01:24:03.950375
915 01:24:03.950458
916 01:24:03.950523 TX Vref Scan disable
917 01:24:03.953618 == TX Byte 0 ==
918 01:24:03.956928 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
919 01:24:03.960515 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
920 01:24:03.963698 == TX Byte 1 ==
921 01:24:03.967155 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
922 01:24:03.970812 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
923 01:24:03.970895 ==
924 01:24:03.974019 Dram Type= 6, Freq= 0, CH_0, rank 0
925 01:24:03.981013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 01:24:03.981097 ==
927 01:24:03.992360 TX Vref=22, minBit 0, minWin=27, winSum=441
928 01:24:03.995608 TX Vref=24, minBit 0, minWin=27, winSum=441
929 01:24:03.999057 TX Vref=26, minBit 12, minWin=27, winSum=450
930 01:24:04.002517 TX Vref=28, minBit 0, minWin=28, winSum=452
931 01:24:04.006402 TX Vref=30, minBit 12, minWin=27, winSum=452
932 01:24:04.009421 TX Vref=32, minBit 3, minWin=27, winSum=452
933 01:24:04.015722 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
934 01:24:04.015807
935 01:24:04.019067 Final TX Range 1 Vref 28
936 01:24:04.019150
937 01:24:04.019215 ==
938 01:24:04.022444 Dram Type= 6, Freq= 0, CH_0, rank 0
939 01:24:04.025988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 01:24:04.026072 ==
941 01:24:04.026141
942 01:24:04.026202
943 01:24:04.029436 TX Vref Scan disable
944 01:24:04.032950 == TX Byte 0 ==
945 01:24:04.035858 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 01:24:04.039844 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 01:24:04.043041 == TX Byte 1 ==
948 01:24:04.046371 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
949 01:24:04.049377 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
950 01:24:04.049460
951 01:24:04.052919 [DATLAT]
952 01:24:04.053031 Freq=800, CH0 RK0
953 01:24:04.053115
954 01:24:04.056094 DATLAT Default: 0xa
955 01:24:04.056177 0, 0xFFFF, sum = 0
956 01:24:04.059760 1, 0xFFFF, sum = 0
957 01:24:04.059845 2, 0xFFFF, sum = 0
958 01:24:04.063068 3, 0xFFFF, sum = 0
959 01:24:04.063153 4, 0xFFFF, sum = 0
960 01:24:04.066933 5, 0xFFFF, sum = 0
961 01:24:04.067017 6, 0xFFFF, sum = 0
962 01:24:04.069851 7, 0xFFFF, sum = 0
963 01:24:04.069935 8, 0xFFFF, sum = 0
964 01:24:04.073602 9, 0x0, sum = 1
965 01:24:04.073686 10, 0x0, sum = 2
966 01:24:04.076426 11, 0x0, sum = 3
967 01:24:04.076539 12, 0x0, sum = 4
968 01:24:04.080004 best_step = 10
969 01:24:04.080086
970 01:24:04.080167 ==
971 01:24:04.083581 Dram Type= 6, Freq= 0, CH_0, rank 0
972 01:24:04.086664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 01:24:04.086747 ==
974 01:24:04.086812 RX Vref Scan: 1
975 01:24:04.086873
976 01:24:04.090105 Set Vref Range= 32 -> 127
977 01:24:04.090188
978 01:24:04.093334 RX Vref 32 -> 127, step: 1
979 01:24:04.093416
980 01:24:04.096890 RX Delay -95 -> 252, step: 8
981 01:24:04.096972
982 01:24:04.100197 Set Vref, RX VrefLevel [Byte0]: 32
983 01:24:04.103532 [Byte1]: 32
984 01:24:04.103616
985 01:24:04.107038 Set Vref, RX VrefLevel [Byte0]: 33
986 01:24:04.110513 [Byte1]: 33
987 01:24:04.110596
988 01:24:04.114105 Set Vref, RX VrefLevel [Byte0]: 34
989 01:24:04.117333 [Byte1]: 34
990 01:24:04.117417
991 01:24:04.120822 Set Vref, RX VrefLevel [Byte0]: 35
992 01:24:04.123664 [Byte1]: 35
993 01:24:04.128483
994 01:24:04.128566 Set Vref, RX VrefLevel [Byte0]: 36
995 01:24:04.131954 [Byte1]: 36
996 01:24:04.135800
997 01:24:04.135882 Set Vref, RX VrefLevel [Byte0]: 37
998 01:24:04.138783 [Byte1]: 37
999 01:24:04.143723
1000 01:24:04.143806 Set Vref, RX VrefLevel [Byte0]: 38
1001 01:24:04.146874 [Byte1]: 38
1002 01:24:04.151478
1003 01:24:04.151560 Set Vref, RX VrefLevel [Byte0]: 39
1004 01:24:04.154564 [Byte1]: 39
1005 01:24:04.158712
1006 01:24:04.158794 Set Vref, RX VrefLevel [Byte0]: 40
1007 01:24:04.162025 [Byte1]: 40
1008 01:24:04.166253
1009 01:24:04.166335 Set Vref, RX VrefLevel [Byte0]: 41
1010 01:24:04.169539 [Byte1]: 41
1011 01:24:04.174009
1012 01:24:04.174091 Set Vref, RX VrefLevel [Byte0]: 42
1013 01:24:04.177675 [Byte1]: 42
1014 01:24:04.181334
1015 01:24:04.181416 Set Vref, RX VrefLevel [Byte0]: 43
1016 01:24:04.184362 [Byte1]: 43
1017 01:24:04.188917
1018 01:24:04.189034 Set Vref, RX VrefLevel [Byte0]: 44
1019 01:24:04.192011 [Byte1]: 44
1020 01:24:04.196344
1021 01:24:04.196426 Set Vref, RX VrefLevel [Byte0]: 45
1022 01:24:04.199554 [Byte1]: 45
1023 01:24:04.203813
1024 01:24:04.203896 Set Vref, RX VrefLevel [Byte0]: 46
1025 01:24:04.207151 [Byte1]: 46
1026 01:24:04.211459
1027 01:24:04.211540 Set Vref, RX VrefLevel [Byte0]: 47
1028 01:24:04.215592 [Byte1]: 47
1029 01:24:04.219062
1030 01:24:04.219143 Set Vref, RX VrefLevel [Byte0]: 48
1031 01:24:04.222478 [Byte1]: 48
1032 01:24:04.226745
1033 01:24:04.226826 Set Vref, RX VrefLevel [Byte0]: 49
1034 01:24:04.229910 [Byte1]: 49
1035 01:24:04.234443
1036 01:24:04.234524 Set Vref, RX VrefLevel [Byte0]: 50
1037 01:24:04.237483 [Byte1]: 50
1038 01:24:04.242161
1039 01:24:04.242242 Set Vref, RX VrefLevel [Byte0]: 51
1040 01:24:04.245595 [Byte1]: 51
1041 01:24:04.249343
1042 01:24:04.249424 Set Vref, RX VrefLevel [Byte0]: 52
1043 01:24:04.252583 [Byte1]: 52
1044 01:24:04.257140
1045 01:24:04.257252 Set Vref, RX VrefLevel [Byte0]: 53
1046 01:24:04.260865 [Byte1]: 53
1047 01:24:04.264479
1048 01:24:04.264560 Set Vref, RX VrefLevel [Byte0]: 54
1049 01:24:04.267881 [Byte1]: 54
1050 01:24:04.272124
1051 01:24:04.272205 Set Vref, RX VrefLevel [Byte0]: 55
1052 01:24:04.275604 [Byte1]: 55
1053 01:24:04.279704
1054 01:24:04.279785 Set Vref, RX VrefLevel [Byte0]: 56
1055 01:24:04.282890 [Byte1]: 56
1056 01:24:04.287510
1057 01:24:04.287592 Set Vref, RX VrefLevel [Byte0]: 57
1058 01:24:04.290581 [Byte1]: 57
1059 01:24:04.294927
1060 01:24:04.295008 Set Vref, RX VrefLevel [Byte0]: 58
1061 01:24:04.298084 [Byte1]: 58
1062 01:24:04.302735
1063 01:24:04.302816 Set Vref, RX VrefLevel [Byte0]: 59
1064 01:24:04.305784 [Byte1]: 59
1065 01:24:04.310267
1066 01:24:04.310348 Set Vref, RX VrefLevel [Byte0]: 60
1067 01:24:04.313510 [Byte1]: 60
1068 01:24:04.317596
1069 01:24:04.317677 Set Vref, RX VrefLevel [Byte0]: 61
1070 01:24:04.321394 [Byte1]: 61
1071 01:24:04.325699
1072 01:24:04.325780 Set Vref, RX VrefLevel [Byte0]: 62
1073 01:24:04.328702 [Byte1]: 62
1074 01:24:04.332894
1075 01:24:04.332975 Set Vref, RX VrefLevel [Byte0]: 63
1076 01:24:04.336378 [Byte1]: 63
1077 01:24:04.340479
1078 01:24:04.340560 Set Vref, RX VrefLevel [Byte0]: 64
1079 01:24:04.344367 [Byte1]: 64
1080 01:24:04.348101
1081 01:24:04.348182 Set Vref, RX VrefLevel [Byte0]: 65
1082 01:24:04.351320 [Byte1]: 65
1083 01:24:04.355559
1084 01:24:04.355640 Set Vref, RX VrefLevel [Byte0]: 66
1085 01:24:04.359171 [Byte1]: 66
1086 01:24:04.363395
1087 01:24:04.363476 Set Vref, RX VrefLevel [Byte0]: 67
1088 01:24:04.366875 [Byte1]: 67
1089 01:24:04.371758
1090 01:24:04.371838 Set Vref, RX VrefLevel [Byte0]: 68
1091 01:24:04.374258 [Byte1]: 68
1092 01:24:04.378446
1093 01:24:04.378527 Set Vref, RX VrefLevel [Byte0]: 69
1094 01:24:04.381971 [Byte1]: 69
1095 01:24:04.386006
1096 01:24:04.386087 Set Vref, RX VrefLevel [Byte0]: 70
1097 01:24:04.389363 [Byte1]: 70
1098 01:24:04.394021
1099 01:24:04.394102 Set Vref, RX VrefLevel [Byte0]: 71
1100 01:24:04.397161 [Byte1]: 71
1101 01:24:04.401087
1102 01:24:04.401168 Set Vref, RX VrefLevel [Byte0]: 72
1103 01:24:04.405043 [Byte1]: 72
1104 01:24:04.409069
1105 01:24:04.409150 Set Vref, RX VrefLevel [Byte0]: 73
1106 01:24:04.412221 [Byte1]: 73
1107 01:24:04.416566
1108 01:24:04.416649 Set Vref, RX VrefLevel [Byte0]: 74
1109 01:24:04.419963 [Byte1]: 74
1110 01:24:04.424324
1111 01:24:04.424405 Set Vref, RX VrefLevel [Byte0]: 75
1112 01:24:04.427403 [Byte1]: 75
1113 01:24:04.431605
1114 01:24:04.431686 Set Vref, RX VrefLevel [Byte0]: 76
1115 01:24:04.435157 [Byte1]: 76
1116 01:24:04.439283
1117 01:24:04.439364 Final RX Vref Byte 0 = 57 to rank0
1118 01:24:04.442700 Final RX Vref Byte 1 = 53 to rank0
1119 01:24:04.445992 Final RX Vref Byte 0 = 57 to rank1
1120 01:24:04.449401 Final RX Vref Byte 1 = 53 to rank1==
1121 01:24:04.452786 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 01:24:04.456066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 01:24:04.459726 ==
1124 01:24:04.459807 DQS Delay:
1125 01:24:04.459870 DQS0 = 0, DQS1 = 0
1126 01:24:04.463271 DQM Delay:
1127 01:24:04.463352 DQM0 = 85, DQM1 = 79
1128 01:24:04.466302 DQ Delay:
1129 01:24:04.466383 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1130 01:24:04.469735 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1131 01:24:04.472978 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =76
1132 01:24:04.476226 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1133 01:24:04.476307
1134 01:24:04.476370
1135 01:24:04.486655 [DQSOSCAuto] RK0, (LSB)MR18= 0x260e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1136 01:24:04.489695 CH0 RK0: MR19=606, MR18=260E
1137 01:24:04.492955 CH0_RK0: MR19=0x606, MR18=0x260E, DQSOSC=400, MR23=63, INC=92, DEC=61
1138 01:24:04.496799
1139 01:24:04.499813 ----->DramcWriteLeveling(PI) begin...
1140 01:24:04.499896 ==
1141 01:24:04.503037 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 01:24:04.506457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 01:24:04.506539 ==
1144 01:24:04.510079 Write leveling (Byte 0): 31 => 31
1145 01:24:04.513105 Write leveling (Byte 1): 30 => 30
1146 01:24:04.516510 DramcWriteLeveling(PI) end<-----
1147 01:24:04.516616
1148 01:24:04.516756 ==
1149 01:24:04.520121 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 01:24:04.523041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 01:24:04.523123 ==
1152 01:24:04.526816 [Gating] SW mode calibration
1153 01:24:04.533507 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 01:24:04.536851 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 01:24:04.543268 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 01:24:04.546643 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 01:24:04.550041 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 01:24:04.597813 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:24:04.597896 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:24:04.598214 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:24:04.598344 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:24:04.598741 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:24:04.599020 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:24:04.599089 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:24:04.599456 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:24:04.599794 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 01:24:04.600302 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:24:04.641372 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:24:04.641469 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:24:04.641822 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:24:04.642438 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1172 01:24:04.642700 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 01:24:04.643170 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1174 01:24:04.643252 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:24:04.643917 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 01:24:04.644258 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:24:04.644559 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:24:04.685786 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:24:04.685874 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 01:24:04.686149 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1181 01:24:04.686248 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1182 01:24:04.686520 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1183 01:24:04.686769 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 01:24:04.686852 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 01:24:04.686923 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 01:24:04.687240 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 01:24:04.687503 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 01:24:04.695226 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1189 01:24:04.695308 0 10 8 | B1->B0 | 3232 2929 | 0 1 | (0 0) (1 0)
1190 01:24:04.698808 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1191 01:24:04.702372 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 01:24:04.705401 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 01:24:04.708766 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 01:24:04.715549 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 01:24:04.719049 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 01:24:04.722620 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1197 01:24:04.726205 0 11 8 | B1->B0 | 2626 4444 | 0 0 | (1 1) (0 0)
1198 01:24:04.730402 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1199 01:24:04.737768 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 01:24:04.740833 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 01:24:04.744071 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 01:24:04.747480 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 01:24:04.755055 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 01:24:04.758674 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 01:24:04.761548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 01:24:04.768365 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 01:24:04.771798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:24:04.775085 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:24:04.778255 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:24:04.785108 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:24:04.788426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:24:04.791904 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:24:04.798375 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:24:04.801775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 01:24:04.805329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 01:24:04.812032 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 01:24:04.815100 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 01:24:04.818748 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 01:24:04.825227 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1220 01:24:04.828623 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1221 01:24:04.832296 Total UI for P1: 0, mck2ui 16
1222 01:24:04.835479 best dqsien dly found for B0: ( 0, 14, 0)
1223 01:24:04.838653 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1224 01:24:04.841960 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 01:24:04.845729 Total UI for P1: 0, mck2ui 16
1226 01:24:04.848890 best dqsien dly found for B1: ( 0, 14, 8)
1227 01:24:04.853217 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1228 01:24:04.856002 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 01:24:04.856108
1230 01:24:04.862487 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1231 01:24:04.866214 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 01:24:04.866295 [Gating] SW calibration Done
1233 01:24:04.869371 ==
1234 01:24:04.869453 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 01:24:04.876129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 01:24:04.876212 ==
1237 01:24:04.876278 RX Vref Scan: 0
1238 01:24:04.876337
1239 01:24:04.879195 RX Vref 0 -> 0, step: 1
1240 01:24:04.879276
1241 01:24:04.883036 RX Delay -130 -> 252, step: 16
1242 01:24:04.885974 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1243 01:24:04.889243 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1244 01:24:04.892917 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 01:24:04.899467 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 01:24:04.902851 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1247 01:24:04.906357 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1248 01:24:04.909870 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1249 01:24:04.913060 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 01:24:04.916225 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1251 01:24:04.923100 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1252 01:24:04.926222 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1253 01:24:04.929919 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1254 01:24:04.933463 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1255 01:24:04.936554 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 01:24:04.943855 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1257 01:24:04.946984 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1258 01:24:04.947067 ==
1259 01:24:04.949881 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 01:24:04.953379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 01:24:04.953461 ==
1262 01:24:04.956685 DQS Delay:
1263 01:24:04.956767 DQS0 = 0, DQS1 = 0
1264 01:24:04.956832 DQM Delay:
1265 01:24:04.959858 DQM0 = 87, DQM1 = 75
1266 01:24:04.959939 DQ Delay:
1267 01:24:04.963491 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1268 01:24:04.966653 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1269 01:24:04.970355 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1270 01:24:04.973938 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1271 01:24:04.974020
1272 01:24:04.974084
1273 01:24:04.974142 ==
1274 01:24:04.976810 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 01:24:04.983400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 01:24:04.983482 ==
1277 01:24:04.983546
1278 01:24:04.983604
1279 01:24:04.983660 TX Vref Scan disable
1280 01:24:04.986719 == TX Byte 0 ==
1281 01:24:04.990181 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 01:24:04.993808 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 01:24:04.996952 == TX Byte 1 ==
1284 01:24:05.000331 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 01:24:05.003795 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 01:24:05.007318 ==
1287 01:24:05.007401 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 01:24:05.014005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 01:24:05.014131 ==
1290 01:24:05.026052 TX Vref=22, minBit 9, minWin=27, winSum=447
1291 01:24:05.029311 TX Vref=24, minBit 9, minWin=27, winSum=447
1292 01:24:05.032429 TX Vref=26, minBit 9, minWin=27, winSum=450
1293 01:24:05.036439 TX Vref=28, minBit 9, minWin=27, winSum=450
1294 01:24:05.039564 TX Vref=30, minBit 3, minWin=28, winSum=455
1295 01:24:05.042719 TX Vref=32, minBit 2, minWin=28, winSum=454
1296 01:24:05.049546 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 30
1297 01:24:05.049629
1298 01:24:05.052537 Final TX Range 1 Vref 30
1299 01:24:05.052644
1300 01:24:05.052759 ==
1301 01:24:05.056168 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 01:24:05.059722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 01:24:05.059804 ==
1304 01:24:05.059867
1305 01:24:05.059925
1306 01:24:05.062804 TX Vref Scan disable
1307 01:24:05.066333 == TX Byte 0 ==
1308 01:24:05.069644 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1309 01:24:05.073080 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1310 01:24:05.075915 == TX Byte 1 ==
1311 01:24:05.079595 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 01:24:05.083020 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 01:24:05.083102
1314 01:24:05.086444 [DATLAT]
1315 01:24:05.086524 Freq=800, CH0 RK1
1316 01:24:05.086587
1317 01:24:05.089573 DATLAT Default: 0xa
1318 01:24:05.089654 0, 0xFFFF, sum = 0
1319 01:24:05.092958 1, 0xFFFF, sum = 0
1320 01:24:05.093041 2, 0xFFFF, sum = 0
1321 01:24:05.096292 3, 0xFFFF, sum = 0
1322 01:24:05.096374 4, 0xFFFF, sum = 0
1323 01:24:05.099810 5, 0xFFFF, sum = 0
1324 01:24:05.099893 6, 0xFFFF, sum = 0
1325 01:24:05.102926 7, 0xFFFF, sum = 0
1326 01:24:05.103009 8, 0xFFFF, sum = 0
1327 01:24:05.106309 9, 0x0, sum = 1
1328 01:24:05.106392 10, 0x0, sum = 2
1329 01:24:05.109635 11, 0x0, sum = 3
1330 01:24:05.109717 12, 0x0, sum = 4
1331 01:24:05.113450 best_step = 10
1332 01:24:05.113530
1333 01:24:05.113593 ==
1334 01:24:05.116407 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 01:24:05.119826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 01:24:05.119908 ==
1337 01:24:05.119971 RX Vref Scan: 0
1338 01:24:05.123567
1339 01:24:05.123647 RX Vref 0 -> 0, step: 1
1340 01:24:05.123711
1341 01:24:05.126758 RX Delay -95 -> 252, step: 8
1342 01:24:05.129864 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1343 01:24:05.136745 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1344 01:24:05.140288 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1345 01:24:05.143149 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1346 01:24:05.146526 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1347 01:24:05.150109 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1348 01:24:05.157021 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1349 01:24:05.159822 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1350 01:24:05.163334 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1351 01:24:05.166914 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1352 01:24:05.170043 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1353 01:24:05.176648 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1354 01:24:05.180095 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1355 01:24:05.183458 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1356 01:24:05.186727 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1357 01:24:05.190293 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 01:24:05.190373 ==
1359 01:24:05.194201 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 01:24:05.200465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 01:24:05.200547 ==
1362 01:24:05.200611 DQS Delay:
1363 01:24:05.203789 DQS0 = 0, DQS1 = 0
1364 01:24:05.203871 DQM Delay:
1365 01:24:05.203934 DQM0 = 87, DQM1 = 78
1366 01:24:05.207131 DQ Delay:
1367 01:24:05.210482 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1368 01:24:05.214182 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1369 01:24:05.217205 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1370 01:24:05.220270 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1371 01:24:05.220353
1372 01:24:05.220437
1373 01:24:05.227372 [DQSOSCAuto] RK1, (LSB)MR18= 0x321b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1374 01:24:05.230385 CH0 RK1: MR19=606, MR18=321B
1375 01:24:05.237391 CH0_RK1: MR19=0x606, MR18=0x321B, DQSOSC=397, MR23=63, INC=93, DEC=62
1376 01:24:05.241040 [RxdqsGatingPostProcess] freq 800
1377 01:24:05.243770 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 01:24:05.247274 Pre-setting of DQS Precalculation
1379 01:24:05.254242 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 01:24:05.254326 ==
1381 01:24:05.257551 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 01:24:05.260510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 01:24:05.260594 ==
1384 01:24:05.267191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 01:24:05.270524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 01:24:05.280785 [CA 0] Center 36 (6~67) winsize 62
1387 01:24:05.284430 [CA 1] Center 36 (5~67) winsize 63
1388 01:24:05.287777 [CA 2] Center 34 (4~65) winsize 62
1389 01:24:05.291034 [CA 3] Center 33 (3~64) winsize 62
1390 01:24:05.294474 [CA 4] Center 33 (3~64) winsize 62
1391 01:24:05.297709 [CA 5] Center 33 (3~64) winsize 62
1392 01:24:05.297790
1393 01:24:05.300753 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 01:24:05.300834
1395 01:24:05.304207 [CATrainingPosCal] consider 1 rank data
1396 01:24:05.307574 u2DelayCellTimex100 = 270/100 ps
1397 01:24:05.311100 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1398 01:24:05.314616 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1399 01:24:05.318096 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 01:24:05.324434 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 01:24:05.327712 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 01:24:05.331075 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 01:24:05.331171
1404 01:24:05.334435 CA PerBit enable=1, Macro0, CA PI delay=33
1405 01:24:05.334535
1406 01:24:05.337737 [CBTSetCACLKResult] CA Dly = 33
1407 01:24:05.337823 CS Dly: 3 (0~34)
1408 01:24:05.337909 ==
1409 01:24:05.341078 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 01:24:05.348530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 01:24:05.348615 ==
1412 01:24:05.351009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 01:24:05.357821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 01:24:05.367151 [CA 0] Center 36 (5~67) winsize 63
1415 01:24:05.370223 [CA 1] Center 36 (5~67) winsize 63
1416 01:24:05.373508 [CA 2] Center 34 (4~64) winsize 61
1417 01:24:05.376890 [CA 3] Center 33 (3~64) winsize 62
1418 01:24:05.380404 [CA 4] Center 34 (3~65) winsize 63
1419 01:24:05.383408 [CA 5] Center 33 (3~64) winsize 62
1420 01:24:05.383494
1421 01:24:05.386936 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1422 01:24:05.387045
1423 01:24:05.390561 [CATrainingPosCal] consider 2 rank data
1424 01:24:05.394349 u2DelayCellTimex100 = 270/100 ps
1425 01:24:05.398457 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1426 01:24:05.402084 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1427 01:24:05.405690 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 01:24:05.409376 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 01:24:05.412966 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 01:24:05.416694 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 01:24:05.416784
1432 01:24:05.420867 CA PerBit enable=1, Macro0, CA PI delay=33
1433 01:24:05.420986
1434 01:24:05.424391 [CBTSetCACLKResult] CA Dly = 33
1435 01:24:05.424491 CS Dly: 4 (0~36)
1436 01:24:05.424594
1437 01:24:05.427600 ----->DramcWriteLeveling(PI) begin...
1438 01:24:05.427688 ==
1439 01:24:05.430916 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 01:24:05.434673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 01:24:05.437830 ==
1442 01:24:05.437917 Write leveling (Byte 0): 26 => 26
1443 01:24:05.440973 Write leveling (Byte 1): 27 => 27
1444 01:24:05.444516 DramcWriteLeveling(PI) end<-----
1445 01:24:05.444613
1446 01:24:05.444747 ==
1447 01:24:05.448001 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 01:24:05.454530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 01:24:05.454620 ==
1450 01:24:05.454708 [Gating] SW mode calibration
1451 01:24:05.464946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 01:24:05.468136 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 01:24:05.471485 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1454 01:24:05.478522 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1455 01:24:05.481663 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1456 01:24:05.485153 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:24:05.491933 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:24:05.495325 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:24:05.498936 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:24:05.501605 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:24:05.508530 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:24:05.512117 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:24:05.515328 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 01:24:05.522083 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 01:24:05.525042 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1466 01:24:05.528529 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 01:24:05.535248 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1468 01:24:05.538583 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1469 01:24:05.541912 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 01:24:05.548908 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:24:05.552058 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1472 01:24:05.555567 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:24:05.562437 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 01:24:05.565577 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 01:24:05.569093 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 01:24:05.573427 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1477 01:24:05.579068 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 01:24:05.582300 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1479 01:24:05.585947 0 9 8 | B1->B0 | 2c2c 2b2b | 0 0 | (0 0) (0 0)
1480 01:24:05.592638 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 01:24:05.595999 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1482 01:24:05.599175 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 01:24:05.605985 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 01:24:05.609299 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1485 01:24:05.612657 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 01:24:05.616067 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1487 01:24:05.622640 0 10 8 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (0 0)
1488 01:24:05.626091 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:24:05.629284 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 01:24:05.636005 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 01:24:05.639466 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 01:24:05.643110 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 01:24:05.649769 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 01:24:05.652655 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1495 01:24:05.656288 0 11 8 | B1->B0 | 3b3b 3636 | 0 0 | (0 0) (0 0)
1496 01:24:05.663149 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:24:05.666661 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 01:24:05.670017 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 01:24:05.673107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 01:24:05.680015 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 01:24:05.683292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 01:24:05.686627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 01:24:05.694018 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 01:24:05.696790 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:24:05.700309 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:24:05.707219 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:24:05.710299 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:24:05.713672 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:24:05.720350 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:24:05.723541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:24:05.726868 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:24:05.730390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:24:05.736636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 01:24:05.740304 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 01:24:05.743432 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 01:24:05.750414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 01:24:05.754167 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 01:24:05.756818 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1519 01:24:05.763339 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 01:24:05.767281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 01:24:05.770181 Total UI for P1: 0, mck2ui 16
1522 01:24:05.773417 best dqsien dly found for B0: ( 0, 14, 6)
1523 01:24:05.776988 Total UI for P1: 0, mck2ui 16
1524 01:24:05.780354 best dqsien dly found for B1: ( 0, 14, 8)
1525 01:24:05.783826 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1526 01:24:05.787175 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1527 01:24:05.787259
1528 01:24:05.790550 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 01:24:05.793689 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 01:24:05.796942 [Gating] SW calibration Done
1531 01:24:05.797025 ==
1532 01:24:05.800624 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 01:24:05.804041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 01:24:05.804126 ==
1535 01:24:05.807200 RX Vref Scan: 0
1536 01:24:05.807283
1537 01:24:05.810562 RX Vref 0 -> 0, step: 1
1538 01:24:05.810646
1539 01:24:05.810732 RX Delay -130 -> 252, step: 16
1540 01:24:05.817260 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1541 01:24:05.820518 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1542 01:24:05.824175 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1543 01:24:05.827466 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1544 01:24:05.830679 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1545 01:24:05.834400 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1546 01:24:05.840922 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1547 01:24:05.844003 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1548 01:24:05.847630 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1549 01:24:05.850964 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1550 01:24:05.853963 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1551 01:24:05.860694 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1552 01:24:05.864478 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1553 01:24:05.867407 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1554 01:24:05.870929 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1555 01:24:05.874203 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1556 01:24:05.877665 ==
1557 01:24:05.880897 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 01:24:05.884729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 01:24:05.884814 ==
1560 01:24:05.884899 DQS Delay:
1561 01:24:05.887461 DQS0 = 0, DQS1 = 0
1562 01:24:05.887545 DQM Delay:
1563 01:24:05.891457 DQM0 = 80, DQM1 = 73
1564 01:24:05.891541 DQ Delay:
1565 01:24:05.894264 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1566 01:24:05.897848 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1567 01:24:05.900895 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1568 01:24:05.904822 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1569 01:24:05.904907
1570 01:24:05.904991
1571 01:24:05.905072 ==
1572 01:24:05.907867 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 01:24:05.911142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 01:24:05.911226 ==
1575 01:24:05.911312
1576 01:24:05.911392
1577 01:24:05.914541 TX Vref Scan disable
1578 01:24:05.918010 == TX Byte 0 ==
1579 01:24:05.921675 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1580 01:24:05.924581 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1581 01:24:05.924671 == TX Byte 1 ==
1582 01:24:05.931548 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1583 01:24:05.934809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1584 01:24:05.934893 ==
1585 01:24:05.938295 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 01:24:05.941237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 01:24:05.941323 ==
1588 01:24:05.955687 TX Vref=22, minBit 11, minWin=25, winSum=432
1589 01:24:05.958878 TX Vref=24, minBit 11, minWin=26, winSum=433
1590 01:24:05.962392 TX Vref=26, minBit 11, minWin=26, winSum=440
1591 01:24:05.965631 TX Vref=28, minBit 9, minWin=27, winSum=445
1592 01:24:05.968949 TX Vref=30, minBit 5, minWin=27, winSum=448
1593 01:24:05.972599 TX Vref=32, minBit 10, minWin=27, winSum=450
1594 01:24:05.980231 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 32
1595 01:24:05.980316
1596 01:24:05.983152 Final TX Range 1 Vref 32
1597 01:24:05.983237
1598 01:24:05.983321 ==
1599 01:24:05.986287 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 01:24:05.989671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 01:24:05.989756 ==
1602 01:24:05.989841
1603 01:24:05.989922
1604 01:24:05.993201 TX Vref Scan disable
1605 01:24:05.996579 == TX Byte 0 ==
1606 01:24:05.999946 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 01:24:06.003351 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 01:24:06.006957 == TX Byte 1 ==
1609 01:24:06.010369 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1610 01:24:06.013580 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1611 01:24:06.013664
1612 01:24:06.013749 [DATLAT]
1613 01:24:06.016688 Freq=800, CH1 RK0
1614 01:24:06.016789
1615 01:24:06.020418 DATLAT Default: 0xa
1616 01:24:06.020502 0, 0xFFFF, sum = 0
1617 01:24:06.023227 1, 0xFFFF, sum = 0
1618 01:24:06.023313 2, 0xFFFF, sum = 0
1619 01:24:06.026994 3, 0xFFFF, sum = 0
1620 01:24:06.027080 4, 0xFFFF, sum = 0
1621 01:24:06.030366 5, 0xFFFF, sum = 0
1622 01:24:06.030452 6, 0xFFFF, sum = 0
1623 01:24:06.033433 7, 0xFFFF, sum = 0
1624 01:24:06.033519 8, 0xFFFF, sum = 0
1625 01:24:06.036851 9, 0x0, sum = 1
1626 01:24:06.036937 10, 0x0, sum = 2
1627 01:24:06.037023 11, 0x0, sum = 3
1628 01:24:06.040150 12, 0x0, sum = 4
1629 01:24:06.040235 best_step = 10
1630 01:24:06.040320
1631 01:24:06.044144 ==
1632 01:24:06.044251 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 01:24:06.050363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 01:24:06.050448 ==
1635 01:24:06.050534 RX Vref Scan: 1
1636 01:24:06.050615
1637 01:24:06.054257 Set Vref Range= 32 -> 127
1638 01:24:06.054341
1639 01:24:06.057114 RX Vref 32 -> 127, step: 1
1640 01:24:06.057198
1641 01:24:06.060468 RX Delay -111 -> 252, step: 8
1642 01:24:06.060552
1643 01:24:06.063845 Set Vref, RX VrefLevel [Byte0]: 32
1644 01:24:06.067577 [Byte1]: 32
1645 01:24:06.067661
1646 01:24:06.070858 Set Vref, RX VrefLevel [Byte0]: 33
1647 01:24:06.074008 [Byte1]: 33
1648 01:24:06.074092
1649 01:24:06.077605 Set Vref, RX VrefLevel [Byte0]: 34
1650 01:24:06.080876 [Byte1]: 34
1651 01:24:06.083767
1652 01:24:06.083851 Set Vref, RX VrefLevel [Byte0]: 35
1653 01:24:06.087127 [Byte1]: 35
1654 01:24:06.091457
1655 01:24:06.091540 Set Vref, RX VrefLevel [Byte0]: 36
1656 01:24:06.094728 [Byte1]: 36
1657 01:24:06.098935
1658 01:24:06.099019 Set Vref, RX VrefLevel [Byte0]: 37
1659 01:24:06.102500 [Byte1]: 37
1660 01:24:06.106779
1661 01:24:06.106863 Set Vref, RX VrefLevel [Byte0]: 38
1662 01:24:06.109946 [Byte1]: 38
1663 01:24:06.114356
1664 01:24:06.114440 Set Vref, RX VrefLevel [Byte0]: 39
1665 01:24:06.117504 [Byte1]: 39
1666 01:24:06.121696
1667 01:24:06.121780 Set Vref, RX VrefLevel [Byte0]: 40
1668 01:24:06.125137 [Byte1]: 40
1669 01:24:06.129601
1670 01:24:06.129683 Set Vref, RX VrefLevel [Byte0]: 41
1671 01:24:06.132816 [Byte1]: 41
1672 01:24:06.137160
1673 01:24:06.137241 Set Vref, RX VrefLevel [Byte0]: 42
1674 01:24:06.140825 [Byte1]: 42
1675 01:24:06.144715
1676 01:24:06.144796 Set Vref, RX VrefLevel [Byte0]: 43
1677 01:24:06.148085 [Byte1]: 43
1678 01:24:06.152662
1679 01:24:06.152752 Set Vref, RX VrefLevel [Byte0]: 44
1680 01:24:06.156413 [Byte1]: 44
1681 01:24:06.160566
1682 01:24:06.160647 Set Vref, RX VrefLevel [Byte0]: 45
1683 01:24:06.163513 [Byte1]: 45
1684 01:24:06.167622
1685 01:24:06.167704 Set Vref, RX VrefLevel [Byte0]: 46
1686 01:24:06.171031 [Byte1]: 46
1687 01:24:06.175756
1688 01:24:06.175837 Set Vref, RX VrefLevel [Byte0]: 47
1689 01:24:06.178586 [Byte1]: 47
1690 01:24:06.183338
1691 01:24:06.183419 Set Vref, RX VrefLevel [Byte0]: 48
1692 01:24:06.186418 [Byte1]: 48
1693 01:24:06.190657
1694 01:24:06.190739 Set Vref, RX VrefLevel [Byte0]: 49
1695 01:24:06.194362 [Byte1]: 49
1696 01:24:06.198598
1697 01:24:06.198679 Set Vref, RX VrefLevel [Byte0]: 50
1698 01:24:06.201659 [Byte1]: 50
1699 01:24:06.205969
1700 01:24:06.206050 Set Vref, RX VrefLevel [Byte0]: 51
1701 01:24:06.209349 [Byte1]: 51
1702 01:24:06.213570
1703 01:24:06.213654 Set Vref, RX VrefLevel [Byte0]: 52
1704 01:24:06.217286 [Byte1]: 52
1705 01:24:06.221455
1706 01:24:06.221537 Set Vref, RX VrefLevel [Byte0]: 53
1707 01:24:06.224536 [Byte1]: 53
1708 01:24:06.228904
1709 01:24:06.228985 Set Vref, RX VrefLevel [Byte0]: 54
1710 01:24:06.232166 [Byte1]: 54
1711 01:24:06.236660
1712 01:24:06.236750 Set Vref, RX VrefLevel [Byte0]: 55
1713 01:24:06.240516 [Byte1]: 55
1714 01:24:06.244210
1715 01:24:06.244291 Set Vref, RX VrefLevel [Byte0]: 56
1716 01:24:06.247480 [Byte1]: 56
1717 01:24:06.251997
1718 01:24:06.252082 Set Vref, RX VrefLevel [Byte0]: 57
1719 01:24:06.255393 [Byte1]: 57
1720 01:24:06.259734
1721 01:24:06.259819 Set Vref, RX VrefLevel [Byte0]: 58
1722 01:24:06.263224 [Byte1]: 58
1723 01:24:06.267082
1724 01:24:06.267166 Set Vref, RX VrefLevel [Byte0]: 59
1725 01:24:06.270634 [Byte1]: 59
1726 01:24:06.274956
1727 01:24:06.275041 Set Vref, RX VrefLevel [Byte0]: 60
1728 01:24:06.278248 [Byte1]: 60
1729 01:24:06.282621
1730 01:24:06.282705 Set Vref, RX VrefLevel [Byte0]: 61
1731 01:24:06.286063 [Byte1]: 61
1732 01:24:06.290176
1733 01:24:06.290260 Set Vref, RX VrefLevel [Byte0]: 62
1734 01:24:06.293530 [Byte1]: 62
1735 01:24:06.297682
1736 01:24:06.297766 Set Vref, RX VrefLevel [Byte0]: 63
1737 01:24:06.301327 [Byte1]: 63
1738 01:24:06.305413
1739 01:24:06.305497 Set Vref, RX VrefLevel [Byte0]: 64
1740 01:24:06.308994 [Byte1]: 64
1741 01:24:06.313098
1742 01:24:06.313181 Set Vref, RX VrefLevel [Byte0]: 65
1743 01:24:06.316404 [Byte1]: 65
1744 01:24:06.320741
1745 01:24:06.320825 Set Vref, RX VrefLevel [Byte0]: 66
1746 01:24:06.324137 [Byte1]: 66
1747 01:24:06.328513
1748 01:24:06.328597 Set Vref, RX VrefLevel [Byte0]: 67
1749 01:24:06.331636 [Byte1]: 67
1750 01:24:06.336069
1751 01:24:06.336153 Set Vref, RX VrefLevel [Byte0]: 68
1752 01:24:06.339338 [Byte1]: 68
1753 01:24:06.343531
1754 01:24:06.343617 Set Vref, RX VrefLevel [Byte0]: 69
1755 01:24:06.347297 [Byte1]: 69
1756 01:24:06.351251
1757 01:24:06.351334 Set Vref, RX VrefLevel [Byte0]: 70
1758 01:24:06.354707 [Byte1]: 70
1759 01:24:06.358892
1760 01:24:06.358976 Set Vref, RX VrefLevel [Byte0]: 71
1761 01:24:06.362486 [Byte1]: 71
1762 01:24:06.366961
1763 01:24:06.367045 Set Vref, RX VrefLevel [Byte0]: 72
1764 01:24:06.369876 [Byte1]: 72
1765 01:24:06.374207
1766 01:24:06.374296 Set Vref, RX VrefLevel [Byte0]: 73
1767 01:24:06.377914 [Byte1]: 73
1768 01:24:06.381808
1769 01:24:06.381892 Set Vref, RX VrefLevel [Byte0]: 74
1770 01:24:06.385078 [Byte1]: 74
1771 01:24:06.389772
1772 01:24:06.389855 Set Vref, RX VrefLevel [Byte0]: 75
1773 01:24:06.392888 [Byte1]: 75
1774 01:24:06.397160
1775 01:24:06.397244 Final RX Vref Byte 0 = 65 to rank0
1776 01:24:06.400463 Final RX Vref Byte 1 = 61 to rank0
1777 01:24:06.403958 Final RX Vref Byte 0 = 65 to rank1
1778 01:24:06.407157 Final RX Vref Byte 1 = 61 to rank1==
1779 01:24:06.410487 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 01:24:06.414066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 01:24:06.417491 ==
1782 01:24:06.417579 DQS Delay:
1783 01:24:06.417681 DQS0 = 0, DQS1 = 0
1784 01:24:06.421098 DQM Delay:
1785 01:24:06.421182 DQM0 = 82, DQM1 = 75
1786 01:24:06.424089 DQ Delay:
1787 01:24:06.427315 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1788 01:24:06.427400 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1789 01:24:06.431001 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1790 01:24:06.434060 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1791 01:24:06.434144
1792 01:24:06.437727
1793 01:24:06.444226 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
1794 01:24:06.447650 CH1 RK0: MR19=605, MR18=28FC
1795 01:24:06.454705 CH1_RK0: MR19=0x605, MR18=0x28FC, DQSOSC=399, MR23=63, INC=92, DEC=61
1796 01:24:06.454790
1797 01:24:06.457635 ----->DramcWriteLeveling(PI) begin...
1798 01:24:06.457721 ==
1799 01:24:06.461160 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 01:24:06.464955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 01:24:06.465040 ==
1802 01:24:06.467547 Write leveling (Byte 0): 28 => 28
1803 01:24:06.470890 Write leveling (Byte 1): 27 => 27
1804 01:24:06.474381 DramcWriteLeveling(PI) end<-----
1805 01:24:06.474465
1806 01:24:06.474550 ==
1807 01:24:06.477648 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 01:24:06.481093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 01:24:06.481178 ==
1810 01:24:06.484477 [Gating] SW mode calibration
1811 01:24:06.491547 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 01:24:06.494482 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 01:24:06.501340 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 01:24:06.504606 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1815 01:24:06.508400 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:24:06.515025 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:24:06.517973 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:24:06.521388 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:24:06.528110 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:24:06.531613 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:24:06.535249 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:24:06.541665 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 01:24:06.544964 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 01:24:06.548499 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 01:24:06.555338 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1826 01:24:06.558923 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:24:06.561991 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:24:06.565062 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1829 01:24:06.571833 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1830 01:24:06.575751 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1831 01:24:06.578630 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1832 01:24:06.585440 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 01:24:06.588887 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:24:06.591890 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:24:06.598917 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:24:06.602062 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:24:06.605327 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 01:24:06.608601 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1839 01:24:06.615456 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1840 01:24:06.618951 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 01:24:06.622368 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 01:24:06.629181 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 01:24:06.632330 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 01:24:06.636139 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1845 01:24:06.642636 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 01:24:06.646087 0 10 4 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 0)
1847 01:24:06.649336 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1848 01:24:06.655750 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 01:24:06.659416 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1850 01:24:06.662282 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1851 01:24:06.665966 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 01:24:06.672393 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1853 01:24:06.675841 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 01:24:06.679308 0 11 4 | B1->B0 | 2c2c 3737 | 0 0 | (0 0) (0 0)
1855 01:24:06.685885 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
1856 01:24:06.689295 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 01:24:06.693024 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 01:24:06.699272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 01:24:06.702893 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 01:24:06.706377 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 01:24:06.712874 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 01:24:06.716211 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1863 01:24:06.720126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 01:24:06.725957 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 01:24:06.729862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 01:24:06.733069 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 01:24:06.736230 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 01:24:06.743268 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 01:24:06.746661 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 01:24:06.749922 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 01:24:06.756893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 01:24:06.759862 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 01:24:06.763214 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 01:24:06.769906 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 01:24:06.773406 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 01:24:06.776497 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 01:24:06.783194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1878 01:24:06.786702 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1879 01:24:06.790075 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 01:24:06.793499 Total UI for P1: 0, mck2ui 16
1881 01:24:06.796686 best dqsien dly found for B0: ( 0, 14, 2)
1882 01:24:06.800305 Total UI for P1: 0, mck2ui 16
1883 01:24:06.803382 best dqsien dly found for B1: ( 0, 14, 4)
1884 01:24:06.807110 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1885 01:24:06.810366 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1886 01:24:06.810476
1887 01:24:06.813519 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1888 01:24:06.817132 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 01:24:06.820571 [Gating] SW calibration Done
1890 01:24:06.820744 ==
1891 01:24:06.823589 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 01:24:06.826893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 01:24:06.826989 ==
1894 01:24:06.830549 RX Vref Scan: 0
1895 01:24:06.830666
1896 01:24:06.833729 RX Vref 0 -> 0, step: 1
1897 01:24:06.833828
1898 01:24:06.833894 RX Delay -130 -> 252, step: 16
1899 01:24:06.840469 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1900 01:24:06.843744 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1901 01:24:06.848116 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1902 01:24:06.850748 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1903 01:24:06.854083 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1904 01:24:06.860617 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1905 01:24:06.864130 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1906 01:24:06.867552 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1907 01:24:06.871230 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1908 01:24:06.874168 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1909 01:24:06.877854 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1910 01:24:06.884483 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1911 01:24:06.887509 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1912 01:24:06.891006 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1913 01:24:06.894636 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1914 01:24:06.901257 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1915 01:24:06.901381 ==
1916 01:24:06.904894 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 01:24:06.908394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 01:24:06.908478 ==
1919 01:24:06.908585 DQS Delay:
1920 01:24:06.911283 DQS0 = 0, DQS1 = 0
1921 01:24:06.911366 DQM Delay:
1922 01:24:06.914577 DQM0 = 78, DQM1 = 76
1923 01:24:06.914660 DQ Delay:
1924 01:24:06.917944 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1925 01:24:06.921224 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1926 01:24:06.924672 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1927 01:24:06.927966 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1928 01:24:06.928080
1929 01:24:06.928172
1930 01:24:06.928259 ==
1931 01:24:06.931322 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 01:24:06.934937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 01:24:06.935093 ==
1934 01:24:06.935171
1935 01:24:06.935232
1936 01:24:06.937792 TX Vref Scan disable
1937 01:24:06.942179 == TX Byte 0 ==
1938 01:24:06.944646 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1939 01:24:06.948111 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1940 01:24:06.951562 == TX Byte 1 ==
1941 01:24:06.954931 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1942 01:24:06.958391 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1943 01:24:06.958492 ==
1944 01:24:06.961316 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 01:24:06.964995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 01:24:06.965094 ==
1947 01:24:06.979003 TX Vref=22, minBit 13, minWin=26, winSum=438
1948 01:24:06.982206 TX Vref=24, minBit 13, minWin=26, winSum=438
1949 01:24:06.985782 TX Vref=26, minBit 15, minWin=26, winSum=443
1950 01:24:06.988966 TX Vref=28, minBit 15, minWin=26, winSum=446
1951 01:24:06.992197 TX Vref=30, minBit 10, minWin=27, winSum=449
1952 01:24:06.999095 TX Vref=32, minBit 9, minWin=27, winSum=450
1953 01:24:07.002718 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 32
1954 01:24:07.002857
1955 01:24:07.005744 Final TX Range 1 Vref 32
1956 01:24:07.005836
1957 01:24:07.005900 ==
1958 01:24:07.009024 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 01:24:07.013140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 01:24:07.013233 ==
1961 01:24:07.016058
1962 01:24:07.016166
1963 01:24:07.016256 TX Vref Scan disable
1964 01:24:07.019205 == TX Byte 0 ==
1965 01:24:07.022446 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 01:24:07.025892 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 01:24:07.029236 == TX Byte 1 ==
1968 01:24:07.032589 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1969 01:24:07.036154 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1970 01:24:07.039906
1971 01:24:07.040050 [DATLAT]
1972 01:24:07.040163 Freq=800, CH1 RK1
1973 01:24:07.040275
1974 01:24:07.042822 DATLAT Default: 0xa
1975 01:24:07.042932 0, 0xFFFF, sum = 0
1976 01:24:07.045997 1, 0xFFFF, sum = 0
1977 01:24:07.046130 2, 0xFFFF, sum = 0
1978 01:24:07.049463 3, 0xFFFF, sum = 0
1979 01:24:07.049597 4, 0xFFFF, sum = 0
1980 01:24:07.052907 5, 0xFFFF, sum = 0
1981 01:24:07.053058 6, 0xFFFF, sum = 0
1982 01:24:07.057097 7, 0xFFFF, sum = 0
1983 01:24:07.057250 8, 0xFFFF, sum = 0
1984 01:24:07.059663 9, 0x0, sum = 1
1985 01:24:07.059768 10, 0x0, sum = 2
1986 01:24:07.062781 11, 0x0, sum = 3
1987 01:24:07.062878 12, 0x0, sum = 4
1988 01:24:07.066126 best_step = 10
1989 01:24:07.066217
1990 01:24:07.066283 ==
1991 01:24:07.069708 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 01:24:07.073355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 01:24:07.073469 ==
1994 01:24:07.076468 RX Vref Scan: 0
1995 01:24:07.076560
1996 01:24:07.076625 RX Vref 0 -> 0, step: 1
1997 01:24:07.076728
1998 01:24:07.079664 RX Delay -111 -> 252, step: 8
1999 01:24:07.086325 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2000 01:24:07.089814 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2001 01:24:07.092972 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2002 01:24:07.096091 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2003 01:24:07.100277 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2004 01:24:07.106302 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2005 01:24:07.109577 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2006 01:24:07.113070 iDelay=201, Bit 7, Center 76 (-31 ~ 184) 216
2007 01:24:07.116322 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2008 01:24:07.120072 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2009 01:24:07.123503 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2010 01:24:07.130299 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2011 01:24:07.133363 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2012 01:24:07.136650 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2013 01:24:07.139919 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2014 01:24:07.146638 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2015 01:24:07.146740 ==
2016 01:24:07.149740 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 01:24:07.153414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 01:24:07.153502 ==
2019 01:24:07.153565 DQS Delay:
2020 01:24:07.156846 DQS0 = 0, DQS1 = 0
2021 01:24:07.156975 DQM Delay:
2022 01:24:07.160139 DQM0 = 79, DQM1 = 76
2023 01:24:07.160221 DQ Delay:
2024 01:24:07.163314 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =76
2025 01:24:07.167137 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
2026 01:24:07.170172 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2027 01:24:07.173379 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2028 01:24:07.173471
2029 01:24:07.173535
2030 01:24:07.180115 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2031 01:24:07.183844 CH1 RK1: MR19=606, MR18=1E28
2032 01:24:07.190210 CH1_RK1: MR19=0x606, MR18=0x1E28, DQSOSC=399, MR23=63, INC=92, DEC=61
2033 01:24:07.193637 [RxdqsGatingPostProcess] freq 800
2034 01:24:07.197514 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 01:24:07.200200 Pre-setting of DQS Precalculation
2036 01:24:07.207046 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 01:24:07.214375 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 01:24:07.220954 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 01:24:07.221086
2040 01:24:07.221157
2041 01:24:07.224902 [Calibration Summary] 1600 Mbps
2042 01:24:07.224991 CH 0, Rank 0
2043 01:24:07.227530 SW Impedance : PASS
2044 01:24:07.230847 DUTY Scan : NO K
2045 01:24:07.230940 ZQ Calibration : PASS
2046 01:24:07.233959 Jitter Meter : NO K
2047 01:24:07.234045 CBT Training : PASS
2048 01:24:07.237333 Write leveling : PASS
2049 01:24:07.240592 RX DQS gating : PASS
2050 01:24:07.240745 RX DQ/DQS(RDDQC) : PASS
2051 01:24:07.244012 TX DQ/DQS : PASS
2052 01:24:07.247252 RX DATLAT : PASS
2053 01:24:07.247351 RX DQ/DQS(Engine): PASS
2054 01:24:07.250563 TX OE : NO K
2055 01:24:07.250657 All Pass.
2056 01:24:07.250744
2057 01:24:07.254158 CH 0, Rank 1
2058 01:24:07.254247 SW Impedance : PASS
2059 01:24:07.257704 DUTY Scan : NO K
2060 01:24:07.260571 ZQ Calibration : PASS
2061 01:24:07.260685 Jitter Meter : NO K
2062 01:24:07.264059 CBT Training : PASS
2063 01:24:07.267370 Write leveling : PASS
2064 01:24:07.267455 RX DQS gating : PASS
2065 01:24:07.270800 RX DQ/DQS(RDDQC) : PASS
2066 01:24:07.273832 TX DQ/DQS : PASS
2067 01:24:07.273917 RX DATLAT : PASS
2068 01:24:07.278029 RX DQ/DQS(Engine): PASS
2069 01:24:07.278127 TX OE : NO K
2070 01:24:07.280808 All Pass.
2071 01:24:07.280892
2072 01:24:07.280992 CH 1, Rank 0
2073 01:24:07.284160 SW Impedance : PASS
2074 01:24:07.284269 DUTY Scan : NO K
2075 01:24:07.287804 ZQ Calibration : PASS
2076 01:24:07.290971 Jitter Meter : NO K
2077 01:24:07.291056 CBT Training : PASS
2078 01:24:07.294817 Write leveling : PASS
2079 01:24:07.297619 RX DQS gating : PASS
2080 01:24:07.297704 RX DQ/DQS(RDDQC) : PASS
2081 01:24:07.301050 TX DQ/DQS : PASS
2082 01:24:07.301135 RX DATLAT : PASS
2083 01:24:07.304856 RX DQ/DQS(Engine): PASS
2084 01:24:07.308191 TX OE : NO K
2085 01:24:07.308300 All Pass.
2086 01:24:07.308400
2087 01:24:07.308498 CH 1, Rank 1
2088 01:24:07.311022 SW Impedance : PASS
2089 01:24:07.314394 DUTY Scan : NO K
2090 01:24:07.314479 ZQ Calibration : PASS
2091 01:24:07.318106 Jitter Meter : NO K
2092 01:24:07.321143 CBT Training : PASS
2093 01:24:07.321229 Write leveling : PASS
2094 01:24:07.324708 RX DQS gating : PASS
2095 01:24:07.328098 RX DQ/DQS(RDDQC) : PASS
2096 01:24:07.328182 TX DQ/DQS : PASS
2097 01:24:07.331522 RX DATLAT : PASS
2098 01:24:07.334606 RX DQ/DQS(Engine): PASS
2099 01:24:07.334690 TX OE : NO K
2100 01:24:07.334775 All Pass.
2101 01:24:07.337836
2102 01:24:07.337920 DramC Write-DBI off
2103 01:24:07.341666 PER_BANK_REFRESH: Hybrid Mode
2104 01:24:07.341751 TX_TRACKING: ON
2105 01:24:07.344849 [GetDramInforAfterCalByMRR] Vendor 6.
2106 01:24:07.348106 [GetDramInforAfterCalByMRR] Revision 606.
2107 01:24:07.354717 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 01:24:07.354801 MR0 0x3b3b
2109 01:24:07.354886 MR8 0x5151
2110 01:24:07.358126 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 01:24:07.358209
2112 01:24:07.361557 MR0 0x3b3b
2113 01:24:07.361640 MR8 0x5151
2114 01:24:07.364905 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 01:24:07.364989
2116 01:24:07.375400 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 01:24:07.378386 [FAST_K] Save calibration result to emmc
2118 01:24:07.381777 [FAST_K] Save calibration result to emmc
2119 01:24:07.385148 dram_init: config_dvfs: 1
2120 01:24:07.388792 dramc_set_vcore_voltage set vcore to 662500
2121 01:24:07.388876 Read voltage for 1200, 2
2122 01:24:07.391720 Vio18 = 0
2123 01:24:07.391806 Vcore = 662500
2124 01:24:07.391906 Vdram = 0
2125 01:24:07.395695 Vddq = 0
2126 01:24:07.395803 Vmddr = 0
2127 01:24:07.398437 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 01:24:07.404956 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 01:24:07.408399 MEM_TYPE=3, freq_sel=15
2130 01:24:07.411986 sv_algorithm_assistance_LP4_1600
2131 01:24:07.415391 ============ PULL DRAM RESETB DOWN ============
2132 01:24:07.418971 ========== PULL DRAM RESETB DOWN end =========
2133 01:24:07.421892 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 01:24:07.425244 ===================================
2135 01:24:07.428860 LPDDR4 DRAM CONFIGURATION
2136 01:24:07.432319 ===================================
2137 01:24:07.435733 EX_ROW_EN[0] = 0x0
2138 01:24:07.435818 EX_ROW_EN[1] = 0x0
2139 01:24:07.438638 LP4Y_EN = 0x0
2140 01:24:07.438722 WORK_FSP = 0x0
2141 01:24:07.442721 WL = 0x4
2142 01:24:07.442805 RL = 0x4
2143 01:24:07.445577 BL = 0x2
2144 01:24:07.445662 RPST = 0x0
2145 01:24:07.448965 RD_PRE = 0x0
2146 01:24:07.449049 WR_PRE = 0x1
2147 01:24:07.452108 WR_PST = 0x0
2148 01:24:07.452192 DBI_WR = 0x0
2149 01:24:07.455576 DBI_RD = 0x0
2150 01:24:07.455660 OTF = 0x1
2151 01:24:07.459155 ===================================
2152 01:24:07.462479 ===================================
2153 01:24:07.465777 ANA top config
2154 01:24:07.469065 ===================================
2155 01:24:07.469150 DLL_ASYNC_EN = 0
2156 01:24:07.472417 ALL_SLAVE_EN = 0
2157 01:24:07.476030 NEW_RANK_MODE = 1
2158 01:24:07.479469 DLL_IDLE_MODE = 1
2159 01:24:07.482518 LP45_APHY_COMB_EN = 1
2160 01:24:07.482603 TX_ODT_DIS = 1
2161 01:24:07.486206 NEW_8X_MODE = 1
2162 01:24:07.489412 ===================================
2163 01:24:07.492596 ===================================
2164 01:24:07.496511 data_rate = 2400
2165 01:24:07.499456 CKR = 1
2166 01:24:07.502892 DQ_P2S_RATIO = 8
2167 01:24:07.506047 ===================================
2168 01:24:07.506131 CA_P2S_RATIO = 8
2169 01:24:07.509368 DQ_CA_OPEN = 0
2170 01:24:07.512506 DQ_SEMI_OPEN = 0
2171 01:24:07.516045 CA_SEMI_OPEN = 0
2172 01:24:07.519541 CA_FULL_RATE = 0
2173 01:24:07.519651 DQ_CKDIV4_EN = 0
2174 01:24:07.522957 CA_CKDIV4_EN = 0
2175 01:24:07.525909 CA_PREDIV_EN = 0
2176 01:24:07.529565 PH8_DLY = 17
2177 01:24:07.532606 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 01:24:07.536593 DQ_AAMCK_DIV = 4
2179 01:24:07.536681 CA_AAMCK_DIV = 4
2180 01:24:07.539550 CA_ADMCK_DIV = 4
2181 01:24:07.542976 DQ_TRACK_CA_EN = 0
2182 01:24:07.546405 CA_PICK = 1200
2183 01:24:07.549667 CA_MCKIO = 1200
2184 01:24:07.553147 MCKIO_SEMI = 0
2185 01:24:07.556344 PLL_FREQ = 2366
2186 01:24:07.556425 DQ_UI_PI_RATIO = 32
2187 01:24:07.559851 CA_UI_PI_RATIO = 0
2188 01:24:07.563104 ===================================
2189 01:24:07.566965 ===================================
2190 01:24:07.569560 memory_type:LPDDR4
2191 01:24:07.572820 GP_NUM : 10
2192 01:24:07.572901 SRAM_EN : 1
2193 01:24:07.576419 MD32_EN : 0
2194 01:24:07.579981 ===================================
2195 01:24:07.580062 [ANA_INIT] >>>>>>>>>>>>>>
2196 01:24:07.583529 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 01:24:07.586764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 01:24:07.589715 ===================================
2199 01:24:07.593111 data_rate = 2400,PCW = 0X5b00
2200 01:24:07.596474 ===================================
2201 01:24:07.599949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 01:24:07.607072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 01:24:07.609857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 01:24:07.616983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 01:24:07.620215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 01:24:07.623461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 01:24:07.623543 [ANA_INIT] flow start
2208 01:24:07.626864 [ANA_INIT] PLL >>>>>>>>
2209 01:24:07.630248 [ANA_INIT] PLL <<<<<<<<
2210 01:24:07.630329 [ANA_INIT] MIDPI >>>>>>>>
2211 01:24:07.633402 [ANA_INIT] MIDPI <<<<<<<<
2212 01:24:07.637033 [ANA_INIT] DLL >>>>>>>>
2213 01:24:07.640498 [ANA_INIT] DLL <<<<<<<<
2214 01:24:07.640579 [ANA_INIT] flow end
2215 01:24:07.644018 ============ LP4 DIFF to SE enter ============
2216 01:24:07.650475 ============ LP4 DIFF to SE exit ============
2217 01:24:07.650557 [ANA_INIT] <<<<<<<<<<<<<
2218 01:24:07.653591 [Flow] Enable top DCM control >>>>>
2219 01:24:07.656923 [Flow] Enable top DCM control <<<<<
2220 01:24:07.660398 Enable DLL master slave shuffle
2221 01:24:07.667570 ==============================================================
2222 01:24:07.667652 Gating Mode config
2223 01:24:07.673603 ==============================================================
2224 01:24:07.677293 Config description:
2225 01:24:07.683655 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 01:24:07.690673 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 01:24:07.697471 SELPH_MODE 0: By rank 1: By Phase
2228 01:24:07.700949 ==============================================================
2229 01:24:07.703977 GAT_TRACK_EN = 1
2230 01:24:07.707382 RX_GATING_MODE = 2
2231 01:24:07.710936 RX_GATING_TRACK_MODE = 2
2232 01:24:07.714470 SELPH_MODE = 1
2233 01:24:07.717759 PICG_EARLY_EN = 1
2234 01:24:07.720901 VALID_LAT_VALUE = 1
2235 01:24:07.724512 ==============================================================
2236 01:24:07.727806 Enter into Gating configuration >>>>
2237 01:24:07.731180 Exit from Gating configuration <<<<
2238 01:24:07.734560 Enter into DVFS_PRE_config >>>>>
2239 01:24:07.747994 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 01:24:07.751172 Exit from DVFS_PRE_config <<<<<
2241 01:24:07.751254 Enter into PICG configuration >>>>
2242 01:24:07.755040 Exit from PICG configuration <<<<
2243 01:24:07.757750 [RX_INPUT] configuration >>>>>
2244 01:24:07.760961 [RX_INPUT] configuration <<<<<
2245 01:24:07.768462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 01:24:07.771402 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 01:24:07.777883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 01:24:07.784558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 01:24:07.792056 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 01:24:07.797929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 01:24:07.801646 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 01:24:07.804562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 01:24:07.808437 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 01:24:07.814776 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 01:24:07.818238 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 01:24:07.821271 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 01:24:07.825005 ===================================
2258 01:24:07.827971 LPDDR4 DRAM CONFIGURATION
2259 01:24:07.831546 ===================================
2260 01:24:07.831631 EX_ROW_EN[0] = 0x0
2261 01:24:07.834752 EX_ROW_EN[1] = 0x0
2262 01:24:07.834836 LP4Y_EN = 0x0
2263 01:24:07.838190 WORK_FSP = 0x0
2264 01:24:07.838275 WL = 0x4
2265 01:24:07.841706 RL = 0x4
2266 01:24:07.841790 BL = 0x2
2267 01:24:07.845080 RPST = 0x0
2268 01:24:07.845163 RD_PRE = 0x0
2269 01:24:07.848211 WR_PRE = 0x1
2270 01:24:07.851496 WR_PST = 0x0
2271 01:24:07.851612 DBI_WR = 0x0
2272 01:24:07.854941 DBI_RD = 0x0
2273 01:24:07.855025 OTF = 0x1
2274 01:24:07.858286 ===================================
2275 01:24:07.861669 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 01:24:07.865258 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 01:24:07.872352 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 01:24:07.875324 ===================================
2279 01:24:07.875408 LPDDR4 DRAM CONFIGURATION
2280 01:24:07.878347 ===================================
2281 01:24:07.881805 EX_ROW_EN[0] = 0x10
2282 01:24:07.885374 EX_ROW_EN[1] = 0x0
2283 01:24:07.885458 LP4Y_EN = 0x0
2284 01:24:07.888459 WORK_FSP = 0x0
2285 01:24:07.888543 WL = 0x4
2286 01:24:07.892449 RL = 0x4
2287 01:24:07.892534 BL = 0x2
2288 01:24:07.895277 RPST = 0x0
2289 01:24:07.895360 RD_PRE = 0x0
2290 01:24:07.898810 WR_PRE = 0x1
2291 01:24:07.898894 WR_PST = 0x0
2292 01:24:07.902034 DBI_WR = 0x0
2293 01:24:07.902118 DBI_RD = 0x0
2294 01:24:07.905246 OTF = 0x1
2295 01:24:07.908644 ===================================
2296 01:24:07.915731 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 01:24:07.915816 ==
2298 01:24:07.918691 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 01:24:07.922544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 01:24:07.922666 ==
2301 01:24:07.925469 [Duty_Offset_Calibration]
2302 01:24:07.925550 B0:2 B1:-1 CA:1
2303 01:24:07.925612
2304 01:24:07.928861 [DutyScan_Calibration_Flow] k_type=0
2305 01:24:07.938442
2306 01:24:07.938523 ==CLK 0==
2307 01:24:07.941196 Final CLK duty delay cell = -4
2308 01:24:07.945104 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2309 01:24:07.948295 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2310 01:24:07.951414 [-4] AVG Duty = 4953%(X100)
2311 01:24:07.951495
2312 01:24:07.954748 CH0 CLK Duty spec in!! Max-Min= 156%
2313 01:24:07.958075 [DutyScan_Calibration_Flow] ====Done====
2314 01:24:07.958155
2315 01:24:07.961511 [DutyScan_Calibration_Flow] k_type=1
2316 01:24:07.976221
2317 01:24:07.976302 ==DQS 0 ==
2318 01:24:07.980005 Final DQS duty delay cell = -4
2319 01:24:07.983167 [-4] MAX Duty = 5000%(X100), DQS PI = 44
2320 01:24:07.986425 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2321 01:24:07.990180 [-4] AVG Duty = 4938%(X100)
2322 01:24:07.990260
2323 01:24:07.990322 ==DQS 1 ==
2324 01:24:07.993023 Final DQS duty delay cell = -4
2325 01:24:07.996532 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2326 01:24:07.999746 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2327 01:24:08.003397 [-4] AVG Duty = 5062%(X100)
2328 01:24:08.003476
2329 01:24:08.006604 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2330 01:24:08.006685
2331 01:24:08.009771 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2332 01:24:08.013156 [DutyScan_Calibration_Flow] ====Done====
2333 01:24:08.013237
2334 01:24:08.017067 [DutyScan_Calibration_Flow] k_type=3
2335 01:24:08.033497
2336 01:24:08.033579 ==DQM 0 ==
2337 01:24:08.036517 Final DQM duty delay cell = 0
2338 01:24:08.040135 [0] MAX Duty = 5031%(X100), DQS PI = 56
2339 01:24:08.043615 [0] MIN Duty = 4907%(X100), DQS PI = 2
2340 01:24:08.043696 [0] AVG Duty = 4969%(X100)
2341 01:24:08.046602
2342 01:24:08.046681 ==DQM 1 ==
2343 01:24:08.050454 Final DQM duty delay cell = 0
2344 01:24:08.053254 [0] MAX Duty = 5156%(X100), DQS PI = 62
2345 01:24:08.056851 [0] MIN Duty = 4969%(X100), DQS PI = 10
2346 01:24:08.056932 [0] AVG Duty = 5062%(X100)
2347 01:24:08.060135
2348 01:24:08.063284 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2349 01:24:08.063365
2350 01:24:08.066817 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2351 01:24:08.070075 [DutyScan_Calibration_Flow] ====Done====
2352 01:24:08.070156
2353 01:24:08.073884 [DutyScan_Calibration_Flow] k_type=2
2354 01:24:08.089103
2355 01:24:08.089184 ==DQ 0 ==
2356 01:24:08.092323 Final DQ duty delay cell = -4
2357 01:24:08.096073 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2358 01:24:08.099604 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2359 01:24:08.099735 [-4] AVG Duty = 4969%(X100)
2360 01:24:08.102361
2361 01:24:08.102441 ==DQ 1 ==
2362 01:24:08.105800 Final DQ duty delay cell = 0
2363 01:24:08.109252 [0] MAX Duty = 5031%(X100), DQS PI = 26
2364 01:24:08.112587 [0] MIN Duty = 4907%(X100), DQS PI = 46
2365 01:24:08.112690 [0] AVG Duty = 4969%(X100)
2366 01:24:08.112767
2367 01:24:08.116197 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2368 01:24:08.119550
2369 01:24:08.122596 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2370 01:24:08.126263 [DutyScan_Calibration_Flow] ====Done====
2371 01:24:08.126344 ==
2372 01:24:08.129677 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 01:24:08.132746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 01:24:08.132832 ==
2375 01:24:08.136387 [Duty_Offset_Calibration]
2376 01:24:08.136472 B0:1 B1:1 CA:2
2377 01:24:08.136572
2378 01:24:08.139273 [DutyScan_Calibration_Flow] k_type=0
2379 01:24:08.149734
2380 01:24:08.149819 ==CLK 0==
2381 01:24:08.152548 Final CLK duty delay cell = 0
2382 01:24:08.156317 [0] MAX Duty = 5187%(X100), DQS PI = 24
2383 01:24:08.159410 [0] MIN Duty = 4969%(X100), DQS PI = 40
2384 01:24:08.159494 [0] AVG Duty = 5078%(X100)
2385 01:24:08.159580
2386 01:24:08.162870 CH1 CLK Duty spec in!! Max-Min= 218%
2387 01:24:08.169306 [DutyScan_Calibration_Flow] ====Done====
2388 01:24:08.169391
2389 01:24:08.172478 [DutyScan_Calibration_Flow] k_type=1
2390 01:24:08.188871
2391 01:24:08.188955 ==DQS 0 ==
2392 01:24:08.191857 Final DQS duty delay cell = 0
2393 01:24:08.195253 [0] MAX Duty = 5031%(X100), DQS PI = 18
2394 01:24:08.198897 [0] MIN Duty = 4844%(X100), DQS PI = 48
2395 01:24:08.198983 [0] AVG Duty = 4937%(X100)
2396 01:24:08.202176
2397 01:24:08.202260 ==DQS 1 ==
2398 01:24:08.205266 Final DQS duty delay cell = 0
2399 01:24:08.209312 [0] MAX Duty = 5062%(X100), DQS PI = 36
2400 01:24:08.212422 [0] MIN Duty = 4907%(X100), DQS PI = 16
2401 01:24:08.212506 [0] AVG Duty = 4984%(X100)
2402 01:24:08.212607
2403 01:24:08.219366 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2404 01:24:08.219451
2405 01:24:08.222298 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2406 01:24:08.225605 [DutyScan_Calibration_Flow] ====Done====
2407 01:24:08.225689
2408 01:24:08.228972 [DutyScan_Calibration_Flow] k_type=3
2409 01:24:08.245168
2410 01:24:08.245251 ==DQM 0 ==
2411 01:24:08.248439 Final DQM duty delay cell = 0
2412 01:24:08.251949 [0] MAX Duty = 5093%(X100), DQS PI = 18
2413 01:24:08.255229 [0] MIN Duty = 4907%(X100), DQS PI = 44
2414 01:24:08.259007 [0] AVG Duty = 5000%(X100)
2415 01:24:08.259092
2416 01:24:08.259177 ==DQM 1 ==
2417 01:24:08.261862 Final DQM duty delay cell = 0
2418 01:24:08.265481 [0] MAX Duty = 5156%(X100), DQS PI = 62
2419 01:24:08.268284 [0] MIN Duty = 4938%(X100), DQS PI = 24
2420 01:24:08.272022 [0] AVG Duty = 5047%(X100)
2421 01:24:08.272106
2422 01:24:08.275646 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2423 01:24:08.275730
2424 01:24:08.278413 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2425 01:24:08.281955 [DutyScan_Calibration_Flow] ====Done====
2426 01:24:08.282056
2427 01:24:08.285668 [DutyScan_Calibration_Flow] k_type=2
2428 01:24:08.301708
2429 01:24:08.301789 ==DQ 0 ==
2430 01:24:08.305347 Final DQ duty delay cell = 0
2431 01:24:08.308446 [0] MAX Duty = 5125%(X100), DQS PI = 18
2432 01:24:08.312630 [0] MIN Duty = 4938%(X100), DQS PI = 50
2433 01:24:08.312734 [0] AVG Duty = 5031%(X100)
2434 01:24:08.312797
2435 01:24:08.315271 ==DQ 1 ==
2436 01:24:08.318556 Final DQ duty delay cell = 0
2437 01:24:08.321800 [0] MAX Duty = 5093%(X100), DQS PI = 8
2438 01:24:08.325465 [0] MIN Duty = 5031%(X100), DQS PI = 2
2439 01:24:08.325546 [0] AVG Duty = 5062%(X100)
2440 01:24:08.325609
2441 01:24:08.328941 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2442 01:24:08.329048
2443 01:24:08.331990 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2444 01:24:08.335594 [DutyScan_Calibration_Flow] ====Done====
2445 01:24:08.340973 nWR fixed to 30
2446 01:24:08.344015 [ModeRegInit_LP4] CH0 RK0
2447 01:24:08.344099 [ModeRegInit_LP4] CH0 RK1
2448 01:24:08.347403 [ModeRegInit_LP4] CH1 RK0
2449 01:24:08.351251 [ModeRegInit_LP4] CH1 RK1
2450 01:24:08.351335 match AC timing 7
2451 01:24:08.357346 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 01:24:08.360616 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 01:24:08.364352 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 01:24:08.371040 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 01:24:08.373911 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 01:24:08.373989 ==
2457 01:24:08.377064 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 01:24:08.380613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 01:24:08.380710 ==
2460 01:24:08.387472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 01:24:08.394326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 01:24:08.401624 [CA 0] Center 40 (10~71) winsize 62
2463 01:24:08.404810 [CA 1] Center 39 (9~70) winsize 62
2464 01:24:08.408149 [CA 2] Center 36 (6~67) winsize 62
2465 01:24:08.411969 [CA 3] Center 35 (5~66) winsize 62
2466 01:24:08.414820 [CA 4] Center 34 (4~65) winsize 62
2467 01:24:08.418227 [CA 5] Center 34 (4~64) winsize 61
2468 01:24:08.418308
2469 01:24:08.421872 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2470 01:24:08.421992
2471 01:24:08.425228 [CATrainingPosCal] consider 1 rank data
2472 01:24:08.428308 u2DelayCellTimex100 = 270/100 ps
2473 01:24:08.432089 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2474 01:24:08.434868 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2475 01:24:08.441777 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2476 01:24:08.445497 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2477 01:24:08.448334 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2478 01:24:08.451750 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2479 01:24:08.451823
2480 01:24:08.455429 CA PerBit enable=1, Macro0, CA PI delay=34
2481 01:24:08.455503
2482 01:24:08.458534 [CBTSetCACLKResult] CA Dly = 34
2483 01:24:08.458608 CS Dly: 7 (0~38)
2484 01:24:08.458668 ==
2485 01:24:08.461951 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 01:24:08.468652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 01:24:08.468744 ==
2488 01:24:08.471948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 01:24:08.478467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 01:24:08.487685 [CA 0] Center 39 (9~70) winsize 62
2491 01:24:08.490826 [CA 1] Center 39 (9~70) winsize 62
2492 01:24:08.494241 [CA 2] Center 36 (6~67) winsize 62
2493 01:24:08.497518 [CA 3] Center 35 (5~66) winsize 62
2494 01:24:08.500893 [CA 4] Center 34 (4~65) winsize 62
2495 01:24:08.504607 [CA 5] Center 34 (4~64) winsize 61
2496 01:24:08.504707
2497 01:24:08.507395 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 01:24:08.507470
2499 01:24:08.511168 [CATrainingPosCal] consider 2 rank data
2500 01:24:08.514292 u2DelayCellTimex100 = 270/100 ps
2501 01:24:08.517536 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2502 01:24:08.521033 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2503 01:24:08.524508 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2504 01:24:08.531415 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2505 01:24:08.535235 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2506 01:24:08.537956 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2507 01:24:08.538032
2508 01:24:08.541919 CA PerBit enable=1, Macro0, CA PI delay=34
2509 01:24:08.541991
2510 01:24:08.544566 [CBTSetCACLKResult] CA Dly = 34
2511 01:24:08.544661 CS Dly: 8 (0~41)
2512 01:24:08.544789
2513 01:24:08.548356 ----->DramcWriteLeveling(PI) begin...
2514 01:24:08.548461 ==
2515 01:24:08.551443 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 01:24:08.558246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 01:24:08.558348 ==
2518 01:24:08.561708 Write leveling (Byte 0): 31 => 31
2519 01:24:08.561809 Write leveling (Byte 1): 29 => 29
2520 01:24:08.565166 DramcWriteLeveling(PI) end<-----
2521 01:24:08.565237
2522 01:24:08.565297 ==
2523 01:24:08.568536 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 01:24:08.575069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 01:24:08.575143 ==
2526 01:24:08.578289 [Gating] SW mode calibration
2527 01:24:08.585526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 01:24:08.588259 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 01:24:08.595142 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 01:24:08.598581 0 15 4 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
2531 01:24:08.601909 0 15 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2532 01:24:08.605229 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 01:24:08.611907 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 01:24:08.615353 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 01:24:08.618834 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 01:24:08.625503 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 01:24:08.628963 1 0 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
2538 01:24:08.631993 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2539 01:24:08.639230 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 01:24:08.642157 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 01:24:08.645524 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 01:24:08.648896 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 01:24:08.655544 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 01:24:08.659100 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 01:24:08.663044 1 1 0 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (1 1)
2546 01:24:08.669204 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2547 01:24:08.672640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 01:24:08.675786 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 01:24:08.682674 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 01:24:08.685746 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 01:24:08.688931 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 01:24:08.695667 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 01:24:08.699705 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2554 01:24:08.702979 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2555 01:24:08.705962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 01:24:08.712761 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 01:24:08.716006 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 01:24:08.719686 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 01:24:08.726090 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 01:24:08.729431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 01:24:08.733343 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 01:24:08.739550 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 01:24:08.742906 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 01:24:08.746393 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 01:24:08.753219 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 01:24:08.756417 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 01:24:08.760026 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 01:24:08.763302 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 01:24:08.769854 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 01:24:08.773339 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 01:24:08.776634 Total UI for P1: 0, mck2ui 16
2572 01:24:08.780165 best dqsien dly found for B0: ( 1, 4, 0)
2573 01:24:08.783275 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 01:24:08.786879 Total UI for P1: 0, mck2ui 16
2575 01:24:08.790273 best dqsien dly found for B1: ( 1, 4, 2)
2576 01:24:08.793683 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2577 01:24:08.796626 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2578 01:24:08.796749
2579 01:24:08.800265 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 01:24:08.806758 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2581 01:24:08.806840 [Gating] SW calibration Done
2582 01:24:08.806904 ==
2583 01:24:08.810321 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 01:24:08.816621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 01:24:08.816747 ==
2586 01:24:08.816812 RX Vref Scan: 0
2587 01:24:08.816872
2588 01:24:08.819958 RX Vref 0 -> 0, step: 1
2589 01:24:08.820030
2590 01:24:08.823518 RX Delay -40 -> 252, step: 8
2591 01:24:08.827021 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2592 01:24:08.830288 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2593 01:24:08.834013 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2594 01:24:08.836828 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2595 01:24:08.843856 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2596 01:24:08.847310 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2597 01:24:08.850487 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2598 01:24:08.854039 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2599 01:24:08.857003 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2600 01:24:08.860430 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2601 01:24:08.867189 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2602 01:24:08.870632 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2603 01:24:08.873843 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2604 01:24:08.877179 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2605 01:24:08.880914 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2606 01:24:08.887569 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2607 01:24:08.887647 ==
2608 01:24:08.891295 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 01:24:08.894670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 01:24:08.894772 ==
2611 01:24:08.894861 DQS Delay:
2612 01:24:08.897515 DQS0 = 0, DQS1 = 0
2613 01:24:08.897613 DQM Delay:
2614 01:24:08.900968 DQM0 = 115, DQM1 = 106
2615 01:24:08.901043 DQ Delay:
2616 01:24:08.904523 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2617 01:24:08.907455 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2618 01:24:08.910756 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2619 01:24:08.914647 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2620 01:24:08.914730
2621 01:24:08.914793
2622 01:24:08.914853 ==
2623 01:24:08.917903 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 01:24:08.924502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 01:24:08.924613 ==
2626 01:24:08.924740
2627 01:24:08.924802
2628 01:24:08.924860 TX Vref Scan disable
2629 01:24:08.927929 == TX Byte 0 ==
2630 01:24:08.931324 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2631 01:24:08.934922 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2632 01:24:08.938949 == TX Byte 1 ==
2633 01:24:08.941895 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2634 01:24:08.945090 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2635 01:24:08.948409 ==
2636 01:24:08.948493 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 01:24:08.955024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 01:24:08.955109 ==
2639 01:24:08.966154 TX Vref=22, minBit 1, minWin=24, winSum=415
2640 01:24:08.969360 TX Vref=24, minBit 7, minWin=24, winSum=418
2641 01:24:08.973353 TX Vref=26, minBit 1, minWin=25, winSum=423
2642 01:24:08.976520 TX Vref=28, minBit 1, minWin=26, winSum=431
2643 01:24:08.979510 TX Vref=30, minBit 0, minWin=26, winSum=429
2644 01:24:08.982659 TX Vref=32, minBit 0, minWin=26, winSum=429
2645 01:24:08.989811 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
2646 01:24:08.989913
2647 01:24:08.992839 Final TX Range 1 Vref 28
2648 01:24:08.992911
2649 01:24:08.992975 ==
2650 01:24:08.996317 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 01:24:08.999499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 01:24:08.999596 ==
2653 01:24:08.999684
2654 01:24:08.999770
2655 01:24:09.003562 TX Vref Scan disable
2656 01:24:09.006227 == TX Byte 0 ==
2657 01:24:09.009985 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2658 01:24:09.013493 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2659 01:24:09.016787 == TX Byte 1 ==
2660 01:24:09.019702 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2661 01:24:09.023309 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2662 01:24:09.023414
2663 01:24:09.026604 [DATLAT]
2664 01:24:09.026705 Freq=1200, CH0 RK0
2665 01:24:09.026794
2666 01:24:09.030228 DATLAT Default: 0xd
2667 01:24:09.030328 0, 0xFFFF, sum = 0
2668 01:24:09.033314 1, 0xFFFF, sum = 0
2669 01:24:09.033399 2, 0xFFFF, sum = 0
2670 01:24:09.036846 3, 0xFFFF, sum = 0
2671 01:24:09.036929 4, 0xFFFF, sum = 0
2672 01:24:09.039805 5, 0xFFFF, sum = 0
2673 01:24:09.039889 6, 0xFFFF, sum = 0
2674 01:24:09.043492 7, 0xFFFF, sum = 0
2675 01:24:09.043575 8, 0xFFFF, sum = 0
2676 01:24:09.046876 9, 0xFFFF, sum = 0
2677 01:24:09.047022 10, 0xFFFF, sum = 0
2678 01:24:09.050229 11, 0xFFFF, sum = 0
2679 01:24:09.050315 12, 0x0, sum = 1
2680 01:24:09.053768 13, 0x0, sum = 2
2681 01:24:09.053854 14, 0x0, sum = 3
2682 01:24:09.056775 15, 0x0, sum = 4
2683 01:24:09.056861 best_step = 13
2684 01:24:09.056964
2685 01:24:09.057093 ==
2686 01:24:09.060329 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 01:24:09.063391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 01:24:09.066914 ==
2689 01:24:09.066999 RX Vref Scan: 1
2690 01:24:09.067085
2691 01:24:09.070307 Set Vref Range= 32 -> 127
2692 01:24:09.070391
2693 01:24:09.070477 RX Vref 32 -> 127, step: 1
2694 01:24:09.070558
2695 01:24:09.073741 RX Delay -21 -> 252, step: 4
2696 01:24:09.073825
2697 01:24:09.077339 Set Vref, RX VrefLevel [Byte0]: 32
2698 01:24:09.080580 [Byte1]: 32
2699 01:24:09.084280
2700 01:24:09.084364 Set Vref, RX VrefLevel [Byte0]: 33
2701 01:24:09.088055 [Byte1]: 33
2702 01:24:09.092086
2703 01:24:09.092170 Set Vref, RX VrefLevel [Byte0]: 34
2704 01:24:09.095430 [Byte1]: 34
2705 01:24:09.100525
2706 01:24:09.100610 Set Vref, RX VrefLevel [Byte0]: 35
2707 01:24:09.103451 [Byte1]: 35
2708 01:24:09.108420
2709 01:24:09.108504 Set Vref, RX VrefLevel [Byte0]: 36
2710 01:24:09.111547 [Byte1]: 36
2711 01:24:09.115831
2712 01:24:09.115915 Set Vref, RX VrefLevel [Byte0]: 37
2713 01:24:09.119588 [Byte1]: 37
2714 01:24:09.123717
2715 01:24:09.123803 Set Vref, RX VrefLevel [Byte0]: 38
2716 01:24:09.127320 [Byte1]: 38
2717 01:24:09.131814
2718 01:24:09.131899 Set Vref, RX VrefLevel [Byte0]: 39
2719 01:24:09.135176 [Byte1]: 39
2720 01:24:09.139722
2721 01:24:09.139809 Set Vref, RX VrefLevel [Byte0]: 40
2722 01:24:09.143286 [Byte1]: 40
2723 01:24:09.147855
2724 01:24:09.147975 Set Vref, RX VrefLevel [Byte0]: 41
2725 01:24:09.150875 [Byte1]: 41
2726 01:24:09.155430
2727 01:24:09.155515 Set Vref, RX VrefLevel [Byte0]: 42
2728 01:24:09.159206 [Byte1]: 42
2729 01:24:09.163461
2730 01:24:09.163547 Set Vref, RX VrefLevel [Byte0]: 43
2731 01:24:09.166816 [Byte1]: 43
2732 01:24:09.171329
2733 01:24:09.171418 Set Vref, RX VrefLevel [Byte0]: 44
2734 01:24:09.174876 [Byte1]: 44
2735 01:24:09.179632
2736 01:24:09.179744 Set Vref, RX VrefLevel [Byte0]: 45
2737 01:24:09.183416 [Byte1]: 45
2738 01:24:09.187495
2739 01:24:09.187580 Set Vref, RX VrefLevel [Byte0]: 46
2740 01:24:09.190595 [Byte1]: 46
2741 01:24:09.195094
2742 01:24:09.195180 Set Vref, RX VrefLevel [Byte0]: 47
2743 01:24:09.198754 [Byte1]: 47
2744 01:24:09.203158
2745 01:24:09.203246 Set Vref, RX VrefLevel [Byte0]: 48
2746 01:24:09.206554 [Byte1]: 48
2747 01:24:09.211194
2748 01:24:09.211283 Set Vref, RX VrefLevel [Byte0]: 49
2749 01:24:09.214334 [Byte1]: 49
2750 01:24:09.219362
2751 01:24:09.219448 Set Vref, RX VrefLevel [Byte0]: 50
2752 01:24:09.222285 [Byte1]: 50
2753 01:24:09.227266
2754 01:24:09.227354 Set Vref, RX VrefLevel [Byte0]: 51
2755 01:24:09.230210 [Byte1]: 51
2756 01:24:09.234965
2757 01:24:09.235053 Set Vref, RX VrefLevel [Byte0]: 52
2758 01:24:09.238319 [Byte1]: 52
2759 01:24:09.243122
2760 01:24:09.243209 Set Vref, RX VrefLevel [Byte0]: 53
2761 01:24:09.246458 [Byte1]: 53
2762 01:24:09.250620
2763 01:24:09.250706 Set Vref, RX VrefLevel [Byte0]: 54
2764 01:24:09.254270 [Byte1]: 54
2765 01:24:09.258780
2766 01:24:09.258865 Set Vref, RX VrefLevel [Byte0]: 55
2767 01:24:09.262326 [Byte1]: 55
2768 01:24:09.266799
2769 01:24:09.266883 Set Vref, RX VrefLevel [Byte0]: 56
2770 01:24:09.269676 [Byte1]: 56
2771 01:24:09.274464
2772 01:24:09.274549 Set Vref, RX VrefLevel [Byte0]: 57
2773 01:24:09.277874 [Byte1]: 57
2774 01:24:09.282488
2775 01:24:09.282572 Set Vref, RX VrefLevel [Byte0]: 58
2776 01:24:09.285777 [Byte1]: 58
2777 01:24:09.290611
2778 01:24:09.290696 Set Vref, RX VrefLevel [Byte0]: 59
2779 01:24:09.293931 [Byte1]: 59
2780 01:24:09.298140
2781 01:24:09.298226 Set Vref, RX VrefLevel [Byte0]: 60
2782 01:24:09.304870 [Byte1]: 60
2783 01:24:09.304958
2784 01:24:09.309056 Set Vref, RX VrefLevel [Byte0]: 61
2785 01:24:09.311597 [Byte1]: 61
2786 01:24:09.311681
2787 01:24:09.315188 Set Vref, RX VrefLevel [Byte0]: 62
2788 01:24:09.318108 [Byte1]: 62
2789 01:24:09.322034
2790 01:24:09.322119 Set Vref, RX VrefLevel [Byte0]: 63
2791 01:24:09.325974 [Byte1]: 63
2792 01:24:09.329841
2793 01:24:09.329927 Set Vref, RX VrefLevel [Byte0]: 64
2794 01:24:09.333120 [Byte1]: 64
2795 01:24:09.338015
2796 01:24:09.338100 Set Vref, RX VrefLevel [Byte0]: 65
2797 01:24:09.341404 [Byte1]: 65
2798 01:24:09.345849
2799 01:24:09.345933 Set Vref, RX VrefLevel [Byte0]: 66
2800 01:24:09.348988 [Byte1]: 66
2801 01:24:09.353628
2802 01:24:09.353713 Set Vref, RX VrefLevel [Byte0]: 67
2803 01:24:09.357202 [Byte1]: 67
2804 01:24:09.362078
2805 01:24:09.362164 Set Vref, RX VrefLevel [Byte0]: 68
2806 01:24:09.365213 [Byte1]: 68
2807 01:24:09.369476
2808 01:24:09.369561 Final RX Vref Byte 0 = 53 to rank0
2809 01:24:09.373381 Final RX Vref Byte 1 = 49 to rank0
2810 01:24:09.376536 Final RX Vref Byte 0 = 53 to rank1
2811 01:24:09.379724 Final RX Vref Byte 1 = 49 to rank1==
2812 01:24:09.382712 Dram Type= 6, Freq= 0, CH_0, rank 0
2813 01:24:09.386646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2814 01:24:09.389673 ==
2815 01:24:09.389755 DQS Delay:
2816 01:24:09.389823 DQS0 = 0, DQS1 = 0
2817 01:24:09.393385 DQM Delay:
2818 01:24:09.393471 DQM0 = 115, DQM1 = 104
2819 01:24:09.396266 DQ Delay:
2820 01:24:09.400262 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2821 01:24:09.403548 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2822 01:24:09.406770 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2823 01:24:09.410275 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =114
2824 01:24:09.410362
2825 01:24:09.410446
2826 01:24:09.416780 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2827 01:24:09.419824 CH0 RK0: MR19=303, MR18=FCEC
2828 01:24:09.426518 CH0_RK0: MR19=0x303, MR18=0xFCEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2829 01:24:09.426612
2830 01:24:09.429744 ----->DramcWriteLeveling(PI) begin...
2831 01:24:09.429831 ==
2832 01:24:09.433424 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 01:24:09.436311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 01:24:09.436415 ==
2835 01:24:09.440092 Write leveling (Byte 0): 31 => 31
2836 01:24:09.443207 Write leveling (Byte 1): 29 => 29
2837 01:24:09.446785 DramcWriteLeveling(PI) end<-----
2838 01:24:09.446870
2839 01:24:09.446956 ==
2840 01:24:09.450343 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 01:24:09.453889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 01:24:09.453975 ==
2843 01:24:09.457081 [Gating] SW mode calibration
2844 01:24:09.463496 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2845 01:24:09.470266 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2846 01:24:09.473773 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2847 01:24:09.477378 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2848 01:24:09.484116 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 01:24:09.486951 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 01:24:09.490387 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 01:24:09.497663 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 01:24:09.500521 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2853 01:24:09.503753 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2854 01:24:09.510878 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2855 01:24:09.513744 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 01:24:09.517275 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 01:24:09.523861 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 01:24:09.527397 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 01:24:09.530575 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 01:24:09.537288 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2861 01:24:09.540712 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2862 01:24:09.543889 1 1 0 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
2863 01:24:09.547494 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 01:24:09.554377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 01:24:09.557727 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 01:24:09.560970 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 01:24:09.567566 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 01:24:09.571213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2869 01:24:09.574155 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2870 01:24:09.581341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2871 01:24:09.584224 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2872 01:24:09.588142 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 01:24:09.594459 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 01:24:09.597834 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 01:24:09.601624 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 01:24:09.604580 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 01:24:09.611641 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 01:24:09.614853 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 01:24:09.618447 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 01:24:09.624931 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 01:24:09.628989 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 01:24:09.631341 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 01:24:09.638198 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 01:24:09.641992 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 01:24:09.645148 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2886 01:24:09.651896 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2887 01:24:09.651985 Total UI for P1: 0, mck2ui 16
2888 01:24:09.655057 best dqsien dly found for B0: ( 1, 3, 28)
2889 01:24:09.661987 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 01:24:09.665371 Total UI for P1: 0, mck2ui 16
2891 01:24:09.668525 best dqsien dly found for B1: ( 1, 4, 0)
2892 01:24:09.672111 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2893 01:24:09.675340 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2894 01:24:09.675449
2895 01:24:09.678796 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2896 01:24:09.682097 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2897 01:24:09.685446 [Gating] SW calibration Done
2898 01:24:09.685531 ==
2899 01:24:09.688846 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 01:24:09.691967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 01:24:09.692048 ==
2902 01:24:09.695433 RX Vref Scan: 0
2903 01:24:09.695518
2904 01:24:09.695602 RX Vref 0 -> 0, step: 1
2905 01:24:09.695683
2906 01:24:09.698699 RX Delay -40 -> 252, step: 8
2907 01:24:09.702115 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2908 01:24:09.709043 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2909 01:24:09.712098 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2910 01:24:09.715531 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2911 01:24:09.718822 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2912 01:24:09.722287 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2913 01:24:09.725676 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2914 01:24:09.732285 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2915 01:24:09.735425 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2916 01:24:09.738830 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2917 01:24:09.742219 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2918 01:24:09.745831 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2919 01:24:09.752652 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2920 01:24:09.756187 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2921 01:24:09.759274 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2922 01:24:09.762466 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2923 01:24:09.762547 ==
2924 01:24:09.766419 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 01:24:09.769405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 01:24:09.769487 ==
2927 01:24:09.772925 DQS Delay:
2928 01:24:09.773006 DQS0 = 0, DQS1 = 0
2929 01:24:09.776067 DQM Delay:
2930 01:24:09.776148 DQM0 = 115, DQM1 = 105
2931 01:24:09.779589 DQ Delay:
2932 01:24:09.782945 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2933 01:24:09.786243 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2934 01:24:09.789405 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2935 01:24:09.792753 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2936 01:24:09.792835
2937 01:24:09.792898
2938 01:24:09.792956 ==
2939 01:24:09.796157 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 01:24:09.800383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 01:24:09.800464 ==
2942 01:24:09.800528
2943 01:24:09.800587
2944 01:24:09.802769 TX Vref Scan disable
2945 01:24:09.802851 == TX Byte 0 ==
2946 01:24:09.809520 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2947 01:24:09.812913 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2948 01:24:09.812994 == TX Byte 1 ==
2949 01:24:09.820010 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2950 01:24:09.823603 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2951 01:24:09.823685 ==
2952 01:24:09.826104 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 01:24:09.829541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 01:24:09.829623 ==
2955 01:24:09.842868 TX Vref=22, minBit 5, minWin=25, winSum=429
2956 01:24:09.846645 TX Vref=24, minBit 1, minWin=26, winSum=432
2957 01:24:09.849945 TX Vref=26, minBit 0, minWin=27, winSum=436
2958 01:24:09.853030 TX Vref=28, minBit 0, minWin=27, winSum=440
2959 01:24:09.856438 TX Vref=30, minBit 5, minWin=26, winSum=438
2960 01:24:09.859618 TX Vref=32, minBit 12, minWin=26, winSum=440
2961 01:24:09.866430 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 28
2962 01:24:09.866512
2963 01:24:09.869883 Final TX Range 1 Vref 28
2964 01:24:09.869965
2965 01:24:09.870028 ==
2966 01:24:09.873143 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 01:24:09.876585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 01:24:09.876688 ==
2969 01:24:09.876768
2970 01:24:09.876827
2971 01:24:09.879683 TX Vref Scan disable
2972 01:24:09.882894 == TX Byte 0 ==
2973 01:24:09.886288 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2974 01:24:09.890098 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2975 01:24:09.893510 == TX Byte 1 ==
2976 01:24:09.896515 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2977 01:24:09.899842 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2978 01:24:09.899923
2979 01:24:09.903162 [DATLAT]
2980 01:24:09.903243 Freq=1200, CH0 RK1
2981 01:24:09.903306
2982 01:24:09.906982 DATLAT Default: 0xd
2983 01:24:09.907063 0, 0xFFFF, sum = 0
2984 01:24:09.909740 1, 0xFFFF, sum = 0
2985 01:24:09.909823 2, 0xFFFF, sum = 0
2986 01:24:09.913553 3, 0xFFFF, sum = 0
2987 01:24:09.913636 4, 0xFFFF, sum = 0
2988 01:24:09.916803 5, 0xFFFF, sum = 0
2989 01:24:09.916885 6, 0xFFFF, sum = 0
2990 01:24:09.919895 7, 0xFFFF, sum = 0
2991 01:24:09.919978 8, 0xFFFF, sum = 0
2992 01:24:09.923447 9, 0xFFFF, sum = 0
2993 01:24:09.923530 10, 0xFFFF, sum = 0
2994 01:24:09.927102 11, 0xFFFF, sum = 0
2995 01:24:09.927185 12, 0x0, sum = 1
2996 01:24:09.930068 13, 0x0, sum = 2
2997 01:24:09.930153 14, 0x0, sum = 3
2998 01:24:09.933628 15, 0x0, sum = 4
2999 01:24:09.933710 best_step = 13
3000 01:24:09.933773
3001 01:24:09.933831 ==
3002 01:24:09.936930 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 01:24:09.940565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 01:24:09.943843 ==
3005 01:24:09.943924 RX Vref Scan: 0
3006 01:24:09.943987
3007 01:24:09.946856 RX Vref 0 -> 0, step: 1
3008 01:24:09.946937
3009 01:24:09.950375 RX Delay -21 -> 252, step: 4
3010 01:24:09.953961 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3011 01:24:09.956998 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3012 01:24:09.960429 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3013 01:24:09.967106 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3014 01:24:09.970767 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3015 01:24:09.973732 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3016 01:24:09.977611 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3017 01:24:09.980773 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3018 01:24:09.984035 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3019 01:24:09.990671 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3020 01:24:09.993848 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3021 01:24:09.996980 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3022 01:24:10.000541 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3023 01:24:10.003809 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3024 01:24:10.010897 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3025 01:24:10.013887 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3026 01:24:10.013954 ==
3027 01:24:10.017428 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 01:24:10.020291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 01:24:10.020387 ==
3030 01:24:10.023921 DQS Delay:
3031 01:24:10.024023 DQS0 = 0, DQS1 = 0
3032 01:24:10.024115 DQM Delay:
3033 01:24:10.027193 DQM0 = 114, DQM1 = 104
3034 01:24:10.027294 DQ Delay:
3035 01:24:10.030289 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3036 01:24:10.033572 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =120
3037 01:24:10.037285 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3038 01:24:10.043797 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3039 01:24:10.043873
3040 01:24:10.043935
3041 01:24:10.050643 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3042 01:24:10.053889 CH0 RK1: MR19=403, MR18=4F6
3043 01:24:10.060887 CH0_RK1: MR19=0x403, MR18=0x4F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3044 01:24:10.060959 [RxdqsGatingPostProcess] freq 1200
3045 01:24:10.067390 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3046 01:24:10.070572 best DQS0 dly(2T, 0.5T) = (0, 12)
3047 01:24:10.074438 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 01:24:10.077422 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3049 01:24:10.080748 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 01:24:10.084209 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 01:24:10.087368 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 01:24:10.090828 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 01:24:10.094470 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 01:24:10.094567 Pre-setting of DQS Precalculation
3055 01:24:10.101249 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3056 01:24:10.101326 ==
3057 01:24:10.104199 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 01:24:10.107892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 01:24:10.107991 ==
3060 01:24:10.114691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3061 01:24:10.121568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3062 01:24:10.128314 [CA 0] Center 38 (8~68) winsize 61
3063 01:24:10.131863 [CA 1] Center 38 (8~68) winsize 61
3064 01:24:10.135467 [CA 2] Center 35 (5~65) winsize 61
3065 01:24:10.138443 [CA 3] Center 34 (4~65) winsize 62
3066 01:24:10.142155 [CA 4] Center 34 (4~65) winsize 62
3067 01:24:10.145180 [CA 5] Center 34 (4~64) winsize 61
3068 01:24:10.145279
3069 01:24:10.148533 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3070 01:24:10.148615
3071 01:24:10.151711 [CATrainingPosCal] consider 1 rank data
3072 01:24:10.155563 u2DelayCellTimex100 = 270/100 ps
3073 01:24:10.158391 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3074 01:24:10.161961 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3075 01:24:10.165362 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3076 01:24:10.168864 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3077 01:24:10.175257 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3078 01:24:10.179146 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3079 01:24:10.179215
3080 01:24:10.182091 CA PerBit enable=1, Macro0, CA PI delay=34
3081 01:24:10.182167
3082 01:24:10.185479 [CBTSetCACLKResult] CA Dly = 34
3083 01:24:10.185550 CS Dly: 6 (0~37)
3084 01:24:10.185615 ==
3085 01:24:10.189080 Dram Type= 6, Freq= 0, CH_1, rank 1
3086 01:24:10.195706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 01:24:10.195779 ==
3088 01:24:10.198698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 01:24:10.205367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3090 01:24:10.214025 [CA 0] Center 38 (8~68) winsize 61
3091 01:24:10.217291 [CA 1] Center 38 (8~68) winsize 61
3092 01:24:10.220983 [CA 2] Center 34 (4~65) winsize 62
3093 01:24:10.224242 [CA 3] Center 34 (4~65) winsize 62
3094 01:24:10.227076 [CA 4] Center 34 (4~65) winsize 62
3095 01:24:10.230634 [CA 5] Center 33 (3~64) winsize 62
3096 01:24:10.230714
3097 01:24:10.233824 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3098 01:24:10.233896
3099 01:24:10.237411 [CATrainingPosCal] consider 2 rank data
3100 01:24:10.240451 u2DelayCellTimex100 = 270/100 ps
3101 01:24:10.244355 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3102 01:24:10.247810 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3103 01:24:10.250863 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3104 01:24:10.257193 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3105 01:24:10.260933 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3106 01:24:10.264079 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3107 01:24:10.264149
3108 01:24:10.267729 CA PerBit enable=1, Macro0, CA PI delay=34
3109 01:24:10.267808
3110 01:24:10.270815 [CBTSetCACLKResult] CA Dly = 34
3111 01:24:10.270885 CS Dly: 7 (0~40)
3112 01:24:10.270949
3113 01:24:10.274258 ----->DramcWriteLeveling(PI) begin...
3114 01:24:10.274339 ==
3115 01:24:10.277830 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 01:24:10.284507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 01:24:10.284586 ==
3118 01:24:10.287980 Write leveling (Byte 0): 25 => 25
3119 01:24:10.288055 Write leveling (Byte 1): 30 => 30
3120 01:24:10.290948 DramcWriteLeveling(PI) end<-----
3121 01:24:10.291024
3122 01:24:10.291086 ==
3123 01:24:10.294513 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 01:24:10.301570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 01:24:10.301679 ==
3126 01:24:10.305264 [Gating] SW mode calibration
3127 01:24:10.311394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3128 01:24:10.314583 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3129 01:24:10.321792 0 15 0 | B1->B0 | 2828 2424 | 1 1 | (0 0) (0 0)
3130 01:24:10.324554 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 01:24:10.328054 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 01:24:10.331723 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 01:24:10.338358 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 01:24:10.341653 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 01:24:10.344985 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 01:24:10.351594 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3137 01:24:10.355090 1 0 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3138 01:24:10.358259 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 01:24:10.365447 1 0 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3140 01:24:10.368245 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 01:24:10.371776 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 01:24:10.378410 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 01:24:10.381813 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 01:24:10.385155 1 0 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3145 01:24:10.388768 1 1 0 | B1->B0 | 4242 3333 | 0 0 | (0 0) (0 0)
3146 01:24:10.395300 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 01:24:10.398441 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 01:24:10.401810 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 01:24:10.409013 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 01:24:10.412474 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 01:24:10.415716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 01:24:10.422592 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3153 01:24:10.425601 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3154 01:24:10.428821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 01:24:10.435586 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 01:24:10.439180 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 01:24:10.442328 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 01:24:10.445585 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 01:24:10.452310 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 01:24:10.456130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 01:24:10.459243 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 01:24:10.465805 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 01:24:10.468969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 01:24:10.472292 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 01:24:10.479327 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 01:24:10.482745 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 01:24:10.486134 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 01:24:10.492500 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3169 01:24:10.496229 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3170 01:24:10.499252 Total UI for P1: 0, mck2ui 16
3171 01:24:10.502693 best dqsien dly found for B1: ( 1, 3, 30)
3172 01:24:10.506248 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 01:24:10.509560 Total UI for P1: 0, mck2ui 16
3174 01:24:10.512923 best dqsien dly found for B0: ( 1, 3, 30)
3175 01:24:10.516281 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3176 01:24:10.519553 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3177 01:24:10.519643
3178 01:24:10.523374 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3179 01:24:10.526475 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3180 01:24:10.529781 [Gating] SW calibration Done
3181 01:24:10.529862 ==
3182 01:24:10.532936 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 01:24:10.536312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 01:24:10.540017 ==
3185 01:24:10.540098 RX Vref Scan: 0
3186 01:24:10.540162
3187 01:24:10.543219 RX Vref 0 -> 0, step: 1
3188 01:24:10.543300
3189 01:24:10.543363 RX Delay -40 -> 252, step: 8
3190 01:24:10.550066 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3191 01:24:10.553769 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3192 01:24:10.556709 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3193 01:24:10.560038 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3194 01:24:10.563479 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3195 01:24:10.570486 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3196 01:24:10.573753 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3197 01:24:10.577106 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3198 01:24:10.580398 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3199 01:24:10.583970 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3200 01:24:10.587312 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3201 01:24:10.593899 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3202 01:24:10.597053 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3203 01:24:10.600601 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3204 01:24:10.604269 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3205 01:24:10.607335 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3206 01:24:10.610704 ==
3207 01:24:10.610789 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 01:24:10.617301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 01:24:10.617386 ==
3210 01:24:10.617472 DQS Delay:
3211 01:24:10.620742 DQS0 = 0, DQS1 = 0
3212 01:24:10.620825 DQM Delay:
3213 01:24:10.624054 DQM0 = 116, DQM1 = 108
3214 01:24:10.624174 DQ Delay:
3215 01:24:10.627611 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3216 01:24:10.630764 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3217 01:24:10.634156 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3218 01:24:10.637637 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3219 01:24:10.637720
3220 01:24:10.637783
3221 01:24:10.637841 ==
3222 01:24:10.641104 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 01:24:10.644478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 01:24:10.647544 ==
3225 01:24:10.647625
3226 01:24:10.647688
3227 01:24:10.647746 TX Vref Scan disable
3228 01:24:10.650984 == TX Byte 0 ==
3229 01:24:10.654342 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3230 01:24:10.657959 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3231 01:24:10.661217 == TX Byte 1 ==
3232 01:24:10.664541 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3233 01:24:10.667921 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3234 01:24:10.668003 ==
3235 01:24:10.671599 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 01:24:10.677799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 01:24:10.677882 ==
3238 01:24:10.688402 TX Vref=22, minBit 4, minWin=25, winSum=411
3239 01:24:10.692073 TX Vref=24, minBit 1, minWin=25, winSum=415
3240 01:24:10.695097 TX Vref=26, minBit 13, minWin=25, winSum=420
3241 01:24:10.698596 TX Vref=28, minBit 13, minWin=25, winSum=426
3242 01:24:10.702438 TX Vref=30, minBit 1, minWin=26, winSum=427
3243 01:24:10.708526 TX Vref=32, minBit 13, minWin=25, winSum=426
3244 01:24:10.712166 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3245 01:24:10.712248
3246 01:24:10.715397 Final TX Range 1 Vref 30
3247 01:24:10.715479
3248 01:24:10.715542 ==
3249 01:24:10.718667 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 01:24:10.722014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 01:24:10.722097 ==
3252 01:24:10.722159
3253 01:24:10.725455
3254 01:24:10.725536 TX Vref Scan disable
3255 01:24:10.728862 == TX Byte 0 ==
3256 01:24:10.732024 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3257 01:24:10.735561 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3258 01:24:10.739028 == TX Byte 1 ==
3259 01:24:10.742467 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3260 01:24:10.745676 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3261 01:24:10.745758
3262 01:24:10.749077 [DATLAT]
3263 01:24:10.749159 Freq=1200, CH1 RK0
3264 01:24:10.749222
3265 01:24:10.752350 DATLAT Default: 0xd
3266 01:24:10.752431 0, 0xFFFF, sum = 0
3267 01:24:10.755956 1, 0xFFFF, sum = 0
3268 01:24:10.756039 2, 0xFFFF, sum = 0
3269 01:24:10.758899 3, 0xFFFF, sum = 0
3270 01:24:10.758982 4, 0xFFFF, sum = 0
3271 01:24:10.762331 5, 0xFFFF, sum = 0
3272 01:24:10.762444 6, 0xFFFF, sum = 0
3273 01:24:10.765857 7, 0xFFFF, sum = 0
3274 01:24:10.765940 8, 0xFFFF, sum = 0
3275 01:24:10.769229 9, 0xFFFF, sum = 0
3276 01:24:10.769311 10, 0xFFFF, sum = 0
3277 01:24:10.772999 11, 0xFFFF, sum = 0
3278 01:24:10.773094 12, 0x0, sum = 1
3279 01:24:10.775976 13, 0x0, sum = 2
3280 01:24:10.776059 14, 0x0, sum = 3
3281 01:24:10.779383 15, 0x0, sum = 4
3282 01:24:10.779466 best_step = 13
3283 01:24:10.779530
3284 01:24:10.779588 ==
3285 01:24:10.782401 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 01:24:10.789205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 01:24:10.789288 ==
3288 01:24:10.789387 RX Vref Scan: 1
3289 01:24:10.789445
3290 01:24:10.793014 Set Vref Range= 32 -> 127
3291 01:24:10.793095
3292 01:24:10.795889 RX Vref 32 -> 127, step: 1
3293 01:24:10.795970
3294 01:24:10.796032 RX Delay -21 -> 252, step: 4
3295 01:24:10.796092
3296 01:24:10.799353 Set Vref, RX VrefLevel [Byte0]: 32
3297 01:24:10.802666 [Byte1]: 32
3298 01:24:10.807213
3299 01:24:10.807293 Set Vref, RX VrefLevel [Byte0]: 33
3300 01:24:10.810893 [Byte1]: 33
3301 01:24:10.815176
3302 01:24:10.815256 Set Vref, RX VrefLevel [Byte0]: 34
3303 01:24:10.818752 [Byte1]: 34
3304 01:24:10.823067
3305 01:24:10.823147 Set Vref, RX VrefLevel [Byte0]: 35
3306 01:24:10.826152 [Byte1]: 35
3307 01:24:10.831116
3308 01:24:10.831196 Set Vref, RX VrefLevel [Byte0]: 36
3309 01:24:10.834348 [Byte1]: 36
3310 01:24:10.838771
3311 01:24:10.838856 Set Vref, RX VrefLevel [Byte0]: 37
3312 01:24:10.842426 [Byte1]: 37
3313 01:24:10.846577
3314 01:24:10.846657 Set Vref, RX VrefLevel [Byte0]: 38
3315 01:24:10.850076 [Byte1]: 38
3316 01:24:10.854659
3317 01:24:10.854740 Set Vref, RX VrefLevel [Byte0]: 39
3318 01:24:10.858193 [Byte1]: 39
3319 01:24:10.862773
3320 01:24:10.862853 Set Vref, RX VrefLevel [Byte0]: 40
3321 01:24:10.865590 [Byte1]: 40
3322 01:24:10.870341
3323 01:24:10.870424 Set Vref, RX VrefLevel [Byte0]: 41
3324 01:24:10.873823 [Byte1]: 41
3325 01:24:10.878375
3326 01:24:10.878455 Set Vref, RX VrefLevel [Byte0]: 42
3327 01:24:10.881907 [Byte1]: 42
3328 01:24:10.886388
3329 01:24:10.886468 Set Vref, RX VrefLevel [Byte0]: 43
3330 01:24:10.889581 [Byte1]: 43
3331 01:24:10.894120
3332 01:24:10.894200 Set Vref, RX VrefLevel [Byte0]: 44
3333 01:24:10.897526 [Byte1]: 44
3334 01:24:10.902359
3335 01:24:10.902439 Set Vref, RX VrefLevel [Byte0]: 45
3336 01:24:10.905335 [Byte1]: 45
3337 01:24:10.910418
3338 01:24:10.910498 Set Vref, RX VrefLevel [Byte0]: 46
3339 01:24:10.913533 [Byte1]: 46
3340 01:24:10.918097
3341 01:24:10.918177 Set Vref, RX VrefLevel [Byte0]: 47
3342 01:24:10.921449 [Byte1]: 47
3343 01:24:10.926187
3344 01:24:10.926267 Set Vref, RX VrefLevel [Byte0]: 48
3345 01:24:10.929252 [Byte1]: 48
3346 01:24:10.933761
3347 01:24:10.933841 Set Vref, RX VrefLevel [Byte0]: 49
3348 01:24:10.937433 [Byte1]: 49
3349 01:24:10.941651
3350 01:24:10.941731 Set Vref, RX VrefLevel [Byte0]: 50
3351 01:24:10.945044 [Byte1]: 50
3352 01:24:10.949527
3353 01:24:10.949609 Set Vref, RX VrefLevel [Byte0]: 51
3354 01:24:10.952918 [Byte1]: 51
3355 01:24:10.957849
3356 01:24:10.957929 Set Vref, RX VrefLevel [Byte0]: 52
3357 01:24:10.961370 [Byte1]: 52
3358 01:24:10.965947
3359 01:24:10.966028 Set Vref, RX VrefLevel [Byte0]: 53
3360 01:24:10.968978 [Byte1]: 53
3361 01:24:10.973417
3362 01:24:10.973497 Set Vref, RX VrefLevel [Byte0]: 54
3363 01:24:10.976922 [Byte1]: 54
3364 01:24:10.981589
3365 01:24:10.981670 Set Vref, RX VrefLevel [Byte0]: 55
3366 01:24:10.984633 [Byte1]: 55
3367 01:24:10.989119
3368 01:24:10.989199 Set Vref, RX VrefLevel [Byte0]: 56
3369 01:24:10.992569 [Byte1]: 56
3370 01:24:10.996896
3371 01:24:10.996977 Set Vref, RX VrefLevel [Byte0]: 57
3372 01:24:11.000652 [Byte1]: 57
3373 01:24:11.005013
3374 01:24:11.005093 Set Vref, RX VrefLevel [Byte0]: 58
3375 01:24:11.008685 [Byte1]: 58
3376 01:24:11.012900
3377 01:24:11.012981 Set Vref, RX VrefLevel [Byte0]: 59
3378 01:24:11.016485 [Byte1]: 59
3379 01:24:11.021164
3380 01:24:11.021245 Set Vref, RX VrefLevel [Byte0]: 60
3381 01:24:11.024081 [Byte1]: 60
3382 01:24:11.028954
3383 01:24:11.029035 Set Vref, RX VrefLevel [Byte0]: 61
3384 01:24:11.031950 [Byte1]: 61
3385 01:24:11.037052
3386 01:24:11.037136 Set Vref, RX VrefLevel [Byte0]: 62
3387 01:24:11.040316 [Byte1]: 62
3388 01:24:11.044582
3389 01:24:11.044662 Set Vref, RX VrefLevel [Byte0]: 63
3390 01:24:11.047946 [Byte1]: 63
3391 01:24:11.052882
3392 01:24:11.052964 Set Vref, RX VrefLevel [Byte0]: 64
3393 01:24:11.055860 [Byte1]: 64
3394 01:24:11.060475
3395 01:24:11.060556 Set Vref, RX VrefLevel [Byte0]: 65
3396 01:24:11.063950 [Byte1]: 65
3397 01:24:11.068569
3398 01:24:11.068650 Set Vref, RX VrefLevel [Byte0]: 66
3399 01:24:11.071699 [Byte1]: 66
3400 01:24:11.076609
3401 01:24:11.076712 Set Vref, RX VrefLevel [Byte0]: 67
3402 01:24:11.079509 [Byte1]: 67
3403 01:24:11.084321
3404 01:24:11.084402 Set Vref, RX VrefLevel [Byte0]: 68
3405 01:24:11.087706 [Byte1]: 68
3406 01:24:11.092299
3407 01:24:11.092379 Set Vref, RX VrefLevel [Byte0]: 69
3408 01:24:11.095735 [Byte1]: 69
3409 01:24:11.100098
3410 01:24:11.100183 Set Vref, RX VrefLevel [Byte0]: 70
3411 01:24:11.103436 [Byte1]: 70
3412 01:24:11.108066
3413 01:24:11.108147 Final RX Vref Byte 0 = 59 to rank0
3414 01:24:11.111381 Final RX Vref Byte 1 = 53 to rank0
3415 01:24:11.114716 Final RX Vref Byte 0 = 59 to rank1
3416 01:24:11.118288 Final RX Vref Byte 1 = 53 to rank1==
3417 01:24:11.121492 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 01:24:11.124866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 01:24:11.128117 ==
3420 01:24:11.128220 DQS Delay:
3421 01:24:11.128342 DQS0 = 0, DQS1 = 0
3422 01:24:11.131394 DQM Delay:
3423 01:24:11.131478 DQM0 = 116, DQM1 = 109
3424 01:24:11.134993 DQ Delay:
3425 01:24:11.138810 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3426 01:24:11.141600 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3427 01:24:11.145003 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =104
3428 01:24:11.148311 DQ12 =118, DQ13 =114, DQ14 =116, DQ15 =114
3429 01:24:11.148395
3430 01:24:11.148494
3431 01:24:11.155099 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3432 01:24:11.158436 CH1 RK0: MR19=303, MR18=FFE3
3433 01:24:11.164954 CH1_RK0: MR19=0x303, MR18=0xFFE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3434 01:24:11.165038
3435 01:24:11.168662 ----->DramcWriteLeveling(PI) begin...
3436 01:24:11.168769 ==
3437 01:24:11.171917 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 01:24:11.175133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 01:24:11.175217 ==
3440 01:24:11.178392 Write leveling (Byte 0): 26 => 26
3441 01:24:11.181954 Write leveling (Byte 1): 30 => 30
3442 01:24:11.185140 DramcWriteLeveling(PI) end<-----
3443 01:24:11.185248
3444 01:24:11.185349 ==
3445 01:24:11.188588 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 01:24:11.192191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 01:24:11.192276 ==
3448 01:24:11.195506 [Gating] SW mode calibration
3449 01:24:11.202261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 01:24:11.208970 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 01:24:11.212557 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3452 01:24:11.215429 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3453 01:24:11.222437 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 01:24:11.225759 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 01:24:11.229009 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 01:24:11.235706 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3457 01:24:11.239072 0 15 24 | B1->B0 | 3434 2727 | 0 1 | (0 0) (1 0)
3458 01:24:11.242648 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3459 01:24:11.249081 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 01:24:11.252363 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 01:24:11.255913 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 01:24:11.263214 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 01:24:11.266170 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3464 01:24:11.269651 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 01:24:11.273166 1 0 24 | B1->B0 | 2424 3e3e | 0 1 | (0 0) (0 0)
3466 01:24:11.279428 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3467 01:24:11.282730 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 01:24:11.286371 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 01:24:11.293177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 01:24:11.296931 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 01:24:11.299877 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 01:24:11.306577 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 01:24:11.309450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3474 01:24:11.312933 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3475 01:24:11.319513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 01:24:11.323348 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 01:24:11.326593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 01:24:11.330170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 01:24:11.336216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 01:24:11.339873 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 01:24:11.343576 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 01:24:11.349558 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 01:24:11.352993 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 01:24:11.356451 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 01:24:11.363012 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 01:24:11.366516 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 01:24:11.369852 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 01:24:11.376474 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3489 01:24:11.379605 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 01:24:11.383164 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3491 01:24:11.386592 Total UI for P1: 0, mck2ui 16
3492 01:24:11.389716 best dqsien dly found for B0: ( 1, 3, 22)
3493 01:24:11.396276 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 01:24:11.396380 Total UI for P1: 0, mck2ui 16
3495 01:24:11.403193 best dqsien dly found for B1: ( 1, 3, 26)
3496 01:24:11.406501 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3497 01:24:11.409919 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3498 01:24:11.410017
3499 01:24:11.412909 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3500 01:24:11.416441 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3501 01:24:11.419555 [Gating] SW calibration Done
3502 01:24:11.419626 ==
3503 01:24:11.423081 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 01:24:11.426428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 01:24:11.426528 ==
3506 01:24:11.429599 RX Vref Scan: 0
3507 01:24:11.429678
3508 01:24:11.429767 RX Vref 0 -> 0, step: 1
3509 01:24:11.429851
3510 01:24:11.433111 RX Delay -40 -> 252, step: 8
3511 01:24:11.436612 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3512 01:24:11.443324 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3513 01:24:11.446484 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3514 01:24:11.449888 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3515 01:24:11.453504 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3516 01:24:11.456644 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3517 01:24:11.459982 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3518 01:24:11.466392 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3519 01:24:11.469859 iDelay=192, Bit 8, Center 99 (32 ~ 167) 136
3520 01:24:11.473336 iDelay=192, Bit 9, Center 99 (32 ~ 167) 136
3521 01:24:11.476474 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3522 01:24:11.479825 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3523 01:24:11.486521 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3524 01:24:11.490144 iDelay=192, Bit 13, Center 123 (56 ~ 191) 136
3525 01:24:11.493350 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3526 01:24:11.497029 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3527 01:24:11.497103 ==
3528 01:24:11.499903 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 01:24:11.507005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 01:24:11.507113 ==
3531 01:24:11.507204 DQS Delay:
3532 01:24:11.507290 DQS0 = 0, DQS1 = 0
3533 01:24:11.510125 DQM Delay:
3534 01:24:11.510197 DQM0 = 112, DQM1 = 111
3535 01:24:11.513236 DQ Delay:
3536 01:24:11.516660 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3537 01:24:11.519889 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3538 01:24:11.523646 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3539 01:24:11.527093 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3540 01:24:11.527198
3541 01:24:11.527288
3542 01:24:11.527373 ==
3543 01:24:11.530417 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 01:24:11.533927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 01:24:11.534028 ==
3546 01:24:11.534117
3547 01:24:11.534201
3548 01:24:11.536794 TX Vref Scan disable
3549 01:24:11.540231 == TX Byte 0 ==
3550 01:24:11.543614 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 01:24:11.546883 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 01:24:11.550369 == TX Byte 1 ==
3553 01:24:11.553559 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3554 01:24:11.557063 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3555 01:24:11.557144 ==
3556 01:24:11.560175 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 01:24:11.563475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 01:24:11.566857 ==
3559 01:24:11.577232 TX Vref=22, minBit 1, minWin=25, winSum=415
3560 01:24:11.580519 TX Vref=24, minBit 0, minWin=25, winSum=421
3561 01:24:11.583677 TX Vref=26, minBit 0, minWin=26, winSum=426
3562 01:24:11.587451 TX Vref=28, minBit 1, minWin=26, winSum=428
3563 01:24:11.590751 TX Vref=30, minBit 13, minWin=25, winSum=426
3564 01:24:11.594001 TX Vref=32, minBit 15, minWin=25, winSum=426
3565 01:24:11.600513 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3566 01:24:11.600614
3567 01:24:11.603987 Final TX Range 1 Vref 28
3568 01:24:11.604058
3569 01:24:11.604116 ==
3570 01:24:11.607258 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 01:24:11.610866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 01:24:11.610937 ==
3573 01:24:11.610994
3574 01:24:11.613853
3575 01:24:11.613947 TX Vref Scan disable
3576 01:24:11.617256 == TX Byte 0 ==
3577 01:24:11.620412 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3578 01:24:11.624287 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3579 01:24:11.627257 == TX Byte 1 ==
3580 01:24:11.630978 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3581 01:24:11.633801 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3582 01:24:11.633898
3583 01:24:11.637134 [DATLAT]
3584 01:24:11.637207 Freq=1200, CH1 RK1
3585 01:24:11.637267
3586 01:24:11.640880 DATLAT Default: 0xd
3587 01:24:11.640953 0, 0xFFFF, sum = 0
3588 01:24:11.644431 1, 0xFFFF, sum = 0
3589 01:24:11.644527 2, 0xFFFF, sum = 0
3590 01:24:11.647520 3, 0xFFFF, sum = 0
3591 01:24:11.647618 4, 0xFFFF, sum = 0
3592 01:24:11.650476 5, 0xFFFF, sum = 0
3593 01:24:11.650569 6, 0xFFFF, sum = 0
3594 01:24:11.654093 7, 0xFFFF, sum = 0
3595 01:24:11.657192 8, 0xFFFF, sum = 0
3596 01:24:11.657263 9, 0xFFFF, sum = 0
3597 01:24:11.660776 10, 0xFFFF, sum = 0
3598 01:24:11.660873 11, 0xFFFF, sum = 0
3599 01:24:11.664100 12, 0x0, sum = 1
3600 01:24:11.664206 13, 0x0, sum = 2
3601 01:24:11.667149 14, 0x0, sum = 3
3602 01:24:11.667247 15, 0x0, sum = 4
3603 01:24:11.667334 best_step = 13
3604 01:24:11.667428
3605 01:24:11.670685 ==
3606 01:24:11.674222 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 01:24:11.677322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 01:24:11.677404 ==
3609 01:24:11.677467 RX Vref Scan: 0
3610 01:24:11.677525
3611 01:24:11.680715 RX Vref 0 -> 0, step: 1
3612 01:24:11.680797
3613 01:24:11.683855 RX Delay -13 -> 252, step: 4
3614 01:24:11.687174 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3615 01:24:11.693977 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3616 01:24:11.697396 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3617 01:24:11.700464 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3618 01:24:11.703993 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3619 01:24:11.706971 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3620 01:24:11.710610 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3621 01:24:11.717172 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3622 01:24:11.720617 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3623 01:24:11.723817 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3624 01:24:11.727320 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3625 01:24:11.730601 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3626 01:24:11.737329 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3627 01:24:11.740569 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3628 01:24:11.743990 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3629 01:24:11.747813 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3630 01:24:11.747895 ==
3631 01:24:11.750404 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 01:24:11.757277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 01:24:11.757359 ==
3634 01:24:11.757424 DQS Delay:
3635 01:24:11.760430 DQS0 = 0, DQS1 = 0
3636 01:24:11.760511 DQM Delay:
3637 01:24:11.760574 DQM0 = 113, DQM1 = 109
3638 01:24:11.763840 DQ Delay:
3639 01:24:11.767474 DQ0 =112, DQ1 =108, DQ2 =104, DQ3 =112
3640 01:24:11.770502 DQ4 =116, DQ5 =124, DQ6 =120, DQ7 =110
3641 01:24:11.774627 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3642 01:24:11.777398 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3643 01:24:11.777480
3644 01:24:11.777543
3645 01:24:11.783973 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3646 01:24:11.787557 CH1 RK1: MR19=303, MR18=F7FE
3647 01:24:11.793963 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3648 01:24:11.797763 [RxdqsGatingPostProcess] freq 1200
3649 01:24:11.803869 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 01:24:11.807377 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 01:24:11.807458 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 01:24:11.810673 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 01:24:11.814188 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 01:24:11.817127 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 01:24:11.820488 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 01:24:11.824351 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 01:24:11.828000 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 01:24:11.830570 Pre-setting of DQS Precalculation
3659 01:24:11.837156 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 01:24:11.844198 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 01:24:11.850877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 01:24:11.850960
3663 01:24:11.851023
3664 01:24:11.854269 [Calibration Summary] 2400 Mbps
3665 01:24:11.854380 CH 0, Rank 0
3666 01:24:11.857405 SW Impedance : PASS
3667 01:24:11.860919 DUTY Scan : NO K
3668 01:24:11.861029 ZQ Calibration : PASS
3669 01:24:11.864022 Jitter Meter : NO K
3670 01:24:11.867846 CBT Training : PASS
3671 01:24:11.867943 Write leveling : PASS
3672 01:24:11.870783 RX DQS gating : PASS
3673 01:24:11.870880 RX DQ/DQS(RDDQC) : PASS
3674 01:24:11.874208 TX DQ/DQS : PASS
3675 01:24:11.877539 RX DATLAT : PASS
3676 01:24:11.877608 RX DQ/DQS(Engine): PASS
3677 01:24:11.880586 TX OE : NO K
3678 01:24:11.880706 All Pass.
3679 01:24:11.880769
3680 01:24:11.884523 CH 0, Rank 1
3681 01:24:11.884590 SW Impedance : PASS
3682 01:24:11.887434 DUTY Scan : NO K
3683 01:24:11.890824 ZQ Calibration : PASS
3684 01:24:11.890894 Jitter Meter : NO K
3685 01:24:11.894007 CBT Training : PASS
3686 01:24:11.897830 Write leveling : PASS
3687 01:24:11.897907 RX DQS gating : PASS
3688 01:24:11.900775 RX DQ/DQS(RDDQC) : PASS
3689 01:24:11.904234 TX DQ/DQS : PASS
3690 01:24:11.904302 RX DATLAT : PASS
3691 01:24:11.907572 RX DQ/DQS(Engine): PASS
3692 01:24:11.907669 TX OE : NO K
3693 01:24:11.910594 All Pass.
3694 01:24:11.910688
3695 01:24:11.910773 CH 1, Rank 0
3696 01:24:11.913952 SW Impedance : PASS
3697 01:24:11.914020 DUTY Scan : NO K
3698 01:24:11.917420 ZQ Calibration : PASS
3699 01:24:11.920573 Jitter Meter : NO K
3700 01:24:11.920692 CBT Training : PASS
3701 01:24:11.924324 Write leveling : PASS
3702 01:24:11.927243 RX DQS gating : PASS
3703 01:24:11.927349 RX DQ/DQS(RDDQC) : PASS
3704 01:24:11.930867 TX DQ/DQS : PASS
3705 01:24:11.934095 RX DATLAT : PASS
3706 01:24:11.934194 RX DQ/DQS(Engine): PASS
3707 01:24:11.937342 TX OE : NO K
3708 01:24:11.937414 All Pass.
3709 01:24:11.937475
3710 01:24:11.940491 CH 1, Rank 1
3711 01:24:11.940587 SW Impedance : PASS
3712 01:24:11.943976 DUTY Scan : NO K
3713 01:24:11.947246 ZQ Calibration : PASS
3714 01:24:11.947350 Jitter Meter : NO K
3715 01:24:11.950788 CBT Training : PASS
3716 01:24:11.954169 Write leveling : PASS
3717 01:24:11.954267 RX DQS gating : PASS
3718 01:24:11.957633 RX DQ/DQS(RDDQC) : PASS
3719 01:24:11.957704 TX DQ/DQS : PASS
3720 01:24:11.961146 RX DATLAT : PASS
3721 01:24:11.964400 RX DQ/DQS(Engine): PASS
3722 01:24:11.964503 TX OE : NO K
3723 01:24:11.967526 All Pass.
3724 01:24:11.967629
3725 01:24:11.967721 DramC Write-DBI off
3726 01:24:11.970663 PER_BANK_REFRESH: Hybrid Mode
3727 01:24:11.974525 TX_TRACKING: ON
3728 01:24:11.980983 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 01:24:11.984536 [FAST_K] Save calibration result to emmc
3730 01:24:11.987431 dramc_set_vcore_voltage set vcore to 650000
3731 01:24:11.990953 Read voltage for 600, 5
3732 01:24:11.991057 Vio18 = 0
3733 01:24:11.994070 Vcore = 650000
3734 01:24:11.994164 Vdram = 0
3735 01:24:11.994260 Vddq = 0
3736 01:24:11.997697 Vmddr = 0
3737 01:24:12.001124 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 01:24:12.007577 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 01:24:12.007676 MEM_TYPE=3, freq_sel=19
3740 01:24:12.010887 sv_algorithm_assistance_LP4_1600
3741 01:24:12.014485 ============ PULL DRAM RESETB DOWN ============
3742 01:24:12.021193 ========== PULL DRAM RESETB DOWN end =========
3743 01:24:12.024910 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 01:24:12.028036 ===================================
3745 01:24:12.031121 LPDDR4 DRAM CONFIGURATION
3746 01:24:12.034865 ===================================
3747 01:24:12.034969 EX_ROW_EN[0] = 0x0
3748 01:24:12.038272 EX_ROW_EN[1] = 0x0
3749 01:24:12.038342 LP4Y_EN = 0x0
3750 01:24:12.041649 WORK_FSP = 0x0
3751 01:24:12.041717 WL = 0x2
3752 01:24:12.044584 RL = 0x2
3753 01:24:12.044712 BL = 0x2
3754 01:24:12.048224 RPST = 0x0
3755 01:24:12.048318 RD_PRE = 0x0
3756 01:24:12.051376 WR_PRE = 0x1
3757 01:24:12.054839 WR_PST = 0x0
3758 01:24:12.054910 DBI_WR = 0x0
3759 01:24:12.058241 DBI_RD = 0x0
3760 01:24:12.058315 OTF = 0x1
3761 01:24:12.062007 ===================================
3762 01:24:12.064868 ===================================
3763 01:24:12.064936 ANA top config
3764 01:24:12.068398 ===================================
3765 01:24:12.071995 DLL_ASYNC_EN = 0
3766 01:24:12.074834 ALL_SLAVE_EN = 1
3767 01:24:12.078563 NEW_RANK_MODE = 1
3768 01:24:12.078672 DLL_IDLE_MODE = 1
3769 01:24:12.081712 LP45_APHY_COMB_EN = 1
3770 01:24:12.085320 TX_ODT_DIS = 1
3771 01:24:12.088258 NEW_8X_MODE = 1
3772 01:24:12.091746 ===================================
3773 01:24:12.095133 ===================================
3774 01:24:12.098441 data_rate = 1200
3775 01:24:12.098540 CKR = 1
3776 01:24:12.101667 DQ_P2S_RATIO = 8
3777 01:24:12.105434 ===================================
3778 01:24:12.108417 CA_P2S_RATIO = 8
3779 01:24:12.111866 DQ_CA_OPEN = 0
3780 01:24:12.115103 DQ_SEMI_OPEN = 0
3781 01:24:12.118660 CA_SEMI_OPEN = 0
3782 01:24:12.118731 CA_FULL_RATE = 0
3783 01:24:12.121679 DQ_CKDIV4_EN = 1
3784 01:24:12.125144 CA_CKDIV4_EN = 1
3785 01:24:12.129120 CA_PREDIV_EN = 0
3786 01:24:12.131900 PH8_DLY = 0
3787 01:24:12.132000 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 01:24:12.135069 DQ_AAMCK_DIV = 4
3789 01:24:12.138699 CA_AAMCK_DIV = 4
3790 01:24:12.141893 CA_ADMCK_DIV = 4
3791 01:24:12.144973 DQ_TRACK_CA_EN = 0
3792 01:24:12.148310 CA_PICK = 600
3793 01:24:12.151820 CA_MCKIO = 600
3794 01:24:12.151908 MCKIO_SEMI = 0
3795 01:24:12.155329 PLL_FREQ = 2288
3796 01:24:12.158573 DQ_UI_PI_RATIO = 32
3797 01:24:12.161940 CA_UI_PI_RATIO = 0
3798 01:24:12.165346 ===================================
3799 01:24:12.168623 ===================================
3800 01:24:12.171867 memory_type:LPDDR4
3801 01:24:12.171975 GP_NUM : 10
3802 01:24:12.175455 SRAM_EN : 1
3803 01:24:12.175554 MD32_EN : 0
3804 01:24:12.178745 ===================================
3805 01:24:12.181854 [ANA_INIT] >>>>>>>>>>>>>>
3806 01:24:12.185310 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 01:24:12.188515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 01:24:12.192287 ===================================
3809 01:24:12.195224 data_rate = 1200,PCW = 0X5800
3810 01:24:12.198814 ===================================
3811 01:24:12.202015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 01:24:12.205456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 01:24:12.212100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 01:24:12.218722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 01:24:12.221874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 01:24:12.225325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 01:24:12.225445 [ANA_INIT] flow start
3818 01:24:12.228866 [ANA_INIT] PLL >>>>>>>>
3819 01:24:12.232020 [ANA_INIT] PLL <<<<<<<<
3820 01:24:12.232135 [ANA_INIT] MIDPI >>>>>>>>
3821 01:24:12.235267 [ANA_INIT] MIDPI <<<<<<<<
3822 01:24:12.238812 [ANA_INIT] DLL >>>>>>>>
3823 01:24:12.238925 [ANA_INIT] flow end
3824 01:24:12.242279 ============ LP4 DIFF to SE enter ============
3825 01:24:12.249017 ============ LP4 DIFF to SE exit ============
3826 01:24:12.249099 [ANA_INIT] <<<<<<<<<<<<<
3827 01:24:12.251913 [Flow] Enable top DCM control >>>>>
3828 01:24:12.255538 [Flow] Enable top DCM control <<<<<
3829 01:24:12.258825 Enable DLL master slave shuffle
3830 01:24:12.265693 ==============================================================
3831 01:24:12.265776 Gating Mode config
3832 01:24:12.272253 ==============================================================
3833 01:24:12.275301 Config description:
3834 01:24:12.285817 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 01:24:12.289182 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 01:24:12.295442 SELPH_MODE 0: By rank 1: By Phase
3837 01:24:12.302312 ==============================================================
3838 01:24:12.302406 GAT_TRACK_EN = 1
3839 01:24:12.305806 RX_GATING_MODE = 2
3840 01:24:12.308906 RX_GATING_TRACK_MODE = 2
3841 01:24:12.312618 SELPH_MODE = 1
3842 01:24:12.315871 PICG_EARLY_EN = 1
3843 01:24:12.319471 VALID_LAT_VALUE = 1
3844 01:24:12.325737 ==============================================================
3845 01:24:12.328821 Enter into Gating configuration >>>>
3846 01:24:12.332516 Exit from Gating configuration <<<<
3847 01:24:12.336248 Enter into DVFS_PRE_config >>>>>
3848 01:24:12.345892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 01:24:12.349171 Exit from DVFS_PRE_config <<<<<
3850 01:24:12.352489 Enter into PICG configuration >>>>
3851 01:24:12.356017 Exit from PICG configuration <<<<
3852 01:24:12.356101 [RX_INPUT] configuration >>>>>
3853 01:24:12.359027 [RX_INPUT] configuration <<<<<
3854 01:24:12.366196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 01:24:12.369455 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 01:24:12.375910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 01:24:12.382323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 01:24:12.389078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 01:24:12.396069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 01:24:12.399325 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 01:24:12.402408 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 01:24:12.409284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 01:24:12.412797 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 01:24:12.415819 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 01:24:12.419571 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 01:24:12.422403 ===================================
3867 01:24:12.425813 LPDDR4 DRAM CONFIGURATION
3868 01:24:12.429429 ===================================
3869 01:24:12.433150 EX_ROW_EN[0] = 0x0
3870 01:24:12.433240 EX_ROW_EN[1] = 0x0
3871 01:24:12.436365 LP4Y_EN = 0x0
3872 01:24:12.436441 WORK_FSP = 0x0
3873 01:24:12.439245 WL = 0x2
3874 01:24:12.439327 RL = 0x2
3875 01:24:12.442773 BL = 0x2
3876 01:24:12.442845 RPST = 0x0
3877 01:24:12.446324 RD_PRE = 0x0
3878 01:24:12.446399 WR_PRE = 0x1
3879 01:24:12.449552 WR_PST = 0x0
3880 01:24:12.449663 DBI_WR = 0x0
3881 01:24:12.452853 DBI_RD = 0x0
3882 01:24:12.452931 OTF = 0x1
3883 01:24:12.455840 ===================================
3884 01:24:12.462268 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 01:24:12.465880 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 01:24:12.469328 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 01:24:12.472570 ===================================
3888 01:24:12.475733 LPDDR4 DRAM CONFIGURATION
3889 01:24:12.479326 ===================================
3890 01:24:12.482489 EX_ROW_EN[0] = 0x10
3891 01:24:12.482563 EX_ROW_EN[1] = 0x0
3892 01:24:12.485987 LP4Y_EN = 0x0
3893 01:24:12.486059 WORK_FSP = 0x0
3894 01:24:12.488816 WL = 0x2
3895 01:24:12.488885 RL = 0x2
3896 01:24:12.492378 BL = 0x2
3897 01:24:12.492449 RPST = 0x0
3898 01:24:12.495691 RD_PRE = 0x0
3899 01:24:12.495760 WR_PRE = 0x1
3900 01:24:12.498879 WR_PST = 0x0
3901 01:24:12.499002 DBI_WR = 0x0
3902 01:24:12.502407 DBI_RD = 0x0
3903 01:24:12.502480 OTF = 0x1
3904 01:24:12.505696 ===================================
3905 01:24:12.512234 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 01:24:12.516941 nWR fixed to 30
3907 01:24:12.520615 [ModeRegInit_LP4] CH0 RK0
3908 01:24:12.520698 [ModeRegInit_LP4] CH0 RK1
3909 01:24:12.523393 [ModeRegInit_LP4] CH1 RK0
3910 01:24:12.527319 [ModeRegInit_LP4] CH1 RK1
3911 01:24:12.527399 match AC timing 17
3912 01:24:12.533736 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 01:24:12.537413 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 01:24:12.540547 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 01:24:12.547288 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 01:24:12.550501 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 01:24:12.550609 ==
3918 01:24:12.554211 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 01:24:12.557130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 01:24:12.557209 ==
3921 01:24:12.564130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 01:24:12.571328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 01:24:12.573658 [CA 0] Center 36 (6~67) winsize 62
3924 01:24:12.576954 [CA 1] Center 36 (6~66) winsize 61
3925 01:24:12.580293 [CA 2] Center 34 (4~65) winsize 62
3926 01:24:12.584086 [CA 3] Center 34 (4~65) winsize 62
3927 01:24:12.586966 [CA 4] Center 34 (4~64) winsize 61
3928 01:24:12.590485 [CA 5] Center 33 (3~64) winsize 62
3929 01:24:12.590566
3930 01:24:12.593649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 01:24:12.593730
3932 01:24:12.597538 [CATrainingPosCal] consider 1 rank data
3933 01:24:12.600529 u2DelayCellTimex100 = 270/100 ps
3934 01:24:12.603538 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3935 01:24:12.606990 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3936 01:24:12.610260 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 01:24:12.614092 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3938 01:24:12.617066 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3939 01:24:12.620443 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 01:24:12.620540
3941 01:24:12.623870 CA PerBit enable=1, Macro0, CA PI delay=33
3942 01:24:12.623948
3943 01:24:12.627361 [CBTSetCACLKResult] CA Dly = 33
3944 01:24:12.630898 CS Dly: 4 (0~35)
3945 01:24:12.630978 ==
3946 01:24:12.633842 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 01:24:12.637119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 01:24:12.637198 ==
3949 01:24:12.644227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 01:24:12.650645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3951 01:24:12.654053 [CA 0] Center 36 (6~66) winsize 61
3952 01:24:12.657362 [CA 1] Center 36 (6~66) winsize 61
3953 01:24:12.660566 [CA 2] Center 34 (4~65) winsize 62
3954 01:24:12.663830 [CA 3] Center 34 (4~65) winsize 62
3955 01:24:12.667451 [CA 4] Center 33 (3~64) winsize 62
3956 01:24:12.670702 [CA 5] Center 33 (3~64) winsize 62
3957 01:24:12.670773
3958 01:24:12.674030 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3959 01:24:12.674103
3960 01:24:12.677328 [CATrainingPosCal] consider 2 rank data
3961 01:24:12.681077 u2DelayCellTimex100 = 270/100 ps
3962 01:24:12.684172 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 01:24:12.687403 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3964 01:24:12.691018 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 01:24:12.694910 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 01:24:12.697750 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3967 01:24:12.700994 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 01:24:12.701067
3969 01:24:12.704169 CA PerBit enable=1, Macro0, CA PI delay=33
3970 01:24:12.704240
3971 01:24:12.707358 [CBTSetCACLKResult] CA Dly = 33
3972 01:24:12.710965 CS Dly: 5 (0~37)
3973 01:24:12.711046
3974 01:24:12.713844 ----->DramcWriteLeveling(PI) begin...
3975 01:24:12.713926 ==
3976 01:24:12.717518 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 01:24:12.720785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 01:24:12.720867 ==
3979 01:24:12.724152 Write leveling (Byte 0): 32 => 32
3980 01:24:12.727689 Write leveling (Byte 1): 29 => 29
3981 01:24:12.730603 DramcWriteLeveling(PI) end<-----
3982 01:24:12.730704
3983 01:24:12.730781 ==
3984 01:24:12.734089 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 01:24:12.737497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 01:24:12.737575 ==
3987 01:24:12.740641 [Gating] SW mode calibration
3988 01:24:12.747339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 01:24:12.754068 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 01:24:12.757597 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 01:24:12.763946 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 01:24:12.767590 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 01:24:12.771424 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3994 01:24:12.773940 0 9 16 | B1->B0 | 3232 2b2b | 1 0 | (0 0) (0 0)
3995 01:24:12.780899 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 01:24:12.784206 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 01:24:12.787689 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 01:24:12.794343 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 01:24:12.797502 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 01:24:12.800629 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 01:24:12.807724 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4002 01:24:12.811051 0 10 16 | B1->B0 | 3232 3d3d | 0 0 | (0 0) (1 1)
4003 01:24:12.814236 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4004 01:24:12.821157 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 01:24:12.823926 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 01:24:12.827611 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 01:24:12.834226 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 01:24:12.837610 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 01:24:12.841169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 01:24:12.844442 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4011 01:24:12.851009 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 01:24:12.854126 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 01:24:12.857545 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 01:24:12.864380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 01:24:12.867784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 01:24:12.870908 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 01:24:12.878158 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 01:24:12.881451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 01:24:12.884556 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 01:24:12.891133 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 01:24:12.894862 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 01:24:12.897845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 01:24:12.904570 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 01:24:12.908192 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 01:24:12.911269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 01:24:12.914592 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4027 01:24:12.921526 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 01:24:12.924463 Total UI for P1: 0, mck2ui 16
4029 01:24:12.928285 best dqsien dly found for B0: ( 0, 13, 16)
4030 01:24:12.931111 Total UI for P1: 0, mck2ui 16
4031 01:24:12.934607 best dqsien dly found for B1: ( 0, 13, 16)
4032 01:24:12.937961 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4033 01:24:12.941231 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4034 01:24:12.941307
4035 01:24:12.944505 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4036 01:24:12.948286 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4037 01:24:12.951357 [Gating] SW calibration Done
4038 01:24:12.951436 ==
4039 01:24:12.955035 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 01:24:12.957898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 01:24:12.957973 ==
4042 01:24:12.961111 RX Vref Scan: 0
4043 01:24:12.961184
4044 01:24:12.961243 RX Vref 0 -> 0, step: 1
4045 01:24:12.964823
4046 01:24:12.964899 RX Delay -230 -> 252, step: 16
4047 01:24:12.971182 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4048 01:24:12.974890 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4049 01:24:12.977852 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4050 01:24:12.981461 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4051 01:24:12.984582 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4052 01:24:12.991534 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4053 01:24:12.994488 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4054 01:24:12.997967 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4055 01:24:13.001224 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4056 01:24:13.008014 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4057 01:24:13.011312 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4058 01:24:13.014946 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4059 01:24:13.018039 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4060 01:24:13.021683 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4061 01:24:13.028442 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4062 01:24:13.031555 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4063 01:24:13.031635 ==
4064 01:24:13.034686 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 01:24:13.038194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 01:24:13.038274 ==
4067 01:24:13.041478 DQS Delay:
4068 01:24:13.041554 DQS0 = 0, DQS1 = 0
4069 01:24:13.044423 DQM Delay:
4070 01:24:13.044493 DQM0 = 41, DQM1 = 34
4071 01:24:13.044563 DQ Delay:
4072 01:24:13.047976 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4073 01:24:13.051328 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4074 01:24:13.054577 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4075 01:24:13.057926 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4076 01:24:13.057998
4077 01:24:13.058064
4078 01:24:13.058124 ==
4079 01:24:13.061360 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 01:24:13.067901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 01:24:13.067978 ==
4082 01:24:13.068039
4083 01:24:13.068099
4084 01:24:13.068156 TX Vref Scan disable
4085 01:24:13.072301 == TX Byte 0 ==
4086 01:24:13.075342 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4087 01:24:13.078707 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4088 01:24:13.082114 == TX Byte 1 ==
4089 01:24:13.085661 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4090 01:24:13.088951 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4091 01:24:13.092488 ==
4092 01:24:13.092560 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 01:24:13.099151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 01:24:13.099228 ==
4095 01:24:13.099290
4096 01:24:13.099348
4097 01:24:13.102191 TX Vref Scan disable
4098 01:24:13.102259 == TX Byte 0 ==
4099 01:24:13.108936 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4100 01:24:13.112273 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4101 01:24:13.112345 == TX Byte 1 ==
4102 01:24:13.118701 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4103 01:24:13.121855 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4104 01:24:13.121933
4105 01:24:13.121997 [DATLAT]
4106 01:24:13.126335 Freq=600, CH0 RK0
4107 01:24:13.126416
4108 01:24:13.126479 DATLAT Default: 0x9
4109 01:24:13.128737 0, 0xFFFF, sum = 0
4110 01:24:13.128817 1, 0xFFFF, sum = 0
4111 01:24:13.132434 2, 0xFFFF, sum = 0
4112 01:24:13.132517 3, 0xFFFF, sum = 0
4113 01:24:13.135509 4, 0xFFFF, sum = 0
4114 01:24:13.135594 5, 0xFFFF, sum = 0
4115 01:24:13.138643 6, 0xFFFF, sum = 0
4116 01:24:13.138718 7, 0xFFFF, sum = 0
4117 01:24:13.142000 8, 0x0, sum = 1
4118 01:24:13.142078 9, 0x0, sum = 2
4119 01:24:13.145464 10, 0x0, sum = 3
4120 01:24:13.145538 11, 0x0, sum = 4
4121 01:24:13.149003 best_step = 9
4122 01:24:13.149075
4123 01:24:13.149136 ==
4124 01:24:13.152025 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 01:24:13.155291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 01:24:13.155370 ==
4127 01:24:13.159417 RX Vref Scan: 1
4128 01:24:13.159493
4129 01:24:13.159554 RX Vref 0 -> 0, step: 1
4130 01:24:13.159613
4131 01:24:13.162378 RX Delay -179 -> 252, step: 8
4132 01:24:13.162450
4133 01:24:13.165312 Set Vref, RX VrefLevel [Byte0]: 53
4134 01:24:13.168747 [Byte1]: 49
4135 01:24:13.172288
4136 01:24:13.172359 Final RX Vref Byte 0 = 53 to rank0
4137 01:24:13.175673 Final RX Vref Byte 1 = 49 to rank0
4138 01:24:13.178955 Final RX Vref Byte 0 = 53 to rank1
4139 01:24:13.182269 Final RX Vref Byte 1 = 49 to rank1==
4140 01:24:13.186020 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 01:24:13.189337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 01:24:13.192447 ==
4143 01:24:13.192530 DQS Delay:
4144 01:24:13.192625 DQS0 = 0, DQS1 = 0
4145 01:24:13.195857 DQM Delay:
4146 01:24:13.195927 DQM0 = 42, DQM1 = 34
4147 01:24:13.199165 DQ Delay:
4148 01:24:13.199239 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4149 01:24:13.202956 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4150 01:24:13.205767 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4151 01:24:13.209253 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4152 01:24:13.209325
4153 01:24:13.212642
4154 01:24:13.219957 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4155 01:24:13.222534 CH0 RK0: MR19=808, MR18=3F1F
4156 01:24:13.229291 CH0_RK0: MR19=0x808, MR18=0x3F1F, DQSOSC=397, MR23=63, INC=166, DEC=110
4157 01:24:13.229378
4158 01:24:13.232931 ----->DramcWriteLeveling(PI) begin...
4159 01:24:13.233009 ==
4160 01:24:13.236030 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 01:24:13.239418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 01:24:13.239494 ==
4163 01:24:13.242545 Write leveling (Byte 0): 33 => 33
4164 01:24:13.245840 Write leveling (Byte 1): 33 => 33
4165 01:24:13.249265 DramcWriteLeveling(PI) end<-----
4166 01:24:13.249375
4167 01:24:13.249440 ==
4168 01:24:13.252627 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 01:24:13.255880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 01:24:13.255956 ==
4171 01:24:13.259383 [Gating] SW mode calibration
4172 01:24:13.266143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 01:24:13.272822 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 01:24:13.276007 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 01:24:13.279518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 01:24:13.286065 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 01:24:13.289527 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
4178 01:24:13.293290 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4179 01:24:13.296310 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 01:24:13.303404 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 01:24:13.306557 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 01:24:13.309392 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 01:24:13.316268 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 01:24:13.319817 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 01:24:13.322854 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4186 01:24:13.329331 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4187 01:24:13.333328 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 01:24:13.336654 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 01:24:13.343031 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 01:24:13.346493 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 01:24:13.349453 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 01:24:13.356191 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 01:24:13.359739 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4194 01:24:13.363041 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4195 01:24:13.369748 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 01:24:13.373348 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 01:24:13.376551 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 01:24:13.379736 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 01:24:13.386461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 01:24:13.389632 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 01:24:13.393040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 01:24:13.399601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 01:24:13.403040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 01:24:13.406479 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 01:24:13.413441 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 01:24:13.416392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 01:24:13.419987 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 01:24:13.426977 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 01:24:13.430329 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4210 01:24:13.433343 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4211 01:24:13.437207 Total UI for P1: 0, mck2ui 16
4212 01:24:13.440177 best dqsien dly found for B0: ( 0, 13, 12)
4213 01:24:13.443243 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 01:24:13.446541 Total UI for P1: 0, mck2ui 16
4215 01:24:13.450171 best dqsien dly found for B1: ( 0, 13, 14)
4216 01:24:13.453874 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4217 01:24:13.460373 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4218 01:24:13.460452
4219 01:24:13.463357 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4220 01:24:13.466944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4221 01:24:13.470107 [Gating] SW calibration Done
4222 01:24:13.470179 ==
4223 01:24:13.473588 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 01:24:13.477482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 01:24:13.477597 ==
4226 01:24:13.477679 RX Vref Scan: 0
4227 01:24:13.480187
4228 01:24:13.480255 RX Vref 0 -> 0, step: 1
4229 01:24:13.480313
4230 01:24:13.483702 RX Delay -230 -> 252, step: 16
4231 01:24:13.487088 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4232 01:24:13.493849 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4233 01:24:13.496978 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4234 01:24:13.500256 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4235 01:24:13.503776 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4236 01:24:13.507009 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4237 01:24:13.513686 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4238 01:24:13.517144 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4239 01:24:13.520807 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4240 01:24:13.523729 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4241 01:24:13.527153 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4242 01:24:13.533891 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4243 01:24:13.537318 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4244 01:24:13.540922 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4245 01:24:13.543636 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4246 01:24:13.550549 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4247 01:24:13.550628 ==
4248 01:24:13.553932 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 01:24:13.557245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 01:24:13.557319 ==
4251 01:24:13.557382 DQS Delay:
4252 01:24:13.560161 DQS0 = 0, DQS1 = 0
4253 01:24:13.560230 DQM Delay:
4254 01:24:13.564024 DQM0 = 42, DQM1 = 34
4255 01:24:13.564099 DQ Delay:
4256 01:24:13.566890 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4257 01:24:13.570964 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4258 01:24:13.573406 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4259 01:24:13.576830 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4260 01:24:13.576904
4261 01:24:13.576965
4262 01:24:13.577028 ==
4263 01:24:13.580357 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 01:24:13.584027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 01:24:13.584103 ==
4266 01:24:13.584166
4267 01:24:13.587191
4268 01:24:13.587264 TX Vref Scan disable
4269 01:24:13.590776 == TX Byte 0 ==
4270 01:24:13.593736 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4271 01:24:13.597491 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4272 01:24:13.600501 == TX Byte 1 ==
4273 01:24:13.604183 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4274 01:24:13.607151 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4275 01:24:13.607232 ==
4276 01:24:13.611020 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 01:24:13.617340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 01:24:13.617439 ==
4279 01:24:13.617517
4280 01:24:13.617580
4281 01:24:13.617637 TX Vref Scan disable
4282 01:24:13.621340 == TX Byte 0 ==
4283 01:24:13.624590 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4284 01:24:13.627892 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4285 01:24:13.631448 == TX Byte 1 ==
4286 01:24:13.634883 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4287 01:24:13.637945 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4288 01:24:13.641548
4289 01:24:13.641630 [DATLAT]
4290 01:24:13.641710 Freq=600, CH0 RK1
4291 01:24:13.641833
4292 01:24:13.645038 DATLAT Default: 0x9
4293 01:24:13.645120 0, 0xFFFF, sum = 0
4294 01:24:13.647908 1, 0xFFFF, sum = 0
4295 01:24:13.647991 2, 0xFFFF, sum = 0
4296 01:24:13.651419 3, 0xFFFF, sum = 0
4297 01:24:13.651502 4, 0xFFFF, sum = 0
4298 01:24:13.654880 5, 0xFFFF, sum = 0
4299 01:24:13.654964 6, 0xFFFF, sum = 0
4300 01:24:13.658091 7, 0xFFFF, sum = 0
4301 01:24:13.658175 8, 0x0, sum = 1
4302 01:24:13.661800 9, 0x0, sum = 2
4303 01:24:13.661882 10, 0x0, sum = 3
4304 01:24:13.665124 11, 0x0, sum = 4
4305 01:24:13.665210 best_step = 9
4306 01:24:13.665275
4307 01:24:13.665368 ==
4308 01:24:13.668002 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 01:24:13.675199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 01:24:13.675275 ==
4311 01:24:13.675338 RX Vref Scan: 0
4312 01:24:13.675399
4313 01:24:13.678233 RX Vref 0 -> 0, step: 1
4314 01:24:13.678306
4315 01:24:13.681546 RX Delay -195 -> 252, step: 8
4316 01:24:13.685241 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4317 01:24:13.688828 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4318 01:24:13.695065 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4319 01:24:13.698650 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4320 01:24:13.701874 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4321 01:24:13.705060 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4322 01:24:13.711812 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4323 01:24:13.714723 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4324 01:24:13.718246 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4325 01:24:13.721824 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4326 01:24:13.724822 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4327 01:24:13.731547 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4328 01:24:13.734914 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4329 01:24:13.738535 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4330 01:24:13.741942 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4331 01:24:13.748284 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4332 01:24:13.748358 ==
4333 01:24:13.751481 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 01:24:13.755145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 01:24:13.755232 ==
4336 01:24:13.755295 DQS Delay:
4337 01:24:13.758545 DQS0 = 0, DQS1 = 0
4338 01:24:13.758616 DQM Delay:
4339 01:24:13.762074 DQM0 = 40, DQM1 = 33
4340 01:24:13.762146 DQ Delay:
4341 01:24:13.765232 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4342 01:24:13.768380 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4343 01:24:13.771954 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4344 01:24:13.774908 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4345 01:24:13.774977
4346 01:24:13.775036
4347 01:24:13.781896 [DQSOSCAuto] RK1, (LSB)MR18= 0x482a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4348 01:24:13.785432 CH0 RK1: MR19=808, MR18=482A
4349 01:24:13.791415 CH0_RK1: MR19=0x808, MR18=0x482A, DQSOSC=396, MR23=63, INC=167, DEC=111
4350 01:24:13.794921 [RxdqsGatingPostProcess] freq 600
4351 01:24:13.801928 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 01:24:13.805066 Pre-setting of DQS Precalculation
4353 01:24:13.808925 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 01:24:13.808996 ==
4355 01:24:13.811435 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 01:24:13.815550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 01:24:13.815617 ==
4358 01:24:13.821684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 01:24:13.828502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4360 01:24:13.831714 [CA 0] Center 35 (5~66) winsize 62
4361 01:24:13.834976 [CA 1] Center 35 (5~65) winsize 61
4362 01:24:13.838451 [CA 2] Center 34 (3~65) winsize 63
4363 01:24:13.841953 [CA 3] Center 33 (3~64) winsize 62
4364 01:24:13.845123 [CA 4] Center 34 (3~65) winsize 63
4365 01:24:13.848231 [CA 5] Center 33 (2~64) winsize 63
4366 01:24:13.848307
4367 01:24:13.851899 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4368 01:24:13.851971
4369 01:24:13.855243 [CATrainingPosCal] consider 1 rank data
4370 01:24:13.858150 u2DelayCellTimex100 = 270/100 ps
4371 01:24:13.861879 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 01:24:13.864826 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4373 01:24:13.868550 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4374 01:24:13.871623 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 01:24:13.874950 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4376 01:24:13.878206 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4377 01:24:13.878273
4378 01:24:13.885008 CA PerBit enable=1, Macro0, CA PI delay=33
4379 01:24:13.885088
4380 01:24:13.885152 [CBTSetCACLKResult] CA Dly = 33
4381 01:24:13.888493 CS Dly: 4 (0~35)
4382 01:24:13.888561 ==
4383 01:24:13.891756 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 01:24:13.895105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 01:24:13.895191 ==
4386 01:24:13.902527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 01:24:13.908440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4388 01:24:13.911958 [CA 0] Center 35 (5~66) winsize 62
4389 01:24:13.915153 [CA 1] Center 35 (5~66) winsize 62
4390 01:24:13.918392 [CA 2] Center 34 (3~65) winsize 63
4391 01:24:13.921910 [CA 3] Center 34 (3~65) winsize 63
4392 01:24:13.925476 [CA 4] Center 34 (4~65) winsize 62
4393 01:24:13.928805 [CA 5] Center 33 (3~64) winsize 62
4394 01:24:13.928923
4395 01:24:13.932286 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4396 01:24:13.932382
4397 01:24:13.935541 [CATrainingPosCal] consider 2 rank data
4398 01:24:13.939428 u2DelayCellTimex100 = 270/100 ps
4399 01:24:13.942015 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 01:24:13.945315 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4401 01:24:13.948778 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4402 01:24:13.952123 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 01:24:13.955312 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 01:24:13.958757 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 01:24:13.958832
4406 01:24:13.965155 CA PerBit enable=1, Macro0, CA PI delay=33
4407 01:24:13.965235
4408 01:24:13.965298 [CBTSetCACLKResult] CA Dly = 33
4409 01:24:13.968907 CS Dly: 4 (0~35)
4410 01:24:13.968979
4411 01:24:13.971931 ----->DramcWriteLeveling(PI) begin...
4412 01:24:13.972004 ==
4413 01:24:13.975876 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 01:24:13.978652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 01:24:13.978726 ==
4416 01:24:13.981977 Write leveling (Byte 0): 30 => 30
4417 01:24:13.985274 Write leveling (Byte 1): 30 => 30
4418 01:24:13.988545 DramcWriteLeveling(PI) end<-----
4419 01:24:13.988618
4420 01:24:13.988706 ==
4421 01:24:13.992203 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 01:24:13.995685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 01:24:13.995756 ==
4424 01:24:13.998822 [Gating] SW mode calibration
4425 01:24:14.005555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 01:24:14.012332 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 01:24:14.015688 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 01:24:14.022405 0 9 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4429 01:24:14.025662 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4430 01:24:14.029126 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (0 0) (1 1)
4431 01:24:14.032499 0 9 16 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
4432 01:24:14.039384 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 01:24:14.042419 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 01:24:14.046110 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 01:24:14.052245 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 01:24:14.055623 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 01:24:14.058951 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 01:24:14.065596 0 10 12 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
4439 01:24:14.069154 0 10 16 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
4440 01:24:14.072516 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 01:24:14.079019 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 01:24:14.082480 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 01:24:14.086155 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 01:24:14.092457 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 01:24:14.095791 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 01:24:14.099243 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4447 01:24:14.102377 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4448 01:24:14.109199 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 01:24:14.112384 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 01:24:14.115615 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 01:24:14.122330 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 01:24:14.125648 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 01:24:14.129342 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 01:24:14.136210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 01:24:14.139085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 01:24:14.142223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 01:24:14.148850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 01:24:14.152169 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 01:24:14.155415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 01:24:14.162127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 01:24:14.165988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 01:24:14.169139 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4463 01:24:14.175839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 01:24:14.175921 Total UI for P1: 0, mck2ui 16
4465 01:24:14.182400 best dqsien dly found for B0: ( 0, 13, 12)
4466 01:24:14.182550 Total UI for P1: 0, mck2ui 16
4467 01:24:14.185663 best dqsien dly found for B1: ( 0, 13, 12)
4468 01:24:14.192478 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4469 01:24:14.195567 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4470 01:24:14.195664
4471 01:24:14.199152 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 01:24:14.202575 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4473 01:24:14.205446 [Gating] SW calibration Done
4474 01:24:14.205540 ==
4475 01:24:14.209208 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 01:24:14.212551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 01:24:14.212633 ==
4478 01:24:14.215808 RX Vref Scan: 0
4479 01:24:14.215879
4480 01:24:14.215940 RX Vref 0 -> 0, step: 1
4481 01:24:14.216032
4482 01:24:14.219104 RX Delay -230 -> 252, step: 16
4483 01:24:14.222520 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4484 01:24:14.229246 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4485 01:24:14.232661 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4486 01:24:14.235725 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4487 01:24:14.239224 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4488 01:24:14.245892 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4489 01:24:14.249030 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4490 01:24:14.252586 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4491 01:24:14.255773 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4492 01:24:14.259169 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4493 01:24:14.266372 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4494 01:24:14.269190 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4495 01:24:14.272955 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4496 01:24:14.276503 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4497 01:24:14.282836 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4498 01:24:14.285912 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4499 01:24:14.285994 ==
4500 01:24:14.289649 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 01:24:14.293086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 01:24:14.293168 ==
4503 01:24:14.293231 DQS Delay:
4504 01:24:14.295927 DQS0 = 0, DQS1 = 0
4505 01:24:14.296008 DQM Delay:
4506 01:24:14.299367 DQM0 = 44, DQM1 = 35
4507 01:24:14.299448 DQ Delay:
4508 01:24:14.302564 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4509 01:24:14.306246 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4510 01:24:14.309574 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4511 01:24:14.312685 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4512 01:24:14.312779
4513 01:24:14.312841
4514 01:24:14.312899 ==
4515 01:24:14.315978 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 01:24:14.319404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 01:24:14.322783 ==
4518 01:24:14.322871
4519 01:24:14.322935
4520 01:24:14.322992 TX Vref Scan disable
4521 01:24:14.325896 == TX Byte 0 ==
4522 01:24:14.329258 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4523 01:24:14.333214 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4524 01:24:14.335971 == TX Byte 1 ==
4525 01:24:14.339515 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4526 01:24:14.342638 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4527 01:24:14.345937 ==
4528 01:24:14.346014 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 01:24:14.352533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 01:24:14.352609 ==
4531 01:24:14.352693
4532 01:24:14.352768
4533 01:24:14.356203 TX Vref Scan disable
4534 01:24:14.356277 == TX Byte 0 ==
4535 01:24:14.362940 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4536 01:24:14.366039 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4537 01:24:14.366108 == TX Byte 1 ==
4538 01:24:14.373485 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 01:24:14.376623 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 01:24:14.376753
4541 01:24:14.376833 [DATLAT]
4542 01:24:14.379589 Freq=600, CH1 RK0
4543 01:24:14.379670
4544 01:24:14.379733 DATLAT Default: 0x9
4545 01:24:14.383008 0, 0xFFFF, sum = 0
4546 01:24:14.383090 1, 0xFFFF, sum = 0
4547 01:24:14.386618 2, 0xFFFF, sum = 0
4548 01:24:14.386699 3, 0xFFFF, sum = 0
4549 01:24:14.389494 4, 0xFFFF, sum = 0
4550 01:24:14.389575 5, 0xFFFF, sum = 0
4551 01:24:14.393050 6, 0xFFFF, sum = 0
4552 01:24:14.393199 7, 0xFFFF, sum = 0
4553 01:24:14.396054 8, 0x0, sum = 1
4554 01:24:14.396136 9, 0x0, sum = 2
4555 01:24:14.400029 10, 0x0, sum = 3
4556 01:24:14.400112 11, 0x0, sum = 4
4557 01:24:14.403746 best_step = 9
4558 01:24:14.403826
4559 01:24:14.403888 ==
4560 01:24:14.406505 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 01:24:14.409441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 01:24:14.409522 ==
4563 01:24:14.409584 RX Vref Scan: 1
4564 01:24:14.412785
4565 01:24:14.412866 RX Vref 0 -> 0, step: 1
4566 01:24:14.412929
4567 01:24:14.416259 RX Delay -195 -> 252, step: 8
4568 01:24:14.416339
4569 01:24:14.419993 Set Vref, RX VrefLevel [Byte0]: 59
4570 01:24:14.423257 [Byte1]: 53
4571 01:24:14.426721
4572 01:24:14.426823 Final RX Vref Byte 0 = 59 to rank0
4573 01:24:14.429612 Final RX Vref Byte 1 = 53 to rank0
4574 01:24:14.433222 Final RX Vref Byte 0 = 59 to rank1
4575 01:24:14.436131 Final RX Vref Byte 1 = 53 to rank1==
4576 01:24:14.440006 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 01:24:14.446338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 01:24:14.446421 ==
4579 01:24:14.446484 DQS Delay:
4580 01:24:14.446542 DQS0 = 0, DQS1 = 0
4581 01:24:14.449388 DQM Delay:
4582 01:24:14.449469 DQM0 = 41, DQM1 = 33
4583 01:24:14.453092 DQ Delay:
4584 01:24:14.456408 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4585 01:24:14.456491 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4586 01:24:14.459380 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4587 01:24:14.462742 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4588 01:24:14.466338
4589 01:24:14.466419
4590 01:24:14.472957 [DQSOSCAuto] RK0, (LSB)MR18= 0x4107, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4591 01:24:14.476325 CH1 RK0: MR19=808, MR18=4107
4592 01:24:14.483160 CH1_RK0: MR19=0x808, MR18=0x4107, DQSOSC=397, MR23=63, INC=166, DEC=110
4593 01:24:14.483273
4594 01:24:14.486002 ----->DramcWriteLeveling(PI) begin...
4595 01:24:14.486104 ==
4596 01:24:14.489754 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 01:24:14.493111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 01:24:14.493228 ==
4599 01:24:14.496223 Write leveling (Byte 0): 29 => 29
4600 01:24:14.499613 Write leveling (Byte 1): 29 => 29
4601 01:24:14.503219 DramcWriteLeveling(PI) end<-----
4602 01:24:14.503320
4603 01:24:14.503411 ==
4604 01:24:14.506370 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 01:24:14.509399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 01:24:14.509490 ==
4607 01:24:14.512791 [Gating] SW mode calibration
4608 01:24:14.519820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4609 01:24:14.526440 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4610 01:24:14.529611 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 01:24:14.533082 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 01:24:14.540050 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 01:24:14.543119 0 9 12 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 1)
4614 01:24:14.547201 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4615 01:24:14.553083 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 01:24:14.556807 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 01:24:14.559792 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4618 01:24:14.566455 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 01:24:14.569864 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 01:24:14.573224 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4621 01:24:14.576866 0 10 12 | B1->B0 | 3737 3d3d | 0 0 | (1 1) (0 0)
4622 01:24:14.583238 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4623 01:24:14.586563 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 01:24:14.589841 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 01:24:14.596446 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 01:24:14.599948 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 01:24:14.603303 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 01:24:14.609906 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 01:24:14.613165 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4630 01:24:14.616398 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 01:24:14.623511 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 01:24:14.626547 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 01:24:14.629867 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 01:24:14.636825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 01:24:14.640189 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 01:24:14.643237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 01:24:14.646849 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 01:24:14.653391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 01:24:14.656925 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 01:24:14.660188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 01:24:14.666809 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 01:24:14.670405 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 01:24:14.674044 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 01:24:14.680470 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4645 01:24:14.683742 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4646 01:24:14.687326 Total UI for P1: 0, mck2ui 16
4647 01:24:14.690380 best dqsien dly found for B0: ( 0, 13, 8)
4648 01:24:14.693539 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 01:24:14.697514 Total UI for P1: 0, mck2ui 16
4650 01:24:14.700574 best dqsien dly found for B1: ( 0, 13, 10)
4651 01:24:14.703906 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4652 01:24:14.707303 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4653 01:24:14.707383
4654 01:24:14.710594 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4655 01:24:14.717015 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4656 01:24:14.717092 [Gating] SW calibration Done
4657 01:24:14.717161 ==
4658 01:24:14.720297 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 01:24:14.727092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 01:24:14.727177 ==
4661 01:24:14.727240 RX Vref Scan: 0
4662 01:24:14.727299
4663 01:24:14.730490 RX Vref 0 -> 0, step: 1
4664 01:24:14.730564
4665 01:24:14.733740 RX Delay -230 -> 252, step: 16
4666 01:24:14.737248 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4667 01:24:14.740402 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4668 01:24:14.744144 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4669 01:24:14.750640 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4670 01:24:14.753761 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4671 01:24:14.756964 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4672 01:24:14.760521 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4673 01:24:14.764004 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4674 01:24:14.770491 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4675 01:24:14.774377 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4676 01:24:14.777253 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4677 01:24:14.780563 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4678 01:24:14.787083 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4679 01:24:14.790624 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4680 01:24:14.793841 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4681 01:24:14.797199 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4682 01:24:14.797272 ==
4683 01:24:14.800444 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 01:24:14.807316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 01:24:14.807396 ==
4686 01:24:14.807459 DQS Delay:
4687 01:24:14.810732 DQS0 = 0, DQS1 = 0
4688 01:24:14.810805 DQM Delay:
4689 01:24:14.810869 DQM0 = 42, DQM1 = 36
4690 01:24:14.813773 DQ Delay:
4691 01:24:14.817359 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4692 01:24:14.820402 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4693 01:24:14.823800 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4694 01:24:14.827298 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4695 01:24:14.827372
4696 01:24:14.827434
4697 01:24:14.827497 ==
4698 01:24:14.830568 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 01:24:14.833767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 01:24:14.833851 ==
4701 01:24:14.833915
4702 01:24:14.834002
4703 01:24:14.837279 TX Vref Scan disable
4704 01:24:14.837355 == TX Byte 0 ==
4705 01:24:14.844033 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4706 01:24:14.847283 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4707 01:24:14.847385 == TX Byte 1 ==
4708 01:24:14.854219 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 01:24:14.857486 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 01:24:14.857566 ==
4711 01:24:14.860529 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 01:24:14.864248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 01:24:14.864325 ==
4714 01:24:14.864388
4715 01:24:14.864447
4716 01:24:14.867155 TX Vref Scan disable
4717 01:24:14.870845 == TX Byte 0 ==
4718 01:24:14.873922 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4719 01:24:14.877445 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4720 01:24:14.880763 == TX Byte 1 ==
4721 01:24:14.884115 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4722 01:24:14.887372 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4723 01:24:14.890898
4724 01:24:14.890973 [DATLAT]
4725 01:24:14.891036 Freq=600, CH1 RK1
4726 01:24:14.891095
4727 01:24:14.893907 DATLAT Default: 0x9
4728 01:24:14.893981 0, 0xFFFF, sum = 0
4729 01:24:14.897447 1, 0xFFFF, sum = 0
4730 01:24:14.897519 2, 0xFFFF, sum = 0
4731 01:24:14.900450 3, 0xFFFF, sum = 0
4732 01:24:14.900526 4, 0xFFFF, sum = 0
4733 01:24:14.903777 5, 0xFFFF, sum = 0
4734 01:24:14.903865 6, 0xFFFF, sum = 0
4735 01:24:14.907385 7, 0xFFFF, sum = 0
4736 01:24:14.907462 8, 0x0, sum = 1
4737 01:24:14.910479 9, 0x0, sum = 2
4738 01:24:14.910552 10, 0x0, sum = 3
4739 01:24:14.914101 11, 0x0, sum = 4
4740 01:24:14.914172 best_step = 9
4741 01:24:14.914230
4742 01:24:14.914286 ==
4743 01:24:14.917130 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 01:24:14.924178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 01:24:14.924257 ==
4746 01:24:14.924324 RX Vref Scan: 0
4747 01:24:14.924384
4748 01:24:14.927267 RX Vref 0 -> 0, step: 1
4749 01:24:14.927352
4750 01:24:14.930996 RX Delay -195 -> 252, step: 8
4751 01:24:14.934016 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4752 01:24:14.940460 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4753 01:24:14.943950 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4754 01:24:14.947409 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4755 01:24:14.950462 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4756 01:24:14.954031 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4757 01:24:14.960805 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4758 01:24:14.963878 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4759 01:24:14.967088 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4760 01:24:14.970546 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4761 01:24:14.977085 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4762 01:24:14.980570 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4763 01:24:14.983684 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4764 01:24:14.987721 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4765 01:24:14.990773 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4766 01:24:14.997129 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4767 01:24:14.997204 ==
4768 01:24:15.000691 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 01:24:15.004095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 01:24:15.004177 ==
4771 01:24:15.004241 DQS Delay:
4772 01:24:15.007192 DQS0 = 0, DQS1 = 0
4773 01:24:15.007271 DQM Delay:
4774 01:24:15.011189 DQM0 = 39, DQM1 = 32
4775 01:24:15.011263 DQ Delay:
4776 01:24:15.014055 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =40
4777 01:24:15.017543 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4778 01:24:15.020795 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4779 01:24:15.024176 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4780 01:24:15.024256
4781 01:24:15.024318
4782 01:24:15.030881 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4783 01:24:15.033801 CH1 RK1: MR19=808, MR18=3C4A
4784 01:24:15.040981 CH1_RK1: MR19=0x808, MR18=0x3C4A, DQSOSC=395, MR23=63, INC=168, DEC=112
4785 01:24:15.043929 [RxdqsGatingPostProcess] freq 600
4786 01:24:15.050559 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 01:24:15.054270 Pre-setting of DQS Precalculation
4788 01:24:15.057264 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 01:24:15.063910 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 01:24:15.070379 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 01:24:15.070468
4792 01:24:15.073677
4793 01:24:15.073759 [Calibration Summary] 1200 Mbps
4794 01:24:15.076844 CH 0, Rank 0
4795 01:24:15.076917 SW Impedance : PASS
4796 01:24:15.080514 DUTY Scan : NO K
4797 01:24:15.083899 ZQ Calibration : PASS
4798 01:24:15.083974 Jitter Meter : NO K
4799 01:24:15.086905 CBT Training : PASS
4800 01:24:15.090406 Write leveling : PASS
4801 01:24:15.090479 RX DQS gating : PASS
4802 01:24:15.094034 RX DQ/DQS(RDDQC) : PASS
4803 01:24:15.097006 TX DQ/DQS : PASS
4804 01:24:15.097088 RX DATLAT : PASS
4805 01:24:15.101010 RX DQ/DQS(Engine): PASS
4806 01:24:15.101087 TX OE : NO K
4807 01:24:15.103710 All Pass.
4808 01:24:15.103784
4809 01:24:15.103848 CH 0, Rank 1
4810 01:24:15.106872 SW Impedance : PASS
4811 01:24:15.106943 DUTY Scan : NO K
4812 01:24:15.111044 ZQ Calibration : PASS
4813 01:24:15.113809 Jitter Meter : NO K
4814 01:24:15.113885 CBT Training : PASS
4815 01:24:15.117143 Write leveling : PASS
4816 01:24:15.120415 RX DQS gating : PASS
4817 01:24:15.120495 RX DQ/DQS(RDDQC) : PASS
4818 01:24:15.124102 TX DQ/DQS : PASS
4819 01:24:15.126907 RX DATLAT : PASS
4820 01:24:15.126980 RX DQ/DQS(Engine): PASS
4821 01:24:15.130590 TX OE : NO K
4822 01:24:15.130668 All Pass.
4823 01:24:15.130777
4824 01:24:15.133682 CH 1, Rank 0
4825 01:24:15.133761 SW Impedance : PASS
4826 01:24:15.137053 DUTY Scan : NO K
4827 01:24:15.140391 ZQ Calibration : PASS
4828 01:24:15.140471 Jitter Meter : NO K
4829 01:24:15.144101 CBT Training : PASS
4830 01:24:15.147041 Write leveling : PASS
4831 01:24:15.147114 RX DQS gating : PASS
4832 01:24:15.151372 RX DQ/DQS(RDDQC) : PASS
4833 01:24:15.151443 TX DQ/DQS : PASS
4834 01:24:15.154444 RX DATLAT : PASS
4835 01:24:15.157286 RX DQ/DQS(Engine): PASS
4836 01:24:15.157361 TX OE : NO K
4837 01:24:15.160419 All Pass.
4838 01:24:15.160489
4839 01:24:15.160549 CH 1, Rank 1
4840 01:24:15.163905 SW Impedance : PASS
4841 01:24:15.163975 DUTY Scan : NO K
4842 01:24:15.167094 ZQ Calibration : PASS
4843 01:24:15.170677 Jitter Meter : NO K
4844 01:24:15.170755 CBT Training : PASS
4845 01:24:15.173789 Write leveling : PASS
4846 01:24:15.177314 RX DQS gating : PASS
4847 01:24:15.177386 RX DQ/DQS(RDDQC) : PASS
4848 01:24:15.180430 TX DQ/DQS : PASS
4849 01:24:15.184364 RX DATLAT : PASS
4850 01:24:15.184439 RX DQ/DQS(Engine): PASS
4851 01:24:15.187388 TX OE : NO K
4852 01:24:15.187463 All Pass.
4853 01:24:15.187524
4854 01:24:15.190728 DramC Write-DBI off
4855 01:24:15.193822 PER_BANK_REFRESH: Hybrid Mode
4856 01:24:15.193898 TX_TRACKING: ON
4857 01:24:15.203661 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 01:24:15.207511 [FAST_K] Save calibration result to emmc
4859 01:24:15.211263 dramc_set_vcore_voltage set vcore to 662500
4860 01:24:15.211340 Read voltage for 933, 3
4861 01:24:15.213863 Vio18 = 0
4862 01:24:15.213934 Vcore = 662500
4863 01:24:15.214000 Vdram = 0
4864 01:24:15.217225 Vddq = 0
4865 01:24:15.217301 Vmddr = 0
4866 01:24:15.220524 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 01:24:15.227084 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 01:24:15.230514 MEM_TYPE=3, freq_sel=17
4869 01:24:15.233796 sv_algorithm_assistance_LP4_1600
4870 01:24:15.237247 ============ PULL DRAM RESETB DOWN ============
4871 01:24:15.240551 ========== PULL DRAM RESETB DOWN end =========
4872 01:24:15.247405 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 01:24:15.250319 ===================================
4874 01:24:15.250404 LPDDR4 DRAM CONFIGURATION
4875 01:24:15.253891 ===================================
4876 01:24:15.257048 EX_ROW_EN[0] = 0x0
4877 01:24:15.257128 EX_ROW_EN[1] = 0x0
4878 01:24:15.260334 LP4Y_EN = 0x0
4879 01:24:15.260406 WORK_FSP = 0x0
4880 01:24:15.263826 WL = 0x3
4881 01:24:15.263900 RL = 0x3
4882 01:24:15.267416 BL = 0x2
4883 01:24:15.270985 RPST = 0x0
4884 01:24:15.271056 RD_PRE = 0x0
4885 01:24:15.273756 WR_PRE = 0x1
4886 01:24:15.273827 WR_PST = 0x0
4887 01:24:15.277375 DBI_WR = 0x0
4888 01:24:15.277447 DBI_RD = 0x0
4889 01:24:15.280430 OTF = 0x1
4890 01:24:15.283712 ===================================
4891 01:24:15.288028 ===================================
4892 01:24:15.288105 ANA top config
4893 01:24:15.290720 ===================================
4894 01:24:15.293871 DLL_ASYNC_EN = 0
4895 01:24:15.297641 ALL_SLAVE_EN = 1
4896 01:24:15.297716 NEW_RANK_MODE = 1
4897 01:24:15.300387 DLL_IDLE_MODE = 1
4898 01:24:15.303641 LP45_APHY_COMB_EN = 1
4899 01:24:15.307472 TX_ODT_DIS = 1
4900 01:24:15.307545 NEW_8X_MODE = 1
4901 01:24:15.310356 ===================================
4902 01:24:15.313756 ===================================
4903 01:24:15.317145 data_rate = 1866
4904 01:24:15.320403 CKR = 1
4905 01:24:15.323600 DQ_P2S_RATIO = 8
4906 01:24:15.327191 ===================================
4907 01:24:15.331013 CA_P2S_RATIO = 8
4908 01:24:15.334079 DQ_CA_OPEN = 0
4909 01:24:15.334158 DQ_SEMI_OPEN = 0
4910 01:24:15.337438 CA_SEMI_OPEN = 0
4911 01:24:15.340508 CA_FULL_RATE = 0
4912 01:24:15.343837 DQ_CKDIV4_EN = 1
4913 01:24:15.347600 CA_CKDIV4_EN = 1
4914 01:24:15.351171 CA_PREDIV_EN = 0
4915 01:24:15.351243 PH8_DLY = 0
4916 01:24:15.354151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 01:24:15.357470 DQ_AAMCK_DIV = 4
4918 01:24:15.360938 CA_AAMCK_DIV = 4
4919 01:24:15.364179 CA_ADMCK_DIV = 4
4920 01:24:15.364255 DQ_TRACK_CA_EN = 0
4921 01:24:15.367243 CA_PICK = 933
4922 01:24:15.370605 CA_MCKIO = 933
4923 01:24:15.373847 MCKIO_SEMI = 0
4924 01:24:15.377264 PLL_FREQ = 3732
4925 01:24:15.380962 DQ_UI_PI_RATIO = 32
4926 01:24:15.384159 CA_UI_PI_RATIO = 0
4927 01:24:15.387385 ===================================
4928 01:24:15.390534 ===================================
4929 01:24:15.390606 memory_type:LPDDR4
4930 01:24:15.394741 GP_NUM : 10
4931 01:24:15.397326 SRAM_EN : 1
4932 01:24:15.397399 MD32_EN : 0
4933 01:24:15.400877 ===================================
4934 01:24:15.404323 [ANA_INIT] >>>>>>>>>>>>>>
4935 01:24:15.407221 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 01:24:15.410971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 01:24:15.414209 ===================================
4938 01:24:15.417413 data_rate = 1866,PCW = 0X8f00
4939 01:24:15.417489 ===================================
4940 01:24:15.423937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 01:24:15.427437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 01:24:15.434645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 01:24:15.437581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 01:24:15.440803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 01:24:15.444357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 01:24:15.447703 [ANA_INIT] flow start
4947 01:24:15.450943 [ANA_INIT] PLL >>>>>>>>
4948 01:24:15.451016 [ANA_INIT] PLL <<<<<<<<
4949 01:24:15.454323 [ANA_INIT] MIDPI >>>>>>>>
4950 01:24:15.457566 [ANA_INIT] MIDPI <<<<<<<<
4951 01:24:15.457644 [ANA_INIT] DLL >>>>>>>>
4952 01:24:15.460808 [ANA_INIT] flow end
4953 01:24:15.464318 ============ LP4 DIFF to SE enter ============
4954 01:24:15.467797 ============ LP4 DIFF to SE exit ============
4955 01:24:15.471233 [ANA_INIT] <<<<<<<<<<<<<
4956 01:24:15.474452 [Flow] Enable top DCM control >>>>>
4957 01:24:15.477872 [Flow] Enable top DCM control <<<<<
4958 01:24:15.481048 Enable DLL master slave shuffle
4959 01:24:15.487503 ==============================================================
4960 01:24:15.487577 Gating Mode config
4961 01:24:15.494864 ==============================================================
4962 01:24:15.494939 Config description:
4963 01:24:15.504160 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 01:24:15.510955 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 01:24:15.517510 SELPH_MODE 0: By rank 1: By Phase
4966 01:24:15.520785 ==============================================================
4967 01:24:15.524400 GAT_TRACK_EN = 1
4968 01:24:15.527925 RX_GATING_MODE = 2
4969 01:24:15.530549 RX_GATING_TRACK_MODE = 2
4970 01:24:15.534013 SELPH_MODE = 1
4971 01:24:15.537404 PICG_EARLY_EN = 1
4972 01:24:15.540649 VALID_LAT_VALUE = 1
4973 01:24:15.543985 ==============================================================
4974 01:24:15.547897 Enter into Gating configuration >>>>
4975 01:24:15.551432 Exit from Gating configuration <<<<
4976 01:24:15.554017 Enter into DVFS_PRE_config >>>>>
4977 01:24:15.567519 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 01:24:15.570949 Exit from DVFS_PRE_config <<<<<
4979 01:24:15.574531 Enter into PICG configuration >>>>
4980 01:24:15.574603 Exit from PICG configuration <<<<
4981 01:24:15.577581 [RX_INPUT] configuration >>>>>
4982 01:24:15.581128 [RX_INPUT] configuration <<<<<
4983 01:24:15.587689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 01:24:15.591043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 01:24:15.597792 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 01:24:15.604335 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 01:24:15.610960 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 01:24:15.617933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 01:24:15.621170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 01:24:15.624625 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 01:24:15.627847 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 01:24:15.634794 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 01:24:15.638162 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 01:24:15.641370 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 01:24:15.644427 ===================================
4996 01:24:15.648110 LPDDR4 DRAM CONFIGURATION
4997 01:24:15.651029 ===================================
4998 01:24:15.651099 EX_ROW_EN[0] = 0x0
4999 01:24:15.654636 EX_ROW_EN[1] = 0x0
5000 01:24:15.658174 LP4Y_EN = 0x0
5001 01:24:15.658246 WORK_FSP = 0x0
5002 01:24:15.661457 WL = 0x3
5003 01:24:15.661525 RL = 0x3
5004 01:24:15.664735 BL = 0x2
5005 01:24:15.664814 RPST = 0x0
5006 01:24:15.667907 RD_PRE = 0x0
5007 01:24:15.667975 WR_PRE = 0x1
5008 01:24:15.671271 WR_PST = 0x0
5009 01:24:15.671344 DBI_WR = 0x0
5010 01:24:15.674481 DBI_RD = 0x0
5011 01:24:15.674624 OTF = 0x1
5012 01:24:15.678070 ===================================
5013 01:24:15.681195 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 01:24:15.687849 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 01:24:15.691532 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 01:24:15.694505 ===================================
5017 01:24:15.697940 LPDDR4 DRAM CONFIGURATION
5018 01:24:15.701135 ===================================
5019 01:24:15.701208 EX_ROW_EN[0] = 0x10
5020 01:24:15.704425 EX_ROW_EN[1] = 0x0
5021 01:24:15.704499 LP4Y_EN = 0x0
5022 01:24:15.707874 WORK_FSP = 0x0
5023 01:24:15.707948 WL = 0x3
5024 01:24:15.711445 RL = 0x3
5025 01:24:15.711517 BL = 0x2
5026 01:24:15.714517 RPST = 0x0
5027 01:24:15.714586 RD_PRE = 0x0
5028 01:24:15.718004 WR_PRE = 0x1
5029 01:24:15.718075 WR_PST = 0x0
5030 01:24:15.721156 DBI_WR = 0x0
5031 01:24:15.724573 DBI_RD = 0x0
5032 01:24:15.724644 OTF = 0x1
5033 01:24:15.728365 ===================================
5034 01:24:15.734614 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 01:24:15.738142 nWR fixed to 30
5036 01:24:15.741306 [ModeRegInit_LP4] CH0 RK0
5037 01:24:15.741380 [ModeRegInit_LP4] CH0 RK1
5038 01:24:15.744506 [ModeRegInit_LP4] CH1 RK0
5039 01:24:15.747910 [ModeRegInit_LP4] CH1 RK1
5040 01:24:15.747982 match AC timing 9
5041 01:24:15.754637 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 01:24:15.757851 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 01:24:15.761669 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 01:24:15.767883 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 01:24:15.771163 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 01:24:15.771239 ==
5047 01:24:15.774793 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 01:24:15.778130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 01:24:15.778203 ==
5050 01:24:15.784623 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 01:24:15.791411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5052 01:24:15.794871 [CA 0] Center 38 (8~69) winsize 62
5053 01:24:15.797920 [CA 1] Center 38 (7~69) winsize 63
5054 01:24:15.801309 [CA 2] Center 35 (5~66) winsize 62
5055 01:24:15.805211 [CA 3] Center 35 (5~65) winsize 61
5056 01:24:15.808197 [CA 4] Center 34 (4~64) winsize 61
5057 01:24:15.811390 [CA 5] Center 34 (4~64) winsize 61
5058 01:24:15.811499
5059 01:24:15.814985 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5060 01:24:15.815061
5061 01:24:15.818053 [CATrainingPosCal] consider 1 rank data
5062 01:24:15.821347 u2DelayCellTimex100 = 270/100 ps
5063 01:24:15.825211 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5064 01:24:15.828242 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5065 01:24:15.831745 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5066 01:24:15.835399 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5067 01:24:15.838327 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5068 01:24:15.841552 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5069 01:24:15.841627
5070 01:24:15.844884 CA PerBit enable=1, Macro0, CA PI delay=34
5071 01:24:15.844972
5072 01:24:15.848635 [CBTSetCACLKResult] CA Dly = 34
5073 01:24:15.851734 CS Dly: 6 (0~37)
5074 01:24:15.851830 ==
5075 01:24:15.855237 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 01:24:15.858260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 01:24:15.858339 ==
5078 01:24:15.864961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 01:24:15.871505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 01:24:15.874738 [CA 0] Center 38 (7~69) winsize 63
5081 01:24:15.878063 [CA 1] Center 38 (7~69) winsize 63
5082 01:24:15.881345 [CA 2] Center 35 (5~66) winsize 62
5083 01:24:15.884840 [CA 3] Center 35 (5~66) winsize 62
5084 01:24:15.888083 [CA 4] Center 34 (4~65) winsize 62
5085 01:24:15.891747 [CA 5] Center 33 (3~64) winsize 62
5086 01:24:15.891814
5087 01:24:15.894782 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 01:24:15.894849
5089 01:24:15.898086 [CATrainingPosCal] consider 2 rank data
5090 01:24:15.901641 u2DelayCellTimex100 = 270/100 ps
5091 01:24:15.904928 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5092 01:24:15.907894 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5093 01:24:15.911557 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5094 01:24:15.914990 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5095 01:24:15.918298 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5096 01:24:15.921468 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5097 01:24:15.921543
5098 01:24:15.924582 CA PerBit enable=1, Macro0, CA PI delay=34
5099 01:24:15.927952
5100 01:24:15.928049 [CBTSetCACLKResult] CA Dly = 34
5101 01:24:15.931131 CS Dly: 7 (0~39)
5102 01:24:15.931226
5103 01:24:15.934651 ----->DramcWriteLeveling(PI) begin...
5104 01:24:15.934730 ==
5105 01:24:15.937854 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 01:24:15.941028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 01:24:15.941113 ==
5108 01:24:15.944824 Write leveling (Byte 0): 32 => 32
5109 01:24:15.947887 Write leveling (Byte 1): 28 => 28
5110 01:24:15.951614 DramcWriteLeveling(PI) end<-----
5111 01:24:15.951691
5112 01:24:15.951754 ==
5113 01:24:15.954515 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 01:24:15.958043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 01:24:15.958120 ==
5116 01:24:15.961094 [Gating] SW mode calibration
5117 01:24:15.968081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 01:24:15.974778 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 01:24:15.977911 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5120 01:24:15.984768 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5121 01:24:15.988088 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 01:24:15.991493 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 01:24:15.997977 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 01:24:16.001497 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 01:24:16.004680 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 01:24:16.011331 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5127 01:24:16.014946 0 15 0 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (0 1)
5128 01:24:16.017992 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5129 01:24:16.021846 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 01:24:16.028189 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 01:24:16.031533 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 01:24:16.034981 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 01:24:16.041495 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 01:24:16.044837 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5135 01:24:16.048245 1 0 0 | B1->B0 | 2d2d 3d3d | 0 0 | (0 0) (0 0)
5136 01:24:16.055105 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5137 01:24:16.058170 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 01:24:16.061240 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 01:24:16.068072 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 01:24:16.071458 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 01:24:16.074924 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 01:24:16.081643 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 01:24:16.084917 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5144 01:24:16.087978 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5145 01:24:16.094750 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 01:24:16.098076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 01:24:16.101752 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 01:24:16.105172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 01:24:16.111476 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 01:24:16.115331 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 01:24:16.118104 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 01:24:16.124960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 01:24:16.128496 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 01:24:16.131644 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 01:24:16.138066 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 01:24:16.141413 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 01:24:16.144936 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 01:24:16.151909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5159 01:24:16.154742 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5160 01:24:16.158585 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5161 01:24:16.161364 Total UI for P1: 0, mck2ui 16
5162 01:24:16.165146 best dqsien dly found for B0: ( 1, 2, 30)
5163 01:24:16.171375 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 01:24:16.171462 Total UI for P1: 0, mck2ui 16
5165 01:24:16.174733 best dqsien dly found for B1: ( 1, 3, 4)
5166 01:24:16.178293 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5167 01:24:16.185377 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5168 01:24:16.185459
5169 01:24:16.188606 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5170 01:24:16.191594 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5171 01:24:16.195192 [Gating] SW calibration Done
5172 01:24:16.195266 ==
5173 01:24:16.198410 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 01:24:16.201767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 01:24:16.201844 ==
5176 01:24:16.201905 RX Vref Scan: 0
5177 01:24:16.201963
5178 01:24:16.204929 RX Vref 0 -> 0, step: 1
5179 01:24:16.205004
5180 01:24:16.208460 RX Delay -80 -> 252, step: 8
5181 01:24:16.211571 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5182 01:24:16.215214 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5183 01:24:16.218163 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5184 01:24:16.224987 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5185 01:24:16.228896 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5186 01:24:16.231845 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5187 01:24:16.235151 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5188 01:24:16.238584 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5189 01:24:16.242603 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5190 01:24:16.249205 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5191 01:24:16.251695 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5192 01:24:16.255198 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5193 01:24:16.258377 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5194 01:24:16.262053 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5195 01:24:16.265657 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5196 01:24:16.272426 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5197 01:24:16.272500 ==
5198 01:24:16.275116 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 01:24:16.278749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 01:24:16.278827 ==
5201 01:24:16.278887 DQS Delay:
5202 01:24:16.282233 DQS0 = 0, DQS1 = 0
5203 01:24:16.282304 DQM Delay:
5204 01:24:16.286174 DQM0 = 98, DQM1 = 87
5205 01:24:16.286244 DQ Delay:
5206 01:24:16.288702 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5207 01:24:16.291946 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5208 01:24:16.295864 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5209 01:24:16.298752 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5210 01:24:16.298822
5211 01:24:16.298959
5212 01:24:16.299032 ==
5213 01:24:16.302109 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 01:24:16.305769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 01:24:16.305845 ==
5216 01:24:16.305907
5217 01:24:16.308914
5218 01:24:16.309015 TX Vref Scan disable
5219 01:24:16.312204 == TX Byte 0 ==
5220 01:24:16.315896 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5221 01:24:16.318976 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5222 01:24:16.322170 == TX Byte 1 ==
5223 01:24:16.325152 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5224 01:24:16.328628 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5225 01:24:16.328736 ==
5226 01:24:16.331938 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 01:24:16.338626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 01:24:16.338707 ==
5229 01:24:16.338801
5230 01:24:16.338866
5231 01:24:16.338924 TX Vref Scan disable
5232 01:24:16.343523 == TX Byte 0 ==
5233 01:24:16.346280 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5234 01:24:16.349518 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5235 01:24:16.353035 == TX Byte 1 ==
5236 01:24:16.356392 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5237 01:24:16.359780 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5238 01:24:16.363021
5239 01:24:16.363132 [DATLAT]
5240 01:24:16.363203 Freq=933, CH0 RK0
5241 01:24:16.363262
5242 01:24:16.366285 DATLAT Default: 0xd
5243 01:24:16.366355 0, 0xFFFF, sum = 0
5244 01:24:16.369618 1, 0xFFFF, sum = 0
5245 01:24:16.369689 2, 0xFFFF, sum = 0
5246 01:24:16.372902 3, 0xFFFF, sum = 0
5247 01:24:16.372973 4, 0xFFFF, sum = 0
5248 01:24:16.376270 5, 0xFFFF, sum = 0
5249 01:24:16.376341 6, 0xFFFF, sum = 0
5250 01:24:16.379924 7, 0xFFFF, sum = 0
5251 01:24:16.379995 8, 0xFFFF, sum = 0
5252 01:24:16.383144 9, 0xFFFF, sum = 0
5253 01:24:16.383242 10, 0x0, sum = 1
5254 01:24:16.386382 11, 0x0, sum = 2
5255 01:24:16.386480 12, 0x0, sum = 3
5256 01:24:16.390022 13, 0x0, sum = 4
5257 01:24:16.390112 best_step = 11
5258 01:24:16.390176
5259 01:24:16.390234 ==
5260 01:24:16.393211 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 01:24:16.399557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 01:24:16.399639 ==
5263 01:24:16.399701 RX Vref Scan: 1
5264 01:24:16.399760
5265 01:24:16.403474 RX Vref 0 -> 0, step: 1
5266 01:24:16.403546
5267 01:24:16.406816 RX Delay -61 -> 252, step: 4
5268 01:24:16.406887
5269 01:24:16.409610 Set Vref, RX VrefLevel [Byte0]: 53
5270 01:24:16.413660 [Byte1]: 49
5271 01:24:16.413732
5272 01:24:16.416390 Final RX Vref Byte 0 = 53 to rank0
5273 01:24:16.420205 Final RX Vref Byte 1 = 49 to rank0
5274 01:24:16.422993 Final RX Vref Byte 0 = 53 to rank1
5275 01:24:16.426440 Final RX Vref Byte 1 = 49 to rank1==
5276 01:24:16.430153 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 01:24:16.432987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 01:24:16.433063 ==
5279 01:24:16.436537 DQS Delay:
5280 01:24:16.436611 DQS0 = 0, DQS1 = 0
5281 01:24:16.436695 DQM Delay:
5282 01:24:16.439727 DQM0 = 97, DQM1 = 88
5283 01:24:16.439800 DQ Delay:
5284 01:24:16.442944 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96
5285 01:24:16.446816 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102
5286 01:24:16.449946 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5287 01:24:16.453396 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5288 01:24:16.453502
5289 01:24:16.453598
5290 01:24:16.463302 [DQSOSCAuto] RK0, (LSB)MR18= 0x1803, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5291 01:24:16.466428 CH0 RK0: MR19=505, MR18=1803
5292 01:24:16.470018 CH0_RK0: MR19=0x505, MR18=0x1803, DQSOSC=414, MR23=63, INC=63, DEC=42
5293 01:24:16.470095
5294 01:24:16.473322 ----->DramcWriteLeveling(PI) begin...
5295 01:24:16.476583 ==
5296 01:24:16.476673 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 01:24:16.483498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 01:24:16.483577 ==
5299 01:24:16.486446 Write leveling (Byte 0): 31 => 31
5300 01:24:16.490217 Write leveling (Byte 1): 29 => 29
5301 01:24:16.490320 DramcWriteLeveling(PI) end<-----
5302 01:24:16.493289
5303 01:24:16.493367 ==
5304 01:24:16.496783 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 01:24:16.500088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 01:24:16.500166 ==
5307 01:24:16.503217 [Gating] SW mode calibration
5308 01:24:16.510224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 01:24:16.513265 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 01:24:16.519942 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5311 01:24:16.523998 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5312 01:24:16.527396 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 01:24:16.533896 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 01:24:16.537508 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 01:24:16.540020 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 01:24:16.547083 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5317 01:24:16.550704 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5318 01:24:16.553705 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5319 01:24:16.560345 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 01:24:16.563500 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 01:24:16.566896 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 01:24:16.570501 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 01:24:16.576933 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 01:24:16.580119 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 01:24:16.583592 0 15 28 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5326 01:24:16.590252 1 0 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5327 01:24:16.593807 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 01:24:16.598125 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 01:24:16.603724 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 01:24:16.607092 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 01:24:16.610615 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 01:24:16.617324 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 01:24:16.620894 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5334 01:24:16.623750 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 01:24:16.627375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 01:24:16.633812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 01:24:16.637434 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 01:24:16.640449 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 01:24:16.647056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 01:24:16.650633 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 01:24:16.654267 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 01:24:16.660847 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 01:24:16.664209 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 01:24:16.667675 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 01:24:16.673953 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 01:24:16.677525 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 01:24:16.680490 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 01:24:16.687431 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5349 01:24:16.691107 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5350 01:24:16.694196 Total UI for P1: 0, mck2ui 16
5351 01:24:16.697252 best dqsien dly found for B0: ( 1, 2, 24)
5352 01:24:16.700817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5353 01:24:16.704100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 01:24:16.707231 Total UI for P1: 0, mck2ui 16
5355 01:24:16.710747 best dqsien dly found for B1: ( 1, 3, 2)
5356 01:24:16.713995 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5357 01:24:16.717708 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5358 01:24:16.721009
5359 01:24:16.724079 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5360 01:24:16.727359 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5361 01:24:16.730690 [Gating] SW calibration Done
5362 01:24:16.730769 ==
5363 01:24:16.734070 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 01:24:16.737279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 01:24:16.737356 ==
5366 01:24:16.737427 RX Vref Scan: 0
5367 01:24:16.737485
5368 01:24:16.740654 RX Vref 0 -> 0, step: 1
5369 01:24:16.740766
5370 01:24:16.743867 RX Delay -80 -> 252, step: 8
5371 01:24:16.747475 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5372 01:24:16.750675 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5373 01:24:16.754346 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5374 01:24:16.761265 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5375 01:24:16.764224 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5376 01:24:16.767395 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5377 01:24:16.770791 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5378 01:24:16.774138 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5379 01:24:16.777438 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5380 01:24:16.784430 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5381 01:24:16.787533 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5382 01:24:16.791293 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5383 01:24:16.794162 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5384 01:24:16.797715 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5385 01:24:16.801072 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5386 01:24:16.807672 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5387 01:24:16.807769 ==
5388 01:24:16.811149 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 01:24:16.814502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 01:24:16.814588 ==
5391 01:24:16.814652 DQS Delay:
5392 01:24:16.818057 DQS0 = 0, DQS1 = 0
5393 01:24:16.818154 DQM Delay:
5394 01:24:16.821054 DQM0 = 97, DQM1 = 87
5395 01:24:16.821139 DQ Delay:
5396 01:24:16.824584 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5397 01:24:16.827682 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5398 01:24:16.831196 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5399 01:24:16.834359 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5400 01:24:16.834460
5401 01:24:16.834571
5402 01:24:16.834637 ==
5403 01:24:16.838102 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 01:24:16.841675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 01:24:16.841774 ==
5406 01:24:16.841842
5407 01:24:16.841902
5408 01:24:16.844654 TX Vref Scan disable
5409 01:24:16.848224 == TX Byte 0 ==
5410 01:24:16.851391 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5411 01:24:16.854988 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5412 01:24:16.858229 == TX Byte 1 ==
5413 01:24:16.861268 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5414 01:24:16.865075 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5415 01:24:16.865153 ==
5416 01:24:16.868151 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 01:24:16.871567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 01:24:16.874538 ==
5419 01:24:16.874622
5420 01:24:16.874686
5421 01:24:16.874745 TX Vref Scan disable
5422 01:24:16.878533 == TX Byte 0 ==
5423 01:24:16.881414 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5424 01:24:16.884905 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5425 01:24:16.888169 == TX Byte 1 ==
5426 01:24:16.891628 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5427 01:24:16.898046 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5428 01:24:16.898136
5429 01:24:16.898210 [DATLAT]
5430 01:24:16.898271 Freq=933, CH0 RK1
5431 01:24:16.898329
5432 01:24:16.901517 DATLAT Default: 0xb
5433 01:24:16.901607 0, 0xFFFF, sum = 0
5434 01:24:16.904882 1, 0xFFFF, sum = 0
5435 01:24:16.904975 2, 0xFFFF, sum = 0
5436 01:24:16.908946 3, 0xFFFF, sum = 0
5437 01:24:16.909075 4, 0xFFFF, sum = 0
5438 01:24:16.911710 5, 0xFFFF, sum = 0
5439 01:24:16.914746 6, 0xFFFF, sum = 0
5440 01:24:16.914860 7, 0xFFFF, sum = 0
5441 01:24:16.917934 8, 0xFFFF, sum = 0
5442 01:24:16.918047 9, 0xFFFF, sum = 0
5443 01:24:16.921231 10, 0x0, sum = 1
5444 01:24:16.921348 11, 0x0, sum = 2
5445 01:24:16.921451 12, 0x0, sum = 3
5446 01:24:16.924481 13, 0x0, sum = 4
5447 01:24:16.924594 best_step = 11
5448 01:24:16.924702
5449 01:24:16.927905 ==
5450 01:24:16.928019 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 01:24:16.934982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 01:24:16.935110 ==
5453 01:24:16.935213 RX Vref Scan: 0
5454 01:24:16.935311
5455 01:24:16.938013 RX Vref 0 -> 0, step: 1
5456 01:24:16.938131
5457 01:24:16.941385 RX Delay -61 -> 252, step: 4
5458 01:24:16.944802 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5459 01:24:16.951258 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5460 01:24:16.954703 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5461 01:24:16.958020 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5462 01:24:16.961429 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5463 01:24:16.964953 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5464 01:24:16.968246 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5465 01:24:16.974973 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5466 01:24:16.977936 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5467 01:24:16.981618 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5468 01:24:16.984561 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5469 01:24:16.988008 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5470 01:24:16.991390 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5471 01:24:16.998002 iDelay=199, Bit 13, Center 90 (3 ~ 178) 176
5472 01:24:17.001418 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5473 01:24:17.005251 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5474 01:24:17.005421 ==
5475 01:24:17.007977 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 01:24:17.011256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 01:24:17.011373 ==
5478 01:24:17.014579 DQS Delay:
5479 01:24:17.014698 DQS0 = 0, DQS1 = 0
5480 01:24:17.017926 DQM Delay:
5481 01:24:17.018046 DQM0 = 95, DQM1 = 86
5482 01:24:17.018149 DQ Delay:
5483 01:24:17.021201 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5484 01:24:17.025031 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5485 01:24:17.027944 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =78
5486 01:24:17.031621 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =94
5487 01:24:17.031740
5488 01:24:17.031848
5489 01:24:17.041784 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5490 01:24:17.044538 CH0 RK1: MR19=505, MR18=1A06
5491 01:24:17.047953 CH0_RK1: MR19=0x505, MR18=0x1A06, DQSOSC=413, MR23=63, INC=63, DEC=42
5492 01:24:17.051268 [RxdqsGatingPostProcess] freq 933
5493 01:24:17.057878 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5494 01:24:17.061389 best DQS0 dly(2T, 0.5T) = (0, 10)
5495 01:24:17.064926 best DQS1 dly(2T, 0.5T) = (0, 11)
5496 01:24:17.068330 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5497 01:24:17.071673 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5498 01:24:17.074879 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 01:24:17.078488 best DQS1 dly(2T, 0.5T) = (0, 11)
5500 01:24:17.081878 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 01:24:17.084978 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5502 01:24:17.085054 Pre-setting of DQS Precalculation
5503 01:24:17.091265 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5504 01:24:17.091349 ==
5505 01:24:17.094878 Dram Type= 6, Freq= 0, CH_1, rank 0
5506 01:24:17.098217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 01:24:17.098293 ==
5508 01:24:17.104806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 01:24:17.111757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5510 01:24:17.114926 [CA 0] Center 36 (6~67) winsize 62
5511 01:24:17.118239 [CA 1] Center 36 (6~67) winsize 62
5512 01:24:17.121553 [CA 2] Center 34 (4~64) winsize 61
5513 01:24:17.124884 [CA 3] Center 33 (3~64) winsize 62
5514 01:24:17.128370 [CA 4] Center 34 (4~64) winsize 61
5515 01:24:17.132572 [CA 5] Center 33 (3~63) winsize 61
5516 01:24:17.132699
5517 01:24:17.134960 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5518 01:24:17.135083
5519 01:24:17.138703 [CATrainingPosCal] consider 1 rank data
5520 01:24:17.141495 u2DelayCellTimex100 = 270/100 ps
5521 01:24:17.144976 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 01:24:17.148547 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 01:24:17.152183 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 01:24:17.154967 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 01:24:17.158952 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5526 01:24:17.162028 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5527 01:24:17.162145
5528 01:24:17.164980 CA PerBit enable=1, Macro0, CA PI delay=33
5529 01:24:17.165095
5530 01:24:17.168581 [CBTSetCACLKResult] CA Dly = 33
5531 01:24:17.172114 CS Dly: 5 (0~36)
5532 01:24:17.172237 ==
5533 01:24:17.175146 Dram Type= 6, Freq= 0, CH_1, rank 1
5534 01:24:17.178942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 01:24:17.179086 ==
5536 01:24:17.185351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 01:24:17.192340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5538 01:24:17.195143 [CA 0] Center 36 (6~67) winsize 62
5539 01:24:17.198367 [CA 1] Center 36 (6~67) winsize 62
5540 01:24:17.201978 [CA 2] Center 33 (3~64) winsize 62
5541 01:24:17.205353 [CA 3] Center 33 (3~64) winsize 62
5542 01:24:17.208640 [CA 4] Center 34 (4~64) winsize 61
5543 01:24:17.208748 [CA 5] Center 32 (2~63) winsize 62
5544 01:24:17.211772
5545 01:24:17.215546 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5546 01:24:17.215645
5547 01:24:17.218599 [CATrainingPosCal] consider 2 rank data
5548 01:24:17.221877 u2DelayCellTimex100 = 270/100 ps
5549 01:24:17.225283 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 01:24:17.228421 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 01:24:17.232099 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 01:24:17.235190 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 01:24:17.238869 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5554 01:24:17.241786 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5555 01:24:17.241887
5556 01:24:17.245179 CA PerBit enable=1, Macro0, CA PI delay=33
5557 01:24:17.245266
5558 01:24:17.248410 [CBTSetCACLKResult] CA Dly = 33
5559 01:24:17.251721 CS Dly: 6 (0~38)
5560 01:24:17.251811
5561 01:24:17.255200 ----->DramcWriteLeveling(PI) begin...
5562 01:24:17.255289 ==
5563 01:24:17.258329 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 01:24:17.261955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 01:24:17.262053 ==
5566 01:24:17.265112 Write leveling (Byte 0): 27 => 27
5567 01:24:17.268287 Write leveling (Byte 1): 29 => 29
5568 01:24:17.271786 DramcWriteLeveling(PI) end<-----
5569 01:24:17.271879
5570 01:24:17.271946 ==
5571 01:24:17.275025 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 01:24:17.278637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 01:24:17.278757 ==
5574 01:24:17.281948 [Gating] SW mode calibration
5575 01:24:17.288511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5576 01:24:17.295491 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5577 01:24:17.298594 0 14 0 | B1->B0 | 2f2f 3030 | 1 1 | (1 1) (1 1)
5578 01:24:17.301988 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5579 01:24:17.308737 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5580 01:24:17.311765 0 14 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5581 01:24:17.315258 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 01:24:17.321916 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 01:24:17.325275 0 14 24 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5584 01:24:17.328630 0 14 28 | B1->B0 | 2f2f 3232 | 1 1 | (1 0) (1 0)
5585 01:24:17.335380 0 15 0 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
5586 01:24:17.339155 0 15 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
5587 01:24:17.342229 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 01:24:17.349027 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 01:24:17.352003 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 01:24:17.355132 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 01:24:17.362098 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 01:24:17.365765 0 15 28 | B1->B0 | 3535 3030 | 0 0 | (1 1) (0 0)
5593 01:24:17.368599 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5594 01:24:17.371969 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 01:24:17.378753 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 01:24:17.381886 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 01:24:17.385187 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 01:24:17.392377 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 01:24:17.395089 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5600 01:24:17.399164 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5601 01:24:17.405594 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 01:24:17.409261 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 01:24:17.411938 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 01:24:17.418544 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 01:24:17.422055 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 01:24:17.425384 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 01:24:17.432217 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 01:24:17.435571 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 01:24:17.438731 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 01:24:17.445687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 01:24:17.448639 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 01:24:17.452709 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 01:24:17.458638 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 01:24:17.461941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 01:24:17.465445 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5616 01:24:17.468982 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5617 01:24:17.475625 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5618 01:24:17.479085 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 01:24:17.482315 Total UI for P1: 0, mck2ui 16
5620 01:24:17.485687 best dqsien dly found for B0: ( 1, 2, 28)
5621 01:24:17.489129 Total UI for P1: 0, mck2ui 16
5622 01:24:17.492203 best dqsien dly found for B1: ( 1, 2, 28)
5623 01:24:17.495878 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5624 01:24:17.498869 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5625 01:24:17.498983
5626 01:24:17.502544 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5627 01:24:17.505713 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5628 01:24:17.509295 [Gating] SW calibration Done
5629 01:24:17.509409 ==
5630 01:24:17.512599 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 01:24:17.515706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 01:24:17.519162 ==
5633 01:24:17.519276 RX Vref Scan: 0
5634 01:24:17.519370
5635 01:24:17.522263 RX Vref 0 -> 0, step: 1
5636 01:24:17.522371
5637 01:24:17.525847 RX Delay -80 -> 252, step: 8
5638 01:24:17.529196 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5639 01:24:17.532066 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5640 01:24:17.535844 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5641 01:24:17.538739 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5642 01:24:17.542475 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5643 01:24:17.546057 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5644 01:24:17.552540 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5645 01:24:17.555749 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5646 01:24:17.558950 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5647 01:24:17.562683 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5648 01:24:17.565583 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5649 01:24:17.572429 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5650 01:24:17.575602 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5651 01:24:17.579077 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5652 01:24:17.582391 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5653 01:24:17.586192 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5654 01:24:17.586308 ==
5655 01:24:17.589412 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 01:24:17.592790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 01:24:17.595902 ==
5658 01:24:17.596032 DQS Delay:
5659 01:24:17.596130 DQS0 = 0, DQS1 = 0
5660 01:24:17.599134 DQM Delay:
5661 01:24:17.599236 DQM0 = 96, DQM1 = 89
5662 01:24:17.602664 DQ Delay:
5663 01:24:17.602868 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5664 01:24:17.605864 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5665 01:24:17.609289 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5666 01:24:17.613187 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5667 01:24:17.615919
5668 01:24:17.616095
5669 01:24:17.616240 ==
5670 01:24:17.619213 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 01:24:17.622499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 01:24:17.622666 ==
5673 01:24:17.622810
5674 01:24:17.622948
5675 01:24:17.625881 TX Vref Scan disable
5676 01:24:17.626045 == TX Byte 0 ==
5677 01:24:17.632564 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5678 01:24:17.635924 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5679 01:24:17.636123 == TX Byte 1 ==
5680 01:24:17.643189 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5681 01:24:17.645864 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5682 01:24:17.646041 ==
5683 01:24:17.649344 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 01:24:17.652551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 01:24:17.652732 ==
5686 01:24:17.652864
5687 01:24:17.652999
5688 01:24:17.655868 TX Vref Scan disable
5689 01:24:17.659503 == TX Byte 0 ==
5690 01:24:17.662669 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5691 01:24:17.666001 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5692 01:24:17.669186 == TX Byte 1 ==
5693 01:24:17.673338 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5694 01:24:17.676092 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5695 01:24:17.676268
5696 01:24:17.679298 [DATLAT]
5697 01:24:17.679422 Freq=933, CH1 RK0
5698 01:24:17.679520
5699 01:24:17.682697 DATLAT Default: 0xd
5700 01:24:17.682810 0, 0xFFFF, sum = 0
5701 01:24:17.686432 1, 0xFFFF, sum = 0
5702 01:24:17.686548 2, 0xFFFF, sum = 0
5703 01:24:17.689423 3, 0xFFFF, sum = 0
5704 01:24:17.689513 4, 0xFFFF, sum = 0
5705 01:24:17.692733 5, 0xFFFF, sum = 0
5706 01:24:17.692833 6, 0xFFFF, sum = 0
5707 01:24:17.696022 7, 0xFFFF, sum = 0
5708 01:24:17.696100 8, 0xFFFF, sum = 0
5709 01:24:17.699654 9, 0xFFFF, sum = 0
5710 01:24:17.699756 10, 0x0, sum = 1
5711 01:24:17.702649 11, 0x0, sum = 2
5712 01:24:17.702729 12, 0x0, sum = 3
5713 01:24:17.706402 13, 0x0, sum = 4
5714 01:24:17.706480 best_step = 11
5715 01:24:17.706544
5716 01:24:17.706607 ==
5717 01:24:17.709710 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 01:24:17.712685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 01:24:17.712773 ==
5720 01:24:17.716503 RX Vref Scan: 1
5721 01:24:17.716607
5722 01:24:17.719579 RX Vref 0 -> 0, step: 1
5723 01:24:17.719684
5724 01:24:17.719779 RX Delay -61 -> 252, step: 4
5725 01:24:17.719867
5726 01:24:17.722660 Set Vref, RX VrefLevel [Byte0]: 59
5727 01:24:17.726183 [Byte1]: 53
5728 01:24:17.731145
5729 01:24:17.731259 Final RX Vref Byte 0 = 59 to rank0
5730 01:24:17.734287 Final RX Vref Byte 1 = 53 to rank0
5731 01:24:17.737813 Final RX Vref Byte 0 = 59 to rank1
5732 01:24:17.740908 Final RX Vref Byte 1 = 53 to rank1==
5733 01:24:17.744505 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 01:24:17.748125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 01:24:17.750785 ==
5736 01:24:17.750894 DQS Delay:
5737 01:24:17.750986 DQS0 = 0, DQS1 = 0
5738 01:24:17.754187 DQM Delay:
5739 01:24:17.754291 DQM0 = 98, DQM1 = 90
5740 01:24:17.757754 DQ Delay:
5741 01:24:17.761258 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =96
5742 01:24:17.764845 DQ4 =98, DQ5 =106, DQ6 =108, DQ7 =94
5743 01:24:17.764939 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5744 01:24:17.770871 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5745 01:24:17.770972
5746 01:24:17.771041
5747 01:24:17.777511 [DQSOSCAuto] RK0, (LSB)MR18= 0x16f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5748 01:24:17.781100 CH1 RK0: MR19=504, MR18=16F3
5749 01:24:17.788068 CH1_RK0: MR19=0x504, MR18=0x16F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5750 01:24:17.788294
5751 01:24:17.791151 ----->DramcWriteLeveling(PI) begin...
5752 01:24:17.791324 ==
5753 01:24:17.794624 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 01:24:17.797521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 01:24:17.797699 ==
5756 01:24:17.801265 Write leveling (Byte 0): 29 => 29
5757 01:24:17.804507 Write leveling (Byte 1): 29 => 29
5758 01:24:17.807587 DramcWriteLeveling(PI) end<-----
5759 01:24:17.807748
5760 01:24:17.807890 ==
5761 01:24:17.811012 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 01:24:17.814744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 01:24:17.814923 ==
5764 01:24:17.817741 [Gating] SW mode calibration
5765 01:24:17.824434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5766 01:24:17.831834 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5767 01:24:17.834667 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5768 01:24:17.837964 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 01:24:17.844327 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5770 01:24:17.847822 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5771 01:24:17.851203 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 01:24:17.857925 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5773 01:24:17.861385 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
5774 01:24:17.864592 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
5775 01:24:17.871073 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 01:24:17.874540 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5777 01:24:17.878219 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 01:24:17.881376 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5779 01:24:17.887972 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 01:24:17.891712 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5781 01:24:17.894741 0 15 24 | B1->B0 | 2727 3737 | 0 1 | (0 0) (0 0)
5782 01:24:17.901450 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5783 01:24:17.904588 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 01:24:17.907957 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 01:24:17.914594 1 0 8 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
5786 01:24:17.917942 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 01:24:17.921455 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 01:24:17.928392 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 01:24:17.931570 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5790 01:24:17.935105 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5791 01:24:17.941442 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 01:24:17.945083 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 01:24:17.947962 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 01:24:17.954841 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 01:24:17.958303 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 01:24:17.961947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 01:24:17.965097 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 01:24:17.971322 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 01:24:17.975059 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 01:24:17.977947 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 01:24:17.984634 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 01:24:17.988342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 01:24:17.991123 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 01:24:17.997968 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 01:24:18.001343 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5806 01:24:18.004647 Total UI for P1: 0, mck2ui 16
5807 01:24:18.008115 best dqsien dly found for B0: ( 1, 2, 22)
5808 01:24:18.011440 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 01:24:18.015018 Total UI for P1: 0, mck2ui 16
5810 01:24:18.018125 best dqsien dly found for B1: ( 1, 2, 24)
5811 01:24:18.021641 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5812 01:24:18.024678 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5813 01:24:18.024835
5814 01:24:18.031591 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5815 01:24:18.034935 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5816 01:24:18.035072 [Gating] SW calibration Done
5817 01:24:18.037968 ==
5818 01:24:18.038110 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 01:24:18.045240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 01:24:18.045363 ==
5821 01:24:18.045432 RX Vref Scan: 0
5822 01:24:18.045498
5823 01:24:18.048140 RX Vref 0 -> 0, step: 1
5824 01:24:18.048317
5825 01:24:18.051404 RX Delay -80 -> 252, step: 8
5826 01:24:18.054616 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5827 01:24:18.058094 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5828 01:24:18.061339 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5829 01:24:18.064943 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5830 01:24:18.071521 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5831 01:24:18.074932 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5832 01:24:18.078514 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5833 01:24:18.081810 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5834 01:24:18.085248 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5835 01:24:18.088607 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5836 01:24:18.095275 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5837 01:24:18.098400 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5838 01:24:18.101980 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5839 01:24:18.105280 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5840 01:24:18.108328 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5841 01:24:18.111796 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5842 01:24:18.114966 ==
5843 01:24:18.118401 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 01:24:18.121619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 01:24:18.121704 ==
5846 01:24:18.121770 DQS Delay:
5847 01:24:18.125282 DQS0 = 0, DQS1 = 0
5848 01:24:18.125368 DQM Delay:
5849 01:24:18.128327 DQM0 = 94, DQM1 = 88
5850 01:24:18.128411 DQ Delay:
5851 01:24:18.132069 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5852 01:24:18.135484 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5853 01:24:18.138474 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5854 01:24:18.142107 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5855 01:24:18.142209
5856 01:24:18.142277
5857 01:24:18.142337 ==
5858 01:24:18.145267 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 01:24:18.148612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 01:24:18.148723 ==
5861 01:24:18.148790
5862 01:24:18.148851
5863 01:24:18.151820 TX Vref Scan disable
5864 01:24:18.155570 == TX Byte 0 ==
5865 01:24:18.158953 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5866 01:24:18.162505 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5867 01:24:18.165253 == TX Byte 1 ==
5868 01:24:18.168431 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5869 01:24:18.171647 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5870 01:24:18.171734 ==
5871 01:24:18.175205 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 01:24:18.178514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 01:24:18.178643 ==
5874 01:24:18.181917
5875 01:24:18.182030
5876 01:24:18.182128 TX Vref Scan disable
5877 01:24:18.185332 == TX Byte 0 ==
5878 01:24:18.188641 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5879 01:24:18.191811 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5880 01:24:18.195225 == TX Byte 1 ==
5881 01:24:18.198436 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5882 01:24:18.201930 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5883 01:24:18.205270
5884 01:24:18.205367 [DATLAT]
5885 01:24:18.205470 Freq=933, CH1 RK1
5886 01:24:18.205573
5887 01:24:18.208552 DATLAT Default: 0xb
5888 01:24:18.208654 0, 0xFFFF, sum = 0
5889 01:24:18.211725 1, 0xFFFF, sum = 0
5890 01:24:18.211828 2, 0xFFFF, sum = 0
5891 01:24:18.215489 3, 0xFFFF, sum = 0
5892 01:24:18.215595 4, 0xFFFF, sum = 0
5893 01:24:18.218718 5, 0xFFFF, sum = 0
5894 01:24:18.218827 6, 0xFFFF, sum = 0
5895 01:24:18.222063 7, 0xFFFF, sum = 0
5896 01:24:18.225703 8, 0xFFFF, sum = 0
5897 01:24:18.225782 9, 0xFFFF, sum = 0
5898 01:24:18.225859 10, 0x0, sum = 1
5899 01:24:18.228791 11, 0x0, sum = 2
5900 01:24:18.228867 12, 0x0, sum = 3
5901 01:24:18.232247 13, 0x0, sum = 4
5902 01:24:18.232354 best_step = 11
5903 01:24:18.232443
5904 01:24:18.232528 ==
5905 01:24:18.235427 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 01:24:18.241988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 01:24:18.242123 ==
5908 01:24:18.242217 RX Vref Scan: 0
5909 01:24:18.242315
5910 01:24:18.245279 RX Vref 0 -> 0, step: 1
5911 01:24:18.245357
5912 01:24:18.248781 RX Delay -61 -> 252, step: 4
5913 01:24:18.251801 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5914 01:24:18.255338 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5915 01:24:18.262496 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5916 01:24:18.265078 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5917 01:24:18.268520 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5918 01:24:18.272484 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5919 01:24:18.275235 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5920 01:24:18.278476 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5921 01:24:18.285412 iDelay=199, Bit 8, Center 82 (-9 ~ 174) 184
5922 01:24:18.288490 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5923 01:24:18.291741 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5924 01:24:18.295248 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5925 01:24:18.298806 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5926 01:24:18.301964 iDelay=199, Bit 13, Center 96 (3 ~ 190) 188
5927 01:24:18.308892 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5928 01:24:18.312093 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5929 01:24:18.312204 ==
5930 01:24:18.315483 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 01:24:18.319114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 01:24:18.319193 ==
5933 01:24:18.322105 DQS Delay:
5934 01:24:18.322190 DQS0 = 0, DQS1 = 0
5935 01:24:18.322253 DQM Delay:
5936 01:24:18.325514 DQM0 = 95, DQM1 = 90
5937 01:24:18.325595 DQ Delay:
5938 01:24:18.328656 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5939 01:24:18.331924 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =90
5940 01:24:18.335577 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =82
5941 01:24:18.338896 DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =98
5942 01:24:18.338981
5943 01:24:18.339045
5944 01:24:18.348995 [DQSOSCAuto] RK1, (LSB)MR18= 0xe16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5945 01:24:18.349085 CH1 RK1: MR19=505, MR18=E16
5946 01:24:18.355433 CH1_RK1: MR19=0x505, MR18=0xE16, DQSOSC=414, MR23=63, INC=63, DEC=42
5947 01:24:18.358851 [RxdqsGatingPostProcess] freq 933
5948 01:24:18.365842 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5949 01:24:18.369291 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 01:24:18.372877 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 01:24:18.375886 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 01:24:18.378817 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 01:24:18.378952 best DQS0 dly(2T, 0.5T) = (0, 10)
5954 01:24:18.382225 best DQS1 dly(2T, 0.5T) = (0, 10)
5955 01:24:18.385477 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5956 01:24:18.389092 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5957 01:24:18.393167 Pre-setting of DQS Precalculation
5958 01:24:18.399436 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5959 01:24:18.405781 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5960 01:24:18.412233 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5961 01:24:18.412357
5962 01:24:18.412476
5963 01:24:18.415599 [Calibration Summary] 1866 Mbps
5964 01:24:18.415702 CH 0, Rank 0
5965 01:24:18.419548 SW Impedance : PASS
5966 01:24:18.422283 DUTY Scan : NO K
5967 01:24:18.422390 ZQ Calibration : PASS
5968 01:24:18.425895 Jitter Meter : NO K
5969 01:24:18.429497 CBT Training : PASS
5970 01:24:18.429582 Write leveling : PASS
5971 01:24:18.432387 RX DQS gating : PASS
5972 01:24:18.432459 RX DQ/DQS(RDDQC) : PASS
5973 01:24:18.435808 TX DQ/DQS : PASS
5974 01:24:18.439013 RX DATLAT : PASS
5975 01:24:18.439097 RX DQ/DQS(Engine): PASS
5976 01:24:18.442474 TX OE : NO K
5977 01:24:18.442579 All Pass.
5978 01:24:18.442676
5979 01:24:18.446325 CH 0, Rank 1
5980 01:24:18.446402 SW Impedance : PASS
5981 01:24:18.448826 DUTY Scan : NO K
5982 01:24:18.452288 ZQ Calibration : PASS
5983 01:24:18.452400 Jitter Meter : NO K
5984 01:24:18.455979 CBT Training : PASS
5985 01:24:18.459395 Write leveling : PASS
5986 01:24:18.459482 RX DQS gating : PASS
5987 01:24:18.462680 RX DQ/DQS(RDDQC) : PASS
5988 01:24:18.465909 TX DQ/DQS : PASS
5989 01:24:18.466018 RX DATLAT : PASS
5990 01:24:18.468948 RX DQ/DQS(Engine): PASS
5991 01:24:18.472434 TX OE : NO K
5992 01:24:18.472542 All Pass.
5993 01:24:18.472630
5994 01:24:18.472726 CH 1, Rank 0
5995 01:24:18.475776 SW Impedance : PASS
5996 01:24:18.479188 DUTY Scan : NO K
5997 01:24:18.479296 ZQ Calibration : PASS
5998 01:24:18.482259 Jitter Meter : NO K
5999 01:24:18.482363 CBT Training : PASS
6000 01:24:18.485540 Write leveling : PASS
6001 01:24:18.489039 RX DQS gating : PASS
6002 01:24:18.489146 RX DQ/DQS(RDDQC) : PASS
6003 01:24:18.492382 TX DQ/DQS : PASS
6004 01:24:18.495564 RX DATLAT : PASS
6005 01:24:18.495668 RX DQ/DQS(Engine): PASS
6006 01:24:18.498933 TX OE : NO K
6007 01:24:18.499041 All Pass.
6008 01:24:18.499132
6009 01:24:18.502400 CH 1, Rank 1
6010 01:24:18.502507 SW Impedance : PASS
6011 01:24:18.505919 DUTY Scan : NO K
6012 01:24:18.509046 ZQ Calibration : PASS
6013 01:24:18.509152 Jitter Meter : NO K
6014 01:24:18.512525 CBT Training : PASS
6015 01:24:18.515744 Write leveling : PASS
6016 01:24:18.515851 RX DQS gating : PASS
6017 01:24:18.518888 RX DQ/DQS(RDDQC) : PASS
6018 01:24:18.518989 TX DQ/DQS : PASS
6019 01:24:18.522264 RX DATLAT : PASS
6020 01:24:18.525836 RX DQ/DQS(Engine): PASS
6021 01:24:18.525946 TX OE : NO K
6022 01:24:18.529226 All Pass.
6023 01:24:18.529335
6024 01:24:18.529427 DramC Write-DBI off
6025 01:24:18.532439 PER_BANK_REFRESH: Hybrid Mode
6026 01:24:18.536068 TX_TRACKING: ON
6027 01:24:18.542710 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6028 01:24:18.545957 [FAST_K] Save calibration result to emmc
6029 01:24:18.549023 dramc_set_vcore_voltage set vcore to 650000
6030 01:24:18.552688 Read voltage for 400, 6
6031 01:24:18.552797 Vio18 = 0
6032 01:24:18.556121 Vcore = 650000
6033 01:24:18.556227 Vdram = 0
6034 01:24:18.556318 Vddq = 0
6035 01:24:18.559517 Vmddr = 0
6036 01:24:18.562584 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6037 01:24:18.570048 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6038 01:24:18.570157 MEM_TYPE=3, freq_sel=20
6039 01:24:18.573139 sv_algorithm_assistance_LP4_800
6040 01:24:18.575954 ============ PULL DRAM RESETB DOWN ============
6041 01:24:18.582702 ========== PULL DRAM RESETB DOWN end =========
6042 01:24:18.586343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6043 01:24:18.589367 ===================================
6044 01:24:18.593016 LPDDR4 DRAM CONFIGURATION
6045 01:24:18.596156 ===================================
6046 01:24:18.596264 EX_ROW_EN[0] = 0x0
6047 01:24:18.599642 EX_ROW_EN[1] = 0x0
6048 01:24:18.599750 LP4Y_EN = 0x0
6049 01:24:18.602791 WORK_FSP = 0x0
6050 01:24:18.602909 WL = 0x2
6051 01:24:18.606535 RL = 0x2
6052 01:24:18.606645 BL = 0x2
6053 01:24:18.609970 RPST = 0x0
6054 01:24:18.610077 RD_PRE = 0x0
6055 01:24:18.612825 WR_PRE = 0x1
6056 01:24:18.612933 WR_PST = 0x0
6057 01:24:18.616525 DBI_WR = 0x0
6058 01:24:18.619757 DBI_RD = 0x0
6059 01:24:18.619864 OTF = 0x1
6060 01:24:18.623360 ===================================
6061 01:24:18.626671 ===================================
6062 01:24:18.626779 ANA top config
6063 01:24:18.630144 ===================================
6064 01:24:18.632996 DLL_ASYNC_EN = 0
6065 01:24:18.636406 ALL_SLAVE_EN = 1
6066 01:24:18.639890 NEW_RANK_MODE = 1
6067 01:24:18.640007 DLL_IDLE_MODE = 1
6068 01:24:18.643336 LP45_APHY_COMB_EN = 1
6069 01:24:18.646514 TX_ODT_DIS = 1
6070 01:24:18.649722 NEW_8X_MODE = 1
6071 01:24:18.653079 ===================================
6072 01:24:18.656603 ===================================
6073 01:24:18.659689 data_rate = 800
6074 01:24:18.659797 CKR = 1
6075 01:24:18.663220 DQ_P2S_RATIO = 4
6076 01:24:18.666532 ===================================
6077 01:24:18.669884 CA_P2S_RATIO = 4
6078 01:24:18.673227 DQ_CA_OPEN = 0
6079 01:24:18.676844 DQ_SEMI_OPEN = 1
6080 01:24:18.679819 CA_SEMI_OPEN = 1
6081 01:24:18.679925 CA_FULL_RATE = 0
6082 01:24:18.683256 DQ_CKDIV4_EN = 0
6083 01:24:18.686851 CA_CKDIV4_EN = 1
6084 01:24:18.689836 CA_PREDIV_EN = 0
6085 01:24:18.693407 PH8_DLY = 0
6086 01:24:18.696532 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6087 01:24:18.696640 DQ_AAMCK_DIV = 0
6088 01:24:18.699858 CA_AAMCK_DIV = 0
6089 01:24:18.703421 CA_ADMCK_DIV = 4
6090 01:24:18.706807 DQ_TRACK_CA_EN = 0
6091 01:24:18.709728 CA_PICK = 800
6092 01:24:18.713788 CA_MCKIO = 400
6093 01:24:18.713898 MCKIO_SEMI = 400
6094 01:24:18.716580 PLL_FREQ = 3016
6095 01:24:18.720101 DQ_UI_PI_RATIO = 32
6096 01:24:18.723394 CA_UI_PI_RATIO = 32
6097 01:24:18.726924 ===================================
6098 01:24:18.730095 ===================================
6099 01:24:18.733421 memory_type:LPDDR4
6100 01:24:18.733529 GP_NUM : 10
6101 01:24:18.736879 SRAM_EN : 1
6102 01:24:18.740084 MD32_EN : 0
6103 01:24:18.743808 ===================================
6104 01:24:18.743922 [ANA_INIT] >>>>>>>>>>>>>>
6105 01:24:18.746762 <<<<<< [CONFIGURE PHASE]: ANA_TX
6106 01:24:18.750300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6107 01:24:18.753689 ===================================
6108 01:24:18.756738 data_rate = 800,PCW = 0X7400
6109 01:24:18.760289 ===================================
6110 01:24:18.763534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6111 01:24:18.770073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6112 01:24:18.780135 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6113 01:24:18.783708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6114 01:24:18.786753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6115 01:24:18.790031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6116 01:24:18.793309 [ANA_INIT] flow start
6117 01:24:18.796948 [ANA_INIT] PLL >>>>>>>>
6118 01:24:18.797055 [ANA_INIT] PLL <<<<<<<<
6119 01:24:18.800012 [ANA_INIT] MIDPI >>>>>>>>
6120 01:24:18.803592 [ANA_INIT] MIDPI <<<<<<<<
6121 01:24:18.807037 [ANA_INIT] DLL >>>>>>>>
6122 01:24:18.807142 [ANA_INIT] flow end
6123 01:24:18.810193 ============ LP4 DIFF to SE enter ============
6124 01:24:18.817299 ============ LP4 DIFF to SE exit ============
6125 01:24:18.817412 [ANA_INIT] <<<<<<<<<<<<<
6126 01:24:18.820366 [Flow] Enable top DCM control >>>>>
6127 01:24:18.823512 [Flow] Enable top DCM control <<<<<
6128 01:24:18.827264 Enable DLL master slave shuffle
6129 01:24:18.833780 ==============================================================
6130 01:24:18.833892 Gating Mode config
6131 01:24:18.840340 ==============================================================
6132 01:24:18.843804 Config description:
6133 01:24:18.850289 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6134 01:24:18.857009 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6135 01:24:18.863640 SELPH_MODE 0: By rank 1: By Phase
6136 01:24:18.870440 ==============================================================
6137 01:24:18.870572 GAT_TRACK_EN = 0
6138 01:24:18.873921 RX_GATING_MODE = 2
6139 01:24:18.877361 RX_GATING_TRACK_MODE = 2
6140 01:24:18.880594 SELPH_MODE = 1
6141 01:24:18.883648 PICG_EARLY_EN = 1
6142 01:24:18.886915 VALID_LAT_VALUE = 1
6143 01:24:18.893467 ==============================================================
6144 01:24:18.897128 Enter into Gating configuration >>>>
6145 01:24:18.900479 Exit from Gating configuration <<<<
6146 01:24:18.900587 Enter into DVFS_PRE_config >>>>>
6147 01:24:18.913975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6148 01:24:18.917003 Exit from DVFS_PRE_config <<<<<
6149 01:24:18.920808 Enter into PICG configuration >>>>
6150 01:24:18.923762 Exit from PICG configuration <<<<
6151 01:24:18.923871 [RX_INPUT] configuration >>>>>
6152 01:24:18.927205 [RX_INPUT] configuration <<<<<
6153 01:24:18.933560 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6154 01:24:18.937405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6155 01:24:18.943653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 01:24:18.950626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 01:24:18.957356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6158 01:24:18.964017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6159 01:24:18.967375 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6160 01:24:18.970616 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6161 01:24:18.973786 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6162 01:24:18.980540 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6163 01:24:18.984141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6164 01:24:18.987383 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 01:24:18.990845 ===================================
6166 01:24:18.993739 LPDDR4 DRAM CONFIGURATION
6167 01:24:18.997580 ===================================
6168 01:24:19.000713 EX_ROW_EN[0] = 0x0
6169 01:24:19.000823 EX_ROW_EN[1] = 0x0
6170 01:24:19.004168 LP4Y_EN = 0x0
6171 01:24:19.004277 WORK_FSP = 0x0
6172 01:24:19.007250 WL = 0x2
6173 01:24:19.007357 RL = 0x2
6174 01:24:19.010704 BL = 0x2
6175 01:24:19.010817 RPST = 0x0
6176 01:24:19.014174 RD_PRE = 0x0
6177 01:24:19.014283 WR_PRE = 0x1
6178 01:24:19.017246 WR_PST = 0x0
6179 01:24:19.017352 DBI_WR = 0x0
6180 01:24:19.020497 DBI_RD = 0x0
6181 01:24:19.020597 OTF = 0x1
6182 01:24:19.023883 ===================================
6183 01:24:19.027244 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6184 01:24:19.034044 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6185 01:24:19.037450 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6186 01:24:19.041332 ===================================
6187 01:24:19.044279 LPDDR4 DRAM CONFIGURATION
6188 01:24:19.047624 ===================================
6189 01:24:19.047736 EX_ROW_EN[0] = 0x10
6190 01:24:19.051095 EX_ROW_EN[1] = 0x0
6191 01:24:19.051201 LP4Y_EN = 0x0
6192 01:24:19.055021 WORK_FSP = 0x0
6193 01:24:19.055132 WL = 0x2
6194 01:24:19.057877 RL = 0x2
6195 01:24:19.057991 BL = 0x2
6196 01:24:19.060881 RPST = 0x0
6197 01:24:19.060992 RD_PRE = 0x0
6198 01:24:19.064145 WR_PRE = 0x1
6199 01:24:19.067737 WR_PST = 0x0
6200 01:24:19.067841 DBI_WR = 0x0
6201 01:24:19.071297 DBI_RD = 0x0
6202 01:24:19.071404 OTF = 0x1
6203 01:24:19.074532 ===================================
6204 01:24:19.081038 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6205 01:24:19.084986 nWR fixed to 30
6206 01:24:19.087910 [ModeRegInit_LP4] CH0 RK0
6207 01:24:19.088016 [ModeRegInit_LP4] CH0 RK1
6208 01:24:19.091196 [ModeRegInit_LP4] CH1 RK0
6209 01:24:19.094650 [ModeRegInit_LP4] CH1 RK1
6210 01:24:19.094754 match AC timing 19
6211 01:24:19.101185 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6212 01:24:19.104528 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6213 01:24:19.108164 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6214 01:24:19.115043 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6215 01:24:19.118211 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6216 01:24:19.118325 ==
6217 01:24:19.121501 Dram Type= 6, Freq= 0, CH_0, rank 0
6218 01:24:19.125002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6219 01:24:19.125108 ==
6220 01:24:19.131590 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6221 01:24:19.138258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6222 01:24:19.141483 [CA 0] Center 36 (8~64) winsize 57
6223 01:24:19.144644 [CA 1] Center 36 (8~64) winsize 57
6224 01:24:19.144768 [CA 2] Center 36 (8~64) winsize 57
6225 01:24:19.148362 [CA 3] Center 36 (8~64) winsize 57
6226 01:24:19.151707 [CA 4] Center 36 (8~64) winsize 57
6227 01:24:19.154792 [CA 5] Center 36 (8~64) winsize 57
6228 01:24:19.154900
6229 01:24:19.158906 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6230 01:24:19.159015
6231 01:24:19.161644 [CATrainingPosCal] consider 1 rank data
6232 01:24:19.164924 u2DelayCellTimex100 = 270/100 ps
6233 01:24:19.168252 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 01:24:19.171746 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 01:24:19.178471 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 01:24:19.181450 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 01:24:19.185163 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 01:24:19.188243 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 01:24:19.188330
6240 01:24:19.191592 CA PerBit enable=1, Macro0, CA PI delay=36
6241 01:24:19.191678
6242 01:24:19.195156 [CBTSetCACLKResult] CA Dly = 36
6243 01:24:19.195243 CS Dly: 1 (0~32)
6244 01:24:19.195329 ==
6245 01:24:19.198579 Dram Type= 6, Freq= 0, CH_0, rank 1
6246 01:24:19.205175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 01:24:19.205265 ==
6248 01:24:19.208536 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6249 01:24:19.215345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6250 01:24:19.218568 [CA 0] Center 36 (8~64) winsize 57
6251 01:24:19.221796 [CA 1] Center 36 (8~64) winsize 57
6252 01:24:19.224934 [CA 2] Center 36 (8~64) winsize 57
6253 01:24:19.228607 [CA 3] Center 36 (8~64) winsize 57
6254 01:24:19.231960 [CA 4] Center 36 (8~64) winsize 57
6255 01:24:19.235765 [CA 5] Center 36 (8~64) winsize 57
6256 01:24:19.235852
6257 01:24:19.238288 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6258 01:24:19.238398
6259 01:24:19.241667 [CATrainingPosCal] consider 2 rank data
6260 01:24:19.245237 u2DelayCellTimex100 = 270/100 ps
6261 01:24:19.248549 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 01:24:19.251905 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 01:24:19.255192 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 01:24:19.258493 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 01:24:19.261928 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 01:24:19.265428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 01:24:19.265516
6268 01:24:19.271853 CA PerBit enable=1, Macro0, CA PI delay=36
6269 01:24:19.271968
6270 01:24:19.272063 [CBTSetCACLKResult] CA Dly = 36
6271 01:24:19.275113 CS Dly: 1 (0~32)
6272 01:24:19.275223
6273 01:24:19.278764 ----->DramcWriteLeveling(PI) begin...
6274 01:24:19.278874 ==
6275 01:24:19.282302 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 01:24:19.285067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 01:24:19.285175 ==
6278 01:24:19.288849 Write leveling (Byte 0): 40 => 8
6279 01:24:19.291867 Write leveling (Byte 1): 32 => 0
6280 01:24:19.295626 DramcWriteLeveling(PI) end<-----
6281 01:24:19.295731
6282 01:24:19.295822 ==
6283 01:24:19.298532 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 01:24:19.302104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 01:24:19.302214 ==
6286 01:24:19.305179 [Gating] SW mode calibration
6287 01:24:19.312272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6288 01:24:19.318610 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6289 01:24:19.321971 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6290 01:24:19.328632 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6291 01:24:19.332108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 01:24:19.335491 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 01:24:19.342123 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 01:24:19.345844 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 01:24:19.348861 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 01:24:19.352027 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 01:24:19.358641 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 01:24:19.362295 Total UI for P1: 0, mck2ui 16
6299 01:24:19.365625 best dqsien dly found for B0: ( 0, 14, 24)
6300 01:24:19.368478 Total UI for P1: 0, mck2ui 16
6301 01:24:19.372278 best dqsien dly found for B1: ( 0, 14, 24)
6302 01:24:19.375725 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6303 01:24:19.379058 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6304 01:24:19.379165
6305 01:24:19.382410 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6306 01:24:19.385634 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6307 01:24:19.388686 [Gating] SW calibration Done
6308 01:24:19.388793 ==
6309 01:24:19.392289 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 01:24:19.395381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 01:24:19.395488 ==
6312 01:24:19.398560 RX Vref Scan: 0
6313 01:24:19.398666
6314 01:24:19.398757 RX Vref 0 -> 0, step: 1
6315 01:24:19.402451
6316 01:24:19.402553 RX Delay -410 -> 252, step: 16
6317 01:24:19.409237 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6318 01:24:19.412038 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6319 01:24:19.415950 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6320 01:24:19.418876 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6321 01:24:19.425549 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6322 01:24:19.428853 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6323 01:24:19.432133 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6324 01:24:19.435345 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6325 01:24:19.442091 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6326 01:24:19.445508 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6327 01:24:19.449238 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6328 01:24:19.452309 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6329 01:24:19.459177 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6330 01:24:19.462466 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6331 01:24:19.465336 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6332 01:24:19.468970 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6333 01:24:19.469076 ==
6334 01:24:19.472441 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 01:24:19.478996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 01:24:19.479105 ==
6337 01:24:19.479199 DQS Delay:
6338 01:24:19.481973 DQS0 = 35, DQS1 = 51
6339 01:24:19.482076 DQM Delay:
6340 01:24:19.486005 DQM0 = 7, DQM1 = 10
6341 01:24:19.486111 DQ Delay:
6342 01:24:19.489104 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6343 01:24:19.491938 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6344 01:24:19.492045 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6345 01:24:19.495519 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6346 01:24:19.499077
6347 01:24:19.499181
6348 01:24:19.499271 ==
6349 01:24:19.502796 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 01:24:19.505557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 01:24:19.505665 ==
6352 01:24:19.505753
6353 01:24:19.505837
6354 01:24:19.508783 TX Vref Scan disable
6355 01:24:19.508890 == TX Byte 0 ==
6356 01:24:19.511910 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 01:24:19.518799 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 01:24:19.518912 == TX Byte 1 ==
6359 01:24:19.521936 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6360 01:24:19.529182 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6361 01:24:19.529291 ==
6362 01:24:19.532313 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 01:24:19.535520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 01:24:19.535634 ==
6365 01:24:19.535728
6366 01:24:19.535817
6367 01:24:19.539382 TX Vref Scan disable
6368 01:24:19.539488 == TX Byte 0 ==
6369 01:24:19.545204 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 01:24:19.548748 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 01:24:19.548858 == TX Byte 1 ==
6372 01:24:19.552238 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6373 01:24:19.558586 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6374 01:24:19.558697
6375 01:24:19.558788 [DATLAT]
6376 01:24:19.562089 Freq=400, CH0 RK0
6377 01:24:19.562197
6378 01:24:19.562287 DATLAT Default: 0xf
6379 01:24:19.565979 0, 0xFFFF, sum = 0
6380 01:24:19.566088 1, 0xFFFF, sum = 0
6381 01:24:19.568580 2, 0xFFFF, sum = 0
6382 01:24:19.568696 3, 0xFFFF, sum = 0
6383 01:24:19.572711 4, 0xFFFF, sum = 0
6384 01:24:19.572820 5, 0xFFFF, sum = 0
6385 01:24:19.575627 6, 0xFFFF, sum = 0
6386 01:24:19.575737 7, 0xFFFF, sum = 0
6387 01:24:19.578759 8, 0xFFFF, sum = 0
6388 01:24:19.578868 9, 0xFFFF, sum = 0
6389 01:24:19.582439 10, 0xFFFF, sum = 0
6390 01:24:19.582547 11, 0xFFFF, sum = 0
6391 01:24:19.585421 12, 0xFFFF, sum = 0
6392 01:24:19.585529 13, 0x0, sum = 1
6393 01:24:19.588748 14, 0x0, sum = 2
6394 01:24:19.588855 15, 0x0, sum = 3
6395 01:24:19.592290 16, 0x0, sum = 4
6396 01:24:19.592399 best_step = 14
6397 01:24:19.592490
6398 01:24:19.592576 ==
6399 01:24:19.595445 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 01:24:19.602262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 01:24:19.602379 ==
6402 01:24:19.602473 RX Vref Scan: 1
6403 01:24:19.602562
6404 01:24:19.605458 RX Vref 0 -> 0, step: 1
6405 01:24:19.605565
6406 01:24:19.609074 RX Delay -343 -> 252, step: 8
6407 01:24:19.609182
6408 01:24:19.612364 Set Vref, RX VrefLevel [Byte0]: 53
6409 01:24:19.615419 [Byte1]: 49
6410 01:24:19.615526
6411 01:24:19.618858 Final RX Vref Byte 0 = 53 to rank0
6412 01:24:19.622027 Final RX Vref Byte 1 = 49 to rank0
6413 01:24:19.625853 Final RX Vref Byte 0 = 53 to rank1
6414 01:24:19.629041 Final RX Vref Byte 1 = 49 to rank1==
6415 01:24:19.632459 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 01:24:19.635793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 01:24:19.635901 ==
6418 01:24:19.639362 DQS Delay:
6419 01:24:19.639468 DQS0 = 44, DQS1 = 60
6420 01:24:19.642016 DQM Delay:
6421 01:24:19.642123 DQM0 = 11, DQM1 = 15
6422 01:24:19.645528 DQ Delay:
6423 01:24:19.645635 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6424 01:24:19.649126 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6425 01:24:19.652236 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6426 01:24:19.655618 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6427 01:24:19.655719
6428 01:24:19.655809
6429 01:24:19.665833 [DQSOSCAuto] RK0, (LSB)MR18= 0x824f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6430 01:24:19.669247 CH0 RK0: MR19=C0C, MR18=824F
6431 01:24:19.672263 CH0_RK0: MR19=0xC0C, MR18=0x824F, DQSOSC=393, MR23=63, INC=382, DEC=254
6432 01:24:19.675425 ==
6433 01:24:19.675533 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 01:24:19.682277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 01:24:19.682366 ==
6436 01:24:19.685870 [Gating] SW mode calibration
6437 01:24:19.692627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6438 01:24:19.695807 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6439 01:24:19.702260 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 01:24:19.706025 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 01:24:19.709187 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 01:24:19.712822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 01:24:19.719595 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 01:24:19.722733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 01:24:19.726049 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 01:24:19.732894 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 01:24:19.736143 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 01:24:19.739532 Total UI for P1: 0, mck2ui 16
6449 01:24:19.742538 best dqsien dly found for B0: ( 0, 14, 24)
6450 01:24:19.746062 Total UI for P1: 0, mck2ui 16
6451 01:24:19.749340 best dqsien dly found for B1: ( 0, 14, 24)
6452 01:24:19.752599 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6453 01:24:19.756016 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6454 01:24:19.756132
6455 01:24:19.759592 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6456 01:24:19.762909 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6457 01:24:19.765777 [Gating] SW calibration Done
6458 01:24:19.765889 ==
6459 01:24:19.769304 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 01:24:19.772614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 01:24:19.776144 ==
6462 01:24:19.776228 RX Vref Scan: 0
6463 01:24:19.776293
6464 01:24:19.779439 RX Vref 0 -> 0, step: 1
6465 01:24:19.779518
6466 01:24:19.782550 RX Delay -410 -> 252, step: 16
6467 01:24:19.785820 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6468 01:24:19.789238 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6469 01:24:19.792458 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6470 01:24:19.799328 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6471 01:24:19.802633 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6472 01:24:19.805899 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6473 01:24:19.809477 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6474 01:24:19.816136 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6475 01:24:19.819408 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6476 01:24:19.822527 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6477 01:24:19.826247 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6478 01:24:19.832799 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6479 01:24:19.835880 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6480 01:24:19.839495 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6481 01:24:19.842502 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6482 01:24:19.849224 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6483 01:24:19.849345 ==
6484 01:24:19.852681 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 01:24:19.855924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 01:24:19.856034 ==
6487 01:24:19.856127 DQS Delay:
6488 01:24:19.859465 DQS0 = 43, DQS1 = 51
6489 01:24:19.859573 DQM Delay:
6490 01:24:19.862620 DQM0 = 11, DQM1 = 11
6491 01:24:19.862730 DQ Delay:
6492 01:24:19.865853 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6493 01:24:19.869264 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6494 01:24:19.872426 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6495 01:24:19.875752 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6496 01:24:19.875859
6497 01:24:19.875952
6498 01:24:19.876041 ==
6499 01:24:19.879285 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 01:24:19.882524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 01:24:19.882632 ==
6502 01:24:19.882725
6503 01:24:19.882813
6504 01:24:19.885839 TX Vref Scan disable
6505 01:24:19.889143 == TX Byte 0 ==
6506 01:24:19.892866 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6507 01:24:19.895610 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6508 01:24:19.895719 == TX Byte 1 ==
6509 01:24:19.902297 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 01:24:19.905910 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 01:24:19.906020 ==
6512 01:24:19.908925 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 01:24:19.912554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 01:24:19.912671 ==
6515 01:24:19.912766
6516 01:24:19.912855
6517 01:24:19.915913 TX Vref Scan disable
6518 01:24:19.919284 == TX Byte 0 ==
6519 01:24:19.922367 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6520 01:24:19.925836 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6521 01:24:19.925947 == TX Byte 1 ==
6522 01:24:19.932215 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 01:24:19.936109 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 01:24:19.936244
6525 01:24:19.936362 [DATLAT]
6526 01:24:19.938800 Freq=400, CH0 RK1
6527 01:24:19.938935
6528 01:24:19.939027 DATLAT Default: 0xe
6529 01:24:19.942295 0, 0xFFFF, sum = 0
6530 01:24:19.942398 1, 0xFFFF, sum = 0
6531 01:24:19.945569 2, 0xFFFF, sum = 0
6532 01:24:19.945750 3, 0xFFFF, sum = 0
6533 01:24:19.948975 4, 0xFFFF, sum = 0
6534 01:24:19.949082 5, 0xFFFF, sum = 0
6535 01:24:19.952778 6, 0xFFFF, sum = 0
6536 01:24:19.952878 7, 0xFFFF, sum = 0
6537 01:24:19.955996 8, 0xFFFF, sum = 0
6538 01:24:19.959215 9, 0xFFFF, sum = 0
6539 01:24:19.959306 10, 0xFFFF, sum = 0
6540 01:24:19.962330 11, 0xFFFF, sum = 0
6541 01:24:19.962425 12, 0xFFFF, sum = 0
6542 01:24:19.965856 13, 0x0, sum = 1
6543 01:24:19.965968 14, 0x0, sum = 2
6544 01:24:19.969493 15, 0x0, sum = 3
6545 01:24:19.969617 16, 0x0, sum = 4
6546 01:24:19.969710 best_step = 14
6547 01:24:19.969807
6548 01:24:19.972474 ==
6549 01:24:19.976105 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 01:24:19.979261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 01:24:19.979348 ==
6552 01:24:19.979423 RX Vref Scan: 0
6553 01:24:19.979551
6554 01:24:19.982551 RX Vref 0 -> 0, step: 1
6555 01:24:19.982639
6556 01:24:19.985769 RX Delay -343 -> 252, step: 8
6557 01:24:19.992894 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6558 01:24:19.996043 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6559 01:24:20.000004 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6560 01:24:20.002882 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6561 01:24:20.009731 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6562 01:24:20.013537 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6563 01:24:20.016067 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6564 01:24:20.019824 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6565 01:24:20.026213 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6566 01:24:20.029567 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6567 01:24:20.033068 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6568 01:24:20.036499 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6569 01:24:20.043044 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6570 01:24:20.046084 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6571 01:24:20.049447 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6572 01:24:20.052841 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6573 01:24:20.056359 ==
6574 01:24:20.056466 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 01:24:20.063199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 01:24:20.063317 ==
6577 01:24:20.063410 DQS Delay:
6578 01:24:20.066469 DQS0 = 48, DQS1 = 60
6579 01:24:20.066576 DQM Delay:
6580 01:24:20.069942 DQM0 = 14, DQM1 = 14
6581 01:24:20.070056 DQ Delay:
6582 01:24:20.073078 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6583 01:24:20.076409 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6584 01:24:20.076511 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =4
6585 01:24:20.083730 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =24
6586 01:24:20.083840
6587 01:24:20.083931
6588 01:24:20.090107 [DQSOSCAuto] RK1, (LSB)MR18= 0x9a6b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6589 01:24:20.093086 CH0 RK1: MR19=C0C, MR18=9A6B
6590 01:24:20.099921 CH0_RK1: MR19=0xC0C, MR18=0x9A6B, DQSOSC=390, MR23=63, INC=388, DEC=258
6591 01:24:20.103171 [RxdqsGatingPostProcess] freq 400
6592 01:24:20.106811 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6593 01:24:20.110387 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 01:24:20.113193 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 01:24:20.116867 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 01:24:20.120262 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 01:24:20.123661 best DQS0 dly(2T, 0.5T) = (0, 10)
6598 01:24:20.126879 best DQS1 dly(2T, 0.5T) = (0, 10)
6599 01:24:20.130164 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6600 01:24:20.133531 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6601 01:24:20.136784 Pre-setting of DQS Precalculation
6602 01:24:20.140109 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6603 01:24:20.140197 ==
6604 01:24:20.143307 Dram Type= 6, Freq= 0, CH_1, rank 0
6605 01:24:20.146747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 01:24:20.150095 ==
6607 01:24:20.153693 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6608 01:24:20.160008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6609 01:24:20.163348 [CA 0] Center 36 (8~64) winsize 57
6610 01:24:20.166627 [CA 1] Center 36 (8~64) winsize 57
6611 01:24:20.169959 [CA 2] Center 36 (8~64) winsize 57
6612 01:24:20.173561 [CA 3] Center 36 (8~64) winsize 57
6613 01:24:20.176834 [CA 4] Center 36 (8~64) winsize 57
6614 01:24:20.179866 [CA 5] Center 36 (8~64) winsize 57
6615 01:24:20.179941
6616 01:24:20.183366 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6617 01:24:20.183481
6618 01:24:20.186861 [CATrainingPosCal] consider 1 rank data
6619 01:24:20.190099 u2DelayCellTimex100 = 270/100 ps
6620 01:24:20.193415 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 01:24:20.196810 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 01:24:20.200030 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 01:24:20.203646 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 01:24:20.206802 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 01:24:20.210375 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 01:24:20.210458
6627 01:24:20.213350 CA PerBit enable=1, Macro0, CA PI delay=36
6628 01:24:20.213428
6629 01:24:20.216827 [CBTSetCACLKResult] CA Dly = 36
6630 01:24:20.219865 CS Dly: 1 (0~32)
6631 01:24:20.219939 ==
6632 01:24:20.223356 Dram Type= 6, Freq= 0, CH_1, rank 1
6633 01:24:20.226642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 01:24:20.226723 ==
6635 01:24:20.233916 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6636 01:24:20.240430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6637 01:24:20.243487 [CA 0] Center 36 (8~64) winsize 57
6638 01:24:20.243599 [CA 1] Center 36 (8~64) winsize 57
6639 01:24:20.246915 [CA 2] Center 36 (8~64) winsize 57
6640 01:24:20.250009 [CA 3] Center 36 (8~64) winsize 57
6641 01:24:20.253688 [CA 4] Center 36 (8~64) winsize 57
6642 01:24:20.256786 [CA 5] Center 36 (8~64) winsize 57
6643 01:24:20.256877
6644 01:24:20.260288 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6645 01:24:20.260375
6646 01:24:20.263432 [CATrainingPosCal] consider 2 rank data
6647 01:24:20.266627 u2DelayCellTimex100 = 270/100 ps
6648 01:24:20.270145 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 01:24:20.276845 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 01:24:20.279961 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 01:24:20.283622 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 01:24:20.286814 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 01:24:20.290228 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 01:24:20.290311
6655 01:24:20.293443 CA PerBit enable=1, Macro0, CA PI delay=36
6656 01:24:20.293526
6657 01:24:20.297234 [CBTSetCACLKResult] CA Dly = 36
6658 01:24:20.297316 CS Dly: 1 (0~32)
6659 01:24:20.297380
6660 01:24:20.300081 ----->DramcWriteLeveling(PI) begin...
6661 01:24:20.303590 ==
6662 01:24:20.303672 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 01:24:20.310495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 01:24:20.310580 ==
6665 01:24:20.314077 Write leveling (Byte 0): 40 => 8
6666 01:24:20.317437 Write leveling (Byte 1): 40 => 8
6667 01:24:20.317521 DramcWriteLeveling(PI) end<-----
6668 01:24:20.317586
6669 01:24:20.320198 ==
6670 01:24:20.323640 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 01:24:20.327081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 01:24:20.327166 ==
6673 01:24:20.330388 [Gating] SW mode calibration
6674 01:24:20.336871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6675 01:24:20.340462 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6676 01:24:20.347068 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6677 01:24:20.350151 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6678 01:24:20.353590 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 01:24:20.360516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 01:24:20.363745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 01:24:20.367195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 01:24:20.373364 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 01:24:20.377054 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 01:24:20.380541 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 01:24:20.383709 Total UI for P1: 0, mck2ui 16
6686 01:24:20.387009 best dqsien dly found for B0: ( 0, 14, 24)
6687 01:24:20.390238 Total UI for P1: 0, mck2ui 16
6688 01:24:20.393766 best dqsien dly found for B1: ( 0, 14, 24)
6689 01:24:20.397174 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6690 01:24:20.400171 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6691 01:24:20.400254
6692 01:24:20.403801 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6693 01:24:20.410287 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6694 01:24:20.410371 [Gating] SW calibration Done
6695 01:24:20.413548 ==
6696 01:24:20.413631 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 01:24:20.420110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 01:24:20.420201 ==
6699 01:24:20.420266 RX Vref Scan: 0
6700 01:24:20.420326
6701 01:24:20.423506 RX Vref 0 -> 0, step: 1
6702 01:24:20.423588
6703 01:24:20.426996 RX Delay -410 -> 252, step: 16
6704 01:24:20.430489 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6705 01:24:20.433675 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6706 01:24:20.440061 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6707 01:24:20.443469 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6708 01:24:20.446945 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6709 01:24:20.450095 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6710 01:24:20.456968 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6711 01:24:20.460184 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6712 01:24:20.463395 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6713 01:24:20.467091 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6714 01:24:20.473440 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6715 01:24:20.477294 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6716 01:24:20.480416 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6717 01:24:20.483751 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6718 01:24:20.490119 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6719 01:24:20.493465 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6720 01:24:20.493551 ==
6721 01:24:20.497514 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 01:24:20.500389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 01:24:20.500472 ==
6724 01:24:20.503673 DQS Delay:
6725 01:24:20.503757 DQS0 = 51, DQS1 = 59
6726 01:24:20.503821 DQM Delay:
6727 01:24:20.507198 DQM0 = 19, DQM1 = 17
6728 01:24:20.507286 DQ Delay:
6729 01:24:20.510517 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6730 01:24:20.513902 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6731 01:24:20.517088 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6732 01:24:20.520808 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6733 01:24:20.520890
6734 01:24:20.520974
6735 01:24:20.521061 ==
6736 01:24:20.523513 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 01:24:20.530421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 01:24:20.530502 ==
6739 01:24:20.530594
6740 01:24:20.530669
6741 01:24:20.530745 TX Vref Scan disable
6742 01:24:20.533620 == TX Byte 0 ==
6743 01:24:20.537036 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 01:24:20.540714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 01:24:20.543756 == TX Byte 1 ==
6746 01:24:20.547507 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 01:24:20.551022 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 01:24:20.551106 ==
6749 01:24:20.553785 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 01:24:20.557401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 01:24:20.561023 ==
6752 01:24:20.561107
6753 01:24:20.561171
6754 01:24:20.561231 TX Vref Scan disable
6755 01:24:20.564311 == TX Byte 0 ==
6756 01:24:20.567892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 01:24:20.570652 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 01:24:20.574216 == TX Byte 1 ==
6759 01:24:20.577226 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 01:24:20.580531 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 01:24:20.580631
6762 01:24:20.580717 [DATLAT]
6763 01:24:20.584479 Freq=400, CH1 RK0
6764 01:24:20.584577
6765 01:24:20.587387 DATLAT Default: 0xf
6766 01:24:20.587458 0, 0xFFFF, sum = 0
6767 01:24:20.590735 1, 0xFFFF, sum = 0
6768 01:24:20.590808 2, 0xFFFF, sum = 0
6769 01:24:20.594174 3, 0xFFFF, sum = 0
6770 01:24:20.594249 4, 0xFFFF, sum = 0
6771 01:24:20.597503 5, 0xFFFF, sum = 0
6772 01:24:20.597583 6, 0xFFFF, sum = 0
6773 01:24:20.600571 7, 0xFFFF, sum = 0
6774 01:24:20.600688 8, 0xFFFF, sum = 0
6775 01:24:20.604567 9, 0xFFFF, sum = 0
6776 01:24:20.604688 10, 0xFFFF, sum = 0
6777 01:24:20.607555 11, 0xFFFF, sum = 0
6778 01:24:20.607633 12, 0xFFFF, sum = 0
6779 01:24:20.610852 13, 0x0, sum = 1
6780 01:24:20.610934 14, 0x0, sum = 2
6781 01:24:20.613890 15, 0x0, sum = 3
6782 01:24:20.614002 16, 0x0, sum = 4
6783 01:24:20.617649 best_step = 14
6784 01:24:20.617733
6785 01:24:20.617799 ==
6786 01:24:20.620842 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 01:24:20.624126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 01:24:20.624243 ==
6789 01:24:20.624350 RX Vref Scan: 1
6790 01:24:20.627509
6791 01:24:20.627624 RX Vref 0 -> 0, step: 1
6792 01:24:20.627743
6793 01:24:20.631015 RX Delay -359 -> 252, step: 8
6794 01:24:20.631133
6795 01:24:20.634517 Set Vref, RX VrefLevel [Byte0]: 59
6796 01:24:20.637281 [Byte1]: 53
6797 01:24:20.642155
6798 01:24:20.642306 Final RX Vref Byte 0 = 59 to rank0
6799 01:24:20.645320 Final RX Vref Byte 1 = 53 to rank0
6800 01:24:20.648858 Final RX Vref Byte 0 = 59 to rank1
6801 01:24:20.651836 Final RX Vref Byte 1 = 53 to rank1==
6802 01:24:20.655045 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 01:24:20.658375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 01:24:20.661898 ==
6805 01:24:20.662016 DQS Delay:
6806 01:24:20.662110 DQS0 = 48, DQS1 = 60
6807 01:24:20.665281 DQM Delay:
6808 01:24:20.665365 DQM0 = 12, DQM1 = 13
6809 01:24:20.668447 DQ Delay:
6810 01:24:20.672088 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6811 01:24:20.672188 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6812 01:24:20.675160 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6813 01:24:20.678458 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6814 01:24:20.678535
6815 01:24:20.678597
6816 01:24:20.688481 [DQSOSCAuto] RK0, (LSB)MR18= 0x8930, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6817 01:24:20.691645 CH1 RK0: MR19=C0C, MR18=8930
6818 01:24:20.698724 CH1_RK0: MR19=0xC0C, MR18=0x8930, DQSOSC=392, MR23=63, INC=384, DEC=256
6819 01:24:20.698837 ==
6820 01:24:20.702061 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 01:24:20.705512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 01:24:20.705604 ==
6823 01:24:20.708904 [Gating] SW mode calibration
6824 01:24:20.715254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6825 01:24:20.718937 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6826 01:24:20.725381 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6827 01:24:20.728893 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6828 01:24:20.732260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 01:24:20.738470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 01:24:20.742414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 01:24:20.745347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 01:24:20.752346 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 01:24:20.755429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 01:24:20.758618 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 01:24:20.761967 Total UI for P1: 0, mck2ui 16
6836 01:24:20.765279 best dqsien dly found for B0: ( 0, 14, 24)
6837 01:24:20.768625 Total UI for P1: 0, mck2ui 16
6838 01:24:20.772185 best dqsien dly found for B1: ( 0, 14, 24)
6839 01:24:20.775649 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6840 01:24:20.779065 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6841 01:24:20.779168
6842 01:24:20.781784 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6843 01:24:20.788553 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6844 01:24:20.788641 [Gating] SW calibration Done
6845 01:24:20.792000 ==
6846 01:24:20.792085 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 01:24:20.798422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 01:24:20.798523 ==
6849 01:24:20.798589 RX Vref Scan: 0
6850 01:24:20.798650
6851 01:24:20.802545 RX Vref 0 -> 0, step: 1
6852 01:24:20.802648
6853 01:24:20.805227 RX Delay -410 -> 252, step: 16
6854 01:24:20.808570 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6855 01:24:20.812246 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6856 01:24:20.818977 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6857 01:24:20.822377 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6858 01:24:20.825588 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6859 01:24:20.829119 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6860 01:24:20.835326 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6861 01:24:20.839030 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6862 01:24:20.842572 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6863 01:24:20.846011 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6864 01:24:20.852343 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6865 01:24:20.855905 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6866 01:24:20.858611 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6867 01:24:20.862480 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6868 01:24:20.868605 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6869 01:24:20.872341 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6870 01:24:20.872425 ==
6871 01:24:20.875519 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 01:24:20.879103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 01:24:20.879187 ==
6874 01:24:20.882167 DQS Delay:
6875 01:24:20.882250 DQS0 = 43, DQS1 = 59
6876 01:24:20.882314 DQM Delay:
6877 01:24:20.885662 DQM0 = 10, DQM1 = 20
6878 01:24:20.885744 DQ Delay:
6879 01:24:20.889034 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6880 01:24:20.892917 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6881 01:24:20.895573 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6882 01:24:20.898975 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6883 01:24:20.899058
6884 01:24:20.899122
6885 01:24:20.899182 ==
6886 01:24:20.902445 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 01:24:20.905677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 01:24:20.905781 ==
6889 01:24:20.905875
6890 01:24:20.909384
6891 01:24:20.909458 TX Vref Scan disable
6892 01:24:20.912546 == TX Byte 0 ==
6893 01:24:20.915926 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6894 01:24:20.919308 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6895 01:24:20.922604 == TX Byte 1 ==
6896 01:24:20.925619 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6897 01:24:20.929166 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6898 01:24:20.929269 ==
6899 01:24:20.932397 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 01:24:20.935491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 01:24:20.935590 ==
6902 01:24:20.935711
6903 01:24:20.938926
6904 01:24:20.939029 TX Vref Scan disable
6905 01:24:20.942582 == TX Byte 0 ==
6906 01:24:20.946144 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6907 01:24:20.948777 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6908 01:24:20.952571 == TX Byte 1 ==
6909 01:24:20.955659 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6910 01:24:20.958972 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6911 01:24:20.959081
6912 01:24:20.959173 [DATLAT]
6913 01:24:20.962369 Freq=400, CH1 RK1
6914 01:24:20.962476
6915 01:24:20.962570 DATLAT Default: 0xe
6916 01:24:20.965763 0, 0xFFFF, sum = 0
6917 01:24:20.965846 1, 0xFFFF, sum = 0
6918 01:24:20.968807 2, 0xFFFF, sum = 0
6919 01:24:20.972141 3, 0xFFFF, sum = 0
6920 01:24:20.972218 4, 0xFFFF, sum = 0
6921 01:24:20.975748 5, 0xFFFF, sum = 0
6922 01:24:20.975853 6, 0xFFFF, sum = 0
6923 01:24:20.978939 7, 0xFFFF, sum = 0
6924 01:24:20.979042 8, 0xFFFF, sum = 0
6925 01:24:20.982825 9, 0xFFFF, sum = 0
6926 01:24:20.982926 10, 0xFFFF, sum = 0
6927 01:24:20.985705 11, 0xFFFF, sum = 0
6928 01:24:20.985790 12, 0xFFFF, sum = 0
6929 01:24:20.988823 13, 0x0, sum = 1
6930 01:24:20.988928 14, 0x0, sum = 2
6931 01:24:20.992593 15, 0x0, sum = 3
6932 01:24:20.992720 16, 0x0, sum = 4
6933 01:24:20.992806 best_step = 14
6934 01:24:20.995689
6935 01:24:20.995764 ==
6936 01:24:20.998925 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 01:24:21.002413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 01:24:21.002512 ==
6939 01:24:21.002606 RX Vref Scan: 0
6940 01:24:21.002681
6941 01:24:21.005801 RX Vref 0 -> 0, step: 1
6942 01:24:21.005899
6943 01:24:21.008891 RX Delay -359 -> 252, step: 8
6944 01:24:21.016471 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6945 01:24:21.019589 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6946 01:24:21.022749 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6947 01:24:21.026622 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6948 01:24:21.032884 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6949 01:24:21.036350 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6950 01:24:21.039876 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6951 01:24:21.042933 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6952 01:24:21.050213 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6953 01:24:21.052788 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6954 01:24:21.056079 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6955 01:24:21.059380 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6956 01:24:21.066458 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6957 01:24:21.069949 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6958 01:24:21.072816 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6959 01:24:21.076202 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6960 01:24:21.079852 ==
6961 01:24:21.082996 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 01:24:21.086400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 01:24:21.086499 ==
6964 01:24:21.086595 DQS Delay:
6965 01:24:21.089617 DQS0 = 52, DQS1 = 56
6966 01:24:21.089715 DQM Delay:
6967 01:24:21.093029 DQM0 = 13, DQM1 = 9
6968 01:24:21.093141 DQ Delay:
6969 01:24:21.096285 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6970 01:24:21.099659 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6971 01:24:21.102821 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6972 01:24:21.106159 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6973 01:24:21.106262
6974 01:24:21.106359
6975 01:24:21.113138 [DQSOSCAuto] RK1, (LSB)MR18= 0x798e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
6976 01:24:21.116792 CH1 RK1: MR19=C0C, MR18=798E
6977 01:24:21.123357 CH1_RK1: MR19=0xC0C, MR18=0x798E, DQSOSC=392, MR23=63, INC=384, DEC=256
6978 01:24:21.126389 [RxdqsGatingPostProcess] freq 400
6979 01:24:21.129708 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6980 01:24:21.133087 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 01:24:21.136383 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 01:24:21.139565 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 01:24:21.143034 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 01:24:21.146745 best DQS0 dly(2T, 0.5T) = (0, 10)
6985 01:24:21.150481 best DQS1 dly(2T, 0.5T) = (0, 10)
6986 01:24:21.153153 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6987 01:24:21.157050 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6988 01:24:21.160075 Pre-setting of DQS Precalculation
6989 01:24:21.163743 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6990 01:24:21.170052 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6991 01:24:21.176824 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6992 01:24:21.179944
6993 01:24:21.180045
6994 01:24:21.180109 [Calibration Summary] 800 Mbps
6995 01:24:21.183453 CH 0, Rank 0
6996 01:24:21.183550 SW Impedance : PASS
6997 01:24:21.186593 DUTY Scan : NO K
6998 01:24:21.190138 ZQ Calibration : PASS
6999 01:24:21.190236 Jitter Meter : NO K
7000 01:24:21.193386 CBT Training : PASS
7001 01:24:21.196637 Write leveling : PASS
7002 01:24:21.196779 RX DQS gating : PASS
7003 01:24:21.200016 RX DQ/DQS(RDDQC) : PASS
7004 01:24:21.203533 TX DQ/DQS : PASS
7005 01:24:21.203633 RX DATLAT : PASS
7006 01:24:21.206985 RX DQ/DQS(Engine): PASS
7007 01:24:21.209793 TX OE : NO K
7008 01:24:21.209892 All Pass.
7009 01:24:21.209987
7010 01:24:21.210060 CH 0, Rank 1
7011 01:24:21.213381 SW Impedance : PASS
7012 01:24:21.216792 DUTY Scan : NO K
7013 01:24:21.216891 ZQ Calibration : PASS
7014 01:24:21.220095 Jitter Meter : NO K
7015 01:24:21.220193 CBT Training : PASS
7016 01:24:21.223618 Write leveling : NO K
7017 01:24:21.227047 RX DQS gating : PASS
7018 01:24:21.227130 RX DQ/DQS(RDDQC) : PASS
7019 01:24:21.230299 TX DQ/DQS : PASS
7020 01:24:21.233845 RX DATLAT : PASS
7021 01:24:21.233942 RX DQ/DQS(Engine): PASS
7022 01:24:21.236873 TX OE : NO K
7023 01:24:21.236971 All Pass.
7024 01:24:21.237064
7025 01:24:21.240479 CH 1, Rank 0
7026 01:24:21.240577 SW Impedance : PASS
7027 01:24:21.243595 DUTY Scan : NO K
7028 01:24:21.247289 ZQ Calibration : PASS
7029 01:24:21.247374 Jitter Meter : NO K
7030 01:24:21.250177 CBT Training : PASS
7031 01:24:21.253442 Write leveling : PASS
7032 01:24:21.253540 RX DQS gating : PASS
7033 01:24:21.256840 RX DQ/DQS(RDDQC) : PASS
7034 01:24:21.256952 TX DQ/DQS : PASS
7035 01:24:21.260225 RX DATLAT : PASS
7036 01:24:21.263470 RX DQ/DQS(Engine): PASS
7037 01:24:21.263581 TX OE : NO K
7038 01:24:21.266943 All Pass.
7039 01:24:21.267040
7040 01:24:21.267135 CH 1, Rank 1
7041 01:24:21.270530 SW Impedance : PASS
7042 01:24:21.270629 DUTY Scan : NO K
7043 01:24:21.273550 ZQ Calibration : PASS
7044 01:24:21.277257 Jitter Meter : NO K
7045 01:24:21.277355 CBT Training : PASS
7046 01:24:21.280175 Write leveling : NO K
7047 01:24:21.284076 RX DQS gating : PASS
7048 01:24:21.284174 RX DQ/DQS(RDDQC) : PASS
7049 01:24:21.286891 TX DQ/DQS : PASS
7050 01:24:21.286975 RX DATLAT : PASS
7051 01:24:21.290370 RX DQ/DQS(Engine): PASS
7052 01:24:21.293763 TX OE : NO K
7053 01:24:21.293861 All Pass.
7054 01:24:21.293955
7055 01:24:21.297060 DramC Write-DBI off
7056 01:24:21.300087 PER_BANK_REFRESH: Hybrid Mode
7057 01:24:21.300168 TX_TRACKING: ON
7058 01:24:21.310530 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7059 01:24:21.313884 [FAST_K] Save calibration result to emmc
7060 01:24:21.316601 dramc_set_vcore_voltage set vcore to 725000
7061 01:24:21.320301 Read voltage for 1600, 0
7062 01:24:21.320398 Vio18 = 0
7063 01:24:21.320463 Vcore = 725000
7064 01:24:21.323523 Vdram = 0
7065 01:24:21.323620 Vddq = 0
7066 01:24:21.323713 Vmddr = 0
7067 01:24:21.330149 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7068 01:24:21.333322 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7069 01:24:21.336565 MEM_TYPE=3, freq_sel=13
7070 01:24:21.340011 sv_algorithm_assistance_LP4_3733
7071 01:24:21.344066 ============ PULL DRAM RESETB DOWN ============
7072 01:24:21.346919 ========== PULL DRAM RESETB DOWN end =========
7073 01:24:21.353507 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7074 01:24:21.356894 ===================================
7075 01:24:21.357006 LPDDR4 DRAM CONFIGURATION
7076 01:24:21.359857 ===================================
7077 01:24:21.363322 EX_ROW_EN[0] = 0x0
7078 01:24:21.367151 EX_ROW_EN[1] = 0x0
7079 01:24:21.367248 LP4Y_EN = 0x0
7080 01:24:21.370056 WORK_FSP = 0x1
7081 01:24:21.370138 WL = 0x5
7082 01:24:21.373864 RL = 0x5
7083 01:24:21.373962 BL = 0x2
7084 01:24:21.376891 RPST = 0x0
7085 01:24:21.376989 RD_PRE = 0x0
7086 01:24:21.380109 WR_PRE = 0x1
7087 01:24:21.380207 WR_PST = 0x1
7088 01:24:21.383332 DBI_WR = 0x0
7089 01:24:21.383431 DBI_RD = 0x0
7090 01:24:21.387026 OTF = 0x1
7091 01:24:21.390244 ===================================
7092 01:24:21.393651 ===================================
7093 01:24:21.393749 ANA top config
7094 01:24:21.397078 ===================================
7095 01:24:21.400265 DLL_ASYNC_EN = 0
7096 01:24:21.403483 ALL_SLAVE_EN = 0
7097 01:24:21.403581 NEW_RANK_MODE = 1
7098 01:24:21.407029 DLL_IDLE_MODE = 1
7099 01:24:21.410122 LP45_APHY_COMB_EN = 1
7100 01:24:21.413716 TX_ODT_DIS = 0
7101 01:24:21.413797 NEW_8X_MODE = 1
7102 01:24:21.417035 ===================================
7103 01:24:21.420074 ===================================
7104 01:24:21.423671 data_rate = 3200
7105 01:24:21.426836 CKR = 1
7106 01:24:21.430249 DQ_P2S_RATIO = 8
7107 01:24:21.433848 ===================================
7108 01:24:21.437087 CA_P2S_RATIO = 8
7109 01:24:21.440384 DQ_CA_OPEN = 0
7110 01:24:21.440466 DQ_SEMI_OPEN = 0
7111 01:24:21.443439 CA_SEMI_OPEN = 0
7112 01:24:21.447175 CA_FULL_RATE = 0
7113 01:24:21.450109 DQ_CKDIV4_EN = 0
7114 01:24:21.453799 CA_CKDIV4_EN = 0
7115 01:24:21.457074 CA_PREDIV_EN = 0
7116 01:24:21.457158 PH8_DLY = 12
7117 01:24:21.460232 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7118 01:24:21.463599 DQ_AAMCK_DIV = 4
7119 01:24:21.467201 CA_AAMCK_DIV = 4
7120 01:24:21.470314 CA_ADMCK_DIV = 4
7121 01:24:21.473564 DQ_TRACK_CA_EN = 0
7122 01:24:21.473648 CA_PICK = 1600
7123 01:24:21.476805 CA_MCKIO = 1600
7124 01:24:21.480670 MCKIO_SEMI = 0
7125 01:24:21.483703 PLL_FREQ = 3068
7126 01:24:21.487027 DQ_UI_PI_RATIO = 32
7127 01:24:21.490229 CA_UI_PI_RATIO = 0
7128 01:24:21.493684 ===================================
7129 01:24:21.496990 ===================================
7130 01:24:21.500359 memory_type:LPDDR4
7131 01:24:21.500436 GP_NUM : 10
7132 01:24:21.503781 SRAM_EN : 1
7133 01:24:21.503883 MD32_EN : 0
7134 01:24:21.507227 ===================================
7135 01:24:21.510254 [ANA_INIT] >>>>>>>>>>>>>>
7136 01:24:21.513759 <<<<<< [CONFIGURE PHASE]: ANA_TX
7137 01:24:21.517096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7138 01:24:21.520494 ===================================
7139 01:24:21.523931 data_rate = 3200,PCW = 0X7600
7140 01:24:21.527268 ===================================
7141 01:24:21.530183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7142 01:24:21.533484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7143 01:24:21.540253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7144 01:24:21.543711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7145 01:24:21.547096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7146 01:24:21.550386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7147 01:24:21.553608 [ANA_INIT] flow start
7148 01:24:21.557641 [ANA_INIT] PLL >>>>>>>>
7149 01:24:21.557732 [ANA_INIT] PLL <<<<<<<<
7150 01:24:21.560599 [ANA_INIT] MIDPI >>>>>>>>
7151 01:24:21.563770 [ANA_INIT] MIDPI <<<<<<<<
7152 01:24:21.563855 [ANA_INIT] DLL >>>>>>>>
7153 01:24:21.567478 [ANA_INIT] DLL <<<<<<<<
7154 01:24:21.570987 [ANA_INIT] flow end
7155 01:24:21.574284 ============ LP4 DIFF to SE enter ============
7156 01:24:21.577136 ============ LP4 DIFF to SE exit ============
7157 01:24:21.580658 [ANA_INIT] <<<<<<<<<<<<<
7158 01:24:21.583934 [Flow] Enable top DCM control >>>>>
7159 01:24:21.587513 [Flow] Enable top DCM control <<<<<
7160 01:24:21.590926 Enable DLL master slave shuffle
7161 01:24:21.593949 ==============================================================
7162 01:24:21.597755 Gating Mode config
7163 01:24:21.604624 ==============================================================
7164 01:24:21.604746 Config description:
7165 01:24:21.613947 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7166 01:24:21.620563 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7167 01:24:21.624296 SELPH_MODE 0: By rank 1: By Phase
7168 01:24:21.631134 ==============================================================
7169 01:24:21.634422 GAT_TRACK_EN = 1
7170 01:24:21.637547 RX_GATING_MODE = 2
7171 01:24:21.640975 RX_GATING_TRACK_MODE = 2
7172 01:24:21.644539 SELPH_MODE = 1
7173 01:24:21.647754 PICG_EARLY_EN = 1
7174 01:24:21.647833 VALID_LAT_VALUE = 1
7175 01:24:21.654464 ==============================================================
7176 01:24:21.657551 Enter into Gating configuration >>>>
7177 01:24:21.660791 Exit from Gating configuration <<<<
7178 01:24:21.664456 Enter into DVFS_PRE_config >>>>>
7179 01:24:21.674344 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7180 01:24:21.677446 Exit from DVFS_PRE_config <<<<<
7181 01:24:21.681074 Enter into PICG configuration >>>>
7182 01:24:21.684344 Exit from PICG configuration <<<<
7183 01:24:21.687500 [RX_INPUT] configuration >>>>>
7184 01:24:21.691289 [RX_INPUT] configuration <<<<<
7185 01:24:21.697397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7186 01:24:21.701204 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7187 01:24:21.707985 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 01:24:21.714262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 01:24:21.721111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7190 01:24:21.727564 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7191 01:24:21.730741 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7192 01:24:21.734075 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7193 01:24:21.737182 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7194 01:24:21.740919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7195 01:24:21.747347 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7196 01:24:21.750863 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 01:24:21.754235 ===================================
7198 01:24:21.757885 LPDDR4 DRAM CONFIGURATION
7199 01:24:21.760736 ===================================
7200 01:24:21.760815 EX_ROW_EN[0] = 0x0
7201 01:24:21.764080 EX_ROW_EN[1] = 0x0
7202 01:24:21.764187 LP4Y_EN = 0x0
7203 01:24:21.767330 WORK_FSP = 0x1
7204 01:24:21.767444 WL = 0x5
7205 01:24:21.770811 RL = 0x5
7206 01:24:21.770891 BL = 0x2
7207 01:24:21.774417 RPST = 0x0
7208 01:24:21.774551 RD_PRE = 0x0
7209 01:24:21.777527 WR_PRE = 0x1
7210 01:24:21.777598 WR_PST = 0x1
7211 01:24:21.781486 DBI_WR = 0x0
7212 01:24:21.781594 DBI_RD = 0x0
7213 01:24:21.784531 OTF = 0x1
7214 01:24:21.787468 ===================================
7215 01:24:21.790879 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7216 01:24:21.794658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7217 01:24:21.801275 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7218 01:24:21.805085 ===================================
7219 01:24:21.805194 LPDDR4 DRAM CONFIGURATION
7220 01:24:21.807825 ===================================
7221 01:24:21.811121 EX_ROW_EN[0] = 0x10
7222 01:24:21.814335 EX_ROW_EN[1] = 0x0
7223 01:24:21.814455 LP4Y_EN = 0x0
7224 01:24:21.817968 WORK_FSP = 0x1
7225 01:24:21.818052 WL = 0x5
7226 01:24:21.821538 RL = 0x5
7227 01:24:21.821615 BL = 0x2
7228 01:24:21.824466 RPST = 0x0
7229 01:24:21.824539 RD_PRE = 0x0
7230 01:24:21.827957 WR_PRE = 0x1
7231 01:24:21.828107 WR_PST = 0x1
7232 01:24:21.831208 DBI_WR = 0x0
7233 01:24:21.831284 DBI_RD = 0x0
7234 01:24:21.834641 OTF = 0x1
7235 01:24:21.837936 ===================================
7236 01:24:21.844832 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7237 01:24:21.844952 ==
7238 01:24:21.847830 Dram Type= 6, Freq= 0, CH_0, rank 0
7239 01:24:21.851688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7240 01:24:21.851773 ==
7241 01:24:21.855184 [Duty_Offset_Calibration]
7242 01:24:21.855284 B0:2 B1:-1 CA:1
7243 01:24:21.855372
7244 01:24:21.858209 [DutyScan_Calibration_Flow] k_type=0
7245 01:24:21.867821
7246 01:24:21.867923 ==CLK 0==
7247 01:24:21.871515 Final CLK duty delay cell = -4
7248 01:24:21.874032 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7249 01:24:21.877649 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7250 01:24:21.881136 [-4] AVG Duty = 4937%(X100)
7251 01:24:21.881214
7252 01:24:21.884247 CH0 CLK Duty spec in!! Max-Min= 187%
7253 01:24:21.887394 [DutyScan_Calibration_Flow] ====Done====
7254 01:24:21.887486
7255 01:24:21.890849 [DutyScan_Calibration_Flow] k_type=1
7256 01:24:21.906810
7257 01:24:21.906893 ==DQS 0 ==
7258 01:24:21.910340 Final DQS duty delay cell = 0
7259 01:24:21.913463 [0] MAX Duty = 5125%(X100), DQS PI = 20
7260 01:24:21.917015 [0] MIN Duty = 5031%(X100), DQS PI = 4
7261 01:24:21.917104 [0] AVG Duty = 5078%(X100)
7262 01:24:21.920503
7263 01:24:21.920607 ==DQS 1 ==
7264 01:24:21.923942 Final DQS duty delay cell = -4
7265 01:24:21.926900 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7266 01:24:21.930826 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7267 01:24:21.933762 [-4] AVG Duty = 5046%(X100)
7268 01:24:21.933849
7269 01:24:21.937274 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7270 01:24:21.937343
7271 01:24:21.940211 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7272 01:24:21.943737 [DutyScan_Calibration_Flow] ====Done====
7273 01:24:21.943845
7274 01:24:21.946787 [DutyScan_Calibration_Flow] k_type=3
7275 01:24:21.964356
7276 01:24:21.964478 ==DQM 0 ==
7277 01:24:21.967754 Final DQM duty delay cell = 0
7278 01:24:21.970698 [0] MAX Duty = 5000%(X100), DQS PI = 20
7279 01:24:21.974082 [0] MIN Duty = 4875%(X100), DQS PI = 6
7280 01:24:21.974184 [0] AVG Duty = 4937%(X100)
7281 01:24:21.977796
7282 01:24:21.977892 ==DQM 1 ==
7283 01:24:21.981179 Final DQM duty delay cell = 0
7284 01:24:21.984415 [0] MAX Duty = 5187%(X100), DQS PI = 58
7285 01:24:21.987824 [0] MIN Duty = 4969%(X100), DQS PI = 18
7286 01:24:21.987897 [0] AVG Duty = 5078%(X100)
7287 01:24:21.991222
7288 01:24:21.994123 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7289 01:24:21.994194
7290 01:24:21.997465 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7291 01:24:22.000676 [DutyScan_Calibration_Flow] ====Done====
7292 01:24:22.000834
7293 01:24:22.004275 [DutyScan_Calibration_Flow] k_type=2
7294 01:24:22.020588
7295 01:24:22.020702 ==DQ 0 ==
7296 01:24:22.023877 Final DQ duty delay cell = -4
7297 01:24:22.027137 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7298 01:24:22.030859 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7299 01:24:22.033704 [-4] AVG Duty = 4922%(X100)
7300 01:24:22.033782
7301 01:24:22.033844 ==DQ 1 ==
7302 01:24:22.037081 Final DQ duty delay cell = 0
7303 01:24:22.040357 [0] MAX Duty = 5031%(X100), DQS PI = 38
7304 01:24:22.043873 [0] MIN Duty = 4938%(X100), DQS PI = 8
7305 01:24:22.043959 [0] AVG Duty = 4984%(X100)
7306 01:24:22.047569
7307 01:24:22.050949 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7308 01:24:22.051051
7309 01:24:22.053840 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7310 01:24:22.057173 [DutyScan_Calibration_Flow] ====Done====
7311 01:24:22.057247 ==
7312 01:24:22.060571 Dram Type= 6, Freq= 0, CH_1, rank 0
7313 01:24:22.063814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7314 01:24:22.063914 ==
7315 01:24:22.067503 [Duty_Offset_Calibration]
7316 01:24:22.067608 B0:1 B1:1 CA:2
7317 01:24:22.067697
7318 01:24:22.070683 [DutyScan_Calibration_Flow] k_type=0
7319 01:24:22.081223
7320 01:24:22.081308 ==CLK 0==
7321 01:24:22.084234 Final CLK duty delay cell = 0
7322 01:24:22.087753 [0] MAX Duty = 5156%(X100), DQS PI = 24
7323 01:24:22.090802 [0] MIN Duty = 4969%(X100), DQS PI = 42
7324 01:24:22.090884 [0] AVG Duty = 5062%(X100)
7325 01:24:22.094126
7326 01:24:22.097658 CH1 CLK Duty spec in!! Max-Min= 187%
7327 01:24:22.101138 [DutyScan_Calibration_Flow] ====Done====
7328 01:24:22.101219
7329 01:24:22.104383 [DutyScan_Calibration_Flow] k_type=1
7330 01:24:22.121192
7331 01:24:22.121283 ==DQS 0 ==
7332 01:24:22.123947 Final DQS duty delay cell = 0
7333 01:24:22.127551 [0] MAX Duty = 5062%(X100), DQS PI = 20
7334 01:24:22.130843 [0] MIN Duty = 4813%(X100), DQS PI = 50
7335 01:24:22.130949 [0] AVG Duty = 4937%(X100)
7336 01:24:22.133767
7337 01:24:22.133846 ==DQS 1 ==
7338 01:24:22.137110 Final DQS duty delay cell = 0
7339 01:24:22.141206 [0] MAX Duty = 5062%(X100), DQS PI = 58
7340 01:24:22.143926 [0] MIN Duty = 4938%(X100), DQS PI = 12
7341 01:24:22.147230 [0] AVG Duty = 5000%(X100)
7342 01:24:22.147345
7343 01:24:22.150980 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7344 01:24:22.151060
7345 01:24:22.154221 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7346 01:24:22.157384 [DutyScan_Calibration_Flow] ====Done====
7347 01:24:22.157464
7348 01:24:22.160859 [DutyScan_Calibration_Flow] k_type=3
7349 01:24:22.177772
7350 01:24:22.177889 ==DQM 0 ==
7351 01:24:22.181356 Final DQM duty delay cell = 0
7352 01:24:22.184173 [0] MAX Duty = 5156%(X100), DQS PI = 22
7353 01:24:22.187363 [0] MIN Duty = 4813%(X100), DQS PI = 50
7354 01:24:22.190836 [0] AVG Duty = 4984%(X100)
7355 01:24:22.190954
7356 01:24:22.191049 ==DQM 1 ==
7357 01:24:22.194028 Final DQM duty delay cell = 0
7358 01:24:22.197316 [0] MAX Duty = 5125%(X100), DQS PI = 8
7359 01:24:22.200939 [0] MIN Duty = 4875%(X100), DQS PI = 20
7360 01:24:22.203843 [0] AVG Duty = 5000%(X100)
7361 01:24:22.203966
7362 01:24:22.207383 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7363 01:24:22.207460
7364 01:24:22.210585 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7365 01:24:22.213852 [DutyScan_Calibration_Flow] ====Done====
7366 01:24:22.213940
7367 01:24:22.217444 [DutyScan_Calibration_Flow] k_type=2
7368 01:24:22.234595
7369 01:24:22.234684 ==DQ 0 ==
7370 01:24:22.237841 Final DQ duty delay cell = 0
7371 01:24:22.241064 [0] MAX Duty = 5156%(X100), DQS PI = 20
7372 01:24:22.244335 [0] MIN Duty = 4907%(X100), DQS PI = 52
7373 01:24:22.244418 [0] AVG Duty = 5031%(X100)
7374 01:24:22.244517
7375 01:24:22.247962 ==DQ 1 ==
7376 01:24:22.251042 Final DQ duty delay cell = 0
7377 01:24:22.254989 [0] MAX Duty = 5093%(X100), DQS PI = 6
7378 01:24:22.257952 [0] MIN Duty = 5031%(X100), DQS PI = 0
7379 01:24:22.258035 [0] AVG Duty = 5062%(X100)
7380 01:24:22.258122
7381 01:24:22.261418 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7382 01:24:22.261502
7383 01:24:22.264784 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7384 01:24:22.268019 [DutyScan_Calibration_Flow] ====Done====
7385 01:24:22.273281 nWR fixed to 30
7386 01:24:22.276569 [ModeRegInit_LP4] CH0 RK0
7387 01:24:22.276672 [ModeRegInit_LP4] CH0 RK1
7388 01:24:22.279860 [ModeRegInit_LP4] CH1 RK0
7389 01:24:22.283600 [ModeRegInit_LP4] CH1 RK1
7390 01:24:22.283711 match AC timing 5
7391 01:24:22.289722 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7392 01:24:22.293595 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7393 01:24:22.296582 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7394 01:24:22.303148 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7395 01:24:22.306453 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7396 01:24:22.306537 [MiockJmeterHQA]
7397 01:24:22.306621
7398 01:24:22.309918 [DramcMiockJmeter] u1RxGatingPI = 0
7399 01:24:22.313053 0 : 4258, 4029
7400 01:24:22.313153 4 : 4363, 4138
7401 01:24:22.316646 8 : 4253, 4027
7402 01:24:22.316773 12 : 4252, 4027
7403 01:24:22.320009 16 : 4252, 4027
7404 01:24:22.320094 20 : 4255, 4029
7405 01:24:22.320179 24 : 4253, 4027
7406 01:24:22.323105 28 : 4363, 4138
7407 01:24:22.323189 32 : 4363, 4137
7408 01:24:22.326388 36 : 4255, 4029
7409 01:24:22.326475 40 : 4252, 4027
7410 01:24:22.329775 44 : 4253, 4026
7411 01:24:22.329860 48 : 4363, 4138
7412 01:24:22.333224 52 : 4252, 4027
7413 01:24:22.333308 56 : 4363, 4138
7414 01:24:22.333393 60 : 4249, 4027
7415 01:24:22.336604 64 : 4250, 4027
7416 01:24:22.336711 68 : 4250, 4027
7417 01:24:22.339662 72 : 4252, 4029
7418 01:24:22.339746 76 : 4360, 4138
7419 01:24:22.343061 80 : 4249, 4027
7420 01:24:22.343144 84 : 4361, 4137
7421 01:24:22.346453 88 : 4250, 4027
7422 01:24:22.346539 92 : 4250, 4027
7423 01:24:22.346639 96 : 4250, 3944
7424 01:24:22.349952 100 : 4361, 0
7425 01:24:22.350037 104 : 4253, 0
7426 01:24:22.353060 108 : 4250, 0
7427 01:24:22.353144 112 : 4361, 0
7428 01:24:22.353229 116 : 4360, 0
7429 01:24:22.356163 120 : 4363, 0
7430 01:24:22.356247 124 : 4250, 0
7431 01:24:22.359765 128 : 4360, 0
7432 01:24:22.359850 132 : 4360, 0
7433 01:24:22.359952 136 : 4252, 0
7434 01:24:22.363016 140 : 4249, 0
7435 01:24:22.363110 144 : 4250, 0
7436 01:24:22.363212 148 : 4252, 0
7437 01:24:22.366223 152 : 4252, 0
7438 01:24:22.366311 156 : 4250, 0
7439 01:24:22.370256 160 : 4252, 0
7440 01:24:22.370341 164 : 4363, 0
7441 01:24:22.370426 168 : 4360, 0
7442 01:24:22.373275 172 : 4250, 0
7443 01:24:22.373390 176 : 4253, 0
7444 01:24:22.376896 180 : 4360, 0
7445 01:24:22.376980 184 : 4360, 0
7446 01:24:22.377066 188 : 4253, 0
7447 01:24:22.380045 192 : 4252, 0
7448 01:24:22.380158 196 : 4250, 0
7449 01:24:22.380238 200 : 4252, 0
7450 01:24:22.383394 204 : 4253, 0
7451 01:24:22.383478 208 : 4250, 0
7452 01:24:22.386487 212 : 4253, 5
7453 01:24:22.386571 216 : 4363, 3130
7454 01:24:22.389871 220 : 4250, 4027
7455 01:24:22.389955 224 : 4250, 4026
7456 01:24:22.390040 228 : 4361, 4137
7457 01:24:22.393069 232 : 4363, 4138
7458 01:24:22.393153 236 : 4250, 4027
7459 01:24:22.396320 240 : 4363, 4140
7460 01:24:22.396403 244 : 4250, 4027
7461 01:24:22.399907 248 : 4250, 4027
7462 01:24:22.399992 252 : 4250, 4027
7463 01:24:22.403150 256 : 4252, 4029
7464 01:24:22.403234 260 : 4250, 4027
7465 01:24:22.406418 264 : 4250, 4027
7466 01:24:22.406502 268 : 4249, 4027
7467 01:24:22.409745 272 : 4252, 4029
7468 01:24:22.409829 276 : 4250, 4026
7469 01:24:22.413909 280 : 4361, 4137
7470 01:24:22.414007 284 : 4360, 4138
7471 01:24:22.414092 288 : 4250, 4027
7472 01:24:22.416733 292 : 4363, 4140
7473 01:24:22.416842 296 : 4250, 4026
7474 01:24:22.419856 300 : 4250, 4027
7475 01:24:22.419935 304 : 4250, 4027
7476 01:24:22.423160 308 : 4252, 4029
7477 01:24:22.423232 312 : 4250, 4026
7478 01:24:22.426857 316 : 4250, 4027
7479 01:24:22.426931 320 : 4250, 4027
7480 01:24:22.429974 324 : 4252, 4029
7481 01:24:22.430044 328 : 4250, 4026
7482 01:24:22.433223 332 : 4361, 3352
7483 01:24:22.433294 336 : 4360, 103
7484 01:24:22.433358
7485 01:24:22.436487 MIOCK jitter meter ch=0
7486 01:24:22.436581
7487 01:24:22.439724 1T = (336-100) = 236 dly cells
7488 01:24:22.443534 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7489 01:24:22.443631 ==
7490 01:24:22.446408 Dram Type= 6, Freq= 0, CH_0, rank 0
7491 01:24:22.453243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7492 01:24:22.453329 ==
7493 01:24:22.456864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7494 01:24:22.463598 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7495 01:24:22.466574 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7496 01:24:22.473381 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7497 01:24:22.480652 [CA 0] Center 44 (14~75) winsize 62
7498 01:24:22.484082 [CA 1] Center 44 (13~75) winsize 63
7499 01:24:22.487676 [CA 2] Center 40 (11~69) winsize 59
7500 01:24:22.491242 [CA 3] Center 39 (10~69) winsize 60
7501 01:24:22.493932 [CA 4] Center 38 (8~68) winsize 61
7502 01:24:22.497870 [CA 5] Center 37 (7~67) winsize 61
7503 01:24:22.497987
7504 01:24:22.500840 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7505 01:24:22.500938
7506 01:24:22.504595 [CATrainingPosCal] consider 1 rank data
7507 01:24:22.507540 u2DelayCellTimex100 = 275/100 ps
7508 01:24:22.510728 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7509 01:24:22.517826 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7510 01:24:22.521289 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7511 01:24:22.524981 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7512 01:24:22.528044 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7513 01:24:22.531279 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7514 01:24:22.531352
7515 01:24:22.534398 CA PerBit enable=1, Macro0, CA PI delay=37
7516 01:24:22.534468
7517 01:24:22.538034 [CBTSetCACLKResult] CA Dly = 37
7518 01:24:22.541188 CS Dly: 11 (0~42)
7519 01:24:22.545052 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7520 01:24:22.548276 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7521 01:24:22.548352 ==
7522 01:24:22.551284 Dram Type= 6, Freq= 0, CH_0, rank 1
7523 01:24:22.554657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 01:24:22.554757 ==
7525 01:24:22.561451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 01:24:22.564800 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 01:24:22.571464 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 01:24:22.574383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 01:24:22.584382 [CA 0] Center 44 (14~75) winsize 62
7530 01:24:22.588074 [CA 1] Center 44 (14~75) winsize 62
7531 01:24:22.591442 [CA 2] Center 40 (11~69) winsize 59
7532 01:24:22.594862 [CA 3] Center 39 (10~69) winsize 60
7533 01:24:22.597914 [CA 4] Center 38 (8~68) winsize 61
7534 01:24:22.601600 [CA 5] Center 37 (7~67) winsize 61
7535 01:24:22.601684
7536 01:24:22.604619 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7537 01:24:22.604737
7538 01:24:22.608359 [CATrainingPosCal] consider 2 rank data
7539 01:24:22.611652 u2DelayCellTimex100 = 275/100 ps
7540 01:24:22.614718 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7541 01:24:22.621360 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7542 01:24:22.624607 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7543 01:24:22.628250 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7544 01:24:22.631602 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7545 01:24:22.634552 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7546 01:24:22.634672
7547 01:24:22.638137 CA PerBit enable=1, Macro0, CA PI delay=37
7548 01:24:22.638265
7549 01:24:22.641208 [CBTSetCACLKResult] CA Dly = 37
7550 01:24:22.644621 CS Dly: 12 (0~44)
7551 01:24:22.647896 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 01:24:22.651543 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 01:24:22.651654
7554 01:24:22.655061 ----->DramcWriteLeveling(PI) begin...
7555 01:24:22.655162 ==
7556 01:24:22.657706 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 01:24:22.664575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 01:24:22.664698 ==
7559 01:24:22.667961 Write leveling (Byte 0): 33 => 33
7560 01:24:22.668040 Write leveling (Byte 1): 26 => 26
7561 01:24:22.671340 DramcWriteLeveling(PI) end<-----
7562 01:24:22.671439
7563 01:24:22.671538 ==
7564 01:24:22.674791 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 01:24:22.681680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 01:24:22.681770 ==
7567 01:24:22.684941 [Gating] SW mode calibration
7568 01:24:22.691322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7569 01:24:22.694435 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7570 01:24:22.701627 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 01:24:22.704924 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 01:24:22.708130 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 01:24:22.711521 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 01:24:22.718382 1 4 16 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7575 01:24:22.721492 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7576 01:24:22.725249 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7577 01:24:22.731679 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 01:24:22.735104 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 01:24:22.738225 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 01:24:22.745099 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 01:24:22.748163 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7582 01:24:22.751893 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
7583 01:24:22.758200 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7584 01:24:22.761382 1 5 24 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7585 01:24:22.764773 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 01:24:22.771722 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 01:24:22.775179 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 01:24:22.778079 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 01:24:22.785013 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 01:24:22.788009 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7591 01:24:22.791743 1 6 20 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
7592 01:24:22.794727 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7593 01:24:22.801473 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 01:24:22.805301 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 01:24:22.808057 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 01:24:22.814748 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 01:24:22.818611 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 01:24:22.821417 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 01:24:22.828813 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7600 01:24:22.831529 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7601 01:24:22.834841 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 01:24:22.841630 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 01:24:22.844766 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 01:24:22.848122 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 01:24:22.855079 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 01:24:22.857979 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 01:24:22.861656 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 01:24:22.867984 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 01:24:22.871658 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 01:24:22.875171 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 01:24:22.881566 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 01:24:22.884957 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 01:24:22.888461 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7614 01:24:22.891873 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7615 01:24:22.898744 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7616 01:24:22.901609 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7617 01:24:22.904831 Total UI for P1: 0, mck2ui 16
7618 01:24:22.908419 best dqsien dly found for B0: ( 1, 9, 16)
7619 01:24:22.911798 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 01:24:22.914862 Total UI for P1: 0, mck2ui 16
7621 01:24:22.918647 best dqsien dly found for B1: ( 1, 9, 22)
7622 01:24:22.921716 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7623 01:24:22.924800 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7624 01:24:22.924876
7625 01:24:22.931739 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7626 01:24:22.935728 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7627 01:24:22.938201 [Gating] SW calibration Done
7628 01:24:22.938313 ==
7629 01:24:22.941806 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 01:24:22.945311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 01:24:22.945390 ==
7632 01:24:22.945453 RX Vref Scan: 0
7633 01:24:22.945510
7634 01:24:22.948562 RX Vref 0 -> 0, step: 1
7635 01:24:22.948675
7636 01:24:22.951725 RX Delay 0 -> 252, step: 8
7637 01:24:22.955178 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7638 01:24:22.958636 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7639 01:24:22.961871 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7640 01:24:22.969031 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7641 01:24:22.971571 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7642 01:24:22.975177 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7643 01:24:22.978504 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7644 01:24:22.981923 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7645 01:24:22.988217 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7646 01:24:22.992357 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7647 01:24:22.994995 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7648 01:24:22.998996 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7649 01:24:23.001887 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7650 01:24:23.008492 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7651 01:24:23.012193 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7652 01:24:23.015506 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7653 01:24:23.015591 ==
7654 01:24:23.018275 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 01:24:23.022142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 01:24:23.022227 ==
7657 01:24:23.025364 DQS Delay:
7658 01:24:23.025446 DQS0 = 0, DQS1 = 0
7659 01:24:23.028906 DQM Delay:
7660 01:24:23.028987 DQM0 = 132, DQM1 = 123
7661 01:24:23.029051 DQ Delay:
7662 01:24:23.035323 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7663 01:24:23.038566 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7664 01:24:23.041650 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7665 01:24:23.045008 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7666 01:24:23.045104
7667 01:24:23.045189
7668 01:24:23.045288 ==
7669 01:24:23.049024 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 01:24:23.052094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 01:24:23.052168 ==
7672 01:24:23.052236
7673 01:24:23.052293
7674 01:24:23.055153 TX Vref Scan disable
7675 01:24:23.058478 == TX Byte 0 ==
7676 01:24:23.061704 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7677 01:24:23.065399 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7678 01:24:23.068517 == TX Byte 1 ==
7679 01:24:23.072209 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7680 01:24:23.075382 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7681 01:24:23.075456 ==
7682 01:24:23.078525 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 01:24:23.081817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 01:24:23.084696 ==
7685 01:24:23.096794
7686 01:24:23.100370 TX Vref early break, caculate TX vref
7687 01:24:23.103989 TX Vref=16, minBit 4, minWin=21, winSum=353
7688 01:24:23.106983 TX Vref=18, minBit 0, minWin=22, winSum=363
7689 01:24:23.110741 TX Vref=20, minBit 0, minWin=22, winSum=374
7690 01:24:23.113953 TX Vref=22, minBit 4, minWin=22, winSum=386
7691 01:24:23.116776 TX Vref=24, minBit 4, minWin=23, winSum=393
7692 01:24:23.124151 TX Vref=26, minBit 1, minWin=24, winSum=405
7693 01:24:23.126662 TX Vref=28, minBit 4, minWin=24, winSum=415
7694 01:24:23.130327 TX Vref=30, minBit 4, minWin=24, winSum=412
7695 01:24:23.133516 TX Vref=32, minBit 4, minWin=23, winSum=404
7696 01:24:23.136861 TX Vref=34, minBit 4, minWin=23, winSum=393
7697 01:24:23.144244 [TxChooseVref] Worse bit 4, Min win 24, Win sum 415, Final Vref 28
7698 01:24:23.144352
7699 01:24:23.147499 Final TX Range 0 Vref 28
7700 01:24:23.147609
7701 01:24:23.147710 ==
7702 01:24:23.150160 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 01:24:23.153828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 01:24:23.153932 ==
7705 01:24:23.154023
7706 01:24:23.154118
7707 01:24:23.157157 TX Vref Scan disable
7708 01:24:23.160504 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7709 01:24:23.163972 == TX Byte 0 ==
7710 01:24:23.167100 u2DelayCellOfst[0]=17 cells (5 PI)
7711 01:24:23.170700 u2DelayCellOfst[1]=21 cells (6 PI)
7712 01:24:23.173741 u2DelayCellOfst[2]=14 cells (4 PI)
7713 01:24:23.177235 u2DelayCellOfst[3]=17 cells (5 PI)
7714 01:24:23.180676 u2DelayCellOfst[4]=10 cells (3 PI)
7715 01:24:23.180750 u2DelayCellOfst[5]=0 cells (0 PI)
7716 01:24:23.184628 u2DelayCellOfst[6]=21 cells (6 PI)
7717 01:24:23.187307 u2DelayCellOfst[7]=21 cells (6 PI)
7718 01:24:23.194367 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7719 01:24:23.197855 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7720 01:24:23.197931 == TX Byte 1 ==
7721 01:24:23.200947 u2DelayCellOfst[8]=0 cells (0 PI)
7722 01:24:23.204603 u2DelayCellOfst[9]=0 cells (0 PI)
7723 01:24:23.207392 u2DelayCellOfst[10]=7 cells (2 PI)
7724 01:24:23.210637 u2DelayCellOfst[11]=0 cells (0 PI)
7725 01:24:23.214168 u2DelayCellOfst[12]=10 cells (3 PI)
7726 01:24:23.217474 u2DelayCellOfst[13]=10 cells (3 PI)
7727 01:24:23.220680 u2DelayCellOfst[14]=14 cells (4 PI)
7728 01:24:23.224149 u2DelayCellOfst[15]=10 cells (3 PI)
7729 01:24:23.227394 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7730 01:24:23.230991 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7731 01:24:23.234027 DramC Write-DBI on
7732 01:24:23.234130 ==
7733 01:24:23.237215 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 01:24:23.240826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 01:24:23.240900 ==
7736 01:24:23.240962
7737 01:24:23.241028
7738 01:24:23.244106 TX Vref Scan disable
7739 01:24:23.247813 == TX Byte 0 ==
7740 01:24:23.250436 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7741 01:24:23.250544 == TX Byte 1 ==
7742 01:24:23.257520 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7743 01:24:23.257628 DramC Write-DBI off
7744 01:24:23.257722
7745 01:24:23.260553 [DATLAT]
7746 01:24:23.260655 Freq=1600, CH0 RK0
7747 01:24:23.260733
7748 01:24:23.263893 DATLAT Default: 0xf
7749 01:24:23.263974 0, 0xFFFF, sum = 0
7750 01:24:23.267262 1, 0xFFFF, sum = 0
7751 01:24:23.267374 2, 0xFFFF, sum = 0
7752 01:24:23.270623 3, 0xFFFF, sum = 0
7753 01:24:23.270725 4, 0xFFFF, sum = 0
7754 01:24:23.273751 5, 0xFFFF, sum = 0
7755 01:24:23.273825 6, 0xFFFF, sum = 0
7756 01:24:23.277206 7, 0xFFFF, sum = 0
7757 01:24:23.277282 8, 0xFFFF, sum = 0
7758 01:24:23.280303 9, 0xFFFF, sum = 0
7759 01:24:23.280404 10, 0xFFFF, sum = 0
7760 01:24:23.284072 11, 0xFFFF, sum = 0
7761 01:24:23.286989 12, 0xFFFF, sum = 0
7762 01:24:23.287093 13, 0xFFFF, sum = 0
7763 01:24:23.290497 14, 0x0, sum = 1
7764 01:24:23.290579 15, 0x0, sum = 2
7765 01:24:23.290642 16, 0x0, sum = 3
7766 01:24:23.294114 17, 0x0, sum = 4
7767 01:24:23.294186 best_step = 15
7768 01:24:23.294245
7769 01:24:23.294302 ==
7770 01:24:23.297146 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 01:24:23.304032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 01:24:23.304118 ==
7773 01:24:23.304181 RX Vref Scan: 1
7774 01:24:23.304241
7775 01:24:23.307415 Set Vref Range= 24 -> 127
7776 01:24:23.307487
7777 01:24:23.310561 RX Vref 24 -> 127, step: 1
7778 01:24:23.310661
7779 01:24:23.313412 RX Delay 11 -> 252, step: 4
7780 01:24:23.313515
7781 01:24:23.317015 Set Vref, RX VrefLevel [Byte0]: 24
7782 01:24:23.320208 [Byte1]: 24
7783 01:24:23.320316
7784 01:24:23.323775 Set Vref, RX VrefLevel [Byte0]: 25
7785 01:24:23.327019 [Byte1]: 25
7786 01:24:23.327096
7787 01:24:23.330365 Set Vref, RX VrefLevel [Byte0]: 26
7788 01:24:23.333974 [Byte1]: 26
7789 01:24:23.337492
7790 01:24:23.337570 Set Vref, RX VrefLevel [Byte0]: 27
7791 01:24:23.340468 [Byte1]: 27
7792 01:24:23.345119
7793 01:24:23.345222 Set Vref, RX VrefLevel [Byte0]: 28
7794 01:24:23.348338 [Byte1]: 28
7795 01:24:23.352189
7796 01:24:23.352291 Set Vref, RX VrefLevel [Byte0]: 29
7797 01:24:23.355687 [Byte1]: 29
7798 01:24:23.359987
7799 01:24:23.360064 Set Vref, RX VrefLevel [Byte0]: 30
7800 01:24:23.363297 [Byte1]: 30
7801 01:24:23.367796
7802 01:24:23.367877 Set Vref, RX VrefLevel [Byte0]: 31
7803 01:24:23.370492 [Byte1]: 31
7804 01:24:23.375076
7805 01:24:23.375155 Set Vref, RX VrefLevel [Byte0]: 32
7806 01:24:23.378365 [Byte1]: 32
7807 01:24:23.382640
7808 01:24:23.382720 Set Vref, RX VrefLevel [Byte0]: 33
7809 01:24:23.386053 [Byte1]: 33
7810 01:24:23.390040
7811 01:24:23.390116 Set Vref, RX VrefLevel [Byte0]: 34
7812 01:24:23.393560 [Byte1]: 34
7813 01:24:23.397847
7814 01:24:23.397925 Set Vref, RX VrefLevel [Byte0]: 35
7815 01:24:23.401224 [Byte1]: 35
7816 01:24:23.405711
7817 01:24:23.405789 Set Vref, RX VrefLevel [Byte0]: 36
7818 01:24:23.408644 [Byte1]: 36
7819 01:24:23.413168
7820 01:24:23.413246 Set Vref, RX VrefLevel [Byte0]: 37
7821 01:24:23.416227 [Byte1]: 37
7822 01:24:23.420542
7823 01:24:23.420647 Set Vref, RX VrefLevel [Byte0]: 38
7824 01:24:23.423737 [Byte1]: 38
7825 01:24:23.428119
7826 01:24:23.428194 Set Vref, RX VrefLevel [Byte0]: 39
7827 01:24:23.432012 [Byte1]: 39
7828 01:24:23.435710
7829 01:24:23.435811 Set Vref, RX VrefLevel [Byte0]: 40
7830 01:24:23.439484 [Byte1]: 40
7831 01:24:23.443779
7832 01:24:23.443878 Set Vref, RX VrefLevel [Byte0]: 41
7833 01:24:23.447123 [Byte1]: 41
7834 01:24:23.450910
7835 01:24:23.451017 Set Vref, RX VrefLevel [Byte0]: 42
7836 01:24:23.454338 [Byte1]: 42
7837 01:24:23.458972
7838 01:24:23.459073 Set Vref, RX VrefLevel [Byte0]: 43
7839 01:24:23.462489 [Byte1]: 43
7840 01:24:23.466380
7841 01:24:23.466482 Set Vref, RX VrefLevel [Byte0]: 44
7842 01:24:23.469425 [Byte1]: 44
7843 01:24:23.473943
7844 01:24:23.474017 Set Vref, RX VrefLevel [Byte0]: 45
7845 01:24:23.477228 [Byte1]: 45
7846 01:24:23.481513
7847 01:24:23.481586 Set Vref, RX VrefLevel [Byte0]: 46
7848 01:24:23.484909 [Byte1]: 46
7849 01:24:23.489444
7850 01:24:23.489528 Set Vref, RX VrefLevel [Byte0]: 47
7851 01:24:23.492395 [Byte1]: 47
7852 01:24:23.496587
7853 01:24:23.496704 Set Vref, RX VrefLevel [Byte0]: 48
7854 01:24:23.500242 [Byte1]: 48
7855 01:24:23.504261
7856 01:24:23.504367 Set Vref, RX VrefLevel [Byte0]: 49
7857 01:24:23.507640 [Byte1]: 49
7858 01:24:23.512047
7859 01:24:23.512156 Set Vref, RX VrefLevel [Byte0]: 50
7860 01:24:23.515656 [Byte1]: 50
7861 01:24:23.519580
7862 01:24:23.519689 Set Vref, RX VrefLevel [Byte0]: 51
7863 01:24:23.523281 [Byte1]: 51
7864 01:24:23.527335
7865 01:24:23.527437 Set Vref, RX VrefLevel [Byte0]: 52
7866 01:24:23.530869 [Byte1]: 52
7867 01:24:23.535294
7868 01:24:23.535402 Set Vref, RX VrefLevel [Byte0]: 53
7869 01:24:23.538124 [Byte1]: 53
7870 01:24:23.542460
7871 01:24:23.542563 Set Vref, RX VrefLevel [Byte0]: 54
7872 01:24:23.545975 [Byte1]: 54
7873 01:24:23.550249
7874 01:24:23.550361 Set Vref, RX VrefLevel [Byte0]: 55
7875 01:24:23.553520 [Byte1]: 55
7876 01:24:23.558076
7877 01:24:23.558179 Set Vref, RX VrefLevel [Byte0]: 56
7878 01:24:23.560856 [Byte1]: 56
7879 01:24:23.565322
7880 01:24:23.565426 Set Vref, RX VrefLevel [Byte0]: 57
7881 01:24:23.568484 [Byte1]: 57
7882 01:24:23.573038
7883 01:24:23.573140 Set Vref, RX VrefLevel [Byte0]: 58
7884 01:24:23.576166 [Byte1]: 58
7885 01:24:23.580568
7886 01:24:23.580686 Set Vref, RX VrefLevel [Byte0]: 59
7887 01:24:23.584135 [Byte1]: 59
7888 01:24:23.588157
7889 01:24:23.588262 Set Vref, RX VrefLevel [Byte0]: 60
7890 01:24:23.591607 [Byte1]: 60
7891 01:24:23.595826
7892 01:24:23.595932 Set Vref, RX VrefLevel [Byte0]: 61
7893 01:24:23.599117 [Byte1]: 61
7894 01:24:23.603364
7895 01:24:23.603465 Set Vref, RX VrefLevel [Byte0]: 62
7896 01:24:23.606481 [Byte1]: 62
7897 01:24:23.611294
7898 01:24:23.611396 Set Vref, RX VrefLevel [Byte0]: 63
7899 01:24:23.614554 [Byte1]: 63
7900 01:24:23.618971
7901 01:24:23.619076 Set Vref, RX VrefLevel [Byte0]: 64
7902 01:24:23.622069 [Byte1]: 64
7903 01:24:23.626278
7904 01:24:23.626392 Set Vref, RX VrefLevel [Byte0]: 65
7905 01:24:23.630007 [Byte1]: 65
7906 01:24:23.633846
7907 01:24:23.633960 Set Vref, RX VrefLevel [Byte0]: 66
7908 01:24:23.637221 [Byte1]: 66
7909 01:24:23.641947
7910 01:24:23.642053 Set Vref, RX VrefLevel [Byte0]: 67
7911 01:24:23.647803 [Byte1]: 67
7912 01:24:23.647900
7913 01:24:23.651173 Set Vref, RX VrefLevel [Byte0]: 68
7914 01:24:23.654563 [Byte1]: 68
7915 01:24:23.654661
7916 01:24:23.657695 Set Vref, RX VrefLevel [Byte0]: 69
7917 01:24:23.661017 [Byte1]: 69
7918 01:24:23.661089
7919 01:24:23.664337 Set Vref, RX VrefLevel [Byte0]: 70
7920 01:24:23.668210 [Byte1]: 70
7921 01:24:23.671671
7922 01:24:23.671770 Set Vref, RX VrefLevel [Byte0]: 71
7923 01:24:23.675056 [Byte1]: 71
7924 01:24:23.679615
7925 01:24:23.679713 Set Vref, RX VrefLevel [Byte0]: 72
7926 01:24:23.682681 [Byte1]: 72
7927 01:24:23.686999
7928 01:24:23.687087 Set Vref, RX VrefLevel [Byte0]: 73
7929 01:24:23.690733 [Byte1]: 73
7930 01:24:23.694744
7931 01:24:23.694856 Set Vref, RX VrefLevel [Byte0]: 74
7932 01:24:23.698696 [Byte1]: 74
7933 01:24:23.702156
7934 01:24:23.702263 Set Vref, RX VrefLevel [Byte0]: 75
7935 01:24:23.705845 [Byte1]: 75
7936 01:24:23.710348
7937 01:24:23.710454 Set Vref, RX VrefLevel [Byte0]: 76
7938 01:24:23.713312 [Byte1]: 76
7939 01:24:23.717364
7940 01:24:23.717470 Set Vref, RX VrefLevel [Byte0]: 77
7941 01:24:23.721315 [Byte1]: 77
7942 01:24:23.725812
7943 01:24:23.725924 Final RX Vref Byte 0 = 62 to rank0
7944 01:24:23.728824 Final RX Vref Byte 1 = 61 to rank0
7945 01:24:23.731773 Final RX Vref Byte 0 = 62 to rank1
7946 01:24:23.735155 Final RX Vref Byte 1 = 61 to rank1==
7947 01:24:23.738407 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 01:24:23.742289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 01:24:23.745200 ==
7950 01:24:23.745280 DQS Delay:
7951 01:24:23.745343 DQS0 = 0, DQS1 = 0
7952 01:24:23.748639 DQM Delay:
7953 01:24:23.748761 DQM0 = 130, DQM1 = 121
7954 01:24:23.752046 DQ Delay:
7955 01:24:23.755548 DQ0 =132, DQ1 =132, DQ2 =126, DQ3 =126
7956 01:24:23.759119 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7957 01:24:23.762072 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7958 01:24:23.765464 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7959 01:24:23.765544
7960 01:24:23.765606
7961 01:24:23.765664
7962 01:24:23.768782 [DramC_TX_OE_Calibration] TA2
7963 01:24:23.771977 Original DQ_B0 (3 6) =30, OEN = 27
7964 01:24:23.775514 Original DQ_B1 (3 6) =30, OEN = 27
7965 01:24:23.778804 24, 0x0, End_B0=24 End_B1=24
7966 01:24:23.778880 25, 0x0, End_B0=25 End_B1=25
7967 01:24:23.781742 26, 0x0, End_B0=26 End_B1=26
7968 01:24:23.785420 27, 0x0, End_B0=27 End_B1=27
7969 01:24:23.788482 28, 0x0, End_B0=28 End_B1=28
7970 01:24:23.788591 29, 0x0, End_B0=29 End_B1=29
7971 01:24:23.791897 30, 0x0, End_B0=30 End_B1=30
7972 01:24:23.795650 31, 0x4141, End_B0=30 End_B1=30
7973 01:24:23.798563 Byte0 end_step=30 best_step=27
7974 01:24:23.802022 Byte1 end_step=30 best_step=27
7975 01:24:23.805454 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 01:24:23.805562 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 01:24:23.805664
7978 01:24:23.805753
7979 01:24:23.815541 [DQSOSCAuto] RK0, (LSB)MR18= 0x160a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
7980 01:24:23.818738 CH0 RK0: MR19=303, MR18=160A
7981 01:24:23.822437 CH0_RK0: MR19=0x303, MR18=0x160A, DQSOSC=398, MR23=63, INC=23, DEC=15
7982 01:24:23.822511
7983 01:24:23.828782 ----->DramcWriteLeveling(PI) begin...
7984 01:24:23.828857 ==
7985 01:24:23.832140 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 01:24:23.835341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 01:24:23.835423 ==
7988 01:24:23.839154 Write leveling (Byte 0): 33 => 33
7989 01:24:23.842354 Write leveling (Byte 1): 26 => 26
7990 01:24:23.845456 DramcWriteLeveling(PI) end<-----
7991 01:24:23.845537
7992 01:24:23.845599 ==
7993 01:24:23.848838 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 01:24:23.852263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 01:24:23.852358 ==
7996 01:24:23.855554 [Gating] SW mode calibration
7997 01:24:23.862172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 01:24:23.869128 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 01:24:23.872291 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 01:24:23.875583 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 01:24:23.879073 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8002 01:24:23.885595 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8003 01:24:23.888843 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8004 01:24:23.892613 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8005 01:24:23.898930 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 01:24:23.902370 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 01:24:23.905752 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 01:24:23.912462 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8009 01:24:23.915557 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8010 01:24:23.919209 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8011 01:24:23.926576 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8012 01:24:23.929343 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8013 01:24:23.932468 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8014 01:24:23.939017 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 01:24:23.942768 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 01:24:23.946226 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 01:24:23.949695 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8018 01:24:23.955808 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8019 01:24:23.959597 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8020 01:24:23.962602 1 6 20 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
8021 01:24:23.969272 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 01:24:23.973213 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 01:24:23.975848 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 01:24:23.982587 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 01:24:23.985591 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 01:24:23.989191 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8027 01:24:23.996161 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 01:24:23.999211 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 01:24:24.002804 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8030 01:24:24.009736 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 01:24:24.012791 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 01:24:24.016350 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 01:24:24.022419 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 01:24:24.025781 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 01:24:24.029952 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 01:24:24.032837 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 01:24:24.039449 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 01:24:24.042706 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 01:24:24.045971 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 01:24:24.052348 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 01:24:24.056059 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8042 01:24:24.059065 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 01:24:24.066266 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8044 01:24:24.069044 Total UI for P1: 0, mck2ui 16
8045 01:24:24.072965 best dqsien dly found for B0: ( 1, 9, 10)
8046 01:24:24.075961 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 01:24:24.079141 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 01:24:24.082614 Total UI for P1: 0, mck2ui 16
8049 01:24:24.086610 best dqsien dly found for B1: ( 1, 9, 20)
8050 01:24:24.089649 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8051 01:24:24.093244 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8052 01:24:24.093345
8053 01:24:24.099624 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8054 01:24:24.102994 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8055 01:24:24.106370 [Gating] SW calibration Done
8056 01:24:24.106451 ==
8057 01:24:24.109546 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 01:24:24.112425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 01:24:24.112505 ==
8060 01:24:24.112567 RX Vref Scan: 0
8061 01:24:24.112625
8062 01:24:24.115771 RX Vref 0 -> 0, step: 1
8063 01:24:24.115896
8064 01:24:24.119375 RX Delay 0 -> 252, step: 8
8065 01:24:24.122417 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8066 01:24:24.125984 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8067 01:24:24.129698 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8068 01:24:24.135834 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8069 01:24:24.139108 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8070 01:24:24.142892 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8071 01:24:24.146199 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8072 01:24:24.149318 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8073 01:24:24.156096 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8074 01:24:24.159346 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8075 01:24:24.163272 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8076 01:24:24.166085 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8077 01:24:24.169297 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8078 01:24:24.176289 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8079 01:24:24.179752 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8080 01:24:24.182518 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8081 01:24:24.182599 ==
8082 01:24:24.186125 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 01:24:24.189712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 01:24:24.189824 ==
8085 01:24:24.192876 DQS Delay:
8086 01:24:24.192956 DQS0 = 0, DQS1 = 0
8087 01:24:24.196425 DQM Delay:
8088 01:24:24.196505 DQM0 = 131, DQM1 = 124
8089 01:24:24.196567 DQ Delay:
8090 01:24:24.199385 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8091 01:24:24.203120 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8092 01:24:24.209661 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8093 01:24:24.213173 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8094 01:24:24.213255
8095 01:24:24.213317
8096 01:24:24.213375 ==
8097 01:24:24.216437 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 01:24:24.219735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 01:24:24.219816 ==
8100 01:24:24.219879
8101 01:24:24.219937
8102 01:24:24.223179 TX Vref Scan disable
8103 01:24:24.226870 == TX Byte 0 ==
8104 01:24:24.229377 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8105 01:24:24.233291 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8106 01:24:24.236023 == TX Byte 1 ==
8107 01:24:24.239795 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8108 01:24:24.243017 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8109 01:24:24.243097 ==
8110 01:24:24.246167 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 01:24:24.249466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 01:24:24.249551 ==
8113 01:24:24.265884
8114 01:24:24.268998 TX Vref early break, caculate TX vref
8115 01:24:24.272380 TX Vref=16, minBit 1, minWin=21, winSum=368
8116 01:24:24.275927 TX Vref=18, minBit 4, minWin=22, winSum=376
8117 01:24:24.279113 TX Vref=20, minBit 5, minWin=23, winSum=384
8118 01:24:24.282275 TX Vref=22, minBit 1, minWin=24, winSum=393
8119 01:24:24.285820 TX Vref=24, minBit 4, minWin=24, winSum=402
8120 01:24:24.292528 TX Vref=26, minBit 0, minWin=25, winSum=412
8121 01:24:24.296069 TX Vref=28, minBit 1, minWin=25, winSum=415
8122 01:24:24.299456 TX Vref=30, minBit 1, minWin=25, winSum=416
8123 01:24:24.302239 TX Vref=32, minBit 8, minWin=24, winSum=409
8124 01:24:24.305630 TX Vref=34, minBit 0, minWin=24, winSum=402
8125 01:24:24.309438 TX Vref=36, minBit 4, minWin=23, winSum=394
8126 01:24:24.315653 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
8127 01:24:24.315745
8128 01:24:24.319086 Final TX Range 0 Vref 30
8129 01:24:24.319208
8130 01:24:24.319298 ==
8131 01:24:24.322656 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 01:24:24.325586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 01:24:24.325697 ==
8134 01:24:24.325759
8135 01:24:24.325817
8136 01:24:24.329642 TX Vref Scan disable
8137 01:24:24.336594 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8138 01:24:24.336684 == TX Byte 0 ==
8139 01:24:24.339395 u2DelayCellOfst[0]=14 cells (4 PI)
8140 01:24:24.342842 u2DelayCellOfst[1]=17 cells (5 PI)
8141 01:24:24.345962 u2DelayCellOfst[2]=10 cells (3 PI)
8142 01:24:24.349098 u2DelayCellOfst[3]=10 cells (3 PI)
8143 01:24:24.353012 u2DelayCellOfst[4]=10 cells (3 PI)
8144 01:24:24.356218 u2DelayCellOfst[5]=0 cells (0 PI)
8145 01:24:24.359101 u2DelayCellOfst[6]=17 cells (5 PI)
8146 01:24:24.362552 u2DelayCellOfst[7]=21 cells (6 PI)
8147 01:24:24.365934 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8148 01:24:24.369479 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8149 01:24:24.369561 == TX Byte 1 ==
8150 01:24:24.372428 u2DelayCellOfst[8]=0 cells (0 PI)
8151 01:24:24.375885 u2DelayCellOfst[9]=0 cells (0 PI)
8152 01:24:24.379645 u2DelayCellOfst[10]=7 cells (2 PI)
8153 01:24:24.382913 u2DelayCellOfst[11]=0 cells (0 PI)
8154 01:24:24.386207 u2DelayCellOfst[12]=10 cells (3 PI)
8155 01:24:24.389520 u2DelayCellOfst[13]=10 cells (3 PI)
8156 01:24:24.392528 u2DelayCellOfst[14]=14 cells (4 PI)
8157 01:24:24.396240 u2DelayCellOfst[15]=10 cells (3 PI)
8158 01:24:24.399430 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8159 01:24:24.402876 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8160 01:24:24.406253 DramC Write-DBI on
8161 01:24:24.406334 ==
8162 01:24:24.409536 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 01:24:24.412926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 01:24:24.413004 ==
8165 01:24:24.413067
8166 01:24:24.416162
8167 01:24:24.416235 TX Vref Scan disable
8168 01:24:24.419936 == TX Byte 0 ==
8169 01:24:24.422569 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8170 01:24:24.426168 == TX Byte 1 ==
8171 01:24:24.429307 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8172 01:24:24.429377 DramC Write-DBI off
8173 01:24:24.429437
8174 01:24:24.432521 [DATLAT]
8175 01:24:24.432632 Freq=1600, CH0 RK1
8176 01:24:24.432728
8177 01:24:24.436461 DATLAT Default: 0xf
8178 01:24:24.436559 0, 0xFFFF, sum = 0
8179 01:24:24.439547 1, 0xFFFF, sum = 0
8180 01:24:24.439629 2, 0xFFFF, sum = 0
8181 01:24:24.443132 3, 0xFFFF, sum = 0
8182 01:24:24.443241 4, 0xFFFF, sum = 0
8183 01:24:24.446227 5, 0xFFFF, sum = 0
8184 01:24:24.446334 6, 0xFFFF, sum = 0
8185 01:24:24.449642 7, 0xFFFF, sum = 0
8186 01:24:24.449735 8, 0xFFFF, sum = 0
8187 01:24:24.452865 9, 0xFFFF, sum = 0
8188 01:24:24.452937 10, 0xFFFF, sum = 0
8189 01:24:24.456375 11, 0xFFFF, sum = 0
8190 01:24:24.459841 12, 0xFFFF, sum = 0
8191 01:24:24.459941 13, 0xFFFF, sum = 0
8192 01:24:24.463407 14, 0x0, sum = 1
8193 01:24:24.463507 15, 0x0, sum = 2
8194 01:24:24.463601 16, 0x0, sum = 3
8195 01:24:24.466474 17, 0x0, sum = 4
8196 01:24:24.466555 best_step = 15
8197 01:24:24.466617
8198 01:24:24.469909 ==
8199 01:24:24.469993 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 01:24:24.476234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 01:24:24.476345 ==
8202 01:24:24.476437 RX Vref Scan: 0
8203 01:24:24.476522
8204 01:24:24.479933 RX Vref 0 -> 0, step: 1
8205 01:24:24.480043
8206 01:24:24.483165 RX Delay 11 -> 252, step: 4
8207 01:24:24.486485 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8208 01:24:24.489777 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8209 01:24:24.496374 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8210 01:24:24.499869 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8211 01:24:24.502771 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8212 01:24:24.506409 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8213 01:24:24.509632 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8214 01:24:24.512877 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8215 01:24:24.519584 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8216 01:24:24.522962 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8217 01:24:24.526419 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8218 01:24:24.529831 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8219 01:24:24.536465 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8220 01:24:24.539586 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8221 01:24:24.543148 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8222 01:24:24.546535 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8223 01:24:24.546637 ==
8224 01:24:24.549798 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 01:24:24.553243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 01:24:24.556482 ==
8227 01:24:24.556584 DQS Delay:
8228 01:24:24.556704 DQS0 = 0, DQS1 = 0
8229 01:24:24.559688 DQM Delay:
8230 01:24:24.559794 DQM0 = 127, DQM1 = 122
8231 01:24:24.562990 DQ Delay:
8232 01:24:24.566216 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8233 01:24:24.569642 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8234 01:24:24.572870 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8235 01:24:24.576013 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8236 01:24:24.576093
8237 01:24:24.576155
8238 01:24:24.576213
8239 01:24:24.579635 [DramC_TX_OE_Calibration] TA2
8240 01:24:24.583205 Original DQ_B0 (3 6) =30, OEN = 27
8241 01:24:24.586630 Original DQ_B1 (3 6) =30, OEN = 27
8242 01:24:24.590059 24, 0x0, End_B0=24 End_B1=24
8243 01:24:24.590139 25, 0x0, End_B0=25 End_B1=25
8244 01:24:24.593068 26, 0x0, End_B0=26 End_B1=26
8245 01:24:24.596052 27, 0x0, End_B0=27 End_B1=27
8246 01:24:24.599945 28, 0x0, End_B0=28 End_B1=28
8247 01:24:24.600015 29, 0x0, End_B0=29 End_B1=29
8248 01:24:24.602847 30, 0x0, End_B0=30 End_B1=30
8249 01:24:24.606100 31, 0x5151, End_B0=30 End_B1=30
8250 01:24:24.609398 Byte0 end_step=30 best_step=27
8251 01:24:24.613118 Byte1 end_step=30 best_step=27
8252 01:24:24.616489 Byte0 TX OE(2T, 0.5T) = (3, 3)
8253 01:24:24.616569 Byte1 TX OE(2T, 0.5T) = (3, 3)
8254 01:24:24.616631
8255 01:24:24.616727
8256 01:24:24.626322 [DQSOSCAuto] RK1, (LSB)MR18= 0x190d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8257 01:24:24.629969 CH0 RK1: MR19=303, MR18=190D
8258 01:24:24.632914 CH0_RK1: MR19=0x303, MR18=0x190D, DQSOSC=397, MR23=63, INC=23, DEC=15
8259 01:24:24.636181 [RxdqsGatingPostProcess] freq 1600
8260 01:24:24.643144 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8261 01:24:24.646475 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 01:24:24.649774 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 01:24:24.653171 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 01:24:24.656165 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 01:24:24.659708 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 01:24:24.663217 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 01:24:24.663302 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 01:24:24.666521 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 01:24:24.669510 Pre-setting of DQS Precalculation
8270 01:24:24.676218 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8271 01:24:24.676301 ==
8272 01:24:24.679866 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 01:24:24.683167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 01:24:24.683251 ==
8275 01:24:24.689601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 01:24:24.692911 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 01:24:24.696529 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 01:24:24.703431 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 01:24:24.712135 [CA 0] Center 42 (13~71) winsize 59
8280 01:24:24.715508 [CA 1] Center 41 (12~71) winsize 60
8281 01:24:24.718865 [CA 2] Center 37 (8~66) winsize 59
8282 01:24:24.722091 [CA 3] Center 36 (7~65) winsize 59
8283 01:24:24.725570 [CA 4] Center 37 (8~66) winsize 59
8284 01:24:24.728950 [CA 5] Center 36 (7~66) winsize 60
8285 01:24:24.729033
8286 01:24:24.732481 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 01:24:24.732563
8288 01:24:24.735834 [CATrainingPosCal] consider 1 rank data
8289 01:24:24.739880 u2DelayCellTimex100 = 275/100 ps
8290 01:24:24.742442 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8291 01:24:24.748775 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8292 01:24:24.752561 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8293 01:24:24.755694 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8294 01:24:24.758971 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8295 01:24:24.762401 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8296 01:24:24.762512
8297 01:24:24.765579 CA PerBit enable=1, Macro0, CA PI delay=36
8298 01:24:24.765663
8299 01:24:24.768976 [CBTSetCACLKResult] CA Dly = 36
8300 01:24:24.769085 CS Dly: 8 (0~39)
8301 01:24:24.775566 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 01:24:24.778914 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 01:24:24.778996 ==
8304 01:24:24.782136 Dram Type= 6, Freq= 0, CH_1, rank 1
8305 01:24:24.785606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 01:24:24.785689 ==
8307 01:24:24.792446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 01:24:24.795872 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 01:24:24.798772 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 01:24:24.805792 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 01:24:24.815208 [CA 0] Center 43 (14~72) winsize 59
8312 01:24:24.818556 [CA 1] Center 43 (14~72) winsize 59
8313 01:24:24.822458 [CA 2] Center 38 (9~67) winsize 59
8314 01:24:24.825132 [CA 3] Center 37 (8~67) winsize 60
8315 01:24:24.828580 [CA 4] Center 39 (10~68) winsize 59
8316 01:24:24.831828 [CA 5] Center 37 (8~66) winsize 59
8317 01:24:24.831910
8318 01:24:24.834898 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8319 01:24:24.835004
8320 01:24:24.838771 [CATrainingPosCal] consider 2 rank data
8321 01:24:24.842072 u2DelayCellTimex100 = 275/100 ps
8322 01:24:24.845056 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8323 01:24:24.852120 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8324 01:24:24.855042 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8325 01:24:24.858191 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8326 01:24:24.861801 CA4 delay=38 (10~66),Diff = 2 PI (7 cell)
8327 01:24:24.865103 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8328 01:24:24.865185
8329 01:24:24.868516 CA PerBit enable=1, Macro0, CA PI delay=36
8330 01:24:24.868601
8331 01:24:24.872259 [CBTSetCACLKResult] CA Dly = 36
8332 01:24:24.875129 CS Dly: 10 (0~43)
8333 01:24:24.878952 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 01:24:24.881802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 01:24:24.881882
8336 01:24:24.885658 ----->DramcWriteLeveling(PI) begin...
8337 01:24:24.885740 ==
8338 01:24:24.888575 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 01:24:24.891796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 01:24:24.895334 ==
8341 01:24:24.895417 Write leveling (Byte 0): 25 => 25
8342 01:24:24.898531 Write leveling (Byte 1): 28 => 28
8343 01:24:24.902086 DramcWriteLeveling(PI) end<-----
8344 01:24:24.902195
8345 01:24:24.902285 ==
8346 01:24:24.905369 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 01:24:24.912053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 01:24:24.912160 ==
8349 01:24:24.912252 [Gating] SW mode calibration
8350 01:24:24.922009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8351 01:24:24.925331 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8352 01:24:24.928592 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 01:24:24.935234 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 01:24:24.938454 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 01:24:24.941721 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 01:24:24.948926 1 4 16 | B1->B0 | 2929 2626 | 1 1 | (1 1) (1 1)
8357 01:24:24.952025 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8358 01:24:24.955434 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 01:24:24.961768 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 01:24:24.965633 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 01:24:24.969168 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 01:24:24.975245 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 01:24:24.978824 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8364 01:24:24.982425 1 5 16 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
8365 01:24:24.988820 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 01:24:24.992315 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 01:24:24.995653 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 01:24:24.998985 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 01:24:25.005666 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 01:24:25.009066 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 01:24:25.012435 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 01:24:25.018797 1 6 16 | B1->B0 | 2f2f 2929 | 0 0 | (1 1) (0 0)
8373 01:24:25.022144 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 01:24:25.025816 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 01:24:25.032415 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 01:24:25.035794 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 01:24:25.039200 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 01:24:25.046169 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 01:24:25.049527 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 01:24:25.052962 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8381 01:24:25.056361 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 01:24:25.062750 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 01:24:25.065901 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 01:24:25.069564 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 01:24:25.075940 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 01:24:25.079411 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 01:24:25.082998 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 01:24:25.089606 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 01:24:25.092946 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 01:24:25.096096 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 01:24:25.102433 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 01:24:25.105943 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 01:24:25.109431 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 01:24:25.116055 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 01:24:25.119859 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8396 01:24:25.122675 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8397 01:24:25.129356 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 01:24:25.129436 Total UI for P1: 0, mck2ui 16
8399 01:24:25.132836 best dqsien dly found for B0: ( 1, 9, 14)
8400 01:24:25.135883 Total UI for P1: 0, mck2ui 16
8401 01:24:25.139665 best dqsien dly found for B1: ( 1, 9, 14)
8402 01:24:25.142616 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8403 01:24:25.149280 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8404 01:24:25.149364
8405 01:24:25.152741 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8406 01:24:25.156414 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8407 01:24:25.159445 [Gating] SW calibration Done
8408 01:24:25.159525 ==
8409 01:24:25.162945 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 01:24:25.166467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 01:24:25.166549 ==
8412 01:24:25.169225 RX Vref Scan: 0
8413 01:24:25.169307
8414 01:24:25.169370 RX Vref 0 -> 0, step: 1
8415 01:24:25.169428
8416 01:24:25.172514 RX Delay 0 -> 252, step: 8
8417 01:24:25.176434 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8418 01:24:25.179797 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8419 01:24:25.186230 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8420 01:24:25.189374 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8421 01:24:25.192927 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8422 01:24:25.195963 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8423 01:24:25.199320 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8424 01:24:25.206203 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8425 01:24:25.209462 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8426 01:24:25.212874 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8427 01:24:25.216190 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8428 01:24:25.219267 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8429 01:24:25.226513 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8430 01:24:25.229420 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8431 01:24:25.232867 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8432 01:24:25.236334 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8433 01:24:25.236418 ==
8434 01:24:25.239721 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 01:24:25.243152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 01:24:25.246067 ==
8437 01:24:25.246149 DQS Delay:
8438 01:24:25.246211 DQS0 = 0, DQS1 = 0
8439 01:24:25.249603 DQM Delay:
8440 01:24:25.249716 DQM0 = 134, DQM1 = 127
8441 01:24:25.253368 DQ Delay:
8442 01:24:25.256221 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8443 01:24:25.259898 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8444 01:24:25.263010 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8445 01:24:25.266201 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8446 01:24:25.266284
8447 01:24:25.266346
8448 01:24:25.266404 ==
8449 01:24:25.270489 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 01:24:25.273124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 01:24:25.273204 ==
8452 01:24:25.273265
8453 01:24:25.273335
8454 01:24:25.276598 TX Vref Scan disable
8455 01:24:25.279830 == TX Byte 0 ==
8456 01:24:25.282909 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8457 01:24:25.286373 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8458 01:24:25.289629 == TX Byte 1 ==
8459 01:24:25.292987 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8460 01:24:25.296548 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8461 01:24:25.296628 ==
8462 01:24:25.299682 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 01:24:25.303120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 01:24:25.306446 ==
8465 01:24:25.317827
8466 01:24:25.321070 TX Vref early break, caculate TX vref
8467 01:24:25.324333 TX Vref=16, minBit 8, minWin=20, winSum=363
8468 01:24:25.327393 TX Vref=18, minBit 8, minWin=21, winSum=366
8469 01:24:25.331034 TX Vref=20, minBit 8, minWin=20, winSum=385
8470 01:24:25.334369 TX Vref=22, minBit 8, minWin=22, winSum=393
8471 01:24:25.337709 TX Vref=24, minBit 5, minWin=24, winSum=402
8472 01:24:25.344824 TX Vref=26, minBit 8, minWin=24, winSum=413
8473 01:24:25.347693 TX Vref=28, minBit 13, minWin=24, winSum=417
8474 01:24:25.351011 TX Vref=30, minBit 6, minWin=25, winSum=420
8475 01:24:25.354316 TX Vref=32, minBit 11, minWin=24, winSum=413
8476 01:24:25.357745 TX Vref=34, minBit 8, minWin=23, winSum=396
8477 01:24:25.364430 [TxChooseVref] Worse bit 6, Min win 25, Win sum 420, Final Vref 30
8478 01:24:25.364537
8479 01:24:25.367600 Final TX Range 0 Vref 30
8480 01:24:25.367705
8481 01:24:25.367791 ==
8482 01:24:25.370905 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 01:24:25.374313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 01:24:25.374388 ==
8485 01:24:25.374448
8486 01:24:25.374504
8487 01:24:25.377681 TX Vref Scan disable
8488 01:24:25.384113 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8489 01:24:25.384198 == TX Byte 0 ==
8490 01:24:25.387331 u2DelayCellOfst[0]=14 cells (4 PI)
8491 01:24:25.391047 u2DelayCellOfst[1]=10 cells (3 PI)
8492 01:24:25.394070 u2DelayCellOfst[2]=0 cells (0 PI)
8493 01:24:25.397352 u2DelayCellOfst[3]=7 cells (2 PI)
8494 01:24:25.400650 u2DelayCellOfst[4]=7 cells (2 PI)
8495 01:24:25.404373 u2DelayCellOfst[5]=17 cells (5 PI)
8496 01:24:25.407021 u2DelayCellOfst[6]=17 cells (5 PI)
8497 01:24:25.407102 u2DelayCellOfst[7]=7 cells (2 PI)
8498 01:24:25.414295 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8499 01:24:25.417647 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8500 01:24:25.417759 == TX Byte 1 ==
8501 01:24:25.420870 u2DelayCellOfst[8]=0 cells (0 PI)
8502 01:24:25.424311 u2DelayCellOfst[9]=7 cells (2 PI)
8503 01:24:25.427417 u2DelayCellOfst[10]=10 cells (3 PI)
8504 01:24:25.430766 u2DelayCellOfst[11]=7 cells (2 PI)
8505 01:24:25.434307 u2DelayCellOfst[12]=14 cells (4 PI)
8506 01:24:25.437496 u2DelayCellOfst[13]=17 cells (5 PI)
8507 01:24:25.440816 u2DelayCellOfst[14]=17 cells (5 PI)
8508 01:24:25.443962 u2DelayCellOfst[15]=17 cells (5 PI)
8509 01:24:25.447501 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8510 01:24:25.450612 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8511 01:24:25.453958 DramC Write-DBI on
8512 01:24:25.454071 ==
8513 01:24:25.457389 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 01:24:25.460636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 01:24:25.460765 ==
8516 01:24:25.460829
8517 01:24:25.460887
8518 01:24:25.464390 TX Vref Scan disable
8519 01:24:25.468237 == TX Byte 0 ==
8520 01:24:25.470934 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8521 01:24:25.474101 == TX Byte 1 ==
8522 01:24:25.477626 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8523 01:24:25.477707 DramC Write-DBI off
8524 01:24:25.477769
8525 01:24:25.480998 [DATLAT]
8526 01:24:25.481078 Freq=1600, CH1 RK0
8527 01:24:25.481141
8528 01:24:25.484372 DATLAT Default: 0xf
8529 01:24:25.484452 0, 0xFFFF, sum = 0
8530 01:24:25.488088 1, 0xFFFF, sum = 0
8531 01:24:25.488171 2, 0xFFFF, sum = 0
8532 01:24:25.491423 3, 0xFFFF, sum = 0
8533 01:24:25.491505 4, 0xFFFF, sum = 0
8534 01:24:25.494280 5, 0xFFFF, sum = 0
8535 01:24:25.494362 6, 0xFFFF, sum = 0
8536 01:24:25.497843 7, 0xFFFF, sum = 0
8537 01:24:25.497936 8, 0xFFFF, sum = 0
8538 01:24:25.501658 9, 0xFFFF, sum = 0
8539 01:24:25.501766 10, 0xFFFF, sum = 0
8540 01:24:25.504343 11, 0xFFFF, sum = 0
8541 01:24:25.504422 12, 0xFFFF, sum = 0
8542 01:24:25.507970 13, 0xFFFF, sum = 0
8543 01:24:25.508050 14, 0x0, sum = 1
8544 01:24:25.511359 15, 0x0, sum = 2
8545 01:24:25.511430 16, 0x0, sum = 3
8546 01:24:25.514322 17, 0x0, sum = 4
8547 01:24:25.514395 best_step = 15
8548 01:24:25.514453
8549 01:24:25.514509 ==
8550 01:24:25.518082 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 01:24:25.524373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 01:24:25.524456 ==
8553 01:24:25.524520 RX Vref Scan: 1
8554 01:24:25.524579
8555 01:24:25.527825 Set Vref Range= 24 -> 127
8556 01:24:25.527896
8557 01:24:25.531303 RX Vref 24 -> 127, step: 1
8558 01:24:25.531376
8559 01:24:25.531435 RX Delay 19 -> 252, step: 4
8560 01:24:25.534681
8561 01:24:25.534763 Set Vref, RX VrefLevel [Byte0]: 24
8562 01:24:25.537803 [Byte1]: 24
8563 01:24:25.542721
8564 01:24:25.542809 Set Vref, RX VrefLevel [Byte0]: 25
8565 01:24:25.545493 [Byte1]: 25
8566 01:24:25.549564
8567 01:24:25.549664 Set Vref, RX VrefLevel [Byte0]: 26
8568 01:24:25.553171 [Byte1]: 26
8569 01:24:25.557143
8570 01:24:25.557223 Set Vref, RX VrefLevel [Byte0]: 27
8571 01:24:25.560541 [Byte1]: 27
8572 01:24:25.564614
8573 01:24:25.564739 Set Vref, RX VrefLevel [Byte0]: 28
8574 01:24:25.568047 [Byte1]: 28
8575 01:24:25.572435
8576 01:24:25.572539 Set Vref, RX VrefLevel [Byte0]: 29
8577 01:24:25.576317 [Byte1]: 29
8578 01:24:25.580234
8579 01:24:25.580306 Set Vref, RX VrefLevel [Byte0]: 30
8580 01:24:25.583011 [Byte1]: 30
8581 01:24:25.587464
8582 01:24:25.587607 Set Vref, RX VrefLevel [Byte0]: 31
8583 01:24:25.590950 [Byte1]: 31
8584 01:24:25.595151
8585 01:24:25.595227 Set Vref, RX VrefLevel [Byte0]: 32
8586 01:24:25.598410 [Byte1]: 32
8587 01:24:25.602420
8588 01:24:25.602508 Set Vref, RX VrefLevel [Byte0]: 33
8589 01:24:25.606074 [Byte1]: 33
8590 01:24:25.610250
8591 01:24:25.610356 Set Vref, RX VrefLevel [Byte0]: 34
8592 01:24:25.614302 [Byte1]: 34
8593 01:24:25.618118
8594 01:24:25.618200 Set Vref, RX VrefLevel [Byte0]: 35
8595 01:24:25.620890 [Byte1]: 35
8596 01:24:25.625356
8597 01:24:25.625438 Set Vref, RX VrefLevel [Byte0]: 36
8598 01:24:25.628886 [Byte1]: 36
8599 01:24:25.632880
8600 01:24:25.632962 Set Vref, RX VrefLevel [Byte0]: 37
8601 01:24:25.636116 [Byte1]: 37
8602 01:24:25.640626
8603 01:24:25.640750 Set Vref, RX VrefLevel [Byte0]: 38
8604 01:24:25.644387 [Byte1]: 38
8605 01:24:25.648569
8606 01:24:25.648649 Set Vref, RX VrefLevel [Byte0]: 39
8607 01:24:25.651689 [Byte1]: 39
8608 01:24:25.655658
8609 01:24:25.655740 Set Vref, RX VrefLevel [Byte0]: 40
8610 01:24:25.659151 [Byte1]: 40
8611 01:24:25.663172
8612 01:24:25.663254 Set Vref, RX VrefLevel [Byte0]: 41
8613 01:24:25.667019 [Byte1]: 41
8614 01:24:25.671004
8615 01:24:25.671087 Set Vref, RX VrefLevel [Byte0]: 42
8616 01:24:25.674176 [Byte1]: 42
8617 01:24:25.678345
8618 01:24:25.678426 Set Vref, RX VrefLevel [Byte0]: 43
8619 01:24:25.681825 [Byte1]: 43
8620 01:24:25.685912
8621 01:24:25.685993 Set Vref, RX VrefLevel [Byte0]: 44
8622 01:24:25.689345 [Byte1]: 44
8623 01:24:25.694373
8624 01:24:25.694454 Set Vref, RX VrefLevel [Byte0]: 45
8625 01:24:25.696824 [Byte1]: 45
8626 01:24:25.700941
8627 01:24:25.701036 Set Vref, RX VrefLevel [Byte0]: 46
8628 01:24:25.704197 [Byte1]: 46
8629 01:24:25.708841
8630 01:24:25.708922 Set Vref, RX VrefLevel [Byte0]: 47
8631 01:24:25.711870 [Byte1]: 47
8632 01:24:25.716604
8633 01:24:25.716750 Set Vref, RX VrefLevel [Byte0]: 48
8634 01:24:25.719689 [Byte1]: 48
8635 01:24:25.723787
8636 01:24:25.723872 Set Vref, RX VrefLevel [Byte0]: 49
8637 01:24:25.727262 [Byte1]: 49
8638 01:24:25.731078
8639 01:24:25.731159 Set Vref, RX VrefLevel [Byte0]: 50
8640 01:24:25.734591 [Byte1]: 50
8641 01:24:25.738918
8642 01:24:25.739000 Set Vref, RX VrefLevel [Byte0]: 51
8643 01:24:25.742378 [Byte1]: 51
8644 01:24:25.746700
8645 01:24:25.746786 Set Vref, RX VrefLevel [Byte0]: 52
8646 01:24:25.749624 [Byte1]: 52
8647 01:24:25.754081
8648 01:24:25.754172 Set Vref, RX VrefLevel [Byte0]: 53
8649 01:24:25.757587 [Byte1]: 53
8650 01:24:25.761573
8651 01:24:25.761692 Set Vref, RX VrefLevel [Byte0]: 54
8652 01:24:25.767945 [Byte1]: 54
8653 01:24:25.768034
8654 01:24:25.771646 Set Vref, RX VrefLevel [Byte0]: 55
8655 01:24:25.774613 [Byte1]: 55
8656 01:24:25.774716
8657 01:24:25.778149 Set Vref, RX VrefLevel [Byte0]: 56
8658 01:24:25.781694 [Byte1]: 56
8659 01:24:25.781780
8660 01:24:25.785010 Set Vref, RX VrefLevel [Byte0]: 57
8661 01:24:25.788368 [Byte1]: 57
8662 01:24:25.792047
8663 01:24:25.792129 Set Vref, RX VrefLevel [Byte0]: 58
8664 01:24:25.795397 [Byte1]: 58
8665 01:24:25.799355
8666 01:24:25.799436 Set Vref, RX VrefLevel [Byte0]: 59
8667 01:24:25.803094 [Byte1]: 59
8668 01:24:25.807211
8669 01:24:25.807292 Set Vref, RX VrefLevel [Byte0]: 60
8670 01:24:25.811008 [Byte1]: 60
8671 01:24:25.815055
8672 01:24:25.815136 Set Vref, RX VrefLevel [Byte0]: 61
8673 01:24:25.818117 [Byte1]: 61
8674 01:24:25.822483
8675 01:24:25.822603 Set Vref, RX VrefLevel [Byte0]: 62
8676 01:24:25.825660 [Byte1]: 62
8677 01:24:25.830224
8678 01:24:25.830310 Set Vref, RX VrefLevel [Byte0]: 63
8679 01:24:25.832988 [Byte1]: 63
8680 01:24:25.837645
8681 01:24:25.837728 Set Vref, RX VrefLevel [Byte0]: 64
8682 01:24:25.841005 [Byte1]: 64
8683 01:24:25.844849
8684 01:24:25.844963 Set Vref, RX VrefLevel [Byte0]: 65
8685 01:24:25.848388 [Byte1]: 65
8686 01:24:25.852611
8687 01:24:25.852738 Set Vref, RX VrefLevel [Byte0]: 66
8688 01:24:25.856025 [Byte1]: 66
8689 01:24:25.860435
8690 01:24:25.860519 Set Vref, RX VrefLevel [Byte0]: 67
8691 01:24:25.863272 [Byte1]: 67
8692 01:24:25.867466
8693 01:24:25.867569 Set Vref, RX VrefLevel [Byte0]: 68
8694 01:24:25.871113 [Byte1]: 68
8695 01:24:25.875414
8696 01:24:25.875568 Set Vref, RX VrefLevel [Byte0]: 69
8697 01:24:25.878438 [Byte1]: 69
8698 01:24:25.882903
8699 01:24:25.883012 Set Vref, RX VrefLevel [Byte0]: 70
8700 01:24:25.885976 [Byte1]: 70
8701 01:24:25.890207
8702 01:24:25.890288 Set Vref, RX VrefLevel [Byte0]: 71
8703 01:24:25.893943 [Byte1]: 71
8704 01:24:25.897794
8705 01:24:25.897877 Set Vref, RX VrefLevel [Byte0]: 72
8706 01:24:25.900986 [Byte1]: 72
8707 01:24:25.905482
8708 01:24:25.905574 Set Vref, RX VrefLevel [Byte0]: 73
8709 01:24:25.908970 [Byte1]: 73
8710 01:24:25.913071
8711 01:24:25.913153 Set Vref, RX VrefLevel [Byte0]: 74
8712 01:24:25.916988 [Byte1]: 74
8713 01:24:25.920849
8714 01:24:25.920953 Final RX Vref Byte 0 = 63 to rank0
8715 01:24:25.924257 Final RX Vref Byte 1 = 56 to rank0
8716 01:24:25.927301 Final RX Vref Byte 0 = 63 to rank1
8717 01:24:25.930961 Final RX Vref Byte 1 = 56 to rank1==
8718 01:24:25.933989 Dram Type= 6, Freq= 0, CH_1, rank 0
8719 01:24:25.940604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 01:24:25.940758 ==
8721 01:24:25.940834 DQS Delay:
8722 01:24:25.940919 DQS0 = 0, DQS1 = 0
8723 01:24:25.944655 DQM Delay:
8724 01:24:25.944842 DQM0 = 132, DQM1 = 124
8725 01:24:25.947341 DQ Delay:
8726 01:24:25.950788 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132
8727 01:24:25.954149 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8728 01:24:25.957734 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8729 01:24:25.960807 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8730 01:24:25.960900
8731 01:24:25.960964
8732 01:24:25.961023
8733 01:24:25.964061 [DramC_TX_OE_Calibration] TA2
8734 01:24:25.967385 Original DQ_B0 (3 6) =30, OEN = 27
8735 01:24:25.970769 Original DQ_B1 (3 6) =30, OEN = 27
8736 01:24:25.974155 24, 0x0, End_B0=24 End_B1=24
8737 01:24:25.974238 25, 0x0, End_B0=25 End_B1=25
8738 01:24:25.977664 26, 0x0, End_B0=26 End_B1=26
8739 01:24:25.981032 27, 0x0, End_B0=27 End_B1=27
8740 01:24:25.984321 28, 0x0, End_B0=28 End_B1=28
8741 01:24:25.984424 29, 0x0, End_B0=29 End_B1=29
8742 01:24:25.987772 30, 0x0, End_B0=30 End_B1=30
8743 01:24:25.990994 31, 0x5151, End_B0=30 End_B1=30
8744 01:24:25.994055 Byte0 end_step=30 best_step=27
8745 01:24:25.997238 Byte1 end_step=30 best_step=27
8746 01:24:26.001018 Byte0 TX OE(2T, 0.5T) = (3, 3)
8747 01:24:26.001095 Byte1 TX OE(2T, 0.5T) = (3, 3)
8748 01:24:26.001161
8749 01:24:26.001223
8750 01:24:26.010969 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8751 01:24:26.014205 CH1 RK0: MR19=302, MR18=14FF
8752 01:24:26.020633 CH1_RK0: MR19=0x302, MR18=0x14FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8753 01:24:26.020744
8754 01:24:26.024561 ----->DramcWriteLeveling(PI) begin...
8755 01:24:26.024673 ==
8756 01:24:26.027535 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 01:24:26.030906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 01:24:26.030989 ==
8759 01:24:26.034069 Write leveling (Byte 0): 24 => 24
8760 01:24:26.037936 Write leveling (Byte 1): 26 => 26
8761 01:24:26.041014 DramcWriteLeveling(PI) end<-----
8762 01:24:26.041100
8763 01:24:26.041163 ==
8764 01:24:26.044442 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 01:24:26.047675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 01:24:26.047780 ==
8767 01:24:26.050824 [Gating] SW mode calibration
8768 01:24:26.057196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8769 01:24:26.064550 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8770 01:24:26.067918 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 01:24:26.070793 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 01:24:26.077487 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8773 01:24:26.080738 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8774 01:24:26.084395 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 01:24:26.087863 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 01:24:26.094234 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 01:24:26.097846 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 01:24:26.101253 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 01:24:26.107698 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8780 01:24:26.111290 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
8781 01:24:26.114699 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8782 01:24:26.121004 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 01:24:26.124295 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 01:24:26.127648 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 01:24:26.134781 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 01:24:26.138040 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 01:24:26.141447 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8788 01:24:26.148072 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8789 01:24:26.151360 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8790 01:24:26.154643 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 01:24:26.157893 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 01:24:26.164763 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 01:24:26.168168 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 01:24:26.171159 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 01:24:26.178363 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8796 01:24:26.181158 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8797 01:24:26.184440 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8798 01:24:26.191393 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8799 01:24:26.194662 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 01:24:26.197971 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 01:24:26.204739 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 01:24:26.208299 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 01:24:26.211444 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 01:24:26.218020 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 01:24:26.221116 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 01:24:26.224607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 01:24:26.231597 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 01:24:26.234482 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 01:24:26.237738 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 01:24:26.241776 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 01:24:26.247956 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 01:24:26.251232 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8813 01:24:26.254670 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8814 01:24:26.261342 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 01:24:26.265038 Total UI for P1: 0, mck2ui 16
8816 01:24:26.267845 best dqsien dly found for B0: ( 1, 9, 8)
8817 01:24:26.267974 Total UI for P1: 0, mck2ui 16
8818 01:24:26.274685 best dqsien dly found for B1: ( 1, 9, 12)
8819 01:24:26.278254 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8820 01:24:26.281516 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8821 01:24:26.281617
8822 01:24:26.285127 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8823 01:24:26.288109 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8824 01:24:26.291620 [Gating] SW calibration Done
8825 01:24:26.291734 ==
8826 01:24:26.295222 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 01:24:26.298181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 01:24:26.298298 ==
8829 01:24:26.301596 RX Vref Scan: 0
8830 01:24:26.301714
8831 01:24:26.301817 RX Vref 0 -> 0, step: 1
8832 01:24:26.301916
8833 01:24:26.304838 RX Delay 0 -> 252, step: 8
8834 01:24:26.308203 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8835 01:24:26.314634 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8836 01:24:26.318072 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8837 01:24:26.321768 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8838 01:24:26.325111 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8839 01:24:26.328182 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8840 01:24:26.331915 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8841 01:24:26.338874 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8842 01:24:26.341735 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8843 01:24:26.344948 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8844 01:24:26.348246 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8845 01:24:26.351781 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8846 01:24:26.358429 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8847 01:24:26.361500 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8848 01:24:26.365083 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8849 01:24:26.368385 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8850 01:24:26.368482 ==
8851 01:24:26.371734 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 01:24:26.378361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 01:24:26.378446 ==
8854 01:24:26.378521 DQS Delay:
8855 01:24:26.381664 DQS0 = 0, DQS1 = 0
8856 01:24:26.381737 DQM Delay:
8857 01:24:26.381797 DQM0 = 133, DQM1 = 127
8858 01:24:26.385150 DQ Delay:
8859 01:24:26.388534 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8860 01:24:26.391423 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8861 01:24:26.395371 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8862 01:24:26.398378 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8863 01:24:26.398475
8864 01:24:26.398561
8865 01:24:26.398682 ==
8866 01:24:26.401647 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 01:24:26.405211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 01:24:26.405313 ==
8869 01:24:26.409185
8870 01:24:26.409256
8871 01:24:26.409323 TX Vref Scan disable
8872 01:24:26.411967 == TX Byte 0 ==
8873 01:24:26.415182 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8874 01:24:26.418453 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8875 01:24:26.422633 == TX Byte 1 ==
8876 01:24:26.425180 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8877 01:24:26.428484 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8878 01:24:26.428605 ==
8879 01:24:26.432015 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 01:24:26.438452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 01:24:26.438559 ==
8882 01:24:26.450870
8883 01:24:26.454324 TX Vref early break, caculate TX vref
8884 01:24:26.458106 TX Vref=16, minBit 8, minWin=22, winSum=380
8885 01:24:26.461040 TX Vref=18, minBit 0, minWin=23, winSum=396
8886 01:24:26.464404 TX Vref=20, minBit 0, minWin=24, winSum=399
8887 01:24:26.467779 TX Vref=22, minBit 15, minWin=24, winSum=408
8888 01:24:26.470940 TX Vref=24, minBit 5, minWin=25, winSum=420
8889 01:24:26.477715 TX Vref=26, minBit 0, minWin=26, winSum=426
8890 01:24:26.481145 TX Vref=28, minBit 5, minWin=26, winSum=431
8891 01:24:26.484072 TX Vref=30, minBit 0, minWin=25, winSum=426
8892 01:24:26.487773 TX Vref=32, minBit 0, minWin=25, winSum=423
8893 01:24:26.490904 TX Vref=34, minBit 0, minWin=25, winSum=414
8894 01:24:26.494598 TX Vref=36, minBit 0, minWin=24, winSum=407
8895 01:24:26.501877 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 28
8896 01:24:26.501992
8897 01:24:26.504557 Final TX Range 0 Vref 28
8898 01:24:26.504680
8899 01:24:26.504796 ==
8900 01:24:26.507755 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 01:24:26.511367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 01:24:26.511481 ==
8903 01:24:26.511581
8904 01:24:26.511677
8905 01:24:26.514663 TX Vref Scan disable
8906 01:24:26.521446 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8907 01:24:26.521562 == TX Byte 0 ==
8908 01:24:26.524679 u2DelayCellOfst[0]=17 cells (5 PI)
8909 01:24:26.528122 u2DelayCellOfst[1]=10 cells (3 PI)
8910 01:24:26.531135 u2DelayCellOfst[2]=0 cells (0 PI)
8911 01:24:26.534236 u2DelayCellOfst[3]=7 cells (2 PI)
8912 01:24:26.538219 u2DelayCellOfst[4]=7 cells (2 PI)
8913 01:24:26.540949 u2DelayCellOfst[5]=17 cells (5 PI)
8914 01:24:26.544574 u2DelayCellOfst[6]=17 cells (5 PI)
8915 01:24:26.547616 u2DelayCellOfst[7]=3 cells (1 PI)
8916 01:24:26.551031 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8917 01:24:26.554667 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8918 01:24:26.554787 == TX Byte 1 ==
8919 01:24:26.557949 u2DelayCellOfst[8]=0 cells (0 PI)
8920 01:24:26.561197 u2DelayCellOfst[9]=3 cells (1 PI)
8921 01:24:26.564350 u2DelayCellOfst[10]=10 cells (3 PI)
8922 01:24:26.568170 u2DelayCellOfst[11]=7 cells (2 PI)
8923 01:24:26.571546 u2DelayCellOfst[12]=14 cells (4 PI)
8924 01:24:26.574262 u2DelayCellOfst[13]=14 cells (4 PI)
8925 01:24:26.577755 u2DelayCellOfst[14]=17 cells (5 PI)
8926 01:24:26.581655 u2DelayCellOfst[15]=14 cells (4 PI)
8927 01:24:26.585158 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8928 01:24:26.591556 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8929 01:24:26.591675 DramC Write-DBI on
8930 01:24:26.591778 ==
8931 01:24:26.594884 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 01:24:26.597849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 01:24:26.597967 ==
8934 01:24:26.598068
8935 01:24:26.603830
8936 01:24:26.603944 TX Vref Scan disable
8937 01:24:26.606988 == TX Byte 0 ==
8938 01:24:26.609902 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 01:24:26.611634 == TX Byte 1 ==
8940 01:24:26.615050 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8941 01:24:26.615164 DramC Write-DBI off
8942 01:24:26.615266
8943 01:24:26.617861 [DATLAT]
8944 01:24:26.617973 Freq=1600, CH1 RK1
8945 01:24:26.618076
8946 01:24:26.621214 DATLAT Default: 0xf
8947 01:24:26.621327 0, 0xFFFF, sum = 0
8948 01:24:26.624958 1, 0xFFFF, sum = 0
8949 01:24:26.625073 2, 0xFFFF, sum = 0
8950 01:24:26.628040 3, 0xFFFF, sum = 0
8951 01:24:26.628153 4, 0xFFFF, sum = 0
8952 01:24:26.631408 5, 0xFFFF, sum = 0
8953 01:24:26.631524 6, 0xFFFF, sum = 0
8954 01:24:26.634632 7, 0xFFFF, sum = 0
8955 01:24:26.634749 8, 0xFFFF, sum = 0
8956 01:24:26.638330 9, 0xFFFF, sum = 0
8957 01:24:26.638448 10, 0xFFFF, sum = 0
8958 01:24:26.641549 11, 0xFFFF, sum = 0
8959 01:24:26.644625 12, 0xFFFF, sum = 0
8960 01:24:26.644775 13, 0xFFFF, sum = 0
8961 01:24:26.648133 14, 0x0, sum = 1
8962 01:24:26.648251 15, 0x0, sum = 2
8963 01:24:26.648353 16, 0x0, sum = 3
8964 01:24:26.651145 17, 0x0, sum = 4
8965 01:24:26.651259 best_step = 15
8966 01:24:26.651356
8967 01:24:26.654977 ==
8968 01:24:26.655067 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 01:24:26.661255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 01:24:26.661376 ==
8971 01:24:26.661480 RX Vref Scan: 0
8972 01:24:26.661576
8973 01:24:26.664797 RX Vref 0 -> 0, step: 1
8974 01:24:26.664910
8975 01:24:26.668000 RX Delay 11 -> 252, step: 4
8976 01:24:26.671415 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8977 01:24:26.674911 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8978 01:24:26.681795 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8979 01:24:26.685279 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8980 01:24:26.688099 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8981 01:24:26.691445 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8982 01:24:26.694932 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8983 01:24:26.698378 iDelay=195, Bit 7, Center 124 (75 ~ 174) 100
8984 01:24:26.705037 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8985 01:24:26.708601 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8986 01:24:26.711871 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8987 01:24:26.714976 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8988 01:24:26.721543 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8989 01:24:26.725170 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8990 01:24:26.728163 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8991 01:24:26.731607 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8992 01:24:26.731679 ==
8993 01:24:26.735048 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 01:24:26.738229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 01:24:26.741534 ==
8996 01:24:26.741652 DQS Delay:
8997 01:24:26.741755 DQS0 = 0, DQS1 = 0
8998 01:24:26.744829 DQM Delay:
8999 01:24:26.744942 DQM0 = 130, DQM1 = 126
9000 01:24:26.748281 DQ Delay:
9001 01:24:26.751255 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =130
9002 01:24:26.755270 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =124
9003 01:24:26.758395 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =118
9004 01:24:26.761911 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9005 01:24:26.761994
9006 01:24:26.762059
9007 01:24:26.762117
9008 01:24:26.764831 [DramC_TX_OE_Calibration] TA2
9009 01:24:26.768382 Original DQ_B0 (3 6) =30, OEN = 27
9010 01:24:26.771728 Original DQ_B1 (3 6) =30, OEN = 27
9011 01:24:26.771814 24, 0x0, End_B0=24 End_B1=24
9012 01:24:26.775359 25, 0x0, End_B0=25 End_B1=25
9013 01:24:26.778418 26, 0x0, End_B0=26 End_B1=26
9014 01:24:26.782054 27, 0x0, End_B0=27 End_B1=27
9015 01:24:26.782137 28, 0x0, End_B0=28 End_B1=28
9016 01:24:26.785065 29, 0x0, End_B0=29 End_B1=29
9017 01:24:26.788613 30, 0x0, End_B0=30 End_B1=30
9018 01:24:26.791908 31, 0x4141, End_B0=30 End_B1=30
9019 01:24:26.795190 Byte0 end_step=30 best_step=27
9020 01:24:26.798316 Byte1 end_step=30 best_step=27
9021 01:24:26.798400 Byte0 TX OE(2T, 0.5T) = (3, 3)
9022 01:24:26.801964 Byte1 TX OE(2T, 0.5T) = (3, 3)
9023 01:24:26.802047
9024 01:24:26.802109
9025 01:24:26.811957 [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9026 01:24:26.815101 CH1 RK1: MR19=303, MR18=1016
9027 01:24:26.818589 CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15
9028 01:24:26.822311 [RxdqsGatingPostProcess] freq 1600
9029 01:24:26.828210 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9030 01:24:26.831689 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 01:24:26.835060 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 01:24:26.838423 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 01:24:26.842191 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 01:24:26.845003 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 01:24:26.845116 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 01:24:26.848184 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 01:24:26.851812 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 01:24:26.855501 Pre-setting of DQS Precalculation
9039 01:24:26.861561 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9040 01:24:26.868611 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9041 01:24:26.875117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9042 01:24:26.875221
9043 01:24:26.875294
9044 01:24:26.878464 [Calibration Summary] 3200 Mbps
9045 01:24:26.878541 CH 0, Rank 0
9046 01:24:26.882174 SW Impedance : PASS
9047 01:24:26.884950 DUTY Scan : NO K
9048 01:24:26.885027 ZQ Calibration : PASS
9049 01:24:26.888661 Jitter Meter : NO K
9050 01:24:26.891592 CBT Training : PASS
9051 01:24:26.891666 Write leveling : PASS
9052 01:24:26.895104 RX DQS gating : PASS
9053 01:24:26.898266 RX DQ/DQS(RDDQC) : PASS
9054 01:24:26.898341 TX DQ/DQS : PASS
9055 01:24:26.901653 RX DATLAT : PASS
9056 01:24:26.904941 RX DQ/DQS(Engine): PASS
9057 01:24:26.905022 TX OE : PASS
9058 01:24:26.905083 All Pass.
9059 01:24:26.908496
9060 01:24:26.908587 CH 0, Rank 1
9061 01:24:26.912290 SW Impedance : PASS
9062 01:24:26.912363 DUTY Scan : NO K
9063 01:24:26.915467 ZQ Calibration : PASS
9064 01:24:26.915549 Jitter Meter : NO K
9065 01:24:26.918253 CBT Training : PASS
9066 01:24:26.921688 Write leveling : PASS
9067 01:24:26.921761 RX DQS gating : PASS
9068 01:24:26.924980 RX DQ/DQS(RDDQC) : PASS
9069 01:24:26.928663 TX DQ/DQS : PASS
9070 01:24:26.928778 RX DATLAT : PASS
9071 01:24:26.931667 RX DQ/DQS(Engine): PASS
9072 01:24:26.935469 TX OE : PASS
9073 01:24:26.935562 All Pass.
9074 01:24:26.935625
9075 01:24:26.935685 CH 1, Rank 0
9076 01:24:26.938687 SW Impedance : PASS
9077 01:24:26.947208 DUTY Scan : NO K
9078 01:24:26.947590 ZQ Calibration : PASS
9079 01:24:26.947719 Jitter Meter : NO K
9080 01:24:26.948394 CBT Training : PASS
9081 01:24:26.948497 Write leveling : PASS
9082 01:24:26.952050 RX DQS gating : PASS
9083 01:24:26.955721 RX DQ/DQS(RDDQC) : PASS
9084 01:24:26.955872 TX DQ/DQS : PASS
9085 01:24:26.958591 RX DATLAT : PASS
9086 01:24:26.958676 RX DQ/DQS(Engine): PASS
9087 01:24:26.961937 TX OE : PASS
9088 01:24:26.962032 All Pass.
9089 01:24:26.962094
9090 01:24:26.964985 CH 1, Rank 1
9091 01:24:26.965061 SW Impedance : PASS
9092 01:24:26.968817 DUTY Scan : NO K
9093 01:24:26.972214 ZQ Calibration : PASS
9094 01:24:26.972313 Jitter Meter : NO K
9095 01:24:26.975387 CBT Training : PASS
9096 01:24:26.978825 Write leveling : PASS
9097 01:24:26.978912 RX DQS gating : PASS
9098 01:24:26.982187 RX DQ/DQS(RDDQC) : PASS
9099 01:24:26.985051 TX DQ/DQS : PASS
9100 01:24:26.985136 RX DATLAT : PASS
9101 01:24:26.988904 RX DQ/DQS(Engine): PASS
9102 01:24:26.988992 TX OE : PASS
9103 01:24:26.991969 All Pass.
9104 01:24:26.992043
9105 01:24:26.992103 DramC Write-DBI on
9106 01:24:26.995125 PER_BANK_REFRESH: Hybrid Mode
9107 01:24:26.998612 TX_TRACKING: ON
9108 01:24:27.005915 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9109 01:24:27.015167 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9110 01:24:27.022218 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9111 01:24:27.025820 [FAST_K] Save calibration result to emmc
9112 01:24:27.029104 sync common calibartion params.
9113 01:24:27.029192 sync cbt_mode0:1, 1:1
9114 01:24:27.032786 dram_init: ddr_geometry: 2
9115 01:24:27.035621 dram_init: ddr_geometry: 2
9116 01:24:27.035700 dram_init: ddr_geometry: 2
9117 01:24:27.038992 0:dram_rank_size:100000000
9118 01:24:27.042196 1:dram_rank_size:100000000
9119 01:24:27.049096 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9120 01:24:27.049202 DFS_SHUFFLE_HW_MODE: ON
9121 01:24:27.052482 dramc_set_vcore_voltage set vcore to 725000
9122 01:24:27.056136 Read voltage for 1600, 0
9123 01:24:27.056235 Vio18 = 0
9124 01:24:27.059884 Vcore = 725000
9125 01:24:27.059967 Vdram = 0
9126 01:24:27.060029 Vddq = 0
9127 01:24:27.062806 Vmddr = 0
9128 01:24:27.062884 switch to 3200 Mbps bootup
9129 01:24:27.065866 [DramcRunTimeConfig]
9130 01:24:27.065948 PHYPLL
9131 01:24:27.069051 DPM_CONTROL_AFTERK: ON
9132 01:24:27.069130 PER_BANK_REFRESH: ON
9133 01:24:27.072291 REFRESH_OVERHEAD_REDUCTION: ON
9134 01:24:27.075519 CMD_PICG_NEW_MODE: OFF
9135 01:24:27.075596 XRTWTW_NEW_MODE: ON
9136 01:24:27.079257 XRTRTR_NEW_MODE: ON
9137 01:24:27.079336 TX_TRACKING: ON
9138 01:24:27.082653 RDSEL_TRACKING: OFF
9139 01:24:27.085725 DQS Precalculation for DVFS: ON
9140 01:24:27.085802 RX_TRACKING: OFF
9141 01:24:27.089267 HW_GATING DBG: ON
9142 01:24:27.089344 ZQCS_ENABLE_LP4: ON
9143 01:24:27.092537 RX_PICG_NEW_MODE: ON
9144 01:24:27.092624 TX_PICG_NEW_MODE: ON
9145 01:24:27.095663 ENABLE_RX_DCM_DPHY: ON
9146 01:24:27.099094 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9147 01:24:27.102331 DUMMY_READ_FOR_TRACKING: OFF
9148 01:24:27.102413 !!! SPM_CONTROL_AFTERK: OFF
9149 01:24:27.106415 !!! SPM could not control APHY
9150 01:24:27.108733 IMPEDANCE_TRACKING: ON
9151 01:24:27.108815 TEMP_SENSOR: ON
9152 01:24:27.112489 HW_SAVE_FOR_SR: OFF
9153 01:24:27.115566 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9154 01:24:27.119081 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9155 01:24:27.119176 Read ODT Tracking: ON
9156 01:24:27.122450 Refresh Rate DeBounce: ON
9157 01:24:27.125814 DFS_NO_QUEUE_FLUSH: ON
9158 01:24:27.129466 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9159 01:24:27.129561 ENABLE_DFS_RUNTIME_MRW: OFF
9160 01:24:27.132688 DDR_RESERVE_NEW_MODE: ON
9161 01:24:27.136155 MR_CBT_SWITCH_FREQ: ON
9162 01:24:27.136242 =========================
9163 01:24:27.156058 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9164 01:24:27.159291 dram_init: ddr_geometry: 2
9165 01:24:27.177825 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9166 01:24:27.180845 dram_init: dram init end (result: 0)
9167 01:24:27.187435 DRAM-K: Full calibration passed in 24544 msecs
9168 01:24:27.192228 MRC: failed to locate region type 0.
9169 01:24:27.192356 DRAM rank0 size:0x100000000,
9170 01:24:27.194029 DRAM rank1 size=0x100000000
9171 01:24:27.204159 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9172 01:24:27.210578 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9173 01:24:27.217355 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9174 01:24:27.224635 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9175 01:24:27.227382 DRAM rank0 size:0x100000000,
9176 01:24:27.230878 DRAM rank1 size=0x100000000
9177 01:24:27.230971 CBMEM:
9178 01:24:27.234054 IMD: root @ 0xfffff000 254 entries.
9179 01:24:27.237330 IMD: root @ 0xffffec00 62 entries.
9180 01:24:27.241005 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9181 01:24:27.244397 WARNING: RO_VPD is uninitialized or empty.
9182 01:24:27.250787 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9183 01:24:27.257382 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9184 01:24:27.270369 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9185 01:24:27.281687 BS: romstage times (exec / console): total (unknown) / 24056 ms
9186 01:24:27.281876
9187 01:24:27.281973
9188 01:24:27.292035 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9189 01:24:27.295223 ARM64: Exception handlers installed.
9190 01:24:27.298062 ARM64: Testing exception
9191 01:24:27.302157 ARM64: Done test exception
9192 01:24:27.302260 Enumerating buses...
9193 01:24:27.304705 Show all devs... Before device enumeration.
9194 01:24:27.308597 Root Device: enabled 1
9195 01:24:27.312289 CPU_CLUSTER: 0: enabled 1
9196 01:24:27.312378 CPU: 00: enabled 1
9197 01:24:27.315269 Compare with tree...
9198 01:24:27.315374 Root Device: enabled 1
9199 01:24:27.318370 CPU_CLUSTER: 0: enabled 1
9200 01:24:27.321386 CPU: 00: enabled 1
9201 01:24:27.321471 Root Device scanning...
9202 01:24:27.324920 scan_static_bus for Root Device
9203 01:24:27.328545 CPU_CLUSTER: 0 enabled
9204 01:24:27.332021 scan_static_bus for Root Device done
9205 01:24:27.334766 scan_bus: bus Root Device finished in 8 msecs
9206 01:24:27.334875 done
9207 01:24:27.341399 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9208 01:24:27.345011 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9209 01:24:27.351351 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9210 01:24:27.354611 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9211 01:24:27.358178 Allocating resources...
9212 01:24:27.358286 Reading resources...
9213 01:24:27.364418 Root Device read_resources bus 0 link: 0
9214 01:24:27.364552 DRAM rank0 size:0x100000000,
9215 01:24:27.368102 DRAM rank1 size=0x100000000
9216 01:24:27.371493 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9217 01:24:27.374634 CPU: 00 missing read_resources
9218 01:24:27.378404 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9219 01:24:27.385102 Root Device read_resources bus 0 link: 0 done
9220 01:24:27.385245 Done reading resources.
9221 01:24:27.391119 Show resources in subtree (Root Device)...After reading.
9222 01:24:27.394962 Root Device child on link 0 CPU_CLUSTER: 0
9223 01:24:27.397997 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 01:24:27.408071 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 01:24:27.408209 CPU: 00
9226 01:24:27.411813 Root Device assign_resources, bus 0 link: 0
9227 01:24:27.414511 CPU_CLUSTER: 0 missing set_resources
9228 01:24:27.417760 Root Device assign_resources, bus 0 link: 0 done
9229 01:24:27.421484 Done setting resources.
9230 01:24:27.427879 Show resources in subtree (Root Device)...After assigning values.
9231 01:24:27.431501 Root Device child on link 0 CPU_CLUSTER: 0
9232 01:24:27.434715 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 01:24:27.444845 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 01:24:27.444979 CPU: 00
9235 01:24:27.447985 Done allocating resources.
9236 01:24:27.451453 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9237 01:24:27.454490 Enabling resources...
9238 01:24:27.454604 done.
9239 01:24:27.461395 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9240 01:24:27.461518 Initializing devices...
9241 01:24:27.464467 Root Device init
9242 01:24:27.464589 init hardware done!
9243 01:24:27.468014 0x00000018: ctrlr->caps
9244 01:24:27.471321 52.000 MHz: ctrlr->f_max
9245 01:24:27.471420 0.400 MHz: ctrlr->f_min
9246 01:24:27.474505 0x40ff8080: ctrlr->voltages
9247 01:24:27.474609 sclk: 390625
9248 01:24:27.477617 Bus Width = 1
9249 01:24:27.477708 sclk: 390625
9250 01:24:27.477773 Bus Width = 1
9251 01:24:27.481109 Early init status = 3
9252 01:24:27.484478 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9253 01:24:27.488842 in-header: 03 fc 00 00 01 00 00 00
9254 01:24:27.492745 in-data: 00
9255 01:24:27.495787 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9256 01:24:27.500786 in-header: 03 fd 00 00 00 00 00 00
9257 01:24:27.504063 in-data:
9258 01:24:27.507321 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9259 01:24:27.511585 in-header: 03 fc 00 00 01 00 00 00
9260 01:24:27.514741 in-data: 00
9261 01:24:27.517843 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9262 01:24:27.523636 in-header: 03 fd 00 00 00 00 00 00
9263 01:24:27.527089 in-data:
9264 01:24:27.530565 [SSUSB] Setting up USB HOST controller...
9265 01:24:27.533694 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 01:24:27.536660 [SSUSB] phy power-on done.
9267 01:24:27.540356 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 01:24:27.547435 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 01:24:27.550015 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 01:24:27.557165 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 01:24:27.564070 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 01:24:27.570430 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 01:24:27.576961 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 01:24:27.583505 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9275 01:24:27.583640 SPM: binary array size = 0x9dc
9276 01:24:27.590881 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 01:24:27.597095 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 01:24:27.603927 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 01:24:27.607696 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 01:24:27.610307 configure_display: Starting display init
9281 01:24:27.646742 anx7625_power_on_init: Init interface.
9282 01:24:27.650770 anx7625_disable_pd_protocol: Disabled PD feature.
9283 01:24:27.653929 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 01:24:27.681384 anx7625_start_dp_work: Secure OCM version=00
9285 01:24:27.684382 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 01:24:27.699323 sp_tx_get_edid_block: EDID Block = 1
9287 01:24:27.801967 Extracted contents:
9288 01:24:27.805551 header: 00 ff ff ff ff ff ff 00
9289 01:24:27.808610 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 01:24:27.811815 version: 01 04
9291 01:24:27.815192 basic params: 95 1f 11 78 0a
9292 01:24:27.818168 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 01:24:27.821901 established: 00 00 00
9294 01:24:27.828680 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 01:24:27.831755 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 01:24:27.838012 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 01:24:27.844877 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 01:24:27.851350 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 01:24:27.855192 extensions: 00
9300 01:24:27.855376 checksum: fb
9301 01:24:27.855473
9302 01:24:27.858186 Manufacturer: IVO Model 57d Serial Number 0
9303 01:24:27.861454 Made week 0 of 2020
9304 01:24:27.861570 EDID version: 1.4
9305 01:24:27.865121 Digital display
9306 01:24:27.868433 6 bits per primary color channel
9307 01:24:27.868557 DisplayPort interface
9308 01:24:27.871249 Maximum image size: 31 cm x 17 cm
9309 01:24:27.875630 Gamma: 220%
9310 01:24:27.875752 Check DPMS levels
9311 01:24:27.878479 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 01:24:27.881848 First detailed timing is preferred timing
9313 01:24:27.885205 Established timings supported:
9314 01:24:27.888945 Standard timings supported:
9315 01:24:27.891714 Detailed timings
9316 01:24:27.895132 Hex of detail: 383680a07038204018303c0035ae10000019
9317 01:24:27.898002 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 01:24:27.905042 0780 0798 07c8 0820 hborder 0
9319 01:24:27.908141 0438 043b 0447 0458 vborder 0
9320 01:24:27.911791 -hsync -vsync
9321 01:24:27.911916 Did detailed timing
9322 01:24:27.914833 Hex of detail: 000000000000000000000000000000000000
9323 01:24:27.917952 Manufacturer-specified data, tag 0
9324 01:24:27.924694 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 01:24:27.924838 ASCII string: InfoVision
9326 01:24:27.931688 Hex of detail: 000000fe00523134304e574635205248200a
9327 01:24:27.934930 ASCII string: R140NWF5 RH
9328 01:24:27.935057 Checksum
9329 01:24:27.935153 Checksum: 0xfb (valid)
9330 01:24:27.941898 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 01:24:27.945094 DSI data_rate: 832800000 bps
9332 01:24:27.948279 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 01:24:27.951418 anx7625_parse_edid: pixelclock(138800).
9334 01:24:27.958361 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 01:24:27.961763 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 01:24:27.964981 anx7625_dsi_config: config dsi.
9337 01:24:27.971385 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 01:24:27.983642 anx7625_dsi_config: success to config DSI
9339 01:24:27.987200 anx7625_dp_start: MIPI phy setup OK.
9340 01:24:27.990384 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 01:24:27.993830 mtk_ddp_mode_set invalid vrefresh 60
9342 01:24:27.997446 main_disp_path_setup
9343 01:24:27.997575 ovl_layer_smi_id_en
9344 01:24:28.000560 ovl_layer_smi_id_en
9345 01:24:28.000689 ccorr_config
9346 01:24:28.000788 aal_config
9347 01:24:28.003739 gamma_config
9348 01:24:28.003853 postmask_config
9349 01:24:28.007629 dither_config
9350 01:24:28.010727 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 01:24:28.017168 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 01:24:28.020609 Root Device init finished in 553 msecs
9353 01:24:28.023521 CPU_CLUSTER: 0 init
9354 01:24:28.030194 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 01:24:28.033897 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 01:24:28.037016 APU_MBOX 0x190000b0 = 0x10001
9357 01:24:28.040602 APU_MBOX 0x190001b0 = 0x10001
9358 01:24:28.043944 APU_MBOX 0x190005b0 = 0x10001
9359 01:24:28.047336 APU_MBOX 0x190006b0 = 0x10001
9360 01:24:28.050272 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 01:24:28.062775 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9362 01:24:28.075320 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 01:24:28.081983 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 01:24:28.093915 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9365 01:24:28.102982 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 01:24:28.106201 CPU_CLUSTER: 0 init finished in 81 msecs
9367 01:24:28.109335 Devices initialized
9368 01:24:28.112528 Show all devs... After init.
9369 01:24:28.112652 Root Device: enabled 1
9370 01:24:28.115798 CPU_CLUSTER: 0: enabled 1
9371 01:24:28.119601 CPU: 00: enabled 1
9372 01:24:28.122553 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9373 01:24:28.126156 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 01:24:28.129728 ELOG: NV offset 0x57f000 size 0x1000
9375 01:24:28.136490 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9376 01:24:28.142640 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 01:24:28.146409 ELOG: Event(17) added with size 13 at 2023-08-28 01:24:28 UTC
9378 01:24:28.149359 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 01:24:28.154108 in-header: 03 f8 00 00 2c 00 00 00
9380 01:24:28.167289 in-data: 67 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 01:24:28.173972 ELOG: Event(A1) added with size 10 at 2023-08-28 01:24:28 UTC
9382 01:24:28.180776 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 01:24:28.187640 ELOG: Event(A0) added with size 9 at 2023-08-28 01:24:28 UTC
9384 01:24:28.191015 ELOG: Event(16) added with size 11 at 2023-08-28 01:24:28 UTC
9385 01:24:28.292822 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 01:24:28.296410 elog_add_boot_reason: Logged dev mode boot
9387 01:24:28.302759 BS: BS_POST_DEVICE entry times (exec / console): 100 / 74 ms
9388 01:24:28.302878 Finalize devices...
9389 01:24:28.305933 Devices finalized
9390 01:24:28.310050 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9391 01:24:28.312965 Writing coreboot table at 0xffe64000
9392 01:24:28.319444 0. 000000000010a000-0000000000113fff: RAMSTAGE
9393 01:24:28.322436 1. 0000000040000000-00000000400fffff: RAM
9394 01:24:28.326457 2. 0000000040100000-000000004032afff: RAMSTAGE
9395 01:24:28.329120 3. 000000004032b000-00000000545fffff: RAM
9396 01:24:28.332579 4. 0000000054600000-000000005465ffff: BL31
9397 01:24:28.336285 5. 0000000054660000-00000000ffe63fff: RAM
9398 01:24:28.342988 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9399 01:24:28.346222 7. 0000000100000000-000000023fffffff: RAM
9400 01:24:28.349234 Passing 5 GPIOs to payload:
9401 01:24:28.352834 NAME | PORT | POLARITY | VALUE
9402 01:24:28.359363 EC in RW | 0x000000aa | low | undefined
9403 01:24:28.362966 EC interrupt | 0x00000005 | low | undefined
9404 01:24:28.366048 TPM interrupt | 0x000000ab | high | undefined
9405 01:24:28.372709 SD card detect | 0x00000011 | high | undefined
9406 01:24:28.375938 speaker enable | 0x00000093 | high | undefined
9407 01:24:28.379406 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9408 01:24:28.383163 in-header: 03 f9 00 00 02 00 00 00
9409 01:24:28.386293 in-data: 02 00
9410 01:24:28.389251 ADC[4]: Raw value=900221 ID=7
9411 01:24:28.389363 ADC[3]: Raw value=212967 ID=1
9412 01:24:28.392806 RAM Code: 0x71
9413 01:24:28.395974 ADC[6]: Raw value=74926 ID=0
9414 01:24:28.396112 ADC[5]: Raw value=212229 ID=1
9415 01:24:28.399380 SKU Code: 0x1
9416 01:24:28.402891 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9417 01:24:28.406144 coreboot table: 964 bytes.
9418 01:24:28.409381 IMD ROOT 0. 0xfffff000 0x00001000
9419 01:24:28.412595 IMD SMALL 1. 0xffffe000 0x00001000
9420 01:24:28.416000 RO MCACHE 2. 0xffffc000 0x00001104
9421 01:24:28.419440 CONSOLE 3. 0xfff7c000 0x00080000
9422 01:24:28.422829 FMAP 4. 0xfff7b000 0x00000452
9423 01:24:28.425912 TIME STAMP 5. 0xfff7a000 0x00000910
9424 01:24:28.429725 VBOOT WORK 6. 0xfff66000 0x00014000
9425 01:24:28.432476 RAMOOPS 7. 0xffe66000 0x00100000
9426 01:24:28.436278 COREBOOT 8. 0xffe64000 0x00002000
9427 01:24:28.439591 IMD small region:
9428 01:24:28.442627 IMD ROOT 0. 0xffffec00 0x00000400
9429 01:24:28.445992 VPD 1. 0xffffeb80 0x0000006c
9430 01:24:28.449617 MMC STATUS 2. 0xffffeb60 0x00000004
9431 01:24:28.452515 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9432 01:24:28.456285 Probing TPM: done!
9433 01:24:28.459433 Connected to device vid:did:rid of 1ae0:0028:00
9434 01:24:28.469689 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9435 01:24:28.473395 Initialized TPM device CR50 revision 0
9436 01:24:28.476727 Checking cr50 for pending updates
9437 01:24:28.480301 Reading cr50 TPM mode
9438 01:24:28.489232 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9439 01:24:28.496109 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9440 01:24:28.536190 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9441 01:24:28.539075 Checking segment from ROM address 0x40100000
9442 01:24:28.542362 Checking segment from ROM address 0x4010001c
9443 01:24:28.549457 Loading segment from ROM address 0x40100000
9444 01:24:28.549581 code (compression=0)
9445 01:24:28.556172 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9446 01:24:28.565764 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9447 01:24:28.565901 it's not compressed!
9448 01:24:28.572993 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9449 01:24:28.575895 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9450 01:24:28.596249 Loading segment from ROM address 0x4010001c
9451 01:24:28.596389 Entry Point 0x80000000
9452 01:24:28.599827 Loaded segments
9453 01:24:28.603157 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9454 01:24:28.609861 Jumping to boot code at 0x80000000(0xffe64000)
9455 01:24:28.616974 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9456 01:24:28.623110 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9457 01:24:28.630736 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9458 01:24:28.634258 Checking segment from ROM address 0x40100000
9459 01:24:28.637659 Checking segment from ROM address 0x4010001c
9460 01:24:28.640626 Loading segment from ROM address 0x40100000
9461 01:24:28.644367 code (compression=1)
9462 01:24:28.650916 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9463 01:24:28.660882 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9464 01:24:28.661021 using LZMA
9465 01:24:28.669125 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9466 01:24:28.675653 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9467 01:24:28.678916 Loading segment from ROM address 0x4010001c
9468 01:24:28.679023 Entry Point 0x54601000
9469 01:24:28.682337 Loaded segments
9470 01:24:28.685663 NOTICE: MT8192 bl31_setup
9471 01:24:28.692595 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9472 01:24:28.695998 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9473 01:24:28.699408 WARNING: region 0:
9474 01:24:28.702591 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 01:24:28.702693 WARNING: region 1:
9476 01:24:28.709168 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9477 01:24:28.713000 WARNING: region 2:
9478 01:24:28.716141 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9479 01:24:28.719392 WARNING: region 3:
9480 01:24:28.722859 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 01:24:28.725839 WARNING: region 4:
9482 01:24:28.729944 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 01:24:28.732810 WARNING: region 5:
9484 01:24:28.736254 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 01:24:28.739332 WARNING: region 6:
9486 01:24:28.742733 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 01:24:28.742837 WARNING: region 7:
9488 01:24:28.749643 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 01:24:28.756090 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9490 01:24:28.759875 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9491 01:24:28.762746 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9492 01:24:28.766313 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9493 01:24:28.773254 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9494 01:24:28.776850 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9495 01:24:28.783090 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9496 01:24:28.786206 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9497 01:24:28.789677 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9498 01:24:28.796557 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9499 01:24:28.799873 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9500 01:24:28.803475 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9501 01:24:28.809804 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9502 01:24:28.813111 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9503 01:24:28.816516 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9504 01:24:28.823390 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9505 01:24:28.826537 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9506 01:24:28.833312 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9507 01:24:28.836571 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9508 01:24:28.840409 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9509 01:24:28.846687 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9510 01:24:28.850154 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9511 01:24:28.853294 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9512 01:24:28.860417 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9513 01:24:28.863670 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9514 01:24:28.870542 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9515 01:24:28.873433 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9516 01:24:28.876749 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9517 01:24:28.883705 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9518 01:24:28.886904 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9519 01:24:28.893955 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9520 01:24:28.897493 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9521 01:24:28.901019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9522 01:24:28.903732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9523 01:24:28.910735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9524 01:24:28.914031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9525 01:24:28.917769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9526 01:24:28.920552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9527 01:24:28.927430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9528 01:24:28.930548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9529 01:24:28.933956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9530 01:24:28.937280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9531 01:24:28.940535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9532 01:24:28.947440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9533 01:24:28.950744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9534 01:24:28.954367 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9535 01:24:28.961099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9536 01:24:28.964064 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9537 01:24:28.967637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9538 01:24:28.974731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9539 01:24:28.977385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9540 01:24:28.980814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9541 01:24:28.987839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9542 01:24:28.991171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9543 01:24:28.997855 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9544 01:24:29.001711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9545 01:24:29.007957 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9546 01:24:29.010915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9547 01:24:29.014721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9548 01:24:29.020965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9549 01:24:29.024629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9550 01:24:29.031170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9551 01:24:29.034546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9552 01:24:29.041298 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9553 01:24:29.044450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9554 01:24:29.048277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9555 01:24:29.054521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9556 01:24:29.058640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9557 01:24:29.065165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9558 01:24:29.068015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9559 01:24:29.071644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9560 01:24:29.078140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9561 01:24:29.081961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9562 01:24:29.088404 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9563 01:24:29.091764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9564 01:24:29.095202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9565 01:24:29.101694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9566 01:24:29.105145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9567 01:24:29.111899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9568 01:24:29.115703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9569 01:24:29.122434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9570 01:24:29.125572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9571 01:24:29.129029 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9572 01:24:29.135841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9573 01:24:29.139267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9574 01:24:29.145826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9575 01:24:29.149049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9576 01:24:29.152554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9577 01:24:29.159128 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9578 01:24:29.162736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9579 01:24:29.169321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9580 01:24:29.172745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9581 01:24:29.179856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9582 01:24:29.182873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9583 01:24:29.186294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9584 01:24:29.192618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9585 01:24:29.196290 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9586 01:24:29.199531 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9587 01:24:29.206601 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9588 01:24:29.209352 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9589 01:24:29.212718 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9590 01:24:29.219618 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9591 01:24:29.222989 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9592 01:24:29.226171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9593 01:24:29.232838 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9594 01:24:29.236211 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9595 01:24:29.239885 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9596 01:24:29.246343 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9597 01:24:29.249930 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9598 01:24:29.256738 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9599 01:24:29.260296 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9600 01:24:29.263419 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9601 01:24:29.270087 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9602 01:24:29.273175 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9603 01:24:29.279998 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9604 01:24:29.283448 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9605 01:24:29.286939 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9606 01:24:29.290143 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9607 01:24:29.296661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9608 01:24:29.300225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9609 01:24:29.303335 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9610 01:24:29.307646 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9611 01:24:29.313544 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9612 01:24:29.317523 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9613 01:24:29.320556 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9614 01:24:29.327431 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9615 01:24:29.330759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9616 01:24:29.333676 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9617 01:24:29.340138 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9618 01:24:29.343873 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9619 01:24:29.350527 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9620 01:24:29.354017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9621 01:24:29.357347 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9622 01:24:29.363919 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9623 01:24:29.367211 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9624 01:24:29.371026 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9625 01:24:29.377163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9626 01:24:29.380582 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9627 01:24:29.387150 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9628 01:24:29.391167 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9629 01:24:29.394237 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9630 01:24:29.401022 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9631 01:24:29.404468 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9632 01:24:29.407399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9633 01:24:29.414550 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9634 01:24:29.418188 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9635 01:24:29.424259 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9636 01:24:29.427903 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9637 01:24:29.431109 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9638 01:24:29.437882 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9639 01:24:29.441185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9640 01:24:29.444750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9641 01:24:29.451570 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9642 01:24:29.455079 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9643 01:24:29.461638 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9644 01:24:29.465181 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9645 01:24:29.468306 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9646 01:24:29.474511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9647 01:24:29.477801 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9648 01:24:29.481260 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9649 01:24:29.487980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9650 01:24:29.491091 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9651 01:24:29.498606 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9652 01:24:29.501076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9653 01:24:29.504344 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9654 01:24:29.511222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9655 01:24:29.514435 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9656 01:24:29.521149 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9657 01:24:29.524785 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9658 01:24:29.528076 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9659 01:24:29.534489 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9660 01:24:29.538148 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9661 01:24:29.541283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9662 01:24:29.548229 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9663 01:24:29.551578 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9664 01:24:29.558201 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9665 01:24:29.561734 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9666 01:24:29.564821 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9667 01:24:29.571229 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9668 01:24:29.574909 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9669 01:24:29.581911 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9670 01:24:29.585143 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9671 01:24:29.588008 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9672 01:24:29.594898 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9673 01:24:29.598396 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9674 01:24:29.601414 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9675 01:24:29.608131 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9676 01:24:29.611386 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9677 01:24:29.617922 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9678 01:24:29.621328 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9679 01:24:29.624882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9680 01:24:29.631811 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9681 01:24:29.634592 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9682 01:24:29.641677 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9683 01:24:29.644865 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9684 01:24:29.651524 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9685 01:24:29.654917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9686 01:24:29.658102 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9687 01:24:29.665003 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9688 01:24:29.668260 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9689 01:24:29.674892 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9690 01:24:29.678154 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9691 01:24:29.681536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9692 01:24:29.688021 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9693 01:24:29.691506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9694 01:24:29.698276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9695 01:24:29.701759 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9696 01:24:29.704747 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9697 01:24:29.711436 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9698 01:24:29.715109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9699 01:24:29.721562 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9700 01:24:29.724991 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9701 01:24:29.728220 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9702 01:24:29.734905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9703 01:24:29.738350 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9704 01:24:29.744895 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9705 01:24:29.748601 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9706 01:24:29.751827 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9707 01:24:29.758472 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9708 01:24:29.761430 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9709 01:24:29.768481 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9710 01:24:29.772020 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9711 01:24:29.778483 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9712 01:24:29.782011 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9713 01:24:29.785263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9714 01:24:29.791829 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9715 01:24:29.795077 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9716 01:24:29.801499 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9717 01:24:29.804945 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9718 01:24:29.808452 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9719 01:24:29.811651 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9720 01:24:29.818625 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9721 01:24:29.821611 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9722 01:24:29.825061 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9723 01:24:29.828722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9724 01:24:29.834955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9725 01:24:29.838464 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9726 01:24:29.844889 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9727 01:24:29.848684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9728 01:24:29.851837 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9729 01:24:29.858610 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9730 01:24:29.861795 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9731 01:24:29.865256 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9732 01:24:29.871816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9733 01:24:29.875024 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9734 01:24:29.878407 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9735 01:24:29.885211 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9736 01:24:29.888567 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9737 01:24:29.891921 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9738 01:24:29.898698 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9739 01:24:29.902011 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9740 01:24:29.908682 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9741 01:24:29.912165 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9742 01:24:29.915235 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9743 01:24:29.921988 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9744 01:24:29.925420 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9745 01:24:29.928920 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9746 01:24:29.935503 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9747 01:24:29.938702 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9748 01:24:29.941842 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9749 01:24:29.948662 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9750 01:24:29.951676 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9751 01:24:29.958816 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9752 01:24:29.962417 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9753 01:24:29.965655 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9754 01:24:29.971772 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9755 01:24:29.975708 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9756 01:24:29.978517 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9757 01:24:29.985354 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9758 01:24:29.988794 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9759 01:24:29.992277 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9760 01:24:29.995324 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9761 01:24:29.998522 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9762 01:24:30.001766 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9763 01:24:30.008511 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9764 01:24:30.012259 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9765 01:24:30.015559 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9766 01:24:30.022230 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9767 01:24:30.025321 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9768 01:24:30.028880 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9769 01:24:30.032125 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9770 01:24:30.038949 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9771 01:24:30.042223 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9772 01:24:30.045685 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9773 01:24:30.052054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9774 01:24:30.055282 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9775 01:24:30.062326 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9776 01:24:30.065517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9777 01:24:30.072260 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9778 01:24:30.075585 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9779 01:24:30.079000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9780 01:24:30.085864 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9781 01:24:30.088650 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9782 01:24:30.095554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9783 01:24:30.098572 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9784 01:24:30.101915 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9785 01:24:30.108680 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9786 01:24:30.112038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9787 01:24:30.115377 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9788 01:24:30.122084 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9789 01:24:30.125278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9790 01:24:30.132119 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9791 01:24:30.135605 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9792 01:24:30.141965 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9793 01:24:30.145512 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9794 01:24:30.149234 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9795 01:24:30.155351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9796 01:24:30.158938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9797 01:24:30.165393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9798 01:24:30.168861 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9799 01:24:30.172195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9800 01:24:30.179129 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9801 01:24:30.182356 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9802 01:24:30.188742 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9803 01:24:30.191987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9804 01:24:30.195522 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9805 01:24:30.202188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9806 01:24:30.205763 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9807 01:24:30.212642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9808 01:24:30.215689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9809 01:24:30.218770 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9810 01:24:30.225547 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9811 01:24:30.228871 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9812 01:24:30.235726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9813 01:24:30.239103 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9814 01:24:30.242253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9815 01:24:30.248807 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9816 01:24:30.252409 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9817 01:24:30.258995 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9818 01:24:30.262127 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9819 01:24:30.265645 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9820 01:24:30.272493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9821 01:24:30.275523 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9822 01:24:30.282542 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9823 01:24:30.285597 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9824 01:24:30.288983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9825 01:24:30.295965 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9826 01:24:30.298857 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9827 01:24:30.305609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9828 01:24:30.309495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9829 01:24:30.312614 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9830 01:24:30.319514 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9831 01:24:30.322243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9832 01:24:30.329056 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9833 01:24:30.332550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9834 01:24:30.335959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9835 01:24:30.342477 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9836 01:24:30.346171 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9837 01:24:30.349590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9838 01:24:30.356196 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9839 01:24:30.359732 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9840 01:24:30.366455 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9841 01:24:30.369483 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9842 01:24:30.372504 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9843 01:24:30.379298 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9844 01:24:30.382611 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9845 01:24:30.389226 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9846 01:24:30.392639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9847 01:24:30.399417 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9848 01:24:30.402375 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9849 01:24:30.409160 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9850 01:24:30.412407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9851 01:24:30.415781 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9852 01:24:30.422421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9853 01:24:30.426056 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9854 01:24:30.432554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9855 01:24:30.435880 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9856 01:24:30.442331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9857 01:24:30.445939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9858 01:24:30.449263 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9859 01:24:30.455728 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9860 01:24:30.459265 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9861 01:24:30.465934 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9862 01:24:30.469511 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9863 01:24:30.476020 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9864 01:24:30.479435 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9865 01:24:30.482959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9866 01:24:30.489875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9867 01:24:30.493225 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9868 01:24:30.499247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9869 01:24:30.502625 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9870 01:24:30.509458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9871 01:24:30.512773 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9872 01:24:30.516142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9873 01:24:30.523032 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9874 01:24:30.525831 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9875 01:24:30.532649 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9876 01:24:30.536236 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9877 01:24:30.539534 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9878 01:24:30.546799 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9879 01:24:30.549521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9880 01:24:30.556187 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9881 01:24:30.559813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9882 01:24:30.563093 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9883 01:24:30.569793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9884 01:24:30.573287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9885 01:24:30.579944 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9886 01:24:30.583357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9887 01:24:30.590081 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9888 01:24:30.592978 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9889 01:24:30.599666 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9890 01:24:30.603002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9891 01:24:30.606433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9892 01:24:30.613113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9893 01:24:30.616513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9894 01:24:30.623303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9895 01:24:30.627011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9896 01:24:30.629669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9897 01:24:30.636508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9898 01:24:30.639631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9899 01:24:30.646320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9900 01:24:30.649916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9901 01:24:30.656423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9902 01:24:30.659730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9903 01:24:30.666495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9904 01:24:30.669870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9905 01:24:30.676742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9906 01:24:30.679885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9907 01:24:30.686684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9908 01:24:30.690211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9909 01:24:30.696416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9910 01:24:30.700238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9911 01:24:30.706499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9912 01:24:30.710106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9913 01:24:30.716725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9914 01:24:30.719727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9915 01:24:30.726557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9916 01:24:30.729728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9917 01:24:30.736892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9918 01:24:30.740069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9919 01:24:30.746418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9920 01:24:30.749910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9921 01:24:30.756884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9922 01:24:30.760355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9923 01:24:30.763351 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9924 01:24:30.767039 INFO: [APUAPC] vio 0
9925 01:24:30.769921 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9926 01:24:30.776500 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9927 01:24:30.780276 INFO: [APUAPC] D0_APC_0: 0x400510
9928 01:24:30.783900 INFO: [APUAPC] D0_APC_1: 0x0
9929 01:24:30.787014 INFO: [APUAPC] D0_APC_2: 0x1540
9930 01:24:30.787121 INFO: [APUAPC] D0_APC_3: 0x0
9931 01:24:30.790433 INFO: [APUAPC] D1_APC_0: 0xffffffff
9932 01:24:30.793193 INFO: [APUAPC] D1_APC_1: 0xffffffff
9933 01:24:30.797044 INFO: [APUAPC] D1_APC_2: 0x3fffff
9934 01:24:30.800127 INFO: [APUAPC] D1_APC_3: 0x0
9935 01:24:30.803829 INFO: [APUAPC] D2_APC_0: 0xffffffff
9936 01:24:30.806708 INFO: [APUAPC] D2_APC_1: 0xffffffff
9937 01:24:30.810456 INFO: [APUAPC] D2_APC_2: 0x3fffff
9938 01:24:30.813643 INFO: [APUAPC] D2_APC_3: 0x0
9939 01:24:30.816963 INFO: [APUAPC] D3_APC_0: 0xffffffff
9940 01:24:30.820179 INFO: [APUAPC] D3_APC_1: 0xffffffff
9941 01:24:30.823517 INFO: [APUAPC] D3_APC_2: 0x3fffff
9942 01:24:30.827410 INFO: [APUAPC] D3_APC_3: 0x0
9943 01:24:30.830283 INFO: [APUAPC] D4_APC_0: 0xffffffff
9944 01:24:30.833585 INFO: [APUAPC] D4_APC_1: 0xffffffff
9945 01:24:30.836954 INFO: [APUAPC] D4_APC_2: 0x3fffff
9946 01:24:30.840369 INFO: [APUAPC] D4_APC_3: 0x0
9947 01:24:30.843510 INFO: [APUAPC] D5_APC_0: 0xffffffff
9948 01:24:30.847158 INFO: [APUAPC] D5_APC_1: 0xffffffff
9949 01:24:30.849950 INFO: [APUAPC] D5_APC_2: 0x3fffff
9950 01:24:30.853874 INFO: [APUAPC] D5_APC_3: 0x0
9951 01:24:30.857080 INFO: [APUAPC] D6_APC_0: 0xffffffff
9952 01:24:30.860732 INFO: [APUAPC] D6_APC_1: 0xffffffff
9953 01:24:30.863830 INFO: [APUAPC] D6_APC_2: 0x3fffff
9954 01:24:30.866954 INFO: [APUAPC] D6_APC_3: 0x0
9955 01:24:30.870180 INFO: [APUAPC] D7_APC_0: 0xffffffff
9956 01:24:30.873533 INFO: [APUAPC] D7_APC_1: 0xffffffff
9957 01:24:30.876844 INFO: [APUAPC] D7_APC_2: 0x3fffff
9958 01:24:30.880145 INFO: [APUAPC] D7_APC_3: 0x0
9959 01:24:30.883602 INFO: [APUAPC] D8_APC_0: 0xffffffff
9960 01:24:30.886793 INFO: [APUAPC] D8_APC_1: 0xffffffff
9961 01:24:30.890154 INFO: [APUAPC] D8_APC_2: 0x3fffff
9962 01:24:30.893291 INFO: [APUAPC] D8_APC_3: 0x0
9963 01:24:30.896606 INFO: [APUAPC] D9_APC_0: 0xffffffff
9964 01:24:30.900024 INFO: [APUAPC] D9_APC_1: 0xffffffff
9965 01:24:30.903615 INFO: [APUAPC] D9_APC_2: 0x3fffff
9966 01:24:30.906583 INFO: [APUAPC] D9_APC_3: 0x0
9967 01:24:30.910420 INFO: [APUAPC] D10_APC_0: 0xffffffff
9968 01:24:30.913576 INFO: [APUAPC] D10_APC_1: 0xffffffff
9969 01:24:30.917154 INFO: [APUAPC] D10_APC_2: 0x3fffff
9970 01:24:30.920146 INFO: [APUAPC] D10_APC_3: 0x0
9971 01:24:30.923605 INFO: [APUAPC] D11_APC_0: 0xffffffff
9972 01:24:30.926961 INFO: [APUAPC] D11_APC_1: 0xffffffff
9973 01:24:30.930399 INFO: [APUAPC] D11_APC_2: 0x3fffff
9974 01:24:30.933700 INFO: [APUAPC] D11_APC_3: 0x0
9975 01:24:30.937093 INFO: [APUAPC] D12_APC_0: 0xffffffff
9976 01:24:30.940140 INFO: [APUAPC] D12_APC_1: 0xffffffff
9977 01:24:30.943717 INFO: [APUAPC] D12_APC_2: 0x3fffff
9978 01:24:30.946680 INFO: [APUAPC] D12_APC_3: 0x0
9979 01:24:30.950138 INFO: [APUAPC] D13_APC_0: 0xffffffff
9980 01:24:30.953364 INFO: [APUAPC] D13_APC_1: 0xffffffff
9981 01:24:30.956749 INFO: [APUAPC] D13_APC_2: 0x3fffff
9982 01:24:30.960381 INFO: [APUAPC] D13_APC_3: 0x0
9983 01:24:30.963792 INFO: [APUAPC] D14_APC_0: 0xffffffff
9984 01:24:30.967123 INFO: [APUAPC] D14_APC_1: 0xffffffff
9985 01:24:30.970256 INFO: [APUAPC] D14_APC_2: 0x3fffff
9986 01:24:30.973724 INFO: [APUAPC] D14_APC_3: 0x0
9987 01:24:30.977068 INFO: [APUAPC] D15_APC_0: 0xffffffff
9988 01:24:30.980333 INFO: [APUAPC] D15_APC_1: 0xffffffff
9989 01:24:30.983727 INFO: [APUAPC] D15_APC_2: 0x3fffff
9990 01:24:30.987103 INFO: [APUAPC] D15_APC_3: 0x0
9991 01:24:30.987220 INFO: [APUAPC] APC_CON: 0x4
9992 01:24:30.990265 INFO: [NOCDAPC] D0_APC_0: 0x0
9993 01:24:30.994019 INFO: [NOCDAPC] D0_APC_1: 0x0
9994 01:24:30.996866 INFO: [NOCDAPC] D1_APC_0: 0x0
9995 01:24:31.000476 INFO: [NOCDAPC] D1_APC_1: 0xfff
9996 01:24:31.003827 INFO: [NOCDAPC] D2_APC_0: 0x0
9997 01:24:31.007271 INFO: [NOCDAPC] D2_APC_1: 0xfff
9998 01:24:31.010238 INFO: [NOCDAPC] D3_APC_0: 0x0
9999 01:24:31.013557 INFO: [NOCDAPC] D3_APC_1: 0xfff
10000 01:24:31.013648 INFO: [NOCDAPC] D4_APC_0: 0x0
10001 01:24:31.017190 INFO: [NOCDAPC] D4_APC_1: 0xfff
10002 01:24:31.020548 INFO: [NOCDAPC] D5_APC_0: 0x0
10003 01:24:31.024015 INFO: [NOCDAPC] D5_APC_1: 0xfff
10004 01:24:31.026925 INFO: [NOCDAPC] D6_APC_0: 0x0
10005 01:24:31.030172 INFO: [NOCDAPC] D6_APC_1: 0xfff
10006 01:24:31.033928 INFO: [NOCDAPC] D7_APC_0: 0x0
10007 01:24:31.036967 INFO: [NOCDAPC] D7_APC_1: 0xfff
10008 01:24:31.040436 INFO: [NOCDAPC] D8_APC_0: 0x0
10009 01:24:31.043684 INFO: [NOCDAPC] D8_APC_1: 0xfff
10010 01:24:31.043817 INFO: [NOCDAPC] D9_APC_0: 0x0
10011 01:24:31.047100 INFO: [NOCDAPC] D9_APC_1: 0xfff
10012 01:24:31.050327 INFO: [NOCDAPC] D10_APC_0: 0x0
10013 01:24:31.053970 INFO: [NOCDAPC] D10_APC_1: 0xfff
10014 01:24:31.057179 INFO: [NOCDAPC] D11_APC_0: 0x0
10015 01:24:31.060648 INFO: [NOCDAPC] D11_APC_1: 0xfff
10016 01:24:31.063891 INFO: [NOCDAPC] D12_APC_0: 0x0
10017 01:24:31.067358 INFO: [NOCDAPC] D12_APC_1: 0xfff
10018 01:24:31.070588 INFO: [NOCDAPC] D13_APC_0: 0x0
10019 01:24:31.073692 INFO: [NOCDAPC] D13_APC_1: 0xfff
10020 01:24:31.077151 INFO: [NOCDAPC] D14_APC_0: 0x0
10021 01:24:31.080540 INFO: [NOCDAPC] D14_APC_1: 0xfff
10022 01:24:31.083720 INFO: [NOCDAPC] D15_APC_0: 0x0
10023 01:24:31.086991 INFO: [NOCDAPC] D15_APC_1: 0xfff
10024 01:24:31.087106 INFO: [NOCDAPC] APC_CON: 0x4
10025 01:24:31.090532 INFO: [APUAPC] set_apusys_apc done
10026 01:24:31.093803 INFO: [DEVAPC] devapc_init done
10027 01:24:31.100543 INFO: GICv3 without legacy support detected.
10028 01:24:31.104145 INFO: ARM GICv3 driver initialized in EL3
10029 01:24:31.107681 INFO: Maximum SPI INTID supported: 639
10030 01:24:31.110436 INFO: BL31: Initializing runtime services
10031 01:24:31.117528 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10032 01:24:31.120697 INFO: SPM: enable CPC mode
10033 01:24:31.124342 INFO: mcdi ready for mcusys-off-idle and system suspend
10034 01:24:31.130480 INFO: BL31: Preparing for EL3 exit to normal world
10035 01:24:31.134074 INFO: Entry point address = 0x80000000
10036 01:24:31.134173 INFO: SPSR = 0x8
10037 01:24:31.140885
10038 01:24:31.140988
10039 01:24:31.141062
10040 01:24:31.144345 Starting depthcharge on Spherion...
10041 01:24:31.144455
10042 01:24:31.144546 Wipe memory regions:
10043 01:24:31.144635
10044 01:24:31.145336 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10045 01:24:31.145490 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10046 01:24:31.145621 Setting prompt string to ['asurada:']
10047 01:24:31.145729 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10048 01:24:31.146935 [0x00000040000000, 0x00000054600000)
10049 01:24:31.269855
10050 01:24:31.269984 [0x00000054660000, 0x00000080000000)
10051 01:24:31.529785
10052 01:24:31.529913 [0x000000821a7280, 0x000000ffe64000)
10053 01:24:32.274883
10054 01:24:32.275043 [0x00000100000000, 0x00000240000000)
10055 01:24:34.164130
10056 01:24:34.167182 Initializing XHCI USB controller at 0x11200000.
10057 01:24:35.206277
10058 01:24:35.209655 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10059 01:24:35.209743
10060 01:24:35.209805
10061 01:24:35.209864
10062 01:24:35.210142 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 01:24:35.310480 asurada: tftpboot 192.168.201.1 11368532/tftp-deploy-oxmtxrpo/kernel/image.itb 11368532/tftp-deploy-oxmtxrpo/kernel/cmdline
10065 01:24:35.310632 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 01:24:35.310717 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10067 01:24:35.315016 tftpboot 192.168.201.1 11368532/tftp-deploy-oxmtxrpo/kernel/image.ittp-deploy-oxmtxrpo/kernel/cmdline
10068 01:24:35.315104
10069 01:24:35.315169 Waiting for link
10070 01:24:35.475320
10071 01:24:35.475458 R8152: Initializing
10072 01:24:35.475526
10073 01:24:35.478665 Version 6 (ocp_data = 5c30)
10074 01:24:35.478749
10075 01:24:35.481945 R8152: Done initializing
10076 01:24:35.482027
10077 01:24:35.482091 Adding net device
10078 01:24:37.447846
10079 01:24:37.448007 done.
10080 01:24:37.448112
10081 01:24:37.448212 MAC: 00:24:32:30:78:52
10082 01:24:37.448298
10083 01:24:37.450771 Sending DHCP discover... done.
10084 01:24:37.450874
10085 01:24:37.454624 Waiting for reply... done.
10086 01:24:37.454738
10087 01:24:37.457588 Sending DHCP request... done.
10088 01:24:37.457708
10089 01:24:37.461459 Waiting for reply... done.
10090 01:24:37.461571
10091 01:24:37.461638 My ip is 192.168.201.14
10092 01:24:37.461701
10093 01:24:37.465242 The DHCP server ip is 192.168.201.1
10094 01:24:37.465343
10095 01:24:37.471730 TFTP server IP predefined by user: 192.168.201.1
10096 01:24:37.471812
10097 01:24:37.477935 Bootfile predefined by user: 11368532/tftp-deploy-oxmtxrpo/kernel/image.itb
10098 01:24:37.478022
10099 01:24:37.481779 Sending tftp read request... done.
10100 01:24:37.481934
10101 01:24:37.485270 Waiting for the transfer...
10102 01:24:37.485371
10103 01:24:38.015634 00000000 ################################################################
10104 01:24:38.015770
10105 01:24:38.532005 00080000 ################################################################
10106 01:24:38.532170
10107 01:24:39.048033 00100000 ################################################################
10108 01:24:39.048191
10109 01:24:39.563152 00180000 ################################################################
10110 01:24:39.563343
10111 01:24:40.079467 00200000 ################################################################
10112 01:24:40.079605
10113 01:24:40.594298 00280000 ################################################################
10114 01:24:40.594559
10115 01:24:41.130330 00300000 ################################################################
10116 01:24:41.130471
10117 01:24:41.643740 00380000 ################################################################
10118 01:24:41.643871
10119 01:24:42.161139 00400000 ################################################################
10120 01:24:42.161282
10121 01:24:42.698302 00480000 ################################################################
10122 01:24:42.698477
10123 01:24:43.249875 00500000 ################################################################
10124 01:24:43.250032
10125 01:24:43.802154 00580000 ################################################################
10126 01:24:43.802299
10127 01:24:44.318122 00600000 ################################################################
10128 01:24:44.318262
10129 01:24:44.855141 00680000 ################################################################
10130 01:24:44.855294
10131 01:24:45.380106 00700000 ################################################################
10132 01:24:45.380256
10133 01:24:45.895882 00780000 ################################################################
10134 01:24:45.896018
10135 01:24:46.413013 00800000 ################################################################
10136 01:24:46.413158
10137 01:24:46.942371 00880000 ################################################################
10138 01:24:46.942505
10139 01:24:47.473940 00900000 ################################################################
10140 01:24:47.474069
10141 01:24:48.009651 00980000 ################################################################
10142 01:24:48.009790
10143 01:24:48.550604 00a00000 ################################################################
10144 01:24:48.550735
10145 01:24:49.070643 00a80000 ################################################################
10146 01:24:49.070777
10147 01:24:49.593219 00b00000 ################################################################
10148 01:24:49.593385
10149 01:24:50.130717 00b80000 ################################################################
10150 01:24:50.130930
10151 01:24:50.656550 00c00000 ################################################################
10152 01:24:50.656748
10153 01:24:51.176499 00c80000 ################################################################
10154 01:24:51.176641
10155 01:24:51.702478 00d00000 ################################################################
10156 01:24:51.702653
10157 01:24:52.237880 00d80000 ################################################################
10158 01:24:52.238033
10159 01:24:52.759697 00e00000 ################################################################
10160 01:24:52.759853
10161 01:24:53.301540 00e80000 ################################################################
10162 01:24:53.301681
10163 01:24:53.822169 00f00000 ################################################################
10164 01:24:53.822359
10165 01:24:54.374802 00f80000 ################################################################
10166 01:24:54.374938
10167 01:24:54.910737 01000000 ################################################################
10168 01:24:54.910895
10169 01:24:55.426162 01080000 ################################################################
10170 01:24:55.426316
10171 01:24:55.941752 01100000 ################################################################
10172 01:24:55.941901
10173 01:24:56.462539 01180000 ################################################################
10174 01:24:56.462684
10175 01:24:56.988020 01200000 ################################################################
10176 01:24:56.988181
10177 01:24:57.520765 01280000 ################################################################
10178 01:24:57.520935
10179 01:24:58.077567 01300000 ################################################################
10180 01:24:58.077711
10181 01:24:58.617673 01380000 ################################################################
10182 01:24:58.617845
10183 01:24:59.134259 01400000 ################################################################
10184 01:24:59.134396
10185 01:24:59.675104 01480000 ################################################################
10186 01:24:59.675252
10187 01:25:00.196619 01500000 ################################################################
10188 01:25:00.196769
10189 01:25:00.721118 01580000 ################################################################
10190 01:25:00.721256
10191 01:25:01.245806 01600000 ################################################################
10192 01:25:01.245944
10193 01:25:01.763540 01680000 ################################################################
10194 01:25:01.763681
10195 01:25:02.282569 01700000 ################################################################
10196 01:25:02.282699
10197 01:25:02.797790 01780000 ################################################################
10198 01:25:02.797968
10199 01:25:03.327491 01800000 ################################################################
10200 01:25:03.327628
10201 01:25:03.854147 01880000 ################################################################
10202 01:25:03.854294
10203 01:25:04.405924 01900000 ################################################################
10204 01:25:04.406063
10205 01:25:04.934062 01980000 ################################################################
10206 01:25:04.934228
10207 01:25:05.472053 01a00000 ################################################################
10208 01:25:05.472194
10209 01:25:05.999505 01a80000 ################################################################
10210 01:25:05.999671
10211 01:25:06.518977 01b00000 ################################################################
10212 01:25:06.519141
10213 01:25:07.037079 01b80000 ################################################################
10214 01:25:07.037221
10215 01:25:07.553770 01c00000 ################################################################
10216 01:25:07.553941
10217 01:25:08.070677 01c80000 ################################################################
10218 01:25:08.070845
10219 01:25:08.591610 01d00000 ################################################################
10220 01:25:08.591749
10221 01:25:09.126972 01d80000 ################################################################
10222 01:25:09.127148
10223 01:25:09.644427 01e00000 ################################################################
10224 01:25:09.644580
10225 01:25:10.167278 01e80000 ################################################################
10226 01:25:10.167450
10227 01:25:10.695832 01f00000 ################################################################
10228 01:25:10.695991
10229 01:25:11.215569 01f80000 ################################################################
10230 01:25:11.215732
10231 01:25:11.732566 02000000 ################################################################
10232 01:25:11.732763
10233 01:25:12.247471 02080000 ################################################################
10234 01:25:12.247634
10235 01:25:12.764339 02100000 ################################################################
10236 01:25:12.764505
10237 01:25:13.282334 02180000 ################################################################
10238 01:25:13.282502
10239 01:25:13.804294 02200000 ################################################################
10240 01:25:13.804472
10241 01:25:14.332590 02280000 ################################################################
10242 01:25:14.332783
10243 01:25:14.852434 02300000 ################################################################
10244 01:25:14.852607
10245 01:25:15.370321 02380000 ################################################################
10246 01:25:15.370484
10247 01:25:15.887604 02400000 ################################################################
10248 01:25:15.887788
10249 01:25:16.411471 02480000 ################################################################
10250 01:25:16.411640
10251 01:25:16.927302 02500000 ################################################################
10252 01:25:16.927451
10253 01:25:17.444638 02580000 ################################################################
10254 01:25:17.444816
10255 01:25:17.962698 02600000 ################################################################
10256 01:25:17.962843
10257 01:25:18.488108 02680000 ################################################################
10258 01:25:18.488251
10259 01:25:19.008708 02700000 ################################################################
10260 01:25:19.008870
10261 01:25:19.565064 02780000 ################################################################
10262 01:25:19.565208
10263 01:25:20.093636 02800000 ################################################################
10264 01:25:20.093784
10265 01:25:20.625036 02880000 ################################################################
10266 01:25:20.625190
10267 01:25:21.145485 02900000 ################################################################
10268 01:25:21.145633
10269 01:25:21.695338 02980000 ################################################################
10270 01:25:21.695474
10271 01:25:22.230514 02a00000 ################################################################
10272 01:25:22.230652
10273 01:25:22.758161 02a80000 ################################################################
10274 01:25:22.758300
10275 01:25:23.299282 02b00000 ################################################################
10276 01:25:23.299416
10277 01:25:23.833614 02b80000 ################################################################
10278 01:25:23.833749
10279 01:25:24.369746 02c00000 ################################################################
10280 01:25:24.369880
10281 01:25:24.893783 02c80000 ################################################################
10282 01:25:24.893922
10283 01:25:25.416389 02d00000 ################################################################
10284 01:25:25.416522
10285 01:25:25.937789 02d80000 ################################################################
10286 01:25:25.937936
10287 01:25:26.467495 02e00000 ################################################################
10288 01:25:26.467634
10289 01:25:27.010433 02e80000 ################################################################
10290 01:25:27.010575
10291 01:25:27.546718 02f00000 ################################################################
10292 01:25:27.546862
10293 01:25:28.100581 02f80000 ################################################################
10294 01:25:28.100731
10295 01:25:28.623601 03000000 ################################################################
10296 01:25:28.623750
10297 01:25:29.172214 03080000 ################################################################
10298 01:25:29.172362
10299 01:25:29.734345 03100000 ################################################################
10300 01:25:29.734488
10301 01:25:30.266314 03180000 ################################################################
10302 01:25:30.266456
10303 01:25:30.795674 03200000 ################################################################
10304 01:25:30.795815
10305 01:25:31.327523 03280000 ################################################################
10306 01:25:31.327654
10307 01:25:31.863521 03300000 ################################################################
10308 01:25:31.863662
10309 01:25:32.397027 03380000 ################################################################
10310 01:25:32.397203
10311 01:25:32.930258 03400000 ################################################################
10312 01:25:32.930417
10313 01:25:33.456597 03480000 ################################################################
10314 01:25:33.456811
10315 01:25:33.986747 03500000 ################################################################
10316 01:25:33.986895
10317 01:25:34.521448 03580000 ################################################################
10318 01:25:34.521596
10319 01:25:35.058412 03600000 ################################################################
10320 01:25:35.058558
10321 01:25:35.586388 03680000 ################################################################
10322 01:25:35.586540
10323 01:25:36.126828 03700000 ################################################################
10324 01:25:36.126977
10325 01:25:36.657361 03780000 ################################################################
10326 01:25:36.657500
10327 01:25:37.188281 03800000 ################################################################
10328 01:25:37.188422
10329 01:25:37.724084 03880000 ################################################################
10330 01:25:37.724218
10331 01:25:38.251504 03900000 ################################################################
10332 01:25:38.251640
10333 01:25:38.786780 03980000 ################################################################
10334 01:25:38.786949
10335 01:25:39.314130 03a00000 ################################################################
10336 01:25:39.314275
10337 01:25:39.849750 03a80000 ################################################################
10338 01:25:39.849884
10339 01:25:40.369458 03b00000 ################################################################
10340 01:25:40.369595
10341 01:25:40.889298 03b80000 ################################################################
10342 01:25:40.889457
10343 01:25:41.423633 03c00000 ################################################################
10344 01:25:41.423776
10345 01:25:41.963062 03c80000 ################################################################
10346 01:25:41.963198
10347 01:25:42.490376 03d00000 ################################################################
10348 01:25:42.490511
10349 01:25:43.009212 03d80000 ################################################################
10350 01:25:43.009364
10351 01:25:43.549933 03e00000 ################################################################
10352 01:25:43.550068
10353 01:25:44.082444 03e80000 ################################################################
10354 01:25:44.082580
10355 01:25:44.607235 03f00000 ################################################################
10356 01:25:44.607372
10357 01:25:45.144808 03f80000 ################################################################
10358 01:25:45.144945
10359 01:25:45.670626 04000000 ################################################################
10360 01:25:45.670763
10361 01:25:46.262328 04080000 ################################################################
10362 01:25:46.262821
10363 01:25:46.969123 04100000 ################################################################
10364 01:25:46.969671
10365 01:25:47.660579 04180000 ################################################################
10366 01:25:47.661211
10367 01:25:48.361059 04200000 ################################################################
10368 01:25:48.361549
10369 01:25:49.035008 04280000 ################################################################
10370 01:25:49.035199
10371 01:25:49.670026 04300000 ################################################################
10372 01:25:49.670519
10373 01:25:50.392427 04380000 ################################################################
10374 01:25:50.393008
10375 01:25:51.111074 04400000 ################################################################
10376 01:25:51.111577
10377 01:25:51.829139 04480000 ################################################################
10378 01:25:51.829736
10379 01:25:52.532273 04500000 ################################################################
10380 01:25:52.532807
10381 01:25:53.217864 04580000 ################################################################
10382 01:25:53.218415
10383 01:25:53.846766 04600000 ################################################################
10384 01:25:53.847293
10385 01:25:54.555875 04680000 ################################################################
10386 01:25:54.556407
10387 01:25:55.275317 04700000 ################################################################
10388 01:25:55.275884
10389 01:25:55.994458 04780000 ################################################################
10390 01:25:55.994955
10391 01:25:56.688164 04800000 ################################################################
10392 01:25:56.688784
10393 01:25:57.414004 04880000 ################################################################
10394 01:25:57.414518
10395 01:25:58.133773 04900000 ################################################################
10396 01:25:58.134359
10397 01:25:58.771889 04980000 ################################################################
10398 01:25:58.772443
10399 01:25:59.503697 04a00000 ################################################################
10400 01:25:59.504332
10401 01:26:00.224856 04a80000 ################################################################
10402 01:26:00.225492
10403 01:26:00.919472 04b00000 ################################################################
10404 01:26:00.920000
10405 01:26:01.591901 04b80000 ################################################################
10406 01:26:01.592408
10407 01:26:02.291726 04c00000 ################################################################
10408 01:26:02.292310
10409 01:26:03.008941 04c80000 ################################################################
10410 01:26:03.009454
10411 01:26:03.667100 04d00000 ################################################################
10412 01:26:03.667235
10413 01:26:04.333748 04d80000 ################################################################
10414 01:26:04.334269
10415 01:26:05.051024 04e00000 ################################################################
10416 01:26:05.051579
10417 01:26:05.762712 04e80000 ################################################################
10418 01:26:05.763341
10419 01:26:06.430167 04f00000 ################################################################
10420 01:26:06.430660
10421 01:26:07.132425 04f80000 ################################################################
10422 01:26:07.132980
10423 01:26:07.855836 05000000 ################################################################
10424 01:26:07.856382
10425 01:26:08.576820 05080000 ################################################################
10426 01:26:08.577392
10427 01:26:09.180728 05100000 ################################################################
10428 01:26:09.181260
10429 01:26:09.900799 05180000 ################################################################
10430 01:26:09.901296
10431 01:26:10.633363 05200000 ################################################################
10432 01:26:10.633866
10433 01:26:11.334692 05280000 ################################################################
10434 01:26:11.335200
10435 01:26:12.020102 05300000 ################################################################
10436 01:26:12.020623
10437 01:26:12.751385 05380000 ################################################################
10438 01:26:12.751926
10439 01:26:13.484378 05400000 ################################################################
10440 01:26:13.485007
10441 01:26:14.131107 05480000 ################################################################
10442 01:26:14.131244
10443 01:26:14.835216 05500000 ################################################################
10444 01:26:14.835785
10445 01:26:15.547176 05580000 ################################################################
10446 01:26:15.547733
10447 01:26:16.262780 05600000 ################################################################
10448 01:26:16.263288
10449 01:26:16.911833 05680000 ################################################################
10450 01:26:16.912405
10451 01:26:17.507413 05700000 ################################################################
10452 01:26:17.507545
10453 01:26:18.199783 05780000 ################################################################
10454 01:26:18.200354
10455 01:26:18.936806 05800000 ################################################################
10456 01:26:18.937688
10457 01:26:19.667858 05880000 ################################################################
10458 01:26:19.668357
10459 01:26:20.372536 05900000 ################################################################
10460 01:26:20.373116
10461 01:26:21.091028 05980000 ################################################################
10462 01:26:21.091572
10463 01:26:21.807743 05a00000 ################################################################
10464 01:26:21.808253
10465 01:26:22.536056 05a80000 ################################################################
10466 01:26:22.536590
10467 01:26:23.251519 05b00000 ################################################################
10468 01:26:23.252080
10469 01:26:23.972214 05b80000 ################################################################
10470 01:26:23.972727
10471 01:26:24.677496 05c00000 ################################################################
10472 01:26:24.678009
10473 01:26:25.386330 05c80000 ################################################################
10474 01:26:25.386835
10475 01:26:26.091258 05d00000 ################################################################
10476 01:26:26.091778
10477 01:26:26.806053 05d80000 ################################################################
10478 01:26:26.806600
10479 01:26:27.529522 05e00000 ################################################################
10480 01:26:27.530044
10481 01:26:28.252611 05e80000 ################################################################
10482 01:26:28.253244
10483 01:26:28.962774 05f00000 ################################################################
10484 01:26:28.963285
10485 01:26:29.683647 05f80000 ################################################################
10486 01:26:29.684290
10487 01:26:30.401385 06000000 ################################################################
10488 01:26:30.401895
10489 01:26:31.116318 06080000 ################################################################
10490 01:26:31.116865
10491 01:26:31.829807 06100000 ################################################################
10492 01:26:31.830377
10493 01:26:32.559597 06180000 ################################################################
10494 01:26:32.560125
10495 01:26:33.284147 06200000 ################################################################
10496 01:26:33.284805
10497 01:26:33.985139 06280000 ################################################################
10498 01:26:33.985670
10499 01:26:34.673403 06300000 ################################################################
10500 01:26:34.673938
10501 01:26:35.396651 06380000 ################################################################
10502 01:26:35.397227
10503 01:26:36.115173 06400000 ################################################################
10504 01:26:36.115755
10505 01:26:36.829978 06480000 ################################################################
10506 01:26:36.830539
10507 01:26:37.554481 06500000 ################################################################
10508 01:26:37.555058
10509 01:26:38.267206 06580000 ################################################################
10510 01:26:38.267701
10511 01:26:38.981672 06600000 ################################################################
10512 01:26:38.982186
10513 01:26:39.701057 06680000 ################################################################
10514 01:26:39.701727
10515 01:26:40.432290 06700000 ################################################################
10516 01:26:40.432861
10517 01:26:41.148195 06780000 ################################################################
10518 01:26:41.148782
10519 01:26:41.647811 06800000 ############################################ done.
10520 01:26:41.648387
10521 01:26:41.650849 The bootfile was 109405050 bytes long.
10522 01:26:41.651318
10523 01:26:41.654320 Sending tftp read request... done.
10524 01:26:41.654785
10525 01:26:41.657539 Waiting for the transfer...
10526 01:26:41.658002
10527 01:26:41.660921 00000000 # done.
10528 01:26:41.661395
10529 01:26:41.668477 Command line loaded dynamically from TFTP file: 11368532/tftp-deploy-oxmtxrpo/kernel/cmdline
10530 01:26:41.669077
10531 01:26:41.681062 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10532 01:26:41.681638
10533 01:26:41.682001 Loading FIT.
10534 01:26:41.682339
10535 01:26:41.684483 Image ramdisk-1 has 98317070 bytes.
10536 01:26:41.685100
10537 01:26:41.687551 Image fdt-1 has 47278 bytes.
10538 01:26:41.687970
10539 01:26:41.691049 Image kernel-1 has 11038667 bytes.
10540 01:26:41.691468
10541 01:26:41.701292 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10542 01:26:41.701769
10543 01:26:41.718151 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10544 01:26:41.718698
10545 01:26:41.721162 Choosing best match conf-1 for compat google,spherion-rev2.
10546 01:26:41.727645
10547 01:26:41.732079 Connected to device vid:did:rid of 1ae0:0028:00
10548 01:26:41.740229
10549 01:26:41.742952 tpm_get_response: command 0x17b, return code 0x0
10550 01:26:41.743422
10551 01:26:41.746510 ec_init: CrosEC protocol v3 supported (256, 248)
10552 01:26:41.750517
10553 01:26:41.753909 tpm_cleanup: add release locality here.
10554 01:26:41.754373
10555 01:26:41.754734 Shutting down all USB controllers.
10556 01:26:41.755073
10557 01:26:41.757145 Removing current net device
10558 01:26:41.757610
10559 01:26:41.764264 Exiting depthcharge with code 4 at timestamp: 160095528
10560 01:26:41.764868
10561 01:26:41.767085 LZMA decompressing kernel-1 to 0x821a6718
10562 01:26:41.767640
10563 01:26:41.770359 LZMA decompressing kernel-1 to 0x40000000
10564 01:26:43.157693
10565 01:26:43.158384 jumping to kernel
10566 01:26:43.160201 end: 2.2.4 bootloader-commands (duration 00:02:12) [common]
10567 01:26:43.160794 start: 2.2.5 auto-login-action (timeout 00:02:13) [common]
10568 01:26:43.161217 Setting prompt string to ['Linux version [0-9]']
10569 01:26:43.161591 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10570 01:26:43.161967 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10571 01:26:43.240082
10572 01:26:43.243229 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10573 01:26:43.246755 start: 2.2.5.1 login-action (timeout 00:02:13) [common]
10574 01:26:43.247269 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10575 01:26:43.247737 Setting prompt string to []
10576 01:26:43.248178 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10577 01:26:43.248583 Using line separator: #'\n'#
10578 01:26:43.248964 No login prompt set.
10579 01:26:43.249504 Parsing kernel messages
10580 01:26:43.249836 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10581 01:26:43.250393 [login-action] Waiting for messages, (timeout 00:02:13)
10582 01:26:43.266758 [ 0.000000] Linux version 6.1.46-cip4 (KernelCI@build-j24548-arm64-gcc-10-defconfig-arm64-chromebook-xnj4p) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023
10583 01:26:43.269755 [ 0.000000] random: crng init done
10584 01:26:43.273067 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10585 01:26:43.276315 [ 0.000000] efi: UEFI not found.
10586 01:26:43.286655 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10587 01:26:43.292809 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10588 01:26:43.303010 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10589 01:26:43.312617 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10590 01:26:43.319402 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10591 01:26:43.323194 [ 0.000000] printk: bootconsole [mtk8250] enabled
10592 01:26:43.331601 [ 0.000000] NUMA: No NUMA configuration found
10593 01:26:43.338407 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10594 01:26:43.345160 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10595 01:26:43.345629 [ 0.000000] Zone ranges:
10596 01:26:43.351203 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10597 01:26:43.355105 [ 0.000000] DMA32 empty
10598 01:26:43.361467 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10599 01:26:43.365234 [ 0.000000] Movable zone start for each node
10600 01:26:43.368444 [ 0.000000] Early memory node ranges
10601 01:26:43.374827 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10602 01:26:43.381261 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10603 01:26:43.388295 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10604 01:26:43.394848 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10605 01:26:43.401952 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10606 01:26:43.408249 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10607 01:26:43.463758 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10608 01:26:43.470743 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10609 01:26:43.477322 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10610 01:26:43.480824 [ 0.000000] psci: probing for conduit method from DT.
10611 01:26:43.487723 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10612 01:26:43.490648 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10613 01:26:43.497483 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10614 01:26:43.500613 [ 0.000000] psci: SMC Calling Convention v1.2
10615 01:26:43.507569 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10616 01:26:43.510526 [ 0.000000] Detected VIPT I-cache on CPU0
10617 01:26:43.517306 [ 0.000000] CPU features: detected: GIC system register CPU interface
10618 01:26:43.523867 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10619 01:26:43.530803 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10620 01:26:43.536987 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10621 01:26:43.544386 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10622 01:26:43.550254 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10623 01:26:43.557053 [ 0.000000] alternatives: applying boot alternatives
10624 01:26:43.560425 [ 0.000000] Fallback order for Node 0: 0
10625 01:26:43.567403 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10626 01:26:43.570440 [ 0.000000] Policy zone: Normal
10627 01:26:43.587645 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10628 01:26:43.597451 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10629 01:26:43.608534 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10630 01:26:43.618425 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10631 01:26:43.625175 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10632 01:26:43.628237 <6>[ 0.000000] software IO TLB: area num 8.
10633 01:26:43.684943 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10634 01:26:43.833689 <6>[ 0.000000] Memory: 7873544K/8385536K available (17984K kernel code, 4098K rwdata, 17464K rodata, 8384K init, 615K bss, 479224K reserved, 32768K cma-reserved)
10635 01:26:43.840133 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10636 01:26:43.847078 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10637 01:26:43.850310 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10638 01:26:43.856727 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10639 01:26:43.863280 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10640 01:26:43.866669 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10641 01:26:43.877076 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10642 01:26:43.883547 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10643 01:26:43.886796 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10644 01:26:43.894738 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10645 01:26:43.898057 <6>[ 0.000000] GICv3: 608 SPIs implemented
10646 01:26:43.904921 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10647 01:26:43.907924 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10648 01:26:43.911238 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10649 01:26:43.921603 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10650 01:26:43.931291 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10651 01:26:43.944845 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10652 01:26:43.951320 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10653 01:26:43.959847 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10654 01:26:43.973580 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10655 01:26:43.980517 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10656 01:26:43.987021 <6>[ 0.009183] Console: colour dummy device 80x25
10657 01:26:43.997170 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10658 01:26:44.000551 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10659 01:26:44.007137 <6>[ 0.029225] LSM: Security Framework initializing
10660 01:26:44.013240 <6>[ 0.034162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10661 01:26:44.023703 <6>[ 0.042024] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10662 01:26:44.030328 <6>[ 0.051451] cblist_init_generic: Setting adjustable number of callback queues.
10663 01:26:44.036890 <6>[ 0.058897] cblist_init_generic: Setting shift to 3 and lim to 1.
10664 01:26:44.046420 <6>[ 0.065236] cblist_init_generic: Setting adjustable number of callback queues.
10665 01:26:44.050290 <6>[ 0.072661] cblist_init_generic: Setting shift to 3 and lim to 1.
10666 01:26:44.056605 <6>[ 0.079059] rcu: Hierarchical SRCU implementation.
10667 01:26:44.063146 <6>[ 0.084073] rcu: Max phase no-delay instances is 1000.
10668 01:26:44.066478 <6>[ 0.091103] EFI services will not be available.
10669 01:26:44.073439 <6>[ 0.096107] smp: Bringing up secondary CPUs ...
10670 01:26:44.081149 <6>[ 0.101195] Detected VIPT I-cache on CPU1
10671 01:26:44.087719 <6>[ 0.101264] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10672 01:26:44.094685 <6>[ 0.101296] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10673 01:26:44.097291 <6>[ 0.101636] Detected VIPT I-cache on CPU2
10674 01:26:44.104060 <6>[ 0.101688] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10675 01:26:44.110977 <6>[ 0.101704] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10676 01:26:44.118109 <6>[ 0.101962] Detected VIPT I-cache on CPU3
10677 01:26:44.124293 <6>[ 0.102009] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10678 01:26:44.131213 <6>[ 0.102023] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10679 01:26:44.134995 <6>[ 0.102330] CPU features: detected: Spectre-v4
10680 01:26:44.141109 <6>[ 0.102336] CPU features: detected: Spectre-BHB
10681 01:26:44.144761 <6>[ 0.102342] Detected PIPT I-cache on CPU4
10682 01:26:44.151252 <6>[ 0.102396] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10683 01:26:44.157722 <6>[ 0.102413] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10684 01:26:44.161145 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10685 01:26:44.171246 <6>[ 0.102766] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10686 01:26:44.178161 <6>[ 0.102783] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10687 01:26:44.181201 <6>[ 0.103068] Detected PIPT I-cache on CPU6
10688 01:26:44.188351 <6>[ 0.103131] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10689 01:26:44.194574 <6>[ 0.103147] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10690 01:26:44.198097 <6>[ 0.103448] Detected PIPT I-cache on CPU7
10691 01:26:44.205226 <6>[ 0.103513] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10692 01:26:44.214325 <6>[ 0.103530] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10693 01:26:44.218234 <6>[ 0.103577] smp: Brought up 1 node, 8 CPUs
10694 01:26:44.221444 <6>[ 0.244875] SMP: Total of 8 processors activated.
10695 01:26:44.228162 <6>[ 0.249826] CPU features: detected: 32-bit EL0 Support
10696 01:26:44.238033 <6>[ 0.255221] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10697 01:26:44.244316 <6>[ 0.264021] CPU features: detected: Common not Private translations
10698 01:26:44.247829 <6>[ 0.270496] CPU features: detected: CRC32 instructions
10699 01:26:44.254259 <6>[ 0.275847] CPU features: detected: RCpc load-acquire (LDAPR)
10700 01:26:44.261600 <6>[ 0.281844] CPU features: detected: LSE atomic instructions
10701 01:26:44.264429 <6>[ 0.287661] CPU features: detected: Privileged Access Never
10702 01:26:44.271854 <6>[ 0.293476] CPU features: detected: RAS Extension Support
10703 01:26:44.277505 <6>[ 0.299084] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10704 01:26:44.284767 <6>[ 0.306304] CPU: All CPU(s) started at EL2
10705 01:26:44.287966 <6>[ 0.310621] alternatives: applying system-wide alternatives
10706 01:26:44.298585 <6>[ 0.321315] devtmpfs: initialized
10707 01:26:44.310665 <6>[ 0.330168] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10708 01:26:44.321258 <6>[ 0.340132] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10709 01:26:44.327725 <6>[ 0.348140] pinctrl core: initialized pinctrl subsystem
10710 01:26:44.330991 <6>[ 0.354787] DMI not present or invalid.
10711 01:26:44.337264 <6>[ 0.359197] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10712 01:26:44.344842 <6>[ 0.366044] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10713 01:26:44.354233 <6>[ 0.373626] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10714 01:26:44.360995 <6>[ 0.381841] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10715 01:26:44.367848 <6>[ 0.390084] audit: initializing netlink subsys (disabled)
10716 01:26:44.377627 <5>[ 0.395777] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10717 01:26:44.381217 <6>[ 0.396475] thermal_sys: Registered thermal governor 'step_wise'
10718 01:26:44.387525 <6>[ 0.403745] thermal_sys: Registered thermal governor 'power_allocator'
10719 01:26:44.394214 <6>[ 0.410001] cpuidle: using governor menu
10720 01:26:44.397564 <6>[ 0.420961] NET: Registered PF_QIPCRTR protocol family
10721 01:26:44.404536 <6>[ 0.426441] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10722 01:26:44.410951 <6>[ 0.433548] ASID allocator initialised with 32768 entries
10723 01:26:44.417414 <6>[ 0.440070] Serial: AMBA PL011 UART driver
10724 01:26:44.426112 <4>[ 0.448774] Trying to register duplicate clock ID: 134
10725 01:26:44.480224 <6>[ 0.506062] KASLR enabled
10726 01:26:44.494208 <6>[ 0.513691] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10727 01:26:44.501086 <6>[ 0.520703] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10728 01:26:44.507821 <6>[ 0.527193] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10729 01:26:44.514637 <6>[ 0.534199] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10730 01:26:44.521431 <6>[ 0.540685] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10731 01:26:44.527836 <6>[ 0.547692] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10732 01:26:44.534528 <6>[ 0.554179] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10733 01:26:44.541237 <6>[ 0.561187] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10734 01:26:44.544420 <6>[ 0.568632] ACPI: Interpreter disabled.
10735 01:26:44.552176 <6>[ 0.575067] iommu: Default domain type: Translated
10736 01:26:44.559033 <6>[ 0.580180] iommu: DMA domain TLB invalidation policy: strict mode
10737 01:26:44.562204 <5>[ 0.586841] SCSI subsystem initialized
10738 01:26:44.568953 <6>[ 0.591089] usbcore: registered new interface driver usbfs
10739 01:26:44.575725 <6>[ 0.596816] usbcore: registered new interface driver hub
10740 01:26:44.579250 <6>[ 0.602372] usbcore: registered new device driver usb
10741 01:26:44.585691 <6>[ 0.608488] pps_core: LinuxPPS API ver. 1 registered
10742 01:26:44.596034 <6>[ 0.613682] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10743 01:26:44.599730 <6>[ 0.623025] PTP clock support registered
10744 01:26:44.602465 <6>[ 0.627267] EDAC MC: Ver: 3.0.0
10745 01:26:44.609867 <6>[ 0.632442] FPGA manager framework
10746 01:26:44.616428 <6>[ 0.636119] Advanced Linux Sound Architecture Driver Initialized.
10747 01:26:44.619972 <6>[ 0.642879] vgaarb: loaded
10748 01:26:44.626518 <6>[ 0.646041] clocksource: Switched to clocksource arch_sys_counter
10749 01:26:44.629638 <5>[ 0.652483] VFS: Disk quotas dquot_6.6.0
10750 01:26:44.636386 <6>[ 0.656670] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10751 01:26:44.639371 <6>[ 0.663858] pnp: PnP ACPI: disabled
10752 01:26:44.647971 <6>[ 0.670498] NET: Registered PF_INET protocol family
10753 01:26:44.657702 <6>[ 0.676084] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10754 01:26:44.668855 <6>[ 0.688375] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10755 01:26:44.678777 <6>[ 0.697190] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10756 01:26:44.685220 <6>[ 0.705163] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10757 01:26:44.691941 <6>[ 0.713865] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10758 01:26:44.700949 <6>[ 0.723608] TCP: Hash tables configured (established 65536 bind 65536)
10759 01:26:44.711454 <6>[ 0.730474] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10760 01:26:44.717594 <6>[ 0.737673] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10761 01:26:44.724623 <6>[ 0.745370] NET: Registered PF_UNIX/PF_LOCAL protocol family
10762 01:26:44.731699 <6>[ 0.751535] RPC: Registered named UNIX socket transport module.
10763 01:26:44.735026 <6>[ 0.757688] RPC: Registered udp transport module.
10764 01:26:44.741648 <6>[ 0.762622] RPC: Registered tcp transport module.
10765 01:26:44.748158 <6>[ 0.767553] RPC: Registered tcp NFSv4.1 backchannel transport module.
10766 01:26:44.750938 <6>[ 0.774220] PCI: CLS 0 bytes, default 64
10767 01:26:44.754606 <6>[ 0.778632] Unpacking initramfs...
10768 01:26:44.778940 <6>[ 0.798197] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10769 01:26:44.788567 <6>[ 0.806843] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10770 01:26:44.792209 <6>[ 0.815685] kvm [1]: IPA Size Limit: 40 bits
10771 01:26:44.798808 <6>[ 0.820211] kvm [1]: GICv3: no GICV resource entry
10772 01:26:44.802571 <6>[ 0.825231] kvm [1]: disabling GICv2 emulation
10773 01:26:44.808700 <6>[ 0.829916] kvm [1]: GIC system register CPU interface enabled
10774 01:26:44.812039 <6>[ 0.836079] kvm [1]: vgic interrupt IRQ18
10775 01:26:44.818552 <6>[ 0.840444] kvm [1]: VHE mode initialized successfully
10776 01:26:44.825976 <5>[ 0.846905] Initialise system trusted keyrings
10777 01:26:44.832105 <6>[ 0.851713] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10778 01:26:44.839139 <6>[ 0.861655] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10779 01:26:44.845646 <5>[ 0.868046] NFS: Registering the id_resolver key type
10780 01:26:44.848969 <5>[ 0.873349] Key type id_resolver registered
10781 01:26:44.855540 <5>[ 0.877765] Key type id_legacy registered
10782 01:26:44.862486 <6>[ 0.882058] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10783 01:26:44.868735 <6>[ 0.888980] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10784 01:26:44.875933 <6>[ 0.896705] 9p: Installing v9fs 9p2000 file system support
10785 01:26:44.911822 <5>[ 0.934389] Key type asymmetric registered
10786 01:26:44.915662 <5>[ 0.938721] Asymmetric key parser 'x509' registered
10787 01:26:44.925191 <6>[ 0.943905] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10788 01:26:44.928459 <6>[ 0.951524] io scheduler mq-deadline registered
10789 01:26:44.931548 <6>[ 0.956292] io scheduler kyber registered
10790 01:26:44.950433 <6>[ 0.973374] EINJ: ACPI disabled.
10791 01:26:44.983322 <4>[ 0.999033] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10792 01:26:44.992777 <4>[ 1.009638] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10793 01:26:45.007461 <6>[ 1.030455] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10794 01:26:45.015518 <6>[ 1.038426] printk: console [ttyS0] disabled
10795 01:26:45.043703 <6>[ 1.063063] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10796 01:26:45.050770 <6>[ 1.072541] printk: console [ttyS0] enabled
10797 01:26:45.053703 <6>[ 1.072541] printk: console [ttyS0] enabled
10798 01:26:45.060353 <6>[ 1.081436] printk: bootconsole [mtk8250] disabled
10799 01:26:45.063543 <6>[ 1.081436] printk: bootconsole [mtk8250] disabled
10800 01:26:45.070719 <6>[ 1.092685] SuperH (H)SCI(F) driver initialized
10801 01:26:45.073605 <6>[ 1.097965] msm_serial: driver initialized
10802 01:26:45.087692 <6>[ 1.106943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10803 01:26:45.097793 <6>[ 1.115496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10804 01:26:45.104042 <6>[ 1.124038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10805 01:26:45.114239 <6>[ 1.132666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10806 01:26:45.120514 <6>[ 1.141372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10807 01:26:45.131019 <6>[ 1.150093] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10808 01:26:45.140833 <6>[ 1.158634] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10809 01:26:45.147080 <6>[ 1.167443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10810 01:26:45.157558 <6>[ 1.175985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10811 01:26:45.168948 <6>[ 1.191744] loop: module loaded
10812 01:26:45.175569 <6>[ 1.197703] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10813 01:26:45.198328 <4>[ 1.220892] mtk-pmic-keys: Failed to locate of_node [id: -1]
10814 01:26:45.205225 <6>[ 1.227581] megasas: 07.719.03.00-rc1
10815 01:26:45.214326 <6>[ 1.237073] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10816 01:26:45.222796 <6>[ 1.245406] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10817 01:26:45.239026 <6>[ 1.261822] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10818 01:26:45.295984 <6>[ 1.311679] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10819 01:26:48.752898 <6>[ 4.776522] Freeing initrd memory: 96008K
10820 01:26:48.763088 <6>[ 4.786797] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10821 01:26:48.773962 <6>[ 4.797739] tun: Universal TUN/TAP device driver, 1.6
10822 01:26:48.777459 <6>[ 4.803826] thunder_xcv, ver 1.0
10823 01:26:48.780888 <6>[ 4.807330] thunder_bgx, ver 1.0
10824 01:26:48.784156 <6>[ 4.810823] nicpf, ver 1.0
10825 01:26:48.794429 <6>[ 4.814851] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10826 01:26:48.797934 <6>[ 4.822327] hns3: Copyright (c) 2017 Huawei Corporation.
10827 01:26:48.804702 <6>[ 4.827916] hclge is initializing
10828 01:26:48.807426 <6>[ 4.831495] e1000: Intel(R) PRO/1000 Network Driver
10829 01:26:48.814543 <6>[ 4.836623] e1000: Copyright (c) 1999-2006 Intel Corporation.
10830 01:26:48.817656 <6>[ 4.842639] e1000e: Intel(R) PRO/1000 Network Driver
10831 01:26:48.824389 <6>[ 4.847855] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10832 01:26:48.831327 <6>[ 4.854046] igb: Intel(R) Gigabit Ethernet Network Driver
10833 01:26:48.837555 <6>[ 4.859697] igb: Copyright (c) 2007-2014 Intel Corporation.
10834 01:26:48.844388 <6>[ 4.865533] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10835 01:26:48.850462 <6>[ 4.872051] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10836 01:26:48.854361 <6>[ 4.878516] sky2: driver version 1.30
10837 01:26:48.860455 <6>[ 4.883513] VFIO - User Level meta-driver version: 0.3
10838 01:26:48.868148 <6>[ 4.891752] usbcore: registered new interface driver usb-storage
10839 01:26:48.874892 <6>[ 4.898203] usbcore: registered new device driver onboard-usb-hub
10840 01:26:48.883924 <6>[ 4.907346] mt6397-rtc mt6359-rtc: registered as rtc0
10841 01:26:48.893661 <6>[ 4.912806] mt6397-rtc mt6359-rtc: setting system clock to 2023-08-28T01:26:48 UTC (1693186008)
10842 01:26:48.896882 <6>[ 4.922386] i2c_dev: i2c /dev entries driver
10843 01:26:48.913671 <6>[ 4.934216] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10844 01:26:48.933255 <6>[ 4.957212] cpu cpu0: EM: created perf domain
10845 01:26:48.936858 <6>[ 4.962216] cpu cpu4: EM: created perf domain
10846 01:26:48.944258 <6>[ 4.967896] sdhci: Secure Digital Host Controller Interface driver
10847 01:26:48.950588 <6>[ 4.974329] sdhci: Copyright(c) Pierre Ossman
10848 01:26:48.957506 <6>[ 4.979284] Synopsys Designware Multimedia Card Interface Driver
10849 01:26:48.963960 <6>[ 4.985919] sdhci-pltfm: SDHCI platform and OF driver helper
10850 01:26:48.967329 <6>[ 4.985973] mmc0: CQHCI version 5.10
10851 01:26:48.974008 <6>[ 4.996141] ledtrig-cpu: registered to indicate activity on CPUs
10852 01:26:48.980822 <6>[ 5.003249] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10853 01:26:48.987564 <6>[ 5.010309] usbcore: registered new interface driver usbhid
10854 01:26:48.990453 <6>[ 5.016132] usbhid: USB HID core driver
10855 01:26:48.997316 <6>[ 5.020342] spi_master spi0: will run message pump with realtime priority
10856 01:26:49.042580 <6>[ 5.059774] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10857 01:26:49.061502 <6>[ 5.075207] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10858 01:26:49.069557 <6>[ 5.089969] cros-ec-spi spi0.0: Chrome EC device registered
10859 01:26:49.072411 <6>[ 5.095999] mmc0: Command Queue Engine enabled
10860 01:26:49.079112 <6>[ 5.100755] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10861 01:26:49.085251 <6>[ 5.108252] mmcblk0: mmc0:0001 DA4128 116 GiB
10862 01:26:49.095577 <6>[ 5.114372] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10863 01:26:49.102179 <6>[ 5.121964] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10864 01:26:49.105269 <6>[ 5.124783] NET: Registered PF_PACKET protocol family
10865 01:26:49.112159 <6>[ 5.130510] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10866 01:26:49.115259 <6>[ 5.134984] 9pnet: Installing 9P2000 support
10867 01:26:49.122151 <6>[ 5.140728] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10868 01:26:49.125719 <5>[ 5.144691] Key type dns_resolver registered
10869 01:26:49.132165 <6>[ 5.150435] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10870 01:26:49.135342 <6>[ 5.154870] registered taskstats version 1
10871 01:26:49.141573 <5>[ 5.165289] Loading compiled-in X.509 certificates
10872 01:26:49.169619 <4>[ 5.186686] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10873 01:26:49.179722 <4>[ 5.197395] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10874 01:26:49.186210 <3>[ 5.207930] debugfs: File 'uA_load' in directory '/' already present!
10875 01:26:49.193007 <3>[ 5.214632] debugfs: File 'min_uV' in directory '/' already present!
10876 01:26:49.199692 <3>[ 5.221238] debugfs: File 'max_uV' in directory '/' already present!
10877 01:26:49.206116 <3>[ 5.227900] debugfs: File 'constraint_flags' in directory '/' already present!
10878 01:26:49.217614 <3>[ 5.237720] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10879 01:26:49.229639 <6>[ 5.253243] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10880 01:26:49.236222 <6>[ 5.259999] xhci-mtk 11200000.usb: xHCI Host Controller
10881 01:26:49.242725 <6>[ 5.265498] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10882 01:26:49.252769 <6>[ 5.273350] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10883 01:26:49.259539 <6>[ 5.282771] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10884 01:26:49.265979 <6>[ 5.288960] xhci-mtk 11200000.usb: xHCI Host Controller
10885 01:26:49.272794 <6>[ 5.294475] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10886 01:26:49.279604 <6>[ 5.302134] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10887 01:26:49.286445 <6>[ 5.310002] hub 1-0:1.0: USB hub found
10888 01:26:49.289942 <6>[ 5.314053] hub 1-0:1.0: 1 port detected
10889 01:26:49.299409 <6>[ 5.318351] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10890 01:26:49.302710 <6>[ 5.327144] hub 2-0:1.0: USB hub found
10891 01:26:49.306405 <6>[ 5.331167] hub 2-0:1.0: 1 port detected
10892 01:26:49.315791 <6>[ 5.339328] mtk-msdc 11f70000.mmc: Got CD GPIO
10893 01:26:49.325612 <6>[ 5.345708] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10894 01:26:49.332611 <6>[ 5.353737] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10895 01:26:49.342871 <4>[ 5.361657] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10896 01:26:49.349122 <6>[ 5.371190] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10897 01:26:49.358862 <6>[ 5.379267] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10898 01:26:49.365920 <6>[ 5.387263] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10899 01:26:49.375369 <6>[ 5.395178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10900 01:26:49.382514 <6>[ 5.402994] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10901 01:26:49.391963 <6>[ 5.410811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10902 01:26:49.401849 <6>[ 5.421282] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10903 01:26:49.408447 <6>[ 5.429644] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10904 01:26:49.418768 <6>[ 5.437986] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10905 01:26:49.425348 <6>[ 5.446332] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10906 01:26:49.435207 <6>[ 5.454671] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10907 01:26:49.442285 <6>[ 5.463010] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10908 01:26:49.452430 <6>[ 5.471347] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10909 01:26:49.459118 <6>[ 5.479693] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10910 01:26:49.468407 <6>[ 5.488030] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10911 01:26:49.475510 <6>[ 5.496369] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10912 01:26:49.485263 <6>[ 5.504709] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10913 01:26:49.492200 <6>[ 5.513047] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10914 01:26:49.501715 <6>[ 5.521385] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10915 01:26:49.508913 <6>[ 5.529723] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10916 01:26:49.518291 <6>[ 5.538062] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10917 01:26:49.525107 <6>[ 5.546808] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10918 01:26:49.531878 <6>[ 5.553956] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10919 01:26:49.538243 <6>[ 5.560714] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10920 01:26:49.544790 <6>[ 5.567483] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10921 01:26:49.551602 <6>[ 5.574421] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10922 01:26:49.561732 <6>[ 5.581268] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10923 01:26:49.571329 <6>[ 5.590406] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10924 01:26:49.581445 <6>[ 5.599525] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10925 01:26:49.588398 <6>[ 5.608820] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10926 01:26:49.598114 <6>[ 5.618289] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10927 01:26:49.608051 <6>[ 5.627756] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10928 01:26:49.617879 <6>[ 5.636876] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10929 01:26:49.628365 <6>[ 5.646342] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10930 01:26:49.635204 <6>[ 5.655462] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10931 01:26:49.645443 <6>[ 5.664758] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10932 01:26:49.654666 <6>[ 5.674918] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10933 01:26:49.666567 <6>[ 5.686839] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10934 01:26:49.722087 <6>[ 5.742307] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10935 01:26:49.876524 <6>[ 5.900062] hub 1-1:1.0: USB hub found
10936 01:26:49.879492 <6>[ 5.904567] hub 1-1:1.0: 4 ports detected
10937 01:26:50.001772 <6>[ 6.022371] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10938 01:26:50.027852 <6>[ 6.051403] hub 2-1:1.0: USB hub found
10939 01:26:50.031141 <6>[ 6.055848] hub 2-1:1.0: 3 ports detected
10940 01:26:50.201806 <6>[ 6.222318] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10941 01:26:50.334575 <6>[ 6.358446] hub 1-1.4:1.0: USB hub found
10942 01:26:50.337898 <6>[ 6.363183] hub 1-1.4:1.0: 2 ports detected
10943 01:26:50.417941 <6>[ 6.438567] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10944 01:26:50.633998 <6>[ 6.654305] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10945 01:26:50.825802 <6>[ 6.846328] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10946 01:27:01.939127 <6>[ 17.967323] ALSA device list:
10947 01:27:01.945749 <6>[ 17.970612] No soundcards found.
10948 01:27:01.953709 <6>[ 17.978613] Freeing unused kernel memory: 8384K
10949 01:27:01.957078 <6>[ 17.983623] Run /init as init process
10950 01:27:02.005636 <6>[ 18.030494] NET: Registered PF_INET6 protocol family
10951 01:27:02.012083 <6>[ 18.037163] Segment Routing with IPv6
10952 01:27:02.015681 <6>[ 18.041128] In-situ OAM (IOAM) with IPv6
10953 01:27:02.050113 <30>[ 18.055329] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10954 01:27:02.053685 <30>[ 18.079101] systemd[1]: Detected architecture arm64.
10955 01:27:02.054235
10956 01:27:02.059931 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10957 01:27:02.060354
10958 01:27:02.073188 <30>[ 18.098291] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10959 01:27:02.208005 <30>[ 18.230234] systemd[1]: Queued start job for default target Graphical Interface.
10960 01:27:02.253897 <30>[ 18.279271] systemd[1]: Created slice system-getty.slice.
10961 01:27:02.260492 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10962 01:27:02.281949 <30>[ 18.307048] systemd[1]: Created slice system-modprobe.slice.
10963 01:27:02.289058 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10964 01:27:02.305505 <30>[ 18.330762] systemd[1]: Created slice system-serial\x2dgetty.slice.
10965 01:27:02.315342 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10966 01:27:02.330113 <30>[ 18.354614] systemd[1]: Created slice User and Session Slice.
10967 01:27:02.336125 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10968 01:27:02.357345 <30>[ 18.378864] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10969 01:27:02.363858 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10970 01:27:02.385313 <30>[ 18.406929] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10971 01:27:02.392130 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10972 01:27:02.416187 <30>[ 18.434418] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10973 01:27:02.422708 <30>[ 18.446602] systemd[1]: Reached target Local Encrypted Volumes.
10974 01:27:02.429323 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10975 01:27:02.445925 <30>[ 18.470802] systemd[1]: Reached target Paths.
10976 01:27:02.449004 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10977 01:27:02.465143 <30>[ 18.490323] systemd[1]: Reached target Remote File Systems.
10978 01:27:02.472332 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10979 01:27:02.489671 <30>[ 18.514697] systemd[1]: Reached target Slices.
10980 01:27:02.496118 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10981 01:27:02.509422 <30>[ 18.534349] systemd[1]: Reached target Swap.
10982 01:27:02.512483 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10983 01:27:02.533023 <30>[ 18.554779] systemd[1]: Listening on initctl Compatibility Named Pipe.
10984 01:27:02.539551 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10985 01:27:02.546538 <30>[ 18.569904] systemd[1]: Listening on Journal Audit Socket.
10986 01:27:02.552906 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10987 01:27:02.565835 <30>[ 18.590784] systemd[1]: Listening on Journal Socket (/dev/log).
10988 01:27:02.572598 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10989 01:27:02.590365 <30>[ 18.615555] systemd[1]: Listening on Journal Socket.
10990 01:27:02.597766 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10991 01:27:02.610105 <30>[ 18.634896] systemd[1]: Listening on udev Control Socket.
10992 01:27:02.616357 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10993 01:27:02.634685 <30>[ 18.659343] systemd[1]: Listening on udev Kernel Socket.
10994 01:27:02.641167 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10995 01:27:02.681703 <30>[ 18.706402] systemd[1]: Mounting Huge Pages File System...
10996 01:27:02.688213 Mounting [0;1;39mHuge Pages File System[0m...
10997 01:27:02.705707 <30>[ 18.730283] systemd[1]: Mounting POSIX Message Queue File System...
10998 01:27:02.711905 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10999 01:27:02.749376 <30>[ 18.774388] systemd[1]: Mounting Kernel Debug File System...
11000 01:27:02.756489 Mounting [0;1;39mKernel Debug File System[0m...
11001 01:27:02.772880 <30>[ 18.794730] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11002 01:27:02.785974 <30>[ 18.807747] systemd[1]: Starting Create list of static device nodes for the current kernel...
11003 01:27:02.792602 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11004 01:27:02.814090 <30>[ 18.838720] systemd[1]: Starting Load Kernel Module configfs...
11005 01:27:02.820175 Starting [0;1;39mLoad Kernel Module configfs[0m...
11006 01:27:02.837417 <30>[ 18.862059] systemd[1]: Starting Load Kernel Module drm...
11007 01:27:02.843784 Starting [0;1;39mLoad Kernel Module drm[0m...
11008 01:27:02.861115 <30>[ 18.882395] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11009 01:27:02.893808 <30>[ 18.918853] systemd[1]: Starting Journal Service...
11010 01:27:02.897351 Starting [0;1;39mJournal Service[0m...
11011 01:27:02.916146 <30>[ 18.941145] systemd[1]: Starting Load Kernel Modules...
11012 01:27:02.922803 Starting [0;1;39mLoad Kernel Modules[0m...
11013 01:27:02.943667 <30>[ 18.965279] systemd[1]: Starting Remount Root and Kernel File Systems...
11014 01:27:02.950074 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11015 01:27:02.968023 <30>[ 18.993368] systemd[1]: Starting Coldplug All udev Devices...
11016 01:27:02.974910 Starting [0;1;39mColdplug All udev Devices[0m...
11017 01:27:02.993698 <30>[ 19.018596] systemd[1]: Started Journal Service.
11018 01:27:03.000010 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11019 01:27:03.016527 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11020 01:27:03.034362 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11021 01:27:03.050429 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11022 01:27:03.071736 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11023 01:27:03.087444 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11024 01:27:03.108453 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11025 01:27:03.127228 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11026 01:27:03.147022 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11027 01:27:03.161248 See 'systemctl status systemd-remount-fs.service' for details.
11028 01:27:03.214987 Mounting [0;1;39mKernel Configuration File System[0m...
11029 01:27:03.236728 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11030 01:27:03.260307 <46>[ 19.282361] systemd-journald[174]: Received client request to flush runtime journal.
11031 01:27:03.267222 Starting [0;1;39mLoad/Save Random Seed[0m...
11032 01:27:03.286321 Starting [0;1;39mApply Kernel Variables[0m...
11033 01:27:03.310094 Starting [0;1;39mCreate System Users[0m...
11034 01:27:03.329492 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11035 01:27:03.350118 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11036 01:27:03.374179 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11037 01:27:03.387058 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11038 01:27:03.401462 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11039 01:27:03.417903 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11040 01:27:03.457463 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11041 01:27:03.477769 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11042 01:27:03.489722 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11043 01:27:03.505018 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11044 01:27:03.557716 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11045 01:27:03.580733 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11046 01:27:03.597969 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11047 01:27:03.619152 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11048 01:27:03.662822 Starting [0;1;39mNetwork Time Synchronization[0m...
11049 01:27:03.684363 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11050 01:27:03.730890 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11051 01:27:03.755793 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11052 01:27:03.776307 <6>[ 19.797808] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11053 01:27:03.782769 <3>[ 19.800179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11054 01:27:03.789316 <6>[ 19.808132] remoteproc remoteproc0: scp is available
11055 01:27:03.795880 <3>[ 19.813662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11056 01:27:03.802771 <6>[ 19.818722] remoteproc remoteproc0: powering up scp
11057 01:27:03.809113 <3>[ 19.827750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11058 01:27:03.819686 <6>[ 19.832599] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11059 01:27:03.825809 <4>[ 19.832678] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11060 01:27:03.832841 <4>[ 19.834167] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11061 01:27:03.839371 <6>[ 19.839344] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11062 01:27:03.849357 <6>[ 19.839370] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11063 01:27:03.858957 <6>[ 19.839375] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11064 01:27:03.865876 <3>[ 19.846737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11065 01:27:03.872422 <6>[ 19.848428] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11066 01:27:03.879368 <3>[ 19.855722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11067 01:27:03.885559 <6>[ 19.891116] usbcore: registered new interface driver r8152
11068 01:27:03.892342 <3>[ 19.896181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11069 01:27:03.899097 <6>[ 19.908178] mc: Linux media interface: v0.10
11070 01:27:03.905651 <3>[ 19.909911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11071 01:27:03.915729 <6>[ 19.915644] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11072 01:27:03.922361 <3>[ 19.923724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11073 01:27:03.932111 <3>[ 19.932309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 01:27:03.935685 <6>[ 19.953220] videodev: Linux video capture interface: v2.00
11075 01:27:03.945143 <6>[ 19.953241] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11076 01:27:03.955473 <3>[ 19.963221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11077 01:27:03.961676 <6>[ 19.963437] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11078 01:27:03.968649 <6>[ 19.963443] pci_bus 0000:00: root bus resource [bus 00-ff]
11079 01:27:03.975800 <6>[ 19.963446] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11080 01:27:03.982677 <6>[ 19.963449] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11081 01:27:03.989250 <6>[ 19.963480] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11082 01:27:03.996025 <6>[ 19.963493] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11083 01:27:04.002808 <6>[ 19.963562] pci 0000:00:00.0: supports D1 D2
11084 01:27:04.009298 <6>[ 19.963564] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11085 01:27:04.016519 <6>[ 19.964837] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11086 01:27:04.023564 <6>[ 19.964979] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11087 01:27:04.029850 <6>[ 19.965007] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11088 01:27:04.040210 <6>[ 19.965026] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11089 01:27:04.046791 <6>[ 19.965041] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11090 01:27:04.050121 <6>[ 19.965149] pci 0000:01:00.0: supports D1 D2
11091 01:27:04.056402 <6>[ 19.965151] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11092 01:27:04.066797 <4>[ 19.972881] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11093 01:27:04.069609 <4>[ 19.972881] Fallback method does not support PEC.
11094 01:27:04.079787 <6>[ 19.974180] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11095 01:27:04.086775 <6>[ 19.974273] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11096 01:27:04.093168 <6>[ 19.974280] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11097 01:27:04.103860 <6>[ 19.974293] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11098 01:27:04.110574 <6>[ 19.974308] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11099 01:27:04.117936 <6>[ 19.974322] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11100 01:27:04.125062 <6>[ 19.974343] pci 0000:00:00.0: PCI bridge to [bus 01]
11101 01:27:04.131906 <6>[ 19.974350] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11102 01:27:04.138485 <6>[ 19.974873] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11103 01:27:04.145630 <6>[ 19.976299] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11104 01:27:04.152480 <3>[ 19.977318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11105 01:27:04.159211 <3>[ 19.977371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11106 01:27:04.168766 <3>[ 19.977594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11107 01:27:04.175624 <3>[ 19.977604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11108 01:27:04.185595 <3>[ 19.977612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11109 01:27:04.192848 <3>[ 19.977625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11110 01:27:04.199582 <3>[ 19.977633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11111 01:27:04.209854 <3>[ 19.977684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11112 01:27:04.216309 <6>[ 19.984116] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11113 01:27:04.223188 <6>[ 19.984116] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11114 01:27:04.229919 <6>[ 19.984136] remoteproc remoteproc0: remote processor scp is now up
11115 01:27:04.239809 <3>[ 20.013869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11116 01:27:04.251031 <6>[ 20.018875] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11117 01:27:04.254327 <6>[ 20.021165] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11118 01:27:04.264165 <6>[ 20.028312] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11119 01:27:04.270863 <6>[ 20.032486] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11120 01:27:04.281104 <6>[ 20.057165] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11121 01:27:04.288145 <5>[ 20.064551] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11122 01:27:04.294858 <6>[ 20.069264] usbcore: registered new interface driver cdc_ether
11123 01:27:04.304337 <3>[ 20.072626] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11124 01:27:04.311397 <6>[ 20.084639] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11125 01:27:04.317606 <6>[ 20.089597] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11126 01:27:04.324493 <5>[ 20.093482] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11127 01:27:04.334846 <4>[ 20.093561] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11128 01:27:04.338001 <6>[ 20.093570] cfg80211: failed to load regulatory.db
11129 01:27:04.344340 <6>[ 20.103749] usbcore: registered new interface driver r8153_ecm
11130 01:27:04.348388 <6>[ 20.103790] Bluetooth: Core ver 2.22
11131 01:27:04.354206 <6>[ 20.103879] NET: Registered PF_BLUETOOTH protocol family
11132 01:27:04.361277 <6>[ 20.103882] Bluetooth: HCI device and connection manager initialized
11133 01:27:04.368259 <6>[ 20.103902] Bluetooth: HCI socket layer initialized
11134 01:27:04.371377 <6>[ 20.103908] Bluetooth: L2CAP socket layer initialized
11135 01:27:04.377895 <6>[ 20.103920] Bluetooth: SCO socket layer initialized
11136 01:27:04.388061 <6>[ 20.111387] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11137 01:27:04.398275 <4>[ 20.118609] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11138 01:27:04.404409 <6>[ 20.125215] usbcore: registered new interface driver uvcvideo
11139 01:27:04.411200 <6>[ 20.127211] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11140 01:27:04.418033 <4>[ 20.133133] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11141 01:27:04.427582 <3>[ 20.147022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11142 01:27:04.438158 <3>[ 20.147646] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
11143 01:27:04.440869 <6>[ 20.149589] usbcore: registered new interface driver btusb
11144 01:27:04.450930 <4>[ 20.149965] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11145 01:27:04.457853 <3>[ 20.149970] Bluetooth: hci0: Failed to load firmware file (-2)
11146 01:27:04.463934 <3>[ 20.149972] Bluetooth: hci0: Failed to set up firmware (-2)
11147 01:27:04.473943 <4>[ 20.149976] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11148 01:27:04.483549 <3>[ 20.154784] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11149 01:27:04.490586 <3>[ 20.177402] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11150 01:27:04.501070 <6>[ 20.195996] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11151 01:27:04.504725 <6>[ 20.198357] r8152 2-1.3:1.0 eth0: v1.12.13
11152 01:27:04.510801 <6>[ 20.208530] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11153 01:27:04.517864 <6>[ 20.215535] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11154 01:27:04.524188 <3>[ 20.224338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11155 01:27:04.531283 <6>[ 20.252011] mt7921e 0000:01:00.0: ASIC revision: 79610010
11156 01:27:04.541177 <3>[ 20.280033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11157 01:27:04.551427 <4>[ 20.372967] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11158 01:27:04.561275 <3>[ 20.397129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11159 01:27:04.571212 <4>[ 20.507518] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11160 01:27:04.581402 <3>[ 20.534880] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11161 01:27:04.584599 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11162 01:27:04.626628 <4>[ 20.645173] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11163 01:27:04.722722 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11164 01:27:04.744223 [[0;32m OK [<4>[ 20.763931] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11165 01:27:04.750825 0m] Reached target [0;1;39mBluetooth[0m.
11166 01:27:04.765429 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11167 01:27:04.781425 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11168 01:27:04.804801 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11169 01:27:04.862022 <4>[ 20.880620] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11170 01:27:04.868643 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11171 01:27:04.889630 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11172 01:27:04.906228 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11173 01:27:04.926777 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11174 01:27:04.941820 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11175 01:27:04.961605 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11176 01:27:04.980781 [[0;32m OK [<4>[ 21.000704] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11177 01:27:04.987181 0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11178 01:27:05.001893 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11179 01:27:05.021458 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11180 01:27:05.033309 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11181 01:27:05.049164 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11182 01:27:05.101684 <4>[ 21.120510] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11183 01:27:05.115530 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11184 01:27:05.148669 Starting [0;1;39mUser Login Management[0m...
11185 01:27:05.169003 Starting [0;1;39mPermit User Sessions[0m...
11186 01:27:05.188618 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11187 01:27:05.203401 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11188 01:27:05.222865 <4>[ 21.241815] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11189 01:27:05.231055 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11190 01:27:05.239167 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11191 01:27:05.256244 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11192 01:27:05.275274 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11193 01:27:05.294030 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11194 01:27:05.341827 <4>[ 21.360227] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11195 01:27:05.363573 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11196 01:27:05.405450 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11197 01:27:05.462333 <4>[ 21.480830] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11198 01:27:05.462809
11199 01:27:05.463137
11200 01:27:05.468804 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11201 01:27:05.469223
11202 01:27:05.472460 debian-bullseye-arm64 login: root (automatic login)
11203 01:27:05.472931
11204 01:27:05.473269
11205 01:27:05.507797 Linux debian-bullseye-arm64 6.1.46-cip4 #1 SMP PREEMPT Mon Aug 28 01:06:33 UTC 2023 aarch64
11206 01:27:05.508234
11207 01:27:05.514488 The programs included with the Debian GNU/Linux system are free software;
11208 01:27:05.520505 the exact distribution terms for each program are described in the
11209 01:27:05.524331 individual files in /usr/share/doc/*/copyright.
11210 01:27:05.524923
11211 01:27:05.530726 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11212 01:27:05.534133 permitted by applicable law.
11213 01:27:05.535261 Matched prompt #10: / #
11215 01:27:05.536243 Setting prompt string to ['/ #']
11216 01:27:05.536661 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11218 01:27:05.537881 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11219 01:27:05.538317 start: 2.2.6 expect-shell-connection (timeout 00:01:51) [common]
11220 01:27:05.538671 Setting prompt string to ['/ #']
11221 01:27:05.538979 Forcing a shell prompt, looking for ['/ #']
11223 01:27:05.589705 / #
11224 01:27:05.590055 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11225 01:27:05.590322 Waiting using forced prompt support (timeout 00:02:30)
11226 01:27:05.590646 <3>[ 21.598749] mt7921e 0000:01:00.0: hardware init failed
11227 01:27:05.594885
11228 01:27:05.595466 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11229 01:27:05.595791 start: 2.2.7 export-device-env (timeout 00:01:51) [common]
11230 01:27:05.596124 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11231 01:27:05.596493 end: 2.2 depthcharge-retry (duration 00:03:09) [common]
11232 01:27:05.596848 end: 2 depthcharge-action (duration 00:03:09) [common]
11233 01:27:05.597161 start: 3 lava-test-retry (timeout 00:05:00) [common]
11234 01:27:05.597469 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11235 01:27:05.597732 Using namespace: common
11237 01:27:05.698465 / # #
11238 01:27:05.698943 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11239 01:27:05.704615 #
11240 01:27:05.705447 Using /lava-11368532
11242 01:27:05.806525 / # export SHELL=/bin/sh
11243 01:27:05.812791 export SHELL=/bin/sh
11245 01:27:05.914062 / # . /lava-11368532/environment
11246 01:27:05.920473 . /lava-11368532/environment
11248 01:27:06.021852 / # /lava-11368532/bin/lava-test-runner /lava-11368532/0
11249 01:27:06.022044 Test shell timeout: 10s (minimum of the action and connection timeout)
11250 01:27:06.027392 /lava-11368532/bin/lava-test-runner /lava-11368532/0
11251 01:27:06.049495 + export TESTRUN_ID=0_sleep
11252 01:27:06.052134 + cd /lava-11368532/0/tests/0_sleep
11253 01:27:06.055731 + cat uuid
11254 01:27:06.055979 + UUID=11368532_1.5.2.3.1
11255 01:27:06.059307 + set +x
11256 01:27:06.061976 <LAVA_SIGNAL_STARTRUN 0_sleep 11368532_1.5.2.3.1>
11257 01:27:06.062453 Received signal: <STARTRUN> 0_sleep 11368532_1.5.2.3.1
11258 01:27:06.062757 Starting test lava.0_sleep (11368532_1.5.2.3.1)
11259 01:27:06.062999 Skipping test definition patterns.
11260 01:27:06.065495 + ./config/lava/sleep/sleep.sh mem freeze
11261 01:27:06.068832 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11263 01:27:06.072070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11264 01:27:06.075323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11265 01:27:06.075890 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11267 01:27:06.078961 rtcwake: assuming RTC uses UTC ...
11268 01:27:06.089230 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:12<6>[ 22.114939] PM: suspend entry (deep)
11269 01:27:06.092564 <6>[ 22.119329] Filesystems sync: 0.000 seconds
11270 01:27:06.095802 2023
11271 01:27:06.098563 <6>[ 22.125971] Freezing user space processes
11272 01:27:06.110116 <6>[ 22.132259] Freezing user space processes completed (elapsed 0.001 seconds)
11273 01:27:06.113275 <6>[ 22.139520] OOM killer disabled.
11274 01:27:06.116553 <6>[ 22.143011] Freezing remaining freezable tasks
11275 01:27:06.126357 <6>[ 22.148942] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11276 01:27:06.133379 <6>[ 22.156619] printk: Suspending console(s) (use no_console_suspend to debug)
11277 01:27:09.366052 <3>[ 25.166424] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11278 01:27:09.376104 <3>[ 25.166459] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11279 01:27:09.385919 <3>[ 25.166486] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11280 01:27:09.392976 <3>[ 25.166509] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11281 01:27:09.399334 <3>[ 25.166697] PM: Some devices failed to suspend, or early wake event detected
11282 01:27:09.406046 <4>[ 25.183363] typec port0-partner: PM: parent port0 should not be sleeping
11283 01:27:09.412716 <6>[ 25.438620] OOM killer enabled.
11284 01:27:09.416195 <6>[ 25.442022] Restarting tasks ... done.
11285 01:27:09.422689 <5>[ 25.448274] random: crng reseeded on system resumption
11286 01:27:09.426280 <6>[ 25.455673] PM: suspend exit
11287 01:27:09.429760 rtcwake: write error
11288 01:27:09.437352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11289 01:27:09.438015 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11291 01:27:09.440592 rtcwake: assuming RTC uses UTC ...
11292 01:27:09.447053 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:15 2023
11293 01:27:09.459449 <6>[ 25.485303] PM: suspend entry (deep)
11294 01:27:09.462976 <6>[ 25.489221] Filesystems sync: 0.000 seconds
11295 01:27:09.466572 <6>[ 25.494294] Freezing user space processes
11296 01:27:09.477879 <6>[ 25.500233] Freezing user space processes completed (elapsed 0.001 seconds)
11297 01:27:09.481315 <6>[ 25.507474] OOM killer disabled.
11298 01:27:09.484739 <6>[ 25.510958] Freezing remaining freezable tasks
11299 01:27:09.494827 <6>[ 25.516833] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11300 01:27:09.501426 <6>[ 25.524486] printk: Suspending console(s) (use no_console_suspend to debug)
11301 01:27:12.950386 <3>[ 28.750383] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11302 01:27:12.960285 <3>[ 28.750412] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11303 01:27:12.970434 <3>[ 28.750457] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11304 01:27:12.977485 <3>[ 28.750497] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11305 01:27:12.983909 <3>[ 28.750798] PM: Some devices failed to suspend, or early wake event detected
11306 01:27:12.987069 <6>[ 29.016366] OOM killer enabled.
11307 01:27:12.996755 <6>[ 29.019783] Restarting tasks ... done.
11308 01:27:13.000217 <5>[ 29.027112] random: crng reseeded on system resumption
11309 01:27:13.004906 <6>[ 29.034434] PM: suspend exit
11310 01:27:13.008343 rtcwake: write error
11311 01:27:13.016943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11312 01:27:13.017769 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11314 01:27:13.020329 rtcwake: assuming RTC uses UTC ...
11315 01:27:13.027062 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:19 2023
11316 01:27:13.039972 <6>[ 29.065921] PM: suspend entry (deep)
11317 01:27:13.042781 <6>[ 29.069811] Filesystems sync: 0.000 seconds
11318 01:27:13.046153 <6>[ 29.074844] Freezing user space processes
11319 01:27:13.057671 <6>[ 29.080743] Freezing user space processes completed (elapsed 0.001 seconds)
11320 01:27:13.061080 <6>[ 29.087973] OOM killer disabled.
11321 01:27:13.064417 <6>[ 29.091456] Freezing remaining freezable tasks
11322 01:27:13.075009 <6>[ 29.097448] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11323 01:27:13.081223 <6>[ 29.105101] printk: Suspending console(s) (use no_console_suspend to debug)
11324 01:27:16.541929 <3>[ 32.334341] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11325 01:27:16.551743 <3>[ 32.334371] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11326 01:27:16.561667 <3>[ 32.334416] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11327 01:27:16.568304 <3>[ 32.334455] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11328 01:27:16.575297 <3>[ 32.334744] PM: Some devices failed to suspend, or early wake event detected
11329 01:27:16.578620 <6>[ 32.608391] OOM killer enabled.
11330 01:27:16.586905 <6>[ 32.611808] Restarting tasks ... done.
11331 01:27:16.593665 <5>[ 32.619574] random: crng reseeded on system resumption
11332 01:27:16.597255 <6>[ 32.625853] PM: suspend exit
11333 01:27:16.600717 rtcwake: write error
11334 01:27:16.606998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11335 01:27:16.607256 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11337 01:27:16.610292 rtcwake: assuming RTC uses UTC ...
11338 01:27:16.613789 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:22 2023
11339 01:27:16.628159 <6>[ 32.655418] PM: suspend entry (deep)
11340 01:27:16.631547 <6>[ 32.659305] Filesystems sync: 0.000 seconds
11341 01:27:16.635062 <6>[ 32.664351] Freezing user space processes
11342 01:27:16.646715 <6>[ 32.670113] Freezing user space processes completed (elapsed 0.001 seconds)
11343 01:27:16.650078 <6>[ 32.677333] OOM killer disabled.
11344 01:27:16.653347 <6>[ 32.680812] Freezing remaining freezable tasks
11345 01:27:16.663140 <6>[ 32.686681] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11346 01:27:16.669513 <6>[ 32.694336] printk: Suspending console(s) (use no_console_suspend to debug)
11347 01:27:20.125422 <3>[ 35.918342] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11348 01:27:20.135225 <3>[ 35.918371] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11349 01:27:20.145112 <3>[ 35.918417] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11350 01:27:20.151631 <3>[ 35.918457] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11351 01:27:20.158500 <3>[ 35.918693] PM: Some devices failed to suspend, or early wake event detected
11352 01:27:20.161949 <6>[ 36.192362] OOM killer enabled.
11353 01:27:20.170405 <6>[ 36.195774] Restarting tasks ... done.
11354 01:27:20.177126 <5>[ 36.202900] random: crng reseeded on system resumption
11355 01:27:20.180346 <6>[ 36.209603] PM: suspend exit
11356 01:27:20.184069 rtcwake: write error
11357 01:27:20.190664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11358 01:27:20.190918 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11360 01:27:20.194134 rtcwake: assuming RTC uses UTC ...
11361 01:27:20.201192 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:26 2023
11362 01:27:20.212745 <6>[ 36.240031] PM: suspend entry (deep)
11363 01:27:20.215798 <6>[ 36.243920] Filesystems sync: 0.000 seconds
11364 01:27:20.219258 <6>[ 36.248955] Freezing user space processes
11365 01:27:20.230968 <6>[ 36.254780] Freezing user space processes completed (elapsed 0.001 seconds)
11366 01:27:20.234210 <6>[ 36.261999] OOM killer disabled.
11367 01:27:20.237116 <6>[ 36.265478] Freezing remaining freezable tasks
11368 01:27:20.247302 <6>[ 36.271360] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11369 01:27:20.254008 <6>[ 36.279014] printk: Suspending console(s) (use no_console_suspend to debug)
11370 01:27:23.708640 <3>[ 39.502341] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11371 01:27:23.718825 <3>[ 39.502371] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11372 01:27:23.728949 <3>[ 39.502415] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11373 01:27:23.735285 <3>[ 39.502455] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11374 01:27:23.742242 <3>[ 39.502741] PM: Some devices failed to suspend, or early wake event detected
11375 01:27:23.749111 <6>[ 39.776227] OOM killer enabled.
11376 01:27:23.751978 <6>[ 39.779637] Restarting tasks ... done.
11377 01:27:23.759082 <5>[ 39.785718] random: crng reseeded on system resumption
11378 01:27:23.762153 <6>[ 39.792371] PM: suspend exit
11379 01:27:23.765531 rtcwake: write error
11380 01:27:23.771904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11381 01:27:23.772698 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11383 01:27:23.775540 rtcwake: assuming RTC uses UTC ...
11384 01:27:23.781896 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:29 2023
11385 01:27:23.794454 <6>[ 39.822051] PM: suspend entry (deep)
11386 01:27:23.798020 <6>[ 39.825923] Filesystems sync: 0.000 seconds
11387 01:27:23.801547 <6>[ 39.830970] Freezing user space processes
11388 01:27:23.813084 <6>[ 39.836965] Freezing user space processes completed (elapsed 0.001 seconds)
11389 01:27:23.816241 <6>[ 39.844199] OOM killer disabled.
11390 01:27:23.819669 <6>[ 39.847681] Freezing remaining freezable tasks
11391 01:27:23.829822 <6>[ 39.853785] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11392 01:27:23.836595 <6>[ 39.861458] printk: Suspending console(s) (use no_console_suspend to debug)
11393 01:27:27.292422 <3>[ 43.086351] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11394 01:27:27.302514 <3>[ 43.086382] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11395 01:27:27.312846 <3>[ 43.086426] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11396 01:27:27.319423 <3>[ 43.086466] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11397 01:27:27.325921 <3>[ 43.086716] PM: Some devices failed to suspend, or early wake event detected
11398 01:27:27.329460 <6>[ 43.360494] OOM killer enabled.
11399 01:27:27.337837 <6>[ 43.363905] Restarting tasks ... done.
11400 01:27:27.340940 <5>[ 43.370051] random: crng reseeded on system resumption
11401 01:27:27.345284 <6>[ 43.376742] PM: suspend exit
11402 01:27:27.348406 rtcwake: write error
11403 01:27:27.355994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11404 01:27:27.356284 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11406 01:27:27.358830 rtcwake: assuming RTC uses UTC ...
11407 01:27:27.365765 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:33 2023
11408 01:27:27.378312 <6>[ 43.406453] PM: suspend entry (deep)
11409 01:27:27.381576 <6>[ 43.410353] Filesystems sync: 0.000 seconds
11410 01:27:27.384891 <6>[ 43.415353] Freezing user space processes
11411 01:27:27.396743 <6>[ 43.421224] Freezing user space processes completed (elapsed 0.001 seconds)
11412 01:27:27.399619 <6>[ 43.428442] OOM killer disabled.
11413 01:27:27.402806 <6>[ 43.431921] Freezing remaining freezable tasks
11414 01:27:27.412912 <6>[ 43.438015] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11415 01:27:27.419664 <6>[ 43.445695] printk: Suspending console(s) (use no_console_suspend to debug)
11416 01:27:30.875859 <3>[ 46.670395] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11417 01:27:30.885867 <3>[ 46.670430] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11418 01:27:30.896075 <3>[ 46.670481] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11419 01:27:30.902871 <3>[ 46.670529] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11420 01:27:30.909764 <3>[ 46.671063] PM: Some devices failed to suspend, or early wake event detected
11421 01:27:30.912587 <6>[ 46.944434] OOM killer enabled.
11422 01:27:30.921368 <6>[ 46.947844] Restarting tasks ... done.
11423 01:27:30.928277 <5>[ 46.955407] random: crng reseeded on system resumption
11424 01:27:30.930982 <6>[ 46.962124] PM: suspend exit
11425 01:27:30.935068 rtcwake: write error
11426 01:27:30.941487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11427 01:27:30.941747 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11429 01:27:30.944776 rtcwake: assuming RTC uses UTC ...
11430 01:27:30.951663 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:37 2023
11431 01:27:30.963272 <6>[ 46.991577] PM: suspend entry (deep)
11432 01:27:30.966191 <6>[ 46.995467] Filesystems sync: 0.000 seconds
11433 01:27:30.969878 <6>[ 47.000466] Freezing user space processes
11434 01:27:30.980823 <6>[ 47.006179] Freezing user space processes completed (elapsed 0.001 seconds)
11435 01:27:30.984308 <6>[ 47.013398] OOM killer disabled.
11436 01:27:30.987425 <6>[ 47.016879] Freezing remaining freezable tasks
11437 01:27:30.997956 <6>[ 47.022838] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11438 01:27:31.004205 <6>[ 47.030490] printk: Suspending console(s) (use no_console_suspend to debug)
11439 01:27:34.456188 <6>[ 48.206449] vpu: disabling
11440 01:27:34.459403 <6>[ 48.206589] vproc2: disabling
11441 01:27:34.462985 <6>[ 48.206648] vproc1: disabling
11442 01:27:34.466053 <6>[ 48.206703] vaud18: disabling
11443 01:27:34.469484 <6>[ 48.206949] vsram_others: disabling
11444 01:27:34.472714 <6>[ 48.207147] va09: disabling
11445 01:27:34.475931 <6>[ 48.207224] vsram_md: disabling
11446 01:27:34.479270 <6>[ 48.207351] Vgpu: disabling
11447 01:27:34.486413 <3>[ 50.254348] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11448 01:27:34.496147 <3>[ 50.254379] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11449 01:27:34.506464 <3>[ 50.254423] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11450 01:27:34.513032 <3>[ 50.254464] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11451 01:27:34.519818 <3>[ 50.254725] PM: Some devices failed to suspend, or early wake event detected
11452 01:27:34.523241 <6>[ 50.554293] OOM killer enabled.
11453 01:27:34.530072 <6>[ 50.557692] Restarting tasks ... done.
11454 01:27:34.537469 <5>[ 50.564289] random: crng reseeded on system resumption
11455 01:27:34.540286 <6>[ 50.571077] PM: suspend exit
11456 01:27:34.543746 rtcwake: write error
11457 01:27:34.550816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11458 01:27:34.551077 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11460 01:27:34.553908 rtcwake: assuming RTC uses UTC ...
11461 01:27:34.557124 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:40 2023
11462 01:27:34.570718 <6>[ 50.599849] PM: suspend entry (deep)
11463 01:27:34.573998 <6>[ 50.603747] Filesystems sync: 0.000 seconds
11464 01:27:34.577452 <6>[ 50.608768] Freezing user space processes
11465 01:27:34.588301 <6>[ 50.614187] Freezing user space processes completed (elapsed 0.001 seconds)
11466 01:27:34.591876 <6>[ 50.621406] OOM killer disabled.
11467 01:27:34.594797 <6>[ 50.624885] Freezing remaining freezable tasks
11468 01:27:34.605231 <6>[ 50.630794] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11469 01:27:34.611772 <6>[ 50.638446] printk: Suspending console(s) (use no_console_suspend to debug)
11470 01:27:38.044249 <3>[ 53.838361] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11471 01:27:38.053753 <3>[ 53.838392] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11472 01:27:38.063701 <3>[ 53.838436] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11473 01:27:38.070122 <3>[ 53.838479] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11474 01:27:38.076192 <3>[ 53.838735] PM: Some devices failed to suspend, or early wake event detected
11475 01:27:38.079843 <6>[ 54.112511] OOM killer enabled.
11476 01:27:38.088442 <6>[ 54.115922] Restarting tasks ... done.
11477 01:27:38.095331 <5>[ 54.123213] random: crng reseeded on system resumption
11478 01:27:38.098546 <6>[ 54.129797] PM: suspend exit
11479 01:27:38.101802 rtcwake: write error
11480 01:27:38.108624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11481 01:27:38.109071 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11483 01:27:38.111789 rtcwake: assuming RTC uses UTC ...
11484 01:27:38.115497 rtcwake: wakeup from "mem" using rtc0 at Mon Aug 28 01:27:44 2023
11485 01:27:38.129948 <6>[ 54.158634] PM: suspend entry (deep)
11486 01:27:38.132823 <6>[ 54.162539] Filesystems sync: 0.000 seconds
11487 01:27:38.136464 <6>[ 54.167589] Freezing user space processes
11488 01:27:38.148508 <6>[ 54.173529] Freezing user space processes completed (elapsed 0.001 seconds)
11489 01:27:38.151429 <6>[ 54.180765] OOM killer disabled.
11490 01:27:38.155261 <6>[ 54.184246] Freezing remaining freezable tasks
11491 01:27:38.165159 <6>[ 54.190293] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11492 01:27:38.171484 <6>[ 54.197963] printk: Suspending console(s) (use no_console_suspend to debug)
11493 01:27:41.626862 <3>[ 57.422381] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11494 01:27:41.636958 <3>[ 57.422414] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11495 01:27:41.647768 <3>[ 57.422463] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11496 01:27:41.653714 <3>[ 57.422508] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11497 01:27:41.660801 <3>[ 57.422844] PM: Some devices failed to suspend, or early wake event detected
11498 01:27:41.663543 <6>[ 57.696468] OOM killer enabled.
11499 01:27:41.672363 <6>[ 57.699880] Restarting tasks ... done.
11500 01:27:41.678966 <5>[ 57.707112] random: crng reseeded on system resumption
11501 01:27:41.682627 <6>[ 57.713673] PM: suspend exit
11502 01:27:41.685325 rtcwake: write error
11503 01:27:41.692279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11504 01:27:41.693197 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11506 01:27:41.695757 rtcwake: assuming RTC uses UTC ...
11507 01:27:41.698947 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:27:47 2023
11508 01:27:41.714798 <6>[ 57.743918] PM: suspend entry (s2idle)
11509 01:27:41.718191 <6>[ 57.747994] Filesystems sync: 0.000 seconds
11510 01:27:41.721313 <6>[ 57.753040] Freezing user space processes
11511 01:27:41.732788 <6>[ 57.758887] Freezing user space processes completed (elapsed 0.001 seconds)
11512 01:27:41.736310 <6>[ 57.766112] OOM killer disabled.
11513 01:27:41.738968 <6>[ 57.769590] Freezing remaining freezable tasks
11514 01:27:41.749305 <6>[ 57.775664] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11515 01:27:41.755923 <6>[ 57.783337] printk: Suspending console(s) (use no_console_suspend to debug)
11516 01:27:45.210855 <3>[ 61.006342] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11517 01:27:45.220814 <3>[ 61.006373] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11518 01:27:45.230688 <3>[ 61.006417] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11519 01:27:45.238041 <3>[ 61.006458] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11520 01:27:45.244234 <3>[ 61.006755] PM: Some devices failed to suspend, or early wake event detected
11521 01:27:45.247546 <6>[ 61.280382] OOM killer enabled.
11522 01:27:45.255576 <6>[ 61.283793] Restarting tasks ... done.
11523 01:27:45.258923 <5>[ 61.289692] random: crng reseeded on system resumption
11524 01:27:45.262791 <6>[ 61.296049] PM: suspend exit
11525 01:27:45.266282 rtcwake: write error
11526 01:27:45.274490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11527 01:27:45.275316 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11529 01:27:45.277624 rtcwake: assuming RTC uses UTC ...
11530 01:27:45.284490 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:27:51 2023
11531 01:27:45.296782 <6>[ 61.326569] PM: suspend entry (s2idle)
11532 01:27:45.299993 <6>[ 61.330633] Filesystems sync: 0.000 seconds
11533 01:27:45.303255 <6>[ 61.335667] Freezing user space processes
11534 01:27:45.315291 <6>[ 61.341563] Freezing user space processes completed (elapsed 0.001 seconds)
11535 01:27:45.318243 <6>[ 61.348793] OOM killer disabled.
11536 01:27:45.321499 <6>[ 61.352273] Freezing remaining freezable tasks
11537 01:27:45.331795 <6>[ 61.358288] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11538 01:27:45.338635 <6>[ 61.365956] printk: Suspending console(s) (use no_console_suspend to debug)
11539 01:27:48.790226 <3>[ 64.590329] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11540 01:27:48.800551 <3>[ 64.590357] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11541 01:27:48.810702 <3>[ 64.590399] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11542 01:27:48.817179 <3>[ 64.590436] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11543 01:27:48.823927 <3>[ 64.590725] PM: Some devices failed to suspend, or early wake event detected
11544 01:27:48.826993 <6>[ 64.860236] OOM killer enabled.
11545 01:27:48.838301 <6>[ 64.863646] Restarting tasks ... done.
11546 01:27:48.841284 <5>[ 64.872368] random: crng reseeded on system resumption
11547 01:27:48.845732 <6>[ 64.879319] PM: suspend exit
11548 01:27:48.848775 rtcwake: write error
11549 01:27:48.855571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11550 01:27:48.856369 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11552 01:27:48.859075 rtcwake: assuming RTC uses UTC ...
11553 01:27:48.865515 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:27:54 2023
11554 01:27:48.877455 <6>[ 64.908117] PM: suspend entry (s2idle)
11555 01:27:48.880911 <6>[ 64.912191] Filesystems sync: 0.000 seconds
11556 01:27:48.887862 <6>[ 64.917188] Freezing user space processes
11557 01:27:48.894602 <6>[ 64.923161] Freezing user space processes completed (elapsed 0.001 seconds)
11558 01:27:48.898178 <6>[ 64.930391] OOM killer disabled.
11559 01:27:48.904457 <6>[ 64.933868] Freezing remaining freezable tasks
11560 01:27:48.910996 <6>[ 64.939989] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11561 01:27:48.920721 <6>[ 64.947662] printk: Suspending console(s) (use no_console_suspend to debug)
11562 01:27:52.377812 <3>[ 68.174340] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11563 01:27:52.387703 <3>[ 68.174370] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11564 01:27:52.397924 <3>[ 68.174415] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11565 01:27:52.404738 <3>[ 68.174456] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11566 01:27:52.411137 <3>[ 68.174747] PM: Some devices failed to suspend, or early wake event detected
11567 01:27:52.414253 <6>[ 68.448354] OOM killer enabled.
11568 01:27:52.423310 <6>[ 68.451767] Restarting tasks ... done.
11569 01:27:52.429544 <5>[ 68.458651] random: crng reseeded on system resumption
11570 01:27:52.432743 <6>[ 68.465223] PM: suspend exit
11571 01:27:52.436128 rtcwake: write error
11572 01:27:52.443025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11573 01:27:52.443742 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11575 01:27:52.446290 rtcwake: assuming RTC uses UTC ...
11576 01:27:52.450223 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:27:58 2023
11577 01:27:52.463680 <6>[ 68.494320] PM: suspend entry (s2idle)
11578 01:27:52.466848 <6>[ 68.498383] Filesystems sync: 0.000 seconds
11579 01:27:52.470469 <6>[ 68.503424] Freezing user space processes
11580 01:27:52.481882 <6>[ 68.509359] Freezing user space processes completed (elapsed 0.001 seconds)
11581 01:27:52.485441 <6>[ 68.516591] OOM killer disabled.
11582 01:27:52.488549 <6>[ 68.520072] Freezing remaining freezable tasks
11583 01:27:52.498898 <6>[ 68.526160] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11584 01:27:52.505568 <6>[ 68.533832] printk: Suspending console(s) (use no_console_suspend to debug)
11585 01:27:55.953328 <3>[ 71.758378] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11586 01:27:55.963160 <3>[ 71.758411] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11587 01:27:55.973724 <3>[ 71.758459] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11588 01:27:55.979749 <3>[ 71.758500] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11589 01:27:55.986299 <3>[ 71.758764] PM: Some devices failed to suspend, or early wake event detected
11590 01:27:55.989733 <6>[ 72.024196] OOM killer enabled.
11591 01:27:56.002812 <6>[ 72.027608] Restarting tasks ... done.
11592 01:27:56.006072 <5>[ 72.038173] random: crng reseeded on system resumption
11593 01:27:56.013507 rtcwake: <6>[ 72.044895] PM: suspend exit
11594 01:27:56.014054 write error
11595 01:27:56.020760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11596 01:27:56.021458 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11598 01:27:56.024395 rtcwake: assuming RTC uses UTC ...
11599 01:27:56.031056 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:28:02 2023
11600 01:27:56.043106 <6>[ 72.074470] PM: suspend entry (s2idle)
11601 01:27:56.046689 <6>[ 72.078551] Filesystems sync: 0.000 seconds
11602 01:27:56.049664 <6>[ 72.083542] Freezing user space processes
11603 01:27:56.061542 <6>[ 72.089478] Freezing user space processes completed (elapsed 0.001 seconds)
11604 01:27:56.064999 <6>[ 72.096707] OOM killer disabled.
11605 01:27:56.068233 <6>[ 72.100187] Freezing remaining freezable tasks
11606 01:27:56.078580 <6>[ 72.106303] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11607 01:27:56.085133 <6>[ 72.113968] printk: Suspending console(s) (use no_console_suspend to debug)
11608 01:27:59.545027 <3>[ 75.342354] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11609 01:27:59.554700 <3>[ 75.342384] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11610 01:27:59.565109 <3>[ 75.342439] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11611 01:27:59.571504 <3>[ 75.342480] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11612 01:27:59.578483 <3>[ 75.342780] PM: Some devices failed to suspend, or early wake event detected
11613 01:27:59.581504 <6>[ 75.616358] OOM killer enabled.
11614 01:27:59.590171 <6>[ 75.619768] Restarting tasks ... done.
11615 01:27:59.597132 <5>[ 75.627406] random: crng reseeded on system resumption
11616 01:27:59.600108 <6>[ 75.634748] PM: suspend exit
11617 01:27:59.603420 rtcwake: write error
11618 01:27:59.610989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11619 01:27:59.611775 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11621 01:27:59.613593 rtcwake: assuming RTC uses UTC ...
11622 01:27:59.620033 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:28:05 2023
11623 01:27:59.632326 <6>[ 75.663900] PM: suspend entry (s2idle)
11624 01:27:59.635983 <6>[ 75.667962] Filesystems sync: 0.000 seconds
11625 01:27:59.638996 <6>[ 75.673018] Freezing user space processes
11626 01:27:59.650276 <6>[ 75.678770] Freezing user space processes completed (elapsed 0.001 seconds)
11627 01:27:59.653406 <6>[ 75.685988] OOM killer disabled.
11628 01:27:59.657253 <6>[ 75.689467] Freezing remaining freezable tasks
11629 01:27:59.666900 <6>[ 75.695350] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11630 01:27:59.673538 <6>[ 75.703000] printk: Suspending console(s) (use no_console_suspend to debug)
11631 01:28:03.120822 <3>[ 78.926355] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11632 01:28:03.130282 <3>[ 78.926385] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11633 01:28:03.140524 <3>[ 78.926430] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11634 01:28:03.147042 <3>[ 78.926469] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11635 01:28:03.153962 <3>[ 78.926767] PM: Some devices failed to suspend, or early wake event detected
11636 01:28:03.157145 <6>[ 79.192236] OOM killer enabled.
11637 01:28:03.165252 <6>[ 79.195653] Restarting tasks ... done.
11638 01:28:03.169069 <5>[ 79.201529] random: crng reseeded on system resumption
11639 01:28:03.173694 <6>[ 79.209255] PM: suspend exit
11640 01:28:03.176981 rtcwake: write error
11641 01:28:03.184773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11642 01:28:03.185470 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11644 01:28:03.188316 rtcwake: assuming RTC uses UTC ...
11645 01:28:03.194610 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:28:09 2023
11646 01:28:03.207710 <6>[ 79.238990] PM: suspend entry (s2idle)
11647 01:28:03.211127 <6>[ 79.243050] Filesystems sync: 0.000 seconds
11648 01:28:03.213613 <6>[ 79.248034] Freezing user space processes
11649 01:28:03.225155 <6>[ 79.253930] Freezing user space processes completed (elapsed 0.001 seconds)
11650 01:28:03.228320 <6>[ 79.261164] OOM killer disabled.
11651 01:28:03.232461 <6>[ 79.264645] Freezing remaining freezable tasks
11652 01:28:03.242344 <6>[ 79.270079] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11653 01:28:03.248991 <6>[ 79.277731] printk: Suspending console(s) (use no_console_suspend to debug)
11654 01:28:06.712193 <3>[ 82.510381] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11655 01:28:06.722195 <3>[ 82.510414] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11656 01:28:06.732254 <3>[ 82.510471] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11657 01:28:06.739248 <3>[ 82.510517] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11658 01:28:06.745587 <3>[ 82.510835] PM: Some devices failed to suspend, or early wake event detected
11659 01:28:06.748548 <6>[ 82.784374] OOM killer enabled.
11660 01:28:06.757576 <6>[ 82.787784] Restarting tasks ... done.
11661 01:28:06.764344 <5>[ 82.796036] random: crng reseeded on system resumption
11662 01:28:06.767829 <6>[ 82.802770] PM: suspend exit
11663 01:28:06.771252 rtcwake: write error
11664 01:28:06.777951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11665 01:28:06.778733 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11667 01:28:06.781831 rtcwake: assuming RTC uses UTC ...
11668 01:28:06.788163 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:28:12 2023
11669 01:28:06.799471 <6>[ 82.831810] PM: suspend entry (s2idle)
11670 01:28:06.802515 <6>[ 82.835888] Filesystems sync: 0.000 seconds
11671 01:28:06.805922 <6>[ 82.840915] Freezing user space processes
11672 01:28:06.817338 <6>[ 82.846765] Freezing user space processes completed (elapsed 0.001 seconds)
11673 01:28:06.820344 <6>[ 82.853987] OOM killer disabled.
11674 01:28:06.823955 <6>[ 82.857465] Freezing remaining freezable tasks
11675 01:28:06.833820 <6>[ 82.863594] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11676 01:28:06.840443 <6>[ 82.871269] printk: Suspending console(s) (use no_console_suspend to debug)
11677 01:28:10.291904 <3>[ 86.094338] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11678 01:28:10.301756 <3>[ 86.094368] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11679 01:28:10.311338 <3>[ 86.094413] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11680 01:28:10.318055 <3>[ 86.094457] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11681 01:28:10.324832 <3>[ 86.094646] PM: Some devices failed to suspend, or early wake event detected
11682 01:28:10.331800 <6>[ 86.364380] OOM killer enabled.
11683 01:28:10.335283 <6>[ 86.367791] Restarting tasks ... done.
11684 01:28:10.342470 <5>[ 86.375325] random: crng reseeded on system resumption
11685 01:28:10.345936 <6>[ 86.382253] PM: suspend exit
11686 01:28:10.349224 rtcwake: write error
11687 01:28:10.356444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11688 01:28:10.357192 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11690 01:28:10.359852 rtcwake: assuming RTC uses UTC ...
11691 01:28:10.366759 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:28:16 2023
11692 01:28:10.378882 <6>[ 86.411785] PM: suspend entry (s2idle)
11693 01:28:10.382021 <6>[ 86.415852] Filesystems sync: 0.000 seconds
11694 01:28:10.389195 <6>[ 86.420880] Freezing user space processes
11695 01:28:10.395997 <6>[ 86.426681] Freezing user space processes completed (elapsed 0.001 seconds)
11696 01:28:10.398673 <6>[ 86.433899] OOM killer disabled.
11697 01:28:10.406001 <6>[ 86.437380] Freezing remaining freezable tasks
11698 01:28:10.412395 <6>[ 86.443507] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11699 01:28:10.418852 <6>[ 86.451176] printk: Suspending console(s) (use no_console_suspend to debug)
11700 01:28:13.879184 <3>[ 89.678385] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11701 01:28:13.889127 <3>[ 89.678414] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11702 01:28:13.899193 <3>[ 89.678459] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11703 01:28:13.906016 <3>[ 89.678500] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11704 01:28:13.912475 <3>[ 89.678790] PM: Some devices failed to suspend, or early wake event detected
11705 01:28:13.915711 <6>[ 89.952402] OOM killer enabled.
11706 01:28:13.924028 <6>[ 89.955815] Restarting tasks ... done.
11707 01:28:13.927130 <5>[ 89.961574] random: crng reseeded on system resumption
11708 01:28:13.932272 <6>[ 89.969226] PM: suspend exit
11709 01:28:13.935655 rtcwake: write error
11710 01:28:13.942526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11711 01:28:13.943214 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11713 01:28:13.945765 rtcwake: assuming RTC uses UTC ...
11714 01:28:13.952616 rtcwake: wakeup from "freeze" using rtc0 at Mon Aug 28 01:28:20 2023
11715 01:28:13.964760 <6>[ 89.998208] PM: suspend entry (s2idle)
11716 01:28:13.968330 <6>[ 90.002305] Filesystems sync: 0.000 seconds
11717 01:28:13.975160 <6>[ 90.007326] Freezing user space processes
11718 01:28:13.981298 <6>[ 90.013282] Freezing user space processes completed (elapsed 0.001 seconds)
11719 01:28:13.984636 <6>[ 90.020516] OOM killer disabled.
11720 01:28:13.991543 <6>[ 90.023996] Freezing remaining freezable tasks
11721 01:28:13.998206 <6>[ 90.030059] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11722 01:28:14.005023 <6>[ 90.037723] printk: Suspending console(s) (use no_console_suspend to debug)
11723 01:28:17.462878 <3>[ 93.262377] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11724 01:28:17.473032 <3>[ 93.262410] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11725 01:28:17.483077 <3>[ 93.262461] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11726 01:28:17.489749 <3>[ 93.262506] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11727 01:28:17.496268 <3>[ 93.262792] PM: Some devices failed to suspend, or early wake event detected
11728 01:28:17.499376 <6>[ 93.536459] OOM killer enabled.
11729 01:28:17.508185 <6>[ 93.539871] Restarting tasks ... done.
11730 01:28:17.514829 <5>[ 93.547084] random: crng reseeded on system resumption
11731 01:28:17.518363 <6>[ 93.554383] PM: suspend exit
11732 01:28:17.521505 rtcwake: write error
11733 01:28:17.528146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11734 01:28:17.528568 + set +x
11735 01:28:17.529252 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11737 01:28:17.531755 Received signal: <ENDRUN> 0_sleep 11368532_1.5.2.3.1
11738 01:28:17.532209 Ending use of test pattern.
11739 01:28:17.532542 Ending test lava.0_sleep (11368532_1.5.2.3.1), duration 71.47
11741 01:28:17.534690 <LAVA_SIGNAL_ENDRUN 0_sleep 11368532_1.5.2.3.1>
11742 01:28:17.535108 <LAVA_TEST_RUNNER EXIT>
11743 01:28:17.535688 ok: lava_test_shell seems to have completed
11744 01:28:17.536627 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11745 01:28:17.537158 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11746 01:28:17.537587 end: 3 lava-test-retry (duration 00:01:12) [common]
11747 01:28:17.538004 start: 4 finalize (timeout 00:05:06) [common]
11748 01:28:17.538446 start: 4.1 power-off (timeout 00:00:30) [common]
11749 01:28:17.539173 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11750 01:28:17.659838 >> Command sent successfully.
11751 01:28:17.663015 Returned 0 in 0 seconds
11752 01:28:17.763510 end: 4.1 power-off (duration 00:00:00) [common]
11754 01:28:17.763824 start: 4.2 read-feedback (timeout 00:05:06) [common]
11755 01:28:17.764087 Listened to connection for namespace 'common' for up to 1s
11756 01:28:18.764737 Finalising connection for namespace 'common'
11757 01:28:18.764918 Disconnecting from shell: Finalise
11758 01:28:18.765005 / #
11759 01:28:18.865497 end: 4.2 read-feedback (duration 00:00:01) [common]
11760 01:28:18.865810 end: 4 finalize (duration 00:00:01) [common]
11761 01:28:18.866050 Cleaning after the job
11762 01:28:18.866272 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/ramdisk
11763 01:28:18.895081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/kernel
11764 01:28:18.925868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/dtb
11765 01:28:18.926102 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11368532/tftp-deploy-oxmtxrpo/modules
11766 01:28:18.933154 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11368532
11767 01:28:19.103694 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11368532
11768 01:28:19.103885 Job finished correctly