Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 17:43:20.473179 lava-dispatcher, installed at version: 2023.06
2 17:43:20.473378 start: 0 validate
3 17:43:20.473513 Start time: 2023-09-13 17:43:20.473503+00:00 (UTC)
4 17:43:20.473645 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:43:20.473855 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 17:43:20.743148 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:43:20.743926 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:43:20.996652 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:43:20.996917 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:43:21.255566 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:43:21.256255 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 17:43:21.764619 validate duration: 1.29
14 17:43:21.765942 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:43:21.766591 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:43:21.767111 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:43:21.767742 Not decompressing ramdisk as can be used compressed.
18 17:43:21.768222 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 17:43:21.768625 saving as /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/ramdisk/rootfs.cpio.gz
20 17:43:21.769035 total size: 34390042 (32 MB)
21 17:43:21.775191 progress 0 % (0 MB)
22 17:43:21.806269 progress 5 % (1 MB)
23 17:43:21.819691 progress 10 % (3 MB)
24 17:43:21.830107 progress 15 % (4 MB)
25 17:43:21.838883 progress 20 % (6 MB)
26 17:43:21.847702 progress 25 % (8 MB)
27 17:43:21.856359 progress 30 % (9 MB)
28 17:43:21.865167 progress 35 % (11 MB)
29 17:43:21.873897 progress 40 % (13 MB)
30 17:43:21.882677 progress 45 % (14 MB)
31 17:43:21.891259 progress 50 % (16 MB)
32 17:43:21.900003 progress 55 % (18 MB)
33 17:43:21.908496 progress 60 % (19 MB)
34 17:43:21.917270 progress 65 % (21 MB)
35 17:43:21.925881 progress 70 % (22 MB)
36 17:43:21.934863 progress 75 % (24 MB)
37 17:43:21.943479 progress 80 % (26 MB)
38 17:43:21.952156 progress 85 % (27 MB)
39 17:43:21.960628 progress 90 % (29 MB)
40 17:43:21.969208 progress 95 % (31 MB)
41 17:43:21.977578 progress 100 % (32 MB)
42 17:43:21.977758 32 MB downloaded in 0.21 s (157.12 MB/s)
43 17:43:21.977917 end: 1.1.1 http-download (duration 00:00:00) [common]
45 17:43:21.978154 end: 1.1 download-retry (duration 00:00:00) [common]
46 17:43:21.978241 start: 1.2 download-retry (timeout 00:10:00) [common]
47 17:43:21.978325 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 17:43:21.978461 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 17:43:21.978534 saving as /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/kernel/Image
50 17:43:21.978596 total size: 49220096 (46 MB)
51 17:43:21.978657 No compression specified
52 17:43:21.979865 progress 0 % (0 MB)
53 17:43:21.992364 progress 5 % (2 MB)
54 17:43:22.004661 progress 10 % (4 MB)
55 17:43:22.016913 progress 15 % (7 MB)
56 17:43:22.029418 progress 20 % (9 MB)
57 17:43:22.041931 progress 25 % (11 MB)
58 17:43:22.054200 progress 30 % (14 MB)
59 17:43:22.066444 progress 35 % (16 MB)
60 17:43:22.078627 progress 40 % (18 MB)
61 17:43:22.090742 progress 45 % (21 MB)
62 17:43:22.103249 progress 50 % (23 MB)
63 17:43:22.115995 progress 55 % (25 MB)
64 17:43:22.128306 progress 60 % (28 MB)
65 17:43:22.140719 progress 65 % (30 MB)
66 17:43:22.153253 progress 70 % (32 MB)
67 17:43:22.165513 progress 75 % (35 MB)
68 17:43:22.177722 progress 80 % (37 MB)
69 17:43:22.189986 progress 85 % (39 MB)
70 17:43:22.202238 progress 90 % (42 MB)
71 17:43:22.214156 progress 95 % (44 MB)
72 17:43:22.226200 progress 100 % (46 MB)
73 17:43:22.226321 46 MB downloaded in 0.25 s (189.49 MB/s)
74 17:43:22.226471 end: 1.2.1 http-download (duration 00:00:00) [common]
76 17:43:22.226701 end: 1.2 download-retry (duration 00:00:00) [common]
77 17:43:22.226788 start: 1.3 download-retry (timeout 00:10:00) [common]
78 17:43:22.226879 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 17:43:22.227015 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 17:43:22.227086 saving as /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/dtb/mt8192-asurada-spherion-r0.dtb
81 17:43:22.227148 total size: 47278 (0 MB)
82 17:43:22.227210 No compression specified
83 17:43:22.228278 progress 69 % (0 MB)
84 17:43:22.228546 progress 100 % (0 MB)
85 17:43:22.228700 0 MB downloaded in 0.00 s (29.09 MB/s)
86 17:43:22.228824 end: 1.3.1 http-download (duration 00:00:00) [common]
88 17:43:22.229057 end: 1.3 download-retry (duration 00:00:00) [common]
89 17:43:22.229144 start: 1.4 download-retry (timeout 00:10:00) [common]
90 17:43:22.229227 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 17:43:22.229335 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 17:43:22.229403 saving as /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/modules/modules.tar
93 17:43:22.229478 total size: 8628656 (8 MB)
94 17:43:22.229569 Using unxz to decompress xz
95 17:43:22.233475 progress 0 % (0 MB)
96 17:43:22.255230 progress 5 % (0 MB)
97 17:43:22.276797 progress 10 % (0 MB)
98 17:43:22.302203 progress 15 % (1 MB)
99 17:43:22.326539 progress 20 % (1 MB)
100 17:43:22.351433 progress 25 % (2 MB)
101 17:43:22.376868 progress 30 % (2 MB)
102 17:43:22.403099 progress 35 % (2 MB)
103 17:43:22.426957 progress 40 % (3 MB)
104 17:43:22.450630 progress 45 % (3 MB)
105 17:43:22.477056 progress 50 % (4 MB)
106 17:43:22.501797 progress 55 % (4 MB)
107 17:43:22.525801 progress 60 % (4 MB)
108 17:43:22.550047 progress 65 % (5 MB)
109 17:43:22.574578 progress 70 % (5 MB)
110 17:43:22.598378 progress 75 % (6 MB)
111 17:43:22.623784 progress 80 % (6 MB)
112 17:43:22.652780 progress 85 % (7 MB)
113 17:43:22.679216 progress 90 % (7 MB)
114 17:43:22.704942 progress 95 % (7 MB)
115 17:43:22.728075 progress 100 % (8 MB)
116 17:43:22.733306 8 MB downloaded in 0.50 s (16.33 MB/s)
117 17:43:22.733543 end: 1.4.1 http-download (duration 00:00:01) [common]
119 17:43:22.733800 end: 1.4 download-retry (duration 00:00:01) [common]
120 17:43:22.733894 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 17:43:22.733994 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 17:43:22.734077 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 17:43:22.734167 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 17:43:22.734386 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g
125 17:43:22.734514 makedir: /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin
126 17:43:22.734616 makedir: /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/tests
127 17:43:22.734712 makedir: /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/results
128 17:43:22.734826 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-add-keys
129 17:43:22.734969 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-add-sources
130 17:43:22.735102 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-background-process-start
131 17:43:22.735227 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-background-process-stop
132 17:43:22.735350 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-common-functions
133 17:43:22.735471 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-echo-ipv4
134 17:43:22.735594 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-install-packages
135 17:43:22.735717 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-installed-packages
136 17:43:22.735837 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-os-build
137 17:43:22.735958 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-probe-channel
138 17:43:22.736078 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-probe-ip
139 17:43:22.736199 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-target-ip
140 17:43:22.736319 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-target-mac
141 17:43:22.736439 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-target-storage
142 17:43:22.736563 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-case
143 17:43:22.736685 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-event
144 17:43:22.736805 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-feedback
145 17:43:22.736935 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-raise
146 17:43:22.737093 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-reference
147 17:43:22.737214 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-runner
148 17:43:22.737336 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-set
149 17:43:22.737457 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-test-shell
150 17:43:22.737582 Updating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-install-packages (oe)
151 17:43:22.737730 Updating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/bin/lava-installed-packages (oe)
152 17:43:22.737848 Creating /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/environment
153 17:43:22.737947 LAVA metadata
154 17:43:22.738020 - LAVA_JOB_ID=11518305
155 17:43:22.738085 - LAVA_DISPATCHER_IP=192.168.201.1
156 17:43:22.738188 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 17:43:22.738258 skipped lava-vland-overlay
158 17:43:22.738333 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 17:43:22.738413 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 17:43:22.738480 skipped lava-multinode-overlay
161 17:43:22.738562 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 17:43:22.738647 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 17:43:22.738725 Loading test definitions
164 17:43:22.738817 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 17:43:22.738889 Using /lava-11518305 at stage 0
166 17:43:22.739179 uuid=11518305_1.5.2.3.1 testdef=None
167 17:43:22.739268 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 17:43:22.739353 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 17:43:22.739857 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 17:43:22.740088 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 17:43:22.740688 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 17:43:22.740918 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 17:43:22.741542 runner path: /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/0/tests/0_cros-ec test_uuid 11518305_1.5.2.3.1
176 17:43:22.741695 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 17:43:22.741903 Creating lava-test-runner.conf files
179 17:43:22.741968 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11518305/lava-overlay-alw8ra4g/lava-11518305/0 for stage 0
180 17:43:22.742055 - 0_cros-ec
181 17:43:22.742151 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 17:43:22.742236 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 17:43:22.748698 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 17:43:22.748803 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 17:43:22.748890 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 17:43:22.749048 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 17:43:22.749134 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 17:43:23.664787 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 17:43:23.665202 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 17:43:23.665315 extracting modules file /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11518305/extract-overlay-ramdisk-72fnr775/ramdisk
191 17:43:23.874913 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 17:43:23.875088 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 17:43:23.875188 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518305/compress-overlay-q0j1g1fj/overlay-1.5.2.4.tar.gz to ramdisk
194 17:43:23.875262 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518305/compress-overlay-q0j1g1fj/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11518305/extract-overlay-ramdisk-72fnr775/ramdisk
195 17:43:23.881577 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 17:43:23.881688 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 17:43:23.881780 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 17:43:23.881869 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 17:43:23.881946 Building ramdisk /var/lib/lava/dispatcher/tmp/11518305/extract-overlay-ramdisk-72fnr775/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11518305/extract-overlay-ramdisk-72fnr775/ramdisk
200 17:43:24.603057 >> 271013 blocks
201 17:43:29.262819 rename /var/lib/lava/dispatcher/tmp/11518305/extract-overlay-ramdisk-72fnr775/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/ramdisk/ramdisk.cpio.gz
202 17:43:29.263246 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 17:43:29.263373 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 17:43:29.263474 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 17:43:29.263582 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/kernel/Image'
206 17:43:41.216422 Returned 0 in 11 seconds
207 17:43:41.317302 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/kernel/image.itb
208 17:43:42.009326 output: FIT description: Kernel Image image with one or more FDT blobs
209 17:43:42.009676 output: Created: Wed Sep 13 18:43:41 2023
210 17:43:42.009754 output: Image 0 (kernel-1)
211 17:43:42.009821 output: Description:
212 17:43:42.009885 output: Created: Wed Sep 13 18:43:41 2023
213 17:43:42.009948 output: Type: Kernel Image
214 17:43:42.010009 output: Compression: lzma compressed
215 17:43:42.010068 output: Data Size: 11039249 Bytes = 10780.52 KiB = 10.53 MiB
216 17:43:42.010125 output: Architecture: AArch64
217 17:43:42.010182 output: OS: Linux
218 17:43:42.010236 output: Load Address: 0x00000000
219 17:43:42.010290 output: Entry Point: 0x00000000
220 17:43:42.010342 output: Hash algo: crc32
221 17:43:42.010394 output: Hash value: 2ab54ae9
222 17:43:42.010446 output: Image 1 (fdt-1)
223 17:43:42.010499 output: Description: mt8192-asurada-spherion-r0
224 17:43:42.010551 output: Created: Wed Sep 13 18:43:41 2023
225 17:43:42.010604 output: Type: Flat Device Tree
226 17:43:42.010656 output: Compression: uncompressed
227 17:43:42.010709 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 17:43:42.010762 output: Architecture: AArch64
229 17:43:42.010814 output: Hash algo: crc32
230 17:43:42.010865 output: Hash value: cc4352de
231 17:43:42.010918 output: Image 2 (ramdisk-1)
232 17:43:42.010969 output: Description: unavailable
233 17:43:42.011021 output: Created: Wed Sep 13 18:43:41 2023
234 17:43:42.011074 output: Type: RAMDisk Image
235 17:43:42.011126 output: Compression: Unknown Compression
236 17:43:42.011178 output: Data Size: 47526898 Bytes = 46412.99 KiB = 45.33 MiB
237 17:43:42.011230 output: Architecture: AArch64
238 17:43:42.011282 output: OS: Linux
239 17:43:42.011334 output: Load Address: unavailable
240 17:43:42.011386 output: Entry Point: unavailable
241 17:43:42.011437 output: Hash algo: crc32
242 17:43:42.011488 output: Hash value: c5173f12
243 17:43:42.011540 output: Default Configuration: 'conf-1'
244 17:43:42.011592 output: Configuration 0 (conf-1)
245 17:43:42.011644 output: Description: mt8192-asurada-spherion-r0
246 17:43:42.011695 output: Kernel: kernel-1
247 17:43:42.011747 output: Init Ramdisk: ramdisk-1
248 17:43:42.011799 output: FDT: fdt-1
249 17:43:42.011851 output: Loadables: kernel-1
250 17:43:42.011902 output:
251 17:43:42.012090 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 17:43:42.012187 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 17:43:42.012287 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 17:43:42.012387 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 17:43:42.012466 No LXC device requested
256 17:43:42.012543 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 17:43:42.012629 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 17:43:42.012705 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 17:43:42.012775 Checking files for TFTP limit of 4294967296 bytes.
260 17:43:42.013260 end: 1 tftp-deploy (duration 00:00:20) [common]
261 17:43:42.013363 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 17:43:42.013452 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 17:43:42.013569 substitutions:
264 17:43:42.013635 - {DTB}: 11518305/tftp-deploy-_ikyzgwh/dtb/mt8192-asurada-spherion-r0.dtb
265 17:43:42.013701 - {INITRD}: 11518305/tftp-deploy-_ikyzgwh/ramdisk/ramdisk.cpio.gz
266 17:43:42.013760 - {KERNEL}: 11518305/tftp-deploy-_ikyzgwh/kernel/Image
267 17:43:42.013818 - {LAVA_MAC}: None
268 17:43:42.013875 - {PRESEED_CONFIG}: None
269 17:43:42.013930 - {PRESEED_LOCAL}: None
270 17:43:42.013984 - {RAMDISK}: 11518305/tftp-deploy-_ikyzgwh/ramdisk/ramdisk.cpio.gz
271 17:43:42.014038 - {ROOT_PART}: None
272 17:43:42.014091 - {ROOT}: None
273 17:43:42.014145 - {SERVER_IP}: 192.168.201.1
274 17:43:42.014199 - {TEE}: None
275 17:43:42.014252 Parsed boot commands:
276 17:43:42.014305 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 17:43:42.014472 Parsed boot commands: tftpboot 192.168.201.1 11518305/tftp-deploy-_ikyzgwh/kernel/image.itb 11518305/tftp-deploy-_ikyzgwh/kernel/cmdline
278 17:43:42.014560 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 17:43:42.014645 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 17:43:42.014736 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 17:43:42.014825 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 17:43:42.014895 Not connected, no need to disconnect.
283 17:43:42.014968 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 17:43:42.015046 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 17:43:42.015112 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 17:43:42.018472 Setting prompt string to ['lava-test: # ']
287 17:43:42.018785 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 17:43:42.018887 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 17:43:42.019002 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 17:43:42.019095 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 17:43:42.019322 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 17:43:47.176382 >> Command sent successfully.
293 17:43:47.186644 Returned 0 in 5 seconds
294 17:43:47.287807 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 17:43:47.289559 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 17:43:47.290338 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 17:43:47.291031 Setting prompt string to 'Starting depthcharge on Spherion...'
299 17:43:47.291634 Changing prompt to 'Starting depthcharge on Spherion...'
300 17:43:47.292221 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 17:43:47.292769 [Enter `^Ec?' for help]
302 17:43:47.452389
303 17:43:47.452686
304 17:43:47.452870 F0: 102B 0000
305 17:43:47.453061
306 17:43:47.453250 F3: 1001 0000 [0200]
307 17:43:47.453417
308 17:43:47.455972 F3: 1001 0000
309 17:43:47.456158
310 17:43:47.456304 F7: 102D 0000
311 17:43:47.456439
312 17:43:47.456586 F1: 0000 0000
313 17:43:47.456715
314 17:43:47.459988 V0: 0000 0000 [0001]
315 17:43:47.460162
316 17:43:47.460286 00: 0007 8000
317 17:43:47.460474
318 17:43:47.463807 01: 0000 0000
319 17:43:47.463964
320 17:43:47.464126 BP: 0C00 0209 [0000]
321 17:43:47.464338
322 17:43:47.464455 G0: 1182 0000
323 17:43:47.464552
324 17:43:47.467269 EC: 0000 0021 [4000]
325 17:43:47.467402
326 17:43:47.467508 S7: 0000 0000 [0000]
327 17:43:47.470790
328 17:43:47.470906 CC: 0000 0000 [0001]
329 17:43:47.470999
330 17:43:47.473931 T0: 0000 0040 [010F]
331 17:43:47.474052
332 17:43:47.474154 Jump to BL
333 17:43:47.474241
334 17:43:47.498829
335 17:43:47.498955
336 17:43:47.499022
337 17:43:47.506267 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 17:43:47.509904 ARM64: Exception handlers installed.
339 17:43:47.513212 ARM64: Testing exception
340 17:43:47.516867 ARM64: Done test exception
341 17:43:47.523987 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 17:43:47.531689 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 17:43:47.538557 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 17:43:47.549658 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 17:43:47.556178 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 17:43:47.566308 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 17:43:47.577130 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 17:43:47.583453 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 17:43:47.601609 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 17:43:47.604577 WDT: Last reset was cold boot
351 17:43:47.607854 SPI1(PAD0) initialized at 2873684 Hz
352 17:43:47.611263 SPI5(PAD0) initialized at 992727 Hz
353 17:43:47.614508 VBOOT: Loading verstage.
354 17:43:47.621350 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 17:43:47.624668 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 17:43:47.628082 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 17:43:47.631297 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 17:43:47.638996 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 17:43:47.645599 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 17:43:47.656336 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 17:43:47.656437
362 17:43:47.656506
363 17:43:47.666679 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 17:43:47.669737 ARM64: Exception handlers installed.
365 17:43:47.673181 ARM64: Testing exception
366 17:43:47.673266 ARM64: Done test exception
367 17:43:47.679709 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 17:43:47.683244 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 17:43:47.697240 Probing TPM: . done!
370 17:43:47.697330 TPM ready after 0 ms
371 17:43:47.704253 Connected to device vid:did:rid of 1ae0:0028:00
372 17:43:47.711391 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 17:43:47.715135 Initialized TPM device CR50 revision 0
374 17:43:47.780496 tlcl_send_startup: Startup return code is 0
375 17:43:47.780667 TPM: setup succeeded
376 17:43:47.791835 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 17:43:47.800737 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 17:43:47.810616 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 17:43:47.819975 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 17:43:47.823204 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 17:43:47.831840 in-header: 03 07 00 00 08 00 00 00
382 17:43:47.835639 in-data: aa e4 47 04 13 02 00 00
383 17:43:47.839009 Chrome EC: UHEPI supported
384 17:43:47.846653 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 17:43:47.850158 in-header: 03 ad 00 00 08 00 00 00
386 17:43:47.854014 in-data: 00 20 20 08 00 00 00 00
387 17:43:47.854100 Phase 1
388 17:43:47.858089 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 17:43:47.865229 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 17:43:47.869400 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 17:43:47.873053 Recovery requested (1009000e)
392 17:43:47.881084 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 17:43:47.886889 tlcl_extend: response is 0
394 17:43:47.896011 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 17:43:47.901914 tlcl_extend: response is 0
396 17:43:47.909109 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 17:43:47.928904 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 17:43:47.936387 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 17:43:47.936527
400 17:43:47.936596
401 17:43:47.946003 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 17:43:47.949554 ARM64: Exception handlers installed.
403 17:43:47.949642 ARM64: Testing exception
404 17:43:47.952837 ARM64: Done test exception
405 17:43:47.974665 pmic_efuse_setting: Set efuses in 11 msecs
406 17:43:47.977856 pmwrap_interface_init: Select PMIF_VLD_RDY
407 17:43:47.984516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 17:43:47.988094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 17:43:47.991767 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 17:43:47.998236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 17:43:48.002172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 17:43:48.009407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 17:43:48.012867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 17:43:48.016359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 17:43:48.020110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 17:43:48.027743 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 17:43:48.031676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 17:43:48.035188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 17:43:48.041468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 17:43:48.044951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 17:43:48.051513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 17:43:48.058375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 17:43:48.062180 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 17:43:48.069457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 17:43:48.073413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 17:43:48.080062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 17:43:48.087971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 17:43:48.090889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 17:43:48.097568 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 17:43:48.101053 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 17:43:48.107898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 17:43:48.114269 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 17:43:48.118144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 17:43:48.124655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 17:43:48.127736 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 17:43:48.131384 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 17:43:48.137654 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 17:43:48.144468 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 17:43:48.147886 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 17:43:48.154654 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 17:43:48.157987 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 17:43:48.164619 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 17:43:48.168095 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 17:43:48.175024 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 17:43:48.177878 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 17:43:48.181387 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 17:43:48.184920 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 17:43:48.191517 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 17:43:48.194628 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 17:43:48.198312 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 17:43:48.205182 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 17:43:48.208906 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 17:43:48.212046 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 17:43:48.215495 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 17:43:48.222204 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 17:43:48.225497 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 17:43:48.228858 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 17:43:48.235289 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 17:43:48.245633 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 17:43:48.248660 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 17:43:48.258944 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 17:43:48.265569 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 17:43:48.272094 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 17:43:48.275310 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 17:43:48.278734 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 17:43:48.286962 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2b
467 17:43:48.293254 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 17:43:48.296851 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 17:43:48.300056 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 17:43:48.311463 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 17:43:48.321246 [RTC]rtc_get_frequency_meter,154: input=23, output=955
472 17:43:48.330252 [RTC]rtc_get_frequency_meter,154: input=19, output=863
473 17:43:48.339648 [RTC]rtc_get_frequency_meter,154: input=17, output=816
474 17:43:48.349474 [RTC]rtc_get_frequency_meter,154: input=16, output=792
475 17:43:48.353032 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 17:43:48.359184 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 17:43:48.362736 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 17:43:48.365776 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 17:43:48.369204 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 17:43:48.372842 ADC[4]: Raw value=902507 ID=7
481 17:43:48.375922 ADC[3]: Raw value=213179 ID=1
482 17:43:48.379186 RAM Code: 0x71
483 17:43:48.382753 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 17:43:48.386402 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 17:43:48.395899 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 17:43:48.402619 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 17:43:48.406227 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 17:43:48.409349 in-header: 03 07 00 00 08 00 00 00
489 17:43:48.412723 in-data: aa e4 47 04 13 02 00 00
490 17:43:48.416405 Chrome EC: UHEPI supported
491 17:43:48.422649 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 17:43:48.426364 in-header: 03 ed 00 00 08 00 00 00
493 17:43:48.429550 in-data: 80 20 60 08 00 00 00 00
494 17:43:48.432917 MRC: failed to locate region type 0.
495 17:43:48.439306 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 17:43:48.439390 DRAM-K: Running full calibration
497 17:43:48.446220 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 17:43:48.449451 header.status = 0x0
499 17:43:48.452804 header.version = 0x6 (expected: 0x6)
500 17:43:48.456385 header.size = 0xd00 (expected: 0xd00)
501 17:43:48.456469 header.flags = 0x0
502 17:43:48.462913 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 17:43:48.481179 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
504 17:43:48.488017 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 17:43:48.491130 dram_init: ddr_geometry: 2
506 17:43:48.491215 [EMI] MDL number = 2
507 17:43:48.494734 [EMI] Get MDL freq = 0
508 17:43:48.498020 dram_init: ddr_type: 0
509 17:43:48.498104 is_discrete_lpddr4: 1
510 17:43:48.501291 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 17:43:48.501376
512 17:43:48.501443
513 17:43:48.504651 [Bian_co] ETT version 0.0.0.1
514 17:43:48.511332 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 17:43:48.511417
516 17:43:48.514428 dramc_set_vcore_voltage set vcore to 650000
517 17:43:48.514512 Read voltage for 800, 4
518 17:43:48.518047 Vio18 = 0
519 17:43:48.518132 Vcore = 650000
520 17:43:48.518199 Vdram = 0
521 17:43:48.521183 Vddq = 0
522 17:43:48.521267 Vmddr = 0
523 17:43:48.524431 dram_init: config_dvfs: 1
524 17:43:48.528390 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 17:43:48.535355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 17:43:48.539052 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
527 17:43:48.542204 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
528 17:43:48.546170 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 17:43:48.549721 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 17:43:48.553656 MEM_TYPE=3, freq_sel=18
531 17:43:48.553742 sv_algorithm_assistance_LP4_1600
532 17:43:48.560690 ============ PULL DRAM RESETB DOWN ============
533 17:43:48.564506 ========== PULL DRAM RESETB DOWN end =========
534 17:43:48.568321 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 17:43:48.571506 ===================================
536 17:43:48.571592 LPDDR4 DRAM CONFIGURATION
537 17:43:48.575410 ===================================
538 17:43:48.579629 EX_ROW_EN[0] = 0x0
539 17:43:48.579713 EX_ROW_EN[1] = 0x0
540 17:43:48.582782 LP4Y_EN = 0x0
541 17:43:48.582867 WORK_FSP = 0x0
542 17:43:48.586745 WL = 0x2
543 17:43:48.586829 RL = 0x2
544 17:43:48.590775 BL = 0x2
545 17:43:48.590859 RPST = 0x0
546 17:43:48.593789 RD_PRE = 0x0
547 17:43:48.593873 WR_PRE = 0x1
548 17:43:48.596897 WR_PST = 0x0
549 17:43:48.597018 DBI_WR = 0x0
550 17:43:48.600369 DBI_RD = 0x0
551 17:43:48.600453 OTF = 0x1
552 17:43:48.603397 ===================================
553 17:43:48.606829 ===================================
554 17:43:48.610236 ANA top config
555 17:43:48.613644 ===================================
556 17:43:48.613728 DLL_ASYNC_EN = 0
557 17:43:48.616665 ALL_SLAVE_EN = 1
558 17:43:48.620420 NEW_RANK_MODE = 1
559 17:43:48.623555 DLL_IDLE_MODE = 1
560 17:43:48.627157 LP45_APHY_COMB_EN = 1
561 17:43:48.627241 TX_ODT_DIS = 1
562 17:43:48.629998 NEW_8X_MODE = 1
563 17:43:48.633425 ===================================
564 17:43:48.636635 ===================================
565 17:43:48.639975 data_rate = 1600
566 17:43:48.643648 CKR = 1
567 17:43:48.646907 DQ_P2S_RATIO = 8
568 17:43:48.650753 ===================================
569 17:43:48.650837 CA_P2S_RATIO = 8
570 17:43:48.654531 DQ_CA_OPEN = 0
571 17:43:48.658114 DQ_SEMI_OPEN = 0
572 17:43:48.661989 CA_SEMI_OPEN = 0
573 17:43:48.662073 CA_FULL_RATE = 0
574 17:43:48.665509 DQ_CKDIV4_EN = 1
575 17:43:48.669258 CA_CKDIV4_EN = 1
576 17:43:48.669342 CA_PREDIV_EN = 0
577 17:43:48.672468 PH8_DLY = 0
578 17:43:48.676082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 17:43:48.679474 DQ_AAMCK_DIV = 4
580 17:43:48.682534 CA_AAMCK_DIV = 4
581 17:43:48.685864 CA_ADMCK_DIV = 4
582 17:43:48.685949 DQ_TRACK_CA_EN = 0
583 17:43:48.689529 CA_PICK = 800
584 17:43:48.692808 CA_MCKIO = 800
585 17:43:48.696353 MCKIO_SEMI = 0
586 17:43:48.699581 PLL_FREQ = 3068
587 17:43:48.702816 DQ_UI_PI_RATIO = 32
588 17:43:48.702901 CA_UI_PI_RATIO = 0
589 17:43:48.706230 ===================================
590 17:43:48.709526 ===================================
591 17:43:48.713105 memory_type:LPDDR4
592 17:43:48.716523 GP_NUM : 10
593 17:43:48.716608 SRAM_EN : 1
594 17:43:48.719575 MD32_EN : 0
595 17:43:48.723303 ===================================
596 17:43:48.726930 [ANA_INIT] >>>>>>>>>>>>>>
597 17:43:48.727015 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 17:43:48.730622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 17:43:48.734254 ===================================
600 17:43:48.738131 data_rate = 1600,PCW = 0X7600
601 17:43:48.741909 ===================================
602 17:43:48.745456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 17:43:48.749306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 17:43:48.756907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 17:43:48.760470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 17:43:48.763639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 17:43:48.767147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 17:43:48.770605 [ANA_INIT] flow start
609 17:43:48.770709 [ANA_INIT] PLL >>>>>>>>
610 17:43:48.773533 [ANA_INIT] PLL <<<<<<<<
611 17:43:48.777536 [ANA_INIT] MIDPI >>>>>>>>
612 17:43:48.777621 [ANA_INIT] MIDPI <<<<<<<<
613 17:43:48.780534 [ANA_INIT] DLL >>>>>>>>
614 17:43:48.783668 [ANA_INIT] flow end
615 17:43:48.787027 ============ LP4 DIFF to SE enter ============
616 17:43:48.790601 ============ LP4 DIFF to SE exit ============
617 17:43:48.793709 [ANA_INIT] <<<<<<<<<<<<<
618 17:43:48.797175 [Flow] Enable top DCM control >>>>>
619 17:43:48.800288 [Flow] Enable top DCM control <<<<<
620 17:43:48.803559 Enable DLL master slave shuffle
621 17:43:48.807242 ==============================================================
622 17:43:48.810609 Gating Mode config
623 17:43:48.813976 ==============================================================
624 17:43:48.817141 Config description:
625 17:43:48.826952 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 17:43:48.833921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 17:43:48.837277 SELPH_MODE 0: By rank 1: By Phase
628 17:43:48.843952 ==============================================================
629 17:43:48.847208 GAT_TRACK_EN = 1
630 17:43:48.850605 RX_GATING_MODE = 2
631 17:43:48.853919 RX_GATING_TRACK_MODE = 2
632 17:43:48.857495 SELPH_MODE = 1
633 17:43:48.860501 PICG_EARLY_EN = 1
634 17:43:48.860585 VALID_LAT_VALUE = 1
635 17:43:48.867022 ==============================================================
636 17:43:48.870535 Enter into Gating configuration >>>>
637 17:43:48.873805 Exit from Gating configuration <<<<
638 17:43:48.877339 Enter into DVFS_PRE_config >>>>>
639 17:43:48.887477 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 17:43:48.890531 Exit from DVFS_PRE_config <<<<<
641 17:43:48.893934 Enter into PICG configuration >>>>
642 17:43:48.897203 Exit from PICG configuration <<<<
643 17:43:48.900478 [RX_INPUT] configuration >>>>>
644 17:43:48.903714 [RX_INPUT] configuration <<<<<
645 17:43:48.907093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 17:43:48.913716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 17:43:48.920391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 17:43:48.927168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 17:43:48.933977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 17:43:48.937092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 17:43:48.943773 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 17:43:48.947260 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 17:43:48.950705 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 17:43:48.954682 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 17:43:48.957865 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 17:43:48.964448 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 17:43:48.967748 ===================================
658 17:43:48.967829 LPDDR4 DRAM CONFIGURATION
659 17:43:48.971192 ===================================
660 17:43:48.974659 EX_ROW_EN[0] = 0x0
661 17:43:48.977798 EX_ROW_EN[1] = 0x0
662 17:43:48.977874 LP4Y_EN = 0x0
663 17:43:48.981269 WORK_FSP = 0x0
664 17:43:48.981356 WL = 0x2
665 17:43:48.984413 RL = 0x2
666 17:43:48.984487 BL = 0x2
667 17:43:48.987873 RPST = 0x0
668 17:43:48.987950 RD_PRE = 0x0
669 17:43:48.991035 WR_PRE = 0x1
670 17:43:48.991123 WR_PST = 0x0
671 17:43:48.994477 DBI_WR = 0x0
672 17:43:48.994597 DBI_RD = 0x0
673 17:43:48.998005 OTF = 0x1
674 17:43:49.000917 ===================================
675 17:43:49.004580 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 17:43:49.007848 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 17:43:49.011557 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 17:43:49.015324 ===================================
679 17:43:49.019212 LPDDR4 DRAM CONFIGURATION
680 17:43:49.023335 ===================================
681 17:43:49.023422 EX_ROW_EN[0] = 0x10
682 17:43:49.026777 EX_ROW_EN[1] = 0x0
683 17:43:49.026898 LP4Y_EN = 0x0
684 17:43:49.030541 WORK_FSP = 0x0
685 17:43:49.030632 WL = 0x2
686 17:43:49.034089 RL = 0x2
687 17:43:49.034187 BL = 0x2
688 17:43:49.037669 RPST = 0x0
689 17:43:49.037774 RD_PRE = 0x0
690 17:43:49.041494 WR_PRE = 0x1
691 17:43:49.041599 WR_PST = 0x0
692 17:43:49.045068 DBI_WR = 0x0
693 17:43:49.045184 DBI_RD = 0x0
694 17:43:49.045274 OTF = 0x1
695 17:43:49.048761 ===================================
696 17:43:49.055469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 17:43:49.059933 nWR fixed to 40
698 17:43:49.063577 [ModeRegInit_LP4] CH0 RK0
699 17:43:49.063756 [ModeRegInit_LP4] CH0 RK1
700 17:43:49.067462 [ModeRegInit_LP4] CH1 RK0
701 17:43:49.071167 [ModeRegInit_LP4] CH1 RK1
702 17:43:49.071374 match AC timing 13
703 17:43:49.074957 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 17:43:49.079011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 17:43:49.086505 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 17:43:49.090184 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 17:43:49.093592 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 17:43:49.094024 [EMI DOE] emi_dcm 0
709 17:43:49.100628 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 17:43:49.101195 ==
711 17:43:49.105039 Dram Type= 6, Freq= 0, CH_0, rank 0
712 17:43:49.108307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 17:43:49.108746 ==
714 17:43:49.112026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 17:43:49.119462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 17:43:49.128457 [CA 0] Center 38 (7~69) winsize 63
717 17:43:49.131857 [CA 1] Center 38 (7~69) winsize 63
718 17:43:49.135426 [CA 2] Center 35 (5~66) winsize 62
719 17:43:49.139283 [CA 3] Center 35 (5~66) winsize 62
720 17:43:49.142875 [CA 4] Center 34 (4~65) winsize 62
721 17:43:49.146642 [CA 5] Center 33 (3~64) winsize 62
722 17:43:49.147076
723 17:43:49.150092 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 17:43:49.150529
725 17:43:49.154083 [CATrainingPosCal] consider 1 rank data
726 17:43:49.154621 u2DelayCellTimex100 = 270/100 ps
727 17:43:49.158040 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
728 17:43:49.161616 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 17:43:49.165505 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 17:43:49.169095 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 17:43:49.173023 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 17:43:49.176807 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 17:43:49.177397
734 17:43:49.180391 CA PerBit enable=1, Macro0, CA PI delay=33
735 17:43:49.180829
736 17:43:49.184459 [CBTSetCACLKResult] CA Dly = 33
737 17:43:49.187739 CS Dly: 5 (0~36)
738 17:43:49.188178 ==
739 17:43:49.188526 Dram Type= 6, Freq= 0, CH_0, rank 1
740 17:43:49.195574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 17:43:49.196016 ==
742 17:43:49.199524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 17:43:49.206321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 17:43:49.214480 [CA 0] Center 38 (7~69) winsize 63
745 17:43:49.218120 [CA 1] Center 38 (8~69) winsize 62
746 17:43:49.221992 [CA 2] Center 36 (6~67) winsize 62
747 17:43:49.225715 [CA 3] Center 36 (5~67) winsize 63
748 17:43:49.229426 [CA 4] Center 35 (4~66) winsize 63
749 17:43:49.233006 [CA 5] Center 34 (4~65) winsize 62
750 17:43:49.233540
751 17:43:49.236885 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 17:43:49.237521
753 17:43:49.240002 [CATrainingPosCal] consider 2 rank data
754 17:43:49.240435 u2DelayCellTimex100 = 270/100 ps
755 17:43:49.244236 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 17:43:49.248011 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 17:43:49.251133 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 17:43:49.255423 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 17:43:49.258747 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 17:43:49.262872 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 17:43:49.263435
762 17:43:49.266205 CA PerBit enable=1, Macro0, CA PI delay=34
763 17:43:49.266728
764 17:43:49.269639 [CBTSetCACLKResult] CA Dly = 34
765 17:43:49.273425 CS Dly: 6 (0~38)
766 17:43:49.273875
767 17:43:49.277434 ----->DramcWriteLeveling(PI) begin...
768 17:43:49.277878 ==
769 17:43:49.281330 Dram Type= 6, Freq= 0, CH_0, rank 0
770 17:43:49.284807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 17:43:49.285281 ==
772 17:43:49.288635 Write leveling (Byte 0): 33 => 33
773 17:43:49.289118 Write leveling (Byte 1): 29 => 29
774 17:43:49.292495 DramcWriteLeveling(PI) end<-----
775 17:43:49.292962
776 17:43:49.293333 ==
777 17:43:49.296372 Dram Type= 6, Freq= 0, CH_0, rank 0
778 17:43:49.299681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 17:43:49.300121 ==
780 17:43:49.303626 [Gating] SW mode calibration
781 17:43:49.311316 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 17:43:49.314821 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 17:43:49.322106 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 17:43:49.326079 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 17:43:49.329463 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 17:43:49.333197 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 17:43:49.336985 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 17:43:49.343855 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 17:43:49.347004 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 17:43:49.350363 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 17:43:49.356721 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 17:43:49.360459 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 17:43:49.363839 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 17:43:49.367075 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 17:43:49.373977 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 17:43:49.377361 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 17:43:49.380609 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 17:43:49.387210 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 17:43:49.390464 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 17:43:49.394042 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
801 17:43:49.400334 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
802 17:43:49.404264 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 17:43:49.407587 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 17:43:49.413885 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 17:43:49.417474 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 17:43:49.420650 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 17:43:49.427269 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 17:43:49.430420 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 17:43:49.434066 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 17:43:49.437504 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
811 17:43:49.443700 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 17:43:49.447158 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 17:43:49.450699 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 17:43:49.457306 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 17:43:49.460298 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 17:43:49.463820 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 1)
817 17:43:49.470902 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
818 17:43:49.473609 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 17:43:49.477476 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 17:43:49.484372 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 17:43:49.487224 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 17:43:49.490828 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 17:43:49.497065 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 17:43:49.500709 0 11 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
825 17:43:49.503988 0 11 8 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
826 17:43:49.511025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 17:43:49.513707 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 17:43:49.517511 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 17:43:49.524430 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 17:43:49.527627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 17:43:49.530950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 17:43:49.534465 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 17:43:49.540888 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 17:43:49.544060 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 17:43:49.547651 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 17:43:49.554351 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 17:43:49.557397 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 17:43:49.561021 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 17:43:49.567601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 17:43:49.570651 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 17:43:49.573914 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 17:43:49.580564 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 17:43:49.584086 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 17:43:49.587502 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 17:43:49.594279 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 17:43:49.597002 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 17:43:49.600764 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 17:43:49.607304 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 17:43:49.610727 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 17:43:49.613740 Total UI for P1: 0, mck2ui 16
851 17:43:49.616859 best dqsien dly found for B0: ( 0, 14, 4)
852 17:43:49.620440 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 17:43:49.623914 Total UI for P1: 0, mck2ui 16
854 17:43:49.627384 best dqsien dly found for B1: ( 0, 14, 6)
855 17:43:49.630517 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 17:43:49.633811 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
857 17:43:49.634371
858 17:43:49.637517 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 17:43:49.643635 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
860 17:43:49.644086 [Gating] SW calibration Done
861 17:43:49.644535 ==
862 17:43:49.647692 Dram Type= 6, Freq= 0, CH_0, rank 0
863 17:43:49.654018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 17:43:49.654569 ==
865 17:43:49.655026 RX Vref Scan: 0
866 17:43:49.655452
867 17:43:49.657504 RX Vref 0 -> 0, step: 1
868 17:43:49.658041
869 17:43:49.660679 RX Delay -130 -> 252, step: 16
870 17:43:49.663824 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 17:43:49.667444 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 17:43:49.670949 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 17:43:49.673965 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 17:43:49.680659 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 17:43:49.684315 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
876 17:43:49.687638 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 17:43:49.690618 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 17:43:49.697262 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 17:43:49.700277 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 17:43:49.704211 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 17:43:49.707494 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 17:43:49.710266 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 17:43:49.717452 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 17:43:49.720921 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 17:43:49.724144 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 17:43:49.724696 ==
887 17:43:49.727123 Dram Type= 6, Freq= 0, CH_0, rank 0
888 17:43:49.730610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 17:43:49.731162 ==
890 17:43:49.733783 DQS Delay:
891 17:43:49.734287 DQS0 = 0, DQS1 = 0
892 17:43:49.737053 DQM Delay:
893 17:43:49.737489 DQM0 = 91, DQM1 = 80
894 17:43:49.737836 DQ Delay:
895 17:43:49.740456 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 17:43:49.744330 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =101
897 17:43:49.747214 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 17:43:49.750249 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
899 17:43:49.750786
900 17:43:49.751179
901 17:43:49.753725 ==
902 17:43:49.754162 Dram Type= 6, Freq= 0, CH_0, rank 0
903 17:43:49.760898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 17:43:49.761467 ==
905 17:43:49.761812
906 17:43:49.762132
907 17:43:49.764215 TX Vref Scan disable
908 17:43:49.764753 == TX Byte 0 ==
909 17:43:49.767202 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
910 17:43:49.773873 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
911 17:43:49.774404 == TX Byte 1 ==
912 17:43:49.777451 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
913 17:43:49.783991 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
914 17:43:49.784537 ==
915 17:43:49.787307 Dram Type= 6, Freq= 0, CH_0, rank 0
916 17:43:49.790638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 17:43:49.791188 ==
918 17:43:49.804037 TX Vref=22, minBit 11, minWin=26, winSum=439
919 17:43:49.807100 TX Vref=24, minBit 11, minWin=27, winSum=446
920 17:43:49.810283 TX Vref=26, minBit 8, minWin=27, winSum=447
921 17:43:49.813870 TX Vref=28, minBit 9, minWin=27, winSum=451
922 17:43:49.817299 TX Vref=30, minBit 8, minWin=27, winSum=455
923 17:43:49.823900 TX Vref=32, minBit 13, minWin=27, winSum=455
924 17:43:49.827271 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 30
925 17:43:49.827807
926 17:43:49.830945 Final TX Range 1 Vref 30
927 17:43:49.831484
928 17:43:49.831829 ==
929 17:43:49.834218 Dram Type= 6, Freq= 0, CH_0, rank 0
930 17:43:49.837290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 17:43:49.837828 ==
932 17:43:49.840479
933 17:43:49.840965
934 17:43:49.841330 TX Vref Scan disable
935 17:43:49.844039 == TX Byte 0 ==
936 17:43:49.847841 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
937 17:43:49.854015 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
938 17:43:49.854555 == TX Byte 1 ==
939 17:43:49.857536 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
940 17:43:49.864040 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
941 17:43:49.864577
942 17:43:49.864923 [DATLAT]
943 17:43:49.865305 Freq=800, CH0 RK0
944 17:43:49.865618
945 17:43:49.867407 DATLAT Default: 0xa
946 17:43:49.867936 0, 0xFFFF, sum = 0
947 17:43:49.871131 1, 0xFFFF, sum = 0
948 17:43:49.871702 2, 0xFFFF, sum = 0
949 17:43:49.873775 3, 0xFFFF, sum = 0
950 17:43:49.874227 4, 0xFFFF, sum = 0
951 17:43:49.877155 5, 0xFFFF, sum = 0
952 17:43:49.880658 6, 0xFFFF, sum = 0
953 17:43:49.881120 7, 0xFFFF, sum = 0
954 17:43:49.883951 8, 0xFFFF, sum = 0
955 17:43:49.884490 9, 0x0, sum = 1
956 17:43:49.884854 10, 0x0, sum = 2
957 17:43:49.887571 11, 0x0, sum = 3
958 17:43:49.888110 12, 0x0, sum = 4
959 17:43:49.891076 best_step = 10
960 17:43:49.891620
961 17:43:49.891966 ==
962 17:43:49.894234 Dram Type= 6, Freq= 0, CH_0, rank 0
963 17:43:49.897886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 17:43:49.898447 ==
965 17:43:49.900866 RX Vref Scan: 1
966 17:43:49.901575
967 17:43:49.901968 Set Vref Range= 32 -> 127
968 17:43:49.902293
969 17:43:49.904220 RX Vref 32 -> 127, step: 1
970 17:43:49.904646
971 17:43:49.907382 RX Delay -95 -> 252, step: 8
972 17:43:49.907810
973 17:43:49.910903 Set Vref, RX VrefLevel [Byte0]: 32
974 17:43:49.914199 [Byte1]: 32
975 17:43:49.914667
976 17:43:49.917539 Set Vref, RX VrefLevel [Byte0]: 33
977 17:43:49.920465 [Byte1]: 33
978 17:43:49.924706
979 17:43:49.925275 Set Vref, RX VrefLevel [Byte0]: 34
980 17:43:49.927441 [Byte1]: 34
981 17:43:49.932293
982 17:43:49.932862 Set Vref, RX VrefLevel [Byte0]: 35
983 17:43:49.935363 [Byte1]: 35
984 17:43:49.939733
985 17:43:49.940286 Set Vref, RX VrefLevel [Byte0]: 36
986 17:43:49.942729 [Byte1]: 36
987 17:43:49.947323
988 17:43:49.947909 Set Vref, RX VrefLevel [Byte0]: 37
989 17:43:49.950340 [Byte1]: 37
990 17:43:49.955052
991 17:43:49.955595 Set Vref, RX VrefLevel [Byte0]: 38
992 17:43:49.958523 [Byte1]: 38
993 17:43:49.962581
994 17:43:49.963127 Set Vref, RX VrefLevel [Byte0]: 39
995 17:43:49.965836 [Byte1]: 39
996 17:43:49.970084
997 17:43:49.970627 Set Vref, RX VrefLevel [Byte0]: 40
998 17:43:49.973456 [Byte1]: 40
999 17:43:49.977833
1000 17:43:49.978382 Set Vref, RX VrefLevel [Byte0]: 41
1001 17:43:49.981496 [Byte1]: 41
1002 17:43:49.985374
1003 17:43:49.985810 Set Vref, RX VrefLevel [Byte0]: 42
1004 17:43:49.988847 [Byte1]: 42
1005 17:43:49.993040
1006 17:43:49.993561 Set Vref, RX VrefLevel [Byte0]: 43
1007 17:43:49.995984 [Byte1]: 43
1008 17:43:50.000281
1009 17:43:50.000904 Set Vref, RX VrefLevel [Byte0]: 44
1010 17:43:50.003510 [Byte1]: 44
1011 17:43:50.008288
1012 17:43:50.008756 Set Vref, RX VrefLevel [Byte0]: 45
1013 17:43:50.011529 [Byte1]: 45
1014 17:43:50.015445
1015 17:43:50.015978 Set Vref, RX VrefLevel [Byte0]: 46
1016 17:43:50.018638 [Byte1]: 46
1017 17:43:50.023266
1018 17:43:50.023932 Set Vref, RX VrefLevel [Byte0]: 47
1019 17:43:50.026362 [Byte1]: 47
1020 17:43:50.030981
1021 17:43:50.031508 Set Vref, RX VrefLevel [Byte0]: 48
1022 17:43:50.034188 [Byte1]: 48
1023 17:43:50.038091
1024 17:43:50.038526 Set Vref, RX VrefLevel [Byte0]: 49
1025 17:43:50.041558 [Byte1]: 49
1026 17:43:50.045689
1027 17:43:50.046115 Set Vref, RX VrefLevel [Byte0]: 50
1028 17:43:50.049001 [Byte1]: 50
1029 17:43:50.053599
1030 17:43:50.054125 Set Vref, RX VrefLevel [Byte0]: 51
1031 17:43:50.056802 [Byte1]: 51
1032 17:43:50.061319
1033 17:43:50.061847 Set Vref, RX VrefLevel [Byte0]: 52
1034 17:43:50.064381 [Byte1]: 52
1035 17:43:50.068907
1036 17:43:50.069466 Set Vref, RX VrefLevel [Byte0]: 53
1037 17:43:50.072062 [Byte1]: 53
1038 17:43:50.076331
1039 17:43:50.076859 Set Vref, RX VrefLevel [Byte0]: 54
1040 17:43:50.079244 [Byte1]: 54
1041 17:43:50.084206
1042 17:43:50.084732 Set Vref, RX VrefLevel [Byte0]: 55
1043 17:43:50.087124 [Byte1]: 55
1044 17:43:50.091486
1045 17:43:50.091982 Set Vref, RX VrefLevel [Byte0]: 56
1046 17:43:50.095036 [Byte1]: 56
1047 17:43:50.099173
1048 17:43:50.099623 Set Vref, RX VrefLevel [Byte0]: 57
1049 17:43:50.102179 [Byte1]: 57
1050 17:43:50.106653
1051 17:43:50.107177 Set Vref, RX VrefLevel [Byte0]: 58
1052 17:43:50.110205 [Byte1]: 58
1053 17:43:50.114620
1054 17:43:50.115154 Set Vref, RX VrefLevel [Byte0]: 59
1055 17:43:50.117660 [Byte1]: 59
1056 17:43:50.121806
1057 17:43:50.122230 Set Vref, RX VrefLevel [Byte0]: 60
1058 17:43:50.125145 [Byte1]: 60
1059 17:43:50.129661
1060 17:43:50.130208 Set Vref, RX VrefLevel [Byte0]: 61
1061 17:43:50.132848 [Byte1]: 61
1062 17:43:50.137471
1063 17:43:50.137995 Set Vref, RX VrefLevel [Byte0]: 62
1064 17:43:50.140253 [Byte1]: 62
1065 17:43:50.144707
1066 17:43:50.145400 Set Vref, RX VrefLevel [Byte0]: 63
1067 17:43:50.148325 [Byte1]: 63
1068 17:43:50.152469
1069 17:43:50.153036 Set Vref, RX VrefLevel [Byte0]: 64
1070 17:43:50.155738 [Byte1]: 64
1071 17:43:50.160077
1072 17:43:50.160610 Set Vref, RX VrefLevel [Byte0]: 65
1073 17:43:50.163335 [Byte1]: 65
1074 17:43:50.167962
1075 17:43:50.168486 Set Vref, RX VrefLevel [Byte0]: 66
1076 17:43:50.171128 [Byte1]: 66
1077 17:43:50.175382
1078 17:43:50.175908 Set Vref, RX VrefLevel [Byte0]: 67
1079 17:43:50.178796 [Byte1]: 67
1080 17:43:50.182632
1081 17:43:50.183160 Set Vref, RX VrefLevel [Byte0]: 68
1082 17:43:50.186367 [Byte1]: 68
1083 17:43:50.190118
1084 17:43:50.190667 Set Vref, RX VrefLevel [Byte0]: 69
1085 17:43:50.193352 [Byte1]: 69
1086 17:43:50.197900
1087 17:43:50.198323 Set Vref, RX VrefLevel [Byte0]: 70
1088 17:43:50.201190 [Byte1]: 70
1089 17:43:50.205235
1090 17:43:50.205655 Set Vref, RX VrefLevel [Byte0]: 71
1091 17:43:50.208956 [Byte1]: 71
1092 17:43:50.213081
1093 17:43:50.213603 Set Vref, RX VrefLevel [Byte0]: 72
1094 17:43:50.216597 [Byte1]: 72
1095 17:43:50.220912
1096 17:43:50.221488 Set Vref, RX VrefLevel [Byte0]: 73
1097 17:43:50.224421 [Byte1]: 73
1098 17:43:50.228688
1099 17:43:50.229292 Set Vref, RX VrefLevel [Byte0]: 74
1100 17:43:50.231471 [Byte1]: 74
1101 17:43:50.235825
1102 17:43:50.236372 Set Vref, RX VrefLevel [Byte0]: 75
1103 17:43:50.239350 [Byte1]: 75
1104 17:43:50.243185
1105 17:43:50.243608 Set Vref, RX VrefLevel [Byte0]: 76
1106 17:43:50.247203 [Byte1]: 76
1107 17:43:50.251223
1108 17:43:50.251759 Final RX Vref Byte 0 = 62 to rank0
1109 17:43:50.254573 Final RX Vref Byte 1 = 58 to rank0
1110 17:43:50.258172 Final RX Vref Byte 0 = 62 to rank1
1111 17:43:50.261542 Final RX Vref Byte 1 = 58 to rank1==
1112 17:43:50.264856 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 17:43:50.268076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 17:43:50.271715 ==
1115 17:43:50.272241 DQS Delay:
1116 17:43:50.272585 DQS0 = 0, DQS1 = 0
1117 17:43:50.274848 DQM Delay:
1118 17:43:50.275293 DQM0 = 93, DQM1 = 81
1119 17:43:50.277683 DQ Delay:
1120 17:43:50.278109 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1121 17:43:50.281605 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1122 17:43:50.284894 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1123 17:43:50.288296 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1124 17:43:50.288722
1125 17:43:50.291537
1126 17:43:50.298033 [DQSOSCAuto] RK0, (LSB)MR18= 0x3833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1127 17:43:50.301508 CH0 RK0: MR19=606, MR18=3833
1128 17:43:50.307880 CH0_RK0: MR19=0x606, MR18=0x3833, DQSOSC=395, MR23=63, INC=94, DEC=63
1129 17:43:50.308308
1130 17:43:50.311720 ----->DramcWriteLeveling(PI) begin...
1131 17:43:50.312262 ==
1132 17:43:50.315023 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 17:43:50.317992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 17:43:50.318425 ==
1135 17:43:50.321305 Write leveling (Byte 0): 32 => 32
1136 17:43:50.324801 Write leveling (Byte 1): 29 => 29
1137 17:43:50.328474 DramcWriteLeveling(PI) end<-----
1138 17:43:50.329047
1139 17:43:50.329391 ==
1140 17:43:50.331800 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 17:43:50.335143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 17:43:50.335572 ==
1143 17:43:50.338038 [Gating] SW mode calibration
1144 17:43:50.345004 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 17:43:50.351678 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 17:43:50.354949 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1147 17:43:50.358400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1148 17:43:50.365301 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1149 17:43:50.368492 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 17:43:50.371741 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 17:43:50.375169 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 17:43:50.419072 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 17:43:50.419704 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 17:43:50.420404 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 17:43:50.420806 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 17:43:50.421193 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 17:43:50.421504 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 17:43:50.421803 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 17:43:50.422094 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 17:43:50.422381 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 17:43:50.422665 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 17:43:50.426814 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 17:43:50.430612 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1164 17:43:50.433628 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1165 17:43:50.437324 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 17:43:50.444140 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 17:43:50.447239 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 17:43:50.450175 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 17:43:50.456590 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 17:43:50.460486 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 17:43:50.464196 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1172 17:43:50.470399 0 9 8 | B1->B0 | 2b2b 3332 | 1 1 | (1 1) (0 0)
1173 17:43:50.473891 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 17:43:50.477285 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 17:43:50.480536 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 17:43:50.487274 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 17:43:50.490461 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 17:43:50.493623 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 17:43:50.500495 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
1180 17:43:50.503650 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1181 17:43:50.507178 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 17:43:50.513628 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 17:43:50.517072 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 17:43:50.520463 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 17:43:50.527006 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 17:43:50.530490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 17:43:50.533846 0 11 4 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
1188 17:43:50.540344 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1189 17:43:50.543546 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 17:43:50.547291 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 17:43:50.553943 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 17:43:50.557925 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 17:43:50.561714 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 17:43:50.565191 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 17:43:50.569158 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1196 17:43:50.575853 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1197 17:43:50.579308 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 17:43:50.583264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 17:43:50.586349 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 17:43:50.593146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 17:43:50.596424 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 17:43:50.599720 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 17:43:50.606367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 17:43:50.609802 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 17:43:50.612925 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 17:43:50.619989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 17:43:50.623142 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 17:43:50.626746 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 17:43:50.632858 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 17:43:50.636324 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 17:43:50.639995 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1212 17:43:50.642906 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1213 17:43:50.646388 Total UI for P1: 0, mck2ui 16
1214 17:43:50.649551 best dqsien dly found for B1: ( 0, 14, 6)
1215 17:43:50.656558 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 17:43:50.660036 Total UI for P1: 0, mck2ui 16
1217 17:43:50.663062 best dqsien dly found for B0: ( 0, 14, 6)
1218 17:43:50.666232 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1219 17:43:50.670178 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1220 17:43:50.670830
1221 17:43:50.672907 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1222 17:43:50.676796 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1223 17:43:50.679898 [Gating] SW calibration Done
1224 17:43:50.680440 ==
1225 17:43:50.683481 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 17:43:50.686588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 17:43:50.687158 ==
1228 17:43:50.689815 RX Vref Scan: 0
1229 17:43:50.690402
1230 17:43:50.690747 RX Vref 0 -> 0, step: 1
1231 17:43:50.691068
1232 17:43:50.693636 RX Delay -130 -> 252, step: 16
1233 17:43:50.696723 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1234 17:43:50.703259 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1235 17:43:50.706174 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1236 17:43:50.709658 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1237 17:43:50.713380 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1238 17:43:50.716544 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1239 17:43:50.723075 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1240 17:43:50.726545 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1241 17:43:50.730058 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1242 17:43:50.733075 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1243 17:43:50.736719 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1244 17:43:50.743204 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1245 17:43:50.746413 iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208
1246 17:43:50.749972 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1247 17:43:50.753115 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1248 17:43:50.756701 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1249 17:43:50.759416 ==
1250 17:43:50.762995 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 17:43:50.766261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 17:43:50.766700 ==
1253 17:43:50.767042 DQS Delay:
1254 17:43:50.769668 DQS0 = 0, DQS1 = 0
1255 17:43:50.770383 DQM Delay:
1256 17:43:50.772836 DQM0 = 90, DQM1 = 81
1257 17:43:50.773282 DQ Delay:
1258 17:43:50.776461 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1259 17:43:50.779944 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1260 17:43:50.782872 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1261 17:43:50.786855 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1262 17:43:50.787404
1263 17:43:50.787754
1264 17:43:50.788075 ==
1265 17:43:50.790011 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 17:43:50.793337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 17:43:50.793772 ==
1268 17:43:50.794113
1269 17:43:50.794426
1270 17:43:50.796381 TX Vref Scan disable
1271 17:43:50.799707 == TX Byte 0 ==
1272 17:43:50.803680 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1273 17:43:50.806449 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1274 17:43:50.806887 == TX Byte 1 ==
1275 17:43:50.812996 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1276 17:43:50.816386 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1277 17:43:50.816815 ==
1278 17:43:50.820030 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 17:43:50.822694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 17:43:50.825964 ==
1281 17:43:50.837792 TX Vref=22, minBit 8, minWin=26, winSum=447
1282 17:43:50.841557 TX Vref=24, minBit 8, minWin=27, winSum=450
1283 17:43:50.844562 TX Vref=26, minBit 8, minWin=27, winSum=455
1284 17:43:50.847778 TX Vref=28, minBit 8, minWin=27, winSum=454
1285 17:43:50.851653 TX Vref=30, minBit 4, minWin=28, winSum=456
1286 17:43:50.854860 TX Vref=32, minBit 4, minWin=28, winSum=459
1287 17:43:50.861497 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 32
1288 17:43:50.862034
1289 17:43:50.865061 Final TX Range 1 Vref 32
1290 17:43:50.865592
1291 17:43:50.865935 ==
1292 17:43:50.868011 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 17:43:50.871569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 17:43:50.871993 ==
1295 17:43:50.872321
1296 17:43:50.872629
1297 17:43:50.874609 TX Vref Scan disable
1298 17:43:50.877783 == TX Byte 0 ==
1299 17:43:50.881517 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1300 17:43:50.884498 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1301 17:43:50.887813 == TX Byte 1 ==
1302 17:43:50.891288 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1303 17:43:50.895051 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1304 17:43:50.895579
1305 17:43:50.898510 [DATLAT]
1306 17:43:50.899043 Freq=800, CH0 RK1
1307 17:43:50.899378
1308 17:43:50.901455 DATLAT Default: 0xa
1309 17:43:50.901979 0, 0xFFFF, sum = 0
1310 17:43:50.905211 1, 0xFFFF, sum = 0
1311 17:43:50.905746 2, 0xFFFF, sum = 0
1312 17:43:50.908166 3, 0xFFFF, sum = 0
1313 17:43:50.908612 4, 0xFFFF, sum = 0
1314 17:43:50.911624 5, 0xFFFF, sum = 0
1315 17:43:50.912187 6, 0xFFFF, sum = 0
1316 17:43:50.915279 7, 0xFFFF, sum = 0
1317 17:43:50.915821 8, 0xFFFF, sum = 0
1318 17:43:50.918191 9, 0x0, sum = 1
1319 17:43:50.918621 10, 0x0, sum = 2
1320 17:43:50.921619 11, 0x0, sum = 3
1321 17:43:50.922048 12, 0x0, sum = 4
1322 17:43:50.925088 best_step = 10
1323 17:43:50.925596
1324 17:43:50.925937 ==
1325 17:43:50.928611 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 17:43:50.932012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 17:43:50.932533 ==
1328 17:43:50.932867 RX Vref Scan: 0
1329 17:43:50.933204
1330 17:43:50.934968 RX Vref 0 -> 0, step: 1
1331 17:43:50.935382
1332 17:43:50.938390 RX Delay -95 -> 252, step: 8
1333 17:43:50.941754 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1334 17:43:50.948634 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1335 17:43:50.952032 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1336 17:43:50.955555 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1337 17:43:50.958384 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1338 17:43:50.961971 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1339 17:43:50.968604 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1340 17:43:50.971852 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1341 17:43:50.975311 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1342 17:43:50.978524 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1343 17:43:50.981885 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1344 17:43:50.988271 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1345 17:43:50.991869 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1346 17:43:50.995295 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1347 17:43:50.998450 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1348 17:43:51.001925 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1349 17:43:51.005262 ==
1350 17:43:51.005674 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 17:43:51.011843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 17:43:51.012286 ==
1353 17:43:51.012618 DQS Delay:
1354 17:43:51.015057 DQS0 = 0, DQS1 = 0
1355 17:43:51.015469 DQM Delay:
1356 17:43:51.018405 DQM0 = 91, DQM1 = 81
1357 17:43:51.018933 DQ Delay:
1358 17:43:51.021679 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1359 17:43:51.025243 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1360 17:43:51.028539 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1361 17:43:51.031596 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1362 17:43:51.032135
1363 17:43:51.032641
1364 17:43:51.038878 [DQSOSCAuto] RK1, (LSB)MR18= 0x3914, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 395 ps
1365 17:43:51.041655 CH0 RK1: MR19=606, MR18=3914
1366 17:43:51.048201 CH0_RK1: MR19=0x606, MR18=0x3914, DQSOSC=395, MR23=63, INC=94, DEC=63
1367 17:43:51.051518 [RxdqsGatingPostProcess] freq 800
1368 17:43:51.055025 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 17:43:51.058558 Pre-setting of DQS Precalculation
1370 17:43:51.064904 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1371 17:43:51.065152 ==
1372 17:43:51.068411 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 17:43:51.071801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 17:43:51.072036 ==
1375 17:43:51.078276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 17:43:51.084882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 17:43:51.092602 [CA 0] Center 36 (6~67) winsize 62
1378 17:43:51.096264 [CA 1] Center 36 (6~67) winsize 62
1379 17:43:51.099485 [CA 2] Center 34 (4~65) winsize 62
1380 17:43:51.102799 [CA 3] Center 34 (4~65) winsize 62
1381 17:43:51.105939 [CA 4] Center 34 (4~65) winsize 62
1382 17:43:51.109330 [CA 5] Center 33 (3~64) winsize 62
1383 17:43:51.109712
1384 17:43:51.113016 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1385 17:43:51.113423
1386 17:43:51.116321 [CATrainingPosCal] consider 1 rank data
1387 17:43:51.119697 u2DelayCellTimex100 = 270/100 ps
1388 17:43:51.122982 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 17:43:51.126439 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1390 17:43:51.133286 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 17:43:51.136320 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 17:43:51.139712 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 17:43:51.143002 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 17:43:51.143419
1395 17:43:51.146076 CA PerBit enable=1, Macro0, CA PI delay=33
1396 17:43:51.146575
1397 17:43:51.149776 [CBTSetCACLKResult] CA Dly = 33
1398 17:43:51.150293 CS Dly: 5 (0~36)
1399 17:43:51.150621 ==
1400 17:43:51.153469 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 17:43:51.159675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 17:43:51.160229 ==
1403 17:43:51.163325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 17:43:51.169873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 17:43:51.179215 [CA 0] Center 37 (6~68) winsize 63
1406 17:43:51.182527 [CA 1] Center 37 (6~68) winsize 63
1407 17:43:51.185831 [CA 2] Center 35 (5~66) winsize 62
1408 17:43:51.189435 [CA 3] Center 34 (4~65) winsize 62
1409 17:43:51.192406 [CA 4] Center 34 (4~65) winsize 62
1410 17:43:51.195675 [CA 5] Center 34 (4~64) winsize 61
1411 17:43:51.196089
1412 17:43:51.199073 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1413 17:43:51.199595
1414 17:43:51.202355 [CATrainingPosCal] consider 2 rank data
1415 17:43:51.206042 u2DelayCellTimex100 = 270/100 ps
1416 17:43:51.208831 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 17:43:51.212196 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 17:43:51.219451 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1419 17:43:51.223278 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 17:43:51.226432 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 17:43:51.230537 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1422 17:43:51.231062
1423 17:43:51.234005 CA PerBit enable=1, Macro0, CA PI delay=34
1424 17:43:51.234432
1425 17:43:51.234760 [CBTSetCACLKResult] CA Dly = 34
1426 17:43:51.237888 CS Dly: 6 (0~38)
1427 17:43:51.238476
1428 17:43:51.241331 ----->DramcWriteLeveling(PI) begin...
1429 17:43:51.241787 ==
1430 17:43:51.244986 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 17:43:51.248590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 17:43:51.249038 ==
1433 17:43:51.252796 Write leveling (Byte 0): 26 => 26
1434 17:43:51.256327 Write leveling (Byte 1): 31 => 31
1435 17:43:51.256849 DramcWriteLeveling(PI) end<-----
1436 17:43:51.257238
1437 17:43:51.257543 ==
1438 17:43:51.259621 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 17:43:51.266566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 17:43:51.267084 ==
1441 17:43:51.269823 [Gating] SW mode calibration
1442 17:43:51.276507 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 17:43:51.279523 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 17:43:51.286813 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1445 17:43:51.289811 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1446 17:43:51.293349 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 17:43:51.296462 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 17:43:51.302886 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 17:43:51.306598 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 17:43:51.309685 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 17:43:51.316851 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 17:43:51.319612 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 17:43:51.323056 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 17:43:51.329625 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 17:43:51.333141 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 17:43:51.336695 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 17:43:51.342842 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 17:43:51.346679 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 17:43:51.349512 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 17:43:51.356427 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 17:43:51.359704 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 17:43:51.363039 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 17:43:51.369702 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 17:43:51.373400 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 17:43:51.376578 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 17:43:51.383151 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 17:43:51.386463 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 17:43:51.389700 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 17:43:51.393273 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1470 17:43:51.400378 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1471 17:43:51.403467 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 17:43:51.406172 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 17:43:51.413195 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 17:43:51.416556 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 17:43:51.420252 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 17:43:51.426304 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 17:43:51.429715 0 10 4 | B1->B0 | 2e2e 2b2b | 1 1 | (1 0) (1 0)
1478 17:43:51.433209 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 17:43:51.440181 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 17:43:51.443063 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 17:43:51.446859 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 17:43:51.453524 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 17:43:51.457159 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 17:43:51.460069 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1485 17:43:51.467227 0 11 4 | B1->B0 | 2c2c 3737 | 0 0 | (0 0) (1 1)
1486 17:43:51.470124 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1487 17:43:51.473586 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 17:43:51.477081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 17:43:51.483454 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 17:43:51.486637 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 17:43:51.490081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 17:43:51.496545 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1493 17:43:51.500157 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1494 17:43:51.503591 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 17:43:51.510013 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 17:43:51.513113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 17:43:51.516562 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 17:43:51.523500 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 17:43:51.526375 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 17:43:51.530028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 17:43:51.536699 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 17:43:51.540252 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 17:43:51.543372 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 17:43:51.550501 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 17:43:51.553525 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 17:43:51.557001 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 17:43:51.560539 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 17:43:51.566644 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1509 17:43:51.570191 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1510 17:43:51.573398 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 17:43:51.577144 Total UI for P1: 0, mck2ui 16
1512 17:43:51.580228 best dqsien dly found for B0: ( 0, 14, 2)
1513 17:43:51.583105 Total UI for P1: 0, mck2ui 16
1514 17:43:51.586898 best dqsien dly found for B1: ( 0, 14, 4)
1515 17:43:51.589793 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1516 17:43:51.593317 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1517 17:43:51.596705
1518 17:43:51.600087 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1519 17:43:51.603383 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1520 17:43:51.606613 [Gating] SW calibration Done
1521 17:43:51.607191 ==
1522 17:43:51.609872 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 17:43:51.613172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 17:43:51.613763 ==
1525 17:43:51.614142 RX Vref Scan: 0
1526 17:43:51.614489
1527 17:43:51.616481 RX Vref 0 -> 0, step: 1
1528 17:43:51.616972
1529 17:43:51.620290 RX Delay -130 -> 252, step: 16
1530 17:43:51.623447 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1531 17:43:51.626913 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1532 17:43:51.633196 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1533 17:43:51.636659 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1534 17:43:51.640047 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1535 17:43:51.643480 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1536 17:43:51.646999 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1537 17:43:51.650116 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1538 17:43:51.656703 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1539 17:43:51.660112 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1540 17:43:51.663604 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1541 17:43:51.666764 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1542 17:43:51.670210 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1543 17:43:51.676454 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1544 17:43:51.680188 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1545 17:43:51.683547 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1546 17:43:51.684121 ==
1547 17:43:51.686556 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 17:43:51.690246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 17:43:51.693273 ==
1550 17:43:51.693839 DQS Delay:
1551 17:43:51.694215 DQS0 = 0, DQS1 = 0
1552 17:43:51.696745 DQM Delay:
1553 17:43:51.697322 DQM0 = 90, DQM1 = 80
1554 17:43:51.700174 DQ Delay:
1555 17:43:51.700718 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1556 17:43:51.703347 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1557 17:43:51.706972 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1558 17:43:51.710110 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1559 17:43:51.710719
1560 17:43:51.713315
1561 17:43:51.713787 ==
1562 17:43:51.716760 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 17:43:51.720126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 17:43:51.720701 ==
1565 17:43:51.721120
1566 17:43:51.721477
1567 17:43:51.723748 TX Vref Scan disable
1568 17:43:51.724304 == TX Byte 0 ==
1569 17:43:51.730169 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1570 17:43:51.733244 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1571 17:43:51.733758 == TX Byte 1 ==
1572 17:43:51.739775 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1573 17:43:51.743455 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1574 17:43:51.743974 ==
1575 17:43:51.746530 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 17:43:51.750488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 17:43:51.751011 ==
1578 17:43:51.764018 TX Vref=22, minBit 8, minWin=27, winSum=448
1579 17:43:51.767043 TX Vref=24, minBit 8, minWin=27, winSum=452
1580 17:43:51.770960 TX Vref=26, minBit 8, minWin=27, winSum=456
1581 17:43:51.774274 TX Vref=28, minBit 15, minWin=27, winSum=457
1582 17:43:51.776890 TX Vref=30, minBit 15, minWin=27, winSum=459
1583 17:43:51.783777 TX Vref=32, minBit 15, minWin=27, winSum=458
1584 17:43:51.786951 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1585 17:43:51.787430
1586 17:43:51.790868 Final TX Range 1 Vref 30
1587 17:43:51.791427
1588 17:43:51.791804 ==
1589 17:43:51.793749 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 17:43:51.797123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 17:43:51.800799 ==
1592 17:43:51.801398
1593 17:43:51.801774
1594 17:43:51.802126 TX Vref Scan disable
1595 17:43:51.804718 == TX Byte 0 ==
1596 17:43:51.808153 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1597 17:43:51.811268 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1598 17:43:51.815106 == TX Byte 1 ==
1599 17:43:51.818542 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1600 17:43:51.821576 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1601 17:43:51.822007
1602 17:43:51.824891 [DATLAT]
1603 17:43:51.825447 Freq=800, CH1 RK0
1604 17:43:51.825794
1605 17:43:51.828088 DATLAT Default: 0xa
1606 17:43:51.828611 0, 0xFFFF, sum = 0
1607 17:43:51.831654 1, 0xFFFF, sum = 0
1608 17:43:51.832188 2, 0xFFFF, sum = 0
1609 17:43:51.834962 3, 0xFFFF, sum = 0
1610 17:43:51.835499 4, 0xFFFF, sum = 0
1611 17:43:51.838138 5, 0xFFFF, sum = 0
1612 17:43:51.838662 6, 0xFFFF, sum = 0
1613 17:43:51.841821 7, 0xFFFF, sum = 0
1614 17:43:51.842350 8, 0xFFFF, sum = 0
1615 17:43:51.845063 9, 0x0, sum = 1
1616 17:43:51.845598 10, 0x0, sum = 2
1617 17:43:51.847830 11, 0x0, sum = 3
1618 17:43:51.848268 12, 0x0, sum = 4
1619 17:43:51.851539 best_step = 10
1620 17:43:51.852075
1621 17:43:51.852421 ==
1622 17:43:51.854544 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 17:43:51.858448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 17:43:51.858979 ==
1625 17:43:51.859324 RX Vref Scan: 1
1626 17:43:51.861325
1627 17:43:51.861754 Set Vref Range= 32 -> 127
1628 17:43:51.862094
1629 17:43:51.865007 RX Vref 32 -> 127, step: 1
1630 17:43:51.865526
1631 17:43:51.868304 RX Delay -95 -> 252, step: 8
1632 17:43:51.868840
1633 17:43:51.871274 Set Vref, RX VrefLevel [Byte0]: 32
1634 17:43:51.874920 [Byte1]: 32
1635 17:43:51.875358
1636 17:43:51.878081 Set Vref, RX VrefLevel [Byte0]: 33
1637 17:43:51.881196 [Byte1]: 33
1638 17:43:51.881625
1639 17:43:51.885044 Set Vref, RX VrefLevel [Byte0]: 34
1640 17:43:51.888045 [Byte1]: 34
1641 17:43:51.892122
1642 17:43:51.892644 Set Vref, RX VrefLevel [Byte0]: 35
1643 17:43:51.895356 [Byte1]: 35
1644 17:43:51.899734
1645 17:43:51.900255 Set Vref, RX VrefLevel [Byte0]: 36
1646 17:43:51.903063 [Byte1]: 36
1647 17:43:51.907341
1648 17:43:51.907868 Set Vref, RX VrefLevel [Byte0]: 37
1649 17:43:51.910285 [Byte1]: 37
1650 17:43:51.914903
1651 17:43:51.915430 Set Vref, RX VrefLevel [Byte0]: 38
1652 17:43:51.918341 [Byte1]: 38
1653 17:43:51.922402
1654 17:43:51.922853 Set Vref, RX VrefLevel [Byte0]: 39
1655 17:43:51.925860 [Byte1]: 39
1656 17:43:51.929869
1657 17:43:51.930393 Set Vref, RX VrefLevel [Byte0]: 40
1658 17:43:51.933362 [Byte1]: 40
1659 17:43:51.937697
1660 17:43:51.938217 Set Vref, RX VrefLevel [Byte0]: 41
1661 17:43:51.941164 [Byte1]: 41
1662 17:43:51.945463
1663 17:43:51.945892 Set Vref, RX VrefLevel [Byte0]: 42
1664 17:43:51.948783 [Byte1]: 42
1665 17:43:51.952785
1666 17:43:51.953353 Set Vref, RX VrefLevel [Byte0]: 43
1667 17:43:51.956023 [Byte1]: 43
1668 17:43:51.960533
1669 17:43:51.961095 Set Vref, RX VrefLevel [Byte0]: 44
1670 17:43:51.963891 [Byte1]: 44
1671 17:43:51.968028
1672 17:43:51.968551 Set Vref, RX VrefLevel [Byte0]: 45
1673 17:43:51.971613 [Byte1]: 45
1674 17:43:51.975837
1675 17:43:51.976355 Set Vref, RX VrefLevel [Byte0]: 46
1676 17:43:51.978886 [Byte1]: 46
1677 17:43:51.983785
1678 17:43:51.984314 Set Vref, RX VrefLevel [Byte0]: 47
1679 17:43:51.986971 [Byte1]: 47
1680 17:43:51.991252
1681 17:43:51.991774 Set Vref, RX VrefLevel [Byte0]: 48
1682 17:43:51.994022 [Byte1]: 48
1683 17:43:51.998177
1684 17:43:51.998604 Set Vref, RX VrefLevel [Byte0]: 49
1685 17:43:52.002075 [Byte1]: 49
1686 17:43:52.006623
1687 17:43:52.007188 Set Vref, RX VrefLevel [Byte0]: 50
1688 17:43:52.009380 [Byte1]: 50
1689 17:43:52.013747
1690 17:43:52.014306 Set Vref, RX VrefLevel [Byte0]: 51
1691 17:43:52.016811 [Byte1]: 51
1692 17:43:52.021444
1693 17:43:52.021968 Set Vref, RX VrefLevel [Byte0]: 52
1694 17:43:52.024500 [Byte1]: 52
1695 17:43:52.028958
1696 17:43:52.029486 Set Vref, RX VrefLevel [Byte0]: 53
1697 17:43:52.031986 [Byte1]: 53
1698 17:43:52.036869
1699 17:43:52.037435 Set Vref, RX VrefLevel [Byte0]: 54
1700 17:43:52.039882 [Byte1]: 54
1701 17:43:52.043992
1702 17:43:52.044422 Set Vref, RX VrefLevel [Byte0]: 55
1703 17:43:52.047120 [Byte1]: 55
1704 17:43:52.051606
1705 17:43:52.052216 Set Vref, RX VrefLevel [Byte0]: 56
1706 17:43:52.054684 [Byte1]: 56
1707 17:43:52.059015
1708 17:43:52.059525 Set Vref, RX VrefLevel [Byte0]: 57
1709 17:43:52.062642 [Byte1]: 57
1710 17:43:52.066808
1711 17:43:52.067245 Set Vref, RX VrefLevel [Byte0]: 58
1712 17:43:52.069963 [Byte1]: 58
1713 17:43:52.074271
1714 17:43:52.074788 Set Vref, RX VrefLevel [Byte0]: 59
1715 17:43:52.077381 [Byte1]: 59
1716 17:43:52.081968
1717 17:43:52.082480 Set Vref, RX VrefLevel [Byte0]: 60
1718 17:43:52.085135 [Byte1]: 60
1719 17:43:52.089831
1720 17:43:52.090375 Set Vref, RX VrefLevel [Byte0]: 61
1721 17:43:52.092815 [Byte1]: 61
1722 17:43:52.097139
1723 17:43:52.097657 Set Vref, RX VrefLevel [Byte0]: 62
1724 17:43:52.100609 [Byte1]: 62
1725 17:43:52.104688
1726 17:43:52.105153 Set Vref, RX VrefLevel [Byte0]: 63
1727 17:43:52.108268 [Byte1]: 63
1728 17:43:52.112449
1729 17:43:52.112878 Set Vref, RX VrefLevel [Byte0]: 64
1730 17:43:52.115988 [Byte1]: 64
1731 17:43:52.120303
1732 17:43:52.120889 Set Vref, RX VrefLevel [Byte0]: 65
1733 17:43:52.123202 [Byte1]: 65
1734 17:43:52.127689
1735 17:43:52.128112 Set Vref, RX VrefLevel [Byte0]: 66
1736 17:43:52.131230 [Byte1]: 66
1737 17:43:52.135390
1738 17:43:52.135912 Set Vref, RX VrefLevel [Byte0]: 67
1739 17:43:52.138125 [Byte1]: 67
1740 17:43:52.142810
1741 17:43:52.143331 Set Vref, RX VrefLevel [Byte0]: 68
1742 17:43:52.146305 [Byte1]: 68
1743 17:43:52.150578
1744 17:43:52.151099 Set Vref, RX VrefLevel [Byte0]: 69
1745 17:43:52.153492 [Byte1]: 69
1746 17:43:52.157814
1747 17:43:52.158342 Set Vref, RX VrefLevel [Byte0]: 70
1748 17:43:52.160984 [Byte1]: 70
1749 17:43:52.165778
1750 17:43:52.166306 Set Vref, RX VrefLevel [Byte0]: 71
1751 17:43:52.168981 [Byte1]: 71
1752 17:43:52.173177
1753 17:43:52.173747 Set Vref, RX VrefLevel [Byte0]: 72
1754 17:43:52.176436 [Byte1]: 72
1755 17:43:52.180659
1756 17:43:52.181267 Set Vref, RX VrefLevel [Byte0]: 73
1757 17:43:52.184278 [Byte1]: 73
1758 17:43:52.188631
1759 17:43:52.189379 Set Vref, RX VrefLevel [Byte0]: 74
1760 17:43:52.191715 [Byte1]: 74
1761 17:43:52.195646
1762 17:43:52.196063 Set Vref, RX VrefLevel [Byte0]: 75
1763 17:43:52.199132 [Byte1]: 75
1764 17:43:52.203547
1765 17:43:52.204077 Set Vref, RX VrefLevel [Byte0]: 76
1766 17:43:52.207215 [Byte1]: 76
1767 17:43:52.211151
1768 17:43:52.211722 Set Vref, RX VrefLevel [Byte0]: 77
1769 17:43:52.214258 [Byte1]: 77
1770 17:43:52.218580
1771 17:43:52.219022 Set Vref, RX VrefLevel [Byte0]: 78
1772 17:43:52.222235 [Byte1]: 78
1773 17:43:52.226072
1774 17:43:52.226498 Final RX Vref Byte 0 = 51 to rank0
1775 17:43:52.229403 Final RX Vref Byte 1 = 61 to rank0
1776 17:43:52.233140 Final RX Vref Byte 0 = 51 to rank1
1777 17:43:52.236369 Final RX Vref Byte 1 = 61 to rank1==
1778 17:43:52.239781 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 17:43:52.246142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 17:43:52.246668 ==
1781 17:43:52.247012 DQS Delay:
1782 17:43:52.249214 DQS0 = 0, DQS1 = 0
1783 17:43:52.249677 DQM Delay:
1784 17:43:52.250013 DQM0 = 91, DQM1 = 81
1785 17:43:52.252700 DQ Delay:
1786 17:43:52.256278 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1787 17:43:52.259585 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1788 17:43:52.262800 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1789 17:43:52.266575 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1790 17:43:52.267104
1791 17:43:52.267477
1792 17:43:52.273211 [DQSOSCAuto] RK0, (LSB)MR18= 0x2744, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 400 ps
1793 17:43:52.276037 CH1 RK0: MR19=606, MR18=2744
1794 17:43:52.282609 CH1_RK0: MR19=0x606, MR18=0x2744, DQSOSC=392, MR23=63, INC=96, DEC=64
1795 17:43:52.283030
1796 17:43:52.286461 ----->DramcWriteLeveling(PI) begin...
1797 17:43:52.286991 ==
1798 17:43:52.289693 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 17:43:52.292587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 17:43:52.293035 ==
1801 17:43:52.296490 Write leveling (Byte 0): 30 => 30
1802 17:43:52.299816 Write leveling (Byte 1): 29 => 29
1803 17:43:52.303129 DramcWriteLeveling(PI) end<-----
1804 17:43:52.303661
1805 17:43:52.304013 ==
1806 17:43:52.306413 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 17:43:52.309364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 17:43:52.309797 ==
1809 17:43:52.312815 [Gating] SW mode calibration
1810 17:43:52.319494 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 17:43:52.326207 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 17:43:52.329601 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 17:43:52.332770 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1814 17:43:52.339204 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 17:43:52.342853 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 17:43:52.346382 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 17:43:52.352911 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 17:43:52.356114 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 17:43:52.359867 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 17:43:52.366313 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 17:43:52.369613 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 17:43:52.373140 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 17:43:52.379932 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 17:43:52.382816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 17:43:52.386425 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 17:43:52.393312 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 17:43:52.396864 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 17:43:52.399687 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 17:43:52.403373 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1830 17:43:52.409769 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 17:43:52.413095 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 17:43:52.416062 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 17:43:52.423066 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 17:43:52.426430 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 17:43:52.429411 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 17:43:52.436536 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 17:43:52.439827 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1838 17:43:52.443024 0 9 8 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
1839 17:43:52.449830 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 17:43:52.453096 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 17:43:52.456575 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 17:43:52.463187 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 17:43:52.466202 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 17:43:52.469776 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 17:43:52.476468 0 10 4 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
1846 17:43:52.479601 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1847 17:43:52.482763 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 17:43:52.489723 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 17:43:52.493093 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 17:43:52.496369 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 17:43:52.499682 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 17:43:52.506906 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 17:43:52.509676 0 11 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (0 0)
1854 17:43:52.512998 0 11 8 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1855 17:43:52.519635 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 17:43:52.523349 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 17:43:52.526466 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 17:43:52.533453 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 17:43:52.536442 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 17:43:52.539855 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 17:43:52.546328 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 17:43:52.549865 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 17:43:52.553412 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 17:43:52.559832 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 17:43:52.563213 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 17:43:52.566507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 17:43:52.573187 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 17:43:52.576778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 17:43:52.579924 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 17:43:52.582975 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 17:43:52.589783 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 17:43:52.593134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 17:43:52.596682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 17:43:52.603186 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 17:43:52.606715 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 17:43:52.610026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 17:43:52.616609 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 17:43:52.620016 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1879 17:43:52.623446 Total UI for P1: 0, mck2ui 16
1880 17:43:52.626300 best dqsien dly found for B1: ( 0, 14, 6)
1881 17:43:52.629672 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 17:43:52.633098 Total UI for P1: 0, mck2ui 16
1883 17:43:52.636652 best dqsien dly found for B0: ( 0, 14, 8)
1884 17:43:52.639640 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1885 17:43:52.643594 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1886 17:43:52.644160
1887 17:43:52.646323 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1888 17:43:52.653131 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 17:43:52.653711 [Gating] SW calibration Done
1890 17:43:52.654081 ==
1891 17:43:52.656393 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 17:43:52.662816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 17:43:52.663338 ==
1894 17:43:52.663678 RX Vref Scan: 0
1895 17:43:52.663994
1896 17:43:52.666523 RX Vref 0 -> 0, step: 1
1897 17:43:52.666950
1898 17:43:52.670022 RX Delay -130 -> 252, step: 16
1899 17:43:52.673375 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1900 17:43:52.676384 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1901 17:43:52.680134 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1902 17:43:52.686244 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1903 17:43:52.689881 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1904 17:43:52.693484 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1905 17:43:52.696484 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1906 17:43:52.700237 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1907 17:43:52.707150 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1908 17:43:52.710295 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1909 17:43:52.713259 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1910 17:43:52.716210 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1911 17:43:52.720158 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1912 17:43:52.726660 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1913 17:43:52.729730 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1914 17:43:52.733057 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1915 17:43:52.733526 ==
1916 17:43:52.736467 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 17:43:52.740056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 17:43:52.740805 ==
1919 17:43:52.743143 DQS Delay:
1920 17:43:52.743703 DQS0 = 0, DQS1 = 0
1921 17:43:52.744076 DQM Delay:
1922 17:43:52.746652 DQM0 = 88, DQM1 = 81
1923 17:43:52.747124 DQ Delay:
1924 17:43:52.750035 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1925 17:43:52.753268 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1926 17:43:52.756722 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1927 17:43:52.760433 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1928 17:43:52.761039
1929 17:43:52.761415
1930 17:43:52.761760 ==
1931 17:43:52.763597 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 17:43:52.769808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 17:43:52.770363 ==
1934 17:43:52.770732
1935 17:43:52.771074
1936 17:43:52.771403 TX Vref Scan disable
1937 17:43:52.773817 == TX Byte 0 ==
1938 17:43:52.776815 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1939 17:43:52.780704 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1940 17:43:52.783809 == TX Byte 1 ==
1941 17:43:52.787120 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1942 17:43:52.790078 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1943 17:43:52.793808 ==
1944 17:43:52.797085 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 17:43:52.800229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 17:43:52.800795 ==
1947 17:43:52.813297 TX Vref=22, minBit 13, minWin=27, winSum=451
1948 17:43:52.816069 TX Vref=24, minBit 3, minWin=27, winSum=453
1949 17:43:52.819428 TX Vref=26, minBit 0, minWin=28, winSum=458
1950 17:43:52.822335 TX Vref=28, minBit 8, minWin=28, winSum=461
1951 17:43:52.825873 TX Vref=30, minBit 8, minWin=28, winSum=460
1952 17:43:52.833098 TX Vref=32, minBit 8, minWin=28, winSum=458
1953 17:43:52.836366 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
1954 17:43:52.836837
1955 17:43:52.839463 Final TX Range 1 Vref 28
1956 17:43:52.840016
1957 17:43:52.840387 ==
1958 17:43:52.842654 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 17:43:52.845950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 17:43:52.846424 ==
1961 17:43:52.846790
1962 17:43:52.849643
1963 17:43:52.850211 TX Vref Scan disable
1964 17:43:52.852963 == TX Byte 0 ==
1965 17:43:52.856195 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1966 17:43:52.859350 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1967 17:43:52.862826 == TX Byte 1 ==
1968 17:43:52.866221 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 17:43:52.869618 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 17:43:52.870044
1971 17:43:52.872611 [DATLAT]
1972 17:43:52.873065 Freq=800, CH1 RK1
1973 17:43:52.873673
1974 17:43:52.876058 DATLAT Default: 0xa
1975 17:43:52.876487 0, 0xFFFF, sum = 0
1976 17:43:52.879464 1, 0xFFFF, sum = 0
1977 17:43:52.879992 2, 0xFFFF, sum = 0
1978 17:43:52.882723 3, 0xFFFF, sum = 0
1979 17:43:52.883155 4, 0xFFFF, sum = 0
1980 17:43:52.886009 5, 0xFFFF, sum = 0
1981 17:43:52.886620 6, 0xFFFF, sum = 0
1982 17:43:52.889694 7, 0xFFFF, sum = 0
1983 17:43:52.890124 8, 0xFFFF, sum = 0
1984 17:43:52.893030 9, 0x0, sum = 1
1985 17:43:52.893460 10, 0x0, sum = 2
1986 17:43:52.896411 11, 0x0, sum = 3
1987 17:43:52.896964 12, 0x0, sum = 4
1988 17:43:52.899653 best_step = 10
1989 17:43:52.900175
1990 17:43:52.900514 ==
1991 17:43:52.902803 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 17:43:52.906312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 17:43:52.906845 ==
1994 17:43:52.909479 RX Vref Scan: 0
1995 17:43:52.910001
1996 17:43:52.910336 RX Vref 0 -> 0, step: 1
1997 17:43:52.910658
1998 17:43:52.912950 RX Delay -95 -> 252, step: 8
1999 17:43:52.919697 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2000 17:43:52.922512 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2001 17:43:52.926296 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2002 17:43:52.929464 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2003 17:43:52.933075 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2004 17:43:52.936355 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2005 17:43:52.942734 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2006 17:43:52.945984 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2007 17:43:52.949546 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2008 17:43:52.952861 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2009 17:43:52.956292 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2010 17:43:52.962978 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2011 17:43:52.966107 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2012 17:43:52.969828 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2013 17:43:52.972748 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2014 17:43:52.979310 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2015 17:43:52.979865 ==
2016 17:43:52.983081 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 17:43:52.986118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 17:43:52.986692 ==
2019 17:43:52.987067 DQS Delay:
2020 17:43:52.989568 DQS0 = 0, DQS1 = 0
2021 17:43:52.990133 DQM Delay:
2022 17:43:52.992872 DQM0 = 91, DQM1 = 83
2023 17:43:52.993474 DQ Delay:
2024 17:43:52.996197 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2025 17:43:52.999526 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2026 17:43:53.002812 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2027 17:43:53.005788 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2028 17:43:53.006355
2029 17:43:53.006724
2030 17:43:53.012883 [DQSOSCAuto] RK1, (LSB)MR18= 0x340a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2031 17:43:53.015981 CH1 RK1: MR19=606, MR18=340A
2032 17:43:53.022828 CH1_RK1: MR19=0x606, MR18=0x340A, DQSOSC=396, MR23=63, INC=94, DEC=62
2033 17:43:53.026032 [RxdqsGatingPostProcess] freq 800
2034 17:43:53.032956 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 17:43:53.033646 Pre-setting of DQS Precalculation
2036 17:43:53.039558 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 17:43:53.045822 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 17:43:53.052786 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 17:43:53.053292
2040 17:43:53.053657
2041 17:43:53.056131 [Calibration Summary] 1600 Mbps
2042 17:43:53.059746 CH 0, Rank 0
2043 17:43:53.060305 SW Impedance : PASS
2044 17:43:53.062935 DUTY Scan : NO K
2045 17:43:53.065967 ZQ Calibration : PASS
2046 17:43:53.066438 Jitter Meter : NO K
2047 17:43:53.069261 CBT Training : PASS
2048 17:43:53.069802 Write leveling : PASS
2049 17:43:53.072614 RX DQS gating : PASS
2050 17:43:53.076542 RX DQ/DQS(RDDQC) : PASS
2051 17:43:53.077096 TX DQ/DQS : PASS
2052 17:43:53.079591 RX DATLAT : PASS
2053 17:43:53.083091 RX DQ/DQS(Engine): PASS
2054 17:43:53.083661 TX OE : NO K
2055 17:43:53.086596 All Pass.
2056 17:43:53.087156
2057 17:43:53.087522 CH 0, Rank 1
2058 17:43:53.089702 SW Impedance : PASS
2059 17:43:53.090275 DUTY Scan : NO K
2060 17:43:53.093033 ZQ Calibration : PASS
2061 17:43:53.096422 Jitter Meter : NO K
2062 17:43:53.097017 CBT Training : PASS
2063 17:43:53.099769 Write leveling : PASS
2064 17:43:53.102918 RX DQS gating : PASS
2065 17:43:53.103483 RX DQ/DQS(RDDQC) : PASS
2066 17:43:53.106524 TX DQ/DQS : PASS
2067 17:43:53.107091 RX DATLAT : PASS
2068 17:43:53.109817 RX DQ/DQS(Engine): PASS
2069 17:43:53.112879 TX OE : NO K
2070 17:43:53.113483 All Pass.
2071 17:43:53.113857
2072 17:43:53.114201 CH 1, Rank 0
2073 17:43:53.116233 SW Impedance : PASS
2074 17:43:53.119759 DUTY Scan : NO K
2075 17:43:53.120223 ZQ Calibration : PASS
2076 17:43:53.123232 Jitter Meter : NO K
2077 17:43:53.126167 CBT Training : PASS
2078 17:43:53.126638 Write leveling : PASS
2079 17:43:53.129183 RX DQS gating : PASS
2080 17:43:53.132864 RX DQ/DQS(RDDQC) : PASS
2081 17:43:53.133475 TX DQ/DQS : PASS
2082 17:43:53.136247 RX DATLAT : PASS
2083 17:43:53.139612 RX DQ/DQS(Engine): PASS
2084 17:43:53.140209 TX OE : NO K
2085 17:43:53.140590 All Pass.
2086 17:43:53.143024
2087 17:43:53.143587 CH 1, Rank 1
2088 17:43:53.146047 SW Impedance : PASS
2089 17:43:53.146529 DUTY Scan : NO K
2090 17:43:53.149418 ZQ Calibration : PASS
2091 17:43:53.149882 Jitter Meter : NO K
2092 17:43:53.152814 CBT Training : PASS
2093 17:43:53.156233 Write leveling : PASS
2094 17:43:53.156793 RX DQS gating : PASS
2095 17:43:53.159462 RX DQ/DQS(RDDQC) : PASS
2096 17:43:53.163147 TX DQ/DQS : PASS
2097 17:43:53.163921 RX DATLAT : PASS
2098 17:43:53.166398 RX DQ/DQS(Engine): PASS
2099 17:43:53.169842 TX OE : NO K
2100 17:43:53.170431 All Pass.
2101 17:43:53.170801
2102 17:43:53.171142 DramC Write-DBI off
2103 17:43:53.173244 PER_BANK_REFRESH: Hybrid Mode
2104 17:43:53.176362 TX_TRACKING: ON
2105 17:43:53.179640 [GetDramInforAfterCalByMRR] Vendor 6.
2106 17:43:53.183159 [GetDramInforAfterCalByMRR] Revision 606.
2107 17:43:53.186518 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 17:43:53.187047 MR0 0x3b3b
2109 17:43:53.189586 MR8 0x5151
2110 17:43:53.193071 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 17:43:53.193490
2112 17:43:53.193820 MR0 0x3b3b
2113 17:43:53.194131 MR8 0x5151
2114 17:43:53.196493 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 17:43:53.199533
2116 17:43:53.206296 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 17:43:53.209975 [FAST_K] Save calibration result to emmc
2118 17:43:53.213414 [FAST_K] Save calibration result to emmc
2119 17:43:53.216519 dram_init: config_dvfs: 1
2120 17:43:53.219963 dramc_set_vcore_voltage set vcore to 662500
2121 17:43:53.223181 Read voltage for 1200, 2
2122 17:43:53.223749 Vio18 = 0
2123 17:43:53.226753 Vcore = 662500
2124 17:43:53.227318 Vdram = 0
2125 17:43:53.227690 Vddq = 0
2126 17:43:53.228034 Vmddr = 0
2127 17:43:53.232970 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 17:43:53.239403 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 17:43:53.239936 MEM_TYPE=3, freq_sel=15
2130 17:43:53.242979 sv_algorithm_assistance_LP4_1600
2131 17:43:53.246204 ============ PULL DRAM RESETB DOWN ============
2132 17:43:53.253326 ========== PULL DRAM RESETB DOWN end =========
2133 17:43:53.256370 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 17:43:53.259787 ===================================
2135 17:43:53.263389 LPDDR4 DRAM CONFIGURATION
2136 17:43:53.266642 ===================================
2137 17:43:53.267206 EX_ROW_EN[0] = 0x0
2138 17:43:53.269831 EX_ROW_EN[1] = 0x0
2139 17:43:53.270440 LP4Y_EN = 0x0
2140 17:43:53.273095 WORK_FSP = 0x0
2141 17:43:53.273661 WL = 0x4
2142 17:43:53.276434 RL = 0x4
2143 17:43:53.277043 BL = 0x2
2144 17:43:53.279737 RPST = 0x0
2145 17:43:53.280201 RD_PRE = 0x0
2146 17:43:53.282706 WR_PRE = 0x1
2147 17:43:53.286092 WR_PST = 0x0
2148 17:43:53.286559 DBI_WR = 0x0
2149 17:43:53.289566 DBI_RD = 0x0
2150 17:43:53.290083 OTF = 0x1
2151 17:43:53.293172 ===================================
2152 17:43:53.296257 ===================================
2153 17:43:53.296682 ANA top config
2154 17:43:53.299451 ===================================
2155 17:43:53.302926 DLL_ASYNC_EN = 0
2156 17:43:53.306575 ALL_SLAVE_EN = 0
2157 17:43:53.309669 NEW_RANK_MODE = 1
2158 17:43:53.310334 DLL_IDLE_MODE = 1
2159 17:43:53.312815 LP45_APHY_COMB_EN = 1
2160 17:43:53.316116 TX_ODT_DIS = 1
2161 17:43:53.319602 NEW_8X_MODE = 1
2162 17:43:53.323586 ===================================
2163 17:43:53.326212 ===================================
2164 17:43:53.329858 data_rate = 2400
2165 17:43:53.333038 CKR = 1
2166 17:43:53.333463 DQ_P2S_RATIO = 8
2167 17:43:53.336649 ===================================
2168 17:43:53.339785 CA_P2S_RATIO = 8
2169 17:43:53.342836 DQ_CA_OPEN = 0
2170 17:43:53.346160 DQ_SEMI_OPEN = 0
2171 17:43:53.349463 CA_SEMI_OPEN = 0
2172 17:43:53.350039 CA_FULL_RATE = 0
2173 17:43:53.353167 DQ_CKDIV4_EN = 0
2174 17:43:53.356106 CA_CKDIV4_EN = 0
2175 17:43:53.359949 CA_PREDIV_EN = 0
2176 17:43:53.362769 PH8_DLY = 17
2177 17:43:53.366332 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 17:43:53.366783 DQ_AAMCK_DIV = 4
2179 17:43:53.369530 CA_AAMCK_DIV = 4
2180 17:43:53.373008 CA_ADMCK_DIV = 4
2181 17:43:53.376370 DQ_TRACK_CA_EN = 0
2182 17:43:53.379890 CA_PICK = 1200
2183 17:43:53.382803 CA_MCKIO = 1200
2184 17:43:53.386606 MCKIO_SEMI = 0
2185 17:43:53.387143 PLL_FREQ = 2366
2186 17:43:53.389789 DQ_UI_PI_RATIO = 32
2187 17:43:53.393031 CA_UI_PI_RATIO = 0
2188 17:43:53.396516 ===================================
2189 17:43:53.399534 ===================================
2190 17:43:53.403017 memory_type:LPDDR4
2191 17:43:53.403321 GP_NUM : 10
2192 17:43:53.407349 SRAM_EN : 1
2193 17:43:53.409760 MD32_EN : 0
2194 17:43:53.412914 ===================================
2195 17:43:53.413258 [ANA_INIT] >>>>>>>>>>>>>>
2196 17:43:53.415951 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 17:43:53.419755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 17:43:53.422829 ===================================
2199 17:43:53.426138 data_rate = 2400,PCW = 0X5b00
2200 17:43:53.429713 ===================================
2201 17:43:53.433077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 17:43:53.439886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 17:43:53.443145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 17:43:53.449550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 17:43:53.453014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 17:43:53.456359 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 17:43:53.456687 [ANA_INIT] flow start
2208 17:43:53.459945 [ANA_INIT] PLL >>>>>>>>
2209 17:43:53.463028 [ANA_INIT] PLL <<<<<<<<
2210 17:43:53.463410 [ANA_INIT] MIDPI >>>>>>>>
2211 17:43:53.466276 [ANA_INIT] MIDPI <<<<<<<<
2212 17:43:53.469632 [ANA_INIT] DLL >>>>>>>>
2213 17:43:53.473274 [ANA_INIT] DLL <<<<<<<<
2214 17:43:53.473617 [ANA_INIT] flow end
2215 17:43:53.476364 ============ LP4 DIFF to SE enter ============
2216 17:43:53.483247 ============ LP4 DIFF to SE exit ============
2217 17:43:53.483561 [ANA_INIT] <<<<<<<<<<<<<
2218 17:43:53.486782 [Flow] Enable top DCM control >>>>>
2219 17:43:53.489692 [Flow] Enable top DCM control <<<<<
2220 17:43:53.493124 Enable DLL master slave shuffle
2221 17:43:53.499689 ==============================================================
2222 17:43:53.499997 Gating Mode config
2223 17:43:53.506316 ==============================================================
2224 17:43:53.509682 Config description:
2225 17:43:53.516213 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 17:43:53.522952 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 17:43:53.529679 SELPH_MODE 0: By rank 1: By Phase
2228 17:43:53.533118 ==============================================================
2229 17:43:53.536334 GAT_TRACK_EN = 1
2230 17:43:53.540143 RX_GATING_MODE = 2
2231 17:43:53.543187 RX_GATING_TRACK_MODE = 2
2232 17:43:53.546848 SELPH_MODE = 1
2233 17:43:53.549979 PICG_EARLY_EN = 1
2234 17:43:53.552995 VALID_LAT_VALUE = 1
2235 17:43:53.559798 ==============================================================
2236 17:43:53.562917 Enter into Gating configuration >>>>
2237 17:43:53.566764 Exit from Gating configuration <<<<
2238 17:43:53.569670 Enter into DVFS_PRE_config >>>>>
2239 17:43:53.579820 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 17:43:53.583376 Exit from DVFS_PRE_config <<<<<
2241 17:43:53.587024 Enter into PICG configuration >>>>
2242 17:43:53.589806 Exit from PICG configuration <<<<
2243 17:43:53.593766 [RX_INPUT] configuration >>>>>
2244 17:43:53.594305 [RX_INPUT] configuration <<<<<
2245 17:43:53.599922 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 17:43:53.606410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 17:43:53.610005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 17:43:53.616494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 17:43:53.623458 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 17:43:53.629866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 17:43:53.633225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 17:43:53.637053 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 17:43:53.643127 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 17:43:53.646664 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 17:43:53.649758 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 17:43:53.653528 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 17:43:53.656653 ===================================
2258 17:43:53.660007 LPDDR4 DRAM CONFIGURATION
2259 17:43:53.663247 ===================================
2260 17:43:53.666544 EX_ROW_EN[0] = 0x0
2261 17:43:53.666988 EX_ROW_EN[1] = 0x0
2262 17:43:53.669789 LP4Y_EN = 0x0
2263 17:43:53.670230 WORK_FSP = 0x0
2264 17:43:53.673293 WL = 0x4
2265 17:43:53.673733 RL = 0x4
2266 17:43:53.676556 BL = 0x2
2267 17:43:53.677134 RPST = 0x0
2268 17:43:53.680113 RD_PRE = 0x0
2269 17:43:53.680562 WR_PRE = 0x1
2270 17:43:53.683386 WR_PST = 0x0
2271 17:43:53.683948 DBI_WR = 0x0
2272 17:43:53.687037 DBI_RD = 0x0
2273 17:43:53.687565 OTF = 0x1
2274 17:43:53.690143 ===================================
2275 17:43:53.696611 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 17:43:53.699913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 17:43:53.703667 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 17:43:53.706747 ===================================
2279 17:43:53.709604 LPDDR4 DRAM CONFIGURATION
2280 17:43:53.713229 ===================================
2281 17:43:53.716410 EX_ROW_EN[0] = 0x10
2282 17:43:53.716863 EX_ROW_EN[1] = 0x0
2283 17:43:53.719734 LP4Y_EN = 0x0
2284 17:43:53.720195 WORK_FSP = 0x0
2285 17:43:53.723086 WL = 0x4
2286 17:43:53.723507 RL = 0x4
2287 17:43:53.726394 BL = 0x2
2288 17:43:53.726814 RPST = 0x0
2289 17:43:53.729579 RD_PRE = 0x0
2290 17:43:53.729999 WR_PRE = 0x1
2291 17:43:53.733110 WR_PST = 0x0
2292 17:43:53.733528 DBI_WR = 0x0
2293 17:43:53.736243 DBI_RD = 0x0
2294 17:43:53.736676 OTF = 0x1
2295 17:43:53.739823 ===================================
2296 17:43:53.746572 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 17:43:53.747061 ==
2298 17:43:53.749564 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 17:43:53.753231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 17:43:53.756554 ==
2301 17:43:53.756997 [Duty_Offset_Calibration]
2302 17:43:53.759883 B0:2 B1:0 CA:1
2303 17:43:53.760290
2304 17:43:53.763307 [DutyScan_Calibration_Flow] k_type=0
2305 17:43:53.770824
2306 17:43:53.771262 ==CLK 0==
2307 17:43:53.774050 Final CLK duty delay cell = -4
2308 17:43:53.777592 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2309 17:43:53.780988 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2310 17:43:53.784591 [-4] AVG Duty = 4953%(X100)
2311 17:43:53.785038
2312 17:43:53.787731 CH0 CLK Duty spec in!! Max-Min= 156%
2313 17:43:53.790746 [DutyScan_Calibration_Flow] ====Done====
2314 17:43:53.791179
2315 17:43:53.794327 [DutyScan_Calibration_Flow] k_type=1
2316 17:43:53.809838
2317 17:43:53.810285 ==DQS 0 ==
2318 17:43:53.812975 Final DQS duty delay cell = 0
2319 17:43:53.816306 [0] MAX Duty = 5187%(X100), DQS PI = 30
2320 17:43:53.819747 [0] MIN Duty = 4938%(X100), DQS PI = 0
2321 17:43:53.820163 [0] AVG Duty = 5062%(X100)
2322 17:43:53.823096
2323 17:43:53.823504 ==DQS 1 ==
2324 17:43:53.826833 Final DQS duty delay cell = -4
2325 17:43:53.829886 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2326 17:43:53.832985 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2327 17:43:53.836677 [-4] AVG Duty = 5031%(X100)
2328 17:43:53.837192
2329 17:43:53.839501 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2330 17:43:53.839911
2331 17:43:53.842798 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2332 17:43:53.846131 [DutyScan_Calibration_Flow] ====Done====
2333 17:43:53.846543
2334 17:43:53.849836 [DutyScan_Calibration_Flow] k_type=3
2335 17:43:53.866454
2336 17:43:53.867049 ==DQM 0 ==
2337 17:43:53.869670 Final DQM duty delay cell = 0
2338 17:43:53.873446 [0] MAX Duty = 5062%(X100), DQS PI = 24
2339 17:43:53.876515 [0] MIN Duty = 4875%(X100), DQS PI = 0
2340 17:43:53.876927 [0] AVG Duty = 4968%(X100)
2341 17:43:53.879753
2342 17:43:53.880280 ==DQM 1 ==
2343 17:43:53.883122 Final DQM duty delay cell = 0
2344 17:43:53.886458 [0] MAX Duty = 5187%(X100), DQS PI = 46
2345 17:43:53.890145 [0] MIN Duty = 5000%(X100), DQS PI = 12
2346 17:43:53.890558 [0] AVG Duty = 5093%(X100)
2347 17:43:53.893784
2348 17:43:53.896853 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2349 17:43:53.897434
2350 17:43:53.900116 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2351 17:43:53.903278 [DutyScan_Calibration_Flow] ====Done====
2352 17:43:53.903788
2353 17:43:53.906381 [DutyScan_Calibration_Flow] k_type=2
2354 17:43:53.923348
2355 17:43:53.923864 ==DQ 0 ==
2356 17:43:53.926043 Final DQ duty delay cell = -4
2357 17:43:53.929583 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2358 17:43:53.932873 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2359 17:43:53.936193 [-4] AVG Duty = 4953%(X100)
2360 17:43:53.936605
2361 17:43:53.936926 ==DQ 1 ==
2362 17:43:53.939653 Final DQ duty delay cell = 4
2363 17:43:53.943031 [4] MAX Duty = 5093%(X100), DQS PI = 4
2364 17:43:53.946107 [4] MIN Duty = 5031%(X100), DQS PI = 0
2365 17:43:53.946517 [4] AVG Duty = 5062%(X100)
2366 17:43:53.949615
2367 17:43:53.952890 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2368 17:43:53.953334
2369 17:43:53.956418 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2370 17:43:53.959508 [DutyScan_Calibration_Flow] ====Done====
2371 17:43:53.959936 ==
2372 17:43:53.962714 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 17:43:53.966454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 17:43:53.966867 ==
2375 17:43:53.969546 [Duty_Offset_Calibration]
2376 17:43:53.969956 B0:0 B1:-1 CA:2
2377 17:43:53.970278
2378 17:43:53.972794 [DutyScan_Calibration_Flow] k_type=0
2379 17:43:53.982911
2380 17:43:53.983505 ==CLK 0==
2381 17:43:53.986369 Final CLK duty delay cell = 0
2382 17:43:53.989567 [0] MAX Duty = 5156%(X100), DQS PI = 16
2383 17:43:53.993192 [0] MIN Duty = 4938%(X100), DQS PI = 44
2384 17:43:53.993754 [0] AVG Duty = 5047%(X100)
2385 17:43:53.996664
2386 17:43:53.999806 CH1 CLK Duty spec in!! Max-Min= 218%
2387 17:43:54.003083 [DutyScan_Calibration_Flow] ====Done====
2388 17:43:54.003501
2389 17:43:54.006137 [DutyScan_Calibration_Flow] k_type=1
2390 17:43:54.022488
2391 17:43:54.023124 ==DQS 0 ==
2392 17:43:54.025772 Final DQS duty delay cell = 0
2393 17:43:54.028970 [0] MAX Duty = 5093%(X100), DQS PI = 24
2394 17:43:54.032737 [0] MIN Duty = 4969%(X100), DQS PI = 0
2395 17:43:54.033164 [0] AVG Duty = 5031%(X100)
2396 17:43:54.035959
2397 17:43:54.036477 ==DQS 1 ==
2398 17:43:54.039156 Final DQS duty delay cell = 0
2399 17:43:54.042508 [0] MAX Duty = 5156%(X100), DQS PI = 0
2400 17:43:54.046079 [0] MIN Duty = 4844%(X100), DQS PI = 36
2401 17:43:54.046506 [0] AVG Duty = 5000%(X100)
2402 17:43:54.049561
2403 17:43:54.052479 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2404 17:43:54.053048
2405 17:43:54.056070 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2406 17:43:54.059229 [DutyScan_Calibration_Flow] ====Done====
2407 17:43:54.059651
2408 17:43:54.062380 [DutyScan_Calibration_Flow] k_type=3
2409 17:43:54.079151
2410 17:43:54.079715 ==DQM 0 ==
2411 17:43:54.082306 Final DQM duty delay cell = 4
2412 17:43:54.086038 [4] MAX Duty = 5093%(X100), DQS PI = 22
2413 17:43:54.088996 [4] MIN Duty = 4938%(X100), DQS PI = 30
2414 17:43:54.089424 [4] AVG Duty = 5015%(X100)
2415 17:43:54.092709
2416 17:43:54.093168 ==DQM 1 ==
2417 17:43:54.095820 Final DQM duty delay cell = -4
2418 17:43:54.098926 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2419 17:43:54.102483 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2420 17:43:54.105534 [-4] AVG Duty = 4891%(X100)
2421 17:43:54.105961
2422 17:43:54.109152 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2423 17:43:54.109614
2424 17:43:54.112261 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2425 17:43:54.115814 [DutyScan_Calibration_Flow] ====Done====
2426 17:43:54.116235
2427 17:43:54.118808 [DutyScan_Calibration_Flow] k_type=2
2428 17:43:54.136132
2429 17:43:54.136593 ==DQ 0 ==
2430 17:43:54.139131 Final DQ duty delay cell = 0
2431 17:43:54.142720 [0] MAX Duty = 5062%(X100), DQS PI = 20
2432 17:43:54.146114 [0] MIN Duty = 4938%(X100), DQS PI = 2
2433 17:43:54.146546 [0] AVG Duty = 5000%(X100)
2434 17:43:54.146888
2435 17:43:54.149410 ==DQ 1 ==
2436 17:43:54.152545 Final DQ duty delay cell = 0
2437 17:43:54.156015 [0] MAX Duty = 5031%(X100), DQS PI = 0
2438 17:43:54.159202 [0] MIN Duty = 4813%(X100), DQS PI = 36
2439 17:43:54.159800 [0] AVG Duty = 4922%(X100)
2440 17:43:54.160367
2441 17:43:54.162400 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 17:43:54.162769
2443 17:43:54.165957 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2444 17:43:54.173002 [DutyScan_Calibration_Flow] ====Done====
2445 17:43:54.176243 nWR fixed to 30
2446 17:43:54.176681 [ModeRegInit_LP4] CH0 RK0
2447 17:43:54.179486 [ModeRegInit_LP4] CH0 RK1
2448 17:43:54.182599 [ModeRegInit_LP4] CH1 RK0
2449 17:43:54.183028 [ModeRegInit_LP4] CH1 RK1
2450 17:43:54.186218 match AC timing 7
2451 17:43:54.189766 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 17:43:54.192434 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 17:43:54.199291 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 17:43:54.202634 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 17:43:54.209520 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 17:43:54.209951 ==
2457 17:43:54.212712 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 17:43:54.216330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 17:43:54.216853 ==
2460 17:43:54.222648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 17:43:54.226127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2462 17:43:54.235857 [CA 0] Center 38 (8~69) winsize 62
2463 17:43:54.239094 [CA 1] Center 38 (8~69) winsize 62
2464 17:43:54.242755 [CA 2] Center 35 (5~66) winsize 62
2465 17:43:54.245777 [CA 3] Center 35 (4~66) winsize 63
2466 17:43:54.249200 [CA 4] Center 34 (4~65) winsize 62
2467 17:43:54.252760 [CA 5] Center 33 (3~63) winsize 61
2468 17:43:54.253268
2469 17:43:54.255589 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2470 17:43:54.256020
2471 17:43:54.259258 [CATrainingPosCal] consider 1 rank data
2472 17:43:54.262354 u2DelayCellTimex100 = 270/100 ps
2473 17:43:54.265972 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2474 17:43:54.268960 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 17:43:54.275955 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 17:43:54.279389 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2477 17:43:54.282354 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 17:43:54.285950 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 17:43:54.286429
2480 17:43:54.289104 CA PerBit enable=1, Macro0, CA PI delay=33
2481 17:43:54.289548
2482 17:43:54.292214 [CBTSetCACLKResult] CA Dly = 33
2483 17:43:54.292729 CS Dly: 6 (0~37)
2484 17:43:54.293110 ==
2485 17:43:54.295892 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 17:43:54.302255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 17:43:54.302788 ==
2488 17:43:54.305765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 17:43:54.312668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 17:43:54.321467 [CA 0] Center 39 (8~70) winsize 63
2491 17:43:54.324789 [CA 1] Center 38 (8~69) winsize 62
2492 17:43:54.328030 [CA 2] Center 35 (5~66) winsize 62
2493 17:43:54.331340 [CA 3] Center 35 (5~66) winsize 62
2494 17:43:54.334846 [CA 4] Center 34 (4~65) winsize 62
2495 17:43:54.338119 [CA 5] Center 34 (4~64) winsize 61
2496 17:43:54.338576
2497 17:43:54.341582 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2498 17:43:54.342013
2499 17:43:54.344789 [CATrainingPosCal] consider 2 rank data
2500 17:43:54.348602 u2DelayCellTimex100 = 270/100 ps
2501 17:43:54.351774 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2502 17:43:54.354968 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 17:43:54.358360 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 17:43:54.364742 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 17:43:54.368353 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 17:43:54.371657 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2507 17:43:54.372076
2508 17:43:54.374924 CA PerBit enable=1, Macro0, CA PI delay=33
2509 17:43:54.375367
2510 17:43:54.378282 [CBTSetCACLKResult] CA Dly = 33
2511 17:43:54.378700 CS Dly: 7 (0~39)
2512 17:43:54.379026
2513 17:43:54.381985 ----->DramcWriteLeveling(PI) begin...
2514 17:43:54.382410 ==
2515 17:43:54.385023 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 17:43:54.391710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 17:43:54.392135 ==
2518 17:43:54.394747 Write leveling (Byte 0): 34 => 34
2519 17:43:54.398021 Write leveling (Byte 1): 29 => 29
2520 17:43:54.398443 DramcWriteLeveling(PI) end<-----
2521 17:43:54.401737
2522 17:43:54.402155 ==
2523 17:43:54.404734 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 17:43:54.408417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 17:43:54.408838 ==
2526 17:43:54.411600 [Gating] SW mode calibration
2527 17:43:54.418351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 17:43:54.421387 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 17:43:54.428044 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2530 17:43:54.431672 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2531 17:43:54.435047 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 17:43:54.441562 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 17:43:54.444911 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 17:43:54.448326 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 17:43:54.455097 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
2536 17:43:54.458217 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2537 17:43:54.461855 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2538 17:43:54.468378 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 17:43:54.471545 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 17:43:54.474796 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 17:43:54.481430 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 17:43:54.484956 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 17:43:54.488053 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2544 17:43:54.491470 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2545 17:43:54.498575 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2546 17:43:54.501785 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2547 17:43:54.504861 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 17:43:54.511696 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 17:43:54.514947 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 17:43:54.518598 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 17:43:54.524756 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 17:43:54.528375 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 17:43:54.531868 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 17:43:54.538381 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 17:43:54.541871 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 17:43:54.545222 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 17:43:54.551652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 17:43:54.554841 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 17:43:54.558594 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 17:43:54.564852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 17:43:54.568639 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 17:43:54.571772 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 17:43:54.575189 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 17:43:54.581945 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 17:43:54.585182 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 17:43:54.588564 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 17:43:54.595391 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 17:43:54.598435 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 17:43:54.601926 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 17:43:54.605039 Total UI for P1: 0, mck2ui 16
2571 17:43:54.608589 best dqsien dly found for B0: ( 1, 3, 28)
2572 17:43:54.615276 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 17:43:54.615817 Total UI for P1: 0, mck2ui 16
2574 17:43:54.621892 best dqsien dly found for B1: ( 1, 4, 0)
2575 17:43:54.625515 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2576 17:43:54.628599 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 17:43:54.629250
2578 17:43:54.632119 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2579 17:43:54.635783 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 17:43:54.638920 [Gating] SW calibration Done
2581 17:43:54.639343 ==
2582 17:43:54.642234 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 17:43:54.645254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 17:43:54.645686 ==
2585 17:43:54.648650 RX Vref Scan: 0
2586 17:43:54.649125
2587 17:43:54.649468 RX Vref 0 -> 0, step: 1
2588 17:43:54.649786
2589 17:43:54.651781 RX Delay -40 -> 252, step: 8
2590 17:43:54.655471 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2591 17:43:54.661830 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2592 17:43:54.665530 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2593 17:43:54.668604 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2594 17:43:54.671715 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2595 17:43:54.675194 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2596 17:43:54.678676 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2597 17:43:54.685067 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2598 17:43:54.688800 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2599 17:43:54.691803 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2600 17:43:54.694905 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2601 17:43:54.698531 iDelay=208, Bit 11, Center 111 (48 ~ 175) 128
2602 17:43:54.705407 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2603 17:43:54.708456 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2604 17:43:54.711872 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2605 17:43:54.715303 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2606 17:43:54.715730 ==
2607 17:43:54.718590 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 17:43:54.725279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 17:43:54.725895 ==
2610 17:43:54.726262 DQS Delay:
2611 17:43:54.728424 DQS0 = 0, DQS1 = 0
2612 17:43:54.728845 DQM Delay:
2613 17:43:54.729233 DQM0 = 123, DQM1 = 110
2614 17:43:54.732062 DQ Delay:
2615 17:43:54.735361 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2616 17:43:54.738465 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2617 17:43:54.742199 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =111
2618 17:43:54.745398 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2619 17:43:54.745824
2620 17:43:54.746157
2621 17:43:54.746469 ==
2622 17:43:54.748407 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 17:43:54.752100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 17:43:54.752586 ==
2625 17:43:54.755081
2626 17:43:54.755501
2627 17:43:54.755830 TX Vref Scan disable
2628 17:43:54.758783 == TX Byte 0 ==
2629 17:43:54.761832 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2630 17:43:54.765021 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2631 17:43:54.768888 == TX Byte 1 ==
2632 17:43:54.771948 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2633 17:43:54.775301 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2634 17:43:54.775726 ==
2635 17:43:54.778494 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 17:43:54.785016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 17:43:54.785442 ==
2638 17:43:54.796054 TX Vref=22, minBit 0, minWin=24, winSum=408
2639 17:43:54.799534 TX Vref=24, minBit 0, minWin=24, winSum=411
2640 17:43:54.802718 TX Vref=26, minBit 7, minWin=24, winSum=416
2641 17:43:54.806078 TX Vref=28, minBit 3, minWin=25, winSum=419
2642 17:43:54.809344 TX Vref=30, minBit 3, minWin=25, winSum=425
2643 17:43:54.812560 TX Vref=32, minBit 3, minWin=25, winSum=421
2644 17:43:54.819473 [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 30
2645 17:43:54.819919
2646 17:43:54.822569 Final TX Range 1 Vref 30
2647 17:43:54.823008
2648 17:43:54.823340 ==
2649 17:43:54.826229 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 17:43:54.829475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 17:43:54.829897 ==
2652 17:43:54.830230
2653 17:43:54.832685
2654 17:43:54.833202 TX Vref Scan disable
2655 17:43:54.836289 == TX Byte 0 ==
2656 17:43:54.839646 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2657 17:43:54.843155 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2658 17:43:54.845957 == TX Byte 1 ==
2659 17:43:54.849645 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2660 17:43:54.853232 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2661 17:43:54.853656
2662 17:43:54.856314 [DATLAT]
2663 17:43:54.856736 Freq=1200, CH0 RK0
2664 17:43:54.857104
2665 17:43:54.859635 DATLAT Default: 0xd
2666 17:43:54.860057 0, 0xFFFF, sum = 0
2667 17:43:54.863292 1, 0xFFFF, sum = 0
2668 17:43:54.863726 2, 0xFFFF, sum = 0
2669 17:43:54.866395 3, 0xFFFF, sum = 0
2670 17:43:54.866959 4, 0xFFFF, sum = 0
2671 17:43:54.869378 5, 0xFFFF, sum = 0
2672 17:43:54.869771 6, 0xFFFF, sum = 0
2673 17:43:54.872902 7, 0xFFFF, sum = 0
2674 17:43:54.873369 8, 0xFFFF, sum = 0
2675 17:43:54.876272 9, 0xFFFF, sum = 0
2676 17:43:54.876701 10, 0xFFFF, sum = 0
2677 17:43:54.879608 11, 0xFFFF, sum = 0
2678 17:43:54.882610 12, 0x0, sum = 1
2679 17:43:54.883045 13, 0x0, sum = 2
2680 17:43:54.886269 14, 0x0, sum = 3
2681 17:43:54.886701 15, 0x0, sum = 4
2682 17:43:54.887045 best_step = 13
2683 17:43:54.887398
2684 17:43:54.889397 ==
2685 17:43:54.889893 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 17:43:54.895954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 17:43:54.896381 ==
2688 17:43:54.896851 RX Vref Scan: 1
2689 17:43:54.897224
2690 17:43:54.899519 Set Vref Range= 32 -> 127
2691 17:43:54.899941
2692 17:43:54.902618 RX Vref 32 -> 127, step: 1
2693 17:43:54.903040
2694 17:43:54.906015 RX Delay -13 -> 252, step: 4
2695 17:43:54.906489
2696 17:43:54.909670 Set Vref, RX VrefLevel [Byte0]: 32
2697 17:43:54.912785 [Byte1]: 32
2698 17:43:54.913245
2699 17:43:54.915992 Set Vref, RX VrefLevel [Byte0]: 33
2700 17:43:54.919666 [Byte1]: 33
2701 17:43:54.920089
2702 17:43:54.922835 Set Vref, RX VrefLevel [Byte0]: 34
2703 17:43:54.926006 [Byte1]: 34
2704 17:43:54.930029
2705 17:43:54.930446 Set Vref, RX VrefLevel [Byte0]: 35
2706 17:43:54.933396 [Byte1]: 35
2707 17:43:54.938159
2708 17:43:54.938589 Set Vref, RX VrefLevel [Byte0]: 36
2709 17:43:54.941493 [Byte1]: 36
2710 17:43:54.946057
2711 17:43:54.946620 Set Vref, RX VrefLevel [Byte0]: 37
2712 17:43:54.949493 [Byte1]: 37
2713 17:43:54.953632
2714 17:43:54.954205 Set Vref, RX VrefLevel [Byte0]: 38
2715 17:43:54.957195 [Byte1]: 38
2716 17:43:54.961529
2717 17:43:54.961951 Set Vref, RX VrefLevel [Byte0]: 39
2718 17:43:54.965287 [Byte1]: 39
2719 17:43:54.969512
2720 17:43:54.969936 Set Vref, RX VrefLevel [Byte0]: 40
2721 17:43:54.972906 [Byte1]: 40
2722 17:43:54.977361
2723 17:43:54.977906 Set Vref, RX VrefLevel [Byte0]: 41
2724 17:43:54.980847 [Byte1]: 41
2725 17:43:54.985185
2726 17:43:54.985607 Set Vref, RX VrefLevel [Byte0]: 42
2727 17:43:54.988526 [Byte1]: 42
2728 17:43:54.993119
2729 17:43:54.993541 Set Vref, RX VrefLevel [Byte0]: 43
2730 17:43:54.996735 [Byte1]: 43
2731 17:43:55.001255
2732 17:43:55.001863 Set Vref, RX VrefLevel [Byte0]: 44
2733 17:43:55.004461 [Byte1]: 44
2734 17:43:55.008843
2735 17:43:55.009322 Set Vref, RX VrefLevel [Byte0]: 45
2736 17:43:55.012478 [Byte1]: 45
2737 17:43:55.017036
2738 17:43:55.017468 Set Vref, RX VrefLevel [Byte0]: 46
2739 17:43:55.020195 [Byte1]: 46
2740 17:43:55.024578
2741 17:43:55.025044 Set Vref, RX VrefLevel [Byte0]: 47
2742 17:43:55.028351 [Byte1]: 47
2743 17:43:55.032659
2744 17:43:55.033113 Set Vref, RX VrefLevel [Byte0]: 48
2745 17:43:55.036064 [Byte1]: 48
2746 17:43:55.040672
2747 17:43:55.041144 Set Vref, RX VrefLevel [Byte0]: 49
2748 17:43:55.043746 [Byte1]: 49
2749 17:43:55.048541
2750 17:43:55.049030 Set Vref, RX VrefLevel [Byte0]: 50
2751 17:43:55.051895 [Byte1]: 50
2752 17:43:55.056309
2753 17:43:55.056866 Set Vref, RX VrefLevel [Byte0]: 51
2754 17:43:55.060069 [Byte1]: 51
2755 17:43:55.064187
2756 17:43:55.064644 Set Vref, RX VrefLevel [Byte0]: 52
2757 17:43:55.067395 [Byte1]: 52
2758 17:43:55.072146
2759 17:43:55.072565 Set Vref, RX VrefLevel [Byte0]: 53
2760 17:43:55.075625 [Byte1]: 53
2761 17:43:55.080261
2762 17:43:55.080678 Set Vref, RX VrefLevel [Byte0]: 54
2763 17:43:55.083615 [Byte1]: 54
2764 17:43:55.088076
2765 17:43:55.088620 Set Vref, RX VrefLevel [Byte0]: 55
2766 17:43:55.091074 [Byte1]: 55
2767 17:43:55.095717
2768 17:43:55.096134 Set Vref, RX VrefLevel [Byte0]: 56
2769 17:43:55.098992 [Byte1]: 56
2770 17:43:55.103489
2771 17:43:55.103910 Set Vref, RX VrefLevel [Byte0]: 57
2772 17:43:55.107105 [Byte1]: 57
2773 17:43:55.111518
2774 17:43:55.111936 Set Vref, RX VrefLevel [Byte0]: 58
2775 17:43:55.114934 [Byte1]: 58
2776 17:43:55.119587
2777 17:43:55.120005 Set Vref, RX VrefLevel [Byte0]: 59
2778 17:43:55.122899 [Byte1]: 59
2779 17:43:55.127514
2780 17:43:55.128030 Set Vref, RX VrefLevel [Byte0]: 60
2781 17:43:55.130721 [Byte1]: 60
2782 17:43:55.135273
2783 17:43:55.135693 Set Vref, RX VrefLevel [Byte0]: 61
2784 17:43:55.138508 [Byte1]: 61
2785 17:43:55.143047
2786 17:43:55.143466 Set Vref, RX VrefLevel [Byte0]: 62
2787 17:43:55.146311 [Byte1]: 62
2788 17:43:55.151194
2789 17:43:55.151630 Set Vref, RX VrefLevel [Byte0]: 63
2790 17:43:55.154142 [Byte1]: 63
2791 17:43:55.158738
2792 17:43:55.159188 Set Vref, RX VrefLevel [Byte0]: 64
2793 17:43:55.162153 [Byte1]: 64
2794 17:43:55.166844
2795 17:43:55.167286 Set Vref, RX VrefLevel [Byte0]: 65
2796 17:43:55.170172 [Byte1]: 65
2797 17:43:55.174727
2798 17:43:55.175254 Set Vref, RX VrefLevel [Byte0]: 66
2799 17:43:55.178090 [Byte1]: 66
2800 17:43:55.182351
2801 17:43:55.182916 Set Vref, RX VrefLevel [Byte0]: 67
2802 17:43:55.185984 [Byte1]: 67
2803 17:43:55.190378
2804 17:43:55.190843 Set Vref, RX VrefLevel [Byte0]: 68
2805 17:43:55.193577 [Byte1]: 68
2806 17:43:55.198321
2807 17:43:55.198738 Set Vref, RX VrefLevel [Byte0]: 69
2808 17:43:55.201796 [Byte1]: 69
2809 17:43:55.206208
2810 17:43:55.206628 Final RX Vref Byte 0 = 59 to rank0
2811 17:43:55.209907 Final RX Vref Byte 1 = 48 to rank0
2812 17:43:55.212894 Final RX Vref Byte 0 = 59 to rank1
2813 17:43:55.216646 Final RX Vref Byte 1 = 48 to rank1==
2814 17:43:55.219802 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 17:43:55.223065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 17:43:55.226630 ==
2817 17:43:55.227075 DQS Delay:
2818 17:43:55.227617 DQS0 = 0, DQS1 = 0
2819 17:43:55.229842 DQM Delay:
2820 17:43:55.230269 DQM0 = 123, DQM1 = 108
2821 17:43:55.233034 DQ Delay:
2822 17:43:55.236619 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2823 17:43:55.239650 DQ4 =126, DQ5 =116, DQ6 =132, DQ7 =128
2824 17:43:55.243281 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2825 17:43:55.246269 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2826 17:43:55.246689
2827 17:43:55.247015
2828 17:43:55.253174 [DQSOSCAuto] RK0, (LSB)MR18= 0x502, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 408 ps
2829 17:43:55.256298 CH0 RK0: MR19=404, MR18=502
2830 17:43:55.262958 CH0_RK0: MR19=0x404, MR18=0x502, DQSOSC=408, MR23=63, INC=39, DEC=26
2831 17:43:55.263393
2832 17:43:55.266587 ----->DramcWriteLeveling(PI) begin...
2833 17:43:55.267022 ==
2834 17:43:55.269739 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 17:43:55.273038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 17:43:55.273468 ==
2837 17:43:55.276746 Write leveling (Byte 0): 36 => 36
2838 17:43:55.280455 Write leveling (Byte 1): 30 => 30
2839 17:43:55.283236 DramcWriteLeveling(PI) end<-----
2840 17:43:55.283682
2841 17:43:55.284016 ==
2842 17:43:55.286626 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 17:43:55.290282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 17:43:55.290708 ==
2845 17:43:55.293341 [Gating] SW mode calibration
2846 17:43:55.299966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 17:43:55.306714 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 17:43:55.310183 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2849 17:43:55.316383 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 17:43:55.320018 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 17:43:55.322974 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 17:43:55.329764 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 17:43:55.333173 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 17:43:55.336436 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 17:43:55.342984 0 15 28 | B1->B0 | 3030 2c2c | 0 0 | (1 0) (0 1)
2856 17:43:55.346574 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 17:43:55.349573 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 17:43:55.356331 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 17:43:55.359956 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 17:43:55.363463 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 17:43:55.366663 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 17:43:55.373277 1 0 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2863 17:43:55.376742 1 0 28 | B1->B0 | 3636 4343 | 1 0 | (0 0) (0 0)
2864 17:43:55.379885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 17:43:55.386461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 17:43:55.389996 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 17:43:55.393501 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 17:43:55.399930 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 17:43:55.403494 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 17:43:55.406440 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 17:43:55.413063 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2872 17:43:55.416681 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2873 17:43:55.420180 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 17:43:55.427126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 17:43:55.430129 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 17:43:55.433352 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 17:43:55.440022 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 17:43:55.443122 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 17:43:55.446370 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 17:43:55.452914 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 17:43:55.456306 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 17:43:55.459903 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 17:43:55.462997 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 17:43:55.469576 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 17:43:55.473234 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 17:43:55.476699 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 17:43:55.483424 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2888 17:43:55.486641 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2889 17:43:55.489712 Total UI for P1: 0, mck2ui 16
2890 17:43:55.493149 best dqsien dly found for B1: ( 1, 3, 28)
2891 17:43:55.496571 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 17:43:55.499687 Total UI for P1: 0, mck2ui 16
2893 17:43:55.503162 best dqsien dly found for B0: ( 1, 3, 30)
2894 17:43:55.506371 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2895 17:43:55.510080 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2896 17:43:55.510509
2897 17:43:55.516375 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2898 17:43:55.520203 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2899 17:43:55.520632 [Gating] SW calibration Done
2900 17:43:55.523170 ==
2901 17:43:55.523610 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 17:43:55.529891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 17:43:55.530352 ==
2904 17:43:55.530691 RX Vref Scan: 0
2905 17:43:55.531005
2906 17:43:55.533299 RX Vref 0 -> 0, step: 1
2907 17:43:55.533724
2908 17:43:55.536561 RX Delay -40 -> 252, step: 8
2909 17:43:55.540188 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2910 17:43:55.543285 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2911 17:43:55.546737 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2912 17:43:55.553284 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2913 17:43:55.556513 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2914 17:43:55.560034 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2915 17:43:55.563459 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2916 17:43:55.566653 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2917 17:43:55.570083 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2918 17:43:55.577046 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2919 17:43:55.580481 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2920 17:43:55.583319 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2921 17:43:55.586657 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2922 17:43:55.593483 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2923 17:43:55.596644 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2924 17:43:55.600424 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2925 17:43:55.600853 ==
2926 17:43:55.603723 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 17:43:55.606637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 17:43:55.607070 ==
2929 17:43:55.610374 DQS Delay:
2930 17:43:55.610801 DQS0 = 0, DQS1 = 0
2931 17:43:55.611200 DQM Delay:
2932 17:43:55.613477 DQM0 = 120, DQM1 = 108
2933 17:43:55.613905 DQ Delay:
2934 17:43:55.617280 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2935 17:43:55.620420 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2936 17:43:55.623471 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2937 17:43:55.630233 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2938 17:43:55.630688
2939 17:43:55.631057
2940 17:43:55.631382 ==
2941 17:43:55.634181 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 17:43:55.637316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 17:43:55.637790 ==
2944 17:43:55.638130
2945 17:43:55.638442
2946 17:43:55.640458 TX Vref Scan disable
2947 17:43:55.640952 == TX Byte 0 ==
2948 17:43:55.647407 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2949 17:43:55.650724 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2950 17:43:55.651180 == TX Byte 1 ==
2951 17:43:55.657429 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2952 17:43:55.660379 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2953 17:43:55.660844 ==
2954 17:43:55.664313 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 17:43:55.667094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 17:43:55.667526 ==
2957 17:43:55.680459 TX Vref=22, minBit 1, minWin=25, winSum=419
2958 17:43:55.683649 TX Vref=24, minBit 2, minWin=25, winSum=426
2959 17:43:55.686964 TX Vref=26, minBit 1, minWin=25, winSum=422
2960 17:43:55.690127 TX Vref=28, minBit 0, minWin=26, winSum=430
2961 17:43:55.693252 TX Vref=30, minBit 5, minWin=25, winSum=432
2962 17:43:55.696776 TX Vref=32, minBit 0, minWin=26, winSum=430
2963 17:43:55.703595 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
2964 17:43:55.704127
2965 17:43:55.706809 Final TX Range 1 Vref 28
2966 17:43:55.707250
2967 17:43:55.707622 ==
2968 17:43:55.710067 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 17:43:55.713339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 17:43:55.713769 ==
2971 17:43:55.714105
2972 17:43:55.714418
2973 17:43:55.717002 TX Vref Scan disable
2974 17:43:55.720325 == TX Byte 0 ==
2975 17:43:55.723843 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2976 17:43:55.727386 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2977 17:43:55.730421 == TX Byte 1 ==
2978 17:43:55.733467 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2979 17:43:55.737109 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2980 17:43:55.737677
2981 17:43:55.740206 [DATLAT]
2982 17:43:55.740779 Freq=1200, CH0 RK1
2983 17:43:55.741223
2984 17:43:55.743496 DATLAT Default: 0xd
2985 17:43:55.744074 0, 0xFFFF, sum = 0
2986 17:43:55.747054 1, 0xFFFF, sum = 0
2987 17:43:55.747638 2, 0xFFFF, sum = 0
2988 17:43:55.749980 3, 0xFFFF, sum = 0
2989 17:43:55.750459 4, 0xFFFF, sum = 0
2990 17:43:55.753313 5, 0xFFFF, sum = 0
2991 17:43:55.753906 6, 0xFFFF, sum = 0
2992 17:43:55.756871 7, 0xFFFF, sum = 0
2993 17:43:55.760458 8, 0xFFFF, sum = 0
2994 17:43:55.760984 9, 0xFFFF, sum = 0
2995 17:43:55.763458 10, 0xFFFF, sum = 0
2996 17:43:55.763938 11, 0xFFFF, sum = 0
2997 17:43:55.767228 12, 0x0, sum = 1
2998 17:43:55.767815 13, 0x0, sum = 2
2999 17:43:55.768199 14, 0x0, sum = 3
3000 17:43:55.770188 15, 0x0, sum = 4
3001 17:43:55.770783 best_step = 13
3002 17:43:55.771365
3003 17:43:55.773367 ==
3004 17:43:55.776409 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 17:43:55.780117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 17:43:55.780695 ==
3007 17:43:55.781121 RX Vref Scan: 0
3008 17:43:55.781481
3009 17:43:55.783655 RX Vref 0 -> 0, step: 1
3010 17:43:55.784235
3011 17:43:55.786999 RX Delay -21 -> 252, step: 4
3012 17:43:55.790073 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3013 17:43:55.797272 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3014 17:43:55.800057 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3015 17:43:55.803488 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3016 17:43:55.806715 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3017 17:43:55.809949 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3018 17:43:55.816645 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3019 17:43:55.820164 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3020 17:43:55.823034 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3021 17:43:55.826609 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3022 17:43:55.830094 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3023 17:43:55.833178 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3024 17:43:55.840270 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3025 17:43:55.843616 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3026 17:43:55.846884 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3027 17:43:55.849867 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3028 17:43:55.850347 ==
3029 17:43:55.853100 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 17:43:55.860335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 17:43:55.860895 ==
3032 17:43:55.861354 DQS Delay:
3033 17:43:55.863174 DQS0 = 0, DQS1 = 0
3034 17:43:55.863732 DQM Delay:
3035 17:43:55.864113 DQM0 = 119, DQM1 = 107
3036 17:43:55.867074 DQ Delay:
3037 17:43:55.870571 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3038 17:43:55.873382 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3039 17:43:55.876857 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3040 17:43:55.879934 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =114
3041 17:43:55.880437
3042 17:43:55.880838
3043 17:43:55.886702 [DQSOSCAuto] RK1, (LSB)MR18= 0x8f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
3044 17:43:55.889872 CH0 RK1: MR19=403, MR18=8F0
3045 17:43:55.897039 CH0_RK1: MR19=0x403, MR18=0x8F0, DQSOSC=406, MR23=63, INC=39, DEC=26
3046 17:43:55.900013 [RxdqsGatingPostProcess] freq 1200
3047 17:43:55.906421 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 17:43:55.909833 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 17:43:55.910309 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 17:43:55.913278 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 17:43:55.916613 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 17:43:55.919897 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 17:43:55.923066 best DQS1 dly(2T, 0.5T) = (0, 11)
3054 17:43:55.926497 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 17:43:55.929654 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3056 17:43:55.933065 Pre-setting of DQS Precalculation
3057 17:43:55.940041 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 17:43:55.940556 ==
3059 17:43:55.943355 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 17:43:55.946548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 17:43:55.946971 ==
3062 17:43:55.953728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 17:43:55.956877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3064 17:43:55.966038 [CA 0] Center 37 (7~68) winsize 62
3065 17:43:55.969244 [CA 1] Center 37 (7~68) winsize 62
3066 17:43:55.972957 [CA 2] Center 35 (5~65) winsize 61
3067 17:43:55.975902 [CA 3] Center 34 (4~65) winsize 62
3068 17:43:55.979092 [CA 4] Center 34 (4~65) winsize 62
3069 17:43:55.982576 [CA 5] Center 33 (3~64) winsize 62
3070 17:43:55.983046
3071 17:43:55.986298 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3072 17:43:55.986768
3073 17:43:55.989371 [CATrainingPosCal] consider 1 rank data
3074 17:43:55.992776 u2DelayCellTimex100 = 270/100 ps
3075 17:43:55.996138 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 17:43:55.999155 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 17:43:56.005836 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3078 17:43:56.009291 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3079 17:43:56.012492 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3080 17:43:56.015825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3081 17:43:56.016293
3082 17:43:56.019922 CA PerBit enable=1, Macro0, CA PI delay=33
3083 17:43:56.020479
3084 17:43:56.022714 [CBTSetCACLKResult] CA Dly = 33
3085 17:43:56.023183 CS Dly: 5 (0~36)
3086 17:43:56.026173 ==
3087 17:43:56.026735 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 17:43:56.032341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 17:43:56.032813 ==
3090 17:43:56.035844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 17:43:56.042415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3092 17:43:56.052056 [CA 0] Center 38 (8~68) winsize 61
3093 17:43:56.055174 [CA 1] Center 38 (7~69) winsize 63
3094 17:43:56.058251 [CA 2] Center 35 (5~66) winsize 62
3095 17:43:56.061598 [CA 3] Center 35 (5~65) winsize 61
3096 17:43:56.064925 [CA 4] Center 35 (5~65) winsize 61
3097 17:43:56.068120 [CA 5] Center 34 (4~64) winsize 61
3098 17:43:56.068586
3099 17:43:56.071864 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3100 17:43:56.072475
3101 17:43:56.075240 [CATrainingPosCal] consider 2 rank data
3102 17:43:56.078652 u2DelayCellTimex100 = 270/100 ps
3103 17:43:56.082275 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3104 17:43:56.084876 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3105 17:43:56.091908 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3106 17:43:56.095282 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3107 17:43:56.098327 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3108 17:43:56.101890 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3109 17:43:56.102357
3110 17:43:56.105365 CA PerBit enable=1, Macro0, CA PI delay=34
3111 17:43:56.105834
3112 17:43:56.108567 [CBTSetCACLKResult] CA Dly = 34
3113 17:43:56.109160 CS Dly: 6 (0~39)
3114 17:43:56.109540
3115 17:43:56.111809 ----->DramcWriteLeveling(PI) begin...
3116 17:43:56.112493 ==
3117 17:43:56.115313 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 17:43:56.121539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 17:43:56.122049 ==
3120 17:43:56.125225 Write leveling (Byte 0): 25 => 25
3121 17:43:56.128771 Write leveling (Byte 1): 28 => 28
3122 17:43:56.129280 DramcWriteLeveling(PI) end<-----
3123 17:43:56.132096
3124 17:43:56.132559 ==
3125 17:43:56.135254 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 17:43:56.138722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 17:43:56.139205 ==
3128 17:43:56.141880 [Gating] SW mode calibration
3129 17:43:56.148902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 17:43:56.152056 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 17:43:56.158733 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 17:43:56.161743 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 17:43:56.165184 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 17:43:56.172264 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 17:43:56.175033 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 17:43:56.178394 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3137 17:43:56.184870 0 15 24 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (0 0)
3138 17:43:56.188216 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 17:43:56.191409 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 17:43:56.198265 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 17:43:56.201522 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 17:43:56.205081 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 17:43:56.211669 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 17:43:56.214974 1 0 20 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
3145 17:43:56.218187 1 0 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3146 17:43:56.224924 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 17:43:56.228516 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 17:43:56.231619 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 17:43:56.234756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 17:43:56.241817 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 17:43:56.244923 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 17:43:56.248530 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 17:43:56.255012 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3154 17:43:56.258425 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 17:43:56.261534 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 17:43:56.268202 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 17:43:56.272181 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 17:43:56.275110 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 17:43:56.281570 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 17:43:56.284796 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 17:43:56.288304 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 17:43:56.295542 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 17:43:56.298545 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 17:43:56.301526 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 17:43:56.308159 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 17:43:56.312060 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 17:43:56.314723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 17:43:56.321541 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3169 17:43:56.325090 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3170 17:43:56.328228 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3171 17:43:56.331360 Total UI for P1: 0, mck2ui 16
3172 17:43:56.334666 best dqsien dly found for B0: ( 1, 3, 22)
3173 17:43:56.337989 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 17:43:56.341577 Total UI for P1: 0, mck2ui 16
3175 17:43:56.344901 best dqsien dly found for B1: ( 1, 3, 26)
3176 17:43:56.347959 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3177 17:43:56.354798 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3178 17:43:56.355222
3179 17:43:56.358249 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3180 17:43:56.361551 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3181 17:43:56.364857 [Gating] SW calibration Done
3182 17:43:56.365317 ==
3183 17:43:56.368358 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 17:43:56.371527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 17:43:56.372054 ==
3186 17:43:56.374733 RX Vref Scan: 0
3187 17:43:56.375153
3188 17:43:56.375486 RX Vref 0 -> 0, step: 1
3189 17:43:56.375799
3190 17:43:56.378335 RX Delay -40 -> 252, step: 8
3191 17:43:56.381210 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 17:43:56.387969 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 17:43:56.391119 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3194 17:43:56.394596 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3195 17:43:56.398203 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3196 17:43:56.401706 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3197 17:43:56.404825 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3198 17:43:56.411655 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3199 17:43:56.414813 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3200 17:43:56.418042 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3201 17:43:56.421311 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 17:43:56.424921 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3203 17:43:56.431736 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 17:43:56.434744 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3205 17:43:56.438396 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3206 17:43:56.441326 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3207 17:43:56.441747 ==
3208 17:43:56.444851 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 17:43:56.448143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 17:43:56.451720 ==
3211 17:43:56.452139 DQS Delay:
3212 17:43:56.452554 DQS0 = 0, DQS1 = 0
3213 17:43:56.454655 DQM Delay:
3214 17:43:56.455074 DQM0 = 119, DQM1 = 112
3215 17:43:56.457924 DQ Delay:
3216 17:43:56.461629 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3217 17:43:56.464904 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3218 17:43:56.468027 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3219 17:43:56.471706 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3220 17:43:56.472236
3221 17:43:56.472568
3222 17:43:56.472876 ==
3223 17:43:56.474725 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 17:43:56.478162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 17:43:56.478588 ==
3226 17:43:56.478921
3227 17:43:56.481188
3228 17:43:56.481606 TX Vref Scan disable
3229 17:43:56.484788 == TX Byte 0 ==
3230 17:43:56.487921 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3231 17:43:56.491529 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3232 17:43:56.494410 == TX Byte 1 ==
3233 17:43:56.497856 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3234 17:43:56.501567 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3235 17:43:56.502103 ==
3236 17:43:56.504618 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 17:43:56.511662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 17:43:56.512203 ==
3239 17:43:56.521891 TX Vref=22, minBit 11, minWin=24, winSum=405
3240 17:43:56.524844 TX Vref=24, minBit 3, minWin=25, winSum=411
3241 17:43:56.528274 TX Vref=26, minBit 8, minWin=25, winSum=415
3242 17:43:56.532017 TX Vref=28, minBit 10, minWin=25, winSum=419
3243 17:43:56.534777 TX Vref=30, minBit 10, minWin=25, winSum=424
3244 17:43:56.541472 TX Vref=32, minBit 9, minWin=25, winSum=423
3245 17:43:56.544950 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 30
3246 17:43:56.545402
3247 17:43:56.548436 Final TX Range 1 Vref 30
3248 17:43:56.549022
3249 17:43:56.549400 ==
3250 17:43:56.552005 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 17:43:56.554807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 17:43:56.558374 ==
3253 17:43:56.558793
3254 17:43:56.559122
3255 17:43:56.559426 TX Vref Scan disable
3256 17:43:56.561451 == TX Byte 0 ==
3257 17:43:56.565046 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3258 17:43:56.568049 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3259 17:43:56.571657 == TX Byte 1 ==
3260 17:43:56.575085 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3261 17:43:56.578340 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3262 17:43:56.581902
3263 17:43:56.582442 [DATLAT]
3264 17:43:56.582785 Freq=1200, CH1 RK0
3265 17:43:56.583097
3266 17:43:56.584893 DATLAT Default: 0xd
3267 17:43:56.585398 0, 0xFFFF, sum = 0
3268 17:43:56.588109 1, 0xFFFF, sum = 0
3269 17:43:56.588582 2, 0xFFFF, sum = 0
3270 17:43:56.592125 3, 0xFFFF, sum = 0
3271 17:43:56.592683 4, 0xFFFF, sum = 0
3272 17:43:56.595272 5, 0xFFFF, sum = 0
3273 17:43:56.598592 6, 0xFFFF, sum = 0
3274 17:43:56.599049 7, 0xFFFF, sum = 0
3275 17:43:56.599391 8, 0xFFFF, sum = 0
3276 17:43:56.602438 9, 0xFFFF, sum = 0
3277 17:43:56.605539 10, 0xFFFF, sum = 0
3278 17:43:56.606089 11, 0xFFFF, sum = 0
3279 17:43:56.608859 12, 0x0, sum = 1
3280 17:43:56.609448 13, 0x0, sum = 2
3281 17:43:56.609800 14, 0x0, sum = 3
3282 17:43:56.612117 15, 0x0, sum = 4
3283 17:43:56.612553 best_step = 13
3284 17:43:56.612886
3285 17:43:56.613231 ==
3286 17:43:56.615645 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 17:43:56.621965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 17:43:56.622509 ==
3289 17:43:56.622887 RX Vref Scan: 1
3290 17:43:56.623234
3291 17:43:56.625369 Set Vref Range= 32 -> 127
3292 17:43:56.625843
3293 17:43:56.628766 RX Vref 32 -> 127, step: 1
3294 17:43:56.629268
3295 17:43:56.631775 RX Delay -13 -> 252, step: 4
3296 17:43:56.632189
3297 17:43:56.635096 Set Vref, RX VrefLevel [Byte0]: 32
3298 17:43:56.638455 [Byte1]: 32
3299 17:43:56.638981
3300 17:43:56.641915 Set Vref, RX VrefLevel [Byte0]: 33
3301 17:43:56.645167 [Byte1]: 33
3302 17:43:56.645707
3303 17:43:56.648304 Set Vref, RX VrefLevel [Byte0]: 34
3304 17:43:56.651872 [Byte1]: 34
3305 17:43:56.656168
3306 17:43:56.656681 Set Vref, RX VrefLevel [Byte0]: 35
3307 17:43:56.659302 [Byte1]: 35
3308 17:43:56.663637
3309 17:43:56.664046 Set Vref, RX VrefLevel [Byte0]: 36
3310 17:43:56.666912 [Byte1]: 36
3311 17:43:56.671941
3312 17:43:56.672435 Set Vref, RX VrefLevel [Byte0]: 37
3313 17:43:56.675216 [Byte1]: 37
3314 17:43:56.679463
3315 17:43:56.680005 Set Vref, RX VrefLevel [Byte0]: 38
3316 17:43:56.683085 [Byte1]: 38
3317 17:43:56.687377
3318 17:43:56.687811 Set Vref, RX VrefLevel [Byte0]: 39
3319 17:43:56.691098 [Byte1]: 39
3320 17:43:56.695547
3321 17:43:56.696058 Set Vref, RX VrefLevel [Byte0]: 40
3322 17:43:56.698578 [Byte1]: 40
3323 17:43:56.703337
3324 17:43:56.703745 Set Vref, RX VrefLevel [Byte0]: 41
3325 17:43:56.706401 [Byte1]: 41
3326 17:43:56.711505
3327 17:43:56.712046 Set Vref, RX VrefLevel [Byte0]: 42
3328 17:43:56.714543 [Byte1]: 42
3329 17:43:56.719145
3330 17:43:56.719667 Set Vref, RX VrefLevel [Byte0]: 43
3331 17:43:56.722560 [Byte1]: 43
3332 17:43:56.727182
3333 17:43:56.727590 Set Vref, RX VrefLevel [Byte0]: 44
3334 17:43:56.730399 [Byte1]: 44
3335 17:43:56.734769
3336 17:43:56.735257 Set Vref, RX VrefLevel [Byte0]: 45
3337 17:43:56.737987 [Byte1]: 45
3338 17:43:56.742892
3339 17:43:56.743373 Set Vref, RX VrefLevel [Byte0]: 46
3340 17:43:56.746153 [Byte1]: 46
3341 17:43:56.750569
3342 17:43:56.750983 Set Vref, RX VrefLevel [Byte0]: 47
3343 17:43:56.753983 [Byte1]: 47
3344 17:43:56.758525
3345 17:43:56.759006 Set Vref, RX VrefLevel [Byte0]: 48
3346 17:43:56.761700 [Byte1]: 48
3347 17:43:56.766320
3348 17:43:56.766806 Set Vref, RX VrefLevel [Byte0]: 49
3349 17:43:56.769544 [Byte1]: 49
3350 17:43:56.774390
3351 17:43:56.774900 Set Vref, RX VrefLevel [Byte0]: 50
3352 17:43:56.777807 [Byte1]: 50
3353 17:43:56.782300
3354 17:43:56.782873 Set Vref, RX VrefLevel [Byte0]: 51
3355 17:43:56.785539 [Byte1]: 51
3356 17:43:56.790162
3357 17:43:56.790685 Set Vref, RX VrefLevel [Byte0]: 52
3358 17:43:56.793208 [Byte1]: 52
3359 17:43:56.797738
3360 17:43:56.798164 Set Vref, RX VrefLevel [Byte0]: 53
3361 17:43:56.801580 [Byte1]: 53
3362 17:43:56.805697
3363 17:43:56.806232 Set Vref, RX VrefLevel [Byte0]: 54
3364 17:43:56.809223 [Byte1]: 54
3365 17:43:56.813611
3366 17:43:56.814032 Set Vref, RX VrefLevel [Byte0]: 55
3367 17:43:56.816878 [Byte1]: 55
3368 17:43:56.821766
3369 17:43:56.822333 Set Vref, RX VrefLevel [Byte0]: 56
3370 17:43:56.825051 [Byte1]: 56
3371 17:43:56.829503
3372 17:43:56.830078 Set Vref, RX VrefLevel [Byte0]: 57
3373 17:43:56.832692 [Byte1]: 57
3374 17:43:56.837483
3375 17:43:56.837901 Set Vref, RX VrefLevel [Byte0]: 58
3376 17:43:56.840870 [Byte1]: 58
3377 17:43:56.845471
3378 17:43:56.846005 Set Vref, RX VrefLevel [Byte0]: 59
3379 17:43:56.848398 [Byte1]: 59
3380 17:43:56.853045
3381 17:43:56.853462 Set Vref, RX VrefLevel [Byte0]: 60
3382 17:43:56.856220 [Byte1]: 60
3383 17:43:56.861169
3384 17:43:56.861657 Set Vref, RX VrefLevel [Byte0]: 61
3385 17:43:56.864417 [Byte1]: 61
3386 17:43:56.869093
3387 17:43:56.869643 Set Vref, RX VrefLevel [Byte0]: 62
3388 17:43:56.872171 [Byte1]: 62
3389 17:43:56.876515
3390 17:43:56.876968 Set Vref, RX VrefLevel [Byte0]: 63
3391 17:43:56.880284 [Byte1]: 63
3392 17:43:56.884802
3393 17:43:56.885510 Set Vref, RX VrefLevel [Byte0]: 64
3394 17:43:56.888310 [Byte1]: 64
3395 17:43:56.892765
3396 17:43:56.893406 Set Vref, RX VrefLevel [Byte0]: 65
3397 17:43:56.896066 [Byte1]: 65
3398 17:43:56.900502
3399 17:43:56.901060 Set Vref, RX VrefLevel [Byte0]: 66
3400 17:43:56.903561 [Byte1]: 66
3401 17:43:56.908478
3402 17:43:56.909051 Set Vref, RX VrefLevel [Byte0]: 67
3403 17:43:56.911966 [Byte1]: 67
3404 17:43:56.916494
3405 17:43:56.917137 Final RX Vref Byte 0 = 53 to rank0
3406 17:43:56.919519 Final RX Vref Byte 1 = 57 to rank0
3407 17:43:56.922835 Final RX Vref Byte 0 = 53 to rank1
3408 17:43:56.926344 Final RX Vref Byte 1 = 57 to rank1==
3409 17:43:56.929546 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 17:43:56.933143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 17:43:56.936409 ==
3412 17:43:56.936831 DQS Delay:
3413 17:43:56.937212 DQS0 = 0, DQS1 = 0
3414 17:43:56.939292 DQM Delay:
3415 17:43:56.939776 DQM0 = 119, DQM1 = 113
3416 17:43:56.942975 DQ Delay:
3417 17:43:56.946160 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3418 17:43:56.949691 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3419 17:43:56.953120 DQ8 =102, DQ9 =100, DQ10 =118, DQ11 =106
3420 17:43:56.956440 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =120
3421 17:43:56.956996
3422 17:43:56.957363
3423 17:43:56.963032 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3424 17:43:56.966190 CH1 RK0: MR19=404, MR18=215
3425 17:43:56.973266 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3426 17:43:56.973829
3427 17:43:56.976456 ----->DramcWriteLeveling(PI) begin...
3428 17:43:56.976972 ==
3429 17:43:56.979486 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 17:43:56.983073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 17:43:56.983503 ==
3432 17:43:56.986121 Write leveling (Byte 0): 25 => 25
3433 17:43:56.989615 Write leveling (Byte 1): 29 => 29
3434 17:43:56.992802 DramcWriteLeveling(PI) end<-----
3435 17:43:56.993331
3436 17:43:56.993671 ==
3437 17:43:56.996303 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 17:43:57.003038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 17:43:57.003539 ==
3440 17:43:57.003882 [Gating] SW mode calibration
3441 17:43:57.012862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 17:43:57.016363 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 17:43:57.019293 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 17:43:57.026462 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 17:43:57.029692 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 17:43:57.033324 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 17:43:57.039517 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 17:43:57.043054 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 17:43:57.046214 0 15 24 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 1)
3450 17:43:57.053255 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (0 1)
3451 17:43:57.056328 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 17:43:57.059836 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 17:43:57.066413 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 17:43:57.069773 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 17:43:57.072736 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 17:43:57.079862 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 17:43:57.083297 1 0 24 | B1->B0 | 3f3f 2c2c | 0 0 | (0 0) (0 0)
3458 17:43:57.086126 1 0 28 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (1 1)
3459 17:43:57.089534 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 17:43:57.096360 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 17:43:57.099958 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 17:43:57.103024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 17:43:57.109453 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 17:43:57.113090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 17:43:57.116155 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 17:43:57.122697 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3467 17:43:57.126690 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 17:43:57.129355 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 17:43:57.135946 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 17:43:57.139987 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 17:43:57.142738 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 17:43:57.149357 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 17:43:57.152608 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 17:43:57.156383 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 17:43:57.162701 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 17:43:57.165892 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 17:43:57.169407 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 17:43:57.176082 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 17:43:57.179093 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 17:43:57.182565 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 17:43:57.189102 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 17:43:57.192504 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 17:43:57.195764 Total UI for P1: 0, mck2ui 16
3484 17:43:57.199014 best dqsien dly found for B0: ( 1, 3, 24)
3485 17:43:57.202572 Total UI for P1: 0, mck2ui 16
3486 17:43:57.206066 best dqsien dly found for B1: ( 1, 3, 24)
3487 17:43:57.209054 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3488 17:43:57.212289 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3489 17:43:57.212764
3490 17:43:57.215740 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3491 17:43:57.219077 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3492 17:43:57.222107 [Gating] SW calibration Done
3493 17:43:57.222538 ==
3494 17:43:57.225633 Dram Type= 6, Freq= 0, CH_1, rank 1
3495 17:43:57.228786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 17:43:57.232292 ==
3497 17:43:57.232864 RX Vref Scan: 0
3498 17:43:57.233314
3499 17:43:57.235322 RX Vref 0 -> 0, step: 1
3500 17:43:57.235840
3501 17:43:57.238522 RX Delay -40 -> 252, step: 8
3502 17:43:57.242112 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3503 17:43:57.245394 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3504 17:43:57.248965 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3505 17:43:57.252174 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3506 17:43:57.258459 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3507 17:43:57.262019 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3508 17:43:57.265101 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3509 17:43:57.268483 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3510 17:43:57.271873 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3511 17:43:57.278494 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3512 17:43:57.281706 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3513 17:43:57.285043 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3514 17:43:57.289015 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3515 17:43:57.291728 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3516 17:43:57.298507 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3517 17:43:57.301838 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3518 17:43:57.302413 ==
3519 17:43:57.305033 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 17:43:57.308528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 17:43:57.309044 ==
3522 17:43:57.311600 DQS Delay:
3523 17:43:57.312076 DQS0 = 0, DQS1 = 0
3524 17:43:57.312414 DQM Delay:
3525 17:43:57.315396 DQM0 = 120, DQM1 = 112
3526 17:43:57.315928 DQ Delay:
3527 17:43:57.318391 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3528 17:43:57.321799 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =119
3529 17:43:57.325387 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3530 17:43:57.331772 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3531 17:43:57.332338
3532 17:43:57.332711
3533 17:43:57.333109 ==
3534 17:43:57.335367 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 17:43:57.338241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 17:43:57.338715 ==
3537 17:43:57.339084
3538 17:43:57.339431
3539 17:43:57.341852 TX Vref Scan disable
3540 17:43:57.342321 == TX Byte 0 ==
3541 17:43:57.348470 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3542 17:43:57.351910 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3543 17:43:57.352458 == TX Byte 1 ==
3544 17:43:57.358001 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3545 17:43:57.361197 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3546 17:43:57.361668 ==
3547 17:43:57.365079 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 17:43:57.368475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 17:43:57.369106 ==
3550 17:43:57.381091 TX Vref=22, minBit 1, minWin=25, winSum=417
3551 17:43:57.384388 TX Vref=24, minBit 1, minWin=26, winSum=421
3552 17:43:57.388059 TX Vref=26, minBit 1, minWin=25, winSum=423
3553 17:43:57.390769 TX Vref=28, minBit 1, minWin=26, winSum=426
3554 17:43:57.394384 TX Vref=30, minBit 1, minWin=26, winSum=428
3555 17:43:57.400798 TX Vref=32, minBit 1, minWin=26, winSum=428
3556 17:43:57.403898 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3557 17:43:57.404393
3558 17:43:57.407714 Final TX Range 1 Vref 30
3559 17:43:57.408293
3560 17:43:57.408670 ==
3561 17:43:57.410664 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 17:43:57.414046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 17:43:57.414475 ==
3564 17:43:57.417357
3565 17:43:57.417778
3566 17:43:57.418114 TX Vref Scan disable
3567 17:43:57.420926 == TX Byte 0 ==
3568 17:43:57.423929 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3569 17:43:57.431102 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3570 17:43:57.431679 == TX Byte 1 ==
3571 17:43:57.433876 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 17:43:57.440571 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 17:43:57.441141
3574 17:43:57.441517 [DATLAT]
3575 17:43:57.441865 Freq=1200, CH1 RK1
3576 17:43:57.442202
3577 17:43:57.443683 DATLAT Default: 0xd
3578 17:43:57.444147 0, 0xFFFF, sum = 0
3579 17:43:57.447238 1, 0xFFFF, sum = 0
3580 17:43:57.450563 2, 0xFFFF, sum = 0
3581 17:43:57.450987 3, 0xFFFF, sum = 0
3582 17:43:57.453671 4, 0xFFFF, sum = 0
3583 17:43:57.454115 5, 0xFFFF, sum = 0
3584 17:43:57.457277 6, 0xFFFF, sum = 0
3585 17:43:57.457702 7, 0xFFFF, sum = 0
3586 17:43:57.460722 8, 0xFFFF, sum = 0
3587 17:43:57.461289 9, 0xFFFF, sum = 0
3588 17:43:57.463719 10, 0xFFFF, sum = 0
3589 17:43:57.464146 11, 0xFFFF, sum = 0
3590 17:43:57.466874 12, 0x0, sum = 1
3591 17:43:57.467322 13, 0x0, sum = 2
3592 17:43:57.470267 14, 0x0, sum = 3
3593 17:43:57.470697 15, 0x0, sum = 4
3594 17:43:57.473743 best_step = 13
3595 17:43:57.474170
3596 17:43:57.474508 ==
3597 17:43:57.476872 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 17:43:57.480465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 17:43:57.480900 ==
3600 17:43:57.481276 RX Vref Scan: 0
3601 17:43:57.483776
3602 17:43:57.484310 RX Vref 0 -> 0, step: 1
3603 17:43:57.484655
3604 17:43:57.486710 RX Delay -13 -> 252, step: 4
3605 17:43:57.490265 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3606 17:43:57.496875 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3607 17:43:57.500017 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3608 17:43:57.503450 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3609 17:43:57.506945 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3610 17:43:57.510187 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3611 17:43:57.516848 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3612 17:43:57.520318 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3613 17:43:57.523533 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3614 17:43:57.527044 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3615 17:43:57.530289 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3616 17:43:57.537077 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3617 17:43:57.540305 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3618 17:43:57.543534 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3619 17:43:57.547088 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3620 17:43:57.550185 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3621 17:43:57.553434 ==
3622 17:43:57.557076 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 17:43:57.560381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 17:43:57.560905 ==
3625 17:43:57.561299 DQS Delay:
3626 17:43:57.563472 DQS0 = 0, DQS1 = 0
3627 17:43:57.563990 DQM Delay:
3628 17:43:57.566517 DQM0 = 119, DQM1 = 113
3629 17:43:57.566948 DQ Delay:
3630 17:43:57.569975 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3631 17:43:57.573245 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3632 17:43:57.576820 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3633 17:43:57.579929 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =124
3634 17:43:57.580359
3635 17:43:57.580694
3636 17:43:57.589889 [DQSOSCAuto] RK1, (LSB)MR18= 0x6eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3637 17:43:57.593517 CH1 RK1: MR19=403, MR18=6EB
3638 17:43:57.596781 CH1_RK1: MR19=0x403, MR18=0x6EB, DQSOSC=407, MR23=63, INC=39, DEC=26
3639 17:43:57.599805 [RxdqsGatingPostProcess] freq 1200
3640 17:43:57.606658 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3641 17:43:57.609712 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 17:43:57.613182 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 17:43:57.616469 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 17:43:57.619796 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 17:43:57.623092 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 17:43:57.626607 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 17:43:57.629502 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 17:43:57.632914 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 17:43:57.633424 Pre-setting of DQS Precalculation
3650 17:43:57.639782 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3651 17:43:57.646415 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3652 17:43:57.652671 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3653 17:43:57.653085
3654 17:43:57.653410
3655 17:43:57.656582 [Calibration Summary] 2400 Mbps
3656 17:43:57.659719 CH 0, Rank 0
3657 17:43:57.660145 SW Impedance : PASS
3658 17:43:57.662953 DUTY Scan : NO K
3659 17:43:57.666594 ZQ Calibration : PASS
3660 17:43:57.667120 Jitter Meter : NO K
3661 17:43:57.669918 CBT Training : PASS
3662 17:43:57.673241 Write leveling : PASS
3663 17:43:57.673732 RX DQS gating : PASS
3664 17:43:57.676155 RX DQ/DQS(RDDQC) : PASS
3665 17:43:57.676578 TX DQ/DQS : PASS
3666 17:43:57.679388 RX DATLAT : PASS
3667 17:43:57.683013 RX DQ/DQS(Engine): PASS
3668 17:43:57.683439 TX OE : NO K
3669 17:43:57.686100 All Pass.
3670 17:43:57.686522
3671 17:43:57.686856 CH 0, Rank 1
3672 17:43:57.689655 SW Impedance : PASS
3673 17:43:57.690076 DUTY Scan : NO K
3674 17:43:57.692769 ZQ Calibration : PASS
3675 17:43:57.696358 Jitter Meter : NO K
3676 17:43:57.696778 CBT Training : PASS
3677 17:43:57.699469 Write leveling : PASS
3678 17:43:57.702681 RX DQS gating : PASS
3679 17:43:57.703278 RX DQ/DQS(RDDQC) : PASS
3680 17:43:57.706179 TX DQ/DQS : PASS
3681 17:43:57.709455 RX DATLAT : PASS
3682 17:43:57.709980 RX DQ/DQS(Engine): PASS
3683 17:43:57.712748 TX OE : NO K
3684 17:43:57.713261 All Pass.
3685 17:43:57.713595
3686 17:43:57.716212 CH 1, Rank 0
3687 17:43:57.716647 SW Impedance : PASS
3688 17:43:57.719088 DUTY Scan : NO K
3689 17:43:57.722950 ZQ Calibration : PASS
3690 17:43:57.723473 Jitter Meter : NO K
3691 17:43:57.725745 CBT Training : PASS
3692 17:43:57.729577 Write leveling : PASS
3693 17:43:57.729999 RX DQS gating : PASS
3694 17:43:57.732313 RX DQ/DQS(RDDQC) : PASS
3695 17:43:57.735775 TX DQ/DQS : PASS
3696 17:43:57.736199 RX DATLAT : PASS
3697 17:43:57.738991 RX DQ/DQS(Engine): PASS
3698 17:43:57.739605 TX OE : NO K
3699 17:43:57.742329 All Pass.
3700 17:43:57.742749
3701 17:43:57.743078 CH 1, Rank 1
3702 17:43:57.745613 SW Impedance : PASS
3703 17:43:57.746034 DUTY Scan : NO K
3704 17:43:57.749297 ZQ Calibration : PASS
3705 17:43:57.752221 Jitter Meter : NO K
3706 17:43:57.752643 CBT Training : PASS
3707 17:43:57.755640 Write leveling : PASS
3708 17:43:57.759094 RX DQS gating : PASS
3709 17:43:57.759516 RX DQ/DQS(RDDQC) : PASS
3710 17:43:57.762833 TX DQ/DQS : PASS
3711 17:43:57.765903 RX DATLAT : PASS
3712 17:43:57.766322 RX DQ/DQS(Engine): PASS
3713 17:43:57.769014 TX OE : NO K
3714 17:43:57.769437 All Pass.
3715 17:43:57.769766
3716 17:43:57.772311 DramC Write-DBI off
3717 17:43:57.775633 PER_BANK_REFRESH: Hybrid Mode
3718 17:43:57.776123 TX_TRACKING: ON
3719 17:43:57.785959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3720 17:43:57.789116 [FAST_K] Save calibration result to emmc
3721 17:43:57.792422 dramc_set_vcore_voltage set vcore to 650000
3722 17:43:57.795506 Read voltage for 600, 5
3723 17:43:57.796006 Vio18 = 0
3724 17:43:57.796458 Vcore = 650000
3725 17:43:57.799141 Vdram = 0
3726 17:43:57.799654 Vddq = 0
3727 17:43:57.799985 Vmddr = 0
3728 17:43:57.805364 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3729 17:43:57.808991 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3730 17:43:57.812147 MEM_TYPE=3, freq_sel=19
3731 17:43:57.815401 sv_algorithm_assistance_LP4_1600
3732 17:43:57.818498 ============ PULL DRAM RESETB DOWN ============
3733 17:43:57.821808 ========== PULL DRAM RESETB DOWN end =========
3734 17:43:57.828856 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3735 17:43:57.831899 ===================================
3736 17:43:57.835411 LPDDR4 DRAM CONFIGURATION
3737 17:43:57.838684 ===================================
3738 17:43:57.839319 EX_ROW_EN[0] = 0x0
3739 17:43:57.841867 EX_ROW_EN[1] = 0x0
3740 17:43:57.842381 LP4Y_EN = 0x0
3741 17:43:57.845327 WORK_FSP = 0x0
3742 17:43:57.845983 WL = 0x2
3743 17:43:57.848537 RL = 0x2
3744 17:43:57.849044 BL = 0x2
3745 17:43:57.852040 RPST = 0x0
3746 17:43:57.852632 RD_PRE = 0x0
3747 17:43:57.855222 WR_PRE = 0x1
3748 17:43:57.855668 WR_PST = 0x0
3749 17:43:57.858437 DBI_WR = 0x0
3750 17:43:57.859025 DBI_RD = 0x0
3751 17:43:57.862042 OTF = 0x1
3752 17:43:57.865203 ===================================
3753 17:43:57.868812 ===================================
3754 17:43:57.869468 ANA top config
3755 17:43:57.872091 ===================================
3756 17:43:57.875039 DLL_ASYNC_EN = 0
3757 17:43:57.878325 ALL_SLAVE_EN = 1
3758 17:43:57.881591 NEW_RANK_MODE = 1
3759 17:43:57.882057 DLL_IDLE_MODE = 1
3760 17:43:57.885349 LP45_APHY_COMB_EN = 1
3761 17:43:57.888316 TX_ODT_DIS = 1
3762 17:43:57.891530 NEW_8X_MODE = 1
3763 17:43:57.895024 ===================================
3764 17:43:57.898359 ===================================
3765 17:43:57.901883 data_rate = 1200
3766 17:43:57.902586 CKR = 1
3767 17:43:57.905106 DQ_P2S_RATIO = 8
3768 17:43:57.908663 ===================================
3769 17:43:57.911841 CA_P2S_RATIO = 8
3770 17:43:57.915187 DQ_CA_OPEN = 0
3771 17:43:57.918630 DQ_SEMI_OPEN = 0
3772 17:43:57.921576 CA_SEMI_OPEN = 0
3773 17:43:57.922000 CA_FULL_RATE = 0
3774 17:43:57.925135 DQ_CKDIV4_EN = 1
3775 17:43:57.928537 CA_CKDIV4_EN = 1
3776 17:43:57.931836 CA_PREDIV_EN = 0
3777 17:43:57.935160 PH8_DLY = 0
3778 17:43:57.938388 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3779 17:43:57.938819 DQ_AAMCK_DIV = 4
3780 17:43:57.941607 CA_AAMCK_DIV = 4
3781 17:43:57.945094 CA_ADMCK_DIV = 4
3782 17:43:57.948175 DQ_TRACK_CA_EN = 0
3783 17:43:57.951504 CA_PICK = 600
3784 17:43:57.954672 CA_MCKIO = 600
3785 17:43:57.955138 MCKIO_SEMI = 0
3786 17:43:57.957947 PLL_FREQ = 2288
3787 17:43:57.961535 DQ_UI_PI_RATIO = 32
3788 17:43:57.964846 CA_UI_PI_RATIO = 0
3789 17:43:57.968345 ===================================
3790 17:43:57.971523 ===================================
3791 17:43:57.974740 memory_type:LPDDR4
3792 17:43:57.975270 GP_NUM : 10
3793 17:43:57.978201 SRAM_EN : 1
3794 17:43:57.981192 MD32_EN : 0
3795 17:43:57.984842 ===================================
3796 17:43:57.985394 [ANA_INIT] >>>>>>>>>>>>>>
3797 17:43:57.987876 <<<<<< [CONFIGURE PHASE]: ANA_TX
3798 17:43:57.991446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3799 17:43:57.994730 ===================================
3800 17:43:57.998000 data_rate = 1200,PCW = 0X5800
3801 17:43:58.001239 ===================================
3802 17:43:58.004683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3803 17:43:58.011415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 17:43:58.014197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 17:43:58.021256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3806 17:43:58.024309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3807 17:43:58.028063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3808 17:43:58.030755 [ANA_INIT] flow start
3809 17:43:58.031225 [ANA_INIT] PLL >>>>>>>>
3810 17:43:58.034320 [ANA_INIT] PLL <<<<<<<<
3811 17:43:58.037624 [ANA_INIT] MIDPI >>>>>>>>
3812 17:43:58.038229 [ANA_INIT] MIDPI <<<<<<<<
3813 17:43:58.041196 [ANA_INIT] DLL >>>>>>>>
3814 17:43:58.044412 [ANA_INIT] flow end
3815 17:43:58.048095 ============ LP4 DIFF to SE enter ============
3816 17:43:58.051040 ============ LP4 DIFF to SE exit ============
3817 17:43:58.053898 [ANA_INIT] <<<<<<<<<<<<<
3818 17:43:58.057199 [Flow] Enable top DCM control >>>>>
3819 17:43:58.060669 [Flow] Enable top DCM control <<<<<
3820 17:43:58.063890 Enable DLL master slave shuffle
3821 17:43:58.067540 ==============================================================
3822 17:43:58.070647 Gating Mode config
3823 17:43:58.077457 ==============================================================
3824 17:43:58.078031 Config description:
3825 17:43:58.087025 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3826 17:43:58.093993 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3827 17:43:58.100818 SELPH_MODE 0: By rank 1: By Phase
3828 17:43:58.104261 ==============================================================
3829 17:43:58.107264 GAT_TRACK_EN = 1
3830 17:43:58.110483 RX_GATING_MODE = 2
3831 17:43:58.113882 RX_GATING_TRACK_MODE = 2
3832 17:43:58.117014 SELPH_MODE = 1
3833 17:43:58.120532 PICG_EARLY_EN = 1
3834 17:43:58.123679 VALID_LAT_VALUE = 1
3835 17:43:58.127240 ==============================================================
3836 17:43:58.130209 Enter into Gating configuration >>>>
3837 17:43:58.133599 Exit from Gating configuration <<<<
3838 17:43:58.136460 Enter into DVFS_PRE_config >>>>>
3839 17:43:58.149781 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3840 17:43:58.153447 Exit from DVFS_PRE_config <<<<<
3841 17:43:58.156472 Enter into PICG configuration >>>>
3842 17:43:58.156890 Exit from PICG configuration <<<<
3843 17:43:58.159686 [RX_INPUT] configuration >>>>>
3844 17:43:58.163247 [RX_INPUT] configuration <<<<<
3845 17:43:58.169770 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3846 17:43:58.173413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3847 17:43:58.180238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 17:43:58.186583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 17:43:58.192851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 17:43:58.200057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 17:43:58.203487 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3852 17:43:58.206901 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3853 17:43:58.209637 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3854 17:43:58.216497 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3855 17:43:58.219632 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3856 17:43:58.223053 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 17:43:58.226212 ===================================
3858 17:43:58.229524 LPDDR4 DRAM CONFIGURATION
3859 17:43:58.233225 ===================================
3860 17:43:58.235968 EX_ROW_EN[0] = 0x0
3861 17:43:58.236433 EX_ROW_EN[1] = 0x0
3862 17:43:58.239265 LP4Y_EN = 0x0
3863 17:43:58.239731 WORK_FSP = 0x0
3864 17:43:58.242612 WL = 0x2
3865 17:43:58.243075 RL = 0x2
3866 17:43:58.245753 BL = 0x2
3867 17:43:58.246215 RPST = 0x0
3868 17:43:58.249280 RD_PRE = 0x0
3869 17:43:58.249742 WR_PRE = 0x1
3870 17:43:58.252681 WR_PST = 0x0
3871 17:43:58.253291 DBI_WR = 0x0
3872 17:43:58.255691 DBI_RD = 0x0
3873 17:43:58.256303 OTF = 0x1
3874 17:43:58.259535 ===================================
3875 17:43:58.265837 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3876 17:43:58.269227 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3877 17:43:58.272714 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 17:43:58.276273 ===================================
3879 17:43:58.279471 LPDDR4 DRAM CONFIGURATION
3880 17:43:58.282774 ===================================
3881 17:43:58.286409 EX_ROW_EN[0] = 0x10
3882 17:43:58.286985 EX_ROW_EN[1] = 0x0
3883 17:43:58.289359 LP4Y_EN = 0x0
3884 17:43:58.289922 WORK_FSP = 0x0
3885 17:43:58.292620 WL = 0x2
3886 17:43:58.293117 RL = 0x2
3887 17:43:58.295717 BL = 0x2
3888 17:43:58.296183 RPST = 0x0
3889 17:43:58.298924 RD_PRE = 0x0
3890 17:43:58.299395 WR_PRE = 0x1
3891 17:43:58.302522 WR_PST = 0x0
3892 17:43:58.302990 DBI_WR = 0x0
3893 17:43:58.305824 DBI_RD = 0x0
3894 17:43:58.306393 OTF = 0x1
3895 17:43:58.309212 ===================================
3896 17:43:58.315767 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3897 17:43:58.320297 nWR fixed to 30
3898 17:43:58.323616 [ModeRegInit_LP4] CH0 RK0
3899 17:43:58.324086 [ModeRegInit_LP4] CH0 RK1
3900 17:43:58.327182 [ModeRegInit_LP4] CH1 RK0
3901 17:43:58.330480 [ModeRegInit_LP4] CH1 RK1
3902 17:43:58.331017 match AC timing 17
3903 17:43:58.337093 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3904 17:43:58.340317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3905 17:43:58.343595 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3906 17:43:58.350355 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3907 17:43:58.353698 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3908 17:43:58.354168 ==
3909 17:43:58.356828 Dram Type= 6, Freq= 0, CH_0, rank 0
3910 17:43:58.359968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3911 17:43:58.360431 ==
3912 17:43:58.366854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3913 17:43:58.373427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3914 17:43:58.376753 [CA 0] Center 36 (5~67) winsize 63
3915 17:43:58.380085 [CA 1] Center 36 (6~67) winsize 62
3916 17:43:58.383150 [CA 2] Center 34 (4~65) winsize 62
3917 17:43:58.386835 [CA 3] Center 34 (3~65) winsize 63
3918 17:43:58.389809 [CA 4] Center 33 (3~64) winsize 62
3919 17:43:58.393203 [CA 5] Center 33 (3~64) winsize 62
3920 17:43:58.393670
3921 17:43:58.396800 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3922 17:43:58.397405
3923 17:43:58.399917 [CATrainingPosCal] consider 1 rank data
3924 17:43:58.403295 u2DelayCellTimex100 = 270/100 ps
3925 17:43:58.406632 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3926 17:43:58.410151 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 17:43:58.413161 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 17:43:58.416454 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3929 17:43:58.419919 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3930 17:43:58.426614 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 17:43:58.427194
3932 17:43:58.430044 CA PerBit enable=1, Macro0, CA PI delay=33
3933 17:43:58.430509
3934 17:43:58.433048 [CBTSetCACLKResult] CA Dly = 33
3935 17:43:58.433512 CS Dly: 4 (0~35)
3936 17:43:58.433937 ==
3937 17:43:58.436555 Dram Type= 6, Freq= 0, CH_0, rank 1
3938 17:43:58.439854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 17:43:58.443082 ==
3940 17:43:58.446225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3941 17:43:58.453006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3942 17:43:58.456328 [CA 0] Center 36 (6~67) winsize 62
3943 17:43:58.459708 [CA 1] Center 36 (6~67) winsize 62
3944 17:43:58.463188 [CA 2] Center 35 (4~66) winsize 63
3945 17:43:58.466221 [CA 3] Center 34 (4~65) winsize 62
3946 17:43:58.469859 [CA 4] Center 34 (3~65) winsize 63
3947 17:43:58.473051 [CA 5] Center 33 (3~64) winsize 62
3948 17:43:58.473648
3949 17:43:58.476162 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3950 17:43:58.476629
3951 17:43:58.479723 [CATrainingPosCal] consider 2 rank data
3952 17:43:58.482769 u2DelayCellTimex100 = 270/100 ps
3953 17:43:58.486517 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 17:43:58.489315 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 17:43:58.492859 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 17:43:58.499776 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3957 17:43:58.502981 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 17:43:58.506378 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 17:43:58.506934
3960 17:43:58.509607 CA PerBit enable=1, Macro0, CA PI delay=33
3961 17:43:58.510188
3962 17:43:58.513266 [CBTSetCACLKResult] CA Dly = 33
3963 17:43:58.513833 CS Dly: 5 (0~37)
3964 17:43:58.514205
3965 17:43:58.516478 ----->DramcWriteLeveling(PI) begin...
3966 17:43:58.517080 ==
3967 17:43:58.519333 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 17:43:58.526221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 17:43:58.526761 ==
3970 17:43:58.529250 Write leveling (Byte 0): 33 => 33
3971 17:43:58.532693 Write leveling (Byte 1): 32 => 32
3972 17:43:58.533210 DramcWriteLeveling(PI) end<-----
3973 17:43:58.533586
3974 17:43:58.535790 ==
3975 17:43:58.539667 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 17:43:58.542589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 17:43:58.543065 ==
3978 17:43:58.546158 [Gating] SW mode calibration
3979 17:43:58.552608 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3980 17:43:58.556325 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3981 17:43:58.562451 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 17:43:58.566079 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 17:43:58.569228 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 17:43:58.576279 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
3985 17:43:58.579366 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3986 17:43:58.582680 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 17:43:58.589191 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 17:43:58.592429 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 17:43:58.596012 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 17:43:58.602157 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 17:43:58.605948 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3992 17:43:58.608878 0 10 12 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
3993 17:43:58.615724 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3994 17:43:58.618818 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 17:43:58.622465 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 17:43:58.629059 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 17:43:58.632151 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 17:43:58.635367 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 17:43:58.638767 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 17:43:58.645380 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4001 17:43:58.648480 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4002 17:43:58.651729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 17:43:58.658796 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 17:43:58.661839 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 17:43:58.665359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 17:43:58.671834 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 17:43:58.675217 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 17:43:58.678873 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 17:43:58.685637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 17:43:58.688565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 17:43:58.691978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 17:43:58.698300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 17:43:58.701915 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 17:43:58.705072 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 17:43:58.711742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 17:43:58.715158 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4017 17:43:58.718807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4018 17:43:58.721786 Total UI for P1: 0, mck2ui 16
4019 17:43:58.725112 best dqsien dly found for B0: ( 0, 13, 12)
4020 17:43:58.731785 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 17:43:58.732051 Total UI for P1: 0, mck2ui 16
4022 17:43:58.738403 best dqsien dly found for B1: ( 0, 13, 16)
4023 17:43:58.741561 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4024 17:43:58.745045 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4025 17:43:58.745313
4026 17:43:58.748286 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4027 17:43:58.751991 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4028 17:43:58.755083 [Gating] SW calibration Done
4029 17:43:58.755517 ==
4030 17:43:58.758704 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 17:43:58.761643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 17:43:58.762129 ==
4033 17:43:58.764842 RX Vref Scan: 0
4034 17:43:58.765366
4035 17:43:58.765839 RX Vref 0 -> 0, step: 1
4036 17:43:58.766288
4037 17:43:58.768509 RX Delay -230 -> 252, step: 16
4038 17:43:58.775233 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4039 17:43:58.778351 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4040 17:43:58.781461 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4041 17:43:58.784979 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4042 17:43:58.788102 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4043 17:43:58.795014 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4044 17:43:58.798126 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4045 17:43:58.801919 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4046 17:43:58.805077 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4047 17:43:58.811722 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4048 17:43:58.815021 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4049 17:43:58.818329 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4050 17:43:58.821524 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4051 17:43:58.828319 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4052 17:43:58.831703 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4053 17:43:58.835446 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4054 17:43:58.836024 ==
4055 17:43:58.838607 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 17:43:58.841612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 17:43:58.842088 ==
4058 17:43:58.844615 DQS Delay:
4059 17:43:58.845123 DQS0 = 0, DQS1 = 0
4060 17:43:58.848156 DQM Delay:
4061 17:43:58.848625 DQM0 = 50, DQM1 = 38
4062 17:43:58.849038 DQ Delay:
4063 17:43:58.851649 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4064 17:43:58.854683 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4065 17:43:58.858197 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4066 17:43:58.861213 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4067 17:43:58.861658
4068 17:43:58.861995
4069 17:43:58.864816 ==
4070 17:43:58.865280 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 17:43:58.871362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 17:43:58.871791 ==
4073 17:43:58.872130
4074 17:43:58.872439
4075 17:43:58.874607 TX Vref Scan disable
4076 17:43:58.875031 == TX Byte 0 ==
4077 17:43:58.877924 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4078 17:43:58.884723 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4079 17:43:58.885296 == TX Byte 1 ==
4080 17:43:58.891457 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4081 17:43:58.894870 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4082 17:43:58.895403 ==
4083 17:43:58.897580 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 17:43:58.901252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 17:43:58.901677 ==
4086 17:43:58.902013
4087 17:43:58.902325
4088 17:43:58.904337 TX Vref Scan disable
4089 17:43:58.907665 == TX Byte 0 ==
4090 17:43:58.911214 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4091 17:43:58.914274 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4092 17:43:58.917749 == TX Byte 1 ==
4093 17:43:58.920735 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4094 17:43:58.924398 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4095 17:43:58.924997
4096 17:43:58.927546 [DATLAT]
4097 17:43:58.927997 Freq=600, CH0 RK0
4098 17:43:58.928440
4099 17:43:58.931109 DATLAT Default: 0x9
4100 17:43:58.931550 0, 0xFFFF, sum = 0
4101 17:43:58.934869 1, 0xFFFF, sum = 0
4102 17:43:58.935424 2, 0xFFFF, sum = 0
4103 17:43:58.937782 3, 0xFFFF, sum = 0
4104 17:43:58.938228 4, 0xFFFF, sum = 0
4105 17:43:58.941413 5, 0xFFFF, sum = 0
4106 17:43:58.941860 6, 0xFFFF, sum = 0
4107 17:43:58.943998 7, 0xFFFF, sum = 0
4108 17:43:58.944459 8, 0x0, sum = 1
4109 17:43:58.947723 9, 0x0, sum = 2
4110 17:43:58.948158 10, 0x0, sum = 3
4111 17:43:58.951083 11, 0x0, sum = 4
4112 17:43:58.951520 best_step = 9
4113 17:43:58.951856
4114 17:43:58.952167 ==
4115 17:43:58.954398 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 17:43:58.957553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 17:43:58.960833 ==
4118 17:43:58.961365 RX Vref Scan: 1
4119 17:43:58.961710
4120 17:43:58.964324 RX Vref 0 -> 0, step: 1
4121 17:43:58.964744
4122 17:43:58.967447 RX Delay -179 -> 252, step: 8
4123 17:43:58.967869
4124 17:43:58.970713 Set Vref, RX VrefLevel [Byte0]: 59
4125 17:43:58.973577 [Byte1]: 48
4126 17:43:58.974130
4127 17:43:58.977328 Final RX Vref Byte 0 = 59 to rank0
4128 17:43:58.980817 Final RX Vref Byte 1 = 48 to rank0
4129 17:43:58.984162 Final RX Vref Byte 0 = 59 to rank1
4130 17:43:58.987151 Final RX Vref Byte 1 = 48 to rank1==
4131 17:43:58.990564 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 17:43:58.993685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 17:43:58.994117 ==
4134 17:43:58.997404 DQS Delay:
4135 17:43:58.997833 DQS0 = 0, DQS1 = 0
4136 17:43:58.998173 DQM Delay:
4137 17:43:59.000504 DQM0 = 50, DQM1 = 37
4138 17:43:59.000960 DQ Delay:
4139 17:43:59.003696 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4140 17:43:59.007366 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4141 17:43:59.010850 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4142 17:43:59.014134 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4143 17:43:59.014565
4144 17:43:59.014901
4145 17:43:59.023738 [DQSOSCAuto] RK0, (LSB)MR18= 0x544f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4146 17:43:59.024170 CH0 RK0: MR19=808, MR18=544F
4147 17:43:59.030722 CH0_RK0: MR19=0x808, MR18=0x544F, DQSOSC=393, MR23=63, INC=169, DEC=113
4148 17:43:59.031219
4149 17:43:59.033874 ----->DramcWriteLeveling(PI) begin...
4150 17:43:59.034308 ==
4151 17:43:59.037117 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 17:43:59.043910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 17:43:59.044429 ==
4154 17:43:59.047183 Write leveling (Byte 0): 34 => 34
4155 17:43:59.050872 Write leveling (Byte 1): 29 => 29
4156 17:43:59.051302 DramcWriteLeveling(PI) end<-----
4157 17:43:59.051637
4158 17:43:59.054008 ==
4159 17:43:59.057159 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 17:43:59.060565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 17:43:59.061028 ==
4162 17:43:59.063695 [Gating] SW mode calibration
4163 17:43:59.070423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4164 17:43:59.073339 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4165 17:43:59.080237 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 17:43:59.083511 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 17:43:59.087018 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 17:43:59.093140 0 9 12 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
4169 17:43:59.096814 0 9 16 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 0)
4170 17:43:59.099873 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 17:43:59.106893 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 17:43:59.109959 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 17:43:59.113353 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 17:43:59.120043 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 17:43:59.123377 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 17:43:59.126709 0 10 12 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (0 0)
4177 17:43:59.133448 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4178 17:43:59.136647 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 17:43:59.139991 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 17:43:59.146386 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 17:43:59.149869 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 17:43:59.153006 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 17:43:59.159989 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 17:43:59.162843 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4185 17:43:59.166371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4186 17:43:59.173064 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 17:43:59.176356 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 17:43:59.179882 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 17:43:59.186661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 17:43:59.189421 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 17:43:59.193021 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 17:43:59.199784 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 17:43:59.203143 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 17:43:59.206342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 17:43:59.209865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 17:43:59.216257 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 17:43:59.219848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 17:43:59.222751 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 17:43:59.229501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4200 17:43:59.232923 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4201 17:43:59.236685 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4202 17:43:59.239693 Total UI for P1: 0, mck2ui 16
4203 17:43:59.242839 best dqsien dly found for B0: ( 0, 13, 14)
4204 17:43:59.249539 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 17:43:59.252499 Total UI for P1: 0, mck2ui 16
4206 17:43:59.255934 best dqsien dly found for B1: ( 0, 13, 14)
4207 17:43:59.259471 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4208 17:43:59.262580 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4209 17:43:59.263006
4210 17:43:59.265765 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4211 17:43:59.269361 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4212 17:43:59.272407 [Gating] SW calibration Done
4213 17:43:59.272834 ==
4214 17:43:59.275755 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 17:43:59.279566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 17:43:59.280104 ==
4217 17:43:59.282752 RX Vref Scan: 0
4218 17:43:59.283280
4219 17:43:59.285685 RX Vref 0 -> 0, step: 1
4220 17:43:59.286113
4221 17:43:59.286445 RX Delay -230 -> 252, step: 16
4222 17:43:59.292707 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4223 17:43:59.295984 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4224 17:43:59.299320 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4225 17:43:59.302786 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4226 17:43:59.309445 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4227 17:43:59.312538 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4228 17:43:59.316189 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4229 17:43:59.319249 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4230 17:43:59.322705 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4231 17:43:59.329059 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4232 17:43:59.332535 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4233 17:43:59.335789 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4234 17:43:59.339590 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4235 17:43:59.345706 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4236 17:43:59.349266 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4237 17:43:59.352907 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4238 17:43:59.353549 ==
4239 17:43:59.355973 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 17:43:59.359202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 17:43:59.359772 ==
4242 17:43:59.362117 DQS Delay:
4243 17:43:59.362595 DQS0 = 0, DQS1 = 0
4244 17:43:59.365627 DQM Delay:
4245 17:43:59.366118 DQM0 = 48, DQM1 = 39
4246 17:43:59.366487 DQ Delay:
4247 17:43:59.368738 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4248 17:43:59.372289 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4249 17:43:59.375576 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4250 17:43:59.378965 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4251 17:43:59.379559
4252 17:43:59.382260
4253 17:43:59.382847 ==
4254 17:43:59.385667 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 17:43:59.388751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 17:43:59.389261 ==
4257 17:43:59.389639
4258 17:43:59.389988
4259 17:43:59.391966 TX Vref Scan disable
4260 17:43:59.392438 == TX Byte 0 ==
4261 17:43:59.398989 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4262 17:43:59.402232 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4263 17:43:59.402688 == TX Byte 1 ==
4264 17:43:59.409027 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4265 17:43:59.412073 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4266 17:43:59.412613 ==
4267 17:43:59.415241 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 17:43:59.418411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 17:43:59.418847 ==
4270 17:43:59.419190
4271 17:43:59.419503
4272 17:43:59.421990 TX Vref Scan disable
4273 17:43:59.425058 == TX Byte 0 ==
4274 17:43:59.428881 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4275 17:43:59.431868 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4276 17:43:59.435555 == TX Byte 1 ==
4277 17:43:59.438518 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4278 17:43:59.441721 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4279 17:43:59.445064
4280 17:43:59.445557 [DATLAT]
4281 17:43:59.445900 Freq=600, CH0 RK1
4282 17:43:59.446218
4283 17:43:59.448338 DATLAT Default: 0x9
4284 17:43:59.448798 0, 0xFFFF, sum = 0
4285 17:43:59.451704 1, 0xFFFF, sum = 0
4286 17:43:59.452129 2, 0xFFFF, sum = 0
4287 17:43:59.454880 3, 0xFFFF, sum = 0
4288 17:43:59.455308 4, 0xFFFF, sum = 0
4289 17:43:59.458655 5, 0xFFFF, sum = 0
4290 17:43:59.459080 6, 0xFFFF, sum = 0
4291 17:43:59.461703 7, 0xFFFF, sum = 0
4292 17:43:59.462126 8, 0x0, sum = 1
4293 17:43:59.465348 9, 0x0, sum = 2
4294 17:43:59.465762 10, 0x0, sum = 3
4295 17:43:59.468322 11, 0x0, sum = 4
4296 17:43:59.468737 best_step = 9
4297 17:43:59.469100
4298 17:43:59.469408 ==
4299 17:43:59.471607 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 17:43:59.478383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 17:43:59.478798 ==
4302 17:43:59.479119 RX Vref Scan: 0
4303 17:43:59.479423
4304 17:43:59.481647 RX Vref 0 -> 0, step: 1
4305 17:43:59.482056
4306 17:43:59.484874 RX Delay -179 -> 252, step: 8
4307 17:43:59.488617 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4308 17:43:59.491406 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4309 17:43:59.498262 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4310 17:43:59.501706 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4311 17:43:59.504860 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4312 17:43:59.507925 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4313 17:43:59.514889 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4314 17:43:59.517906 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4315 17:43:59.521022 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4316 17:43:59.524489 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4317 17:43:59.527907 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4318 17:43:59.534647 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4319 17:43:59.537847 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4320 17:43:59.541382 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4321 17:43:59.544486 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4322 17:43:59.551249 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4323 17:43:59.551730 ==
4324 17:43:59.554649 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 17:43:59.557942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 17:43:59.558359 ==
4327 17:43:59.558682 DQS Delay:
4328 17:43:59.561061 DQS0 = 0, DQS1 = 0
4329 17:43:59.561474 DQM Delay:
4330 17:43:59.564704 DQM0 = 49, DQM1 = 41
4331 17:43:59.565155 DQ Delay:
4332 17:43:59.567882 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4333 17:43:59.570991 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4334 17:43:59.574773 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4335 17:43:59.577701 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =48
4336 17:43:59.578110
4337 17:43:59.578427
4338 17:43:59.584609 [DQSOSCAuto] RK1, (LSB)MR18= 0x612f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4339 17:43:59.587788 CH0 RK1: MR19=808, MR18=612F
4340 17:43:59.594503 CH0_RK1: MR19=0x808, MR18=0x612F, DQSOSC=391, MR23=63, INC=171, DEC=114
4341 17:43:59.597845 [RxdqsGatingPostProcess] freq 600
4342 17:43:59.604191 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 17:43:59.607631 Pre-setting of DQS Precalculation
4344 17:43:59.610919 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 17:43:59.611380 ==
4346 17:43:59.614399 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 17:43:59.617562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 17:43:59.618190 ==
4349 17:43:59.624066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 17:43:59.630817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4351 17:43:59.634425 [CA 0] Center 35 (5~66) winsize 62
4352 17:43:59.637640 [CA 1] Center 35 (5~66) winsize 62
4353 17:43:59.641068 [CA 2] Center 34 (4~65) winsize 62
4354 17:43:59.644086 [CA 3] Center 33 (3~64) winsize 62
4355 17:43:59.647565 [CA 4] Center 34 (3~65) winsize 63
4356 17:43:59.650706 [CA 5] Center 33 (3~64) winsize 62
4357 17:43:59.651116
4358 17:43:59.654241 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4359 17:43:59.654655
4360 17:43:59.657363 [CATrainingPosCal] consider 1 rank data
4361 17:43:59.660724 u2DelayCellTimex100 = 270/100 ps
4362 17:43:59.664206 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 17:43:59.667365 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 17:43:59.670590 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 17:43:59.673878 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 17:43:59.677476 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4367 17:43:59.683810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 17:43:59.684322
4369 17:43:59.687469 CA PerBit enable=1, Macro0, CA PI delay=33
4370 17:43:59.687954
4371 17:43:59.690719 [CBTSetCACLKResult] CA Dly = 33
4372 17:43:59.691135 CS Dly: 5 (0~36)
4373 17:43:59.691459 ==
4374 17:43:59.694170 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 17:43:59.697363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 17:43:59.700226 ==
4377 17:43:59.703508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 17:43:59.710227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 17:43:59.713793 [CA 0] Center 35 (5~66) winsize 62
4380 17:43:59.716698 [CA 1] Center 36 (5~67) winsize 63
4381 17:43:59.720683 [CA 2] Center 34 (4~65) winsize 62
4382 17:43:59.723507 [CA 3] Center 34 (4~65) winsize 62
4383 17:43:59.726711 [CA 4] Center 34 (4~65) winsize 62
4384 17:43:59.730611 [CA 5] Center 34 (4~65) winsize 62
4385 17:43:59.731099
4386 17:43:59.733596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 17:43:59.734016
4388 17:43:59.737368 [CATrainingPosCal] consider 2 rank data
4389 17:43:59.740587 u2DelayCellTimex100 = 270/100 ps
4390 17:43:59.743910 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4391 17:43:59.747180 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4392 17:43:59.750470 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 17:43:59.754097 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4394 17:43:59.757264 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4395 17:43:59.763875 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4396 17:43:59.764364
4397 17:43:59.767133 CA PerBit enable=1, Macro0, CA PI delay=34
4398 17:43:59.767627
4399 17:43:59.770329 [CBTSetCACLKResult] CA Dly = 34
4400 17:43:59.770800 CS Dly: 5 (0~37)
4401 17:43:59.771137
4402 17:43:59.773868 ----->DramcWriteLeveling(PI) begin...
4403 17:43:59.774293 ==
4404 17:43:59.776813 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 17:43:59.780275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 17:43:59.783631 ==
4407 17:43:59.784054 Write leveling (Byte 0): 29 => 29
4408 17:43:59.787378 Write leveling (Byte 1): 30 => 30
4409 17:43:59.790357 DramcWriteLeveling(PI) end<-----
4410 17:43:59.790778
4411 17:43:59.791109 ==
4412 17:43:59.793528 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 17:43:59.800248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 17:43:59.800749 ==
4415 17:43:59.804325 [Gating] SW mode calibration
4416 17:43:59.810516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 17:43:59.813555 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 17:43:59.820128 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 17:43:59.823538 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 17:43:59.826918 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4421 17:43:59.833660 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (1 1) (0 0)
4422 17:43:59.836910 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 17:43:59.840301 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 17:43:59.843521 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 17:43:59.850150 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 17:43:59.853346 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 17:43:59.856906 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 17:43:59.863519 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4429 17:43:59.866791 0 10 12 | B1->B0 | 3535 3939 | 0 0 | (0 0) (0 0)
4430 17:43:59.870244 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 17:43:59.877028 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 17:43:59.880237 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 17:43:59.883454 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 17:43:59.890130 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 17:43:59.893539 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 17:43:59.896592 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4437 17:43:59.903855 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 17:43:59.906813 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 17:43:59.909841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 17:43:59.916814 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 17:43:59.920065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 17:43:59.923111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 17:43:59.929946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 17:43:59.933540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 17:43:59.936651 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 17:43:59.943466 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 17:43:59.946795 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 17:43:59.950153 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 17:43:59.956428 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 17:43:59.959605 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 17:43:59.963568 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 17:43:59.969966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 17:43:59.973534 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4454 17:43:59.976492 Total UI for P1: 0, mck2ui 16
4455 17:43:59.979843 best dqsien dly found for B0: ( 0, 13, 10)
4456 17:43:59.983241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 17:43:59.986725 Total UI for P1: 0, mck2ui 16
4458 17:43:59.989507 best dqsien dly found for B1: ( 0, 13, 12)
4459 17:43:59.992727 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4460 17:43:59.996273 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4461 17:43:59.996766
4462 17:43:59.999672 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4463 17:44:00.006279 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4464 17:44:00.006851 [Gating] SW calibration Done
4465 17:44:00.007222 ==
4466 17:44:00.009674 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 17:44:00.016244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 17:44:00.016776 ==
4469 17:44:00.017179 RX Vref Scan: 0
4470 17:44:00.017525
4471 17:44:00.019653 RX Vref 0 -> 0, step: 1
4472 17:44:00.020215
4473 17:44:00.022725 RX Delay -230 -> 252, step: 16
4474 17:44:00.026085 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4475 17:44:00.029784 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4476 17:44:00.035838 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4477 17:44:00.039866 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4478 17:44:00.042426 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4479 17:44:00.045862 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4480 17:44:00.049577 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4481 17:44:00.055852 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4482 17:44:00.059362 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4483 17:44:00.062633 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4484 17:44:00.065964 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4485 17:44:00.072458 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4486 17:44:00.076125 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4487 17:44:00.079544 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4488 17:44:00.082798 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4489 17:44:00.086474 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4490 17:44:00.089530 ==
4491 17:44:00.092795 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 17:44:00.095920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 17:44:00.096388 ==
4494 17:44:00.096754 DQS Delay:
4495 17:44:00.099764 DQS0 = 0, DQS1 = 0
4496 17:44:00.100346 DQM Delay:
4497 17:44:00.102612 DQM0 = 49, DQM1 = 38
4498 17:44:00.103078 DQ Delay:
4499 17:44:00.105947 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4500 17:44:00.109278 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4501 17:44:00.112892 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4502 17:44:00.115665 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4503 17:44:00.116136
4504 17:44:00.116499
4505 17:44:00.116837 ==
4506 17:44:00.119247 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 17:44:00.122567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 17:44:00.123143 ==
4509 17:44:00.123515
4510 17:44:00.123946
4511 17:44:00.126277 TX Vref Scan disable
4512 17:44:00.129094 == TX Byte 0 ==
4513 17:44:00.132661 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4514 17:44:00.136038 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4515 17:44:00.139268 == TX Byte 1 ==
4516 17:44:00.142421 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 17:44:00.145855 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 17:44:00.146318 ==
4519 17:44:00.149138 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 17:44:00.152386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 17:44:00.155660 ==
4522 17:44:00.156127
4523 17:44:00.156490
4524 17:44:00.156877 TX Vref Scan disable
4525 17:44:00.159934 == TX Byte 0 ==
4526 17:44:00.163049 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4527 17:44:00.169760 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4528 17:44:00.170224 == TX Byte 1 ==
4529 17:44:00.172826 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4530 17:44:00.179820 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4531 17:44:00.180279
4532 17:44:00.180613 [DATLAT]
4533 17:44:00.180922 Freq=600, CH1 RK0
4534 17:44:00.181269
4535 17:44:00.183168 DATLAT Default: 0x9
4536 17:44:00.183744 0, 0xFFFF, sum = 0
4537 17:44:00.186387 1, 0xFFFF, sum = 0
4538 17:44:00.189170 2, 0xFFFF, sum = 0
4539 17:44:00.189600 3, 0xFFFF, sum = 0
4540 17:44:00.192562 4, 0xFFFF, sum = 0
4541 17:44:00.193264 5, 0xFFFF, sum = 0
4542 17:44:00.195917 6, 0xFFFF, sum = 0
4543 17:44:00.196374 7, 0xFFFF, sum = 0
4544 17:44:00.199933 8, 0x0, sum = 1
4545 17:44:00.200475 9, 0x0, sum = 2
4546 17:44:00.200819 10, 0x0, sum = 3
4547 17:44:00.202982 11, 0x0, sum = 4
4548 17:44:00.203486 best_step = 9
4549 17:44:00.203964
4550 17:44:00.204288 ==
4551 17:44:00.206165 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 17:44:00.212696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 17:44:00.213243 ==
4554 17:44:00.213617 RX Vref Scan: 1
4555 17:44:00.213932
4556 17:44:00.216224 RX Vref 0 -> 0, step: 1
4557 17:44:00.216794
4558 17:44:00.219400 RX Delay -179 -> 252, step: 8
4559 17:44:00.219971
4560 17:44:00.222973 Set Vref, RX VrefLevel [Byte0]: 53
4561 17:44:00.226005 [Byte1]: 57
4562 17:44:00.226461
4563 17:44:00.229467 Final RX Vref Byte 0 = 53 to rank0
4564 17:44:00.232794 Final RX Vref Byte 1 = 57 to rank0
4565 17:44:00.236033 Final RX Vref Byte 0 = 53 to rank1
4566 17:44:00.239492 Final RX Vref Byte 1 = 57 to rank1==
4567 17:44:00.242832 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 17:44:00.245862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 17:44:00.246291 ==
4570 17:44:00.249032 DQS Delay:
4571 17:44:00.249454 DQS0 = 0, DQS1 = 0
4572 17:44:00.252436 DQM Delay:
4573 17:44:00.253075 DQM0 = 47, DQM1 = 40
4574 17:44:00.253432 DQ Delay:
4575 17:44:00.255756 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4576 17:44:00.259493 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4577 17:44:00.262459 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4578 17:44:00.265759 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4579 17:44:00.266185
4580 17:44:00.266519
4581 17:44:00.275786 [DQSOSCAuto] RK0, (LSB)MR18= 0x446b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4582 17:44:00.279492 CH1 RK0: MR19=808, MR18=446B
4583 17:44:00.285694 CH1_RK0: MR19=0x808, MR18=0x446B, DQSOSC=389, MR23=63, INC=173, DEC=115
4584 17:44:00.286191
4585 17:44:00.288957 ----->DramcWriteLeveling(PI) begin...
4586 17:44:00.289400 ==
4587 17:44:00.292395 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 17:44:00.295757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 17:44:00.296309 ==
4590 17:44:00.298701 Write leveling (Byte 0): 31 => 31
4591 17:44:00.302530 Write leveling (Byte 1): 28 => 28
4592 17:44:00.305459 DramcWriteLeveling(PI) end<-----
4593 17:44:00.305883
4594 17:44:00.306214 ==
4595 17:44:00.309262 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 17:44:00.312481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 17:44:00.313063 ==
4598 17:44:00.315541 [Gating] SW mode calibration
4599 17:44:00.322476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4600 17:44:00.328696 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4601 17:44:00.332499 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 17:44:00.335571 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 17:44:00.342536 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 17:44:00.345658 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
4605 17:44:00.348755 0 9 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4606 17:44:00.355299 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 17:44:00.358700 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 17:44:00.362022 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 17:44:00.368439 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 17:44:00.372022 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 17:44:00.375515 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4612 17:44:00.382025 0 10 12 | B1->B0 | 3a3a 2e2e | 0 0 | (0 0) (0 0)
4613 17:44:00.384980 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4614 17:44:00.388829 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 17:44:00.391979 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 17:44:00.399094 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 17:44:00.401975 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 17:44:00.405354 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 17:44:00.411870 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 17:44:00.415710 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4621 17:44:00.418374 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 17:44:00.425333 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 17:44:00.428646 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 17:44:00.432222 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 17:44:00.438481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 17:44:00.442025 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 17:44:00.445140 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 17:44:00.452044 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 17:44:00.455202 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 17:44:00.458524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 17:44:00.464980 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 17:44:00.468275 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 17:44:00.471701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 17:44:00.478415 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 17:44:00.481483 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 17:44:00.484817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4637 17:44:00.488554 Total UI for P1: 0, mck2ui 16
4638 17:44:00.491648 best dqsien dly found for B0: ( 0, 13, 10)
4639 17:44:00.498544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 17:44:00.498985 Total UI for P1: 0, mck2ui 16
4641 17:44:00.501690 best dqsien dly found for B1: ( 0, 13, 12)
4642 17:44:00.508293 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4643 17:44:00.511817 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4644 17:44:00.512360
4645 17:44:00.514866 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4646 17:44:00.518337 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4647 17:44:00.521547 [Gating] SW calibration Done
4648 17:44:00.521973 ==
4649 17:44:00.524903 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 17:44:00.528409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 17:44:00.528992 ==
4652 17:44:00.531461 RX Vref Scan: 0
4653 17:44:00.532003
4654 17:44:00.532373 RX Vref 0 -> 0, step: 1
4655 17:44:00.532715
4656 17:44:00.535060 RX Delay -230 -> 252, step: 16
4657 17:44:00.538504 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4658 17:44:00.545173 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4659 17:44:00.548247 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4660 17:44:00.551558 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4661 17:44:00.554818 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4662 17:44:00.558054 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4663 17:44:00.564732 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4664 17:44:00.568093 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4665 17:44:00.571264 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4666 17:44:00.574499 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4667 17:44:00.581317 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4668 17:44:00.584520 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4669 17:44:00.587745 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4670 17:44:00.591183 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4671 17:44:00.597741 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4672 17:44:00.601218 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4673 17:44:00.601787 ==
4674 17:44:00.604619 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 17:44:00.608254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 17:44:00.608830 ==
4677 17:44:00.609239 DQS Delay:
4678 17:44:00.611384 DQS0 = 0, DQS1 = 0
4679 17:44:00.611949 DQM Delay:
4680 17:44:00.614482 DQM0 = 54, DQM1 = 49
4681 17:44:00.615046 DQ Delay:
4682 17:44:00.618149 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =57
4683 17:44:00.621190 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4684 17:44:00.624173 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4685 17:44:00.627865 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4686 17:44:00.628412
4687 17:44:00.628805
4688 17:44:00.629208 ==
4689 17:44:00.630637 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 17:44:00.637543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 17:44:00.638116 ==
4692 17:44:00.638490
4693 17:44:00.638830
4694 17:44:00.639151 TX Vref Scan disable
4695 17:44:00.640695 == TX Byte 0 ==
4696 17:44:00.644039 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4697 17:44:00.650582 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4698 17:44:00.651130 == TX Byte 1 ==
4699 17:44:00.653918 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4700 17:44:00.660720 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4701 17:44:00.661216 ==
4702 17:44:00.663749 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 17:44:00.667094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 17:44:00.667519 ==
4705 17:44:00.667848
4706 17:44:00.668152
4707 17:44:00.670562 TX Vref Scan disable
4708 17:44:00.674245 == TX Byte 0 ==
4709 17:44:00.677252 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4710 17:44:00.680411 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4711 17:44:00.683657 == TX Byte 1 ==
4712 17:44:00.687132 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4713 17:44:00.690161 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4714 17:44:00.690585
4715 17:44:00.690916 [DATLAT]
4716 17:44:00.693336 Freq=600, CH1 RK1
4717 17:44:00.693757
4718 17:44:00.696806 DATLAT Default: 0x9
4719 17:44:00.697266 0, 0xFFFF, sum = 0
4720 17:44:00.700257 1, 0xFFFF, sum = 0
4721 17:44:00.700684 2, 0xFFFF, sum = 0
4722 17:44:00.703853 3, 0xFFFF, sum = 0
4723 17:44:00.704384 4, 0xFFFF, sum = 0
4724 17:44:00.707206 5, 0xFFFF, sum = 0
4725 17:44:00.707738 6, 0xFFFF, sum = 0
4726 17:44:00.710296 7, 0xFFFF, sum = 0
4727 17:44:00.710723 8, 0x0, sum = 1
4728 17:44:00.713633 9, 0x0, sum = 2
4729 17:44:00.714059 10, 0x0, sum = 3
4730 17:44:00.717295 11, 0x0, sum = 4
4731 17:44:00.717822 best_step = 9
4732 17:44:00.718155
4733 17:44:00.718464 ==
4734 17:44:00.720172 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 17:44:00.723489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 17:44:00.724017 ==
4737 17:44:00.726973 RX Vref Scan: 0
4738 17:44:00.727502
4739 17:44:00.729989 RX Vref 0 -> 0, step: 1
4740 17:44:00.730410
4741 17:44:00.730741 RX Delay -179 -> 252, step: 8
4742 17:44:00.737836 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4743 17:44:00.741470 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4744 17:44:00.744531 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4745 17:44:00.748099 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4746 17:44:00.751600 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4747 17:44:00.757656 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4748 17:44:00.761287 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4749 17:44:00.764568 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4750 17:44:00.767884 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4751 17:44:00.774315 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4752 17:44:00.777684 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4753 17:44:00.781320 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4754 17:44:00.784426 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4755 17:44:00.787734 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4756 17:44:00.794263 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4757 17:44:00.797575 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4758 17:44:00.798044 ==
4759 17:44:00.801195 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 17:44:00.804151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 17:44:00.804622 ==
4762 17:44:00.807684 DQS Delay:
4763 17:44:00.808206 DQS0 = 0, DQS1 = 0
4764 17:44:00.808578 DQM Delay:
4765 17:44:00.810577 DQM0 = 48, DQM1 = 43
4766 17:44:00.811000 DQ Delay:
4767 17:44:00.814429 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4768 17:44:00.817412 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4769 17:44:00.821089 DQ8 =32, DQ9 =32, DQ10 =40, DQ11 =40
4770 17:44:00.824211 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4771 17:44:00.824772
4772 17:44:00.825174
4773 17:44:00.834210 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d14, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
4774 17:44:00.837605 CH1 RK1: MR19=808, MR18=4D14
4775 17:44:00.841163 CH1_RK1: MR19=0x808, MR18=0x4D14, DQSOSC=395, MR23=63, INC=168, DEC=112
4776 17:44:00.843659 [RxdqsGatingPostProcess] freq 600
4777 17:44:00.850848 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4778 17:44:00.854152 Pre-setting of DQS Precalculation
4779 17:44:00.857575 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4780 17:44:00.867601 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4781 17:44:00.873682 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4782 17:44:00.874256
4783 17:44:00.874750
4784 17:44:00.876985 [Calibration Summary] 1200 Mbps
4785 17:44:00.877457 CH 0, Rank 0
4786 17:44:00.880754 SW Impedance : PASS
4787 17:44:00.881382 DUTY Scan : NO K
4788 17:44:00.884250 ZQ Calibration : PASS
4789 17:44:00.887531 Jitter Meter : NO K
4790 17:44:00.888108 CBT Training : PASS
4791 17:44:00.890266 Write leveling : PASS
4792 17:44:00.893479 RX DQS gating : PASS
4793 17:44:00.893977 RX DQ/DQS(RDDQC) : PASS
4794 17:44:00.897415 TX DQ/DQS : PASS
4795 17:44:00.901007 RX DATLAT : PASS
4796 17:44:00.901607 RX DQ/DQS(Engine): PASS
4797 17:44:00.903464 TX OE : NO K
4798 17:44:00.903949 All Pass.
4799 17:44:00.904426
4800 17:44:00.907027 CH 0, Rank 1
4801 17:44:00.907510 SW Impedance : PASS
4802 17:44:00.910230 DUTY Scan : NO K
4803 17:44:00.910712 ZQ Calibration : PASS
4804 17:44:00.913876 Jitter Meter : NO K
4805 17:44:00.917068 CBT Training : PASS
4806 17:44:00.917600 Write leveling : PASS
4807 17:44:00.920494 RX DQS gating : PASS
4808 17:44:00.923797 RX DQ/DQS(RDDQC) : PASS
4809 17:44:00.924232 TX DQ/DQS : PASS
4810 17:44:00.926944 RX DATLAT : PASS
4811 17:44:00.930410 RX DQ/DQS(Engine): PASS
4812 17:44:00.930943 TX OE : NO K
4813 17:44:00.933963 All Pass.
4814 17:44:00.934497
4815 17:44:00.934945 CH 1, Rank 0
4816 17:44:00.937299 SW Impedance : PASS
4817 17:44:00.937837 DUTY Scan : NO K
4818 17:44:00.940476 ZQ Calibration : PASS
4819 17:44:00.943469 Jitter Meter : NO K
4820 17:44:00.943906 CBT Training : PASS
4821 17:44:00.947233 Write leveling : PASS
4822 17:44:00.950303 RX DQS gating : PASS
4823 17:44:00.950844 RX DQ/DQS(RDDQC) : PASS
4824 17:44:00.953834 TX DQ/DQS : PASS
4825 17:44:00.954378 RX DATLAT : PASS
4826 17:44:00.956658 RX DQ/DQS(Engine): PASS
4827 17:44:00.960430 TX OE : NO K
4828 17:44:00.961033 All Pass.
4829 17:44:00.961486
4830 17:44:00.961894 CH 1, Rank 1
4831 17:44:00.963408 SW Impedance : PASS
4832 17:44:00.966856 DUTY Scan : NO K
4833 17:44:00.967315 ZQ Calibration : PASS
4834 17:44:00.970019 Jitter Meter : NO K
4835 17:44:00.973344 CBT Training : PASS
4836 17:44:00.973777 Write leveling : PASS
4837 17:44:00.976852 RX DQS gating : PASS
4838 17:44:00.980601 RX DQ/DQS(RDDQC) : PASS
4839 17:44:00.981170 TX DQ/DQS : PASS
4840 17:44:00.983801 RX DATLAT : PASS
4841 17:44:00.987174 RX DQ/DQS(Engine): PASS
4842 17:44:00.987726 TX OE : NO K
4843 17:44:00.988180 All Pass.
4844 17:44:00.988594
4845 17:44:00.990629 DramC Write-DBI off
4846 17:44:00.993763 PER_BANK_REFRESH: Hybrid Mode
4847 17:44:00.994303 TX_TRACKING: ON
4848 17:44:01.003994 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4849 17:44:01.007643 [FAST_K] Save calibration result to emmc
4850 17:44:01.010275 dramc_set_vcore_voltage set vcore to 662500
4851 17:44:01.013682 Read voltage for 933, 3
4852 17:44:01.014191 Vio18 = 0
4853 17:44:01.016911 Vcore = 662500
4854 17:44:01.017379 Vdram = 0
4855 17:44:01.017814 Vddq = 0
4856 17:44:01.018223 Vmddr = 0
4857 17:44:01.023803 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4858 17:44:01.027089 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4859 17:44:01.030482 MEM_TYPE=3, freq_sel=17
4860 17:44:01.033824 sv_algorithm_assistance_LP4_1600
4861 17:44:01.037482 ============ PULL DRAM RESETB DOWN ============
4862 17:44:01.043731 ========== PULL DRAM RESETB DOWN end =========
4863 17:44:01.046894 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4864 17:44:01.050281 ===================================
4865 17:44:01.053803 LPDDR4 DRAM CONFIGURATION
4866 17:44:01.056542 ===================================
4867 17:44:01.057104 EX_ROW_EN[0] = 0x0
4868 17:44:01.060055 EX_ROW_EN[1] = 0x0
4869 17:44:01.060505 LP4Y_EN = 0x0
4870 17:44:01.063303 WORK_FSP = 0x0
4871 17:44:01.063741 WL = 0x3
4872 17:44:01.066398 RL = 0x3
4873 17:44:01.066838 BL = 0x2
4874 17:44:01.069705 RPST = 0x0
4875 17:44:01.073400 RD_PRE = 0x0
4876 17:44:01.073830 WR_PRE = 0x1
4877 17:44:01.076630 WR_PST = 0x0
4878 17:44:01.077098 DBI_WR = 0x0
4879 17:44:01.079726 DBI_RD = 0x0
4880 17:44:01.080153 OTF = 0x1
4881 17:44:01.083249 ===================================
4882 17:44:01.086525 ===================================
4883 17:44:01.089614 ANA top config
4884 17:44:01.092856 ===================================
4885 17:44:01.093197 DLL_ASYNC_EN = 0
4886 17:44:01.096723 ALL_SLAVE_EN = 1
4887 17:44:01.099668 NEW_RANK_MODE = 1
4888 17:44:01.102983 DLL_IDLE_MODE = 1
4889 17:44:01.103296 LP45_APHY_COMB_EN = 1
4890 17:44:01.106633 TX_ODT_DIS = 1
4891 17:44:01.109796 NEW_8X_MODE = 1
4892 17:44:01.112781 ===================================
4893 17:44:01.116621 ===================================
4894 17:44:01.119800 data_rate = 1866
4895 17:44:01.122754 CKR = 1
4896 17:44:01.123051 DQ_P2S_RATIO = 8
4897 17:44:01.126190 ===================================
4898 17:44:01.129669 CA_P2S_RATIO = 8
4899 17:44:01.133290 DQ_CA_OPEN = 0
4900 17:44:01.136325 DQ_SEMI_OPEN = 0
4901 17:44:01.139445 CA_SEMI_OPEN = 0
4902 17:44:01.143493 CA_FULL_RATE = 0
4903 17:44:01.144060 DQ_CKDIV4_EN = 1
4904 17:44:01.146610 CA_CKDIV4_EN = 1
4905 17:44:01.149864 CA_PREDIV_EN = 0
4906 17:44:01.153114 PH8_DLY = 0
4907 17:44:01.156195 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4908 17:44:01.159351 DQ_AAMCK_DIV = 4
4909 17:44:01.159825 CA_AAMCK_DIV = 4
4910 17:44:01.163292 CA_ADMCK_DIV = 4
4911 17:44:01.166114 DQ_TRACK_CA_EN = 0
4912 17:44:01.169481 CA_PICK = 933
4913 17:44:01.172838 CA_MCKIO = 933
4914 17:44:01.176349 MCKIO_SEMI = 0
4915 17:44:01.179096 PLL_FREQ = 3732
4916 17:44:01.182573 DQ_UI_PI_RATIO = 32
4917 17:44:01.183196 CA_UI_PI_RATIO = 0
4918 17:44:01.186107 ===================================
4919 17:44:01.189070 ===================================
4920 17:44:01.192294 memory_type:LPDDR4
4921 17:44:01.195711 GP_NUM : 10
4922 17:44:01.196139 SRAM_EN : 1
4923 17:44:01.198915 MD32_EN : 0
4924 17:44:01.202280 ===================================
4925 17:44:01.206197 [ANA_INIT] >>>>>>>>>>>>>>
4926 17:44:01.209510 <<<<<< [CONFIGURE PHASE]: ANA_TX
4927 17:44:01.212708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4928 17:44:01.215678 ===================================
4929 17:44:01.216199 data_rate = 1866,PCW = 0X8f00
4930 17:44:01.219094 ===================================
4931 17:44:01.222719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4932 17:44:01.229526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 17:44:01.235494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 17:44:01.238727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4935 17:44:01.242266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4936 17:44:01.245601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4937 17:44:01.249061 [ANA_INIT] flow start
4938 17:44:01.249495 [ANA_INIT] PLL >>>>>>>>
4939 17:44:01.252452 [ANA_INIT] PLL <<<<<<<<
4940 17:44:01.255393 [ANA_INIT] MIDPI >>>>>>>>
4941 17:44:01.258951 [ANA_INIT] MIDPI <<<<<<<<
4942 17:44:01.259382 [ANA_INIT] DLL >>>>>>>>
4943 17:44:01.262100 [ANA_INIT] flow end
4944 17:44:01.265819 ============ LP4 DIFF to SE enter ============
4945 17:44:01.268845 ============ LP4 DIFF to SE exit ============
4946 17:44:01.272286 [ANA_INIT] <<<<<<<<<<<<<
4947 17:44:01.275405 [Flow] Enable top DCM control >>>>>
4948 17:44:01.278688 [Flow] Enable top DCM control <<<<<
4949 17:44:01.281956 Enable DLL master slave shuffle
4950 17:44:01.288745 ==============================================================
4951 17:44:01.289208 Gating Mode config
4952 17:44:01.295513 ==============================================================
4953 17:44:01.295936 Config description:
4954 17:44:01.304824 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4955 17:44:01.311541 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4956 17:44:01.318049 SELPH_MODE 0: By rank 1: By Phase
4957 17:44:01.321724 ==============================================================
4958 17:44:01.324711 GAT_TRACK_EN = 1
4959 17:44:01.328131 RX_GATING_MODE = 2
4960 17:44:01.331756 RX_GATING_TRACK_MODE = 2
4961 17:44:01.334819 SELPH_MODE = 1
4962 17:44:01.338071 PICG_EARLY_EN = 1
4963 17:44:01.341502 VALID_LAT_VALUE = 1
4964 17:44:01.344799 ==============================================================
4965 17:44:01.347914 Enter into Gating configuration >>>>
4966 17:44:01.351554 Exit from Gating configuration <<<<
4967 17:44:01.354531 Enter into DVFS_PRE_config >>>>>
4968 17:44:01.367926 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4969 17:44:01.371010 Exit from DVFS_PRE_config <<<<<
4970 17:44:01.374167 Enter into PICG configuration >>>>
4971 17:44:01.377769 Exit from PICG configuration <<<<
4972 17:44:01.377873 [RX_INPUT] configuration >>>>>
4973 17:44:01.381068 [RX_INPUT] configuration <<<<<
4974 17:44:01.387409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4975 17:44:01.391020 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4976 17:44:01.397875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 17:44:01.404013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 17:44:01.410900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 17:44:01.417401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 17:44:01.421043 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4981 17:44:01.423926 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4982 17:44:01.430796 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4983 17:44:01.433990 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4984 17:44:01.437456 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4985 17:44:01.440466 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4986 17:44:01.443889 ===================================
4987 17:44:01.447305 LPDDR4 DRAM CONFIGURATION
4988 17:44:01.450354 ===================================
4989 17:44:01.453668 EX_ROW_EN[0] = 0x0
4990 17:44:01.453770 EX_ROW_EN[1] = 0x0
4991 17:44:01.457108 LP4Y_EN = 0x0
4992 17:44:01.457208 WORK_FSP = 0x0
4993 17:44:01.460189 WL = 0x3
4994 17:44:01.460265 RL = 0x3
4995 17:44:01.463887 BL = 0x2
4996 17:44:01.463989 RPST = 0x0
4997 17:44:01.467033 RD_PRE = 0x0
4998 17:44:01.467137 WR_PRE = 0x1
4999 17:44:01.470634 WR_PST = 0x0
5000 17:44:01.473652 DBI_WR = 0x0
5001 17:44:01.473756 DBI_RD = 0x0
5002 17:44:01.477377 OTF = 0x1
5003 17:44:01.480507 ===================================
5004 17:44:01.483688 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5005 17:44:01.487101 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5006 17:44:01.490314 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 17:44:01.494068 ===================================
5008 17:44:01.497044 LPDDR4 DRAM CONFIGURATION
5009 17:44:01.500238 ===================================
5010 17:44:01.503928 EX_ROW_EN[0] = 0x10
5011 17:44:01.504007 EX_ROW_EN[1] = 0x0
5012 17:44:01.506840 LP4Y_EN = 0x0
5013 17:44:01.506947 WORK_FSP = 0x0
5014 17:44:01.510242 WL = 0x3
5015 17:44:01.510330 RL = 0x3
5016 17:44:01.513862 BL = 0x2
5017 17:44:01.513951 RPST = 0x0
5018 17:44:01.517047 RD_PRE = 0x0
5019 17:44:01.517139 WR_PRE = 0x1
5020 17:44:01.520315 WR_PST = 0x0
5021 17:44:01.520415 DBI_WR = 0x0
5022 17:44:01.523976 DBI_RD = 0x0
5023 17:44:01.524073 OTF = 0x1
5024 17:44:01.527235 ===================================
5025 17:44:01.533797 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5026 17:44:01.538692 nWR fixed to 30
5027 17:44:01.542116 [ModeRegInit_LP4] CH0 RK0
5028 17:44:01.542192 [ModeRegInit_LP4] CH0 RK1
5029 17:44:01.545133 [ModeRegInit_LP4] CH1 RK0
5030 17:44:01.548324 [ModeRegInit_LP4] CH1 RK1
5031 17:44:01.548423 match AC timing 9
5032 17:44:01.555203 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5033 17:44:01.558474 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5034 17:44:01.561541 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5035 17:44:01.568037 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5036 17:44:01.571371 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5037 17:44:01.571473 ==
5038 17:44:01.574780 Dram Type= 6, Freq= 0, CH_0, rank 0
5039 17:44:01.578036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5040 17:44:01.578135 ==
5041 17:44:01.584766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5042 17:44:01.591428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5043 17:44:01.594557 [CA 0] Center 38 (7~69) winsize 63
5044 17:44:01.597934 [CA 1] Center 38 (8~69) winsize 62
5045 17:44:01.601443 [CA 2] Center 35 (5~66) winsize 62
5046 17:44:01.604642 [CA 3] Center 34 (4~65) winsize 62
5047 17:44:01.608192 [CA 4] Center 34 (4~65) winsize 62
5048 17:44:01.611302 [CA 5] Center 33 (3~64) winsize 62
5049 17:44:01.611398
5050 17:44:01.614527 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5051 17:44:01.614624
5052 17:44:01.618226 [CATrainingPosCal] consider 1 rank data
5053 17:44:01.621467 u2DelayCellTimex100 = 270/100 ps
5054 17:44:01.624474 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5055 17:44:01.627791 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5056 17:44:01.631351 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5057 17:44:01.634506 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5058 17:44:01.637974 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5059 17:44:01.644460 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5060 17:44:01.644560
5061 17:44:01.648120 CA PerBit enable=1, Macro0, CA PI delay=33
5062 17:44:01.648195
5063 17:44:01.651338 [CBTSetCACLKResult] CA Dly = 33
5064 17:44:01.651436 CS Dly: 6 (0~37)
5065 17:44:01.651533 ==
5066 17:44:01.654352 Dram Type= 6, Freq= 0, CH_0, rank 1
5067 17:44:01.658022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5068 17:44:01.661305 ==
5069 17:44:01.664860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5070 17:44:01.671354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5071 17:44:01.674597 [CA 0] Center 38 (8~69) winsize 62
5072 17:44:01.677700 [CA 1] Center 38 (8~69) winsize 62
5073 17:44:01.680837 [CA 2] Center 36 (6~66) winsize 61
5074 17:44:01.684286 [CA 3] Center 35 (5~66) winsize 62
5075 17:44:01.687838 [CA 4] Center 34 (4~65) winsize 62
5076 17:44:01.691086 [CA 5] Center 34 (4~64) winsize 61
5077 17:44:01.691162
5078 17:44:01.694569 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5079 17:44:01.694733
5080 17:44:01.697583 [CATrainingPosCal] consider 2 rank data
5081 17:44:01.701247 u2DelayCellTimex100 = 270/100 ps
5082 17:44:01.704547 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5083 17:44:01.707630 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 17:44:01.711236 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5085 17:44:01.714303 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5086 17:44:01.721027 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5087 17:44:01.724632 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5088 17:44:01.724732
5089 17:44:01.727710 CA PerBit enable=1, Macro0, CA PI delay=34
5090 17:44:01.727794
5091 17:44:01.730888 [CBTSetCACLKResult] CA Dly = 34
5092 17:44:01.730972 CS Dly: 7 (0~39)
5093 17:44:01.731039
5094 17:44:01.734502 ----->DramcWriteLeveling(PI) begin...
5095 17:44:01.734587 ==
5096 17:44:01.737600 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 17:44:01.744334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 17:44:01.744418 ==
5099 17:44:01.747723 Write leveling (Byte 0): 32 => 32
5100 17:44:01.747807 Write leveling (Byte 1): 32 => 32
5101 17:44:01.751023 DramcWriteLeveling(PI) end<-----
5102 17:44:01.751106
5103 17:44:01.754223 ==
5104 17:44:01.754307 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 17:44:01.760887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 17:44:01.761010 ==
5107 17:44:01.764018 [Gating] SW mode calibration
5108 17:44:01.770805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5109 17:44:01.774259 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5110 17:44:01.780663 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5111 17:44:01.784233 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 17:44:01.787367 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 17:44:01.794022 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 17:44:01.796986 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 17:44:01.800210 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 17:44:01.806981 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5117 17:44:01.810781 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 1) (1 0)
5118 17:44:01.813906 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5119 17:44:01.820602 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 17:44:01.823966 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 17:44:01.827502 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 17:44:01.833677 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 17:44:01.837188 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 17:44:01.840268 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5125 17:44:01.847213 0 15 28 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
5126 17:44:01.850447 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5127 17:44:01.853732 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 17:44:01.860433 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 17:44:01.863720 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 17:44:01.866883 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 17:44:01.873643 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 17:44:01.877118 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5133 17:44:01.880078 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 17:44:01.883367 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 17:44:01.890202 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 17:44:01.893378 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 17:44:01.896680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 17:44:01.903236 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 17:44:01.906604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 17:44:01.909836 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 17:44:01.916780 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 17:44:01.919964 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 17:44:01.923079 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 17:44:01.929460 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 17:44:01.933134 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 17:44:01.936327 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 17:44:01.942923 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 17:44:01.946713 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5149 17:44:01.949955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 17:44:01.953201 Total UI for P1: 0, mck2ui 16
5151 17:44:01.956472 best dqsien dly found for B0: ( 1, 2, 22)
5152 17:44:01.962842 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5153 17:44:01.966419 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 17:44:01.969611 Total UI for P1: 0, mck2ui 16
5155 17:44:01.973325 best dqsien dly found for B1: ( 1, 2, 30)
5156 17:44:01.976532 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5157 17:44:01.979863 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5158 17:44:01.979946
5159 17:44:01.982650 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5160 17:44:01.986436 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5161 17:44:01.989613 [Gating] SW calibration Done
5162 17:44:01.989695 ==
5163 17:44:01.992818 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 17:44:01.995912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 17:44:01.999613 ==
5166 17:44:01.999695 RX Vref Scan: 0
5167 17:44:01.999760
5168 17:44:02.002690 RX Vref 0 -> 0, step: 1
5169 17:44:02.002772
5170 17:44:02.006171 RX Delay -80 -> 252, step: 8
5171 17:44:02.009125 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5172 17:44:02.012786 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5173 17:44:02.016278 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5174 17:44:02.019499 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5175 17:44:02.025805 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5176 17:44:02.029204 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5177 17:44:02.032478 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5178 17:44:02.035756 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5179 17:44:02.038930 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5180 17:44:02.042308 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5181 17:44:02.049165 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5182 17:44:02.052480 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5183 17:44:02.056050 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5184 17:44:02.059235 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5185 17:44:02.062569 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5186 17:44:02.065763 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5187 17:44:02.069059 ==
5188 17:44:02.069142 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 17:44:02.075398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 17:44:02.075481 ==
5191 17:44:02.075547 DQS Delay:
5192 17:44:02.078921 DQS0 = 0, DQS1 = 0
5193 17:44:02.079003 DQM Delay:
5194 17:44:02.082040 DQM0 = 105, DQM1 = 90
5195 17:44:02.082122 DQ Delay:
5196 17:44:02.085647 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5197 17:44:02.088750 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5198 17:44:02.092248 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5199 17:44:02.095442 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5200 17:44:02.095524
5201 17:44:02.095588
5202 17:44:02.095647 ==
5203 17:44:02.098932 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 17:44:02.102229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 17:44:02.102312 ==
5206 17:44:02.102376
5207 17:44:02.105304
5208 17:44:02.105386 TX Vref Scan disable
5209 17:44:02.108937 == TX Byte 0 ==
5210 17:44:02.111907 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5211 17:44:02.115330 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5212 17:44:02.118704 == TX Byte 1 ==
5213 17:44:02.122223 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5214 17:44:02.125277 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5215 17:44:02.125359 ==
5216 17:44:02.128838 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 17:44:02.135229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 17:44:02.135312 ==
5219 17:44:02.135378
5220 17:44:02.135437
5221 17:44:02.135494 TX Vref Scan disable
5222 17:44:02.139583 == TX Byte 0 ==
5223 17:44:02.142623 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5224 17:44:02.149505 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5225 17:44:02.149587 == TX Byte 1 ==
5226 17:44:02.152464 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5227 17:44:02.159118 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5228 17:44:02.159203
5229 17:44:02.159270 [DATLAT]
5230 17:44:02.159332 Freq=933, CH0 RK0
5231 17:44:02.159390
5232 17:44:02.162606 DATLAT Default: 0xd
5233 17:44:02.162687 0, 0xFFFF, sum = 0
5234 17:44:02.166023 1, 0xFFFF, sum = 0
5235 17:44:02.166096 2, 0xFFFF, sum = 0
5236 17:44:02.169082 3, 0xFFFF, sum = 0
5237 17:44:02.172672 4, 0xFFFF, sum = 0
5238 17:44:02.172745 5, 0xFFFF, sum = 0
5239 17:44:02.175778 6, 0xFFFF, sum = 0
5240 17:44:02.175878 7, 0xFFFF, sum = 0
5241 17:44:02.179061 8, 0xFFFF, sum = 0
5242 17:44:02.179159 9, 0xFFFF, sum = 0
5243 17:44:02.182310 10, 0x0, sum = 1
5244 17:44:02.182409 11, 0x0, sum = 2
5245 17:44:02.185648 12, 0x0, sum = 3
5246 17:44:02.185750 13, 0x0, sum = 4
5247 17:44:02.185841 best_step = 11
5248 17:44:02.185926
5249 17:44:02.188908 ==
5250 17:44:02.192587 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 17:44:02.195652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 17:44:02.195754 ==
5253 17:44:02.195847 RX Vref Scan: 1
5254 17:44:02.195944
5255 17:44:02.199177 RX Vref 0 -> 0, step: 1
5256 17:44:02.199303
5257 17:44:02.202708 RX Delay -53 -> 252, step: 4
5258 17:44:02.202798
5259 17:44:02.205880 Set Vref, RX VrefLevel [Byte0]: 59
5260 17:44:02.208853 [Byte1]: 48
5261 17:44:02.208992
5262 17:44:02.212386 Final RX Vref Byte 0 = 59 to rank0
5263 17:44:02.215522 Final RX Vref Byte 1 = 48 to rank0
5264 17:44:02.218878 Final RX Vref Byte 0 = 59 to rank1
5265 17:44:02.222415 Final RX Vref Byte 1 = 48 to rank1==
5266 17:44:02.225787 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 17:44:02.229385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 17:44:02.229470 ==
5269 17:44:02.232442 DQS Delay:
5270 17:44:02.232527 DQS0 = 0, DQS1 = 0
5271 17:44:02.235676 DQM Delay:
5272 17:44:02.235759 DQM0 = 108, DQM1 = 91
5273 17:44:02.235825 DQ Delay:
5274 17:44:02.242514 DQ0 =108, DQ1 =106, DQ2 =104, DQ3 =104
5275 17:44:02.245657 DQ4 =110, DQ5 =100, DQ6 =116, DQ7 =116
5276 17:44:02.249300 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =88
5277 17:44:02.252275 DQ12 =94, DQ13 =94, DQ14 =104, DQ15 =100
5278 17:44:02.252358
5279 17:44:02.252422
5280 17:44:02.258671 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5281 17:44:02.262238 CH0 RK0: MR19=505, MR18=1D19
5282 17:44:02.268803 CH0_RK0: MR19=0x505, MR18=0x1D19, DQSOSC=412, MR23=63, INC=63, DEC=42
5283 17:44:02.268887
5284 17:44:02.272011 ----->DramcWriteLeveling(PI) begin...
5285 17:44:02.272095 ==
5286 17:44:02.275608 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 17:44:02.278642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 17:44:02.278725 ==
5289 17:44:02.282159 Write leveling (Byte 0): 33 => 33
5290 17:44:02.285470 Write leveling (Byte 1): 32 => 32
5291 17:44:02.288645 DramcWriteLeveling(PI) end<-----
5292 17:44:02.288730
5293 17:44:02.288794 ==
5294 17:44:02.292547 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 17:44:02.295573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 17:44:02.295660 ==
5297 17:44:02.298872 [Gating] SW mode calibration
5298 17:44:02.305612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5299 17:44:02.312051 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5300 17:44:02.315311 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 17:44:02.322085 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 17:44:02.325437 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 17:44:02.328568 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 17:44:02.335272 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 17:44:02.338828 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 17:44:02.341847 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5307 17:44:02.348592 0 14 28 | B1->B0 | 2b2b 2525 | 0 0 | (0 1) (0 1)
5308 17:44:02.352191 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 17:44:02.355283 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 17:44:02.358433 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 17:44:02.365651 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 17:44:02.368659 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 17:44:02.371749 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 17:44:02.378352 0 15 24 | B1->B0 | 2525 2a2a | 0 1 | (0 0) (1 1)
5315 17:44:02.381882 0 15 28 | B1->B0 | 3b3b 4343 | 1 0 | (0 0) (0 0)
5316 17:44:02.385196 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 17:44:02.391752 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 17:44:02.395013 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 17:44:02.398541 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 17:44:02.404961 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 17:44:02.408156 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 17:44:02.411444 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5323 17:44:02.418382 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5324 17:44:02.421455 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5325 17:44:02.424955 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 17:44:02.431762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 17:44:02.434951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 17:44:02.438384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 17:44:02.445186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 17:44:02.448427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 17:44:02.451759 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 17:44:02.458261 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 17:44:02.461468 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 17:44:02.465111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 17:44:02.471754 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 17:44:02.474927 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 17:44:02.478456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 17:44:02.484885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5339 17:44:02.488047 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5340 17:44:02.491599 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 17:44:02.494874 Total UI for P1: 0, mck2ui 16
5342 17:44:02.498182 best dqsien dly found for B0: ( 1, 2, 26)
5343 17:44:02.501923 Total UI for P1: 0, mck2ui 16
5344 17:44:02.504857 best dqsien dly found for B1: ( 1, 2, 28)
5345 17:44:02.508236 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5346 17:44:02.511605 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5347 17:44:02.511687
5348 17:44:02.514651 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5349 17:44:02.521248 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5350 17:44:02.521331 [Gating] SW calibration Done
5351 17:44:02.521396 ==
5352 17:44:02.524802 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 17:44:02.531178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 17:44:02.531269 ==
5355 17:44:02.531339 RX Vref Scan: 0
5356 17:44:02.531400
5357 17:44:02.534465 RX Vref 0 -> 0, step: 1
5358 17:44:02.534545
5359 17:44:02.537810 RX Delay -80 -> 252, step: 8
5360 17:44:02.541274 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5361 17:44:02.544409 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5362 17:44:02.547637 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5363 17:44:02.550844 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5364 17:44:02.557893 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5365 17:44:02.560856 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5366 17:44:02.564184 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5367 17:44:02.567500 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5368 17:44:02.571095 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5369 17:44:02.577698 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5370 17:44:02.580795 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5371 17:44:02.584294 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5372 17:44:02.587581 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5373 17:44:02.590629 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5374 17:44:02.594404 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5375 17:44:02.600702 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5376 17:44:02.600783 ==
5377 17:44:02.604201 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 17:44:02.607470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 17:44:02.607544 ==
5380 17:44:02.607607 DQS Delay:
5381 17:44:02.610966 DQS0 = 0, DQS1 = 0
5382 17:44:02.611049 DQM Delay:
5383 17:44:02.614134 DQM0 = 104, DQM1 = 90
5384 17:44:02.614207 DQ Delay:
5385 17:44:02.617337 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5386 17:44:02.620567 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5387 17:44:02.623843 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5388 17:44:02.627610 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5389 17:44:02.627691
5390 17:44:02.627753
5391 17:44:02.627809 ==
5392 17:44:02.630538 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 17:44:02.634019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 17:44:02.634090 ==
5395 17:44:02.637359
5396 17:44:02.637460
5397 17:44:02.637548 TX Vref Scan disable
5398 17:44:02.640425 == TX Byte 0 ==
5399 17:44:02.643875 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5400 17:44:02.647327 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5401 17:44:02.650772 == TX Byte 1 ==
5402 17:44:02.654010 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5403 17:44:02.657077 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5404 17:44:02.657156 ==
5405 17:44:02.660462 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 17:44:02.667159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 17:44:02.667237 ==
5408 17:44:02.667299
5409 17:44:02.667357
5410 17:44:02.667417 TX Vref Scan disable
5411 17:44:02.671541 == TX Byte 0 ==
5412 17:44:02.674672 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5413 17:44:02.681574 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5414 17:44:02.681649 == TX Byte 1 ==
5415 17:44:02.684860 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5416 17:44:02.687969 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5417 17:44:02.691579
5418 17:44:02.691652 [DATLAT]
5419 17:44:02.691712 Freq=933, CH0 RK1
5420 17:44:02.691769
5421 17:44:02.694735 DATLAT Default: 0xb
5422 17:44:02.694805 0, 0xFFFF, sum = 0
5423 17:44:02.698511 1, 0xFFFF, sum = 0
5424 17:44:02.698588 2, 0xFFFF, sum = 0
5425 17:44:02.701603 3, 0xFFFF, sum = 0
5426 17:44:02.701672 4, 0xFFFF, sum = 0
5427 17:44:02.705076 5, 0xFFFF, sum = 0
5428 17:44:02.708335 6, 0xFFFF, sum = 0
5429 17:44:02.708405 7, 0xFFFF, sum = 0
5430 17:44:02.711434 8, 0xFFFF, sum = 0
5431 17:44:02.711510 9, 0xFFFF, sum = 0
5432 17:44:02.714793 10, 0x0, sum = 1
5433 17:44:02.714862 11, 0x0, sum = 2
5434 17:44:02.714928 12, 0x0, sum = 3
5435 17:44:02.718017 13, 0x0, sum = 4
5436 17:44:02.718093 best_step = 11
5437 17:44:02.718193
5438 17:44:02.721092 ==
5439 17:44:02.721171 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 17:44:02.727866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 17:44:02.727949 ==
5442 17:44:02.728016 RX Vref Scan: 0
5443 17:44:02.728074
5444 17:44:02.731153 RX Vref 0 -> 0, step: 1
5445 17:44:02.731226
5446 17:44:02.734571 RX Delay -53 -> 252, step: 4
5447 17:44:02.738001 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5448 17:44:02.744341 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5449 17:44:02.748075 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5450 17:44:02.750974 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5451 17:44:02.754564 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5452 17:44:02.757948 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5453 17:44:02.764582 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5454 17:44:02.767738 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5455 17:44:02.771430 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5456 17:44:02.774322 iDelay=203, Bit 9, Center 78 (-5 ~ 162) 168
5457 17:44:02.777951 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5458 17:44:02.781242 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5459 17:44:02.787712 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5460 17:44:02.791059 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5461 17:44:02.794195 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5462 17:44:02.797743 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5463 17:44:02.797816 ==
5464 17:44:02.801253 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 17:44:02.807612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 17:44:02.807687 ==
5467 17:44:02.807755 DQS Delay:
5468 17:44:02.807818 DQS0 = 0, DQS1 = 0
5469 17:44:02.811183 DQM Delay:
5470 17:44:02.811268 DQM0 = 104, DQM1 = 91
5471 17:44:02.814220 DQ Delay:
5472 17:44:02.817547 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5473 17:44:02.820860 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112
5474 17:44:02.824374 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =90
5475 17:44:02.828074 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5476 17:44:02.828147
5477 17:44:02.828214
5478 17:44:02.834351 [DQSOSCAuto] RK1, (LSB)MR18= 0x2203, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 411 ps
5479 17:44:02.837621 CH0 RK1: MR19=505, MR18=2203
5480 17:44:02.844001 CH0_RK1: MR19=0x505, MR18=0x2203, DQSOSC=411, MR23=63, INC=64, DEC=42
5481 17:44:02.847563 [RxdqsGatingPostProcess] freq 933
5482 17:44:02.850827 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 17:44:02.854293 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 17:44:02.857437 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 17:44:02.860866 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 17:44:02.864628 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 17:44:02.867580 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 17:44:02.870998 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 17:44:02.874105 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 17:44:02.877580 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 17:44:02.880696 Pre-setting of DQS Precalculation
5492 17:44:02.884239 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 17:44:02.887437 ==
5494 17:44:02.890601 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 17:44:02.894297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 17:44:02.894368 ==
5497 17:44:02.897348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 17:44:02.903835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5499 17:44:02.907766 [CA 0] Center 38 (8~68) winsize 61
5500 17:44:02.910922 [CA 1] Center 38 (8~68) winsize 61
5501 17:44:02.914178 [CA 2] Center 35 (5~66) winsize 62
5502 17:44:02.917634 [CA 3] Center 34 (4~65) winsize 62
5503 17:44:02.920850 [CA 4] Center 35 (4~66) winsize 63
5504 17:44:02.924297 [CA 5] Center 34 (4~65) winsize 62
5505 17:44:02.924368
5506 17:44:02.927522 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5507 17:44:02.927596
5508 17:44:02.930997 [CATrainingPosCal] consider 1 rank data
5509 17:44:02.934146 u2DelayCellTimex100 = 270/100 ps
5510 17:44:02.937670 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5511 17:44:02.944007 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5512 17:44:02.947561 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5513 17:44:02.950909 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5514 17:44:02.954028 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5515 17:44:02.957246 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5516 17:44:02.957321
5517 17:44:02.960435 CA PerBit enable=1, Macro0, CA PI delay=34
5518 17:44:02.960517
5519 17:44:02.963800 [CBTSetCACLKResult] CA Dly = 34
5520 17:44:02.963878 CS Dly: 6 (0~37)
5521 17:44:02.967045 ==
5522 17:44:02.970544 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 17:44:02.973718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 17:44:02.973817 ==
5525 17:44:02.980396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 17:44:02.983604 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5527 17:44:02.987664 [CA 0] Center 38 (7~69) winsize 63
5528 17:44:02.990861 [CA 1] Center 38 (7~69) winsize 63
5529 17:44:02.994563 [CA 2] Center 36 (6~66) winsize 61
5530 17:44:02.997765 [CA 3] Center 36 (6~66) winsize 61
5531 17:44:03.001172 [CA 4] Center 36 (6~66) winsize 61
5532 17:44:03.004165 [CA 5] Center 35 (5~65) winsize 61
5533 17:44:03.004234
5534 17:44:03.007283 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5535 17:44:03.007354
5536 17:44:03.010957 [CATrainingPosCal] consider 2 rank data
5537 17:44:03.014010 u2DelayCellTimex100 = 270/100 ps
5538 17:44:03.017568 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5539 17:44:03.020720 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5540 17:44:03.027396 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5541 17:44:03.031124 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5542 17:44:03.034101 CA4 delay=36 (6~66),Diff = 1 PI (6 cell)
5543 17:44:03.037283 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5544 17:44:03.037352
5545 17:44:03.040801 CA PerBit enable=1, Macro0, CA PI delay=35
5546 17:44:03.040902
5547 17:44:03.043966 [CBTSetCACLKResult] CA Dly = 35
5548 17:44:03.044040 CS Dly: 7 (0~40)
5549 17:44:03.044104
5550 17:44:03.050745 ----->DramcWriteLeveling(PI) begin...
5551 17:44:03.050818 ==
5552 17:44:03.053955 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 17:44:03.057406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 17:44:03.057486 ==
5555 17:44:03.060647 Write leveling (Byte 0): 25 => 25
5556 17:44:03.063757 Write leveling (Byte 1): 27 => 27
5557 17:44:03.067340 DramcWriteLeveling(PI) end<-----
5558 17:44:03.067413
5559 17:44:03.067475 ==
5560 17:44:03.070203 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 17:44:03.073794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 17:44:03.073873 ==
5563 17:44:03.077032 [Gating] SW mode calibration
5564 17:44:03.083609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 17:44:03.090621 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 17:44:03.093801 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 17:44:03.096996 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 17:44:03.103891 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 17:44:03.106872 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 17:44:03.109906 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 17:44:03.116788 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 17:44:03.119859 0 14 24 | B1->B0 | 3232 3232 | 0 0 | (0 1) (1 1)
5573 17:44:03.123248 0 14 28 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5574 17:44:03.130235 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 17:44:03.133531 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 17:44:03.136619 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 17:44:03.143526 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 17:44:03.146690 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 17:44:03.149876 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 17:44:03.156404 0 15 24 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
5581 17:44:03.159793 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5582 17:44:03.163189 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 17:44:03.169813 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 17:44:03.173099 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 17:44:03.176501 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 17:44:03.179905 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 17:44:03.186366 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5588 17:44:03.189821 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5589 17:44:03.193016 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5590 17:44:03.199846 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 17:44:03.202995 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 17:44:03.206343 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 17:44:03.213401 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 17:44:03.216637 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 17:44:03.219596 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 17:44:03.226377 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 17:44:03.229480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 17:44:03.233167 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 17:44:03.239520 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 17:44:03.242658 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 17:44:03.245974 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 17:44:03.252678 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 17:44:03.256435 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5604 17:44:03.259393 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5605 17:44:03.265914 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5606 17:44:03.266025 Total UI for P1: 0, mck2ui 16
5607 17:44:03.272882 best dqsien dly found for B0: ( 1, 2, 22)
5608 17:44:03.276104 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 17:44:03.279343 Total UI for P1: 0, mck2ui 16
5610 17:44:03.282719 best dqsien dly found for B1: ( 1, 2, 28)
5611 17:44:03.285925 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5612 17:44:03.289477 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5613 17:44:03.289556
5614 17:44:03.292625 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5615 17:44:03.296077 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5616 17:44:03.299534 [Gating] SW calibration Done
5617 17:44:03.299642 ==
5618 17:44:03.302852 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 17:44:03.306378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 17:44:03.306449 ==
5621 17:44:03.309558 RX Vref Scan: 0
5622 17:44:03.309627
5623 17:44:03.312509 RX Vref 0 -> 0, step: 1
5624 17:44:03.312584
5625 17:44:03.312646 RX Delay -80 -> 252, step: 8
5626 17:44:03.319619 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5627 17:44:03.322779 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5628 17:44:03.325966 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5629 17:44:03.329360 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5630 17:44:03.332476 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5631 17:44:03.335934 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5632 17:44:03.342472 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5633 17:44:03.345714 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5634 17:44:03.349209 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5635 17:44:03.352600 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5636 17:44:03.355774 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5637 17:44:03.362523 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5638 17:44:03.365662 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5639 17:44:03.368737 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5640 17:44:03.372280 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5641 17:44:03.375898 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5642 17:44:03.376009 ==
5643 17:44:03.379719 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 17:44:03.385802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 17:44:03.385890 ==
5646 17:44:03.385955 DQS Delay:
5647 17:44:03.389202 DQS0 = 0, DQS1 = 0
5648 17:44:03.389285 DQM Delay:
5649 17:44:03.389350 DQM0 = 101, DQM1 = 95
5650 17:44:03.392227 DQ Delay:
5651 17:44:03.395565 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5652 17:44:03.398791 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5653 17:44:03.402308 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5654 17:44:03.405738 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5655 17:44:03.405821
5656 17:44:03.405886
5657 17:44:03.405945 ==
5658 17:44:03.408919 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 17:44:03.412456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 17:44:03.412540 ==
5661 17:44:03.412605
5662 17:44:03.412664
5663 17:44:03.415415 TX Vref Scan disable
5664 17:44:03.418596 == TX Byte 0 ==
5665 17:44:03.422029 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5666 17:44:03.425482 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5667 17:44:03.428671 == TX Byte 1 ==
5668 17:44:03.432255 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 17:44:03.435463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 17:44:03.435546 ==
5671 17:44:03.439123 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 17:44:03.445387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 17:44:03.445471 ==
5674 17:44:03.445536
5675 17:44:03.445597
5676 17:44:03.445654 TX Vref Scan disable
5677 17:44:03.449147 == TX Byte 0 ==
5678 17:44:03.452659 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5679 17:44:03.455737 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5680 17:44:03.458931 == TX Byte 1 ==
5681 17:44:03.462742 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5682 17:44:03.465790 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5683 17:44:03.469079
5684 17:44:03.469160 [DATLAT]
5685 17:44:03.469225 Freq=933, CH1 RK0
5686 17:44:03.469284
5687 17:44:03.472677 DATLAT Default: 0xd
5688 17:44:03.472759 0, 0xFFFF, sum = 0
5689 17:44:03.475799 1, 0xFFFF, sum = 0
5690 17:44:03.475883 2, 0xFFFF, sum = 0
5691 17:44:03.478837 3, 0xFFFF, sum = 0
5692 17:44:03.482135 4, 0xFFFF, sum = 0
5693 17:44:03.482219 5, 0xFFFF, sum = 0
5694 17:44:03.485511 6, 0xFFFF, sum = 0
5695 17:44:03.485594 7, 0xFFFF, sum = 0
5696 17:44:03.488947 8, 0xFFFF, sum = 0
5697 17:44:03.489044 9, 0xFFFF, sum = 0
5698 17:44:03.492327 10, 0x0, sum = 1
5699 17:44:03.492410 11, 0x0, sum = 2
5700 17:44:03.495489 12, 0x0, sum = 3
5701 17:44:03.495572 13, 0x0, sum = 4
5702 17:44:03.495637 best_step = 11
5703 17:44:03.495696
5704 17:44:03.498867 ==
5705 17:44:03.502482 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 17:44:03.505451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 17:44:03.505533 ==
5708 17:44:03.505598 RX Vref Scan: 1
5709 17:44:03.505657
5710 17:44:03.508528 RX Vref 0 -> 0, step: 1
5711 17:44:03.508609
5712 17:44:03.511961 RX Delay -53 -> 252, step: 4
5713 17:44:03.512043
5714 17:44:03.515460 Set Vref, RX VrefLevel [Byte0]: 53
5715 17:44:03.518560 [Byte1]: 57
5716 17:44:03.518642
5717 17:44:03.521886 Final RX Vref Byte 0 = 53 to rank0
5718 17:44:03.525230 Final RX Vref Byte 1 = 57 to rank0
5719 17:44:03.528756 Final RX Vref Byte 0 = 53 to rank1
5720 17:44:03.531984 Final RX Vref Byte 1 = 57 to rank1==
5721 17:44:03.535118 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 17:44:03.538341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 17:44:03.541961 ==
5724 17:44:03.542043 DQS Delay:
5725 17:44:03.542107 DQS0 = 0, DQS1 = 0
5726 17:44:03.545239 DQM Delay:
5727 17:44:03.545321 DQM0 = 104, DQM1 = 97
5728 17:44:03.548319 DQ Delay:
5729 17:44:03.551964 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5730 17:44:03.555164 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5731 17:44:03.558475 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5732 17:44:03.561608 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5733 17:44:03.561690
5734 17:44:03.561754
5735 17:44:03.568607 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5736 17:44:03.571588 CH1 RK0: MR19=505, MR18=152D
5737 17:44:03.578471 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5738 17:44:03.578554
5739 17:44:03.581700 ----->DramcWriteLeveling(PI) begin...
5740 17:44:03.581783 ==
5741 17:44:03.584748 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 17:44:03.588360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 17:44:03.588444 ==
5744 17:44:03.591298 Write leveling (Byte 0): 29 => 29
5745 17:44:03.595224 Write leveling (Byte 1): 27 => 27
5746 17:44:03.597974 DramcWriteLeveling(PI) end<-----
5747 17:44:03.598056
5748 17:44:03.598120 ==
5749 17:44:03.601329 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 17:44:03.607946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 17:44:03.608028 ==
5752 17:44:03.608093 [Gating] SW mode calibration
5753 17:44:03.617737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 17:44:03.621246 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 17:44:03.624701 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5756 17:44:03.631450 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 17:44:03.634718 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 17:44:03.638313 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 17:44:03.644578 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 17:44:03.648124 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 17:44:03.651257 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5762 17:44:03.657710 0 14 28 | B1->B0 | 2424 2c2c | 0 0 | (1 0) (1 0)
5763 17:44:03.661323 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 17:44:03.664428 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 17:44:03.670865 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 17:44:03.674433 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 17:44:03.677662 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 17:44:03.684213 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 17:44:03.688008 0 15 24 | B1->B0 | 2b2b 2323 | 0 1 | (0 0) (0 0)
5770 17:44:03.690886 0 15 28 | B1->B0 | 4141 3939 | 0 0 | (0 0) (0 0)
5771 17:44:03.697724 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5772 17:44:03.700716 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 17:44:03.703980 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 17:44:03.710650 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 17:44:03.714222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 17:44:03.717554 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 17:44:03.724214 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 17:44:03.727308 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5779 17:44:03.730502 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 17:44:03.737218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 17:44:03.740350 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 17:44:03.744034 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 17:44:03.750908 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 17:44:03.753961 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 17:44:03.757082 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 17:44:03.763939 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 17:44:03.766967 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 17:44:03.770630 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 17:44:03.777394 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 17:44:03.780560 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 17:44:03.783929 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 17:44:03.787021 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 17:44:03.793597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 17:44:03.797383 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5795 17:44:03.800513 Total UI for P1: 0, mck2ui 16
5796 17:44:03.803627 best dqsien dly found for B1: ( 1, 2, 26)
5797 17:44:03.807091 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 17:44:03.810419 Total UI for P1: 0, mck2ui 16
5799 17:44:03.813582 best dqsien dly found for B0: ( 1, 2, 28)
5800 17:44:03.817115 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5801 17:44:03.820567 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5802 17:44:03.820641
5803 17:44:03.827197 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5804 17:44:03.830212 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5805 17:44:03.833808 [Gating] SW calibration Done
5806 17:44:03.833890 ==
5807 17:44:03.837155 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 17:44:03.840445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 17:44:03.840528 ==
5810 17:44:03.840594 RX Vref Scan: 0
5811 17:44:03.840655
5812 17:44:03.843629 RX Vref 0 -> 0, step: 1
5813 17:44:03.843712
5814 17:44:03.846709 RX Delay -80 -> 252, step: 8
5815 17:44:03.850162 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5816 17:44:03.853484 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5817 17:44:03.860240 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5818 17:44:03.863353 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5819 17:44:03.866713 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5820 17:44:03.870329 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5821 17:44:03.873334 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5822 17:44:03.876462 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5823 17:44:03.883232 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5824 17:44:03.886658 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5825 17:44:03.890227 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5826 17:44:03.893475 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5827 17:44:03.896529 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5828 17:44:03.899902 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5829 17:44:03.906654 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5830 17:44:03.910215 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5831 17:44:03.910298 ==
5832 17:44:03.913196 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 17:44:03.916681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 17:44:03.916764 ==
5835 17:44:03.919864 DQS Delay:
5836 17:44:03.919946 DQS0 = 0, DQS1 = 0
5837 17:44:03.920010 DQM Delay:
5838 17:44:03.923084 DQM0 = 101, DQM1 = 95
5839 17:44:03.923166 DQ Delay:
5840 17:44:03.926247 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5841 17:44:03.929729 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5842 17:44:03.932765 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5843 17:44:03.936357 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5844 17:44:03.936439
5845 17:44:03.939683
5846 17:44:03.939764 ==
5847 17:44:03.942929 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 17:44:03.946417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 17:44:03.946500 ==
5850 17:44:03.946565
5851 17:44:03.946623
5852 17:44:03.949791 TX Vref Scan disable
5853 17:44:03.949873 == TX Byte 0 ==
5854 17:44:03.955953 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5855 17:44:03.959660 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5856 17:44:03.959742 == TX Byte 1 ==
5857 17:44:03.966180 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5858 17:44:03.969824 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5859 17:44:03.969907 ==
5860 17:44:03.972561 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 17:44:03.976160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 17:44:03.976243 ==
5863 17:44:03.976308
5864 17:44:03.976367
5865 17:44:03.979372 TX Vref Scan disable
5866 17:44:03.982513 == TX Byte 0 ==
5867 17:44:03.985841 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5868 17:44:03.989065 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5869 17:44:03.992694 == TX Byte 1 ==
5870 17:44:03.995755 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5871 17:44:03.999423 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5872 17:44:03.999505
5873 17:44:04.002551 [DATLAT]
5874 17:44:04.002633 Freq=933, CH1 RK1
5875 17:44:04.002698
5876 17:44:04.005785 DATLAT Default: 0xb
5877 17:44:04.005866 0, 0xFFFF, sum = 0
5878 17:44:04.009298 1, 0xFFFF, sum = 0
5879 17:44:04.009382 2, 0xFFFF, sum = 0
5880 17:44:04.012485 3, 0xFFFF, sum = 0
5881 17:44:04.012568 4, 0xFFFF, sum = 0
5882 17:44:04.015834 5, 0xFFFF, sum = 0
5883 17:44:04.015918 6, 0xFFFF, sum = 0
5884 17:44:04.019002 7, 0xFFFF, sum = 0
5885 17:44:04.019085 8, 0xFFFF, sum = 0
5886 17:44:04.022801 9, 0xFFFF, sum = 0
5887 17:44:04.022884 10, 0x0, sum = 1
5888 17:44:04.026045 11, 0x0, sum = 2
5889 17:44:04.026128 12, 0x0, sum = 3
5890 17:44:04.029126 13, 0x0, sum = 4
5891 17:44:04.029209 best_step = 11
5892 17:44:04.029273
5893 17:44:04.029332 ==
5894 17:44:04.032674 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 17:44:04.039059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 17:44:04.039142 ==
5897 17:44:04.039207 RX Vref Scan: 0
5898 17:44:04.039267
5899 17:44:04.042093 RX Vref 0 -> 0, step: 1
5900 17:44:04.042200
5901 17:44:04.045589 RX Delay -53 -> 252, step: 4
5902 17:44:04.048805 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5903 17:44:04.052421 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5904 17:44:04.058694 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5905 17:44:04.061871 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5906 17:44:04.065150 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5907 17:44:04.068426 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5908 17:44:04.071971 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5909 17:44:04.078911 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5910 17:44:04.081660 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5911 17:44:04.085572 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5912 17:44:04.088680 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5913 17:44:04.091894 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5914 17:44:04.098222 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5915 17:44:04.101798 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5916 17:44:04.105113 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5917 17:44:04.108290 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5918 17:44:04.108412 ==
5919 17:44:04.111469 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 17:44:04.118087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 17:44:04.118170 ==
5922 17:44:04.118234 DQS Delay:
5923 17:44:04.121551 DQS0 = 0, DQS1 = 0
5924 17:44:04.121634 DQM Delay:
5925 17:44:04.121699 DQM0 = 104, DQM1 = 97
5926 17:44:04.124780 DQ Delay:
5927 17:44:04.127907 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5928 17:44:04.131355 DQ4 =106, DQ5 =114, DQ6 =110, DQ7 =102
5929 17:44:04.134702 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5930 17:44:04.137995 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5931 17:44:04.138077
5932 17:44:04.138141
5933 17:44:04.144807 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5934 17:44:04.148086 CH1 RK1: MR19=504, MR18=21FE
5935 17:44:04.154373 CH1_RK1: MR19=0x504, MR18=0x21FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5936 17:44:04.158085 [RxdqsGatingPostProcess] freq 933
5937 17:44:04.164409 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5938 17:44:04.167875 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 17:44:04.171436 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 17:44:04.174541 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 17:44:04.177874 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 17:44:04.177950 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 17:44:04.181112 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 17:44:04.184506 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 17:44:04.187651 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 17:44:04.190940 Pre-setting of DQS Precalculation
5947 17:44:04.197808 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5948 17:44:04.204530 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5949 17:44:04.211198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5950 17:44:04.211282
5951 17:44:04.211347
5952 17:44:04.214454 [Calibration Summary] 1866 Mbps
5953 17:44:04.214538 CH 0, Rank 0
5954 17:44:04.217462 SW Impedance : PASS
5955 17:44:04.221048 DUTY Scan : NO K
5956 17:44:04.221131 ZQ Calibration : PASS
5957 17:44:04.224236 Jitter Meter : NO K
5958 17:44:04.227779 CBT Training : PASS
5959 17:44:04.227862 Write leveling : PASS
5960 17:44:04.230982 RX DQS gating : PASS
5961 17:44:04.234187 RX DQ/DQS(RDDQC) : PASS
5962 17:44:04.234269 TX DQ/DQS : PASS
5963 17:44:04.237644 RX DATLAT : PASS
5964 17:44:04.240579 RX DQ/DQS(Engine): PASS
5965 17:44:04.240662 TX OE : NO K
5966 17:44:04.240728 All Pass.
5967 17:44:04.244125
5968 17:44:04.244208 CH 0, Rank 1
5969 17:44:04.247202 SW Impedance : PASS
5970 17:44:04.247285 DUTY Scan : NO K
5971 17:44:04.250776 ZQ Calibration : PASS
5972 17:44:04.250859 Jitter Meter : NO K
5973 17:44:04.254098 CBT Training : PASS
5974 17:44:04.257524 Write leveling : PASS
5975 17:44:04.257633 RX DQS gating : PASS
5976 17:44:04.260621 RX DQ/DQS(RDDQC) : PASS
5977 17:44:04.263972 TX DQ/DQS : PASS
5978 17:44:04.264057 RX DATLAT : PASS
5979 17:44:04.267267 RX DQ/DQS(Engine): PASS
5980 17:44:04.270536 TX OE : NO K
5981 17:44:04.270619 All Pass.
5982 17:44:04.270685
5983 17:44:04.270746 CH 1, Rank 0
5984 17:44:04.273870 SW Impedance : PASS
5985 17:44:04.277248 DUTY Scan : NO K
5986 17:44:04.277348 ZQ Calibration : PASS
5987 17:44:04.280734 Jitter Meter : NO K
5988 17:44:04.284070 CBT Training : PASS
5989 17:44:04.284154 Write leveling : PASS
5990 17:44:04.287044 RX DQS gating : PASS
5991 17:44:04.290326 RX DQ/DQS(RDDQC) : PASS
5992 17:44:04.290409 TX DQ/DQS : PASS
5993 17:44:04.293698 RX DATLAT : PASS
5994 17:44:04.297341 RX DQ/DQS(Engine): PASS
5995 17:44:04.297424 TX OE : NO K
5996 17:44:04.297490 All Pass.
5997 17:44:04.297549
5998 17:44:04.300557 CH 1, Rank 1
5999 17:44:04.300640 SW Impedance : PASS
6000 17:44:04.304230 DUTY Scan : NO K
6001 17:44:04.307241 ZQ Calibration : PASS
6002 17:44:04.307323 Jitter Meter : NO K
6003 17:44:04.310509 CBT Training : PASS
6004 17:44:04.313642 Write leveling : PASS
6005 17:44:04.313725 RX DQS gating : PASS
6006 17:44:04.317354 RX DQ/DQS(RDDQC) : PASS
6007 17:44:04.320860 TX DQ/DQS : PASS
6008 17:44:04.320979 RX DATLAT : PASS
6009 17:44:04.323726 RX DQ/DQS(Engine): PASS
6010 17:44:04.327397 TX OE : NO K
6011 17:44:04.327480 All Pass.
6012 17:44:04.327546
6013 17:44:04.330679 DramC Write-DBI off
6014 17:44:04.330765 PER_BANK_REFRESH: Hybrid Mode
6015 17:44:04.333840 TX_TRACKING: ON
6016 17:44:04.340415 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6017 17:44:04.347056 [FAST_K] Save calibration result to emmc
6018 17:44:04.350329 dramc_set_vcore_voltage set vcore to 650000
6019 17:44:04.350413 Read voltage for 400, 6
6020 17:44:04.353727 Vio18 = 0
6021 17:44:04.353810 Vcore = 650000
6022 17:44:04.353875 Vdram = 0
6023 17:44:04.356866 Vddq = 0
6024 17:44:04.356984 Vmddr = 0
6025 17:44:04.360484 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6026 17:44:04.367093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6027 17:44:04.370230 MEM_TYPE=3, freq_sel=20
6028 17:44:04.373520 sv_algorithm_assistance_LP4_800
6029 17:44:04.376758 ============ PULL DRAM RESETB DOWN ============
6030 17:44:04.380372 ========== PULL DRAM RESETB DOWN end =========
6031 17:44:04.383575 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6032 17:44:04.386736 ===================================
6033 17:44:04.390044 LPDDR4 DRAM CONFIGURATION
6034 17:44:04.393586 ===================================
6035 17:44:04.396858 EX_ROW_EN[0] = 0x0
6036 17:44:04.396948 EX_ROW_EN[1] = 0x0
6037 17:44:04.400227 LP4Y_EN = 0x0
6038 17:44:04.400311 WORK_FSP = 0x0
6039 17:44:04.403540 WL = 0x2
6040 17:44:04.403623 RL = 0x2
6041 17:44:04.406716 BL = 0x2
6042 17:44:04.406798 RPST = 0x0
6043 17:44:04.410119 RD_PRE = 0x0
6044 17:44:04.413229 WR_PRE = 0x1
6045 17:44:04.413311 WR_PST = 0x0
6046 17:44:04.416747 DBI_WR = 0x0
6047 17:44:04.416830 DBI_RD = 0x0
6048 17:44:04.419914 OTF = 0x1
6049 17:44:04.423255 ===================================
6050 17:44:04.426769 ===================================
6051 17:44:04.426852 ANA top config
6052 17:44:04.429934 ===================================
6053 17:44:04.433250 DLL_ASYNC_EN = 0
6054 17:44:04.436448 ALL_SLAVE_EN = 1
6055 17:44:04.436530 NEW_RANK_MODE = 1
6056 17:44:04.439979 DLL_IDLE_MODE = 1
6057 17:44:04.443220 LP45_APHY_COMB_EN = 1
6058 17:44:04.446689 TX_ODT_DIS = 1
6059 17:44:04.446772 NEW_8X_MODE = 1
6060 17:44:04.449808 ===================================
6061 17:44:04.453368 ===================================
6062 17:44:04.456543 data_rate = 800
6063 17:44:04.459642 CKR = 1
6064 17:44:04.463201 DQ_P2S_RATIO = 4
6065 17:44:04.466326 ===================================
6066 17:44:04.470035 CA_P2S_RATIO = 4
6067 17:44:04.472977 DQ_CA_OPEN = 0
6068 17:44:04.473060 DQ_SEMI_OPEN = 1
6069 17:44:04.476416 CA_SEMI_OPEN = 1
6070 17:44:04.479902 CA_FULL_RATE = 0
6071 17:44:04.483322 DQ_CKDIV4_EN = 0
6072 17:44:04.486720 CA_CKDIV4_EN = 1
6073 17:44:04.489888 CA_PREDIV_EN = 0
6074 17:44:04.489971 PH8_DLY = 0
6075 17:44:04.493215 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6076 17:44:04.496226 DQ_AAMCK_DIV = 0
6077 17:44:04.499697 CA_AAMCK_DIV = 0
6078 17:44:04.503118 CA_ADMCK_DIV = 4
6079 17:44:04.506559 DQ_TRACK_CA_EN = 0
6080 17:44:04.506641 CA_PICK = 800
6081 17:44:04.509572 CA_MCKIO = 400
6082 17:44:04.513116 MCKIO_SEMI = 400
6083 17:44:04.516258 PLL_FREQ = 3016
6084 17:44:04.519847 DQ_UI_PI_RATIO = 32
6085 17:44:04.522814 CA_UI_PI_RATIO = 32
6086 17:44:04.526386 ===================================
6087 17:44:04.529720 ===================================
6088 17:44:04.532760 memory_type:LPDDR4
6089 17:44:04.532841 GP_NUM : 10
6090 17:44:04.536434 SRAM_EN : 1
6091 17:44:04.536516 MD32_EN : 0
6092 17:44:04.539770 ===================================
6093 17:44:04.542959 [ANA_INIT] >>>>>>>>>>>>>>
6094 17:44:04.546110 <<<<<< [CONFIGURE PHASE]: ANA_TX
6095 17:44:04.549282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6096 17:44:04.552794 ===================================
6097 17:44:04.556183 data_rate = 800,PCW = 0X7400
6098 17:44:04.559324 ===================================
6099 17:44:04.562580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6100 17:44:04.566338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 17:44:04.579464 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 17:44:04.582435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6103 17:44:04.586210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6104 17:44:04.589200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6105 17:44:04.592435 [ANA_INIT] flow start
6106 17:44:04.595703 [ANA_INIT] PLL >>>>>>>>
6107 17:44:04.595776 [ANA_INIT] PLL <<<<<<<<
6108 17:44:04.599246 [ANA_INIT] MIDPI >>>>>>>>
6109 17:44:04.602325 [ANA_INIT] MIDPI <<<<<<<<
6110 17:44:04.606012 [ANA_INIT] DLL >>>>>>>>
6111 17:44:04.606090 [ANA_INIT] flow end
6112 17:44:04.609088 ============ LP4 DIFF to SE enter ============
6113 17:44:04.615868 ============ LP4 DIFF to SE exit ============
6114 17:44:04.615945 [ANA_INIT] <<<<<<<<<<<<<
6115 17:44:04.618892 [Flow] Enable top DCM control >>>>>
6116 17:44:04.622509 [Flow] Enable top DCM control <<<<<
6117 17:44:04.625732 Enable DLL master slave shuffle
6118 17:44:04.632471 ==============================================================
6119 17:44:04.632549 Gating Mode config
6120 17:44:04.639110 ==============================================================
6121 17:44:04.642311 Config description:
6122 17:44:04.649009 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6123 17:44:04.658716 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6124 17:44:04.662084 SELPH_MODE 0: By rank 1: By Phase
6125 17:44:04.668387 ==============================================================
6126 17:44:04.671849 GAT_TRACK_EN = 0
6127 17:44:04.671940 RX_GATING_MODE = 2
6128 17:44:04.675434 RX_GATING_TRACK_MODE = 2
6129 17:44:04.678640 SELPH_MODE = 1
6130 17:44:04.681872 PICG_EARLY_EN = 1
6131 17:44:04.684874 VALID_LAT_VALUE = 1
6132 17:44:04.691528 ==============================================================
6133 17:44:04.694899 Enter into Gating configuration >>>>
6134 17:44:04.698329 Exit from Gating configuration <<<<
6135 17:44:04.701490 Enter into DVFS_PRE_config >>>>>
6136 17:44:04.711493 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6137 17:44:04.714688 Exit from DVFS_PRE_config <<<<<
6138 17:44:04.718158 Enter into PICG configuration >>>>
6139 17:44:04.721761 Exit from PICG configuration <<<<
6140 17:44:04.724861 [RX_INPUT] configuration >>>>>
6141 17:44:04.728464 [RX_INPUT] configuration <<<<<
6142 17:44:04.731277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6143 17:44:04.738102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6144 17:44:04.744834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 17:44:04.751186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 17:44:04.754373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 17:44:04.761050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 17:44:04.764404 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6149 17:44:04.771104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6150 17:44:04.774156 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6151 17:44:04.777599 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6152 17:44:04.780787 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6153 17:44:04.787688 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 17:44:04.790695 ===================================
6155 17:44:04.794252 LPDDR4 DRAM CONFIGURATION
6156 17:44:04.797324 ===================================
6157 17:44:04.797399 EX_ROW_EN[0] = 0x0
6158 17:44:04.800925 EX_ROW_EN[1] = 0x0
6159 17:44:04.801001 LP4Y_EN = 0x0
6160 17:44:04.804052 WORK_FSP = 0x0
6161 17:44:04.804134 WL = 0x2
6162 17:44:04.807739 RL = 0x2
6163 17:44:04.807822 BL = 0x2
6164 17:44:04.811081 RPST = 0x0
6165 17:44:04.811164 RD_PRE = 0x0
6166 17:44:04.813980 WR_PRE = 0x1
6167 17:44:04.814063 WR_PST = 0x0
6168 17:44:04.817635 DBI_WR = 0x0
6169 17:44:04.817718 DBI_RD = 0x0
6170 17:44:04.820811 OTF = 0x1
6171 17:44:04.823911 ===================================
6172 17:44:04.827445 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6173 17:44:04.830669 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6174 17:44:04.837404 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 17:44:04.840514 ===================================
6176 17:44:04.840597 LPDDR4 DRAM CONFIGURATION
6177 17:44:04.843640 ===================================
6178 17:44:04.846855 EX_ROW_EN[0] = 0x10
6179 17:44:04.850498 EX_ROW_EN[1] = 0x0
6180 17:44:04.850571 LP4Y_EN = 0x0
6181 17:44:04.853610 WORK_FSP = 0x0
6182 17:44:04.853687 WL = 0x2
6183 17:44:04.856751 RL = 0x2
6184 17:44:04.856825 BL = 0x2
6185 17:44:04.860544 RPST = 0x0
6186 17:44:04.860618 RD_PRE = 0x0
6187 17:44:04.863471 WR_PRE = 0x1
6188 17:44:04.863592 WR_PST = 0x0
6189 17:44:04.866933 DBI_WR = 0x0
6190 17:44:04.867017 DBI_RD = 0x0
6191 17:44:04.870267 OTF = 0x1
6192 17:44:04.873696 ===================================
6193 17:44:04.880357 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6194 17:44:04.883472 nWR fixed to 30
6195 17:44:04.886868 [ModeRegInit_LP4] CH0 RK0
6196 17:44:04.886943 [ModeRegInit_LP4] CH0 RK1
6197 17:44:04.889915 [ModeRegInit_LP4] CH1 RK0
6198 17:44:04.893463 [ModeRegInit_LP4] CH1 RK1
6199 17:44:04.893536 match AC timing 19
6200 17:44:04.899862 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6201 17:44:04.903642 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6202 17:44:04.906953 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6203 17:44:04.913290 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6204 17:44:04.916590 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6205 17:44:04.916700 ==
6206 17:44:04.919857 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 17:44:04.923163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 17:44:04.923238 ==
6209 17:44:04.929982 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 17:44:04.936571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6211 17:44:04.939712 [CA 0] Center 36 (8~64) winsize 57
6212 17:44:04.943167 [CA 1] Center 36 (8~64) winsize 57
6213 17:44:04.946308 [CA 2] Center 36 (8~64) winsize 57
6214 17:44:04.949497 [CA 3] Center 36 (8~64) winsize 57
6215 17:44:04.949574 [CA 4] Center 36 (8~64) winsize 57
6216 17:44:04.953116 [CA 5] Center 36 (8~64) winsize 57
6217 17:44:04.953192
6218 17:44:04.959527 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6219 17:44:04.959605
6220 17:44:04.962976 [CATrainingPosCal] consider 1 rank data
6221 17:44:04.966620 u2DelayCellTimex100 = 270/100 ps
6222 17:44:04.969496 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 17:44:04.972759 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 17:44:04.976228 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 17:44:04.979386 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 17:44:04.982896 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 17:44:04.985976 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 17:44:04.986050
6229 17:44:04.989609 CA PerBit enable=1, Macro0, CA PI delay=36
6230 17:44:04.989683
6231 17:44:04.992774 [CBTSetCACLKResult] CA Dly = 36
6232 17:44:04.996165 CS Dly: 1 (0~32)
6233 17:44:04.996241 ==
6234 17:44:04.999266 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 17:44:05.002712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 17:44:05.002811 ==
6237 17:44:05.009427 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 17:44:05.016098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6239 17:44:05.016175 [CA 0] Center 36 (8~64) winsize 57
6240 17:44:05.019466 [CA 1] Center 36 (8~64) winsize 57
6241 17:44:05.022580 [CA 2] Center 36 (8~64) winsize 57
6242 17:44:05.026040 [CA 3] Center 36 (8~64) winsize 57
6243 17:44:05.029192 [CA 4] Center 36 (8~64) winsize 57
6244 17:44:05.032417 [CA 5] Center 36 (8~64) winsize 57
6245 17:44:05.032518
6246 17:44:05.035697 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6247 17:44:05.035769
6248 17:44:05.039462 [CATrainingPosCal] consider 2 rank data
6249 17:44:05.042532 u2DelayCellTimex100 = 270/100 ps
6250 17:44:05.045557 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 17:44:05.052454 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 17:44:05.055597 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 17:44:05.058912 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 17:44:05.062163 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 17:44:05.065713 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 17:44:05.065830
6257 17:44:05.068919 CA PerBit enable=1, Macro0, CA PI delay=36
6258 17:44:05.069055
6259 17:44:05.072050 [CBTSetCACLKResult] CA Dly = 36
6260 17:44:05.072162 CS Dly: 1 (0~32)
6261 17:44:05.075576
6262 17:44:05.078746 ----->DramcWriteLeveling(PI) begin...
6263 17:44:05.078830 ==
6264 17:44:05.082322 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 17:44:05.085431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 17:44:05.085514 ==
6267 17:44:05.088939 Write leveling (Byte 0): 40 => 8
6268 17:44:05.092210 Write leveling (Byte 1): 32 => 0
6269 17:44:05.095475 DramcWriteLeveling(PI) end<-----
6270 17:44:05.095557
6271 17:44:05.095621 ==
6272 17:44:05.098893 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 17:44:05.102265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 17:44:05.102348 ==
6275 17:44:05.105382 [Gating] SW mode calibration
6276 17:44:05.112308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 17:44:05.118538 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6278 17:44:05.122028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 17:44:05.125329 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 17:44:05.132030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 17:44:05.135579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 17:44:05.138618 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 17:44:05.145301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 17:44:05.148468 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 17:44:05.152114 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 17:44:05.158227 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 17:44:05.158311 Total UI for P1: 0, mck2ui 16
6288 17:44:05.161839 best dqsien dly found for B0: ( 0, 14, 24)
6289 17:44:05.165048 Total UI for P1: 0, mck2ui 16
6290 17:44:05.168552 best dqsien dly found for B1: ( 0, 14, 24)
6291 17:44:05.174973 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6292 17:44:05.178370 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6293 17:44:05.178452
6294 17:44:05.181538 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 17:44:05.184912 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 17:44:05.188158 [Gating] SW calibration Done
6297 17:44:05.188272 ==
6298 17:44:05.191675 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 17:44:05.194881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 17:44:05.194964 ==
6301 17:44:05.198615 RX Vref Scan: 0
6302 17:44:05.198697
6303 17:44:05.198760 RX Vref 0 -> 0, step: 1
6304 17:44:05.198820
6305 17:44:05.201824 RX Delay -410 -> 252, step: 16
6306 17:44:05.204910 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6307 17:44:05.211557 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6308 17:44:05.214785 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6309 17:44:05.218495 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6310 17:44:05.221659 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6311 17:44:05.228404 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6312 17:44:05.231841 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6313 17:44:05.234782 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6314 17:44:05.238196 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6315 17:44:05.244790 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6316 17:44:05.248518 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6317 17:44:05.251383 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6318 17:44:05.255025 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6319 17:44:05.261477 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6320 17:44:05.264809 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6321 17:44:05.268431 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6322 17:44:05.268512 ==
6323 17:44:05.271442 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 17:44:05.277895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 17:44:05.277977 ==
6326 17:44:05.278042 DQS Delay:
6327 17:44:05.281472 DQS0 = 27, DQS1 = 43
6328 17:44:05.281554 DQM Delay:
6329 17:44:05.281619 DQM0 = 11, DQM1 = 12
6330 17:44:05.284789 DQ Delay:
6331 17:44:05.288058 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6332 17:44:05.291174 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6333 17:44:05.291256 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6334 17:44:05.294827 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6335 17:44:05.297817
6336 17:44:05.297897
6337 17:44:05.297960 ==
6338 17:44:05.301548 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 17:44:05.304744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 17:44:05.304849 ==
6341 17:44:05.304948
6342 17:44:05.305012
6343 17:44:05.307825 TX Vref Scan disable
6344 17:44:05.307905 == TX Byte 0 ==
6345 17:44:05.311013 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 17:44:05.318063 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 17:44:05.318149 == TX Byte 1 ==
6348 17:44:05.321228 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6349 17:44:05.327814 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6350 17:44:05.327896 ==
6351 17:44:05.331311 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 17:44:05.334454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 17:44:05.334536 ==
6354 17:44:05.334599
6355 17:44:05.334659
6356 17:44:05.337779 TX Vref Scan disable
6357 17:44:05.337860 == TX Byte 0 ==
6358 17:44:05.344491 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 17:44:05.347490 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 17:44:05.347572 == TX Byte 1 ==
6361 17:44:05.354360 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6362 17:44:05.357703 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6363 17:44:05.357787
6364 17:44:05.357852 [DATLAT]
6365 17:44:05.360840 Freq=400, CH0 RK0
6366 17:44:05.360924
6367 17:44:05.361040 DATLAT Default: 0xf
6368 17:44:05.364399 0, 0xFFFF, sum = 0
6369 17:44:05.364484 1, 0xFFFF, sum = 0
6370 17:44:05.367613 2, 0xFFFF, sum = 0
6371 17:44:05.367698 3, 0xFFFF, sum = 0
6372 17:44:05.370903 4, 0xFFFF, sum = 0
6373 17:44:05.370988 5, 0xFFFF, sum = 0
6374 17:44:05.374282 6, 0xFFFF, sum = 0
6375 17:44:05.374366 7, 0xFFFF, sum = 0
6376 17:44:05.377422 8, 0xFFFF, sum = 0
6377 17:44:05.377506 9, 0xFFFF, sum = 0
6378 17:44:05.380728 10, 0xFFFF, sum = 0
6379 17:44:05.384060 11, 0xFFFF, sum = 0
6380 17:44:05.384144 12, 0xFFFF, sum = 0
6381 17:44:05.387274 13, 0x0, sum = 1
6382 17:44:05.387359 14, 0x0, sum = 2
6383 17:44:05.387427 15, 0x0, sum = 3
6384 17:44:05.390753 16, 0x0, sum = 4
6385 17:44:05.390837 best_step = 14
6386 17:44:05.390903
6387 17:44:05.394078 ==
6388 17:44:05.394162 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 17:44:05.400717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 17:44:05.400802 ==
6391 17:44:05.400893 RX Vref Scan: 1
6392 17:44:05.400977
6393 17:44:05.403967 RX Vref 0 -> 0, step: 1
6394 17:44:05.404050
6395 17:44:05.407347 RX Delay -327 -> 252, step: 8
6396 17:44:05.407431
6397 17:44:05.410632 Set Vref, RX VrefLevel [Byte0]: 59
6398 17:44:05.413868 [Byte1]: 48
6399 17:44:05.417495
6400 17:44:05.417579 Final RX Vref Byte 0 = 59 to rank0
6401 17:44:05.420841 Final RX Vref Byte 1 = 48 to rank0
6402 17:44:05.424021 Final RX Vref Byte 0 = 59 to rank1
6403 17:44:05.427160 Final RX Vref Byte 1 = 48 to rank1==
6404 17:44:05.430910 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 17:44:05.437234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 17:44:05.437317 ==
6407 17:44:05.437382 DQS Delay:
6408 17:44:05.440633 DQS0 = 28, DQS1 = 48
6409 17:44:05.440715 DQM Delay:
6410 17:44:05.440781 DQM0 = 12, DQM1 = 16
6411 17:44:05.443866 DQ Delay:
6412 17:44:05.447512 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =12
6413 17:44:05.447595 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6414 17:44:05.450699 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6415 17:44:05.453762 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6416 17:44:05.457411
6417 17:44:05.457493
6418 17:44:05.463729 [DQSOSCAuto] RK0, (LSB)MR18= 0x9e97, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6419 17:44:05.467240 CH0 RK0: MR19=C0C, MR18=9E97
6420 17:44:05.473917 CH0_RK0: MR19=0xC0C, MR18=0x9E97, DQSOSC=390, MR23=63, INC=388, DEC=258
6421 17:44:05.474027 ==
6422 17:44:05.477047 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 17:44:05.480615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 17:44:05.480698 ==
6425 17:44:05.483854 [Gating] SW mode calibration
6426 17:44:05.490629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 17:44:05.497306 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6428 17:44:05.500793 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 17:44:05.503989 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 17:44:05.510660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 17:44:05.513763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 17:44:05.516855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 17:44:05.520508 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 17:44:05.526976 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 17:44:05.530122 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 17:44:05.533648 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 17:44:05.536753 Total UI for P1: 0, mck2ui 16
6438 17:44:05.540028 best dqsien dly found for B0: ( 0, 14, 24)
6439 17:44:05.543685 Total UI for P1: 0, mck2ui 16
6440 17:44:05.546685 best dqsien dly found for B1: ( 0, 14, 24)
6441 17:44:05.550139 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6442 17:44:05.556536 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6443 17:44:05.556621
6444 17:44:05.560276 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 17:44:05.563247 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 17:44:05.566586 [Gating] SW calibration Done
6447 17:44:05.566684 ==
6448 17:44:05.570001 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 17:44:05.573300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 17:44:05.573386 ==
6451 17:44:05.576645 RX Vref Scan: 0
6452 17:44:05.576730
6453 17:44:05.576832 RX Vref 0 -> 0, step: 1
6454 17:44:05.576937
6455 17:44:05.580095 RX Delay -410 -> 252, step: 16
6456 17:44:05.583576 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6457 17:44:05.589774 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6458 17:44:05.593524 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6459 17:44:05.596516 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6460 17:44:05.599770 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6461 17:44:05.606249 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6462 17:44:05.610041 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6463 17:44:05.613076 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6464 17:44:05.616252 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6465 17:44:05.623267 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6466 17:44:05.626244 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6467 17:44:05.629655 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6468 17:44:05.636194 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6469 17:44:05.639724 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6470 17:44:05.643040 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6471 17:44:05.646198 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6472 17:44:05.646274 ==
6473 17:44:05.649638 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 17:44:05.656007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 17:44:05.656091 ==
6476 17:44:05.656158 DQS Delay:
6477 17:44:05.659341 DQS0 = 27, DQS1 = 43
6478 17:44:05.659416 DQM Delay:
6479 17:44:05.659477 DQM0 = 10, DQM1 = 15
6480 17:44:05.662907 DQ Delay:
6481 17:44:05.666046 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6482 17:44:05.669501 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6483 17:44:05.669583 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6484 17:44:05.673068 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6485 17:44:05.676013
6486 17:44:05.676116
6487 17:44:05.676208 ==
6488 17:44:05.679634 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 17:44:05.682648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 17:44:05.682723 ==
6491 17:44:05.682784
6492 17:44:05.682848
6493 17:44:05.686245 TX Vref Scan disable
6494 17:44:05.686346 == TX Byte 0 ==
6495 17:44:05.689416 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6496 17:44:05.696346 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6497 17:44:05.696428 == TX Byte 1 ==
6498 17:44:05.699361 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6499 17:44:05.706197 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6500 17:44:05.706279 ==
6501 17:44:05.709734 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 17:44:05.712892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 17:44:05.713009 ==
6504 17:44:05.713074
6505 17:44:05.713133
6506 17:44:05.715983 TX Vref Scan disable
6507 17:44:05.716065 == TX Byte 0 ==
6508 17:44:05.719649 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6509 17:44:05.725959 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6510 17:44:05.726042 == TX Byte 1 ==
6511 17:44:05.729603 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6512 17:44:05.735999 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6513 17:44:05.736082
6514 17:44:05.736146 [DATLAT]
6515 17:44:05.736221 Freq=400, CH0 RK1
6516 17:44:05.736292
6517 17:44:05.739326 DATLAT Default: 0xe
6518 17:44:05.742630 0, 0xFFFF, sum = 0
6519 17:44:05.742713 1, 0xFFFF, sum = 0
6520 17:44:05.746113 2, 0xFFFF, sum = 0
6521 17:44:05.746196 3, 0xFFFF, sum = 0
6522 17:44:05.749288 4, 0xFFFF, sum = 0
6523 17:44:05.749371 5, 0xFFFF, sum = 0
6524 17:44:05.752453 6, 0xFFFF, sum = 0
6525 17:44:05.752536 7, 0xFFFF, sum = 0
6526 17:44:05.755795 8, 0xFFFF, sum = 0
6527 17:44:05.755949 9, 0xFFFF, sum = 0
6528 17:44:05.759334 10, 0xFFFF, sum = 0
6529 17:44:05.759418 11, 0xFFFF, sum = 0
6530 17:44:05.762461 12, 0xFFFF, sum = 0
6531 17:44:05.762543 13, 0x0, sum = 1
6532 17:44:05.765769 14, 0x0, sum = 2
6533 17:44:05.765853 15, 0x0, sum = 3
6534 17:44:05.769014 16, 0x0, sum = 4
6535 17:44:05.769097 best_step = 14
6536 17:44:05.769212
6537 17:44:05.769298 ==
6538 17:44:05.772467 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 17:44:05.779094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 17:44:05.779177 ==
6541 17:44:05.779299 RX Vref Scan: 0
6542 17:44:05.779373
6543 17:44:05.782363 RX Vref 0 -> 0, step: 1
6544 17:44:05.782460
6545 17:44:05.785467 RX Delay -327 -> 252, step: 8
6546 17:44:05.792127 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6547 17:44:05.795907 iDelay=217, Bit 1, Center -20 (-247 ~ 208) 456
6548 17:44:05.799017 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6549 17:44:05.802020 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6550 17:44:05.808803 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6551 17:44:05.812438 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6552 17:44:05.815552 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6553 17:44:05.818892 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6554 17:44:05.825628 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6555 17:44:05.828897 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6556 17:44:05.832334 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6557 17:44:05.835303 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6558 17:44:05.842174 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6559 17:44:05.845659 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6560 17:44:05.848813 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6561 17:44:05.851949 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6562 17:44:05.852032 ==
6563 17:44:05.855328 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 17:44:05.861946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 17:44:05.862030 ==
6566 17:44:05.862096 DQS Delay:
6567 17:44:05.865116 DQS0 = 28, DQS1 = 44
6568 17:44:05.865204 DQM Delay:
6569 17:44:05.868874 DQM0 = 9, DQM1 = 15
6570 17:44:05.868993 DQ Delay:
6571 17:44:05.871851 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6572 17:44:05.875124 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6573 17:44:05.875207 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6574 17:44:05.881935 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6575 17:44:05.882019
6576 17:44:05.882085
6577 17:44:05.888456 [DQSOSCAuto] RK1, (LSB)MR18= 0xb265, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 387 ps
6578 17:44:05.891696 CH0 RK1: MR19=C0C, MR18=B265
6579 17:44:05.898831 CH0_RK1: MR19=0xC0C, MR18=0xB265, DQSOSC=387, MR23=63, INC=394, DEC=262
6580 17:44:05.901718 [RxdqsGatingPostProcess] freq 400
6581 17:44:05.904924 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6582 17:44:05.908540 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 17:44:05.911604 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 17:44:05.915004 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 17:44:05.918471 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 17:44:05.921660 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 17:44:05.925210 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 17:44:05.928425 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 17:44:05.931540 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 17:44:05.934927 Pre-setting of DQS Precalculation
6591 17:44:05.938565 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6592 17:44:05.938649 ==
6593 17:44:05.941612 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 17:44:05.948199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 17:44:05.948283 ==
6596 17:44:05.951671 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 17:44:05.958183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6598 17:44:05.961587 [CA 0] Center 36 (8~64) winsize 57
6599 17:44:05.964575 [CA 1] Center 36 (8~64) winsize 57
6600 17:44:05.968113 [CA 2] Center 36 (8~64) winsize 57
6601 17:44:05.971257 [CA 3] Center 36 (8~64) winsize 57
6602 17:44:05.974849 [CA 4] Center 36 (8~64) winsize 57
6603 17:44:05.978118 [CA 5] Center 36 (8~64) winsize 57
6604 17:44:05.978202
6605 17:44:05.981631 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6606 17:44:05.981715
6607 17:44:05.984601 [CATrainingPosCal] consider 1 rank data
6608 17:44:05.987974 u2DelayCellTimex100 = 270/100 ps
6609 17:44:05.991607 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 17:44:05.995116 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 17:44:05.998021 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 17:44:06.001171 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 17:44:06.004658 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 17:44:06.008209 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 17:44:06.008293
6616 17:44:06.014524 CA PerBit enable=1, Macro0, CA PI delay=36
6617 17:44:06.014608
6618 17:44:06.017686 [CBTSetCACLKResult] CA Dly = 36
6619 17:44:06.017770 CS Dly: 1 (0~32)
6620 17:44:06.017836 ==
6621 17:44:06.021104 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 17:44:06.024341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 17:44:06.024427 ==
6624 17:44:06.031126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 17:44:06.037912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6626 17:44:06.041239 [CA 0] Center 36 (8~64) winsize 57
6627 17:44:06.044407 [CA 1] Center 36 (8~64) winsize 57
6628 17:44:06.047873 [CA 2] Center 36 (8~64) winsize 57
6629 17:44:06.051247 [CA 3] Center 36 (8~64) winsize 57
6630 17:44:06.054626 [CA 4] Center 36 (8~64) winsize 57
6631 17:44:06.054708 [CA 5] Center 36 (8~64) winsize 57
6632 17:44:06.054773
6633 17:44:06.061113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6634 17:44:06.061195
6635 17:44:06.064723 [CATrainingPosCal] consider 2 rank data
6636 17:44:06.067853 u2DelayCellTimex100 = 270/100 ps
6637 17:44:06.071172 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 17:44:06.074496 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 17:44:06.077877 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 17:44:06.080908 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 17:44:06.084438 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 17:44:06.087551 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 17:44:06.087633
6644 17:44:06.090927 CA PerBit enable=1, Macro0, CA PI delay=36
6645 17:44:06.091010
6646 17:44:06.094453 [CBTSetCACLKResult] CA Dly = 36
6647 17:44:06.097996 CS Dly: 1 (0~32)
6648 17:44:06.098079
6649 17:44:06.101249 ----->DramcWriteLeveling(PI) begin...
6650 17:44:06.101332 ==
6651 17:44:06.104413 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 17:44:06.107608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 17:44:06.107706 ==
6654 17:44:06.110820 Write leveling (Byte 0): 40 => 8
6655 17:44:06.114024 Write leveling (Byte 1): 32 => 0
6656 17:44:06.117617 DramcWriteLeveling(PI) end<-----
6657 17:44:06.117721
6658 17:44:06.117800 ==
6659 17:44:06.120667 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 17:44:06.124246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 17:44:06.124343 ==
6662 17:44:06.127445 [Gating] SW mode calibration
6663 17:44:06.133920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6664 17:44:06.140492 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6665 17:44:06.143837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 17:44:06.150373 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 17:44:06.153683 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 17:44:06.156990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 17:44:06.160627 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 17:44:06.167131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 17:44:06.170263 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 17:44:06.173748 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 17:44:06.180592 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 17:44:06.183570 Total UI for P1: 0, mck2ui 16
6675 17:44:06.187282 best dqsien dly found for B0: ( 0, 14, 24)
6676 17:44:06.190274 Total UI for P1: 0, mck2ui 16
6677 17:44:06.193525 best dqsien dly found for B1: ( 0, 14, 24)
6678 17:44:06.196809 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6679 17:44:06.200053 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6680 17:44:06.200181
6681 17:44:06.203590 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 17:44:06.206703 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 17:44:06.210050 [Gating] SW calibration Done
6684 17:44:06.210158 ==
6685 17:44:06.213449 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 17:44:06.216571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 17:44:06.216653 ==
6688 17:44:06.220115 RX Vref Scan: 0
6689 17:44:06.220227
6690 17:44:06.223643 RX Vref 0 -> 0, step: 1
6691 17:44:06.223727
6692 17:44:06.223792 RX Delay -410 -> 252, step: 16
6693 17:44:06.230241 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6694 17:44:06.233239 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6695 17:44:06.236762 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6696 17:44:06.240116 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6697 17:44:06.246681 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6698 17:44:06.249963 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6699 17:44:06.253318 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6700 17:44:06.256840 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6701 17:44:06.267074 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6702 17:44:06.267161 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6703 17:44:06.269928 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6704 17:44:06.273482 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6705 17:44:06.280043 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6706 17:44:06.283231 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6707 17:44:06.286409 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6708 17:44:06.293015 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6709 17:44:06.293099 ==
6710 17:44:06.296326 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 17:44:06.299704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 17:44:06.299789 ==
6713 17:44:06.299855 DQS Delay:
6714 17:44:06.303109 DQS0 = 27, DQS1 = 43
6715 17:44:06.303192 DQM Delay:
6716 17:44:06.306303 DQM0 = 6, DQM1 = 17
6717 17:44:06.306413 DQ Delay:
6718 17:44:06.309847 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6719 17:44:06.313007 DQ4 =0, DQ5 =24, DQ6 =16, DQ7 =0
6720 17:44:06.316152 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6721 17:44:06.319739 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6722 17:44:06.319822
6723 17:44:06.319887
6724 17:44:06.319945 ==
6725 17:44:06.323129 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 17:44:06.326510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 17:44:06.326593 ==
6728 17:44:06.326658
6729 17:44:06.326718
6730 17:44:06.329524 TX Vref Scan disable
6731 17:44:06.329607 == TX Byte 0 ==
6732 17:44:06.336611 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 17:44:06.339735 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 17:44:06.339820 == TX Byte 1 ==
6735 17:44:06.345994 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6736 17:44:06.349553 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6737 17:44:06.349637 ==
6738 17:44:06.352605 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 17:44:06.356167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 17:44:06.356252 ==
6741 17:44:06.356318
6742 17:44:06.356378
6743 17:44:06.359362 TX Vref Scan disable
6744 17:44:06.362741 == TX Byte 0 ==
6745 17:44:06.366011 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 17:44:06.369189 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 17:44:06.372673 == TX Byte 1 ==
6748 17:44:06.376177 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6749 17:44:06.379423 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6750 17:44:06.379507
6751 17:44:06.379572 [DATLAT]
6752 17:44:06.382830 Freq=400, CH1 RK0
6753 17:44:06.382914
6754 17:44:06.382979 DATLAT Default: 0xf
6755 17:44:06.385937 0, 0xFFFF, sum = 0
6756 17:44:06.389158 1, 0xFFFF, sum = 0
6757 17:44:06.389244 2, 0xFFFF, sum = 0
6758 17:44:06.392383 3, 0xFFFF, sum = 0
6759 17:44:06.392467 4, 0xFFFF, sum = 0
6760 17:44:06.395767 5, 0xFFFF, sum = 0
6761 17:44:06.395852 6, 0xFFFF, sum = 0
6762 17:44:06.399102 7, 0xFFFF, sum = 0
6763 17:44:06.399187 8, 0xFFFF, sum = 0
6764 17:44:06.402484 9, 0xFFFF, sum = 0
6765 17:44:06.402570 10, 0xFFFF, sum = 0
6766 17:44:06.405782 11, 0xFFFF, sum = 0
6767 17:44:06.405867 12, 0xFFFF, sum = 0
6768 17:44:06.408894 13, 0x0, sum = 1
6769 17:44:06.408984 14, 0x0, sum = 2
6770 17:44:06.412258 15, 0x0, sum = 3
6771 17:44:06.412342 16, 0x0, sum = 4
6772 17:44:06.415491 best_step = 14
6773 17:44:06.415574
6774 17:44:06.415639 ==
6775 17:44:06.419278 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 17:44:06.422491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 17:44:06.422574 ==
6778 17:44:06.425651 RX Vref Scan: 1
6779 17:44:06.425733
6780 17:44:06.425797 RX Vref 0 -> 0, step: 1
6781 17:44:06.425857
6782 17:44:06.429116 RX Delay -327 -> 252, step: 8
6783 17:44:06.429198
6784 17:44:06.432351 Set Vref, RX VrefLevel [Byte0]: 53
6785 17:44:06.435568 [Byte1]: 57
6786 17:44:06.439717
6787 17:44:06.439799 Final RX Vref Byte 0 = 53 to rank0
6788 17:44:06.443219 Final RX Vref Byte 1 = 57 to rank0
6789 17:44:06.446379 Final RX Vref Byte 0 = 53 to rank1
6790 17:44:06.450075 Final RX Vref Byte 1 = 57 to rank1==
6791 17:44:06.453183 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 17:44:06.459814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 17:44:06.459897 ==
6794 17:44:06.459961 DQS Delay:
6795 17:44:06.463236 DQS0 = 32, DQS1 = 44
6796 17:44:06.463318 DQM Delay:
6797 17:44:06.463382 DQM0 = 11, DQM1 = 15
6798 17:44:06.466431 DQ Delay:
6799 17:44:06.469641 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6800 17:44:06.469723 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6801 17:44:06.472832 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6802 17:44:06.476517 DQ12 =28, DQ13 =24, DQ14 =20, DQ15 =20
6803 17:44:06.476599
6804 17:44:06.479664
6805 17:44:06.486230 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6806 17:44:06.489360 CH1 RK0: MR19=C0C, MR18=92CC
6807 17:44:06.496242 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6808 17:44:06.496325 ==
6809 17:44:06.499789 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 17:44:06.502798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 17:44:06.502883 ==
6812 17:44:06.506005 [Gating] SW mode calibration
6813 17:44:06.512571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6814 17:44:06.519292 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6815 17:44:06.523051 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 17:44:06.526307 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 17:44:06.532886 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 17:44:06.535988 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 17:44:06.539294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 17:44:06.542426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 17:44:06.549351 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 17:44:06.552610 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 17:44:06.555791 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 17:44:06.559341 Total UI for P1: 0, mck2ui 16
6825 17:44:06.562264 best dqsien dly found for B0: ( 0, 14, 24)
6826 17:44:06.565980 Total UI for P1: 0, mck2ui 16
6827 17:44:06.569057 best dqsien dly found for B1: ( 0, 14, 24)
6828 17:44:06.572646 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6829 17:44:06.579265 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6830 17:44:06.579346
6831 17:44:06.582314 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 17:44:06.585665 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 17:44:06.589167 [Gating] SW calibration Done
6834 17:44:06.589285 ==
6835 17:44:06.592151 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 17:44:06.595666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 17:44:06.595747 ==
6838 17:44:06.599208 RX Vref Scan: 0
6839 17:44:06.599288
6840 17:44:06.599351 RX Vref 0 -> 0, step: 1
6841 17:44:06.599410
6842 17:44:06.602411 RX Delay -410 -> 252, step: 16
6843 17:44:06.605900 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6844 17:44:06.612142 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6845 17:44:06.615468 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6846 17:44:06.619337 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6847 17:44:06.622399 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6848 17:44:06.629242 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6849 17:44:06.632451 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6850 17:44:06.635332 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6851 17:44:06.638763 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6852 17:44:06.645255 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6853 17:44:06.648729 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6854 17:44:06.652164 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6855 17:44:06.655397 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6856 17:44:06.662020 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6857 17:44:06.665477 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6858 17:44:06.668684 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6859 17:44:06.668770 ==
6860 17:44:06.671732 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 17:44:06.678425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 17:44:06.678504 ==
6863 17:44:06.678569 DQS Delay:
6864 17:44:06.681888 DQS0 = 35, DQS1 = 43
6865 17:44:06.681958 DQM Delay:
6866 17:44:06.684943 DQM0 = 17, DQM1 = 18
6867 17:44:06.685017 DQ Delay:
6868 17:44:06.688738 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6869 17:44:06.691762 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6870 17:44:06.694981 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6871 17:44:06.697956 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6872 17:44:06.698038
6873 17:44:06.698104
6874 17:44:06.698164 ==
6875 17:44:06.701677 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 17:44:06.704756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 17:44:06.704828 ==
6878 17:44:06.704889
6879 17:44:06.704979
6880 17:44:06.707859 TX Vref Scan disable
6881 17:44:06.707930 == TX Byte 0 ==
6882 17:44:06.714888 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6883 17:44:06.718182 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6884 17:44:06.718263 == TX Byte 1 ==
6885 17:44:06.724416 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6886 17:44:06.728041 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6887 17:44:06.728115 ==
6888 17:44:06.731132 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 17:44:06.734288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 17:44:06.734356 ==
6891 17:44:06.734415
6892 17:44:06.734479
6893 17:44:06.738104 TX Vref Scan disable
6894 17:44:06.738175 == TX Byte 0 ==
6895 17:44:06.744362 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6896 17:44:06.747654 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6897 17:44:06.747728 == TX Byte 1 ==
6898 17:44:06.754403 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6899 17:44:06.757523 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6900 17:44:06.757600
6901 17:44:06.757662 [DATLAT]
6902 17:44:06.760880 Freq=400, CH1 RK1
6903 17:44:06.761017
6904 17:44:06.761080 DATLAT Default: 0xe
6905 17:44:06.764212 0, 0xFFFF, sum = 0
6906 17:44:06.764288 1, 0xFFFF, sum = 0
6907 17:44:06.767469 2, 0xFFFF, sum = 0
6908 17:44:06.767551 3, 0xFFFF, sum = 0
6909 17:44:06.771052 4, 0xFFFF, sum = 0
6910 17:44:06.771130 5, 0xFFFF, sum = 0
6911 17:44:06.774240 6, 0xFFFF, sum = 0
6912 17:44:06.777242 7, 0xFFFF, sum = 0
6913 17:44:06.777316 8, 0xFFFF, sum = 0
6914 17:44:06.781093 9, 0xFFFF, sum = 0
6915 17:44:06.781171 10, 0xFFFF, sum = 0
6916 17:44:06.783977 11, 0xFFFF, sum = 0
6917 17:44:06.784051 12, 0xFFFF, sum = 0
6918 17:44:06.787419 13, 0x0, sum = 1
6919 17:44:06.787499 14, 0x0, sum = 2
6920 17:44:06.790721 15, 0x0, sum = 3
6921 17:44:06.790796 16, 0x0, sum = 4
6922 17:44:06.793868 best_step = 14
6923 17:44:06.793936
6924 17:44:06.793997 ==
6925 17:44:06.796918 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 17:44:06.800379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 17:44:06.800457 ==
6928 17:44:06.800521 RX Vref Scan: 0
6929 17:44:06.803752
6930 17:44:06.803849 RX Vref 0 -> 0, step: 1
6931 17:44:06.803946
6932 17:44:06.806920 RX Delay -327 -> 252, step: 8
6933 17:44:06.814585 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6934 17:44:06.817670 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6935 17:44:06.821208 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6936 17:44:06.824581 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6937 17:44:06.830932 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6938 17:44:06.834209 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6939 17:44:06.837787 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6940 17:44:06.840926 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6941 17:44:06.847419 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6942 17:44:06.851027 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6943 17:44:06.854177 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6944 17:44:06.860750 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6945 17:44:06.864083 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6946 17:44:06.867667 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6947 17:44:06.871021 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6948 17:44:06.877708 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6949 17:44:06.877790 ==
6950 17:44:06.880810 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 17:44:06.884529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 17:44:06.884604 ==
6953 17:44:06.884666 DQS Delay:
6954 17:44:06.887502 DQS0 = 32, DQS1 = 40
6955 17:44:06.887571 DQM Delay:
6956 17:44:06.890921 DQM0 = 12, DQM1 = 15
6957 17:44:06.890999 DQ Delay:
6958 17:44:06.894101 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6959 17:44:06.897421 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =8
6960 17:44:06.900856 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6961 17:44:06.904076 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6962 17:44:06.904150
6963 17:44:06.904211
6964 17:44:06.910942 [DQSOSCAuto] RK1, (LSB)MR18= 0x9b45, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 390 ps
6965 17:44:06.914017 CH1 RK1: MR19=C0C, MR18=9B45
6966 17:44:06.920884 CH1_RK1: MR19=0xC0C, MR18=0x9B45, DQSOSC=390, MR23=63, INC=388, DEC=258
6967 17:44:06.923935 [RxdqsGatingPostProcess] freq 400
6968 17:44:06.930995 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6969 17:44:06.931076 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 17:44:06.934147 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 17:44:06.937426 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 17:44:06.940550 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 17:44:06.944081 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 17:44:06.947432 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 17:44:06.950558 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 17:44:06.954199 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 17:44:06.957447 Pre-setting of DQS Precalculation
6978 17:44:06.963848 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6979 17:44:06.970421 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6980 17:44:06.977335 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6981 17:44:06.977418
6982 17:44:06.977483
6983 17:44:06.980485 [Calibration Summary] 800 Mbps
6984 17:44:06.980567 CH 0, Rank 0
6985 17:44:06.983738 SW Impedance : PASS
6986 17:44:06.987096 DUTY Scan : NO K
6987 17:44:06.987182 ZQ Calibration : PASS
6988 17:44:06.990433 Jitter Meter : NO K
6989 17:44:06.990516 CBT Training : PASS
6990 17:44:06.993897 Write leveling : PASS
6991 17:44:06.997126 RX DQS gating : PASS
6992 17:44:06.997208 RX DQ/DQS(RDDQC) : PASS
6993 17:44:07.000236 TX DQ/DQS : PASS
6994 17:44:07.003602 RX DATLAT : PASS
6995 17:44:07.003685 RX DQ/DQS(Engine): PASS
6996 17:44:07.006968 TX OE : NO K
6997 17:44:07.007051 All Pass.
6998 17:44:07.007116
6999 17:44:07.010245 CH 0, Rank 1
7000 17:44:07.010327 SW Impedance : PASS
7001 17:44:07.013760 DUTY Scan : NO K
7002 17:44:07.017361 ZQ Calibration : PASS
7003 17:44:07.017447 Jitter Meter : NO K
7004 17:44:07.020157 CBT Training : PASS
7005 17:44:07.023743 Write leveling : NO K
7006 17:44:07.023826 RX DQS gating : PASS
7007 17:44:07.027091 RX DQ/DQS(RDDQC) : PASS
7008 17:44:07.030141 TX DQ/DQS : PASS
7009 17:44:07.030225 RX DATLAT : PASS
7010 17:44:07.033745 RX DQ/DQS(Engine): PASS
7011 17:44:07.036890 TX OE : NO K
7012 17:44:07.037013 All Pass.
7013 17:44:07.037079
7014 17:44:07.037139 CH 1, Rank 0
7015 17:44:07.040020 SW Impedance : PASS
7016 17:44:07.043598 DUTY Scan : NO K
7017 17:44:07.043681 ZQ Calibration : PASS
7018 17:44:07.046857 Jitter Meter : NO K
7019 17:44:07.046940 CBT Training : PASS
7020 17:44:07.050043 Write leveling : PASS
7021 17:44:07.053668 RX DQS gating : PASS
7022 17:44:07.053751 RX DQ/DQS(RDDQC) : PASS
7023 17:44:07.056844 TX DQ/DQS : PASS
7024 17:44:07.060428 RX DATLAT : PASS
7025 17:44:07.060511 RX DQ/DQS(Engine): PASS
7026 17:44:07.063607 TX OE : NO K
7027 17:44:07.063690 All Pass.
7028 17:44:07.063756
7029 17:44:07.066676 CH 1, Rank 1
7030 17:44:07.066763 SW Impedance : PASS
7031 17:44:07.070161 DUTY Scan : NO K
7032 17:44:07.073273 ZQ Calibration : PASS
7033 17:44:07.073357 Jitter Meter : NO K
7034 17:44:07.076661 CBT Training : PASS
7035 17:44:07.080045 Write leveling : NO K
7036 17:44:07.080129 RX DQS gating : PASS
7037 17:44:07.083512 RX DQ/DQS(RDDQC) : PASS
7038 17:44:07.086682 TX DQ/DQS : PASS
7039 17:44:07.086779 RX DATLAT : PASS
7040 17:44:07.089934 RX DQ/DQS(Engine): PASS
7041 17:44:07.090019 TX OE : NO K
7042 17:44:07.093210 All Pass.
7043 17:44:07.093294
7044 17:44:07.093359 DramC Write-DBI off
7045 17:44:07.096686 PER_BANK_REFRESH: Hybrid Mode
7046 17:44:07.099945 TX_TRACKING: ON
7047 17:44:07.106931 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7048 17:44:07.109987 [FAST_K] Save calibration result to emmc
7049 17:44:07.113694 dramc_set_vcore_voltage set vcore to 725000
7050 17:44:07.116651 Read voltage for 1600, 0
7051 17:44:07.116726 Vio18 = 0
7052 17:44:07.119824 Vcore = 725000
7053 17:44:07.119896 Vdram = 0
7054 17:44:07.119958 Vddq = 0
7055 17:44:07.123533 Vmddr = 0
7056 17:44:07.126663 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7057 17:44:07.133266 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7058 17:44:07.133368 MEM_TYPE=3, freq_sel=13
7059 17:44:07.136735 sv_algorithm_assistance_LP4_3733
7060 17:44:07.143375 ============ PULL DRAM RESETB DOWN ============
7061 17:44:07.146564 ========== PULL DRAM RESETB DOWN end =========
7062 17:44:07.150118 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7063 17:44:07.153302 ===================================
7064 17:44:07.156528 LPDDR4 DRAM CONFIGURATION
7065 17:44:07.160178 ===================================
7066 17:44:07.163756 EX_ROW_EN[0] = 0x0
7067 17:44:07.163859 EX_ROW_EN[1] = 0x0
7068 17:44:07.166858 LP4Y_EN = 0x0
7069 17:44:07.166968 WORK_FSP = 0x1
7070 17:44:07.170000 WL = 0x5
7071 17:44:07.170073 RL = 0x5
7072 17:44:07.173532 BL = 0x2
7073 17:44:07.173615 RPST = 0x0
7074 17:44:07.176556 RD_PRE = 0x0
7075 17:44:07.176639 WR_PRE = 0x1
7076 17:44:07.180197 WR_PST = 0x1
7077 17:44:07.180280 DBI_WR = 0x0
7078 17:44:07.183316 DBI_RD = 0x0
7079 17:44:07.183400 OTF = 0x1
7080 17:44:07.186756 ===================================
7081 17:44:07.189681 ===================================
7082 17:44:07.193457 ANA top config
7083 17:44:07.196723 ===================================
7084 17:44:07.199620 DLL_ASYNC_EN = 0
7085 17:44:07.199706 ALL_SLAVE_EN = 0
7086 17:44:07.203109 NEW_RANK_MODE = 1
7087 17:44:07.206293 DLL_IDLE_MODE = 1
7088 17:44:07.209694 LP45_APHY_COMB_EN = 1
7089 17:44:07.209778 TX_ODT_DIS = 0
7090 17:44:07.212851 NEW_8X_MODE = 1
7091 17:44:07.216539 ===================================
7092 17:44:07.219536 ===================================
7093 17:44:07.222764 data_rate = 3200
7094 17:44:07.226316 CKR = 1
7095 17:44:07.229596 DQ_P2S_RATIO = 8
7096 17:44:07.232960 ===================================
7097 17:44:07.236224 CA_P2S_RATIO = 8
7098 17:44:07.236309 DQ_CA_OPEN = 0
7099 17:44:07.239519 DQ_SEMI_OPEN = 0
7100 17:44:07.243122 CA_SEMI_OPEN = 0
7101 17:44:07.246353 CA_FULL_RATE = 0
7102 17:44:07.249437 DQ_CKDIV4_EN = 0
7103 17:44:07.252689 CA_CKDIV4_EN = 0
7104 17:44:07.252772 CA_PREDIV_EN = 0
7105 17:44:07.256162 PH8_DLY = 12
7106 17:44:07.259693 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7107 17:44:07.263025 DQ_AAMCK_DIV = 4
7108 17:44:07.266037 CA_AAMCK_DIV = 4
7109 17:44:07.269408 CA_ADMCK_DIV = 4
7110 17:44:07.269493 DQ_TRACK_CA_EN = 0
7111 17:44:07.272789 CA_PICK = 1600
7112 17:44:07.276132 CA_MCKIO = 1600
7113 17:44:07.279469 MCKIO_SEMI = 0
7114 17:44:07.282695 PLL_FREQ = 3068
7115 17:44:07.286145 DQ_UI_PI_RATIO = 32
7116 17:44:07.289754 CA_UI_PI_RATIO = 0
7117 17:44:07.292904 ===================================
7118 17:44:07.296302 ===================================
7119 17:44:07.296380 memory_type:LPDDR4
7120 17:44:07.299838 GP_NUM : 10
7121 17:44:07.302879 SRAM_EN : 1
7122 17:44:07.302955 MD32_EN : 0
7123 17:44:07.306187 ===================================
7124 17:44:07.309326 [ANA_INIT] >>>>>>>>>>>>>>
7125 17:44:07.313094 <<<<<< [CONFIGURE PHASE]: ANA_TX
7126 17:44:07.316272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7127 17:44:07.319358 ===================================
7128 17:44:07.322436 data_rate = 3200,PCW = 0X7600
7129 17:44:07.326041 ===================================
7130 17:44:07.329189 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7131 17:44:07.332435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 17:44:07.339249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 17:44:07.342518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7134 17:44:07.345676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7135 17:44:07.349147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7136 17:44:07.352715 [ANA_INIT] flow start
7137 17:44:07.355914 [ANA_INIT] PLL >>>>>>>>
7138 17:44:07.355998 [ANA_INIT] PLL <<<<<<<<
7139 17:44:07.359059 [ANA_INIT] MIDPI >>>>>>>>
7140 17:44:07.362380 [ANA_INIT] MIDPI <<<<<<<<
7141 17:44:07.365815 [ANA_INIT] DLL >>>>>>>>
7142 17:44:07.365898 [ANA_INIT] DLL <<<<<<<<
7143 17:44:07.368926 [ANA_INIT] flow end
7144 17:44:07.372127 ============ LP4 DIFF to SE enter ============
7145 17:44:07.375654 ============ LP4 DIFF to SE exit ============
7146 17:44:07.378733 [ANA_INIT] <<<<<<<<<<<<<
7147 17:44:07.382465 [Flow] Enable top DCM control >>>>>
7148 17:44:07.385440 [Flow] Enable top DCM control <<<<<
7149 17:44:07.388922 Enable DLL master slave shuffle
7150 17:44:07.395633 ==============================================================
7151 17:44:07.395717 Gating Mode config
7152 17:44:07.402068 ==============================================================
7153 17:44:07.402152 Config description:
7154 17:44:07.412221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7155 17:44:07.418839 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7156 17:44:07.425589 SELPH_MODE 0: By rank 1: By Phase
7157 17:44:07.428707 ==============================================================
7158 17:44:07.432192 GAT_TRACK_EN = 1
7159 17:44:07.435430 RX_GATING_MODE = 2
7160 17:44:07.438674 RX_GATING_TRACK_MODE = 2
7161 17:44:07.442259 SELPH_MODE = 1
7162 17:44:07.445604 PICG_EARLY_EN = 1
7163 17:44:07.448952 VALID_LAT_VALUE = 1
7164 17:44:07.452323 ==============================================================
7165 17:44:07.455257 Enter into Gating configuration >>>>
7166 17:44:07.458822 Exit from Gating configuration <<<<
7167 17:44:07.462109 Enter into DVFS_PRE_config >>>>>
7168 17:44:07.475151 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7169 17:44:07.478445 Exit from DVFS_PRE_config <<<<<
7170 17:44:07.481917 Enter into PICG configuration >>>>
7171 17:44:07.482000 Exit from PICG configuration <<<<
7172 17:44:07.485125 [RX_INPUT] configuration >>>>>
7173 17:44:07.488695 [RX_INPUT] configuration <<<<<
7174 17:44:07.495240 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7175 17:44:07.498386 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7176 17:44:07.505308 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 17:44:07.512085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 17:44:07.518418 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 17:44:07.525200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 17:44:07.528360 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7181 17:44:07.531877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7182 17:44:07.534980 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7183 17:44:07.541617 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7184 17:44:07.545119 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7185 17:44:07.548276 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 17:44:07.551408 ===================================
7187 17:44:07.554779 LPDDR4 DRAM CONFIGURATION
7188 17:44:07.558100 ===================================
7189 17:44:07.561265 EX_ROW_EN[0] = 0x0
7190 17:44:07.561352 EX_ROW_EN[1] = 0x0
7191 17:44:07.564874 LP4Y_EN = 0x0
7192 17:44:07.565000 WORK_FSP = 0x1
7193 17:44:07.568142 WL = 0x5
7194 17:44:07.568225 RL = 0x5
7195 17:44:07.571488 BL = 0x2
7196 17:44:07.571572 RPST = 0x0
7197 17:44:07.574865 RD_PRE = 0x0
7198 17:44:07.574949 WR_PRE = 0x1
7199 17:44:07.577896 WR_PST = 0x1
7200 17:44:07.577980 DBI_WR = 0x0
7201 17:44:07.581409 DBI_RD = 0x0
7202 17:44:07.581492 OTF = 0x1
7203 17:44:07.584593 ===================================
7204 17:44:07.591516 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7205 17:44:07.594584 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7206 17:44:07.598191 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 17:44:07.601178 ===================================
7208 17:44:07.604440 LPDDR4 DRAM CONFIGURATION
7209 17:44:07.607720 ===================================
7210 17:44:07.611188 EX_ROW_EN[0] = 0x10
7211 17:44:07.611275 EX_ROW_EN[1] = 0x0
7212 17:44:07.614819 LP4Y_EN = 0x0
7213 17:44:07.614903 WORK_FSP = 0x1
7214 17:44:07.617744 WL = 0x5
7215 17:44:07.617828 RL = 0x5
7216 17:44:07.620901 BL = 0x2
7217 17:44:07.620992 RPST = 0x0
7218 17:44:07.624516 RD_PRE = 0x0
7219 17:44:07.624599 WR_PRE = 0x1
7220 17:44:07.627806 WR_PST = 0x1
7221 17:44:07.627889 DBI_WR = 0x0
7222 17:44:07.630982 DBI_RD = 0x0
7223 17:44:07.631066 OTF = 0x1
7224 17:44:07.634514 ===================================
7225 17:44:07.640945 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7226 17:44:07.641029 ==
7227 17:44:07.644688 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 17:44:07.651009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7229 17:44:07.651093 ==
7230 17:44:07.651160 [Duty_Offset_Calibration]
7231 17:44:07.654180 B0:2 B1:0 CA:1
7232 17:44:07.654263
7233 17:44:07.657534 [DutyScan_Calibration_Flow] k_type=0
7234 17:44:07.666074
7235 17:44:07.666157 ==CLK 0==
7236 17:44:07.669111 Final CLK duty delay cell = -4
7237 17:44:07.672640 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7238 17:44:07.675806 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7239 17:44:07.679041 [-4] AVG Duty = 4922%(X100)
7240 17:44:07.679124
7241 17:44:07.682493 CH0 CLK Duty spec in!! Max-Min= 218%
7242 17:44:07.685653 [DutyScan_Calibration_Flow] ====Done====
7243 17:44:07.685745
7244 17:44:07.689113 [DutyScan_Calibration_Flow] k_type=1
7245 17:44:07.705400
7246 17:44:07.705483 ==DQS 0 ==
7247 17:44:07.708822 Final DQS duty delay cell = 0
7248 17:44:07.712027 [0] MAX Duty = 5249%(X100), DQS PI = 32
7249 17:44:07.715200 [0] MIN Duty = 4969%(X100), DQS PI = 0
7250 17:44:07.715285 [0] AVG Duty = 5109%(X100)
7251 17:44:07.718481
7252 17:44:07.718564 ==DQS 1 ==
7253 17:44:07.721910 Final DQS duty delay cell = -4
7254 17:44:07.725096 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7255 17:44:07.728395 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7256 17:44:07.731776 [-4] AVG Duty = 4984%(X100)
7257 17:44:07.731859
7258 17:44:07.735160 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7259 17:44:07.735244
7260 17:44:07.738554 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7261 17:44:07.741676 [DutyScan_Calibration_Flow] ====Done====
7262 17:44:07.741759
7263 17:44:07.744993 [DutyScan_Calibration_Flow] k_type=3
7264 17:44:07.762733
7265 17:44:07.762816 ==DQM 0 ==
7266 17:44:07.766060 Final DQM duty delay cell = 0
7267 17:44:07.769191 [0] MAX Duty = 5124%(X100), DQS PI = 26
7268 17:44:07.772547 [0] MIN Duty = 4813%(X100), DQS PI = 50
7269 17:44:07.776009 [0] AVG Duty = 4968%(X100)
7270 17:44:07.776094
7271 17:44:07.776160 ==DQM 1 ==
7272 17:44:07.779083 Final DQM duty delay cell = 0
7273 17:44:07.782685 [0] MAX Duty = 5249%(X100), DQS PI = 28
7274 17:44:07.785914 [0] MIN Duty = 5031%(X100), DQS PI = 6
7275 17:44:07.789364 [0] AVG Duty = 5140%(X100)
7276 17:44:07.789448
7277 17:44:07.792464 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7278 17:44:07.792548
7279 17:44:07.795851 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7280 17:44:07.799211 [DutyScan_Calibration_Flow] ====Done====
7281 17:44:07.799295
7282 17:44:07.802436 [DutyScan_Calibration_Flow] k_type=2
7283 17:44:07.819704
7284 17:44:07.819788 ==DQ 0 ==
7285 17:44:07.823152 Final DQ duty delay cell = 0
7286 17:44:07.826456 [0] MAX Duty = 5124%(X100), DQS PI = 32
7287 17:44:07.829726 [0] MIN Duty = 5000%(X100), DQS PI = 16
7288 17:44:07.829807 [0] AVG Duty = 5062%(X100)
7289 17:44:07.833359
7290 17:44:07.833454 ==DQ 1 ==
7291 17:44:07.836725 Final DQ duty delay cell = 0
7292 17:44:07.839766 [0] MAX Duty = 4969%(X100), DQS PI = 42
7293 17:44:07.843090 [0] MIN Duty = 4875%(X100), DQS PI = 10
7294 17:44:07.843176 [0] AVG Duty = 4922%(X100)
7295 17:44:07.846469
7296 17:44:07.849970 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7297 17:44:07.850045
7298 17:44:07.853097 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7299 17:44:07.856551 [DutyScan_Calibration_Flow] ====Done====
7300 17:44:07.856620 ==
7301 17:44:07.859659 Dram Type= 6, Freq= 0, CH_1, rank 0
7302 17:44:07.862867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 17:44:07.862937 ==
7304 17:44:07.866192 [Duty_Offset_Calibration]
7305 17:44:07.866292 B0:0 B1:-1 CA:2
7306 17:44:07.866369
7307 17:44:07.869703 [DutyScan_Calibration_Flow] k_type=0
7308 17:44:07.880301
7309 17:44:07.880382 ==CLK 0==
7310 17:44:07.883516 Final CLK duty delay cell = 0
7311 17:44:07.886593 [0] MAX Duty = 5156%(X100), DQS PI = 10
7312 17:44:07.890245 [0] MIN Duty = 4906%(X100), DQS PI = 46
7313 17:44:07.893255 [0] AVG Duty = 5031%(X100)
7314 17:44:07.893335
7315 17:44:07.896679 CH1 CLK Duty spec in!! Max-Min= 250%
7316 17:44:07.900086 [DutyScan_Calibration_Flow] ====Done====
7317 17:44:07.900166
7318 17:44:07.903179 [DutyScan_Calibration_Flow] k_type=1
7319 17:44:07.919866
7320 17:44:07.919946 ==DQS 0 ==
7321 17:44:07.923158 Final DQS duty delay cell = 0
7322 17:44:07.926326 [0] MAX Duty = 5093%(X100), DQS PI = 26
7323 17:44:07.929972 [0] MIN Duty = 4969%(X100), DQS PI = 0
7324 17:44:07.930054 [0] AVG Duty = 5031%(X100)
7325 17:44:07.933217
7326 17:44:07.933299 ==DQS 1 ==
7327 17:44:07.936475 Final DQS duty delay cell = 0
7328 17:44:07.939625 [0] MAX Duty = 5187%(X100), DQS PI = 0
7329 17:44:07.943328 [0] MIN Duty = 4844%(X100), DQS PI = 34
7330 17:44:07.943410 [0] AVG Duty = 5015%(X100)
7331 17:44:07.946455
7332 17:44:07.949672 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7333 17:44:07.949754
7334 17:44:07.953073 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7335 17:44:07.956325 [DutyScan_Calibration_Flow] ====Done====
7336 17:44:07.956409
7337 17:44:07.959733 [DutyScan_Calibration_Flow] k_type=3
7338 17:44:07.977534
7339 17:44:07.977617 ==DQM 0 ==
7340 17:44:07.980719 Final DQM duty delay cell = 4
7341 17:44:07.984399 [4] MAX Duty = 5156%(X100), DQS PI = 24
7342 17:44:07.987491 [4] MIN Duty = 4969%(X100), DQS PI = 44
7343 17:44:07.990660 [4] AVG Duty = 5062%(X100)
7344 17:44:07.990741
7345 17:44:07.990805 ==DQM 1 ==
7346 17:44:07.994130 Final DQM duty delay cell = 0
7347 17:44:07.997433 [0] MAX Duty = 5281%(X100), DQS PI = 58
7348 17:44:08.001021 [0] MIN Duty = 4876%(X100), DQS PI = 34
7349 17:44:08.004008 [0] AVG Duty = 5078%(X100)
7350 17:44:08.004090
7351 17:44:08.007207 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7352 17:44:08.007289
7353 17:44:08.010925 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7354 17:44:08.013887 [DutyScan_Calibration_Flow] ====Done====
7355 17:44:08.013968
7356 17:44:08.017089 [DutyScan_Calibration_Flow] k_type=2
7357 17:44:08.034251
7358 17:44:08.034332 ==DQ 0 ==
7359 17:44:08.037489 Final DQ duty delay cell = 0
7360 17:44:08.041100 [0] MAX Duty = 5093%(X100), DQS PI = 20
7361 17:44:08.044297 [0] MIN Duty = 4969%(X100), DQS PI = 46
7362 17:44:08.044379 [0] AVG Duty = 5031%(X100)
7363 17:44:08.047614
7364 17:44:08.047696 ==DQ 1 ==
7365 17:44:08.050950 Final DQ duty delay cell = 0
7366 17:44:08.054474 [0] MAX Duty = 5062%(X100), DQS PI = 2
7367 17:44:08.058042 [0] MIN Duty = 4813%(X100), DQS PI = 34
7368 17:44:08.058125 [0] AVG Duty = 4937%(X100)
7369 17:44:08.058189
7370 17:44:08.060953 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7371 17:44:08.064100
7372 17:44:08.067933 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7373 17:44:08.071325 [DutyScan_Calibration_Flow] ====Done====
7374 17:44:08.074501 nWR fixed to 30
7375 17:44:08.074583 [ModeRegInit_LP4] CH0 RK0
7376 17:44:08.077850 [ModeRegInit_LP4] CH0 RK1
7377 17:44:08.081040 [ModeRegInit_LP4] CH1 RK0
7378 17:44:08.083977 [ModeRegInit_LP4] CH1 RK1
7379 17:44:08.084060 match AC timing 5
7380 17:44:08.090548 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7381 17:44:08.094019 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7382 17:44:08.097280 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7383 17:44:08.104042 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7384 17:44:08.107168 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7385 17:44:08.107252 [MiockJmeterHQA]
7386 17:44:08.107318
7387 17:44:08.110722 [DramcMiockJmeter] u1RxGatingPI = 0
7388 17:44:08.113507 0 : 4255, 4027
7389 17:44:08.113594 4 : 4254, 4027
7390 17:44:08.117055 8 : 4363, 4137
7391 17:44:08.117144 12 : 4252, 4027
7392 17:44:08.117211 16 : 4253, 4026
7393 17:44:08.120220 20 : 4363, 4138
7394 17:44:08.120305 24 : 4253, 4026
7395 17:44:08.123472 28 : 4253, 4027
7396 17:44:08.123558 32 : 4252, 4027
7397 17:44:08.127324 36 : 4254, 4029
7398 17:44:08.127409 40 : 4253, 4027
7399 17:44:08.130427 44 : 4250, 4027
7400 17:44:08.130512 48 : 4365, 4140
7401 17:44:08.130580 52 : 4250, 4027
7402 17:44:08.133625 56 : 4255, 4029
7403 17:44:08.133710 60 : 4250, 4026
7404 17:44:08.137031 64 : 4360, 4137
7405 17:44:08.137117 68 : 4250, 4027
7406 17:44:08.140228 72 : 4361, 4137
7407 17:44:08.140313 76 : 4252, 4029
7408 17:44:08.143291 80 : 4250, 4027
7409 17:44:08.143376 84 : 4252, 4027
7410 17:44:08.143443 88 : 4253, 3561
7411 17:44:08.146829 92 : 4360, 0
7412 17:44:08.146914 96 : 4250, 0
7413 17:44:08.149985 100 : 4250, 0
7414 17:44:08.150070 104 : 4361, 0
7415 17:44:08.150137 108 : 4361, 0
7416 17:44:08.153527 112 : 4363, 0
7417 17:44:08.153612 116 : 4250, 0
7418 17:44:08.153680 120 : 4360, 0
7419 17:44:08.156775 124 : 4250, 0
7420 17:44:08.156860 128 : 4250, 0
7421 17:44:08.159912 132 : 4250, 0
7422 17:44:08.159997 136 : 4250, 0
7423 17:44:08.160064 140 : 4252, 0
7424 17:44:08.163175 144 : 4360, 0
7425 17:44:08.163260 148 : 4250, 0
7426 17:44:08.166846 152 : 4250, 0
7427 17:44:08.166931 156 : 4361, 0
7428 17:44:08.166999 160 : 4361, 0
7429 17:44:08.169845 164 : 4364, 0
7430 17:44:08.169930 168 : 4250, 0
7431 17:44:08.173280 172 : 4360, 0
7432 17:44:08.173365 176 : 4250, 0
7433 17:44:08.173432 180 : 4250, 0
7434 17:44:08.176702 184 : 4250, 0
7435 17:44:08.176814 188 : 4250, 0
7436 17:44:08.176910 192 : 4253, 0
7437 17:44:08.180074 196 : 4360, 0
7438 17:44:08.180160 200 : 4250, 0
7439 17:44:08.183385 204 : 4250, 2149
7440 17:44:08.183489 208 : 4250, 4027
7441 17:44:08.186624 212 : 4250, 4027
7442 17:44:08.186708 216 : 4360, 4138
7443 17:44:08.190144 220 : 4250, 4027
7444 17:44:08.190268 224 : 4250, 4026
7445 17:44:08.193377 228 : 4361, 4137
7446 17:44:08.193486 232 : 4360, 4138
7447 17:44:08.196386 236 : 4250, 4027
7448 17:44:08.196472 240 : 4364, 4140
7449 17:44:08.196540 244 : 4250, 4026
7450 17:44:08.199939 248 : 4250, 4027
7451 17:44:08.200024 252 : 4252, 4029
7452 17:44:08.203191 256 : 4253, 4029
7453 17:44:08.203276 260 : 4250, 4026
7454 17:44:08.206183 264 : 4250, 4027
7455 17:44:08.206280 268 : 4250, 4027
7456 17:44:08.209979 272 : 4252, 4029
7457 17:44:08.210064 276 : 4250, 4026
7458 17:44:08.213026 280 : 4361, 4138
7459 17:44:08.213112 284 : 4360, 4138
7460 17:44:08.216508 288 : 4250, 4027
7461 17:44:08.216593 292 : 4363, 4140
7462 17:44:08.219634 296 : 4250, 4026
7463 17:44:08.219719 300 : 4250, 4027
7464 17:44:08.219787 304 : 4250, 4027
7465 17:44:08.223340 308 : 4253, 4029
7466 17:44:08.223424 312 : 4250, 3965
7467 17:44:08.226486 316 : 4250, 2212
7468 17:44:08.226571 320 : 4250, 12
7469 17:44:08.226638
7470 17:44:08.229836 MIOCK jitter meter ch=0
7471 17:44:08.229937
7472 17:44:08.233101 1T = (320-92) = 228 dly cells
7473 17:44:08.239709 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7474 17:44:08.239794 ==
7475 17:44:08.242914 Dram Type= 6, Freq= 0, CH_0, rank 0
7476 17:44:08.246603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7477 17:44:08.246689 ==
7478 17:44:08.252902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7479 17:44:08.256407 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7480 17:44:08.259416 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7481 17:44:08.266004 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7482 17:44:08.274599 [CA 0] Center 43 (13~73) winsize 61
7483 17:44:08.278079 [CA 1] Center 43 (13~73) winsize 61
7484 17:44:08.281173 [CA 2] Center 38 (8~68) winsize 61
7485 17:44:08.284627 [CA 3] Center 37 (8~67) winsize 60
7486 17:44:08.287612 [CA 4] Center 36 (6~66) winsize 61
7487 17:44:08.291225 [CA 5] Center 35 (5~65) winsize 61
7488 17:44:08.291309
7489 17:44:08.294615 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7490 17:44:08.294699
7491 17:44:08.298223 [CATrainingPosCal] consider 1 rank data
7492 17:44:08.301300 u2DelayCellTimex100 = 285/100 ps
7493 17:44:08.304332 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7494 17:44:08.311121 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7495 17:44:08.314385 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7496 17:44:08.317787 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7497 17:44:08.321274 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7498 17:44:08.324469 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7499 17:44:08.324554
7500 17:44:08.327601 CA PerBit enable=1, Macro0, CA PI delay=35
7501 17:44:08.327685
7502 17:44:08.331094 [CBTSetCACLKResult] CA Dly = 35
7503 17:44:08.334696 CS Dly: 10 (0~41)
7504 17:44:08.338044 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7505 17:44:08.341140 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7506 17:44:08.341223 ==
7507 17:44:08.344244 Dram Type= 6, Freq= 0, CH_0, rank 1
7508 17:44:08.347469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 17:44:08.350841 ==
7510 17:44:08.353983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 17:44:08.357564 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 17:44:08.364318 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 17:44:08.367666 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 17:44:08.378018 [CA 0] Center 43 (13~74) winsize 62
7515 17:44:08.381659 [CA 1] Center 43 (14~73) winsize 60
7516 17:44:08.384964 [CA 2] Center 38 (9~68) winsize 60
7517 17:44:08.388094 [CA 3] Center 38 (9~68) winsize 60
7518 17:44:08.391372 [CA 4] Center 37 (7~67) winsize 61
7519 17:44:08.394914 [CA 5] Center 36 (7~66) winsize 60
7520 17:44:08.394998
7521 17:44:08.398212 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 17:44:08.398297
7523 17:44:08.401234 [CATrainingPosCal] consider 2 rank data
7524 17:44:08.404711 u2DelayCellTimex100 = 285/100 ps
7525 17:44:08.407818 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7526 17:44:08.414596 CA1 delay=43 (14~73),Diff = 7 PI (23 cell)
7527 17:44:08.418137 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7528 17:44:08.421158 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7529 17:44:08.424774 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7530 17:44:08.428056 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7531 17:44:08.428140
7532 17:44:08.431083 CA PerBit enable=1, Macro0, CA PI delay=36
7533 17:44:08.431167
7534 17:44:08.434636 [CBTSetCACLKResult] CA Dly = 36
7535 17:44:08.437779 CS Dly: 11 (0~43)
7536 17:44:08.441220 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 17:44:08.444450 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 17:44:08.444534
7539 17:44:08.447537 ----->DramcWriteLeveling(PI) begin...
7540 17:44:08.447623 ==
7541 17:44:08.451248 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 17:44:08.457753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 17:44:08.457837 ==
7544 17:44:08.461245 Write leveling (Byte 0): 36 => 36
7545 17:44:08.461328 Write leveling (Byte 1): 31 => 31
7546 17:44:08.464308 DramcWriteLeveling(PI) end<-----
7547 17:44:08.464392
7548 17:44:08.464458 ==
7549 17:44:08.467795 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 17:44:08.474157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 17:44:08.474241 ==
7552 17:44:08.477499 [Gating] SW mode calibration
7553 17:44:08.483876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7554 17:44:08.487514 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7555 17:44:08.493968 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 17:44:08.497256 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 17:44:08.500798 1 4 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7558 17:44:08.507009 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7559 17:44:08.510598 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7560 17:44:08.514034 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 17:44:08.520446 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 17:44:08.523956 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 17:44:08.527167 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 17:44:08.533892 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 17:44:08.537258 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
7566 17:44:08.540608 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7567 17:44:08.543727 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7568 17:44:08.550389 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7569 17:44:08.554046 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 17:44:08.557172 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 17:44:08.563848 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 17:44:08.567122 1 6 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7573 17:44:08.570245 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7574 17:44:08.576910 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7575 17:44:08.580433 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7576 17:44:08.583543 1 6 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7577 17:44:08.590122 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 17:44:08.593604 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 17:44:08.596969 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 17:44:08.603435 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 17:44:08.606830 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 17:44:08.610060 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 17:44:08.616937 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7584 17:44:08.620495 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 17:44:08.623334 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 17:44:08.630055 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 17:44:08.633781 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 17:44:08.636752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 17:44:08.643622 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 17:44:08.646686 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 17:44:08.650232 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 17:44:08.656870 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 17:44:08.660011 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 17:44:08.663213 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 17:44:08.669901 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 17:44:08.673139 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 17:44:08.676721 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 17:44:08.683366 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7599 17:44:08.683451 Total UI for P1: 0, mck2ui 16
7600 17:44:08.689788 best dqsien dly found for B0: ( 1, 9, 8)
7601 17:44:08.692975 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7602 17:44:08.696627 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 17:44:08.699679 Total UI for P1: 0, mck2ui 16
7604 17:44:08.703021 best dqsien dly found for B1: ( 1, 9, 16)
7605 17:44:08.706509 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7606 17:44:08.709675 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7607 17:44:08.709764
7608 17:44:08.713100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7609 17:44:08.719971 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7610 17:44:08.720055 [Gating] SW calibration Done
7611 17:44:08.720121 ==
7612 17:44:08.722935 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 17:44:08.729899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 17:44:08.729989 ==
7615 17:44:08.730056 RX Vref Scan: 0
7616 17:44:08.730118
7617 17:44:08.733100 RX Vref 0 -> 0, step: 1
7618 17:44:08.733183
7619 17:44:08.736251 RX Delay 0 -> 252, step: 8
7620 17:44:08.739898 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7621 17:44:08.743031 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7622 17:44:08.746172 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7623 17:44:08.749744 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7624 17:44:08.756054 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7625 17:44:08.759578 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7626 17:44:08.762700 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7627 17:44:08.766309 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7628 17:44:08.769524 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7629 17:44:08.776197 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7630 17:44:08.779564 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7631 17:44:08.782527 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7632 17:44:08.786320 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7633 17:44:08.789499 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7634 17:44:08.796208 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7635 17:44:08.799433 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7636 17:44:08.799515 ==
7637 17:44:08.802974 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 17:44:08.806109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 17:44:08.806217 ==
7640 17:44:08.809459 DQS Delay:
7641 17:44:08.809541 DQS0 = 0, DQS1 = 0
7642 17:44:08.809605 DQM Delay:
7643 17:44:08.813077 DQM0 = 138, DQM1 = 127
7644 17:44:08.813159 DQ Delay:
7645 17:44:08.816037 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7646 17:44:08.819593 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7647 17:44:08.822943 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7648 17:44:08.829511 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7649 17:44:08.829600
7650 17:44:08.829664
7651 17:44:08.829725 ==
7652 17:44:08.832940 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 17:44:08.836297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 17:44:08.836401 ==
7655 17:44:08.836498
7656 17:44:08.836591
7657 17:44:08.839257 TX Vref Scan disable
7658 17:44:08.839355 == TX Byte 0 ==
7659 17:44:08.846218 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7660 17:44:08.849213 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7661 17:44:08.849317 == TX Byte 1 ==
7662 17:44:08.856018 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7663 17:44:08.859174 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7664 17:44:08.859263 ==
7665 17:44:08.862467 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 17:44:08.865617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 17:44:08.865700 ==
7668 17:44:08.879893
7669 17:44:08.883652 TX Vref early break, caculate TX vref
7670 17:44:08.886702 TX Vref=16, minBit 12, minWin=21, winSum=378
7671 17:44:08.890091 TX Vref=18, minBit 2, minWin=23, winSum=384
7672 17:44:08.893474 TX Vref=20, minBit 0, minWin=24, winSum=397
7673 17:44:08.896553 TX Vref=22, minBit 4, minWin=24, winSum=406
7674 17:44:08.900283 TX Vref=24, minBit 7, minWin=24, winSum=414
7675 17:44:08.906537 TX Vref=26, minBit 2, minWin=25, winSum=422
7676 17:44:08.909993 TX Vref=28, minBit 0, minWin=26, winSum=432
7677 17:44:08.913467 TX Vref=30, minBit 0, minWin=25, winSum=424
7678 17:44:08.916508 TX Vref=32, minBit 0, minWin=25, winSum=415
7679 17:44:08.920071 TX Vref=34, minBit 7, minWin=24, winSum=403
7680 17:44:08.926896 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
7681 17:44:08.926981
7682 17:44:08.929957 Final TX Range 0 Vref 28
7683 17:44:08.930042
7684 17:44:08.930106 ==
7685 17:44:08.933138 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 17:44:08.936598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 17:44:08.936683 ==
7688 17:44:08.936749
7689 17:44:08.936809
7690 17:44:08.939941 TX Vref Scan disable
7691 17:44:08.946714 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7692 17:44:08.946798 == TX Byte 0 ==
7693 17:44:08.949848 u2DelayCellOfst[0]=13 cells (4 PI)
7694 17:44:08.953180 u2DelayCellOfst[1]=17 cells (5 PI)
7695 17:44:08.956709 u2DelayCellOfst[2]=10 cells (3 PI)
7696 17:44:08.959887 u2DelayCellOfst[3]=13 cells (4 PI)
7697 17:44:08.963030 u2DelayCellOfst[4]=6 cells (2 PI)
7698 17:44:08.966689 u2DelayCellOfst[5]=0 cells (0 PI)
7699 17:44:08.969651 u2DelayCellOfst[6]=17 cells (5 PI)
7700 17:44:08.972837 u2DelayCellOfst[7]=17 cells (5 PI)
7701 17:44:08.976226 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7702 17:44:08.979793 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7703 17:44:08.982896 == TX Byte 1 ==
7704 17:44:08.982980 u2DelayCellOfst[8]=0 cells (0 PI)
7705 17:44:08.986121 u2DelayCellOfst[9]=0 cells (0 PI)
7706 17:44:08.989751 u2DelayCellOfst[10]=3 cells (1 PI)
7707 17:44:08.992707 u2DelayCellOfst[11]=0 cells (0 PI)
7708 17:44:08.996122 u2DelayCellOfst[12]=10 cells (3 PI)
7709 17:44:08.999319 u2DelayCellOfst[13]=6 cells (2 PI)
7710 17:44:09.002812 u2DelayCellOfst[14]=10 cells (3 PI)
7711 17:44:09.005974 u2DelayCellOfst[15]=10 cells (3 PI)
7712 17:44:09.009342 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7713 17:44:09.016246 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7714 17:44:09.016330 DramC Write-DBI on
7715 17:44:09.016396 ==
7716 17:44:09.019456 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 17:44:09.022672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 17:44:09.025869 ==
7719 17:44:09.025952
7720 17:44:09.026017
7721 17:44:09.026075 TX Vref Scan disable
7722 17:44:09.029331 == TX Byte 0 ==
7723 17:44:09.033146 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7724 17:44:09.035987 == TX Byte 1 ==
7725 17:44:09.039796 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7726 17:44:09.042869 DramC Write-DBI off
7727 17:44:09.042951
7728 17:44:09.043016 [DATLAT]
7729 17:44:09.043075 Freq=1600, CH0 RK0
7730 17:44:09.043133
7731 17:44:09.045990 DATLAT Default: 0xf
7732 17:44:09.046071 0, 0xFFFF, sum = 0
7733 17:44:09.049453 1, 0xFFFF, sum = 0
7734 17:44:09.053016 2, 0xFFFF, sum = 0
7735 17:44:09.053099 3, 0xFFFF, sum = 0
7736 17:44:09.056034 4, 0xFFFF, sum = 0
7737 17:44:09.056117 5, 0xFFFF, sum = 0
7738 17:44:09.059765 6, 0xFFFF, sum = 0
7739 17:44:09.059848 7, 0xFFFF, sum = 0
7740 17:44:09.062736 8, 0xFFFF, sum = 0
7741 17:44:09.062819 9, 0xFFFF, sum = 0
7742 17:44:09.065912 10, 0xFFFF, sum = 0
7743 17:44:09.065995 11, 0xFFFF, sum = 0
7744 17:44:09.069261 12, 0xFFFF, sum = 0
7745 17:44:09.069361 13, 0xFFFF, sum = 0
7746 17:44:09.072791 14, 0x0, sum = 1
7747 17:44:09.072869 15, 0x0, sum = 2
7748 17:44:09.075877 16, 0x0, sum = 3
7749 17:44:09.075961 17, 0x0, sum = 4
7750 17:44:09.079126 best_step = 15
7751 17:44:09.079208
7752 17:44:09.079272 ==
7753 17:44:09.082755 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 17:44:09.085934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 17:44:09.086031 ==
7756 17:44:09.086110 RX Vref Scan: 1
7757 17:44:09.089613
7758 17:44:09.089717 Set Vref Range= 24 -> 127
7759 17:44:09.089811
7760 17:44:09.092611 RX Vref 24 -> 127, step: 1
7761 17:44:09.092693
7762 17:44:09.095948 RX Delay 19 -> 252, step: 4
7763 17:44:09.096046
7764 17:44:09.099225 Set Vref, RX VrefLevel [Byte0]: 24
7765 17:44:09.102615 [Byte1]: 24
7766 17:44:09.102712
7767 17:44:09.105723 Set Vref, RX VrefLevel [Byte0]: 25
7768 17:44:09.109162 [Byte1]: 25
7769 17:44:09.109259
7770 17:44:09.112286 Set Vref, RX VrefLevel [Byte0]: 26
7771 17:44:09.115690 [Byte1]: 26
7772 17:44:09.119880
7773 17:44:09.119962 Set Vref, RX VrefLevel [Byte0]: 27
7774 17:44:09.123242 [Byte1]: 27
7775 17:44:09.127165
7776 17:44:09.127249 Set Vref, RX VrefLevel [Byte0]: 28
7777 17:44:09.130651 [Byte1]: 28
7778 17:44:09.134725
7779 17:44:09.134808 Set Vref, RX VrefLevel [Byte0]: 29
7780 17:44:09.138273 [Byte1]: 29
7781 17:44:09.142630
7782 17:44:09.142713 Set Vref, RX VrefLevel [Byte0]: 30
7783 17:44:09.145644 [Byte1]: 30
7784 17:44:09.150250
7785 17:44:09.150334 Set Vref, RX VrefLevel [Byte0]: 31
7786 17:44:09.153273 [Byte1]: 31
7787 17:44:09.157499
7788 17:44:09.157582 Set Vref, RX VrefLevel [Byte0]: 32
7789 17:44:09.161236 [Byte1]: 32
7790 17:44:09.165080
7791 17:44:09.165163 Set Vref, RX VrefLevel [Byte0]: 33
7792 17:44:09.168799 [Byte1]: 33
7793 17:44:09.173036
7794 17:44:09.173120 Set Vref, RX VrefLevel [Byte0]: 34
7795 17:44:09.176062 [Byte1]: 34
7796 17:44:09.180638
7797 17:44:09.180748 Set Vref, RX VrefLevel [Byte0]: 35
7798 17:44:09.183761 [Byte1]: 35
7799 17:44:09.187751
7800 17:44:09.187867 Set Vref, RX VrefLevel [Byte0]: 36
7801 17:44:09.191437 [Byte1]: 36
7802 17:44:09.195639
7803 17:44:09.195747 Set Vref, RX VrefLevel [Byte0]: 37
7804 17:44:09.198746 [Byte1]: 37
7805 17:44:09.203227
7806 17:44:09.203310 Set Vref, RX VrefLevel [Byte0]: 38
7807 17:44:09.206488 [Byte1]: 38
7808 17:44:09.210428
7809 17:44:09.210528 Set Vref, RX VrefLevel [Byte0]: 39
7810 17:44:09.214072 [Byte1]: 39
7811 17:44:09.218162
7812 17:44:09.218235 Set Vref, RX VrefLevel [Byte0]: 40
7813 17:44:09.221371 [Byte1]: 40
7814 17:44:09.225770
7815 17:44:09.225878 Set Vref, RX VrefLevel [Byte0]: 41
7816 17:44:09.228921 [Byte1]: 41
7817 17:44:09.233390
7818 17:44:09.233462 Set Vref, RX VrefLevel [Byte0]: 42
7819 17:44:09.236599 [Byte1]: 42
7820 17:44:09.241072
7821 17:44:09.241156 Set Vref, RX VrefLevel [Byte0]: 43
7822 17:44:09.244350 [Byte1]: 43
7823 17:44:09.248679
7824 17:44:09.248790 Set Vref, RX VrefLevel [Byte0]: 44
7825 17:44:09.251639 [Byte1]: 44
7826 17:44:09.256019
7827 17:44:09.256121 Set Vref, RX VrefLevel [Byte0]: 45
7828 17:44:09.259171 [Byte1]: 45
7829 17:44:09.263589
7830 17:44:09.263663 Set Vref, RX VrefLevel [Byte0]: 46
7831 17:44:09.267212 [Byte1]: 46
7832 17:44:09.270962
7833 17:44:09.271065 Set Vref, RX VrefLevel [Byte0]: 47
7834 17:44:09.274325 [Byte1]: 47
7835 17:44:09.278557
7836 17:44:09.278637 Set Vref, RX VrefLevel [Byte0]: 48
7837 17:44:09.281909 [Byte1]: 48
7838 17:44:09.286369
7839 17:44:09.286443 Set Vref, RX VrefLevel [Byte0]: 49
7840 17:44:09.289490 [Byte1]: 49
7841 17:44:09.294062
7842 17:44:09.294145 Set Vref, RX VrefLevel [Byte0]: 50
7843 17:44:09.297203 [Byte1]: 50
7844 17:44:09.301504
7845 17:44:09.301579 Set Vref, RX VrefLevel [Byte0]: 51
7846 17:44:09.304913 [Byte1]: 51
7847 17:44:09.309329
7848 17:44:09.309412 Set Vref, RX VrefLevel [Byte0]: 52
7849 17:44:09.312389 [Byte1]: 52
7850 17:44:09.316885
7851 17:44:09.316992 Set Vref, RX VrefLevel [Byte0]: 53
7852 17:44:09.319954 [Byte1]: 53
7853 17:44:09.323956
7854 17:44:09.324038 Set Vref, RX VrefLevel [Byte0]: 54
7855 17:44:09.327532 [Byte1]: 54
7856 17:44:09.331620
7857 17:44:09.331727 Set Vref, RX VrefLevel [Byte0]: 55
7858 17:44:09.334999 [Byte1]: 55
7859 17:44:09.339080
7860 17:44:09.339154 Set Vref, RX VrefLevel [Byte0]: 56
7861 17:44:09.342714 [Byte1]: 56
7862 17:44:09.346803
7863 17:44:09.346875 Set Vref, RX VrefLevel [Byte0]: 57
7864 17:44:09.350326 [Byte1]: 57
7865 17:44:09.354361
7866 17:44:09.354444 Set Vref, RX VrefLevel [Byte0]: 58
7867 17:44:09.357637 [Byte1]: 58
7868 17:44:09.362116
7869 17:44:09.362220 Set Vref, RX VrefLevel [Byte0]: 59
7870 17:44:09.365175 [Byte1]: 59
7871 17:44:09.369832
7872 17:44:09.369936 Set Vref, RX VrefLevel [Byte0]: 60
7873 17:44:09.372838 [Byte1]: 60
7874 17:44:09.377060
7875 17:44:09.377138 Set Vref, RX VrefLevel [Byte0]: 61
7876 17:44:09.380362 [Byte1]: 61
7877 17:44:09.384860
7878 17:44:09.384951 Set Vref, RX VrefLevel [Byte0]: 62
7879 17:44:09.388051 [Byte1]: 62
7880 17:44:09.392544
7881 17:44:09.392627 Set Vref, RX VrefLevel [Byte0]: 63
7882 17:44:09.395710 [Byte1]: 63
7883 17:44:09.399705
7884 17:44:09.403425 Set Vref, RX VrefLevel [Byte0]: 64
7885 17:44:09.403509 [Byte1]: 64
7886 17:44:09.407353
7887 17:44:09.407436 Set Vref, RX VrefLevel [Byte0]: 65
7888 17:44:09.410709 [Byte1]: 65
7889 17:44:09.415268
7890 17:44:09.415351 Set Vref, RX VrefLevel [Byte0]: 66
7891 17:44:09.418373 [Byte1]: 66
7892 17:44:09.422494
7893 17:44:09.422577 Set Vref, RX VrefLevel [Byte0]: 67
7894 17:44:09.425678 [Byte1]: 67
7895 17:44:09.430144
7896 17:44:09.430227 Set Vref, RX VrefLevel [Byte0]: 68
7897 17:44:09.433553 [Byte1]: 68
7898 17:44:09.437526
7899 17:44:09.437609 Set Vref, RX VrefLevel [Byte0]: 69
7900 17:44:09.440970 [Byte1]: 69
7901 17:44:09.445480
7902 17:44:09.445563 Set Vref, RX VrefLevel [Byte0]: 70
7903 17:44:09.448572 [Byte1]: 70
7904 17:44:09.452968
7905 17:44:09.453051 Set Vref, RX VrefLevel [Byte0]: 71
7906 17:44:09.456269 [Byte1]: 71
7907 17:44:09.460528
7908 17:44:09.460612 Set Vref, RX VrefLevel [Byte0]: 72
7909 17:44:09.463564 [Byte1]: 72
7910 17:44:09.468199
7911 17:44:09.468282 Set Vref, RX VrefLevel [Byte0]: 73
7912 17:44:09.471477 [Byte1]: 73
7913 17:44:09.475431
7914 17:44:09.475546 Set Vref, RX VrefLevel [Byte0]: 74
7915 17:44:09.479146 [Byte1]: 74
7916 17:44:09.483031
7917 17:44:09.483116 Set Vref, RX VrefLevel [Byte0]: 75
7918 17:44:09.486615 [Byte1]: 75
7919 17:44:09.491009
7920 17:44:09.491095 Set Vref, RX VrefLevel [Byte0]: 76
7921 17:44:09.494001 [Byte1]: 76
7922 17:44:09.498182
7923 17:44:09.498268 Set Vref, RX VrefLevel [Byte0]: 77
7924 17:44:09.501873 [Byte1]: 77
7925 17:44:09.505830
7926 17:44:09.505916 Set Vref, RX VrefLevel [Byte0]: 78
7927 17:44:09.509460 [Byte1]: 78
7928 17:44:09.513642
7929 17:44:09.513728 Set Vref, RX VrefLevel [Byte0]: 79
7930 17:44:09.516694 [Byte1]: 79
7931 17:44:09.521021
7932 17:44:09.521106 Final RX Vref Byte 0 = 61 to rank0
7933 17:44:09.524589 Final RX Vref Byte 1 = 59 to rank0
7934 17:44:09.527694 Final RX Vref Byte 0 = 61 to rank1
7935 17:44:09.530919 Final RX Vref Byte 1 = 59 to rank1==
7936 17:44:09.534445 Dram Type= 6, Freq= 0, CH_0, rank 0
7937 17:44:09.541244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7938 17:44:09.541332 ==
7939 17:44:09.541418 DQS Delay:
7940 17:44:09.541499 DQS0 = 0, DQS1 = 0
7941 17:44:09.544500 DQM Delay:
7942 17:44:09.544585 DQM0 = 137, DQM1 = 124
7943 17:44:09.547577 DQ Delay:
7944 17:44:09.551059 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7945 17:44:09.554411 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7946 17:44:09.557859 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7947 17:44:09.561107 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7948 17:44:09.561193
7949 17:44:09.561279
7950 17:44:09.561359
7951 17:44:09.564498 [DramC_TX_OE_Calibration] TA2
7952 17:44:09.567912 Original DQ_B0 (3 6) =30, OEN = 27
7953 17:44:09.571007 Original DQ_B1 (3 6) =30, OEN = 27
7954 17:44:09.574345 24, 0x0, End_B0=24 End_B1=24
7955 17:44:09.574432 25, 0x0, End_B0=25 End_B1=25
7956 17:44:09.577731 26, 0x0, End_B0=26 End_B1=26
7957 17:44:09.580861 27, 0x0, End_B0=27 End_B1=27
7958 17:44:09.584534 28, 0x0, End_B0=28 End_B1=28
7959 17:44:09.584621 29, 0x0, End_B0=29 End_B1=29
7960 17:44:09.588016 30, 0x0, End_B0=30 End_B1=30
7961 17:44:09.591110 31, 0x4141, End_B0=30 End_B1=30
7962 17:44:09.594238 Byte0 end_step=30 best_step=27
7963 17:44:09.597456 Byte1 end_step=30 best_step=27
7964 17:44:09.600686 Byte0 TX OE(2T, 0.5T) = (3, 3)
7965 17:44:09.600772 Byte1 TX OE(2T, 0.5T) = (3, 3)
7966 17:44:09.604019
7967 17:44:09.604103
7968 17:44:09.610732 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7969 17:44:09.613998 CH0 RK0: MR19=303, MR18=1D1B
7970 17:44:09.620473 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7971 17:44:09.620559
7972 17:44:09.624317 ----->DramcWriteLeveling(PI) begin...
7973 17:44:09.624403 ==
7974 17:44:09.627397 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 17:44:09.630918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 17:44:09.631005 ==
7977 17:44:09.634020 Write leveling (Byte 0): 38 => 38
7978 17:44:09.637289 Write leveling (Byte 1): 27 => 27
7979 17:44:09.640766 DramcWriteLeveling(PI) end<-----
7980 17:44:09.640876
7981 17:44:09.640984 ==
7982 17:44:09.644131 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 17:44:09.647379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 17:44:09.647464 ==
7985 17:44:09.650498 [Gating] SW mode calibration
7986 17:44:09.657175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7987 17:44:09.663680 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7988 17:44:09.667391 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 17:44:09.670591 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 17:44:09.677155 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 17:44:09.680629 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7992 17:44:09.683851 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 17:44:09.690423 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 17:44:09.693796 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 17:44:09.697265 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 17:44:09.703893 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 17:44:09.706844 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 17:44:09.710095 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 17:44:09.716857 1 5 12 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 1)
8000 17:44:09.720261 1 5 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8001 17:44:09.723560 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 17:44:09.730027 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 17:44:09.733506 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 17:44:09.736844 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 17:44:09.743495 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 17:44:09.746720 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 17:44:09.750016 1 6 12 | B1->B0 | 2d2d 4242 | 1 1 | (1 1) (0 0)
8008 17:44:09.756728 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 17:44:09.760315 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 17:44:09.763503 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 17:44:09.770350 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 17:44:09.773677 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 17:44:09.776730 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 17:44:09.780390 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 17:44:09.786820 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8016 17:44:09.790275 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8017 17:44:09.793347 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8018 17:44:09.799954 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 17:44:09.803424 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 17:44:09.806814 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 17:44:09.813118 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 17:44:09.816881 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 17:44:09.819883 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 17:44:09.826743 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 17:44:09.829618 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 17:44:09.833193 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 17:44:09.839703 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 17:44:09.843405 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 17:44:09.846566 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 17:44:09.853193 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 17:44:09.856303 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8032 17:44:09.860008 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8033 17:44:09.863186 Total UI for P1: 0, mck2ui 16
8034 17:44:09.866262 best dqsien dly found for B0: ( 1, 9, 12)
8035 17:44:09.872968 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 17:44:09.873059 Total UI for P1: 0, mck2ui 16
8037 17:44:09.879610 best dqsien dly found for B1: ( 1, 9, 14)
8038 17:44:09.883152 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8039 17:44:09.886240 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8040 17:44:09.886323
8041 17:44:09.889964 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8042 17:44:09.892912 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8043 17:44:09.896077 [Gating] SW calibration Done
8044 17:44:09.896177 ==
8045 17:44:09.899671 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 17:44:09.902865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 17:44:09.902948 ==
8048 17:44:09.906220 RX Vref Scan: 0
8049 17:44:09.906302
8050 17:44:09.906367 RX Vref 0 -> 0, step: 1
8051 17:44:09.906427
8052 17:44:09.909479 RX Delay 0 -> 252, step: 8
8053 17:44:09.913008 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8054 17:44:09.919380 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8055 17:44:09.922648 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8056 17:44:09.925920 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8057 17:44:09.929378 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8058 17:44:09.932714 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8059 17:44:09.939417 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8060 17:44:09.942731 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8061 17:44:09.946243 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8062 17:44:09.949451 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8063 17:44:09.952874 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8064 17:44:09.959319 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8065 17:44:09.962916 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8066 17:44:09.965885 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8067 17:44:09.969480 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8068 17:44:09.972596 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8069 17:44:09.975764 ==
8070 17:44:09.979256 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 17:44:09.982580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 17:44:09.982663 ==
8073 17:44:09.982729 DQS Delay:
8074 17:44:09.985753 DQS0 = 0, DQS1 = 0
8075 17:44:09.985835 DQM Delay:
8076 17:44:09.989083 DQM0 = 135, DQM1 = 125
8077 17:44:09.989165 DQ Delay:
8078 17:44:09.992578 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8079 17:44:09.995685 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8080 17:44:09.998856 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8081 17:44:10.002446 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8082 17:44:10.002529
8083 17:44:10.002594
8084 17:44:10.002653 ==
8085 17:44:10.005740 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 17:44:10.012268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 17:44:10.012354 ==
8088 17:44:10.012419
8089 17:44:10.012478
8090 17:44:10.012535 TX Vref Scan disable
8091 17:44:10.016145 == TX Byte 0 ==
8092 17:44:10.019274 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8093 17:44:10.026477 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8094 17:44:10.026560 == TX Byte 1 ==
8095 17:44:10.029533 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8096 17:44:10.036011 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8097 17:44:10.036093 ==
8098 17:44:10.039313 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 17:44:10.042936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 17:44:10.043020 ==
8101 17:44:10.057534
8102 17:44:10.061110 TX Vref early break, caculate TX vref
8103 17:44:10.064197 TX Vref=16, minBit 0, minWin=23, winSum=384
8104 17:44:10.067443 TX Vref=18, minBit 2, minWin=23, winSum=390
8105 17:44:10.071035 TX Vref=20, minBit 8, minWin=24, winSum=404
8106 17:44:10.074074 TX Vref=22, minBit 0, minWin=25, winSum=412
8107 17:44:10.077750 TX Vref=24, minBit 4, minWin=25, winSum=419
8108 17:44:10.084058 TX Vref=26, minBit 0, minWin=26, winSum=427
8109 17:44:10.087411 TX Vref=28, minBit 0, minWin=26, winSum=428
8110 17:44:10.090521 TX Vref=30, minBit 4, minWin=25, winSum=425
8111 17:44:10.094173 TX Vref=32, minBit 8, minWin=25, winSum=420
8112 17:44:10.097201 TX Vref=34, minBit 0, minWin=25, winSum=406
8113 17:44:10.100427 TX Vref=36, minBit 2, minWin=24, winSum=400
8114 17:44:10.107233 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8115 17:44:10.107316
8116 17:44:10.110609 Final TX Range 0 Vref 28
8117 17:44:10.110692
8118 17:44:10.110757 ==
8119 17:44:10.113812 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 17:44:10.117147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 17:44:10.117259 ==
8122 17:44:10.117327
8123 17:44:10.117388
8124 17:44:10.120551 TX Vref Scan disable
8125 17:44:10.127219 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8126 17:44:10.127302 == TX Byte 0 ==
8127 17:44:10.130785 u2DelayCellOfst[0]=10 cells (3 PI)
8128 17:44:10.133627 u2DelayCellOfst[1]=17 cells (5 PI)
8129 17:44:10.137223 u2DelayCellOfst[2]=10 cells (3 PI)
8130 17:44:10.140476 u2DelayCellOfst[3]=13 cells (4 PI)
8131 17:44:10.143816 u2DelayCellOfst[4]=6 cells (2 PI)
8132 17:44:10.147585 u2DelayCellOfst[5]=0 cells (0 PI)
8133 17:44:10.150803 u2DelayCellOfst[6]=17 cells (5 PI)
8134 17:44:10.154101 u2DelayCellOfst[7]=17 cells (5 PI)
8135 17:44:10.157055 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8136 17:44:10.160633 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8137 17:44:10.163735 == TX Byte 1 ==
8138 17:44:10.166857 u2DelayCellOfst[8]=3 cells (1 PI)
8139 17:44:10.170554 u2DelayCellOfst[9]=0 cells (0 PI)
8140 17:44:10.173733 u2DelayCellOfst[10]=6 cells (2 PI)
8141 17:44:10.173815 u2DelayCellOfst[11]=3 cells (1 PI)
8142 17:44:10.177253 u2DelayCellOfst[12]=13 cells (4 PI)
8143 17:44:10.180401 u2DelayCellOfst[13]=13 cells (4 PI)
8144 17:44:10.183532 u2DelayCellOfst[14]=13 cells (4 PI)
8145 17:44:10.187188 u2DelayCellOfst[15]=10 cells (3 PI)
8146 17:44:10.193712 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8147 17:44:10.197077 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8148 17:44:10.197160 DramC Write-DBI on
8149 17:44:10.197226 ==
8150 17:44:10.200606 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 17:44:10.207000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 17:44:10.207114 ==
8153 17:44:10.207209
8154 17:44:10.207275
8155 17:44:10.207333 TX Vref Scan disable
8156 17:44:10.211458 == TX Byte 0 ==
8157 17:44:10.214543 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8158 17:44:10.217691 == TX Byte 1 ==
8159 17:44:10.221436 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8160 17:44:10.224596 DramC Write-DBI off
8161 17:44:10.224678
8162 17:44:10.224742 [DATLAT]
8163 17:44:10.224804 Freq=1600, CH0 RK1
8164 17:44:10.224863
8165 17:44:10.228005 DATLAT Default: 0xf
8166 17:44:10.228087 0, 0xFFFF, sum = 0
8167 17:44:10.230989 1, 0xFFFF, sum = 0
8168 17:44:10.231074 2, 0xFFFF, sum = 0
8169 17:44:10.234543 3, 0xFFFF, sum = 0
8170 17:44:10.238097 4, 0xFFFF, sum = 0
8171 17:44:10.238181 5, 0xFFFF, sum = 0
8172 17:44:10.240898 6, 0xFFFF, sum = 0
8173 17:44:10.241022 7, 0xFFFF, sum = 0
8174 17:44:10.244246 8, 0xFFFF, sum = 0
8175 17:44:10.244330 9, 0xFFFF, sum = 0
8176 17:44:10.247999 10, 0xFFFF, sum = 0
8177 17:44:10.248082 11, 0xFFFF, sum = 0
8178 17:44:10.251055 12, 0xFFFF, sum = 0
8179 17:44:10.251139 13, 0xFFFF, sum = 0
8180 17:44:10.254333 14, 0x0, sum = 1
8181 17:44:10.254417 15, 0x0, sum = 2
8182 17:44:10.257533 16, 0x0, sum = 3
8183 17:44:10.257637 17, 0x0, sum = 4
8184 17:44:10.261074 best_step = 15
8185 17:44:10.261156
8186 17:44:10.261220 ==
8187 17:44:10.264218 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 17:44:10.267469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 17:44:10.267553 ==
8190 17:44:10.270877 RX Vref Scan: 0
8191 17:44:10.270960
8192 17:44:10.271025 RX Vref 0 -> 0, step: 1
8193 17:44:10.271085
8194 17:44:10.274239 RX Delay 11 -> 252, step: 4
8195 17:44:10.277592 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8196 17:44:10.284183 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8197 17:44:10.287474 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8198 17:44:10.290622 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8199 17:44:10.294175 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8200 17:44:10.297751 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8201 17:44:10.303781 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8202 17:44:10.307084 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8203 17:44:10.310580 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8204 17:44:10.313966 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8205 17:44:10.317275 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8206 17:44:10.323528 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8207 17:44:10.327150 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8208 17:44:10.330291 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8209 17:44:10.333719 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8210 17:44:10.340365 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8211 17:44:10.340446 ==
8212 17:44:10.344043 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 17:44:10.346962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 17:44:10.347045 ==
8215 17:44:10.347109 DQS Delay:
8216 17:44:10.350516 DQS0 = 0, DQS1 = 0
8217 17:44:10.350597 DQM Delay:
8218 17:44:10.353498 DQM0 = 133, DQM1 = 123
8219 17:44:10.353579 DQ Delay:
8220 17:44:10.357350 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8221 17:44:10.360371 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8222 17:44:10.363882 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8223 17:44:10.366968 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8224 17:44:10.367050
8225 17:44:10.367114
8226 17:44:10.367173
8227 17:44:10.370464 [DramC_TX_OE_Calibration] TA2
8228 17:44:10.373615 Original DQ_B0 (3 6) =30, OEN = 27
8229 17:44:10.376808 Original DQ_B1 (3 6) =30, OEN = 27
8230 17:44:10.380119 24, 0x0, End_B0=24 End_B1=24
8231 17:44:10.383505 25, 0x0, End_B0=25 End_B1=25
8232 17:44:10.383590 26, 0x0, End_B0=26 End_B1=26
8233 17:44:10.387030 27, 0x0, End_B0=27 End_B1=27
8234 17:44:10.390093 28, 0x0, End_B0=28 End_B1=28
8235 17:44:10.393675 29, 0x0, End_B0=29 End_B1=29
8236 17:44:10.396999 30, 0x0, End_B0=30 End_B1=30
8237 17:44:10.397084 31, 0x4141, End_B0=30 End_B1=30
8238 17:44:10.400288 Byte0 end_step=30 best_step=27
8239 17:44:10.403481 Byte1 end_step=30 best_step=27
8240 17:44:10.407205 Byte0 TX OE(2T, 0.5T) = (3, 3)
8241 17:44:10.410179 Byte1 TX OE(2T, 0.5T) = (3, 3)
8242 17:44:10.410263
8243 17:44:10.410328
8244 17:44:10.416618 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8245 17:44:10.420285 CH0 RK1: MR19=303, MR18=200D
8246 17:44:10.426858 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8247 17:44:10.430303 [RxdqsGatingPostProcess] freq 1600
8248 17:44:10.436826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8249 17:44:10.436911 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 17:44:10.439986 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 17:44:10.443124 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 17:44:10.446725 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 17:44:10.450041 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 17:44:10.453123 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 17:44:10.456502 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 17:44:10.460147 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 17:44:10.463276 Pre-setting of DQS Precalculation
8258 17:44:10.466445 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8259 17:44:10.466529 ==
8260 17:44:10.469923 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 17:44:10.476239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 17:44:10.476324 ==
8263 17:44:10.480049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 17:44:10.486476 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 17:44:10.489732 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 17:44:10.496236 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 17:44:10.504033 [CA 0] Center 40 (11~70) winsize 60
8268 17:44:10.507605 [CA 1] Center 41 (11~71) winsize 61
8269 17:44:10.510820 [CA 2] Center 37 (7~67) winsize 61
8270 17:44:10.513947 [CA 3] Center 36 (7~66) winsize 60
8271 17:44:10.517604 [CA 4] Center 36 (7~66) winsize 60
8272 17:44:10.520633 [CA 5] Center 36 (6~66) winsize 61
8273 17:44:10.520738
8274 17:44:10.523923 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8275 17:44:10.524021
8276 17:44:10.527040 [CATrainingPosCal] consider 1 rank data
8277 17:44:10.530921 u2DelayCellTimex100 = 285/100 ps
8278 17:44:10.537177 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8279 17:44:10.540565 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8280 17:44:10.543987 CA2 delay=37 (7~67),Diff = 1 PI (3 cell)
8281 17:44:10.547347 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8282 17:44:10.550253 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8283 17:44:10.553879 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8284 17:44:10.553954
8285 17:44:10.557114 CA PerBit enable=1, Macro0, CA PI delay=36
8286 17:44:10.557211
8287 17:44:10.560608 [CBTSetCACLKResult] CA Dly = 36
8288 17:44:10.563531 CS Dly: 9 (0~40)
8289 17:44:10.566828 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 17:44:10.570113 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 17:44:10.570217 ==
8292 17:44:10.573590 Dram Type= 6, Freq= 0, CH_1, rank 1
8293 17:44:10.577011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 17:44:10.580163 ==
8295 17:44:10.583454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 17:44:10.586575 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 17:44:10.593342 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 17:44:10.599777 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 17:44:10.607124 [CA 0] Center 42 (13~72) winsize 60
8300 17:44:10.610333 [CA 1] Center 42 (12~72) winsize 61
8301 17:44:10.613966 [CA 2] Center 39 (10~68) winsize 59
8302 17:44:10.617141 [CA 3] Center 37 (8~67) winsize 60
8303 17:44:10.620243 [CA 4] Center 38 (9~68) winsize 60
8304 17:44:10.623815 [CA 5] Center 37 (8~67) winsize 60
8305 17:44:10.623897
8306 17:44:10.627141 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 17:44:10.627223
8308 17:44:10.630107 [CATrainingPosCal] consider 2 rank data
8309 17:44:10.633848 u2DelayCellTimex100 = 285/100 ps
8310 17:44:10.640149 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8311 17:44:10.643419 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8312 17:44:10.646741 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8313 17:44:10.650105 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8314 17:44:10.653716 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8315 17:44:10.657072 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8316 17:44:10.657153
8317 17:44:10.660273 CA PerBit enable=1, Macro0, CA PI delay=37
8318 17:44:10.660355
8319 17:44:10.663398 [CBTSetCACLKResult] CA Dly = 37
8320 17:44:10.666513 CS Dly: 9 (0~41)
8321 17:44:10.669917 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 17:44:10.673293 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 17:44:10.673375
8324 17:44:10.676360 ----->DramcWriteLeveling(PI) begin...
8325 17:44:10.676441 ==
8326 17:44:10.679785 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 17:44:10.686666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 17:44:10.686748 ==
8329 17:44:10.689943 Write leveling (Byte 0): 23 => 23
8330 17:44:10.693005 Write leveling (Byte 1): 28 => 28
8331 17:44:10.693089 DramcWriteLeveling(PI) end<-----
8332 17:44:10.693154
8333 17:44:10.696429 ==
8334 17:44:10.699922 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 17:44:10.703018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 17:44:10.703102 ==
8337 17:44:10.706377 [Gating] SW mode calibration
8338 17:44:10.712966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8339 17:44:10.716406 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8340 17:44:10.722705 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 17:44:10.726241 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 17:44:10.729392 1 4 8 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
8343 17:44:10.736249 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8344 17:44:10.739425 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 17:44:10.742641 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 17:44:10.749525 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 17:44:10.752542 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 17:44:10.755747 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 17:44:10.762822 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 17:44:10.765894 1 5 8 | B1->B0 | 3030 2a2a | 1 0 | (1 0) (1 0)
8351 17:44:10.769133 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8352 17:44:10.775801 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 17:44:10.779138 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 17:44:10.782590 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 17:44:10.788799 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 17:44:10.792371 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 17:44:10.795406 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8358 17:44:10.802300 1 6 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
8359 17:44:10.806088 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 17:44:10.808978 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 17:44:10.815371 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 17:44:10.818841 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 17:44:10.821835 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 17:44:10.828379 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 17:44:10.831843 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 17:44:10.835131 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8367 17:44:10.842251 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8368 17:44:10.845197 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 17:44:10.848869 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 17:44:10.855017 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 17:44:10.858574 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 17:44:10.861666 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 17:44:10.868725 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 17:44:10.871781 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 17:44:10.875270 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 17:44:10.881829 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 17:44:10.885008 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 17:44:10.888250 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 17:44:10.895006 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 17:44:10.898143 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 17:44:10.901486 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8382 17:44:10.908541 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8383 17:44:10.911598 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 17:44:10.914825 Total UI for P1: 0, mck2ui 16
8385 17:44:10.917870 best dqsien dly found for B0: ( 1, 9, 6)
8386 17:44:10.921395 Total UI for P1: 0, mck2ui 16
8387 17:44:10.924977 best dqsien dly found for B1: ( 1, 9, 8)
8388 17:44:10.927987 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8389 17:44:10.931586 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8390 17:44:10.932022
8391 17:44:10.934800 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8392 17:44:10.937929 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8393 17:44:10.941052 [Gating] SW calibration Done
8394 17:44:10.941518 ==
8395 17:44:10.944689 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 17:44:10.947774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 17:44:10.948244 ==
8398 17:44:10.951306 RX Vref Scan: 0
8399 17:44:10.951771
8400 17:44:10.954291 RX Vref 0 -> 0, step: 1
8401 17:44:10.954755
8402 17:44:10.955118 RX Delay 0 -> 252, step: 8
8403 17:44:10.961169 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8404 17:44:10.964514 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8405 17:44:10.967879 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8406 17:44:10.971190 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8407 17:44:10.974381 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8408 17:44:10.980834 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8409 17:44:10.984061 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8410 17:44:10.987341 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8411 17:44:10.990899 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8412 17:44:10.993992 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8413 17:44:11.000585 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8414 17:44:11.004068 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8415 17:44:11.007420 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8416 17:44:11.010627 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8417 17:44:11.013990 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8418 17:44:11.020773 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8419 17:44:11.021346 ==
8420 17:44:11.023843 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 17:44:11.027536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 17:44:11.028039 ==
8423 17:44:11.028432 DQS Delay:
8424 17:44:11.031046 DQS0 = 0, DQS1 = 0
8425 17:44:11.031542 DQM Delay:
8426 17:44:11.033878 DQM0 = 136, DQM1 = 130
8427 17:44:11.034410 DQ Delay:
8428 17:44:11.037213 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8429 17:44:11.040494 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =131
8430 17:44:11.044149 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8431 17:44:11.047517 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8432 17:44:11.047959
8433 17:44:11.050659
8434 17:44:11.051111 ==
8435 17:44:11.053971 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 17:44:11.057219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 17:44:11.057660 ==
8438 17:44:11.058017
8439 17:44:11.058354
8440 17:44:11.060839 TX Vref Scan disable
8441 17:44:11.061325 == TX Byte 0 ==
8442 17:44:11.067342 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8443 17:44:11.070416 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8444 17:44:11.070867 == TX Byte 1 ==
8445 17:44:11.077031 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8446 17:44:11.080150 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8447 17:44:11.080609 ==
8448 17:44:11.083901 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 17:44:11.086971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 17:44:11.087535 ==
8451 17:44:11.100507
8452 17:44:11.103539 TX Vref early break, caculate TX vref
8453 17:44:11.107160 TX Vref=16, minBit 10, minWin=20, winSum=360
8454 17:44:11.110659 TX Vref=18, minBit 8, minWin=22, winSum=375
8455 17:44:11.113926 TX Vref=20, minBit 10, minWin=22, winSum=385
8456 17:44:11.116897 TX Vref=22, minBit 10, minWin=22, winSum=395
8457 17:44:11.120317 TX Vref=24, minBit 10, minWin=23, winSum=404
8458 17:44:11.127118 TX Vref=26, minBit 10, minWin=24, winSum=411
8459 17:44:11.130188 TX Vref=28, minBit 12, minWin=25, winSum=419
8460 17:44:11.133603 TX Vref=30, minBit 9, minWin=24, winSum=414
8461 17:44:11.136819 TX Vref=32, minBit 8, minWin=24, winSum=406
8462 17:44:11.139957 TX Vref=34, minBit 9, minWin=23, winSum=395
8463 17:44:11.146738 [TxChooseVref] Worse bit 12, Min win 25, Win sum 419, Final Vref 28
8464 17:44:11.146863
8465 17:44:11.150025 Final TX Range 0 Vref 28
8466 17:44:11.150141
8467 17:44:11.150240 ==
8468 17:44:11.153134 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 17:44:11.156903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 17:44:11.157033 ==
8471 17:44:11.157139
8472 17:44:11.157234
8473 17:44:11.160026 TX Vref Scan disable
8474 17:44:11.166803 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8475 17:44:11.166926 == TX Byte 0 ==
8476 17:44:11.170168 u2DelayCellOfst[0]=17 cells (5 PI)
8477 17:44:11.173123 u2DelayCellOfst[1]=10 cells (3 PI)
8478 17:44:11.176849 u2DelayCellOfst[2]=0 cells (0 PI)
8479 17:44:11.179921 u2DelayCellOfst[3]=6 cells (2 PI)
8480 17:44:11.183491 u2DelayCellOfst[4]=6 cells (2 PI)
8481 17:44:11.186657 u2DelayCellOfst[5]=17 cells (5 PI)
8482 17:44:11.190056 u2DelayCellOfst[6]=17 cells (5 PI)
8483 17:44:11.193155 u2DelayCellOfst[7]=6 cells (2 PI)
8484 17:44:11.196398 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8485 17:44:11.200118 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8486 17:44:11.203338 == TX Byte 1 ==
8487 17:44:11.206705 u2DelayCellOfst[8]=0 cells (0 PI)
8488 17:44:11.207151 u2DelayCellOfst[9]=6 cells (2 PI)
8489 17:44:11.209943 u2DelayCellOfst[10]=10 cells (3 PI)
8490 17:44:11.213529 u2DelayCellOfst[11]=3 cells (1 PI)
8491 17:44:11.216804 u2DelayCellOfst[12]=17 cells (5 PI)
8492 17:44:11.220001 u2DelayCellOfst[13]=20 cells (6 PI)
8493 17:44:11.223301 u2DelayCellOfst[14]=20 cells (6 PI)
8494 17:44:11.226613 u2DelayCellOfst[15]=20 cells (6 PI)
8495 17:44:11.229907 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8496 17:44:11.236796 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8497 17:44:11.237300 DramC Write-DBI on
8498 17:44:11.237683 ==
8499 17:44:11.239820 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 17:44:11.246369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 17:44:11.246796 ==
8502 17:44:11.247163
8503 17:44:11.247515
8504 17:44:11.247849 TX Vref Scan disable
8505 17:44:11.250739 == TX Byte 0 ==
8506 17:44:11.253824 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8507 17:44:11.257461 == TX Byte 1 ==
8508 17:44:11.260127 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8509 17:44:11.263776 DramC Write-DBI off
8510 17:44:11.264333
8511 17:44:11.264882 [DATLAT]
8512 17:44:11.265274 Freq=1600, CH1 RK0
8513 17:44:11.265610
8514 17:44:11.266893 DATLAT Default: 0xf
8515 17:44:11.267384 0, 0xFFFF, sum = 0
8516 17:44:11.270203 1, 0xFFFF, sum = 0
8517 17:44:11.273523 2, 0xFFFF, sum = 0
8518 17:44:11.274165 3, 0xFFFF, sum = 0
8519 17:44:11.276847 4, 0xFFFF, sum = 0
8520 17:44:11.277543 5, 0xFFFF, sum = 0
8521 17:44:11.280090 6, 0xFFFF, sum = 0
8522 17:44:11.280563 7, 0xFFFF, sum = 0
8523 17:44:11.283618 8, 0xFFFF, sum = 0
8524 17:44:11.284271 9, 0xFFFF, sum = 0
8525 17:44:11.286997 10, 0xFFFF, sum = 0
8526 17:44:11.287427 11, 0xFFFF, sum = 0
8527 17:44:11.289973 12, 0xFFFF, sum = 0
8528 17:44:11.290544 13, 0xFFFF, sum = 0
8529 17:44:11.293294 14, 0x0, sum = 1
8530 17:44:11.293723 15, 0x0, sum = 2
8531 17:44:11.296836 16, 0x0, sum = 3
8532 17:44:11.297444 17, 0x0, sum = 4
8533 17:44:11.299998 best_step = 15
8534 17:44:11.300416
8535 17:44:11.300750 ==
8536 17:44:11.303394 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 17:44:11.306732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 17:44:11.307160 ==
8539 17:44:11.310242 RX Vref Scan: 1
8540 17:44:11.310673
8541 17:44:11.311051 Set Vref Range= 24 -> 127
8542 17:44:11.311624
8543 17:44:11.313235 RX Vref 24 -> 127, step: 1
8544 17:44:11.313659
8545 17:44:11.316609 RX Delay 19 -> 252, step: 4
8546 17:44:11.317072
8547 17:44:11.320136 Set Vref, RX VrefLevel [Byte0]: 24
8548 17:44:11.323261 [Byte1]: 24
8549 17:44:11.323684
8550 17:44:11.326618 Set Vref, RX VrefLevel [Byte0]: 25
8551 17:44:11.329931 [Byte1]: 25
8552 17:44:11.330355
8553 17:44:11.333573 Set Vref, RX VrefLevel [Byte0]: 26
8554 17:44:11.336430 [Byte1]: 26
8555 17:44:11.340741
8556 17:44:11.341205 Set Vref, RX VrefLevel [Byte0]: 27
8557 17:44:11.344080 [Byte1]: 27
8558 17:44:11.348125
8559 17:44:11.348596 Set Vref, RX VrefLevel [Byte0]: 28
8560 17:44:11.351529 [Byte1]: 28
8561 17:44:11.355729
8562 17:44:11.356148 Set Vref, RX VrefLevel [Byte0]: 29
8563 17:44:11.358829 [Byte1]: 29
8564 17:44:11.363323
8565 17:44:11.363744 Set Vref, RX VrefLevel [Byte0]: 30
8566 17:44:11.366682 [Byte1]: 30
8567 17:44:11.370863
8568 17:44:11.371284 Set Vref, RX VrefLevel [Byte0]: 31
8569 17:44:11.374087 [Byte1]: 31
8570 17:44:11.378419
8571 17:44:11.378834 Set Vref, RX VrefLevel [Byte0]: 32
8572 17:44:11.381844 [Byte1]: 32
8573 17:44:11.385848
8574 17:44:11.386265 Set Vref, RX VrefLevel [Byte0]: 33
8575 17:44:11.389370 [Byte1]: 33
8576 17:44:11.393844
8577 17:44:11.394259 Set Vref, RX VrefLevel [Byte0]: 34
8578 17:44:11.396923 [Byte1]: 34
8579 17:44:11.401304
8580 17:44:11.401722 Set Vref, RX VrefLevel [Byte0]: 35
8581 17:44:11.404402 [Byte1]: 35
8582 17:44:11.408593
8583 17:44:11.409185 Set Vref, RX VrefLevel [Byte0]: 36
8584 17:44:11.411956 [Byte1]: 36
8585 17:44:11.416155
8586 17:44:11.416579 Set Vref, RX VrefLevel [Byte0]: 37
8587 17:44:11.419679 [Byte1]: 37
8588 17:44:11.423961
8589 17:44:11.424386 Set Vref, RX VrefLevel [Byte0]: 38
8590 17:44:11.427406 [Byte1]: 38
8591 17:44:11.431727
8592 17:44:11.432161 Set Vref, RX VrefLevel [Byte0]: 39
8593 17:44:11.434928 [Byte1]: 39
8594 17:44:11.439015
8595 17:44:11.439481 Set Vref, RX VrefLevel [Byte0]: 40
8596 17:44:11.442329 [Byte1]: 40
8597 17:44:11.446622
8598 17:44:11.447057 Set Vref, RX VrefLevel [Byte0]: 41
8599 17:44:11.449916 [Byte1]: 41
8600 17:44:11.454112
8601 17:44:11.454517 Set Vref, RX VrefLevel [Byte0]: 42
8602 17:44:11.457780 [Byte1]: 42
8603 17:44:11.461597
8604 17:44:11.461980 Set Vref, RX VrefLevel [Byte0]: 43
8605 17:44:11.464883 [Byte1]: 43
8606 17:44:11.469154
8607 17:44:11.469530 Set Vref, RX VrefLevel [Byte0]: 44
8608 17:44:11.472608 [Byte1]: 44
8609 17:44:11.477054
8610 17:44:11.477464 Set Vref, RX VrefLevel [Byte0]: 45
8611 17:44:11.480172 [Byte1]: 45
8612 17:44:11.484356
8613 17:44:11.484815 Set Vref, RX VrefLevel [Byte0]: 46
8614 17:44:11.487772 [Byte1]: 46
8615 17:44:11.492397
8616 17:44:11.492856 Set Vref, RX VrefLevel [Byte0]: 47
8617 17:44:11.495362 [Byte1]: 47
8618 17:44:11.499512
8619 17:44:11.499978 Set Vref, RX VrefLevel [Byte0]: 48
8620 17:44:11.503397 [Byte1]: 48
8621 17:44:11.507415
8622 17:44:11.507874 Set Vref, RX VrefLevel [Byte0]: 49
8623 17:44:11.510343 [Byte1]: 49
8624 17:44:11.514788
8625 17:44:11.515250 Set Vref, RX VrefLevel [Byte0]: 50
8626 17:44:11.517893 [Byte1]: 50
8627 17:44:11.522443
8628 17:44:11.522905 Set Vref, RX VrefLevel [Byte0]: 51
8629 17:44:11.525582 [Byte1]: 51
8630 17:44:11.529932
8631 17:44:11.530394 Set Vref, RX VrefLevel [Byte0]: 52
8632 17:44:11.533063 [Byte1]: 52
8633 17:44:11.537531
8634 17:44:11.537989 Set Vref, RX VrefLevel [Byte0]: 53
8635 17:44:11.540736 [Byte1]: 53
8636 17:44:11.545219
8637 17:44:11.545680 Set Vref, RX VrefLevel [Byte0]: 54
8638 17:44:11.548302 [Byte1]: 54
8639 17:44:11.552562
8640 17:44:11.553054 Set Vref, RX VrefLevel [Byte0]: 55
8641 17:44:11.555816 [Byte1]: 55
8642 17:44:11.560426
8643 17:44:11.560887 Set Vref, RX VrefLevel [Byte0]: 56
8644 17:44:11.563902 [Byte1]: 56
8645 17:44:11.568005
8646 17:44:11.568477 Set Vref, RX VrefLevel [Byte0]: 57
8647 17:44:11.571269 [Byte1]: 57
8648 17:44:11.575158
8649 17:44:11.575703 Set Vref, RX VrefLevel [Byte0]: 58
8650 17:44:11.578931 [Byte1]: 58
8651 17:44:11.583003
8652 17:44:11.583474 Set Vref, RX VrefLevel [Byte0]: 59
8653 17:44:11.586232 [Byte1]: 59
8654 17:44:11.590744
8655 17:44:11.591212 Set Vref, RX VrefLevel [Byte0]: 60
8656 17:44:11.593710 [Byte1]: 60
8657 17:44:11.598207
8658 17:44:11.598679 Set Vref, RX VrefLevel [Byte0]: 61
8659 17:44:11.601731 [Byte1]: 61
8660 17:44:11.605646
8661 17:44:11.606118 Set Vref, RX VrefLevel [Byte0]: 62
8662 17:44:11.608829 [Byte1]: 62
8663 17:44:11.613056
8664 17:44:11.613544 Set Vref, RX VrefLevel [Byte0]: 63
8665 17:44:11.616458 [Byte1]: 63
8666 17:44:11.620556
8667 17:44:11.621200 Set Vref, RX VrefLevel [Byte0]: 64
8668 17:44:11.623989 [Byte1]: 64
8669 17:44:11.628355
8670 17:44:11.628847 Set Vref, RX VrefLevel [Byte0]: 65
8671 17:44:11.631597 [Byte1]: 65
8672 17:44:11.635837
8673 17:44:11.636265 Set Vref, RX VrefLevel [Byte0]: 66
8674 17:44:11.639072 [Byte1]: 66
8675 17:44:11.643109
8676 17:44:11.643193 Set Vref, RX VrefLevel [Byte0]: 67
8677 17:44:11.646681 [Byte1]: 67
8678 17:44:11.650769
8679 17:44:11.650852 Set Vref, RX VrefLevel [Byte0]: 68
8680 17:44:11.653829 [Byte1]: 68
8681 17:44:11.658549
8682 17:44:11.658633 Set Vref, RX VrefLevel [Byte0]: 69
8683 17:44:11.661678 [Byte1]: 69
8684 17:44:11.665942
8685 17:44:11.666026 Set Vref, RX VrefLevel [Byte0]: 70
8686 17:44:11.669487 [Byte1]: 70
8687 17:44:11.673687
8688 17:44:11.673771 Set Vref, RX VrefLevel [Byte0]: 71
8689 17:44:11.676724 [Byte1]: 71
8690 17:44:11.680748
8691 17:44:11.680858 Set Vref, RX VrefLevel [Byte0]: 72
8692 17:44:11.684464 [Byte1]: 72
8693 17:44:11.688447
8694 17:44:11.688531 Set Vref, RX VrefLevel [Byte0]: 73
8695 17:44:11.692054 [Byte1]: 73
8696 17:44:11.696093
8697 17:44:11.696176 Set Vref, RX VrefLevel [Byte0]: 74
8698 17:44:11.699305 [Byte1]: 74
8699 17:44:11.704016
8700 17:44:11.704100 Set Vref, RX VrefLevel [Byte0]: 75
8701 17:44:11.707038 [Byte1]: 75
8702 17:44:11.711268
8703 17:44:11.711352 Set Vref, RX VrefLevel [Byte0]: 76
8704 17:44:11.714796 [Byte1]: 76
8705 17:44:11.718794
8706 17:44:11.718878 Final RX Vref Byte 0 = 55 to rank0
8707 17:44:11.722361 Final RX Vref Byte 1 = 60 to rank0
8708 17:44:11.725473 Final RX Vref Byte 0 = 55 to rank1
8709 17:44:11.728617 Final RX Vref Byte 1 = 60 to rank1==
8710 17:44:11.732280 Dram Type= 6, Freq= 0, CH_1, rank 0
8711 17:44:11.738704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8712 17:44:11.738788 ==
8713 17:44:11.738855 DQS Delay:
8714 17:44:11.738917 DQS0 = 0, DQS1 = 0
8715 17:44:11.742165 DQM Delay:
8716 17:44:11.742248 DQM0 = 133, DQM1 = 130
8717 17:44:11.745583 DQ Delay:
8718 17:44:11.748628 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8719 17:44:11.752085 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8720 17:44:11.755737 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =124
8721 17:44:11.758694 DQ12 =142, DQ13 =134, DQ14 =136, DQ15 =138
8722 17:44:11.758778
8723 17:44:11.758844
8724 17:44:11.758905
8725 17:44:11.762088 [DramC_TX_OE_Calibration] TA2
8726 17:44:11.765229 Original DQ_B0 (3 6) =30, OEN = 27
8727 17:44:11.768789 Original DQ_B1 (3 6) =30, OEN = 27
8728 17:44:11.772190 24, 0x0, End_B0=24 End_B1=24
8729 17:44:11.772275 25, 0x0, End_B0=25 End_B1=25
8730 17:44:11.775290 26, 0x0, End_B0=26 End_B1=26
8731 17:44:11.778428 27, 0x0, End_B0=27 End_B1=27
8732 17:44:11.781866 28, 0x0, End_B0=28 End_B1=28
8733 17:44:11.785141 29, 0x0, End_B0=29 End_B1=29
8734 17:44:11.785226 30, 0x0, End_B0=30 End_B1=30
8735 17:44:11.788762 31, 0x4141, End_B0=30 End_B1=30
8736 17:44:11.791741 Byte0 end_step=30 best_step=27
8737 17:44:11.795236 Byte1 end_step=30 best_step=27
8738 17:44:11.798453 Byte0 TX OE(2T, 0.5T) = (3, 3)
8739 17:44:11.801921 Byte1 TX OE(2T, 0.5T) = (3, 3)
8740 17:44:11.802004
8741 17:44:11.802070
8742 17:44:11.808062 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8743 17:44:11.811442 CH1 RK0: MR19=303, MR18=1826
8744 17:44:11.818078 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8745 17:44:11.818159
8746 17:44:11.821569 ----->DramcWriteLeveling(PI) begin...
8747 17:44:11.821649 ==
8748 17:44:11.824652 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 17:44:11.828358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 17:44:11.828436 ==
8751 17:44:11.831505 Write leveling (Byte 0): 23 => 23
8752 17:44:11.834776 Write leveling (Byte 1): 29 => 29
8753 17:44:11.838306 DramcWriteLeveling(PI) end<-----
8754 17:44:11.838408
8755 17:44:11.838499 ==
8756 17:44:11.841499 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 17:44:11.844649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 17:44:11.844751 ==
8759 17:44:11.848016 [Gating] SW mode calibration
8760 17:44:11.854805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8761 17:44:11.861084 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8762 17:44:11.864464 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 17:44:11.871283 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 17:44:11.874272 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
8765 17:44:11.877668 1 4 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
8766 17:44:11.884315 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 17:44:11.887695 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 17:44:11.891186 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 17:44:11.897620 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 17:44:11.901088 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 17:44:11.904227 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 17:44:11.907820 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8773 17:44:11.914373 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (0 1)
8774 17:44:11.917796 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 17:44:11.921009 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 17:44:11.927746 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 17:44:11.931366 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 17:44:11.934577 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 17:44:11.940760 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8780 17:44:11.944273 1 6 8 | B1->B0 | 3e3e 2323 | 0 0 | (0 0) (0 0)
8781 17:44:11.947567 1 6 12 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
8782 17:44:11.954238 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 17:44:11.957410 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 17:44:11.960664 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 17:44:11.967593 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 17:44:11.970981 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 17:44:11.974209 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8788 17:44:11.980857 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 17:44:11.984371 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8790 17:44:11.987455 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8791 17:44:11.993957 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 17:44:11.997437 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 17:44:12.000876 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 17:44:12.007179 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 17:44:12.010787 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 17:44:12.013709 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 17:44:12.020580 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 17:44:12.023945 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 17:44:12.027189 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 17:44:12.034029 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 17:44:12.037116 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 17:44:12.040486 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 17:44:12.047159 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 17:44:12.050504 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8805 17:44:12.053937 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8806 17:44:12.056866 Total UI for P1: 0, mck2ui 16
8807 17:44:12.060462 best dqsien dly found for B1: ( 1, 9, 8)
8808 17:44:12.063606 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 17:44:12.066884 Total UI for P1: 0, mck2ui 16
8810 17:44:12.070481 best dqsien dly found for B0: ( 1, 9, 10)
8811 17:44:12.073490 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8812 17:44:12.080481 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8813 17:44:12.080564
8814 17:44:12.083462 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8815 17:44:12.086907 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8816 17:44:12.090064 [Gating] SW calibration Done
8817 17:44:12.090146 ==
8818 17:44:12.093363 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 17:44:12.096866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 17:44:12.096976 ==
8821 17:44:12.100233 RX Vref Scan: 0
8822 17:44:12.100347
8823 17:44:12.100450 RX Vref 0 -> 0, step: 1
8824 17:44:12.100528
8825 17:44:12.103179 RX Delay 0 -> 252, step: 8
8826 17:44:12.107096 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8827 17:44:12.110188 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8828 17:44:12.116847 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8829 17:44:12.120042 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8830 17:44:12.123549 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8831 17:44:12.126722 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8832 17:44:12.130316 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8833 17:44:12.136511 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8834 17:44:12.139703 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8835 17:44:12.143078 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8836 17:44:12.146528 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8837 17:44:12.149705 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8838 17:44:12.156454 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8839 17:44:12.159917 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8840 17:44:12.162894 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8841 17:44:12.166177 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8842 17:44:12.166262 ==
8843 17:44:12.169700 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 17:44:12.176439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 17:44:12.176515 ==
8846 17:44:12.176586 DQS Delay:
8847 17:44:12.179368 DQS0 = 0, DQS1 = 0
8848 17:44:12.179469 DQM Delay:
8849 17:44:12.179559 DQM0 = 136, DQM1 = 132
8850 17:44:12.182883 DQ Delay:
8851 17:44:12.186255 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8852 17:44:12.189666 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8853 17:44:12.192830 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8854 17:44:12.196425 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8855 17:44:12.196527
8856 17:44:12.196617
8857 17:44:12.196704 ==
8858 17:44:12.199668 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 17:44:12.206193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 17:44:12.206279 ==
8861 17:44:12.206344
8862 17:44:12.206415
8863 17:44:12.206477 TX Vref Scan disable
8864 17:44:12.209572 == TX Byte 0 ==
8865 17:44:12.212713 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8866 17:44:12.216225 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8867 17:44:12.219420 == TX Byte 1 ==
8868 17:44:12.222809 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8869 17:44:12.226133 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8870 17:44:12.229361 ==
8871 17:44:12.232844 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 17:44:12.236138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 17:44:12.236220 ==
8874 17:44:12.249473
8875 17:44:12.253074 TX Vref early break, caculate TX vref
8876 17:44:12.256209 TX Vref=16, minBit 8, minWin=22, winSum=381
8877 17:44:12.259366 TX Vref=18, minBit 9, minWin=22, winSum=387
8878 17:44:12.262564 TX Vref=20, minBit 8, minWin=23, winSum=394
8879 17:44:12.266072 TX Vref=22, minBit 9, minWin=23, winSum=400
8880 17:44:12.269633 TX Vref=24, minBit 11, minWin=24, winSum=414
8881 17:44:12.275936 TX Vref=26, minBit 9, minWin=24, winSum=414
8882 17:44:12.279478 TX Vref=28, minBit 9, minWin=25, winSum=417
8883 17:44:12.282800 TX Vref=30, minBit 8, minWin=24, winSum=412
8884 17:44:12.285901 TX Vref=32, minBit 8, minWin=24, winSum=404
8885 17:44:12.289471 TX Vref=34, minBit 10, minWin=23, winSum=398
8886 17:44:12.292557 TX Vref=36, minBit 9, minWin=22, winSum=389
8887 17:44:12.299648 [TxChooseVref] Worse bit 9, Min win 25, Win sum 417, Final Vref 28
8888 17:44:12.299731
8889 17:44:12.302819 Final TX Range 0 Vref 28
8890 17:44:12.302902
8891 17:44:12.302967 ==
8892 17:44:12.305935 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 17:44:12.309066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 17:44:12.309149 ==
8895 17:44:12.312629
8896 17:44:12.312711
8897 17:44:12.312775 TX Vref Scan disable
8898 17:44:12.319099 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8899 17:44:12.319181 == TX Byte 0 ==
8900 17:44:12.322379 u2DelayCellOfst[0]=17 cells (5 PI)
8901 17:44:12.325608 u2DelayCellOfst[1]=10 cells (3 PI)
8902 17:44:12.329102 u2DelayCellOfst[2]=0 cells (0 PI)
8903 17:44:12.332494 u2DelayCellOfst[3]=3 cells (1 PI)
8904 17:44:12.335555 u2DelayCellOfst[4]=6 cells (2 PI)
8905 17:44:12.339247 u2DelayCellOfst[5]=17 cells (5 PI)
8906 17:44:12.342405 u2DelayCellOfst[6]=17 cells (5 PI)
8907 17:44:12.345524 u2DelayCellOfst[7]=3 cells (1 PI)
8908 17:44:12.349096 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8909 17:44:12.352647 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8910 17:44:12.355789 == TX Byte 1 ==
8911 17:44:12.358818 u2DelayCellOfst[8]=0 cells (0 PI)
8912 17:44:12.362324 u2DelayCellOfst[9]=3 cells (1 PI)
8913 17:44:12.362409 u2DelayCellOfst[10]=10 cells (3 PI)
8914 17:44:12.365478 u2DelayCellOfst[11]=3 cells (1 PI)
8915 17:44:12.369035 u2DelayCellOfst[12]=13 cells (4 PI)
8916 17:44:12.372408 u2DelayCellOfst[13]=17 cells (5 PI)
8917 17:44:12.375540 u2DelayCellOfst[14]=17 cells (5 PI)
8918 17:44:12.379275 u2DelayCellOfst[15]=17 cells (5 PI)
8919 17:44:12.385510 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8920 17:44:12.389186 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8921 17:44:12.389279 DramC Write-DBI on
8922 17:44:12.389353 ==
8923 17:44:12.392332 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 17:44:12.398969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 17:44:12.399051 ==
8926 17:44:12.399116
8927 17:44:12.399176
8928 17:44:12.399234 TX Vref Scan disable
8929 17:44:12.402837 == TX Byte 0 ==
8930 17:44:12.406413 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8931 17:44:12.409636 == TX Byte 1 ==
8932 17:44:12.412737 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8933 17:44:12.416287 DramC Write-DBI off
8934 17:44:12.416368
8935 17:44:12.416433 [DATLAT]
8936 17:44:12.416493 Freq=1600, CH1 RK1
8937 17:44:12.416551
8938 17:44:12.419298 DATLAT Default: 0xf
8939 17:44:12.419368 0, 0xFFFF, sum = 0
8940 17:44:12.422913 1, 0xFFFF, sum = 0
8941 17:44:12.426023 2, 0xFFFF, sum = 0
8942 17:44:12.426108 3, 0xFFFF, sum = 0
8943 17:44:12.429286 4, 0xFFFF, sum = 0
8944 17:44:12.429360 5, 0xFFFF, sum = 0
8945 17:44:12.432807 6, 0xFFFF, sum = 0
8946 17:44:12.432884 7, 0xFFFF, sum = 0
8947 17:44:12.436086 8, 0xFFFF, sum = 0
8948 17:44:12.436174 9, 0xFFFF, sum = 0
8949 17:44:12.439704 10, 0xFFFF, sum = 0
8950 17:44:12.439791 11, 0xFFFF, sum = 0
8951 17:44:12.442856 12, 0xFFFF, sum = 0
8952 17:44:12.442943 13, 0xFFFF, sum = 0
8953 17:44:12.446169 14, 0x0, sum = 1
8954 17:44:12.446255 15, 0x0, sum = 2
8955 17:44:12.449248 16, 0x0, sum = 3
8956 17:44:12.449400 17, 0x0, sum = 4
8957 17:44:12.452839 best_step = 15
8958 17:44:12.452978
8959 17:44:12.453103 ==
8960 17:44:12.456373 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 17:44:12.459407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 17:44:12.459476 ==
8963 17:44:12.459539 RX Vref Scan: 0
8964 17:44:12.462943
8965 17:44:12.463023 RX Vref 0 -> 0, step: 1
8966 17:44:12.463085
8967 17:44:12.466338 RX Delay 19 -> 252, step: 4
8968 17:44:12.469471 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8969 17:44:12.476188 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8970 17:44:12.479454 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8971 17:44:12.482794 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8972 17:44:12.486151 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8973 17:44:12.489453 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8974 17:44:12.492517 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8975 17:44:12.499251 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8976 17:44:12.502380 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8977 17:44:12.506028 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8978 17:44:12.509201 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8979 17:44:12.512464 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8980 17:44:12.519114 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8981 17:44:12.522339 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8982 17:44:12.525867 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8983 17:44:12.529089 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8984 17:44:12.529172 ==
8985 17:44:12.532163 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 17:44:12.538976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 17:44:12.539060 ==
8988 17:44:12.539126 DQS Delay:
8989 17:44:12.542157 DQS0 = 0, DQS1 = 0
8990 17:44:12.542240 DQM Delay:
8991 17:44:12.545670 DQM0 = 133, DQM1 = 130
8992 17:44:12.545753 DQ Delay:
8993 17:44:12.548901 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8994 17:44:12.552112 DQ4 =134, DQ5 =144, DQ6 =140, DQ7 =130
8995 17:44:12.555673 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8996 17:44:12.558797 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8997 17:44:12.558880
8998 17:44:12.558946
8999 17:44:12.559006
9000 17:44:12.562016 [DramC_TX_OE_Calibration] TA2
9001 17:44:12.565387 Original DQ_B0 (3 6) =30, OEN = 27
9002 17:44:12.568846 Original DQ_B1 (3 6) =30, OEN = 27
9003 17:44:12.571991 24, 0x0, End_B0=24 End_B1=24
9004 17:44:12.575128 25, 0x0, End_B0=25 End_B1=25
9005 17:44:12.575212 26, 0x0, End_B0=26 End_B1=26
9006 17:44:12.578723 27, 0x0, End_B0=27 End_B1=27
9007 17:44:12.582321 28, 0x0, End_B0=28 End_B1=28
9008 17:44:12.585314 29, 0x0, End_B0=29 End_B1=29
9009 17:44:12.585399 30, 0x0, End_B0=30 End_B1=30
9010 17:44:12.588643 31, 0x4545, End_B0=30 End_B1=30
9011 17:44:12.592043 Byte0 end_step=30 best_step=27
9012 17:44:12.595085 Byte1 end_step=30 best_step=27
9013 17:44:12.598790 Byte0 TX OE(2T, 0.5T) = (3, 3)
9014 17:44:12.602011 Byte1 TX OE(2T, 0.5T) = (3, 3)
9015 17:44:12.602094
9016 17:44:12.602159
9017 17:44:12.608513 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9018 17:44:12.611756 CH1 RK1: MR19=303, MR18=1A05
9019 17:44:12.618591 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
9020 17:44:12.621633 [RxdqsGatingPostProcess] freq 1600
9021 17:44:12.625473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9022 17:44:12.628208 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 17:44:12.631608 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 17:44:12.634767 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 17:44:12.638520 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 17:44:12.641726 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 17:44:12.644742 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 17:44:12.648166 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 17:44:12.651823 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 17:44:12.654996 Pre-setting of DQS Precalculation
9031 17:44:12.658248 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9032 17:44:12.664842 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9033 17:44:12.674658 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9034 17:44:12.674774
9035 17:44:12.674874
9036 17:44:12.677862 [Calibration Summary] 3200 Mbps
9037 17:44:12.677945 CH 0, Rank 0
9038 17:44:12.681567 SW Impedance : PASS
9039 17:44:12.681651 DUTY Scan : NO K
9040 17:44:12.684559 ZQ Calibration : PASS
9041 17:44:12.688019 Jitter Meter : NO K
9042 17:44:12.688129 CBT Training : PASS
9043 17:44:12.691222 Write leveling : PASS
9044 17:44:12.694842 RX DQS gating : PASS
9045 17:44:12.694951 RX DQ/DQS(RDDQC) : PASS
9046 17:44:12.697804 TX DQ/DQS : PASS
9047 17:44:12.697887 RX DATLAT : PASS
9048 17:44:12.701525 RX DQ/DQS(Engine): PASS
9049 17:44:12.704574 TX OE : PASS
9050 17:44:12.704658 All Pass.
9051 17:44:12.704723
9052 17:44:12.704784 CH 0, Rank 1
9053 17:44:12.708181 SW Impedance : PASS
9054 17:44:12.711149 DUTY Scan : NO K
9055 17:44:12.711231 ZQ Calibration : PASS
9056 17:44:12.714629 Jitter Meter : NO K
9057 17:44:12.717801 CBT Training : PASS
9058 17:44:12.717885 Write leveling : PASS
9059 17:44:12.721100 RX DQS gating : PASS
9060 17:44:12.724731 RX DQ/DQS(RDDQC) : PASS
9061 17:44:12.724814 TX DQ/DQS : PASS
9062 17:44:12.727845 RX DATLAT : PASS
9063 17:44:12.731112 RX DQ/DQS(Engine): PASS
9064 17:44:12.731194 TX OE : PASS
9065 17:44:12.734432 All Pass.
9066 17:44:12.734516
9067 17:44:12.734581 CH 1, Rank 0
9068 17:44:12.738146 SW Impedance : PASS
9069 17:44:12.738228 DUTY Scan : NO K
9070 17:44:12.741276 ZQ Calibration : PASS
9071 17:44:12.744752 Jitter Meter : NO K
9072 17:44:12.744835 CBT Training : PASS
9073 17:44:12.747952 Write leveling : PASS
9074 17:44:12.748035 RX DQS gating : PASS
9075 17:44:12.751404 RX DQ/DQS(RDDQC) : PASS
9076 17:44:12.754591 TX DQ/DQS : PASS
9077 17:44:12.754675 RX DATLAT : PASS
9078 17:44:12.757613 RX DQ/DQS(Engine): PASS
9079 17:44:12.761324 TX OE : PASS
9080 17:44:12.761408 All Pass.
9081 17:44:12.761474
9082 17:44:12.761534 CH 1, Rank 1
9083 17:44:12.764348 SW Impedance : PASS
9084 17:44:12.767533 DUTY Scan : NO K
9085 17:44:12.767616 ZQ Calibration : PASS
9086 17:44:12.771004 Jitter Meter : NO K
9087 17:44:12.774117 CBT Training : PASS
9088 17:44:12.774201 Write leveling : PASS
9089 17:44:12.777731 RX DQS gating : PASS
9090 17:44:12.780819 RX DQ/DQS(RDDQC) : PASS
9091 17:44:12.780920 TX DQ/DQS : PASS
9092 17:44:12.784168 RX DATLAT : PASS
9093 17:44:12.787759 RX DQ/DQS(Engine): PASS
9094 17:44:12.787842 TX OE : PASS
9095 17:44:12.790655 All Pass.
9096 17:44:12.790737
9097 17:44:12.790802 DramC Write-DBI on
9098 17:44:12.794223 PER_BANK_REFRESH: Hybrid Mode
9099 17:44:12.794307 TX_TRACKING: ON
9100 17:44:12.804065 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9101 17:44:12.810787 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9102 17:44:12.820884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 17:44:12.823987 [FAST_K] Save calibration result to emmc
9104 17:44:12.827578 sync common calibartion params.
9105 17:44:12.827661 sync cbt_mode0:1, 1:1
9106 17:44:12.830777 dram_init: ddr_geometry: 2
9107 17:44:12.833950 dram_init: ddr_geometry: 2
9108 17:44:12.834032 dram_init: ddr_geometry: 2
9109 17:44:12.837597 0:dram_rank_size:100000000
9110 17:44:12.840609 1:dram_rank_size:100000000
9111 17:44:12.847347 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9112 17:44:12.847430 DFS_SHUFFLE_HW_MODE: ON
9113 17:44:12.851043 dramc_set_vcore_voltage set vcore to 725000
9114 17:44:12.854162 Read voltage for 1600, 0
9115 17:44:12.854245 Vio18 = 0
9116 17:44:12.857343 Vcore = 725000
9117 17:44:12.857426 Vdram = 0
9118 17:44:12.857492 Vddq = 0
9119 17:44:12.860589 Vmddr = 0
9120 17:44:12.860672 switch to 3200 Mbps bootup
9121 17:44:12.863919 [DramcRunTimeConfig]
9122 17:44:12.864002 PHYPLL
9123 17:44:12.867265 DPM_CONTROL_AFTERK: ON
9124 17:44:12.867347 PER_BANK_REFRESH: ON
9125 17:44:12.870384 REFRESH_OVERHEAD_REDUCTION: ON
9126 17:44:12.873887 CMD_PICG_NEW_MODE: OFF
9127 17:44:12.873970 XRTWTW_NEW_MODE: ON
9128 17:44:12.877108 XRTRTR_NEW_MODE: ON
9129 17:44:12.877219 TX_TRACKING: ON
9130 17:44:12.880413 RDSEL_TRACKING: OFF
9131 17:44:12.883903 DQS Precalculation for DVFS: ON
9132 17:44:12.883987 RX_TRACKING: OFF
9133 17:44:12.887294 HW_GATING DBG: ON
9134 17:44:12.887404 ZQCS_ENABLE_LP4: ON
9135 17:44:12.890471 RX_PICG_NEW_MODE: ON
9136 17:44:12.890556 TX_PICG_NEW_MODE: ON
9137 17:44:12.893837 ENABLE_RX_DCM_DPHY: ON
9138 17:44:12.897091 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9139 17:44:12.900277 DUMMY_READ_FOR_TRACKING: OFF
9140 17:44:12.900361 !!! SPM_CONTROL_AFTERK: OFF
9141 17:44:12.903637 !!! SPM could not control APHY
9142 17:44:12.906937 IMPEDANCE_TRACKING: ON
9143 17:44:12.907020 TEMP_SENSOR: ON
9144 17:44:12.910428 HW_SAVE_FOR_SR: OFF
9145 17:44:12.913547 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9146 17:44:12.916976 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9147 17:44:12.917061 Read ODT Tracking: ON
9148 17:44:12.920412 Refresh Rate DeBounce: ON
9149 17:44:12.923466 DFS_NO_QUEUE_FLUSH: ON
9150 17:44:12.926782 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9151 17:44:12.926866 ENABLE_DFS_RUNTIME_MRW: OFF
9152 17:44:12.930280 DDR_RESERVE_NEW_MODE: ON
9153 17:44:12.933338 MR_CBT_SWITCH_FREQ: ON
9154 17:44:12.933425 =========================
9155 17:44:12.953718 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9156 17:44:12.957299 dram_init: ddr_geometry: 2
9157 17:44:12.975408 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9158 17:44:12.978593 dram_init: dram init end (result: 0)
9159 17:44:12.985254 DRAM-K: Full calibration passed in 24532 msecs
9160 17:44:12.988601 MRC: failed to locate region type 0.
9161 17:44:12.988685 DRAM rank0 size:0x100000000,
9162 17:44:12.991813 DRAM rank1 size=0x100000000
9163 17:44:13.002070 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9164 17:44:13.008499 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9165 17:44:13.015040 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9166 17:44:13.021898 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9167 17:44:13.025030 DRAM rank0 size:0x100000000,
9168 17:44:13.028472 DRAM rank1 size=0x100000000
9169 17:44:13.028556 CBMEM:
9170 17:44:13.031803 IMD: root @ 0xfffff000 254 entries.
9171 17:44:13.035003 IMD: root @ 0xffffec00 62 entries.
9172 17:44:13.038052 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9173 17:44:13.044732 WARNING: RO_VPD is uninitialized or empty.
9174 17:44:13.048408 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9175 17:44:13.055619 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9176 17:44:13.067975 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9177 17:44:13.079354 BS: romstage times (exec / console): total (unknown) / 24026 ms
9178 17:44:13.079465
9179 17:44:13.079559
9180 17:44:13.089580 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9181 17:44:13.092738 ARM64: Exception handlers installed.
9182 17:44:13.096259 ARM64: Testing exception
9183 17:44:13.099403 ARM64: Done test exception
9184 17:44:13.099548 Enumerating buses...
9185 17:44:13.102907 Show all devs... Before device enumeration.
9186 17:44:13.106352 Root Device: enabled 1
9187 17:44:13.109411 CPU_CLUSTER: 0: enabled 1
9188 17:44:13.109495 CPU: 00: enabled 1
9189 17:44:13.112966 Compare with tree...
9190 17:44:13.113051 Root Device: enabled 1
9191 17:44:13.116014 CPU_CLUSTER: 0: enabled 1
9192 17:44:13.119774 CPU: 00: enabled 1
9193 17:44:13.119859 Root Device scanning...
9194 17:44:13.122867 scan_static_bus for Root Device
9195 17:44:13.126298 CPU_CLUSTER: 0 enabled
9196 17:44:13.129395 scan_static_bus for Root Device done
9197 17:44:13.132606 scan_bus: bus Root Device finished in 8 msecs
9198 17:44:13.132690 done
9199 17:44:13.139376 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9200 17:44:13.142562 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9201 17:44:13.149209 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9202 17:44:13.152830 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9203 17:44:13.155992 Allocating resources...
9204 17:44:13.156077 Reading resources...
9205 17:44:13.162987 Root Device read_resources bus 0 link: 0
9206 17:44:13.163071 DRAM rank0 size:0x100000000,
9207 17:44:13.166158 DRAM rank1 size=0x100000000
9208 17:44:13.169229 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9209 17:44:13.172408 CPU: 00 missing read_resources
9210 17:44:13.175858 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9211 17:44:13.182689 Root Device read_resources bus 0 link: 0 done
9212 17:44:13.182774 Done reading resources.
9213 17:44:13.189398 Show resources in subtree (Root Device)...After reading.
9214 17:44:13.192618 Root Device child on link 0 CPU_CLUSTER: 0
9215 17:44:13.195938 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 17:44:13.205569 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 17:44:13.205657 CPU: 00
9218 17:44:13.208857 Root Device assign_resources, bus 0 link: 0
9219 17:44:13.212393 CPU_CLUSTER: 0 missing set_resources
9220 17:44:13.219028 Root Device assign_resources, bus 0 link: 0 done
9221 17:44:13.219113 Done setting resources.
9222 17:44:13.225701 Show resources in subtree (Root Device)...After assigning values.
9223 17:44:13.228860 Root Device child on link 0 CPU_CLUSTER: 0
9224 17:44:13.232337 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 17:44:13.242062 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 17:44:13.242147 CPU: 00
9227 17:44:13.245532 Done allocating resources.
9228 17:44:13.248732 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9229 17:44:13.251774 Enabling resources...
9230 17:44:13.251858 done.
9231 17:44:13.258485 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9232 17:44:13.258569 Initializing devices...
9233 17:44:13.261858 Root Device init
9234 17:44:13.261942 init hardware done!
9235 17:44:13.265450 0x00000018: ctrlr->caps
9236 17:44:13.268726 52.000 MHz: ctrlr->f_max
9237 17:44:13.268812 0.400 MHz: ctrlr->f_min
9238 17:44:13.271770 0x40ff8080: ctrlr->voltages
9239 17:44:13.271860 sclk: 390625
9240 17:44:13.275336 Bus Width = 1
9241 17:44:13.275420 sclk: 390625
9242 17:44:13.278491 Bus Width = 1
9243 17:44:13.278575 Early init status = 3
9244 17:44:13.285126 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9245 17:44:13.288777 in-header: 03 fc 00 00 01 00 00 00
9246 17:44:13.291828 in-data: 00
9247 17:44:13.295155 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9248 17:44:13.300200 in-header: 03 fd 00 00 00 00 00 00
9249 17:44:13.303424 in-data:
9250 17:44:13.306588 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9251 17:44:13.310942 in-header: 03 fc 00 00 01 00 00 00
9252 17:44:13.314611 in-data: 00
9253 17:44:13.317824 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9254 17:44:13.323250 in-header: 03 fd 00 00 00 00 00 00
9255 17:44:13.326557 in-data:
9256 17:44:13.330584 [SSUSB] Setting up USB HOST controller...
9257 17:44:13.333342 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9258 17:44:13.336768 [SSUSB] phy power-on done.
9259 17:44:13.340293 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9260 17:44:13.346701 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9261 17:44:13.349894 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9262 17:44:13.356465 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9263 17:44:13.363014 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9264 17:44:13.369828 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9265 17:44:13.376156 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9266 17:44:13.382825 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9267 17:44:13.386420 SPM: binary array size = 0x9dc
9268 17:44:13.389617 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9269 17:44:13.396457 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9270 17:44:13.403063 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9271 17:44:13.409601 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9272 17:44:13.412748 configure_display: Starting display init
9273 17:44:13.446594 anx7625_power_on_init: Init interface.
9274 17:44:13.449952 anx7625_disable_pd_protocol: Disabled PD feature.
9275 17:44:13.453499 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9276 17:44:13.481078 anx7625_start_dp_work: Secure OCM version=00
9277 17:44:13.484392 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9278 17:44:13.499599 sp_tx_get_edid_block: EDID Block = 1
9279 17:44:13.602239 Extracted contents:
9280 17:44:13.605400 header: 00 ff ff ff ff ff ff 00
9281 17:44:13.608646 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9282 17:44:13.612106 version: 01 04
9283 17:44:13.615285 basic params: 95 1f 11 78 0a
9284 17:44:13.618770 chroma info: 76 90 94 55 54 90 27 21 50 54
9285 17:44:13.621814 established: 00 00 00
9286 17:44:13.628658 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9287 17:44:13.632173 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9288 17:44:13.638148 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9289 17:44:13.644976 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9290 17:44:13.651709 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9291 17:44:13.654769 extensions: 00
9292 17:44:13.655149 checksum: fb
9293 17:44:13.655487
9294 17:44:13.658312 Manufacturer: IVO Model 57d Serial Number 0
9295 17:44:13.661492 Made week 0 of 2020
9296 17:44:13.661880 EDID version: 1.4
9297 17:44:13.664777 Digital display
9298 17:44:13.667929 6 bits per primary color channel
9299 17:44:13.668427 DisplayPort interface
9300 17:44:13.671435 Maximum image size: 31 cm x 17 cm
9301 17:44:13.674647 Gamma: 220%
9302 17:44:13.675265 Check DPMS levels
9303 17:44:13.678193 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9304 17:44:13.684907 First detailed timing is preferred timing
9305 17:44:13.685476 Established timings supported:
9306 17:44:13.688412 Standard timings supported:
9307 17:44:13.691320 Detailed timings
9308 17:44:13.694941 Hex of detail: 383680a07038204018303c0035ae10000019
9309 17:44:13.701529 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9310 17:44:13.704708 0780 0798 07c8 0820 hborder 0
9311 17:44:13.707766 0438 043b 0447 0458 vborder 0
9312 17:44:13.711165 -hsync -vsync
9313 17:44:13.711589 Did detailed timing
9314 17:44:13.718008 Hex of detail: 000000000000000000000000000000000000
9315 17:44:13.721382 Manufacturer-specified data, tag 0
9316 17:44:13.724403 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9317 17:44:13.727835 ASCII string: InfoVision
9318 17:44:13.731241 Hex of detail: 000000fe00523134304e574635205248200a
9319 17:44:13.734151 ASCII string: R140NWF5 RH
9320 17:44:13.734798 Checksum
9321 17:44:13.737653 Checksum: 0xfb (valid)
9322 17:44:13.740889 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9323 17:44:13.744272 DSI data_rate: 832800000 bps
9324 17:44:13.750713 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9325 17:44:13.754426 anx7625_parse_edid: pixelclock(138800).
9326 17:44:13.757428 hactive(1920), hsync(48), hfp(24), hbp(88)
9327 17:44:13.760603 vactive(1080), vsync(12), vfp(3), vbp(17)
9328 17:44:13.763945 anx7625_dsi_config: config dsi.
9329 17:44:13.770365 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9330 17:44:13.784090 anx7625_dsi_config: success to config DSI
9331 17:44:13.787221 anx7625_dp_start: MIPI phy setup OK.
9332 17:44:13.790365 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9333 17:44:13.793616 mtk_ddp_mode_set invalid vrefresh 60
9334 17:44:13.797200 main_disp_path_setup
9335 17:44:13.797429 ovl_layer_smi_id_en
9336 17:44:13.800250 ovl_layer_smi_id_en
9337 17:44:13.800478 ccorr_config
9338 17:44:13.800662 aal_config
9339 17:44:13.803623 gamma_config
9340 17:44:13.803852 postmask_config
9341 17:44:13.806846 dither_config
9342 17:44:13.810664 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9343 17:44:13.816974 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9344 17:44:13.820639 Root Device init finished in 555 msecs
9345 17:44:13.823635 CPU_CLUSTER: 0 init
9346 17:44:13.830225 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9347 17:44:13.833771 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9348 17:44:13.837322 APU_MBOX 0x190000b0 = 0x10001
9349 17:44:13.840544 APU_MBOX 0x190001b0 = 0x10001
9350 17:44:13.843593 APU_MBOX 0x190005b0 = 0x10001
9351 17:44:13.846866 APU_MBOX 0x190006b0 = 0x10001
9352 17:44:13.850335 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9353 17:44:13.863155 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9354 17:44:13.875470 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9355 17:44:13.882111 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9356 17:44:13.893656 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9357 17:44:13.902800 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9358 17:44:13.906351 CPU_CLUSTER: 0 init finished in 81 msecs
9359 17:44:13.909803 Devices initialized
9360 17:44:13.912775 Show all devs... After init.
9361 17:44:13.913332 Root Device: enabled 1
9362 17:44:13.916445 CPU_CLUSTER: 0: enabled 1
9363 17:44:13.919363 CPU: 00: enabled 1
9364 17:44:13.923074 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9365 17:44:13.926471 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9366 17:44:13.929485 ELOG: NV offset 0x57f000 size 0x1000
9367 17:44:13.936267 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9368 17:44:13.942723 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9369 17:44:13.945984 ELOG: Event(17) added with size 13 at 2023-09-13 17:43:49 UTC
9370 17:44:13.949195 out: cmd=0x121: 03 db 21 01 00 00 00 00
9371 17:44:13.953154 in-header: 03 0e 00 00 2c 00 00 00
9372 17:44:13.966253 in-data: 51 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 17:44:13.972641 ELOG: Event(A1) added with size 10 at 2023-09-13 17:43:49 UTC
9374 17:44:13.979536 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9375 17:44:13.986387 ELOG: Event(A0) added with size 9 at 2023-09-13 17:43:49 UTC
9376 17:44:13.996959 elog_add_boot_reason: Logged dev mode boot
9377 17:44:13.997259 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9378 17:44:13.997505 Finalize devices...
9379 17:44:13.997748 Devices finalized
9380 17:44:14.002666 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9381 17:44:14.005975 Writing coreboot table at 0xffe64000
9382 17:44:14.009069 0. 000000000010a000-0000000000113fff: RAMSTAGE
9383 17:44:14.012519 1. 0000000040000000-00000000400fffff: RAM
9384 17:44:14.019208 2. 0000000040100000-000000004032afff: RAMSTAGE
9385 17:44:14.022368 3. 000000004032b000-00000000545fffff: RAM
9386 17:44:14.025934 4. 0000000054600000-000000005465ffff: BL31
9387 17:44:14.029785 5. 0000000054660000-00000000ffe63fff: RAM
9388 17:44:14.035699 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9389 17:44:14.039142 7. 0000000100000000-000000023fffffff: RAM
9390 17:44:14.039248 Passing 5 GPIOs to payload:
9391 17:44:14.045670 NAME | PORT | POLARITY | VALUE
9392 17:44:14.049049 EC in RW | 0x000000aa | low | undefined
9393 17:44:14.055927 EC interrupt | 0x00000005 | low | undefined
9394 17:44:14.059130 TPM interrupt | 0x000000ab | high | undefined
9395 17:44:14.062635 SD card detect | 0x00000011 | high | undefined
9396 17:44:14.068869 speaker enable | 0x00000093 | high | undefined
9397 17:44:14.072308 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9398 17:44:14.075946 in-header: 03 f9 00 00 02 00 00 00
9399 17:44:14.076029 in-data: 02 00
9400 17:44:14.078872 ADC[4]: Raw value=900295 ID=7
9401 17:44:14.082269 ADC[3]: Raw value=213179 ID=1
9402 17:44:14.082372 RAM Code: 0x71
9403 17:44:14.085480 ADC[6]: Raw value=74502 ID=0
9404 17:44:14.088716 ADC[5]: Raw value=212441 ID=1
9405 17:44:14.088807 SKU Code: 0x1
9406 17:44:14.095542 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd8
9407 17:44:14.099080 coreboot table: 964 bytes.
9408 17:44:14.102285 IMD ROOT 0. 0xfffff000 0x00001000
9409 17:44:14.105321 IMD SMALL 1. 0xffffe000 0x00001000
9410 17:44:14.108713 RO MCACHE 2. 0xffffc000 0x00001104
9411 17:44:14.112400 CONSOLE 3. 0xfff7c000 0x00080000
9412 17:44:14.115478 FMAP 4. 0xfff7b000 0x00000452
9413 17:44:14.119087 TIME STAMP 5. 0xfff7a000 0x00000910
9414 17:44:14.122107 VBOOT WORK 6. 0xfff66000 0x00014000
9415 17:44:14.125332 RAMOOPS 7. 0xffe66000 0x00100000
9416 17:44:14.128821 COREBOOT 8. 0xffe64000 0x00002000
9417 17:44:14.128907 IMD small region:
9418 17:44:14.131896 IMD ROOT 0. 0xffffec00 0x00000400
9419 17:44:14.135290 VPD 1. 0xffffeb80 0x0000006c
9420 17:44:14.138878 MMC STATUS 2. 0xffffeb60 0x00000004
9421 17:44:14.145266 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9422 17:44:14.148784 Probing TPM: done!
9423 17:44:14.152025 Connected to device vid:did:rid of 1ae0:0028:00
9424 17:44:14.162131 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9425 17:44:14.165527 Initialized TPM device CR50 revision 0
9426 17:44:14.168805 Checking cr50 for pending updates
9427 17:44:14.172216 Reading cr50 TPM mode
9428 17:44:14.180616 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9429 17:44:14.187563 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9430 17:44:14.227341 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9431 17:44:14.230851 Checking segment from ROM address 0x40100000
9432 17:44:14.234317 Checking segment from ROM address 0x4010001c
9433 17:44:14.241077 Loading segment from ROM address 0x40100000
9434 17:44:14.241160 code (compression=0)
9435 17:44:14.251012 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9436 17:44:14.257374 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9437 17:44:14.257457 it's not compressed!
9438 17:44:14.264316 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9439 17:44:14.267570 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9440 17:44:14.287925 Loading segment from ROM address 0x4010001c
9441 17:44:14.288012 Entry Point 0x80000000
9442 17:44:14.291165 Loaded segments
9443 17:44:14.294273 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9444 17:44:14.301066 Jumping to boot code at 0x80000000(0xffe64000)
9445 17:44:14.307921 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9446 17:44:14.314173 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9447 17:44:14.322253 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9448 17:44:14.325548 Checking segment from ROM address 0x40100000
9449 17:44:14.329099 Checking segment from ROM address 0x4010001c
9450 17:44:14.335801 Loading segment from ROM address 0x40100000
9451 17:44:14.335903 code (compression=1)
9452 17:44:14.342584 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9453 17:44:14.352463 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9454 17:44:14.352576 using LZMA
9455 17:44:14.360552 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9456 17:44:14.367289 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9457 17:44:14.371165 Loading segment from ROM address 0x4010001c
9458 17:44:14.371243 Entry Point 0x54601000
9459 17:44:14.374292 Loaded segments
9460 17:44:14.377375 NOTICE: MT8192 bl31_setup
9461 17:44:14.384071 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9462 17:44:14.387770 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9463 17:44:14.391126 WARNING: region 0:
9464 17:44:14.394158 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 17:44:14.394242 WARNING: region 1:
9466 17:44:14.400905 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9467 17:44:14.404155 WARNING: region 2:
9468 17:44:14.407643 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9469 17:44:14.410912 WARNING: region 3:
9470 17:44:14.414275 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 17:44:14.417846 WARNING: region 4:
9472 17:44:14.424036 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 17:44:14.424120 WARNING: region 5:
9474 17:44:14.427394 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 17:44:14.431031 WARNING: region 6:
9476 17:44:14.434351 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 17:44:14.437459 WARNING: region 7:
9478 17:44:14.440917 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 17:44:14.447297 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9480 17:44:14.450609 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9481 17:44:14.454563 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9482 17:44:14.460714 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9483 17:44:14.464317 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9484 17:44:14.467396 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9485 17:44:14.474061 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9486 17:44:14.477635 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9487 17:44:14.484385 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9488 17:44:14.487800 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9489 17:44:14.490762 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9490 17:44:14.497731 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9491 17:44:14.501049 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9492 17:44:14.504287 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9493 17:44:14.510935 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9494 17:44:14.514126 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9495 17:44:14.520887 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9496 17:44:14.524241 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9497 17:44:14.527703 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9498 17:44:14.534570 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9499 17:44:14.537554 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9500 17:44:14.541083 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9501 17:44:14.547771 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9502 17:44:14.550840 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9503 17:44:14.557651 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9504 17:44:14.560893 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9505 17:44:14.564207 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9506 17:44:14.570920 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9507 17:44:14.574206 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9508 17:44:14.577622 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9509 17:44:14.584258 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9510 17:44:14.587808 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9511 17:44:14.594505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9512 17:44:14.597679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9513 17:44:14.601051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9514 17:44:14.604355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9515 17:44:14.611402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9516 17:44:14.614441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9517 17:44:14.617603 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9518 17:44:14.621162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9519 17:44:14.624492 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9520 17:44:14.630943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9521 17:44:14.634348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9522 17:44:14.637747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9523 17:44:14.640872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9524 17:44:14.647985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9525 17:44:14.651488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9526 17:44:14.654520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9527 17:44:14.661208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9528 17:44:14.664504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9529 17:44:14.668083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9530 17:44:14.674284 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9531 17:44:14.677948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9532 17:44:14.684666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9533 17:44:14.687722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9534 17:44:14.694415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9535 17:44:14.697695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9536 17:44:14.700872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9537 17:44:14.707800 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9538 17:44:14.710865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9539 17:44:14.717767 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9540 17:44:14.720948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9541 17:44:14.727649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9542 17:44:14.731345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9543 17:44:14.738114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9544 17:44:14.741067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9545 17:44:14.744524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9546 17:44:14.751075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9547 17:44:14.754631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9548 17:44:14.761438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9549 17:44:14.764603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9550 17:44:14.771267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9551 17:44:14.774421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9552 17:44:14.778016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9553 17:44:14.784477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9554 17:44:14.787764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9555 17:44:14.794656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9556 17:44:14.798290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9557 17:44:14.804555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9558 17:44:14.808214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9559 17:44:14.811221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9560 17:44:14.817975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9561 17:44:14.821510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9562 17:44:14.827991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9563 17:44:14.831359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9564 17:44:14.838055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9565 17:44:14.841193 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9566 17:44:14.844798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9567 17:44:14.851576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9568 17:44:14.854682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9569 17:44:14.861530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9570 17:44:14.865031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9571 17:44:14.871771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9572 17:44:14.874880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9573 17:44:14.878506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9574 17:44:14.884816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9575 17:44:14.888361 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9576 17:44:14.891382 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9577 17:44:14.898092 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9578 17:44:14.901893 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9579 17:44:14.904920 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9580 17:44:14.908092 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9581 17:44:14.914540 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9582 17:44:14.918065 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9583 17:44:14.924616 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9584 17:44:14.928015 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9585 17:44:14.931509 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9586 17:44:14.937968 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9587 17:44:14.941397 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9588 17:44:14.948225 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9589 17:44:14.951683 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9590 17:44:14.954581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9591 17:44:14.961558 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9592 17:44:14.964796 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9593 17:44:14.971491 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9594 17:44:14.974799 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9595 17:44:14.977952 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9596 17:44:14.984719 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9597 17:44:14.988067 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9598 17:44:14.991735 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9599 17:44:14.994814 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9600 17:44:15.001694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9601 17:44:15.004779 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9602 17:44:15.007994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9603 17:44:15.014732 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9604 17:44:15.017793 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9605 17:44:15.021146 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9606 17:44:15.027742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9607 17:44:15.031302 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9608 17:44:15.037740 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9609 17:44:15.040905 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9610 17:44:15.044446 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9611 17:44:15.050997 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9612 17:44:15.054193 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9613 17:44:15.060759 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9614 17:44:15.064454 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9615 17:44:15.067615 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9616 17:44:15.074232 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9617 17:44:15.077454 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9618 17:44:15.080982 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9619 17:44:15.088088 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9620 17:44:15.091031 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9621 17:44:15.097571 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9622 17:44:15.100968 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9623 17:44:15.104306 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9624 17:44:15.111119 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9625 17:44:15.114214 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9626 17:44:15.121083 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9627 17:44:15.124286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9628 17:44:15.127867 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9629 17:44:15.134524 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9630 17:44:15.137936 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9631 17:44:15.140822 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9632 17:44:15.147536 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9633 17:44:15.151126 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9634 17:44:15.157677 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9635 17:44:15.161054 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9636 17:44:15.164362 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9637 17:44:15.170853 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9638 17:44:15.174034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9639 17:44:15.180906 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9640 17:44:15.184044 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9641 17:44:15.187636 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9642 17:44:15.194214 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9643 17:44:15.197520 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9644 17:44:15.201093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9645 17:44:15.207203 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9646 17:44:15.210533 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9647 17:44:15.217310 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9648 17:44:15.220801 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9649 17:44:15.224076 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9650 17:44:15.230808 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9651 17:44:15.233950 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9652 17:44:15.240526 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9653 17:44:15.243937 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9654 17:44:15.247023 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9655 17:44:15.253725 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9656 17:44:15.257059 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9657 17:44:15.263715 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9658 17:44:15.267272 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9659 17:44:15.270477 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9660 17:44:15.277468 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9661 17:44:15.280362 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9662 17:44:15.286985 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9663 17:44:15.290598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9664 17:44:15.293746 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9665 17:44:15.300223 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9666 17:44:15.303803 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9667 17:44:15.310076 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9668 17:44:15.313700 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9669 17:44:15.316786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9670 17:44:15.323797 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9671 17:44:15.326748 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9672 17:44:15.333617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9673 17:44:15.336881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9674 17:44:15.340245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9675 17:44:15.346771 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9676 17:44:15.350266 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9677 17:44:15.356871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9678 17:44:15.360764 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9679 17:44:15.363389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9680 17:44:15.370184 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9681 17:44:15.373643 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9682 17:44:15.380131 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9683 17:44:15.383433 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9684 17:44:15.390253 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9685 17:44:15.393346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9686 17:44:15.396870 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9687 17:44:15.403281 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9688 17:44:15.406699 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9689 17:44:15.413101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9690 17:44:15.416730 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9691 17:44:15.423463 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9692 17:44:15.426560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9693 17:44:15.429870 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9694 17:44:15.436678 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9695 17:44:15.439746 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9696 17:44:15.446490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9697 17:44:15.449978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9698 17:44:15.453171 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9699 17:44:15.459874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9700 17:44:15.463213 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9701 17:44:15.470029 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9702 17:44:15.473133 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9703 17:44:15.476313 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9704 17:44:15.483268 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9705 17:44:15.486506 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9706 17:44:15.493068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9707 17:44:15.496256 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9708 17:44:15.499749 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9709 17:44:15.506584 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9710 17:44:15.509565 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9711 17:44:15.512872 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9712 17:44:15.516301 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9713 17:44:15.522771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9714 17:44:15.526137 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9715 17:44:15.529696 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9716 17:44:15.536160 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9717 17:44:15.539459 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9718 17:44:15.542572 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9719 17:44:15.549599 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9720 17:44:15.552596 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9721 17:44:15.559339 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9722 17:44:15.562828 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9723 17:44:15.566257 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9724 17:44:15.572824 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9725 17:44:15.576106 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9726 17:44:15.579624 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9727 17:44:15.586305 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9728 17:44:15.589083 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9729 17:44:15.595830 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9730 17:44:15.599388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9731 17:44:15.602367 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9732 17:44:15.609191 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9733 17:44:15.612684 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9734 17:44:15.615824 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9735 17:44:15.622655 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9736 17:44:15.625941 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9737 17:44:15.628819 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9738 17:44:15.635706 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9739 17:44:15.638749 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9740 17:44:15.645410 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9741 17:44:15.649092 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9742 17:44:15.652053 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9743 17:44:15.658740 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9744 17:44:15.662438 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9745 17:44:15.665463 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9746 17:44:15.671876 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9747 17:44:15.675377 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9748 17:44:15.678685 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9749 17:44:15.685509 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9750 17:44:15.688688 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9751 17:44:15.692107 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9752 17:44:15.695057 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9753 17:44:15.698478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9754 17:44:15.705348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9755 17:44:15.708516 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9756 17:44:15.712132 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9757 17:44:15.715314 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9758 17:44:15.721830 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9759 17:44:15.725099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9760 17:44:15.728601 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9761 17:44:15.735018 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9762 17:44:15.738238 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9763 17:44:15.744946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9764 17:44:15.748236 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9765 17:44:15.751866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9766 17:44:15.758185 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9767 17:44:15.761459 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9768 17:44:15.768319 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9769 17:44:15.771593 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9770 17:44:15.774864 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9771 17:44:15.781227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9772 17:44:15.784940 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9773 17:44:15.791626 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9774 17:44:15.794587 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9775 17:44:15.801659 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9776 17:44:15.804654 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9777 17:44:15.808259 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9778 17:44:15.814602 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9779 17:44:15.818103 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9780 17:44:15.824824 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9781 17:44:15.827983 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9782 17:44:15.831295 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9783 17:44:15.838161 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9784 17:44:15.841389 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9785 17:44:15.848216 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9786 17:44:15.851263 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9787 17:44:15.854480 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9788 17:44:15.861032 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9789 17:44:15.864642 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9790 17:44:15.871344 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9791 17:44:15.874567 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9792 17:44:15.878228 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9793 17:44:15.884407 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9794 17:44:15.887996 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9795 17:44:15.894318 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9796 17:44:15.897996 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9797 17:44:15.900883 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9798 17:44:15.907580 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9799 17:44:15.911020 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9800 17:44:15.917460 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9801 17:44:15.920802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9802 17:44:15.927570 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9803 17:44:15.930656 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9804 17:44:15.933836 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9805 17:44:15.940542 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9806 17:44:15.944073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9807 17:44:15.950505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9808 17:44:15.953841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9809 17:44:15.957371 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9810 17:44:15.963989 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9811 17:44:15.967237 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9812 17:44:15.974037 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9813 17:44:15.977106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9814 17:44:15.983603 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9815 17:44:15.987078 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9816 17:44:15.990134 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9817 17:44:15.996760 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9818 17:44:16.000384 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9819 17:44:16.007206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9820 17:44:16.010518 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9821 17:44:16.013947 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9822 17:44:16.020997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9823 17:44:16.023942 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9824 17:44:16.030405 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9825 17:44:16.034118 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9826 17:44:16.037068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9827 17:44:16.044107 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9828 17:44:16.047209 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9829 17:44:16.053886 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9830 17:44:16.056958 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9831 17:44:16.063568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9832 17:44:16.067116 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9833 17:44:16.070139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9834 17:44:16.077009 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9835 17:44:16.080791 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9836 17:44:16.086996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9837 17:44:16.090388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9838 17:44:16.097129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9839 17:44:16.100826 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9840 17:44:16.103935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9841 17:44:16.110315 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9842 17:44:16.113745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9843 17:44:16.120077 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9844 17:44:16.123809 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9845 17:44:16.130444 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9846 17:44:16.134128 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9847 17:44:16.136666 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9848 17:44:16.143718 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9849 17:44:16.147131 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9850 17:44:16.153750 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9851 17:44:16.157001 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9852 17:44:16.163478 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9853 17:44:16.166878 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9854 17:44:16.170562 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9855 17:44:16.176750 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9856 17:44:16.180212 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9857 17:44:16.187021 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9858 17:44:16.190424 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9859 17:44:16.196768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9860 17:44:16.200221 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9861 17:44:16.204003 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9862 17:44:16.210598 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9863 17:44:16.213394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9864 17:44:16.220333 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9865 17:44:16.223732 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9866 17:44:16.226515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9867 17:44:16.233625 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9868 17:44:16.236900 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9869 17:44:16.243302 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9870 17:44:16.246899 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9871 17:44:16.253637 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9872 17:44:16.256657 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9873 17:44:16.263719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9874 17:44:16.266717 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9875 17:44:16.269659 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9876 17:44:16.276712 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9877 17:44:16.280077 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9878 17:44:16.286701 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9879 17:44:16.289845 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9880 17:44:16.296450 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9881 17:44:16.299760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9882 17:44:16.303401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9883 17:44:16.310053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9884 17:44:16.312954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9885 17:44:16.319754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9886 17:44:16.323063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9887 17:44:16.329617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9888 17:44:16.333399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9889 17:44:16.339712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9890 17:44:16.342671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9891 17:44:16.349393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9892 17:44:16.353108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9893 17:44:16.359470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9894 17:44:16.363030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9895 17:44:16.369325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9896 17:44:16.372958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9897 17:44:16.379184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9898 17:44:16.382975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9899 17:44:16.386189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9900 17:44:16.392908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9901 17:44:16.395901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9902 17:44:16.402847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9903 17:44:16.406027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9904 17:44:16.413056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9905 17:44:16.419424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9906 17:44:16.422398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9907 17:44:16.428974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9908 17:44:16.432602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9909 17:44:16.439287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9910 17:44:16.442896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9911 17:44:16.449318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9912 17:44:16.452403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9913 17:44:16.455967 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9914 17:44:16.459318 INFO: [APUAPC] vio 0
9915 17:44:16.461999 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9916 17:44:16.469139 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9917 17:44:16.472479 INFO: [APUAPC] D0_APC_0: 0x400510
9918 17:44:16.475935 INFO: [APUAPC] D0_APC_1: 0x0
9919 17:44:16.479075 INFO: [APUAPC] D0_APC_2: 0x1540
9920 17:44:16.479545 INFO: [APUAPC] D0_APC_3: 0x0
9921 17:44:16.482492 INFO: [APUAPC] D1_APC_0: 0xffffffff
9922 17:44:16.485813 INFO: [APUAPC] D1_APC_1: 0xffffffff
9923 17:44:16.489283 INFO: [APUAPC] D1_APC_2: 0x3fffff
9924 17:44:16.492538 INFO: [APUAPC] D1_APC_3: 0x0
9925 17:44:16.495682 INFO: [APUAPC] D2_APC_0: 0xffffffff
9926 17:44:16.499194 INFO: [APUAPC] D2_APC_1: 0xffffffff
9927 17:44:16.502320 INFO: [APUAPC] D2_APC_2: 0x3fffff
9928 17:44:16.505552 INFO: [APUAPC] D2_APC_3: 0x0
9929 17:44:16.509212 INFO: [APUAPC] D3_APC_0: 0xffffffff
9930 17:44:16.512195 INFO: [APUAPC] D3_APC_1: 0xffffffff
9931 17:44:16.515573 INFO: [APUAPC] D3_APC_2: 0x3fffff
9932 17:44:16.519177 INFO: [APUAPC] D3_APC_3: 0x0
9933 17:44:16.522275 INFO: [APUAPC] D4_APC_0: 0xffffffff
9934 17:44:16.525717 INFO: [APUAPC] D4_APC_1: 0xffffffff
9935 17:44:16.528957 INFO: [APUAPC] D4_APC_2: 0x3fffff
9936 17:44:16.532182 INFO: [APUAPC] D4_APC_3: 0x0
9937 17:44:16.535839 INFO: [APUAPC] D5_APC_0: 0xffffffff
9938 17:44:16.538416 INFO: [APUAPC] D5_APC_1: 0xffffffff
9939 17:44:16.541819 INFO: [APUAPC] D5_APC_2: 0x3fffff
9940 17:44:16.544982 INFO: [APUAPC] D5_APC_3: 0x0
9941 17:44:16.548453 INFO: [APUAPC] D6_APC_0: 0xffffffff
9942 17:44:16.551537 INFO: [APUAPC] D6_APC_1: 0xffffffff
9943 17:44:16.555249 INFO: [APUAPC] D6_APC_2: 0x3fffff
9944 17:44:16.558259 INFO: [APUAPC] D6_APC_3: 0x0
9945 17:44:16.561723 INFO: [APUAPC] D7_APC_0: 0xffffffff
9946 17:44:16.565128 INFO: [APUAPC] D7_APC_1: 0xffffffff
9947 17:44:16.568467 INFO: [APUAPC] D7_APC_2: 0x3fffff
9948 17:44:16.571467 INFO: [APUAPC] D7_APC_3: 0x0
9949 17:44:16.574943 INFO: [APUAPC] D8_APC_0: 0xffffffff
9950 17:44:16.578269 INFO: [APUAPC] D8_APC_1: 0xffffffff
9951 17:44:16.581514 INFO: [APUAPC] D8_APC_2: 0x3fffff
9952 17:44:16.584725 INFO: [APUAPC] D8_APC_3: 0x0
9953 17:44:16.587937 INFO: [APUAPC] D9_APC_0: 0xffffffff
9954 17:44:16.591304 INFO: [APUAPC] D9_APC_1: 0xffffffff
9955 17:44:16.594875 INFO: [APUAPC] D9_APC_2: 0x3fffff
9956 17:44:16.598008 INFO: [APUAPC] D9_APC_3: 0x0
9957 17:44:16.601244 INFO: [APUAPC] D10_APC_0: 0xffffffff
9958 17:44:16.604491 INFO: [APUAPC] D10_APC_1: 0xffffffff
9959 17:44:16.608112 INFO: [APUAPC] D10_APC_2: 0x3fffff
9960 17:44:16.611339 INFO: [APUAPC] D10_APC_3: 0x0
9961 17:44:16.614561 INFO: [APUAPC] D11_APC_0: 0xffffffff
9962 17:44:16.617919 INFO: [APUAPC] D11_APC_1: 0xffffffff
9963 17:44:16.621419 INFO: [APUAPC] D11_APC_2: 0x3fffff
9964 17:44:16.624841 INFO: [APUAPC] D11_APC_3: 0x0
9965 17:44:16.628134 INFO: [APUAPC] D12_APC_0: 0xffffffff
9966 17:44:16.631277 INFO: [APUAPC] D12_APC_1: 0xffffffff
9967 17:44:16.634291 INFO: [APUAPC] D12_APC_2: 0x3fffff
9968 17:44:16.637889 INFO: [APUAPC] D12_APC_3: 0x0
9969 17:44:16.641248 INFO: [APUAPC] D13_APC_0: 0xffffffff
9970 17:44:16.644223 INFO: [APUAPC] D13_APC_1: 0xffffffff
9971 17:44:16.647994 INFO: [APUAPC] D13_APC_2: 0x3fffff
9972 17:44:16.651300 INFO: [APUAPC] D13_APC_3: 0x0
9973 17:44:16.654557 INFO: [APUAPC] D14_APC_0: 0xffffffff
9974 17:44:16.657574 INFO: [APUAPC] D14_APC_1: 0xffffffff
9975 17:44:16.661174 INFO: [APUAPC] D14_APC_2: 0x3fffff
9976 17:44:16.664363 INFO: [APUAPC] D14_APC_3: 0x0
9977 17:44:16.667697 INFO: [APUAPC] D15_APC_0: 0xffffffff
9978 17:44:16.671168 INFO: [APUAPC] D15_APC_1: 0xffffffff
9979 17:44:16.674073 INFO: [APUAPC] D15_APC_2: 0x3fffff
9980 17:44:16.677717 INFO: [APUAPC] D15_APC_3: 0x0
9981 17:44:16.680923 INFO: [APUAPC] APC_CON: 0x4
9982 17:44:16.684339 INFO: [NOCDAPC] D0_APC_0: 0x0
9983 17:44:16.684424 INFO: [NOCDAPC] D0_APC_1: 0x0
9984 17:44:16.687537 INFO: [NOCDAPC] D1_APC_0: 0x0
9985 17:44:16.691044 INFO: [NOCDAPC] D1_APC_1: 0xfff
9986 17:44:16.694052 INFO: [NOCDAPC] D2_APC_0: 0x0
9987 17:44:16.697456 INFO: [NOCDAPC] D2_APC_1: 0xfff
9988 17:44:16.701051 INFO: [NOCDAPC] D3_APC_0: 0x0
9989 17:44:16.704324 INFO: [NOCDAPC] D3_APC_1: 0xfff
9990 17:44:16.707419 INFO: [NOCDAPC] D4_APC_0: 0x0
9991 17:44:16.710789 INFO: [NOCDAPC] D4_APC_1: 0xfff
9992 17:44:16.714444 INFO: [NOCDAPC] D5_APC_0: 0x0
9993 17:44:16.717365 INFO: [NOCDAPC] D5_APC_1: 0xfff
9994 17:44:16.717449 INFO: [NOCDAPC] D6_APC_0: 0x0
9995 17:44:16.721107 INFO: [NOCDAPC] D6_APC_1: 0xfff
9996 17:44:16.724081 INFO: [NOCDAPC] D7_APC_0: 0x0
9997 17:44:16.727443 INFO: [NOCDAPC] D7_APC_1: 0xfff
9998 17:44:16.730673 INFO: [NOCDAPC] D8_APC_0: 0x0
9999 17:44:16.733828 INFO: [NOCDAPC] D8_APC_1: 0xfff
10000 17:44:16.737421 INFO: [NOCDAPC] D9_APC_0: 0x0
10001 17:44:16.740878 INFO: [NOCDAPC] D9_APC_1: 0xfff
10002 17:44:16.744018 INFO: [NOCDAPC] D10_APC_0: 0x0
10003 17:44:16.747264 INFO: [NOCDAPC] D10_APC_1: 0xfff
10004 17:44:16.750431 INFO: [NOCDAPC] D11_APC_0: 0x0
10005 17:44:16.754222 INFO: [NOCDAPC] D11_APC_1: 0xfff
10006 17:44:16.754305 INFO: [NOCDAPC] D12_APC_0: 0x0
10007 17:44:16.757287 INFO: [NOCDAPC] D12_APC_1: 0xfff
10008 17:44:16.760602 INFO: [NOCDAPC] D13_APC_0: 0x0
10009 17:44:16.764043 INFO: [NOCDAPC] D13_APC_1: 0xfff
10010 17:44:16.767506 INFO: [NOCDAPC] D14_APC_0: 0x0
10011 17:44:16.770580 INFO: [NOCDAPC] D14_APC_1: 0xfff
10012 17:44:16.773888 INFO: [NOCDAPC] D15_APC_0: 0x0
10013 17:44:16.777245 INFO: [NOCDAPC] D15_APC_1: 0xfff
10014 17:44:16.780614 INFO: [NOCDAPC] APC_CON: 0x4
10015 17:44:16.783806 INFO: [APUAPC] set_apusys_apc done
10016 17:44:16.786959 INFO: [DEVAPC] devapc_init done
10017 17:44:16.790753 INFO: GICv3 without legacy support detected.
10018 17:44:16.793530 INFO: ARM GICv3 driver initialized in EL3
10019 17:44:16.796883 INFO: Maximum SPI INTID supported: 639
10020 17:44:16.803791 INFO: BL31: Initializing runtime services
10021 17:44:16.806926 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10022 17:44:16.810275 INFO: SPM: enable CPC mode
10023 17:44:16.817262 INFO: mcdi ready for mcusys-off-idle and system suspend
10024 17:44:16.820411 INFO: BL31: Preparing for EL3 exit to normal world
10025 17:44:16.823773 INFO: Entry point address = 0x80000000
10026 17:44:16.826939 INFO: SPSR = 0x8
10027 17:44:16.832415
10028 17:44:16.832499
10029 17:44:16.832566
10030 17:44:16.833251 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10031 17:44:16.833353 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10032 17:44:16.833435 Setting prompt string to ['asurada:']
10033 17:44:16.833514 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10034 17:44:16.835728 Starting depthcharge on Spherion...
10035 17:44:16.835812
10036 17:44:16.835878 Wipe memory regions:
10037 17:44:16.835940
10038 17:44:16.838932 [0x00000040000000, 0x00000054600000)
10039 17:44:16.961562
10040 17:44:16.961849 [0x00000054660000, 0x00000080000000)
10041 17:44:17.221875
10042 17:44:17.222411 [0x000000821a7280, 0x000000ffe64000)
10043 17:44:17.966369
10044 17:44:17.966903 [0x00000100000000, 0x00000240000000)
10045 17:44:19.855644
10046 17:44:19.858918 Initializing XHCI USB controller at 0x11200000.
10047 17:44:20.897015
10048 17:44:20.899869 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10049 17:44:20.900341
10050 17:44:20.900705
10051 17:44:20.901079
10052 17:44:20.901862 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 17:44:21.003151 asurada: tftpboot 192.168.201.1 11518305/tftp-deploy-_ikyzgwh/kernel/image.itb 11518305/tftp-deploy-_ikyzgwh/kernel/cmdline
10055 17:44:21.003770 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 17:44:21.004219 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10057 17:44:21.009260 tftpboot 192.168.201.1 11518305/tftp-deploy-_ikyzgwh/kernel/image.ittp-deploy-_ikyzgwh/kernel/cmdline
10058 17:44:21.009741
10059 17:44:21.010115 Waiting for link
10060 17:44:21.169684
10061 17:44:21.170249 R8152: Initializing
10062 17:44:21.170622
10063 17:44:21.172765 Version 9 (ocp_data = 6010)
10064 17:44:21.173375
10065 17:44:21.176320 R8152: Done initializing
10066 17:44:21.176881
10067 17:44:21.177395 Adding net device
10068 17:44:23.118018
10069 17:44:23.118657 done.
10070 17:44:23.119169
10071 17:44:23.119627 MAC: 00:e0:4c:72:2d:d6
10072 17:44:23.120075
10073 17:44:23.121285 Sending DHCP discover... done.
10074 17:44:23.121771
10075 17:44:23.124572 Waiting for reply... done.
10076 17:44:23.125123
10077 17:44:23.128074 Sending DHCP request... done.
10078 17:44:23.128544
10079 17:44:23.131694 Waiting for reply... done.
10080 17:44:23.132258
10081 17:44:23.132667 My ip is 192.168.201.21
10082 17:44:23.133066
10083 17:44:23.135250 The DHCP server ip is 192.168.201.1
10084 17:44:23.135813
10085 17:44:23.141338 TFTP server IP predefined by user: 192.168.201.1
10086 17:44:23.141813
10087 17:44:23.148108 Bootfile predefined by user: 11518305/tftp-deploy-_ikyzgwh/kernel/image.itb
10088 17:44:23.148577
10089 17:44:23.151378 Sending tftp read request... done.
10090 17:44:23.151850
10091 17:44:23.155855 Waiting for the transfer...
10092 17:44:23.156419
10093 17:44:23.527876 00000000 ################################################################
10094 17:44:23.528082
10095 17:44:23.907681 00080000 ################################################################
10096 17:44:23.908288
10097 17:44:24.284545 00100000 ################################################################
10098 17:44:24.285088
10099 17:44:24.656736 00180000 ################################################################
10100 17:44:24.657303
10101 17:44:25.031645 00200000 ################################################################
10102 17:44:25.032171
10103 17:44:25.409934 00280000 ################################################################
10104 17:44:25.410482
10105 17:44:25.770653 00300000 ################################################################
10106 17:44:25.770830
10107 17:44:26.070113 00380000 ################################################################
10108 17:44:26.070249
10109 17:44:26.366288 00400000 ################################################################
10110 17:44:26.366417
10111 17:44:26.658538 00480000 ################################################################
10112 17:44:26.658681
10113 17:44:26.948994 00500000 ################################################################
10114 17:44:26.949142
10115 17:44:27.201464 00580000 ################################################################
10116 17:44:27.201593
10117 17:44:27.482486 00600000 ################################################################
10118 17:44:27.482620
10119 17:44:27.766023 00680000 ################################################################
10120 17:44:27.766160
10121 17:44:28.061324 00700000 ################################################################
10122 17:44:28.061466
10123 17:44:28.341425 00780000 ################################################################
10124 17:44:28.341565
10125 17:44:28.634610 00800000 ################################################################
10126 17:44:28.634753
10127 17:44:28.913085 00880000 ################################################################
10128 17:44:28.913233
10129 17:44:29.184896 00900000 ################################################################
10130 17:44:29.185065
10131 17:44:29.477945 00980000 ################################################################
10132 17:44:29.478087
10133 17:44:29.772700 00a00000 ################################################################
10134 17:44:29.772843
10135 17:44:30.068792 00a80000 ################################################################
10136 17:44:30.068939
10137 17:44:30.347802 00b00000 ################################################################
10138 17:44:30.347945
10139 17:44:30.622683 00b80000 ################################################################
10140 17:44:30.622825
10141 17:44:30.916390 00c00000 ################################################################
10142 17:44:30.916527
10143 17:44:31.210100 00c80000 ################################################################
10144 17:44:31.210242
10145 17:44:31.498166 00d00000 ################################################################
10146 17:44:31.498327
10147 17:44:31.781622 00d80000 ################################################################
10148 17:44:31.781769
10149 17:44:32.057118 00e00000 ################################################################
10150 17:44:32.057261
10151 17:44:32.316195 00e80000 ################################################################
10152 17:44:32.316331
10153 17:44:32.575848 00f00000 ################################################################
10154 17:44:32.575985
10155 17:44:32.834311 00f80000 ################################################################
10156 17:44:32.834454
10157 17:44:33.083985 01000000 ################################################################
10158 17:44:33.084126
10159 17:44:33.354458 01080000 ################################################################
10160 17:44:33.354594
10161 17:44:33.613788 01100000 ################################################################
10162 17:44:33.613960
10163 17:44:33.868031 01180000 ################################################################
10164 17:44:33.868176
10165 17:44:34.133784 01200000 ################################################################
10166 17:44:34.133919
10167 17:44:34.412890 01280000 ################################################################
10168 17:44:34.413058
10169 17:44:34.678629 01300000 ################################################################
10170 17:44:34.678763
10171 17:44:34.957083 01380000 ################################################################
10172 17:44:34.957219
10173 17:44:35.249970 01400000 ################################################################
10174 17:44:35.250106
10175 17:44:35.545880 01480000 ################################################################
10176 17:44:35.546015
10177 17:44:35.841184 01500000 ################################################################
10178 17:44:35.841322
10179 17:44:36.137174 01580000 ################################################################
10180 17:44:36.137310
10181 17:44:36.431560 01600000 ################################################################
10182 17:44:36.431698
10183 17:44:36.725667 01680000 ################################################################
10184 17:44:36.725810
10185 17:44:37.018266 01700000 ################################################################
10186 17:44:37.018407
10187 17:44:37.297510 01780000 ################################################################
10188 17:44:37.297645
10189 17:44:37.570988 01800000 ################################################################
10190 17:44:37.571120
10191 17:44:37.866603 01880000 ################################################################
10192 17:44:37.866747
10193 17:44:38.162547 01900000 ################################################################
10194 17:44:38.162682
10195 17:44:38.456459 01980000 ################################################################
10196 17:44:38.456599
10197 17:44:38.753088 01a00000 ################################################################
10198 17:44:38.753224
10199 17:44:39.049909 01a80000 ################################################################
10200 17:44:39.050043
10201 17:44:39.345293 01b00000 ################################################################
10202 17:44:39.345425
10203 17:44:39.642844 01b80000 ################################################################
10204 17:44:39.642977
10205 17:44:39.939961 01c00000 ################################################################
10206 17:44:39.940105
10207 17:44:40.235471 01c80000 ################################################################
10208 17:44:40.235611
10209 17:44:40.531109 01d00000 ################################################################
10210 17:44:40.531250
10211 17:44:40.897038 01d80000 ################################################################
10212 17:44:40.897607
10213 17:44:41.290025 01e00000 ################################################################
10214 17:44:41.290589
10215 17:44:41.681837 01e80000 ################################################################
10216 17:44:41.682395
10217 17:44:42.085921 01f00000 ################################################################
10218 17:44:42.086567
10219 17:44:42.490452 01f80000 ################################################################
10220 17:44:42.491031
10221 17:44:42.881805 02000000 ################################################################
10222 17:44:42.882368
10223 17:44:43.264735 02080000 ################################################################
10224 17:44:43.265325
10225 17:44:43.634046 02100000 ################################################################
10226 17:44:43.634586
10227 17:44:44.018314 02180000 ################################################################
10228 17:44:44.018857
10229 17:44:44.340476 02200000 ################################################################
10230 17:44:44.340640
10231 17:44:44.619425 02280000 ################################################################
10232 17:44:44.619576
10233 17:44:44.886998 02300000 ################################################################
10234 17:44:44.887176
10235 17:44:45.136902 02380000 ################################################################
10236 17:44:45.137090
10237 17:44:45.395466 02400000 ################################################################
10238 17:44:45.395648
10239 17:44:45.648017 02480000 ################################################################
10240 17:44:45.648162
10241 17:44:45.902125 02500000 ################################################################
10242 17:44:45.902273
10243 17:44:46.170532 02580000 ################################################################
10244 17:44:46.170681
10245 17:44:46.430208 02600000 ################################################################
10246 17:44:46.430384
10247 17:44:46.695261 02680000 ################################################################
10248 17:44:46.695437
10249 17:44:46.982963 02700000 ################################################################
10250 17:44:46.983139
10251 17:44:47.275758 02780000 ################################################################
10252 17:44:47.275936
10253 17:44:47.551878 02800000 ################################################################
10254 17:44:47.552052
10255 17:44:47.804562 02880000 ################################################################
10256 17:44:47.804713
10257 17:44:48.078716 02900000 ################################################################
10258 17:44:48.078865
10259 17:44:48.329425 02980000 ################################################################
10260 17:44:48.329576
10261 17:44:48.585153 02a00000 ################################################################
10262 17:44:48.585305
10263 17:44:48.841360 02a80000 ################################################################
10264 17:44:48.841512
10265 17:44:49.097551 02b00000 ################################################################
10266 17:44:49.097731
10267 17:44:49.370042 02b80000 ################################################################
10268 17:44:49.370194
10269 17:44:49.624639 02c00000 ################################################################
10270 17:44:49.624823
10271 17:44:49.883343 02c80000 ################################################################
10272 17:44:49.883510
10273 17:44:50.139250 02d00000 ################################################################
10274 17:44:50.139398
10275 17:44:50.390498 02d80000 ################################################################
10276 17:44:50.390649
10277 17:44:50.642109 02e00000 ################################################################
10278 17:44:50.642258
10279 17:44:50.906432 02e80000 ################################################################
10280 17:44:50.906583
10281 17:44:51.158861 02f00000 ################################################################
10282 17:44:51.159031
10283 17:44:51.438071 02f80000 ################################################################
10284 17:44:51.438221
10285 17:44:51.735746 03000000 ################################################################
10286 17:44:51.735895
10287 17:44:52.031137 03080000 ################################################################
10288 17:44:52.031284
10289 17:44:52.327689 03100000 ################################################################
10290 17:44:52.327840
10291 17:44:52.606465 03180000 ################################################################
10292 17:44:52.606618
10293 17:44:52.865047 03200000 ################################################################
10294 17:44:52.865202
10295 17:44:53.155799 03280000 ################################################################
10296 17:44:53.155949
10297 17:44:53.422212 03300000 ################################################################
10298 17:44:53.422373
10299 17:44:53.703231 03380000 ################################################################
10300 17:44:53.703415
10301 17:44:53.994790 03400000 ################################################################
10302 17:44:53.994944
10303 17:44:54.281984 03480000 ################################################################
10304 17:44:54.282134
10305 17:44:54.578883 03500000 ################################################################
10306 17:44:54.579030
10307 17:44:54.874061 03580000 ################################################################
10308 17:44:54.874214
10309 17:44:55.133097 03600000 ################################################################
10310 17:44:55.133251
10311 17:44:55.383297 03680000 ################################################################
10312 17:44:55.383453
10313 17:44:55.658709 03700000 ################################################################
10314 17:44:55.658867
10315 17:44:55.892400 03780000 #################################################### done.
10316 17:44:55.892564
10317 17:44:55.895567 The bootfile was 58615462 bytes long.
10318 17:44:55.895658
10319 17:44:55.898995 Sending tftp read request... done.
10320 17:44:55.899086
10321 17:44:55.902149 Waiting for the transfer...
10322 17:44:55.902274
10323 17:44:55.902345 00000000 # done.
10324 17:44:55.902411
10325 17:44:55.912239 Command line loaded dynamically from TFTP file: 11518305/tftp-deploy-_ikyzgwh/kernel/cmdline
10326 17:44:55.912368
10327 17:44:55.925548 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10328 17:44:55.925701
10329 17:44:55.925769 Loading FIT.
10330 17:44:55.925829
10331 17:44:55.928561 Image ramdisk-1 has 47526898 bytes.
10332 17:44:55.928671
10333 17:44:55.932007 Image fdt-1 has 47278 bytes.
10334 17:44:55.932118
10335 17:44:55.935740 Image kernel-1 has 11039249 bytes.
10336 17:44:55.935824
10337 17:44:55.942018 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10338 17:44:55.942111
10339 17:44:55.961996 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10340 17:44:55.962141
10341 17:44:55.965855 Choosing best match conf-1 for compat google,spherion-rev2.
10342 17:44:55.970748
10343 17:44:55.975155 Connected to device vid:did:rid of 1ae0:0028:00
10344 17:44:55.983468
10345 17:44:55.986559 tpm_get_response: command 0x17b, return code 0x0
10346 17:44:55.986649
10347 17:44:55.989758 ec_init: CrosEC protocol v3 supported (256, 248)
10348 17:44:55.994652
10349 17:44:55.997151 tpm_cleanup: add release locality here.
10350 17:44:55.997240
10351 17:44:55.997307 Shutting down all USB controllers.
10352 17:44:56.000499
10353 17:44:56.000588 Removing current net device
10354 17:44:56.000656
10355 17:44:56.007263 Exiting depthcharge with code 4 at timestamp: 68505005
10356 17:44:56.007366
10357 17:44:56.010403 LZMA decompressing kernel-1 to 0x821a6718
10358 17:44:56.010490
10359 17:44:56.013784 LZMA decompressing kernel-1 to 0x40000000
10360 17:44:57.403530
10361 17:44:57.403692 jumping to kernel
10362 17:44:57.404126 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10363 17:44:57.404231 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10364 17:44:57.404310 Setting prompt string to ['Linux version [0-9]']
10365 17:44:57.404379 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10366 17:44:57.404447 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10367 17:44:57.485380
10368 17:44:57.489015 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10369 17:44:57.492485 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10370 17:44:57.492595 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10371 17:44:57.492670 Setting prompt string to []
10372 17:44:57.492750 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10373 17:44:57.492826 Using line separator: #'\n'#
10374 17:44:57.492887 No login prompt set.
10375 17:44:57.493007 Parsing kernel messages
10376 17:44:57.493066 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10377 17:44:57.493164 [login-action] Waiting for messages, (timeout 00:03:45)
10378 17:44:57.512044 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j44859-arm64-gcc-10-defconfig-arm64-chromebook-gptb4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023
10379 17:44:57.515491 [ 0.000000] random: crng init done
10380 17:44:57.522106 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10381 17:44:57.522214 [ 0.000000] efi: UEFI not found.
10382 17:44:57.531960 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10383 17:44:57.538556 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10384 17:44:57.548433 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10385 17:44:57.558685 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10386 17:44:57.565392 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10387 17:44:57.568456 [ 0.000000] printk: bootconsole [mtk8250] enabled
10388 17:44:57.577285 [ 0.000000] NUMA: No NUMA configuration found
10389 17:44:57.583661 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10390 17:44:57.590316 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10391 17:44:57.590430 [ 0.000000] Zone ranges:
10392 17:44:57.596833 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10393 17:44:57.600247 [ 0.000000] DMA32 empty
10394 17:44:57.607015 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10395 17:44:57.610286 [ 0.000000] Movable zone start for each node
10396 17:44:57.613548 [ 0.000000] Early memory node ranges
10397 17:44:57.620248 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10398 17:44:57.626549 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10399 17:44:57.633539 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10400 17:44:57.640026 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10401 17:44:57.646918 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10402 17:44:57.652912 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10403 17:44:57.709688 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10404 17:44:57.716407 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10405 17:44:57.722851 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10406 17:44:57.726334 [ 0.000000] psci: probing for conduit method from DT.
10407 17:44:57.733107 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10408 17:44:57.736130 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10409 17:44:57.742784 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10410 17:44:57.746179 [ 0.000000] psci: SMC Calling Convention v1.2
10411 17:44:57.752675 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10412 17:44:57.756085 [ 0.000000] Detected VIPT I-cache on CPU0
10413 17:44:57.762740 [ 0.000000] CPU features: detected: GIC system register CPU interface
10414 17:44:57.769201 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10415 17:44:57.775864 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10416 17:44:57.782627 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10417 17:44:57.788879 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10418 17:44:57.799115 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10419 17:44:57.802383 [ 0.000000] alternatives: applying boot alternatives
10420 17:44:57.808922 [ 0.000000] Fallback order for Node 0: 0
10421 17:44:57.815531 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10422 17:44:57.818641 [ 0.000000] Policy zone: Normal
10423 17:44:57.832171 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10424 17:44:57.842203 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10425 17:44:57.854266 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10426 17:44:57.864453 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10427 17:44:57.870724 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10428 17:44:57.873882 <6>[ 0.000000] software IO TLB: area num 8.
10429 17:44:57.931160 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10430 17:44:58.079883 <6>[ 0.000000] Memory: 7923076K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 429692K reserved, 32768K cma-reserved)
10431 17:44:58.086716 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10432 17:44:58.093370 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10433 17:44:58.096625 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10434 17:44:58.103469 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10435 17:44:58.109840 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10436 17:44:58.113621 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10437 17:44:58.123581 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10438 17:44:58.130003 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10439 17:44:58.136365 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10440 17:44:58.142968 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10441 17:44:58.146150 <6>[ 0.000000] GICv3: 608 SPIs implemented
10442 17:44:58.149655 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10443 17:44:58.156523 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10444 17:44:58.159669 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10445 17:44:58.166281 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10446 17:44:58.179406 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10447 17:44:58.189507 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10448 17:44:58.199497 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10449 17:44:58.206645 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10450 17:44:58.219901 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10451 17:44:58.226584 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10452 17:44:58.233193 <6>[ 0.009236] Console: colour dummy device 80x25
10453 17:44:58.243080 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10454 17:44:58.249735 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10455 17:44:58.252922 <6>[ 0.029306] LSM: Security Framework initializing
10456 17:44:58.259702 <6>[ 0.034273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10457 17:44:58.270180 <6>[ 0.042135] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10458 17:44:58.276354 <6>[ 0.051549] cblist_init_generic: Setting adjustable number of callback queues.
10459 17:44:58.282934 <6>[ 0.058993] cblist_init_generic: Setting shift to 3 and lim to 1.
10460 17:44:58.293227 <6>[ 0.065330] cblist_init_generic: Setting adjustable number of callback queues.
10461 17:44:58.299400 <6>[ 0.072757] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 17:44:58.302882 <6>[ 0.079159] rcu: Hierarchical SRCU implementation.
10463 17:44:58.309479 <6>[ 0.084174] rcu: Max phase no-delay instances is 1000.
10464 17:44:58.316361 <6>[ 0.091232] EFI services will not be available.
10465 17:44:58.319193 <6>[ 0.096215] smp: Bringing up secondary CPUs ...
10466 17:44:58.327499 <6>[ 0.101269] Detected VIPT I-cache on CPU1
10467 17:44:58.334350 <6>[ 0.101338] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10468 17:44:58.340990 <6>[ 0.101370] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10469 17:44:58.344272 <6>[ 0.101703] Detected VIPT I-cache on CPU2
10470 17:44:58.351077 <6>[ 0.101752] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10471 17:44:58.357245 <6>[ 0.101768] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10472 17:44:58.364142 <6>[ 0.102024] Detected VIPT I-cache on CPU3
10473 17:44:58.370556 <6>[ 0.102070] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10474 17:44:58.377161 <6>[ 0.102083] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10475 17:44:58.380636 <6>[ 0.102386] CPU features: detected: Spectre-v4
10476 17:44:58.387090 <6>[ 0.102391] CPU features: detected: Spectre-BHB
10477 17:44:58.390611 <6>[ 0.102396] Detected PIPT I-cache on CPU4
10478 17:44:58.397074 <6>[ 0.102455] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10479 17:44:58.403876 <6>[ 0.102472] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10480 17:44:58.410922 <6>[ 0.102764] Detected PIPT I-cache on CPU5
10481 17:44:58.417351 <6>[ 0.102831] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10482 17:44:58.423823 <6>[ 0.102847] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10483 17:44:58.427118 <6>[ 0.103131] Detected PIPT I-cache on CPU6
10484 17:44:58.433748 <6>[ 0.103197] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10485 17:44:58.440457 <6>[ 0.103214] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10486 17:44:58.447115 <6>[ 0.103511] Detected PIPT I-cache on CPU7
10487 17:44:58.453518 <6>[ 0.103578] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10488 17:44:58.460209 <6>[ 0.103594] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10489 17:44:58.463719 <6>[ 0.103642] smp: Brought up 1 node, 8 CPUs
10490 17:44:58.470062 <6>[ 0.244902] SMP: Total of 8 processors activated.
10491 17:44:58.473533 <6>[ 0.249854] CPU features: detected: 32-bit EL0 Support
10492 17:44:58.483527 <6>[ 0.255216] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10493 17:44:58.490036 <6>[ 0.264017] CPU features: detected: Common not Private translations
10494 17:44:58.493269 <6>[ 0.270492] CPU features: detected: CRC32 instructions
10495 17:44:58.500098 <6>[ 0.275843] CPU features: detected: RCpc load-acquire (LDAPR)
10496 17:44:58.506630 <6>[ 0.281840] CPU features: detected: LSE atomic instructions
10497 17:44:58.513331 <6>[ 0.287622] CPU features: detected: Privileged Access Never
10498 17:44:58.516579 <6>[ 0.293401] CPU features: detected: RAS Extension Support
10499 17:44:58.526742 <6>[ 0.299010] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10500 17:44:58.530048 <6>[ 0.306230] CPU: All CPU(s) started at EL2
10501 17:44:58.536348 <6>[ 0.310573] alternatives: applying system-wide alternatives
10502 17:44:58.544876 <6>[ 0.321244] devtmpfs: initialized
10503 17:44:58.557630 <6>[ 0.330175] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10504 17:44:58.567390 <6>[ 0.340134] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10505 17:44:58.574050 <6>[ 0.348147] pinctrl core: initialized pinctrl subsystem
10506 17:44:58.577512 <6>[ 0.354928] DMI not present or invalid.
10507 17:44:58.584686 <6>[ 0.359345] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10508 17:44:58.593545 <6>[ 0.366191] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10509 17:44:58.600682 <6>[ 0.373772] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10510 17:44:58.610490 <6>[ 0.381992] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10511 17:44:58.613697 <6>[ 0.390235] audit: initializing netlink subsys (disabled)
10512 17:44:58.623612 <5>[ 0.395928] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10513 17:44:58.630542 <6>[ 0.396670] thermal_sys: Registered thermal governor 'step_wise'
10514 17:44:58.636772 <6>[ 0.403895] thermal_sys: Registered thermal governor 'power_allocator'
10515 17:44:58.640364 <6>[ 0.410150] cpuidle: using governor menu
10516 17:44:58.646837 <6>[ 0.421113] NET: Registered PF_QIPCRTR protocol family
10517 17:44:58.653536 <6>[ 0.426595] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10518 17:44:58.656871 <6>[ 0.433695] ASID allocator initialised with 32768 entries
10519 17:44:58.664192 <6>[ 0.440316] Serial: AMBA PL011 UART driver
10520 17:44:58.673457 <4>[ 0.449489] Trying to register duplicate clock ID: 134
10521 17:44:58.730035 <6>[ 0.509563] KASLR enabled
10522 17:44:58.744623 <6>[ 0.517312] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10523 17:44:58.751113 <6>[ 0.524324] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10524 17:44:58.757706 <6>[ 0.530812] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10525 17:44:58.764234 <6>[ 0.537814] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10526 17:44:58.770772 <6>[ 0.544301] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10527 17:44:58.777436 <6>[ 0.551308] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10528 17:44:58.784181 <6>[ 0.557797] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10529 17:44:58.790795 <6>[ 0.564803] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10530 17:44:58.794115 <6>[ 0.572317] ACPI: Interpreter disabled.
10531 17:44:58.802770 <6>[ 0.578783] iommu: Default domain type: Translated
10532 17:44:58.809629 <6>[ 0.583895] iommu: DMA domain TLB invalidation policy: strict mode
10533 17:44:58.812925 <5>[ 0.590547] SCSI subsystem initialized
10534 17:44:58.819554 <6>[ 0.594713] usbcore: registered new interface driver usbfs
10535 17:44:58.826167 <6>[ 0.600442] usbcore: registered new interface driver hub
10536 17:44:58.829476 <6>[ 0.605994] usbcore: registered new device driver usb
10537 17:44:58.835857 <6>[ 0.612137] pps_core: LinuxPPS API ver. 1 registered
10538 17:44:58.846054 <6>[ 0.617331] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10539 17:44:58.849198 <6>[ 0.626677] PTP clock support registered
10540 17:44:58.852667 <6>[ 0.630922] EDAC MC: Ver: 3.0.0
10541 17:44:58.859962 <6>[ 0.636114] FPGA manager framework
10542 17:44:58.863809 <6>[ 0.639793] Advanced Linux Sound Architecture Driver Initialized.
10543 17:44:58.867084 <6>[ 0.646567] vgaarb: loaded
10544 17:44:58.873487 <6>[ 0.649727] clocksource: Switched to clocksource arch_sys_counter
10545 17:44:58.880426 <5>[ 0.656162] VFS: Disk quotas dquot_6.6.0
10546 17:44:58.887351 <6>[ 0.660348] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10547 17:44:58.890148 <6>[ 0.667537] pnp: PnP ACPI: disabled
10548 17:44:58.898148 <6>[ 0.674249] NET: Registered PF_INET protocol family
10549 17:44:58.904991 <6>[ 0.679842] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10550 17:44:58.919214 <6>[ 0.692155] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10551 17:44:58.929597 <6>[ 0.700967] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10552 17:44:58.936099 <6>[ 0.708940] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10553 17:44:58.942715 <6>[ 0.717636] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10554 17:44:58.954585 <6>[ 0.727380] TCP: Hash tables configured (established 65536 bind 65536)
10555 17:44:58.961229 <6>[ 0.734243] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 17:44:58.967710 <6>[ 0.741441] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10557 17:44:58.974367 <6>[ 0.749141] NET: Registered PF_UNIX/PF_LOCAL protocol family
10558 17:44:58.980825 <6>[ 0.755313] RPC: Registered named UNIX socket transport module.
10559 17:44:58.983924 <6>[ 0.761465] RPC: Registered udp transport module.
10560 17:44:58.990695 <6>[ 0.766397] RPC: Registered tcp transport module.
10561 17:44:58.997242 <6>[ 0.771326] RPC: Registered tcp NFSv4.1 backchannel transport module.
10562 17:44:59.000694 <6>[ 0.777996] PCI: CLS 0 bytes, default 64
10563 17:44:59.003971 <6>[ 0.782395] Unpacking initramfs...
10564 17:44:59.029184 <6>[ 0.801847] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10565 17:44:59.038846 <6>[ 0.810520] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10566 17:44:59.042164 <6>[ 0.819325] kvm [1]: IPA Size Limit: 40 bits
10567 17:44:59.048681 <6>[ 0.823851] kvm [1]: GICv3: no GICV resource entry
10568 17:44:59.052112 <6>[ 0.828872] kvm [1]: disabling GICv2 emulation
10569 17:44:59.058900 <6>[ 0.833559] kvm [1]: GIC system register CPU interface enabled
10570 17:44:59.061977 <6>[ 0.839744] kvm [1]: vgic interrupt IRQ18
10571 17:44:59.068555 <6>[ 0.844109] kvm [1]: VHE mode initialized successfully
10572 17:44:59.075287 <5>[ 0.850678] Initialise system trusted keyrings
10573 17:44:59.082058 <6>[ 0.855555] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10574 17:44:59.089743 <6>[ 0.865557] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10575 17:44:59.096100 <5>[ 0.871954] NFS: Registering the id_resolver key type
10576 17:44:59.099468 <5>[ 0.877257] Key type id_resolver registered
10577 17:44:59.105827 <5>[ 0.881671] Key type id_legacy registered
10578 17:44:59.112480 <6>[ 0.885947] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10579 17:44:59.118985 <6>[ 0.892871] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10580 17:44:59.125734 <6>[ 0.900580] 9p: Installing v9fs 9p2000 file system support
10581 17:44:59.163149 <5>[ 0.939233] Key type asymmetric registered
10582 17:44:59.166539 <5>[ 0.943565] Asymmetric key parser 'x509' registered
10583 17:44:59.176114 <6>[ 0.948751] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10584 17:44:59.179720 <6>[ 0.956364] io scheduler mq-deadline registered
10585 17:44:59.182798 <6>[ 0.961131] io scheduler kyber registered
10586 17:44:59.202255 <6>[ 0.978469] EINJ: ACPI disabled.
10587 17:44:59.234674 <4>[ 1.004177] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 17:44:59.244219 <4>[ 1.014803] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 17:44:59.259468 <6>[ 1.035637] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10590 17:44:59.267342 <6>[ 1.043571] printk: console [ttyS0] disabled
10591 17:44:59.295681 <6>[ 1.068217] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10592 17:44:59.302416 <6>[ 1.077686] printk: console [ttyS0] enabled
10593 17:44:59.305465 <6>[ 1.077686] printk: console [ttyS0] enabled
10594 17:44:59.309239 <6>[ 1.086580] printk: bootconsole [mtk8250] disabled
10595 17:44:59.315619 <6>[ 1.086580] printk: bootconsole [mtk8250] disabled
10596 17:44:59.321953 <6>[ 1.097615] SuperH (H)SCI(F) driver initialized
10597 17:44:59.325367 <6>[ 1.102903] msm_serial: driver initialized
10598 17:44:59.339012 <6>[ 1.111919] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10599 17:44:59.349214 <6>[ 1.120463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10600 17:44:59.355656 <6>[ 1.129004] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10601 17:44:59.365921 <6>[ 1.137633] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10602 17:44:59.372401 <6>[ 1.146340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10603 17:44:59.382231 <6>[ 1.155053] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10604 17:44:59.392421 <6>[ 1.163593] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10605 17:44:59.398736 <6>[ 1.172392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10606 17:44:59.408702 <6>[ 1.180935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10607 17:44:59.420473 <6>[ 1.196560] loop: module loaded
10608 17:44:59.426943 <6>[ 1.202578] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10609 17:44:59.449563 <4>[ 1.225631] mtk-pmic-keys: Failed to locate of_node [id: -1]
10610 17:44:59.456421 <6>[ 1.232345] megasas: 07.719.03.00-rc1
10611 17:44:59.465863 <6>[ 1.241977] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10612 17:44:59.473382 <6>[ 1.249117] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10613 17:44:59.489629 <6>[ 1.265620] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10614 17:44:59.546036 <6>[ 1.315684] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10615 17:45:01.009437 <6>[ 2.785739] Freeing initrd memory: 46412K
10616 17:45:01.019452 <6>[ 2.795964] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10617 17:45:01.030462 <6>[ 2.806813] tun: Universal TUN/TAP device driver, 1.6
10618 17:45:01.034468 <6>[ 2.812902] thunder_xcv, ver 1.0
10619 17:45:01.036914 <6>[ 2.816405] thunder_bgx, ver 1.0
10620 17:45:01.040783 <6>[ 2.819904] nicpf, ver 1.0
10621 17:45:01.051335 <6>[ 2.823950] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10622 17:45:01.054144 <6>[ 2.831425] hns3: Copyright (c) 2017 Huawei Corporation.
10623 17:45:01.060824 <6>[ 2.837014] hclge is initializing
10624 17:45:01.064291 <6>[ 2.840589] e1000: Intel(R) PRO/1000 Network Driver
10625 17:45:01.070875 <6>[ 2.845720] e1000: Copyright (c) 1999-2006 Intel Corporation.
10626 17:45:01.074272 <6>[ 2.851732] e1000e: Intel(R) PRO/1000 Network Driver
10627 17:45:01.080753 <6>[ 2.856947] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10628 17:45:01.087679 <6>[ 2.863134] igb: Intel(R) Gigabit Ethernet Network Driver
10629 17:45:01.094225 <6>[ 2.868784] igb: Copyright (c) 2007-2014 Intel Corporation.
10630 17:45:01.100469 <6>[ 2.874619] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10631 17:45:01.107305 <6>[ 2.881137] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10632 17:45:01.110718 <6>[ 2.887610] sky2: driver version 1.30
10633 17:45:01.117342 <6>[ 2.892642] VFIO - User Level meta-driver version: 0.3
10634 17:45:01.124752 <6>[ 2.900947] usbcore: registered new interface driver usb-storage
10635 17:45:01.131705 <6>[ 2.907399] usbcore: registered new device driver onboard-usb-hub
10636 17:45:01.140306 <6>[ 2.916559] mt6397-rtc mt6359-rtc: registered as rtc0
10637 17:45:01.150111 <6>[ 2.922027] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-13T17:44:36 UTC (1694627076)
10638 17:45:01.153963 <6>[ 2.931607] i2c_dev: i2c /dev entries driver
10639 17:45:01.170307 <6>[ 2.943501] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10640 17:45:01.191477 <6>[ 2.967487] cpu cpu0: EM: created perf domain
10641 17:45:01.194302 <6>[ 2.972429] cpu cpu4: EM: created perf domain
10642 17:45:01.201709 <6>[ 2.978029] sdhci: Secure Digital Host Controller Interface driver
10643 17:45:01.208381 <6>[ 2.984458] sdhci: Copyright(c) Pierre Ossman
10644 17:45:01.214901 <6>[ 2.989421] Synopsys Designware Multimedia Card Interface Driver
10645 17:45:01.221551 <6>[ 2.996063] sdhci-pltfm: SDHCI platform and OF driver helper
10646 17:45:01.224919 <6>[ 2.996065] mmc0: CQHCI version 5.10
10647 17:45:01.231558 <6>[ 3.006374] ledtrig-cpu: registered to indicate activity on CPUs
10648 17:45:01.238045 <6>[ 3.013353] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10649 17:45:01.244891 <6>[ 3.020409] usbcore: registered new interface driver usbhid
10650 17:45:01.248072 <6>[ 3.026232] usbhid: USB HID core driver
10651 17:45:01.254463 <6>[ 3.030446] spi_master spi0: will run message pump with realtime priority
10652 17:45:01.300083 <6>[ 3.069771] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10653 17:45:01.319447 <6>[ 3.085861] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10654 17:45:01.322870 <6>[ 3.099394] mmc0: Command Queue Engine enabled
10655 17:45:01.329874 <6>[ 3.104146] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10656 17:45:01.336174 <6>[ 3.111729] mmcblk0: mmc0:0001 DA4128 116 GiB
10657 17:45:01.339451 <6>[ 3.116679] cros-ec-spi spi0.0: Chrome EC device registered
10658 17:45:01.346408 <6>[ 3.120145] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10659 17:45:01.353260 <6>[ 3.129402] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10660 17:45:01.359657 <6>[ 3.135541] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10661 17:45:01.366495 <6>[ 3.141446] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10662 17:45:01.386528 <6>[ 3.159299] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10663 17:45:01.394164 <6>[ 3.170059] NET: Registered PF_PACKET protocol family
10664 17:45:01.396904 <6>[ 3.175465] 9pnet: Installing 9P2000 support
10665 17:45:01.404064 <5>[ 3.180036] Key type dns_resolver registered
10666 17:45:01.407150 <6>[ 3.185175] registered taskstats version 1
10667 17:45:01.413796 <5>[ 3.189563] Loading compiled-in X.509 certificates
10668 17:45:01.445094 <4>[ 3.214310] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 17:45:01.455045 <4>[ 3.225033] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10670 17:45:01.461787 <3>[ 3.235563] debugfs: File 'uA_load' in directory '/' already present!
10671 17:45:01.468214 <3>[ 3.242264] debugfs: File 'min_uV' in directory '/' already present!
10672 17:45:01.475119 <3>[ 3.248872] debugfs: File 'max_uV' in directory '/' already present!
10673 17:45:01.481876 <3>[ 3.255478] debugfs: File 'constraint_flags' in directory '/' already present!
10674 17:45:01.492650 <3>[ 3.265083] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10675 17:45:01.504970 <6>[ 3.280916] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10676 17:45:01.512088 <6>[ 3.287747] xhci-mtk 11200000.usb: xHCI Host Controller
10677 17:45:01.518657 <6>[ 3.293278] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10678 17:45:01.528683 <6>[ 3.301203] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10679 17:45:01.535334 <6>[ 3.310640] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10680 17:45:01.541885 <6>[ 3.316709] xhci-mtk 11200000.usb: xHCI Host Controller
10681 17:45:01.548904 <6>[ 3.322189] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10682 17:45:01.555076 <6>[ 3.329841] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10683 17:45:01.561753 <6>[ 3.337473] hub 1-0:1.0: USB hub found
10684 17:45:01.565040 <6>[ 3.341507] hub 1-0:1.0: 1 port detected
10685 17:45:01.571841 <6>[ 3.345801] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10686 17:45:01.578931 <6>[ 3.354611] hub 2-0:1.0: USB hub found
10687 17:45:01.581843 <6>[ 3.358638] hub 2-0:1.0: 1 port detected
10688 17:45:01.589919 <6>[ 3.365481] mtk-msdc 11f70000.mmc: Got CD GPIO
10689 17:45:01.600557 <6>[ 3.373425] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10690 17:45:01.607263 <6>[ 3.381492] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10691 17:45:01.617251 <4>[ 3.389418] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10692 17:45:01.627130 <6>[ 3.398955] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10693 17:45:01.633703 <6>[ 3.407031] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10694 17:45:01.640702 <6>[ 3.415063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10695 17:45:01.650387 <6>[ 3.422984] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10696 17:45:01.657565 <6>[ 3.430806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10697 17:45:01.667715 <6>[ 3.438622] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10698 17:45:01.677059 <6>[ 3.449023] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10699 17:45:01.683580 <6>[ 3.457379] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10700 17:45:01.693748 <6>[ 3.465734] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10701 17:45:01.699757 <6>[ 3.474076] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10702 17:45:01.710321 <6>[ 3.482414] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10703 17:45:01.716682 <6>[ 3.490752] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10704 17:45:01.726474 <6>[ 3.499090] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10705 17:45:01.736544 <6>[ 3.507429] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10706 17:45:01.742918 <6>[ 3.515767] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10707 17:45:01.752664 <6>[ 3.524107] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10708 17:45:01.759315 <6>[ 3.532447] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10709 17:45:01.769353 <6>[ 3.540785] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10710 17:45:01.775633 <6>[ 3.549123] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10711 17:45:01.785953 <6>[ 3.557461] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10712 17:45:01.792562 <6>[ 3.565799] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10713 17:45:01.799352 <6>[ 3.574607] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10714 17:45:01.805776 <6>[ 3.581799] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10715 17:45:01.812538 <6>[ 3.588560] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10716 17:45:01.822899 <6>[ 3.595330] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10717 17:45:01.829201 <6>[ 3.602271] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10718 17:45:01.835639 <6>[ 3.609110] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10719 17:45:01.845883 <6>[ 3.618248] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10720 17:45:01.855290 <6>[ 3.627370] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10721 17:45:01.865515 <6>[ 3.636665] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10722 17:45:01.875150 <6>[ 3.646133] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10723 17:45:01.885608 <6>[ 3.655603] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10724 17:45:01.892045 <6>[ 3.664724] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10725 17:45:01.901699 <6>[ 3.674199] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10726 17:45:01.911722 <6>[ 3.683319] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10727 17:45:01.921445 <6>[ 3.692613] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10728 17:45:01.931443 <6>[ 3.702773] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10729 17:45:01.941949 <6>[ 3.714661] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10730 17:45:01.973542 <6>[ 3.746155] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10731 17:45:02.000346 <6>[ 3.776606] hub 2-1:1.0: USB hub found
10732 17:45:02.003996 <6>[ 3.781031] hub 2-1:1.0: 3 ports detected
10733 17:45:02.125095 <6>[ 3.898019] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10734 17:45:02.279763 <6>[ 4.055645] hub 1-1:1.0: USB hub found
10735 17:45:02.282866 <6>[ 4.060103] hub 1-1:1.0: 4 ports detected
10736 17:45:02.357277 <6>[ 4.130337] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10737 17:45:02.604882 <6>[ 4.378050] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10738 17:45:02.737584 <6>[ 4.513894] hub 1-1.4:1.0: USB hub found
10739 17:45:02.741095 <6>[ 4.518560] hub 1-1.4:1.0: 2 ports detected
10740 17:45:03.037235 <6>[ 4.809996] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10741 17:45:03.229382 <6>[ 5.002048] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10742 17:45:14.234735 <6>[ 16.015056] ALSA device list:
10743 17:45:14.240995 <6>[ 16.018345] No soundcards found.
10744 17:45:14.249455 <6>[ 16.026341] Freeing unused kernel memory: 8384K
10745 17:45:14.252608 <6>[ 16.031392] Run /init as init process
10746 17:45:14.300370 <6>[ 16.077521] NET: Registered PF_INET6 protocol family
10747 17:45:14.306708 <6>[ 16.083772] Segment Routing with IPv6
10748 17:45:14.310384 <6>[ 16.087717] In-situ OAM (IOAM) with IPv6
10749 17:45:14.341828 <30>[ 16.102508] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10750 17:45:14.348833 <30>[ 16.126311] systemd[1]: Detected architecture arm64.
10751 17:45:14.349473
10752 17:45:14.355610 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10753 17:45:14.356185
10754 17:45:14.368637 <30>[ 16.145961] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10755 17:45:14.532000 <30>[ 16.306406] systemd[1]: Queued start job for default target Graphical Interface.
10756 17:45:14.581676 <30>[ 16.358662] systemd[1]: Created slice system-getty.slice.
10757 17:45:14.587936 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10758 17:45:14.605206 <30>[ 16.382460] systemd[1]: Created slice system-modprobe.slice.
10759 17:45:14.611352 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10760 17:45:14.629374 <30>[ 16.406590] systemd[1]: Created slice system-serial\x2dgetty.slice.
10761 17:45:14.638870 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10762 17:45:14.653980 <30>[ 16.431209] systemd[1]: Created slice User and Session Slice.
10763 17:45:14.660548 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10764 17:45:14.680431 <30>[ 16.454701] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10765 17:45:14.690108 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10766 17:45:14.708858 <30>[ 16.482739] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10767 17:45:14.715273 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10768 17:45:14.739400 <30>[ 16.510522] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10769 17:45:14.746357 <30>[ 16.522793] systemd[1]: Reached target Local Encrypted Volumes.
10770 17:45:14.753015 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10771 17:45:14.769441 <30>[ 16.546542] systemd[1]: Reached target Paths.
10772 17:45:14.772474 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10773 17:45:14.788613 <30>[ 16.566018] systemd[1]: Reached target Remote File Systems.
10774 17:45:14.795541 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10775 17:45:14.813075 <30>[ 16.590375] systemd[1]: Reached target Slices.
10776 17:45:14.819475 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10777 17:45:14.832676 <30>[ 16.610037] systemd[1]: Reached target Swap.
10778 17:45:14.836088 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10779 17:45:14.856617 <30>[ 16.630498] systemd[1]: Listening on initctl Compatibility Named Pipe.
10780 17:45:14.863057 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10781 17:45:14.869379 <30>[ 16.645776] systemd[1]: Listening on Journal Audit Socket.
10782 17:45:14.875739 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10783 17:45:14.889283 <30>[ 16.666498] systemd[1]: Listening on Journal Socket (/dev/log).
10784 17:45:14.895857 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10785 17:45:14.913998 <30>[ 16.691244] systemd[1]: Listening on Journal Socket.
10786 17:45:14.920646 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10787 17:45:14.936460 <30>[ 16.710700] systemd[1]: Listening on Network Service Netlink Socket.
10788 17:45:14.943192 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10789 17:45:14.957237 <30>[ 16.734563] systemd[1]: Listening on udev Control Socket.
10790 17:45:14.964095 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10791 17:45:14.981846 <30>[ 16.759113] systemd[1]: Listening on udev Kernel Socket.
10792 17:45:14.988331 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10793 17:45:15.041059 <30>[ 16.818069] systemd[1]: Mounting Huge Pages File System...
10794 17:45:15.047311 Mounting [0;1;39mHuge Pages File System[0m...
10795 17:45:15.062254 <30>[ 16.839836] systemd[1]: Mounting POSIX Message Queue File System...
10796 17:45:15.069265 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10797 17:45:15.086971 <30>[ 16.863834] systemd[1]: Mounting Kernel Debug File System...
10798 17:45:15.092883 Mounting [0;1;39mKernel Debug File System[0m...
10799 17:45:15.112118 <30>[ 16.886311] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10800 17:45:15.123892 <30>[ 16.897834] systemd[1]: Starting Create list of static device nodes for the current kernel...
10801 17:45:15.130413 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10802 17:45:15.153575 <30>[ 16.930806] systemd[1]: Starting Load Kernel Module configfs...
10803 17:45:15.160203 Starting [0;1;39mLoad Kernel Module configfs[0m...
10804 17:45:15.180706 <30>[ 16.958564] systemd[1]: Starting Load Kernel Module drm...
10805 17:45:15.187266 Starting [0;1;39mLoad Kernel Module drm[0m...
10806 17:45:15.204293 <30>[ 16.978504] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10807 17:45:15.218661 <30>[ 16.996461] systemd[1]: Starting Journal Service...
10808 17:45:15.222421 Starting [0;1;39mJournal Service[0m...
10809 17:45:15.246269 <30>[ 17.023442] systemd[1]: Starting Load Kernel Modules...
10810 17:45:15.252698 Starting [0;1;39mLoad Kernel Modules[0m...
10811 17:45:15.276437 <30>[ 17.050675] systemd[1]: Starting Remount Root and Kernel File Systems...
10812 17:45:15.283117 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10813 17:45:15.305093 <30>[ 17.082409] systemd[1]: Starting Coldplug All udev Devices...
10814 17:45:15.312188 Starting [0;1;39mColdplug All udev Devices[0m...
10815 17:45:15.335104 <30>[ 17.112244] systemd[1]: Started Journal Service.
10816 17:45:15.341612 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10817 17:45:15.360444 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10818 17:45:15.378146 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10819 17:45:15.393851 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10820 17:45:15.413366 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10821 17:45:15.435310 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10822 17:45:15.457654 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10823 17:45:15.478093 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10824 17:45:15.497500 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10825 17:45:15.512379 See 'systemctl status systemd-remount-fs.service' for details.
10826 17:45:15.554503 Mounting [0;1;39mKernel Configuration File System[0m...
10827 17:45:15.575208 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10828 17:45:15.593289 <46>[ 17.367934] systemd-journald[181]: Received client request to flush runtime journal.
10829 17:45:15.601844 Starting [0;1;39mLoad/Save Random Seed[0m...
10830 17:45:15.621503 Starting [0;1;39mApply Kernel Variables[0m...
10831 17:45:15.641525 Starting [0;1;39mCreate System Users[0m...
10832 17:45:15.662077 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10833 17:45:15.678684 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10834 17:45:15.701540 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10835 17:45:15.718055 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10836 17:45:15.734094 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10837 17:45:15.749538 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10838 17:45:15.805296 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10839 17:45:15.837686 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10840 17:45:15.849084 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10841 17:45:15.864879 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10842 17:45:15.925256 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10843 17:45:15.949845 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10844 17:45:15.970517 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10845 17:45:15.992674 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10846 17:45:16.025939 Starting [0;1;39mNetwork Service[0m...
10847 17:45:16.048037 Starting [0;1;39mNetwork Time Synchronization[0m...
10848 17:45:16.073182 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10849 17:45:16.092157 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10850 17:45:16.153511 <6>[ 17.927638] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10851 17:45:16.163610 Starting [0;1;39mNetwork Name Resoluti<6>[ 17.939252] mc: Linux media interface: v0.10
10852 17:45:16.164184 on[0m...
10853 17:45:16.178112 [[0;32m OK [<6>[ 17.956021] remoteproc remoteproc0: scp is available
10854 17:45:16.185029 0m] Started [0;<6>[ 17.962756] remoteproc remoteproc0: powering up scp
10855 17:45:16.191619 <6>[ 17.966518] videodev: Linux video capture interface: v2.00
10856 17:45:16.200858 <6>[ 17.968908] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10857 17:45:16.208150 1;39mNetwork Tim<6>[ 17.983486] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10858 17:45:16.217784 e Synchronizatio<6>[ 17.987345] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10859 17:45:16.218354 n[0m.
10860 17:45:16.224609 <6>[ 17.999454] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10861 17:45:16.234899 <6>[ 18.008928] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10862 17:45:16.241040 <4>[ 18.009752] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10863 17:45:16.251123 <4>[ 18.025155] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10864 17:45:16.257577 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10865 17:45:16.269665 <6>[ 18.046619] usbcore: registered new interface driver r8152
10866 17:45:16.282682 <6>[ 18.060308] Bluetooth: Core ver 2.22
10867 17:45:16.289177 <6>[ 18.064974] NET: Registered PF_BLUETOOTH protocol family
10868 17:45:16.296029 <6>[ 18.070688] Bluetooth: HCI device and connection manager initialized
10869 17:45:16.299446 <6>[ 18.070755] Bluetooth: HCI socket layer initialized
10870 17:45:16.306003 <6>[ 18.082792] Bluetooth: L2CAP socket layer initialized
10871 17:45:16.309018 <6>[ 18.088235] Bluetooth: SCO socket layer initialized
10872 17:45:16.319548 <3>[ 18.088969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 17:45:16.329357 [[0;32m OK [0m] Found device<3>[ 18.103349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 17:45:16.339135 [0;1;39m/dev/t<3>[ 18.112569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 17:45:16.339690 tyS0[0m.
10876 17:45:16.349057 <6>[ 18.115595] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10877 17:45:16.355708 <6>[ 18.115595] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10878 17:45:16.365857 <3>[ 18.122573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 17:45:16.372319 <6>[ 18.131940] remoteproc remoteproc0: remote processor scp is now up
10880 17:45:16.378785 <3>[ 18.139243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 17:45:16.385480 <6>[ 18.147477] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10882 17:45:16.395535 <6>[ 18.148524] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10883 17:45:16.401875 <6>[ 18.154682] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10884 17:45:16.412150 <3>[ 18.154958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 17:45:16.418326 <3>[ 18.154976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10886 17:45:16.425740 <3>[ 18.154984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10887 17:45:16.435758 <3>[ 18.155033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 17:45:16.442297 <3>[ 18.155095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10889 17:45:16.452302 <3>[ 18.155103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 17:45:16.458883 <3>[ 18.155110] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 17:45:16.468887 <3>[ 18.155186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 17:45:16.475711 <3>[ 18.155195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 17:45:16.485541 <3>[ 18.155202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 17:45:16.491984 <3>[ 18.155210] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 17:45:16.498970 <3>[ 18.155217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 17:45:16.508817 <3>[ 18.155254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10897 17:45:16.515344 <6>[ 18.159525] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10898 17:45:16.522020 <6>[ 18.162249] pci_bus 0000:00: root bus resource [bus 00-ff]
10899 17:45:16.528808 <4>[ 18.175788] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10900 17:45:16.535457 <4>[ 18.175788] Fallback method does not support PEC.
10901 17:45:16.542441 <6>[ 18.177450] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10902 17:45:16.552426 <6>[ 18.194420] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10903 17:45:16.559614 <6>[ 18.194814] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10904 17:45:16.569409 <6>[ 18.196019] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10905 17:45:16.576608 <6>[ 18.201974] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10906 17:45:16.583281 <6>[ 18.206832] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10907 17:45:16.593337 <3>[ 18.207105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 17:45:16.603255 <6>[ 18.210896] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10909 17:45:16.610276 <6>[ 18.218143] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10910 17:45:16.617469 <6>[ 18.218157] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10911 17:45:16.620725 <6>[ 18.218223] pci 0000:00:00.0: supports D1 D2
10912 17:45:16.627523 <6>[ 18.259899] usbcore: registered new interface driver cdc_ether
10913 17:45:16.634073 <6>[ 18.266653] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10914 17:45:16.641488 <6>[ 18.267237] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10915 17:45:16.648386 <6>[ 18.267879] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10916 17:45:16.654619 <6>[ 18.268002] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10917 17:45:16.661297 <6>[ 18.268028] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10918 17:45:16.671708 <6>[ 18.268044] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10919 17:45:16.678719 <6>[ 18.268059] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10920 17:45:16.681926 <6>[ 18.268164] pci 0000:01:00.0: supports D1 D2
10921 17:45:16.688496 <6>[ 18.268166] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10922 17:45:16.695460 <6>[ 18.273842] r8152 2-1.3:1.0 eth0: v1.12.13
10923 17:45:16.701856 <6>[ 18.277811] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10924 17:45:16.705409 <6>[ 18.283285] usbcore: registered new interface driver r8153_ecm
10925 17:45:16.718475 <6>[ 18.284323] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10926 17:45:16.725177 <6>[ 18.284419] usbcore: registered new interface driver uvcvideo
10927 17:45:16.731905 <6>[ 18.291091] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10928 17:45:16.738676 <6>[ 18.291853] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10929 17:45:16.745738 <6>[ 18.292201] usbcore: registered new interface driver btusb
10930 17:45:16.755277 <4>[ 18.292968] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10931 17:45:16.762307 <3>[ 18.292983] Bluetooth: hci0: Failed to load firmware file (-2)
10932 17:45:16.769201 <3>[ 18.292989] Bluetooth: hci0: Failed to set up firmware (-2)
10933 17:45:16.778796 <4>[ 18.292994] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10934 17:45:16.785922 <6>[ 18.303481] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10935 17:45:16.793032 <6>[ 18.303928] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10936 17:45:16.803105 <3>[ 18.316785] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 17:45:16.810059 <3>[ 18.317615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10938 17:45:16.816938 <6>[ 18.324683] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10939 17:45:16.827276 <6>[ 18.324696] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10940 17:45:16.833932 <3>[ 18.344168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 17:45:16.844064 <3>[ 18.344891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10942 17:45:16.851005 <6>[ 18.351272] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10943 17:45:16.857239 <6>[ 18.351284] pci 0000:00:00.0: PCI bridge to [bus 01]
10944 17:45:16.867278 <3>[ 18.362658] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 17:45:16.873811 <6>[ 18.367870] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10946 17:45:16.880541 <6>[ 18.368020] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10947 17:45:16.890585 <3>[ 18.397556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 17:45:16.893670 <6>[ 18.399937] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10949 17:45:16.903716 <3>[ 18.427232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 17:45:16.910065 <6>[ 18.432607] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10951 17:45:16.916661 <3>[ 18.458890] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 17:45:16.926960 <5>[ 18.487339] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10953 17:45:16.933299 <3>[ 18.511800] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 17:45:16.943704 <5>[ 18.526234] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10955 17:45:16.949901 <4>[ 18.725390] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10956 17:45:16.956509 <6>[ 18.734288] cfg80211: failed to load regulatory.db
10957 17:45:16.963066 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10958 17:45:16.996675 <6>[ 18.771404] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10959 17:45:17.002847 <6>[ 18.778902] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10960 17:45:17.023668 <6>[ 18.801855] mt7921e 0000:01:00.0: ASIC revision: 79610010
10961 17:45:17.060555 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10962 17:45:17.075849 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10963 17:45:17.091651 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10964 17:45:17.110963 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10965 17:45:17.130804 <4>[ 18.902331] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10966 17:45:17.137097 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10967 17:45:17.152064 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10968 17:45:17.171201 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10969 17:45:17.219984 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10970 17:45:17.248874 <4>[ 19.020486] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10971 17:45:17.255543 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10972 17:45:17.272666 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10973 17:45:17.288548 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10974 17:45:17.307297 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10975 17:45:17.319845 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10976 17:45:17.340178 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10977 17:45:17.352591 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10978 17:45:17.368700 <4>[ 19.140338] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 17:45:17.375029 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10980 17:45:17.424904 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10981 17:45:17.453170 Starting [0;1;39mUser Login Management[0m...
10982 17:45:17.493283 Starting [0;1;39mLoad/<4>[ 19.263179] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 17:45:17.496177 Save RF Kill Switch Status[0m...
10984 17:45:17.517490 Starting [0;1;39mPermit User Sessions[0m...
10985 17:45:17.533531 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10986 17:45:17.554044 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10987 17:45:17.617339 [[0;32m OK [0m] Started [0;<4>[ 19.388555] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10988 17:45:17.617430 1;39mGetty on tty1[0m.
10989 17:45:17.639818 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10990 17:45:17.656268 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10991 17:45:17.672905 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10992 17:45:17.689791 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10993 17:45:17.704556 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10994 17:45:17.737508 <4>[ 19.509093] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10995 17:45:17.765577 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10996 17:45:17.800218 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10997 17:45:17.831429
10998 17:45:17.831537
10999 17:45:17.835023 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11000 17:45:17.835132
11001 17:45:17.838075 debian-bullseye-arm64 login: root (automatic login)
11002 17:45:17.838180
11003 17:45:17.841516
11004 17:45:17.858723 <4>[ 19.630426] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11005 17:45:17.865297 Linux debian-bullseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023 aarch64
11006 17:45:17.868558
11007 17:45:17.875539 The programs included with the Debian GNU/Linux system are free software;
11008 17:45:17.878542 the exact distribution terms for each program are described in the
11009 17:45:17.885352 individual files in /usr/share/doc/*/copyright.
11010 17:45:17.885439
11011 17:45:17.888742 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11012 17:45:17.891685 permitted by applicable law.
11013 17:45:17.892049 Matched prompt #10: / #
11015 17:45:17.892299 Setting prompt string to ['/ #']
11016 17:45:17.892394 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11018 17:45:17.892588 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11019 17:45:17.892680 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11020 17:45:17.892754 Setting prompt string to ['/ #']
11021 17:45:17.892814 Forcing a shell prompt, looking for ['/ #']
11023 17:45:17.943028 / #
11024 17:45:17.943124 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11025 17:45:17.943200 Waiting using forced prompt support (timeout 00:02:30)
11026 17:45:17.948074
11027 17:45:17.948340 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11028 17:45:17.948429 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11029 17:45:17.948532 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11030 17:45:17.948623 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11031 17:45:17.948723 end: 2 depthcharge-action (duration 00:01:36) [common]
11032 17:45:17.948810 start: 3 lava-test-retry (timeout 00:05:00) [common]
11033 17:45:17.948894 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11034 17:45:17.948981 Using namespace: common
11036 17:45:18.049345 / # #
11037 17:45:18.049496 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11038 17:45:18.049614 <4>[ 19.752523] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11039 17:45:18.054300 #
11040 17:45:18.054563 Using /lava-11518305
11042 17:45:18.154861 / # export SHELL=/bin/sh
11043 17:45:18.155008 <4>[ 19.872373] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11044 17:45:18.155082 export SHELL=/bin/sh<6>[ 19.903343] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11045 17:45:18.155157 <6>[ 19.911123] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11046 17:45:18.159843
11048 17:45:18.260357 / # . /lava-11518305/environment
11049 17:45:18.260501 <4>[ 19.992290] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11050 17:45:18.265485 . /lava-11518305/environment
11052 17:45:18.366016 / # /lava-11518305/bin/lava-test-runner /lava-11518305/0
11053 17:45:18.366130 Test shell timeout: 10s (minimum of the action and connection timeout)
11054 17:45:18.366463 /lava-11518305/bin/lava-test-runner /lava-11518305/0<3>[ 20.110056] mt7921e 0000:01:00.0: hardware init failed
11055 17:45:18.371299
11056 17:45:18.413118 + export TESTRUN_ID=0_cros-ec
11057 17:45:18.413207 +<8>[ 20.175548] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11518305_1.5.2.3.1>
11058 17:45:18.413275 cd /lava-11518305/0/tests/0_cros-ec
11059 17:45:18.413337 + cat uuid
11060 17:45:18.413397 + UUID=11518305_1.5.2.3.1
11061 17:45:18.413455 + set +x
11062 17:45:18.413512 + python3 -m cros.runners.lava_runner -v
11063 17:45:18.413742 Received signal: <STARTRUN> 0_cros-ec 11518305_1.5.2.3.1
11064 17:45:18.413809 Starting test lava.0_cros-ec (11518305_1.5.2.3.1)
11065 17:45:18.413889 Skipping test definition patterns.
11066 17:45:18.792020 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11067 17:45:18.799032 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11068 17:45:18.802362
11069 17:45:18.809124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11070 17:45:18.809380 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11072 17:45:18.815590 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11073 17:45:18.825534 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11074 17:45:18.825618
11075 17:45:18.828921 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_ac<8
11076 17:45:18.829053 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_ac<8', 'result': 'unknown'}
11077 17:45:18.835176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_ac<8>[ 20.611330] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11518305_1.5.2.3.1>
11078 17:45:18.835429 Received signal: <ENDRUN> 0_cros-ec 11518305_1.5.2.3.1
11079 17:45:18.835511 Ending use of test pattern.
11080 17:45:18.835573 Ending test lava.0_cros-ec (11518305_1.5.2.3.1), duration 0.42
11082 17:45:18.838739 cel_iio_data_is_valid RESULT=skip>
11083 17:45:18.841873 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11084 17:45:18.848673 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11085 17:45:18.851825
11086 17:45:18.855210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11087 17:45:18.855480 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11089 17:45:18.862032 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11090 17:45:18.868298 Checks the standard ABI for the main Embedded Controller. ... ok
11091 17:45:18.868381
11092 17:45:18.872089 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11094 17:45:18.875186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11095 17:45:18.878117 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11096 17:45:18.884910 Checks the main Embedded controller character device. ... ok
11097 17:45:18.885039
11098 17:45:18.891375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11099 17:45:18.891628 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11101 17:45:18.894751 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11102 17:45:18.901715 Checks basic comunication with the main Embedded controller. ... ok
11103 17:45:18.901800
11104 17:45:18.907899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11105 17:45:18.908151 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11107 17:45:18.911103 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11108 17:45:18.921187 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11109 17:45:18.921271
11110 17:45:18.924522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11111 17:45:18.924777 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11113 17:45:18.931146 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11114 17:45:18.941195 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11115 17:45:18.941279
11116 17:45:18.944425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11117 17:45:18.944678 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11119 17:45:18.950987 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11120 17:45:18.957246 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11121 17:45:18.957330
11122 17:45:18.964183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11123 17:45:18.964434 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11125 17:45:18.967534 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11126 17:45:18.977452 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11127 17:45:18.977537
11128 17:45:18.980623 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11130 17:45:18.983979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11131 17:45:18.987259 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11132 17:45:18.997046 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11133 17:45:18.997132
11134 17:45:19.000568 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11136 17:45:19.004093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11137 17:45:19.007223 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11138 17:45:19.013463 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11139 17:45:19.013548
11140 17:45:19.020238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11141 17:45:19.020481 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11143 17:45:19.026859 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11144 17:45:19.033576 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11145 17:45:19.033653
11146 17:45:19.040072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11147 17:45:19.040319 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11149 17:45:19.046838 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11150 17:45:19.053448 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11151 17:45:19.053525
11152 17:45:19.060055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11153 17:45:19.060294 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11155 17:45:19.066746 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11156 17:45:19.073192 Check the cros battery ABI. ... skipped 'No BAT found'
11157 17:45:19.073268
11158 17:45:19.079896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11159 17:45:19.080142 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11161 17:45:19.086635 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11162 17:45:19.093232 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11163 17:45:19.093307
11164 17:45:19.099497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11165 17:45:19.099741 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11167 17:45:19.106227 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11168 17:45:19.112878 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11169 17:45:19.112992
11170 17:45:19.116359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11171 17:45:19.116595 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11173 17:45:19.122823 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11174 17:45:19.129188 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11175 17:45:19.129258
11176 17:45:19.135919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11177 17:45:19.135998
11178 17:45:19.136230 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11180 17:45:19.142531 ----------------------------------------------------------------------
11181 17:45:19.146059 Ran 18 tests in 0.006s
11182 17:45:19.146131
11183 17:45:19.146195 OK (skipped=15)
11184 17:45:19.149138 + set +x
11185 17:45:19.149210 <LAVA_TEST_RUNNER EXIT>
11186 17:45:19.149443 ok: lava_test_shell seems to have completed
11187 17:45:19.149605 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11188 17:45:19.149704 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11189 17:45:19.149789 end: 3 lava-test-retry (duration 00:00:01) [common]
11190 17:45:19.149876 start: 4 finalize (timeout 00:08:03) [common]
11191 17:45:19.149968 start: 4.1 power-off (timeout 00:00:30) [common]
11192 17:45:19.150124 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11193 17:45:19.224535 >> Command sent successfully.
11194 17:45:19.226909 Returned 0 in 0 seconds
11195 17:45:19.327276 end: 4.1 power-off (duration 00:00:00) [common]
11197 17:45:19.327596 start: 4.2 read-feedback (timeout 00:08:02) [common]
11198 17:45:19.327856 Listened to connection for namespace 'common' for up to 1s
11199 17:45:20.328787 Finalising connection for namespace 'common'
11200 17:45:20.329001 Disconnecting from shell: Finalise
11201 17:45:20.329083 / #
11202 17:45:20.429368 end: 4.2 read-feedback (duration 00:00:01) [common]
11203 17:45:20.429512 end: 4 finalize (duration 00:00:01) [common]
11204 17:45:20.429624 Cleaning after the job
11205 17:45:20.429727 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/ramdisk
11206 17:45:20.434730 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/kernel
11207 17:45:20.441007 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/dtb
11208 17:45:20.441180 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518305/tftp-deploy-_ikyzgwh/modules
11209 17:45:20.446546 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11518305
11210 17:45:20.541411 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11518305
11211 17:45:20.541586 Job finished correctly