Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 19
1 17:33:39.025351 lava-dispatcher, installed at version: 2023.06
2 17:33:39.025592 start: 0 validate
3 17:33:39.025737 Start time: 2023-09-13 17:33:39.025729+00:00 (UTC)
4 17:33:39.025886 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:33:39.026043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 17:33:39.277972 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:33:39.278206 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:33:39.525948 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:33:39.526127 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:33:39.776169 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:33:39.776371 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 17:33:40.271489 validate duration: 1.25
14 17:33:40.271858 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:33:40.271962 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:33:40.272052 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:33:40.272194 Not decompressing ramdisk as can be used compressed.
18 17:33:40.272293 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 17:33:40.272364 saving as /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/ramdisk/rootfs.cpio.gz
20 17:33:40.272451 total size: 8181372 (7 MB)
21 17:33:40.274104 progress 0 % (0 MB)
22 17:33:40.276977 progress 5 % (0 MB)
23 17:33:40.279750 progress 10 % (0 MB)
24 17:33:40.282451 progress 15 % (1 MB)
25 17:33:40.284938 progress 20 % (1 MB)
26 17:33:40.287744 progress 25 % (1 MB)
27 17:33:40.290197 progress 30 % (2 MB)
28 17:33:40.292834 progress 35 % (2 MB)
29 17:33:40.295103 progress 40 % (3 MB)
30 17:33:40.297507 progress 45 % (3 MB)
31 17:33:40.299721 progress 50 % (3 MB)
32 17:33:40.302057 progress 55 % (4 MB)
33 17:33:40.304231 progress 60 % (4 MB)
34 17:33:40.306532 progress 65 % (5 MB)
35 17:33:40.308768 progress 70 % (5 MB)
36 17:33:40.311045 progress 75 % (5 MB)
37 17:33:40.313197 progress 80 % (6 MB)
38 17:33:40.315581 progress 85 % (6 MB)
39 17:33:40.317767 progress 90 % (7 MB)
40 17:33:40.320121 progress 95 % (7 MB)
41 17:33:40.322318 progress 100 % (7 MB)
42 17:33:40.322554 7 MB downloaded in 0.05 s (155.73 MB/s)
43 17:33:40.322763 end: 1.1.1 http-download (duration 00:00:00) [common]
45 17:33:40.323145 end: 1.1 download-retry (duration 00:00:00) [common]
46 17:33:40.323265 start: 1.2 download-retry (timeout 00:10:00) [common]
47 17:33:40.323384 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 17:33:40.323561 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 17:33:40.323703 saving as /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/kernel/Image
50 17:33:40.323794 total size: 49220096 (46 MB)
51 17:33:40.323885 No compression specified
52 17:33:40.325478 progress 0 % (0 MB)
53 17:33:40.338985 progress 5 % (2 MB)
54 17:33:40.352708 progress 10 % (4 MB)
55 17:33:40.365846 progress 15 % (7 MB)
56 17:33:40.378906 progress 20 % (9 MB)
57 17:33:40.392477 progress 25 % (11 MB)
58 17:33:40.405893 progress 30 % (14 MB)
59 17:33:40.419428 progress 35 % (16 MB)
60 17:33:40.433124 progress 40 % (18 MB)
61 17:33:40.446518 progress 45 % (21 MB)
62 17:33:40.460417 progress 50 % (23 MB)
63 17:33:40.475036 progress 55 % (25 MB)
64 17:33:40.488993 progress 60 % (28 MB)
65 17:33:40.503005 progress 65 % (30 MB)
66 17:33:40.516984 progress 70 % (32 MB)
67 17:33:40.531169 progress 75 % (35 MB)
68 17:33:40.545635 progress 80 % (37 MB)
69 17:33:40.559842 progress 85 % (39 MB)
70 17:33:40.573906 progress 90 % (42 MB)
71 17:33:40.587410 progress 95 % (44 MB)
72 17:33:40.601183 progress 100 % (46 MB)
73 17:33:40.601332 46 MB downloaded in 0.28 s (169.13 MB/s)
74 17:33:40.601540 end: 1.2.1 http-download (duration 00:00:00) [common]
76 17:33:40.601903 end: 1.2 download-retry (duration 00:00:00) [common]
77 17:33:40.602008 start: 1.3 download-retry (timeout 00:10:00) [common]
78 17:33:40.602132 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 17:33:40.602326 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 17:33:40.602398 saving as /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/dtb/mt8192-asurada-spherion-r0.dtb
81 17:33:40.602459 total size: 47278 (0 MB)
82 17:33:40.602520 No compression specified
83 17:33:40.603802 progress 69 % (0 MB)
84 17:33:40.604094 progress 100 % (0 MB)
85 17:33:40.604288 0 MB downloaded in 0.00 s (24.71 MB/s)
86 17:33:40.604465 end: 1.3.1 http-download (duration 00:00:00) [common]
88 17:33:40.604735 end: 1.3 download-retry (duration 00:00:00) [common]
89 17:33:40.604819 start: 1.4 download-retry (timeout 00:10:00) [common]
90 17:33:40.604899 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 17:33:40.605018 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 17:33:40.605085 saving as /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/modules/modules.tar
93 17:33:40.605144 total size: 8628656 (8 MB)
94 17:33:40.605204 Using unxz to decompress xz
95 17:33:40.609336 progress 0 % (0 MB)
96 17:33:40.631625 progress 5 % (0 MB)
97 17:33:40.654833 progress 10 % (0 MB)
98 17:33:40.682802 progress 15 % (1 MB)
99 17:33:40.710443 progress 20 % (1 MB)
100 17:33:40.737376 progress 25 % (2 MB)
101 17:33:40.765396 progress 30 % (2 MB)
102 17:33:40.794369 progress 35 % (2 MB)
103 17:33:40.821278 progress 40 % (3 MB)
104 17:33:40.846387 progress 45 % (3 MB)
105 17:33:40.874268 progress 50 % (4 MB)
106 17:33:40.900748 progress 55 % (4 MB)
107 17:33:40.926596 progress 60 % (4 MB)
108 17:33:40.953788 progress 65 % (5 MB)
109 17:33:40.980669 progress 70 % (5 MB)
110 17:33:41.005998 progress 75 % (6 MB)
111 17:33:41.033868 progress 80 % (6 MB)
112 17:33:41.065891 progress 85 % (7 MB)
113 17:33:41.095241 progress 90 % (7 MB)
114 17:33:41.122356 progress 95 % (7 MB)
115 17:33:41.146688 progress 100 % (8 MB)
116 17:33:41.152189 8 MB downloaded in 0.55 s (15.04 MB/s)
117 17:33:41.152431 end: 1.4.1 http-download (duration 00:00:01) [common]
119 17:33:41.152786 end: 1.4 download-retry (duration 00:00:01) [common]
120 17:33:41.152881 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 17:33:41.152978 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 17:33:41.153062 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 17:33:41.153151 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 17:33:41.153380 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc
125 17:33:41.153523 makedir: /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin
126 17:33:41.153633 makedir: /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/tests
127 17:33:41.153734 makedir: /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/results
128 17:33:41.153849 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-add-keys
129 17:33:41.154013 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-add-sources
130 17:33:41.154167 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-background-process-start
131 17:33:41.154300 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-background-process-stop
132 17:33:41.154436 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-common-functions
133 17:33:41.154577 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-echo-ipv4
134 17:33:41.154706 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-install-packages
135 17:33:41.154831 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-installed-packages
136 17:33:41.154967 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-os-build
137 17:33:41.155095 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-probe-channel
138 17:33:41.155221 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-probe-ip
139 17:33:41.155348 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-target-ip
140 17:33:41.155489 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-target-mac
141 17:33:41.155617 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-target-storage
142 17:33:41.155779 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-case
143 17:33:41.155906 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-event
144 17:33:41.156030 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-feedback
145 17:33:41.156156 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-raise
146 17:33:41.156282 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-reference
147 17:33:41.156407 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-runner
148 17:33:41.156531 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-set
149 17:33:41.156660 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-test-shell
150 17:33:41.156790 Updating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-install-packages (oe)
151 17:33:41.156945 Updating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/bin/lava-installed-packages (oe)
152 17:33:41.157099 Creating /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/environment
153 17:33:41.157202 LAVA metadata
154 17:33:41.157274 - LAVA_JOB_ID=11518302
155 17:33:41.157338 - LAVA_DISPATCHER_IP=192.168.201.1
156 17:33:41.157439 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 17:33:41.157505 skipped lava-vland-overlay
158 17:33:41.157578 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 17:33:41.157659 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 17:33:41.157723 skipped lava-multinode-overlay
161 17:33:41.157819 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 17:33:41.157941 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 17:33:41.158040 Loading test definitions
164 17:33:41.158130 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 17:33:41.158206 Using /lava-11518302 at stage 0
166 17:33:41.158535 uuid=11518302_1.5.2.3.1 testdef=None
167 17:33:41.158624 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 17:33:41.158707 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 17:33:41.159280 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 17:33:41.159502 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 17:33:41.160192 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 17:33:41.160414 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 17:33:41.161050 runner path: /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/0/tests/0_dmesg test_uuid 11518302_1.5.2.3.1
176 17:33:41.161207 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 17:33:41.161444 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 17:33:41.161560 Using /lava-11518302 at stage 1
180 17:33:41.161872 uuid=11518302_1.5.2.3.5 testdef=None
181 17:33:41.161960 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 17:33:41.162043 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 17:33:41.162527 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 17:33:41.162741 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 17:33:41.163874 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 17:33:41.164100 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 17:33:41.164727 runner path: /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/1/tests/1_bootrr test_uuid 11518302_1.5.2.3.5
190 17:33:41.164880 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 17:33:41.165080 Creating lava-test-runner.conf files
193 17:33:41.165141 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/0 for stage 0
194 17:33:41.165230 - 0_dmesg
195 17:33:41.165310 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11518302/lava-overlay-vh4t95qc/lava-11518302/1 for stage 1
196 17:33:41.165400 - 1_bootrr
197 17:33:41.165508 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 17:33:41.165595 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 17:33:41.173892 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 17:33:41.174001 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 17:33:41.174088 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 17:33:41.174173 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 17:33:41.174259 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 17:33:41.435415 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 17:33:41.435838 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 17:33:41.435970 extracting modules file /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11518302/extract-overlay-ramdisk-phi4svs2/ramdisk
207 17:33:41.681294 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 17:33:41.681469 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 17:33:41.681590 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518302/compress-overlay-af4cp7v0/overlay-1.5.2.4.tar.gz to ramdisk
210 17:33:41.681676 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518302/compress-overlay-af4cp7v0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11518302/extract-overlay-ramdisk-phi4svs2/ramdisk
211 17:33:41.690439 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 17:33:41.690570 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 17:33:41.690676 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 17:33:41.690784 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 17:33:41.690876 Building ramdisk /var/lib/lava/dispatcher/tmp/11518302/extract-overlay-ramdisk-phi4svs2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11518302/extract-overlay-ramdisk-phi4svs2/ramdisk
216 17:33:42.075975 >> 145256 blocks
217 17:33:44.397263 rename /var/lib/lava/dispatcher/tmp/11518302/extract-overlay-ramdisk-phi4svs2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/ramdisk/ramdisk.cpio.gz
218 17:33:44.397697 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 17:33:44.397826 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 17:33:44.397931 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 17:33:44.398044 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/kernel/Image'
222 17:33:57.662509 Returned 0 in 13 seconds
223 17:33:57.763125 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/kernel/image.itb
224 17:33:58.160749 output: FIT description: Kernel Image image with one or more FDT blobs
225 17:33:58.161116 output: Created: Wed Sep 13 18:33:58 2023
226 17:33:58.161197 output: Image 0 (kernel-1)
227 17:33:58.161267 output: Description:
228 17:33:58.161329 output: Created: Wed Sep 13 18:33:58 2023
229 17:33:58.161392 output: Type: Kernel Image
230 17:33:58.161458 output: Compression: lzma compressed
231 17:33:58.161519 output: Data Size: 11039249 Bytes = 10780.52 KiB = 10.53 MiB
232 17:33:58.161580 output: Architecture: AArch64
233 17:33:58.161643 output: OS: Linux
234 17:33:58.161709 output: Load Address: 0x00000000
235 17:33:58.161766 output: Entry Point: 0x00000000
236 17:33:58.161820 output: Hash algo: crc32
237 17:33:58.161873 output: Hash value: 2ab54ae9
238 17:33:58.161926 output: Image 1 (fdt-1)
239 17:33:58.161982 output: Description: mt8192-asurada-spherion-r0
240 17:33:58.162038 output: Created: Wed Sep 13 18:33:58 2023
241 17:33:58.162091 output: Type: Flat Device Tree
242 17:33:58.162144 output: Compression: uncompressed
243 17:33:58.162200 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 17:33:58.162256 output: Architecture: AArch64
245 17:33:58.162310 output: Hash algo: crc32
246 17:33:58.162363 output: Hash value: cc4352de
247 17:33:58.162416 output: Image 2 (ramdisk-1)
248 17:33:58.162471 output: Description: unavailable
249 17:33:58.162523 output: Created: Wed Sep 13 18:33:58 2023
250 17:33:58.162576 output: Type: RAMDisk Image
251 17:33:58.162628 output: Compression: Unknown Compression
252 17:33:58.162680 output: Data Size: 21389860 Bytes = 20888.54 KiB = 20.40 MiB
253 17:33:58.162736 output: Architecture: AArch64
254 17:33:58.162791 output: OS: Linux
255 17:33:58.162843 output: Load Address: unavailable
256 17:33:58.162896 output: Entry Point: unavailable
257 17:33:58.162951 output: Hash algo: crc32
258 17:33:58.163003 output: Hash value: bb55c8e7
259 17:33:58.163057 output: Default Configuration: 'conf-1'
260 17:33:58.163110 output: Configuration 0 (conf-1)
261 17:33:58.163161 output: Description: mt8192-asurada-spherion-r0
262 17:33:58.163215 output: Kernel: kernel-1
263 17:33:58.163272 output: Init Ramdisk: ramdisk-1
264 17:33:58.163326 output: FDT: fdt-1
265 17:33:58.163379 output: Loadables: kernel-1
266 17:33:58.163430 output:
267 17:33:58.163643 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 17:33:58.163753 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 17:33:58.163859 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 17:33:58.163955 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 17:33:58.164036 No LXC device requested
272 17:33:58.164116 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 17:33:58.164206 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 17:33:58.164286 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 17:33:58.164360 Checking files for TFTP limit of 4294967296 bytes.
276 17:33:58.164882 end: 1 tftp-deploy (duration 00:00:18) [common]
277 17:33:58.164987 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 17:33:58.165085 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 17:33:58.165213 substitutions:
280 17:33:58.165286 - {DTB}: 11518302/tftp-deploy-lkfdnmk9/dtb/mt8192-asurada-spherion-r0.dtb
281 17:33:58.165353 - {INITRD}: 11518302/tftp-deploy-lkfdnmk9/ramdisk/ramdisk.cpio.gz
282 17:33:58.165412 - {KERNEL}: 11518302/tftp-deploy-lkfdnmk9/kernel/Image
283 17:33:58.165472 - {LAVA_MAC}: None
284 17:33:58.165529 - {PRESEED_CONFIG}: None
285 17:33:58.165584 - {PRESEED_LOCAL}: None
286 17:33:58.165638 - {RAMDISK}: 11518302/tftp-deploy-lkfdnmk9/ramdisk/ramdisk.cpio.gz
287 17:33:58.165693 - {ROOT_PART}: None
288 17:33:58.165750 - {ROOT}: None
289 17:33:58.165847 - {SERVER_IP}: 192.168.201.1
290 17:33:58.165933 - {TEE}: None
291 17:33:58.166028 Parsed boot commands:
292 17:33:58.166115 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 17:33:58.166349 Parsed boot commands: tftpboot 192.168.201.1 11518302/tftp-deploy-lkfdnmk9/kernel/image.itb 11518302/tftp-deploy-lkfdnmk9/kernel/cmdline
294 17:33:58.166463 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 17:33:58.166591 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 17:33:58.166720 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 17:33:58.166817 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 17:33:58.166894 Not connected, no need to disconnect.
299 17:33:58.166975 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 17:33:58.167059 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 17:33:58.167129 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 17:33:58.171362 Setting prompt string to ['lava-test: # ']
303 17:33:58.171871 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 17:33:58.171987 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 17:33:58.172129 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 17:33:58.172461 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 17:33:58.172778 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 17:34:03.310376 >> Command sent successfully.
309 17:34:03.313236 Returned 0 in 5 seconds
310 17:34:03.413607 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 17:34:03.413965 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 17:34:03.414065 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 17:34:03.414156 Setting prompt string to 'Starting depthcharge on Spherion...'
315 17:34:03.414225 Changing prompt to 'Starting depthcharge on Spherion...'
316 17:34:03.414298 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 17:34:03.414581 [Enter `^Ec?' for help]
318 17:34:03.588703
319 17:34:03.588884
320 17:34:03.588963 F0: 102B 0000
321 17:34:03.589025
322 17:34:03.589083 F3: 1001 0000 [0200]
323 17:34:03.589144
324 17:34:03.591888 F3: 1001 0000
325 17:34:03.592008
326 17:34:03.592126 F7: 102D 0000
327 17:34:03.592189
328 17:34:03.592246 F1: 0000 0000
329 17:34:03.595566
330 17:34:03.595682 V0: 0000 0000 [0001]
331 17:34:03.595752
332 17:34:03.595810 00: 0007 8000
333 17:34:03.595871
334 17:34:03.598648 01: 0000 0000
335 17:34:03.598720
336 17:34:03.598778 BP: 0C00 0209 [0000]
337 17:34:03.598837
338 17:34:03.601927 G0: 1182 0000
339 17:34:03.601995
340 17:34:03.602055 EC: 0000 0021 [4000]
341 17:34:03.602114
342 17:34:03.605352 S7: 0000 0000 [0000]
343 17:34:03.605419
344 17:34:03.605475 CC: 0000 0000 [0001]
345 17:34:03.605533
346 17:34:03.608796 T0: 0000 0040 [010F]
347 17:34:03.608895
348 17:34:03.608986 Jump to BL
349 17:34:03.609077
350 17:34:03.635371
351 17:34:03.635485
352 17:34:03.635552
353 17:34:03.642207 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 17:34:03.645525 ARM64: Exception handlers installed.
355 17:34:03.648814 ARM64: Testing exception
356 17:34:03.652361 ARM64: Done test exception
357 17:34:03.659173 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 17:34:03.669855 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 17:34:03.676826 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 17:34:03.686448 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 17:34:03.693188 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 17:34:03.699873 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 17:34:03.712197 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 17:34:03.718674 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 17:34:03.737839 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 17:34:03.741242 WDT: Last reset was cold boot
367 17:34:03.744677 SPI1(PAD0) initialized at 2873684 Hz
368 17:34:03.747972 SPI5(PAD0) initialized at 992727 Hz
369 17:34:03.751386 VBOOT: Loading verstage.
370 17:34:03.758000 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 17:34:03.761375 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 17:34:03.764776 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 17:34:03.768277 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 17:34:03.775576 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 17:34:03.781917 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 17:34:03.792879 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 17:34:03.792970
378 17:34:03.793068
379 17:34:03.803695 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 17:34:03.807185 ARM64: Exception handlers installed.
381 17:34:03.807271 ARM64: Testing exception
382 17:34:03.810679 ARM64: Done test exception
383 17:34:03.813591 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 17:34:03.820556 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 17:34:03.833754 Probing TPM: . done!
386 17:34:03.833864 TPM ready after 0 ms
387 17:34:03.841123 Connected to device vid:did:rid of 1ae0:0028:00
388 17:34:03.848381 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 17:34:03.907650 Initialized TPM device CR50 revision 0
390 17:34:03.919563 tlcl_send_startup: Startup return code is 0
391 17:34:03.919696 TPM: setup succeeded
392 17:34:03.930648 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 17:34:03.939771 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 17:34:03.953773 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 17:34:03.960593 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 17:34:03.964336 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 17:34:03.968417 in-header: 03 07 00 00 08 00 00 00
398 17:34:03.971670 in-data: aa e4 47 04 13 02 00 00
399 17:34:03.971768 Chrome EC: UHEPI supported
400 17:34:03.978879 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 17:34:03.983038 in-header: 03 95 00 00 08 00 00 00
402 17:34:03.986437 in-data: 18 20 20 08 00 00 00 00
403 17:34:03.986525 Phase 1
404 17:34:03.989966 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 17:34:03.997559 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 17:34:04.005210 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 17:34:04.005316 Recovery requested (1009000e)
408 17:34:04.015847 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 17:34:04.020388 tlcl_extend: response is 0
410 17:34:04.029946 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 17:34:04.035575 tlcl_extend: response is 0
412 17:34:04.042520 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 17:34:04.062610 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 17:34:04.069215 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 17:34:04.069312
416 17:34:04.069380
417 17:34:04.079489 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 17:34:04.082435 ARM64: Exception handlers installed.
419 17:34:04.085867 ARM64: Testing exception
420 17:34:04.085970 ARM64: Done test exception
421 17:34:04.107931 pmic_efuse_setting: Set efuses in 11 msecs
422 17:34:04.111322 pmwrap_interface_init: Select PMIF_VLD_RDY
423 17:34:04.118263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 17:34:04.121719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 17:34:04.128934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 17:34:04.132827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 17:34:04.136412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 17:34:04.139776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 17:34:04.147499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 17:34:04.151544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 17:34:04.155501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 17:34:04.158988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 17:34:04.166042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 17:34:04.169513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 17:34:04.172911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 17:34:04.180636 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 17:34:04.187509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 17:34:04.191703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 17:34:04.198824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 17:34:04.203478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 17:34:04.209962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 17:34:04.214073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 17:34:04.221102 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 17:34:04.224688 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 17:34:04.232531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 17:34:04.235815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 17:34:04.240374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 17:34:04.247912 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 17:34:04.251364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 17:34:04.258899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 17:34:04.262462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 17:34:04.265856 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 17:34:04.273477 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 17:34:04.276957 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 17:34:04.281046 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 17:34:04.287915 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 17:34:04.292173 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 17:34:04.295803 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 17:34:04.303048 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 17:34:04.307153 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 17:34:04.310787 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 17:34:04.314182 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 17:34:04.321509 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 17:34:04.325062 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 17:34:04.329157 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 17:34:04.332832 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 17:34:04.336849 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 17:34:04.343781 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 17:34:04.347891 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 17:34:04.351172 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 17:34:04.355144 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 17:34:04.358674 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 17:34:04.362023 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 17:34:04.369925 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 17:34:04.381024 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 17:34:04.385423 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 17:34:04.392176 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 17:34:04.399185 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 17:34:04.406730 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 17:34:04.410871 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 17:34:04.414396 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 17:34:04.422180 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x34
483 17:34:04.425028 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 17:34:04.433356 [RTC]rtc_osc_init,62: osc32con val = 0xde71
485 17:34:04.436801 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 17:34:04.446103 [RTC]rtc_get_frequency_meter,154: input=15, output=759
487 17:34:04.455252 [RTC]rtc_get_frequency_meter,154: input=23, output=940
488 17:34:04.464586 [RTC]rtc_get_frequency_meter,154: input=19, output=848
489 17:34:04.474106 [RTC]rtc_get_frequency_meter,154: input=17, output=802
490 17:34:04.483914 [RTC]rtc_get_frequency_meter,154: input=16, output=780
491 17:34:04.493043 [RTC]rtc_get_frequency_meter,154: input=16, output=782
492 17:34:04.503476 [RTC]rtc_get_frequency_meter,154: input=17, output=805
493 17:34:04.506910 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 17:34:04.510971 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 17:34:04.514487 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 17:34:04.521979 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 17:34:04.526165 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 17:34:04.529634 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 17:34:04.529717 ADC[4]: Raw value=905834 ID=7
500 17:34:04.533257 ADC[3]: Raw value=213441 ID=1
501 17:34:04.536544 RAM Code: 0x71
502 17:34:04.540675 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 17:34:04.543987 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 17:34:04.555323 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 17:34:04.559343 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 17:34:04.562639 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 17:34:04.566849 in-header: 03 07 00 00 08 00 00 00
508 17:34:04.570389 in-data: aa e4 47 04 13 02 00 00
509 17:34:04.573833 Chrome EC: UHEPI supported
510 17:34:04.581160 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 17:34:04.584800 in-header: 03 95 00 00 08 00 00 00
512 17:34:04.588581 in-data: 18 20 20 08 00 00 00 00
513 17:34:04.588665 MRC: failed to locate region type 0.
514 17:34:04.595860 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 17:34:04.599408 DRAM-K: Running full calibration
516 17:34:04.606945 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 17:34:04.607030 header.status = 0x0
518 17:34:04.610336 header.version = 0x6 (expected: 0x6)
519 17:34:04.614175 header.size = 0xd00 (expected: 0xd00)
520 17:34:04.618116 header.flags = 0x0
521 17:34:04.621579 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 17:34:04.640328 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
523 17:34:04.648534 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 17:34:04.648619 dram_init: ddr_geometry: 2
525 17:34:04.651978 [EMI] MDL number = 2
526 17:34:04.655509 [EMI] Get MDL freq = 0
527 17:34:04.655617 dram_init: ddr_type: 0
528 17:34:04.659545 is_discrete_lpddr4: 1
529 17:34:04.659659 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 17:34:04.663128
531 17:34:04.663210
532 17:34:04.663274 [Bian_co] ETT version 0.0.0.1
533 17:34:04.670557 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 17:34:04.670640
535 17:34:04.674744 dramc_set_vcore_voltage set vcore to 650000
536 17:34:04.674827 Read voltage for 800, 4
537 17:34:04.674892 Vio18 = 0
538 17:34:04.678246 Vcore = 650000
539 17:34:04.678328 Vdram = 0
540 17:34:04.678392 Vddq = 0
541 17:34:04.678452 Vmddr = 0
542 17:34:04.681789 dram_init: config_dvfs: 1
543 17:34:04.686528 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 17:34:04.694306 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 17:34:04.697154 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 17:34:04.701332 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 17:34:04.704831 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 17:34:04.707606 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 17:34:04.711004 MEM_TYPE=3, freq_sel=18
550 17:34:04.714811 sv_algorithm_assistance_LP4_1600
551 17:34:04.718732 ============ PULL DRAM RESETB DOWN ============
552 17:34:04.721956 ========== PULL DRAM RESETB DOWN end =========
553 17:34:04.725742 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 17:34:04.729322 ===================================
555 17:34:04.733016 LPDDR4 DRAM CONFIGURATION
556 17:34:04.736733 ===================================
557 17:34:04.736864 EX_ROW_EN[0] = 0x0
558 17:34:04.740059 EX_ROW_EN[1] = 0x0
559 17:34:04.740144 LP4Y_EN = 0x0
560 17:34:04.743306 WORK_FSP = 0x0
561 17:34:04.743391 WL = 0x2
562 17:34:04.746436 RL = 0x2
563 17:34:04.746527 BL = 0x2
564 17:34:04.750303 RPST = 0x0
565 17:34:04.750388 RD_PRE = 0x0
566 17:34:04.753706 WR_PRE = 0x1
567 17:34:04.753791 WR_PST = 0x0
568 17:34:04.756428 DBI_WR = 0x0
569 17:34:04.756512 DBI_RD = 0x0
570 17:34:04.760044 OTF = 0x1
571 17:34:04.763359 ===================================
572 17:34:04.766811 ===================================
573 17:34:04.766894 ANA top config
574 17:34:04.770252 ===================================
575 17:34:04.773574 DLL_ASYNC_EN = 0
576 17:34:04.777083 ALL_SLAVE_EN = 1
577 17:34:04.779923 NEW_RANK_MODE = 1
578 17:34:04.780006 DLL_IDLE_MODE = 1
579 17:34:04.783309 LP45_APHY_COMB_EN = 1
580 17:34:04.786712 TX_ODT_DIS = 1
581 17:34:04.790008 NEW_8X_MODE = 1
582 17:34:04.793361 ===================================
583 17:34:04.797495 ===================================
584 17:34:04.797579 data_rate = 1600
585 17:34:04.801033 CKR = 1
586 17:34:04.804602 DQ_P2S_RATIO = 8
587 17:34:04.807389 ===================================
588 17:34:04.810973 CA_P2S_RATIO = 8
589 17:34:04.814445 DQ_CA_OPEN = 0
590 17:34:04.814527 DQ_SEMI_OPEN = 0
591 17:34:04.817329 CA_SEMI_OPEN = 0
592 17:34:04.820724 CA_FULL_RATE = 0
593 17:34:04.824134 DQ_CKDIV4_EN = 1
594 17:34:04.827555 CA_CKDIV4_EN = 1
595 17:34:04.831009 CA_PREDIV_EN = 0
596 17:34:04.831091 PH8_DLY = 0
597 17:34:04.833902 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 17:34:04.837390 DQ_AAMCK_DIV = 4
599 17:34:04.840943 CA_AAMCK_DIV = 4
600 17:34:04.844254 CA_ADMCK_DIV = 4
601 17:34:04.847540 DQ_TRACK_CA_EN = 0
602 17:34:04.847678 CA_PICK = 800
603 17:34:04.851025 CA_MCKIO = 800
604 17:34:04.854759 MCKIO_SEMI = 0
605 17:34:04.857907 PLL_FREQ = 3068
606 17:34:04.861603 DQ_UI_PI_RATIO = 32
607 17:34:04.861716 CA_UI_PI_RATIO = 0
608 17:34:04.865744 ===================================
609 17:34:04.868634 ===================================
610 17:34:04.872601 memory_type:LPDDR4
611 17:34:04.876192 GP_NUM : 10
612 17:34:04.876276 SRAM_EN : 1
613 17:34:04.879239 MD32_EN : 0
614 17:34:04.883263 ===================================
615 17:34:04.883347 [ANA_INIT] >>>>>>>>>>>>>>
616 17:34:04.886683 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 17:34:04.890272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 17:34:04.893637 ===================================
619 17:34:04.897019 data_rate = 1600,PCW = 0X7600
620 17:34:04.900428 ===================================
621 17:34:04.904043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 17:34:04.907509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 17:34:04.913870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 17:34:04.917320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 17:34:04.920650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 17:34:04.924054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 17:34:04.927399 [ANA_INIT] flow start
628 17:34:04.930963 [ANA_INIT] PLL >>>>>>>>
629 17:34:04.931045 [ANA_INIT] PLL <<<<<<<<
630 17:34:04.934316 [ANA_INIT] MIDPI >>>>>>>>
631 17:34:04.937209 [ANA_INIT] MIDPI <<<<<<<<
632 17:34:04.937292 [ANA_INIT] DLL >>>>>>>>
633 17:34:04.940767 [ANA_INIT] flow end
634 17:34:04.944327 ============ LP4 DIFF to SE enter ============
635 17:34:04.950866 ============ LP4 DIFF to SE exit ============
636 17:34:04.950949 [ANA_INIT] <<<<<<<<<<<<<
637 17:34:04.954142 [Flow] Enable top DCM control >>>>>
638 17:34:04.957575 [Flow] Enable top DCM control <<<<<
639 17:34:04.960570 Enable DLL master slave shuffle
640 17:34:04.967527 ==============================================================
641 17:34:04.967616 Gating Mode config
642 17:34:04.974437 ==============================================================
643 17:34:04.974540 Config description:
644 17:34:04.984517 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 17:34:04.991428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 17:34:04.997547 SELPH_MODE 0: By rank 1: By Phase
647 17:34:05.001122 ==============================================================
648 17:34:05.004581 GAT_TRACK_EN = 1
649 17:34:05.008094 RX_GATING_MODE = 2
650 17:34:05.011336 RX_GATING_TRACK_MODE = 2
651 17:34:05.014383 SELPH_MODE = 1
652 17:34:05.018458 PICG_EARLY_EN = 1
653 17:34:05.021142 VALID_LAT_VALUE = 1
654 17:34:05.028319 ==============================================================
655 17:34:05.031823 Enter into Gating configuration >>>>
656 17:34:05.032273 Exit from Gating configuration <<<<
657 17:34:05.034570 Enter into DVFS_PRE_config >>>>>
658 17:34:05.048331 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 17:34:05.051309 Exit from DVFS_PRE_config <<<<<
660 17:34:05.054707 Enter into PICG configuration >>>>
661 17:34:05.057906 Exit from PICG configuration <<<<
662 17:34:05.058335 [RX_INPUT] configuration >>>>>
663 17:34:05.061371 [RX_INPUT] configuration <<<<<
664 17:34:05.068474 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 17:34:05.071898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 17:34:05.077994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 17:34:05.084879 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 17:34:05.091703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 17:34:05.098439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 17:34:05.101917 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 17:34:05.104681 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 17:34:05.107892 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 17:34:05.115014 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 17:34:05.118162 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 17:34:05.121495 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 17:34:05.124655 ===================================
677 17:34:05.128428 LPDDR4 DRAM CONFIGURATION
678 17:34:05.131571 ===================================
679 17:34:05.135035 EX_ROW_EN[0] = 0x0
680 17:34:05.135459 EX_ROW_EN[1] = 0x0
681 17:34:05.138648 LP4Y_EN = 0x0
682 17:34:05.139074 WORK_FSP = 0x0
683 17:34:05.141598 WL = 0x2
684 17:34:05.142021 RL = 0x2
685 17:34:05.144878 BL = 0x2
686 17:34:05.145539 RPST = 0x0
687 17:34:05.148576 RD_PRE = 0x0
688 17:34:05.149008 WR_PRE = 0x1
689 17:34:05.152108 WR_PST = 0x0
690 17:34:05.152535 DBI_WR = 0x0
691 17:34:05.154778 DBI_RD = 0x0
692 17:34:05.155225 OTF = 0x1
693 17:34:05.158250 ===================================
694 17:34:05.161832 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 17:34:05.168409 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 17:34:05.171911 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 17:34:05.175042 ===================================
698 17:34:05.178543 LPDDR4 DRAM CONFIGURATION
699 17:34:05.181293 ===================================
700 17:34:05.181853 EX_ROW_EN[0] = 0x10
701 17:34:05.184652 EX_ROW_EN[1] = 0x0
702 17:34:05.185141 LP4Y_EN = 0x0
703 17:34:05.188141 WORK_FSP = 0x0
704 17:34:05.188586 WL = 0x2
705 17:34:05.191516 RL = 0x2
706 17:34:05.195105 BL = 0x2
707 17:34:05.195563 RPST = 0x0
708 17:34:05.198433 RD_PRE = 0x0
709 17:34:05.198990 WR_PRE = 0x1
710 17:34:05.201905 WR_PST = 0x0
711 17:34:05.202547 DBI_WR = 0x0
712 17:34:05.204727 DBI_RD = 0x0
713 17:34:05.205287 OTF = 0x1
714 17:34:05.208373 ===================================
715 17:34:05.214518 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 17:34:05.218481 nWR fixed to 40
717 17:34:05.221918 [ModeRegInit_LP4] CH0 RK0
718 17:34:05.222398 [ModeRegInit_LP4] CH0 RK1
719 17:34:05.225360 [ModeRegInit_LP4] CH1 RK0
720 17:34:05.228893 [ModeRegInit_LP4] CH1 RK1
721 17:34:05.229319 match AC timing 13
722 17:34:05.235791 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 17:34:05.239075 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 17:34:05.242099 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 17:34:05.248901 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 17:34:05.252157 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 17:34:05.252607 [EMI DOE] emi_dcm 0
728 17:34:05.258978 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 17:34:05.259405 ==
730 17:34:05.261924 Dram Type= 6, Freq= 0, CH_0, rank 0
731 17:34:05.265319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 17:34:05.265829 ==
733 17:34:05.272499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 17:34:05.275374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 17:34:05.286012 [CA 0] Center 36 (6~67) winsize 62
736 17:34:05.289401 [CA 1] Center 36 (6~67) winsize 62
737 17:34:05.292953 [CA 2] Center 34 (4~65) winsize 62
738 17:34:05.296465 [CA 3] Center 34 (4~64) winsize 61
739 17:34:05.300077 [CA 4] Center 33 (3~64) winsize 62
740 17:34:05.303506 [CA 5] Center 32 (2~62) winsize 61
741 17:34:05.304112
742 17:34:05.306291 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 17:34:05.306853
744 17:34:05.309722 [CATrainingPosCal] consider 1 rank data
745 17:34:05.313224 u2DelayCellTimex100 = 270/100 ps
746 17:34:05.316830 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 17:34:05.319594 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 17:34:05.323273 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 17:34:05.329950 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
750 17:34:05.333378 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
751 17:34:05.336926 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
752 17:34:05.337494
753 17:34:05.340261 CA PerBit enable=1, Macro0, CA PI delay=32
754 17:34:05.340841
755 17:34:05.343811 [CBTSetCACLKResult] CA Dly = 32
756 17:34:05.344294 CS Dly: 5 (0~36)
757 17:34:05.344802 ==
758 17:34:05.346623 Dram Type= 6, Freq= 0, CH_0, rank 1
759 17:34:05.353616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 17:34:05.354123 ==
761 17:34:05.357062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 17:34:05.363199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 17:34:05.372736 [CA 0] Center 36 (6~67) winsize 62
764 17:34:05.375993 [CA 1] Center 36 (6~67) winsize 62
765 17:34:05.379276 [CA 2] Center 34 (4~65) winsize 62
766 17:34:05.382538 [CA 3] Center 33 (3~64) winsize 62
767 17:34:05.385784 [CA 4] Center 32 (2~63) winsize 62
768 17:34:05.389116 [CA 5] Center 32 (2~63) winsize 62
769 17:34:05.389709
770 17:34:05.392533 [CmdBusTrainingLP45] Vref(ca) range 1: 30
771 17:34:05.393032
772 17:34:05.395495 [CATrainingPosCal] consider 2 rank data
773 17:34:05.398825 u2DelayCellTimex100 = 270/100 ps
774 17:34:05.402158 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 17:34:05.405885 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 17:34:05.412145 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 17:34:05.415434 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
778 17:34:05.419122 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
779 17:34:05.422117 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
780 17:34:05.422933
781 17:34:05.425564 CA PerBit enable=1, Macro0, CA PI delay=32
782 17:34:05.426300
783 17:34:05.429187 [CBTSetCACLKResult] CA Dly = 32
784 17:34:05.429690 CS Dly: 5 (0~37)
785 17:34:05.431958
786 17:34:05.436077 ----->DramcWriteLeveling(PI) begin...
787 17:34:05.436776 ==
788 17:34:05.437398 Dram Type= 6, Freq= 0, CH_0, rank 0
789 17:34:05.443500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 17:34:05.443986 ==
791 17:34:05.444291 Write leveling (Byte 0): 30 => 30
792 17:34:05.447734 Write leveling (Byte 1): 30 => 30
793 17:34:05.451295 DramcWriteLeveling(PI) end<-----
794 17:34:05.451665
795 17:34:05.451928 ==
796 17:34:05.454806 Dram Type= 6, Freq= 0, CH_0, rank 0
797 17:34:05.458160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 17:34:05.458647 ==
799 17:34:05.461564 [Gating] SW mode calibration
800 17:34:05.468921 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 17:34:05.475308 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 17:34:05.478773 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 17:34:05.481680 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 17:34:05.488487 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 17:34:05.491814 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 17:34:05.495737 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 17:34:05.499227 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 17:34:05.505257 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 17:34:05.508659 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 17:34:05.512127 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 17:34:05.518655 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 17:34:05.522263 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 17:34:05.525262 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 17:34:05.532043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 17:34:05.535542 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 17:34:05.538927 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 17:34:05.545605 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 17:34:05.549140 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 17:34:05.552367 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 17:34:05.555910 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
821 17:34:05.562167 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 17:34:05.565401 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 17:34:05.568906 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 17:34:05.575977 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 17:34:05.578744 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 17:34:05.582115 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 17:34:05.588894 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 17:34:05.592550 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
829 17:34:05.595951 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
830 17:34:05.602490 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 17:34:05.605582 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 17:34:05.608972 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 17:34:05.615952 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 17:34:05.619581 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 17:34:05.622394 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
836 17:34:05.629414 0 10 8 | B1->B0 | 3333 2828 | 0 0 | (0 0) (0 0)
837 17:34:05.632863 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 17:34:05.636132 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 17:34:05.639255 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 17:34:05.646410 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 17:34:05.650014 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 17:34:05.653283 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 17:34:05.659612 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
844 17:34:05.663178 0 11 8 | B1->B0 | 2b2b 3d3d | 0 0 | (1 1) (0 0)
845 17:34:05.665940 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
846 17:34:05.672755 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 17:34:05.676230 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 17:34:05.679715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 17:34:05.686450 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 17:34:05.689951 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 17:34:05.692620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 17:34:05.696123 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 17:34:05.702968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 17:34:05.706327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 17:34:05.709355 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 17:34:05.716269 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 17:34:05.719840 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 17:34:05.723318 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 17:34:05.729776 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 17:34:05.733330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 17:34:05.736768 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 17:34:05.742993 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 17:34:05.746254 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 17:34:05.749555 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 17:34:05.756277 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 17:34:05.759631 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 17:34:05.762972 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 17:34:05.770190 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
869 17:34:05.770512 Total UI for P1: 0, mck2ui 16
870 17:34:05.773082 best dqsien dly found for B0: ( 0, 14, 4)
871 17:34:05.779760 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
872 17:34:05.783409 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 17:34:05.786831 Total UI for P1: 0, mck2ui 16
874 17:34:05.790082 best dqsien dly found for B1: ( 0, 14, 12)
875 17:34:05.793744 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
876 17:34:05.797158 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
877 17:34:05.797524
878 17:34:05.800811 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
879 17:34:05.804051 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
880 17:34:05.807595 [Gating] SW calibration Done
881 17:34:05.808008 ==
882 17:34:05.810476 Dram Type= 6, Freq= 0, CH_0, rank 0
883 17:34:05.813931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 17:34:05.814354 ==
885 17:34:05.817366 RX Vref Scan: 0
886 17:34:05.817779
887 17:34:05.820530 RX Vref 0 -> 0, step: 1
888 17:34:05.820893
889 17:34:05.821244 RX Delay -130 -> 252, step: 16
890 17:34:05.827455 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
891 17:34:05.830962 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
892 17:34:05.834545 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
893 17:34:05.837245 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
894 17:34:05.840630 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
895 17:34:05.847874 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
896 17:34:05.851099 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
897 17:34:05.854426 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
898 17:34:05.857801 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
899 17:34:05.861294 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
900 17:34:05.867396 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
901 17:34:05.870944 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
902 17:34:05.874261 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
903 17:34:05.877556 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
904 17:34:05.881359 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
905 17:34:05.887934 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
906 17:34:05.888627 ==
907 17:34:05.891065 Dram Type= 6, Freq= 0, CH_0, rank 0
908 17:34:05.894050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 17:34:05.894502 ==
910 17:34:05.894914 DQS Delay:
911 17:34:05.897869 DQS0 = 0, DQS1 = 0
912 17:34:05.898215 DQM Delay:
913 17:34:05.900932 DQM0 = 89, DQM1 = 80
914 17:34:05.901265 DQ Delay:
915 17:34:05.904545 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
916 17:34:05.907383 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
917 17:34:05.910684 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
918 17:34:05.914107 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
919 17:34:05.914364
920 17:34:05.914598
921 17:34:05.914802 ==
922 17:34:05.917604 Dram Type= 6, Freq= 0, CH_0, rank 0
923 17:34:05.920945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 17:34:05.921200 ==
925 17:34:05.921417
926 17:34:05.921625
927 17:34:05.924425 TX Vref Scan disable
928 17:34:05.927920 == TX Byte 0 ==
929 17:34:05.931226 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
930 17:34:05.934526 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
931 17:34:05.937417 == TX Byte 1 ==
932 17:34:05.940889 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
933 17:34:05.944262 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
934 17:34:05.944538 ==
935 17:34:05.947840 Dram Type= 6, Freq= 0, CH_0, rank 0
936 17:34:05.951181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 17:34:05.954031 ==
938 17:34:05.965455 TX Vref=22, minBit 8, minWin=27, winSum=446
939 17:34:05.968647 TX Vref=24, minBit 9, minWin=27, winSum=450
940 17:34:05.972065 TX Vref=26, minBit 0, minWin=28, winSum=455
941 17:34:05.975709 TX Vref=28, minBit 8, minWin=28, winSum=460
942 17:34:05.979253 TX Vref=30, minBit 8, minWin=28, winSum=456
943 17:34:05.982468 TX Vref=32, minBit 12, minWin=27, winSum=456
944 17:34:05.989262 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
945 17:34:05.989518
946 17:34:05.991959 Final TX Range 1 Vref 28
947 17:34:05.992162
948 17:34:05.992347 ==
949 17:34:05.995370 Dram Type= 6, Freq= 0, CH_0, rank 0
950 17:34:05.998745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 17:34:05.998985 ==
952 17:34:05.999182
953 17:34:06.002164
954 17:34:06.002415 TX Vref Scan disable
955 17:34:06.005367 == TX Byte 0 ==
956 17:34:06.008571 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
957 17:34:06.011879 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
958 17:34:06.015163 == TX Byte 1 ==
959 17:34:06.018731 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
960 17:34:06.022086 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
961 17:34:06.025263
962 17:34:06.025421 [DATLAT]
963 17:34:06.025526 Freq=800, CH0 RK0
964 17:34:06.025632
965 17:34:06.028892 DATLAT Default: 0xa
966 17:34:06.029051 0, 0xFFFF, sum = 0
967 17:34:06.031683 1, 0xFFFF, sum = 0
968 17:34:06.031807 2, 0xFFFF, sum = 0
969 17:34:06.035190 3, 0xFFFF, sum = 0
970 17:34:06.035332 4, 0xFFFF, sum = 0
971 17:34:06.038681 5, 0xFFFF, sum = 0
972 17:34:06.038820 6, 0xFFFF, sum = 0
973 17:34:06.042300 7, 0xFFFF, sum = 0
974 17:34:06.045172 8, 0xFFFF, sum = 0
975 17:34:06.045304 9, 0x0, sum = 1
976 17:34:06.045399 10, 0x0, sum = 2
977 17:34:06.048627 11, 0x0, sum = 3
978 17:34:06.048750 12, 0x0, sum = 4
979 17:34:06.052214 best_step = 10
980 17:34:06.052323
981 17:34:06.052417 ==
982 17:34:06.055150 Dram Type= 6, Freq= 0, CH_0, rank 0
983 17:34:06.058605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 17:34:06.058713 ==
985 17:34:06.062157 RX Vref Scan: 1
986 17:34:06.062246
987 17:34:06.062310 Set Vref Range= 32 -> 127
988 17:34:06.062370
989 17:34:06.065752 RX Vref 32 -> 127, step: 1
990 17:34:06.065830
991 17:34:06.068571 RX Delay -95 -> 252, step: 8
992 17:34:06.068642
993 17:34:06.072098 Set Vref, RX VrefLevel [Byte0]: 32
994 17:34:06.075366 [Byte1]: 32
995 17:34:06.075465
996 17:34:06.078807 Set Vref, RX VrefLevel [Byte0]: 33
997 17:34:06.082324 [Byte1]: 33
998 17:34:06.085711
999 17:34:06.085815 Set Vref, RX VrefLevel [Byte0]: 34
1000 17:34:06.089232 [Byte1]: 34
1001 17:34:06.093415
1002 17:34:06.093526 Set Vref, RX VrefLevel [Byte0]: 35
1003 17:34:06.096198 [Byte1]: 35
1004 17:34:06.101053
1005 17:34:06.101167 Set Vref, RX VrefLevel [Byte0]: 36
1006 17:34:06.104665 [Byte1]: 36
1007 17:34:06.108877
1008 17:34:06.108962 Set Vref, RX VrefLevel [Byte0]: 37
1009 17:34:06.111773 [Byte1]: 37
1010 17:34:06.116649
1011 17:34:06.116738 Set Vref, RX VrefLevel [Byte0]: 38
1012 17:34:06.119517 [Byte1]: 38
1013 17:34:06.124351
1014 17:34:06.124460 Set Vref, RX VrefLevel [Byte0]: 39
1015 17:34:06.127672 [Byte1]: 39
1016 17:34:06.131103
1017 17:34:06.131187 Set Vref, RX VrefLevel [Byte0]: 40
1018 17:34:06.135024 [Byte1]: 40
1019 17:34:06.139066
1020 17:34:06.139150 Set Vref, RX VrefLevel [Byte0]: 41
1021 17:34:06.142583 [Byte1]: 41
1022 17:34:06.146736
1023 17:34:06.146832 Set Vref, RX VrefLevel [Byte0]: 42
1024 17:34:06.149548 [Byte1]: 42
1025 17:34:06.153797
1026 17:34:06.153878 Set Vref, RX VrefLevel [Byte0]: 43
1027 17:34:06.157375 [Byte1]: 43
1028 17:34:06.161577
1029 17:34:06.161659 Set Vref, RX VrefLevel [Byte0]: 44
1030 17:34:06.165042 [Byte1]: 44
1031 17:34:06.169273
1032 17:34:06.169355 Set Vref, RX VrefLevel [Byte0]: 45
1033 17:34:06.172316 [Byte1]: 45
1034 17:34:06.177095
1035 17:34:06.177175 Set Vref, RX VrefLevel [Byte0]: 46
1036 17:34:06.179850 [Byte1]: 46
1037 17:34:06.184532
1038 17:34:06.184613 Set Vref, RX VrefLevel [Byte0]: 47
1039 17:34:06.187849 [Byte1]: 47
1040 17:34:06.191980
1041 17:34:06.192062 Set Vref, RX VrefLevel [Byte0]: 48
1042 17:34:06.195524 [Byte1]: 48
1043 17:34:06.199665
1044 17:34:06.199767 Set Vref, RX VrefLevel [Byte0]: 49
1045 17:34:06.203310 [Byte1]: 49
1046 17:34:06.207419
1047 17:34:06.207524 Set Vref, RX VrefLevel [Byte0]: 50
1048 17:34:06.210307 [Byte1]: 50
1049 17:34:06.215157
1050 17:34:06.215238 Set Vref, RX VrefLevel [Byte0]: 51
1051 17:34:06.217949 [Byte1]: 51
1052 17:34:06.222571
1053 17:34:06.222647 Set Vref, RX VrefLevel [Byte0]: 52
1054 17:34:06.226151 [Byte1]: 52
1055 17:34:06.230238
1056 17:34:06.230355 Set Vref, RX VrefLevel [Byte0]: 53
1057 17:34:06.233091 [Byte1]: 53
1058 17:34:06.237847
1059 17:34:06.237939 Set Vref, RX VrefLevel [Byte0]: 54
1060 17:34:06.241106 [Byte1]: 54
1061 17:34:06.245118
1062 17:34:06.245190 Set Vref, RX VrefLevel [Byte0]: 55
1063 17:34:06.248265 [Byte1]: 55
1064 17:34:06.253096
1065 17:34:06.253174 Set Vref, RX VrefLevel [Byte0]: 56
1066 17:34:06.255723 [Byte1]: 56
1067 17:34:06.260315
1068 17:34:06.260393 Set Vref, RX VrefLevel [Byte0]: 57
1069 17:34:06.263863 [Byte1]: 57
1070 17:34:06.268208
1071 17:34:06.268282 Set Vref, RX VrefLevel [Byte0]: 58
1072 17:34:06.271074 [Byte1]: 58
1073 17:34:06.275343
1074 17:34:06.275415 Set Vref, RX VrefLevel [Byte0]: 59
1075 17:34:06.278870 [Byte1]: 59
1076 17:34:06.283202
1077 17:34:06.283307 Set Vref, RX VrefLevel [Byte0]: 60
1078 17:34:06.286788 [Byte1]: 60
1079 17:34:06.290853
1080 17:34:06.291012 Set Vref, RX VrefLevel [Byte0]: 61
1081 17:34:06.294305 [Byte1]: 61
1082 17:34:06.298811
1083 17:34:06.298954 Set Vref, RX VrefLevel [Byte0]: 62
1084 17:34:06.301441 [Byte1]: 62
1085 17:34:06.306476
1086 17:34:06.306604 Set Vref, RX VrefLevel [Byte0]: 63
1087 17:34:06.309320 [Byte1]: 63
1088 17:34:06.313511
1089 17:34:06.313633 Set Vref, RX VrefLevel [Byte0]: 64
1090 17:34:06.317077 [Byte1]: 64
1091 17:34:06.320843
1092 17:34:06.320949 Set Vref, RX VrefLevel [Byte0]: 65
1093 17:34:06.324334 [Byte1]: 65
1094 17:34:06.329200
1095 17:34:06.329296 Set Vref, RX VrefLevel [Byte0]: 66
1096 17:34:06.331886 [Byte1]: 66
1097 17:34:06.336520
1098 17:34:06.336636 Set Vref, RX VrefLevel [Byte0]: 67
1099 17:34:06.339432 [Byte1]: 67
1100 17:34:06.343754
1101 17:34:06.343856 Set Vref, RX VrefLevel [Byte0]: 68
1102 17:34:06.347087 [Byte1]: 68
1103 17:34:06.351457
1104 17:34:06.351584 Set Vref, RX VrefLevel [Byte0]: 69
1105 17:34:06.355025 [Byte1]: 69
1106 17:34:06.358990
1107 17:34:06.359111 Set Vref, RX VrefLevel [Byte0]: 70
1108 17:34:06.362146 [Byte1]: 70
1109 17:34:06.366643
1110 17:34:06.366731 Set Vref, RX VrefLevel [Byte0]: 71
1111 17:34:06.370547 [Byte1]: 71
1112 17:34:06.374215
1113 17:34:06.374297 Set Vref, RX VrefLevel [Byte0]: 72
1114 17:34:06.377765 [Byte1]: 72
1115 17:34:06.382041
1116 17:34:06.382125 Set Vref, RX VrefLevel [Byte0]: 73
1117 17:34:06.385539 [Byte1]: 73
1118 17:34:06.389804
1119 17:34:06.389916 Set Vref, RX VrefLevel [Byte0]: 74
1120 17:34:06.393307 [Byte1]: 74
1121 17:34:06.397548
1122 17:34:06.397650 Set Vref, RX VrefLevel [Byte0]: 75
1123 17:34:06.400274 [Byte1]: 75
1124 17:34:06.404943
1125 17:34:06.405047 Set Vref, RX VrefLevel [Byte0]: 76
1126 17:34:06.408259 [Byte1]: 76
1127 17:34:06.412909
1128 17:34:06.412997 Set Vref, RX VrefLevel [Byte0]: 77
1129 17:34:06.415527 [Byte1]: 77
1130 17:34:06.419749
1131 17:34:06.419832 Set Vref, RX VrefLevel [Byte0]: 78
1132 17:34:06.423439 [Byte1]: 78
1133 17:34:06.427873
1134 17:34:06.427961 Set Vref, RX VrefLevel [Byte0]: 79
1135 17:34:06.430618 [Byte1]: 79
1136 17:34:06.435525
1137 17:34:06.435607 Final RX Vref Byte 0 = 56 to rank0
1138 17:34:06.438904 Final RX Vref Byte 1 = 64 to rank0
1139 17:34:06.441600 Final RX Vref Byte 0 = 56 to rank1
1140 17:34:06.445088 Final RX Vref Byte 1 = 64 to rank1==
1141 17:34:06.448474 Dram Type= 6, Freq= 0, CH_0, rank 0
1142 17:34:06.455067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 17:34:06.455152 ==
1144 17:34:06.455217 DQS Delay:
1145 17:34:06.455277 DQS0 = 0, DQS1 = 0
1146 17:34:06.458669 DQM Delay:
1147 17:34:06.458752 DQM0 = 92, DQM1 = 86
1148 17:34:06.462238 DQ Delay:
1149 17:34:06.465064 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1150 17:34:06.465147 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1151 17:34:06.468763 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1152 17:34:06.475391 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1153 17:34:06.475473
1154 17:34:06.475537
1155 17:34:06.482236 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1156 17:34:06.484997 CH0 RK0: MR19=606, MR18=493F
1157 17:34:06.492186 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1158 17:34:06.492262
1159 17:34:06.495081 ----->DramcWriteLeveling(PI) begin...
1160 17:34:06.495151 ==
1161 17:34:06.498537 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 17:34:06.502158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 17:34:06.502240 ==
1164 17:34:06.505650 Write leveling (Byte 0): 33 => 33
1165 17:34:06.549771 Write leveling (Byte 1): 27 => 27
1166 17:34:06.549894 DramcWriteLeveling(PI) end<-----
1167 17:34:06.549975
1168 17:34:06.550057 ==
1169 17:34:06.550334 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 17:34:06.550416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1171 17:34:06.550489 ==
1172 17:34:06.550560 [Gating] SW mode calibration
1173 17:34:06.550630 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1174 17:34:06.550700 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1175 17:34:06.550769 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1176 17:34:06.550836 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1177 17:34:06.550929 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1178 17:34:06.594049 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 17:34:06.594607 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 17:34:06.595135 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 17:34:06.595921 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 17:34:06.596325 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 17:34:06.596708 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 17:34:06.597164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 17:34:06.597628 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 17:34:06.597945 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 17:34:06.598217 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 17:34:06.605315 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 17:34:06.605710 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 17:34:06.606327 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 17:34:06.608908 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 17:34:06.615339 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1193 17:34:06.618230 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1194 17:34:06.621792 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 17:34:06.628186 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 17:34:06.631576 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 17:34:06.635404 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 17:34:06.638733 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 17:34:06.645051 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 17:34:06.648539 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 17:34:06.651340 0 9 8 | B1->B0 | 2c2c 2a2a | 1 1 | (0 0) (1 1)
1202 17:34:06.658295 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 17:34:06.661789 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 17:34:06.664579 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 17:34:06.671531 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 17:34:06.674714 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 17:34:06.678217 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 17:34:06.685261 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1209 17:34:06.688728 0 10 8 | B1->B0 | 2929 2b2b | 0 1 | (1 0) (1 1)
1210 17:34:06.692879 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1211 17:34:06.696295 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 17:34:06.702884 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 17:34:06.706006 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 17:34:06.710430 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 17:34:06.713803 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 17:34:06.720300 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1217 17:34:06.723652 0 11 8 | B1->B0 | 3f3f 3838 | 0 0 | (0 0) (0 0)
1218 17:34:06.726884 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 17:34:06.733264 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 17:34:06.736648 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 17:34:06.740070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 17:34:06.746507 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 17:34:06.749869 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 17:34:06.753461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 17:34:06.760347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1226 17:34:06.763231 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 17:34:06.766725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 17:34:06.770208 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 17:34:06.776828 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 17:34:06.780349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 17:34:06.783758 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 17:34:06.790431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 17:34:06.794010 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 17:34:06.796722 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 17:34:06.803804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 17:34:06.807283 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 17:34:06.810062 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 17:34:06.817329 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 17:34:06.820495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 17:34:06.823550 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 17:34:06.830055 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 17:34:06.833721 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1243 17:34:06.837038 Total UI for P1: 0, mck2ui 16
1244 17:34:06.840529 best dqsien dly found for B0: ( 0, 14, 10)
1245 17:34:06.843339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 17:34:06.846716 Total UI for P1: 0, mck2ui 16
1247 17:34:06.850140 best dqsien dly found for B1: ( 0, 14, 12)
1248 17:34:06.853477 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1249 17:34:06.856779 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1250 17:34:06.856865
1251 17:34:06.859996 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1252 17:34:06.866812 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1253 17:34:06.866940 [Gating] SW calibration Done
1254 17:34:06.867041 ==
1255 17:34:06.870354 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 17:34:06.876974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 17:34:06.877097 ==
1258 17:34:06.877209 RX Vref Scan: 0
1259 17:34:06.877304
1260 17:34:06.880478 RX Vref 0 -> 0, step: 1
1261 17:34:06.880582
1262 17:34:06.883996 RX Delay -130 -> 252, step: 16
1263 17:34:06.886686 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1264 17:34:06.890119 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1265 17:34:06.894036 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1266 17:34:06.897359 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1267 17:34:06.903621 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1268 17:34:06.907198 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1269 17:34:06.910691 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1270 17:34:06.913552 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1271 17:34:06.916966 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1272 17:34:06.923901 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1273 17:34:06.927168 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1274 17:34:06.930549 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1275 17:34:06.933879 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1276 17:34:06.937266 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1277 17:34:06.944215 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1278 17:34:06.947460 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1279 17:34:06.947605 ==
1280 17:34:06.950856 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 17:34:06.954247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 17:34:06.954402 ==
1283 17:34:06.957826 DQS Delay:
1284 17:34:06.957999 DQS0 = 0, DQS1 = 0
1285 17:34:06.958112 DQM Delay:
1286 17:34:06.960418 DQM0 = 92, DQM1 = 83
1287 17:34:06.960543 DQ Delay:
1288 17:34:06.963736 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1289 17:34:06.967563 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1290 17:34:06.970867 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1291 17:34:06.974002 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1292 17:34:06.974142
1293 17:34:06.974237
1294 17:34:06.974331 ==
1295 17:34:06.977426 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 17:34:06.983720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 17:34:06.983807 ==
1298 17:34:06.983908
1299 17:34:06.983999
1300 17:34:06.984061 TX Vref Scan disable
1301 17:34:06.987335 == TX Byte 0 ==
1302 17:34:06.990669 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1303 17:34:06.997667 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1304 17:34:06.997781 == TX Byte 1 ==
1305 17:34:07.001020 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1306 17:34:07.004134 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1307 17:34:07.007477 ==
1308 17:34:07.011014 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 17:34:07.013748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 17:34:07.013866 ==
1311 17:34:07.027602 TX Vref=22, minBit 11, minWin=27, winSum=450
1312 17:34:07.031201 TX Vref=24, minBit 11, minWin=27, winSum=454
1313 17:34:07.034572 TX Vref=26, minBit 11, minWin=27, winSum=454
1314 17:34:07.037332 TX Vref=28, minBit 5, minWin=28, winSum=458
1315 17:34:07.040800 TX Vref=30, minBit 7, minWin=28, winSum=458
1316 17:34:07.044368 TX Vref=32, minBit 7, minWin=28, winSum=458
1317 17:34:07.050789 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28
1318 17:34:07.050874
1319 17:34:07.054324 Final TX Range 1 Vref 28
1320 17:34:07.054405
1321 17:34:07.054467 ==
1322 17:34:07.057533 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 17:34:07.060753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 17:34:07.060832 ==
1325 17:34:07.060893
1326 17:34:07.060949
1327 17:34:07.064078 TX Vref Scan disable
1328 17:34:07.067496 == TX Byte 0 ==
1329 17:34:07.070922 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1330 17:34:07.077794 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1331 17:34:07.077889 == TX Byte 1 ==
1332 17:34:07.081261 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1333 17:34:07.083999 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1334 17:34:07.087907
1335 17:34:07.087989 [DATLAT]
1336 17:34:07.088052 Freq=800, CH0 RK1
1337 17:34:07.088112
1338 17:34:07.091036 DATLAT Default: 0xa
1339 17:34:07.091133 0, 0xFFFF, sum = 0
1340 17:34:07.094270 1, 0xFFFF, sum = 0
1341 17:34:07.094344 2, 0xFFFF, sum = 0
1342 17:34:07.097503 3, 0xFFFF, sum = 0
1343 17:34:07.097575 4, 0xFFFF, sum = 0
1344 17:34:07.101022 5, 0xFFFF, sum = 0
1345 17:34:07.101107 6, 0xFFFF, sum = 0
1346 17:34:07.104389 7, 0xFFFF, sum = 0
1347 17:34:07.107392 8, 0xFFFF, sum = 0
1348 17:34:07.107477 9, 0x0, sum = 1
1349 17:34:07.107587 10, 0x0, sum = 2
1350 17:34:07.111200 11, 0x0, sum = 3
1351 17:34:07.111309 12, 0x0, sum = 4
1352 17:34:07.114437 best_step = 10
1353 17:34:07.114535
1354 17:34:07.114598 ==
1355 17:34:07.117992 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 17:34:07.120741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 17:34:07.120813 ==
1358 17:34:07.124227 RX Vref Scan: 0
1359 17:34:07.124302
1360 17:34:07.124361 RX Vref 0 -> 0, step: 1
1361 17:34:07.124417
1362 17:34:07.127735 RX Delay -79 -> 252, step: 8
1363 17:34:07.134585 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1364 17:34:07.137467 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1365 17:34:07.140790 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1366 17:34:07.144360 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1367 17:34:07.148000 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1368 17:34:07.154309 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1369 17:34:07.157706 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1370 17:34:07.161044 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1371 17:34:07.164272 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1372 17:34:07.167970 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1373 17:34:07.171204 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1374 17:34:07.177476 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1375 17:34:07.181209 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1376 17:34:07.184376 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1377 17:34:07.187564 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1378 17:34:07.194464 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1379 17:34:07.194546 ==
1380 17:34:07.197922 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 17:34:07.201250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 17:34:07.201346 ==
1383 17:34:07.201415 DQS Delay:
1384 17:34:07.204425 DQS0 = 0, DQS1 = 0
1385 17:34:07.204503 DQM Delay:
1386 17:34:07.207877 DQM0 = 93, DQM1 = 83
1387 17:34:07.207963 DQ Delay:
1388 17:34:07.211512 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1389 17:34:07.214215 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1390 17:34:07.218080 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1391 17:34:07.221411 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
1392 17:34:07.221495
1393 17:34:07.221559
1394 17:34:07.227933 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
1395 17:34:07.231535 CH0 RK1: MR19=606, MR18=3E0F
1396 17:34:07.237849 CH0_RK1: MR19=0x606, MR18=0x3E0F, DQSOSC=394, MR23=63, INC=95, DEC=63
1397 17:34:07.241323 [RxdqsGatingPostProcess] freq 800
1398 17:34:07.248263 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1399 17:34:07.248344 Pre-setting of DQS Precalculation
1400 17:34:07.254498 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1401 17:34:07.254573 ==
1402 17:34:07.258026 Dram Type= 6, Freq= 0, CH_1, rank 0
1403 17:34:07.261653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 17:34:07.261731 ==
1405 17:34:07.267768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 17:34:07.274986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 17:34:07.282764 [CA 0] Center 36 (6~67) winsize 62
1408 17:34:07.286073 [CA 1] Center 37 (6~68) winsize 63
1409 17:34:07.289478 [CA 2] Center 35 (5~66) winsize 62
1410 17:34:07.292812 [CA 3] Center 34 (4~65) winsize 62
1411 17:34:07.295904 [CA 4] Center 35 (5~65) winsize 61
1412 17:34:07.299037 [CA 5] Center 34 (4~64) winsize 61
1413 17:34:07.299141
1414 17:34:07.302195 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 17:34:07.302290
1416 17:34:07.305974 [CATrainingPosCal] consider 1 rank data
1417 17:34:07.309161 u2DelayCellTimex100 = 270/100 ps
1418 17:34:07.312876 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 17:34:07.316112 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1420 17:34:07.322469 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1421 17:34:07.325786 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 17:34:07.329090 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1423 17:34:07.332892 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 17:34:07.332983
1425 17:34:07.336290 CA PerBit enable=1, Macro0, CA PI delay=34
1426 17:34:07.336376
1427 17:34:07.339046 [CBTSetCACLKResult] CA Dly = 34
1428 17:34:07.339131 CS Dly: 7 (0~38)
1429 17:34:07.339232 ==
1430 17:34:07.343065 Dram Type= 6, Freq= 0, CH_1, rank 1
1431 17:34:07.346697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 17:34:07.350095 ==
1433 17:34:07.354287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1434 17:34:07.361297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1435 17:34:07.369680 [CA 0] Center 36 (6~67) winsize 62
1436 17:34:07.373234 [CA 1] Center 37 (6~68) winsize 63
1437 17:34:07.377489 [CA 2] Center 35 (5~66) winsize 62
1438 17:34:07.380405 [CA 3] Center 34 (4~65) winsize 62
1439 17:34:07.383811 [CA 4] Center 35 (5~66) winsize 62
1440 17:34:07.387129 [CA 5] Center 34 (4~65) winsize 62
1441 17:34:07.387207
1442 17:34:07.390457 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1443 17:34:07.390534
1444 17:34:07.393741 [CATrainingPosCal] consider 2 rank data
1445 17:34:07.397145 u2DelayCellTimex100 = 270/100 ps
1446 17:34:07.400517 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1447 17:34:07.403984 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1448 17:34:07.407284 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1449 17:34:07.410591 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1450 17:34:07.414010 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1451 17:34:07.417280 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1452 17:34:07.417361
1453 17:34:07.420516 CA PerBit enable=1, Macro0, CA PI delay=34
1454 17:34:07.423614
1455 17:34:07.423744 [CBTSetCACLKResult] CA Dly = 34
1456 17:34:07.427393 CS Dly: 7 (0~38)
1457 17:34:07.427464
1458 17:34:07.430509 ----->DramcWriteLeveling(PI) begin...
1459 17:34:07.430583 ==
1460 17:34:07.433917 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 17:34:07.437314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 17:34:07.437384 ==
1463 17:34:07.440495 Write leveling (Byte 0): 27 => 27
1464 17:34:07.443459 Write leveling (Byte 1): 28 => 28
1465 17:34:07.446732 DramcWriteLeveling(PI) end<-----
1466 17:34:07.446809
1467 17:34:07.446874 ==
1468 17:34:07.450704 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 17:34:07.454008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 17:34:07.456792 ==
1471 17:34:07.456865 [Gating] SW mode calibration
1472 17:34:07.463798 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1473 17:34:07.470625 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1474 17:34:07.474079 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1475 17:34:07.480398 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1476 17:34:07.483850 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 17:34:07.487289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 17:34:07.490699 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 17:34:07.497485 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 17:34:07.500705 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 17:34:07.503998 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 17:34:07.510283 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 17:34:07.513812 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 17:34:07.516990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 17:34:07.524261 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 17:34:07.527082 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 17:34:07.530448 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 17:34:07.537124 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 17:34:07.540520 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 17:34:07.543597 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1491 17:34:07.550319 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1492 17:34:07.553809 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 17:34:07.557271 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 17:34:07.563901 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 17:34:07.567437 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 17:34:07.570961 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 17:34:07.573704 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 17:34:07.580681 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 17:34:07.584218 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1500 17:34:07.587577 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1501 17:34:07.593901 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 17:34:07.597309 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 17:34:07.600628 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 17:34:07.607600 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 17:34:07.610494 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 17:34:07.614313 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 17:34:07.620473 0 10 4 | B1->B0 | 3232 2e2e | 1 1 | (0 1) (1 0)
1508 17:34:07.623896 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1509 17:34:07.627331 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 17:34:07.633941 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 17:34:07.637312 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 17:34:07.640765 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 17:34:07.647584 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 17:34:07.650830 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1515 17:34:07.653930 0 11 4 | B1->B0 | 2c2c 3636 | 0 0 | (0 0) (0 0)
1516 17:34:07.660651 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1517 17:34:07.664261 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 17:34:07.667371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 17:34:07.673761 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 17:34:07.677228 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 17:34:07.680779 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 17:34:07.684192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 17:34:07.690430 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1524 17:34:07.693758 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 17:34:07.697227 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 17:34:07.704060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 17:34:07.707514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 17:34:07.711017 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 17:34:07.717672 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 17:34:07.720828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 17:34:07.724386 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 17:34:07.730539 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 17:34:07.733991 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 17:34:07.737321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 17:34:07.744018 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 17:34:07.747496 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 17:34:07.750998 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 17:34:07.754429 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1539 17:34:07.760758 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1540 17:34:07.764066 Total UI for P1: 0, mck2ui 16
1541 17:34:07.767417 best dqsien dly found for B1: ( 0, 14, 0)
1542 17:34:07.770657 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 17:34:07.774409 Total UI for P1: 0, mck2ui 16
1544 17:34:07.777829 best dqsien dly found for B0: ( 0, 14, 2)
1545 17:34:07.780908 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1546 17:34:07.784516 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1547 17:34:07.784604
1548 17:34:07.787456 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1549 17:34:07.791165 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1550 17:34:07.794182 [Gating] SW calibration Done
1551 17:34:07.794263 ==
1552 17:34:07.797853 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 17:34:07.801309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 17:34:07.801417 ==
1555 17:34:07.804899 RX Vref Scan: 0
1556 17:34:07.805055
1557 17:34:07.807500 RX Vref 0 -> 0, step: 1
1558 17:34:07.807580
1559 17:34:07.807666 RX Delay -130 -> 252, step: 16
1560 17:34:07.815117 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1561 17:34:07.817870 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1562 17:34:07.821418 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1563 17:34:07.824857 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1564 17:34:07.828298 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1565 17:34:07.834418 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1566 17:34:07.837926 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1567 17:34:07.841509 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1568 17:34:07.844935 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1569 17:34:07.848359 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1570 17:34:07.854968 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1571 17:34:07.858376 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1572 17:34:07.861851 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1573 17:34:07.864514 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1574 17:34:07.867998 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1575 17:34:07.874867 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1576 17:34:07.874947 ==
1577 17:34:07.878304 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 17:34:07.881843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 17:34:07.881924 ==
1580 17:34:07.881986 DQS Delay:
1581 17:34:07.884668 DQS0 = 0, DQS1 = 0
1582 17:34:07.884750 DQM Delay:
1583 17:34:07.888061 DQM0 = 95, DQM1 = 90
1584 17:34:07.888163 DQ Delay:
1585 17:34:07.891439 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1586 17:34:07.894772 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1587 17:34:07.898503 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1588 17:34:07.901666 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1589 17:34:07.901808
1590 17:34:07.901885
1591 17:34:07.901947 ==
1592 17:34:07.904903 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 17:34:07.908004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 17:34:07.908108 ==
1595 17:34:07.911215
1596 17:34:07.911309
1597 17:34:07.911372 TX Vref Scan disable
1598 17:34:07.914606 == TX Byte 0 ==
1599 17:34:07.918152 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1600 17:34:07.922341 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1601 17:34:07.925613 == TX Byte 1 ==
1602 17:34:07.928813 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 17:34:07.932253 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 17:34:07.932445 ==
1605 17:34:07.935618 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 17:34:07.939044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 17:34:07.939288 ==
1608 17:34:07.952853 TX Vref=22, minBit 3, minWin=26, winSum=438
1609 17:34:07.957045 TX Vref=24, minBit 3, minWin=26, winSum=441
1610 17:34:07.960240 TX Vref=26, minBit 1, minWin=27, winSum=445
1611 17:34:07.963452 TX Vref=28, minBit 3, minWin=26, winSum=445
1612 17:34:07.966379 TX Vref=30, minBit 0, minWin=27, winSum=449
1613 17:34:07.969806 TX Vref=32, minBit 0, minWin=27, winSum=449
1614 17:34:07.976912 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1615 17:34:07.977025
1616 17:34:07.980296 Final TX Range 1 Vref 30
1617 17:34:07.980393
1618 17:34:07.980460 ==
1619 17:34:07.982949 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 17:34:07.986575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 17:34:07.986659 ==
1622 17:34:07.986724
1623 17:34:07.989912
1624 17:34:07.989995 TX Vref Scan disable
1625 17:34:07.993438 == TX Byte 0 ==
1626 17:34:07.996811 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1627 17:34:07.999545 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1628 17:34:08.003092 == TX Byte 1 ==
1629 17:34:08.006555 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1630 17:34:08.010039 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1631 17:34:08.013457
1632 17:34:08.013536 [DATLAT]
1633 17:34:08.013598 Freq=800, CH1 RK0
1634 17:34:08.013658
1635 17:34:08.016233 DATLAT Default: 0xa
1636 17:34:08.016301 0, 0xFFFF, sum = 0
1637 17:34:08.019648 1, 0xFFFF, sum = 0
1638 17:34:08.019722 2, 0xFFFF, sum = 0
1639 17:34:08.023126 3, 0xFFFF, sum = 0
1640 17:34:08.023202 4, 0xFFFF, sum = 0
1641 17:34:08.026355 5, 0xFFFF, sum = 0
1642 17:34:08.026440 6, 0xFFFF, sum = 0
1643 17:34:08.029886 7, 0xFFFF, sum = 0
1644 17:34:08.033101 8, 0xFFFF, sum = 0
1645 17:34:08.033186 9, 0x0, sum = 1
1646 17:34:08.033252 10, 0x0, sum = 2
1647 17:34:08.036375 11, 0x0, sum = 3
1648 17:34:08.036459 12, 0x0, sum = 4
1649 17:34:08.040062 best_step = 10
1650 17:34:08.040143
1651 17:34:08.040207 ==
1652 17:34:08.043024 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 17:34:08.046797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 17:34:08.046881 ==
1655 17:34:08.049571 RX Vref Scan: 1
1656 17:34:08.049653
1657 17:34:08.049717 Set Vref Range= 32 -> 127
1658 17:34:08.049777
1659 17:34:08.053283 RX Vref 32 -> 127, step: 1
1660 17:34:08.053371
1661 17:34:08.056535 RX Delay -63 -> 252, step: 8
1662 17:34:08.056609
1663 17:34:08.059624 Set Vref, RX VrefLevel [Byte0]: 32
1664 17:34:08.063186 [Byte1]: 32
1665 17:34:08.063258
1666 17:34:08.066487 Set Vref, RX VrefLevel [Byte0]: 33
1667 17:34:08.069786 [Byte1]: 33
1668 17:34:08.073251
1669 17:34:08.073356 Set Vref, RX VrefLevel [Byte0]: 34
1670 17:34:08.076648 [Byte1]: 34
1671 17:34:08.080897
1672 17:34:08.080984 Set Vref, RX VrefLevel [Byte0]: 35
1673 17:34:08.084248 [Byte1]: 35
1674 17:34:08.124893
1675 17:34:08.125170 Set Vref, RX VrefLevel [Byte0]: 36
1676 17:34:08.125565 [Byte1]: 36
1677 17:34:08.125708
1678 17:34:08.125852 Set Vref, RX VrefLevel [Byte0]: 37
1679 17:34:08.125997 [Byte1]: 37
1680 17:34:08.126139
1681 17:34:08.126276 Set Vref, RX VrefLevel [Byte0]: 38
1682 17:34:08.126407 [Byte1]: 38
1683 17:34:08.126588
1684 17:34:08.126732 Set Vref, RX VrefLevel [Byte0]: 39
1685 17:34:08.126899 [Byte1]: 39
1686 17:34:08.127037
1687 17:34:08.127182 Set Vref, RX VrefLevel [Byte0]: 40
1688 17:34:08.127319 [Byte1]: 40
1689 17:34:08.127457
1690 17:34:08.127587 Set Vref, RX VrefLevel [Byte0]: 41
1691 17:34:08.129022 [Byte1]: 41
1692 17:34:08.133007
1693 17:34:08.133155 Set Vref, RX VrefLevel [Byte0]: 42
1694 17:34:08.136800 [Byte1]: 42
1695 17:34:08.140884
1696 17:34:08.140993 Set Vref, RX VrefLevel [Byte0]: 43
1697 17:34:08.143790 [Byte1]: 43
1698 17:34:08.148377
1699 17:34:08.148510 Set Vref, RX VrefLevel [Byte0]: 44
1700 17:34:08.151633 [Byte1]: 44
1701 17:34:08.155626
1702 17:34:08.155844 Set Vref, RX VrefLevel [Byte0]: 45
1703 17:34:08.159035 [Byte1]: 45
1704 17:34:08.162871
1705 17:34:08.163227 Set Vref, RX VrefLevel [Byte0]: 46
1706 17:34:08.166680 [Byte1]: 46
1707 17:34:08.170344
1708 17:34:08.170505 Set Vref, RX VrefLevel [Byte0]: 47
1709 17:34:08.174237 [Byte1]: 47
1710 17:34:08.177939
1711 17:34:08.178160 Set Vref, RX VrefLevel [Byte0]: 48
1712 17:34:08.181685 [Byte1]: 48
1713 17:34:08.185866
1714 17:34:08.185982 Set Vref, RX VrefLevel [Byte0]: 49
1715 17:34:08.189238 [Byte1]: 49
1716 17:34:08.193298
1717 17:34:08.193437 Set Vref, RX VrefLevel [Byte0]: 50
1718 17:34:08.196771 [Byte1]: 50
1719 17:34:08.201035
1720 17:34:08.201150 Set Vref, RX VrefLevel [Byte0]: 51
1721 17:34:08.203833 [Byte1]: 51
1722 17:34:08.208537
1723 17:34:08.208629 Set Vref, RX VrefLevel [Byte0]: 52
1724 17:34:08.211305 [Byte1]: 52
1725 17:34:08.215539
1726 17:34:08.215621 Set Vref, RX VrefLevel [Byte0]: 53
1727 17:34:08.218979 [Byte1]: 53
1728 17:34:08.223141
1729 17:34:08.223223 Set Vref, RX VrefLevel [Byte0]: 54
1730 17:34:08.226530 [Byte1]: 54
1731 17:34:08.230815
1732 17:34:08.230909 Set Vref, RX VrefLevel [Byte0]: 55
1733 17:34:08.233759 [Byte1]: 55
1734 17:34:08.237812
1735 17:34:08.237891 Set Vref, RX VrefLevel [Byte0]: 56
1736 17:34:08.241342 [Byte1]: 56
1737 17:34:08.245640
1738 17:34:08.245723 Set Vref, RX VrefLevel [Byte0]: 57
1739 17:34:08.249198 [Byte1]: 57
1740 17:34:08.253114
1741 17:34:08.253196 Set Vref, RX VrefLevel [Byte0]: 58
1742 17:34:08.256384 [Byte1]: 58
1743 17:34:08.260464
1744 17:34:08.260598 Set Vref, RX VrefLevel [Byte0]: 59
1745 17:34:08.263881 [Byte1]: 59
1746 17:34:08.267922
1747 17:34:08.268131 Set Vref, RX VrefLevel [Byte0]: 60
1748 17:34:08.271423 [Byte1]: 60
1749 17:34:08.275464
1750 17:34:08.275680 Set Vref, RX VrefLevel [Byte0]: 61
1751 17:34:08.279246 [Byte1]: 61
1752 17:34:08.283221
1753 17:34:08.283364 Set Vref, RX VrefLevel [Byte0]: 62
1754 17:34:08.286408 [Byte1]: 62
1755 17:34:08.290501
1756 17:34:08.290652 Set Vref, RX VrefLevel [Byte0]: 63
1757 17:34:08.294108 [Byte1]: 63
1758 17:34:08.298438
1759 17:34:08.298643 Set Vref, RX VrefLevel [Byte0]: 64
1760 17:34:08.301367 [Byte1]: 64
1761 17:34:08.305557
1762 17:34:08.305793 Set Vref, RX VrefLevel [Byte0]: 65
1763 17:34:08.308799 [Byte1]: 65
1764 17:34:08.313164
1765 17:34:08.313368 Set Vref, RX VrefLevel [Byte0]: 66
1766 17:34:08.316573 [Byte1]: 66
1767 17:34:08.320830
1768 17:34:08.320969 Set Vref, RX VrefLevel [Byte0]: 67
1769 17:34:08.323681 [Byte1]: 67
1770 17:34:08.327904
1771 17:34:08.328038 Set Vref, RX VrefLevel [Byte0]: 68
1772 17:34:08.331448 [Byte1]: 68
1773 17:34:08.335608
1774 17:34:08.335739 Set Vref, RX VrefLevel [Byte0]: 69
1775 17:34:08.339335 [Byte1]: 69
1776 17:34:08.343499
1777 17:34:08.343608 Set Vref, RX VrefLevel [Byte0]: 70
1778 17:34:08.346221 [Byte1]: 70
1779 17:34:08.350288
1780 17:34:08.350373 Set Vref, RX VrefLevel [Byte0]: 71
1781 17:34:08.353824 [Byte1]: 71
1782 17:34:08.357974
1783 17:34:08.358059 Set Vref, RX VrefLevel [Byte0]: 72
1784 17:34:08.361415 [Byte1]: 72
1785 17:34:08.365382
1786 17:34:08.365465 Final RX Vref Byte 0 = 60 to rank0
1787 17:34:08.368611 Final RX Vref Byte 1 = 57 to rank0
1788 17:34:08.372208 Final RX Vref Byte 0 = 60 to rank1
1789 17:34:08.375800 Final RX Vref Byte 1 = 57 to rank1==
1790 17:34:08.378709 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 17:34:08.385832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 17:34:08.386367 ==
1793 17:34:08.386853 DQS Delay:
1794 17:34:08.387301 DQS0 = 0, DQS1 = 0
1795 17:34:08.389385 DQM Delay:
1796 17:34:08.389738 DQM0 = 94, DQM1 = 90
1797 17:34:08.392634 DQ Delay:
1798 17:34:08.395854 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1799 17:34:08.399285 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
1800 17:34:08.402552 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1801 17:34:08.406196 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1802 17:34:08.406610
1803 17:34:08.406992
1804 17:34:08.412633 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1805 17:34:08.415623 CH1 RK0: MR19=606, MR18=2945
1806 17:34:08.422872 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1807 17:34:08.423500
1808 17:34:08.425876 ----->DramcWriteLeveling(PI) begin...
1809 17:34:08.426499 ==
1810 17:34:08.429123 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 17:34:08.432314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 17:34:08.432746 ==
1813 17:34:08.435706 Write leveling (Byte 0): 27 => 27
1814 17:34:08.439228 Write leveling (Byte 1): 28 => 28
1815 17:34:08.442633 DramcWriteLeveling(PI) end<-----
1816 17:34:08.443249
1817 17:34:08.443828 ==
1818 17:34:08.446034 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 17:34:08.449646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 17:34:08.450288 ==
1821 17:34:08.452281 [Gating] SW mode calibration
1822 17:34:08.459293 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 17:34:08.465571 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 17:34:08.468830 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 17:34:08.472850 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1826 17:34:08.479356 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 17:34:08.482140 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 17:34:08.485749 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 17:34:08.492624 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 17:34:08.495362 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 17:34:08.498669 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 17:34:08.505566 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 17:34:08.509051 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 17:34:08.511885 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 17:34:08.519023 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 17:34:08.522468 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 17:34:08.525870 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 17:34:08.532237 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 17:34:08.535532 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 17:34:08.538811 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 17:34:08.541957 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1842 17:34:08.548749 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1843 17:34:08.552041 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 17:34:08.558664 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 17:34:08.562128 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 17:34:08.565500 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 17:34:08.568275 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 17:34:08.575427 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 17:34:08.578973 0 9 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1850 17:34:08.582170 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1851 17:34:08.588963 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 17:34:08.592213 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 17:34:08.595215 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 17:34:08.602189 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 17:34:08.605559 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 17:34:08.608296 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1857 17:34:08.615667 0 10 4 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (1 1)
1858 17:34:08.618456 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1859 17:34:08.621843 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 17:34:08.628597 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 17:34:08.632037 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 17:34:08.635429 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 17:34:08.642126 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 17:34:08.645473 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1865 17:34:08.648369 0 11 4 | B1->B0 | 3a3a 2d2d | 0 0 | (0 0) (1 1)
1866 17:34:08.655058 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1867 17:34:08.658436 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 17:34:08.662184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 17:34:08.665204 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 17:34:08.672115 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 17:34:08.675291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 17:34:08.678487 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 17:34:08.685271 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1874 17:34:08.688639 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 17:34:08.691945 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 17:34:08.698765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 17:34:08.702209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 17:34:08.705565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 17:34:08.712254 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 17:34:08.715474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 17:34:08.718946 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 17:34:08.725129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 17:34:08.728649 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 17:34:08.732105 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 17:34:08.739014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 17:34:08.741734 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 17:34:08.745446 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 17:34:08.748762 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 17:34:08.755531 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1890 17:34:08.759052 Total UI for P1: 0, mck2ui 16
1891 17:34:08.762699 best dqsien dly found for B1: ( 0, 14, 2)
1892 17:34:08.765527 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 17:34:08.768936 Total UI for P1: 0, mck2ui 16
1894 17:34:08.772266 best dqsien dly found for B0: ( 0, 14, 4)
1895 17:34:08.775668 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1896 17:34:08.779078 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1897 17:34:08.779170
1898 17:34:08.782480 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 17:34:08.785685 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1900 17:34:08.789423 [Gating] SW calibration Done
1901 17:34:08.789500 ==
1902 17:34:08.792720 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 17:34:08.795908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 17:34:08.795986 ==
1905 17:34:08.799098 RX Vref Scan: 0
1906 17:34:08.799191
1907 17:34:08.802303 RX Vref 0 -> 0, step: 1
1908 17:34:08.802378
1909 17:34:08.802459 RX Delay -130 -> 252, step: 16
1910 17:34:08.808878 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1911 17:34:08.812329 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1912 17:34:08.815801 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1913 17:34:08.819043 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1914 17:34:08.822388 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1915 17:34:08.828999 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1916 17:34:08.832507 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1917 17:34:08.835971 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1918 17:34:08.839432 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1919 17:34:08.842924 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1920 17:34:08.849190 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1921 17:34:08.852611 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1922 17:34:08.856068 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1923 17:34:08.859506 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1924 17:34:08.862420 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1925 17:34:08.869256 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1926 17:34:08.869334 ==
1927 17:34:08.872611 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 17:34:08.875963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 17:34:08.876034 ==
1930 17:34:08.876094 DQS Delay:
1931 17:34:08.879403 DQS0 = 0, DQS1 = 0
1932 17:34:08.879473 DQM Delay:
1933 17:34:08.882417 DQM0 = 92, DQM1 = 91
1934 17:34:08.882496 DQ Delay:
1935 17:34:08.885944 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1936 17:34:08.889328 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1937 17:34:08.892710 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1938 17:34:08.895966 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1939 17:34:08.896054
1940 17:34:08.896127
1941 17:34:08.896215 ==
1942 17:34:08.899391 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 17:34:08.902588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 17:34:08.905947 ==
1945 17:34:08.906047
1946 17:34:08.906161
1947 17:34:08.906270 TX Vref Scan disable
1948 17:34:08.909321 == TX Byte 0 ==
1949 17:34:08.912370 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1950 17:34:08.916202 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1951 17:34:08.919348 == TX Byte 1 ==
1952 17:34:08.922652 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 17:34:08.926269 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 17:34:08.929172 ==
1955 17:34:08.933097 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 17:34:08.936233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 17:34:08.936426 ==
1958 17:34:08.948834 TX Vref=22, minBit 1, minWin=26, winSum=441
1959 17:34:08.952189 TX Vref=24, minBit 0, minWin=27, winSum=444
1960 17:34:08.955517 TX Vref=26, minBit 1, minWin=27, winSum=446
1961 17:34:08.959073 TX Vref=28, minBit 2, minWin=27, winSum=450
1962 17:34:08.961688 TX Vref=30, minBit 2, minWin=27, winSum=454
1963 17:34:08.965320 TX Vref=32, minBit 1, minWin=27, winSum=446
1964 17:34:08.972107 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
1965 17:34:08.972559
1966 17:34:08.975546 Final TX Range 1 Vref 30
1967 17:34:08.976037
1968 17:34:08.976369 ==
1969 17:34:08.978351 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 17:34:08.981925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 17:34:08.982354 ==
1972 17:34:08.982678
1973 17:34:08.982936
1974 17:34:08.985159 TX Vref Scan disable
1975 17:34:08.988391 == TX Byte 0 ==
1976 17:34:08.991882 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1977 17:34:08.995357 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1978 17:34:08.998684 == TX Byte 1 ==
1979 17:34:09.002179 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1980 17:34:09.005036 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1981 17:34:09.005220
1982 17:34:09.008332 [DATLAT]
1983 17:34:09.008497 Freq=800, CH1 RK1
1984 17:34:09.008626
1985 17:34:09.011532 DATLAT Default: 0xa
1986 17:34:09.011683 0, 0xFFFF, sum = 0
1987 17:34:09.015048 1, 0xFFFF, sum = 0
1988 17:34:09.015166 2, 0xFFFF, sum = 0
1989 17:34:09.018473 3, 0xFFFF, sum = 0
1990 17:34:09.018615 4, 0xFFFF, sum = 0
1991 17:34:09.021841 5, 0xFFFF, sum = 0
1992 17:34:09.021954 6, 0xFFFF, sum = 0
1993 17:34:09.025454 7, 0xFFFF, sum = 0
1994 17:34:09.025603 8, 0xFFFF, sum = 0
1995 17:34:09.028772 9, 0x0, sum = 1
1996 17:34:09.028923 10, 0x0, sum = 2
1997 17:34:09.032097 11, 0x0, sum = 3
1998 17:34:09.032251 12, 0x0, sum = 4
1999 17:34:09.035537 best_step = 10
2000 17:34:09.035692
2001 17:34:09.035812 ==
2002 17:34:09.038990 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 17:34:09.042264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 17:34:09.042376 ==
2005 17:34:09.045591 RX Vref Scan: 0
2006 17:34:09.045713
2007 17:34:09.045808 RX Vref 0 -> 0, step: 1
2008 17:34:09.045897
2009 17:34:09.048880 RX Delay -79 -> 252, step: 8
2010 17:34:09.055177 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
2011 17:34:09.058656 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2012 17:34:09.062220 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2013 17:34:09.065497 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2014 17:34:09.068396 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2015 17:34:09.071834 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2016 17:34:09.075381 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2017 17:34:09.082524 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2018 17:34:09.085368 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2019 17:34:09.088776 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2020 17:34:09.092090 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2021 17:34:09.095575 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2022 17:34:09.102525 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2023 17:34:09.105259 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2024 17:34:09.108735 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2025 17:34:09.112147 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2026 17:34:09.112445 ==
2027 17:34:09.115557 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 17:34:09.119084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 17:34:09.121847 ==
2030 17:34:09.122126 DQS Delay:
2031 17:34:09.122366 DQS0 = 0, DQS1 = 0
2032 17:34:09.125518 DQM Delay:
2033 17:34:09.125711 DQM0 = 96, DQM1 = 90
2034 17:34:09.129182 DQ Delay:
2035 17:34:09.131969 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2036 17:34:09.135539 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2037 17:34:09.135733 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2038 17:34:09.142052 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2039 17:34:09.142154
2040 17:34:09.142231
2041 17:34:09.149163 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2042 17:34:09.152495 CH1 RK1: MR19=606, MR18=440E
2043 17:34:09.159199 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2044 17:34:09.162407 [RxdqsGatingPostProcess] freq 800
2045 17:34:09.165761 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 17:34:09.169160 Pre-setting of DQS Precalculation
2047 17:34:09.175535 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 17:34:09.182491 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 17:34:09.188841 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 17:34:09.188963
2051 17:34:09.189056
2052 17:34:09.192271 [Calibration Summary] 1600 Mbps
2053 17:34:09.192366 CH 0, Rank 0
2054 17:34:09.196184 SW Impedance : PASS
2055 17:34:09.198953 DUTY Scan : NO K
2056 17:34:09.199050 ZQ Calibration : PASS
2057 17:34:09.202436 Jitter Meter : NO K
2058 17:34:09.202523 CBT Training : PASS
2059 17:34:09.205769 Write leveling : PASS
2060 17:34:09.209145 RX DQS gating : PASS
2061 17:34:09.209223 RX DQ/DQS(RDDQC) : PASS
2062 17:34:09.212513 TX DQ/DQS : PASS
2063 17:34:09.215917 RX DATLAT : PASS
2064 17:34:09.216003 RX DQ/DQS(Engine): PASS
2065 17:34:09.218669 TX OE : NO K
2066 17:34:09.218781 All Pass.
2067 17:34:09.218874
2068 17:34:09.222610 CH 0, Rank 1
2069 17:34:09.222745 SW Impedance : PASS
2070 17:34:09.225878 DUTY Scan : NO K
2071 17:34:09.229535 ZQ Calibration : PASS
2072 17:34:09.229610 Jitter Meter : NO K
2073 17:34:09.232369 CBT Training : PASS
2074 17:34:09.235970 Write leveling : PASS
2075 17:34:09.236047 RX DQS gating : PASS
2076 17:34:09.239393 RX DQ/DQS(RDDQC) : PASS
2077 17:34:09.239493 TX DQ/DQS : PASS
2078 17:34:09.242801 RX DATLAT : PASS
2079 17:34:09.245551 RX DQ/DQS(Engine): PASS
2080 17:34:09.245639 TX OE : NO K
2081 17:34:09.249183 All Pass.
2082 17:34:09.249312
2083 17:34:09.249383 CH 1, Rank 0
2084 17:34:09.252448 SW Impedance : PASS
2085 17:34:09.252572 DUTY Scan : NO K
2086 17:34:09.255777 ZQ Calibration : PASS
2087 17:34:09.259449 Jitter Meter : NO K
2088 17:34:09.259565 CBT Training : PASS
2089 17:34:09.262470 Write leveling : PASS
2090 17:34:09.265490 RX DQS gating : PASS
2091 17:34:09.265602 RX DQ/DQS(RDDQC) : PASS
2092 17:34:09.269376 TX DQ/DQS : PASS
2093 17:34:09.272609 RX DATLAT : PASS
2094 17:34:09.272738 RX DQ/DQS(Engine): PASS
2095 17:34:09.275792 TX OE : NO K
2096 17:34:09.275874 All Pass.
2097 17:34:09.275941
2098 17:34:09.279356 CH 1, Rank 1
2099 17:34:09.279435 SW Impedance : PASS
2100 17:34:09.282456 DUTY Scan : NO K
2101 17:34:09.282538 ZQ Calibration : PASS
2102 17:34:09.285876 Jitter Meter : NO K
2103 17:34:09.289423 CBT Training : PASS
2104 17:34:09.289524 Write leveling : PASS
2105 17:34:09.292227 RX DQS gating : PASS
2106 17:34:09.295550 RX DQ/DQS(RDDQC) : PASS
2107 17:34:09.295631 TX DQ/DQS : PASS
2108 17:34:09.299193 RX DATLAT : PASS
2109 17:34:09.302487 RX DQ/DQS(Engine): PASS
2110 17:34:09.302606 TX OE : NO K
2111 17:34:09.306106 All Pass.
2112 17:34:09.306190
2113 17:34:09.306254 DramC Write-DBI off
2114 17:34:09.309573 PER_BANK_REFRESH: Hybrid Mode
2115 17:34:09.309655 TX_TRACKING: ON
2116 17:34:09.312395 [GetDramInforAfterCalByMRR] Vendor 6.
2117 17:34:09.319345 [GetDramInforAfterCalByMRR] Revision 606.
2118 17:34:09.322322 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 17:34:09.322439 MR0 0x3b3b
2120 17:34:09.322537 MR8 0x5151
2121 17:34:09.325704 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 17:34:09.325866
2123 17:34:09.329023 MR0 0x3b3b
2124 17:34:09.329148 MR8 0x5151
2125 17:34:09.333048 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 17:34:09.333130
2127 17:34:09.342918 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 17:34:09.346011 [FAST_K] Save calibration result to emmc
2129 17:34:09.349562 [FAST_K] Save calibration result to emmc
2130 17:34:09.352541 dram_init: config_dvfs: 1
2131 17:34:09.355988 dramc_set_vcore_voltage set vcore to 662500
2132 17:34:09.359507 Read voltage for 1200, 2
2133 17:34:09.359612 Vio18 = 0
2134 17:34:09.359725 Vcore = 662500
2135 17:34:09.362357 Vdram = 0
2136 17:34:09.362437 Vddq = 0
2137 17:34:09.362499 Vmddr = 0
2138 17:34:09.369294 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 17:34:09.372571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 17:34:09.375652 MEM_TYPE=3, freq_sel=15
2141 17:34:09.378911 sv_algorithm_assistance_LP4_1600
2142 17:34:09.382390 ============ PULL DRAM RESETB DOWN ============
2143 17:34:09.385692 ========== PULL DRAM RESETB DOWN end =========
2144 17:34:09.392700 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 17:34:09.395992 ===================================
2146 17:34:09.396180 LPDDR4 DRAM CONFIGURATION
2147 17:34:09.399429 ===================================
2148 17:34:09.402266 EX_ROW_EN[0] = 0x0
2149 17:34:09.405754 EX_ROW_EN[1] = 0x0
2150 17:34:09.405891 LP4Y_EN = 0x0
2151 17:34:09.409121 WORK_FSP = 0x0
2152 17:34:09.409213 WL = 0x4
2153 17:34:09.412530 RL = 0x4
2154 17:34:09.412634 BL = 0x2
2155 17:34:09.415446 RPST = 0x0
2156 17:34:09.415571 RD_PRE = 0x0
2157 17:34:09.418938 WR_PRE = 0x1
2158 17:34:09.419020 WR_PST = 0x0
2159 17:34:09.422361 DBI_WR = 0x0
2160 17:34:09.422488 DBI_RD = 0x0
2161 17:34:09.426085 OTF = 0x1
2162 17:34:09.429035 ===================================
2163 17:34:09.432571 ===================================
2164 17:34:09.432665 ANA top config
2165 17:34:09.435889 ===================================
2166 17:34:09.439250 DLL_ASYNC_EN = 0
2167 17:34:09.442715 ALL_SLAVE_EN = 0
2168 17:34:09.442823 NEW_RANK_MODE = 1
2169 17:34:09.445476 DLL_IDLE_MODE = 1
2170 17:34:09.448913 LP45_APHY_COMB_EN = 1
2171 17:34:09.452291 TX_ODT_DIS = 1
2172 17:34:09.455864 NEW_8X_MODE = 1
2173 17:34:09.459339 ===================================
2174 17:34:09.462195 ===================================
2175 17:34:09.462333 data_rate = 2400
2176 17:34:09.465727 CKR = 1
2177 17:34:09.469177 DQ_P2S_RATIO = 8
2178 17:34:09.471923 ===================================
2179 17:34:09.475542 CA_P2S_RATIO = 8
2180 17:34:09.479209 DQ_CA_OPEN = 0
2181 17:34:09.481865 DQ_SEMI_OPEN = 0
2182 17:34:09.481979 CA_SEMI_OPEN = 0
2183 17:34:09.485746 CA_FULL_RATE = 0
2184 17:34:09.489258 DQ_CKDIV4_EN = 0
2185 17:34:09.491949 CA_CKDIV4_EN = 0
2186 17:34:09.495299 CA_PREDIV_EN = 0
2187 17:34:09.498630 PH8_DLY = 17
2188 17:34:09.498740 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 17:34:09.501902 DQ_AAMCK_DIV = 4
2190 17:34:09.505211 CA_AAMCK_DIV = 4
2191 17:34:09.508920 CA_ADMCK_DIV = 4
2192 17:34:09.512098 DQ_TRACK_CA_EN = 0
2193 17:34:09.515451 CA_PICK = 1200
2194 17:34:09.518728 CA_MCKIO = 1200
2195 17:34:09.518806 MCKIO_SEMI = 0
2196 17:34:09.522326 PLL_FREQ = 2366
2197 17:34:09.525632 DQ_UI_PI_RATIO = 32
2198 17:34:09.529170 CA_UI_PI_RATIO = 0
2199 17:34:09.532594 ===================================
2200 17:34:09.535956 ===================================
2201 17:34:09.538910 memory_type:LPDDR4
2202 17:34:09.539030 GP_NUM : 10
2203 17:34:09.542404 SRAM_EN : 1
2204 17:34:09.542529 MD32_EN : 0
2205 17:34:09.545747 ===================================
2206 17:34:09.549181 [ANA_INIT] >>>>>>>>>>>>>>
2207 17:34:09.552706 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 17:34:09.555390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 17:34:09.558801 ===================================
2210 17:34:09.562185 data_rate = 2400,PCW = 0X5b00
2211 17:34:09.565491 ===================================
2212 17:34:09.568943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 17:34:09.575495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 17:34:09.579004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 17:34:09.585525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 17:34:09.589028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 17:34:09.592285 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 17:34:09.592386 [ANA_INIT] flow start
2219 17:34:09.595435 [ANA_INIT] PLL >>>>>>>>
2220 17:34:09.598793 [ANA_INIT] PLL <<<<<<<<
2221 17:34:09.598902 [ANA_INIT] MIDPI >>>>>>>>
2222 17:34:09.602067 [ANA_INIT] MIDPI <<<<<<<<
2223 17:34:09.605670 [ANA_INIT] DLL >>>>>>>>
2224 17:34:09.605751 [ANA_INIT] DLL <<<<<<<<
2225 17:34:09.608960 [ANA_INIT] flow end
2226 17:34:09.612357 ============ LP4 DIFF to SE enter ============
2227 17:34:09.615624 ============ LP4 DIFF to SE exit ============
2228 17:34:09.619470 [ANA_INIT] <<<<<<<<<<<<<
2229 17:34:09.622537 [Flow] Enable top DCM control >>>>>
2230 17:34:09.625881 [Flow] Enable top DCM control <<<<<
2231 17:34:09.629130 Enable DLL master slave shuffle
2232 17:34:09.636187 ==============================================================
2233 17:34:09.636275 Gating Mode config
2234 17:34:09.642450 ==============================================================
2235 17:34:09.642570 Config description:
2236 17:34:09.652914 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 17:34:09.659216 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 17:34:09.665950 SELPH_MODE 0: By rank 1: By Phase
2239 17:34:09.669579 ==============================================================
2240 17:34:09.672217 GAT_TRACK_EN = 1
2241 17:34:09.675591 RX_GATING_MODE = 2
2242 17:34:09.679197 RX_GATING_TRACK_MODE = 2
2243 17:34:09.682646 SELPH_MODE = 1
2244 17:34:09.686070 PICG_EARLY_EN = 1
2245 17:34:09.688921 VALID_LAT_VALUE = 1
2246 17:34:09.692348 ==============================================================
2247 17:34:09.695740 Enter into Gating configuration >>>>
2248 17:34:09.699249 Exit from Gating configuration <<<<
2249 17:34:09.702520 Enter into DVFS_PRE_config >>>>>
2250 17:34:09.716141 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 17:34:09.718949 Exit from DVFS_PRE_config <<<<<
2252 17:34:09.722452 Enter into PICG configuration >>>>
2253 17:34:09.722535 Exit from PICG configuration <<<<
2254 17:34:09.725603 [RX_INPUT] configuration >>>>>
2255 17:34:09.728879 [RX_INPUT] configuration <<<<<
2256 17:34:09.735603 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 17:34:09.739141 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 17:34:09.745917 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 17:34:09.752563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 17:34:09.759495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 17:34:09.765965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 17:34:09.769402 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 17:34:09.772700 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 17:34:09.776217 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 17:34:09.782480 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 17:34:09.786141 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 17:34:09.789494 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 17:34:09.793016 ===================================
2269 17:34:09.795913 LPDDR4 DRAM CONFIGURATION
2270 17:34:09.799394 ===================================
2271 17:34:09.799475 EX_ROW_EN[0] = 0x0
2272 17:34:09.802893 EX_ROW_EN[1] = 0x0
2273 17:34:09.802973 LP4Y_EN = 0x0
2274 17:34:09.806361 WORK_FSP = 0x0
2275 17:34:09.809250 WL = 0x4
2276 17:34:09.809331 RL = 0x4
2277 17:34:09.812685 BL = 0x2
2278 17:34:09.812766 RPST = 0x0
2279 17:34:09.815971 RD_PRE = 0x0
2280 17:34:09.816052 WR_PRE = 0x1
2281 17:34:09.819147 WR_PST = 0x0
2282 17:34:09.819228 DBI_WR = 0x0
2283 17:34:09.822835 DBI_RD = 0x0
2284 17:34:09.822917 OTF = 0x1
2285 17:34:09.826364 ===================================
2286 17:34:09.829796 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 17:34:09.836433 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 17:34:09.839271 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 17:34:09.842805 ===================================
2290 17:34:09.846383 LPDDR4 DRAM CONFIGURATION
2291 17:34:09.849885 ===================================
2292 17:34:09.849966 EX_ROW_EN[0] = 0x10
2293 17:34:09.852648 EX_ROW_EN[1] = 0x0
2294 17:34:09.852729 LP4Y_EN = 0x0
2295 17:34:09.856059 WORK_FSP = 0x0
2296 17:34:09.856149 WL = 0x4
2297 17:34:09.859320 RL = 0x4
2298 17:34:09.859401 BL = 0x2
2299 17:34:09.863193 RPST = 0x0
2300 17:34:09.863289 RD_PRE = 0x0
2301 17:34:09.866621 WR_PRE = 0x1
2302 17:34:09.866702 WR_PST = 0x0
2303 17:34:09.869873 DBI_WR = 0x0
2304 17:34:09.869953 DBI_RD = 0x0
2305 17:34:09.873030 OTF = 0x1
2306 17:34:09.876076 ===================================
2307 17:34:09.882822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 17:34:09.882903 ==
2309 17:34:09.886365 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 17:34:09.889882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 17:34:09.889964 ==
2312 17:34:09.892632 [Duty_Offset_Calibration]
2313 17:34:09.892711 B0:2 B1:1 CA:1
2314 17:34:09.892773
2315 17:34:09.896045 [DutyScan_Calibration_Flow] k_type=0
2316 17:34:09.907323
2317 17:34:09.907405 ==CLK 0==
2318 17:34:09.910503 Final CLK duty delay cell = 0
2319 17:34:09.913864 [0] MAX Duty = 5187%(X100), DQS PI = 24
2320 17:34:09.917346 [0] MIN Duty = 4844%(X100), DQS PI = 48
2321 17:34:09.917426 [0] AVG Duty = 5015%(X100)
2322 17:34:09.917489
2323 17:34:09.920635 CH0 CLK Duty spec in!! Max-Min= 343%
2324 17:34:09.927216 [DutyScan_Calibration_Flow] ====Done====
2325 17:34:09.927334
2326 17:34:09.930047 [DutyScan_Calibration_Flow] k_type=1
2327 17:34:09.945863
2328 17:34:09.945948 ==DQS 0 ==
2329 17:34:09.948624 Final DQS duty delay cell = -4
2330 17:34:09.952064 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2331 17:34:09.955584 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2332 17:34:09.959247 [-4] AVG Duty = 4937%(X100)
2333 17:34:09.959318
2334 17:34:09.959378 ==DQS 1 ==
2335 17:34:09.962112 Final DQS duty delay cell = 0
2336 17:34:09.965564 [0] MAX Duty = 5156%(X100), DQS PI = 0
2337 17:34:09.968956 [0] MIN Duty = 5031%(X100), DQS PI = 32
2338 17:34:09.972489 [0] AVG Duty = 5093%(X100)
2339 17:34:09.972564
2340 17:34:09.975958 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2341 17:34:09.976027
2342 17:34:09.978671 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2343 17:34:09.982091 [DutyScan_Calibration_Flow] ====Done====
2344 17:34:09.982165
2345 17:34:09.985477 [DutyScan_Calibration_Flow] k_type=3
2346 17:34:10.002460
2347 17:34:10.002540 ==DQM 0 ==
2348 17:34:10.005999 Final DQM duty delay cell = 0
2349 17:34:10.008734 [0] MAX Duty = 5156%(X100), DQS PI = 30
2350 17:34:10.012181 [0] MIN Duty = 4875%(X100), DQS PI = 58
2351 17:34:10.012278 [0] AVG Duty = 5015%(X100)
2352 17:34:10.015651
2353 17:34:10.015752 ==DQM 1 ==
2354 17:34:10.019126 Final DQM duty delay cell = 0
2355 17:34:10.022656 [0] MAX Duty = 5093%(X100), DQS PI = 0
2356 17:34:10.025483 [0] MIN Duty = 5031%(X100), DQS PI = 16
2357 17:34:10.025550 [0] AVG Duty = 5062%(X100)
2358 17:34:10.028864
2359 17:34:10.032164 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2360 17:34:10.032242
2361 17:34:10.035482 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2362 17:34:10.038852 [DutyScan_Calibration_Flow] ====Done====
2363 17:34:10.038921
2364 17:34:10.042125 [DutyScan_Calibration_Flow] k_type=2
2365 17:34:10.058427
2366 17:34:10.058498 ==DQ 0 ==
2367 17:34:10.061880 Final DQ duty delay cell = 0
2368 17:34:10.065477 [0] MAX Duty = 5031%(X100), DQS PI = 24
2369 17:34:10.068742 [0] MIN Duty = 4906%(X100), DQS PI = 0
2370 17:34:10.068815 [0] AVG Duty = 4968%(X100)
2371 17:34:10.068883
2372 17:34:10.071978 ==DQ 1 ==
2373 17:34:10.075413 Final DQ duty delay cell = 0
2374 17:34:10.078885 [0] MAX Duty = 5093%(X100), DQS PI = 24
2375 17:34:10.082421 [0] MIN Duty = 4907%(X100), DQS PI = 36
2376 17:34:10.082492 [0] AVG Duty = 5000%(X100)
2377 17:34:10.082564
2378 17:34:10.085363 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2379 17:34:10.085431
2380 17:34:10.088833 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2381 17:34:10.095805 [DutyScan_Calibration_Flow] ====Done====
2382 17:34:10.095886 ==
2383 17:34:10.099027 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 17:34:10.102350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 17:34:10.102421 ==
2386 17:34:10.105563 [Duty_Offset_Calibration]
2387 17:34:10.105641 B0:1 B1:0 CA:0
2388 17:34:10.105701
2389 17:34:10.108758 [DutyScan_Calibration_Flow] k_type=0
2390 17:34:10.118000
2391 17:34:10.118088 ==CLK 0==
2392 17:34:10.121511 Final CLK duty delay cell = -4
2393 17:34:10.124793 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2394 17:34:10.127774 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2395 17:34:10.131173 [-4] AVG Duty = 4953%(X100)
2396 17:34:10.131281
2397 17:34:10.134497 CH1 CLK Duty spec in!! Max-Min= 156%
2398 17:34:10.137956 [DutyScan_Calibration_Flow] ====Done====
2399 17:34:10.138026
2400 17:34:10.141265 [DutyScan_Calibration_Flow] k_type=1
2401 17:34:10.157621
2402 17:34:10.157704 ==DQS 0 ==
2403 17:34:10.161068 Final DQS duty delay cell = 0
2404 17:34:10.164578 [0] MAX Duty = 5062%(X100), DQS PI = 24
2405 17:34:10.168028 [0] MIN Duty = 4844%(X100), DQS PI = 0
2406 17:34:10.168111 [0] AVG Duty = 4953%(X100)
2407 17:34:10.170827
2408 17:34:10.170897 ==DQS 1 ==
2409 17:34:10.174308 Final DQS duty delay cell = 0
2410 17:34:10.177689 [0] MAX Duty = 5218%(X100), DQS PI = 18
2411 17:34:10.181163 [0] MIN Duty = 4969%(X100), DQS PI = 10
2412 17:34:10.181244 [0] AVG Duty = 5093%(X100)
2413 17:34:10.184614
2414 17:34:10.188068 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2415 17:34:10.188138
2416 17:34:10.190904 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2417 17:34:10.194367 [DutyScan_Calibration_Flow] ====Done====
2418 17:34:10.194457
2419 17:34:10.197791 [DutyScan_Calibration_Flow] k_type=3
2420 17:34:10.214466
2421 17:34:10.214543 ==DQM 0 ==
2422 17:34:10.217969 Final DQM duty delay cell = 0
2423 17:34:10.220774 [0] MAX Duty = 5156%(X100), DQS PI = 6
2424 17:34:10.224120 [0] MIN Duty = 5031%(X100), DQS PI = 0
2425 17:34:10.224199 [0] AVG Duty = 5093%(X100)
2426 17:34:10.224260
2427 17:34:10.227490 ==DQM 1 ==
2428 17:34:10.231194 Final DQM duty delay cell = 0
2429 17:34:10.234016 [0] MAX Duty = 5031%(X100), DQS PI = 16
2430 17:34:10.237664 [0] MIN Duty = 4907%(X100), DQS PI = 36
2431 17:34:10.237739 [0] AVG Duty = 4969%(X100)
2432 17:34:10.237807
2433 17:34:10.240724 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2434 17:34:10.244755
2435 17:34:10.247475 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2436 17:34:10.250979 [DutyScan_Calibration_Flow] ====Done====
2437 17:34:10.251048
2438 17:34:10.254389 [DutyScan_Calibration_Flow] k_type=2
2439 17:34:10.269853
2440 17:34:10.269929 ==DQ 0 ==
2441 17:34:10.273419 Final DQ duty delay cell = -4
2442 17:34:10.276724 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2443 17:34:10.280124 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2444 17:34:10.283506 [-4] AVG Duty = 4984%(X100)
2445 17:34:10.283579
2446 17:34:10.283646 ==DQ 1 ==
2447 17:34:10.286465 Final DQ duty delay cell = 0
2448 17:34:10.289769 [0] MAX Duty = 5125%(X100), DQS PI = 20
2449 17:34:10.293362 [0] MIN Duty = 4969%(X100), DQS PI = 12
2450 17:34:10.293438 [0] AVG Duty = 5047%(X100)
2451 17:34:10.293509
2452 17:34:10.300270 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2453 17:34:10.300345
2454 17:34:10.303161 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2455 17:34:10.306589 [DutyScan_Calibration_Flow] ====Done====
2456 17:34:10.309965 nWR fixed to 30
2457 17:34:10.310046 [ModeRegInit_LP4] CH0 RK0
2458 17:34:10.313464 [ModeRegInit_LP4] CH0 RK1
2459 17:34:10.316735 [ModeRegInit_LP4] CH1 RK0
2460 17:34:10.316802 [ModeRegInit_LP4] CH1 RK1
2461 17:34:10.320459 match AC timing 7
2462 17:34:10.323157 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 17:34:10.326592 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 17:34:10.333589 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 17:34:10.336933 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 17:34:10.343132 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 17:34:10.343206 ==
2468 17:34:10.346567 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 17:34:10.350365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 17:34:10.350444 ==
2471 17:34:10.356782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 17:34:10.360201 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 17:34:10.370288 [CA 0] Center 39 (8~70) winsize 63
2474 17:34:10.373348 [CA 1] Center 39 (8~70) winsize 63
2475 17:34:10.376985 [CA 2] Center 35 (5~66) winsize 62
2476 17:34:10.380060 [CA 3] Center 34 (4~65) winsize 62
2477 17:34:10.383843 [CA 4] Center 33 (3~64) winsize 62
2478 17:34:10.387242 [CA 5] Center 32 (3~62) winsize 60
2479 17:34:10.387315
2480 17:34:10.390446 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2481 17:34:10.390524
2482 17:34:10.393926 [CATrainingPosCal] consider 1 rank data
2483 17:34:10.396707 u2DelayCellTimex100 = 270/100 ps
2484 17:34:10.400153 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2485 17:34:10.403807 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2486 17:34:10.410132 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2487 17:34:10.413789 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2488 17:34:10.417216 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2489 17:34:10.421083 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2490 17:34:10.421258
2491 17:34:10.423465 CA PerBit enable=1, Macro0, CA PI delay=32
2492 17:34:10.423664
2493 17:34:10.427441 [CBTSetCACLKResult] CA Dly = 32
2494 17:34:10.427624 CS Dly: 6 (0~37)
2495 17:34:10.427758 ==
2496 17:34:10.430687 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 17:34:10.436851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 17:34:10.436981 ==
2499 17:34:10.440394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 17:34:10.446814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2501 17:34:10.456441 [CA 0] Center 38 (8~69) winsize 62
2502 17:34:10.459258 [CA 1] Center 38 (8~69) winsize 62
2503 17:34:10.462697 [CA 2] Center 35 (5~66) winsize 62
2504 17:34:10.466342 [CA 3] Center 34 (4~65) winsize 62
2505 17:34:10.469924 [CA 4] Center 33 (3~64) winsize 62
2506 17:34:10.473167 [CA 5] Center 32 (3~62) winsize 60
2507 17:34:10.473579
2508 17:34:10.476338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 17:34:10.476752
2510 17:34:10.479776 [CATrainingPosCal] consider 2 rank data
2511 17:34:10.483440 u2DelayCellTimex100 = 270/100 ps
2512 17:34:10.486676 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2513 17:34:10.489462 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2514 17:34:10.496432 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2515 17:34:10.499428 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2516 17:34:10.503140 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2517 17:34:10.506490 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2518 17:34:10.507124
2519 17:34:10.509852 CA PerBit enable=1, Macro0, CA PI delay=32
2520 17:34:10.510298
2521 17:34:10.513270 [CBTSetCACLKResult] CA Dly = 32
2522 17:34:10.513699 CS Dly: 6 (0~38)
2523 17:34:10.514028
2524 17:34:10.516685 ----->DramcWriteLeveling(PI) begin...
2525 17:34:10.517102 ==
2526 17:34:10.519499 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 17:34:10.526398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 17:34:10.526811 ==
2529 17:34:10.530041 Write leveling (Byte 0): 34 => 34
2530 17:34:10.533622 Write leveling (Byte 1): 29 => 29
2531 17:34:10.534233 DramcWriteLeveling(PI) end<-----
2532 17:34:10.534605
2533 17:34:10.536276 ==
2534 17:34:10.539676 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 17:34:10.543125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 17:34:10.543540 ==
2537 17:34:10.546657 [Gating] SW mode calibration
2538 17:34:10.553644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 17:34:10.556406 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 17:34:10.563498 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2541 17:34:10.566896 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2542 17:34:10.570283 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 17:34:10.576405 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 17:34:10.580094 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 17:34:10.583440 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 17:34:10.589586 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2547 17:34:10.593331 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2548 17:34:10.595975 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
2549 17:34:10.602760 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 17:34:10.606105 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 17:34:10.609651 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 17:34:10.616335 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 17:34:10.619499 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 17:34:10.622780 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2555 17:34:10.626394 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2556 17:34:10.632632 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
2557 17:34:10.635909 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 17:34:10.639301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 17:34:10.646126 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 17:34:10.649578 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 17:34:10.653098 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 17:34:10.659327 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 17:34:10.662797 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 17:34:10.666297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2565 17:34:10.673162 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 17:34:10.676416 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 17:34:10.679606 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 17:34:10.686524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 17:34:10.689798 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 17:34:10.693227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 17:34:10.699445 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 17:34:10.702839 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 17:34:10.706331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 17:34:10.709715 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 17:34:10.716181 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 17:34:10.719616 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 17:34:10.722840 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 17:34:10.729629 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 17:34:10.733063 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 17:34:10.736369 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 17:34:10.739495 Total UI for P1: 0, mck2ui 16
2582 17:34:10.743131 best dqsien dly found for B0: ( 1, 3, 28)
2583 17:34:10.746359 Total UI for P1: 0, mck2ui 16
2584 17:34:10.749559 best dqsien dly found for B1: ( 1, 3, 30)
2585 17:34:10.753248 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2586 17:34:10.756688 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2587 17:34:10.756770
2588 17:34:10.762930 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2589 17:34:10.766546 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2590 17:34:10.766627 [Gating] SW calibration Done
2591 17:34:10.769892 ==
2592 17:34:10.772664 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 17:34:10.776130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 17:34:10.776212 ==
2595 17:34:10.776276 RX Vref Scan: 0
2596 17:34:10.776335
2597 17:34:10.779541 RX Vref 0 -> 0, step: 1
2598 17:34:10.779670
2599 17:34:10.783036 RX Delay -40 -> 252, step: 8
2600 17:34:10.786428 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2601 17:34:10.789775 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2602 17:34:10.793249 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2603 17:34:10.799545 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2604 17:34:10.803026 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2605 17:34:10.806535 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2606 17:34:10.810018 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2607 17:34:10.812784 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2608 17:34:10.819816 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2609 17:34:10.823134 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2610 17:34:10.826477 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2611 17:34:10.829653 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2612 17:34:10.833317 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2613 17:34:10.839823 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2614 17:34:10.843261 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2615 17:34:10.846920 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2616 17:34:10.846999 ==
2617 17:34:10.849416 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 17:34:10.853380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 17:34:10.853459 ==
2620 17:34:10.856525 DQS Delay:
2621 17:34:10.856605 DQS0 = 0, DQS1 = 0
2622 17:34:10.859784 DQM Delay:
2623 17:34:10.859864 DQM0 = 121, DQM1 = 113
2624 17:34:10.859926 DQ Delay:
2625 17:34:10.866694 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2626 17:34:10.869922 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2627 17:34:10.873196 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2628 17:34:10.876545 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2629 17:34:10.876626
2630 17:34:10.876689
2631 17:34:10.876746 ==
2632 17:34:10.880018 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 17:34:10.883273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 17:34:10.883353 ==
2635 17:34:10.883415
2636 17:34:10.883472
2637 17:34:10.886777 TX Vref Scan disable
2638 17:34:10.889555 == TX Byte 0 ==
2639 17:34:10.892962 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2640 17:34:10.896322 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2641 17:34:10.899576 == TX Byte 1 ==
2642 17:34:10.902962 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2643 17:34:10.906584 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2644 17:34:10.906669 ==
2645 17:34:10.910193 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 17:34:10.912910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 17:34:10.913002 ==
2648 17:34:10.926772 TX Vref=22, minBit 5, minWin=24, winSum=403
2649 17:34:10.929718 TX Vref=24, minBit 0, minWin=25, winSum=413
2650 17:34:10.933276 TX Vref=26, minBit 0, minWin=25, winSum=416
2651 17:34:10.936740 TX Vref=28, minBit 0, minWin=26, winSum=421
2652 17:34:10.940060 TX Vref=30, minBit 0, minWin=26, winSum=422
2653 17:34:10.943414 TX Vref=32, minBit 4, minWin=25, winSum=421
2654 17:34:10.950195 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
2655 17:34:10.950522
2656 17:34:10.953596 Final TX Range 1 Vref 30
2657 17:34:10.953878
2658 17:34:10.954159 ==
2659 17:34:10.956641 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 17:34:10.960299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 17:34:10.960723 ==
2662 17:34:10.961084
2663 17:34:10.963672
2664 17:34:10.964127 TX Vref Scan disable
2665 17:34:10.966970 == TX Byte 0 ==
2666 17:34:10.970222 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2667 17:34:10.974006 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2668 17:34:10.977229 == TX Byte 1 ==
2669 17:34:10.980416 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2670 17:34:10.983832 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2671 17:34:10.984249
2672 17:34:10.986988 [DATLAT]
2673 17:34:10.987467 Freq=1200, CH0 RK0
2674 17:34:10.987931
2675 17:34:10.990628 DATLAT Default: 0xd
2676 17:34:10.991005 0, 0xFFFF, sum = 0
2677 17:34:10.993679 1, 0xFFFF, sum = 0
2678 17:34:10.994102 2, 0xFFFF, sum = 0
2679 17:34:10.997082 3, 0xFFFF, sum = 0
2680 17:34:10.997597 4, 0xFFFF, sum = 0
2681 17:34:11.000486 5, 0xFFFF, sum = 0
2682 17:34:11.000917 6, 0xFFFF, sum = 0
2683 17:34:11.004007 7, 0xFFFF, sum = 0
2684 17:34:11.004477 8, 0xFFFF, sum = 0
2685 17:34:11.007081 9, 0xFFFF, sum = 0
2686 17:34:11.010132 10, 0xFFFF, sum = 0
2687 17:34:11.010707 11, 0xFFFF, sum = 0
2688 17:34:11.013688 12, 0x0, sum = 1
2689 17:34:11.014156 13, 0x0, sum = 2
2690 17:34:11.014525 14, 0x0, sum = 3
2691 17:34:11.017327 15, 0x0, sum = 4
2692 17:34:11.017750 best_step = 13
2693 17:34:11.018093
2694 17:34:11.018484 ==
2695 17:34:11.020092 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 17:34:11.026710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 17:34:11.027125 ==
2698 17:34:11.027485 RX Vref Scan: 1
2699 17:34:11.027853
2700 17:34:11.030276 Set Vref Range= 32 -> 127
2701 17:34:11.030727
2702 17:34:11.033813 RX Vref 32 -> 127, step: 1
2703 17:34:11.034223
2704 17:34:11.037305 RX Delay -13 -> 252, step: 4
2705 17:34:11.037712
2706 17:34:11.040221 Set Vref, RX VrefLevel [Byte0]: 32
2707 17:34:11.043725 [Byte1]: 32
2708 17:34:11.044155
2709 17:34:11.047191 Set Vref, RX VrefLevel [Byte0]: 33
2710 17:34:11.050583 [Byte1]: 33
2711 17:34:11.050997
2712 17:34:11.053580 Set Vref, RX VrefLevel [Byte0]: 34
2713 17:34:11.056920 [Byte1]: 34
2714 17:34:11.060835
2715 17:34:11.061262 Set Vref, RX VrefLevel [Byte0]: 35
2716 17:34:11.064127 [Byte1]: 35
2717 17:34:11.068897
2718 17:34:11.069303 Set Vref, RX VrefLevel [Byte0]: 36
2719 17:34:11.072047 [Byte1]: 36
2720 17:34:11.076565
2721 17:34:11.076900 Set Vref, RX VrefLevel [Byte0]: 37
2722 17:34:11.079986 [Byte1]: 37
2723 17:34:11.084472
2724 17:34:11.084823 Set Vref, RX VrefLevel [Byte0]: 38
2725 17:34:11.087715 [Byte1]: 38
2726 17:34:11.092339
2727 17:34:11.092836 Set Vref, RX VrefLevel [Byte0]: 39
2728 17:34:11.095554 [Byte1]: 39
2729 17:34:11.100183
2730 17:34:11.100471 Set Vref, RX VrefLevel [Byte0]: 40
2731 17:34:11.103281 [Byte1]: 40
2732 17:34:11.108141
2733 17:34:11.108561 Set Vref, RX VrefLevel [Byte0]: 41
2734 17:34:11.111625 [Byte1]: 41
2735 17:34:11.116103
2736 17:34:11.116391 Set Vref, RX VrefLevel [Byte0]: 42
2737 17:34:11.119388 [Byte1]: 42
2738 17:34:11.123691
2739 17:34:11.123980 Set Vref, RX VrefLevel [Byte0]: 43
2740 17:34:11.127052 [Byte1]: 43
2741 17:34:11.131883
2742 17:34:11.132174 Set Vref, RX VrefLevel [Byte0]: 44
2743 17:34:11.134897 [Byte1]: 44
2744 17:34:11.140032
2745 17:34:11.140325 Set Vref, RX VrefLevel [Byte0]: 45
2746 17:34:11.142669 [Byte1]: 45
2747 17:34:11.147735
2748 17:34:11.148031 Set Vref, RX VrefLevel [Byte0]: 46
2749 17:34:11.151278 [Byte1]: 46
2750 17:34:11.155589
2751 17:34:11.156060 Set Vref, RX VrefLevel [Byte0]: 47
2752 17:34:11.158945 [Byte1]: 47
2753 17:34:11.163863
2754 17:34:11.163943 Set Vref, RX VrefLevel [Byte0]: 48
2755 17:34:11.166281 [Byte1]: 48
2756 17:34:11.170919
2757 17:34:11.171030 Set Vref, RX VrefLevel [Byte0]: 49
2758 17:34:11.174591 [Byte1]: 49
2759 17:34:11.179240
2760 17:34:11.179321 Set Vref, RX VrefLevel [Byte0]: 50
2761 17:34:11.181873 [Byte1]: 50
2762 17:34:11.186495
2763 17:34:11.186577 Set Vref, RX VrefLevel [Byte0]: 51
2764 17:34:11.190362 [Byte1]: 51
2765 17:34:11.194607
2766 17:34:11.194689 Set Vref, RX VrefLevel [Byte0]: 52
2767 17:34:11.198098 [Byte1]: 52
2768 17:34:11.202856
2769 17:34:11.202937 Set Vref, RX VrefLevel [Byte0]: 53
2770 17:34:11.206123 [Byte1]: 53
2771 17:34:11.210115
2772 17:34:11.210197 Set Vref, RX VrefLevel [Byte0]: 54
2773 17:34:11.213553 [Byte1]: 54
2774 17:34:11.218279
2775 17:34:11.218360 Set Vref, RX VrefLevel [Byte0]: 55
2776 17:34:11.221621 [Byte1]: 55
2777 17:34:11.225926
2778 17:34:11.226006 Set Vref, RX VrefLevel [Byte0]: 56
2779 17:34:11.229560 [Byte1]: 56
2780 17:34:11.234174
2781 17:34:11.234279 Set Vref, RX VrefLevel [Byte0]: 57
2782 17:34:11.237322 [Byte1]: 57
2783 17:34:11.242179
2784 17:34:11.242249 Set Vref, RX VrefLevel [Byte0]: 58
2785 17:34:11.245511 [Byte1]: 58
2786 17:34:11.249775
2787 17:34:11.249855 Set Vref, RX VrefLevel [Byte0]: 59
2788 17:34:11.253281 [Byte1]: 59
2789 17:34:11.258104
2790 17:34:11.258191 Set Vref, RX VrefLevel [Byte0]: 60
2791 17:34:11.260906 [Byte1]: 60
2792 17:34:11.265891
2793 17:34:11.265973 Set Vref, RX VrefLevel [Byte0]: 61
2794 17:34:11.268735 [Byte1]: 61
2795 17:34:11.273506
2796 17:34:11.273587 Set Vref, RX VrefLevel [Byte0]: 62
2797 17:34:11.276852 [Byte1]: 62
2798 17:34:11.281574
2799 17:34:11.281656 Set Vref, RX VrefLevel [Byte0]: 63
2800 17:34:11.285115 [Byte1]: 63
2801 17:34:11.289218
2802 17:34:11.289300 Set Vref, RX VrefLevel [Byte0]: 64
2803 17:34:11.292919 [Byte1]: 64
2804 17:34:11.297291
2805 17:34:11.297373 Set Vref, RX VrefLevel [Byte0]: 65
2806 17:34:11.300166 [Byte1]: 65
2807 17:34:11.305397
2808 17:34:11.305522 Set Vref, RX VrefLevel [Byte0]: 66
2809 17:34:11.308698 [Byte1]: 66
2810 17:34:11.313060
2811 17:34:11.313143 Set Vref, RX VrefLevel [Byte0]: 67
2812 17:34:11.316158 [Byte1]: 67
2813 17:34:11.320726
2814 17:34:11.320814 Set Vref, RX VrefLevel [Byte0]: 68
2815 17:34:11.324423 [Byte1]: 68
2816 17:34:11.328834
2817 17:34:11.328915 Set Vref, RX VrefLevel [Byte0]: 69
2818 17:34:11.332335 [Byte1]: 69
2819 17:34:11.336502
2820 17:34:11.336582 Final RX Vref Byte 0 = 56 to rank0
2821 17:34:11.340387 Final RX Vref Byte 1 = 53 to rank0
2822 17:34:11.343509 Final RX Vref Byte 0 = 56 to rank1
2823 17:34:11.346659 Final RX Vref Byte 1 = 53 to rank1==
2824 17:34:11.350296 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 17:34:11.353172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 17:34:11.357074 ==
2827 17:34:11.357179 DQS Delay:
2828 17:34:11.357271 DQS0 = 0, DQS1 = 0
2829 17:34:11.360591 DQM Delay:
2830 17:34:11.360670 DQM0 = 120, DQM1 = 113
2831 17:34:11.363426 DQ Delay:
2832 17:34:11.366773 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2833 17:34:11.370405 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2834 17:34:11.373251 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2835 17:34:11.376718 DQ12 =120, DQ13 =118, DQ14 =124, DQ15 =122
2836 17:34:11.376799
2837 17:34:11.376862
2838 17:34:11.383462 [DQSOSCAuto] RK0, (LSB)MR18= 0x120c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2839 17:34:11.386864 CH0 RK0: MR19=404, MR18=120C
2840 17:34:11.393235 CH0_RK0: MR19=0x404, MR18=0x120C, DQSOSC=403, MR23=63, INC=40, DEC=26
2841 17:34:11.393315
2842 17:34:11.396852 ----->DramcWriteLeveling(PI) begin...
2843 17:34:11.396933 ==
2844 17:34:11.400309 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 17:34:11.403798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 17:34:11.406545 ==
2847 17:34:11.406644 Write leveling (Byte 0): 34 => 34
2848 17:34:11.410590 Write leveling (Byte 1): 29 => 29
2849 17:34:11.414118 DramcWriteLeveling(PI) end<-----
2850 17:34:11.414530
2851 17:34:11.414850 ==
2852 17:34:11.417733 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 17:34:11.424079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 17:34:11.424493 ==
2855 17:34:11.424821 [Gating] SW mode calibration
2856 17:34:11.434368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 17:34:11.437691 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 17:34:11.440668 0 15 0 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
2859 17:34:11.447381 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 17:34:11.450815 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 17:34:11.454066 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 17:34:11.461049 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 17:34:11.464336 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 17:34:11.467393 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 17:34:11.474159 0 15 28 | B1->B0 | 2d2d 2a2a | 1 1 | (1 0) (1 0)
2866 17:34:11.477441 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 17:34:11.480612 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 17:34:11.487907 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 17:34:11.490582 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 17:34:11.494190 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 17:34:11.497640 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 17:34:11.504096 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2873 17:34:11.507546 1 0 28 | B1->B0 | 3d3d 3c3c | 0 1 | (0 0) (0 0)
2874 17:34:11.510967 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2875 17:34:11.517485 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 17:34:11.520981 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 17:34:11.523888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 17:34:11.530871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 17:34:11.534202 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 17:34:11.537927 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 17:34:11.544120 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2882 17:34:11.547421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 17:34:11.550665 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 17:34:11.557155 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 17:34:11.560383 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 17:34:11.564319 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 17:34:11.570486 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 17:34:11.573978 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 17:34:11.577074 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 17:34:11.581054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 17:34:11.587212 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 17:34:11.590927 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 17:34:11.594214 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 17:34:11.600888 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 17:34:11.604270 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 17:34:11.607601 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2897 17:34:11.614656 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2898 17:34:11.617578 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 17:34:11.621099 Total UI for P1: 0, mck2ui 16
2900 17:34:11.624756 best dqsien dly found for B0: ( 1, 3, 28)
2901 17:34:11.627569 Total UI for P1: 0, mck2ui 16
2902 17:34:11.631152 best dqsien dly found for B1: ( 1, 3, 26)
2903 17:34:11.634713 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2904 17:34:11.637872 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2905 17:34:11.638190
2906 17:34:11.641077 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 17:34:11.644850 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2908 17:34:11.648210 [Gating] SW calibration Done
2909 17:34:11.648456 ==
2910 17:34:11.651269 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 17:34:11.654827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 17:34:11.655049 ==
2913 17:34:11.658092 RX Vref Scan: 0
2914 17:34:11.658310
2915 17:34:11.660879 RX Vref 0 -> 0, step: 1
2916 17:34:11.661097
2917 17:34:11.661269 RX Delay -40 -> 252, step: 8
2918 17:34:11.667634 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 17:34:11.671038 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2920 17:34:11.674490 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 17:34:11.677812 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2922 17:34:11.680866 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2923 17:34:11.687893 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2924 17:34:11.690985 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 17:34:11.694345 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2926 17:34:11.697754 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2927 17:34:11.700952 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2928 17:34:11.707713 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2929 17:34:11.711270 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 17:34:11.714613 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2931 17:34:11.718216 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2932 17:34:11.721241 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2933 17:34:11.728216 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2934 17:34:11.728652 ==
2935 17:34:11.731775 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 17:34:11.734429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 17:34:11.734852 ==
2938 17:34:11.735182 DQS Delay:
2939 17:34:11.738306 DQS0 = 0, DQS1 = 0
2940 17:34:11.738721 DQM Delay:
2941 17:34:11.741870 DQM0 = 122, DQM1 = 113
2942 17:34:11.742284 DQ Delay:
2943 17:34:11.744760 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2944 17:34:11.748208 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2945 17:34:11.751723 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
2946 17:34:11.754989 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2947 17:34:11.755419
2948 17:34:11.755920
2949 17:34:11.758318 ==
2950 17:34:11.758776 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 17:34:11.765219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 17:34:11.765652 ==
2953 17:34:11.766087
2954 17:34:11.766497
2955 17:34:11.768099 TX Vref Scan disable
2956 17:34:11.768528 == TX Byte 0 ==
2957 17:34:11.771405 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2958 17:34:11.777815 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2959 17:34:11.778442 == TX Byte 1 ==
2960 17:34:11.781330 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2961 17:34:11.788101 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2962 17:34:11.788763 ==
2963 17:34:11.791460 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 17:34:11.794764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 17:34:11.795410 ==
2966 17:34:11.807312 TX Vref=22, minBit 1, minWin=25, winSum=413
2967 17:34:11.810663 TX Vref=24, minBit 0, minWin=26, winSum=421
2968 17:34:11.813718 TX Vref=26, minBit 0, minWin=26, winSum=424
2969 17:34:11.816974 TX Vref=28, minBit 0, minWin=26, winSum=430
2970 17:34:11.820411 TX Vref=30, minBit 5, minWin=25, winSum=429
2971 17:34:11.823602 TX Vref=32, minBit 2, minWin=26, winSum=429
2972 17:34:11.830365 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
2973 17:34:11.830512
2974 17:34:11.833572 Final TX Range 1 Vref 28
2975 17:34:11.833692
2976 17:34:11.833810 ==
2977 17:34:11.836664 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 17:34:11.839957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 17:34:11.840043 ==
2980 17:34:11.840127
2981 17:34:11.840207
2982 17:34:11.843316 TX Vref Scan disable
2983 17:34:11.846797 == TX Byte 0 ==
2984 17:34:11.850279 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2985 17:34:11.853697 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2986 17:34:11.857135 == TX Byte 1 ==
2987 17:34:11.860521 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2988 17:34:11.863949 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2989 17:34:11.864034
2990 17:34:11.866790 [DATLAT]
2991 17:34:11.866873 Freq=1200, CH0 RK1
2992 17:34:11.866959
2993 17:34:11.870447 DATLAT Default: 0xd
2994 17:34:11.870532 0, 0xFFFF, sum = 0
2995 17:34:11.873917 1, 0xFFFF, sum = 0
2996 17:34:11.874002 2, 0xFFFF, sum = 0
2997 17:34:11.876729 3, 0xFFFF, sum = 0
2998 17:34:11.876815 4, 0xFFFF, sum = 0
2999 17:34:11.880215 5, 0xFFFF, sum = 0
3000 17:34:11.880301 6, 0xFFFF, sum = 0
3001 17:34:11.883358 7, 0xFFFF, sum = 0
3002 17:34:11.883524 8, 0xFFFF, sum = 0
3003 17:34:11.886623 9, 0xFFFF, sum = 0
3004 17:34:11.886717 10, 0xFFFF, sum = 0
3005 17:34:11.890143 11, 0xFFFF, sum = 0
3006 17:34:11.890230 12, 0x0, sum = 1
3007 17:34:11.893511 13, 0x0, sum = 2
3008 17:34:11.893597 14, 0x0, sum = 3
3009 17:34:11.896976 15, 0x0, sum = 4
3010 17:34:11.897060 best_step = 13
3011 17:34:11.897124
3012 17:34:11.897183 ==
3013 17:34:11.900391 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 17:34:11.906980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 17:34:11.907066 ==
3016 17:34:11.907130 RX Vref Scan: 0
3017 17:34:11.907190
3018 17:34:11.910160 RX Vref 0 -> 0, step: 1
3019 17:34:11.910242
3020 17:34:11.913392 RX Delay -13 -> 252, step: 4
3021 17:34:11.917265 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3022 17:34:11.920429 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3023 17:34:11.926801 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3024 17:34:11.929985 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3025 17:34:11.933882 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3026 17:34:11.936707 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3027 17:34:11.940273 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3028 17:34:11.947336 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3029 17:34:11.950135 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3030 17:34:11.953784 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3031 17:34:11.957089 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3032 17:34:11.960544 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3033 17:34:11.967401 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3034 17:34:11.970086 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3035 17:34:11.973579 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3036 17:34:11.977067 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3037 17:34:11.977150 ==
3038 17:34:11.980665 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 17:34:11.984089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 17:34:11.987567 ==
3041 17:34:11.987656 DQS Delay:
3042 17:34:11.987722 DQS0 = 0, DQS1 = 0
3043 17:34:11.990323 DQM Delay:
3044 17:34:11.990405 DQM0 = 121, DQM1 = 111
3045 17:34:11.994121 DQ Delay:
3046 17:34:11.997351 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3047 17:34:12.000614 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3048 17:34:12.003500 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3049 17:34:12.006783 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3050 17:34:12.006866
3051 17:34:12.006929
3052 17:34:12.013763 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3053 17:34:12.016893 CH0 RK1: MR19=403, MR18=CED
3054 17:34:12.023559 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3055 17:34:12.026921 [RxdqsGatingPostProcess] freq 1200
3056 17:34:12.034032 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 17:34:12.034117 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 17:34:12.037068 best DQS1 dly(2T, 0.5T) = (0, 11)
3059 17:34:12.040500 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 17:34:12.043445 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3061 17:34:12.046926 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 17:34:12.050361 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 17:34:12.053634 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 17:34:12.057035 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 17:34:12.060288 Pre-setting of DQS Precalculation
3066 17:34:12.063955 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 17:34:12.066971 ==
3068 17:34:12.070772 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 17:34:12.074086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 17:34:12.074254 ==
3071 17:34:12.077485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 17:34:12.083599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3073 17:34:12.092673 [CA 0] Center 37 (7~68) winsize 62
3074 17:34:12.096030 [CA 1] Center 37 (7~68) winsize 62
3075 17:34:12.100064 [CA 2] Center 35 (5~65) winsize 61
3076 17:34:12.103360 [CA 3] Center 34 (4~65) winsize 62
3077 17:34:12.106618 [CA 4] Center 34 (5~64) winsize 60
3078 17:34:12.109818 [CA 5] Center 33 (3~63) winsize 61
3079 17:34:12.109907
3080 17:34:12.113464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3081 17:34:12.113636
3082 17:34:12.116222 [CATrainingPosCal] consider 1 rank data
3083 17:34:12.119623 u2DelayCellTimex100 = 270/100 ps
3084 17:34:12.123092 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 17:34:12.126257 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 17:34:12.129610 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 17:34:12.136613 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 17:34:12.140031 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3089 17:34:12.143389 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3090 17:34:12.143482
3091 17:34:12.146560 CA PerBit enable=1, Macro0, CA PI delay=33
3092 17:34:12.146693
3093 17:34:12.149795 [CBTSetCACLKResult] CA Dly = 33
3094 17:34:12.149907 CS Dly: 8 (0~39)
3095 17:34:12.149999 ==
3096 17:34:12.153397 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 17:34:12.159870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 17:34:12.159957 ==
3099 17:34:12.163474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 17:34:12.169783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3101 17:34:12.178441 [CA 0] Center 37 (7~68) winsize 62
3102 17:34:12.181990 [CA 1] Center 37 (7~68) winsize 62
3103 17:34:12.185254 [CA 2] Center 35 (5~66) winsize 62
3104 17:34:12.188750 [CA 3] Center 34 (4~65) winsize 62
3105 17:34:12.192196 [CA 4] Center 34 (4~65) winsize 62
3106 17:34:12.195090 [CA 5] Center 33 (4~63) winsize 60
3107 17:34:12.195172
3108 17:34:12.198525 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3109 17:34:12.198643
3110 17:34:12.201947 [CATrainingPosCal] consider 2 rank data
3111 17:34:12.205192 u2DelayCellTimex100 = 270/100 ps
3112 17:34:12.208517 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 17:34:12.211797 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3114 17:34:12.215789 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3115 17:34:12.221980 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3116 17:34:12.225483 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3117 17:34:12.228853 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3118 17:34:12.228960
3119 17:34:12.232174 CA PerBit enable=1, Macro0, CA PI delay=33
3120 17:34:12.232283
3121 17:34:12.235543 [CBTSetCACLKResult] CA Dly = 33
3122 17:34:12.235673 CS Dly: 9 (0~41)
3123 17:34:12.235772
3124 17:34:12.238639 ----->DramcWriteLeveling(PI) begin...
3125 17:34:12.241993 ==
3126 17:34:12.242116 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 17:34:12.248980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 17:34:12.249098 ==
3129 17:34:12.252434 Write leveling (Byte 0): 28 => 28
3130 17:34:12.256229 Write leveling (Byte 1): 30 => 30
3131 17:34:12.256359 DramcWriteLeveling(PI) end<-----
3132 17:34:12.258991
3133 17:34:12.259097 ==
3134 17:34:12.263301 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 17:34:12.265561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 17:34:12.265685 ==
3137 17:34:12.268885 [Gating] SW mode calibration
3138 17:34:12.275358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 17:34:12.278879 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 17:34:12.285805 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3141 17:34:12.288479 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 17:34:12.292373 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 17:34:12.298977 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 17:34:12.302205 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 17:34:12.305600 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 17:34:12.312340 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
3147 17:34:12.315803 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3148 17:34:12.319203 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 17:34:12.325884 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 17:34:12.328605 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 17:34:12.332008 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 17:34:12.335488 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 17:34:12.342399 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3154 17:34:12.345849 1 0 24 | B1->B0 | 3636 4141 | 0 0 | (1 1) (0 0)
3155 17:34:12.348625 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 17:34:12.355598 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 17:34:12.359061 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 17:34:12.362601 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 17:34:12.369406 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 17:34:12.372210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 17:34:12.375770 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 17:34:12.382077 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 17:34:12.385409 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3164 17:34:12.389306 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 17:34:12.395353 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 17:34:12.399142 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 17:34:12.402524 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 17:34:12.408923 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 17:34:12.412209 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 17:34:12.415552 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 17:34:12.422247 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 17:34:12.425866 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 17:34:12.429188 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 17:34:12.432578 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 17:34:12.439007 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 17:34:12.442489 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 17:34:12.445822 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 17:34:12.452293 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 17:34:12.455742 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3180 17:34:12.459383 Total UI for P1: 0, mck2ui 16
3181 17:34:12.462117 best dqsien dly found for B1: ( 1, 3, 24)
3182 17:34:12.465594 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 17:34:12.469182 Total UI for P1: 0, mck2ui 16
3184 17:34:12.472540 best dqsien dly found for B0: ( 1, 3, 26)
3185 17:34:12.476031 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3186 17:34:12.478806 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3187 17:34:12.478938
3188 17:34:12.485890 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3189 17:34:12.488679 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3190 17:34:12.488783 [Gating] SW calibration Done
3191 17:34:12.492249 ==
3192 17:34:12.492355 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 17:34:12.499252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 17:34:12.499366 ==
3195 17:34:12.499461 RX Vref Scan: 0
3196 17:34:12.499549
3197 17:34:12.502525 RX Vref 0 -> 0, step: 1
3198 17:34:12.502625
3199 17:34:12.505695 RX Delay -40 -> 252, step: 8
3200 17:34:12.509394 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3201 17:34:12.512627 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3202 17:34:12.515761 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3203 17:34:12.522583 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3204 17:34:12.525987 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3205 17:34:12.529369 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3206 17:34:12.532440 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3207 17:34:12.536182 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3208 17:34:12.542861 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3209 17:34:12.545770 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3210 17:34:12.549065 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3211 17:34:12.552452 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3212 17:34:12.555930 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3213 17:34:12.562413 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3214 17:34:12.565914 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3215 17:34:12.569314 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3216 17:34:12.569399 ==
3217 17:34:12.572779 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 17:34:12.576195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 17:34:12.576303 ==
3220 17:34:12.578938 DQS Delay:
3221 17:34:12.579016 DQS0 = 0, DQS1 = 0
3222 17:34:12.582563 DQM Delay:
3223 17:34:12.582649 DQM0 = 120, DQM1 = 116
3224 17:34:12.582734 DQ Delay:
3225 17:34:12.586054 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3226 17:34:12.592779 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3227 17:34:12.595477 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3228 17:34:12.599069 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3229 17:34:12.599221
3230 17:34:12.599338
3231 17:34:12.599438 ==
3232 17:34:12.602599 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 17:34:12.606082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 17:34:12.606169 ==
3235 17:34:12.606231
3236 17:34:12.606289
3237 17:34:12.609447 TX Vref Scan disable
3238 17:34:12.612775 == TX Byte 0 ==
3239 17:34:12.616046 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 17:34:12.619362 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 17:34:12.622507 == TX Byte 1 ==
3242 17:34:12.625850 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3243 17:34:12.628970 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3244 17:34:12.629178 ==
3245 17:34:12.632361 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 17:34:12.635659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 17:34:12.635785 ==
3248 17:34:12.649498 TX Vref=22, minBit 9, minWin=24, winSum=409
3249 17:34:12.652278 TX Vref=24, minBit 1, minWin=25, winSum=416
3250 17:34:12.655386 TX Vref=26, minBit 1, minWin=25, winSum=421
3251 17:34:12.658724 TX Vref=28, minBit 1, minWin=26, winSum=427
3252 17:34:12.662100 TX Vref=30, minBit 1, minWin=26, winSum=432
3253 17:34:12.665657 TX Vref=32, minBit 9, minWin=26, winSum=431
3254 17:34:12.671998 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3255 17:34:12.672088
3256 17:34:12.675816 Final TX Range 1 Vref 30
3257 17:34:12.675896
3258 17:34:12.675958 ==
3259 17:34:12.679067 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 17:34:12.681850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 17:34:12.681949 ==
3262 17:34:12.685274
3263 17:34:12.685360
3264 17:34:12.685424 TX Vref Scan disable
3265 17:34:12.688631 == TX Byte 0 ==
3266 17:34:12.691933 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3267 17:34:12.695239 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3268 17:34:12.698608 == TX Byte 1 ==
3269 17:34:12.702052 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3270 17:34:12.705395 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3271 17:34:12.705467
3272 17:34:12.708789 [DATLAT]
3273 17:34:12.708860 Freq=1200, CH1 RK0
3274 17:34:12.708936
3275 17:34:12.712232 DATLAT Default: 0xd
3276 17:34:12.712302 0, 0xFFFF, sum = 0
3277 17:34:12.715792 1, 0xFFFF, sum = 0
3278 17:34:12.715874 2, 0xFFFF, sum = 0
3279 17:34:12.718506 3, 0xFFFF, sum = 0
3280 17:34:12.718587 4, 0xFFFF, sum = 0
3281 17:34:12.722550 5, 0xFFFF, sum = 0
3282 17:34:12.722658 6, 0xFFFF, sum = 0
3283 17:34:12.725330 7, 0xFFFF, sum = 0
3284 17:34:12.725412 8, 0xFFFF, sum = 0
3285 17:34:12.728641 9, 0xFFFF, sum = 0
3286 17:34:12.732243 10, 0xFFFF, sum = 0
3287 17:34:12.732323 11, 0xFFFF, sum = 0
3288 17:34:12.735879 12, 0x0, sum = 1
3289 17:34:12.735959 13, 0x0, sum = 2
3290 17:34:12.736023 14, 0x0, sum = 3
3291 17:34:12.739083 15, 0x0, sum = 4
3292 17:34:12.739206 best_step = 13
3293 17:34:12.739302
3294 17:34:12.742484 ==
3295 17:34:12.742560 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 17:34:12.748667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 17:34:12.748746 ==
3298 17:34:12.748810 RX Vref Scan: 1
3299 17:34:12.748869
3300 17:34:12.752078 Set Vref Range= 32 -> 127
3301 17:34:12.752155
3302 17:34:12.755392 RX Vref 32 -> 127, step: 1
3303 17:34:12.755489
3304 17:34:12.758967 RX Delay -5 -> 252, step: 4
3305 17:34:12.759055
3306 17:34:12.762538 Set Vref, RX VrefLevel [Byte0]: 32
3307 17:34:12.765417 [Byte1]: 32
3308 17:34:12.765499
3309 17:34:12.768801 Set Vref, RX VrefLevel [Byte0]: 33
3310 17:34:12.772286 [Byte1]: 33
3311 17:34:12.772369
3312 17:34:12.775617 Set Vref, RX VrefLevel [Byte0]: 34
3313 17:34:12.779169 [Byte1]: 34
3314 17:34:12.782966
3315 17:34:12.783040 Set Vref, RX VrefLevel [Byte0]: 35
3316 17:34:12.786154 [Byte1]: 35
3317 17:34:12.790444
3318 17:34:12.790551 Set Vref, RX VrefLevel [Byte0]: 36
3319 17:34:12.794023 [Byte1]: 36
3320 17:34:12.798710
3321 17:34:12.798789 Set Vref, RX VrefLevel [Byte0]: 37
3322 17:34:12.801578 [Byte1]: 37
3323 17:34:12.806371
3324 17:34:12.806450 Set Vref, RX VrefLevel [Byte0]: 38
3325 17:34:12.809655 [Byte1]: 38
3326 17:34:12.813743
3327 17:34:12.813850 Set Vref, RX VrefLevel [Byte0]: 39
3328 17:34:12.817288 [Byte1]: 39
3329 17:34:12.821925
3330 17:34:12.822017 Set Vref, RX VrefLevel [Byte0]: 40
3331 17:34:12.825134 [Byte1]: 40
3332 17:34:12.829909
3333 17:34:12.829982 Set Vref, RX VrefLevel [Byte0]: 41
3334 17:34:12.833326 [Byte1]: 41
3335 17:34:12.837640
3336 17:34:12.837712 Set Vref, RX VrefLevel [Byte0]: 42
3337 17:34:12.840796 [Byte1]: 42
3338 17:34:12.845463
3339 17:34:12.845550 Set Vref, RX VrefLevel [Byte0]: 43
3340 17:34:12.848760 [Byte1]: 43
3341 17:34:12.853098
3342 17:34:12.853221 Set Vref, RX VrefLevel [Byte0]: 44
3343 17:34:12.856925 [Byte1]: 44
3344 17:34:12.861087
3345 17:34:12.861168 Set Vref, RX VrefLevel [Byte0]: 45
3346 17:34:12.864650 [Byte1]: 45
3347 17:34:12.868899
3348 17:34:12.869009 Set Vref, RX VrefLevel [Byte0]: 46
3349 17:34:12.872416 [Byte1]: 46
3350 17:34:12.876582
3351 17:34:12.876663 Set Vref, RX VrefLevel [Byte0]: 47
3352 17:34:12.880101 [Byte1]: 47
3353 17:34:12.884919
3354 17:34:12.884999 Set Vref, RX VrefLevel [Byte0]: 48
3355 17:34:12.887735 [Byte1]: 48
3356 17:34:12.892489
3357 17:34:12.892647 Set Vref, RX VrefLevel [Byte0]: 49
3358 17:34:12.895957 [Byte1]: 49
3359 17:34:12.900806
3360 17:34:12.900916 Set Vref, RX VrefLevel [Byte0]: 50
3361 17:34:12.904001 [Byte1]: 50
3362 17:34:12.908754
3363 17:34:12.908885 Set Vref, RX VrefLevel [Byte0]: 51
3364 17:34:12.911611 [Byte1]: 51
3365 17:34:12.916509
3366 17:34:12.916589 Set Vref, RX VrefLevel [Byte0]: 52
3367 17:34:12.919557 [Byte1]: 52
3368 17:34:12.923919
3369 17:34:12.923999 Set Vref, RX VrefLevel [Byte0]: 53
3370 17:34:12.927527 [Byte1]: 53
3371 17:34:12.931596
3372 17:34:12.931724 Set Vref, RX VrefLevel [Byte0]: 54
3373 17:34:12.935418 [Byte1]: 54
3374 17:34:12.939866
3375 17:34:12.939950 Set Vref, RX VrefLevel [Byte0]: 55
3376 17:34:12.943295 [Byte1]: 55
3377 17:34:12.947551
3378 17:34:12.947676 Set Vref, RX VrefLevel [Byte0]: 56
3379 17:34:12.950998 [Byte1]: 56
3380 17:34:12.955112
3381 17:34:12.955191 Set Vref, RX VrefLevel [Byte0]: 57
3382 17:34:12.958454 [Byte1]: 57
3383 17:34:12.963162
3384 17:34:12.963236 Set Vref, RX VrefLevel [Byte0]: 58
3385 17:34:12.966270 [Byte1]: 58
3386 17:34:12.971282
3387 17:34:12.971364 Set Vref, RX VrefLevel [Byte0]: 59
3388 17:34:12.974622 [Byte1]: 59
3389 17:34:12.978748
3390 17:34:12.978843 Set Vref, RX VrefLevel [Byte0]: 60
3391 17:34:12.982232 [Byte1]: 60
3392 17:34:12.987059
3393 17:34:12.987143 Set Vref, RX VrefLevel [Byte0]: 61
3394 17:34:12.990539 [Byte1]: 61
3395 17:34:12.994739
3396 17:34:12.994815 Set Vref, RX VrefLevel [Byte0]: 62
3397 17:34:12.998070 [Byte1]: 62
3398 17:34:13.002255
3399 17:34:13.002363 Set Vref, RX VrefLevel [Byte0]: 63
3400 17:34:13.005745 [Byte1]: 63
3401 17:34:13.010510
3402 17:34:13.010616 Set Vref, RX VrefLevel [Byte0]: 64
3403 17:34:13.013368 [Byte1]: 64
3404 17:34:13.018057
3405 17:34:13.018138 Set Vref, RX VrefLevel [Byte0]: 65
3406 17:34:13.021272 [Byte1]: 65
3407 17:34:13.026024
3408 17:34:13.026110 Set Vref, RX VrefLevel [Byte0]: 66
3409 17:34:13.029323 [Byte1]: 66
3410 17:34:13.033988
3411 17:34:13.034096 Set Vref, RX VrefLevel [Byte0]: 67
3412 17:34:13.037246 [Byte1]: 67
3413 17:34:13.041506
3414 17:34:13.041586 Set Vref, RX VrefLevel [Byte0]: 68
3415 17:34:13.045186 [Byte1]: 68
3416 17:34:13.049872
3417 17:34:13.049952 Final RX Vref Byte 0 = 54 to rank0
3418 17:34:13.053104 Final RX Vref Byte 1 = 46 to rank0
3419 17:34:13.056032 Final RX Vref Byte 0 = 54 to rank1
3420 17:34:13.059621 Final RX Vref Byte 1 = 46 to rank1==
3421 17:34:13.063497 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 17:34:13.066985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 17:34:13.070220 ==
3424 17:34:13.070372 DQS Delay:
3425 17:34:13.070459 DQS0 = 0, DQS1 = 0
3426 17:34:13.073552 DQM Delay:
3427 17:34:13.073677 DQM0 = 120, DQM1 = 115
3428 17:34:13.076847 DQ Delay:
3429 17:34:13.079949 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3430 17:34:13.082978 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3431 17:34:13.086642 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =108
3432 17:34:13.089715 DQ12 =122, DQ13 =120, DQ14 =124, DQ15 =126
3433 17:34:13.089879
3434 17:34:13.089958
3435 17:34:13.096498 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3436 17:34:13.099983 CH1 RK0: MR19=404, MR18=13
3437 17:34:13.106941 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3438 17:34:13.107501
3439 17:34:13.109872 ----->DramcWriteLeveling(PI) begin...
3440 17:34:13.110456 ==
3441 17:34:13.113153 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 17:34:13.116839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 17:34:13.117259 ==
3444 17:34:13.120336 Write leveling (Byte 0): 26 => 26
3445 17:34:13.123736 Write leveling (Byte 1): 29 => 29
3446 17:34:13.126404 DramcWriteLeveling(PI) end<-----
3447 17:34:13.126976
3448 17:34:13.127374 ==
3449 17:34:13.130423 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 17:34:13.133780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 17:34:13.136446 ==
3452 17:34:13.136985 [Gating] SW mode calibration
3453 17:34:13.143425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 17:34:13.150329 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 17:34:13.153487 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 17:34:13.160097 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 17:34:13.163231 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 17:34:13.166349 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 17:34:13.172835 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 17:34:13.176657 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3461 17:34:13.179868 0 15 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 1) (0 0)
3462 17:34:13.186531 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3463 17:34:13.189761 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 17:34:13.192810 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 17:34:13.196268 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 17:34:13.203194 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 17:34:13.206648 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 17:34:13.210118 1 0 20 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
3469 17:34:13.216323 1 0 24 | B1->B0 | 4242 2f2f | 0 0 | (0 0) (0 0)
3470 17:34:13.219785 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 17:34:13.223293 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 17:34:13.229516 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 17:34:13.232779 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 17:34:13.236141 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 17:34:13.242988 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 17:34:13.246478 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 17:34:13.249294 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3478 17:34:13.256095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3479 17:34:13.259544 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 17:34:13.263110 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 17:34:13.269468 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 17:34:13.273001 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 17:34:13.276178 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 17:34:13.282910 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 17:34:13.286539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 17:34:13.289769 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 17:34:13.296268 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 17:34:13.299591 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 17:34:13.302895 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 17:34:13.309326 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 17:34:13.313288 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 17:34:13.316659 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3493 17:34:13.319363 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3494 17:34:13.326523 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3495 17:34:13.330005 Total UI for P1: 0, mck2ui 16
3496 17:34:13.332885 best dqsien dly found for B1: ( 1, 3, 22)
3497 17:34:13.336402 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 17:34:13.339813 Total UI for P1: 0, mck2ui 16
3499 17:34:13.343231 best dqsien dly found for B0: ( 1, 3, 28)
3500 17:34:13.346370 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3501 17:34:13.349499 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3502 17:34:13.349989
3503 17:34:13.352897 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3504 17:34:13.356386 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3505 17:34:13.359604 [Gating] SW calibration Done
3506 17:34:13.360054 ==
3507 17:34:13.362988 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 17:34:13.369502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 17:34:13.370085 ==
3510 17:34:13.370646 RX Vref Scan: 0
3511 17:34:13.371131
3512 17:34:13.372617 RX Vref 0 -> 0, step: 1
3513 17:34:13.373195
3514 17:34:13.376075 RX Delay -40 -> 252, step: 8
3515 17:34:13.379741 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3516 17:34:13.383150 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3517 17:34:13.386648 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3518 17:34:13.389917 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3519 17:34:13.396095 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3520 17:34:13.400140 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3521 17:34:13.402984 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3522 17:34:13.406770 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3523 17:34:13.409761 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3524 17:34:13.416015 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3525 17:34:13.419399 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3526 17:34:13.422737 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3527 17:34:13.426397 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3528 17:34:13.429386 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3529 17:34:13.436158 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3530 17:34:13.439570 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3531 17:34:13.440048 ==
3532 17:34:13.443174 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 17:34:13.445961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 17:34:13.446435 ==
3535 17:34:13.449323 DQS Delay:
3536 17:34:13.449747 DQS0 = 0, DQS1 = 0
3537 17:34:13.450174 DQM Delay:
3538 17:34:13.452878 DQM0 = 121, DQM1 = 118
3539 17:34:13.453317 DQ Delay:
3540 17:34:13.456179 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3541 17:34:13.459416 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3542 17:34:13.465770 DQ8 =107, DQ9 =103, DQ10 =119, DQ11 =115
3543 17:34:13.469259 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127
3544 17:34:13.469683
3545 17:34:13.470147
3546 17:34:13.470644 ==
3547 17:34:13.472673 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 17:34:13.475883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 17:34:13.476499 ==
3550 17:34:13.477047
3551 17:34:13.477388
3552 17:34:13.479421 TX Vref Scan disable
3553 17:34:13.482854 == TX Byte 0 ==
3554 17:34:13.485867 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 17:34:13.489145 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 17:34:13.492674 == TX Byte 1 ==
3557 17:34:13.496365 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3558 17:34:13.499367 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3559 17:34:13.500202 ==
3560 17:34:13.502748 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 17:34:13.505738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 17:34:13.506151 ==
3563 17:34:13.519208 TX Vref=22, minBit 9, minWin=25, winSum=419
3564 17:34:13.522598 TX Vref=24, minBit 2, minWin=26, winSum=425
3565 17:34:13.525604 TX Vref=26, minBit 1, minWin=26, winSum=427
3566 17:34:13.529065 TX Vref=28, minBit 9, minWin=26, winSum=433
3567 17:34:13.532363 TX Vref=30, minBit 10, minWin=25, winSum=435
3568 17:34:13.538834 TX Vref=32, minBit 9, minWin=26, winSum=437
3569 17:34:13.541981 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 32
3570 17:34:13.542510
3571 17:34:13.545678 Final TX Range 1 Vref 32
3572 17:34:13.546027
3573 17:34:13.546265 ==
3574 17:34:13.549132 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 17:34:13.551762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 17:34:13.552078 ==
3577 17:34:13.555260
3578 17:34:13.555493
3579 17:34:13.555696 TX Vref Scan disable
3580 17:34:13.558663 == TX Byte 0 ==
3581 17:34:13.561588 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3582 17:34:13.564942 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3583 17:34:13.568605 == TX Byte 1 ==
3584 17:34:13.571863 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3585 17:34:13.575226 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3586 17:34:13.578505
3587 17:34:13.578631 [DATLAT]
3588 17:34:13.578747 Freq=1200, CH1 RK1
3589 17:34:13.578825
3590 17:34:13.581791 DATLAT Default: 0xd
3591 17:34:13.581883 0, 0xFFFF, sum = 0
3592 17:34:13.585248 1, 0xFFFF, sum = 0
3593 17:34:13.585341 2, 0xFFFF, sum = 0
3594 17:34:13.588663 3, 0xFFFF, sum = 0
3595 17:34:13.591409 4, 0xFFFF, sum = 0
3596 17:34:13.591491 5, 0xFFFF, sum = 0
3597 17:34:13.595011 6, 0xFFFF, sum = 0
3598 17:34:13.595093 7, 0xFFFF, sum = 0
3599 17:34:13.598399 8, 0xFFFF, sum = 0
3600 17:34:13.598482 9, 0xFFFF, sum = 0
3601 17:34:13.601868 10, 0xFFFF, sum = 0
3602 17:34:13.601950 11, 0xFFFF, sum = 0
3603 17:34:13.605272 12, 0x0, sum = 1
3604 17:34:13.605381 13, 0x0, sum = 2
3605 17:34:13.608331 14, 0x0, sum = 3
3606 17:34:13.608436 15, 0x0, sum = 4
3607 17:34:13.608529 best_step = 13
3608 17:34:13.611633
3609 17:34:13.611770 ==
3610 17:34:13.615067 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 17:34:13.618468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 17:34:13.618550 ==
3613 17:34:13.618614 RX Vref Scan: 0
3614 17:34:13.618693
3615 17:34:13.621800 RX Vref 0 -> 0, step: 1
3616 17:34:13.621881
3617 17:34:13.624587 RX Delay -5 -> 252, step: 4
3618 17:34:13.627923 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3619 17:34:13.634553 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3620 17:34:13.638272 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3621 17:34:13.641579 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3622 17:34:13.644912 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3623 17:34:13.648388 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3624 17:34:13.654859 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3625 17:34:13.658389 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3626 17:34:13.661851 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3627 17:34:13.664709 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3628 17:34:13.668222 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3629 17:34:13.674924 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3630 17:34:13.678254 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3631 17:34:13.681618 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3632 17:34:13.685066 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3633 17:34:13.688289 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3634 17:34:13.688734 ==
3635 17:34:13.691767 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 17:34:13.698688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 17:34:13.699131 ==
3638 17:34:13.699440 DQS Delay:
3639 17:34:13.702226 DQS0 = 0, DQS1 = 0
3640 17:34:13.702659 DQM Delay:
3641 17:34:13.704968 DQM0 = 120, DQM1 = 116
3642 17:34:13.705415 DQ Delay:
3643 17:34:13.708391 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3644 17:34:13.711744 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3645 17:34:13.715023 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3646 17:34:13.717996 DQ12 =126, DQ13 =124, DQ14 =120, DQ15 =124
3647 17:34:13.718297
3648 17:34:13.718616
3649 17:34:13.727876 [DQSOSCAuto] RK1, (LSB)MR18= 0xce9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 405 ps
3650 17:34:13.728052 CH1 RK1: MR19=403, MR18=CE9
3651 17:34:13.734654 CH1_RK1: MR19=0x403, MR18=0xCE9, DQSOSC=405, MR23=63, INC=39, DEC=26
3652 17:34:13.737549 [RxdqsGatingPostProcess] freq 1200
3653 17:34:13.744258 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3654 17:34:13.747465 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 17:34:13.751259 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 17:34:13.754222 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 17:34:13.757638 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 17:34:13.761011 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 17:34:13.764410 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 17:34:13.767560 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 17:34:13.771092 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 17:34:13.771176 Pre-setting of DQS Precalculation
3663 17:34:13.777320 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3664 17:34:13.783886 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3665 17:34:13.790434 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3666 17:34:13.790519
3667 17:34:13.790584
3668 17:34:13.793653 [Calibration Summary] 2400 Mbps
3669 17:34:13.797559 CH 0, Rank 0
3670 17:34:13.797642 SW Impedance : PASS
3671 17:34:13.800457 DUTY Scan : NO K
3672 17:34:13.804011 ZQ Calibration : PASS
3673 17:34:13.804094 Jitter Meter : NO K
3674 17:34:13.806859 CBT Training : PASS
3675 17:34:13.810367 Write leveling : PASS
3676 17:34:13.810450 RX DQS gating : PASS
3677 17:34:13.813819 RX DQ/DQS(RDDQC) : PASS
3678 17:34:13.817256 TX DQ/DQS : PASS
3679 17:34:13.817340 RX DATLAT : PASS
3680 17:34:13.820688 RX DQ/DQS(Engine): PASS
3681 17:34:13.820771 TX OE : NO K
3682 17:34:13.823917 All Pass.
3683 17:34:13.823999
3684 17:34:13.824065 CH 0, Rank 1
3685 17:34:13.827141 SW Impedance : PASS
3686 17:34:13.827224 DUTY Scan : NO K
3687 17:34:13.830228 ZQ Calibration : PASS
3688 17:34:13.833871 Jitter Meter : NO K
3689 17:34:13.833954 CBT Training : PASS
3690 17:34:13.836635 Write leveling : PASS
3691 17:34:13.840179 RX DQS gating : PASS
3692 17:34:13.840262 RX DQ/DQS(RDDQC) : PASS
3693 17:34:13.843597 TX DQ/DQS : PASS
3694 17:34:13.846976 RX DATLAT : PASS
3695 17:34:13.847058 RX DQ/DQS(Engine): PASS
3696 17:34:13.850605 TX OE : NO K
3697 17:34:13.850687 All Pass.
3698 17:34:13.850753
3699 17:34:13.853336 CH 1, Rank 0
3700 17:34:13.853419 SW Impedance : PASS
3701 17:34:13.856674 DUTY Scan : NO K
3702 17:34:13.860019 ZQ Calibration : PASS
3703 17:34:13.860102 Jitter Meter : NO K
3704 17:34:13.863828 CBT Training : PASS
3705 17:34:13.866602 Write leveling : PASS
3706 17:34:13.866684 RX DQS gating : PASS
3707 17:34:13.870081 RX DQ/DQS(RDDQC) : PASS
3708 17:34:13.870163 TX DQ/DQS : PASS
3709 17:34:13.873534 RX DATLAT : PASS
3710 17:34:13.876822 RX DQ/DQS(Engine): PASS
3711 17:34:13.876903 TX OE : NO K
3712 17:34:13.879996 All Pass.
3713 17:34:13.880076
3714 17:34:13.880140 CH 1, Rank 1
3715 17:34:13.883779 SW Impedance : PASS
3716 17:34:13.883860 DUTY Scan : NO K
3717 17:34:13.886534 ZQ Calibration : PASS
3718 17:34:13.889853 Jitter Meter : NO K
3719 17:34:13.889935 CBT Training : PASS
3720 17:34:13.893228 Write leveling : PASS
3721 17:34:13.896584 RX DQS gating : PASS
3722 17:34:13.896665 RX DQ/DQS(RDDQC) : PASS
3723 17:34:13.899825 TX DQ/DQS : PASS
3724 17:34:13.902928 RX DATLAT : PASS
3725 17:34:13.903009 RX DQ/DQS(Engine): PASS
3726 17:34:13.906921 TX OE : NO K
3727 17:34:13.907021 All Pass.
3728 17:34:13.907100
3729 17:34:13.909790 DramC Write-DBI off
3730 17:34:13.913283 PER_BANK_REFRESH: Hybrid Mode
3731 17:34:13.913364 TX_TRACKING: ON
3732 17:34:13.923683 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3733 17:34:13.926499 [FAST_K] Save calibration result to emmc
3734 17:34:13.929932 dramc_set_vcore_voltage set vcore to 650000
3735 17:34:13.933327 Read voltage for 600, 5
3736 17:34:13.933408 Vio18 = 0
3737 17:34:13.933472 Vcore = 650000
3738 17:34:13.936563 Vdram = 0
3739 17:34:13.936644 Vddq = 0
3740 17:34:13.936707 Vmddr = 0
3741 17:34:13.943417 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3742 17:34:13.946595 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3743 17:34:13.950023 MEM_TYPE=3, freq_sel=19
3744 17:34:13.953324 sv_algorithm_assistance_LP4_1600
3745 17:34:13.956879 ============ PULL DRAM RESETB DOWN ============
3746 17:34:13.959700 ========== PULL DRAM RESETB DOWN end =========
3747 17:34:13.966666 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 17:34:13.970079 ===================================
3749 17:34:13.970161 LPDDR4 DRAM CONFIGURATION
3750 17:34:13.973243 ===================================
3751 17:34:13.976566 EX_ROW_EN[0] = 0x0
3752 17:34:13.979777 EX_ROW_EN[1] = 0x0
3753 17:34:13.979861 LP4Y_EN = 0x0
3754 17:34:13.983463 WORK_FSP = 0x0
3755 17:34:13.983580 WL = 0x2
3756 17:34:13.986614 RL = 0x2
3757 17:34:13.986733 BL = 0x2
3758 17:34:13.989635 RPST = 0x0
3759 17:34:13.989735 RD_PRE = 0x0
3760 17:34:13.992860 WR_PRE = 0x1
3761 17:34:13.992940 WR_PST = 0x0
3762 17:34:13.996701 DBI_WR = 0x0
3763 17:34:13.996796 DBI_RD = 0x0
3764 17:34:13.999489 OTF = 0x1
3765 17:34:14.002883 ===================================
3766 17:34:14.006194 ===================================
3767 17:34:14.006330 ANA top config
3768 17:34:14.009584 ===================================
3769 17:34:14.012759 DLL_ASYNC_EN = 0
3770 17:34:14.016031 ALL_SLAVE_EN = 1
3771 17:34:14.019604 NEW_RANK_MODE = 1
3772 17:34:14.019738 DLL_IDLE_MODE = 1
3773 17:34:14.023055 LP45_APHY_COMB_EN = 1
3774 17:34:14.026484 TX_ODT_DIS = 1
3775 17:34:14.029233 NEW_8X_MODE = 1
3776 17:34:14.032710 ===================================
3777 17:34:14.036147 ===================================
3778 17:34:14.039597 data_rate = 1200
3779 17:34:14.039707 CKR = 1
3780 17:34:14.042488 DQ_P2S_RATIO = 8
3781 17:34:14.045895 ===================================
3782 17:34:14.049339 CA_P2S_RATIO = 8
3783 17:34:14.052496 DQ_CA_OPEN = 0
3784 17:34:14.056277 DQ_SEMI_OPEN = 0
3785 17:34:14.059001 CA_SEMI_OPEN = 0
3786 17:34:14.059108 CA_FULL_RATE = 0
3787 17:34:14.062377 DQ_CKDIV4_EN = 1
3788 17:34:14.065822 CA_CKDIV4_EN = 1
3789 17:34:14.069310 CA_PREDIV_EN = 0
3790 17:34:14.072709 PH8_DLY = 0
3791 17:34:14.075584 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3792 17:34:14.075695 DQ_AAMCK_DIV = 4
3793 17:34:14.079081 CA_AAMCK_DIV = 4
3794 17:34:14.082598 CA_ADMCK_DIV = 4
3795 17:34:14.085949 DQ_TRACK_CA_EN = 0
3796 17:34:14.089231 CA_PICK = 600
3797 17:34:14.092515 CA_MCKIO = 600
3798 17:34:14.095882 MCKIO_SEMI = 0
3799 17:34:14.095958 PLL_FREQ = 2288
3800 17:34:14.099306 DQ_UI_PI_RATIO = 32
3801 17:34:14.102818 CA_UI_PI_RATIO = 0
3802 17:34:14.105550 ===================================
3803 17:34:14.108975 ===================================
3804 17:34:14.112665 memory_type:LPDDR4
3805 17:34:14.112772 GP_NUM : 10
3806 17:34:14.115763 SRAM_EN : 1
3807 17:34:14.118800 MD32_EN : 0
3808 17:34:14.122421 ===================================
3809 17:34:14.122536 [ANA_INIT] >>>>>>>>>>>>>>
3810 17:34:14.125557 <<<<<< [CONFIGURE PHASE]: ANA_TX
3811 17:34:14.128676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3812 17:34:14.132400 ===================================
3813 17:34:14.135881 data_rate = 1200,PCW = 0X5800
3814 17:34:14.139280 ===================================
3815 17:34:14.142162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3816 17:34:14.148628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 17:34:14.152018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 17:34:14.158778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3819 17:34:14.162053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3820 17:34:14.165764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3821 17:34:14.165874 [ANA_INIT] flow start
3822 17:34:14.169189 [ANA_INIT] PLL >>>>>>>>
3823 17:34:14.171933 [ANA_INIT] PLL <<<<<<<<
3824 17:34:14.175404 [ANA_INIT] MIDPI >>>>>>>>
3825 17:34:14.175505 [ANA_INIT] MIDPI <<<<<<<<
3826 17:34:14.178885 [ANA_INIT] DLL >>>>>>>>
3827 17:34:14.182339 [ANA_INIT] flow end
3828 17:34:14.185160 ============ LP4 DIFF to SE enter ============
3829 17:34:14.188632 ============ LP4 DIFF to SE exit ============
3830 17:34:14.191987 [ANA_INIT] <<<<<<<<<<<<<
3831 17:34:14.195378 [Flow] Enable top DCM control >>>>>
3832 17:34:14.198780 [Flow] Enable top DCM control <<<<<
3833 17:34:14.202012 Enable DLL master slave shuffle
3834 17:34:14.205420 ==============================================================
3835 17:34:14.208991 Gating Mode config
3836 17:34:14.212332 ==============================================================
3837 17:34:14.215952 Config description:
3838 17:34:14.225444 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3839 17:34:14.232447 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3840 17:34:14.235453 SELPH_MODE 0: By rank 1: By Phase
3841 17:34:14.241841 ==============================================================
3842 17:34:14.245570 GAT_TRACK_EN = 1
3843 17:34:14.248581 RX_GATING_MODE = 2
3844 17:34:14.252082 RX_GATING_TRACK_MODE = 2
3845 17:34:14.255506 SELPH_MODE = 1
3846 17:34:14.258319 PICG_EARLY_EN = 1
3847 17:34:14.258430 VALID_LAT_VALUE = 1
3848 17:34:14.265253 ==============================================================
3849 17:34:14.268555 Enter into Gating configuration >>>>
3850 17:34:14.271676 Exit from Gating configuration <<<<
3851 17:34:14.275220 Enter into DVFS_PRE_config >>>>>
3852 17:34:14.285488 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3853 17:34:14.288844 Exit from DVFS_PRE_config <<<<<
3854 17:34:14.292205 Enter into PICG configuration >>>>
3855 17:34:14.295559 Exit from PICG configuration <<<<
3856 17:34:14.298268 [RX_INPUT] configuration >>>>>
3857 17:34:14.301712 [RX_INPUT] configuration <<<<<
3858 17:34:14.305243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3859 17:34:14.311932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3860 17:34:14.318244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 17:34:14.325162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 17:34:14.332196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 17:34:14.335782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 17:34:14.342201 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3865 17:34:14.345434 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3866 17:34:14.348604 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3867 17:34:14.351958 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3868 17:34:14.358347 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3869 17:34:14.362070 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 17:34:14.365293 ===================================
3871 17:34:14.368560 LPDDR4 DRAM CONFIGURATION
3872 17:34:14.371999 ===================================
3873 17:34:14.372417 EX_ROW_EN[0] = 0x0
3874 17:34:14.375474 EX_ROW_EN[1] = 0x0
3875 17:34:14.375938 LP4Y_EN = 0x0
3876 17:34:14.378687 WORK_FSP = 0x0
3877 17:34:14.379103 WL = 0x2
3878 17:34:14.381890 RL = 0x2
3879 17:34:14.382310 BL = 0x2
3880 17:34:14.385058 RPST = 0x0
3881 17:34:14.388831 RD_PRE = 0x0
3882 17:34:14.389350 WR_PRE = 0x1
3883 17:34:14.392115 WR_PST = 0x0
3884 17:34:14.392531 DBI_WR = 0x0
3885 17:34:14.395434 DBI_RD = 0x0
3886 17:34:14.396079 OTF = 0x1
3887 17:34:14.398100 ===================================
3888 17:34:14.401616 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3889 17:34:14.408269 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3890 17:34:14.411482 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 17:34:14.414790 ===================================
3892 17:34:14.418612 LPDDR4 DRAM CONFIGURATION
3893 17:34:14.421306 ===================================
3894 17:34:14.421691 EX_ROW_EN[0] = 0x10
3895 17:34:14.424758 EX_ROW_EN[1] = 0x0
3896 17:34:14.425313 LP4Y_EN = 0x0
3897 17:34:14.428257 WORK_FSP = 0x0
3898 17:34:14.428804 WL = 0x2
3899 17:34:14.431605 RL = 0x2
3900 17:34:14.432184 BL = 0x2
3901 17:34:14.435235 RPST = 0x0
3902 17:34:14.435799 RD_PRE = 0x0
3903 17:34:14.438769 WR_PRE = 0x1
3904 17:34:14.439305 WR_PST = 0x0
3905 17:34:14.441586 DBI_WR = 0x0
3906 17:34:14.441964 DBI_RD = 0x0
3907 17:34:14.444970 OTF = 0x1
3908 17:34:14.448110 ===================================
3909 17:34:14.454873 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3910 17:34:14.458162 nWR fixed to 30
3911 17:34:14.461576 [ModeRegInit_LP4] CH0 RK0
3912 17:34:14.461706 [ModeRegInit_LP4] CH0 RK1
3913 17:34:14.464809 [ModeRegInit_LP4] CH1 RK0
3914 17:34:14.468090 [ModeRegInit_LP4] CH1 RK1
3915 17:34:14.468229 match AC timing 17
3916 17:34:14.474412 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3917 17:34:14.478062 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3918 17:34:14.480987 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3919 17:34:14.487768 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3920 17:34:14.491234 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3921 17:34:14.491337 ==
3922 17:34:14.494571 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 17:34:14.497764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 17:34:14.497852 ==
3925 17:34:14.504316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 17:34:14.510736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3927 17:34:14.514284 [CA 0] Center 36 (5~67) winsize 63
3928 17:34:14.517629 [CA 1] Center 36 (5~67) winsize 63
3929 17:34:14.521160 [CA 2] Center 34 (3~65) winsize 63
3930 17:34:14.524089 [CA 3] Center 34 (3~65) winsize 63
3931 17:34:14.527439 [CA 4] Center 33 (2~64) winsize 63
3932 17:34:14.530873 [CA 5] Center 32 (2~63) winsize 62
3933 17:34:14.530979
3934 17:34:14.534301 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3935 17:34:14.534401
3936 17:34:14.537728 [CATrainingPosCal] consider 1 rank data
3937 17:34:14.541210 u2DelayCellTimex100 = 270/100 ps
3938 17:34:14.543939 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3939 17:34:14.547363 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3940 17:34:14.550803 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3941 17:34:14.554054 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
3942 17:34:14.557453 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3943 17:34:14.564185 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3944 17:34:14.564266
3945 17:34:14.567996 CA PerBit enable=1, Macro0, CA PI delay=32
3946 17:34:14.568408
3947 17:34:14.571618 [CBTSetCACLKResult] CA Dly = 32
3948 17:34:14.572074 CS Dly: 4 (0~35)
3949 17:34:14.572401 ==
3950 17:34:14.574283 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 17:34:14.577698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 17:34:14.581166 ==
3953 17:34:14.584456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 17:34:14.591070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 17:34:14.594254 [CA 0] Center 36 (5~67) winsize 63
3956 17:34:14.597802 [CA 1] Center 36 (5~67) winsize 63
3957 17:34:14.601146 [CA 2] Center 34 (3~65) winsize 63
3958 17:34:14.604327 [CA 3] Center 34 (3~65) winsize 63
3959 17:34:14.607905 [CA 4] Center 33 (2~64) winsize 63
3960 17:34:14.611056 [CA 5] Center 32 (2~63) winsize 62
3961 17:34:14.611702
3962 17:34:14.614649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 17:34:14.615231
3964 17:34:14.617597 [CATrainingPosCal] consider 2 rank data
3965 17:34:14.620834 u2DelayCellTimex100 = 270/100 ps
3966 17:34:14.624723 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3967 17:34:14.627980 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3968 17:34:14.631328 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3969 17:34:14.637403 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
3970 17:34:14.640898 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3971 17:34:14.644421 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3972 17:34:14.644923
3973 17:34:14.647723 CA PerBit enable=1, Macro0, CA PI delay=32
3974 17:34:14.648173
3975 17:34:14.651276 [CBTSetCACLKResult] CA Dly = 32
3976 17:34:14.651929 CS Dly: 4 (0~36)
3977 17:34:14.652398
3978 17:34:14.654667 ----->DramcWriteLeveling(PI) begin...
3979 17:34:14.655173 ==
3980 17:34:14.657631 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 17:34:14.664575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 17:34:14.665120 ==
3983 17:34:14.667735 Write leveling (Byte 0): 36 => 36
3984 17:34:14.671241 Write leveling (Byte 1): 32 => 32
3985 17:34:14.671897 DramcWriteLeveling(PI) end<-----
3986 17:34:14.672395
3987 17:34:14.674614 ==
3988 17:34:14.677382 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 17:34:14.680985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 17:34:14.681530 ==
3991 17:34:14.684324 [Gating] SW mode calibration
3992 17:34:14.691291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3993 17:34:14.693872 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3994 17:34:14.700736 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 17:34:14.704254 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 17:34:14.707734 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 17:34:14.714542 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
3998 17:34:14.717956 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3999 17:34:14.721101 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 17:34:14.727296 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 17:34:14.730750 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 17:34:14.734590 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 17:34:14.741622 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 17:34:14.743849 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4005 17:34:14.747226 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4006 17:34:14.754160 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4007 17:34:14.757517 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 17:34:14.760699 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 17:34:14.766809 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 17:34:14.770146 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 17:34:14.773410 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 17:34:14.779995 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 17:34:14.789190 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4014 17:34:14.789431 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4015 17:34:14.793546 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 17:34:14.797140 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 17:34:14.800156 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 17:34:14.806938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 17:34:14.810328 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 17:34:14.812936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 17:34:14.819568 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 17:34:14.823107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 17:34:14.826635 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 17:34:14.829893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 17:34:14.836446 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 17:34:14.839483 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 17:34:14.842860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 17:34:14.849863 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 17:34:14.852917 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4030 17:34:14.856178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 17:34:14.859634 Total UI for P1: 0, mck2ui 16
4032 17:34:14.863085 best dqsien dly found for B0: ( 0, 13, 12)
4033 17:34:14.866504 Total UI for P1: 0, mck2ui 16
4034 17:34:14.869631 best dqsien dly found for B1: ( 0, 13, 14)
4035 17:34:14.872436 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4036 17:34:14.879106 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4037 17:34:14.879189
4038 17:34:14.882459 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4039 17:34:14.886386 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4040 17:34:14.889859 [Gating] SW calibration Done
4041 17:34:14.889951 ==
4042 17:34:14.893110 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 17:34:14.896040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 17:34:14.896127 ==
4045 17:34:14.896212 RX Vref Scan: 0
4046 17:34:14.899382
4047 17:34:14.899480 RX Vref 0 -> 0, step: 1
4048 17:34:14.899580
4049 17:34:14.902800 RX Delay -230 -> 252, step: 16
4050 17:34:14.906294 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4051 17:34:14.912578 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4052 17:34:14.916067 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4053 17:34:14.919411 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4054 17:34:14.922635 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4055 17:34:14.925944 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4056 17:34:14.932801 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4057 17:34:14.935775 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4058 17:34:14.939139 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4059 17:34:14.942963 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4060 17:34:14.949065 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4061 17:34:14.952587 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4062 17:34:14.955822 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4063 17:34:14.959576 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4064 17:34:14.965832 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4065 17:34:14.969016 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4066 17:34:14.969111 ==
4067 17:34:14.972840 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 17:34:14.976016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 17:34:14.976110 ==
4070 17:34:14.978978 DQS Delay:
4071 17:34:14.979063 DQS0 = 0, DQS1 = 0
4072 17:34:14.979148 DQM Delay:
4073 17:34:14.982222 DQM0 = 52, DQM1 = 48
4074 17:34:14.982308 DQ Delay:
4075 17:34:14.985468 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4076 17:34:14.988791 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4077 17:34:14.992120 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4078 17:34:14.995486 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4079 17:34:14.995573
4080 17:34:14.995709
4081 17:34:14.995791 ==
4082 17:34:14.999256 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 17:34:15.002761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 17:34:15.005497 ==
4085 17:34:15.005586
4086 17:34:15.005670
4087 17:34:15.005749 TX Vref Scan disable
4088 17:34:15.008788 == TX Byte 0 ==
4089 17:34:15.012075 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4090 17:34:15.018846 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4091 17:34:15.018935 == TX Byte 1 ==
4092 17:34:15.022234 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4093 17:34:15.028949 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4094 17:34:15.029047 ==
4095 17:34:15.032462 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 17:34:15.035248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 17:34:15.035335 ==
4098 17:34:15.035436
4099 17:34:15.035533
4100 17:34:15.039082 TX Vref Scan disable
4101 17:34:15.042332 == TX Byte 0 ==
4102 17:34:15.045391 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4103 17:34:15.048778 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4104 17:34:15.052204 == TX Byte 1 ==
4105 17:34:15.055519 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4106 17:34:15.058787 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4107 17:34:15.058873
4108 17:34:15.058958 [DATLAT]
4109 17:34:15.061908 Freq=600, CH0 RK0
4110 17:34:15.062000
4111 17:34:15.065713 DATLAT Default: 0x9
4112 17:34:15.065802 0, 0xFFFF, sum = 0
4113 17:34:15.069049 1, 0xFFFF, sum = 0
4114 17:34:15.069136 2, 0xFFFF, sum = 0
4115 17:34:15.072199 3, 0xFFFF, sum = 0
4116 17:34:15.072288 4, 0xFFFF, sum = 0
4117 17:34:15.075486 5, 0xFFFF, sum = 0
4118 17:34:15.075599 6, 0xFFFF, sum = 0
4119 17:34:15.078698 7, 0xFFFF, sum = 0
4120 17:34:15.078785 8, 0x0, sum = 1
4121 17:34:15.081913 9, 0x0, sum = 2
4122 17:34:15.081999 10, 0x0, sum = 3
4123 17:34:15.082086 11, 0x0, sum = 4
4124 17:34:15.085571 best_step = 9
4125 17:34:15.085694
4126 17:34:15.085830 ==
4127 17:34:15.088795 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 17:34:15.092082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 17:34:15.092169 ==
4130 17:34:15.095536 RX Vref Scan: 1
4131 17:34:15.095657
4132 17:34:15.095742 RX Vref 0 -> 0, step: 1
4133 17:34:15.095802
4134 17:34:15.098252 RX Delay -147 -> 252, step: 8
4135 17:34:15.098387
4136 17:34:15.101818 Set Vref, RX VrefLevel [Byte0]: 56
4137 17:34:15.105667 [Byte1]: 53
4138 17:34:15.109138
4139 17:34:15.109244 Final RX Vref Byte 0 = 56 to rank0
4140 17:34:15.112709 Final RX Vref Byte 1 = 53 to rank0
4141 17:34:15.116162 Final RX Vref Byte 0 = 56 to rank1
4142 17:34:15.119417 Final RX Vref Byte 1 = 53 to rank1==
4143 17:34:15.122157 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 17:34:15.128901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 17:34:15.129010 ==
4146 17:34:15.129107 DQS Delay:
4147 17:34:15.132310 DQS0 = 0, DQS1 = 0
4148 17:34:15.132398 DQM Delay:
4149 17:34:15.132479 DQM0 = 53, DQM1 = 48
4150 17:34:15.135559 DQ Delay:
4151 17:34:15.139017 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4152 17:34:15.142526 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4153 17:34:15.145860 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4154 17:34:15.149092 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =56
4155 17:34:15.149212
4156 17:34:15.149294
4157 17:34:15.155627 [DQSOSCAuto] RK0, (LSB)MR18= 0x695d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
4158 17:34:15.158718 CH0 RK0: MR19=808, MR18=695D
4159 17:34:15.165479 CH0_RK0: MR19=0x808, MR18=0x695D, DQSOSC=390, MR23=63, INC=172, DEC=114
4160 17:34:15.165594
4161 17:34:15.168775 ----->DramcWriteLeveling(PI) begin...
4162 17:34:15.168862 ==
4163 17:34:15.171987 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 17:34:15.175748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 17:34:15.175836 ==
4166 17:34:15.179190 Write leveling (Byte 0): 34 => 34
4167 17:34:15.182516 Write leveling (Byte 1): 31 => 31
4168 17:34:15.185360 DramcWriteLeveling(PI) end<-----
4169 17:34:15.185445
4170 17:34:15.185509 ==
4171 17:34:15.188849 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 17:34:15.192318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 17:34:15.192402 ==
4174 17:34:15.195319 [Gating] SW mode calibration
4175 17:34:15.201994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4176 17:34:15.208753 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4177 17:34:15.212198 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 17:34:15.218309 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 17:34:15.221857 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 17:34:15.225250 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4181 17:34:15.232125 0 9 16 | B1->B0 | 2929 2a2a | 1 1 | (1 1) (0 0)
4182 17:34:15.235408 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 17:34:15.238706 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 17:34:15.244937 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 17:34:15.248383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 17:34:15.251886 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 17:34:15.255480 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 17:34:15.261822 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4189 17:34:15.265009 0 10 16 | B1->B0 | 3d3d 3e3e | 0 0 | (0 0) (0 0)
4190 17:34:15.268224 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 17:34:15.275289 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 17:34:15.278264 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 17:34:15.281718 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 17:34:15.288729 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 17:34:15.291490 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 17:34:15.294946 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 17:34:15.301802 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4198 17:34:15.305227 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 17:34:15.308401 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 17:34:15.315055 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 17:34:15.318487 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 17:34:15.321673 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 17:34:15.328403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 17:34:15.331913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 17:34:15.334660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 17:34:15.341424 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 17:34:15.345005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 17:34:15.348506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 17:34:15.354923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 17:34:15.358381 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 17:34:15.361274 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 17:34:15.368484 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 17:34:15.371266 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4214 17:34:15.374641 Total UI for P1: 0, mck2ui 16
4215 17:34:15.378150 best dqsien dly found for B1: ( 0, 13, 14)
4216 17:34:15.381600 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 17:34:15.384950 Total UI for P1: 0, mck2ui 16
4218 17:34:15.388072 best dqsien dly found for B0: ( 0, 13, 16)
4219 17:34:15.391360 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4220 17:34:15.394459 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4221 17:34:15.394545
4222 17:34:15.398205 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4223 17:34:15.404706 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4224 17:34:15.404814 [Gating] SW calibration Done
4225 17:34:15.404881 ==
4226 17:34:15.408520 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 17:34:15.414896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 17:34:15.415012 ==
4229 17:34:15.415114 RX Vref Scan: 0
4230 17:34:15.415184
4231 17:34:15.418239 RX Vref 0 -> 0, step: 1
4232 17:34:15.418349
4233 17:34:15.421564 RX Delay -230 -> 252, step: 16
4234 17:34:15.425030 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4235 17:34:15.428535 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4236 17:34:15.431530 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4237 17:34:15.438237 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4238 17:34:15.441407 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4239 17:34:15.445081 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4240 17:34:15.447885 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4241 17:34:15.451573 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4242 17:34:15.457746 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4243 17:34:15.461295 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4244 17:34:15.464719 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4245 17:34:15.468276 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4246 17:34:15.474745 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4247 17:34:15.478213 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4248 17:34:15.481702 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4249 17:34:15.484649 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4250 17:34:15.484727 ==
4251 17:34:15.488142 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 17:34:15.494798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 17:34:15.494885 ==
4254 17:34:15.494972 DQS Delay:
4255 17:34:15.498199 DQS0 = 0, DQS1 = 0
4256 17:34:15.498285 DQM Delay:
4257 17:34:15.498371 DQM0 = 50, DQM1 = 42
4258 17:34:15.501622 DQ Delay:
4259 17:34:15.504535 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =41
4260 17:34:15.507939 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4261 17:34:15.511269 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4262 17:34:15.514984 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4263 17:34:15.515167
4264 17:34:15.515294
4265 17:34:15.515370 ==
4266 17:34:15.519130 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 17:34:15.521470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 17:34:15.521648 ==
4269 17:34:15.521759
4270 17:34:15.521861
4271 17:34:15.524810 TX Vref Scan disable
4272 17:34:15.524917 == TX Byte 0 ==
4273 17:34:15.531710 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4274 17:34:15.534753 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4275 17:34:15.534885 == TX Byte 1 ==
4276 17:34:15.541748 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4277 17:34:15.544603 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4278 17:34:15.544692 ==
4279 17:34:15.548125 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 17:34:15.551494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 17:34:15.551607 ==
4282 17:34:15.554891
4283 17:34:15.554964
4284 17:34:15.555026 TX Vref Scan disable
4285 17:34:15.558198 == TX Byte 0 ==
4286 17:34:15.561425 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4287 17:34:15.568196 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4288 17:34:15.568279 == TX Byte 1 ==
4289 17:34:15.571487 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4290 17:34:15.578578 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4291 17:34:15.578691
4292 17:34:15.578760 [DATLAT]
4293 17:34:15.578821 Freq=600, CH0 RK1
4294 17:34:15.578881
4295 17:34:15.581383 DATLAT Default: 0x9
4296 17:34:15.581458 0, 0xFFFF, sum = 0
4297 17:34:15.584891 1, 0xFFFF, sum = 0
4298 17:34:15.584969 2, 0xFFFF, sum = 0
4299 17:34:15.588440 3, 0xFFFF, sum = 0
4300 17:34:15.591257 4, 0xFFFF, sum = 0
4301 17:34:15.591386 5, 0xFFFF, sum = 0
4302 17:34:15.594780 6, 0xFFFF, sum = 0
4303 17:34:15.594878 7, 0xFFFF, sum = 0
4304 17:34:15.598064 8, 0x0, sum = 1
4305 17:34:15.598205 9, 0x0, sum = 2
4306 17:34:15.598333 10, 0x0, sum = 3
4307 17:34:15.601328 11, 0x0, sum = 4
4308 17:34:15.601412 best_step = 9
4309 17:34:15.601476
4310 17:34:15.601535 ==
4311 17:34:15.604752 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 17:34:15.611634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 17:34:15.611727 ==
4314 17:34:15.611792 RX Vref Scan: 0
4315 17:34:15.611852
4316 17:34:15.614445 RX Vref 0 -> 0, step: 1
4317 17:34:15.614559
4318 17:34:15.617915 RX Delay -163 -> 252, step: 8
4319 17:34:15.621298 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4320 17:34:15.627519 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4321 17:34:15.630881 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4322 17:34:15.634432 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4323 17:34:15.637674 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4324 17:34:15.641056 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4325 17:34:15.647494 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4326 17:34:15.650859 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4327 17:34:15.654562 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4328 17:34:15.657562 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4329 17:34:15.660943 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4330 17:34:15.667729 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4331 17:34:15.671061 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4332 17:34:15.674375 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4333 17:34:15.677674 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4334 17:34:15.680900 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4335 17:34:15.684531 ==
4336 17:34:15.687930 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 17:34:15.690854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 17:34:15.690936 ==
4339 17:34:15.691001 DQS Delay:
4340 17:34:15.694826 DQS0 = 0, DQS1 = 0
4341 17:34:15.694908 DQM Delay:
4342 17:34:15.697832 DQM0 = 53, DQM1 = 46
4343 17:34:15.697914 DQ Delay:
4344 17:34:15.701210 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4345 17:34:15.704708 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =64
4346 17:34:15.707968 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4347 17:34:15.711184 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4348 17:34:15.711266
4349 17:34:15.711332
4350 17:34:15.717873 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b1c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
4351 17:34:15.720831 CH0 RK1: MR19=808, MR18=5B1C
4352 17:34:15.727584 CH0_RK1: MR19=0x808, MR18=0x5B1C, DQSOSC=392, MR23=63, INC=170, DEC=113
4353 17:34:15.731185 [RxdqsGatingPostProcess] freq 600
4354 17:34:15.737713 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 17:34:15.737799 Pre-setting of DQS Precalculation
4356 17:34:15.744823 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 17:34:15.744907 ==
4358 17:34:15.747474 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 17:34:15.750744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 17:34:15.750840 ==
4361 17:34:15.757431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 17:34:15.764544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4363 17:34:15.768094 [CA 0] Center 36 (5~67) winsize 63
4364 17:34:15.771420 [CA 1] Center 36 (5~67) winsize 63
4365 17:34:15.774151 [CA 2] Center 35 (4~66) winsize 63
4366 17:34:15.777703 [CA 3] Center 34 (4~65) winsize 62
4367 17:34:15.781285 [CA 4] Center 34 (4~65) winsize 62
4368 17:34:15.784722 [CA 5] Center 34 (3~65) winsize 63
4369 17:34:15.784802
4370 17:34:15.787956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4371 17:34:15.788037
4372 17:34:15.791249 [CATrainingPosCal] consider 1 rank data
4373 17:34:15.794381 u2DelayCellTimex100 = 270/100 ps
4374 17:34:15.797873 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4375 17:34:15.801201 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4376 17:34:15.804048 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4377 17:34:15.807577 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 17:34:15.811048 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 17:34:15.814739 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4380 17:34:15.814868
4381 17:34:15.817328 CA PerBit enable=1, Macro0, CA PI delay=34
4382 17:34:15.820717
4383 17:34:15.820797 [CBTSetCACLKResult] CA Dly = 34
4384 17:34:15.824058 CS Dly: 7 (0~38)
4385 17:34:15.824176 ==
4386 17:34:15.827808 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 17:34:15.831484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 17:34:15.831571 ==
4389 17:34:15.837684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 17:34:15.843831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4391 17:34:15.847854 [CA 0] Center 36 (5~67) winsize 63
4392 17:34:15.850622 [CA 1] Center 36 (5~67) winsize 63
4393 17:34:15.854093 [CA 2] Center 35 (4~66) winsize 63
4394 17:34:15.857546 [CA 3] Center 35 (4~66) winsize 63
4395 17:34:15.861079 [CA 4] Center 35 (4~66) winsize 63
4396 17:34:15.864244 [CA 5] Center 34 (4~65) winsize 62
4397 17:34:15.864314
4398 17:34:15.867500 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4399 17:34:15.867610
4400 17:34:15.870766 [CATrainingPosCal] consider 2 rank data
4401 17:34:15.874119 u2DelayCellTimex100 = 270/100 ps
4402 17:34:15.877422 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4403 17:34:15.880778 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4404 17:34:15.884200 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4405 17:34:15.887033 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 17:34:15.890716 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 17:34:15.894219 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4408 17:34:15.894289
4409 17:34:15.901035 CA PerBit enable=1, Macro0, CA PI delay=34
4410 17:34:15.901107
4411 17:34:15.904128 [CBTSetCACLKResult] CA Dly = 34
4412 17:34:15.904198 CS Dly: 7 (0~38)
4413 17:34:15.904258
4414 17:34:15.907083 ----->DramcWriteLeveling(PI) begin...
4415 17:34:15.907156 ==
4416 17:34:15.910662 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 17:34:15.914229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 17:34:15.914308 ==
4419 17:34:15.917651 Write leveling (Byte 0): 29 => 29
4420 17:34:15.920433 Write leveling (Byte 1): 30 => 30
4421 17:34:15.923907 DramcWriteLeveling(PI) end<-----
4422 17:34:15.923985
4423 17:34:15.924048 ==
4424 17:34:15.927094 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 17:34:15.933726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 17:34:15.933810 ==
4427 17:34:15.933875 [Gating] SW mode calibration
4428 17:34:15.944183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 17:34:15.947129 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 17:34:15.950493 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 17:34:15.957055 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 17:34:15.960471 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 17:34:15.963946 0 9 12 | B1->B0 | 3333 2c2c | 1 1 | (1 0) (1 1)
4434 17:34:15.970270 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4435 17:34:15.973851 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 17:34:15.977306 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 17:34:15.984257 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 17:34:15.987497 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 17:34:15.990346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 17:34:15.997441 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 17:34:16.000829 0 10 12 | B1->B0 | 2f2f 3838 | 1 0 | (0 0) (0 0)
4442 17:34:16.004383 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 17:34:16.010584 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 17:34:16.013854 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 17:34:16.017062 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 17:34:16.023900 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 17:34:16.027146 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 17:34:16.030549 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 17:34:16.034009 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4450 17:34:16.040741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4451 17:34:16.044079 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 17:34:16.046890 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 17:34:16.054132 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 17:34:16.056905 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 17:34:16.060210 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 17:34:16.066992 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 17:34:16.070458 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 17:34:16.074031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 17:34:16.080374 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 17:34:16.083865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 17:34:16.086600 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 17:34:16.093668 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 17:34:16.097066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 17:34:16.100385 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 17:34:16.106559 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4466 17:34:16.110376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 17:34:16.113185 Total UI for P1: 0, mck2ui 16
4468 17:34:16.116687 best dqsien dly found for B0: ( 0, 13, 12)
4469 17:34:16.119896 Total UI for P1: 0, mck2ui 16
4470 17:34:16.123208 best dqsien dly found for B1: ( 0, 13, 14)
4471 17:34:16.126845 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4472 17:34:16.130138 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4473 17:34:16.130218
4474 17:34:16.133389 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 17:34:16.136908 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4476 17:34:16.139593 [Gating] SW calibration Done
4477 17:34:16.139734 ==
4478 17:34:16.142898 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 17:34:16.149664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 17:34:16.149743 ==
4481 17:34:16.149812 RX Vref Scan: 0
4482 17:34:16.149871
4483 17:34:16.152983 RX Vref 0 -> 0, step: 1
4484 17:34:16.153156
4485 17:34:16.156512 RX Delay -230 -> 252, step: 16
4486 17:34:16.159369 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4487 17:34:16.162679 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4488 17:34:16.166318 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4489 17:34:16.173258 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4490 17:34:16.176493 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4491 17:34:16.179838 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4492 17:34:16.182796 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4493 17:34:16.186231 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4494 17:34:16.193125 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4495 17:34:16.195997 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4496 17:34:16.199570 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4497 17:34:16.203332 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4498 17:34:16.209666 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4499 17:34:16.213020 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4500 17:34:16.216078 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4501 17:34:16.219566 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4502 17:34:16.219730 ==
4503 17:34:16.223065 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 17:34:16.229481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 17:34:16.229706 ==
4506 17:34:16.229899 DQS Delay:
4507 17:34:16.232718 DQS0 = 0, DQS1 = 0
4508 17:34:16.232913 DQM Delay:
4509 17:34:16.233068 DQM0 = 51, DQM1 = 48
4510 17:34:16.236323 DQ Delay:
4511 17:34:16.239257 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4512 17:34:16.242778 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41
4513 17:34:16.246237 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4514 17:34:16.249323 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =65
4515 17:34:16.249854
4516 17:34:16.250373
4517 17:34:16.250887 ==
4518 17:34:16.253203 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 17:34:16.256230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 17:34:16.256742 ==
4521 17:34:16.257301
4522 17:34:16.257835
4523 17:34:16.259440 TX Vref Scan disable
4524 17:34:16.260030 == TX Byte 0 ==
4525 17:34:16.265958 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 17:34:16.269636 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 17:34:16.273021 == TX Byte 1 ==
4528 17:34:16.275889 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 17:34:16.279520 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 17:34:16.280239 ==
4531 17:34:16.282838 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 17:34:16.286290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 17:34:16.286849 ==
4534 17:34:16.287330
4535 17:34:16.289762
4536 17:34:16.290253 TX Vref Scan disable
4537 17:34:16.292915 == TX Byte 0 ==
4538 17:34:16.296270 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4539 17:34:16.299784 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4540 17:34:16.302636 == TX Byte 1 ==
4541 17:34:16.306306 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4542 17:34:16.309658 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4543 17:34:16.313196
4544 17:34:16.313664 [DATLAT]
4545 17:34:16.314015 Freq=600, CH1 RK0
4546 17:34:16.314372
4547 17:34:16.315939 DATLAT Default: 0x9
4548 17:34:16.316322 0, 0xFFFF, sum = 0
4549 17:34:16.319603 1, 0xFFFF, sum = 0
4550 17:34:16.320243 2, 0xFFFF, sum = 0
4551 17:34:16.323168 3, 0xFFFF, sum = 0
4552 17:34:16.323580 4, 0xFFFF, sum = 0
4553 17:34:16.326438 5, 0xFFFF, sum = 0
4554 17:34:16.329193 6, 0xFFFF, sum = 0
4555 17:34:16.329738 7, 0xFFFF, sum = 0
4556 17:34:16.330240 8, 0x0, sum = 1
4557 17:34:16.332894 9, 0x0, sum = 2
4558 17:34:16.333427 10, 0x0, sum = 3
4559 17:34:16.336188 11, 0x0, sum = 4
4560 17:34:16.336592 best_step = 9
4561 17:34:16.336923
4562 17:34:16.337217 ==
4563 17:34:16.339624 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 17:34:16.345958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 17:34:16.346339 ==
4566 17:34:16.346635 RX Vref Scan: 1
4567 17:34:16.346944
4568 17:34:16.349298 RX Vref 0 -> 0, step: 1
4569 17:34:16.349723
4570 17:34:16.352565 RX Delay -163 -> 252, step: 8
4571 17:34:16.352939
4572 17:34:16.356256 Set Vref, RX VrefLevel [Byte0]: 54
4573 17:34:16.359033 [Byte1]: 46
4574 17:34:16.359490
4575 17:34:16.362740 Final RX Vref Byte 0 = 54 to rank0
4576 17:34:16.366185 Final RX Vref Byte 1 = 46 to rank0
4577 17:34:16.369616 Final RX Vref Byte 0 = 54 to rank1
4578 17:34:16.372929 Final RX Vref Byte 1 = 46 to rank1==
4579 17:34:16.375708 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 17:34:16.379374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 17:34:16.379916 ==
4582 17:34:16.382530 DQS Delay:
4583 17:34:16.382937 DQS0 = 0, DQS1 = 0
4584 17:34:16.383291 DQM Delay:
4585 17:34:16.385874 DQM0 = 49, DQM1 = 45
4586 17:34:16.386275 DQ Delay:
4587 17:34:16.389473 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4588 17:34:16.391952 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4589 17:34:16.395396 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4590 17:34:16.398717 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4591 17:34:16.398823
4592 17:34:16.398913
4593 17:34:16.408628 [DQSOSCAuto] RK0, (LSB)MR18= 0x4569, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
4594 17:34:16.412194 CH1 RK0: MR19=808, MR18=4569
4595 17:34:16.415558 CH1_RK0: MR19=0x808, MR18=0x4569, DQSOSC=390, MR23=63, INC=172, DEC=114
4596 17:34:16.415666
4597 17:34:16.419294 ----->DramcWriteLeveling(PI) begin...
4598 17:34:16.422058 ==
4599 17:34:16.425610 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 17:34:16.429310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 17:34:16.429392 ==
4602 17:34:16.432204 Write leveling (Byte 0): 30 => 30
4603 17:34:16.435881 Write leveling (Byte 1): 30 => 30
4604 17:34:16.438588 DramcWriteLeveling(PI) end<-----
4605 17:34:16.438683
4606 17:34:16.438757 ==
4607 17:34:16.442123 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 17:34:16.445530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 17:34:16.445634 ==
4610 17:34:16.449137 [Gating] SW mode calibration
4611 17:34:16.456024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 17:34:16.458806 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 17:34:16.465659 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 17:34:16.469026 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 17:34:16.472476 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4616 17:34:16.479317 0 9 12 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
4617 17:34:16.482532 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 17:34:16.485906 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 17:34:16.492586 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 17:34:16.496203 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 17:34:16.499229 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 17:34:16.505558 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 17:34:16.508890 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 17:34:16.512311 0 10 12 | B1->B0 | 3838 3636 | 1 0 | (0 0) (0 0)
4625 17:34:16.519326 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 17:34:16.522099 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 17:34:16.525521 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 17:34:16.532836 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 17:34:16.535595 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 17:34:16.538944 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 17:34:16.545917 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4632 17:34:16.549274 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4633 17:34:16.552110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 17:34:16.559420 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 17:34:16.562352 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 17:34:16.565753 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 17:34:16.569184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 17:34:16.575544 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 17:34:16.578852 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 17:34:16.582363 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 17:34:16.588686 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 17:34:16.592066 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 17:34:16.595433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 17:34:16.601868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 17:34:16.605279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 17:34:16.609033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 17:34:16.615101 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 17:34:16.618837 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4649 17:34:16.621769 Total UI for P1: 0, mck2ui 16
4650 17:34:16.625282 best dqsien dly found for B1: ( 0, 13, 10)
4651 17:34:16.628198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4652 17:34:16.635345 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 17:34:16.635444 Total UI for P1: 0, mck2ui 16
4654 17:34:16.641482 best dqsien dly found for B0: ( 0, 13, 14)
4655 17:34:16.645118 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4656 17:34:16.648450 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4657 17:34:16.648532
4658 17:34:16.651846 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4659 17:34:16.655217 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4660 17:34:16.657900 [Gating] SW calibration Done
4661 17:34:16.658006 ==
4662 17:34:16.661375 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 17:34:16.664954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 17:34:16.665032 ==
4665 17:34:16.668171 RX Vref Scan: 0
4666 17:34:16.668276
4667 17:34:16.668366 RX Vref 0 -> 0, step: 1
4668 17:34:16.671616
4669 17:34:16.671741 RX Delay -230 -> 252, step: 16
4670 17:34:16.678035 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4671 17:34:16.681461 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4672 17:34:16.685049 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4673 17:34:16.688321 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4674 17:34:16.691596 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4675 17:34:16.698231 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4676 17:34:16.700951 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4677 17:34:16.704296 iDelay=218, Bit 7, Center 57 (-86 ~ 201) 288
4678 17:34:16.707671 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4679 17:34:16.711283 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4680 17:34:16.718075 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4681 17:34:16.721484 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4682 17:34:16.724294 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4683 17:34:16.727860 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4684 17:34:16.734216 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4685 17:34:16.738002 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4686 17:34:16.738078 ==
4687 17:34:16.741284 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 17:34:16.744342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 17:34:16.744418 ==
4690 17:34:16.747888 DQS Delay:
4691 17:34:16.747961 DQS0 = 0, DQS1 = 0
4692 17:34:16.748020 DQM Delay:
4693 17:34:16.750786 DQM0 = 55, DQM1 = 51
4694 17:34:16.750874 DQ Delay:
4695 17:34:16.754421 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =57
4696 17:34:16.757783 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =57
4697 17:34:16.760987 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4698 17:34:16.764473 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4699 17:34:16.764553
4700 17:34:16.764640
4701 17:34:16.764742 ==
4702 17:34:16.767503 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 17:34:16.771031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 17:34:16.774602 ==
4705 17:34:16.774682
4706 17:34:16.774743
4707 17:34:16.774801 TX Vref Scan disable
4708 17:34:16.777469 == TX Byte 0 ==
4709 17:34:16.780956 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4710 17:34:16.787369 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4711 17:34:16.787451 == TX Byte 1 ==
4712 17:34:16.790907 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 17:34:16.797916 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 17:34:16.797997 ==
4715 17:34:16.801233 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 17:34:16.804406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 17:34:16.804488 ==
4718 17:34:16.804552
4719 17:34:16.804610
4720 17:34:16.807540 TX Vref Scan disable
4721 17:34:16.810679 == TX Byte 0 ==
4722 17:34:16.814298 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4723 17:34:16.817664 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4724 17:34:16.821199 == TX Byte 1 ==
4725 17:34:16.824394 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4726 17:34:16.827782 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4727 17:34:16.827863
4728 17:34:16.827927 [DATLAT]
4729 17:34:16.830602 Freq=600, CH1 RK1
4730 17:34:16.830686
4731 17:34:16.830749 DATLAT Default: 0x9
4732 17:34:16.834314 0, 0xFFFF, sum = 0
4733 17:34:16.837672 1, 0xFFFF, sum = 0
4734 17:34:16.837755 2, 0xFFFF, sum = 0
4735 17:34:16.841153 3, 0xFFFF, sum = 0
4736 17:34:16.841261 4, 0xFFFF, sum = 0
4737 17:34:16.844019 5, 0xFFFF, sum = 0
4738 17:34:16.844138 6, 0xFFFF, sum = 0
4739 17:34:16.847388 7, 0xFFFF, sum = 0
4740 17:34:16.847496 8, 0x0, sum = 1
4741 17:34:16.851209 9, 0x0, sum = 2
4742 17:34:16.851291 10, 0x0, sum = 3
4743 17:34:16.851355 11, 0x0, sum = 4
4744 17:34:16.853930 best_step = 9
4745 17:34:16.854011
4746 17:34:16.854084 ==
4747 17:34:16.857345 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 17:34:16.860822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 17:34:16.860923 ==
4750 17:34:16.864172 RX Vref Scan: 0
4751 17:34:16.864285
4752 17:34:16.864380 RX Vref 0 -> 0, step: 1
4753 17:34:16.864467
4754 17:34:16.867564 RX Delay -163 -> 252, step: 8
4755 17:34:16.874879 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4756 17:34:16.877751 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4757 17:34:16.881533 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4758 17:34:16.884520 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4759 17:34:16.890795 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4760 17:34:16.894258 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4761 17:34:16.897755 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4762 17:34:16.901238 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4763 17:34:16.903918 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4764 17:34:16.910906 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4765 17:34:16.914249 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4766 17:34:16.917555 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4767 17:34:16.920752 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4768 17:34:16.927599 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4769 17:34:16.930885 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4770 17:34:16.933938 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4771 17:34:16.934039 ==
4772 17:34:16.937364 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 17:34:16.940756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 17:34:16.940845 ==
4775 17:34:16.944215 DQS Delay:
4776 17:34:16.944293 DQS0 = 0, DQS1 = 0
4777 17:34:16.944355 DQM Delay:
4778 17:34:16.947659 DQM0 = 49, DQM1 = 45
4779 17:34:16.947789 DQ Delay:
4780 17:34:16.950601 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4781 17:34:16.954280 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4782 17:34:16.957683 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4783 17:34:16.960529 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4784 17:34:16.960614
4785 17:34:16.960678
4786 17:34:16.970595 [DQSOSCAuto] RK1, (LSB)MR18= 0x651c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4787 17:34:16.973957 CH1 RK1: MR19=808, MR18=651C
4788 17:34:16.977572 CH1_RK1: MR19=0x808, MR18=0x651C, DQSOSC=390, MR23=63, INC=172, DEC=114
4789 17:34:16.980990 [RxdqsGatingPostProcess] freq 600
4790 17:34:16.987288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4791 17:34:16.990791 Pre-setting of DQS Precalculation
4792 17:34:16.994028 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4793 17:34:17.003607 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4794 17:34:17.010631 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4795 17:34:17.010729
4796 17:34:17.010796
4797 17:34:17.013655 [Calibration Summary] 1200 Mbps
4798 17:34:17.013744 CH 0, Rank 0
4799 17:34:17.017130 SW Impedance : PASS
4800 17:34:17.017222 DUTY Scan : NO K
4801 17:34:17.020621 ZQ Calibration : PASS
4802 17:34:17.023925 Jitter Meter : NO K
4803 17:34:17.024029 CBT Training : PASS
4804 17:34:17.027513 Write leveling : PASS
4805 17:34:17.030828 RX DQS gating : PASS
4806 17:34:17.030945 RX DQ/DQS(RDDQC) : PASS
4807 17:34:17.033509 TX DQ/DQS : PASS
4808 17:34:17.037270 RX DATLAT : PASS
4809 17:34:17.037436 RX DQ/DQS(Engine): PASS
4810 17:34:17.040744 TX OE : NO K
4811 17:34:17.040893 All Pass.
4812 17:34:17.041003
4813 17:34:17.041108 CH 0, Rank 1
4814 17:34:17.043763 SW Impedance : PASS
4815 17:34:17.047227 DUTY Scan : NO K
4816 17:34:17.047416 ZQ Calibration : PASS
4817 17:34:17.050434 Jitter Meter : NO K
4818 17:34:17.054132 CBT Training : PASS
4819 17:34:17.054316 Write leveling : PASS
4820 17:34:17.056882 RX DQS gating : PASS
4821 17:34:17.060413 RX DQ/DQS(RDDQC) : PASS
4822 17:34:17.060653 TX DQ/DQS : PASS
4823 17:34:17.063954 RX DATLAT : PASS
4824 17:34:17.067555 RX DQ/DQS(Engine): PASS
4825 17:34:17.068112 TX OE : NO K
4826 17:34:17.070314 All Pass.
4827 17:34:17.070687
4828 17:34:17.071020 CH 1, Rank 0
4829 17:34:17.073903 SW Impedance : PASS
4830 17:34:17.074432 DUTY Scan : NO K
4831 17:34:17.077543 ZQ Calibration : PASS
4832 17:34:17.080343 Jitter Meter : NO K
4833 17:34:17.080802 CBT Training : PASS
4834 17:34:17.083693 Write leveling : PASS
4835 17:34:17.087174 RX DQS gating : PASS
4836 17:34:17.087558 RX DQ/DQS(RDDQC) : PASS
4837 17:34:17.090858 TX DQ/DQS : PASS
4838 17:34:17.091243 RX DATLAT : PASS
4839 17:34:17.094367 RX DQ/DQS(Engine): PASS
4840 17:34:17.096985 TX OE : NO K
4841 17:34:17.097598 All Pass.
4842 17:34:17.098134
4843 17:34:17.098653 CH 1, Rank 1
4844 17:34:17.100176 SW Impedance : PASS
4845 17:34:17.103789 DUTY Scan : NO K
4846 17:34:17.103871 ZQ Calibration : PASS
4847 17:34:17.107117 Jitter Meter : NO K
4848 17:34:17.110371 CBT Training : PASS
4849 17:34:17.110478 Write leveling : PASS
4850 17:34:17.113229 RX DQS gating : PASS
4851 17:34:17.116773 RX DQ/DQS(RDDQC) : PASS
4852 17:34:17.116854 TX DQ/DQS : PASS
4853 17:34:17.120169 RX DATLAT : PASS
4854 17:34:17.123280 RX DQ/DQS(Engine): PASS
4855 17:34:17.123418 TX OE : NO K
4856 17:34:17.123515 All Pass.
4857 17:34:17.126994
4858 17:34:17.127072 DramC Write-DBI off
4859 17:34:17.130068 PER_BANK_REFRESH: Hybrid Mode
4860 17:34:17.130168 TX_TRACKING: ON
4861 17:34:17.140341 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4862 17:34:17.143812 [FAST_K] Save calibration result to emmc
4863 17:34:17.147046 dramc_set_vcore_voltage set vcore to 662500
4864 17:34:17.150474 Read voltage for 933, 3
4865 17:34:17.150595 Vio18 = 0
4866 17:34:17.153334 Vcore = 662500
4867 17:34:17.153475 Vdram = 0
4868 17:34:17.153607 Vddq = 0
4869 17:34:17.153736 Vmddr = 0
4870 17:34:17.160138 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4871 17:34:17.167019 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4872 17:34:17.167153 MEM_TYPE=3, freq_sel=17
4873 17:34:17.169822 sv_algorithm_assistance_LP4_1600
4874 17:34:17.173453 ============ PULL DRAM RESETB DOWN ============
4875 17:34:17.180662 ========== PULL DRAM RESETB DOWN end =========
4876 17:34:17.183385 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 17:34:17.187053 ===================================
4878 17:34:17.190383 LPDDR4 DRAM CONFIGURATION
4879 17:34:17.193892 ===================================
4880 17:34:17.194325 EX_ROW_EN[0] = 0x0
4881 17:34:17.196749 EX_ROW_EN[1] = 0x0
4882 17:34:17.197158 LP4Y_EN = 0x0
4883 17:34:17.200047 WORK_FSP = 0x0
4884 17:34:17.203552 WL = 0x3
4885 17:34:17.204023 RL = 0x3
4886 17:34:17.206643 BL = 0x2
4887 17:34:17.207050 RPST = 0x0
4888 17:34:17.209996 RD_PRE = 0x0
4889 17:34:17.210405 WR_PRE = 0x1
4890 17:34:17.213270 WR_PST = 0x0
4891 17:34:17.213679 DBI_WR = 0x0
4892 17:34:17.216664 DBI_RD = 0x0
4893 17:34:17.217269 OTF = 0x1
4894 17:34:17.219941 ===================================
4895 17:34:17.223572 ===================================
4896 17:34:17.227022 ANA top config
4897 17:34:17.229754 ===================================
4898 17:34:17.230346 DLL_ASYNC_EN = 0
4899 17:34:17.233163 ALL_SLAVE_EN = 1
4900 17:34:17.236483 NEW_RANK_MODE = 1
4901 17:34:17.239693 DLL_IDLE_MODE = 1
4902 17:34:17.240010 LP45_APHY_COMB_EN = 1
4903 17:34:17.243012 TX_ODT_DIS = 1
4904 17:34:17.246661 NEW_8X_MODE = 1
4905 17:34:17.249765 ===================================
4906 17:34:17.252820 ===================================
4907 17:34:17.256376 data_rate = 1866
4908 17:34:17.259569 CKR = 1
4909 17:34:17.259743 DQ_P2S_RATIO = 8
4910 17:34:17.262827 ===================================
4911 17:34:17.266090 CA_P2S_RATIO = 8
4912 17:34:17.269434 DQ_CA_OPEN = 0
4913 17:34:17.272801 DQ_SEMI_OPEN = 0
4914 17:34:17.275996 CA_SEMI_OPEN = 0
4915 17:34:17.280120 CA_FULL_RATE = 0
4916 17:34:17.280204 DQ_CKDIV4_EN = 1
4917 17:34:17.282927 CA_CKDIV4_EN = 1
4918 17:34:17.286478 CA_PREDIV_EN = 0
4919 17:34:17.290087 PH8_DLY = 0
4920 17:34:17.292844 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4921 17:34:17.296389 DQ_AAMCK_DIV = 4
4922 17:34:17.296472 CA_AAMCK_DIV = 4
4923 17:34:17.299816 CA_ADMCK_DIV = 4
4924 17:34:17.302800 DQ_TRACK_CA_EN = 0
4925 17:34:17.306154 CA_PICK = 933
4926 17:34:17.309866 CA_MCKIO = 933
4927 17:34:17.313418 MCKIO_SEMI = 0
4928 17:34:17.316241 PLL_FREQ = 3732
4929 17:34:17.316336 DQ_UI_PI_RATIO = 32
4930 17:34:17.319615 CA_UI_PI_RATIO = 0
4931 17:34:17.322970 ===================================
4932 17:34:17.326556 ===================================
4933 17:34:17.329577 memory_type:LPDDR4
4934 17:34:17.333116 GP_NUM : 10
4935 17:34:17.333249 SRAM_EN : 1
4936 17:34:17.336446 MD32_EN : 0
4937 17:34:17.339332 ===================================
4938 17:34:17.342660 [ANA_INIT] >>>>>>>>>>>>>>
4939 17:34:17.342823 <<<<<< [CONFIGURE PHASE]: ANA_TX
4940 17:34:17.346228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4941 17:34:17.349810 ===================================
4942 17:34:17.352681 data_rate = 1866,PCW = 0X8f00
4943 17:34:17.356348 ===================================
4944 17:34:17.359755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4945 17:34:17.366379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 17:34:17.373175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 17:34:17.376016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4948 17:34:17.379445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4949 17:34:17.382740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4950 17:34:17.386419 [ANA_INIT] flow start
4951 17:34:17.386867 [ANA_INIT] PLL >>>>>>>>
4952 17:34:17.389874 [ANA_INIT] PLL <<<<<<<<
4953 17:34:17.392960 [ANA_INIT] MIDPI >>>>>>>>
4954 17:34:17.393400 [ANA_INIT] MIDPI <<<<<<<<
4955 17:34:17.396235 [ANA_INIT] DLL >>>>>>>>
4956 17:34:17.399823 [ANA_INIT] flow end
4957 17:34:17.402588 ============ LP4 DIFF to SE enter ============
4958 17:34:17.406147 ============ LP4 DIFF to SE exit ============
4959 17:34:17.409623 [ANA_INIT] <<<<<<<<<<<<<
4960 17:34:17.413100 [Flow] Enable top DCM control >>>>>
4961 17:34:17.416088 [Flow] Enable top DCM control <<<<<
4962 17:34:17.419473 Enable DLL master slave shuffle
4963 17:34:17.423041 ==============================================================
4964 17:34:17.425765 Gating Mode config
4965 17:34:17.432507 ==============================================================
4966 17:34:17.432827 Config description:
4967 17:34:17.442450 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4968 17:34:17.449326 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4969 17:34:17.455849 SELPH_MODE 0: By rank 1: By Phase
4970 17:34:17.459464 ==============================================================
4971 17:34:17.462776 GAT_TRACK_EN = 1
4972 17:34:17.466300 RX_GATING_MODE = 2
4973 17:34:17.469102 RX_GATING_TRACK_MODE = 2
4974 17:34:17.472593 SELPH_MODE = 1
4975 17:34:17.475927 PICG_EARLY_EN = 1
4976 17:34:17.479294 VALID_LAT_VALUE = 1
4977 17:34:17.482687 ==============================================================
4978 17:34:17.485994 Enter into Gating configuration >>>>
4979 17:34:17.489041 Exit from Gating configuration <<<<
4980 17:34:17.492050 Enter into DVFS_PRE_config >>>>>
4981 17:34:17.505685 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4982 17:34:17.508982 Exit from DVFS_PRE_config <<<<<
4983 17:34:17.509311 Enter into PICG configuration >>>>
4984 17:34:17.512086 Exit from PICG configuration <<<<
4985 17:34:17.515895 [RX_INPUT] configuration >>>>>
4986 17:34:17.519131 [RX_INPUT] configuration <<<<<
4987 17:34:17.525544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4988 17:34:17.529029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4989 17:34:17.535851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 17:34:17.542195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 17:34:17.548987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 17:34:17.555827 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 17:34:17.558673 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4994 17:34:17.562245 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4995 17:34:17.565850 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4996 17:34:17.572093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4997 17:34:17.575687 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4998 17:34:17.578592 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 17:34:17.581944 ===================================
5000 17:34:17.585420 LPDDR4 DRAM CONFIGURATION
5001 17:34:17.588136 ===================================
5002 17:34:17.591814 EX_ROW_EN[0] = 0x0
5003 17:34:17.592179 EX_ROW_EN[1] = 0x0
5004 17:34:17.595317 LP4Y_EN = 0x0
5005 17:34:17.595748 WORK_FSP = 0x0
5006 17:34:17.598836 WL = 0x3
5007 17:34:17.599251 RL = 0x3
5008 17:34:17.601793 BL = 0x2
5009 17:34:17.602243 RPST = 0x0
5010 17:34:17.605293 RD_PRE = 0x0
5011 17:34:17.605716 WR_PRE = 0x1
5012 17:34:17.608368 WR_PST = 0x0
5013 17:34:17.608824 DBI_WR = 0x0
5014 17:34:17.612035 DBI_RD = 0x0
5015 17:34:17.612462 OTF = 0x1
5016 17:34:17.615030 ===================================
5017 17:34:17.621802 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5018 17:34:17.625241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5019 17:34:17.628540 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 17:34:17.631679 ===================================
5021 17:34:17.634814 LPDDR4 DRAM CONFIGURATION
5022 17:34:17.638532 ===================================
5023 17:34:17.638964 EX_ROW_EN[0] = 0x10
5024 17:34:17.641764 EX_ROW_EN[1] = 0x0
5025 17:34:17.644858 LP4Y_EN = 0x0
5026 17:34:17.645370 WORK_FSP = 0x0
5027 17:34:17.647989 WL = 0x3
5028 17:34:17.648326 RL = 0x3
5029 17:34:17.651404 BL = 0x2
5030 17:34:17.651908 RPST = 0x0
5031 17:34:17.654597 RD_PRE = 0x0
5032 17:34:17.655032 WR_PRE = 0x1
5033 17:34:17.657838 WR_PST = 0x0
5034 17:34:17.658345 DBI_WR = 0x0
5035 17:34:17.661368 DBI_RD = 0x0
5036 17:34:17.661800 OTF = 0x1
5037 17:34:17.665072 ===================================
5038 17:34:17.671422 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5039 17:34:17.675695 nWR fixed to 30
5040 17:34:17.679122 [ModeRegInit_LP4] CH0 RK0
5041 17:34:17.679572 [ModeRegInit_LP4] CH0 RK1
5042 17:34:17.682591 [ModeRegInit_LP4] CH1 RK0
5043 17:34:17.686051 [ModeRegInit_LP4] CH1 RK1
5044 17:34:17.686478 match AC timing 9
5045 17:34:17.692322 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5046 17:34:17.695688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5047 17:34:17.699142 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5048 17:34:17.705466 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5049 17:34:17.708839 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5050 17:34:17.709255 ==
5051 17:34:17.712452 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 17:34:17.715994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5053 17:34:17.716328 ==
5054 17:34:17.722204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5055 17:34:17.729013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5056 17:34:17.731904 [CA 0] Center 37 (6~68) winsize 63
5057 17:34:17.735909 [CA 1] Center 37 (7~68) winsize 62
5058 17:34:17.739133 [CA 2] Center 34 (4~65) winsize 62
5059 17:34:17.742372 [CA 3] Center 34 (3~65) winsize 63
5060 17:34:17.745656 [CA 4] Center 33 (3~64) winsize 62
5061 17:34:17.749013 [CA 5] Center 32 (2~62) winsize 61
5062 17:34:17.749370
5063 17:34:17.752347 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5064 17:34:17.752806
5065 17:34:17.755576 [CATrainingPosCal] consider 1 rank data
5066 17:34:17.758861 u2DelayCellTimex100 = 270/100 ps
5067 17:34:17.761856 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5068 17:34:17.765861 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5069 17:34:17.768596 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5070 17:34:17.772218 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5071 17:34:17.775813 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5072 17:34:17.782104 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5073 17:34:17.782522
5074 17:34:17.785661 CA PerBit enable=1, Macro0, CA PI delay=32
5075 17:34:17.786117
5076 17:34:17.789078 [CBTSetCACLKResult] CA Dly = 32
5077 17:34:17.789406 CS Dly: 5 (0~36)
5078 17:34:17.789685 ==
5079 17:34:17.792375 Dram Type= 6, Freq= 0, CH_0, rank 1
5080 17:34:17.795240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 17:34:17.795554 ==
5082 17:34:17.802314 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 17:34:17.808465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5084 17:34:17.812006 [CA 0] Center 37 (6~68) winsize 63
5085 17:34:17.815327 [CA 1] Center 37 (7~68) winsize 62
5086 17:34:17.818788 [CA 2] Center 34 (4~65) winsize 62
5087 17:34:17.822309 [CA 3] Center 34 (4~65) winsize 62
5088 17:34:17.825050 [CA 4] Center 33 (3~63) winsize 61
5089 17:34:17.828719 [CA 5] Center 32 (2~62) winsize 61
5090 17:34:17.829131
5091 17:34:17.832305 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5092 17:34:17.832720
5093 17:34:17.835176 [CATrainingPosCal] consider 2 rank data
5094 17:34:17.838870 u2DelayCellTimex100 = 270/100 ps
5095 17:34:17.842149 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5096 17:34:17.845425 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5097 17:34:17.848492 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5098 17:34:17.851718 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5099 17:34:17.858482 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5100 17:34:17.861761 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5101 17:34:17.862158
5102 17:34:17.865356 CA PerBit enable=1, Macro0, CA PI delay=32
5103 17:34:17.865677
5104 17:34:17.868679 [CBTSetCACLKResult] CA Dly = 32
5105 17:34:17.869080 CS Dly: 5 (0~37)
5106 17:34:17.869352
5107 17:34:17.872059 ----->DramcWriteLeveling(PI) begin...
5108 17:34:17.872378 ==
5109 17:34:17.875230 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 17:34:17.881835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 17:34:17.882093 ==
5112 17:34:17.885201 Write leveling (Byte 0): 32 => 32
5113 17:34:17.885510 Write leveling (Byte 1): 28 => 28
5114 17:34:17.889112 DramcWriteLeveling(PI) end<-----
5115 17:34:17.889295
5116 17:34:17.889522 ==
5117 17:34:17.891665 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 17:34:17.898708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 17:34:17.898870 ==
5120 17:34:17.901814 [Gating] SW mode calibration
5121 17:34:17.908630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5122 17:34:17.912167 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5123 17:34:17.918551 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5124 17:34:17.921457 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 17:34:17.925004 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 17:34:17.931431 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 17:34:17.934918 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 17:34:17.938447 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 17:34:17.944742 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5130 17:34:17.948186 0 14 28 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
5131 17:34:17.951539 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5132 17:34:17.958329 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 17:34:17.961199 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 17:34:17.964421 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 17:34:17.967607 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 17:34:17.974573 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 17:34:17.977931 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5138 17:34:17.981256 0 15 28 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
5139 17:34:17.988194 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5140 17:34:17.990929 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 17:34:17.994529 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 17:34:18.001691 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 17:34:18.004845 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 17:34:18.008220 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 17:34:18.014424 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5146 17:34:18.017744 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5147 17:34:18.021183 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5148 17:34:18.027669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 17:34:18.031223 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 17:34:18.034105 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 17:34:18.041122 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 17:34:18.044477 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 17:34:18.047807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 17:34:18.054867 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 17:34:18.057650 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 17:34:18.060944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 17:34:18.067998 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 17:34:18.070751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 17:34:18.074304 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 17:34:18.081130 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 17:34:18.084401 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5162 17:34:18.087892 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5163 17:34:18.090996 Total UI for P1: 0, mck2ui 16
5164 17:34:18.094407 best dqsien dly found for B0: ( 1, 2, 24)
5165 17:34:18.097607 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 17:34:18.101341 Total UI for P1: 0, mck2ui 16
5167 17:34:18.104013 best dqsien dly found for B1: ( 1, 2, 28)
5168 17:34:18.107476 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5169 17:34:18.110845 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5170 17:34:18.114395
5171 17:34:18.117924 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5172 17:34:18.121489 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5173 17:34:18.124769 [Gating] SW calibration Done
5174 17:34:18.124870 ==
5175 17:34:18.127480 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 17:34:18.131369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 17:34:18.131441 ==
5178 17:34:18.131502 RX Vref Scan: 0
5179 17:34:18.131595
5180 17:34:18.134179 RX Vref 0 -> 0, step: 1
5181 17:34:18.134323
5182 17:34:18.137486 RX Delay -80 -> 252, step: 8
5183 17:34:18.140953 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5184 17:34:18.144196 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5185 17:34:18.151062 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5186 17:34:18.153928 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5187 17:34:18.157449 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5188 17:34:18.160877 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5189 17:34:18.164222 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5190 17:34:18.167578 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5191 17:34:18.173964 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5192 17:34:18.177463 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5193 17:34:18.180471 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5194 17:34:18.184317 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5195 17:34:18.187841 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5196 17:34:18.190469 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5197 17:34:18.197429 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5198 17:34:18.200613 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5199 17:34:18.200720 ==
5200 17:34:18.203966 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 17:34:18.207164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 17:34:18.207247 ==
5203 17:34:18.210460 DQS Delay:
5204 17:34:18.210540 DQS0 = 0, DQS1 = 0
5205 17:34:18.210635 DQM Delay:
5206 17:34:18.214193 DQM0 = 103, DQM1 = 95
5207 17:34:18.214299 DQ Delay:
5208 17:34:18.217296 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5209 17:34:18.220377 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5210 17:34:18.224044 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5211 17:34:18.227505 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5212 17:34:18.227586
5213 17:34:18.227658
5214 17:34:18.230897 ==
5215 17:34:18.233660 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 17:34:18.237295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 17:34:18.237380 ==
5218 17:34:18.237445
5219 17:34:18.237503
5220 17:34:18.240501 TX Vref Scan disable
5221 17:34:18.240608 == TX Byte 0 ==
5222 17:34:18.246922 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5223 17:34:18.250335 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5224 17:34:18.250447 == TX Byte 1 ==
5225 17:34:18.253950 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5226 17:34:18.260430 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5227 17:34:18.260512 ==
5228 17:34:18.263558 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 17:34:18.267194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 17:34:18.267269 ==
5231 17:34:18.267332
5232 17:34:18.267390
5233 17:34:18.270590 TX Vref Scan disable
5234 17:34:18.273956 == TX Byte 0 ==
5235 17:34:18.276789 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5236 17:34:18.280339 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5237 17:34:18.283950 == TX Byte 1 ==
5238 17:34:18.286823 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5239 17:34:18.290225 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5240 17:34:18.290316
5241 17:34:18.293884 [DATLAT]
5242 17:34:18.293977 Freq=933, CH0 RK0
5243 17:34:18.294046
5244 17:34:18.296826 DATLAT Default: 0xd
5245 17:34:18.296934 0, 0xFFFF, sum = 0
5246 17:34:18.300286 1, 0xFFFF, sum = 0
5247 17:34:18.300368 2, 0xFFFF, sum = 0
5248 17:34:18.303643 3, 0xFFFF, sum = 0
5249 17:34:18.303727 4, 0xFFFF, sum = 0
5250 17:34:18.307285 5, 0xFFFF, sum = 0
5251 17:34:18.307394 6, 0xFFFF, sum = 0
5252 17:34:18.309988 7, 0xFFFF, sum = 0
5253 17:34:18.310070 8, 0xFFFF, sum = 0
5254 17:34:18.313518 9, 0xFFFF, sum = 0
5255 17:34:18.313601 10, 0x0, sum = 1
5256 17:34:18.316832 11, 0x0, sum = 2
5257 17:34:18.316942 12, 0x0, sum = 3
5258 17:34:18.320278 13, 0x0, sum = 4
5259 17:34:18.320350 best_step = 11
5260 17:34:18.320410
5261 17:34:18.320466 ==
5262 17:34:18.323498 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 17:34:18.327121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 17:34:18.330591 ==
5265 17:34:18.330698 RX Vref Scan: 1
5266 17:34:18.330789
5267 17:34:18.333782 RX Vref 0 -> 0, step: 1
5268 17:34:18.333863
5269 17:34:18.337042 RX Delay -53 -> 252, step: 4
5270 17:34:18.337123
5271 17:34:18.340062 Set Vref, RX VrefLevel [Byte0]: 56
5272 17:34:18.340143 [Byte1]: 53
5273 17:34:18.345096
5274 17:34:18.345177 Final RX Vref Byte 0 = 56 to rank0
5275 17:34:18.348818 Final RX Vref Byte 1 = 53 to rank0
5276 17:34:18.352028 Final RX Vref Byte 0 = 56 to rank1
5277 17:34:18.355600 Final RX Vref Byte 1 = 53 to rank1==
5278 17:34:18.358452 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 17:34:18.365050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 17:34:18.365158 ==
5281 17:34:18.365250 DQS Delay:
5282 17:34:18.365338 DQS0 = 0, DQS1 = 0
5283 17:34:18.368352 DQM Delay:
5284 17:34:18.368436 DQM0 = 105, DQM1 = 96
5285 17:34:18.371570 DQ Delay:
5286 17:34:18.374865 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5287 17:34:18.378161 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5288 17:34:18.381671 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5289 17:34:18.385225 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5290 17:34:18.385330
5291 17:34:18.385419
5292 17:34:18.391608 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
5293 17:34:18.395096 CH0 RK0: MR19=505, MR18=2C24
5294 17:34:18.401589 CH0_RK0: MR19=0x505, MR18=0x2C24, DQSOSC=408, MR23=63, INC=65, DEC=43
5295 17:34:18.401694
5296 17:34:18.405089 ----->DramcWriteLeveling(PI) begin...
5297 17:34:18.405169 ==
5298 17:34:18.408679 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 17:34:18.411411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 17:34:18.411515 ==
5301 17:34:18.415053 Write leveling (Byte 0): 30 => 30
5302 17:34:18.418509 Write leveling (Byte 1): 28 => 28
5303 17:34:18.421838 DramcWriteLeveling(PI) end<-----
5304 17:34:18.421942
5305 17:34:18.422031 ==
5306 17:34:18.425187 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 17:34:18.431311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 17:34:18.431414 ==
5309 17:34:18.431505 [Gating] SW mode calibration
5310 17:34:18.441684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5311 17:34:18.444924 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5312 17:34:18.448415 0 14 0 | B1->B0 | 3333 3232 | 0 1 | (0 0) (1 1)
5313 17:34:18.454898 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 17:34:18.457940 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 17:34:18.461499 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 17:34:18.467856 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 17:34:18.471008 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 17:34:18.474407 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5319 17:34:18.481458 0 14 28 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 0)
5320 17:34:18.484728 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5321 17:34:18.487945 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 17:34:18.494709 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 17:34:18.498330 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 17:34:18.501024 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 17:34:18.508010 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 17:34:18.511531 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5327 17:34:18.514364 0 15 28 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (0 0)
5328 17:34:18.521425 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 17:34:18.524852 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 17:34:18.528488 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 17:34:18.534791 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 17:34:18.537492 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 17:34:18.540970 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 17:34:18.547328 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 17:34:18.550693 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5336 17:34:18.554239 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 17:34:18.560884 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 17:34:18.564335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 17:34:18.567625 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 17:34:18.574169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 17:34:18.577185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 17:34:18.580448 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 17:34:18.587066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 17:34:18.590814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 17:34:18.593627 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 17:34:18.600332 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 17:34:18.603981 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 17:34:18.607108 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 17:34:18.613887 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 17:34:18.617212 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5351 17:34:18.620628 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5352 17:34:18.626947 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5353 17:34:18.630383 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 17:34:18.633631 Total UI for P1: 0, mck2ui 16
5355 17:34:18.637056 best dqsien dly found for B0: ( 1, 2, 28)
5356 17:34:18.640417 Total UI for P1: 0, mck2ui 16
5357 17:34:18.643569 best dqsien dly found for B1: ( 1, 3, 0)
5358 17:34:18.647254 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5359 17:34:18.650705 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5360 17:34:18.650801
5361 17:34:18.654272 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5362 17:34:18.656997 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5363 17:34:18.660450 [Gating] SW calibration Done
5364 17:34:18.660530 ==
5365 17:34:18.663407 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 17:34:18.666684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 17:34:18.666766 ==
5368 17:34:18.670158 RX Vref Scan: 0
5369 17:34:18.670256
5370 17:34:18.670320 RX Vref 0 -> 0, step: 1
5371 17:34:18.673756
5372 17:34:18.673863 RX Delay -80 -> 252, step: 8
5373 17:34:18.680153 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5374 17:34:18.683511 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5375 17:34:18.686815 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5376 17:34:18.690333 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5377 17:34:18.693527 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5378 17:34:18.699623 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5379 17:34:18.703291 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5380 17:34:18.706455 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5381 17:34:18.709566 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5382 17:34:18.712998 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5383 17:34:18.716561 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5384 17:34:18.723265 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5385 17:34:18.726232 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5386 17:34:18.729772 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5387 17:34:18.733244 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5388 17:34:18.736156 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5389 17:34:18.736267 ==
5390 17:34:18.739672 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 17:34:18.746442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 17:34:18.746549 ==
5393 17:34:18.746647 DQS Delay:
5394 17:34:18.749703 DQS0 = 0, DQS1 = 0
5395 17:34:18.749815 DQM Delay:
5396 17:34:18.749909 DQM0 = 105, DQM1 = 95
5397 17:34:18.753071 DQ Delay:
5398 17:34:18.756326 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5399 17:34:18.759721 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5400 17:34:18.763257 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5401 17:34:18.765990 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5402 17:34:18.766095
5403 17:34:18.766184
5404 17:34:18.766270 ==
5405 17:34:18.769683 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 17:34:18.773064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 17:34:18.773144 ==
5408 17:34:18.773207
5409 17:34:18.773264
5410 17:34:18.776378 TX Vref Scan disable
5411 17:34:18.779815 == TX Byte 0 ==
5412 17:34:18.783329 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5413 17:34:18.786109 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5414 17:34:18.789451 == TX Byte 1 ==
5415 17:34:18.792841 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5416 17:34:18.796397 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5417 17:34:18.796498 ==
5418 17:34:18.799729 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 17:34:18.806545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 17:34:18.806638 ==
5421 17:34:18.806703
5422 17:34:18.806762
5423 17:34:18.806819 TX Vref Scan disable
5424 17:34:18.810188 == TX Byte 0 ==
5425 17:34:18.813586 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5426 17:34:18.819660 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5427 17:34:18.819770 == TX Byte 1 ==
5428 17:34:18.823756 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5429 17:34:18.830152 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5430 17:34:18.830280
5431 17:34:18.830376 [DATLAT]
5432 17:34:18.830465 Freq=933, CH0 RK1
5433 17:34:18.830555
5434 17:34:18.833306 DATLAT Default: 0xb
5435 17:34:18.833408 0, 0xFFFF, sum = 0
5436 17:34:18.836478 1, 0xFFFF, sum = 0
5437 17:34:18.839807 2, 0xFFFF, sum = 0
5438 17:34:18.839904 3, 0xFFFF, sum = 0
5439 17:34:18.843015 4, 0xFFFF, sum = 0
5440 17:34:18.843098 5, 0xFFFF, sum = 0
5441 17:34:18.846725 6, 0xFFFF, sum = 0
5442 17:34:18.846808 7, 0xFFFF, sum = 0
5443 17:34:18.849573 8, 0xFFFF, sum = 0
5444 17:34:18.849716 9, 0xFFFF, sum = 0
5445 17:34:18.853267 10, 0x0, sum = 1
5446 17:34:18.853377 11, 0x0, sum = 2
5447 17:34:18.856285 12, 0x0, sum = 3
5448 17:34:18.856385 13, 0x0, sum = 4
5449 17:34:18.856483 best_step = 11
5450 17:34:18.856588
5451 17:34:18.859555 ==
5452 17:34:18.863095 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 17:34:18.866609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 17:34:18.866703 ==
5455 17:34:18.866768 RX Vref Scan: 0
5456 17:34:18.866827
5457 17:34:18.869695 RX Vref 0 -> 0, step: 1
5458 17:34:18.869793
5459 17:34:18.873035 RX Delay -45 -> 252, step: 4
5460 17:34:18.876486 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5461 17:34:18.883462 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5462 17:34:18.886289 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5463 17:34:18.889799 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5464 17:34:18.893128 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5465 17:34:18.896664 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5466 17:34:18.902809 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5467 17:34:18.906356 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5468 17:34:18.909731 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5469 17:34:18.913181 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5470 17:34:18.916374 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5471 17:34:18.919588 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5472 17:34:18.926242 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5473 17:34:18.929674 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5474 17:34:18.932912 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5475 17:34:18.936396 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5476 17:34:18.936577 ==
5477 17:34:18.939567 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 17:34:18.946681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 17:34:18.946846 ==
5480 17:34:18.946948 DQS Delay:
5481 17:34:18.947039 DQS0 = 0, DQS1 = 0
5482 17:34:18.949561 DQM Delay:
5483 17:34:18.949689 DQM0 = 104, DQM1 = 95
5484 17:34:18.953032 DQ Delay:
5485 17:34:18.956263 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5486 17:34:18.959777 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5487 17:34:18.962947 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =90
5488 17:34:18.966364 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =104
5489 17:34:18.966473
5490 17:34:18.966579
5491 17:34:18.972662 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5492 17:34:18.976256 CH0 RK1: MR19=505, MR18=2A03
5493 17:34:18.982905 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5494 17:34:18.985958 [RxdqsGatingPostProcess] freq 933
5495 17:34:18.993357 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5496 17:34:18.993495 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 17:34:18.996292 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 17:34:18.999590 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 17:34:19.003135 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 17:34:19.005997 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 17:34:19.009654 best DQS1 dly(2T, 0.5T) = (0, 11)
5502 17:34:19.013045 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 17:34:19.015944 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5504 17:34:19.019215 Pre-setting of DQS Precalculation
5505 17:34:19.026078 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5506 17:34:19.026191 ==
5507 17:34:19.029409 Dram Type= 6, Freq= 0, CH_1, rank 0
5508 17:34:19.032540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 17:34:19.032662 ==
5510 17:34:19.039279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 17:34:19.042812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 17:34:19.046766 [CA 0] Center 36 (6~67) winsize 62
5513 17:34:19.049982 [CA 1] Center 37 (6~68) winsize 63
5514 17:34:19.053395 [CA 2] Center 35 (5~65) winsize 61
5515 17:34:19.056650 [CA 3] Center 34 (4~65) winsize 62
5516 17:34:19.059955 [CA 4] Center 34 (4~65) winsize 62
5517 17:34:19.063255 [CA 5] Center 33 (3~64) winsize 62
5518 17:34:19.063337
5519 17:34:19.066617 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 17:34:19.066724
5521 17:34:19.070077 [CATrainingPosCal] consider 1 rank data
5522 17:34:19.073418 u2DelayCellTimex100 = 270/100 ps
5523 17:34:19.076202 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5524 17:34:19.082860 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5525 17:34:19.086231 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5526 17:34:19.089529 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5527 17:34:19.093415 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5528 17:34:19.096122 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5529 17:34:19.096199
5530 17:34:19.100130 CA PerBit enable=1, Macro0, CA PI delay=33
5531 17:34:19.100207
5532 17:34:19.103118 [CBTSetCACLKResult] CA Dly = 33
5533 17:34:19.103217 CS Dly: 6 (0~37)
5534 17:34:19.106691 ==
5535 17:34:19.109717 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 17:34:19.113315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 17:34:19.113396 ==
5538 17:34:19.116224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 17:34:19.122936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5540 17:34:19.126316 [CA 0] Center 36 (6~67) winsize 62
5541 17:34:19.129756 [CA 1] Center 37 (7~68) winsize 62
5542 17:34:19.133280 [CA 2] Center 35 (5~65) winsize 61
5543 17:34:19.136506 [CA 3] Center 34 (4~65) winsize 62
5544 17:34:19.140360 [CA 4] Center 34 (4~65) winsize 62
5545 17:34:19.143358 [CA 5] Center 33 (3~64) winsize 62
5546 17:34:19.143464
5547 17:34:19.146295 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5548 17:34:19.146395
5549 17:34:19.149883 [CATrainingPosCal] consider 2 rank data
5550 17:34:19.153156 u2DelayCellTimex100 = 270/100 ps
5551 17:34:19.156424 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5552 17:34:19.159660 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5553 17:34:19.166698 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5554 17:34:19.169968 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5555 17:34:19.173345 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 17:34:19.176767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 17:34:19.176875
5558 17:34:19.180274 CA PerBit enable=1, Macro0, CA PI delay=33
5559 17:34:19.180385
5560 17:34:19.182928 [CBTSetCACLKResult] CA Dly = 33
5561 17:34:19.183028 CS Dly: 7 (0~40)
5562 17:34:19.183117
5563 17:34:19.186172 ----->DramcWriteLeveling(PI) begin...
5564 17:34:19.189911 ==
5565 17:34:19.193281 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 17:34:19.196474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 17:34:19.196584 ==
5568 17:34:19.199485 Write leveling (Byte 0): 27 => 27
5569 17:34:19.202857 Write leveling (Byte 1): 27 => 27
5570 17:34:19.206430 DramcWriteLeveling(PI) end<-----
5571 17:34:19.206533
5572 17:34:19.206624 ==
5573 17:34:19.209710 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 17:34:19.212837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 17:34:19.212947 ==
5576 17:34:19.216640 [Gating] SW mode calibration
5577 17:34:19.223086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5578 17:34:19.229688 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5579 17:34:19.233282 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 17:34:19.236741 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 17:34:19.242852 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 17:34:19.246485 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 17:34:19.249850 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 17:34:19.252889 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 17:34:19.259601 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (0 1) (0 1)
5586 17:34:19.263115 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5587 17:34:19.266764 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 17:34:19.272960 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 17:34:19.276937 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 17:34:19.279571 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 17:34:19.286632 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 17:34:19.290279 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 17:34:19.292817 0 15 24 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
5594 17:34:19.300030 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5595 17:34:19.303632 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 17:34:19.306109 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 17:34:19.312919 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 17:34:19.316343 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 17:34:19.319861 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 17:34:19.325982 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 17:34:19.329801 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5602 17:34:19.332922 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 17:34:19.339824 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 17:34:19.342856 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 17:34:19.346289 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 17:34:19.353035 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 17:34:19.356376 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 17:34:19.359590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 17:34:19.366131 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 17:34:19.369981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 17:34:19.372960 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 17:34:19.376532 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 17:34:19.383116 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 17:34:19.386395 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 17:34:19.389880 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 17:34:19.396629 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 17:34:19.399442 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5618 17:34:19.403078 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 17:34:19.406467 Total UI for P1: 0, mck2ui 16
5620 17:34:19.409472 best dqsien dly found for B0: ( 1, 2, 24)
5621 17:34:19.412701 Total UI for P1: 0, mck2ui 16
5622 17:34:19.416703 best dqsien dly found for B1: ( 1, 2, 26)
5623 17:34:19.419561 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5624 17:34:19.423007 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5625 17:34:19.423416
5626 17:34:19.429867 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5627 17:34:19.432773 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5628 17:34:19.436518 [Gating] SW calibration Done
5629 17:34:19.437102 ==
5630 17:34:19.439767 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 17:34:19.442832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 17:34:19.443268 ==
5633 17:34:19.443593 RX Vref Scan: 0
5634 17:34:19.443953
5635 17:34:19.445958 RX Vref 0 -> 0, step: 1
5636 17:34:19.446366
5637 17:34:19.449813 RX Delay -80 -> 252, step: 8
5638 17:34:19.452859 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5639 17:34:19.456317 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5640 17:34:19.459748 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5641 17:34:19.465992 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5642 17:34:19.469331 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5643 17:34:19.472809 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5644 17:34:19.475821 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5645 17:34:19.479902 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5646 17:34:19.483092 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5647 17:34:19.489366 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5648 17:34:19.492646 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5649 17:34:19.496210 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5650 17:34:19.499223 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5651 17:34:19.502214 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5652 17:34:19.509386 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5653 17:34:19.512868 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5654 17:34:19.513280 ==
5655 17:34:19.515589 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 17:34:19.519207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 17:34:19.519673 ==
5658 17:34:19.522591 DQS Delay:
5659 17:34:19.523000 DQS0 = 0, DQS1 = 0
5660 17:34:19.523319 DQM Delay:
5661 17:34:19.525684 DQM0 = 103, DQM1 = 99
5662 17:34:19.526177 DQ Delay:
5663 17:34:19.529179 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5664 17:34:19.532391 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5665 17:34:19.535752 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5666 17:34:19.539189 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5667 17:34:19.539634
5668 17:34:19.540036
5669 17:34:19.542689 ==
5670 17:34:19.545531 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 17:34:19.548798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 17:34:19.549211 ==
5673 17:34:19.549531
5674 17:34:19.549828
5675 17:34:19.552349 TX Vref Scan disable
5676 17:34:19.552760 == TX Byte 0 ==
5677 17:34:19.555626 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5678 17:34:19.562122 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5679 17:34:19.562537 == TX Byte 1 ==
5680 17:34:19.569086 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5681 17:34:19.572463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5682 17:34:19.572911 ==
5683 17:34:19.575975 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 17:34:19.578896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 17:34:19.579310 ==
5686 17:34:19.579666
5687 17:34:19.580009
5688 17:34:19.582410 TX Vref Scan disable
5689 17:34:19.585876 == TX Byte 0 ==
5690 17:34:19.588646 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5691 17:34:19.592040 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5692 17:34:19.595497 == TX Byte 1 ==
5693 17:34:19.598617 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5694 17:34:19.601747 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5695 17:34:19.602158
5696 17:34:19.605339 [DATLAT]
5697 17:34:19.605876 Freq=933, CH1 RK0
5698 17:34:19.606246
5699 17:34:19.608761 DATLAT Default: 0xd
5700 17:34:19.609221 0, 0xFFFF, sum = 0
5701 17:34:19.611515 1, 0xFFFF, sum = 0
5702 17:34:19.611877 2, 0xFFFF, sum = 0
5703 17:34:19.615491 3, 0xFFFF, sum = 0
5704 17:34:19.615927 4, 0xFFFF, sum = 0
5705 17:34:19.618551 5, 0xFFFF, sum = 0
5706 17:34:19.618824 6, 0xFFFF, sum = 0
5707 17:34:19.621532 7, 0xFFFF, sum = 0
5708 17:34:19.621710 8, 0xFFFF, sum = 0
5709 17:34:19.625054 9, 0xFFFF, sum = 0
5710 17:34:19.625233 10, 0x0, sum = 1
5711 17:34:19.628478 11, 0x0, sum = 2
5712 17:34:19.628656 12, 0x0, sum = 3
5713 17:34:19.631661 13, 0x0, sum = 4
5714 17:34:19.631923 best_step = 11
5715 17:34:19.632066
5716 17:34:19.632194 ==
5717 17:34:19.634972 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 17:34:19.638368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 17:34:19.641930 ==
5720 17:34:19.642037 RX Vref Scan: 1
5721 17:34:19.642130
5722 17:34:19.645179 RX Vref 0 -> 0, step: 1
5723 17:34:19.645252
5724 17:34:19.648178 RX Delay -45 -> 252, step: 4
5725 17:34:19.648265
5726 17:34:19.648331 Set Vref, RX VrefLevel [Byte0]: 54
5727 17:34:19.651656 [Byte1]: 46
5728 17:34:19.656736
5729 17:34:19.656818 Final RX Vref Byte 0 = 54 to rank0
5730 17:34:19.659915 Final RX Vref Byte 1 = 46 to rank0
5731 17:34:19.663421 Final RX Vref Byte 0 = 54 to rank1
5732 17:34:19.666800 Final RX Vref Byte 1 = 46 to rank1==
5733 17:34:19.670225 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 17:34:19.676730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 17:34:19.676843 ==
5736 17:34:19.676931 DQS Delay:
5737 17:34:19.677012 DQS0 = 0, DQS1 = 0
5738 17:34:19.680313 DQM Delay:
5739 17:34:19.680425 DQM0 = 104, DQM1 = 99
5740 17:34:19.682820 DQ Delay:
5741 17:34:19.686386 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5742 17:34:19.689908 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =104
5743 17:34:19.693405 DQ8 =84, DQ9 =90, DQ10 =100, DQ11 =94
5744 17:34:19.696183 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =108
5745 17:34:19.696361
5746 17:34:19.696499
5747 17:34:19.703189 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5748 17:34:19.706641 CH1 RK0: MR19=505, MR18=152C
5749 17:34:19.713160 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5750 17:34:19.713294
5751 17:34:19.716137 ----->DramcWriteLeveling(PI) begin...
5752 17:34:19.716270 ==
5753 17:34:19.719541 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 17:34:19.722954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 17:34:19.726435 ==
5756 17:34:19.726507 Write leveling (Byte 0): 25 => 25
5757 17:34:19.729500 Write leveling (Byte 1): 27 => 27
5758 17:34:19.733081 DramcWriteLeveling(PI) end<-----
5759 17:34:19.733168
5760 17:34:19.733230 ==
5761 17:34:19.736389 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 17:34:19.742890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 17:34:19.742971 ==
5764 17:34:19.743034 [Gating] SW mode calibration
5765 17:34:19.752905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5766 17:34:19.756188 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5767 17:34:19.762540 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 17:34:19.766062 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 17:34:19.769494 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 17:34:19.772914 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 17:34:19.779883 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 17:34:19.782965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5773 17:34:19.786279 0 14 24 | B1->B0 | 2929 3131 | 0 1 | (0 0) (1 0)
5774 17:34:19.792518 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5775 17:34:19.796030 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 17:34:19.799416 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 17:34:19.805884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 17:34:19.809294 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 17:34:19.812907 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 17:34:19.819500 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 17:34:19.823084 0 15 24 | B1->B0 | 3939 2626 | 0 0 | (0 0) (0 0)
5782 17:34:19.826099 0 15 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5783 17:34:19.833020 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 17:34:19.836415 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 17:34:19.839603 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 17:34:19.845910 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 17:34:19.849778 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 17:34:19.852987 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5789 17:34:19.859192 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5790 17:34:19.863040 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 17:34:19.866441 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 17:34:19.872536 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 17:34:19.876154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 17:34:19.879553 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 17:34:19.886295 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 17:34:19.889673 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 17:34:19.892905 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 17:34:19.899388 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 17:34:19.902845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 17:34:19.906141 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 17:34:19.912577 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 17:34:19.915014 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 17:34:19.918454 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 17:34:19.925099 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 17:34:19.928954 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5806 17:34:19.931727 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5807 17:34:19.935001 Total UI for P1: 0, mck2ui 16
5808 17:34:19.938421 best dqsien dly found for B1: ( 1, 2, 24)
5809 17:34:19.941943 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 17:34:19.945259 Total UI for P1: 0, mck2ui 16
5811 17:34:19.948370 best dqsien dly found for B0: ( 1, 2, 28)
5812 17:34:19.951607 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5813 17:34:19.958508 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5814 17:34:19.958597
5815 17:34:19.961224 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5816 17:34:19.965059 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5817 17:34:19.968325 [Gating] SW calibration Done
5818 17:34:19.968407 ==
5819 17:34:19.971316 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 17:34:19.974819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 17:34:19.974894 ==
5822 17:34:19.978284 RX Vref Scan: 0
5823 17:34:19.978353
5824 17:34:19.978410 RX Vref 0 -> 0, step: 1
5825 17:34:19.978466
5826 17:34:19.981240 RX Delay -80 -> 252, step: 8
5827 17:34:19.984495 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5828 17:34:19.991631 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5829 17:34:19.995089 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5830 17:34:19.998311 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5831 17:34:20.001559 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5832 17:34:20.004438 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5833 17:34:20.008298 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5834 17:34:20.014655 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5835 17:34:20.018076 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5836 17:34:20.020876 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5837 17:34:20.024264 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5838 17:34:20.027953 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5839 17:34:20.034687 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5840 17:34:20.037805 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5841 17:34:20.041277 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5842 17:34:20.044747 iDelay=208, Bit 15, Center 107 (24 ~ 191) 168
5843 17:34:20.044832 ==
5844 17:34:20.047537 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 17:34:20.054383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 17:34:20.054468 ==
5847 17:34:20.054534 DQS Delay:
5848 17:34:20.054593 DQS0 = 0, DQS1 = 0
5849 17:34:20.057496 DQM Delay:
5850 17:34:20.057564 DQM0 = 105, DQM1 = 98
5851 17:34:20.061278 DQ Delay:
5852 17:34:20.064058 DQ0 =111, DQ1 =103, DQ2 =91, DQ3 =103
5853 17:34:20.067754 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5854 17:34:20.071142 DQ8 =83, DQ9 =91, DQ10 =103, DQ11 =91
5855 17:34:20.074586 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5856 17:34:20.074669
5857 17:34:20.074734
5858 17:34:20.074793 ==
5859 17:34:20.077937 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 17:34:20.081284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 17:34:20.081368 ==
5862 17:34:20.081432
5863 17:34:20.081491
5864 17:34:20.084444 TX Vref Scan disable
5865 17:34:20.087635 == TX Byte 0 ==
5866 17:34:20.091509 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 17:34:20.094351 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 17:34:20.097471 == TX Byte 1 ==
5869 17:34:20.101354 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5870 17:34:20.103946 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5871 17:34:20.104020 ==
5872 17:34:20.107548 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 17:34:20.114399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 17:34:20.114486 ==
5875 17:34:20.114553
5876 17:34:20.114615
5877 17:34:20.114673 TX Vref Scan disable
5878 17:34:20.118335 == TX Byte 0 ==
5879 17:34:20.121045 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5880 17:34:20.127986 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5881 17:34:20.128096 == TX Byte 1 ==
5882 17:34:20.131366 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5883 17:34:20.134886 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5884 17:34:20.138121
5885 17:34:20.138229 [DATLAT]
5886 17:34:20.138321 Freq=933, CH1 RK1
5887 17:34:20.138410
5888 17:34:20.141470 DATLAT Default: 0xb
5889 17:34:20.141574 0, 0xFFFF, sum = 0
5890 17:34:20.144542 1, 0xFFFF, sum = 0
5891 17:34:20.144622 2, 0xFFFF, sum = 0
5892 17:34:20.148034 3, 0xFFFF, sum = 0
5893 17:34:20.148109 4, 0xFFFF, sum = 0
5894 17:34:20.151389 5, 0xFFFF, sum = 0
5895 17:34:20.154853 6, 0xFFFF, sum = 0
5896 17:34:20.154945 7, 0xFFFF, sum = 0
5897 17:34:20.158226 8, 0xFFFF, sum = 0
5898 17:34:20.158341 9, 0xFFFF, sum = 0
5899 17:34:20.160923 10, 0x0, sum = 1
5900 17:34:20.161009 11, 0x0, sum = 2
5901 17:34:20.161076 12, 0x0, sum = 3
5902 17:34:20.164256 13, 0x0, sum = 4
5903 17:34:20.164342 best_step = 11
5904 17:34:20.164407
5905 17:34:20.168068 ==
5906 17:34:20.168172 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 17:34:20.174399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 17:34:20.174492 ==
5909 17:34:20.174559 RX Vref Scan: 0
5910 17:34:20.174620
5911 17:34:20.177826 RX Vref 0 -> 0, step: 1
5912 17:34:20.177910
5913 17:34:20.181020 RX Delay -53 -> 252, step: 4
5914 17:34:20.184448 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5915 17:34:20.190991 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5916 17:34:20.194425 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5917 17:34:20.197598 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5918 17:34:20.200826 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5919 17:34:20.204190 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5920 17:34:20.211351 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5921 17:34:20.214424 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5922 17:34:20.217508 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5923 17:34:20.221009 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5924 17:34:20.224620 iDelay=203, Bit 10, Center 100 (19 ~ 182) 164
5925 17:34:20.227598 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5926 17:34:20.234509 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5927 17:34:20.237875 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5928 17:34:20.241237 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5929 17:34:20.243922 iDelay=203, Bit 15, Center 106 (23 ~ 190) 168
5930 17:34:20.244020 ==
5931 17:34:20.247374 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 17:34:20.254068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 17:34:20.254190 ==
5934 17:34:20.254260 DQS Delay:
5935 17:34:20.257287 DQS0 = 0, DQS1 = 0
5936 17:34:20.257371 DQM Delay:
5937 17:34:20.260729 DQM0 = 105, DQM1 = 100
5938 17:34:20.260813 DQ Delay:
5939 17:34:20.264175 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5940 17:34:20.267532 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5941 17:34:20.270878 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5942 17:34:20.274246 DQ12 =110, DQ13 =104, DQ14 =104, DQ15 =106
5943 17:34:20.274329
5944 17:34:20.274392
5945 17:34:20.284379 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5946 17:34:20.284471 CH1 RK1: MR19=504, MR18=2CFE
5947 17:34:20.291057 CH1_RK1: MR19=0x504, MR18=0x2CFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5948 17:34:20.294281 [RxdqsGatingPostProcess] freq 933
5949 17:34:20.300867 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5950 17:34:20.304051 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 17:34:20.307269 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 17:34:20.310664 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 17:34:20.313967 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 17:34:20.317157 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 17:34:20.317239 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 17:34:20.320555 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 17:34:20.323866 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 17:34:20.327088 Pre-setting of DQS Precalculation
5959 17:34:20.334210 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5960 17:34:20.340687 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5961 17:34:20.346838 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5962 17:34:20.346945
5963 17:34:20.347011
5964 17:34:20.350325 [Calibration Summary] 1866 Mbps
5965 17:34:20.350407 CH 0, Rank 0
5966 17:34:20.353762 SW Impedance : PASS
5967 17:34:20.356974 DUTY Scan : NO K
5968 17:34:20.357054 ZQ Calibration : PASS
5969 17:34:20.360733 Jitter Meter : NO K
5970 17:34:20.363755 CBT Training : PASS
5971 17:34:20.363836 Write leveling : PASS
5972 17:34:20.366911 RX DQS gating : PASS
5973 17:34:20.370315 RX DQ/DQS(RDDQC) : PASS
5974 17:34:20.370395 TX DQ/DQS : PASS
5975 17:34:20.373743 RX DATLAT : PASS
5976 17:34:20.377161 RX DQ/DQS(Engine): PASS
5977 17:34:20.377243 TX OE : NO K
5978 17:34:20.380611 All Pass.
5979 17:34:20.380691
5980 17:34:20.380754 CH 0, Rank 1
5981 17:34:20.383772 SW Impedance : PASS
5982 17:34:20.383853 DUTY Scan : NO K
5983 17:34:20.386970 ZQ Calibration : PASS
5984 17:34:20.390052 Jitter Meter : NO K
5985 17:34:20.390133 CBT Training : PASS
5986 17:34:20.393855 Write leveling : PASS
5987 17:34:20.393937 RX DQS gating : PASS
5988 17:34:20.396861 RX DQ/DQS(RDDQC) : PASS
5989 17:34:20.400017 TX DQ/DQS : PASS
5990 17:34:20.400100 RX DATLAT : PASS
5991 17:34:20.403349 RX DQ/DQS(Engine): PASS
5992 17:34:20.406699 TX OE : NO K
5993 17:34:20.406781 All Pass.
5994 17:34:20.406844
5995 17:34:20.406903 CH 1, Rank 0
5996 17:34:20.409931 SW Impedance : PASS
5997 17:34:20.413248 DUTY Scan : NO K
5998 17:34:20.413329 ZQ Calibration : PASS
5999 17:34:20.416734 Jitter Meter : NO K
6000 17:34:20.420009 CBT Training : PASS
6001 17:34:20.420090 Write leveling : PASS
6002 17:34:20.423203 RX DQS gating : PASS
6003 17:34:20.426538 RX DQ/DQS(RDDQC) : PASS
6004 17:34:20.426619 TX DQ/DQS : PASS
6005 17:34:20.429942 RX DATLAT : PASS
6006 17:34:20.433361 RX DQ/DQS(Engine): PASS
6007 17:34:20.433460 TX OE : NO K
6008 17:34:20.436861 All Pass.
6009 17:34:20.436943
6010 17:34:20.437006 CH 1, Rank 1
6011 17:34:20.440274 SW Impedance : PASS
6012 17:34:20.440384 DUTY Scan : NO K
6013 17:34:20.443077 ZQ Calibration : PASS
6014 17:34:20.446761 Jitter Meter : NO K
6015 17:34:20.446843 CBT Training : PASS
6016 17:34:20.449774 Write leveling : PASS
6017 17:34:20.449856 RX DQS gating : PASS
6018 17:34:20.453483 RX DQ/DQS(RDDQC) : PASS
6019 17:34:20.456422 TX DQ/DQS : PASS
6020 17:34:20.456504 RX DATLAT : PASS
6021 17:34:20.460216 RX DQ/DQS(Engine): PASS
6022 17:34:20.463525 TX OE : NO K
6023 17:34:20.463606 All Pass.
6024 17:34:20.463715
6025 17:34:20.466534 DramC Write-DBI off
6026 17:34:20.466615 PER_BANK_REFRESH: Hybrid Mode
6027 17:34:20.470047 TX_TRACKING: ON
6028 17:34:20.479760 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6029 17:34:20.483114 [FAST_K] Save calibration result to emmc
6030 17:34:20.486545 dramc_set_vcore_voltage set vcore to 650000
6031 17:34:20.486628 Read voltage for 400, 6
6032 17:34:20.490020 Vio18 = 0
6033 17:34:20.490101 Vcore = 650000
6034 17:34:20.490165 Vdram = 0
6035 17:34:20.493340 Vddq = 0
6036 17:34:20.493421 Vmddr = 0
6037 17:34:20.496513 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6038 17:34:20.503569 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6039 17:34:20.506797 MEM_TYPE=3, freq_sel=20
6040 17:34:20.509954 sv_algorithm_assistance_LP4_800
6041 17:34:20.513058 ============ PULL DRAM RESETB DOWN ============
6042 17:34:20.516682 ========== PULL DRAM RESETB DOWN end =========
6043 17:34:20.523430 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6044 17:34:20.526738 ===================================
6045 17:34:20.526958 LPDDR4 DRAM CONFIGURATION
6046 17:34:20.529921 ===================================
6047 17:34:20.533293 EX_ROW_EN[0] = 0x0
6048 17:34:20.533570 EX_ROW_EN[1] = 0x0
6049 17:34:20.536566 LP4Y_EN = 0x0
6050 17:34:20.536811 WORK_FSP = 0x0
6051 17:34:20.539997 WL = 0x2
6052 17:34:20.540185 RL = 0x2
6053 17:34:20.543479 BL = 0x2
6054 17:34:20.546698 RPST = 0x0
6055 17:34:20.546951 RD_PRE = 0x0
6056 17:34:20.549475 WR_PRE = 0x1
6057 17:34:20.549664 WR_PST = 0x0
6058 17:34:20.552910 DBI_WR = 0x0
6059 17:34:20.553108 DBI_RD = 0x0
6060 17:34:20.556150 OTF = 0x1
6061 17:34:20.559425 ===================================
6062 17:34:20.563140 ===================================
6063 17:34:20.563370 ANA top config
6064 17:34:20.566042 ===================================
6065 17:34:20.569828 DLL_ASYNC_EN = 0
6066 17:34:20.573245 ALL_SLAVE_EN = 1
6067 17:34:20.573515 NEW_RANK_MODE = 1
6068 17:34:20.576313 DLL_IDLE_MODE = 1
6069 17:34:20.579501 LP45_APHY_COMB_EN = 1
6070 17:34:20.583174 TX_ODT_DIS = 1
6071 17:34:20.583397 NEW_8X_MODE = 1
6072 17:34:20.586520 ===================================
6073 17:34:20.589902 ===================================
6074 17:34:20.592575 data_rate = 800
6075 17:34:20.595880 CKR = 1
6076 17:34:20.599198 DQ_P2S_RATIO = 4
6077 17:34:20.602654 ===================================
6078 17:34:20.606069 CA_P2S_RATIO = 4
6079 17:34:20.609501 DQ_CA_OPEN = 0
6080 17:34:20.609642 DQ_SEMI_OPEN = 1
6081 17:34:20.612678 CA_SEMI_OPEN = 1
6082 17:34:20.615864 CA_FULL_RATE = 0
6083 17:34:20.619472 DQ_CKDIV4_EN = 0
6084 17:34:20.622663 CA_CKDIV4_EN = 1
6085 17:34:20.626050 CA_PREDIV_EN = 0
6086 17:34:20.626143 PH8_DLY = 0
6087 17:34:20.629321 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6088 17:34:20.632326 DQ_AAMCK_DIV = 0
6089 17:34:20.636010 CA_AAMCK_DIV = 0
6090 17:34:20.639441 CA_ADMCK_DIV = 4
6091 17:34:20.642749 DQ_TRACK_CA_EN = 0
6092 17:34:20.642833 CA_PICK = 800
6093 17:34:20.645987 CA_MCKIO = 400
6094 17:34:20.649357 MCKIO_SEMI = 400
6095 17:34:20.652758 PLL_FREQ = 3016
6096 17:34:20.656057 DQ_UI_PI_RATIO = 32
6097 17:34:20.659280 CA_UI_PI_RATIO = 32
6098 17:34:20.662438 ===================================
6099 17:34:20.665721 ===================================
6100 17:34:20.668957 memory_type:LPDDR4
6101 17:34:20.669030 GP_NUM : 10
6102 17:34:20.672743 SRAM_EN : 1
6103 17:34:20.672815 MD32_EN : 0
6104 17:34:20.675960 ===================================
6105 17:34:20.679153 [ANA_INIT] >>>>>>>>>>>>>>
6106 17:34:20.682273 <<<<<< [CONFIGURE PHASE]: ANA_TX
6107 17:34:20.685494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6108 17:34:20.689174 ===================================
6109 17:34:20.692531 data_rate = 800,PCW = 0X7400
6110 17:34:20.695842 ===================================
6111 17:34:20.699187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6112 17:34:20.705839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6113 17:34:20.715388 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6114 17:34:20.718739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6115 17:34:20.722106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6116 17:34:20.725401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6117 17:34:20.728831 [ANA_INIT] flow start
6118 17:34:20.731956 [ANA_INIT] PLL >>>>>>>>
6119 17:34:20.732037 [ANA_INIT] PLL <<<<<<<<
6120 17:34:20.735442 [ANA_INIT] MIDPI >>>>>>>>
6121 17:34:20.739072 [ANA_INIT] MIDPI <<<<<<<<
6122 17:34:20.739156 [ANA_INIT] DLL >>>>>>>>
6123 17:34:20.741901 [ANA_INIT] flow end
6124 17:34:20.745340 ============ LP4 DIFF to SE enter ============
6125 17:34:20.752228 ============ LP4 DIFF to SE exit ============
6126 17:34:20.752315 [ANA_INIT] <<<<<<<<<<<<<
6127 17:34:20.755365 [Flow] Enable top DCM control >>>>>
6128 17:34:20.758969 [Flow] Enable top DCM control <<<<<
6129 17:34:20.762068 Enable DLL master slave shuffle
6130 17:34:20.768533 ==============================================================
6131 17:34:20.768669 Gating Mode config
6132 17:34:20.775241 ==============================================================
6133 17:34:20.778533 Config description:
6134 17:34:20.785315 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6135 17:34:20.791779 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6136 17:34:20.798527 SELPH_MODE 0: By rank 1: By Phase
6137 17:34:20.805055 ==============================================================
6138 17:34:20.808443 GAT_TRACK_EN = 0
6139 17:34:20.808550 RX_GATING_MODE = 2
6140 17:34:20.811581 RX_GATING_TRACK_MODE = 2
6141 17:34:20.815066 SELPH_MODE = 1
6142 17:34:20.818336 PICG_EARLY_EN = 1
6143 17:34:20.821658 VALID_LAT_VALUE = 1
6144 17:34:20.828305 ==============================================================
6145 17:34:20.831857 Enter into Gating configuration >>>>
6146 17:34:20.835173 Exit from Gating configuration <<<<
6147 17:34:20.838482 Enter into DVFS_PRE_config >>>>>
6148 17:34:20.848141 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6149 17:34:20.851471 Exit from DVFS_PRE_config <<<<<
6150 17:34:20.854595 Enter into PICG configuration >>>>
6151 17:34:20.858257 Exit from PICG configuration <<<<
6152 17:34:20.861418 [RX_INPUT] configuration >>>>>
6153 17:34:20.864572 [RX_INPUT] configuration <<<<<
6154 17:34:20.868206 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6155 17:34:20.874578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6156 17:34:20.881458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6157 17:34:20.884929 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6158 17:34:20.891582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 17:34:20.898011 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 17:34:20.901609 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6161 17:34:20.904599 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6162 17:34:20.911274 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6163 17:34:20.914684 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6164 17:34:20.918046 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6165 17:34:20.924828 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 17:34:20.928118 ===================================
6167 17:34:20.928203 LPDDR4 DRAM CONFIGURATION
6168 17:34:20.931389 ===================================
6169 17:34:20.934573 EX_ROW_EN[0] = 0x0
6170 17:34:20.938022 EX_ROW_EN[1] = 0x0
6171 17:34:20.938106 LP4Y_EN = 0x0
6172 17:34:20.941499 WORK_FSP = 0x0
6173 17:34:20.941580 WL = 0x2
6174 17:34:20.944750 RL = 0x2
6175 17:34:20.944831 BL = 0x2
6176 17:34:20.948160 RPST = 0x0
6177 17:34:20.948241 RD_PRE = 0x0
6178 17:34:20.951569 WR_PRE = 0x1
6179 17:34:20.951700 WR_PST = 0x0
6180 17:34:20.954828 DBI_WR = 0x0
6181 17:34:20.954909 DBI_RD = 0x0
6182 17:34:20.958356 OTF = 0x1
6183 17:34:20.961487 ===================================
6184 17:34:20.964745 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6185 17:34:20.968109 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6186 17:34:20.974796 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6187 17:34:20.977937 ===================================
6188 17:34:20.978020 LPDDR4 DRAM CONFIGURATION
6189 17:34:20.981295 ===================================
6190 17:34:20.984343 EX_ROW_EN[0] = 0x10
6191 17:34:20.984426 EX_ROW_EN[1] = 0x0
6192 17:34:20.987572 LP4Y_EN = 0x0
6193 17:34:20.987663 WORK_FSP = 0x0
6194 17:34:20.991531 WL = 0x2
6195 17:34:20.994553 RL = 0x2
6196 17:34:20.994636 BL = 0x2
6197 17:34:20.997576 RPST = 0x0
6198 17:34:20.997659 RD_PRE = 0x0
6199 17:34:21.001139 WR_PRE = 0x1
6200 17:34:21.001221 WR_PST = 0x0
6201 17:34:21.004636 DBI_WR = 0x0
6202 17:34:21.004718 DBI_RD = 0x0
6203 17:34:21.007826 OTF = 0x1
6204 17:34:21.010880 ===================================
6205 17:34:21.014449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6206 17:34:21.020054 nWR fixed to 30
6207 17:34:21.022962 [ModeRegInit_LP4] CH0 RK0
6208 17:34:21.023072 [ModeRegInit_LP4] CH0 RK1
6209 17:34:21.026877 [ModeRegInit_LP4] CH1 RK0
6210 17:34:21.029533 [ModeRegInit_LP4] CH1 RK1
6211 17:34:21.029614 match AC timing 19
6212 17:34:21.036128 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6213 17:34:21.039494 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6214 17:34:21.043013 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6215 17:34:21.049649 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6216 17:34:21.053093 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6217 17:34:21.053176 ==
6218 17:34:21.056459 Dram Type= 6, Freq= 0, CH_0, rank 0
6219 17:34:21.059604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6220 17:34:21.059711 ==
6221 17:34:21.066260 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6222 17:34:21.073025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6223 17:34:21.076329 [CA 0] Center 36 (8~64) winsize 57
6224 17:34:21.079577 [CA 1] Center 36 (8~64) winsize 57
6225 17:34:21.082833 [CA 2] Center 36 (8~64) winsize 57
6226 17:34:21.082911 [CA 3] Center 36 (8~64) winsize 57
6227 17:34:21.085983 [CA 4] Center 36 (8~64) winsize 57
6228 17:34:21.089948 [CA 5] Center 36 (8~64) winsize 57
6229 17:34:21.090055
6230 17:34:21.096400 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6231 17:34:21.096503
6232 17:34:21.099847 [CATrainingPosCal] consider 1 rank data
6233 17:34:21.103039 u2DelayCellTimex100 = 270/100 ps
6234 17:34:21.106127 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 17:34:21.109663 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 17:34:21.112622 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 17:34:21.116387 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 17:34:21.119779 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 17:34:21.122542 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 17:34:21.122647
6241 17:34:21.126263 CA PerBit enable=1, Macro0, CA PI delay=36
6242 17:34:21.126364
6243 17:34:21.129340 [CBTSetCACLKResult] CA Dly = 36
6244 17:34:21.132545 CS Dly: 1 (0~32)
6245 17:34:21.132644 ==
6246 17:34:21.136014 Dram Type= 6, Freq= 0, CH_0, rank 1
6247 17:34:21.139447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 17:34:21.139548 ==
6249 17:34:21.145854 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 17:34:21.149412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 17:34:21.152754 [CA 0] Center 36 (8~64) winsize 57
6252 17:34:21.156094 [CA 1] Center 36 (8~64) winsize 57
6253 17:34:21.159387 [CA 2] Center 36 (8~64) winsize 57
6254 17:34:21.162794 [CA 3] Center 36 (8~64) winsize 57
6255 17:34:21.166162 [CA 4] Center 36 (8~64) winsize 57
6256 17:34:21.169371 [CA 5] Center 36 (8~64) winsize 57
6257 17:34:21.169450
6258 17:34:21.172656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 17:34:21.172736
6260 17:34:21.175982 [CATrainingPosCal] consider 2 rank data
6261 17:34:21.179341 u2DelayCellTimex100 = 270/100 ps
6262 17:34:21.182730 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 17:34:21.186104 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 17:34:21.189500 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 17:34:21.196469 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 17:34:21.199487 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 17:34:21.202771 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 17:34:21.202851
6269 17:34:21.205998 CA PerBit enable=1, Macro0, CA PI delay=36
6270 17:34:21.206077
6271 17:34:21.209326 [CBTSetCACLKResult] CA Dly = 36
6272 17:34:21.209405 CS Dly: 1 (0~32)
6273 17:34:21.209467
6274 17:34:21.212644 ----->DramcWriteLeveling(PI) begin...
6275 17:34:21.212725 ==
6276 17:34:21.215807 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 17:34:21.222368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 17:34:21.222450 ==
6279 17:34:21.225630 Write leveling (Byte 0): 40 => 8
6280 17:34:21.228975 Write leveling (Byte 1): 40 => 8
6281 17:34:21.229055 DramcWriteLeveling(PI) end<-----
6282 17:34:21.229117
6283 17:34:21.232320 ==
6284 17:34:21.236133 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 17:34:21.239413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 17:34:21.239506 ==
6287 17:34:21.242564 [Gating] SW mode calibration
6288 17:34:21.249063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6289 17:34:21.252362 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6290 17:34:21.259053 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6291 17:34:21.262405 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6292 17:34:21.265678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 17:34:21.272415 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 17:34:21.275521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 17:34:21.278902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 17:34:21.285589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 17:34:21.288995 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 17:34:21.292348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 17:34:21.295616 Total UI for P1: 0, mck2ui 16
6300 17:34:21.298918 best dqsien dly found for B0: ( 0, 14, 24)
6301 17:34:21.302121 Total UI for P1: 0, mck2ui 16
6302 17:34:21.305262 best dqsien dly found for B1: ( 0, 14, 24)
6303 17:34:21.308851 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6304 17:34:21.312159 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6305 17:34:21.312253
6306 17:34:21.318694 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6307 17:34:21.322068 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6308 17:34:21.325372 [Gating] SW calibration Done
6309 17:34:21.325451 ==
6310 17:34:21.328424 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 17:34:21.331947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 17:34:21.332026 ==
6313 17:34:21.332113 RX Vref Scan: 0
6314 17:34:21.332217
6315 17:34:21.335112 RX Vref 0 -> 0, step: 1
6316 17:34:21.335229
6317 17:34:21.338291 RX Delay -410 -> 252, step: 16
6318 17:34:21.341912 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6319 17:34:21.348366 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6320 17:34:21.351625 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6321 17:34:21.355042 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6322 17:34:21.358364 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6323 17:34:21.365074 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6324 17:34:21.368477 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6325 17:34:21.371507 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6326 17:34:21.375144 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6327 17:34:21.381389 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6328 17:34:21.385417 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6329 17:34:21.388579 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6330 17:34:21.391938 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6331 17:34:21.398225 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6332 17:34:21.401576 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6333 17:34:21.404983 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6334 17:34:21.405062 ==
6335 17:34:21.408388 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 17:34:21.411792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 17:34:21.415067 ==
6338 17:34:21.415146 DQS Delay:
6339 17:34:21.415208 DQS0 = 27, DQS1 = 35
6340 17:34:21.418295 DQM Delay:
6341 17:34:21.418377 DQM0 = 10, DQM1 = 12
6342 17:34:21.421271 DQ Delay:
6343 17:34:21.421346 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6344 17:34:21.424731 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6345 17:34:21.428454 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6346 17:34:21.431848 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6347 17:34:21.431923
6348 17:34:21.431984
6349 17:34:21.432042 ==
6350 17:34:21.434460 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 17:34:21.441162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 17:34:21.441266 ==
6353 17:34:21.441368
6354 17:34:21.441439
6355 17:34:21.444396 TX Vref Scan disable
6356 17:34:21.444469 == TX Byte 0 ==
6357 17:34:21.448320 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 17:34:21.454815 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 17:34:21.454893 == TX Byte 1 ==
6360 17:34:21.457878 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 17:34:21.461217 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 17:34:21.464563 ==
6363 17:34:21.467948 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 17:34:21.471272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 17:34:21.471352 ==
6366 17:34:21.471414
6367 17:34:21.471471
6368 17:34:21.474536 TX Vref Scan disable
6369 17:34:21.474618 == TX Byte 0 ==
6370 17:34:21.477875 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 17:34:21.484445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 17:34:21.484527 == TX Byte 1 ==
6373 17:34:21.487678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 17:34:21.494753 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 17:34:21.494835
6376 17:34:21.494899 [DATLAT]
6377 17:34:21.494958 Freq=400, CH0 RK0
6378 17:34:21.495017
6379 17:34:21.497995 DATLAT Default: 0xf
6380 17:34:21.498103 0, 0xFFFF, sum = 0
6381 17:34:21.501104 1, 0xFFFF, sum = 0
6382 17:34:21.501189 2, 0xFFFF, sum = 0
6383 17:34:21.504522 3, 0xFFFF, sum = 0
6384 17:34:21.507915 4, 0xFFFF, sum = 0
6385 17:34:21.508000 5, 0xFFFF, sum = 0
6386 17:34:21.511094 6, 0xFFFF, sum = 0
6387 17:34:21.511179 7, 0xFFFF, sum = 0
6388 17:34:21.514486 8, 0xFFFF, sum = 0
6389 17:34:21.514571 9, 0xFFFF, sum = 0
6390 17:34:21.517768 10, 0xFFFF, sum = 0
6391 17:34:21.517862 11, 0xFFFF, sum = 0
6392 17:34:21.520942 12, 0xFFFF, sum = 0
6393 17:34:21.521026 13, 0x0, sum = 1
6394 17:34:21.524192 14, 0x0, sum = 2
6395 17:34:21.524277 15, 0x0, sum = 3
6396 17:34:21.527598 16, 0x0, sum = 4
6397 17:34:21.527728 best_step = 14
6398 17:34:21.527813
6399 17:34:21.527902 ==
6400 17:34:21.530777 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 17:34:21.534046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 17:34:21.537727 ==
6403 17:34:21.537811 RX Vref Scan: 1
6404 17:34:21.537919
6405 17:34:21.540754 RX Vref 0 -> 0, step: 1
6406 17:34:21.540848
6407 17:34:21.544127 RX Delay -311 -> 252, step: 8
6408 17:34:21.544209
6409 17:34:21.544291 Set Vref, RX VrefLevel [Byte0]: 56
6410 17:34:21.547765 [Byte1]: 53
6411 17:34:21.553114
6412 17:34:21.553203 Final RX Vref Byte 0 = 56 to rank0
6413 17:34:21.556429 Final RX Vref Byte 1 = 53 to rank0
6414 17:34:21.559757 Final RX Vref Byte 0 = 56 to rank1
6415 17:34:21.563333 Final RX Vref Byte 1 = 53 to rank1==
6416 17:34:21.566349 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 17:34:21.572881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 17:34:21.572964 ==
6419 17:34:21.573047 DQS Delay:
6420 17:34:21.576106 DQS0 = 24, DQS1 = 36
6421 17:34:21.576182 DQM Delay:
6422 17:34:21.576262 DQM0 = 8, DQM1 = 12
6423 17:34:21.580051 DQ Delay:
6424 17:34:21.580146 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6425 17:34:21.583485 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6426 17:34:21.586645 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6427 17:34:21.589980 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6428 17:34:21.590060
6429 17:34:21.590139
6430 17:34:21.599434 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6431 17:34:21.603084 CH0 RK0: MR19=C0C, MR18=CAB8
6432 17:34:21.609267 CH0_RK0: MR19=0xC0C, MR18=0xCAB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6433 17:34:21.609347 ==
6434 17:34:21.612929 Dram Type= 6, Freq= 0, CH_0, rank 1
6435 17:34:21.616430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 17:34:21.616510 ==
6437 17:34:21.619453 [Gating] SW mode calibration
6438 17:34:21.626073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6439 17:34:21.629344 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6440 17:34:21.635720 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 17:34:21.639153 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 17:34:21.642474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 17:34:21.649408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 17:34:21.652764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 17:34:21.655693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 17:34:21.662458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 17:34:21.665691 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 17:34:21.669127 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 17:34:21.672872 Total UI for P1: 0, mck2ui 16
6450 17:34:21.675837 best dqsien dly found for B0: ( 0, 14, 24)
6451 17:34:21.679198 Total UI for P1: 0, mck2ui 16
6452 17:34:21.682798 best dqsien dly found for B1: ( 0, 14, 24)
6453 17:34:21.685732 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6454 17:34:21.689572 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6455 17:34:21.689650
6456 17:34:21.696297 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6457 17:34:21.699063 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6458 17:34:21.702514 [Gating] SW calibration Done
6459 17:34:21.702589 ==
6460 17:34:21.705811 Dram Type= 6, Freq= 0, CH_0, rank 1
6461 17:34:21.709160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 17:34:21.709242 ==
6463 17:34:21.709323 RX Vref Scan: 0
6464 17:34:21.709408
6465 17:34:21.712573 RX Vref 0 -> 0, step: 1
6466 17:34:21.712655
6467 17:34:21.715888 RX Delay -410 -> 252, step: 16
6468 17:34:21.719194 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6469 17:34:21.725767 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6470 17:34:21.728893 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6471 17:34:21.732197 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6472 17:34:21.735705 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6473 17:34:21.742093 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6474 17:34:21.745456 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6475 17:34:21.748665 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6476 17:34:21.752150 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6477 17:34:21.758553 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6478 17:34:21.762314 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6479 17:34:21.765375 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6480 17:34:21.769063 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6481 17:34:21.775574 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6482 17:34:21.778632 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6483 17:34:21.781842 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6484 17:34:21.781920 ==
6485 17:34:21.785678 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 17:34:21.788684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 17:34:21.791901 ==
6488 17:34:21.791977 DQS Delay:
6489 17:34:21.792079 DQS0 = 27, DQS1 = 35
6490 17:34:21.795614 DQM Delay:
6491 17:34:21.795722 DQM0 = 12, DQM1 = 11
6492 17:34:21.798721 DQ Delay:
6493 17:34:21.798795 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6494 17:34:21.802097 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6495 17:34:21.805496 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6496 17:34:21.808697 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6497 17:34:21.808771
6498 17:34:21.808831
6499 17:34:21.808888 ==
6500 17:34:21.812061 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 17:34:21.818622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 17:34:21.818703 ==
6503 17:34:21.818765
6504 17:34:21.818823
6505 17:34:21.818878 TX Vref Scan disable
6506 17:34:21.821965 == TX Byte 0 ==
6507 17:34:21.825321 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6508 17:34:21.828563 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6509 17:34:21.831680 == TX Byte 1 ==
6510 17:34:21.835373 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6511 17:34:21.838729 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6512 17:34:21.841905 ==
6513 17:34:21.841983 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 17:34:21.848732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 17:34:21.848810 ==
6516 17:34:21.848874
6517 17:34:21.848942
6518 17:34:21.851809 TX Vref Scan disable
6519 17:34:21.851886 == TX Byte 0 ==
6520 17:34:21.855416 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6521 17:34:21.862028 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6522 17:34:21.862105 == TX Byte 1 ==
6523 17:34:21.865418 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6524 17:34:21.868700 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6525 17:34:21.872054
6526 17:34:21.872147 [DATLAT]
6527 17:34:21.872220 Freq=400, CH0 RK1
6528 17:34:21.872314
6529 17:34:21.875496 DATLAT Default: 0xe
6530 17:34:21.875608 0, 0xFFFF, sum = 0
6531 17:34:21.878828 1, 0xFFFF, sum = 0
6532 17:34:21.878908 2, 0xFFFF, sum = 0
6533 17:34:21.882048 3, 0xFFFF, sum = 0
6534 17:34:21.882129 4, 0xFFFF, sum = 0
6535 17:34:21.885023 5, 0xFFFF, sum = 0
6536 17:34:21.885128 6, 0xFFFF, sum = 0
6537 17:34:21.888348 7, 0xFFFF, sum = 0
6538 17:34:21.892080 8, 0xFFFF, sum = 0
6539 17:34:21.892171 9, 0xFFFF, sum = 0
6540 17:34:21.894987 10, 0xFFFF, sum = 0
6541 17:34:21.895089 11, 0xFFFF, sum = 0
6542 17:34:21.898133 12, 0xFFFF, sum = 0
6543 17:34:21.898210 13, 0x0, sum = 1
6544 17:34:21.901783 14, 0x0, sum = 2
6545 17:34:21.901861 15, 0x0, sum = 3
6546 17:34:21.904785 16, 0x0, sum = 4
6547 17:34:21.904914 best_step = 14
6548 17:34:21.904996
6549 17:34:21.905080 ==
6550 17:34:21.908532 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 17:34:21.911685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 17:34:21.911783 ==
6553 17:34:21.915138 RX Vref Scan: 0
6554 17:34:21.915222
6555 17:34:21.917843 RX Vref 0 -> 0, step: 1
6556 17:34:21.917928
6557 17:34:21.918008 RX Delay -311 -> 252, step: 8
6558 17:34:21.927166 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6559 17:34:21.929946 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6560 17:34:21.933328 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6561 17:34:21.936639 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6562 17:34:21.943695 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6563 17:34:21.946956 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6564 17:34:21.950355 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6565 17:34:21.953642 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6566 17:34:21.959938 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6567 17:34:21.963199 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6568 17:34:21.966714 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6569 17:34:21.973079 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6570 17:34:21.976318 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6571 17:34:21.979573 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6572 17:34:21.983072 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6573 17:34:21.989762 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6574 17:34:21.989844 ==
6575 17:34:21.992903 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 17:34:21.996760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 17:34:21.996842 ==
6578 17:34:21.996905 DQS Delay:
6579 17:34:21.999804 DQS0 = 24, DQS1 = 32
6580 17:34:21.999883 DQM Delay:
6581 17:34:22.003605 DQM0 = 8, DQM1 = 9
6582 17:34:22.003704 DQ Delay:
6583 17:34:22.006243 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6584 17:34:22.009781 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6585 17:34:22.013094 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6586 17:34:22.016198 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6587 17:34:22.016299
6588 17:34:22.016387
6589 17:34:22.022965 [DQSOSCAuto] RK1, (LSB)MR18= 0xb151, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6590 17:34:22.026191 CH0 RK1: MR19=C0C, MR18=B151
6591 17:34:22.032778 CH0_RK1: MR19=0xC0C, MR18=0xB151, DQSOSC=387, MR23=63, INC=394, DEC=262
6592 17:34:22.036666 [RxdqsGatingPostProcess] freq 400
6593 17:34:22.040090 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6594 17:34:22.043354 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 17:34:22.046612 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 17:34:22.049631 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 17:34:22.052931 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 17:34:22.056321 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 17:34:22.059551 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 17:34:22.062957 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 17:34:22.066090 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 17:34:22.069380 Pre-setting of DQS Precalculation
6603 17:34:22.072701 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6604 17:34:22.076294 ==
6605 17:34:22.076375 Dram Type= 6, Freq= 0, CH_1, rank 0
6606 17:34:22.082728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 17:34:22.082809 ==
6608 17:34:22.086164 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6609 17:34:22.093206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6610 17:34:22.096429 [CA 0] Center 36 (8~64) winsize 57
6611 17:34:22.099570 [CA 1] Center 36 (8~64) winsize 57
6612 17:34:22.102870 [CA 2] Center 36 (8~64) winsize 57
6613 17:34:22.106117 [CA 3] Center 36 (8~64) winsize 57
6614 17:34:22.109359 [CA 4] Center 36 (8~64) winsize 57
6615 17:34:22.112747 [CA 5] Center 36 (8~64) winsize 57
6616 17:34:22.112827
6617 17:34:22.115862 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6618 17:34:22.115942
6619 17:34:22.119624 [CATrainingPosCal] consider 1 rank data
6620 17:34:22.122699 u2DelayCellTimex100 = 270/100 ps
6621 17:34:22.126157 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 17:34:22.129849 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 17:34:22.132821 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 17:34:22.135938 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 17:34:22.139240 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 17:34:22.145941 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 17:34:22.146056
6628 17:34:22.149348 CA PerBit enable=1, Macro0, CA PI delay=36
6629 17:34:22.149459
6630 17:34:22.152776 [CBTSetCACLKResult] CA Dly = 36
6631 17:34:22.152895 CS Dly: 1 (0~32)
6632 17:34:22.153003 ==
6633 17:34:22.155983 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 17:34:22.159206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 17:34:22.162338 ==
6636 17:34:22.166205 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 17:34:22.172769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6638 17:34:22.176066 [CA 0] Center 36 (8~64) winsize 57
6639 17:34:22.179409 [CA 1] Center 36 (8~64) winsize 57
6640 17:34:22.182775 [CA 2] Center 36 (8~64) winsize 57
6641 17:34:22.186083 [CA 3] Center 36 (8~64) winsize 57
6642 17:34:22.189471 [CA 4] Center 36 (8~64) winsize 57
6643 17:34:22.192832 [CA 5] Center 36 (8~64) winsize 57
6644 17:34:22.192950
6645 17:34:22.195867 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6646 17:34:22.195984
6647 17:34:22.198993 [CATrainingPosCal] consider 2 rank data
6648 17:34:22.202479 u2DelayCellTimex100 = 270/100 ps
6649 17:34:22.205725 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 17:34:22.209049 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 17:34:22.212521 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 17:34:22.216008 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 17:34:22.219319 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 17:34:22.222615 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 17:34:22.222732
6656 17:34:22.225978 CA PerBit enable=1, Macro0, CA PI delay=36
6657 17:34:22.226094
6658 17:34:22.229379 [CBTSetCACLKResult] CA Dly = 36
6659 17:34:22.232515 CS Dly: 1 (0~32)
6660 17:34:22.232632
6661 17:34:22.235754 ----->DramcWriteLeveling(PI) begin...
6662 17:34:22.235898 ==
6663 17:34:22.239226 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 17:34:22.242748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 17:34:22.242890 ==
6666 17:34:22.245856 Write leveling (Byte 0): 40 => 8
6667 17:34:22.249031 Write leveling (Byte 1): 40 => 8
6668 17:34:22.252529 DramcWriteLeveling(PI) end<-----
6669 17:34:22.252661
6670 17:34:22.252783 ==
6671 17:34:22.255806 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 17:34:22.259128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 17:34:22.259256 ==
6674 17:34:22.262349 [Gating] SW mode calibration
6675 17:34:22.269342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6676 17:34:22.275573 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6677 17:34:22.279014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6678 17:34:22.282405 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6679 17:34:22.289170 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 17:34:22.292580 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 17:34:22.295436 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 17:34:22.302286 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 17:34:22.305506 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 17:34:22.308717 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 17:34:22.315846 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 17:34:22.319161 Total UI for P1: 0, mck2ui 16
6687 17:34:22.322368 best dqsien dly found for B0: ( 0, 14, 24)
6688 17:34:22.325323 Total UI for P1: 0, mck2ui 16
6689 17:34:22.328814 best dqsien dly found for B1: ( 0, 14, 24)
6690 17:34:22.332050 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6691 17:34:22.335222 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6692 17:34:22.335367
6693 17:34:22.339036 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6694 17:34:22.342406 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6695 17:34:22.345626 [Gating] SW calibration Done
6696 17:34:22.345719 ==
6697 17:34:22.348698 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 17:34:22.352330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 17:34:22.352424 ==
6700 17:34:22.355572 RX Vref Scan: 0
6701 17:34:22.355702
6702 17:34:22.358475 RX Vref 0 -> 0, step: 1
6703 17:34:22.358562
6704 17:34:22.358646 RX Delay -410 -> 252, step: 16
6705 17:34:22.365661 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6706 17:34:22.368982 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6707 17:34:22.372053 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6708 17:34:22.375313 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6709 17:34:22.382174 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6710 17:34:22.385522 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6711 17:34:22.388251 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6712 17:34:22.391611 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6713 17:34:22.398334 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6714 17:34:22.401720 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6715 17:34:22.405160 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6716 17:34:22.408662 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6717 17:34:22.415323 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6718 17:34:22.418587 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6719 17:34:22.421978 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6720 17:34:22.428668 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6721 17:34:22.428752 ==
6722 17:34:22.432092 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 17:34:22.435412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 17:34:22.435491 ==
6725 17:34:22.435603 DQS Delay:
6726 17:34:22.438714 DQS0 = 27, DQS1 = 35
6727 17:34:22.438802 DQM Delay:
6728 17:34:22.441808 DQM0 = 11, DQM1 = 13
6729 17:34:22.441891 DQ Delay:
6730 17:34:22.444974 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6731 17:34:22.448506 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6732 17:34:22.451351 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6733 17:34:22.454715 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6734 17:34:22.454801
6735 17:34:22.454883
6736 17:34:22.454972 ==
6737 17:34:22.458285 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 17:34:22.461723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 17:34:22.461809 ==
6740 17:34:22.461902
6741 17:34:22.461986
6742 17:34:22.465112 TX Vref Scan disable
6743 17:34:22.465219 == TX Byte 0 ==
6744 17:34:22.471522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 17:34:22.475111 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 17:34:22.475217 == TX Byte 1 ==
6747 17:34:22.481578 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 17:34:22.484925 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 17:34:22.485025 ==
6750 17:34:22.488555 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 17:34:22.491523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 17:34:22.491631 ==
6753 17:34:22.491744
6754 17:34:22.491837
6755 17:34:22.494852 TX Vref Scan disable
6756 17:34:22.494943 == TX Byte 0 ==
6757 17:34:22.501690 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 17:34:22.504941 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 17:34:22.505041 == TX Byte 1 ==
6760 17:34:22.511739 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 17:34:22.515179 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 17:34:22.515288
6763 17:34:22.515379 [DATLAT]
6764 17:34:22.518423 Freq=400, CH1 RK0
6765 17:34:22.518532
6766 17:34:22.518622 DATLAT Default: 0xf
6767 17:34:22.521726 0, 0xFFFF, sum = 0
6768 17:34:22.521830 1, 0xFFFF, sum = 0
6769 17:34:22.524957 2, 0xFFFF, sum = 0
6770 17:34:22.525060 3, 0xFFFF, sum = 0
6771 17:34:22.528308 4, 0xFFFF, sum = 0
6772 17:34:22.528406 5, 0xFFFF, sum = 0
6773 17:34:22.531554 6, 0xFFFF, sum = 0
6774 17:34:22.531673 7, 0xFFFF, sum = 0
6775 17:34:22.534969 8, 0xFFFF, sum = 0
6776 17:34:22.535053 9, 0xFFFF, sum = 0
6777 17:34:22.538384 10, 0xFFFF, sum = 0
6778 17:34:22.538493 11, 0xFFFF, sum = 0
6779 17:34:22.541734 12, 0xFFFF, sum = 0
6780 17:34:22.545178 13, 0x0, sum = 1
6781 17:34:22.545280 14, 0x0, sum = 2
6782 17:34:22.545373 15, 0x0, sum = 3
6783 17:34:22.548463 16, 0x0, sum = 4
6784 17:34:22.548566 best_step = 14
6785 17:34:22.548667
6786 17:34:22.548757 ==
6787 17:34:22.551651 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 17:34:22.558194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 17:34:22.558305 ==
6790 17:34:22.558393 RX Vref Scan: 1
6791 17:34:22.558490
6792 17:34:22.561439 RX Vref 0 -> 0, step: 1
6793 17:34:22.561559
6794 17:34:22.565202 RX Delay -311 -> 252, step: 8
6795 17:34:22.565318
6796 17:34:22.568390 Set Vref, RX VrefLevel [Byte0]: 54
6797 17:34:22.571508 [Byte1]: 46
6798 17:34:22.571607
6799 17:34:22.574669 Final RX Vref Byte 0 = 54 to rank0
6800 17:34:22.578447 Final RX Vref Byte 1 = 46 to rank0
6801 17:34:22.581400 Final RX Vref Byte 0 = 54 to rank1
6802 17:34:22.584727 Final RX Vref Byte 1 = 46 to rank1==
6803 17:34:22.588042 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 17:34:22.591654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 17:34:22.594762 ==
6806 17:34:22.594837 DQS Delay:
6807 17:34:22.594905 DQS0 = 32, DQS1 = 32
6808 17:34:22.598514 DQM Delay:
6809 17:34:22.598611 DQM0 = 13, DQM1 = 11
6810 17:34:22.601812 DQ Delay:
6811 17:34:22.601946 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6812 17:34:22.605142 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6813 17:34:22.608267 DQ8 =0, DQ9 =4, DQ10 =8, DQ11 =4
6814 17:34:22.611646 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6815 17:34:22.611738
6816 17:34:22.611799
6817 17:34:22.621858 [DQSOSCAuto] RK0, (LSB)MR18= 0x89c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 392 ps
6818 17:34:22.625122 CH1 RK0: MR19=C0C, MR18=89C0
6819 17:34:22.631581 CH1_RK0: MR19=0xC0C, MR18=0x89C0, DQSOSC=386, MR23=63, INC=396, DEC=264
6820 17:34:22.631686 ==
6821 17:34:22.634973 Dram Type= 6, Freq= 0, CH_1, rank 1
6822 17:34:22.638340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 17:34:22.638421 ==
6824 17:34:22.641674 [Gating] SW mode calibration
6825 17:34:22.648370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6826 17:34:22.651828 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6827 17:34:22.658307 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6828 17:34:22.661638 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6829 17:34:22.664924 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 17:34:22.671463 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 17:34:22.674710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 17:34:22.677904 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 17:34:22.684609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 17:34:22.687983 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 17:34:22.691584 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 17:34:22.694619 Total UI for P1: 0, mck2ui 16
6837 17:34:22.697767 best dqsien dly found for B0: ( 0, 14, 24)
6838 17:34:22.701227 Total UI for P1: 0, mck2ui 16
6839 17:34:22.704417 best dqsien dly found for B1: ( 0, 14, 24)
6840 17:34:22.708345 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6841 17:34:22.711150 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6842 17:34:22.711229
6843 17:34:22.718204 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6844 17:34:22.721784 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6845 17:34:22.724483 [Gating] SW calibration Done
6846 17:34:22.724572 ==
6847 17:34:22.727824 Dram Type= 6, Freq= 0, CH_1, rank 1
6848 17:34:22.731305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 17:34:22.731390 ==
6850 17:34:22.731453 RX Vref Scan: 0
6851 17:34:22.731512
6852 17:34:22.734328 RX Vref 0 -> 0, step: 1
6853 17:34:22.734437
6854 17:34:22.737900 RX Delay -410 -> 252, step: 16
6855 17:34:22.741026 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6856 17:34:22.747831 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6857 17:34:22.751135 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6858 17:34:22.754340 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6859 17:34:22.757741 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6860 17:34:22.761000 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6861 17:34:22.767576 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6862 17:34:22.770844 iDelay=230, Bit 7, Center -11 (-234 ~ 213) 448
6863 17:34:22.774184 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6864 17:34:22.777546 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6865 17:34:22.784683 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6866 17:34:22.787386 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6867 17:34:22.790780 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6868 17:34:22.794258 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6869 17:34:22.801222 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6870 17:34:22.804190 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6871 17:34:22.804271 ==
6872 17:34:22.807602 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 17:34:22.810787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 17:34:22.810870 ==
6875 17:34:22.814719 DQS Delay:
6876 17:34:22.814798 DQS0 = 35, DQS1 = 35
6877 17:34:22.818143 DQM Delay:
6878 17:34:22.818218 DQM0 = 21, DQM1 = 19
6879 17:34:22.818299 DQ Delay:
6880 17:34:22.821402 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6881 17:34:22.824712 DQ4 =24, DQ5 =32, DQ6 =32, DQ7 =24
6882 17:34:22.828087 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =16
6883 17:34:22.830833 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6884 17:34:22.830908
6885 17:34:22.830997
6886 17:34:22.831070 ==
6887 17:34:22.834592 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 17:34:22.840732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 17:34:22.840826 ==
6890 17:34:22.840911
6891 17:34:22.840998
6892 17:34:22.841075 TX Vref Scan disable
6893 17:34:22.844533 == TX Byte 0 ==
6894 17:34:22.847532 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6895 17:34:22.850623 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6896 17:34:22.854305 == TX Byte 1 ==
6897 17:34:22.857412 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6898 17:34:22.860717 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6899 17:34:22.860803 ==
6900 17:34:22.864045 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 17:34:22.870694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 17:34:22.870783 ==
6903 17:34:22.870867
6904 17:34:22.870953
6905 17:34:22.871030 TX Vref Scan disable
6906 17:34:22.873869 == TX Byte 0 ==
6907 17:34:22.877640 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6908 17:34:22.880967 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6909 17:34:22.884381 == TX Byte 1 ==
6910 17:34:22.887560 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6911 17:34:22.890885 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6912 17:34:22.890970
6913 17:34:22.894171 [DATLAT]
6914 17:34:22.894251 Freq=400, CH1 RK1
6915 17:34:22.894315
6916 17:34:22.897522 DATLAT Default: 0xe
6917 17:34:22.897602 0, 0xFFFF, sum = 0
6918 17:34:22.900770 1, 0xFFFF, sum = 0
6919 17:34:22.900852 2, 0xFFFF, sum = 0
6920 17:34:22.904050 3, 0xFFFF, sum = 0
6921 17:34:22.904130 4, 0xFFFF, sum = 0
6922 17:34:22.907313 5, 0xFFFF, sum = 0
6923 17:34:22.907394 6, 0xFFFF, sum = 0
6924 17:34:22.910592 7, 0xFFFF, sum = 0
6925 17:34:22.910673 8, 0xFFFF, sum = 0
6926 17:34:22.913643 9, 0xFFFF, sum = 0
6927 17:34:22.917289 10, 0xFFFF, sum = 0
6928 17:34:22.917370 11, 0xFFFF, sum = 0
6929 17:34:22.920268 12, 0xFFFF, sum = 0
6930 17:34:22.920349 13, 0x0, sum = 1
6931 17:34:22.923922 14, 0x0, sum = 2
6932 17:34:22.924003 15, 0x0, sum = 3
6933 17:34:22.927053 16, 0x0, sum = 4
6934 17:34:22.927138 best_step = 14
6935 17:34:22.927232
6936 17:34:22.927310 ==
6937 17:34:22.930478 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 17:34:22.933689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 17:34:22.933774 ==
6940 17:34:22.937099 RX Vref Scan: 0
6941 17:34:22.937188
6942 17:34:22.940456 RX Vref 0 -> 0, step: 1
6943 17:34:22.940547
6944 17:34:22.940654 RX Delay -311 -> 252, step: 8
6945 17:34:22.949014 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6946 17:34:22.952209 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6947 17:34:22.956024 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6948 17:34:22.959363 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6949 17:34:22.965693 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6950 17:34:22.968676 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6951 17:34:22.972339 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6952 17:34:22.975813 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6953 17:34:22.982122 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6954 17:34:22.985502 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6955 17:34:22.988801 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6956 17:34:22.992363 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6957 17:34:22.998763 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6958 17:34:23.002069 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6959 17:34:23.005458 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6960 17:34:23.011920 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6961 17:34:23.012007 ==
6962 17:34:23.015368 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 17:34:23.018589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 17:34:23.018670 ==
6965 17:34:23.018733 DQS Delay:
6966 17:34:23.021722 DQS0 = 28, DQS1 = 36
6967 17:34:23.021806 DQM Delay:
6968 17:34:23.025593 DQM0 = 11, DQM1 = 15
6969 17:34:23.025698 DQ Delay:
6970 17:34:23.028835 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6971 17:34:23.031907 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6972 17:34:23.035540 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6973 17:34:23.038869 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6974 17:34:23.038952
6975 17:34:23.039015
6976 17:34:23.045389 [DQSOSCAuto] RK1, (LSB)MR18= 0xb94a, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6977 17:34:23.048649 CH1 RK1: MR19=C0C, MR18=B94A
6978 17:34:23.055299 CH1_RK1: MR19=0xC0C, MR18=0xB94A, DQSOSC=386, MR23=63, INC=396, DEC=264
6979 17:34:23.058532 [RxdqsGatingPostProcess] freq 400
6980 17:34:23.065234 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6981 17:34:23.065317 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 17:34:23.068545 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 17:34:23.071752 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 17:34:23.075074 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 17:34:23.078281 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 17:34:23.081408 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 17:34:23.085377 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 17:34:23.088356 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 17:34:23.091338 Pre-setting of DQS Precalculation
6990 17:34:23.098561 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6991 17:34:23.105068 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6992 17:34:23.111214 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6993 17:34:23.111298
6994 17:34:23.111363
6995 17:34:23.114654 [Calibration Summary] 800 Mbps
6996 17:34:23.114725 CH 0, Rank 0
6997 17:34:23.117998 SW Impedance : PASS
6998 17:34:23.121377 DUTY Scan : NO K
6999 17:34:23.121449 ZQ Calibration : PASS
7000 17:34:23.124584 Jitter Meter : NO K
7001 17:34:23.128109 CBT Training : PASS
7002 17:34:23.128189 Write leveling : PASS
7003 17:34:23.131416 RX DQS gating : PASS
7004 17:34:23.131494 RX DQ/DQS(RDDQC) : PASS
7005 17:34:23.134795 TX DQ/DQS : PASS
7006 17:34:23.138025 RX DATLAT : PASS
7007 17:34:23.138102 RX DQ/DQS(Engine): PASS
7008 17:34:23.141274 TX OE : NO K
7009 17:34:23.141375 All Pass.
7010 17:34:23.141472
7011 17:34:23.144340 CH 0, Rank 1
7012 17:34:23.144413 SW Impedance : PASS
7013 17:34:23.147438 DUTY Scan : NO K
7014 17:34:23.151227 ZQ Calibration : PASS
7015 17:34:23.151301 Jitter Meter : NO K
7016 17:34:23.154409 CBT Training : PASS
7017 17:34:23.157651 Write leveling : NO K
7018 17:34:23.157763 RX DQS gating : PASS
7019 17:34:23.161051 RX DQ/DQS(RDDQC) : PASS
7020 17:34:23.164227 TX DQ/DQS : PASS
7021 17:34:23.164319 RX DATLAT : PASS
7022 17:34:23.167620 RX DQ/DQS(Engine): PASS
7023 17:34:23.171012 TX OE : NO K
7024 17:34:23.171089 All Pass.
7025 17:34:23.171151
7026 17:34:23.171217 CH 1, Rank 0
7027 17:34:23.174317 SW Impedance : PASS
7028 17:34:23.177467 DUTY Scan : NO K
7029 17:34:23.177556 ZQ Calibration : PASS
7030 17:34:23.180717 Jitter Meter : NO K
7031 17:34:23.180790 CBT Training : PASS
7032 17:34:23.184004 Write leveling : PASS
7033 17:34:23.187305 RX DQS gating : PASS
7034 17:34:23.187388 RX DQ/DQS(RDDQC) : PASS
7035 17:34:23.190613 TX DQ/DQS : PASS
7036 17:34:23.194550 RX DATLAT : PASS
7037 17:34:23.194629 RX DQ/DQS(Engine): PASS
7038 17:34:23.197496 TX OE : NO K
7039 17:34:23.197566 All Pass.
7040 17:34:23.197625
7041 17:34:23.201062 CH 1, Rank 1
7042 17:34:23.201132 SW Impedance : PASS
7043 17:34:23.204254 DUTY Scan : NO K
7044 17:34:23.207438 ZQ Calibration : PASS
7045 17:34:23.207523 Jitter Meter : NO K
7046 17:34:23.210629 CBT Training : PASS
7047 17:34:23.213936 Write leveling : NO K
7048 17:34:23.214015 RX DQS gating : PASS
7049 17:34:23.217345 RX DQ/DQS(RDDQC) : PASS
7050 17:34:23.220745 TX DQ/DQS : PASS
7051 17:34:23.220815 RX DATLAT : PASS
7052 17:34:23.224011 RX DQ/DQS(Engine): PASS
7053 17:34:23.227238 TX OE : NO K
7054 17:34:23.227318 All Pass.
7055 17:34:23.227378
7056 17:34:23.227435 DramC Write-DBI off
7057 17:34:23.230644 PER_BANK_REFRESH: Hybrid Mode
7058 17:34:23.234113 TX_TRACKING: ON
7059 17:34:23.240835 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7060 17:34:23.244174 [FAST_K] Save calibration result to emmc
7061 17:34:23.250744 dramc_set_vcore_voltage set vcore to 725000
7062 17:34:23.250818 Read voltage for 1600, 0
7063 17:34:23.253931 Vio18 = 0
7064 17:34:23.254011 Vcore = 725000
7065 17:34:23.254073 Vdram = 0
7066 17:34:23.257103 Vddq = 0
7067 17:34:23.257172 Vmddr = 0
7068 17:34:23.260689 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7069 17:34:23.267184 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7070 17:34:23.270301 MEM_TYPE=3, freq_sel=13
7071 17:34:23.273579 sv_algorithm_assistance_LP4_3733
7072 17:34:23.276933 ============ PULL DRAM RESETB DOWN ============
7073 17:34:23.280231 ========== PULL DRAM RESETB DOWN end =========
7074 17:34:23.284006 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7075 17:34:23.287237 ===================================
7076 17:34:23.290438 LPDDR4 DRAM CONFIGURATION
7077 17:34:23.293642 ===================================
7078 17:34:23.297067 EX_ROW_EN[0] = 0x0
7079 17:34:23.297144 EX_ROW_EN[1] = 0x0
7080 17:34:23.300436 LP4Y_EN = 0x0
7081 17:34:23.300503 WORK_FSP = 0x1
7082 17:34:23.303890 WL = 0x5
7083 17:34:23.303957 RL = 0x5
7084 17:34:23.306955 BL = 0x2
7085 17:34:23.307021 RPST = 0x0
7086 17:34:23.309954 RD_PRE = 0x0
7087 17:34:23.310031 WR_PRE = 0x1
7088 17:34:23.313178 WR_PST = 0x1
7089 17:34:23.316857 DBI_WR = 0x0
7090 17:34:23.316938 DBI_RD = 0x0
7091 17:34:23.320011 OTF = 0x1
7092 17:34:23.323764 ===================================
7093 17:34:23.326463 ===================================
7094 17:34:23.326544 ANA top config
7095 17:34:23.330288 ===================================
7096 17:34:23.333550 DLL_ASYNC_EN = 0
7097 17:34:23.337007 ALL_SLAVE_EN = 0
7098 17:34:23.337082 NEW_RANK_MODE = 1
7099 17:34:23.339659 DLL_IDLE_MODE = 1
7100 17:34:23.343046 LP45_APHY_COMB_EN = 1
7101 17:34:23.346404 TX_ODT_DIS = 0
7102 17:34:23.346487 NEW_8X_MODE = 1
7103 17:34:23.349696 ===================================
7104 17:34:23.353065 ===================================
7105 17:34:23.356802 data_rate = 3200
7106 17:34:23.360034 CKR = 1
7107 17:34:23.363430 DQ_P2S_RATIO = 8
7108 17:34:23.366837 ===================================
7109 17:34:23.369938 CA_P2S_RATIO = 8
7110 17:34:23.372945 DQ_CA_OPEN = 0
7111 17:34:23.373025 DQ_SEMI_OPEN = 0
7112 17:34:23.376693 CA_SEMI_OPEN = 0
7113 17:34:23.379613 CA_FULL_RATE = 0
7114 17:34:23.383022 DQ_CKDIV4_EN = 0
7115 17:34:23.386346 CA_CKDIV4_EN = 0
7116 17:34:23.389590 CA_PREDIV_EN = 0
7117 17:34:23.389669 PH8_DLY = 12
7118 17:34:23.393116 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7119 17:34:23.396135 DQ_AAMCK_DIV = 4
7120 17:34:23.399928 CA_AAMCK_DIV = 4
7121 17:34:23.403227 CA_ADMCK_DIV = 4
7122 17:34:23.406568 DQ_TRACK_CA_EN = 0
7123 17:34:23.409806 CA_PICK = 1600
7124 17:34:23.409886 CA_MCKIO = 1600
7125 17:34:23.413094 MCKIO_SEMI = 0
7126 17:34:23.416191 PLL_FREQ = 3068
7127 17:34:23.419333 DQ_UI_PI_RATIO = 32
7128 17:34:23.423114 CA_UI_PI_RATIO = 0
7129 17:34:23.426317 ===================================
7130 17:34:23.429350 ===================================
7131 17:34:23.433152 memory_type:LPDDR4
7132 17:34:23.433231 GP_NUM : 10
7133 17:34:23.436188 SRAM_EN : 1
7134 17:34:23.436292 MD32_EN : 0
7135 17:34:23.439409 ===================================
7136 17:34:23.442770 [ANA_INIT] >>>>>>>>>>>>>>
7137 17:34:23.446321 <<<<<< [CONFIGURE PHASE]: ANA_TX
7138 17:34:23.449537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7139 17:34:23.452915 ===================================
7140 17:34:23.456228 data_rate = 3200,PCW = 0X7600
7141 17:34:23.459600 ===================================
7142 17:34:23.462900 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7143 17:34:23.469437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7144 17:34:23.472822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7145 17:34:23.479507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7146 17:34:23.482826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7147 17:34:23.486189 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7148 17:34:23.486269 [ANA_INIT] flow start
7149 17:34:23.489142 [ANA_INIT] PLL >>>>>>>>
7150 17:34:23.492315 [ANA_INIT] PLL <<<<<<<<
7151 17:34:23.492394 [ANA_INIT] MIDPI >>>>>>>>
7152 17:34:23.495957 [ANA_INIT] MIDPI <<<<<<<<
7153 17:34:23.498917 [ANA_INIT] DLL >>>>>>>>
7154 17:34:23.498996 [ANA_INIT] DLL <<<<<<<<
7155 17:34:23.502393 [ANA_INIT] flow end
7156 17:34:23.505861 ============ LP4 DIFF to SE enter ============
7157 17:34:23.509296 ============ LP4 DIFF to SE exit ============
7158 17:34:23.512765 [ANA_INIT] <<<<<<<<<<<<<
7159 17:34:23.515660 [Flow] Enable top DCM control >>>>>
7160 17:34:23.519043 [Flow] Enable top DCM control <<<<<
7161 17:34:23.522313 Enable DLL master slave shuffle
7162 17:34:23.528905 ==============================================================
7163 17:34:23.528985 Gating Mode config
7164 17:34:23.535482 ==============================================================
7165 17:34:23.535562 Config description:
7166 17:34:23.545702 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7167 17:34:23.552346 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7168 17:34:23.559152 SELPH_MODE 0: By rank 1: By Phase
7169 17:34:23.562571 ==============================================================
7170 17:34:23.565984 GAT_TRACK_EN = 1
7171 17:34:23.569227 RX_GATING_MODE = 2
7172 17:34:23.572389 RX_GATING_TRACK_MODE = 2
7173 17:34:23.575747 SELPH_MODE = 1
7174 17:34:23.579068 PICG_EARLY_EN = 1
7175 17:34:23.581880 VALID_LAT_VALUE = 1
7176 17:34:23.588508 ==============================================================
7177 17:34:23.591873 Enter into Gating configuration >>>>
7178 17:34:23.595373 Exit from Gating configuration <<<<
7179 17:34:23.598698 Enter into DVFS_PRE_config >>>>>
7180 17:34:23.608406 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7181 17:34:23.611663 Exit from DVFS_PRE_config <<<<<
7182 17:34:23.615471 Enter into PICG configuration >>>>
7183 17:34:23.618292 Exit from PICG configuration <<<<
7184 17:34:23.621826 [RX_INPUT] configuration >>>>>
7185 17:34:23.621905 [RX_INPUT] configuration <<<<<
7186 17:34:23.628631 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7187 17:34:23.634931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7188 17:34:23.642032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7189 17:34:23.645278 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7190 17:34:23.651562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 17:34:23.658488 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 17:34:23.661823 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7193 17:34:23.665185 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7194 17:34:23.671881 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7195 17:34:23.675157 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7196 17:34:23.678458 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7197 17:34:23.684572 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 17:34:23.688192 ===================================
7199 17:34:23.688273 LPDDR4 DRAM CONFIGURATION
7200 17:34:23.691468 ===================================
7201 17:34:23.694846 EX_ROW_EN[0] = 0x0
7202 17:34:23.694922 EX_ROW_EN[1] = 0x0
7203 17:34:23.698188 LP4Y_EN = 0x0
7204 17:34:23.701613 WORK_FSP = 0x1
7205 17:34:23.701692 WL = 0x5
7206 17:34:23.704882 RL = 0x5
7207 17:34:23.704962 BL = 0x2
7208 17:34:23.708224 RPST = 0x0
7209 17:34:23.708303 RD_PRE = 0x0
7210 17:34:23.711400 WR_PRE = 0x1
7211 17:34:23.711479 WR_PST = 0x1
7212 17:34:23.714807 DBI_WR = 0x0
7213 17:34:23.714886 DBI_RD = 0x0
7214 17:34:23.718193 OTF = 0x1
7215 17:34:23.721518 ===================================
7216 17:34:23.724865 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7217 17:34:23.728020 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7218 17:34:23.731253 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7219 17:34:23.734616 ===================================
7220 17:34:23.737911 LPDDR4 DRAM CONFIGURATION
7221 17:34:23.741207 ===================================
7222 17:34:23.745001 EX_ROW_EN[0] = 0x10
7223 17:34:23.745081 EX_ROW_EN[1] = 0x0
7224 17:34:23.747937 LP4Y_EN = 0x0
7225 17:34:23.748017 WORK_FSP = 0x1
7226 17:34:23.751408 WL = 0x5
7227 17:34:23.751487 RL = 0x5
7228 17:34:23.754624 BL = 0x2
7229 17:34:23.757652 RPST = 0x0
7230 17:34:23.757747 RD_PRE = 0x0
7231 17:34:23.761451 WR_PRE = 0x1
7232 17:34:23.761532 WR_PST = 0x1
7233 17:34:23.764640 DBI_WR = 0x0
7234 17:34:23.764714 DBI_RD = 0x0
7235 17:34:23.767804 OTF = 0x1
7236 17:34:23.771379 ===================================
7237 17:34:23.774335 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7238 17:34:23.777787 ==
7239 17:34:23.781449 Dram Type= 6, Freq= 0, CH_0, rank 0
7240 17:34:23.784605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7241 17:34:23.784685 ==
7242 17:34:23.787914 [Duty_Offset_Calibration]
7243 17:34:23.787993 B0:2 B1:1 CA:1
7244 17:34:23.788087
7245 17:34:23.791361 [DutyScan_Calibration_Flow] k_type=0
7246 17:34:23.800847
7247 17:34:23.800926 ==CLK 0==
7248 17:34:23.804126 Final CLK duty delay cell = 0
7249 17:34:23.807421 [0] MAX Duty = 5156%(X100), DQS PI = 22
7250 17:34:23.811449 [0] MIN Duty = 4876%(X100), DQS PI = 48
7251 17:34:23.811529 [0] AVG Duty = 5016%(X100)
7252 17:34:23.814077
7253 17:34:23.817951 CH0 CLK Duty spec in!! Max-Min= 280%
7254 17:34:23.821257 [DutyScan_Calibration_Flow] ====Done====
7255 17:34:23.821336
7256 17:34:23.824585 [DutyScan_Calibration_Flow] k_type=1
7257 17:34:23.839995
7258 17:34:23.840079 ==DQS 0 ==
7259 17:34:23.843396 Final DQS duty delay cell = -4
7260 17:34:23.846781 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7261 17:34:23.850185 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7262 17:34:23.853502 [-4] AVG Duty = 4906%(X100)
7263 17:34:23.853582
7264 17:34:23.853645 ==DQS 1 ==
7265 17:34:23.856898 Final DQS duty delay cell = 0
7266 17:34:23.860186 [0] MAX Duty = 5187%(X100), DQS PI = 4
7267 17:34:23.863368 [0] MIN Duty = 5062%(X100), DQS PI = 36
7268 17:34:23.866544 [0] AVG Duty = 5124%(X100)
7269 17:34:23.866623
7270 17:34:23.869840 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7271 17:34:23.869919
7272 17:34:23.873664 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7273 17:34:23.876644 [DutyScan_Calibration_Flow] ====Done====
7274 17:34:23.876723
7275 17:34:23.879945 [DutyScan_Calibration_Flow] k_type=3
7276 17:34:23.896556
7277 17:34:23.896636 ==DQM 0 ==
7278 17:34:23.899841 Final DQM duty delay cell = 0
7279 17:34:23.903167 [0] MAX Duty = 5218%(X100), DQS PI = 34
7280 17:34:23.906630 [0] MIN Duty = 4907%(X100), DQS PI = 0
7281 17:34:23.906710 [0] AVG Duty = 5062%(X100)
7282 17:34:23.909953
7283 17:34:23.910032 ==DQM 1 ==
7284 17:34:23.913175 Final DQM duty delay cell = -4
7285 17:34:23.916397 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7286 17:34:23.919685 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7287 17:34:23.922898 [-4] AVG Duty = 4906%(X100)
7288 17:34:23.922977
7289 17:34:23.926272 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7290 17:34:23.926369
7291 17:34:23.929589 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7292 17:34:23.933538 [DutyScan_Calibration_Flow] ====Done====
7293 17:34:23.933617
7294 17:34:23.936169 [DutyScan_Calibration_Flow] k_type=2
7295 17:34:23.954286
7296 17:34:23.954369 ==DQ 0 ==
7297 17:34:23.957628 Final DQ duty delay cell = 0
7298 17:34:23.961044 [0] MAX Duty = 5062%(X100), DQS PI = 24
7299 17:34:23.964242 [0] MIN Duty = 4907%(X100), DQS PI = 0
7300 17:34:23.964321 [0] AVG Duty = 4984%(X100)
7301 17:34:23.964384
7302 17:34:23.967601 ==DQ 1 ==
7303 17:34:23.970824 Final DQ duty delay cell = 0
7304 17:34:23.974210 [0] MAX Duty = 5156%(X100), DQS PI = 22
7305 17:34:23.977605 [0] MIN Duty = 4938%(X100), DQS PI = 34
7306 17:34:23.977684 [0] AVG Duty = 5047%(X100)
7307 17:34:23.977747
7308 17:34:23.980967 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7309 17:34:23.984221
7310 17:34:23.987477 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7311 17:34:23.990580 [DutyScan_Calibration_Flow] ====Done====
7312 17:34:23.990659 ==
7313 17:34:23.994205 Dram Type= 6, Freq= 0, CH_1, rank 0
7314 17:34:23.997799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7315 17:34:23.997878 ==
7316 17:34:24.000803 [Duty_Offset_Calibration]
7317 17:34:24.000882 B0:1 B1:0 CA:0
7318 17:34:24.000944
7319 17:34:24.004323 [DutyScan_Calibration_Flow] k_type=0
7320 17:34:24.013783
7321 17:34:24.013862 ==CLK 0==
7322 17:34:24.016898 Final CLK duty delay cell = -4
7323 17:34:24.020334 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7324 17:34:24.023294 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7325 17:34:24.026604 [-4] AVG Duty = 4906%(X100)
7326 17:34:24.026682
7327 17:34:24.029791 CH1 CLK Duty spec in!! Max-Min= 125%
7328 17:34:24.033509 [DutyScan_Calibration_Flow] ====Done====
7329 17:34:24.033619
7330 17:34:24.036736 [DutyScan_Calibration_Flow] k_type=1
7331 17:34:24.053890
7332 17:34:24.053972 ==DQS 0 ==
7333 17:34:24.057307 Final DQS duty delay cell = 0
7334 17:34:24.060576 [0] MAX Duty = 5094%(X100), DQS PI = 24
7335 17:34:24.063325 [0] MIN Duty = 4875%(X100), DQS PI = 0
7336 17:34:24.066688 [0] AVG Duty = 4984%(X100)
7337 17:34:24.066767
7338 17:34:24.066828 ==DQS 1 ==
7339 17:34:24.070513 Final DQS duty delay cell = 0
7340 17:34:24.073747 [0] MAX Duty = 5249%(X100), DQS PI = 16
7341 17:34:24.076943 [0] MIN Duty = 4969%(X100), DQS PI = 6
7342 17:34:24.080386 [0] AVG Duty = 5109%(X100)
7343 17:34:24.080464
7344 17:34:24.083662 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7345 17:34:24.083754
7346 17:34:24.087005 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7347 17:34:24.090223 [DutyScan_Calibration_Flow] ====Done====
7348 17:34:24.090302
7349 17:34:24.093574 [DutyScan_Calibration_Flow] k_type=3
7350 17:34:24.110358
7351 17:34:24.110443 ==DQM 0 ==
7352 17:34:24.113944 Final DQM duty delay cell = 0
7353 17:34:24.117458 [0] MAX Duty = 5218%(X100), DQS PI = 18
7354 17:34:24.120369 [0] MIN Duty = 4969%(X100), DQS PI = 48
7355 17:34:24.120449 [0] AVG Duty = 5093%(X100)
7356 17:34:24.123927
7357 17:34:24.124007 ==DQM 1 ==
7358 17:34:24.127345 Final DQM duty delay cell = 0
7359 17:34:24.130684 [0] MAX Duty = 5093%(X100), DQS PI = 16
7360 17:34:24.134118 [0] MIN Duty = 4907%(X100), DQS PI = 34
7361 17:34:24.134198 [0] AVG Duty = 5000%(X100)
7362 17:34:24.137312
7363 17:34:24.140405 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7364 17:34:24.140502
7365 17:34:24.144083 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7366 17:34:24.147208 [DutyScan_Calibration_Flow] ====Done====
7367 17:34:24.147287
7368 17:34:24.150672 [DutyScan_Calibration_Flow] k_type=2
7369 17:34:24.166849
7370 17:34:24.166931 ==DQ 0 ==
7371 17:34:24.170036 Final DQ duty delay cell = -4
7372 17:34:24.173288 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7373 17:34:24.176637 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7374 17:34:24.179839 [-4] AVG Duty = 4953%(X100)
7375 17:34:24.179918
7376 17:34:24.179979 ==DQ 1 ==
7377 17:34:24.183046 Final DQ duty delay cell = 0
7378 17:34:24.186350 [0] MAX Duty = 5125%(X100), DQS PI = 18
7379 17:34:24.189798 [0] MIN Duty = 4938%(X100), DQS PI = 8
7380 17:34:24.189878 [0] AVG Duty = 5031%(X100)
7381 17:34:24.193057
7382 17:34:24.196367 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7383 17:34:24.196447
7384 17:34:24.199713 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7385 17:34:24.203132 [DutyScan_Calibration_Flow] ====Done====
7386 17:34:24.206317 nWR fixed to 30
7387 17:34:24.206397 [ModeRegInit_LP4] CH0 RK0
7388 17:34:24.209681 [ModeRegInit_LP4] CH0 RK1
7389 17:34:24.212913 [ModeRegInit_LP4] CH1 RK0
7390 17:34:24.216100 [ModeRegInit_LP4] CH1 RK1
7391 17:34:24.216179 match AC timing 5
7392 17:34:24.222843 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7393 17:34:24.226476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7394 17:34:24.229560 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7395 17:34:24.236236 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7396 17:34:24.239631 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7397 17:34:24.239720 [MiockJmeterHQA]
7398 17:34:24.239783
7399 17:34:24.242967 [DramcMiockJmeter] u1RxGatingPI = 0
7400 17:34:24.246366 0 : 4365, 4137
7401 17:34:24.246447 4 : 4363, 4137
7402 17:34:24.249520 8 : 4253, 4026
7403 17:34:24.249601 12 : 4252, 4027
7404 17:34:24.249665 16 : 4363, 4137
7405 17:34:24.252952 20 : 4363, 4137
7406 17:34:24.253031 24 : 4253, 4026
7407 17:34:24.256440 28 : 4252, 4026
7408 17:34:24.256520 32 : 4252, 4027
7409 17:34:24.259745 36 : 4363, 4137
7410 17:34:24.259825 40 : 4252, 4026
7411 17:34:24.263140 44 : 4363, 4137
7412 17:34:24.263220 48 : 4252, 4027
7413 17:34:24.263281 52 : 4253, 4026
7414 17:34:24.266529 56 : 4250, 4027
7415 17:34:24.266609 60 : 4252, 4029
7416 17:34:24.269618 64 : 4361, 4137
7417 17:34:24.269698 68 : 4250, 4027
7418 17:34:24.272606 72 : 4360, 4137
7419 17:34:24.272687 76 : 4250, 4027
7420 17:34:24.272749 80 : 4249, 4027
7421 17:34:24.276132 84 : 4250, 4025
7422 17:34:24.276212 88 : 4361, 98
7423 17:34:24.279538 92 : 4253, 0
7424 17:34:24.279649 96 : 4253, 0
7425 17:34:24.279739 100 : 4253, 0
7426 17:34:24.282943 104 : 4252, 0
7427 17:34:24.283023 108 : 4252, 0
7428 17:34:24.286081 112 : 4360, 0
7429 17:34:24.286161 116 : 4250, 0
7430 17:34:24.286224 120 : 4250, 0
7431 17:34:24.289399 124 : 4250, 0
7432 17:34:24.289480 128 : 4363, 0
7433 17:34:24.289563 132 : 4250, 0
7434 17:34:24.293103 136 : 4250, 0
7435 17:34:24.293184 140 : 4252, 0
7436 17:34:24.296426 144 : 4361, 0
7437 17:34:24.296510 148 : 4250, 0
7438 17:34:24.296573 152 : 4250, 0
7439 17:34:24.299656 156 : 4250, 0
7440 17:34:24.299803 160 : 4361, 0
7441 17:34:24.302973 164 : 4250, 0
7442 17:34:24.303053 168 : 4250, 0
7443 17:34:24.303116 172 : 4250, 0
7444 17:34:24.306317 176 : 4360, 0
7445 17:34:24.306415 180 : 4360, 0
7446 17:34:24.309601 184 : 4250, 0
7447 17:34:24.309682 188 : 4250, 0
7448 17:34:24.309745 192 : 4252, 0
7449 17:34:24.312919 196 : 4250, 0
7450 17:34:24.312999 200 : 4250, 0
7451 17:34:24.316247 204 : 4252, 1345
7452 17:34:24.316327 208 : 4250, 3998
7453 17:34:24.316390 212 : 4250, 4026
7454 17:34:24.319380 216 : 4361, 4137
7455 17:34:24.319486 220 : 4252, 4029
7456 17:34:24.322719 224 : 4250, 4026
7457 17:34:24.322799 228 : 4361, 4137
7458 17:34:24.326090 232 : 4361, 4137
7459 17:34:24.326171 236 : 4250, 4027
7460 17:34:24.329510 240 : 4363, 4140
7461 17:34:24.329591 244 : 4361, 4137
7462 17:34:24.332785 248 : 4250, 4027
7463 17:34:24.332865 252 : 4250, 4027
7464 17:34:24.336008 256 : 4252, 4029
7465 17:34:24.336088 260 : 4250, 4026
7466 17:34:24.339533 264 : 4250, 4027
7467 17:34:24.339646 268 : 4250, 4027
7468 17:34:24.339731 272 : 4250, 4027
7469 17:34:24.342553 276 : 4250, 4026
7470 17:34:24.342633 280 : 4361, 4137
7471 17:34:24.346461 284 : 4361, 4137
7472 17:34:24.346541 288 : 4250, 4027
7473 17:34:24.349212 292 : 4363, 4140
7474 17:34:24.349292 296 : 4361, 4137
7475 17:34:24.353206 300 : 4250, 4026
7476 17:34:24.353287 304 : 4250, 4027
7477 17:34:24.356462 308 : 4252, 3999
7478 17:34:24.356542 312 : 4250, 1971
7479 17:34:24.356606
7480 17:34:24.359787 MIOCK jitter meter ch=0
7481 17:34:24.359865
7482 17:34:24.363083 1T = (312-88) = 224 dly cells
7483 17:34:24.366342 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7484 17:34:24.369701 ==
7485 17:34:24.372426 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 17:34:24.375780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 17:34:24.375859 ==
7488 17:34:24.379185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 17:34:24.385744 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 17:34:24.389124 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 17:34:24.395688 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 17:34:24.403949 [CA 0] Center 42 (12~73) winsize 62
7493 17:34:24.407565 [CA 1] Center 42 (12~73) winsize 62
7494 17:34:24.410538 [CA 2] Center 38 (8~68) winsize 61
7495 17:34:24.413970 [CA 3] Center 37 (7~67) winsize 61
7496 17:34:24.417223 [CA 4] Center 36 (6~66) winsize 61
7497 17:34:24.420676 [CA 5] Center 35 (6~64) winsize 59
7498 17:34:24.420755
7499 17:34:24.424006 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7500 17:34:24.424117
7501 17:34:24.427196 [CATrainingPosCal] consider 1 rank data
7502 17:34:24.430427 u2DelayCellTimex100 = 290/100 ps
7503 17:34:24.433835 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7504 17:34:24.440585 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7505 17:34:24.443871 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7506 17:34:24.447201 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7507 17:34:24.450816 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7508 17:34:24.454127 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7509 17:34:24.454207
7510 17:34:24.457355 CA PerBit enable=1, Macro0, CA PI delay=35
7511 17:34:24.457434
7512 17:34:24.460608 [CBTSetCACLKResult] CA Dly = 35
7513 17:34:24.464051 CS Dly: 9 (0~40)
7514 17:34:24.467379 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 17:34:24.470658 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 17:34:24.470738 ==
7517 17:34:24.474031 Dram Type= 6, Freq= 0, CH_0, rank 1
7518 17:34:24.477341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 17:34:24.477421 ==
7520 17:34:24.483987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 17:34:24.487482 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 17:34:24.494002 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 17:34:24.497141 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 17:34:24.507576 [CA 0] Center 42 (12~73) winsize 62
7525 17:34:24.510961 [CA 1] Center 42 (12~73) winsize 62
7526 17:34:24.514351 [CA 2] Center 38 (8~68) winsize 61
7527 17:34:24.517641 [CA 3] Center 37 (7~67) winsize 61
7528 17:34:24.520759 [CA 4] Center 36 (6~66) winsize 61
7529 17:34:24.523780 [CA 5] Center 35 (5~65) winsize 61
7530 17:34:24.523858
7531 17:34:24.527350 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 17:34:24.527429
7533 17:34:24.530737 [CATrainingPosCal] consider 2 rank data
7534 17:34:24.534325 u2DelayCellTimex100 = 290/100 ps
7535 17:34:24.537408 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7536 17:34:24.544174 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7537 17:34:24.547042 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7538 17:34:24.550535 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7539 17:34:24.553994 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7540 17:34:24.556892 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7541 17:34:24.556972
7542 17:34:24.559971 CA PerBit enable=1, Macro0, CA PI delay=35
7543 17:34:24.560050
7544 17:34:24.563736 [CBTSetCACLKResult] CA Dly = 35
7545 17:34:24.566836 CS Dly: 10 (0~42)
7546 17:34:24.570017 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 17:34:24.573429 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 17:34:24.573508
7549 17:34:24.576701 ----->DramcWriteLeveling(PI) begin...
7550 17:34:24.576781 ==
7551 17:34:24.580024 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 17:34:24.586651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 17:34:24.586731 ==
7554 17:34:24.590102 Write leveling (Byte 0): 36 => 36
7555 17:34:24.590182 Write leveling (Byte 1): 30 => 30
7556 17:34:24.593428 DramcWriteLeveling(PI) end<-----
7557 17:34:24.593507
7558 17:34:24.596744 ==
7559 17:34:24.596855 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 17:34:24.603398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 17:34:24.603479 ==
7562 17:34:24.606657 [Gating] SW mode calibration
7563 17:34:24.613195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7564 17:34:24.616385 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7565 17:34:24.623146 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 17:34:24.626464 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7567 17:34:24.629976 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7568 17:34:24.636605 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7569 17:34:24.639790 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7570 17:34:24.643231 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7571 17:34:24.649612 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 17:34:24.653410 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7573 17:34:24.656768 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 17:34:24.663660 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 17:34:24.666525 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 17:34:24.669813 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7577 17:34:24.676476 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7578 17:34:24.679994 1 5 20 | B1->B0 | 2727 2525 | 1 0 | (1 0) (0 0)
7579 17:34:24.682970 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7580 17:34:24.689774 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 17:34:24.693278 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 17:34:24.696063 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7583 17:34:24.699393 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7584 17:34:24.706296 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7585 17:34:24.709766 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7586 17:34:24.713040 1 6 20 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
7587 17:34:24.719819 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 17:34:24.723148 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 17:34:24.726576 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 17:34:24.732512 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 17:34:24.736519 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 17:34:24.739182 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 17:34:24.745888 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7594 17:34:24.749174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 17:34:24.752929 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 17:34:24.759201 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 17:34:24.763015 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 17:34:24.765825 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 17:34:24.772908 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 17:34:24.775618 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 17:34:24.778904 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 17:34:24.785874 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 17:34:24.789228 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 17:34:24.792674 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 17:34:24.799065 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 17:34:24.802405 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 17:34:24.805842 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 17:34:24.812395 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7609 17:34:24.815828 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7610 17:34:24.819167 Total UI for P1: 0, mck2ui 16
7611 17:34:24.822401 best dqsien dly found for B0: ( 1, 9, 10)
7612 17:34:24.825836 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7613 17:34:24.829169 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 17:34:24.832404 Total UI for P1: 0, mck2ui 16
7615 17:34:24.835659 best dqsien dly found for B1: ( 1, 9, 20)
7616 17:34:24.839170 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7617 17:34:24.845928 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7618 17:34:24.846006
7619 17:34:24.849311 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7620 17:34:24.852656 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7621 17:34:24.855422 [Gating] SW calibration Done
7622 17:34:24.855494 ==
7623 17:34:24.858716 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 17:34:24.862014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 17:34:24.862087 ==
7626 17:34:24.865900 RX Vref Scan: 0
7627 17:34:24.865978
7628 17:34:24.866039 RX Vref 0 -> 0, step: 1
7629 17:34:24.866096
7630 17:34:24.869212 RX Delay 0 -> 252, step: 8
7631 17:34:24.872398 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7632 17:34:24.875470 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7633 17:34:24.882247 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7634 17:34:24.885638 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7635 17:34:24.889000 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7636 17:34:24.892254 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7637 17:34:24.895560 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7638 17:34:24.902434 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7639 17:34:24.905569 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7640 17:34:24.909258 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7641 17:34:24.912502 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7642 17:34:24.915796 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7643 17:34:24.922680 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7644 17:34:24.925453 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7645 17:34:24.928886 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7646 17:34:24.932287 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7647 17:34:24.932361 ==
7648 17:34:24.935411 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 17:34:24.942172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 17:34:24.942264 ==
7651 17:34:24.942329 DQS Delay:
7652 17:34:24.942396 DQS0 = 0, DQS1 = 0
7653 17:34:24.945432 DQM Delay:
7654 17:34:24.945513 DQM0 = 137, DQM1 = 129
7655 17:34:24.948878 DQ Delay:
7656 17:34:24.952347 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7657 17:34:24.955663 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7658 17:34:24.959159 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7659 17:34:24.962440 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7660 17:34:24.962512
7661 17:34:24.962591
7662 17:34:24.962663 ==
7663 17:34:24.965672 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 17:34:24.968950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 17:34:24.972268 ==
7666 17:34:24.972337
7667 17:34:24.972406
7668 17:34:24.972463 TX Vref Scan disable
7669 17:34:24.975704 == TX Byte 0 ==
7670 17:34:24.979048 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7671 17:34:24.982179 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7672 17:34:24.985309 == TX Byte 1 ==
7673 17:34:24.988480 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7674 17:34:24.992211 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7675 17:34:24.995602 ==
7676 17:34:24.995714 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 17:34:25.001569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 17:34:25.001643 ==
7679 17:34:25.014477
7680 17:34:25.017550 TX Vref early break, caculate TX vref
7681 17:34:25.021434 TX Vref=16, minBit 11, minWin=22, winSum=376
7682 17:34:25.024042 TX Vref=18, minBit 0, minWin=22, winSum=383
7683 17:34:25.027405 TX Vref=20, minBit 0, minWin=24, winSum=398
7684 17:34:25.030585 TX Vref=22, minBit 0, minWin=24, winSum=404
7685 17:34:25.034377 TX Vref=24, minBit 1, minWin=25, winSum=418
7686 17:34:25.040664 TX Vref=26, minBit 3, minWin=25, winSum=424
7687 17:34:25.044171 TX Vref=28, minBit 0, minWin=25, winSum=425
7688 17:34:25.047148 TX Vref=30, minBit 1, minWin=24, winSum=408
7689 17:34:25.051008 TX Vref=32, minBit 0, minWin=24, winSum=403
7690 17:34:25.054355 TX Vref=34, minBit 1, minWin=23, winSum=396
7691 17:34:25.060999 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
7692 17:34:25.061086
7693 17:34:25.064268 Final TX Range 0 Vref 28
7694 17:34:25.064347
7695 17:34:25.064408 ==
7696 17:34:25.067534 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 17:34:25.070969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 17:34:25.071046 ==
7699 17:34:25.071108
7700 17:34:25.071165
7701 17:34:25.074328 TX Vref Scan disable
7702 17:34:25.080875 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7703 17:34:25.080952 == TX Byte 0 ==
7704 17:34:25.084282 u2DelayCellOfst[0]=10 cells (3 PI)
7705 17:34:25.087581 u2DelayCellOfst[1]=13 cells (4 PI)
7706 17:34:25.090877 u2DelayCellOfst[2]=10 cells (3 PI)
7707 17:34:25.094547 u2DelayCellOfst[3]=10 cells (3 PI)
7708 17:34:25.097686 u2DelayCellOfst[4]=6 cells (2 PI)
7709 17:34:25.100743 u2DelayCellOfst[5]=0 cells (0 PI)
7710 17:34:25.100821 u2DelayCellOfst[6]=16 cells (5 PI)
7711 17:34:25.104110 u2DelayCellOfst[7]=13 cells (4 PI)
7712 17:34:25.111160 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7713 17:34:25.114244 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7714 17:34:25.114322 == TX Byte 1 ==
7715 17:34:25.117621 u2DelayCellOfst[8]=0 cells (0 PI)
7716 17:34:25.120875 u2DelayCellOfst[9]=0 cells (0 PI)
7717 17:34:25.124032 u2DelayCellOfst[10]=6 cells (2 PI)
7718 17:34:25.127150 u2DelayCellOfst[11]=3 cells (1 PI)
7719 17:34:25.130770 u2DelayCellOfst[12]=10 cells (3 PI)
7720 17:34:25.134030 u2DelayCellOfst[13]=13 cells (4 PI)
7721 17:34:25.137411 u2DelayCellOfst[14]=16 cells (5 PI)
7722 17:34:25.140899 u2DelayCellOfst[15]=10 cells (3 PI)
7723 17:34:25.143614 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7724 17:34:25.150811 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7725 17:34:25.150885 DramC Write-DBI on
7726 17:34:25.150950 ==
7727 17:34:25.153359 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 17:34:25.157186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 17:34:25.160282 ==
7730 17:34:25.160357
7731 17:34:25.160417
7732 17:34:25.160473 TX Vref Scan disable
7733 17:34:25.163789 == TX Byte 0 ==
7734 17:34:25.167045 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7735 17:34:25.170802 == TX Byte 1 ==
7736 17:34:25.174097 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7737 17:34:25.177372 DramC Write-DBI off
7738 17:34:25.177448
7739 17:34:25.177508 [DATLAT]
7740 17:34:25.177565 Freq=1600, CH0 RK0
7741 17:34:25.177621
7742 17:34:25.180673 DATLAT Default: 0xf
7743 17:34:25.180739 0, 0xFFFF, sum = 0
7744 17:34:25.184023 1, 0xFFFF, sum = 0
7745 17:34:25.184095 2, 0xFFFF, sum = 0
7746 17:34:25.187355 3, 0xFFFF, sum = 0
7747 17:34:25.190779 4, 0xFFFF, sum = 0
7748 17:34:25.190848 5, 0xFFFF, sum = 0
7749 17:34:25.193453 6, 0xFFFF, sum = 0
7750 17:34:25.193522 7, 0xFFFF, sum = 0
7751 17:34:25.197403 8, 0xFFFF, sum = 0
7752 17:34:25.197484 9, 0xFFFF, sum = 0
7753 17:34:25.200520 10, 0xFFFF, sum = 0
7754 17:34:25.200601 11, 0xFFFF, sum = 0
7755 17:34:25.203564 12, 0xFFFF, sum = 0
7756 17:34:25.203674 13, 0xFFFF, sum = 0
7757 17:34:25.206660 14, 0x0, sum = 1
7758 17:34:25.206740 15, 0x0, sum = 2
7759 17:34:25.210569 16, 0x0, sum = 3
7760 17:34:25.210651 17, 0x0, sum = 4
7761 17:34:25.214017 best_step = 15
7762 17:34:25.214096
7763 17:34:25.214159 ==
7764 17:34:25.217001 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 17:34:25.220096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 17:34:25.220177 ==
7767 17:34:25.223423 RX Vref Scan: 1
7768 17:34:25.223503
7769 17:34:25.223565 Set Vref Range= 24 -> 127
7770 17:34:25.223629
7771 17:34:25.226889 RX Vref 24 -> 127, step: 1
7772 17:34:25.226973
7773 17:34:25.230190 RX Delay 19 -> 252, step: 4
7774 17:34:25.230278
7775 17:34:25.233461 Set Vref, RX VrefLevel [Byte0]: 24
7776 17:34:25.236756 [Byte1]: 24
7777 17:34:25.236849
7778 17:34:25.240452 Set Vref, RX VrefLevel [Byte0]: 25
7779 17:34:25.243613 [Byte1]: 25
7780 17:34:25.243769
7781 17:34:25.246716 Set Vref, RX VrefLevel [Byte0]: 26
7782 17:34:25.250117 [Byte1]: 26
7783 17:34:25.254279
7784 17:34:25.254353 Set Vref, RX VrefLevel [Byte0]: 27
7785 17:34:25.257668 [Byte1]: 27
7786 17:34:25.261756
7787 17:34:25.261829 Set Vref, RX VrefLevel [Byte0]: 28
7788 17:34:25.265076 [Byte1]: 28
7789 17:34:25.269055
7790 17:34:25.269124 Set Vref, RX VrefLevel [Byte0]: 29
7791 17:34:25.272894 [Byte1]: 29
7792 17:34:25.276616
7793 17:34:25.276693 Set Vref, RX VrefLevel [Byte0]: 30
7794 17:34:25.280464 [Byte1]: 30
7795 17:34:25.284386
7796 17:34:25.284456 Set Vref, RX VrefLevel [Byte0]: 31
7797 17:34:25.287607 [Byte1]: 31
7798 17:34:25.292109
7799 17:34:25.292183 Set Vref, RX VrefLevel [Byte0]: 32
7800 17:34:25.295282 [Byte1]: 32
7801 17:34:25.299707
7802 17:34:25.299784 Set Vref, RX VrefLevel [Byte0]: 33
7803 17:34:25.303141 [Byte1]: 33
7804 17:34:25.307583
7805 17:34:25.307684 Set Vref, RX VrefLevel [Byte0]: 34
7806 17:34:25.310279 [Byte1]: 34
7807 17:34:25.314609
7808 17:34:25.314680 Set Vref, RX VrefLevel [Byte0]: 35
7809 17:34:25.321576 [Byte1]: 35
7810 17:34:25.321661
7811 17:34:25.324572 Set Vref, RX VrefLevel [Byte0]: 36
7812 17:34:25.327827 [Byte1]: 36
7813 17:34:25.327904
7814 17:34:25.331230 Set Vref, RX VrefLevel [Byte0]: 37
7815 17:34:25.334390 [Byte1]: 37
7816 17:34:25.334464
7817 17:34:25.337713 Set Vref, RX VrefLevel [Byte0]: 38
7818 17:34:25.340949 [Byte1]: 38
7819 17:34:25.344863
7820 17:34:25.344941 Set Vref, RX VrefLevel [Byte0]: 39
7821 17:34:25.348113 [Byte1]: 39
7822 17:34:25.352487
7823 17:34:25.352571 Set Vref, RX VrefLevel [Byte0]: 40
7824 17:34:25.356175 [Byte1]: 40
7825 17:34:25.360317
7826 17:34:25.360400 Set Vref, RX VrefLevel [Byte0]: 41
7827 17:34:25.363732 [Byte1]: 41
7828 17:34:25.367785
7829 17:34:25.367858 Set Vref, RX VrefLevel [Byte0]: 42
7830 17:34:25.371177 [Byte1]: 42
7831 17:34:25.375306
7832 17:34:25.375405 Set Vref, RX VrefLevel [Byte0]: 43
7833 17:34:25.378586 [Byte1]: 43
7834 17:34:25.382650
7835 17:34:25.382739 Set Vref, RX VrefLevel [Byte0]: 44
7836 17:34:25.386024 [Byte1]: 44
7837 17:34:25.390657
7838 17:34:25.390733 Set Vref, RX VrefLevel [Byte0]: 45
7839 17:34:25.393396 [Byte1]: 45
7840 17:34:25.397958
7841 17:34:25.398033 Set Vref, RX VrefLevel [Byte0]: 46
7842 17:34:25.401132 [Byte1]: 46
7843 17:34:25.405872
7844 17:34:25.405956 Set Vref, RX VrefLevel [Byte0]: 47
7845 17:34:25.408822 [Byte1]: 47
7846 17:34:25.412962
7847 17:34:25.413032 Set Vref, RX VrefLevel [Byte0]: 48
7848 17:34:25.416730 [Byte1]: 48
7849 17:34:25.420664
7850 17:34:25.420729 Set Vref, RX VrefLevel [Byte0]: 49
7851 17:34:25.423941 [Byte1]: 49
7852 17:34:25.428287
7853 17:34:25.428373 Set Vref, RX VrefLevel [Byte0]: 50
7854 17:34:25.431962 [Byte1]: 50
7855 17:34:25.435950
7856 17:34:25.436018 Set Vref, RX VrefLevel [Byte0]: 51
7857 17:34:25.439177 [Byte1]: 51
7858 17:34:25.443245
7859 17:34:25.443330 Set Vref, RX VrefLevel [Byte0]: 52
7860 17:34:25.446594 [Byte1]: 52
7861 17:34:25.451245
7862 17:34:25.451314 Set Vref, RX VrefLevel [Byte0]: 53
7863 17:34:25.454538 [Byte1]: 53
7864 17:34:25.458392
7865 17:34:25.458464 Set Vref, RX VrefLevel [Byte0]: 54
7866 17:34:25.461652 [Byte1]: 54
7867 17:34:25.465845
7868 17:34:25.465928 Set Vref, RX VrefLevel [Byte0]: 55
7869 17:34:25.469280 [Byte1]: 55
7870 17:34:25.473511
7871 17:34:25.473576 Set Vref, RX VrefLevel [Byte0]: 56
7872 17:34:25.476892 [Byte1]: 56
7873 17:34:25.481023
7874 17:34:25.481089 Set Vref, RX VrefLevel [Byte0]: 57
7875 17:34:25.484273 [Byte1]: 57
7876 17:34:25.488880
7877 17:34:25.488948 Set Vref, RX VrefLevel [Byte0]: 58
7878 17:34:25.492258 [Byte1]: 58
7879 17:34:25.496406
7880 17:34:25.496477 Set Vref, RX VrefLevel [Byte0]: 59
7881 17:34:25.499831 [Byte1]: 59
7882 17:34:25.503891
7883 17:34:25.503960 Set Vref, RX VrefLevel [Byte0]: 60
7884 17:34:25.507163 [Byte1]: 60
7885 17:34:25.511841
7886 17:34:25.511913 Set Vref, RX VrefLevel [Byte0]: 61
7887 17:34:25.514751 [Byte1]: 61
7888 17:34:25.519432
7889 17:34:25.519498 Set Vref, RX VrefLevel [Byte0]: 62
7890 17:34:25.522770 [Byte1]: 62
7891 17:34:25.526997
7892 17:34:25.527067 Set Vref, RX VrefLevel [Byte0]: 63
7893 17:34:25.530325 [Byte1]: 63
7894 17:34:25.534179
7895 17:34:25.534247 Set Vref, RX VrefLevel [Byte0]: 64
7896 17:34:25.537312 [Byte1]: 64
7897 17:34:25.542047
7898 17:34:25.542163 Set Vref, RX VrefLevel [Byte0]: 65
7899 17:34:25.545447 [Byte1]: 65
7900 17:34:25.549422
7901 17:34:25.549492 Set Vref, RX VrefLevel [Byte0]: 66
7902 17:34:25.552586 [Byte1]: 66
7903 17:34:25.557289
7904 17:34:25.557364 Set Vref, RX VrefLevel [Byte0]: 67
7905 17:34:25.560721 [Byte1]: 67
7906 17:34:25.564682
7907 17:34:25.564751 Set Vref, RX VrefLevel [Byte0]: 68
7908 17:34:25.567879 [Byte1]: 68
7909 17:34:25.571936
7910 17:34:25.572012 Set Vref, RX VrefLevel [Byte0]: 69
7911 17:34:25.575734 [Byte1]: 69
7912 17:34:25.579745
7913 17:34:25.579818 Set Vref, RX VrefLevel [Byte0]: 70
7914 17:34:25.583054 [Byte1]: 70
7915 17:34:25.587112
7916 17:34:25.587184 Set Vref, RX VrefLevel [Byte0]: 71
7917 17:34:25.590531 [Byte1]: 71
7918 17:34:25.595242
7919 17:34:25.595313 Set Vref, RX VrefLevel [Byte0]: 72
7920 17:34:25.598646 [Byte1]: 72
7921 17:34:25.602638
7922 17:34:25.602701 Set Vref, RX VrefLevel [Byte0]: 73
7923 17:34:25.605995 [Byte1]: 73
7924 17:34:25.610009
7925 17:34:25.610084 Set Vref, RX VrefLevel [Byte0]: 74
7926 17:34:25.613370 [Byte1]: 74
7927 17:34:25.618046
7928 17:34:25.618126 Final RX Vref Byte 0 = 59 to rank0
7929 17:34:25.621322 Final RX Vref Byte 1 = 58 to rank0
7930 17:34:25.624750 Final RX Vref Byte 0 = 59 to rank1
7931 17:34:25.627438 Final RX Vref Byte 1 = 58 to rank1==
7932 17:34:25.631171 Dram Type= 6, Freq= 0, CH_0, rank 0
7933 17:34:25.637709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7934 17:34:25.637789 ==
7935 17:34:25.637853 DQS Delay:
7936 17:34:25.637911 DQS0 = 0, DQS1 = 0
7937 17:34:25.641004 DQM Delay:
7938 17:34:25.641084 DQM0 = 134, DQM1 = 127
7939 17:34:25.644474 DQ Delay:
7940 17:34:25.647065 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7941 17:34:25.650527 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7942 17:34:25.653905 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7943 17:34:25.657367 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7944 17:34:25.657447
7945 17:34:25.657508
7946 17:34:25.657566
7947 17:34:25.660623 [DramC_TX_OE_Calibration] TA2
7948 17:34:25.663749 Original DQ_B0 (3 6) =30, OEN = 27
7949 17:34:25.667355 Original DQ_B1 (3 6) =30, OEN = 27
7950 17:34:25.670917 24, 0x0, End_B0=24 End_B1=24
7951 17:34:25.670998 25, 0x0, End_B0=25 End_B1=25
7952 17:34:25.674096 26, 0x0, End_B0=26 End_B1=26
7953 17:34:25.677158 27, 0x0, End_B0=27 End_B1=27
7954 17:34:25.680823 28, 0x0, End_B0=28 End_B1=28
7955 17:34:25.683590 29, 0x0, End_B0=29 End_B1=29
7956 17:34:25.683712 30, 0x0, End_B0=30 End_B1=30
7957 17:34:25.686869 31, 0x4141, End_B0=30 End_B1=30
7958 17:34:25.690127 Byte0 end_step=30 best_step=27
7959 17:34:25.693613 Byte1 end_step=30 best_step=27
7960 17:34:25.696986 Byte0 TX OE(2T, 0.5T) = (3, 3)
7961 17:34:25.700572 Byte1 TX OE(2T, 0.5T) = (3, 3)
7962 17:34:25.700652
7963 17:34:25.700714
7964 17:34:25.706798 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7965 17:34:25.710047 CH0 RK0: MR19=303, MR18=241F
7966 17:34:25.716630 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7967 17:34:25.716735
7968 17:34:25.719996 ----->DramcWriteLeveling(PI) begin...
7969 17:34:25.720076 ==
7970 17:34:25.723408 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 17:34:25.726674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 17:34:25.726754 ==
7973 17:34:25.729960 Write leveling (Byte 0): 35 => 35
7974 17:34:25.733338 Write leveling (Byte 1): 27 => 27
7975 17:34:25.736610 DramcWriteLeveling(PI) end<-----
7976 17:34:25.736690
7977 17:34:25.736752 ==
7978 17:34:25.740480 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 17:34:25.743552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 17:34:25.743632 ==
7981 17:34:25.746942 [Gating] SW mode calibration
7982 17:34:25.753338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7983 17:34:25.760287 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7984 17:34:25.763694 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 17:34:25.769791 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 17:34:25.773634 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 17:34:25.776675 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7988 17:34:25.783559 1 4 16 | B1->B0 | 3030 3534 | 1 1 | (0 0) (0 0)
7989 17:34:25.786321 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7990 17:34:25.790354 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7991 17:34:25.793594 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 17:34:25.799942 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7993 17:34:25.802981 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7994 17:34:25.806419 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7995 17:34:25.813405 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7996 17:34:25.816672 1 5 16 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
7997 17:34:25.819649 1 5 20 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7998 17:34:25.826504 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7999 17:34:25.830029 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8000 17:34:25.833286 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8001 17:34:25.839963 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8002 17:34:25.843232 1 6 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8003 17:34:25.846414 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8004 17:34:25.852931 1 6 16 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
8005 17:34:25.856137 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8006 17:34:25.859445 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 17:34:25.866071 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 17:34:25.869402 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 17:34:25.872720 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 17:34:25.879325 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8011 17:34:25.882783 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8012 17:34:25.886340 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8013 17:34:25.892512 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 17:34:25.896342 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 17:34:25.899669 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 17:34:25.906442 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 17:34:25.909837 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 17:34:25.913169 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 17:34:25.919260 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 17:34:25.923114 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 17:34:25.926227 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 17:34:25.932786 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 17:34:25.936359 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 17:34:25.939320 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 17:34:25.942603 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 17:34:25.949313 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 17:34:25.952478 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8028 17:34:25.955765 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8029 17:34:25.962663 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 17:34:25.966088 Total UI for P1: 0, mck2ui 16
8031 17:34:25.969059 best dqsien dly found for B0: ( 1, 9, 14)
8032 17:34:25.972342 Total UI for P1: 0, mck2ui 16
8033 17:34:25.975709 best dqsien dly found for B1: ( 1, 9, 14)
8034 17:34:25.979044 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8035 17:34:25.982360 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8036 17:34:25.982460
8037 17:34:25.985725 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8038 17:34:25.989155 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8039 17:34:25.992585 [Gating] SW calibration Done
8040 17:34:25.992666 ==
8041 17:34:25.995680 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 17:34:25.999172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 17:34:25.999253 ==
8044 17:34:26.002484 RX Vref Scan: 0
8045 17:34:26.002565
8046 17:34:26.005839 RX Vref 0 -> 0, step: 1
8047 17:34:26.005920
8048 17:34:26.005982 RX Delay 0 -> 252, step: 8
8049 17:34:26.012591 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8050 17:34:26.015390 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8051 17:34:26.019275 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8052 17:34:26.022367 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8053 17:34:26.025743 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8054 17:34:26.032335 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8055 17:34:26.035608 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8056 17:34:26.038981 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8057 17:34:26.042412 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8058 17:34:26.045671 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8059 17:34:26.052604 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8060 17:34:26.055801 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8061 17:34:26.059034 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8062 17:34:26.062014 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8063 17:34:26.065285 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8064 17:34:26.072436 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8065 17:34:26.072518 ==
8066 17:34:26.075872 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 17:34:26.078569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 17:34:26.078650 ==
8069 17:34:26.078774 DQS Delay:
8070 17:34:26.081961 DQS0 = 0, DQS1 = 0
8071 17:34:26.082042 DQM Delay:
8072 17:34:26.085407 DQM0 = 137, DQM1 = 128
8073 17:34:26.085488 DQ Delay:
8074 17:34:26.088871 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8075 17:34:26.091838 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8076 17:34:26.095106 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8077 17:34:26.098472 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8078 17:34:26.098553
8079 17:34:26.102334
8080 17:34:26.102413 ==
8081 17:34:26.105430 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 17:34:26.108425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 17:34:26.108507 ==
8084 17:34:26.108570
8085 17:34:26.108627
8086 17:34:26.111551 TX Vref Scan disable
8087 17:34:26.111632 == TX Byte 0 ==
8088 17:34:26.118371 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8089 17:34:26.121701 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8090 17:34:26.121782 == TX Byte 1 ==
8091 17:34:26.128450 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8092 17:34:26.131693 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8093 17:34:26.131774 ==
8094 17:34:26.135082 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 17:34:26.138280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 17:34:26.138361 ==
8097 17:34:26.152797
8098 17:34:26.156016 TX Vref early break, caculate TX vref
8099 17:34:26.159210 TX Vref=16, minBit 1, minWin=22, winSum=386
8100 17:34:26.162511 TX Vref=18, minBit 0, minWin=23, winSum=395
8101 17:34:26.166353 TX Vref=20, minBit 3, minWin=23, winSum=404
8102 17:34:26.169109 TX Vref=22, minBit 1, minWin=24, winSum=411
8103 17:34:26.172474 TX Vref=24, minBit 1, minWin=24, winSum=419
8104 17:34:26.179064 TX Vref=26, minBit 1, minWin=25, winSum=425
8105 17:34:26.182914 TX Vref=28, minBit 0, minWin=25, winSum=425
8106 17:34:26.186120 TX Vref=30, minBit 1, minWin=25, winSum=416
8107 17:34:26.189389 TX Vref=32, minBit 4, minWin=24, winSum=407
8108 17:34:26.192404 TX Vref=34, minBit 4, minWin=23, winSum=400
8109 17:34:26.199373 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8110 17:34:26.199453
8111 17:34:26.202448 Final TX Range 0 Vref 26
8112 17:34:26.202529
8113 17:34:26.202592 ==
8114 17:34:26.205908 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 17:34:26.208859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 17:34:26.208954 ==
8117 17:34:26.209123
8118 17:34:26.209193
8119 17:34:26.212975 TX Vref Scan disable
8120 17:34:26.219051 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8121 17:34:26.219132 == TX Byte 0 ==
8122 17:34:26.222896 u2DelayCellOfst[0]=13 cells (4 PI)
8123 17:34:26.225634 u2DelayCellOfst[1]=16 cells (5 PI)
8124 17:34:26.228871 u2DelayCellOfst[2]=10 cells (3 PI)
8125 17:34:26.232097 u2DelayCellOfst[3]=10 cells (3 PI)
8126 17:34:26.235497 u2DelayCellOfst[4]=6 cells (2 PI)
8127 17:34:26.239471 u2DelayCellOfst[5]=0 cells (0 PI)
8128 17:34:26.242781 u2DelayCellOfst[6]=13 cells (4 PI)
8129 17:34:26.245475 u2DelayCellOfst[7]=13 cells (4 PI)
8130 17:34:26.249376 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8131 17:34:26.252170 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8132 17:34:26.255430 == TX Byte 1 ==
8133 17:34:26.255543 u2DelayCellOfst[8]=3 cells (1 PI)
8134 17:34:26.259323 u2DelayCellOfst[9]=0 cells (0 PI)
8135 17:34:26.262364 u2DelayCellOfst[10]=10 cells (3 PI)
8136 17:34:26.265590 u2DelayCellOfst[11]=3 cells (1 PI)
8137 17:34:26.268797 u2DelayCellOfst[12]=10 cells (3 PI)
8138 17:34:26.272312 u2DelayCellOfst[13]=10 cells (3 PI)
8139 17:34:26.275622 u2DelayCellOfst[14]=16 cells (5 PI)
8140 17:34:26.279100 u2DelayCellOfst[15]=10 cells (3 PI)
8141 17:34:26.282605 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8142 17:34:26.288749 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8143 17:34:26.288830 DramC Write-DBI on
8144 17:34:26.288893 ==
8145 17:34:26.291972 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 17:34:26.295252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 17:34:26.298509 ==
8148 17:34:26.298589
8149 17:34:26.298653
8150 17:34:26.298710 TX Vref Scan disable
8151 17:34:26.302436 == TX Byte 0 ==
8152 17:34:26.305644 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8153 17:34:26.309261 == TX Byte 1 ==
8154 17:34:26.312557 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8155 17:34:26.315593 DramC Write-DBI off
8156 17:34:26.315689
8157 17:34:26.315751 [DATLAT]
8158 17:34:26.315809 Freq=1600, CH0 RK1
8159 17:34:26.315865
8160 17:34:26.319203 DATLAT Default: 0xf
8161 17:34:26.319303 0, 0xFFFF, sum = 0
8162 17:34:26.322080 1, 0xFFFF, sum = 0
8163 17:34:26.325520 2, 0xFFFF, sum = 0
8164 17:34:26.325601 3, 0xFFFF, sum = 0
8165 17:34:26.329263 4, 0xFFFF, sum = 0
8166 17:34:26.329345 5, 0xFFFF, sum = 0
8167 17:34:26.332275 6, 0xFFFF, sum = 0
8168 17:34:26.332357 7, 0xFFFF, sum = 0
8169 17:34:26.335674 8, 0xFFFF, sum = 0
8170 17:34:26.335770 9, 0xFFFF, sum = 0
8171 17:34:26.339154 10, 0xFFFF, sum = 0
8172 17:34:26.339275 11, 0xFFFF, sum = 0
8173 17:34:26.342450 12, 0xFFFF, sum = 0
8174 17:34:26.342533 13, 0xFFFF, sum = 0
8175 17:34:26.345703 14, 0x0, sum = 1
8176 17:34:26.345785 15, 0x0, sum = 2
8177 17:34:26.348872 16, 0x0, sum = 3
8178 17:34:26.348954 17, 0x0, sum = 4
8179 17:34:26.352256 best_step = 15
8180 17:34:26.352335
8181 17:34:26.352397 ==
8182 17:34:26.355582 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 17:34:26.359012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 17:34:26.359092 ==
8185 17:34:26.359155 RX Vref Scan: 0
8186 17:34:26.359213
8187 17:34:26.362298 RX Vref 0 -> 0, step: 1
8188 17:34:26.362378
8189 17:34:26.365646 RX Delay 19 -> 252, step: 4
8190 17:34:26.369290 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8191 17:34:26.375824 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8192 17:34:26.379256 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8193 17:34:26.382681 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8194 17:34:26.385437 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8195 17:34:26.388689 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8196 17:34:26.392030 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8197 17:34:26.398718 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8198 17:34:26.401952 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8199 17:34:26.405338 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8200 17:34:26.408743 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8201 17:34:26.415205 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8202 17:34:26.419083 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8203 17:34:26.422356 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8204 17:34:26.425714 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8205 17:34:26.428965 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8206 17:34:26.432222 ==
8207 17:34:26.432302 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 17:34:26.438889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 17:34:26.438971 ==
8210 17:34:26.439033 DQS Delay:
8211 17:34:26.441979 DQS0 = 0, DQS1 = 0
8212 17:34:26.442058 DQM Delay:
8213 17:34:26.445090 DQM0 = 134, DQM1 = 127
8214 17:34:26.445170 DQ Delay:
8215 17:34:26.448628 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8216 17:34:26.452080 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8217 17:34:26.455444 DQ8 =118, DQ9 =118, DQ10 =126, DQ11 =118
8218 17:34:26.458365 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8219 17:34:26.458445
8220 17:34:26.458507
8221 17:34:26.458564
8222 17:34:26.461591 [DramC_TX_OE_Calibration] TA2
8223 17:34:26.465512 Original DQ_B0 (3 6) =30, OEN = 27
8224 17:34:26.468846 Original DQ_B1 (3 6) =30, OEN = 27
8225 17:34:26.472068 24, 0x0, End_B0=24 End_B1=24
8226 17:34:26.475230 25, 0x0, End_B0=25 End_B1=25
8227 17:34:26.475311 26, 0x0, End_B0=26 End_B1=26
8228 17:34:26.478425 27, 0x0, End_B0=27 End_B1=27
8229 17:34:26.482233 28, 0x0, End_B0=28 End_B1=28
8230 17:34:26.485441 29, 0x0, End_B0=29 End_B1=29
8231 17:34:26.485523 30, 0x0, End_B0=30 End_B1=30
8232 17:34:26.488753 31, 0x4141, End_B0=30 End_B1=30
8233 17:34:26.492063 Byte0 end_step=30 best_step=27
8234 17:34:26.495330 Byte1 end_step=30 best_step=27
8235 17:34:26.498522 Byte0 TX OE(2T, 0.5T) = (3, 3)
8236 17:34:26.501682 Byte1 TX OE(2T, 0.5T) = (3, 3)
8237 17:34:26.501761
8238 17:34:26.501824
8239 17:34:26.508087 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8240 17:34:26.511963 CH0 RK1: MR19=303, MR18=2008
8241 17:34:26.518631 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8242 17:34:26.521837 [RxdqsGatingPostProcess] freq 1600
8243 17:34:26.524902 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8244 17:34:26.528502 best DQS0 dly(2T, 0.5T) = (1, 1)
8245 17:34:26.531704 best DQS1 dly(2T, 0.5T) = (1, 1)
8246 17:34:26.534906 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8247 17:34:26.538000 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8248 17:34:26.541723 best DQS0 dly(2T, 0.5T) = (1, 1)
8249 17:34:26.544681 best DQS1 dly(2T, 0.5T) = (1, 1)
8250 17:34:26.548488 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8251 17:34:26.551148 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8252 17:34:26.555023 Pre-setting of DQS Precalculation
8253 17:34:26.558291 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8254 17:34:26.558371 ==
8255 17:34:26.561592 Dram Type= 6, Freq= 0, CH_1, rank 0
8256 17:34:26.568214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8257 17:34:26.568295 ==
8258 17:34:26.571127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8259 17:34:26.578287 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8260 17:34:26.581274 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8261 17:34:26.587561 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8262 17:34:26.595261 [CA 0] Center 41 (12~71) winsize 60
8263 17:34:26.598546 [CA 1] Center 41 (12~71) winsize 60
8264 17:34:26.601679 [CA 2] Center 38 (9~68) winsize 60
8265 17:34:26.605504 [CA 3] Center 37 (9~66) winsize 58
8266 17:34:26.608724 [CA 4] Center 37 (8~67) winsize 60
8267 17:34:26.611903 [CA 5] Center 36 (7~66) winsize 60
8268 17:34:26.611986
8269 17:34:26.615281 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8270 17:34:26.615362
8271 17:34:26.618604 [CATrainingPosCal] consider 1 rank data
8272 17:34:26.621829 u2DelayCellTimex100 = 290/100 ps
8273 17:34:26.625112 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8274 17:34:26.632000 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8275 17:34:26.635029 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8276 17:34:26.638704 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8277 17:34:26.641987 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8278 17:34:26.645292 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8279 17:34:26.645376
8280 17:34:26.648330 CA PerBit enable=1, Macro0, CA PI delay=36
8281 17:34:26.648411
8282 17:34:26.651838 [CBTSetCACLKResult] CA Dly = 36
8283 17:34:26.654903 CS Dly: 11 (0~42)
8284 17:34:26.658457 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8285 17:34:26.662340 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8286 17:34:26.662422 ==
8287 17:34:26.665025 Dram Type= 6, Freq= 0, CH_1, rank 1
8288 17:34:26.668278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 17:34:26.668360 ==
8290 17:34:26.675416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8291 17:34:26.678473 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8292 17:34:26.685210 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8293 17:34:26.688062 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8294 17:34:26.698266 [CA 0] Center 42 (12~72) winsize 61
8295 17:34:26.702019 [CA 1] Center 42 (12~72) winsize 61
8296 17:34:26.705228 [CA 2] Center 38 (9~68) winsize 60
8297 17:34:26.708372 [CA 3] Center 37 (8~67) winsize 60
8298 17:34:26.711604 [CA 4] Center 38 (8~68) winsize 61
8299 17:34:26.714807 [CA 5] Center 36 (7~66) winsize 60
8300 17:34:26.714888
8301 17:34:26.718147 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8302 17:34:26.718229
8303 17:34:26.721453 [CATrainingPosCal] consider 2 rank data
8304 17:34:26.724830 u2DelayCellTimex100 = 290/100 ps
8305 17:34:26.731408 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8306 17:34:26.734609 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8307 17:34:26.737852 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8308 17:34:26.741107 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8309 17:34:26.744751 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8310 17:34:26.747901 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8311 17:34:26.747984
8312 17:34:26.751274 CA PerBit enable=1, Macro0, CA PI delay=36
8313 17:34:26.751354
8314 17:34:26.754552 [CBTSetCACLKResult] CA Dly = 36
8315 17:34:26.757714 CS Dly: 12 (0~45)
8316 17:34:26.761599 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8317 17:34:26.764570 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8318 17:34:26.764652
8319 17:34:26.768310 ----->DramcWriteLeveling(PI) begin...
8320 17:34:26.768391 ==
8321 17:34:26.771186 Dram Type= 6, Freq= 0, CH_1, rank 0
8322 17:34:26.778195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 17:34:26.778302 ==
8324 17:34:26.781424 Write leveling (Byte 0): 26 => 26
8325 17:34:26.781559 Write leveling (Byte 1): 28 => 28
8326 17:34:26.784697 DramcWriteLeveling(PI) end<-----
8327 17:34:26.784828
8328 17:34:26.787933 ==
8329 17:34:26.788063 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 17:34:26.794338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 17:34:26.794468 ==
8332 17:34:26.798038 [Gating] SW mode calibration
8333 17:34:26.804635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8334 17:34:26.808036 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8335 17:34:26.814453 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 17:34:26.817743 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 17:34:26.821210 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8338 17:34:26.827924 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8339 17:34:26.831106 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 17:34:26.834490 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 17:34:26.841015 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 17:34:26.844273 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 17:34:26.847469 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 17:34:26.854331 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 17:34:26.857646 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8346 17:34:26.860914 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8347 17:34:26.864605 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 17:34:26.871440 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 17:34:26.874455 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 17:34:26.877555 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 17:34:26.884235 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 17:34:26.887895 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 17:34:26.891203 1 6 8 | B1->B0 | 2525 3d3d | 0 1 | (0 0) (0 0)
8354 17:34:26.897649 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8355 17:34:26.900881 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 17:34:26.904114 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 17:34:26.910827 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 17:34:26.913939 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 17:34:26.917576 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 17:34:26.924407 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 17:34:26.927527 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8362 17:34:26.931070 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8363 17:34:26.937555 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8364 17:34:26.940735 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 17:34:26.944258 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 17:34:26.950654 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 17:34:26.954046 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 17:34:26.957156 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 17:34:26.963865 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 17:34:26.967237 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 17:34:26.970615 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 17:34:26.977446 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 17:34:26.980572 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 17:34:26.983846 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 17:34:26.990271 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 17:34:26.993949 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 17:34:26.997072 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8378 17:34:27.003666 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8379 17:34:27.006936 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 17:34:27.010107 Total UI for P1: 0, mck2ui 16
8381 17:34:27.013507 best dqsien dly found for B0: ( 1, 9, 10)
8382 17:34:27.016791 Total UI for P1: 0, mck2ui 16
8383 17:34:27.019965 best dqsien dly found for B1: ( 1, 9, 10)
8384 17:34:27.023855 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8385 17:34:27.026497 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8386 17:34:27.026578
8387 17:34:27.030257 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8388 17:34:27.033475 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8389 17:34:27.036752 [Gating] SW calibration Done
8390 17:34:27.036833 ==
8391 17:34:27.039948 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 17:34:27.043740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 17:34:27.043822 ==
8394 17:34:27.046853 RX Vref Scan: 0
8395 17:34:27.046933
8396 17:34:27.049734 RX Vref 0 -> 0, step: 1
8397 17:34:27.049814
8398 17:34:27.049877 RX Delay 0 -> 252, step: 8
8399 17:34:27.056314 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8400 17:34:27.059938 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8401 17:34:27.063022 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8402 17:34:27.066754 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8403 17:34:27.069684 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8404 17:34:27.076761 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8405 17:34:27.080005 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8406 17:34:27.083145 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8407 17:34:27.086310 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8408 17:34:27.089338 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8409 17:34:27.096430 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8410 17:34:27.099531 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8411 17:34:27.102666 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8412 17:34:27.106365 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8413 17:34:27.112848 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8414 17:34:27.116105 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8415 17:34:27.116186 ==
8416 17:34:27.119509 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 17:34:27.122842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 17:34:27.122923 ==
8419 17:34:27.122987 DQS Delay:
8420 17:34:27.125892 DQS0 = 0, DQS1 = 0
8421 17:34:27.125972 DQM Delay:
8422 17:34:27.129321 DQM0 = 136, DQM1 = 133
8423 17:34:27.129402 DQ Delay:
8424 17:34:27.133167 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8425 17:34:27.136345 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8426 17:34:27.139493 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8427 17:34:27.142652 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8428 17:34:27.145813
8429 17:34:27.145918
8430 17:34:27.145997 ==
8431 17:34:27.149274 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 17:34:27.153070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 17:34:27.153152 ==
8434 17:34:27.153215
8435 17:34:27.153273
8436 17:34:27.156368 TX Vref Scan disable
8437 17:34:27.156474 == TX Byte 0 ==
8438 17:34:27.162676 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8439 17:34:27.165827 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8440 17:34:27.165908 == TX Byte 1 ==
8441 17:34:27.172456 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8442 17:34:27.176002 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8443 17:34:27.176082 ==
8444 17:34:27.179026 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 17:34:27.182224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 17:34:27.182304 ==
8447 17:34:27.195973
8448 17:34:27.199084 TX Vref early break, caculate TX vref
8449 17:34:27.202445 TX Vref=16, minBit 0, minWin=22, winSum=376
8450 17:34:27.205498 TX Vref=18, minBit 1, minWin=23, winSum=386
8451 17:34:27.208754 TX Vref=20, minBit 1, minWin=23, winSum=393
8452 17:34:27.212714 TX Vref=22, minBit 0, minWin=24, winSum=407
8453 17:34:27.216024 TX Vref=24, minBit 0, minWin=25, winSum=414
8454 17:34:27.221951 TX Vref=26, minBit 0, minWin=25, winSum=424
8455 17:34:27.225280 TX Vref=28, minBit 2, minWin=25, winSum=428
8456 17:34:27.228564 TX Vref=30, minBit 0, minWin=25, winSum=421
8457 17:34:27.232366 TX Vref=32, minBit 0, minWin=24, winSum=410
8458 17:34:27.235515 TX Vref=34, minBit 0, minWin=24, winSum=397
8459 17:34:27.242002 [TxChooseVref] Worse bit 2, Min win 25, Win sum 428, Final Vref 28
8460 17:34:27.242083
8461 17:34:27.245590 Final TX Range 0 Vref 28
8462 17:34:27.245693
8463 17:34:27.245827 ==
8464 17:34:27.248582 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 17:34:27.251864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 17:34:27.251944 ==
8467 17:34:27.252006
8468 17:34:27.252063
8469 17:34:27.254999 TX Vref Scan disable
8470 17:34:27.261602 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8471 17:34:27.261684 == TX Byte 0 ==
8472 17:34:27.265310 u2DelayCellOfst[0]=20 cells (6 PI)
8473 17:34:27.268599 u2DelayCellOfst[1]=13 cells (4 PI)
8474 17:34:27.271768 u2DelayCellOfst[2]=0 cells (0 PI)
8475 17:34:27.275516 u2DelayCellOfst[3]=10 cells (3 PI)
8476 17:34:27.278705 u2DelayCellOfst[4]=13 cells (4 PI)
8477 17:34:27.281736 u2DelayCellOfst[5]=20 cells (6 PI)
8478 17:34:27.285419 u2DelayCellOfst[6]=20 cells (6 PI)
8479 17:34:27.288257 u2DelayCellOfst[7]=10 cells (3 PI)
8480 17:34:27.291853 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8481 17:34:27.295109 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8482 17:34:27.298430 == TX Byte 1 ==
8483 17:34:27.301494 u2DelayCellOfst[8]=0 cells (0 PI)
8484 17:34:27.305083 u2DelayCellOfst[9]=6 cells (2 PI)
8485 17:34:27.305163 u2DelayCellOfst[10]=13 cells (4 PI)
8486 17:34:27.308071 u2DelayCellOfst[11]=6 cells (2 PI)
8487 17:34:27.311494 u2DelayCellOfst[12]=16 cells (5 PI)
8488 17:34:27.314764 u2DelayCellOfst[13]=16 cells (5 PI)
8489 17:34:27.318522 u2DelayCellOfst[14]=20 cells (6 PI)
8490 17:34:27.321680 u2DelayCellOfst[15]=16 cells (5 PI)
8491 17:34:27.324958 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8492 17:34:27.331489 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8493 17:34:27.331568 DramC Write-DBI on
8494 17:34:27.331631 ==
8495 17:34:27.335370 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 17:34:27.341900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 17:34:27.341981 ==
8498 17:34:27.342043
8499 17:34:27.342101
8500 17:34:27.342156 TX Vref Scan disable
8501 17:34:27.345100 == TX Byte 0 ==
8502 17:34:27.349102 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8503 17:34:27.352121 == TX Byte 1 ==
8504 17:34:27.355660 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8505 17:34:27.358576 DramC Write-DBI off
8506 17:34:27.358655
8507 17:34:27.358719 [DATLAT]
8508 17:34:27.358777 Freq=1600, CH1 RK0
8509 17:34:27.358832
8510 17:34:27.362407 DATLAT Default: 0xf
8511 17:34:27.362486 0, 0xFFFF, sum = 0
8512 17:34:27.365676 1, 0xFFFF, sum = 0
8513 17:34:27.365756 2, 0xFFFF, sum = 0
8514 17:34:27.368920 3, 0xFFFF, sum = 0
8515 17:34:27.372236 4, 0xFFFF, sum = 0
8516 17:34:27.372316 5, 0xFFFF, sum = 0
8517 17:34:27.375677 6, 0xFFFF, sum = 0
8518 17:34:27.375771 7, 0xFFFF, sum = 0
8519 17:34:27.378751 8, 0xFFFF, sum = 0
8520 17:34:27.378831 9, 0xFFFF, sum = 0
8521 17:34:27.382390 10, 0xFFFF, sum = 0
8522 17:34:27.382470 11, 0xFFFF, sum = 0
8523 17:34:27.385646 12, 0xFFFF, sum = 0
8524 17:34:27.385726 13, 0xFFFF, sum = 0
8525 17:34:27.388955 14, 0x0, sum = 1
8526 17:34:27.389035 15, 0x0, sum = 2
8527 17:34:27.392073 16, 0x0, sum = 3
8528 17:34:27.392180 17, 0x0, sum = 4
8529 17:34:27.395286 best_step = 15
8530 17:34:27.395365
8531 17:34:27.395426 ==
8532 17:34:27.398762 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 17:34:27.401657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 17:34:27.401737 ==
8535 17:34:27.401799 RX Vref Scan: 1
8536 17:34:27.405476
8537 17:34:27.405554 Set Vref Range= 24 -> 127
8538 17:34:27.405617
8539 17:34:27.408692 RX Vref 24 -> 127, step: 1
8540 17:34:27.408771
8541 17:34:27.411809 RX Delay 27 -> 252, step: 4
8542 17:34:27.411887
8543 17:34:27.415495 Set Vref, RX VrefLevel [Byte0]: 24
8544 17:34:27.418498 [Byte1]: 24
8545 17:34:27.418577
8546 17:34:27.422153 Set Vref, RX VrefLevel [Byte0]: 25
8547 17:34:27.425024 [Byte1]: 25
8548 17:34:27.425103
8549 17:34:27.428628 Set Vref, RX VrefLevel [Byte0]: 26
8550 17:34:27.431897 [Byte1]: 26
8551 17:34:27.435873
8552 17:34:27.435951 Set Vref, RX VrefLevel [Byte0]: 27
8553 17:34:27.438984 [Byte1]: 27
8554 17:34:27.443035
8555 17:34:27.443113 Set Vref, RX VrefLevel [Byte0]: 28
8556 17:34:27.446283 [Byte1]: 28
8557 17:34:27.450890
8558 17:34:27.450969 Set Vref, RX VrefLevel [Byte0]: 29
8559 17:34:27.454056 [Byte1]: 29
8560 17:34:27.458477
8561 17:34:27.458555 Set Vref, RX VrefLevel [Byte0]: 30
8562 17:34:27.461704 [Byte1]: 30
8563 17:34:27.466029
8564 17:34:27.466107 Set Vref, RX VrefLevel [Byte0]: 31
8565 17:34:27.469087 [Byte1]: 31
8566 17:34:27.473168
8567 17:34:27.473247 Set Vref, RX VrefLevel [Byte0]: 32
8568 17:34:27.476378 [Byte1]: 32
8569 17:34:27.480953
8570 17:34:27.481031 Set Vref, RX VrefLevel [Byte0]: 33
8571 17:34:27.484157 [Byte1]: 33
8572 17:34:27.488433
8573 17:34:27.488512 Set Vref, RX VrefLevel [Byte0]: 34
8574 17:34:27.491601 [Byte1]: 34
8575 17:34:27.496249
8576 17:34:27.496328 Set Vref, RX VrefLevel [Byte0]: 35
8577 17:34:27.499513 [Byte1]: 35
8578 17:34:27.503418
8579 17:34:27.503498 Set Vref, RX VrefLevel [Byte0]: 36
8580 17:34:27.506584 [Byte1]: 36
8581 17:34:27.510682
8582 17:34:27.510761 Set Vref, RX VrefLevel [Byte0]: 37
8583 17:34:27.514313 [Byte1]: 37
8584 17:34:27.518373
8585 17:34:27.518452 Set Vref, RX VrefLevel [Byte0]: 38
8586 17:34:27.524796 [Byte1]: 38
8587 17:34:27.524877
8588 17:34:27.528100 Set Vref, RX VrefLevel [Byte0]: 39
8589 17:34:27.531495 [Byte1]: 39
8590 17:34:27.531574
8591 17:34:27.535029 Set Vref, RX VrefLevel [Byte0]: 40
8592 17:34:27.538047 [Byte1]: 40
8593 17:34:27.538136
8594 17:34:27.541597 Set Vref, RX VrefLevel [Byte0]: 41
8595 17:34:27.544559 [Byte1]: 41
8596 17:34:27.548906
8597 17:34:27.548986 Set Vref, RX VrefLevel [Byte0]: 42
8598 17:34:27.552245 [Byte1]: 42
8599 17:34:27.556067
8600 17:34:27.556147 Set Vref, RX VrefLevel [Byte0]: 43
8601 17:34:27.559337 [Byte1]: 43
8602 17:34:27.563982
8603 17:34:27.564062 Set Vref, RX VrefLevel [Byte0]: 44
8604 17:34:27.567209 [Byte1]: 44
8605 17:34:27.571055
8606 17:34:27.571136 Set Vref, RX VrefLevel [Byte0]: 45
8607 17:34:27.574908 [Byte1]: 45
8608 17:34:27.578542
8609 17:34:27.578621 Set Vref, RX VrefLevel [Byte0]: 46
8610 17:34:27.582252 [Byte1]: 46
8611 17:34:27.586362
8612 17:34:27.586473 Set Vref, RX VrefLevel [Byte0]: 47
8613 17:34:27.589680 [Byte1]: 47
8614 17:34:27.593968
8615 17:34:27.594046 Set Vref, RX VrefLevel [Byte0]: 48
8616 17:34:27.597080 [Byte1]: 48
8617 17:34:27.601570
8618 17:34:27.601648 Set Vref, RX VrefLevel [Byte0]: 49
8619 17:34:27.604929 [Byte1]: 49
8620 17:34:27.608724
8621 17:34:27.608803 Set Vref, RX VrefLevel [Byte0]: 50
8622 17:34:27.612066 [Byte1]: 50
8623 17:34:27.616445
8624 17:34:27.616524 Set Vref, RX VrefLevel [Byte0]: 51
8625 17:34:27.619553 [Byte1]: 51
8626 17:34:27.623771
8627 17:34:27.623874 Set Vref, RX VrefLevel [Byte0]: 52
8628 17:34:27.627487 [Byte1]: 52
8629 17:34:27.631580
8630 17:34:27.631697 Set Vref, RX VrefLevel [Byte0]: 53
8631 17:34:27.634805 [Byte1]: 53
8632 17:34:27.638707
8633 17:34:27.638787 Set Vref, RX VrefLevel [Byte0]: 54
8634 17:34:27.642534 [Byte1]: 54
8635 17:34:27.646348
8636 17:34:27.646429 Set Vref, RX VrefLevel [Byte0]: 55
8637 17:34:27.649971 [Byte1]: 55
8638 17:34:27.654179
8639 17:34:27.654261 Set Vref, RX VrefLevel [Byte0]: 56
8640 17:34:27.660304 [Byte1]: 56
8641 17:34:27.660384
8642 17:34:27.663595 Set Vref, RX VrefLevel [Byte0]: 57
8643 17:34:27.666825 [Byte1]: 57
8644 17:34:27.666909
8645 17:34:27.670154 Set Vref, RX VrefLevel [Byte0]: 58
8646 17:34:27.673933 [Byte1]: 58
8647 17:34:27.674014
8648 17:34:27.677291 Set Vref, RX VrefLevel [Byte0]: 59
8649 17:34:27.680504 [Byte1]: 59
8650 17:34:27.683996
8651 17:34:27.684076 Set Vref, RX VrefLevel [Byte0]: 60
8652 17:34:27.687824 [Byte1]: 60
8653 17:34:27.691405
8654 17:34:27.691484 Set Vref, RX VrefLevel [Byte0]: 61
8655 17:34:27.694995 [Byte1]: 61
8656 17:34:27.699418
8657 17:34:27.699498 Set Vref, RX VrefLevel [Byte0]: 62
8658 17:34:27.702490 [Byte1]: 62
8659 17:34:27.706721
8660 17:34:27.706800 Set Vref, RX VrefLevel [Byte0]: 63
8661 17:34:27.709960 [Byte1]: 63
8662 17:34:27.714560
8663 17:34:27.714640 Set Vref, RX VrefLevel [Byte0]: 64
8664 17:34:27.717851 [Byte1]: 64
8665 17:34:27.721655
8666 17:34:27.721734 Set Vref, RX VrefLevel [Byte0]: 65
8667 17:34:27.724881 [Byte1]: 65
8668 17:34:27.729306
8669 17:34:27.729385 Set Vref, RX VrefLevel [Byte0]: 66
8670 17:34:27.732542 [Byte1]: 66
8671 17:34:27.736908
8672 17:34:27.736988 Set Vref, RX VrefLevel [Byte0]: 67
8673 17:34:27.739884 [Byte1]: 67
8674 17:34:27.744203
8675 17:34:27.744286 Set Vref, RX VrefLevel [Byte0]: 68
8676 17:34:27.747969 [Byte1]: 68
8677 17:34:27.752071
8678 17:34:27.752150 Set Vref, RX VrefLevel [Byte0]: 69
8679 17:34:27.755223 [Byte1]: 69
8680 17:34:27.759384
8681 17:34:27.759465 Set Vref, RX VrefLevel [Byte0]: 70
8682 17:34:27.762849 [Byte1]: 70
8683 17:34:27.766849
8684 17:34:27.766927 Set Vref, RX VrefLevel [Byte0]: 71
8685 17:34:27.770640 [Byte1]: 71
8686 17:34:27.774444
8687 17:34:27.774523 Set Vref, RX VrefLevel [Byte0]: 72
8688 17:34:27.777697 [Byte1]: 72
8689 17:34:27.782247
8690 17:34:27.782325 Set Vref, RX VrefLevel [Byte0]: 73
8691 17:34:27.785550 [Byte1]: 73
8692 17:34:27.789440
8693 17:34:27.789519 Set Vref, RX VrefLevel [Byte0]: 74
8694 17:34:27.792588 [Byte1]: 74
8695 17:34:27.797308
8696 17:34:27.797388 Set Vref, RX VrefLevel [Byte0]: 75
8697 17:34:27.800510 [Byte1]: 75
8698 17:34:27.804714
8699 17:34:27.804793 Final RX Vref Byte 0 = 58 to rank0
8700 17:34:27.807851 Final RX Vref Byte 1 = 57 to rank0
8701 17:34:27.811413 Final RX Vref Byte 0 = 58 to rank1
8702 17:34:27.814487 Final RX Vref Byte 1 = 57 to rank1==
8703 17:34:27.818119 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 17:34:27.824432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 17:34:27.824512 ==
8706 17:34:27.824575 DQS Delay:
8707 17:34:27.824632 DQS0 = 0, DQS1 = 0
8708 17:34:27.827815 DQM Delay:
8709 17:34:27.827894 DQM0 = 133, DQM1 = 131
8710 17:34:27.831545 DQ Delay:
8711 17:34:27.834836 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8712 17:34:27.838029 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8713 17:34:27.841217 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8714 17:34:27.844291 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8715 17:34:27.844371
8716 17:34:27.844434
8717 17:34:27.844491
8718 17:34:27.847847 [DramC_TX_OE_Calibration] TA2
8719 17:34:27.851002 Original DQ_B0 (3 6) =30, OEN = 27
8720 17:34:27.854557 Original DQ_B1 (3 6) =30, OEN = 27
8721 17:34:27.857967 24, 0x0, End_B0=24 End_B1=24
8722 17:34:27.858070 25, 0x0, End_B0=25 End_B1=25
8723 17:34:27.861232 26, 0x0, End_B0=26 End_B1=26
8724 17:34:27.864408 27, 0x0, End_B0=27 End_B1=27
8725 17:34:27.868132 28, 0x0, End_B0=28 End_B1=28
8726 17:34:27.868232 29, 0x0, End_B0=29 End_B1=29
8727 17:34:27.871256 30, 0x0, End_B0=30 End_B1=30
8728 17:34:27.874620 31, 0x4141, End_B0=30 End_B1=30
8729 17:34:27.877586 Byte0 end_step=30 best_step=27
8730 17:34:27.881124 Byte1 end_step=30 best_step=27
8731 17:34:27.884747 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 17:34:27.884829 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 17:34:27.887890
8734 17:34:27.888021
8735 17:34:27.894262 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8736 17:34:27.897564 CH1 RK0: MR19=303, MR18=1523
8737 17:34:27.904169 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8738 17:34:27.904254
8739 17:34:27.907841 ----->DramcWriteLeveling(PI) begin...
8740 17:34:27.907924 ==
8741 17:34:27.911010 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 17:34:27.914264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 17:34:27.914345 ==
8744 17:34:27.917505 Write leveling (Byte 0): 27 => 27
8745 17:34:27.920630 Write leveling (Byte 1): 30 => 30
8746 17:34:27.924224 DramcWriteLeveling(PI) end<-----
8747 17:34:27.924307
8748 17:34:27.924369 ==
8749 17:34:27.927523 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 17:34:27.931170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 17:34:27.931252 ==
8752 17:34:27.934338 [Gating] SW mode calibration
8753 17:34:27.940765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 17:34:27.947247 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 17:34:27.950997 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 17:34:27.954131 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 17:34:27.960479 1 4 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8758 17:34:27.964229 1 4 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
8759 17:34:27.967546 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 17:34:27.974280 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 17:34:27.977551 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 17:34:27.980655 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 17:34:27.987358 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 17:34:27.990885 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8765 17:34:27.993815 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8766 17:34:28.000891 1 5 12 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (1 0)
8767 17:34:28.004213 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 17:34:28.007201 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 17:34:28.013978 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 17:34:28.017337 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 17:34:28.020645 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 17:34:28.027376 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 17:34:28.030594 1 6 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8774 17:34:28.034042 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8775 17:34:28.040556 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 17:34:28.043662 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 17:34:28.047061 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 17:34:28.054325 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 17:34:28.057546 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 17:34:28.060825 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 17:34:28.063927 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8782 17:34:28.070994 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 17:34:28.074318 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 17:34:28.077543 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 17:34:28.084074 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 17:34:28.087376 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 17:34:28.090525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 17:34:28.097160 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 17:34:28.100789 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 17:34:28.103766 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 17:34:28.110759 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 17:34:28.113896 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 17:34:28.117183 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 17:34:28.123517 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 17:34:28.126777 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 17:34:28.130124 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8797 17:34:28.136924 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8798 17:34:28.140266 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8799 17:34:28.143538 Total UI for P1: 0, mck2ui 16
8800 17:34:28.146632 best dqsien dly found for B1: ( 1, 9, 6)
8801 17:34:28.150522 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 17:34:28.153492 Total UI for P1: 0, mck2ui 16
8803 17:34:28.157094 best dqsien dly found for B0: ( 1, 9, 12)
8804 17:34:28.160074 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8805 17:34:28.163525 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8806 17:34:28.163609
8807 17:34:28.166830 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8808 17:34:28.173615 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8809 17:34:28.173727 [Gating] SW calibration Done
8810 17:34:28.176532 ==
8811 17:34:28.176616 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 17:34:28.183371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 17:34:28.183467 ==
8814 17:34:28.183533 RX Vref Scan: 0
8815 17:34:28.183592
8816 17:34:28.186635 RX Vref 0 -> 0, step: 1
8817 17:34:28.186718
8818 17:34:28.189777 RX Delay 0 -> 252, step: 8
8819 17:34:28.193537 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8820 17:34:28.196691 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8821 17:34:28.199992 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8822 17:34:28.206879 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8823 17:34:28.209718 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8824 17:34:28.213346 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8825 17:34:28.216373 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8826 17:34:28.219627 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8827 17:34:28.226329 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8828 17:34:28.230189 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8829 17:34:28.233523 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8830 17:34:28.236825 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8831 17:34:28.239486 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8832 17:34:28.246681 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8833 17:34:28.249985 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8834 17:34:28.253244 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8835 17:34:28.253330 ==
8836 17:34:28.256271 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 17:34:28.259546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 17:34:28.259696 ==
8839 17:34:28.262916 DQS Delay:
8840 17:34:28.262999 DQS0 = 0, DQS1 = 0
8841 17:34:28.266713 DQM Delay:
8842 17:34:28.266796 DQM0 = 136, DQM1 = 133
8843 17:34:28.269812 DQ Delay:
8844 17:34:28.272961 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8845 17:34:28.276138 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8846 17:34:28.279677 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8847 17:34:28.282676 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8848 17:34:28.282764
8849 17:34:28.282827
8850 17:34:28.282886 ==
8851 17:34:28.286099 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 17:34:28.289778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 17:34:28.289868 ==
8854 17:34:28.289931
8855 17:34:28.289989
8856 17:34:28.293230 TX Vref Scan disable
8857 17:34:28.296184 == TX Byte 0 ==
8858 17:34:28.299624 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8859 17:34:28.302902 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8860 17:34:28.306206 == TX Byte 1 ==
8861 17:34:28.309512 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8862 17:34:28.312701 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8863 17:34:28.312794 ==
8864 17:34:28.316550 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 17:34:28.319530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 17:34:28.322715 ==
8867 17:34:28.334004
8868 17:34:28.337426 TX Vref early break, caculate TX vref
8869 17:34:28.341030 TX Vref=16, minBit 1, minWin=23, winSum=383
8870 17:34:28.344477 TX Vref=18, minBit 0, minWin=24, winSum=394
8871 17:34:28.347050 TX Vref=20, minBit 0, minWin=24, winSum=401
8872 17:34:28.351082 TX Vref=22, minBit 0, minWin=24, winSum=405
8873 17:34:28.353747 TX Vref=24, minBit 1, minWin=24, winSum=411
8874 17:34:28.360830 TX Vref=26, minBit 0, minWin=25, winSum=420
8875 17:34:28.363998 TX Vref=28, minBit 0, minWin=26, winSum=426
8876 17:34:28.367327 TX Vref=30, minBit 6, minWin=25, winSum=420
8877 17:34:28.370541 TX Vref=32, minBit 1, minWin=25, winSum=411
8878 17:34:28.373744 TX Vref=34, minBit 0, minWin=24, winSum=402
8879 17:34:28.380661 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8880 17:34:28.380765
8881 17:34:28.383892 Final TX Range 0 Vref 28
8882 17:34:28.383976
8883 17:34:28.384039 ==
8884 17:34:28.387052 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 17:34:28.390894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 17:34:28.391012 ==
8887 17:34:28.391114
8888 17:34:28.391207
8889 17:34:28.393870 TX Vref Scan disable
8890 17:34:28.400730 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8891 17:34:28.400840 == TX Byte 0 ==
8892 17:34:28.403983 u2DelayCellOfst[0]=16 cells (5 PI)
8893 17:34:28.407054 u2DelayCellOfst[1]=10 cells (3 PI)
8894 17:34:28.410622 u2DelayCellOfst[2]=0 cells (0 PI)
8895 17:34:28.413623 u2DelayCellOfst[3]=6 cells (2 PI)
8896 17:34:28.416930 u2DelayCellOfst[4]=6 cells (2 PI)
8897 17:34:28.420375 u2DelayCellOfst[5]=16 cells (5 PI)
8898 17:34:28.423620 u2DelayCellOfst[6]=16 cells (5 PI)
8899 17:34:28.423766 u2DelayCellOfst[7]=6 cells (2 PI)
8900 17:34:28.430529 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8901 17:34:28.433869 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8902 17:34:28.433967 == TX Byte 1 ==
8903 17:34:28.437079 u2DelayCellOfst[8]=0 cells (0 PI)
8904 17:34:28.440405 u2DelayCellOfst[9]=0 cells (0 PI)
8905 17:34:28.443441 u2DelayCellOfst[10]=6 cells (2 PI)
8906 17:34:28.447082 u2DelayCellOfst[11]=0 cells (0 PI)
8907 17:34:28.450050 u2DelayCellOfst[12]=13 cells (4 PI)
8908 17:34:28.453934 u2DelayCellOfst[13]=13 cells (4 PI)
8909 17:34:28.457144 u2DelayCellOfst[14]=13 cells (4 PI)
8910 17:34:28.460522 u2DelayCellOfst[15]=13 cells (4 PI)
8911 17:34:28.463796 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8912 17:34:28.466852 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8913 17:34:28.470018 DramC Write-DBI on
8914 17:34:28.470105 ==
8915 17:34:28.473839 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 17:34:28.477190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 17:34:28.477283 ==
8918 17:34:28.477346
8919 17:34:28.480337
8920 17:34:28.480418 TX Vref Scan disable
8921 17:34:28.483528 == TX Byte 0 ==
8922 17:34:28.486908 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8923 17:34:28.490319 == TX Byte 1 ==
8924 17:34:28.493620 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8925 17:34:28.493708 DramC Write-DBI off
8926 17:34:28.493778
8927 17:34:28.496741 [DATLAT]
8928 17:34:28.496823 Freq=1600, CH1 RK1
8929 17:34:28.496887
8930 17:34:28.499847 DATLAT Default: 0xf
8931 17:34:28.499930 0, 0xFFFF, sum = 0
8932 17:34:28.503366 1, 0xFFFF, sum = 0
8933 17:34:28.503452 2, 0xFFFF, sum = 0
8934 17:34:28.506398 3, 0xFFFF, sum = 0
8935 17:34:28.506486 4, 0xFFFF, sum = 0
8936 17:34:28.510359 5, 0xFFFF, sum = 0
8937 17:34:28.510445 6, 0xFFFF, sum = 0
8938 17:34:28.513635 7, 0xFFFF, sum = 0
8939 17:34:28.513721 8, 0xFFFF, sum = 0
8940 17:34:28.516884 9, 0xFFFF, sum = 0
8941 17:34:28.520071 10, 0xFFFF, sum = 0
8942 17:34:28.520160 11, 0xFFFF, sum = 0
8943 17:34:28.523478 12, 0xFFFF, sum = 0
8944 17:34:28.523569 13, 0xFFFF, sum = 0
8945 17:34:28.526556 14, 0x0, sum = 1
8946 17:34:28.526648 15, 0x0, sum = 2
8947 17:34:28.530047 16, 0x0, sum = 3
8948 17:34:28.530133 17, 0x0, sum = 4
8949 17:34:28.530197 best_step = 15
8950 17:34:28.533441
8951 17:34:28.533524 ==
8952 17:34:28.536719 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 17:34:28.540009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 17:34:28.540096 ==
8955 17:34:28.540159 RX Vref Scan: 0
8956 17:34:28.540218
8957 17:34:28.543036 RX Vref 0 -> 0, step: 1
8958 17:34:28.543119
8959 17:34:28.546478 RX Delay 19 -> 252, step: 4
8960 17:34:28.550135 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8961 17:34:28.556479 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8962 17:34:28.559518 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8963 17:34:28.562759 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8964 17:34:28.566669 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8965 17:34:28.569940 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8966 17:34:28.573074 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8967 17:34:28.579741 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8968 17:34:28.582942 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8969 17:34:28.586308 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8970 17:34:28.589323 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8971 17:34:28.593193 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8972 17:34:28.599830 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
8973 17:34:28.603054 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8974 17:34:28.606321 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8975 17:34:28.609599 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8976 17:34:28.609691 ==
8977 17:34:28.612456 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 17:34:28.619592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 17:34:28.619732 ==
8980 17:34:28.619801 DQS Delay:
8981 17:34:28.622703 DQS0 = 0, DQS1 = 0
8982 17:34:28.622786 DQM Delay:
8983 17:34:28.626000 DQM0 = 134, DQM1 = 131
8984 17:34:28.626083 DQ Delay:
8985 17:34:28.629245 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8986 17:34:28.632531 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8987 17:34:28.635806 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8988 17:34:28.639527 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
8989 17:34:28.639613
8990 17:34:28.639713
8991 17:34:28.639772
8992 17:34:28.642597 [DramC_TX_OE_Calibration] TA2
8993 17:34:28.645796 Original DQ_B0 (3 6) =30, OEN = 27
8994 17:34:28.649013 Original DQ_B1 (3 6) =30, OEN = 27
8995 17:34:28.652485 24, 0x0, End_B0=24 End_B1=24
8996 17:34:28.656082 25, 0x0, End_B0=25 End_B1=25
8997 17:34:28.656175 26, 0x0, End_B0=26 End_B1=26
8998 17:34:28.659174 27, 0x0, End_B0=27 End_B1=27
8999 17:34:28.662303 28, 0x0, End_B0=28 End_B1=28
9000 17:34:28.665635 29, 0x0, End_B0=29 End_B1=29
9001 17:34:28.665728 30, 0x0, End_B0=30 End_B1=30
9002 17:34:28.668826 31, 0x4141, End_B0=30 End_B1=30
9003 17:34:28.672218 Byte0 end_step=30 best_step=27
9004 17:34:28.675324 Byte1 end_step=30 best_step=27
9005 17:34:28.678930 Byte0 TX OE(2T, 0.5T) = (3, 3)
9006 17:34:28.681989 Byte1 TX OE(2T, 0.5T) = (3, 3)
9007 17:34:28.682080
9008 17:34:28.682143
9009 17:34:28.688567 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9010 17:34:28.692466 CH1 RK1: MR19=303, MR18=2106
9011 17:34:28.698694 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9012 17:34:28.701906 [RxdqsGatingPostProcess] freq 1600
9013 17:34:28.705277 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9014 17:34:28.708570 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 17:34:28.711875 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 17:34:28.715632 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 17:34:28.718720 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 17:34:28.722342 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 17:34:28.725276 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 17:34:28.728771 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 17:34:28.731978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 17:34:28.735274 Pre-setting of DQS Precalculation
9023 17:34:28.738558 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9024 17:34:28.748888 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9025 17:34:28.755518 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9026 17:34:28.755663
9027 17:34:28.755751
9028 17:34:28.758690 [Calibration Summary] 3200 Mbps
9029 17:34:28.758774 CH 0, Rank 0
9030 17:34:28.762021 SW Impedance : PASS
9031 17:34:28.762106 DUTY Scan : NO K
9032 17:34:28.765299 ZQ Calibration : PASS
9033 17:34:28.768430 Jitter Meter : NO K
9034 17:34:28.768517 CBT Training : PASS
9035 17:34:28.772210 Write leveling : PASS
9036 17:34:28.772298 RX DQS gating : PASS
9037 17:34:28.775218 RX DQ/DQS(RDDQC) : PASS
9038 17:34:28.778491 TX DQ/DQS : PASS
9039 17:34:28.778581 RX DATLAT : PASS
9040 17:34:28.781763 RX DQ/DQS(Engine): PASS
9041 17:34:28.785541 TX OE : PASS
9042 17:34:28.785634 All Pass.
9043 17:34:28.785700
9044 17:34:28.785759 CH 0, Rank 1
9045 17:34:28.788829 SW Impedance : PASS
9046 17:34:28.791835 DUTY Scan : NO K
9047 17:34:28.791934 ZQ Calibration : PASS
9048 17:34:28.795158 Jitter Meter : NO K
9049 17:34:28.798726 CBT Training : PASS
9050 17:34:28.798817 Write leveling : PASS
9051 17:34:28.801951 RX DQS gating : PASS
9052 17:34:28.805199 RX DQ/DQS(RDDQC) : PASS
9053 17:34:28.805291 TX DQ/DQS : PASS
9054 17:34:28.808356 RX DATLAT : PASS
9055 17:34:28.811942 RX DQ/DQS(Engine): PASS
9056 17:34:28.812034 TX OE : PASS
9057 17:34:28.812100 All Pass.
9058 17:34:28.815371
9059 17:34:28.815456 CH 1, Rank 0
9060 17:34:28.818509 SW Impedance : PASS
9061 17:34:28.818594 DUTY Scan : NO K
9062 17:34:28.821891 ZQ Calibration : PASS
9063 17:34:28.821977 Jitter Meter : NO K
9064 17:34:28.825038 CBT Training : PASS
9065 17:34:28.828773 Write leveling : PASS
9066 17:34:28.828866 RX DQS gating : PASS
9067 17:34:28.831900 RX DQ/DQS(RDDQC) : PASS
9068 17:34:28.834952 TX DQ/DQS : PASS
9069 17:34:28.835042 RX DATLAT : PASS
9070 17:34:28.838446 RX DQ/DQS(Engine): PASS
9071 17:34:28.841818 TX OE : PASS
9072 17:34:28.841911 All Pass.
9073 17:34:28.841977
9074 17:34:28.842036 CH 1, Rank 1
9075 17:34:28.845155 SW Impedance : PASS
9076 17:34:28.848405 DUTY Scan : NO K
9077 17:34:28.848501 ZQ Calibration : PASS
9078 17:34:28.851563 Jitter Meter : NO K
9079 17:34:28.854915 CBT Training : PASS
9080 17:34:28.855005 Write leveling : PASS
9081 17:34:28.858191 RX DQS gating : PASS
9082 17:34:28.861495 RX DQ/DQS(RDDQC) : PASS
9083 17:34:28.861584 TX DQ/DQS : PASS
9084 17:34:28.864822 RX DATLAT : PASS
9085 17:34:28.864909 RX DQ/DQS(Engine): PASS
9086 17:34:28.868828 TX OE : PASS
9087 17:34:28.868916 All Pass.
9088 17:34:28.868982
9089 17:34:28.871535 DramC Write-DBI on
9090 17:34:28.875353 PER_BANK_REFRESH: Hybrid Mode
9091 17:34:28.875451 TX_TRACKING: ON
9092 17:34:28.885208 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9093 17:34:28.891890 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9094 17:34:28.901456 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 17:34:28.904555 [FAST_K] Save calibration result to emmc
9096 17:34:28.904663 sync common calibartion params.
9097 17:34:28.908282 sync cbt_mode0:1, 1:1
9098 17:34:28.911199 dram_init: ddr_geometry: 2
9099 17:34:28.914827 dram_init: ddr_geometry: 2
9100 17:34:28.914928 dram_init: ddr_geometry: 2
9101 17:34:28.918375 0:dram_rank_size:100000000
9102 17:34:28.921350 1:dram_rank_size:100000000
9103 17:34:28.924645 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9104 17:34:28.927935 DFS_SHUFFLE_HW_MODE: ON
9105 17:34:28.931214 dramc_set_vcore_voltage set vcore to 725000
9106 17:34:28.934827 Read voltage for 1600, 0
9107 17:34:28.934957 Vio18 = 0
9108 17:34:28.938039 Vcore = 725000
9109 17:34:28.938129 Vdram = 0
9110 17:34:28.938193 Vddq = 0
9111 17:34:28.938253 Vmddr = 0
9112 17:34:28.941437 switch to 3200 Mbps bootup
9113 17:34:28.944608 [DramcRunTimeConfig]
9114 17:34:28.944696 PHYPLL
9115 17:34:28.948216 DPM_CONTROL_AFTERK: ON
9116 17:34:28.948334 PER_BANK_REFRESH: ON
9117 17:34:28.951142 REFRESH_OVERHEAD_REDUCTION: ON
9118 17:34:28.954620 CMD_PICG_NEW_MODE: OFF
9119 17:34:28.954732 XRTWTW_NEW_MODE: ON
9120 17:34:28.958177 XRTRTR_NEW_MODE: ON
9121 17:34:28.958268 TX_TRACKING: ON
9122 17:34:28.961393 RDSEL_TRACKING: OFF
9123 17:34:28.961482 DQS Precalculation for DVFS: ON
9124 17:34:28.964677 RX_TRACKING: OFF
9125 17:34:28.964763 HW_GATING DBG: ON
9126 17:34:28.967964 ZQCS_ENABLE_LP4: ON
9127 17:34:28.971224 RX_PICG_NEW_MODE: ON
9128 17:34:28.971318 TX_PICG_NEW_MODE: ON
9129 17:34:28.974555 ENABLE_RX_DCM_DPHY: ON
9130 17:34:28.977822 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9131 17:34:28.977907 DUMMY_READ_FOR_TRACKING: OFF
9132 17:34:28.981158 !!! SPM_CONTROL_AFTERK: OFF
9133 17:34:28.984493 !!! SPM could not control APHY
9134 17:34:28.988482 IMPEDANCE_TRACKING: ON
9135 17:34:28.988587 TEMP_SENSOR: ON
9136 17:34:28.991559 HW_SAVE_FOR_SR: OFF
9137 17:34:28.994899 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9138 17:34:28.997993 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9139 17:34:28.998082 Read ODT Tracking: ON
9140 17:34:29.001165 Refresh Rate DeBounce: ON
9141 17:34:29.004746 DFS_NO_QUEUE_FLUSH: ON
9142 17:34:29.007908 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9143 17:34:29.008009 ENABLE_DFS_RUNTIME_MRW: OFF
9144 17:34:29.011429 DDR_RESERVE_NEW_MODE: ON
9145 17:34:29.014763 MR_CBT_SWITCH_FREQ: ON
9146 17:34:29.014853 =========================
9147 17:34:29.034592 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9148 17:34:29.037663 dram_init: ddr_geometry: 2
9149 17:34:29.055924 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9150 17:34:29.059523 dram_init: dram init end (result: 0)
9151 17:34:29.066056 DRAM-K: Full calibration passed in 24454 msecs
9152 17:34:29.069471 MRC: failed to locate region type 0.
9153 17:34:29.069570 DRAM rank0 size:0x100000000,
9154 17:34:29.072650 DRAM rank1 size=0x100000000
9155 17:34:29.082322 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9156 17:34:29.089614 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9157 17:34:29.095644 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9158 17:34:29.102194 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9159 17:34:29.105503 DRAM rank0 size:0x100000000,
9160 17:34:29.108875 DRAM rank1 size=0x100000000
9161 17:34:29.109008 CBMEM:
9162 17:34:29.112786 IMD: root @ 0xfffff000 254 entries.
9163 17:34:29.115850 IMD: root @ 0xffffec00 62 entries.
9164 17:34:29.118939 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9165 17:34:29.122430 WARNING: RO_VPD is uninitialized or empty.
9166 17:34:29.128877 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9167 17:34:29.135879 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9168 17:34:29.148907 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9169 17:34:29.159861 BS: romstage times (exec / console): total (unknown) / 23987 ms
9170 17:34:29.160000
9171 17:34:29.160069
9172 17:34:29.170086 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9173 17:34:29.173599 ARM64: Exception handlers installed.
9174 17:34:29.176554 ARM64: Testing exception
9175 17:34:29.179917 ARM64: Done test exception
9176 17:34:29.180011 Enumerating buses...
9177 17:34:29.183526 Show all devs... Before device enumeration.
9178 17:34:29.186708 Root Device: enabled 1
9179 17:34:29.190037 CPU_CLUSTER: 0: enabled 1
9180 17:34:29.190125 CPU: 00: enabled 1
9181 17:34:29.193140 Compare with tree...
9182 17:34:29.193306 Root Device: enabled 1
9183 17:34:29.197038 CPU_CLUSTER: 0: enabled 1
9184 17:34:29.200349 CPU: 00: enabled 1
9185 17:34:29.200440 Root Device scanning...
9186 17:34:29.203416 scan_static_bus for Root Device
9187 17:34:29.206825 CPU_CLUSTER: 0 enabled
9188 17:34:29.210241 scan_static_bus for Root Device done
9189 17:34:29.213505 scan_bus: bus Root Device finished in 8 msecs
9190 17:34:29.213640 done
9191 17:34:29.219976 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9192 17:34:29.223380 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9193 17:34:29.229656 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9194 17:34:29.233584 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9195 17:34:29.236832 Allocating resources...
9196 17:34:29.239850 Reading resources...
9197 17:34:29.243198 Root Device read_resources bus 0 link: 0
9198 17:34:29.243289 DRAM rank0 size:0x100000000,
9199 17:34:29.246545 DRAM rank1 size=0x100000000
9200 17:34:29.249893 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9201 17:34:29.253239 CPU: 00 missing read_resources
9202 17:34:29.256475 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9203 17:34:29.262830 Root Device read_resources bus 0 link: 0 done
9204 17:34:29.262936 Done reading resources.
9205 17:34:29.269899 Show resources in subtree (Root Device)...After reading.
9206 17:34:29.272877 Root Device child on link 0 CPU_CLUSTER: 0
9207 17:34:29.276561 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 17:34:29.286529 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 17:34:29.286668 CPU: 00
9210 17:34:29.289708 Root Device assign_resources, bus 0 link: 0
9211 17:34:29.292719 CPU_CLUSTER: 0 missing set_resources
9212 17:34:29.296228 Root Device assign_resources, bus 0 link: 0 done
9213 17:34:29.299577 Done setting resources.
9214 17:34:29.306355 Show resources in subtree (Root Device)...After assigning values.
9215 17:34:29.309486 Root Device child on link 0 CPU_CLUSTER: 0
9216 17:34:29.312954 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 17:34:29.322512 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 17:34:29.322662 CPU: 00
9219 17:34:29.325772 Done allocating resources.
9220 17:34:29.329664 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9221 17:34:29.332957 Enabling resources...
9222 17:34:29.333066 done.
9223 17:34:29.339128 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9224 17:34:29.339241 Initializing devices...
9225 17:34:29.342231 Root Device init
9226 17:34:29.342322 init hardware done!
9227 17:34:29.345966 0x00000018: ctrlr->caps
9228 17:34:29.348935 52.000 MHz: ctrlr->f_max
9229 17:34:29.349054 0.400 MHz: ctrlr->f_min
9230 17:34:29.352775 0x40ff8080: ctrlr->voltages
9231 17:34:29.352900 sclk: 390625
9232 17:34:29.356091 Bus Width = 1
9233 17:34:29.356180 sclk: 390625
9234 17:34:29.358765 Bus Width = 1
9235 17:34:29.358850 Early init status = 3
9236 17:34:29.365878 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9237 17:34:29.369170 in-header: 03 fc 00 00 01 00 00 00
9238 17:34:29.372461 in-data: 00
9239 17:34:29.375782 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9240 17:34:29.380918 in-header: 03 fd 00 00 00 00 00 00
9241 17:34:29.383916 in-data:
9242 17:34:29.387775 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9243 17:34:29.391859 in-header: 03 fc 00 00 01 00 00 00
9244 17:34:29.395229 in-data: 00
9245 17:34:29.398402 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9246 17:34:29.404392 in-header: 03 fd 00 00 00 00 00 00
9247 17:34:29.407459 in-data:
9248 17:34:29.410520 [SSUSB] Setting up USB HOST controller...
9249 17:34:29.414331 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9250 17:34:29.417370 [SSUSB] phy power-on done.
9251 17:34:29.420424 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9252 17:34:29.427127 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9253 17:34:29.430835 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9254 17:34:29.437455 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9255 17:34:29.443932 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9256 17:34:29.450388 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9257 17:34:29.457181 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9258 17:34:29.463818 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9259 17:34:29.466955 SPM: binary array size = 0x9dc
9260 17:34:29.470218 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9261 17:34:29.477471 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9262 17:34:29.484085 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9263 17:34:29.487282 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9264 17:34:29.493675 configure_display: Starting display init
9265 17:34:29.527220 anx7625_power_on_init: Init interface.
9266 17:34:29.530391 anx7625_disable_pd_protocol: Disabled PD feature.
9267 17:34:29.533622 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9268 17:34:29.561441 anx7625_start_dp_work: Secure OCM version=00
9269 17:34:29.565072 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9270 17:34:29.580030 sp_tx_get_edid_block: EDID Block = 1
9271 17:34:29.682333 Extracted contents:
9272 17:34:29.685854 header: 00 ff ff ff ff ff ff 00
9273 17:34:29.689205 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9274 17:34:29.692569 version: 01 04
9275 17:34:29.695288 basic params: 95 1f 11 78 0a
9276 17:34:29.698624 chroma info: 76 90 94 55 54 90 27 21 50 54
9277 17:34:29.702091 established: 00 00 00
9278 17:34:29.708770 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9279 17:34:29.715264 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9280 17:34:29.718374 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9281 17:34:29.724982 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9282 17:34:29.731964 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9283 17:34:29.735228 extensions: 00
9284 17:34:29.735367 checksum: fb
9285 17:34:29.735461
9286 17:34:29.741760 Manufacturer: IVO Model 57d Serial Number 0
9287 17:34:29.741867 Made week 0 of 2020
9288 17:34:29.745129 EDID version: 1.4
9289 17:34:29.745216 Digital display
9290 17:34:29.748524 6 bits per primary color channel
9291 17:34:29.748616 DisplayPort interface
9292 17:34:29.751627 Maximum image size: 31 cm x 17 cm
9293 17:34:29.755044 Gamma: 220%
9294 17:34:29.755140 Check DPMS levels
9295 17:34:29.761771 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9296 17:34:29.764536 First detailed timing is preferred timing
9297 17:34:29.764633 Established timings supported:
9298 17:34:29.767814 Standard timings supported:
9299 17:34:29.771756 Detailed timings
9300 17:34:29.774863 Hex of detail: 383680a07038204018303c0035ae10000019
9301 17:34:29.781156 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9302 17:34:29.784485 0780 0798 07c8 0820 hborder 0
9303 17:34:29.787868 0438 043b 0447 0458 vborder 0
9304 17:34:29.791033 -hsync -vsync
9305 17:34:29.791123 Did detailed timing
9306 17:34:29.797855 Hex of detail: 000000000000000000000000000000000000
9307 17:34:29.800996 Manufacturer-specified data, tag 0
9308 17:34:29.804577 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9309 17:34:29.807806 ASCII string: InfoVision
9310 17:34:29.810928 Hex of detail: 000000fe00523134304e574635205248200a
9311 17:34:29.814503 ASCII string: R140NWF5 RH
9312 17:34:29.814605 Checksum
9313 17:34:29.817530 Checksum: 0xfb (valid)
9314 17:34:29.820819 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9315 17:34:29.824169 DSI data_rate: 832800000 bps
9316 17:34:29.830774 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9317 17:34:29.834510 anx7625_parse_edid: pixelclock(138800).
9318 17:34:29.837509 hactive(1920), hsync(48), hfp(24), hbp(88)
9319 17:34:29.841046 vactive(1080), vsync(12), vfp(3), vbp(17)
9320 17:34:29.844335 anx7625_dsi_config: config dsi.
9321 17:34:29.850691 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9322 17:34:29.864409 anx7625_dsi_config: success to config DSI
9323 17:34:29.867621 anx7625_dp_start: MIPI phy setup OK.
9324 17:34:29.870810 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9325 17:34:29.874267 mtk_ddp_mode_set invalid vrefresh 60
9326 17:34:29.877496 main_disp_path_setup
9327 17:34:29.877584 ovl_layer_smi_id_en
9328 17:34:29.880864 ovl_layer_smi_id_en
9329 17:34:29.880949 ccorr_config
9330 17:34:29.881011 aal_config
9331 17:34:29.884584 gamma_config
9332 17:34:29.884671 postmask_config
9333 17:34:29.887748 dither_config
9334 17:34:29.890980 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9335 17:34:29.897385 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9336 17:34:29.901218 Root Device init finished in 555 msecs
9337 17:34:29.901323 CPU_CLUSTER: 0 init
9338 17:34:29.910841 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9339 17:34:29.914050 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9340 17:34:29.917479 APU_MBOX 0x190000b0 = 0x10001
9341 17:34:29.920792 APU_MBOX 0x190001b0 = 0x10001
9342 17:34:29.924130 APU_MBOX 0x190005b0 = 0x10001
9343 17:34:29.927235 APU_MBOX 0x190006b0 = 0x10001
9344 17:34:29.930906 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9345 17:34:29.943543 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9346 17:34:29.956042 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9347 17:34:29.962330 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9348 17:34:29.974194 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9349 17:34:29.983247 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9350 17:34:29.986554 CPU_CLUSTER: 0 init finished in 81 msecs
9351 17:34:29.989638 Devices initialized
9352 17:34:29.992789 Show all devs... After init.
9353 17:34:29.992925 Root Device: enabled 1
9354 17:34:29.996599 CPU_CLUSTER: 0: enabled 1
9355 17:34:29.999847 CPU: 00: enabled 1
9356 17:34:30.003011 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9357 17:34:30.006015 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9358 17:34:30.009657 ELOG: NV offset 0x57f000 size 0x1000
9359 17:34:30.016435 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9360 17:34:30.022620 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9361 17:34:30.025868 ELOG: Event(17) added with size 13 at 2023-09-13 17:33:02 UTC
9362 17:34:30.029258 out: cmd=0x121: 03 db 21 01 00 00 00 00
9363 17:34:30.033130 in-header: 03 d7 00 00 2c 00 00 00
9364 17:34:30.047012 in-data: 88 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9365 17:34:30.053038 ELOG: Event(A1) added with size 10 at 2023-09-13 17:33:02 UTC
9366 17:34:30.059970 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9367 17:34:30.066601 ELOG: Event(A0) added with size 9 at 2023-09-13 17:33:02 UTC
9368 17:34:30.070034 elog_add_boot_reason: Logged dev mode boot
9369 17:34:30.073491 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9370 17:34:30.076239 Finalize devices...
9371 17:34:30.076355 Devices finalized
9372 17:34:30.083426 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9373 17:34:30.086435 Writing coreboot table at 0xffe64000
9374 17:34:30.089731 0. 000000000010a000-0000000000113fff: RAMSTAGE
9375 17:34:30.093040 1. 0000000040000000-00000000400fffff: RAM
9376 17:34:30.099938 2. 0000000040100000-000000004032afff: RAMSTAGE
9377 17:34:30.102879 3. 000000004032b000-00000000545fffff: RAM
9378 17:34:30.106266 4. 0000000054600000-000000005465ffff: BL31
9379 17:34:30.109455 5. 0000000054660000-00000000ffe63fff: RAM
9380 17:34:30.116547 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9381 17:34:30.119542 7. 0000000100000000-000000023fffffff: RAM
9382 17:34:30.119713 Passing 5 GPIOs to payload:
9383 17:34:30.126554 NAME | PORT | POLARITY | VALUE
9384 17:34:30.129477 EC in RW | 0x000000aa | low | undefined
9385 17:34:30.136706 EC interrupt | 0x00000005 | low | undefined
9386 17:34:30.139952 TPM interrupt | 0x000000ab | high | undefined
9387 17:34:30.143097 SD card detect | 0x00000011 | high | undefined
9388 17:34:30.149363 speaker enable | 0x00000093 | high | undefined
9389 17:34:30.153123 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9390 17:34:30.156237 in-header: 03 f9 00 00 02 00 00 00
9391 17:34:30.159383 in-data: 02 00
9392 17:34:30.159474 ADC[4]: Raw value=904357 ID=7
9393 17:34:30.163164 ADC[3]: Raw value=213810 ID=1
9394 17:34:30.166412 RAM Code: 0x71
9395 17:34:30.166504 ADC[6]: Raw value=75332 ID=0
9396 17:34:30.169675 ADC[5]: Raw value=213072 ID=1
9397 17:34:30.172774 SKU Code: 0x1
9398 17:34:30.176487 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9399 17:34:30.179434 coreboot table: 964 bytes.
9400 17:34:30.182482 IMD ROOT 0. 0xfffff000 0x00001000
9401 17:34:30.185793 IMD SMALL 1. 0xffffe000 0x00001000
9402 17:34:30.189637 RO MCACHE 2. 0xffffc000 0x00001104
9403 17:34:30.192949 CONSOLE 3. 0xfff7c000 0x00080000
9404 17:34:30.196301 FMAP 4. 0xfff7b000 0x00000452
9405 17:34:30.199667 TIME STAMP 5. 0xfff7a000 0x00000910
9406 17:34:30.202928 VBOOT WORK 6. 0xfff66000 0x00014000
9407 17:34:30.206034 RAMOOPS 7. 0xffe66000 0x00100000
9408 17:34:30.209168 COREBOOT 8. 0xffe64000 0x00002000
9409 17:34:30.209266 IMD small region:
9410 17:34:30.212540 IMD ROOT 0. 0xffffec00 0x00000400
9411 17:34:30.215757 VPD 1. 0xffffeb80 0x0000006c
9412 17:34:30.219537 MMC STATUS 2. 0xffffeb60 0x00000004
9413 17:34:30.225948 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9414 17:34:30.228996 Probing TPM: done!
9415 17:34:30.232886 Connected to device vid:did:rid of 1ae0:0028:00
9416 17:34:30.242763 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9417 17:34:30.246164 Initialized TPM device CR50 revision 0
9418 17:34:30.249435 Checking cr50 for pending updates
9419 17:34:30.253451 Reading cr50 TPM mode
9420 17:34:30.262019 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9421 17:34:30.268799 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9422 17:34:30.308539 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9423 17:34:30.311778 Checking segment from ROM address 0x40100000
9424 17:34:30.315539 Checking segment from ROM address 0x4010001c
9425 17:34:30.322319 Loading segment from ROM address 0x40100000
9426 17:34:30.322450 code (compression=0)
9427 17:34:30.331815 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9428 17:34:30.338556 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9429 17:34:30.338683 it's not compressed!
9430 17:34:30.345357 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9431 17:34:30.348705 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9432 17:34:30.369329 Loading segment from ROM address 0x4010001c
9433 17:34:30.369483 Entry Point 0x80000000
9434 17:34:30.372442 Loaded segments
9435 17:34:30.376108 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9436 17:34:30.382623 Jumping to boot code at 0x80000000(0xffe64000)
9437 17:34:30.389211 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9438 17:34:30.396112 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9439 17:34:30.403825 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9440 17:34:30.406929 Checking segment from ROM address 0x40100000
9441 17:34:30.410182 Checking segment from ROM address 0x4010001c
9442 17:34:30.417448 Loading segment from ROM address 0x40100000
9443 17:34:30.417567 code (compression=1)
9444 17:34:30.423766 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9445 17:34:30.433509 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9446 17:34:30.433654 using LZMA
9447 17:34:30.441682 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9448 17:34:30.448366 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9449 17:34:30.452005 Loading segment from ROM address 0x4010001c
9450 17:34:30.452119 Entry Point 0x54601000
9451 17:34:30.455059 Loaded segments
9452 17:34:30.458608 NOTICE: MT8192 bl31_setup
9453 17:34:30.465885 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9454 17:34:30.469093 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9455 17:34:30.472269 WARNING: region 0:
9456 17:34:30.475589 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 17:34:30.475726 WARNING: region 1:
9458 17:34:30.482120 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9459 17:34:30.485952 WARNING: region 2:
9460 17:34:30.489064 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9461 17:34:30.492160 WARNING: region 3:
9462 17:34:30.495918 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 17:34:30.499246 WARNING: region 4:
9464 17:34:30.502547 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 17:34:30.505852 WARNING: region 5:
9466 17:34:30.508759 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 17:34:30.512279 WARNING: region 6:
9468 17:34:30.515857 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 17:34:30.515970 WARNING: region 7:
9470 17:34:30.522297 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 17:34:30.528857 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9472 17:34:30.532692 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9473 17:34:30.535823 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9474 17:34:30.542609 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9475 17:34:30.545579 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9476 17:34:30.548831 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9477 17:34:30.555985 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9478 17:34:30.559093 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9479 17:34:30.562784 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9480 17:34:30.569160 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9481 17:34:30.572454 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9482 17:34:30.578947 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9483 17:34:30.582106 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9484 17:34:30.586101 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9485 17:34:30.592387 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9486 17:34:30.595613 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9487 17:34:30.599315 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9488 17:34:30.606007 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9489 17:34:30.609301 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9490 17:34:30.612578 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9491 17:34:30.619339 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9492 17:34:30.622183 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9493 17:34:30.628941 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9494 17:34:30.632726 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9495 17:34:30.635869 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9496 17:34:30.642338 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9497 17:34:30.645524 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9498 17:34:30.652371 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9499 17:34:30.655492 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9500 17:34:30.659504 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9501 17:34:30.666021 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9502 17:34:30.669090 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9503 17:34:30.672863 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9504 17:34:30.679437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9505 17:34:30.682604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9506 17:34:30.685915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9507 17:34:30.689264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9508 17:34:30.696264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9509 17:34:30.699530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9510 17:34:30.702739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9511 17:34:30.705918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9512 17:34:30.709636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9513 17:34:30.716237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9514 17:34:30.719480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9515 17:34:30.722815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9516 17:34:30.726700 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9517 17:34:30.732817 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9518 17:34:30.736341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9519 17:34:30.740031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9520 17:34:30.746305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9521 17:34:30.749880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9522 17:34:30.756839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9523 17:34:30.759890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9524 17:34:30.763391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9525 17:34:30.769943 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9526 17:34:30.773184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9527 17:34:30.779888 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9528 17:34:30.783260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9529 17:34:30.790242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9530 17:34:30.793576 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9531 17:34:30.799864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9532 17:34:30.803733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9533 17:34:30.807106 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9534 17:34:30.813580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9535 17:34:30.816812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9536 17:34:30.823553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9537 17:34:30.826592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9538 17:34:30.829921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9539 17:34:30.836955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9540 17:34:30.840063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9541 17:34:30.847007 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9542 17:34:30.850115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9543 17:34:30.857137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9544 17:34:30.860001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9545 17:34:30.863428 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9546 17:34:30.870025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9547 17:34:30.873655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9548 17:34:30.880272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9549 17:34:30.883576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9550 17:34:30.890840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9551 17:34:30.893713 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9552 17:34:30.900141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9553 17:34:30.903311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9554 17:34:30.907178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9555 17:34:30.913732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9556 17:34:30.917181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9557 17:34:30.923568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9558 17:34:30.926824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9559 17:34:30.933131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9560 17:34:30.936711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9561 17:34:30.939829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9562 17:34:30.946954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9563 17:34:30.950268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9564 17:34:30.957072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9565 17:34:30.960343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9566 17:34:30.966827 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9567 17:34:30.969963 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9568 17:34:30.973551 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9569 17:34:30.976503 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9570 17:34:30.983433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9571 17:34:30.986781 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9572 17:34:30.989945 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9573 17:34:30.997062 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9574 17:34:31.000233 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9575 17:34:31.003815 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9576 17:34:31.010063 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9577 17:34:31.013903 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9578 17:34:31.020537 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9579 17:34:31.023743 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9580 17:34:31.027040 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9581 17:34:31.033650 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9582 17:34:31.036948 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9583 17:34:31.043368 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9584 17:34:31.046871 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9585 17:34:31.050276 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9586 17:34:31.056664 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9587 17:34:31.060493 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9588 17:34:31.063675 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9589 17:34:31.070422 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9590 17:34:31.073503 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9591 17:34:31.076703 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9592 17:34:31.080629 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9593 17:34:31.086960 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9594 17:34:31.090228 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9595 17:34:31.093838 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9596 17:34:31.100486 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9597 17:34:31.103564 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9598 17:34:31.107292 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9599 17:34:31.113722 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9600 17:34:31.117084 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9601 17:34:31.120287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9602 17:34:31.127019 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9603 17:34:31.130346 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9604 17:34:31.136971 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9605 17:34:31.140233 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9606 17:34:31.143482 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9607 17:34:31.150827 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9608 17:34:31.153538 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9609 17:34:31.160367 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9610 17:34:31.163551 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9611 17:34:31.166766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9612 17:34:31.173361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9613 17:34:31.176764 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9614 17:34:31.183673 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9615 17:34:31.187258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9616 17:34:31.190523 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9617 17:34:31.197241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9618 17:34:31.200441 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9619 17:34:31.203477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9620 17:34:31.210047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9621 17:34:31.213900 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9622 17:34:31.220500 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9623 17:34:31.223402 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9624 17:34:31.226912 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9625 17:34:31.233730 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9626 17:34:31.237117 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9627 17:34:31.243632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9628 17:34:31.246923 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9629 17:34:31.250894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9630 17:34:31.256998 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9631 17:34:31.260318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9632 17:34:31.263497 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9633 17:34:31.270241 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9634 17:34:31.274165 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9635 17:34:31.280309 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9636 17:34:31.283384 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9637 17:34:31.287006 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9638 17:34:31.293552 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9639 17:34:31.296861 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9640 17:34:31.303041 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9641 17:34:31.306730 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9642 17:34:31.309946 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9643 17:34:31.316186 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9644 17:34:31.319826 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9645 17:34:31.326314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9646 17:34:31.330086 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9647 17:34:31.333253 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9648 17:34:31.339776 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9649 17:34:31.343354 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9650 17:34:31.349403 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9651 17:34:31.353288 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9652 17:34:31.356592 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9653 17:34:31.362970 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9654 17:34:31.366334 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9655 17:34:31.372722 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9656 17:34:31.376484 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9657 17:34:31.379754 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9658 17:34:31.386304 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9659 17:34:31.389638 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9660 17:34:31.396626 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9661 17:34:31.399887 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9662 17:34:31.403177 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9663 17:34:31.409725 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9664 17:34:31.412663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9665 17:34:31.419195 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9666 17:34:31.422499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9667 17:34:31.425940 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9668 17:34:31.432521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9669 17:34:31.435893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9670 17:34:31.442313 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9671 17:34:31.445833 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9672 17:34:31.452559 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9673 17:34:31.456221 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9674 17:34:31.458893 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9675 17:34:31.466154 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9676 17:34:31.469376 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9677 17:34:31.475978 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9678 17:34:31.479123 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9679 17:34:31.482941 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9680 17:34:31.489475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9681 17:34:31.492198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9682 17:34:31.499389 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9683 17:34:31.502564 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9684 17:34:31.509255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9685 17:34:31.512535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9686 17:34:31.515756 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9687 17:34:31.522322 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9688 17:34:31.525508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9689 17:34:31.532555 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9690 17:34:31.535786 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9691 17:34:31.538887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9692 17:34:31.545560 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9693 17:34:31.548762 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9694 17:34:31.555610 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9695 17:34:31.559134 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9696 17:34:31.565893 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9697 17:34:31.569205 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9698 17:34:31.572597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9699 17:34:31.579089 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9700 17:34:31.582285 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9701 17:34:31.585290 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9702 17:34:31.589157 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9703 17:34:31.595810 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9704 17:34:31.598484 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9705 17:34:31.602406 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9706 17:34:31.608652 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9707 17:34:31.611936 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9708 17:34:31.615222 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9709 17:34:31.621871 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9710 17:34:31.625170 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9711 17:34:31.628375 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9712 17:34:31.635219 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9713 17:34:31.638720 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9714 17:34:31.645233 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9715 17:34:31.648365 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9716 17:34:31.651741 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9717 17:34:31.658581 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9718 17:34:31.661959 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9719 17:34:31.664969 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9720 17:34:31.672072 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9721 17:34:31.675231 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9722 17:34:31.678298 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9723 17:34:31.685260 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9724 17:34:31.688532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9725 17:34:31.692063 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9726 17:34:31.698867 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9727 17:34:31.702212 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9728 17:34:31.708865 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9729 17:34:31.711926 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9730 17:34:31.715280 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9731 17:34:31.721654 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9732 17:34:31.724921 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9733 17:34:31.731444 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9734 17:34:31.734732 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9735 17:34:31.738082 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9736 17:34:31.744606 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9737 17:34:31.748315 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9738 17:34:31.751616 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9739 17:34:31.758258 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9740 17:34:31.761543 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9741 17:34:31.764747 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9742 17:34:31.767822 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9743 17:34:31.771491 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9744 17:34:31.777848 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9745 17:34:31.780984 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9746 17:34:31.784279 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9747 17:34:31.791311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9748 17:34:31.794510 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9749 17:34:31.797790 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9750 17:34:31.801110 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9751 17:34:31.807528 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9752 17:34:31.810965 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9753 17:34:31.814004 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9754 17:34:31.820799 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9755 17:34:31.824085 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9756 17:34:31.830819 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9757 17:34:31.834107 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9758 17:34:31.840818 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9759 17:34:31.844101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9760 17:34:31.847337 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9761 17:34:31.853857 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9762 17:34:31.857096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9763 17:34:31.863658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9764 17:34:31.867234 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9765 17:34:31.870302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9766 17:34:31.876745 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9767 17:34:31.880073 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9768 17:34:31.886685 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9769 17:34:31.890163 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9770 17:34:31.893293 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9771 17:34:31.900541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9772 17:34:31.903658 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9773 17:34:31.910307 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9774 17:34:31.913394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9775 17:34:31.920097 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9776 17:34:31.923224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9777 17:34:31.926658 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9778 17:34:31.933390 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9779 17:34:31.936707 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9780 17:34:31.943161 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9781 17:34:31.946505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9782 17:34:31.949735 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9783 17:34:31.956392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9784 17:34:31.960290 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9785 17:34:31.966866 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9786 17:34:31.970099 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9787 17:34:31.973024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9788 17:34:31.979672 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9789 17:34:31.982910 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9790 17:34:31.990141 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9791 17:34:31.993265 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9792 17:34:31.996830 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9793 17:34:32.003566 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9794 17:34:32.006791 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9795 17:34:32.013331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9796 17:34:32.016769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9797 17:34:32.020039 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9798 17:34:32.026545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9799 17:34:32.029732 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9800 17:34:32.036772 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9801 17:34:32.039684 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9802 17:34:32.043242 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9803 17:34:32.049835 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9804 17:34:32.053193 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9805 17:34:32.059897 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9806 17:34:32.063212 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9807 17:34:32.069744 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9808 17:34:32.073089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9809 17:34:32.076391 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9810 17:34:32.082791 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9811 17:34:32.086338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9812 17:34:32.092848 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9813 17:34:32.096484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9814 17:34:32.099809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9815 17:34:32.106463 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9816 17:34:32.109480 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9817 17:34:32.115985 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9818 17:34:32.119267 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9819 17:34:32.122526 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9820 17:34:32.129652 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9821 17:34:32.132732 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9822 17:34:32.139368 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9823 17:34:32.142602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9824 17:34:32.145807 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9825 17:34:32.152828 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9826 17:34:32.156059 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9827 17:34:32.162283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9828 17:34:32.165879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9829 17:34:32.172579 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9830 17:34:32.175888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9831 17:34:32.182564 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9832 17:34:32.185664 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9833 17:34:32.188890 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9834 17:34:32.196040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9835 17:34:32.198974 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9836 17:34:32.205667 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9837 17:34:32.209109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9838 17:34:32.215627 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9839 17:34:32.218795 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9840 17:34:32.222627 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9841 17:34:32.228756 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9842 17:34:32.232100 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9843 17:34:32.239042 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9844 17:34:32.242330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9845 17:34:32.248793 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9846 17:34:32.251764 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9847 17:34:32.258952 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9848 17:34:32.262186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9849 17:34:32.265525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9850 17:34:32.272012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9851 17:34:32.275308 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9852 17:34:32.282147 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9853 17:34:32.285134 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9854 17:34:32.291832 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9855 17:34:32.295094 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9856 17:34:32.298400 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9857 17:34:32.304751 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9858 17:34:32.308398 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9859 17:34:32.314809 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9860 17:34:32.318384 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9861 17:34:32.325004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9862 17:34:32.328066 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9863 17:34:32.334523 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9864 17:34:32.337774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9865 17:34:32.341020 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9866 17:34:32.348272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9867 17:34:32.350964 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9868 17:34:32.357946 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9869 17:34:32.361139 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9870 17:34:32.367459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9871 17:34:32.370681 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9872 17:34:32.374547 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9873 17:34:32.381109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9874 17:34:32.384450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9875 17:34:32.391305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9876 17:34:32.394188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9877 17:34:32.400911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9878 17:34:32.404027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9879 17:34:32.411088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9880 17:34:32.414373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9881 17:34:32.421035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9882 17:34:32.424068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9883 17:34:32.427668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9884 17:34:32.434190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9885 17:34:32.437341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9886 17:34:32.444219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9887 17:34:32.447403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9888 17:34:32.454385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9889 17:34:32.457837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9890 17:34:32.464177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9891 17:34:32.467316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9892 17:34:32.474158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9893 17:34:32.477296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9894 17:34:32.483859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9895 17:34:32.487669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9896 17:34:32.493787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9897 17:34:32.497232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9898 17:34:32.503925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9899 17:34:32.506907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9900 17:34:32.513692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9901 17:34:32.517425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9902 17:34:32.523818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9903 17:34:32.527189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9904 17:34:32.533578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9905 17:34:32.537193 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9906 17:34:32.540177 INFO: [APUAPC] vio 0
9907 17:34:32.543382 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9908 17:34:32.550031 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9909 17:34:32.553749 INFO: [APUAPC] D0_APC_0: 0x400510
9910 17:34:32.553876 INFO: [APUAPC] D0_APC_1: 0x0
9911 17:34:32.556715 INFO: [APUAPC] D0_APC_2: 0x1540
9912 17:34:32.559904 INFO: [APUAPC] D0_APC_3: 0x0
9913 17:34:32.563794 INFO: [APUAPC] D1_APC_0: 0xffffffff
9914 17:34:32.566852 INFO: [APUAPC] D1_APC_1: 0xffffffff
9915 17:34:32.570259 INFO: [APUAPC] D1_APC_2: 0x3fffff
9916 17:34:32.573518 INFO: [APUAPC] D1_APC_3: 0x0
9917 17:34:32.576694 INFO: [APUAPC] D2_APC_0: 0xffffffff
9918 17:34:32.579868 INFO: [APUAPC] D2_APC_1: 0xffffffff
9919 17:34:32.583498 INFO: [APUAPC] D2_APC_2: 0x3fffff
9920 17:34:32.586816 INFO: [APUAPC] D2_APC_3: 0x0
9921 17:34:32.590200 INFO: [APUAPC] D3_APC_0: 0xffffffff
9922 17:34:32.593391 INFO: [APUAPC] D3_APC_1: 0xffffffff
9923 17:34:32.596738 INFO: [APUAPC] D3_APC_2: 0x3fffff
9924 17:34:32.600051 INFO: [APUAPC] D3_APC_3: 0x0
9925 17:34:32.603381 INFO: [APUAPC] D4_APC_0: 0xffffffff
9926 17:34:32.606744 INFO: [APUAPC] D4_APC_1: 0xffffffff
9927 17:34:32.609991 INFO: [APUAPC] D4_APC_2: 0x3fffff
9928 17:34:32.613214 INFO: [APUAPC] D4_APC_3: 0x0
9929 17:34:32.617074 INFO: [APUAPC] D5_APC_0: 0xffffffff
9930 17:34:32.619961 INFO: [APUAPC] D5_APC_1: 0xffffffff
9931 17:34:32.623463 INFO: [APUAPC] D5_APC_2: 0x3fffff
9932 17:34:32.626972 INFO: [APUAPC] D5_APC_3: 0x0
9933 17:34:32.630153 INFO: [APUAPC] D6_APC_0: 0xffffffff
9934 17:34:32.633470 INFO: [APUAPC] D6_APC_1: 0xffffffff
9935 17:34:32.636327 INFO: [APUAPC] D6_APC_2: 0x3fffff
9936 17:34:32.640163 INFO: [APUAPC] D6_APC_3: 0x0
9937 17:34:32.643387 INFO: [APUAPC] D7_APC_0: 0xffffffff
9938 17:34:32.646232 INFO: [APUAPC] D7_APC_1: 0xffffffff
9939 17:34:32.649922 INFO: [APUAPC] D7_APC_2: 0x3fffff
9940 17:34:32.652960 INFO: [APUAPC] D7_APC_3: 0x0
9941 17:34:32.656778 INFO: [APUAPC] D8_APC_0: 0xffffffff
9942 17:34:32.659505 INFO: [APUAPC] D8_APC_1: 0xffffffff
9943 17:34:32.663006 INFO: [APUAPC] D8_APC_2: 0x3fffff
9944 17:34:32.666580 INFO: [APUAPC] D8_APC_3: 0x0
9945 17:34:32.669654 INFO: [APUAPC] D9_APC_0: 0xffffffff
9946 17:34:32.673260 INFO: [APUAPC] D9_APC_1: 0xffffffff
9947 17:34:32.676507 INFO: [APUAPC] D9_APC_2: 0x3fffff
9948 17:34:32.679831 INFO: [APUAPC] D9_APC_3: 0x0
9949 17:34:32.683046 INFO: [APUAPC] D10_APC_0: 0xffffffff
9950 17:34:32.686258 INFO: [APUAPC] D10_APC_1: 0xffffffff
9951 17:34:32.689284 INFO: [APUAPC] D10_APC_2: 0x3fffff
9952 17:34:32.693001 INFO: [APUAPC] D10_APC_3: 0x0
9953 17:34:32.696305 INFO: [APUAPC] D11_APC_0: 0xffffffff
9954 17:34:32.699670 INFO: [APUAPC] D11_APC_1: 0xffffffff
9955 17:34:32.702972 INFO: [APUAPC] D11_APC_2: 0x3fffff
9956 17:34:32.706194 INFO: [APUAPC] D11_APC_3: 0x0
9957 17:34:32.709573 INFO: [APUAPC] D12_APC_0: 0xffffffff
9958 17:34:32.712859 INFO: [APUAPC] D12_APC_1: 0xffffffff
9959 17:34:32.716078 INFO: [APUAPC] D12_APC_2: 0x3fffff
9960 17:34:32.719461 INFO: [APUAPC] D12_APC_3: 0x0
9961 17:34:32.722755 INFO: [APUAPC] D13_APC_0: 0xffffffff
9962 17:34:32.726006 INFO: [APUAPC] D13_APC_1: 0xffffffff
9963 17:34:32.729858 INFO: [APUAPC] D13_APC_2: 0x3fffff
9964 17:34:32.732899 INFO: [APUAPC] D13_APC_3: 0x0
9965 17:34:32.736238 INFO: [APUAPC] D14_APC_0: 0xffffffff
9966 17:34:32.739379 INFO: [APUAPC] D14_APC_1: 0xffffffff
9967 17:34:32.742897 INFO: [APUAPC] D14_APC_2: 0x3fffff
9968 17:34:32.746487 INFO: [APUAPC] D14_APC_3: 0x0
9969 17:34:32.749417 INFO: [APUAPC] D15_APC_0: 0xffffffff
9970 17:34:32.752766 INFO: [APUAPC] D15_APC_1: 0xffffffff
9971 17:34:32.756445 INFO: [APUAPC] D15_APC_2: 0x3fffff
9972 17:34:32.759246 INFO: [APUAPC] D15_APC_3: 0x0
9973 17:34:32.759358 INFO: [APUAPC] APC_CON: 0x4
9974 17:34:32.762529 INFO: [NOCDAPC] D0_APC_0: 0x0
9975 17:34:32.766209 INFO: [NOCDAPC] D0_APC_1: 0x0
9976 17:34:32.769463 INFO: [NOCDAPC] D1_APC_0: 0x0
9977 17:34:32.772738 INFO: [NOCDAPC] D1_APC_1: 0xfff
9978 17:34:32.776156 INFO: [NOCDAPC] D2_APC_0: 0x0
9979 17:34:32.779338 INFO: [NOCDAPC] D2_APC_1: 0xfff
9980 17:34:32.782762 INFO: [NOCDAPC] D3_APC_0: 0x0
9981 17:34:32.785739 INFO: [NOCDAPC] D3_APC_1: 0xfff
9982 17:34:32.789478 INFO: [NOCDAPC] D4_APC_0: 0x0
9983 17:34:32.792773 INFO: [NOCDAPC] D4_APC_1: 0xfff
9984 17:34:32.792888 INFO: [NOCDAPC] D5_APC_0: 0x0
9985 17:34:32.795929 INFO: [NOCDAPC] D5_APC_1: 0xfff
9986 17:34:32.799532 INFO: [NOCDAPC] D6_APC_0: 0x0
9987 17:34:32.802804 INFO: [NOCDAPC] D6_APC_1: 0xfff
9988 17:34:32.806089 INFO: [NOCDAPC] D7_APC_0: 0x0
9989 17:34:32.809499 INFO: [NOCDAPC] D7_APC_1: 0xfff
9990 17:34:32.812838 INFO: [NOCDAPC] D8_APC_0: 0x0
9991 17:34:32.816162 INFO: [NOCDAPC] D8_APC_1: 0xfff
9992 17:34:32.819421 INFO: [NOCDAPC] D9_APC_0: 0x0
9993 17:34:32.822607 INFO: [NOCDAPC] D9_APC_1: 0xfff
9994 17:34:32.825876 INFO: [NOCDAPC] D10_APC_0: 0x0
9995 17:34:32.825981 INFO: [NOCDAPC] D10_APC_1: 0xfff
9996 17:34:32.829105 INFO: [NOCDAPC] D11_APC_0: 0x0
9997 17:34:32.832343 INFO: [NOCDAPC] D11_APC_1: 0xfff
9998 17:34:32.835472 INFO: [NOCDAPC] D12_APC_0: 0x0
9999 17:34:32.838713 INFO: [NOCDAPC] D12_APC_1: 0xfff
10000 17:34:32.842068 INFO: [NOCDAPC] D13_APC_0: 0x0
10001 17:34:32.845324 INFO: [NOCDAPC] D13_APC_1: 0xfff
10002 17:34:32.849230 INFO: [NOCDAPC] D14_APC_0: 0x0
10003 17:34:32.852261 INFO: [NOCDAPC] D14_APC_1: 0xfff
10004 17:34:32.856029 INFO: [NOCDAPC] D15_APC_0: 0x0
10005 17:34:32.858943 INFO: [NOCDAPC] D15_APC_1: 0xfff
10006 17:34:32.862206 INFO: [NOCDAPC] APC_CON: 0x4
10007 17:34:32.865466 INFO: [APUAPC] set_apusys_apc done
10008 17:34:32.869133 INFO: [DEVAPC] devapc_init done
10009 17:34:32.872320 INFO: GICv3 without legacy support detected.
10010 17:34:32.875300 INFO: ARM GICv3 driver initialized in EL3
10011 17:34:32.878792 INFO: Maximum SPI INTID supported: 639
10012 17:34:32.882252 INFO: BL31: Initializing runtime services
10013 17:34:32.888491 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10014 17:34:32.892558 INFO: SPM: enable CPC mode
10015 17:34:32.898725 INFO: mcdi ready for mcusys-off-idle and system suspend
10016 17:34:32.901971 INFO: BL31: Preparing for EL3 exit to normal world
10017 17:34:32.905197 INFO: Entry point address = 0x80000000
10018 17:34:32.908448 INFO: SPSR = 0x8
10019 17:34:32.913303
10020 17:34:32.913402
10021 17:34:32.913466
10022 17:34:32.914182 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10023 17:34:32.914285 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10024 17:34:32.914365 Setting prompt string to ['asurada:']
10025 17:34:32.914441 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10026 17:34:32.916909 Starting depthcharge on Spherion...
10027 17:34:32.916992
10028 17:34:32.917055 Wipe memory regions:
10029 17:34:32.917113
10030 17:34:32.920310 [0x00000040000000, 0x00000054600000)
10031 17:34:33.042066
10032 17:34:33.042242 [0x00000054660000, 0x00000080000000)
10033 17:34:33.302598
10034 17:34:33.302769 [0x000000821a7280, 0x000000ffe64000)
10035 17:34:34.047600
10036 17:34:34.047789 [0x00000100000000, 0x00000240000000)
10037 17:34:35.936353
10038 17:34:35.940011 Initializing XHCI USB controller at 0x11200000.
10039 17:34:36.978289
10040 17:34:36.981464 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10041 17:34:36.981580
10042 17:34:36.981670
10043 17:34:36.981756
10044 17:34:36.982067 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 17:34:37.082451 asurada: tftpboot 192.168.201.1 11518302/tftp-deploy-lkfdnmk9/kernel/image.itb 11518302/tftp-deploy-lkfdnmk9/kernel/cmdline
10047 17:34:37.082627 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 17:34:37.082734 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10049 17:34:37.087516 tftpboot 192.168.201.1 11518302/tftp-deploy-lkfdnmk9/kernel/image.ittp-deploy-lkfdnmk9/kernel/cmdline
10050 17:34:37.087635
10051 17:34:37.087717 Waiting for link
10052 17:34:37.245448
10053 17:34:37.245601 R8152: Initializing
10054 17:34:37.245668
10055 17:34:37.248818 Version 9 (ocp_data = 6010)
10056 17:34:37.248901
10057 17:34:37.252278 R8152: Done initializing
10058 17:34:37.252365
10059 17:34:37.252436 Adding net device
10060 17:34:39.199926
10061 17:34:39.200070 done.
10062 17:34:39.200139
10063 17:34:39.200198 MAC: 00:e0:4c:78:7a:aa
10064 17:34:39.200254
10065 17:34:39.203588 Sending DHCP discover... done.
10066 17:34:39.203732
10067 17:34:39.206815 Waiting for reply... done.
10068 17:34:39.206927
10069 17:34:39.209663 Sending DHCP request... done.
10070 17:34:39.209737
10071 17:34:39.209798 Waiting for reply... done.
10072 17:34:39.209855
10073 17:34:39.213515 My ip is 192.168.201.12
10074 17:34:39.213595
10075 17:34:39.216271 The DHCP server ip is 192.168.201.1
10076 17:34:39.216351
10077 17:34:39.219890 TFTP server IP predefined by user: 192.168.201.1
10078 17:34:39.219971
10079 17:34:39.226280 Bootfile predefined by user: 11518302/tftp-deploy-lkfdnmk9/kernel/image.itb
10080 17:34:39.226363
10081 17:34:39.229577 Sending tftp read request... done.
10082 17:34:39.229656
10083 17:34:39.232882 Waiting for the transfer...
10084 17:34:39.232964
10085 17:34:39.498224 00000000 ################################################################
10086 17:34:39.498376
10087 17:34:39.759699 00080000 ################################################################
10088 17:34:39.759878
10089 17:34:40.014561 00100000 ################################################################
10090 17:34:40.014710
10091 17:34:40.268384 00180000 ################################################################
10092 17:34:40.268521
10093 17:34:40.525884 00200000 ################################################################
10094 17:34:40.526027
10095 17:34:40.781523 00280000 ################################################################
10096 17:34:40.781673
10097 17:34:41.038183 00300000 ################################################################
10098 17:34:41.038325
10099 17:34:41.292123 00380000 ################################################################
10100 17:34:41.292289
10101 17:34:41.544316 00400000 ################################################################
10102 17:34:41.544524
10103 17:34:41.798741 00480000 ################################################################
10104 17:34:41.798896
10105 17:34:42.052602 00500000 ################################################################
10106 17:34:42.052788
10107 17:34:42.311474 00580000 ################################################################
10108 17:34:42.311680
10109 17:34:42.570572 00600000 ################################################################
10110 17:34:42.570759
10111 17:34:42.867420 00680000 ################################################################
10112 17:34:42.867607
10113 17:34:43.191892 00700000 ################################################################
10114 17:34:43.192046
10115 17:34:43.517081 00780000 ################################################################
10116 17:34:43.517258
10117 17:34:43.852679 00800000 ################################################################
10118 17:34:43.852863
10119 17:34:44.111841 00880000 ################################################################
10120 17:34:44.112029
10121 17:34:44.367787 00900000 ################################################################
10122 17:34:44.367954
10123 17:34:44.619020 00980000 ################################################################
10124 17:34:44.619158
10125 17:34:44.872814 00a00000 ################################################################
10126 17:34:44.872986
10127 17:34:45.139390 00a80000 ################################################################
10128 17:34:45.139525
10129 17:34:45.401432 00b00000 ################################################################
10130 17:34:45.401591
10131 17:34:45.657866 00b80000 ################################################################
10132 17:34:45.658041
10133 17:34:45.918314 00c00000 ################################################################
10134 17:34:45.918450
10135 17:34:46.182301 00c80000 ################################################################
10136 17:34:46.182469
10137 17:34:46.446313 00d00000 ################################################################
10138 17:34:46.446468
10139 17:34:46.725764 00d80000 ################################################################
10140 17:34:46.725906
10141 17:34:46.983491 00e00000 ################################################################
10142 17:34:46.983675
10143 17:34:47.240949 00e80000 ################################################################
10144 17:34:47.241085
10145 17:34:47.493989 00f00000 ################################################################
10146 17:34:47.494136
10147 17:34:47.749568 00f80000 ################################################################
10148 17:34:47.749707
10149 17:34:48.010377 01000000 ################################################################
10150 17:34:48.010540
10151 17:34:48.267199 01080000 ################################################################
10152 17:34:48.267351
10153 17:34:48.520300 01100000 ################################################################
10154 17:34:48.520439
10155 17:34:48.783810 01180000 ################################################################
10156 17:34:48.783964
10157 17:34:49.049895 01200000 ################################################################
10158 17:34:49.050056
10159 17:34:49.321889 01280000 ################################################################
10160 17:34:49.322050
10161 17:34:49.586572 01300000 ################################################################
10162 17:34:49.586717
10163 17:34:49.849025 01380000 ################################################################
10164 17:34:49.849166
10165 17:34:50.113887 01400000 ################################################################
10166 17:34:50.114027
10167 17:34:50.374641 01480000 ################################################################
10168 17:34:50.374788
10169 17:34:50.634786 01500000 ################################################################
10170 17:34:50.634936
10171 17:34:50.912613 01580000 ################################################################
10172 17:34:50.912788
10173 17:34:51.183435 01600000 ################################################################
10174 17:34:51.183625
10175 17:34:51.443261 01680000 ################################################################
10176 17:34:51.443445
10177 17:34:51.701483 01700000 ################################################################
10178 17:34:51.701640
10179 17:34:51.960762 01780000 ################################################################
10180 17:34:51.960924
10181 17:34:52.214174 01800000 ################################################################
10182 17:34:52.214330
10183 17:34:52.469556 01880000 ################################################################
10184 17:34:52.469741
10185 17:34:52.724335 01900000 ################################################################
10186 17:34:52.724475
10187 17:34:52.985393 01980000 ################################################################
10188 17:34:52.985540
10189 17:34:53.308825 01a00000 ################################################################
10190 17:34:53.309002
10191 17:34:53.596843 01a80000 ################################################################
10192 17:34:53.596991
10193 17:34:53.850907 01b00000 ################################################################
10194 17:34:53.851064
10195 17:34:54.106364 01b80000 ################################################################
10196 17:34:54.106527
10197 17:34:54.364033 01c00000 ################################################################
10198 17:34:54.364175
10199 17:34:54.617014 01c80000 ################################################################
10200 17:34:54.617150
10201 17:34:54.868489 01d00000 ################################################################
10202 17:34:54.868621
10203 17:34:55.119328 01d80000 ################################################################
10204 17:34:55.119491
10205 17:34:55.379392 01e00000 ################################################################
10206 17:34:55.379572
10207 17:34:55.629229 01e80000 ############################################################# done.
10208 17:34:55.629375
10209 17:34:55.632371 The bootfile was 32478422 bytes long.
10210 17:34:55.632456
10211 17:34:55.632518 Sending tftp read request... done.
10212 17:34:55.632577
10213 17:34:55.636292 Waiting for the transfer...
10214 17:34:55.636372
10215 17:34:55.639457 00000000 # done.
10216 17:34:55.639539
10217 17:34:55.646180 Command line loaded dynamically from TFTP file: 11518302/tftp-deploy-lkfdnmk9/kernel/cmdline
10218 17:34:55.646261
10219 17:34:55.659279 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10220 17:34:55.659364
10221 17:34:55.662723 Loading FIT.
10222 17:34:55.662803
10223 17:34:55.662865 Image ramdisk-1 has 21389860 bytes.
10224 17:34:55.666000
10225 17:34:55.666079 Image fdt-1 has 47278 bytes.
10226 17:34:55.666142
10227 17:34:55.669207 Image kernel-1 has 11039249 bytes.
10228 17:34:55.669286
10229 17:34:55.679217 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10230 17:34:55.679299
10231 17:34:55.696182 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10232 17:34:55.696311
10233 17:34:55.702652 Choosing best match conf-1 for compat google,spherion-rev2.
10234 17:34:55.702733
10235 17:34:55.710291 Connected to device vid:did:rid of 1ae0:0028:00
10236 17:34:55.718486
10237 17:34:55.722011 tpm_get_response: command 0x17b, return code 0x0
10238 17:34:55.722093
10239 17:34:55.725054 ec_init: CrosEC protocol v3 supported (256, 248)
10240 17:34:55.728860
10241 17:34:55.732234 tpm_cleanup: add release locality here.
10242 17:34:55.732314
10243 17:34:55.732377 Shutting down all USB controllers.
10244 17:34:55.735955
10245 17:34:55.736034 Removing current net device
10246 17:34:55.736096
10247 17:34:55.742623 Exiting depthcharge with code 4 at timestamp: 52103506
10248 17:34:55.742703
10249 17:34:55.745863 LZMA decompressing kernel-1 to 0x821a6718
10250 17:34:55.745942
10251 17:34:55.749445 LZMA decompressing kernel-1 to 0x40000000
10252 17:34:57.139281
10253 17:34:57.139433 jumping to kernel
10254 17:34:57.139858 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10255 17:34:57.139958 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10256 17:34:57.140031 Setting prompt string to ['Linux version [0-9]']
10257 17:34:57.140098 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10258 17:34:57.140162 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10259 17:34:57.222334
10260 17:34:57.225377 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10261 17:34:57.228678 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10262 17:34:57.228792 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10263 17:34:57.228878 Setting prompt string to []
10264 17:34:57.228973 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10265 17:34:57.229062 Using line separator: #'\n'#
10266 17:34:57.229134 No login prompt set.
10267 17:34:57.229215 Parsing kernel messages
10268 17:34:57.229285 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10269 17:34:57.229406 [login-action] Waiting for messages, (timeout 00:04:01)
10270 17:34:57.248256 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j44859-arm64-gcc-10-defconfig-arm64-chromebook-gptb4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023
10271 17:34:57.251372 [ 0.000000] random: crng init done
10272 17:34:57.258393 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10273 17:34:57.258475 [ 0.000000] efi: UEFI not found.
10274 17:34:57.268264 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10275 17:34:57.274722 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10276 17:34:57.284711 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10277 17:34:57.295086 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10278 17:34:57.301431 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10279 17:34:57.307552 [ 0.000000] printk: bootconsole [mtk8250] enabled
10280 17:34:57.311543 [ 0.000000] NUMA: No NUMA configuration found
10281 17:34:57.321214 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10282 17:34:57.324389 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10283 17:34:57.327572 [ 0.000000] Zone ranges:
10284 17:34:57.334678 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10285 17:34:57.337840 [ 0.000000] DMA32 empty
10286 17:34:57.344145 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10287 17:34:57.347885 [ 0.000000] Movable zone start for each node
10288 17:34:57.351118 [ 0.000000] Early memory node ranges
10289 17:34:57.357681 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10290 17:34:57.364146 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10291 17:34:57.370605 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10292 17:34:57.377711 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10293 17:34:57.380700 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10294 17:34:57.390752 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10295 17:34:57.445854 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10296 17:34:57.452228 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10297 17:34:57.458609 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10298 17:34:57.461857 [ 0.000000] psci: probing for conduit method from DT.
10299 17:34:57.468906 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10300 17:34:57.472277 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10301 17:34:57.478514 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10302 17:34:57.482276 [ 0.000000] psci: SMC Calling Convention v1.2
10303 17:34:57.488681 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10304 17:34:57.491899 [ 0.000000] Detected VIPT I-cache on CPU0
10305 17:34:57.498434 [ 0.000000] CPU features: detected: GIC system register CPU interface
10306 17:34:57.505335 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10307 17:34:57.511795 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10308 17:34:57.518072 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10309 17:34:57.528282 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10310 17:34:57.534854 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10311 17:34:57.537877 [ 0.000000] alternatives: applying boot alternatives
10312 17:34:57.544449 [ 0.000000] Fallback order for Node 0: 0
10313 17:34:57.551388 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10314 17:34:57.554510 [ 0.000000] Policy zone: Normal
10315 17:34:57.567399 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10316 17:34:57.577200 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10317 17:34:57.590307 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10318 17:34:57.600072 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10319 17:34:57.606324 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10320 17:34:57.609475 <6>[ 0.000000] software IO TLB: area num 8.
10321 17:34:57.666987 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10322 17:34:57.815568 <6>[ 0.000000] Memory: 7948604K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 404164K reserved, 32768K cma-reserved)
10323 17:34:57.822418 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10324 17:34:57.829301 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10325 17:34:57.832522 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10326 17:34:57.839162 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10327 17:34:57.845526 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10328 17:34:57.848865 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10329 17:34:57.858752 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10330 17:34:57.865373 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10331 17:34:57.871855 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10332 17:34:57.878744 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10333 17:34:57.881885 <6>[ 0.000000] GICv3: 608 SPIs implemented
10334 17:34:57.885680 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10335 17:34:57.892215 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10336 17:34:57.895480 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10337 17:34:57.902028 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10338 17:34:57.915526 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10339 17:34:57.925329 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10340 17:34:57.934867 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10341 17:34:57.941919 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10342 17:34:57.955654 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10343 17:34:57.962346 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10344 17:34:57.968782 <6>[ 0.009180] Console: colour dummy device 80x25
10345 17:34:57.978425 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10346 17:34:57.984878 <6>[ 0.024442] pid_max: default: 32768 minimum: 301
10347 17:34:57.988730 <6>[ 0.029343] LSM: Security Framework initializing
10348 17:34:57.994869 <6>[ 0.034280] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10349 17:34:58.004989 <6>[ 0.042142] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10350 17:34:58.014853 <6>[ 0.051555] cblist_init_generic: Setting adjustable number of callback queues.
10351 17:34:58.021268 <6>[ 0.059044] cblist_init_generic: Setting shift to 3 and lim to 1.
10352 17:34:58.027753 <6>[ 0.065423] cblist_init_generic: Setting adjustable number of callback queues.
10353 17:34:58.034291 <6>[ 0.072849] cblist_init_generic: Setting shift to 3 and lim to 1.
10354 17:34:58.038146 <6>[ 0.079248] rcu: Hierarchical SRCU implementation.
10355 17:34:58.044651 <6>[ 0.084264] rcu: Max phase no-delay instances is 1000.
10356 17:34:58.051279 <6>[ 0.091323] EFI services will not be available.
10357 17:34:58.054278 <6>[ 0.096280] smp: Bringing up secondary CPUs ...
10358 17:34:58.063175 <6>[ 0.101329] Detected VIPT I-cache on CPU1
10359 17:34:58.069859 <6>[ 0.101398] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10360 17:34:58.076387 <6>[ 0.101428] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10361 17:34:58.079715 <6>[ 0.101761] Detected VIPT I-cache on CPU2
10362 17:34:58.089172 <6>[ 0.101811] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10363 17:34:58.095811 <6>[ 0.101826] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10364 17:34:58.098977 <6>[ 0.102080] Detected VIPT I-cache on CPU3
10365 17:34:58.105852 <6>[ 0.102125] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10366 17:34:58.112726 <6>[ 0.102139] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10367 17:34:58.116384 <6>[ 0.102443] CPU features: detected: Spectre-v4
10368 17:34:58.122786 <6>[ 0.102448] CPU features: detected: Spectre-BHB
10369 17:34:58.126172 <6>[ 0.102453] Detected PIPT I-cache on CPU4
10370 17:34:58.132671 <6>[ 0.102511] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10371 17:34:58.139164 <6>[ 0.102528] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10372 17:34:58.145666 <6>[ 0.102822] Detected PIPT I-cache on CPU5
10373 17:34:58.152284 <6>[ 0.102885] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10374 17:34:58.159237 <6>[ 0.102901] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10375 17:34:58.162659 <6>[ 0.103184] Detected PIPT I-cache on CPU6
10376 17:34:58.169104 <6>[ 0.103250] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10377 17:34:58.175724 <6>[ 0.103266] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10378 17:34:58.182464 <6>[ 0.103562] Detected PIPT I-cache on CPU7
10379 17:34:58.189340 <6>[ 0.103627] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10380 17:34:58.195829 <6>[ 0.103644] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10381 17:34:58.198975 <6>[ 0.103692] smp: Brought up 1 node, 8 CPUs
10382 17:34:58.205441 <6>[ 0.245021] SMP: Total of 8 processors activated.
10383 17:34:58.209387 <6>[ 0.249942] CPU features: detected: 32-bit EL0 Support
10384 17:34:58.219098 <6>[ 0.255337] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10385 17:34:58.225381 <6>[ 0.264137] CPU features: detected: Common not Private translations
10386 17:34:58.228585 <6>[ 0.270613] CPU features: detected: CRC32 instructions
10387 17:34:58.235196 <6>[ 0.275964] CPU features: detected: RCpc load-acquire (LDAPR)
10388 17:34:58.242372 <6>[ 0.281925] CPU features: detected: LSE atomic instructions
10389 17:34:58.248852 <6>[ 0.287706] CPU features: detected: Privileged Access Never
10390 17:34:58.251974 <6>[ 0.293486] CPU features: detected: RAS Extension Support
10391 17:34:58.261675 <6>[ 0.299095] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10392 17:34:58.265222 <6>[ 0.306360] CPU: All CPU(s) started at EL2
10393 17:34:58.272038 <6>[ 0.310704] alternatives: applying system-wide alternatives
10394 17:34:58.281007 <6>[ 0.321411] devtmpfs: initialized
10395 17:34:58.292803 <6>[ 0.330211] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10396 17:34:58.303061 <6>[ 0.340171] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10397 17:34:58.309727 <6>[ 0.348190] pinctrl core: initialized pinctrl subsystem
10398 17:34:58.312599 <6>[ 0.354859] DMI not present or invalid.
10399 17:34:58.319632 <6>[ 0.359269] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10400 17:34:58.329651 <6>[ 0.366121] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10401 17:34:58.336475 <6>[ 0.373705] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10402 17:34:58.346216 <6>[ 0.381917] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10403 17:34:58.349567 <6>[ 0.390162] audit: initializing netlink subsys (disabled)
10404 17:34:58.359449 <5>[ 0.395855] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10405 17:34:58.365694 <6>[ 0.396558] thermal_sys: Registered thermal governor 'step_wise'
10406 17:34:58.372851 <6>[ 0.403824] thermal_sys: Registered thermal governor 'power_allocator'
10407 17:34:58.375917 <6>[ 0.410079] cpuidle: using governor menu
10408 17:34:58.379100 <6>[ 0.421041] NET: Registered PF_QIPCRTR protocol family
10409 17:34:58.389580 <6>[ 0.426523] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10410 17:34:58.392726 <6>[ 0.433630] ASID allocator initialised with 32768 entries
10411 17:34:58.399744 <6>[ 0.440200] Serial: AMBA PL011 UART driver
10412 17:34:58.408175 <4>[ 0.448979] Trying to register duplicate clock ID: 134
10413 17:34:58.462216 <6>[ 0.506015] KASLR enabled
10414 17:34:58.476666 <6>[ 0.513666] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10415 17:34:58.482852 <6>[ 0.520679] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10416 17:34:58.489309 <6>[ 0.527166] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10417 17:34:58.496511 <6>[ 0.534171] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10418 17:34:58.503027 <6>[ 0.540658] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10419 17:34:58.509473 <6>[ 0.547662] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10420 17:34:58.516054 <6>[ 0.554150] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10421 17:34:58.522623 <6>[ 0.561153] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10422 17:34:58.525897 <6>[ 0.568608] ACPI: Interpreter disabled.
10423 17:34:58.534621 <6>[ 0.575057] iommu: Default domain type: Translated
10424 17:34:58.541140 <6>[ 0.580168] iommu: DMA domain TLB invalidation policy: strict mode
10425 17:34:58.544135 <5>[ 0.586833] SCSI subsystem initialized
10426 17:34:58.551161 <6>[ 0.591094] usbcore: registered new interface driver usbfs
10427 17:34:58.557772 <6>[ 0.596824] usbcore: registered new interface driver hub
10428 17:34:58.560983 <6>[ 0.602378] usbcore: registered new device driver usb
10429 17:34:58.568025 <6>[ 0.608496] pps_core: LinuxPPS API ver. 1 registered
10430 17:34:58.577740 <6>[ 0.613689] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10431 17:34:58.581023 <6>[ 0.623033] PTP clock support registered
10432 17:34:58.584730 <6>[ 0.627276] EDAC MC: Ver: 3.0.0
10433 17:34:58.592031 <6>[ 0.632455] FPGA manager framework
10434 17:34:58.595164 <6>[ 0.636131] Advanced Linux Sound Architecture Driver Initialized.
10435 17:34:58.598990 <6>[ 0.642892] vgaarb: loaded
10436 17:34:58.605494 <6>[ 0.646065] clocksource: Switched to clocksource arch_sys_counter
10437 17:34:58.612534 <5>[ 0.652521] VFS: Disk quotas dquot_6.6.0
10438 17:34:58.619159 <6>[ 0.656708] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10439 17:34:58.622353 <6>[ 0.663896] pnp: PnP ACPI: disabled
10440 17:34:58.630154 <6>[ 0.670548] NET: Registered PF_INET protocol family
10441 17:34:58.636508 <6>[ 0.675831] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10442 17:34:58.651116 <6>[ 0.688120] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10443 17:34:58.661046 <6>[ 0.696935] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10444 17:34:58.667537 <6>[ 0.704904] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10445 17:34:58.674031 <6>[ 0.713602] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10446 17:34:58.686316 <6>[ 0.723351] TCP: Hash tables configured (established 65536 bind 65536)
10447 17:34:58.692401 <6>[ 0.730218] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10448 17:34:58.699391 <6>[ 0.737417] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10449 17:34:58.705734 <6>[ 0.745121] NET: Registered PF_UNIX/PF_LOCAL protocol family
10450 17:34:58.712280 <6>[ 0.751293] RPC: Registered named UNIX socket transport module.
10451 17:34:58.715836 <6>[ 0.757445] RPC: Registered udp transport module.
10452 17:34:58.722193 <6>[ 0.762376] RPC: Registered tcp transport module.
10453 17:34:58.728717 <6>[ 0.767309] RPC: Registered tcp NFSv4.1 backchannel transport module.
10454 17:34:58.732126 <6>[ 0.773978] PCI: CLS 0 bytes, default 64
10455 17:34:58.735354 <6>[ 0.778384] Unpacking initramfs...
10456 17:34:58.760956 <6>[ 0.798182] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10457 17:34:58.770975 <6>[ 0.806853] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10458 17:34:58.774453 <6>[ 0.815734] kvm [1]: IPA Size Limit: 40 bits
10459 17:34:58.780955 <6>[ 0.820264] kvm [1]: GICv3: no GICV resource entry
10460 17:34:58.784209 <6>[ 0.825288] kvm [1]: disabling GICv2 emulation
10461 17:34:58.790949 <6>[ 0.829975] kvm [1]: GIC system register CPU interface enabled
10462 17:34:58.793983 <6>[ 0.836141] kvm [1]: vgic interrupt IRQ18
10463 17:34:58.800967 <6>[ 0.840507] kvm [1]: VHE mode initialized successfully
10464 17:34:58.807544 <5>[ 0.846925] Initialise system trusted keyrings
10465 17:34:58.813725 <6>[ 0.851745] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10466 17:34:58.821274 <6>[ 0.861596] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10467 17:34:58.827962 <5>[ 0.867953] NFS: Registering the id_resolver key type
10468 17:34:58.831167 <5>[ 0.873251] Key type id_resolver registered
10469 17:34:58.837853 <5>[ 0.877666] Key type id_legacy registered
10470 17:34:58.844223 <6>[ 0.881938] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10471 17:34:58.850712 <6>[ 0.888860] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10472 17:34:58.857183 <6>[ 0.896553] 9p: Installing v9fs 9p2000 file system support
10473 17:34:58.893302 <5>[ 0.933925] Key type asymmetric registered
10474 17:34:58.896578 <5>[ 0.938253] Asymmetric key parser 'x509' registered
10475 17:34:58.906345 <6>[ 0.943385] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10476 17:34:58.910156 <6>[ 0.950999] io scheduler mq-deadline registered
10477 17:34:58.912837 <6>[ 0.955774] io scheduler kyber registered
10478 17:34:58.931550 <6>[ 0.972550] EINJ: ACPI disabled.
10479 17:34:58.963991 <4>[ 0.998074] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 17:34:58.973633 <4>[ 1.008687] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10481 17:34:58.988088 <6>[ 1.028996] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10482 17:34:58.996556 <6>[ 1.036900] printk: console [ttyS0] disabled
10483 17:34:59.024046 <6>[ 1.061546] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10484 17:34:59.030676 <6>[ 1.071016] printk: console [ttyS0] enabled
10485 17:34:59.033972 <6>[ 1.071016] printk: console [ttyS0] enabled
10486 17:34:59.040960 <6>[ 1.079909] printk: bootconsole [mtk8250] disabled
10487 17:34:59.044184 <6>[ 1.079909] printk: bootconsole [mtk8250] disabled
10488 17:34:59.050675 <6>[ 1.090939] SuperH (H)SCI(F) driver initialized
10489 17:34:59.054052 <6>[ 1.096203] msm_serial: driver initialized
10490 17:34:59.067978 <6>[ 1.105066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10491 17:34:59.077472 <6>[ 1.113610] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10492 17:34:59.084408 <6>[ 1.122152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10493 17:34:59.094176 <6>[ 1.130779] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10494 17:34:59.100739 <6>[ 1.139485] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10495 17:34:59.111158 <6>[ 1.148198] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10496 17:34:59.120613 <6>[ 1.156739] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10497 17:34:59.127122 <6>[ 1.165536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10498 17:34:59.137400 <6>[ 1.174092] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10499 17:34:59.148450 <6>[ 1.189451] loop: module loaded
10500 17:34:59.155540 <6>[ 1.195402] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10501 17:34:59.177520 <4>[ 1.218525] mtk-pmic-keys: Failed to locate of_node [id: -1]
10502 17:34:59.184647 <6>[ 1.225254] megasas: 07.719.03.00-rc1
10503 17:34:59.194371 <6>[ 1.234985] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10504 17:34:59.201055 <6>[ 1.241438] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10505 17:34:59.217361 <6>[ 1.258032] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10506 17:34:59.273867 <6>[ 1.308268] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10507 17:34:59.649638 <6>[ 1.690233] Freeing initrd memory: 20884K
10508 17:34:59.665191 <6>[ 1.705908] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10509 17:34:59.676142 <6>[ 1.716779] tun: Universal TUN/TAP device driver, 1.6
10510 17:34:59.679261 <6>[ 1.722842] thunder_xcv, ver 1.0
10511 17:34:59.682386 <6>[ 1.726350] thunder_bgx, ver 1.0
10512 17:34:59.686363 <6>[ 1.729839] nicpf, ver 1.0
10513 17:34:59.696542 <6>[ 1.733855] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10514 17:34:59.700010 <6>[ 1.741332] hns3: Copyright (c) 2017 Huawei Corporation.
10515 17:34:59.703503 <6>[ 1.746918] hclge is initializing
10516 17:34:59.710142 <6>[ 1.750493] e1000: Intel(R) PRO/1000 Network Driver
10517 17:34:59.716836 <6>[ 1.755622] e1000: Copyright (c) 1999-2006 Intel Corporation.
10518 17:34:59.719879 <6>[ 1.761636] e1000e: Intel(R) PRO/1000 Network Driver
10519 17:34:59.726494 <6>[ 1.766852] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10520 17:34:59.732951 <6>[ 1.773037] igb: Intel(R) Gigabit Ethernet Network Driver
10521 17:34:59.740114 <6>[ 1.778686] igb: Copyright (c) 2007-2014 Intel Corporation.
10522 17:34:59.746380 <6>[ 1.784521] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10523 17:34:59.749838 <6>[ 1.791038] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10524 17:34:59.756606 <6>[ 1.797502] sky2: driver version 1.30
10525 17:34:59.763551 <6>[ 1.802502] VFIO - User Level meta-driver version: 0.3
10526 17:34:59.769984 <6>[ 1.810721] usbcore: registered new interface driver usb-storage
10527 17:34:59.776268 <6>[ 1.817166] usbcore: registered new device driver onboard-usb-hub
10528 17:34:59.785318 <6>[ 1.826298] mt6397-rtc mt6359-rtc: registered as rtc0
10529 17:34:59.795762 <6>[ 1.831765] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-13T17:33:32 UTC (1694626412)
10530 17:34:59.798908 <6>[ 1.841325] i2c_dev: i2c /dev entries driver
10531 17:34:59.815686 <6>[ 1.853071] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10532 17:34:59.835380 <6>[ 1.876058] cpu cpu0: EM: created perf domain
10533 17:34:59.838424 <6>[ 1.881006] cpu cpu4: EM: created perf domain
10534 17:34:59.846002 <6>[ 1.886641] sdhci: Secure Digital Host Controller Interface driver
10535 17:34:59.852383 <6>[ 1.893072] sdhci: Copyright(c) Pierre Ossman
10536 17:34:59.859180 <6>[ 1.898026] Synopsys Designware Multimedia Card Interface Driver
10537 17:34:59.865851 <6>[ 1.904660] sdhci-pltfm: SDHCI platform and OF driver helper
10538 17:34:59.869454 <6>[ 1.904796] mmc0: CQHCI version 5.10
10539 17:34:59.875823 <6>[ 1.914626] ledtrig-cpu: registered to indicate activity on CPUs
10540 17:34:59.882517 <6>[ 1.921689] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10541 17:34:59.889479 <6>[ 1.928730] usbcore: registered new interface driver usbhid
10542 17:34:59.892576 <6>[ 1.934554] usbhid: USB HID core driver
10543 17:34:59.898994 <6>[ 1.938764] spi_master spi0: will run message pump with realtime priority
10544 17:34:59.942423 <6>[ 1.976239] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10545 17:34:59.961437 <6>[ 1.992068] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10546 17:34:59.965277 <6>[ 2.005674] mmc0: Command Queue Engine enabled
10547 17:34:59.971649 <6>[ 2.010453] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10548 17:34:59.978545 <6>[ 2.017388] cros-ec-spi spi0.0: Chrome EC device registered
10549 17:34:59.982144 <6>[ 2.017715] mmcblk0: mmc0:0001 DA4128 116 GiB
10550 17:34:59.992766 <6>[ 2.033651] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10551 17:35:00.000500 <6>[ 2.041143] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10552 17:35:00.007160 <6>[ 2.047147] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10553 17:35:00.013584 <6>[ 2.053186] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10554 17:35:00.024021 <6>[ 2.057665] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10555 17:35:00.030480 <6>[ 2.070325] NET: Registered PF_PACKET protocol family
10556 17:35:00.033884 <6>[ 2.075720] 9pnet: Installing 9P2000 support
10557 17:35:00.040355 <5>[ 2.080287] Key type dns_resolver registered
10558 17:35:00.043558 <6>[ 2.085297] registered taskstats version 1
10559 17:35:00.050038 <5>[ 2.089680] Loading compiled-in X.509 certificates
10560 17:35:00.079323 <4>[ 2.113104] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 17:35:00.089182 <4>[ 2.123875] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 17:35:00.095554 <3>[ 2.134470] debugfs: File 'uA_load' in directory '/' already present!
10563 17:35:00.102496 <3>[ 2.141186] debugfs: File 'min_uV' in directory '/' already present!
10564 17:35:00.108892 <3>[ 2.147799] debugfs: File 'max_uV' in directory '/' already present!
10565 17:35:00.115904 <3>[ 2.154409] debugfs: File 'constraint_flags' in directory '/' already present!
10566 17:35:00.127025 <3>[ 2.164434] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10567 17:35:00.139543 <6>[ 2.180192] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10568 17:35:00.146596 <6>[ 2.187030] xhci-mtk 11200000.usb: xHCI Host Controller
10569 17:35:00.153043 <6>[ 2.192550] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10570 17:35:00.163225 <6>[ 2.200403] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10571 17:35:00.169603 <6>[ 2.209833] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10572 17:35:00.176555 <6>[ 2.215908] xhci-mtk 11200000.usb: xHCI Host Controller
10573 17:35:00.183067 <6>[ 2.221385] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10574 17:35:00.189945 <6>[ 2.229034] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10575 17:35:00.196444 <6>[ 2.236666] hub 1-0:1.0: USB hub found
10576 17:35:00.199420 <6>[ 2.240678] hub 1-0:1.0: 1 port detected
10577 17:35:00.206314 <6>[ 2.244941] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10578 17:35:00.213051 <6>[ 2.253443] hub 2-0:1.0: USB hub found
10579 17:35:00.216029 <6>[ 2.257448] hub 2-0:1.0: 1 port detected
10580 17:35:00.223244 <6>[ 2.264318] mtk-msdc 11f70000.mmc: Got CD GPIO
10581 17:35:00.234087 <6>[ 2.271672] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10582 17:35:00.241102 <6>[ 2.279697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10583 17:35:00.250596 <4>[ 2.287607] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10584 17:35:00.260979 <6>[ 2.297139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10585 17:35:00.267274 <6>[ 2.305220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10586 17:35:00.273699 <6>[ 2.313381] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10587 17:35:00.284017 <6>[ 2.321390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10588 17:35:00.290507 <6>[ 2.329219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10589 17:35:00.300260 <6>[ 2.337056] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10590 17:35:00.310130 <6>[ 2.347483] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10591 17:35:00.317091 <6>[ 2.355872] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10592 17:35:00.326777 <6>[ 2.364215] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10593 17:35:00.333967 <6>[ 2.372569] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10594 17:35:00.343954 <6>[ 2.380907] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10595 17:35:00.350472 <6>[ 2.389258] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10596 17:35:00.360569 <6>[ 2.397597] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10597 17:35:00.367043 <6>[ 2.405945] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10598 17:35:00.377151 <6>[ 2.414284] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10599 17:35:00.383586 <6>[ 2.422632] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10600 17:35:00.393303 <6>[ 2.430971] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10601 17:35:00.403616 <6>[ 2.439308] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10602 17:35:00.410099 <6>[ 2.447647] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10603 17:35:00.420170 <6>[ 2.455984] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10604 17:35:00.426834 <6>[ 2.464321] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10605 17:35:00.433518 <6>[ 2.473058] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10606 17:35:00.440139 <6>[ 2.480255] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10607 17:35:00.446418 <6>[ 2.487014] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10608 17:35:00.453201 <6>[ 2.493769] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10609 17:35:00.460177 <6>[ 2.500707] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10610 17:35:00.470325 <6>[ 2.507555] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10611 17:35:00.479968 <6>[ 2.516685] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10612 17:35:00.489584 <6>[ 2.525805] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10613 17:35:00.499922 <6>[ 2.535118] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10614 17:35:00.509641 <6>[ 2.544590] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10615 17:35:00.516152 <6>[ 2.554061] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10616 17:35:00.526375 <6>[ 2.563181] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10617 17:35:00.536100 <6>[ 2.572647] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10618 17:35:00.546122 <6>[ 2.581766] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10619 17:35:00.556335 <6>[ 2.591061] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10620 17:35:00.565658 <6>[ 2.601221] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10621 17:35:00.575731 <6>[ 2.612785] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10622 17:35:00.605298 <6>[ 2.642577] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10623 17:35:00.633145 <6>[ 2.673821] hub 2-1:1.0: USB hub found
10624 17:35:00.636335 <6>[ 2.678303] hub 2-1:1.0: 3 ports detected
10625 17:35:00.756658 <6>[ 2.794267] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10626 17:35:00.911608 <6>[ 2.952745] hub 1-1:1.0: USB hub found
10627 17:35:00.914806 <6>[ 2.957252] hub 1-1:1.0: 4 ports detected
10628 17:35:00.988975 <6>[ 3.026669] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10629 17:35:01.236736 <6>[ 3.274385] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10630 17:35:01.369362 <6>[ 3.410388] hub 1-1.4:1.0: USB hub found
10631 17:35:01.372521 <6>[ 3.415066] hub 1-1.4:1.0: 2 ports detected
10632 17:35:01.668886 <6>[ 3.706368] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10633 17:35:01.860431 <6>[ 3.898367] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10634 17:35:12.849669 <6>[ 14.895347] ALSA device list:
10635 17:35:12.856325 <6>[ 14.898640] No soundcards found.
10636 17:35:12.864315 <6>[ 14.906545] Freeing unused kernel memory: 8384K
10637 17:35:12.867426 <6>[ 14.911529] Run /init as init process
10638 17:35:12.902353 Starting syslogd: OK
10639 17:35:12.906383 Starting klogd: OK
10640 17:35:12.916006 Running sysctl: OK
10641 17:35:12.925807 Populating /dev using udev: <30>[ 14.967451] udevd[195]: starting version 3.2.9
10642 17:35:12.933234 <27>[ 14.975197] udevd[195]: specified user 'tss' unknown
10643 17:35:12.939543 <27>[ 14.980562] udevd[195]: specified group 'tss' unknown
10644 17:35:12.942793 <30>[ 14.987120] udevd[196]: starting eudev-3.2.9
10645 17:35:12.982446 <27>[ 15.024678] udevd[196]: specified user 'tss' unknown
10646 17:35:12.989094 <27>[ 15.030098] udevd[196]: specified group 'tss' unknown
10647 17:35:13.118086 <6>[ 15.157261] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10648 17:35:13.129432 <6>[ 15.168620] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10649 17:35:13.133095 <6>[ 15.169159] remoteproc remoteproc0: scp is available
10650 17:35:13.142801 <6>[ 15.176246] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10651 17:35:13.149675 <6>[ 15.181659] remoteproc remoteproc0: powering up scp
10652 17:35:13.156240 <6>[ 15.190171] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10653 17:35:13.169708 <6>[ 15.208644] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10654 17:35:13.176353 <6>[ 15.217176] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10655 17:35:13.195780 <4>[ 15.234404] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10656 17:35:13.202443 <3>[ 15.239459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 17:35:13.209306 <4>[ 15.246631] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10658 17:35:13.218534 <3>[ 15.250470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 17:35:13.225420 <3>[ 15.265315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 17:35:13.232266 <6>[ 15.265700] mc: Linux media interface: v0.10
10661 17:35:13.238332 <3>[ 15.273539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 17:35:13.245448 <6>[ 15.275992] usbcore: registered new interface driver r8152
10663 17:35:13.251528 <6>[ 15.279420] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10664 17:35:13.261864 <3>[ 15.286018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 17:35:13.268592 <3>[ 15.286023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 17:35:13.274954 <3>[ 15.286031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 17:35:13.285238 <3>[ 15.286035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 17:35:13.292002 <3>[ 15.286126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 17:35:13.302084 <4>[ 15.308473] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10670 17:35:13.305514 <4>[ 15.308473] Fallback method does not support PEC.
10671 17:35:13.312221 <6>[ 15.311925] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10672 17:35:13.318825 <6>[ 15.311974] pci_bus 0000:00: root bus resource [bus 00-ff]
10673 17:35:13.326002 <6>[ 15.311997] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10674 17:35:13.336985 <6>[ 15.312008] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10675 17:35:13.342981 <6>[ 15.312075] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10676 17:35:13.349903 <6>[ 15.312110] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10677 17:35:13.353094 <6>[ 15.312257] pci 0000:00:00.0: supports D1 D2
10678 17:35:13.359902 <6>[ 15.312264] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10679 17:35:13.369729 <6>[ 15.314841] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10680 17:35:13.376556 <6>[ 15.315325] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10681 17:35:13.383174 <6>[ 15.315359] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10682 17:35:13.389531 <6>[ 15.315381] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10683 17:35:13.396235 <6>[ 15.315400] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10684 17:35:13.403420 <6>[ 15.315528] pci 0000:01:00.0: supports D1 D2
10685 17:35:13.409604 <6>[ 15.315531] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10686 17:35:13.416442 <3>[ 15.315657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 17:35:13.423311 <6>[ 15.325711] videodev: Linux video capture interface: v2.00
10688 17:35:13.429735 <6>[ 15.326269] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10689 17:35:13.439613 <6>[ 15.326346] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10690 17:35:13.446000 <6>[ 15.326353] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10691 17:35:13.452773 <6>[ 15.326368] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10692 17:35:13.462841 <6>[ 15.326384] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10693 17:35:13.469334 <6>[ 15.326400] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10694 17:35:13.476124 <6>[ 15.326417] pci 0000:00:00.0: PCI bridge to [bus 01]
10695 17:35:13.482297 <6>[ 15.326426] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10696 17:35:13.488925 <6>[ 15.326639] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10697 17:35:13.495461 <6>[ 15.327964] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10698 17:35:13.502058 <6>[ 15.329322] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10699 17:35:13.508885 <3>[ 15.331787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 17:35:13.518903 <3>[ 15.331792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 17:35:13.525682 <3>[ 15.331821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 17:35:13.535728 <6>[ 15.348174] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10703 17:35:13.541866 <6>[ 15.348202] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10704 17:35:13.548462 <3>[ 15.353517] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 17:35:13.558316 <3>[ 15.353522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 17:35:13.565579 <3>[ 15.353527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 17:35:13.575459 <3>[ 15.354097] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10708 17:35:13.581727 <6>[ 15.354378] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10709 17:35:13.588796 <6>[ 15.360426] remoteproc remoteproc0: remote processor scp is now up
10710 17:35:13.595143 <3>[ 15.366125] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 17:35:13.605289 <3>[ 15.366165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 17:35:13.615156 <6>[ 15.372966] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10713 17:35:13.621383 <3>[ 15.376549] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 17:35:13.631743 <4>[ 15.377155] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10715 17:35:13.638343 <4>[ 15.377165] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10716 17:35:13.648392 <6>[ 15.384466] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10717 17:35:13.658187 <6>[ 15.390809] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10718 17:35:13.664739 <3>[ 15.606258] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: rpmsg send timeout
10719 17:35:13.674863 <6>[ 15.614000] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10720 17:35:13.681475 <6>[ 15.625758] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10721 17:35:13.687608 <6>[ 15.626222] r8152 2-1.3:1.0 eth0: v1.12.13
10722 17:35:13.694902 <5>[ 15.654683] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10723 17:35:13.697866 <6>[ 15.711258] Bluetooth: Core ver 2.22
10724 17:35:13.704752 <6>[ 15.716490] usbcore: registered new interface driver cdc_ether
10725 17:35:13.711285 <6>[ 15.721779] NET: Registered PF_BLUETOOTH protocol family
10726 17:35:13.717901 <6>[ 15.734897] usbcore: registered new interface driver r8153_ecm
10727 17:35:13.724402 <6>[ 15.735806] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10728 17:35:13.737626 <6>[ 15.737251] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10729 17:35:13.740959 <6>[ 15.737350] usbcore: registered new interface driver uvcvideo
10730 17:35:13.747598 <6>[ 15.742311] Bluetooth: HCI device and connection manager initialized
10731 17:35:13.754228 <5>[ 15.747820] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10732 17:35:13.760961 <6>[ 15.752293] Bluetooth: HCI socket layer initialized
10733 17:35:13.767359 <6>[ 15.753131] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10734 17:35:13.777197 <4>[ 15.757939] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10735 17:35:13.780640 <6>[ 15.763954] Bluetooth: L2CAP socket layer initialized
10736 17:35:13.787356 <6>[ 15.763973] Bluetooth: SCO socket layer initialized
10737 17:35:13.790521 <6>[ 15.824051] usbcore: registered new interface driver btusb
10738 17:35:13.803766 <4>[ 15.824928] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10739 17:35:13.810334 <3>[ 15.824939] Bluetooth: hci0: Failed to load firmware file (-2)
10740 17:35:13.813614 <3>[ 15.824943] Bluetooth: hci0: Failed to set up firmware (-2)
10741 17:35:13.823756 <4>[ 15.824947] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10742 17:35:13.830249 <6>[ 15.828675] cfg80211: failed to load regulatory.db
10743 17:35:13.836809 <6>[ 15.855734] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10744 17:35:13.843260 <6>[ 15.885015] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10745 17:35:13.869063 <6>[ 15.911685] mt7921e 0000:01:00.0: ASIC revision: 79610010
10746 17:35:13.974130 <4>[ 16.009815] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 17:35:13.974297 done
10748 17:35:13.993860 Saving random seed: OK
10749 17:35:14.008937 Starting network: OK
10750 17:35:14.049966 Starting dropbear sshd: <6>[ 16.092321] NET: Registered PF_INET6 protocol family
10751 17:35:14.056709 <6>[ 16.099100] Segment Routing with IPv6
10752 17:35:14.060136 <6>[ 16.103034] In-situ OAM (IOAM) with IPv6
10753 17:35:14.063405 OK
10754 17:35:14.073340 /bin/sh: can't access tty; job control turned off
10755 17:35:14.073731 Matched prompt #10: / #
10757 17:35:14.073974 Setting prompt string to ['/ #']
10758 17:35:14.074071 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10760 17:35:14.074295 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10761 17:35:14.074401 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
10762 17:35:14.074476 Setting prompt string to ['/ #']
10763 17:35:14.074543 Forcing a shell prompt, looking for ['/ #']
10765 17:35:14.124755 / #
10766 17:35:14.124909 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10767 17:35:14.125013 Waiting using forced prompt support (timeout 00:02:30)
10768 17:35:14.125119 <4>[ 16.128759] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10769 17:35:14.129659
10770 17:35:14.129950 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10771 17:35:14.130063 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
10772 17:35:14.130183 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10773 17:35:14.130298 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
10774 17:35:14.130409 end: 2 depthcharge-action (duration 00:01:16) [common]
10775 17:35:14.130519 start: 3 lava-test-retry (timeout 00:01:00) [common]
10776 17:35:14.130625 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10777 17:35:14.130720 Using namespace: common
10779 17:35:14.231105 / # #
10780 17:35:14.231289 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10781 17:35:14.231442 #<4>[ 16.248478] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 17:35:14.236151
10783 17:35:14.236419 Using /lava-11518302
10785 17:35:14.336738 / # export SHELL=/bin/sh
10786 17:35:14.336968 export SHELL=/bin/sh<4>[ 16.368547] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 17:35:14.342837
10789 17:35:14.443327 / # . /lava-11518302/environment
10790 17:35:14.491882 . /lava-11518302/environment<4>[ 16.488946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 17:35:14.492017
10793 17:35:14.592520 / # /lava-11518302/bin/lava-test-runner /lava-11518302/0
10794 17:35:14.592669 Test shell timeout: 10s (minimum of the action and connection timeout)
10795 17:35:14.593032 /lava-11518302/bin/lava-test-runner /lava-11518302/0<4>[ 16.608896] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 17:35:14.597620
10797 17:35:14.639749 + export 'TESTRUN_ID=0_dmesg'
10798 17:35:14.639887 +<8>[ 16.665215] <LAVA_SIGNAL_STARTRUN 0_dmesg 11518302_1.5.2.3.1>
10799 17:35:14.639976 cd /lava-11518302/0/tests/0_dmesg
10800 17:35:14.640043 + cat uuid
10801 17:35:14.640290 Received signal: <STARTRUN> 0_dmesg 11518302_1.5.2.3.1
10802 17:35:14.640391 Starting test lava.0_dmesg (11518302_1.5.2.3.1)
10803 17:35:14.640504 Skipping test definition patterns.
10804 17:35:14.640605 + UUID=11518302_1.5.2.3.1
10805 17:35:14.640691 + set +x
10806 17:35:14.640753 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10807 17:35:14.644700 <8>[ 16.684858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10808 17:35:14.645020 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10810 17:35:14.666085 <8>[ 16.704936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10811 17:35:14.666363 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10813 17:35:14.694843 <4>[ 16.730761] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 17:35:14.701742 <8>[ 16.734875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10815 17:35:14.702008 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10817 17:35:14.707565 + set +x
10818 17:35:14.711020 Received signal: <ENDRUN> 0_dmesg 11518302_1.5.2.3.1
10819 17:35:14.711116 Ending use of test pattern.
10820 17:35:14.711184 Ending test lava.0_dmesg (11518302_1.5.2.3.1), duration 0.07
10822 17:35:14.713917 <8>[ 16.753582] <LAVA_SIGNAL_ENDRUN 0_dmesg 11518302_1.5.2.3.1>
10823 17:35:14.713996 <LAVA_TEST_RUNNER EXIT>
10824 17:35:14.714238 ok: lava_test_shell seems to have completed
10825 17:35:14.714340 alert: pass
crit: pass
emerg: pass
10826 17:35:14.714432 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10827 17:35:14.714534 end: 3 lava-test-retry (duration 00:00:01) [common]
10828 17:35:14.714647 start: 4 lava-test-retry (timeout 00:01:00) [common]
10829 17:35:14.714751 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10830 17:35:14.714834 Using namespace: common
10832 17:35:14.815157 /#
10833 17:35:14.815349 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10834 17:35:14.815510 # #<4>[ 16.848703] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10835 17:35:14.815794 Using /lava-11518302
10837 17:35:14.916105 export SHELL=/bin/sh
10838 17:35:14.916331
10840 17:35:15.016873 / # export SHELL=/bin/sh. /lava-11518302/environment
10841 17:35:15.017103
10842 17:35:15.017211 / # <4>[ 16.968967] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10844 17:35:15.117756 . /lava-11518302/environment/lava-11518302/bin/lava-test-runner /lava-11518302/1
10845 17:35:15.118008 Test shell timeout: 10s (minimum of the action and connection timeout)
10846 17:35:15.118204
10847 17:35:15.118316 / # <4>[ 17.088838] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 17:35:15.123390 /lava-11518302/bin/lava-test-runner /lava-11518302/1
10849 17:35:15.163743 + export 'TESTRUN_ID=1_bootrr'
10850 17:35:15.163895 <8>[ 17.189588] <LAVA_SIGNAL_STARTRUN 1_bootrr 11518302_1.5.2.3.5>
10851 17:35:15.163992 + cd /lava-11518302/1/tests/1_bootrr
10852 17:35:15.164255 Received signal: <STARTRUN> 1_bootrr 11518302_1.5.2.3.5
10853 17:35:15.164360 Starting test lava.1_bootrr (11518302_1.5.2.3.5)
10854 17:35:15.164492 Skipping test definition patterns.
10855 17:35:15.164645 + cat uuid
10856 17:35:15.164747 + UUID=11518302_1.5.2.3.5
10857 17:35:15.164854 + set +x
10858 17:35:15.165335 + export 'PATH=/opt/bootrr/libexec/bootrr<3>[ 17.208043] mt7921e 0000:01:00.0: hardware init failed
10859 17:35:15.178434 /helpers:/lava-11518302/1/../bin:/sbin:/usr/sbin<8>[ 17.217167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10860 17:35:15.178535 :/bin:/usr/bin'
10861 17:35:15.178796 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10863 17:35:15.182131 + cd /opt/bootrr/libexec/bootrr
10864 17:35:15.185115 + sh helpers/bootrr-auto
10865 17:35:15.188455 /lava-11518302/1/../bin/lava-test-case
10866 17:35:15.195538 /lava-115183<8>[ 17.236210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10867 17:35:15.195849 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10869 17:35:15.198733 02/1/../bin/lava-test-case
10870 17:35:15.201913 /usr/bin/tpm2_getcap
10871 17:35:15.236289 /lava-11518302/1/../bin/lava-test-case
10872 17:35:15.242892 <8>[ 17.283967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10873 17:35:15.243193 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10875 17:35:15.265963 /lava-11518302/1/../bin/lava-test-case
10876 17:35:15.272112 <8>[ 17.311761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10877 17:35:15.272380 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10879 17:35:15.282366 /lava-11518302/1/../bin/lava-test-case
10880 17:35:15.289047 <8>[ 17.328169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10881 17:35:15.289304 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10883 17:35:15.307925 /lava-11518302/1/../bin/lava-tes<8>[ 17.346359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10884 17:35:15.308032 t-case
10885 17:35:15.308295 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10887 17:35:15.317665 /lava-11518302/1/../bin/lava-test-case
10888 17:35:15.323802 <8>[ 17.364332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10889 17:35:15.324061 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10891 17:35:15.336179 /lava-11518302/1/../bin/lava-test-case
10892 17:35:15.342487 <8>[ 17.381871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10893 17:35:15.342806 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10895 17:35:15.358782 /lava-11518302/1/../bin/lava-tes<8>[ 17.397359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10896 17:35:15.358902 t-case
10897 17:35:15.359166 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10899 17:35:15.370310 /lava-11518302/1/../bin/lava-test-case
10900 17:35:15.377198 <8>[ 17.416303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10901 17:35:15.377452 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10903 17:35:15.385610 /lava-11518302/1/../bin/lava-test-case
10904 17:35:15.395256 <8>[ 17.432948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10905 17:35:15.395525 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10907 17:35:15.405120 /lava-11518302/1/../bin/lava-test-case
10908 17:35:15.411502 <8>[ 17.452003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10909 17:35:15.411763 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10911 17:35:15.423613 /lava-11518302/1/../bin/lava-test-case
10912 17:35:15.430476 <8>[ 17.470030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10913 17:35:15.430741 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10915 17:35:15.442436 /lava-11518302/1/../bin/lava-test-case
10916 17:35:15.452702 <8>[ 17.490132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10917 17:35:15.452998 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10919 17:35:15.462233 /lava-11518302/1/../bin/lava-test-case
10920 17:35:15.468402 <8>[ 17.508150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10921 17:35:15.468659 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10923 17:35:15.477895 /lava-11518302/1/../bin/lava-test-case
10924 17:35:15.484717 <8>[ 17.523893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10925 17:35:15.484995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10927 17:35:15.502586 /lava-11518302/1/../bin/lava-tes<8>[ 17.541348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10928 17:35:15.502695 t-case
10929 17:35:15.502967 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10931 17:35:15.511870 /lava-11518302/1/../bin/lava-test-case
10932 17:35:15.518575 <8>[ 17.558898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10933 17:35:15.518850 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10935 17:35:15.529921 /lava-11518302/1/../bin/lava-test-case
10936 17:35:15.536128 <8>[ 17.575847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10937 17:35:15.536413 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10939 17:35:15.546512 /lava-11518302/1/../bin/lava-test-case
10940 17:35:15.552997 <8>[ 17.592191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10941 17:35:15.553258 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10943 17:35:15.566857 /lava-11518302/1/../bin/lava-test-case
10944 17:35:15.573472 <8>[ 17.612077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10945 17:35:15.573728 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10947 17:35:15.582409 /lava-11518302/1/../bin/lava-test-case
10948 17:35:15.589371 <8>[ 17.628430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10949 17:35:15.589620 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10951 17:35:15.600144 /lava-11518302/1/../bin/lava-test-case
10952 17:35:15.606273 <8>[ 17.645231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10953 17:35:15.606531 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10955 17:35:15.624054 /lava-11518302/1/../bin/lava-tes<8>[ 17.662832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10956 17:35:15.624184 t-case
10957 17:35:15.624467 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10959 17:35:15.635485 /lava-11518302/1/../bin/lava-test-case
10960 17:35:15.642434 <8>[ 17.680747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10961 17:35:15.642692 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10963 17:35:15.660817 /lava-11518302/1/../bin/lava-tes<8>[ 17.699042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10964 17:35:15.660909 t-case
10965 17:35:15.661146 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10967 17:35:15.667816 /lava-11518302/1/../bin/lava-test-case
10968 17:35:15.678492 <8>[ 17.717503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10969 17:35:15.678748 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10971 17:35:15.690557 /lava-11518302/1/../bin/lava-test-case
10972 17:35:15.697263 <8>[ 17.736936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10973 17:35:15.697553 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10975 17:35:15.705924 /lava-11518302/1/../bin/lava-test-case
10976 17:35:15.712755 <8>[ 17.751474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10977 17:35:15.713016 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10979 17:35:15.722958 /lava-11518302/1/../bin/lava-test-case
10980 17:35:15.733148 <8>[ 17.772223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10981 17:35:15.733423 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10983 17:35:15.742842 /lava-11518302/1/../bin/lava-test-case
10984 17:35:15.749169 <8>[ 17.789434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10985 17:35:15.749436 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10987 17:35:15.761502 /lava-11518302/1/../bin/lava-test-case
10988 17:35:15.767876 <8>[ 17.807111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10989 17:35:15.768137 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10991 17:35:15.787207 /lava-11518302/1/../bin/lava-tes<8>[ 17.825298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10992 17:35:15.787295 t-case
10993 17:35:15.787531 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10995 17:35:15.797480 /lava-11518302/1/../bin/lava-test-case
10996 17:35:15.803775 <8>[ 17.843579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10997 17:35:15.804032 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10999 17:35:15.822925 /lava-11518302/1/../bin/lava-tes<8>[ 17.861627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11000 17:35:15.823013 t-case
11001 17:35:15.823249 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11003 17:35:15.840593 /lava-11518302/1/../bin/lava-tes<8>[ 17.879334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11004 17:35:15.840693 t-case
11005 17:35:15.840932 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11007 17:35:15.859656 /lava-11518302/1/../bin/lava-tes<8>[ 17.897876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11008 17:35:15.859750 t-case
11009 17:35:15.859988 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11011 17:35:15.877752 /lava-11518302/1/../bin/lava-tes<8>[ 17.916024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11012 17:35:15.877851 t-case
11013 17:35:15.878087 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11015 17:35:15.886116 /lava-11518302/1/../bin/lava-test-case
11016 17:35:15.892298 <8>[ 17.931949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11017 17:35:15.892597 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11019 17:35:15.904909 /lava-11518302/1/../bin/lava-test-case
11020 17:35:15.911453 <8>[ 17.950235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11021 17:35:15.911664 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11023 17:35:15.924290 /lava-11518302/1/../bin/lava-test-case
11024 17:35:15.930845 <8>[ 17.970367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11025 17:35:15.931101 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11027 17:35:15.950171 /lava-11518302/1/../bin/lava-tes<8>[ 17.989049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11028 17:35:15.950259 t-case
11029 17:35:15.950495 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11031 17:35:15.966091 /lava-11518302/1/../bin/lava-tes<8>[ 18.004648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11032 17:35:15.966181 t-case
11033 17:35:15.966418 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11035 17:35:15.979548 /lava-11518302/1/../bin/lava-test-case
11036 17:35:15.986423 <8>[ 18.026768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11037 17:35:15.986709 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11039 17:35:16.004470 /lava-11518302/1/../bin/lava-tes<8>[ 18.042576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11040 17:35:16.004554 t-case
11041 17:35:16.004789 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11043 17:35:16.013486 /lava-11518302/1/../bin/lava-test-case
11044 17:35:16.020204 <8>[ 18.060546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11045 17:35:16.020456 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11047 17:35:16.030698 /lava-11518302/1/../bin/lava-test-case
11048 17:35:16.036926 <8>[ 18.075743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11049 17:35:16.037182 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11051 17:35:16.047977 /lava-11518302/1/../bin/lava-test-case
11052 17:35:16.054507 <8>[ 18.093913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11053 17:35:16.054759 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11055 17:35:16.063113 /lava-11518302/1/../bin/lava-test-case
11056 17:35:16.069459 <8>[ 18.107958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11057 17:35:16.069751 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11059 17:35:16.084421 /lava-11518302/1/../bin/lava-test-case
11060 17:35:16.091172 <8>[ 18.131792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11061 17:35:16.091426 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11063 17:35:16.103010 /lava-11518302/1/../bin/lava-test-case
11064 17:35:16.112732 <8>[ 18.150764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11065 17:35:16.112984 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11067 17:35:16.121134 /lava-11518302/1/../bin/lava-test-case
11068 17:35:16.127951 <8>[ 18.166653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11069 17:35:16.128205 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11071 17:35:16.146156 /lava-11518302/1/../bin/lava-tes<8>[ 18.184450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11072 17:35:16.146247 t-case
11073 17:35:16.146494 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11075 17:35:16.155107 /lava-11518302/1/../bin/lava-test-case
11076 17:35:16.161418 <8>[ 18.200430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11077 17:35:16.161670 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11079 17:35:16.176380 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11081 17:35:16.179603 /lava-11518302/1/../bin/lava-tes<8>[ 18.217954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11082 17:35:16.179718 t-case
11083 17:35:16.191806 /lava-11518302/1/../bin/lava-test-case
11084 17:35:16.198000 <8>[ 18.236989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11085 17:35:16.198287 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11087 17:35:16.215758 /lava-11518302/1/../bin/lava-tes<8>[ 18.254464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11088 17:35:16.215844 t-case
11089 17:35:16.216079 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11091 17:35:16.226958 /lava-11518302/1/../bin/lava-test-case
11092 17:35:16.233171 <8>[ 18.273763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11093 17:35:16.233452 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11095 17:35:16.246534 /lava-11518302/1/../bin/lava-test-case
11096 17:35:16.252594 <8>[ 18.292280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11097 17:35:16.252845 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11099 17:35:16.262686 /lava-11518302/1/../bin/lava-test-case
11100 17:35:16.269012 <8>[ 18.308030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11101 17:35:16.269260 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11103 17:35:16.285500 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11105 17:35:16.288009 /lava-11518302/1/../bin/lava-tes<8>[ 18.326882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11106 17:35:16.288090 t-case
11107 17:35:16.296993 /lava-11518302/1/../bin/lava-test-case
11108 17:35:16.303413 <8>[ 18.343159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11109 17:35:16.303677 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11111 17:35:16.311358 /lava-11518302/1/../bin/lava-test-case
11112 17:35:16.318303 <8>[ 18.357800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11113 17:35:16.318558 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11115 17:35:16.330450 /lava-11518302/1/../bin/lava-test-case
11116 17:35:16.336829 <8>[ 18.375984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11117 17:35:16.337083 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11119 17:35:16.345353 /lava-11518302/1/../bin/lava-test-case
11120 17:35:16.351822 <8>[ 18.391418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11121 17:35:16.352090 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11123 17:35:16.365388 /lava-11518302/1/../bin/lava-test-case
11124 17:35:16.372180 <8>[ 18.413337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11125 17:35:16.372453 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11127 17:35:16.382217 /lava-11518302/1/../bin/lava-test-case
11128 17:35:16.389194 <8>[ 18.429082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11129 17:35:16.389476 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11131 17:35:16.411236 /lava-11518302/1/../bin/lava-tes<8>[ 18.449962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11132 17:35:16.411347 t-case
11133 17:35:16.411595 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11135 17:35:16.428875 /lava-11518302/1/../bin/lava-tes<8>[ 18.467366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11136 17:35:16.428961 t-case
11137 17:35:16.429197 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11139 17:35:16.438179 /lava-11518302/1/../bin/lava-test-case
11140 17:35:16.444562 <8>[ 18.484580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11141 17:35:16.444833 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11143 17:35:16.455789 /lava-11518302/1/../bin/lava-test-case
11144 17:35:16.462764 <8>[ 18.501965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11145 17:35:16.463038 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11147 17:35:16.480981 /lava-11518302/1/../bin/lava-tes<8>[ 18.519626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11148 17:35:16.481065 t-case
11149 17:35:16.481300 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11151 17:35:16.490628 /lava-11518302/1/../bin/lava-test-case
11152 17:35:16.497592 <8>[ 18.537521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11153 17:35:16.497878 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11155 17:35:16.508733 /lava-11518302/1/../bin/lava-test-case
11156 17:35:16.515119 <8>[ 18.554478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11157 17:35:16.515372 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11159 17:35:16.526010 /lava-11518302/1/../bin/lava-test-case
11160 17:35:16.532855 <8>[ 18.571986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11161 17:35:16.533138 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11163 17:35:16.543323 /lava-11518302/1/../bin/lava-test-case
11164 17:35:16.549944 <8>[ 18.589302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11165 17:35:16.550217 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11167 17:35:16.568498 /lava-11518302/1/../bin/lava-tes<8>[ 18.606937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11168 17:35:16.568581 t-case
11169 17:35:16.568814 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11171 17:35:16.577211 /lava-11518302/1/../bin/lava-test-case
11172 17:35:16.584105 <8>[ 18.625393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11173 17:35:16.584355 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11175 17:35:16.598158 /lava-11518302/1/../bin/lava-test-case
11176 17:35:16.604419 <8>[ 18.643965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11177 17:35:16.604701 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11179 17:35:16.622769 /lava-11518302/1/../bin/lava-tes<8>[ 18.661785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11180 17:35:16.622867 t-case
11181 17:35:16.623105 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11183 17:35:16.634016 /lava-11518302/1/../bin/lava-test-case
11184 17:35:16.640250 <8>[ 18.679208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11185 17:35:16.640533 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11187 17:35:16.651435 /lava-11518302/1/../bin/lava-test-case
11188 17:35:16.658178 <8>[ 18.697532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11189 17:35:16.658451 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11191 17:35:16.668880 /lava-11518302/1/../bin/lava-test-case
11192 17:35:16.675738 <8>[ 18.716633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11193 17:35:16.675997 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11195 17:35:16.687312 /lava-11518302/1/../bin/lava-test-case
11196 17:35:16.694248 <8>[ 18.733635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11197 17:35:16.694505 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11199 17:35:16.701914 /lava-11518302/1/../bin/lava-test-case
11200 17:35:16.712280 <8>[ 18.751457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11201 17:35:16.712538 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11203 17:35:16.723341 /lava-11518302/1/../bin/lava-test-case
11204 17:35:16.729775 <8>[ 18.769276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11205 17:35:16.730034 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11207 17:35:16.738799 /lava-11518302/1/../bin/lava-test-case
11208 17:35:16.745287 <8>[ 18.784287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11209 17:35:16.745544 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11211 17:35:16.759442 /lava-11518302/1/../bin/lava-test-case
11212 17:35:16.765812 <8>[ 18.806317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11213 17:35:16.766069 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11215 17:35:16.775305 /lava-11518302/1/../bin/lava-test-case
11216 17:35:16.782111 <8>[ 18.820715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11217 17:35:16.782361 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11219 17:35:16.797404 /lava-11518302/1/../bin/lava-test-case
11220 17:35:16.804250 <8>[ 18.842981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11221 17:35:16.804499 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11223 17:35:16.814064 /lava-11518302/1/../bin/lava-test-case
11224 17:35:16.820974 <8>[ 18.860215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11225 17:35:16.821225 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11227 17:35:16.834609 /lava-11518302/1/../bin/lava-test-case
11228 17:35:16.841521 <8>[ 18.880183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11229 17:35:16.841781 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11231 17:35:16.849219 /lava-11518302/1/../bin/lava-test-case
11232 17:35:16.856179 <8>[ 18.896011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11233 17:35:16.856429 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11235 17:35:16.875713 /lava-11518302/1/../bin/lava-tes<8>[ 18.914661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11236 17:35:16.875795 t-case
11237 17:35:16.876051 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11239 17:35:16.887328 /lava-11518302/1/../bin/lava-test-case
11240 17:35:16.893321 <8>[ 18.933021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11241 17:35:16.893569 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11243 17:35:16.902322 /lava-11518302/1/../bin/lava-test-case
11244 17:35:16.908647 <8>[ 18.948444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11245 17:35:16.908904 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11247 17:35:16.920119 /lava-11518302/1/../bin/lava-test-case
11248 17:35:16.926933 <8>[ 18.966344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11249 17:35:16.927187 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11251 17:35:16.939404 /lava-11518302/1/../bin/lava-test-case
11252 17:35:16.946281 <8>[ 18.985874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11253 17:35:16.946572 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11255 17:35:16.957325 /lava-11518302/1/../bin/lava-test-case
11256 17:35:16.964142 <8>[ 19.003535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11257 17:35:16.964397 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11259 17:35:16.978667 /lava-11518302/1/../bin/lava-tes<8>[ 19.017275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11260 17:35:16.978760 t-case
11261 17:35:16.979015 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11263 17:35:17.991559 /lava-11518302/1/../bin/lava-test-case
11264 17:35:17.998163 <8>[ 20.039372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11265 17:35:17.998483 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11267 17:35:18.007971 /lava-11518302/1/../bin/lava-test-case
11268 17:35:18.014105 <8>[ 20.053355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11269 17:35:18.014368 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11271 17:35:19.031785 /lava-11518302/1/../bin/lava-test-case
11272 17:35:19.038490 <8>[ 21.079411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11273 17:35:19.038801 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11275 17:35:19.047419 /lava-11518302/1/../bin/lava-test-case
11276 17:35:19.054278 <8>[ 21.093590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11277 17:35:19.054566 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11279 17:35:20.071215 /lava-11518302/1/../bin/lava-test-case
11280 17:35:20.077609 <8>[ 22.117917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11281 17:35:20.077931 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11283 17:35:20.086907 /lava-11518302/1/../bin/lava-test-case
11284 17:35:20.093035 <8>[ 22.133590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11285 17:35:20.093353 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11287 17:35:21.110841 /lava-11518302/1/../bin/lava-test-case
11288 17:35:21.117150 <8>[ 23.158828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11289 17:35:21.117470 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11291 17:35:21.127987 /lava-11518302/1/../bin/lava-test-case
11292 17:35:21.134354 <8>[ 23.174618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11293 17:35:21.134666 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11295 17:35:22.150419 /lava-11518302/1/../bin/lava-test-case
11296 17:35:22.157395 <8>[ 24.198479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11297 17:35:22.157767 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11299 17:35:22.167425 /lava-11518302/1/../bin/lava-test-case
11300 17:35:22.174167 <8>[ 24.213459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11301 17:35:22.174553 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11303 17:35:23.188466 /lava-11518302/1/../bin/lava-test-case
11304 17:35:23.195377 <8>[ 25.236850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11305 17:35:23.195675 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11307 17:35:23.206468 /lava-11518302/1/../bin/lava-test-case
11308 17:35:23.212726 <8>[ 25.252970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11309 17:35:23.213025 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11311 17:35:24.227525 /lava-11518302/1/../bin/lava-test-case
11312 17:35:24.234433 <8>[ 26.276012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11313 17:35:24.234849 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11315 17:35:24.244784 /lava-11518302/1/../bin/lava-test-case
11316 17:35:24.251750 <8>[ 26.291719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11317 17:35:24.252128 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11319 17:35:24.268505 /lava-11518302/1/../bin/lava-tes<8>[ 26.308011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11320 17:35:24.268673 t-case
11321 17:35:24.268957 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11323 17:35:25.281339 /lava-11518302/1/../bin/lava-test-case
11324 17:35:25.288583 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11326 17:35:25.291676 <8>[ 27.330351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11327 17:35:25.300186 /lava-11518302/1/../bin/lava-test-case
11328 17:35:25.306835 <8>[ 27.347156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11329 17:35:25.307170 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11331 17:35:25.319434 /lava-11518302/1/../bin/lava-test-case
11332 17:35:25.325638 <8>[ 27.365656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11333 17:35:25.325985 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11335 17:35:25.338313 /lava-11518302/1/../bin/lava-test-case
11336 17:35:25.345059 <8>[ 27.384833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11337 17:35:25.345401 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11339 17:35:25.357299 /lava-11518302/1/../bin/lava-test-case
11340 17:35:25.363914 <8>[ 27.404330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11341 17:35:25.364248 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11343 17:35:25.382311 /lava-11518302/1/../bin/lava-tes<8>[ 27.421602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11344 17:35:25.382463 t-case
11345 17:35:25.382742 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11347 17:35:25.403282 /lava-11518302/1/../bin/lava-tes<8>[ 27.442892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11348 17:35:25.403413 t-case
11349 17:35:25.403674 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11351 17:35:25.419235 /lava-11518302/1/../bin/lava-tes<8>[ 27.458514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11352 17:35:25.419399 t-case
11353 17:35:25.419680 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11355 17:35:25.432718 /lava-11518302/1/../bin/lava-test-case
11356 17:35:25.439514 <8>[ 27.479996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11357 17:35:25.439847 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11359 17:35:25.457853 /lava-11518302/1/../bin/lava-tes<8>[ 27.497623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11360 17:35:25.458016 t-case
11361 17:35:25.458304 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11363 17:35:25.474326 /lava-11518302/1/../bin/lava-tes<8>[ 27.513382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11364 17:35:25.474487 t-case
11365 17:35:25.474769 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11367 17:35:25.485918 /lava-11518302/1/../bin/lava-test-case
11368 17:35:25.492022 <8>[ 27.532188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11369 17:35:25.492355 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11371 17:35:25.510244 /lava-11518302/1/../bin/lava-tes<8>[ 27.549772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11372 17:35:25.510403 t-case
11373 17:35:25.510681 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11375 17:35:25.522360 /lava-11518302/1/../bin/lava-test-case
11376 17:35:25.528728 <8>[ 27.568639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11377 17:35:25.529051 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11379 17:35:25.544213 /lava-11518302/1/../bin/lava-tes<8>[ 27.583707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11380 17:35:25.544370 t-case
11381 17:35:25.544646 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11383 17:35:25.563261 /lava-11518302/1/../bin/lava-tes<8>[ 27.603074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11384 17:35:25.563429 t-case
11385 17:35:25.563674 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11387 17:35:25.580576 /lava-11518302/1/../bin/lava-tes<8>[ 27.620591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11388 17:35:25.580735 t-case
11389 17:35:25.581014 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11391 17:35:25.592949 /lava-11518302/1/../bin/lava-test-case
11392 17:35:25.599222 <8>[ 27.640147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11393 17:35:25.599560 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11395 17:35:25.609826 /lava-11518302/1/../bin/lava-test-case
11396 17:35:25.616650 <8>[ 27.656792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11397 17:35:25.616995 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11399 17:35:25.635148 /lava-11518302/1/../bin/lava-tes<8>[ 27.674918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11400 17:35:25.635308 t-case
11401 17:35:25.635590 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11403 17:35:25.645664 /lava-11518302/1/../bin/lava-test-case
11404 17:35:25.651809 <8>[ 27.691920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11405 17:35:25.652145 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11407 17:35:26.666803 /lava-11518302/1/../bin/lava-test-case
11408 17:35:26.672914 <8>[ 28.714413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11409 17:35:26.673217 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11411 17:35:27.687414 /lava-11518302/1/../bin/lava-test-case
11412 17:35:27.693723 <8>[ 29.734794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11413 17:35:27.694015 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11415 17:35:27.706783 /lava-11518302/1/../bin/lava-test-case
11416 17:35:27.713678 <8>[ 29.755734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11417 17:35:27.713959 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11419 17:35:27.728997 /lava-11518302/1/../bin/lava-test-case
11420 17:35:27.735602 <8>[ 29.775813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11421 17:35:27.735901 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11423 17:35:27.745609 /lava-11518302/1/../bin/lava-test-case
11424 17:35:27.752013 <8>[ 29.793273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11425 17:35:27.752302 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11427 17:35:27.764106 /lava-11518302/1/../bin/lava-test-case
11428 17:35:27.771013 <8>[ 29.811184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11429 17:35:27.771337 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11431 17:35:27.779142 /lava-11518302/1/../bin/lava-test-case
11432 17:35:27.785549 <8>[ 29.825687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11433 17:35:27.785805 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11435 17:35:27.802187 /lava-11518302/1/../bin/lava-tes<8>[ 29.845174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11436 17:35:27.802475 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11438 17:35:27.805582 t-case
11439 17:35:27.812567 /lava-11518302/1/../bin/lava-test-case
11440 17:35:27.818772 <8>[ 29.859734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11441 17:35:27.819047 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11443 17:35:27.837893 /lava-11518302/1/../bin/lava-tes<8>[ 29.877841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11444 17:35:27.838047 t-case
11445 17:35:27.838327 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11447 17:35:27.854494 /lava-11518302/1/../bin/lava-tes<8>[ 29.894684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11448 17:35:27.854666 t-case
11449 17:35:27.854966 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11451 17:35:27.865472 /lava-11518302/1/../bin/lava-test-case
11452 17:35:27.872393 <8>[ 29.912649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11453 17:35:27.872690 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11455 17:35:27.881097 /lava-11518302/1/../bin/lava-test-case
11456 17:35:27.887805 <8>[ 29.927975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11457 17:35:27.888065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11459 17:35:27.906641 /lava-11518302/1/../bin/lava-tes<8>[ 29.946855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11460 17:35:27.906730 t-case
11461 17:35:27.906963 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11463 17:35:27.915982 /lava-11518302/1/../bin/lava-test-case
11464 17:35:27.922317 <8>[ 29.962435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11465 17:35:27.922595 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11467 17:35:27.937159 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11469 17:35:27.940780 /lava-11518302/1/../bin/lava-tes<8>[ 29.980316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11470 17:35:27.940856 t-case
11471 17:35:27.949894 /lava-11518302/1/../bin/lava-test-case
11472 17:35:27.959840 <8>[ 29.999876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11473 17:35:27.960134 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11475 17:35:27.969662 /lava-11518302/1/../bin/lava-test-case
11476 17:35:27.976765 <8>[ 30.017269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11477 17:35:27.977040 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11479 17:35:27.985376 /lava-11518302/1/../bin/lava-test-case
11480 17:35:27.992023 <8>[ 30.032759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11481 17:35:27.992274 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11483 17:35:28.002047 /lava-11518302/1/../bin/lava-test-case
11484 17:35:28.009162 <8>[ 30.049910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11485 17:35:28.009434 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11487 17:35:28.021293 /lava-11518302/1/../bin/lava-test-case
11488 17:35:28.027839 <8>[ 30.067816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11489 17:35:28.028088 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11491 17:35:28.039605 /lava-11518302/1/../bin/lava-test-case
11492 17:35:28.045959 <8>[ 30.087209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11493 17:35:28.046241 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11495 17:35:29.056774 /lava-11518302/1/../bin/lava-test-case
11496 17:35:29.066377 <8>[ 31.105828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11497 17:35:29.066696 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11499 17:35:30.078425 /lava-11518302/1/../bin/lava-test-case
11500 17:35:30.084704 <8>[ 32.127218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11501 17:35:30.084979 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11502 17:35:30.085100 Bad test result: blocked
11503 17:35:30.095338 /lava-11518302/1/../bin/lava-test-case
11504 17:35:30.101887 <8>[ 32.142633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11505 17:35:30.102182 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11507 17:35:31.118690 /lava-11518302/1/../bin/lava-test-case
11508 17:35:31.129585 <8>[ 33.170254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11509 17:35:31.129938 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11511 17:35:31.138577 /lava-11518302/1/../bin/lava-test-case
11512 17:35:31.145350 <8>[ 33.186428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11513 17:35:31.145696 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11515 17:35:31.160508 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11517 17:35:31.163511 /lava-11518302/1/../bin/lava-tes<8>[ 33.203822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11518 17:35:31.163601 t-case
11519 17:35:31.175215 /lava-11518302/1/../bin/lava-test-case
11520 17:35:31.181787 <8>[ 33.224277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11521 17:35:31.182119 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11523 17:35:31.191198 /lava-11518302/1/../bin/lava-test-case
11524 17:35:31.197957 <8>[ 33.239174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11525 17:35:31.198302 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11527 17:35:31.210182 /lava-11518302/1/../bin/lava-test-case
11528 17:35:31.217010 <8>[ 33.258839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11529 17:35:31.217330 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11531 17:35:31.225520 /lava-11518302/1/../bin/lava-test-case
11532 17:35:31.232349 <8>[ 33.272901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11533 17:35:31.232667 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11535 17:35:32.249240 /lava-11518302/1/../bin/lava-test-case
11536 17:35:32.255942 <8>[ 34.298625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11537 17:35:32.256226 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11539 17:35:32.265124 /lava-11518302/1/../bin/lava-test-case
11540 17:35:32.272018 <8>[ 34.312677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11541 17:35:32.272315 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11543 17:35:33.286216 /lava-11518302/1/../bin/lava-test-case
11544 17:35:33.293124 <8>[ 35.335622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11545 17:35:33.293396 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11547 17:35:33.302499 /lava-11518302/1/../bin/lava-test-case
11548 17:35:33.309528 <8>[ 35.350860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11549 17:35:33.309794 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11551 17:35:34.322857 /lava-11518302/1/../bin/lava-test-case
11552 17:35:34.333961 <8>[ 36.375157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11553 17:35:34.334293 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11555 17:35:34.348141 /lava-11518302/1/../bin/lava-tes<8>[ 36.388801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11556 17:35:34.348277 t-case
11557 17:35:34.348542 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11559 17:35:35.362898 /lava-11518302/1/../bin/lava-test-case
11560 17:35:35.369649 <8>[ 37.412594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11561 17:35:35.369962 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11563 17:35:35.380051 /lava-11518302/1/../bin/lava-test-case
11564 17:35:35.387028 <8>[ 37.428508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11565 17:35:35.387309 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11567 17:35:35.399322 /lava-11518302/1/../bin/lava-test-case
11568 17:35:35.405487 <8>[ 37.446718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11569 17:35:35.405810 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11571 17:35:35.419552 /lava-11518302/1/../bin/lava-tes<8>[ 37.463392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11572 17:35:35.419917 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11574 17:35:35.422772 t-case
11575 17:35:35.437687 /lava-11518302/1/../bin/lava-tes<8>[ 37.478584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11576 17:35:35.437803 t-case
11577 17:35:35.438050 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11579 17:35:35.451781 /lava-11518302/1/../bin/lava-tes<8>[ 37.495641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11580 17:35:35.452108 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11582 17:35:35.454513 t-case
11583 17:35:35.463534 /lava-11518302/1/../bin/lava-test-case
11584 17:35:35.470427 <8>[ 37.511020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11585 17:35:35.470705 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11587 17:35:35.481692 /lava-11518302/1/../bin/lava-test-case
11588 17:35:35.488605 <8>[ 37.529822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11589 17:35:35.488875 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11591 17:35:35.497088 /lava-11518302/1/../bin/lava-test-case
11592 17:35:35.506687 <8>[ 37.546752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11593 17:35:35.506964 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11595 17:35:35.517198 /lava-11518302/1/../bin/lava-test-case
11596 17:35:35.523983 <8>[ 37.565338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11597 17:35:35.524295 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11599 17:35:35.527438 + set +x
11600 17:35:35.531196 Received signal: <ENDRUN> 1_bootrr 11518302_1.5.2.3.5
11601 17:35:35.531294 Ending use of test pattern.
11602 17:35:35.531361 Ending test lava.1_bootrr (11518302_1.5.2.3.5), duration 20.37
11604 17:35:35.534445 <8>[ 37.575688] <LAVA_SIGNAL_ENDRUN 1_bootrr 11518302_1.5.2.3.5>
11605 17:35:35.537252 <LAVA_TEST_RUNNER EXIT>
11606 17:35:35.537511 ok: lava_test_shell seems to have completed
11607 17:35:35.538505 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11608 17:35:35.538653 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11609 17:35:35.538743 end: 4 lava-test-retry (duration 00:00:21) [common]
11610 17:35:35.538832 start: 5 finalize (timeout 00:08:05) [common]
11611 17:35:35.538925 start: 5.1 power-off (timeout 00:00:30) [common]
11612 17:35:35.539083 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11613 17:35:35.616366 >> Command sent successfully.
11614 17:35:35.619321 Returned 0 in 0 seconds
11615 17:35:35.719790 end: 5.1 power-off (duration 00:00:00) [common]
11617 17:35:35.720184 start: 5.2 read-feedback (timeout 00:08:05) [common]
11618 17:35:35.720495 Listened to connection for namespace 'common' for up to 1s
11619 17:35:36.720474 Finalising connection for namespace 'common'
11620 17:35:36.720646 Disconnecting from shell: Finalise
11621 17:35:36.720737 / #
11622 17:35:36.821036 end: 5.2 read-feedback (duration 00:00:01) [common]
11623 17:35:36.821205 end: 5 finalize (duration 00:00:01) [common]
11624 17:35:36.821322 Cleaning after the job
11625 17:35:36.821436 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/ramdisk
11626 17:35:36.824731 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/kernel
11627 17:35:36.833455 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/dtb
11628 17:35:36.833672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518302/tftp-deploy-lkfdnmk9/modules
11629 17:35:36.841183 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11518302
11630 17:35:36.890668 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11518302
11631 17:35:36.890847 Job finished correctly