Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 17:34:15.998068 lava-dispatcher, installed at version: 2023.06
2 17:34:15.998270 start: 0 validate
3 17:34:15.998412 Start time: 2023-09-13 17:34:15.998404+00:00 (UTC)
4 17:34:15.998542 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:34:15.998687 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 17:34:16.252295 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:34:16.253023 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:34:16.506699 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:34:16.507382 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:34:16.761026 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:34:16.761866 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:34:17.259077 Using caching service: 'http://localhost/cache/?uri=%s'
13 17:34:17.260086 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 17:34:17.522024 validate duration: 1.52
16 17:34:17.523183 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:34:17.523770 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:34:17.524233 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:34:17.524847 Not decompressing ramdisk as can be used compressed.
20 17:34:17.525287 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 17:34:17.525618 saving as /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/ramdisk/initrd.cpio.gz
22 17:34:17.525973 total size: 4665412 (4 MB)
23 17:34:17.530966 progress 0 % (0 MB)
24 17:34:17.539090 progress 5 % (0 MB)
25 17:34:17.545979 progress 10 % (0 MB)
26 17:34:17.551200 progress 15 % (0 MB)
27 17:34:17.554922 progress 20 % (0 MB)
28 17:34:17.558083 progress 25 % (1 MB)
29 17:34:17.560895 progress 30 % (1 MB)
30 17:34:17.563285 progress 35 % (1 MB)
31 17:34:17.565557 progress 40 % (1 MB)
32 17:34:17.567915 progress 45 % (2 MB)
33 17:34:17.569943 progress 50 % (2 MB)
34 17:34:17.571893 progress 55 % (2 MB)
35 17:34:17.573613 progress 60 % (2 MB)
36 17:34:17.575320 progress 65 % (2 MB)
37 17:34:17.577055 progress 70 % (3 MB)
38 17:34:17.578646 progress 75 % (3 MB)
39 17:34:17.580229 progress 80 % (3 MB)
40 17:34:17.581966 progress 85 % (3 MB)
41 17:34:17.583268 progress 90 % (4 MB)
42 17:34:17.584532 progress 95 % (4 MB)
43 17:34:17.585776 progress 100 % (4 MB)
44 17:34:17.585930 4 MB downloaded in 0.06 s (74.17 MB/s)
45 17:34:17.586082 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:34:17.586322 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:34:17.586408 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:34:17.586492 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:34:17.586624 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 17:34:17.586697 saving as /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/kernel/Image
52 17:34:17.586757 total size: 49220096 (46 MB)
53 17:34:17.586818 No compression specified
54 17:34:17.587935 progress 0 % (0 MB)
55 17:34:17.601328 progress 5 % (2 MB)
56 17:34:17.614211 progress 10 % (4 MB)
57 17:34:17.626969 progress 15 % (7 MB)
58 17:34:17.639788 progress 20 % (9 MB)
59 17:34:17.652904 progress 25 % (11 MB)
60 17:34:17.666180 progress 30 % (14 MB)
61 17:34:17.679926 progress 35 % (16 MB)
62 17:34:17.693484 progress 40 % (18 MB)
63 17:34:17.706468 progress 45 % (21 MB)
64 17:34:17.719556 progress 50 % (23 MB)
65 17:34:17.732338 progress 55 % (25 MB)
66 17:34:17.745123 progress 60 % (28 MB)
67 17:34:17.757939 progress 65 % (30 MB)
68 17:34:17.770700 progress 70 % (32 MB)
69 17:34:17.783868 progress 75 % (35 MB)
70 17:34:17.796620 progress 80 % (37 MB)
71 17:34:17.809369 progress 85 % (39 MB)
72 17:34:17.822103 progress 90 % (42 MB)
73 17:34:17.834723 progress 95 % (44 MB)
74 17:34:17.847359 progress 100 % (46 MB)
75 17:34:17.847535 46 MB downloaded in 0.26 s (180.00 MB/s)
76 17:34:17.847685 end: 1.2.1 http-download (duration 00:00:00) [common]
78 17:34:17.847924 end: 1.2 download-retry (duration 00:00:00) [common]
79 17:34:17.848012 start: 1.3 download-retry (timeout 00:10:00) [common]
80 17:34:17.848100 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 17:34:17.848245 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 17:34:17.848321 saving as /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/dtb/mt8192-asurada-spherion-r0.dtb
83 17:34:17.848383 total size: 47278 (0 MB)
84 17:34:17.848445 No compression specified
85 17:34:17.849546 progress 69 % (0 MB)
86 17:34:17.849825 progress 100 % (0 MB)
87 17:34:17.849988 0 MB downloaded in 0.00 s (28.14 MB/s)
88 17:34:17.850112 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:34:17.850332 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:34:17.850432 start: 1.4 download-retry (timeout 00:10:00) [common]
92 17:34:17.850527 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 17:34:17.850641 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 17:34:17.850707 saving as /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/nfsrootfs/full.rootfs.tar
95 17:34:17.850790 total size: 125290964 (119 MB)
96 17:34:17.850855 Using unxz to decompress xz
97 17:34:17.855047 progress 0 % (0 MB)
98 17:34:18.177490 progress 5 % (6 MB)
99 17:34:18.510037 progress 10 % (11 MB)
100 17:34:18.861307 progress 15 % (17 MB)
101 17:34:19.047240 progress 20 % (23 MB)
102 17:34:19.219898 progress 25 % (29 MB)
103 17:34:19.567656 progress 30 % (35 MB)
104 17:34:19.919106 progress 35 % (41 MB)
105 17:34:20.307096 progress 40 % (47 MB)
106 17:34:20.684832 progress 45 % (53 MB)
107 17:34:21.073404 progress 50 % (59 MB)
108 17:34:21.428582 progress 55 % (65 MB)
109 17:34:21.797931 progress 60 % (71 MB)
110 17:34:22.142820 progress 65 % (77 MB)
111 17:34:22.508325 progress 70 % (83 MB)
112 17:34:22.888178 progress 75 % (89 MB)
113 17:34:23.310234 progress 80 % (95 MB)
114 17:34:23.729484 progress 85 % (101 MB)
115 17:34:23.972040 progress 90 % (107 MB)
116 17:34:24.305838 progress 95 % (113 MB)
117 17:34:24.672498 progress 100 % (119 MB)
118 17:34:24.678087 119 MB downloaded in 6.83 s (17.50 MB/s)
119 17:34:24.678348 end: 1.4.1 http-download (duration 00:00:07) [common]
121 17:34:24.678765 end: 1.4 download-retry (duration 00:00:07) [common]
122 17:34:24.678918 start: 1.5 download-retry (timeout 00:09:53) [common]
123 17:34:24.679025 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 17:34:24.679199 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 17:34:24.679272 saving as /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/modules/modules.tar
126 17:34:24.679334 total size: 8628656 (8 MB)
127 17:34:24.679417 Using unxz to decompress xz
128 17:34:24.683538 progress 0 % (0 MB)
129 17:34:24.705004 progress 5 % (0 MB)
130 17:34:24.726806 progress 10 % (0 MB)
131 17:34:24.754202 progress 15 % (1 MB)
132 17:34:24.780388 progress 20 % (1 MB)
133 17:34:24.808637 progress 25 % (2 MB)
134 17:34:24.836857 progress 30 % (2 MB)
135 17:34:24.864227 progress 35 % (2 MB)
136 17:34:24.889466 progress 40 % (3 MB)
137 17:34:24.913541 progress 45 % (3 MB)
138 17:34:24.940010 progress 50 % (4 MB)
139 17:34:24.965398 progress 55 % (4 MB)
140 17:34:24.990070 progress 60 % (4 MB)
141 17:34:25.014670 progress 65 % (5 MB)
142 17:34:25.039449 progress 70 % (5 MB)
143 17:34:25.063276 progress 75 % (6 MB)
144 17:34:25.089215 progress 80 % (6 MB)
145 17:34:25.118727 progress 85 % (7 MB)
146 17:34:25.145530 progress 90 % (7 MB)
147 17:34:25.171330 progress 95 % (7 MB)
148 17:34:25.194282 progress 100 % (8 MB)
149 17:34:25.199379 8 MB downloaded in 0.52 s (15.82 MB/s)
150 17:34:25.199680 end: 1.5.1 http-download (duration 00:00:01) [common]
152 17:34:25.199941 end: 1.5 download-retry (duration 00:00:01) [common]
153 17:34:25.200035 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 17:34:25.200133 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 17:34:27.397211 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu
156 17:34:27.397417 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 17:34:27.397521 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 17:34:27.397693 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8
159 17:34:27.397828 makedir: /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin
160 17:34:27.397933 makedir: /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/tests
161 17:34:27.398033 makedir: /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/results
162 17:34:27.398136 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-add-keys
163 17:34:27.398282 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-add-sources
164 17:34:27.398414 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-background-process-start
165 17:34:27.398548 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-background-process-stop
166 17:34:27.398677 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-common-functions
167 17:34:27.398804 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-echo-ipv4
168 17:34:27.398931 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-install-packages
169 17:34:27.399057 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-installed-packages
170 17:34:27.399182 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-os-build
171 17:34:27.399309 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-probe-channel
172 17:34:27.399479 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-probe-ip
173 17:34:27.399609 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-target-ip
174 17:34:27.399735 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-target-mac
175 17:34:27.399862 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-target-storage
176 17:34:27.399990 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-case
177 17:34:27.400120 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-event
178 17:34:27.400246 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-feedback
179 17:34:27.400373 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-raise
180 17:34:27.400499 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-reference
181 17:34:27.400630 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-runner
182 17:34:27.400757 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-set
183 17:34:27.400884 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-test-shell
184 17:34:27.401014 Updating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-install-packages (oe)
185 17:34:27.401171 Updating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/bin/lava-installed-packages (oe)
186 17:34:27.401296 Creating /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/environment
187 17:34:27.401398 LAVA metadata
188 17:34:27.401469 - LAVA_JOB_ID=11518300
189 17:34:27.401532 - LAVA_DISPATCHER_IP=192.168.201.1
190 17:34:27.401651 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 17:34:27.401722 skipped lava-vland-overlay
192 17:34:27.401798 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 17:34:27.401879 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 17:34:27.401941 skipped lava-multinode-overlay
195 17:34:27.402013 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 17:34:27.402091 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 17:34:27.402165 Loading test definitions
198 17:34:27.402255 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 17:34:27.402325 Using /lava-11518300 at stage 0
200 17:34:27.402651 uuid=11518300_1.6.2.3.1 testdef=None
201 17:34:27.402740 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 17:34:27.402825 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 17:34:27.403342 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 17:34:27.403611 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 17:34:27.404259 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 17:34:27.404488 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 17:34:27.405115 runner path: /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/0/tests/0_dmesg test_uuid 11518300_1.6.2.3.1
210 17:34:27.405272 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 17:34:27.405496 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 17:34:27.405568 Using /lava-11518300 at stage 1
214 17:34:27.405874 uuid=11518300_1.6.2.3.5 testdef=None
215 17:34:27.405962 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 17:34:27.406047 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 17:34:27.406519 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 17:34:27.406737 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 17:34:27.407389 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 17:34:27.407647 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 17:34:27.408280 runner path: /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/1/tests/1_bootrr test_uuid 11518300_1.6.2.3.5
224 17:34:27.408433 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 17:34:27.408638 Creating lava-test-runner.conf files
227 17:34:27.408700 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/0 for stage 0
228 17:34:27.408790 - 0_dmesg
229 17:34:27.408870 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11518300/lava-overlay-kjnijuk8/lava-11518300/1 for stage 1
230 17:34:27.408961 - 1_bootrr
231 17:34:27.409056 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 17:34:27.409142 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 17:34:27.416756 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 17:34:27.416857 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 17:34:27.416942 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 17:34:27.417026 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 17:34:27.417111 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 17:34:27.539617 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 17:34:27.540020 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 17:34:27.540142 extracting modules file /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu
241 17:34:27.768164 extracting modules file /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11518300/extract-overlay-ramdisk-ytffu92z/ramdisk
242 17:34:28.006556 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 17:34:28.006732 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
244 17:34:28.006831 [common] Applying overlay to NFS
245 17:34:28.006905 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518300/compress-overlay-d97ud8ez/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu
246 17:34:28.015264 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 17:34:28.015381 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
248 17:34:28.015486 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 17:34:28.015575 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
250 17:34:28.015656 Building ramdisk /var/lib/lava/dispatcher/tmp/11518300/extract-overlay-ramdisk-ytffu92z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11518300/extract-overlay-ramdisk-ytffu92z/ramdisk
251 17:34:28.319766 >> 119344 blocks
252 17:34:30.322705 rename /var/lib/lava/dispatcher/tmp/11518300/extract-overlay-ramdisk-ytffu92z/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/ramdisk/ramdisk.cpio.gz
253 17:34:30.323166 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 17:34:30.323294 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 17:34:30.323442 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 17:34:30.323557 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/kernel/Image'
257 17:34:42.899694 Returned 0 in 12 seconds
258 17:34:43.000738 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/kernel/image.itb
259 17:34:43.368537 output: FIT description: Kernel Image image with one or more FDT blobs
260 17:34:43.369037 output: Created: Wed Sep 13 18:34:43 2023
261 17:34:43.369139 output: Image 0 (kernel-1)
262 17:34:43.369249 output: Description:
263 17:34:43.369362 output: Created: Wed Sep 13 18:34:43 2023
264 17:34:43.369455 output: Type: Kernel Image
265 17:34:43.369516 output: Compression: lzma compressed
266 17:34:43.369577 output: Data Size: 11039249 Bytes = 10780.52 KiB = 10.53 MiB
267 17:34:43.369668 output: Architecture: AArch64
268 17:34:43.369729 output: OS: Linux
269 17:34:43.369802 output: Load Address: 0x00000000
270 17:34:43.369871 output: Entry Point: 0x00000000
271 17:34:43.369924 output: Hash algo: crc32
272 17:34:43.369976 output: Hash value: 2ab54ae9
273 17:34:43.370045 output: Image 1 (fdt-1)
274 17:34:43.370099 output: Description: mt8192-asurada-spherion-r0
275 17:34:43.370167 output: Created: Wed Sep 13 18:34:43 2023
276 17:34:43.370220 output: Type: Flat Device Tree
277 17:34:43.370288 output: Compression: uncompressed
278 17:34:43.370343 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 17:34:43.370397 output: Architecture: AArch64
280 17:34:43.370451 output: Hash algo: crc32
281 17:34:43.370517 output: Hash value: cc4352de
282 17:34:43.370569 output: Image 2 (ramdisk-1)
283 17:34:43.370622 output: Description: unavailable
284 17:34:43.370674 output: Created: Wed Sep 13 18:34:43 2023
285 17:34:43.370726 output: Type: RAMDisk Image
286 17:34:43.370779 output: Compression: Unknown Compression
287 17:34:43.370832 output: Data Size: 17788448 Bytes = 17371.53 KiB = 16.96 MiB
288 17:34:43.370885 output: Architecture: AArch64
289 17:34:43.370937 output: OS: Linux
290 17:34:43.370990 output: Load Address: unavailable
291 17:34:43.371043 output: Entry Point: unavailable
292 17:34:43.371095 output: Hash algo: crc32
293 17:34:43.371147 output: Hash value: 9e3f3050
294 17:34:43.371215 output: Default Configuration: 'conf-1'
295 17:34:43.371269 output: Configuration 0 (conf-1)
296 17:34:43.371322 output: Description: mt8192-asurada-spherion-r0
297 17:34:43.371376 output: Kernel: kernel-1
298 17:34:43.371452 output: Init Ramdisk: ramdisk-1
299 17:34:43.371504 output: FDT: fdt-1
300 17:34:43.371557 output: Loadables: kernel-1
301 17:34:43.371613 output:
302 17:34:43.371849 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 17:34:43.371950 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 17:34:43.372050 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 17:34:43.372148 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 17:34:43.372226 No LXC device requested
307 17:34:43.372305 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 17:34:43.372394 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 17:34:43.372472 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 17:34:43.372541 Checking files for TFTP limit of 4294967296 bytes.
311 17:34:43.373059 end: 1 tftp-deploy (duration 00:00:26) [common]
312 17:34:43.373166 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 17:34:43.373256 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 17:34:43.373381 substitutions:
315 17:34:43.373447 - {DTB}: 11518300/tftp-deploy-6ezufo9_/dtb/mt8192-asurada-spherion-r0.dtb
316 17:34:43.373512 - {INITRD}: 11518300/tftp-deploy-6ezufo9_/ramdisk/ramdisk.cpio.gz
317 17:34:43.373572 - {KERNEL}: 11518300/tftp-deploy-6ezufo9_/kernel/Image
318 17:34:43.373629 - {LAVA_MAC}: None
319 17:34:43.373686 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu
320 17:34:43.373742 - {NFS_SERVER_IP}: 192.168.201.1
321 17:34:43.373797 - {PRESEED_CONFIG}: None
322 17:34:43.373851 - {PRESEED_LOCAL}: None
323 17:34:43.373906 - {RAMDISK}: 11518300/tftp-deploy-6ezufo9_/ramdisk/ramdisk.cpio.gz
324 17:34:43.373960 - {ROOT_PART}: None
325 17:34:43.374014 - {ROOT}: None
326 17:34:43.374067 - {SERVER_IP}: 192.168.201.1
327 17:34:43.374150 - {TEE}: None
328 17:34:43.374219 Parsed boot commands:
329 17:34:43.374273 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 17:34:43.374476 Parsed boot commands: tftpboot 192.168.201.1 11518300/tftp-deploy-6ezufo9_/kernel/image.itb 11518300/tftp-deploy-6ezufo9_/kernel/cmdline
331 17:34:43.374567 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 17:34:43.374653 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 17:34:43.374746 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 17:34:43.374832 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 17:34:43.374905 Not connected, no need to disconnect.
336 17:34:43.374980 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 17:34:43.375067 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 17:34:43.375133 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
339 17:34:43.379315 Setting prompt string to ['lava-test: # ']
340 17:34:43.379709 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 17:34:43.379837 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 17:34:43.379982 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 17:34:43.380093 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 17:34:43.380306 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 17:34:48.515067 >> Command sent successfully.
346 17:34:48.517828 Returned 0 in 5 seconds
347 17:34:48.618203 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 17:34:48.618656 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 17:34:48.618795 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 17:34:48.618917 Setting prompt string to 'Starting depthcharge on Spherion...'
352 17:34:48.619019 Changing prompt to 'Starting depthcharge on Spherion...'
353 17:34:48.619126 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 17:34:48.619521 [Enter `^Ec?' for help]
355 17:34:48.790639
356 17:34:48.790801
357 17:34:48.790899 F0: 102B 0000
358 17:34:48.790993
359 17:34:48.791083 F3: 1001 0000 [0200]
360 17:34:48.794489
361 17:34:48.794588 F3: 1001 0000
362 17:34:48.794656
363 17:34:48.794718 F7: 102D 0000
364 17:34:48.794805
365 17:34:48.797403 F1: 0000 0000
366 17:34:48.797476
367 17:34:48.797536 V0: 0000 0000 [0001]
368 17:34:48.797627
369 17:34:48.801122 00: 0007 8000
370 17:34:48.801224
371 17:34:48.801312 01: 0000 0000
372 17:34:48.801400
373 17:34:48.804784 BP: 0C00 0209 [0000]
374 17:34:48.804880
375 17:34:48.804967 G0: 1182 0000
376 17:34:48.805053
377 17:34:48.808259 EC: 0000 0021 [4000]
378 17:34:48.808327
379 17:34:48.808384 S7: 0000 0000 [0000]
380 17:34:48.808441
381 17:34:48.811460 CC: 0000 0000 [0001]
382 17:34:48.811556
383 17:34:48.811637 T0: 0000 0040 [010F]
384 17:34:48.811695
385 17:34:48.811752 Jump to BL
386 17:34:48.811807
387 17:34:48.838008
388 17:34:48.838105
389 17:34:48.838175
390 17:34:48.845376 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 17:34:48.849468 ARM64: Exception handlers installed.
392 17:34:48.852737 ARM64: Testing exception
393 17:34:48.855820 ARM64: Done test exception
394 17:34:48.862294 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 17:34:48.872747 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 17:34:48.879324 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 17:34:48.889552 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 17:34:48.896016 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 17:34:48.902755 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 17:34:48.914653 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 17:34:48.921356 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 17:34:48.940809 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 17:34:48.944132 WDT: Last reset was cold boot
404 17:34:48.947470 SPI1(PAD0) initialized at 2873684 Hz
405 17:34:48.950437 SPI5(PAD0) initialized at 992727 Hz
406 17:34:48.953749 VBOOT: Loading verstage.
407 17:34:48.960477 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 17:34:48.964245 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 17:34:48.967561 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 17:34:48.970608 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 17:34:48.978040 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 17:34:48.985031 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 17:34:48.995502 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
414 17:34:48.995631
415 17:34:48.995757
416 17:34:49.005530 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 17:34:49.009188 ARM64: Exception handlers installed.
418 17:34:49.012394 ARM64: Testing exception
419 17:34:49.012500 ARM64: Done test exception
420 17:34:49.019211 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 17:34:49.022097 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 17:34:49.036666 Probing TPM: . done!
423 17:34:49.036795 TPM ready after 0 ms
424 17:34:49.043304 Connected to device vid:did:rid of 1ae0:0028:00
425 17:34:49.092242 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 17:34:49.092391 Initialized TPM device CR50 revision 0
427 17:34:49.104298 tlcl_send_startup: Startup return code is 0
428 17:34:49.104408 TPM: setup succeeded
429 17:34:49.116088 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 17:34:49.124657 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 17:34:49.136274 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 17:34:49.145513 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 17:34:49.149411 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 17:34:49.152486 in-header: 03 07 00 00 08 00 00 00
435 17:34:49.156045 in-data: aa e4 47 04 13 02 00 00
436 17:34:49.159747 Chrome EC: UHEPI supported
437 17:34:49.167063 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 17:34:49.171331 in-header: 03 9d 00 00 08 00 00 00
439 17:34:49.174561 in-data: 10 20 20 08 00 00 00 00
440 17:34:49.174645 Phase 1
441 17:34:49.178268 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 17:34:49.182380 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 17:34:49.189421 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 17:34:49.192530 Recovery requested (1009000e)
445 17:34:49.199016 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 17:34:49.205097 tlcl_extend: response is 0
447 17:34:49.213026 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 17:34:49.218622 tlcl_extend: response is 0
449 17:34:49.224777 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 17:34:49.246394 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
451 17:34:49.253141 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 17:34:49.253229
453 17:34:49.253293
454 17:34:49.263753 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 17:34:49.267635 ARM64: Exception handlers installed.
456 17:34:49.267717 ARM64: Testing exception
457 17:34:49.270563 ARM64: Done test exception
458 17:34:49.292051 pmic_efuse_setting: Set efuses in 11 msecs
459 17:34:49.295178 pmwrap_interface_init: Select PMIF_VLD_RDY
460 17:34:49.298556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 17:34:49.306175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 17:34:49.309942 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 17:34:49.313259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 17:34:49.320514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 17:34:49.323786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 17:34:49.330722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 17:34:49.334501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 17:34:49.337943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 17:34:49.344488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 17:34:49.347748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 17:34:49.351335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 17:34:49.358157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 17:34:49.364940 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 17:34:49.367593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 17:34:49.374909 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 17:34:49.380935 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 17:34:49.384672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 17:34:49.391355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 17:34:49.398686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 17:34:49.402169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 17:34:49.409251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 17:34:49.412660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 17:34:49.419436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 17:34:49.423362 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 17:34:49.429833 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 17:34:49.436773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 17:34:49.440963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 17:34:49.444323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 17:34:49.451502 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 17:34:49.454512 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 17:34:49.462168 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 17:34:49.465835 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 17:34:49.469362 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 17:34:49.476605 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 17:34:49.480204 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 17:34:49.487037 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 17:34:49.489862 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 17:34:49.493204 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 17:34:49.499864 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 17:34:49.503699 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 17:34:49.506584 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 17:34:49.513769 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 17:34:49.517069 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 17:34:49.520260 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 17:34:49.526517 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 17:34:49.530117 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 17:34:49.533215 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 17:34:49.536764 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 17:34:49.543652 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 17:34:49.546675 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 17:34:49.553384 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 17:34:49.563350 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 17:34:49.566502 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 17:34:49.576921 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 17:34:49.583812 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 17:34:49.586602 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 17:34:49.593224 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 17:34:49.596698 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 17:34:49.603754 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2b
520 17:34:49.610149 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 17:34:49.613829 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 17:34:49.617096 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 17:34:49.628341 [RTC]rtc_get_frequency_meter,154: input=15, output=792
524 17:34:49.632038 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 17:34:49.638083 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 17:34:49.641568 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 17:34:49.645134 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 17:34:49.648271 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 17:34:49.651521 ADC[4]: Raw value=895561 ID=7
530 17:34:49.655526 ADC[3]: Raw value=213440 ID=1
531 17:34:49.655634 RAM Code: 0x71
532 17:34:49.661854 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 17:34:49.665226 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 17:34:49.675746 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 17:34:49.682007 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 17:34:49.685908 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 17:34:49.689083 in-header: 03 07 00 00 08 00 00 00
538 17:34:49.692423 in-data: aa e4 47 04 13 02 00 00
539 17:34:49.692507 Chrome EC: UHEPI supported
540 17:34:49.699095 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 17:34:49.703516 in-header: 03 d5 00 00 08 00 00 00
542 17:34:49.707022 in-data: 98 20 60 08 00 00 00 00
543 17:34:49.710817 MRC: failed to locate region type 0.
544 17:34:49.718070 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 17:34:49.721194 DRAM-K: Running full calibration
546 17:34:49.728490 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 17:34:49.728577 header.status = 0x0
548 17:34:49.731298 header.version = 0x6 (expected: 0x6)
549 17:34:49.735201 header.size = 0xd00 (expected: 0xd00)
550 17:34:49.738820 header.flags = 0x0
551 17:34:49.741993 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 17:34:49.761885 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
553 17:34:49.769183 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 17:34:49.769264 dram_init: ddr_geometry: 2
555 17:34:49.772873 [EMI] MDL number = 2
556 17:34:49.776270 [EMI] Get MDL freq = 0
557 17:34:49.776356 dram_init: ddr_type: 0
558 17:34:49.780270 is_discrete_lpddr4: 1
559 17:34:49.783933 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 17:34:49.784011
561 17:34:49.784078
562 17:34:49.784149 [Bian_co] ETT version 0.0.0.1
563 17:34:49.787594 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 17:34:49.791173
565 17:34:49.794800 dramc_set_vcore_voltage set vcore to 650000
566 17:34:49.794884 Read voltage for 800, 4
567 17:34:49.798676 Vio18 = 0
568 17:34:49.798760 Vcore = 650000
569 17:34:49.798825 Vdram = 0
570 17:34:49.798932 Vddq = 0
571 17:34:49.802997 Vmddr = 0
572 17:34:49.803082 dram_init: config_dvfs: 1
573 17:34:49.810009 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 17:34:49.813342 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 17:34:49.817573 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 17:34:49.821102 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 17:34:49.824436 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 17:34:49.828386 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 17:34:49.831626 MEM_TYPE=3, freq_sel=18
580 17:34:49.835583 sv_algorithm_assistance_LP4_1600
581 17:34:49.839099 ============ PULL DRAM RESETB DOWN ============
582 17:34:49.841937 ========== PULL DRAM RESETB DOWN end =========
583 17:34:49.845235 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 17:34:49.848883 ===================================
585 17:34:49.852022 LPDDR4 DRAM CONFIGURATION
586 17:34:49.855019 ===================================
587 17:34:49.858310 EX_ROW_EN[0] = 0x0
588 17:34:49.858392 EX_ROW_EN[1] = 0x0
589 17:34:49.861938 LP4Y_EN = 0x0
590 17:34:49.862020 WORK_FSP = 0x0
591 17:34:49.865732 WL = 0x2
592 17:34:49.865886 RL = 0x2
593 17:34:49.868923 BL = 0x2
594 17:34:49.869013 RPST = 0x0
595 17:34:49.872144 RD_PRE = 0x0
596 17:34:49.872284 WR_PRE = 0x1
597 17:34:49.875280 WR_PST = 0x0
598 17:34:49.875410 DBI_WR = 0x0
599 17:34:49.878811 DBI_RD = 0x0
600 17:34:49.878910 OTF = 0x1
601 17:34:49.881825 ===================================
602 17:34:49.885236 ===================================
603 17:34:49.888420 ANA top config
604 17:34:49.891782 ===================================
605 17:34:49.895185 DLL_ASYNC_EN = 0
606 17:34:49.895294 ALL_SLAVE_EN = 1
607 17:34:49.898877 NEW_RANK_MODE = 1
608 17:34:49.901649 DLL_IDLE_MODE = 1
609 17:34:49.905356 LP45_APHY_COMB_EN = 1
610 17:34:49.908435 TX_ODT_DIS = 1
611 17:34:49.908518 NEW_8X_MODE = 1
612 17:34:49.911792 ===================================
613 17:34:49.915303 ===================================
614 17:34:49.918623 data_rate = 1600
615 17:34:49.921823 CKR = 1
616 17:34:49.925346 DQ_P2S_RATIO = 8
617 17:34:49.928861 ===================================
618 17:34:49.931562 CA_P2S_RATIO = 8
619 17:34:49.931645 DQ_CA_OPEN = 0
620 17:34:49.934940 DQ_SEMI_OPEN = 0
621 17:34:49.938620 CA_SEMI_OPEN = 0
622 17:34:49.942107 CA_FULL_RATE = 0
623 17:34:49.944949 DQ_CKDIV4_EN = 1
624 17:34:49.948378 CA_CKDIV4_EN = 1
625 17:34:49.948461 CA_PREDIV_EN = 0
626 17:34:49.952037 PH8_DLY = 0
627 17:34:49.955609 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 17:34:49.958325 DQ_AAMCK_DIV = 4
629 17:34:49.961467 CA_AAMCK_DIV = 4
630 17:34:49.964942 CA_ADMCK_DIV = 4
631 17:34:49.965034 DQ_TRACK_CA_EN = 0
632 17:34:49.968802 CA_PICK = 800
633 17:34:49.971717 CA_MCKIO = 800
634 17:34:49.974757 MCKIO_SEMI = 0
635 17:34:49.978434 PLL_FREQ = 3068
636 17:34:49.981684 DQ_UI_PI_RATIO = 32
637 17:34:49.984790 CA_UI_PI_RATIO = 0
638 17:34:49.988300 ===================================
639 17:34:49.992097 ===================================
640 17:34:49.992180 memory_type:LPDDR4
641 17:34:49.995237 GP_NUM : 10
642 17:34:49.998243 SRAM_EN : 1
643 17:34:49.998356 MD32_EN : 0
644 17:34:50.001428 ===================================
645 17:34:50.005146 [ANA_INIT] >>>>>>>>>>>>>>
646 17:34:50.007940 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 17:34:50.011371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 17:34:50.015141 ===================================
649 17:34:50.018256 data_rate = 1600,PCW = 0X7600
650 17:34:50.021280 ===================================
651 17:34:50.024568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 17:34:50.028045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 17:34:50.034783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 17:34:50.038472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 17:34:50.041677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 17:34:50.044906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 17:34:50.048531 [ANA_INIT] flow start
658 17:34:50.052989 [ANA_INIT] PLL >>>>>>>>
659 17:34:50.053073 [ANA_INIT] PLL <<<<<<<<
660 17:34:50.056669 [ANA_INIT] MIDPI >>>>>>>>
661 17:34:50.056781 [ANA_INIT] MIDPI <<<<<<<<
662 17:34:50.060065 [ANA_INIT] DLL >>>>>>>>
663 17:34:50.060175 [ANA_INIT] flow end
664 17:34:50.067739 ============ LP4 DIFF to SE enter ============
665 17:34:50.071498 ============ LP4 DIFF to SE exit ============
666 17:34:50.071583 [ANA_INIT] <<<<<<<<<<<<<
667 17:34:50.075195 [Flow] Enable top DCM control >>>>>
668 17:34:50.078506 [Flow] Enable top DCM control <<<<<
669 17:34:50.082155 Enable DLL master slave shuffle
670 17:34:50.085912 ==============================================================
671 17:34:50.090201 Gating Mode config
672 17:34:50.093307 ==============================================================
673 17:34:50.096416 Config description:
674 17:34:50.106245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 17:34:50.113258 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 17:34:50.116688 SELPH_MODE 0: By rank 1: By Phase
677 17:34:50.122841 ==============================================================
678 17:34:50.126702 GAT_TRACK_EN = 1
679 17:34:50.129636 RX_GATING_MODE = 2
680 17:34:50.133329 RX_GATING_TRACK_MODE = 2
681 17:34:50.136608 SELPH_MODE = 1
682 17:34:50.136691 PICG_EARLY_EN = 1
683 17:34:50.139589 VALID_LAT_VALUE = 1
684 17:34:50.146830 ==============================================================
685 17:34:50.149808 Enter into Gating configuration >>>>
686 17:34:50.153236 Exit from Gating configuration <<<<
687 17:34:50.156741 Enter into DVFS_PRE_config >>>>>
688 17:34:50.166717 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 17:34:50.169492 Exit from DVFS_PRE_config <<<<<
690 17:34:50.172823 Enter into PICG configuration >>>>
691 17:34:50.176308 Exit from PICG configuration <<<<
692 17:34:50.180051 [RX_INPUT] configuration >>>>>
693 17:34:50.183040 [RX_INPUT] configuration <<<<<
694 17:34:50.186841 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 17:34:50.193158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 17:34:50.199804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 17:34:50.206701 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 17:34:50.212952 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 17:34:50.216838 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 17:34:50.222776 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 17:34:50.226225 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 17:34:50.229750 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 17:34:50.232958 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 17:34:50.239529 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 17:34:50.242704 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 17:34:50.245952 ===================================
707 17:34:50.249562 LPDDR4 DRAM CONFIGURATION
708 17:34:50.253087 ===================================
709 17:34:50.253171 EX_ROW_EN[0] = 0x0
710 17:34:50.256247 EX_ROW_EN[1] = 0x0
711 17:34:50.256345 LP4Y_EN = 0x0
712 17:34:50.259261 WORK_FSP = 0x0
713 17:34:50.259343 WL = 0x2
714 17:34:50.263043 RL = 0x2
715 17:34:50.263126 BL = 0x2
716 17:34:50.267064 RPST = 0x0
717 17:34:50.267148 RD_PRE = 0x0
718 17:34:50.270423 WR_PRE = 0x1
719 17:34:50.270505 WR_PST = 0x0
720 17:34:50.274110 DBI_WR = 0x0
721 17:34:50.274223 DBI_RD = 0x0
722 17:34:50.278255 OTF = 0x1
723 17:34:50.278340 ===================================
724 17:34:50.282057 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 17:34:50.289158 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 17:34:50.292163 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 17:34:50.296272 ===================================
728 17:34:50.296357 LPDDR4 DRAM CONFIGURATION
729 17:34:50.300111 ===================================
730 17:34:50.303192 EX_ROW_EN[0] = 0x10
731 17:34:50.303275 EX_ROW_EN[1] = 0x0
732 17:34:50.306816 LP4Y_EN = 0x0
733 17:34:50.306899 WORK_FSP = 0x0
734 17:34:50.310548 WL = 0x2
735 17:34:50.310630 RL = 0x2
736 17:34:50.314407 BL = 0x2
737 17:34:50.314492 RPST = 0x0
738 17:34:50.317879 RD_PRE = 0x0
739 17:34:50.317962 WR_PRE = 0x1
740 17:34:50.321929 WR_PST = 0x0
741 17:34:50.322012 DBI_WR = 0x0
742 17:34:50.325308 DBI_RD = 0x0
743 17:34:50.325392 OTF = 0x1
744 17:34:50.329117 ===================================
745 17:34:50.336206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 17:34:50.339806 nWR fixed to 40
747 17:34:50.339905 [ModeRegInit_LP4] CH0 RK0
748 17:34:50.343715 [ModeRegInit_LP4] CH0 RK1
749 17:34:50.347223 [ModeRegInit_LP4] CH1 RK0
750 17:34:50.347306 [ModeRegInit_LP4] CH1 RK1
751 17:34:50.351541 match AC timing 13
752 17:34:50.354903 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 17:34:50.358770 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 17:34:50.362692 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 17:34:50.366654 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 17:34:50.373670 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 17:34:50.373755 [EMI DOE] emi_dcm 0
758 17:34:50.377119 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 17:34:50.377203 ==
760 17:34:50.381092 Dram Type= 6, Freq= 0, CH_0, rank 0
761 17:34:50.385376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 17:34:50.385460 ==
763 17:34:50.393267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 17:34:50.396079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 17:34:50.407167 [CA 0] Center 38 (7~69) winsize 63
766 17:34:50.411044 [CA 1] Center 37 (7~68) winsize 62
767 17:34:50.414731 [CA 2] Center 35 (5~66) winsize 62
768 17:34:50.418420 [CA 3] Center 35 (5~66) winsize 62
769 17:34:50.421362 [CA 4] Center 34 (4~65) winsize 62
770 17:34:50.425179 [CA 5] Center 34 (4~65) winsize 62
771 17:34:50.425263
772 17:34:50.428905 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 17:34:50.428988
774 17:34:50.432108 [CATrainingPosCal] consider 1 rank data
775 17:34:50.435875 u2DelayCellTimex100 = 270/100 ps
776 17:34:50.439576 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 17:34:50.443200 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 17:34:50.446818 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 17:34:50.450866 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 17:34:50.451025 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 17:34:50.454422 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
782 17:34:50.454533
783 17:34:50.461605 CA PerBit enable=1, Macro0, CA PI delay=34
784 17:34:50.461690
785 17:34:50.461756 [CBTSetCACLKResult] CA Dly = 34
786 17:34:50.465381 CS Dly: 6 (0~37)
787 17:34:50.465498 ==
788 17:34:50.469288 Dram Type= 6, Freq= 0, CH_0, rank 1
789 17:34:50.472722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 17:34:50.472824 ==
791 17:34:50.476457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 17:34:50.483317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 17:34:50.493030 [CA 0] Center 38 (7~69) winsize 63
794 17:34:50.496773 [CA 1] Center 37 (7~68) winsize 62
795 17:34:50.500863 [CA 2] Center 35 (5~66) winsize 62
796 17:34:50.504542 [CA 3] Center 35 (5~66) winsize 62
797 17:34:50.508135 [CA 4] Center 34 (4~65) winsize 62
798 17:34:50.508230 [CA 5] Center 34 (4~65) winsize 62
799 17:34:50.508304
800 17:34:50.515330 [CmdBusTrainingLP45] Vref(ca) range 1: 30
801 17:34:50.515459
802 17:34:50.519191 [CATrainingPosCal] consider 2 rank data
803 17:34:50.519339 u2DelayCellTimex100 = 270/100 ps
804 17:34:50.522842 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 17:34:50.526388 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 17:34:50.530163 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 17:34:50.533959 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 17:34:50.537870 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 17:34:50.541406 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
810 17:34:50.541515
811 17:34:50.545048 CA PerBit enable=1, Macro0, CA PI delay=34
812 17:34:50.545159
813 17:34:50.548185 [CBTSetCACLKResult] CA Dly = 34
814 17:34:50.552011 CS Dly: 6 (0~37)
815 17:34:50.552094
816 17:34:50.555838 ----->DramcWriteLeveling(PI) begin...
817 17:34:50.555926 ==
818 17:34:50.558918 Dram Type= 6, Freq= 0, CH_0, rank 0
819 17:34:50.562066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 17:34:50.562151 ==
821 17:34:50.565703 Write leveling (Byte 0): 33 => 33
822 17:34:50.568899 Write leveling (Byte 1): 30 => 30
823 17:34:50.572563 DramcWriteLeveling(PI) end<-----
824 17:34:50.572645
825 17:34:50.572709 ==
826 17:34:50.575350 Dram Type= 6, Freq= 0, CH_0, rank 0
827 17:34:50.578552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 17:34:50.578634 ==
829 17:34:50.582211 [Gating] SW mode calibration
830 17:34:50.588920 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 17:34:50.595326 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 17:34:50.599031 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 17:34:50.602103 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 17:34:50.608820 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
835 17:34:50.612602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
836 17:34:50.615430 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 17:34:50.621782 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 17:34:50.625247 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 17:34:50.628646 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 17:34:50.632802 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 17:34:50.640240 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 17:34:50.643772 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 17:34:50.647188 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 17:34:50.650110 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 17:34:50.657738 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 17:34:50.660614 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 17:34:50.664373 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 17:34:50.667436 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 17:34:50.674557 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 17:34:50.677715 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
851 17:34:50.681139 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 17:34:50.687796 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 17:34:50.691150 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 17:34:50.694294 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 17:34:50.700944 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 17:34:50.704827 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 17:34:50.707711 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 17:34:50.714352 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 17:34:50.717557 0 9 12 | B1->B0 | 2625 2f2f | 1 0 | (1 1) (0 0)
860 17:34:50.721128 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 17:34:50.724410 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 17:34:50.730984 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 17:34:50.734525 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 17:34:50.737459 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 17:34:50.744089 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 17:34:50.747426 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
867 17:34:50.750967 0 10 12 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (0 0)
868 17:34:50.757991 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 17:34:50.761253 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 17:34:50.764240 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 17:34:50.770849 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 17:34:50.774536 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 17:34:50.777678 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 17:34:50.784780 0 11 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
875 17:34:50.788166 0 11 12 | B1->B0 | 3838 4040 | 1 0 | (0 0) (1 1)
876 17:34:50.791232 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 17:34:50.797500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 17:34:50.801223 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 17:34:50.804406 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 17:34:50.810818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 17:34:50.814139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 17:34:50.817627 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
883 17:34:50.823958 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
884 17:34:50.827640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 17:34:50.830776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 17:34:50.834060 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 17:34:50.840933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 17:34:50.843949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 17:34:50.847612 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 17:34:50.854338 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 17:34:50.857581 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 17:34:50.860959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 17:34:50.867256 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 17:34:50.870732 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 17:34:50.874486 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 17:34:50.880996 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 17:34:50.884311 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 17:34:50.887645 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
899 17:34:50.890583 Total UI for P1: 0, mck2ui 16
900 17:34:50.893849 best dqsien dly found for B0: ( 0, 14, 6)
901 17:34:50.900641 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
902 17:34:50.904429 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 17:34:50.907124 Total UI for P1: 0, mck2ui 16
904 17:34:50.910572 best dqsien dly found for B1: ( 0, 14, 12)
905 17:34:50.914167 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
906 17:34:50.917336 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
907 17:34:50.917419
908 17:34:50.920649 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
909 17:34:50.923837 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
910 17:34:50.927705 [Gating] SW calibration Done
911 17:34:50.927796 ==
912 17:34:50.930757 Dram Type= 6, Freq= 0, CH_0, rank 0
913 17:34:50.934262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 17:34:50.934397 ==
915 17:34:50.937492 RX Vref Scan: 0
916 17:34:50.937573
917 17:34:50.940785 RX Vref 0 -> 0, step: 1
918 17:34:50.940895
919 17:34:50.940995 RX Delay -130 -> 252, step: 16
920 17:34:50.947779 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
921 17:34:50.950928 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
922 17:34:50.954143 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
923 17:34:50.957520 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
924 17:34:50.960614 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
925 17:34:50.967244 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
926 17:34:50.970730 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
927 17:34:50.974267 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
928 17:34:50.977555 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
929 17:34:50.980595 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
930 17:34:50.987629 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
931 17:34:50.990686 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
932 17:34:50.993955 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
933 17:34:50.997381 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
934 17:34:51.001042 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
935 17:34:51.007840 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
936 17:34:51.007925 ==
937 17:34:51.010780 Dram Type= 6, Freq= 0, CH_0, rank 0
938 17:34:51.014419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 17:34:51.014503 ==
940 17:34:51.014568 DQS Delay:
941 17:34:51.017382 DQS0 = 0, DQS1 = 0
942 17:34:51.017464 DQM Delay:
943 17:34:51.021287 DQM0 = 84, DQM1 = 70
944 17:34:51.021402 DQ Delay:
945 17:34:51.024174 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
946 17:34:51.027645 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
947 17:34:51.030761 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
948 17:34:51.034106 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =85
949 17:34:51.034189
950 17:34:51.034254
951 17:34:51.034313 ==
952 17:34:51.037315 Dram Type= 6, Freq= 0, CH_0, rank 0
953 17:34:51.041487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 17:34:51.041590 ==
955 17:34:51.041688
956 17:34:51.041766
957 17:34:51.045223 TX Vref Scan disable
958 17:34:51.048501 == TX Byte 0 ==
959 17:34:51.051393 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
960 17:34:51.054728 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
961 17:34:51.058321 == TX Byte 1 ==
962 17:34:51.061578 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
963 17:34:51.065369 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
964 17:34:51.065453 ==
965 17:34:51.068418 Dram Type= 6, Freq= 0, CH_0, rank 0
966 17:34:51.071344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 17:34:51.074515 ==
968 17:34:51.086317 TX Vref=22, minBit 8, minWin=26, winSum=436
969 17:34:51.089332 TX Vref=24, minBit 14, minWin=26, winSum=436
970 17:34:51.092968 TX Vref=26, minBit 0, minWin=27, winSum=442
971 17:34:51.095875 TX Vref=28, minBit 14, minWin=26, winSum=440
972 17:34:51.099307 TX Vref=30, minBit 9, minWin=26, winSum=440
973 17:34:51.106582 TX Vref=32, minBit 9, minWin=27, winSum=443
974 17:34:51.109827 [TxChooseVref] Worse bit 9, Min win 27, Win sum 443, Final Vref 32
975 17:34:51.109941
976 17:34:51.112603 Final TX Range 1 Vref 32
977 17:34:51.112688
978 17:34:51.112753 ==
979 17:34:51.116101 Dram Type= 6, Freq= 0, CH_0, rank 0
980 17:34:51.119410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 17:34:51.122888 ==
982 17:34:51.122971
983 17:34:51.123035
984 17:34:51.123094 TX Vref Scan disable
985 17:34:51.126792 == TX Byte 0 ==
986 17:34:51.129713 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
987 17:34:51.136428 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
988 17:34:51.136512 == TX Byte 1 ==
989 17:34:51.139980 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
990 17:34:51.146153 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
991 17:34:51.146236
992 17:34:51.146301 [DATLAT]
993 17:34:51.146361 Freq=800, CH0 RK0
994 17:34:51.146420
995 17:34:51.149672 DATLAT Default: 0xa
996 17:34:51.149754 0, 0xFFFF, sum = 0
997 17:34:51.152692 1, 0xFFFF, sum = 0
998 17:34:51.152779 2, 0xFFFF, sum = 0
999 17:34:51.156294 3, 0xFFFF, sum = 0
1000 17:34:51.156377 4, 0xFFFF, sum = 0
1001 17:34:51.159878 5, 0xFFFF, sum = 0
1002 17:34:51.162934 6, 0xFFFF, sum = 0
1003 17:34:51.163018 7, 0xFFFF, sum = 0
1004 17:34:51.166397 8, 0xFFFF, sum = 0
1005 17:34:51.166481 9, 0x0, sum = 1
1006 17:34:51.166547 10, 0x0, sum = 2
1007 17:34:51.170140 11, 0x0, sum = 3
1008 17:34:51.170223 12, 0x0, sum = 4
1009 17:34:51.173175 best_step = 10
1010 17:34:51.173258
1011 17:34:51.173323 ==
1012 17:34:51.176283 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 17:34:51.180089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 17:34:51.180175 ==
1015 17:34:51.182969 RX Vref Scan: 1
1016 17:34:51.183050
1017 17:34:51.183115 Set Vref Range= 32 -> 127
1018 17:34:51.183175
1019 17:34:51.186312 RX Vref 32 -> 127, step: 1
1020 17:34:51.186394
1021 17:34:51.189656 RX Delay -111 -> 252, step: 8
1022 17:34:51.189738
1023 17:34:51.192986 Set Vref, RX VrefLevel [Byte0]: 32
1024 17:34:51.196202 [Byte1]: 32
1025 17:34:51.196288
1026 17:34:51.199631 Set Vref, RX VrefLevel [Byte0]: 33
1027 17:34:51.203269 [Byte1]: 33
1028 17:34:51.206811
1029 17:34:51.206891 Set Vref, RX VrefLevel [Byte0]: 34
1030 17:34:51.210102 [Byte1]: 34
1031 17:34:51.214908
1032 17:34:51.214986 Set Vref, RX VrefLevel [Byte0]: 35
1033 17:34:51.217925 [Byte1]: 35
1034 17:34:51.222258
1035 17:34:51.222341 Set Vref, RX VrefLevel [Byte0]: 36
1036 17:34:51.225809 [Byte1]: 36
1037 17:34:51.230317
1038 17:34:51.230397 Set Vref, RX VrefLevel [Byte0]: 37
1039 17:34:51.233276 [Byte1]: 37
1040 17:34:51.237805
1041 17:34:51.237886 Set Vref, RX VrefLevel [Byte0]: 38
1042 17:34:51.240800 [Byte1]: 38
1043 17:34:51.245157
1044 17:34:51.245238 Set Vref, RX VrefLevel [Byte0]: 39
1045 17:34:51.248735 [Byte1]: 39
1046 17:34:51.252688
1047 17:34:51.252768 Set Vref, RX VrefLevel [Byte0]: 40
1048 17:34:51.256438 [Byte1]: 40
1049 17:34:51.260210
1050 17:34:51.260290 Set Vref, RX VrefLevel [Byte0]: 41
1051 17:34:51.264075 [Byte1]: 41
1052 17:34:51.268295
1053 17:34:51.268402 Set Vref, RX VrefLevel [Byte0]: 42
1054 17:34:51.271191 [Byte1]: 42
1055 17:34:51.275547
1056 17:34:51.275627 Set Vref, RX VrefLevel [Byte0]: 43
1057 17:34:51.279126 [Byte1]: 43
1058 17:34:51.283094
1059 17:34:51.283197 Set Vref, RX VrefLevel [Byte0]: 44
1060 17:34:51.286930 [Byte1]: 44
1061 17:34:51.290633
1062 17:34:51.290745 Set Vref, RX VrefLevel [Byte0]: 45
1063 17:34:51.295003 [Byte1]: 45
1064 17:34:51.299274
1065 17:34:51.299356 Set Vref, RX VrefLevel [Byte0]: 46
1066 17:34:51.302230 [Byte1]: 46
1067 17:34:51.306744
1068 17:34:51.306824 Set Vref, RX VrefLevel [Byte0]: 47
1069 17:34:51.309469 [Byte1]: 47
1070 17:34:51.313988
1071 17:34:51.314071 Set Vref, RX VrefLevel [Byte0]: 48
1072 17:34:51.317487 [Byte1]: 48
1073 17:34:51.321261
1074 17:34:51.325041 Set Vref, RX VrefLevel [Byte0]: 49
1075 17:34:51.325122 [Byte1]: 49
1076 17:34:51.329251
1077 17:34:51.329332 Set Vref, RX VrefLevel [Byte0]: 50
1078 17:34:51.333133 [Byte1]: 50
1079 17:34:51.336831
1080 17:34:51.336951 Set Vref, RX VrefLevel [Byte0]: 51
1081 17:34:51.340058 [Byte1]: 51
1082 17:34:51.344736
1083 17:34:51.345193 Set Vref, RX VrefLevel [Byte0]: 52
1084 17:34:51.348712 [Byte1]: 52
1085 17:34:51.352742
1086 17:34:51.353199 Set Vref, RX VrefLevel [Byte0]: 53
1087 17:34:51.355806 [Byte1]: 53
1088 17:34:51.360323
1089 17:34:51.360781 Set Vref, RX VrefLevel [Byte0]: 54
1090 17:34:51.363986 [Byte1]: 54
1091 17:34:51.368039
1092 17:34:51.368457 Set Vref, RX VrefLevel [Byte0]: 55
1093 17:34:51.370874 [Byte1]: 55
1094 17:34:51.375676
1095 17:34:51.376218 Set Vref, RX VrefLevel [Byte0]: 56
1096 17:34:51.378762 [Byte1]: 56
1097 17:34:51.383056
1098 17:34:51.383511 Set Vref, RX VrefLevel [Byte0]: 57
1099 17:34:51.386447 [Byte1]: 57
1100 17:34:51.390480
1101 17:34:51.390898 Set Vref, RX VrefLevel [Byte0]: 58
1102 17:34:51.393914 [Byte1]: 58
1103 17:34:51.398139
1104 17:34:51.398556 Set Vref, RX VrefLevel [Byte0]: 59
1105 17:34:51.401462 [Byte1]: 59
1106 17:34:51.406381
1107 17:34:51.406951 Set Vref, RX VrefLevel [Byte0]: 60
1108 17:34:51.409277 [Byte1]: 60
1109 17:34:51.413576
1110 17:34:51.414124 Set Vref, RX VrefLevel [Byte0]: 61
1111 17:34:51.416797 [Byte1]: 61
1112 17:34:51.421307
1113 17:34:51.421944 Set Vref, RX VrefLevel [Byte0]: 62
1114 17:34:51.424290 [Byte1]: 62
1115 17:34:51.428690
1116 17:34:51.429212 Set Vref, RX VrefLevel [Byte0]: 63
1117 17:34:51.432470 [Byte1]: 63
1118 17:34:51.436351
1119 17:34:51.436891 Set Vref, RX VrefLevel [Byte0]: 64
1120 17:34:51.439766 [Byte1]: 64
1121 17:34:51.444249
1122 17:34:51.444688 Set Vref, RX VrefLevel [Byte0]: 65
1123 17:34:51.447958 [Byte1]: 65
1124 17:34:51.452186
1125 17:34:51.452793 Set Vref, RX VrefLevel [Byte0]: 66
1126 17:34:51.455158 [Byte1]: 66
1127 17:34:51.459450
1128 17:34:51.459912 Set Vref, RX VrefLevel [Byte0]: 67
1129 17:34:51.462835 [Byte1]: 67
1130 17:34:51.466954
1131 17:34:51.467630 Set Vref, RX VrefLevel [Byte0]: 68
1132 17:34:51.470158 [Byte1]: 68
1133 17:34:51.474366
1134 17:34:51.477849 Set Vref, RX VrefLevel [Byte0]: 69
1135 17:34:51.481053 [Byte1]: 69
1136 17:34:51.481474
1137 17:34:51.484936 Set Vref, RX VrefLevel [Byte0]: 70
1138 17:34:51.488021 [Byte1]: 70
1139 17:34:51.488623
1140 17:34:51.491154 Set Vref, RX VrefLevel [Byte0]: 71
1141 17:34:51.494864 [Byte1]: 71
1142 17:34:51.495522
1143 17:34:51.497644 Set Vref, RX VrefLevel [Byte0]: 72
1144 17:34:51.501026 [Byte1]: 72
1145 17:34:51.505261
1146 17:34:51.505561 Set Vref, RX VrefLevel [Byte0]: 73
1147 17:34:51.508513 [Byte1]: 73
1148 17:34:51.513478
1149 17:34:51.513773 Set Vref, RX VrefLevel [Byte0]: 74
1150 17:34:51.515909 [Byte1]: 74
1151 17:34:51.520535
1152 17:34:51.520861 Set Vref, RX VrefLevel [Byte0]: 75
1153 17:34:51.523771 [Byte1]: 75
1154 17:34:51.528614
1155 17:34:51.529022 Set Vref, RX VrefLevel [Byte0]: 76
1156 17:34:51.531548 [Byte1]: 76
1157 17:34:51.535665
1158 17:34:51.536078 Set Vref, RX VrefLevel [Byte0]: 77
1159 17:34:51.539335 [Byte1]: 77
1160 17:34:51.543801
1161 17:34:51.544119 Set Vref, RX VrefLevel [Byte0]: 78
1162 17:34:51.546937 [Byte1]: 78
1163 17:34:51.550837
1164 17:34:51.551202 Set Vref, RX VrefLevel [Byte0]: 79
1165 17:34:51.554247 [Byte1]: 79
1166 17:34:51.558663
1167 17:34:51.558772 Final RX Vref Byte 0 = 59 to rank0
1168 17:34:51.562059 Final RX Vref Byte 1 = 63 to rank0
1169 17:34:51.565167 Final RX Vref Byte 0 = 59 to rank1
1170 17:34:51.568258 Final RX Vref Byte 1 = 63 to rank1==
1171 17:34:51.571917 Dram Type= 6, Freq= 0, CH_0, rank 0
1172 17:34:51.578426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1173 17:34:51.578531 ==
1174 17:34:51.578635 DQS Delay:
1175 17:34:51.578723 DQS0 = 0, DQS1 = 0
1176 17:34:51.581631 DQM Delay:
1177 17:34:51.581719 DQM0 = 82, DQM1 = 68
1178 17:34:51.585231 DQ Delay:
1179 17:34:51.588188 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1180 17:34:51.591639 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1181 17:34:51.591720 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1182 17:34:51.598457 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1183 17:34:51.598555
1184 17:34:51.598620
1185 17:34:51.604922 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1186 17:34:51.608205 CH0 RK0: MR19=606, MR18=2424
1187 17:34:51.614767 CH0_RK0: MR19=0x606, MR18=0x2424, DQSOSC=400, MR23=63, INC=92, DEC=61
1188 17:34:51.614880
1189 17:34:51.618591 ----->DramcWriteLeveling(PI) begin...
1190 17:34:51.618704 ==
1191 17:34:51.621686 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 17:34:51.625152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 17:34:51.625267 ==
1194 17:34:51.628239 Write leveling (Byte 0): 33 => 33
1195 17:34:51.631827 Write leveling (Byte 1): 31 => 31
1196 17:34:51.634942 DramcWriteLeveling(PI) end<-----
1197 17:34:51.635072
1198 17:34:51.635189 ==
1199 17:34:51.638469 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 17:34:51.641522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 17:34:51.641683 ==
1202 17:34:51.645297 [Gating] SW mode calibration
1203 17:34:51.651876 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1204 17:34:51.658797 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1205 17:34:51.661761 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1206 17:34:51.665354 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1207 17:34:51.672584 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1208 17:34:51.675698 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 17:34:51.678918 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 17:34:51.685690 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 17:34:51.688727 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 17:34:51.692361 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 17:34:51.699067 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 17:34:51.702136 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 17:34:51.705819 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 17:34:51.709156 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 17:34:51.717118 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 17:34:51.759479 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 17:34:51.759831 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 17:34:51.760075 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 17:34:51.760571 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 17:34:51.760811 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1223 17:34:51.761071 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 17:34:51.761293 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 17:34:51.761502 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 17:34:51.761751 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 17:34:51.761965 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 17:34:51.803268 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 17:34:51.803566 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 17:34:51.803669 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 17:34:51.803763 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
1232 17:34:51.803880 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1233 17:34:51.803959 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 17:34:51.804090 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 17:34:51.804150 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 17:34:51.804221 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 17:34:51.804462 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 17:34:51.830934 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1239 17:34:51.831021 0 10 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 0)
1240 17:34:51.831104 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 17:34:51.831364 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 17:34:51.831454 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 17:34:51.831534 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 17:34:51.834540 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 17:34:51.838270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 17:34:51.841049 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 17:34:51.844811 0 11 8 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)
1248 17:34:51.851379 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1249 17:34:51.855011 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 17:34:51.857998 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 17:34:51.864535 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 17:34:51.868427 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 17:34:51.871987 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 17:34:51.878928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 17:34:51.882775 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1256 17:34:51.887032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1257 17:34:51.890088 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 17:34:51.893539 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 17:34:51.900928 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 17:34:51.904056 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 17:34:51.907740 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 17:34:51.910709 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 17:34:51.917469 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 17:34:51.920797 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 17:34:51.924484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 17:34:51.930739 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 17:34:51.934317 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 17:34:51.937447 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 17:34:51.944210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 17:34:51.947720 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1271 17:34:51.950821 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1272 17:34:51.954216 Total UI for P1: 0, mck2ui 16
1273 17:34:51.957290 best dqsien dly found for B0: ( 0, 14, 4)
1274 17:34:51.963976 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 17:34:51.964111 Total UI for P1: 0, mck2ui 16
1276 17:34:51.970561 best dqsien dly found for B1: ( 0, 14, 8)
1277 17:34:51.973893 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1278 17:34:51.977501 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1279 17:34:51.977582
1280 17:34:51.980645 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1281 17:34:51.984385 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1282 17:34:51.987369 [Gating] SW calibration Done
1283 17:34:51.987500 ==
1284 17:34:51.990698 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 17:34:51.994410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 17:34:51.994512 ==
1287 17:34:51.994607 RX Vref Scan: 0
1288 17:34:51.997461
1289 17:34:51.997598 RX Vref 0 -> 0, step: 1
1290 17:34:51.997667
1291 17:34:52.000628 RX Delay -130 -> 252, step: 16
1292 17:34:52.004259 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1293 17:34:52.007349 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1294 17:34:52.014264 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1295 17:34:52.017668 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1296 17:34:52.021014 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1297 17:34:52.024029 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1298 17:34:52.027714 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1299 17:34:52.034280 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1300 17:34:52.037342 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1301 17:34:52.041071 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1302 17:34:52.044455 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
1303 17:34:52.047539 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1304 17:34:52.054520 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1305 17:34:52.057319 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1306 17:34:52.061062 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1307 17:34:52.064046 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1308 17:34:52.064224 ==
1309 17:34:52.067614 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 17:34:52.074601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 17:34:52.074841 ==
1312 17:34:52.075028 DQS Delay:
1313 17:34:52.077535 DQS0 = 0, DQS1 = 0
1314 17:34:52.077831 DQM Delay:
1315 17:34:52.078065 DQM0 = 80, DQM1 = 68
1316 17:34:52.081026 DQ Delay:
1317 17:34:52.084340 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1318 17:34:52.087732 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1319 17:34:52.091140 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1320 17:34:52.094197 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
1321 17:34:52.094803
1322 17:34:52.095282
1323 17:34:52.095698 ==
1324 17:34:52.097625 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 17:34:52.101352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 17:34:52.101813 ==
1327 17:34:52.102173
1328 17:34:52.102505
1329 17:34:52.104450 TX Vref Scan disable
1330 17:34:52.104905 == TX Byte 0 ==
1331 17:34:52.111274 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1332 17:34:52.114882 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1333 17:34:52.115319 == TX Byte 1 ==
1334 17:34:52.121518 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1335 17:34:52.125025 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1336 17:34:52.125483 ==
1337 17:34:52.128190 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 17:34:52.130971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 17:34:52.131487 ==
1340 17:34:52.145399 TX Vref=22, minBit 9, minWin=26, winSum=432
1341 17:34:52.148605 TX Vref=24, minBit 0, minWin=27, winSum=438
1342 17:34:52.151747 TX Vref=26, minBit 1, minWin=27, winSum=440
1343 17:34:52.155054 TX Vref=28, minBit 1, minWin=27, winSum=439
1344 17:34:52.158583 TX Vref=30, minBit 1, minWin=27, winSum=442
1345 17:34:52.161484 TX Vref=32, minBit 2, minWin=27, winSum=440
1346 17:34:52.168487 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 30
1347 17:34:52.168902
1348 17:34:52.171892 Final TX Range 1 Vref 30
1349 17:34:52.172306
1350 17:34:52.172626 ==
1351 17:34:52.174976 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 17:34:52.178148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 17:34:52.178442 ==
1354 17:34:52.178673
1355 17:34:52.181423
1356 17:34:52.181643 TX Vref Scan disable
1357 17:34:52.184865 == TX Byte 0 ==
1358 17:34:52.188144 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1359 17:34:52.191637 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1360 17:34:52.195042 == TX Byte 1 ==
1361 17:34:52.198369 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1362 17:34:52.201650 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1363 17:34:52.204835
1364 17:34:52.205014 [DATLAT]
1365 17:34:52.205156 Freq=800, CH0 RK1
1366 17:34:52.205289
1367 17:34:52.208581 DATLAT Default: 0xa
1368 17:34:52.208761 0, 0xFFFF, sum = 0
1369 17:34:52.211428 1, 0xFFFF, sum = 0
1370 17:34:52.211684 2, 0xFFFF, sum = 0
1371 17:34:52.214712 3, 0xFFFF, sum = 0
1372 17:34:52.214881 4, 0xFFFF, sum = 0
1373 17:34:52.218456 5, 0xFFFF, sum = 0
1374 17:34:52.218637 6, 0xFFFF, sum = 0
1375 17:34:52.221425 7, 0xFFFF, sum = 0
1376 17:34:52.224650 8, 0xFFFF, sum = 0
1377 17:34:52.224834 9, 0x0, sum = 1
1378 17:34:52.224980 10, 0x0, sum = 2
1379 17:34:52.228321 11, 0x0, sum = 3
1380 17:34:52.228536 12, 0x0, sum = 4
1381 17:34:52.231357 best_step = 10
1382 17:34:52.231564
1383 17:34:52.231704 ==
1384 17:34:52.234918 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 17:34:52.238563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 17:34:52.238747 ==
1387 17:34:52.241682 RX Vref Scan: 0
1388 17:34:52.241858
1389 17:34:52.241997 RX Vref 0 -> 0, step: 1
1390 17:34:52.242131
1391 17:34:52.244990 RX Delay -111 -> 252, step: 8
1392 17:34:52.251369 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1393 17:34:52.255045 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1394 17:34:52.258222 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1395 17:34:52.261293 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1396 17:34:52.264514 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1397 17:34:52.271517 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1398 17:34:52.274692 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1399 17:34:52.278225 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1400 17:34:52.281495 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1401 17:34:52.284660 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1402 17:34:52.291678 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1403 17:34:52.294383 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1404 17:34:52.297846 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1405 17:34:52.301376 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1406 17:34:52.305358 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1407 17:34:52.311573 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1408 17:34:52.311986 ==
1409 17:34:52.315453 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 17:34:52.318489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 17:34:52.319096 ==
1412 17:34:52.319665 DQS Delay:
1413 17:34:52.321715 DQS0 = 0, DQS1 = 0
1414 17:34:52.322240 DQM Delay:
1415 17:34:52.325526 DQM0 = 78, DQM1 = 69
1416 17:34:52.326099 DQ Delay:
1417 17:34:52.328603 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1418 17:34:52.331684 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1419 17:34:52.335323 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1420 17:34:52.338424 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1421 17:34:52.338882
1422 17:34:52.339223
1423 17:34:52.345291 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1424 17:34:52.348291 CH0 RK1: MR19=606, MR18=421D
1425 17:34:52.355277 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1426 17:34:52.358610 [RxdqsGatingPostProcess] freq 800
1427 17:34:52.365145 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1428 17:34:52.368333 Pre-setting of DQS Precalculation
1429 17:34:52.372031 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1430 17:34:52.372507 ==
1431 17:34:52.374811 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 17:34:52.378667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 17:34:52.379235 ==
1434 17:34:52.385404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1435 17:34:52.391842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1436 17:34:52.400278 [CA 0] Center 36 (6~67) winsize 62
1437 17:34:52.403528 [CA 1] Center 36 (6~67) winsize 62
1438 17:34:52.406622 [CA 2] Center 35 (5~65) winsize 61
1439 17:34:52.410087 [CA 3] Center 34 (4~64) winsize 61
1440 17:34:52.413296 [CA 4] Center 34 (4~65) winsize 62
1441 17:34:52.416875 [CA 5] Center 33 (3~64) winsize 62
1442 17:34:52.417325
1443 17:34:52.419881 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1444 17:34:52.420333
1445 17:34:52.423556 [CATrainingPosCal] consider 1 rank data
1446 17:34:52.426626 u2DelayCellTimex100 = 270/100 ps
1447 17:34:52.429888 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1448 17:34:52.433656 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1449 17:34:52.439872 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1450 17:34:52.443626 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1451 17:34:52.446686 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1452 17:34:52.450290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1453 17:34:52.450727
1454 17:34:52.453388 CA PerBit enable=1, Macro0, CA PI delay=33
1455 17:34:52.453817
1456 17:34:52.456538 [CBTSetCACLKResult] CA Dly = 33
1457 17:34:52.456993 CS Dly: 5 (0~36)
1458 17:34:52.460039 ==
1459 17:34:52.460607 Dram Type= 6, Freq= 0, CH_1, rank 1
1460 17:34:52.466975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 17:34:52.467611 ==
1462 17:34:52.469934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 17:34:52.476826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 17:34:52.486893 [CA 0] Center 36 (6~67) winsize 62
1465 17:34:52.490034 [CA 1] Center 36 (6~67) winsize 62
1466 17:34:52.492777 [CA 2] Center 34 (4~65) winsize 62
1467 17:34:52.496258 [CA 3] Center 34 (4~64) winsize 61
1468 17:34:52.499309 [CA 4] Center 34 (4~65) winsize 62
1469 17:34:52.502707 [CA 5] Center 33 (3~64) winsize 62
1470 17:34:52.503278
1471 17:34:52.506215 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1472 17:34:52.506734
1473 17:34:52.509837 [CATrainingPosCal] consider 2 rank data
1474 17:34:52.513301 u2DelayCellTimex100 = 270/100 ps
1475 17:34:52.516481 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1476 17:34:52.519320 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1477 17:34:52.526536 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1478 17:34:52.529745 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1479 17:34:52.533610 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1480 17:34:52.536973 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1481 17:34:52.537566
1482 17:34:52.540758 CA PerBit enable=1, Macro0, CA PI delay=33
1483 17:34:52.541366
1484 17:34:52.544322 [CBTSetCACLKResult] CA Dly = 33
1485 17:34:52.544485 CS Dly: 5 (0~37)
1486 17:34:52.544571
1487 17:34:52.548418 ----->DramcWriteLeveling(PI) begin...
1488 17:34:52.548530 ==
1489 17:34:52.551698 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 17:34:52.555526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1491 17:34:52.555644 ==
1492 17:34:52.559117 Write leveling (Byte 0): 30 => 30
1493 17:34:52.562948 Write leveling (Byte 1): 31 => 31
1494 17:34:52.563034 DramcWriteLeveling(PI) end<-----
1495 17:34:52.566685
1496 17:34:52.566803 ==
1497 17:34:52.566908 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 17:34:52.573394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 17:34:52.573506 ==
1500 17:34:52.573608 [Gating] SW mode calibration
1501 17:34:52.583522 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1502 17:34:52.586606 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1503 17:34:52.590519 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1504 17:34:52.596621 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 17:34:52.600297 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1506 17:34:52.603734 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 17:34:52.610377 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 17:34:52.613511 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 17:34:52.617078 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 17:34:52.623555 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 17:34:52.627079 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 17:34:52.630395 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 17:34:52.636721 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 17:34:52.640334 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 17:34:52.643344 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 17:34:52.650622 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 17:34:52.653647 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 17:34:52.657203 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 17:34:52.663770 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 17:34:52.666798 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1521 17:34:52.670533 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1522 17:34:52.677157 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1523 17:34:52.680051 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 17:34:52.683785 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 17:34:52.686853 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 17:34:52.693699 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 17:34:52.696655 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 17:34:52.700236 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 17:34:52.706820 0 9 8 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
1530 17:34:52.709967 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 17:34:52.713303 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 17:34:52.720333 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 17:34:52.723389 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 17:34:52.727026 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 17:34:52.733719 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 17:34:52.736581 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1537 17:34:52.740521 0 10 8 | B1->B0 | 2e2e 2e2e | 0 1 | (1 0) (1 0)
1538 17:34:52.746572 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 17:34:52.750334 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 17:34:52.753449 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 17:34:52.759945 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 17:34:52.763380 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 17:34:52.766758 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 17:34:52.773615 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1545 17:34:52.776667 0 11 8 | B1->B0 | 3f3f 3838 | 1 0 | (0 0) (0 0)
1546 17:34:52.780281 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 17:34:52.787114 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 17:34:52.789949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 17:34:52.793179 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 17:34:52.796566 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 17:34:52.803758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 17:34:52.806632 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1553 17:34:52.810175 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 17:34:52.816349 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 17:34:52.819709 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 17:34:52.823339 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 17:34:52.829704 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 17:34:52.833269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 17:34:52.836348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 17:34:52.843451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 17:34:52.846701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 17:34:52.850071 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 17:34:52.856802 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 17:34:52.860067 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 17:34:52.863949 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 17:34:52.869764 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 17:34:52.873496 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 17:34:52.876282 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 17:34:52.883016 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 17:34:52.883123 Total UI for P1: 0, mck2ui 16
1571 17:34:52.890179 best dqsien dly found for B0: ( 0, 14, 6)
1572 17:34:52.890284 Total UI for P1: 0, mck2ui 16
1573 17:34:52.893280 best dqsien dly found for B1: ( 0, 14, 6)
1574 17:34:52.899971 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1575 17:34:52.903134 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1576 17:34:52.903214
1577 17:34:52.906648 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1578 17:34:52.910074 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1579 17:34:52.912950 [Gating] SW calibration Done
1580 17:34:52.913034 ==
1581 17:34:52.916484 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 17:34:52.919501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 17:34:52.919608 ==
1584 17:34:52.923260 RX Vref Scan: 0
1585 17:34:52.923366
1586 17:34:52.923473 RX Vref 0 -> 0, step: 1
1587 17:34:52.923572
1588 17:34:52.926766 RX Delay -130 -> 252, step: 16
1589 17:34:52.929938 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1590 17:34:52.936259 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1591 17:34:52.939406 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1592 17:34:52.943040 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1593 17:34:52.946149 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1594 17:34:52.949439 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1595 17:34:52.952979 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1596 17:34:52.959648 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1597 17:34:52.962761 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1598 17:34:52.966179 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1599 17:34:52.969803 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1600 17:34:52.973066 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1601 17:34:52.979791 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1602 17:34:52.982970 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1603 17:34:52.985932 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1604 17:34:52.989673 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1605 17:34:52.989790 ==
1606 17:34:52.992703 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 17:34:52.999432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 17:34:52.999518 ==
1609 17:34:52.999586 DQS Delay:
1610 17:34:53.002768 DQS0 = 0, DQS1 = 0
1611 17:34:53.002847 DQM Delay:
1612 17:34:53.002920 DQM0 = 81, DQM1 = 73
1613 17:34:53.006305 DQ Delay:
1614 17:34:53.009312 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1615 17:34:53.012985 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1616 17:34:53.016129 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1617 17:34:53.019639 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1618 17:34:53.019716
1619 17:34:53.019796
1620 17:34:53.019883 ==
1621 17:34:53.022688 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 17:34:53.026143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 17:34:53.026252 ==
1624 17:34:53.026344
1625 17:34:53.026432
1626 17:34:53.029763 TX Vref Scan disable
1627 17:34:53.029842 == TX Byte 0 ==
1628 17:34:53.036072 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1629 17:34:53.039883 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1630 17:34:53.039961 == TX Byte 1 ==
1631 17:34:53.046541 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1632 17:34:53.049729 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1633 17:34:53.049854 ==
1634 17:34:53.052849 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 17:34:53.056346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 17:34:53.056421 ==
1637 17:34:53.070293 TX Vref=22, minBit 1, minWin=26, winSum=437
1638 17:34:53.073901 TX Vref=24, minBit 1, minWin=26, winSum=439
1639 17:34:53.077004 TX Vref=26, minBit 2, minWin=27, winSum=442
1640 17:34:53.080437 TX Vref=28, minBit 5, minWin=27, winSum=444
1641 17:34:53.083342 TX Vref=30, minBit 9, minWin=27, winSum=450
1642 17:34:53.087239 TX Vref=32, minBit 8, minWin=27, winSum=448
1643 17:34:53.093897 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 30
1644 17:34:53.094031
1645 17:34:53.096958 Final TX Range 1 Vref 30
1646 17:34:53.097102
1647 17:34:53.097229 ==
1648 17:34:53.100246 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 17:34:53.103839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 17:34:53.104002 ==
1651 17:34:53.104106
1652 17:34:53.104206
1653 17:34:53.107175 TX Vref Scan disable
1654 17:34:53.110902 == TX Byte 0 ==
1655 17:34:53.114579 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1656 17:34:53.117861 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1657 17:34:53.121167 == TX Byte 1 ==
1658 17:34:53.124233 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1659 17:34:53.127812 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1660 17:34:53.128120
1661 17:34:53.131753 [DATLAT]
1662 17:34:53.132047 Freq=800, CH1 RK0
1663 17:34:53.132306
1664 17:34:53.134741 DATLAT Default: 0xa
1665 17:34:53.135141 0, 0xFFFF, sum = 0
1666 17:34:53.137806 1, 0xFFFF, sum = 0
1667 17:34:53.138338 2, 0xFFFF, sum = 0
1668 17:34:53.141004 3, 0xFFFF, sum = 0
1669 17:34:53.141112 4, 0xFFFF, sum = 0
1670 17:34:53.144593 5, 0xFFFF, sum = 0
1671 17:34:53.144676 6, 0xFFFF, sum = 0
1672 17:34:53.147485 7, 0xFFFF, sum = 0
1673 17:34:53.147596 8, 0xFFFF, sum = 0
1674 17:34:53.151262 9, 0x0, sum = 1
1675 17:34:53.151395 10, 0x0, sum = 2
1676 17:34:53.154400 11, 0x0, sum = 3
1677 17:34:53.154506 12, 0x0, sum = 4
1678 17:34:53.154602 best_step = 10
1679 17:34:53.157692
1680 17:34:53.157770 ==
1681 17:34:53.161004 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 17:34:53.164141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 17:34:53.164264 ==
1684 17:34:53.164380 RX Vref Scan: 1
1685 17:34:53.164493
1686 17:34:53.168087 Set Vref Range= 32 -> 127
1687 17:34:53.168231
1688 17:34:53.171293 RX Vref 32 -> 127, step: 1
1689 17:34:53.171466
1690 17:34:53.174900 RX Delay -95 -> 252, step: 8
1691 17:34:53.175022
1692 17:34:53.177976 Set Vref, RX VrefLevel [Byte0]: 32
1693 17:34:53.181536 [Byte1]: 32
1694 17:34:53.181687
1695 17:34:53.184824 Set Vref, RX VrefLevel [Byte0]: 33
1696 17:34:53.187787 [Byte1]: 33
1697 17:34:53.187958
1698 17:34:53.191085 Set Vref, RX VrefLevel [Byte0]: 34
1699 17:34:53.194180 [Byte1]: 34
1700 17:34:53.197988
1701 17:34:53.198423 Set Vref, RX VrefLevel [Byte0]: 35
1702 17:34:53.201653 [Byte1]: 35
1703 17:34:53.206006
1704 17:34:53.206441 Set Vref, RX VrefLevel [Byte0]: 36
1705 17:34:53.209310 [Byte1]: 36
1706 17:34:53.213696
1707 17:34:53.214130 Set Vref, RX VrefLevel [Byte0]: 37
1708 17:34:53.217201 [Byte1]: 37
1709 17:34:53.221481
1710 17:34:53.222017 Set Vref, RX VrefLevel [Byte0]: 38
1711 17:34:53.224971 [Byte1]: 38
1712 17:34:53.228902
1713 17:34:53.229449 Set Vref, RX VrefLevel [Byte0]: 39
1714 17:34:53.231758 [Byte1]: 39
1715 17:34:53.236248
1716 17:34:53.236894 Set Vref, RX VrefLevel [Byte0]: 40
1717 17:34:53.239828 [Byte1]: 40
1718 17:34:53.243612
1719 17:34:53.244030 Set Vref, RX VrefLevel [Byte0]: 41
1720 17:34:53.247066 [Byte1]: 41
1721 17:34:53.251853
1722 17:34:53.252449 Set Vref, RX VrefLevel [Byte0]: 42
1723 17:34:53.255127 [Byte1]: 42
1724 17:34:53.258836
1725 17:34:53.259455 Set Vref, RX VrefLevel [Byte0]: 43
1726 17:34:53.262502 [Byte1]: 43
1727 17:34:53.267060
1728 17:34:53.267655 Set Vref, RX VrefLevel [Byte0]: 44
1729 17:34:53.269726 [Byte1]: 44
1730 17:34:53.274048
1731 17:34:53.274505 Set Vref, RX VrefLevel [Byte0]: 45
1732 17:34:53.277387 [Byte1]: 45
1733 17:34:53.281720
1734 17:34:53.282076 Set Vref, RX VrefLevel [Byte0]: 46
1735 17:34:53.284627 [Byte1]: 46
1736 17:34:53.288986
1737 17:34:53.289279 Set Vref, RX VrefLevel [Byte0]: 47
1738 17:34:53.292317 [Byte1]: 47
1739 17:34:53.296688
1740 17:34:53.296803 Set Vref, RX VrefLevel [Byte0]: 48
1741 17:34:53.299933 [Byte1]: 48
1742 17:34:53.304731
1743 17:34:53.304847 Set Vref, RX VrefLevel [Byte0]: 49
1744 17:34:53.307644 [Byte1]: 49
1745 17:34:53.311930
1746 17:34:53.312035 Set Vref, RX VrefLevel [Byte0]: 50
1747 17:34:53.315188 [Byte1]: 50
1748 17:34:53.319345
1749 17:34:53.319450 Set Vref, RX VrefLevel [Byte0]: 51
1750 17:34:53.323198 [Byte1]: 51
1751 17:34:53.327616
1752 17:34:53.327698 Set Vref, RX VrefLevel [Byte0]: 52
1753 17:34:53.330814 [Byte1]: 52
1754 17:34:53.334883
1755 17:34:53.334967 Set Vref, RX VrefLevel [Byte0]: 53
1756 17:34:53.338006 [Byte1]: 53
1757 17:34:53.342227
1758 17:34:53.342311 Set Vref, RX VrefLevel [Byte0]: 54
1759 17:34:53.345743 [Byte1]: 54
1760 17:34:53.349873
1761 17:34:53.349959 Set Vref, RX VrefLevel [Byte0]: 55
1762 17:34:53.353164 [Byte1]: 55
1763 17:34:53.357742
1764 17:34:53.357839 Set Vref, RX VrefLevel [Byte0]: 56
1765 17:34:53.360997 [Byte1]: 56
1766 17:34:53.365183
1767 17:34:53.365326 Set Vref, RX VrefLevel [Byte0]: 57
1768 17:34:53.368453 [Byte1]: 57
1769 17:34:53.372943
1770 17:34:53.373063 Set Vref, RX VrefLevel [Byte0]: 58
1771 17:34:53.376239 [Byte1]: 58
1772 17:34:53.380757
1773 17:34:53.380901 Set Vref, RX VrefLevel [Byte0]: 59
1774 17:34:53.383643 [Byte1]: 59
1775 17:34:53.387989
1776 17:34:53.388166 Set Vref, RX VrefLevel [Byte0]: 60
1777 17:34:53.391462 [Byte1]: 60
1778 17:34:53.395786
1779 17:34:53.395993 Set Vref, RX VrefLevel [Byte0]: 61
1780 17:34:53.399135 [Byte1]: 61
1781 17:34:53.403167
1782 17:34:53.403509 Set Vref, RX VrefLevel [Byte0]: 62
1783 17:34:53.406522 [Byte1]: 62
1784 17:34:53.410924
1785 17:34:53.411627 Set Vref, RX VrefLevel [Byte0]: 63
1786 17:34:53.414651 [Byte1]: 63
1787 17:34:53.418672
1788 17:34:53.419358 Set Vref, RX VrefLevel [Byte0]: 64
1789 17:34:53.421657 [Byte1]: 64
1790 17:34:53.425987
1791 17:34:53.426612 Set Vref, RX VrefLevel [Byte0]: 65
1792 17:34:53.429464 [Byte1]: 65
1793 17:34:53.433978
1794 17:34:53.434518 Set Vref, RX VrefLevel [Byte0]: 66
1795 17:34:53.436964 [Byte1]: 66
1796 17:34:53.441241
1797 17:34:53.441755 Set Vref, RX VrefLevel [Byte0]: 67
1798 17:34:53.445073 [Byte1]: 67
1799 17:34:53.449171
1800 17:34:53.449619 Set Vref, RX VrefLevel [Byte0]: 68
1801 17:34:53.452069 [Byte1]: 68
1802 17:34:53.456611
1803 17:34:53.457204 Set Vref, RX VrefLevel [Byte0]: 69
1804 17:34:53.460189 [Byte1]: 69
1805 17:34:53.464364
1806 17:34:53.464933 Set Vref, RX VrefLevel [Byte0]: 70
1807 17:34:53.467560 [Byte1]: 70
1808 17:34:53.471639
1809 17:34:53.472052 Set Vref, RX VrefLevel [Byte0]: 71
1810 17:34:53.475263 [Byte1]: 71
1811 17:34:53.479560
1812 17:34:53.480213 Set Vref, RX VrefLevel [Byte0]: 72
1813 17:34:53.482419 [Byte1]: 72
1814 17:34:53.486690
1815 17:34:53.487124 Set Vref, RX VrefLevel [Byte0]: 73
1816 17:34:53.490000 [Byte1]: 73
1817 17:34:53.494427
1818 17:34:53.494758 Set Vref, RX VrefLevel [Byte0]: 74
1819 17:34:53.497693 [Byte1]: 74
1820 17:34:53.501985
1821 17:34:53.502090 Set Vref, RX VrefLevel [Byte0]: 75
1822 17:34:53.505242 [Byte1]: 75
1823 17:34:53.509507
1824 17:34:53.509632 Final RX Vref Byte 0 = 59 to rank0
1825 17:34:53.513102 Final RX Vref Byte 1 = 55 to rank0
1826 17:34:53.516058 Final RX Vref Byte 0 = 59 to rank1
1827 17:34:53.519406 Final RX Vref Byte 1 = 55 to rank1==
1828 17:34:53.523050 Dram Type= 6, Freq= 0, CH_1, rank 0
1829 17:34:53.529205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 17:34:53.529319 ==
1831 17:34:53.529416 DQS Delay:
1832 17:34:53.529504 DQS0 = 0, DQS1 = 0
1833 17:34:53.532486 DQM Delay:
1834 17:34:53.532588 DQM0 = 81, DQM1 = 71
1835 17:34:53.535911 DQ Delay:
1836 17:34:53.539160 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1837 17:34:53.539277 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1838 17:34:53.542802 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1839 17:34:53.549085 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1840 17:34:53.549192
1841 17:34:53.549293
1842 17:34:53.556046 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1843 17:34:53.559543 CH1 RK0: MR19=606, MR18=131D
1844 17:34:53.566034 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1845 17:34:53.566148
1846 17:34:53.569682 ----->DramcWriteLeveling(PI) begin...
1847 17:34:53.569791 ==
1848 17:34:53.572833 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 17:34:53.576139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 17:34:53.576252 ==
1851 17:34:53.579270 Write leveling (Byte 0): 28 => 28
1852 17:34:53.582836 Write leveling (Byte 1): 27 => 27
1853 17:34:53.586065 DramcWriteLeveling(PI) end<-----
1854 17:34:53.586151
1855 17:34:53.586237 ==
1856 17:34:53.589876 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 17:34:53.592836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 17:34:53.592922 ==
1859 17:34:53.596263 [Gating] SW mode calibration
1860 17:34:53.602850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1861 17:34:53.609311 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1862 17:34:53.612307 0 6 0 | B1->B0 | 2323 2322 | 0 1 | (1 1) (1 0)
1863 17:34:53.615799 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1864 17:34:53.622251 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1865 17:34:53.626134 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 17:34:53.629254 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 17:34:53.636101 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 17:34:53.639370 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 17:34:53.642407 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 17:34:53.649363 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 17:34:53.652426 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 17:34:53.655655 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 17:34:53.662656 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 17:34:53.665470 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 17:34:53.668997 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 17:34:53.675320 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 17:34:53.678987 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 17:34:53.682145 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 17:34:53.689083 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1880 17:34:53.692136 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 17:34:53.695871 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 17:34:53.701852 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 17:34:53.705622 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 17:34:53.709150 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 17:34:53.716029 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 17:34:53.718954 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 17:34:53.722135 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1888 17:34:53.725788 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1889 17:34:53.732420 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 17:34:53.735607 0 9 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1891 17:34:53.738723 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 17:34:53.745541 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 17:34:53.749028 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 17:34:53.752366 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1895 17:34:53.759151 0 10 4 | B1->B0 | 3333 2e2e | 1 1 | (0 0) (0 0)
1896 17:34:53.762248 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1897 17:34:53.765443 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 17:34:53.772371 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 17:34:53.775380 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 17:34:53.778563 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 17:34:53.785622 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 17:34:53.789519 0 11 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1903 17:34:53.792701 0 11 4 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (1 1)
1904 17:34:53.798712 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
1905 17:34:53.802358 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 17:34:53.805601 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 17:34:53.809487 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 17:34:53.816224 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 17:34:53.819361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 17:34:53.822433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 17:34:53.829479 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1912 17:34:53.832491 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1913 17:34:53.835940 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 17:34:53.842586 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 17:34:53.845540 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 17:34:53.849010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 17:34:53.855832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 17:34:53.858857 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 17:34:53.862119 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 17:34:53.868663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 17:34:53.872361 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 17:34:53.875565 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 17:34:53.882096 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 17:34:53.885584 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 17:34:53.888764 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 17:34:53.895693 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 17:34:53.899216 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1928 17:34:53.902129 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1929 17:34:53.905287 Total UI for P1: 0, mck2ui 16
1930 17:34:53.909235 best dqsien dly found for B0: ( 0, 14, 4)
1931 17:34:53.912254 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 17:34:53.915305 Total UI for P1: 0, mck2ui 16
1933 17:34:53.918763 best dqsien dly found for B1: ( 0, 14, 6)
1934 17:34:53.922317 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1935 17:34:53.929269 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1936 17:34:53.929454
1937 17:34:53.932180 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1938 17:34:53.935459 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1939 17:34:53.938731 [Gating] SW calibration Done
1940 17:34:53.938941 ==
1941 17:34:53.942134 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 17:34:53.945559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 17:34:53.945765 ==
1944 17:34:53.945910 RX Vref Scan: 0
1945 17:34:53.946044
1946 17:34:53.949363 RX Vref 0 -> 0, step: 1
1947 17:34:53.949600
1948 17:34:53.952046 RX Delay -130 -> 252, step: 16
1949 17:34:53.955698 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1950 17:34:53.958554 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1951 17:34:53.965327 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1952 17:34:53.969052 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1953 17:34:53.972253 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1954 17:34:53.975284 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1955 17:34:53.978934 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1956 17:34:53.985723 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1957 17:34:53.988442 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1958 17:34:53.991796 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1959 17:34:53.995522 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1960 17:34:53.998635 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1961 17:34:54.005461 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1962 17:34:54.008958 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1963 17:34:54.011981 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1964 17:34:54.014918 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1965 17:34:54.015025 ==
1966 17:34:54.018700 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 17:34:54.025478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 17:34:54.025564 ==
1969 17:34:54.025630 DQS Delay:
1970 17:34:54.028400 DQS0 = 0, DQS1 = 0
1971 17:34:54.028483 DQM Delay:
1972 17:34:54.028549 DQM0 = 78, DQM1 = 71
1973 17:34:54.031794 DQ Delay:
1974 17:34:54.035086 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1975 17:34:54.038863 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1976 17:34:54.041955 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1977 17:34:54.045252 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1978 17:34:54.045333
1979 17:34:54.045397
1980 17:34:54.045457 ==
1981 17:34:54.048476 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 17:34:54.051982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 17:34:54.052083 ==
1984 17:34:54.052162
1985 17:34:54.052221
1986 17:34:54.055124 TX Vref Scan disable
1987 17:34:54.055205 == TX Byte 0 ==
1988 17:34:54.061682 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1989 17:34:54.065333 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1990 17:34:54.065415 == TX Byte 1 ==
1991 17:34:54.072241 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1992 17:34:54.075209 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1993 17:34:54.075330 ==
1994 17:34:54.078410 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 17:34:54.081744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 17:34:54.081861 ==
1997 17:34:54.095546 TX Vref=22, minBit 0, minWin=28, winSum=453
1998 17:34:54.099079 TX Vref=24, minBit 1, minWin=27, winSum=451
1999 17:34:54.102017 TX Vref=26, minBit 0, minWin=28, winSum=454
2000 17:34:54.105711 TX Vref=28, minBit 0, minWin=28, winSum=458
2001 17:34:54.108789 TX Vref=30, minBit 5, minWin=27, winSum=460
2002 17:34:54.115533 TX Vref=32, minBit 1, minWin=27, winSum=455
2003 17:34:54.119073 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
2004 17:34:54.119150
2005 17:34:54.122221 Final TX Range 1 Vref 28
2006 17:34:54.122297
2007 17:34:54.122399 ==
2008 17:34:54.125989 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 17:34:54.128842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 17:34:54.128924 ==
2011 17:34:54.128988
2012 17:34:54.132304
2013 17:34:54.132453 TX Vref Scan disable
2014 17:34:54.135351 == TX Byte 0 ==
2015 17:34:54.139026 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2016 17:34:54.142581 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2017 17:34:54.145597 == TX Byte 1 ==
2018 17:34:54.148957 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2019 17:34:54.152664 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2020 17:34:54.155423
2021 17:34:54.155517 [DATLAT]
2022 17:34:54.155581 Freq=800, CH1 RK1
2023 17:34:54.155641
2024 17:34:54.159169 DATLAT Default: 0xa
2025 17:34:54.159249 0, 0xFFFF, sum = 0
2026 17:34:54.162245 1, 0xFFFF, sum = 0
2027 17:34:54.162328 2, 0xFFFF, sum = 0
2028 17:34:54.165851 3, 0xFFFF, sum = 0
2029 17:34:54.165933 4, 0xFFFF, sum = 0
2030 17:34:54.169210 5, 0xFFFF, sum = 0
2031 17:34:54.172029 6, 0xFFFF, sum = 0
2032 17:34:54.172125 7, 0xFFFF, sum = 0
2033 17:34:54.175536 8, 0xFFFF, sum = 0
2034 17:34:54.175621 9, 0x0, sum = 1
2035 17:34:54.175687 10, 0x0, sum = 2
2036 17:34:54.178873 11, 0x0, sum = 3
2037 17:34:54.178955 12, 0x0, sum = 4
2038 17:34:54.182051 best_step = 10
2039 17:34:54.182131
2040 17:34:54.182195 ==
2041 17:34:54.185559 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 17:34:54.189182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 17:34:54.189263 ==
2044 17:34:54.192385 RX Vref Scan: 0
2045 17:34:54.192466
2046 17:34:54.192618 RX Vref 0 -> 0, step: 1
2047 17:34:54.192694
2048 17:34:54.195495 RX Delay -111 -> 252, step: 8
2049 17:34:54.202424 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2050 17:34:54.205705 iDelay=209, Bit 1, Center 68 (-55 ~ 192) 248
2051 17:34:54.208853 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2052 17:34:54.212176 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2053 17:34:54.215724 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2054 17:34:54.222749 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2055 17:34:54.225747 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2056 17:34:54.229010 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2057 17:34:54.232677 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2058 17:34:54.235846 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2059 17:34:54.242259 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2060 17:34:54.246028 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2061 17:34:54.249122 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2062 17:34:54.252434 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2063 17:34:54.255692 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2064 17:34:54.262430 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2065 17:34:54.262633 ==
2066 17:34:54.265395 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 17:34:54.268796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 17:34:54.268999 ==
2069 17:34:54.269157 DQS Delay:
2070 17:34:54.272615 DQS0 = 0, DQS1 = 0
2071 17:34:54.272815 DQM Delay:
2072 17:34:54.275538 DQM0 = 77, DQM1 = 74
2073 17:34:54.275738 DQ Delay:
2074 17:34:54.278683 DQ0 =80, DQ1 =68, DQ2 =68, DQ3 =72
2075 17:34:54.282514 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2076 17:34:54.285589 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2077 17:34:54.288926 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2078 17:34:54.289166
2079 17:34:54.289376
2080 17:34:54.295920 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2081 17:34:54.299060 CH1 RK1: MR19=606, MR18=1F37
2082 17:34:54.306020 CH1_RK1: MR19=0x606, MR18=0x1F37, DQSOSC=395, MR23=63, INC=94, DEC=63
2083 17:34:54.308764 [RxdqsGatingPostProcess] freq 800
2084 17:34:54.315669 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2085 17:34:54.319486 Pre-setting of DQS Precalculation
2086 17:34:54.322182 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2087 17:34:54.328848 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2088 17:34:54.335809 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2089 17:34:54.336019
2090 17:34:54.336228
2091 17:34:54.339492 [Calibration Summary] 1600 Mbps
2092 17:34:54.342423 CH 0, Rank 0
2093 17:34:54.342631 SW Impedance : PASS
2094 17:34:54.345505 DUTY Scan : NO K
2095 17:34:54.348715 ZQ Calibration : PASS
2096 17:34:54.348799 Jitter Meter : NO K
2097 17:34:54.352265 CBT Training : PASS
2098 17:34:54.355580 Write leveling : PASS
2099 17:34:54.355665 RX DQS gating : PASS
2100 17:34:54.358894 RX DQ/DQS(RDDQC) : PASS
2101 17:34:54.362056 TX DQ/DQS : PASS
2102 17:34:54.362143 RX DATLAT : PASS
2103 17:34:54.365454 RX DQ/DQS(Engine): PASS
2104 17:34:54.365539 TX OE : NO K
2105 17:34:54.368926 All Pass.
2106 17:34:54.369046
2107 17:34:54.369149 CH 0, Rank 1
2108 17:34:54.372342 SW Impedance : PASS
2109 17:34:54.372466 DUTY Scan : NO K
2110 17:34:54.375521 ZQ Calibration : PASS
2111 17:34:54.378964 Jitter Meter : NO K
2112 17:34:54.379069 CBT Training : PASS
2113 17:34:54.381914 Write leveling : PASS
2114 17:34:54.385715 RX DQS gating : PASS
2115 17:34:54.385830 RX DQ/DQS(RDDQC) : PASS
2116 17:34:54.388991 TX DQ/DQS : PASS
2117 17:34:54.392044 RX DATLAT : PASS
2118 17:34:54.392237 RX DQ/DQS(Engine): PASS
2119 17:34:54.395743 TX OE : NO K
2120 17:34:54.395882 All Pass.
2121 17:34:54.396023
2122 17:34:54.398855 CH 1, Rank 0
2123 17:34:54.399014 SW Impedance : PASS
2124 17:34:54.402114 DUTY Scan : NO K
2125 17:34:54.405568 ZQ Calibration : PASS
2126 17:34:54.405740 Jitter Meter : NO K
2127 17:34:54.408889 CBT Training : PASS
2128 17:34:54.412813 Write leveling : PASS
2129 17:34:54.413019 RX DQS gating : PASS
2130 17:34:54.415555 RX DQ/DQS(RDDQC) : PASS
2131 17:34:54.415822 TX DQ/DQS : PASS
2132 17:34:54.419080 RX DATLAT : PASS
2133 17:34:54.422747 RX DQ/DQS(Engine): PASS
2134 17:34:54.422955 TX OE : NO K
2135 17:34:54.425828 All Pass.
2136 17:34:54.426034
2137 17:34:54.426246 CH 1, Rank 1
2138 17:34:54.428989 SW Impedance : PASS
2139 17:34:54.429193 DUTY Scan : NO K
2140 17:34:54.432445 ZQ Calibration : PASS
2141 17:34:54.435693 Jitter Meter : NO K
2142 17:34:54.435910 CBT Training : PASS
2143 17:34:54.438877 Write leveling : PASS
2144 17:34:54.442424 RX DQS gating : PASS
2145 17:34:54.442631 RX DQ/DQS(RDDQC) : PASS
2146 17:34:54.445657 TX DQ/DQS : PASS
2147 17:34:54.451556 RX DATLAT : PASS
2148 17:34:54.451810 RX DQ/DQS(Engine): PASS
2149 17:34:54.452265 TX OE : NO K
2150 17:34:54.452470 All Pass.
2151 17:34:54.452649
2152 17:34:54.455447 DramC Write-DBI off
2153 17:34:54.459238 PER_BANK_REFRESH: Hybrid Mode
2154 17:34:54.459550 TX_TRACKING: ON
2155 17:34:54.462027 [GetDramInforAfterCalByMRR] Vendor 6.
2156 17:34:54.465237 [GetDramInforAfterCalByMRR] Revision 606.
2157 17:34:54.468964 [GetDramInforAfterCalByMRR] Revision 2 0.
2158 17:34:54.472370 MR0 0x3b3b
2159 17:34:54.472606 MR8 0x5151
2160 17:34:54.475701 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 17:34:54.475975
2162 17:34:54.476227 MR0 0x3b3b
2163 17:34:54.479106 MR8 0x5151
2164 17:34:54.481968 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 17:34:54.482204
2166 17:34:54.488731 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2167 17:34:54.495572 [FAST_K] Save calibration result to emmc
2168 17:34:54.498377 [FAST_K] Save calibration result to emmc
2169 17:34:54.498661 dram_init: config_dvfs: 1
2170 17:34:54.505288 dramc_set_vcore_voltage set vcore to 662500
2171 17:34:54.505533 Read voltage for 1200, 2
2172 17:34:54.505721 Vio18 = 0
2173 17:34:54.509089 Vcore = 662500
2174 17:34:54.509325 Vdram = 0
2175 17:34:54.509512 Vddq = 0
2176 17:34:54.512023 Vmddr = 0
2177 17:34:54.515879 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2178 17:34:54.522048 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2179 17:34:54.522129 MEM_TYPE=3, freq_sel=15
2180 17:34:54.525171 sv_algorithm_assistance_LP4_1600
2181 17:34:54.531689 ============ PULL DRAM RESETB DOWN ============
2182 17:34:54.535311 ========== PULL DRAM RESETB DOWN end =========
2183 17:34:54.538770 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2184 17:34:54.542158 ===================================
2185 17:34:54.545219 LPDDR4 DRAM CONFIGURATION
2186 17:34:54.548502 ===================================
2187 17:34:54.552198 EX_ROW_EN[0] = 0x0
2188 17:34:54.552303 EX_ROW_EN[1] = 0x0
2189 17:34:54.555157 LP4Y_EN = 0x0
2190 17:34:54.555260 WORK_FSP = 0x0
2191 17:34:54.558590 WL = 0x4
2192 17:34:54.558663 RL = 0x4
2193 17:34:54.561835 BL = 0x2
2194 17:34:54.561933 RPST = 0x0
2195 17:34:54.565365 RD_PRE = 0x0
2196 17:34:54.565468 WR_PRE = 0x1
2197 17:34:54.568583 WR_PST = 0x0
2198 17:34:54.568692 DBI_WR = 0x0
2199 17:34:54.571978 DBI_RD = 0x0
2200 17:34:54.572070 OTF = 0x1
2201 17:34:54.575261 ===================================
2202 17:34:54.578347 ===================================
2203 17:34:54.581976 ANA top config
2204 17:34:54.585176 ===================================
2205 17:34:54.585380 DLL_ASYNC_EN = 0
2206 17:34:54.588343 ALL_SLAVE_EN = 0
2207 17:34:54.591966 NEW_RANK_MODE = 1
2208 17:34:54.594940 DLL_IDLE_MODE = 1
2209 17:34:54.598837 LP45_APHY_COMB_EN = 1
2210 17:34:54.598946 TX_ODT_DIS = 1
2211 17:34:54.601784 NEW_8X_MODE = 1
2212 17:34:54.605397 ===================================
2213 17:34:54.608367 ===================================
2214 17:34:54.611513 data_rate = 2400
2215 17:34:54.615423 CKR = 1
2216 17:34:54.618489 DQ_P2S_RATIO = 8
2217 17:34:54.621488 ===================================
2218 17:34:54.625269 CA_P2S_RATIO = 8
2219 17:34:54.625413 DQ_CA_OPEN = 0
2220 17:34:54.628017 DQ_SEMI_OPEN = 0
2221 17:34:54.631490 CA_SEMI_OPEN = 0
2222 17:34:54.635494 CA_FULL_RATE = 0
2223 17:34:54.638257 DQ_CKDIV4_EN = 0
2224 17:34:54.638355 CA_CKDIV4_EN = 0
2225 17:34:54.641420 CA_PREDIV_EN = 0
2226 17:34:54.645016 PH8_DLY = 17
2227 17:34:54.648398 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2228 17:34:54.651707 DQ_AAMCK_DIV = 4
2229 17:34:54.654742 CA_AAMCK_DIV = 4
2230 17:34:54.658444 CA_ADMCK_DIV = 4
2231 17:34:54.658551 DQ_TRACK_CA_EN = 0
2232 17:34:54.661561 CA_PICK = 1200
2233 17:34:54.664664 CA_MCKIO = 1200
2234 17:34:54.668282 MCKIO_SEMI = 0
2235 17:34:54.671682 PLL_FREQ = 2366
2236 17:34:54.674925 DQ_UI_PI_RATIO = 32
2237 17:34:54.678595 CA_UI_PI_RATIO = 0
2238 17:34:54.681505 ===================================
2239 17:34:54.681590 ===================================
2240 17:34:54.685016 memory_type:LPDDR4
2241 17:34:54.688401 GP_NUM : 10
2242 17:34:54.688483 SRAM_EN : 1
2243 17:34:54.691819 MD32_EN : 0
2244 17:34:54.694953 ===================================
2245 17:34:54.698367 [ANA_INIT] >>>>>>>>>>>>>>
2246 17:34:54.701900 <<<<<< [CONFIGURE PHASE]: ANA_TX
2247 17:34:54.705120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2248 17:34:54.708034 ===================================
2249 17:34:54.708118 data_rate = 2400,PCW = 0X5b00
2250 17:34:54.711582 ===================================
2251 17:34:54.714767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2252 17:34:54.721668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 17:34:54.728489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 17:34:54.731529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2255 17:34:54.734672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2256 17:34:54.738150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2257 17:34:54.741236 [ANA_INIT] flow start
2258 17:34:54.745098 [ANA_INIT] PLL >>>>>>>>
2259 17:34:54.745197 [ANA_INIT] PLL <<<<<<<<
2260 17:34:54.747970 [ANA_INIT] MIDPI >>>>>>>>
2261 17:34:54.751790 [ANA_INIT] MIDPI <<<<<<<<
2262 17:34:54.751871 [ANA_INIT] DLL >>>>>>>>
2263 17:34:54.754672 [ANA_INIT] DLL <<<<<<<<
2264 17:34:54.758261 [ANA_INIT] flow end
2265 17:34:54.761607 ============ LP4 DIFF to SE enter ============
2266 17:34:54.765273 ============ LP4 DIFF to SE exit ============
2267 17:34:54.768081 [ANA_INIT] <<<<<<<<<<<<<
2268 17:34:54.771774 [Flow] Enable top DCM control >>>>>
2269 17:34:54.774771 [Flow] Enable top DCM control <<<<<
2270 17:34:54.778416 Enable DLL master slave shuffle
2271 17:34:54.781357 ==============================================================
2272 17:34:54.785072 Gating Mode config
2273 17:34:54.791241 ==============================================================
2274 17:34:54.791327 Config description:
2275 17:34:54.801312 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2276 17:34:54.808081 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2277 17:34:54.811837 SELPH_MODE 0: By rank 1: By Phase
2278 17:34:54.818552 ==============================================================
2279 17:34:54.821733 GAT_TRACK_EN = 1
2280 17:34:54.824518 RX_GATING_MODE = 2
2281 17:34:54.828299 RX_GATING_TRACK_MODE = 2
2282 17:34:54.831640 SELPH_MODE = 1
2283 17:34:54.834588 PICG_EARLY_EN = 1
2284 17:34:54.834674 VALID_LAT_VALUE = 1
2285 17:34:54.841506 ==============================================================
2286 17:34:54.844959 Enter into Gating configuration >>>>
2287 17:34:54.848438 Exit from Gating configuration <<<<
2288 17:34:54.851141 Enter into DVFS_PRE_config >>>>>
2289 17:34:54.861405 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2290 17:34:54.864682 Exit from DVFS_PRE_config <<<<<
2291 17:34:54.867934 Enter into PICG configuration >>>>
2292 17:34:54.871525 Exit from PICG configuration <<<<
2293 17:34:54.874987 [RX_INPUT] configuration >>>>>
2294 17:34:54.878114 [RX_INPUT] configuration <<<<<
2295 17:34:54.881707 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2296 17:34:54.887876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2297 17:34:54.894864 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 17:34:54.901226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 17:34:54.907911 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 17:34:54.911657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 17:34:54.917843 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2302 17:34:54.921288 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2303 17:34:54.924534 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2304 17:34:54.928108 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2305 17:34:54.935047 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2306 17:34:54.937733 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2307 17:34:54.941233 ===================================
2308 17:34:54.944396 LPDDR4 DRAM CONFIGURATION
2309 17:34:54.948139 ===================================
2310 17:34:54.948229 EX_ROW_EN[0] = 0x0
2311 17:34:54.950950 EX_ROW_EN[1] = 0x0
2312 17:34:54.951103 LP4Y_EN = 0x0
2313 17:34:54.954318 WORK_FSP = 0x0
2314 17:34:54.954399 WL = 0x4
2315 17:34:54.957873 RL = 0x4
2316 17:34:54.957954 BL = 0x2
2317 17:34:54.961399 RPST = 0x0
2318 17:34:54.961511 RD_PRE = 0x0
2319 17:34:54.964365 WR_PRE = 0x1
2320 17:34:54.968073 WR_PST = 0x0
2321 17:34:54.968187 DBI_WR = 0x0
2322 17:34:54.971670 DBI_RD = 0x0
2323 17:34:54.971751 OTF = 0x1
2324 17:34:54.974463 ===================================
2325 17:34:54.978092 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2326 17:34:54.981445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2327 17:34:54.987980 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 17:34:54.990895 ===================================
2329 17:34:54.994478 LPDDR4 DRAM CONFIGURATION
2330 17:34:54.997744 ===================================
2331 17:34:54.997830 EX_ROW_EN[0] = 0x10
2332 17:34:55.000946 EX_ROW_EN[1] = 0x0
2333 17:34:55.001026 LP4Y_EN = 0x0
2334 17:34:55.004508 WORK_FSP = 0x0
2335 17:34:55.004590 WL = 0x4
2336 17:34:55.008418 RL = 0x4
2337 17:34:55.008876 BL = 0x2
2338 17:34:55.011528 RPST = 0x0
2339 17:34:55.011991 RD_PRE = 0x0
2340 17:34:55.014928 WR_PRE = 0x1
2341 17:34:55.015616 WR_PST = 0x0
2342 17:34:55.018219 DBI_WR = 0x0
2343 17:34:55.018769 DBI_RD = 0x0
2344 17:34:55.021555 OTF = 0x1
2345 17:34:55.024899 ===================================
2346 17:34:55.031482 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2347 17:34:55.031993 ==
2348 17:34:55.035245 Dram Type= 6, Freq= 0, CH_0, rank 0
2349 17:34:55.038167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2350 17:34:55.038658 ==
2351 17:34:55.041449 [Duty_Offset_Calibration]
2352 17:34:55.041906 B0:2 B1:0 CA:3
2353 17:34:55.042356
2354 17:34:55.045207 [DutyScan_Calibration_Flow] k_type=0
2355 17:34:55.055095
2356 17:34:55.055700 ==CLK 0==
2357 17:34:55.058747 Final CLK duty delay cell = 0
2358 17:34:55.062466 [0] MAX Duty = 5031%(X100), DQS PI = 20
2359 17:34:55.065551 [0] MIN Duty = 4906%(X100), DQS PI = 54
2360 17:34:55.066167 [0] AVG Duty = 4968%(X100)
2361 17:34:55.068894
2362 17:34:55.072241 CH0 CLK Duty spec in!! Max-Min= 125%
2363 17:34:55.075686 [DutyScan_Calibration_Flow] ====Done====
2364 17:34:55.076201
2365 17:34:55.078506 [DutyScan_Calibration_Flow] k_type=1
2366 17:34:55.094093
2367 17:34:55.094524 ==DQS 0 ==
2368 17:34:55.097608 Final DQS duty delay cell = 0
2369 17:34:55.100673 [0] MAX Duty = 5062%(X100), DQS PI = 14
2370 17:34:55.103906 [0] MIN Duty = 4907%(X100), DQS PI = 0
2371 17:34:55.104318 [0] AVG Duty = 4984%(X100)
2372 17:34:55.104639
2373 17:34:55.107216 ==DQS 1 ==
2374 17:34:55.110615 Final DQS duty delay cell = -4
2375 17:34:55.114320 [-4] MAX Duty = 5000%(X100), DQS PI = 34
2376 17:34:55.117858 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2377 17:34:55.120868 [-4] AVG Duty = 4937%(X100)
2378 17:34:55.121372
2379 17:34:55.123742 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2380 17:34:55.124281
2381 17:34:55.127023 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2382 17:34:55.130517 [DutyScan_Calibration_Flow] ====Done====
2383 17:34:55.130927
2384 17:34:55.134040 [DutyScan_Calibration_Flow] k_type=3
2385 17:34:55.151185
2386 17:34:55.151266 ==DQM 0 ==
2387 17:34:55.154371 Final DQM duty delay cell = 0
2388 17:34:55.157598 [0] MAX Duty = 5124%(X100), DQS PI = 28
2389 17:34:55.160860 [0] MIN Duty = 4876%(X100), DQS PI = 0
2390 17:34:55.160940 [0] AVG Duty = 5000%(X100)
2391 17:34:55.164421
2392 17:34:55.164501 ==DQM 1 ==
2393 17:34:55.167877 Final DQM duty delay cell = 4
2394 17:34:55.170784 [4] MAX Duty = 5124%(X100), DQS PI = 50
2395 17:34:55.174108 [4] MIN Duty = 5000%(X100), DQS PI = 12
2396 17:34:55.177575 [4] AVG Duty = 5062%(X100)
2397 17:34:55.177680
2398 17:34:55.181168 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2399 17:34:55.181253
2400 17:34:55.184093 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2401 17:34:55.187444 [DutyScan_Calibration_Flow] ====Done====
2402 17:34:55.187525
2403 17:34:55.190738 [DutyScan_Calibration_Flow] k_type=2
2404 17:34:55.206312
2405 17:34:55.206473 ==DQ 0 ==
2406 17:34:55.209187 Final DQ duty delay cell = -4
2407 17:34:55.212520 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2408 17:34:55.215659 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2409 17:34:55.218954 [-4] AVG Duty = 4969%(X100)
2410 17:34:55.219088
2411 17:34:55.219185 ==DQ 1 ==
2412 17:34:55.222386 Final DQ duty delay cell = -4
2413 17:34:55.225916 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2414 17:34:55.228796 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2415 17:34:55.232389 [-4] AVG Duty = 4938%(X100)
2416 17:34:55.232480
2417 17:34:55.235628 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2418 17:34:55.235709
2419 17:34:55.238937 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2420 17:34:55.242283 [DutyScan_Calibration_Flow] ====Done====
2421 17:34:55.242365 ==
2422 17:34:55.245281 Dram Type= 6, Freq= 0, CH_1, rank 0
2423 17:34:55.249030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2424 17:34:55.249118 ==
2425 17:34:55.252401 [Duty_Offset_Calibration]
2426 17:34:55.252507 B0:1 B1:-2 CA:0
2427 17:34:55.255509
2428 17:34:55.255588 [DutyScan_Calibration_Flow] k_type=0
2429 17:34:55.266381
2430 17:34:55.266487 ==CLK 0==
2431 17:34:55.269679 Final CLK duty delay cell = 0
2432 17:34:55.272820 [0] MAX Duty = 5062%(X100), DQS PI = 30
2433 17:34:55.276288 [0] MIN Duty = 4844%(X100), DQS PI = 58
2434 17:34:55.280064 [0] AVG Duty = 4953%(X100)
2435 17:34:55.280187
2436 17:34:55.282737 CH1 CLK Duty spec in!! Max-Min= 218%
2437 17:34:55.286275 [DutyScan_Calibration_Flow] ====Done====
2438 17:34:55.286428
2439 17:34:55.289833 [DutyScan_Calibration_Flow] k_type=1
2440 17:34:55.305077
2441 17:34:55.305259 ==DQS 0 ==
2442 17:34:55.308191 Final DQS duty delay cell = -4
2443 17:34:55.311877 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2444 17:34:55.314980 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2445 17:34:55.318361 [-4] AVG Duty = 4953%(X100)
2446 17:34:55.318653
2447 17:34:55.318883 ==DQS 1 ==
2448 17:34:55.321231 Final DQS duty delay cell = 0
2449 17:34:55.324635 [0] MAX Duty = 5093%(X100), DQS PI = 0
2450 17:34:55.328162 [0] MIN Duty = 4875%(X100), DQS PI = 26
2451 17:34:55.331313 [0] AVG Duty = 4984%(X100)
2452 17:34:55.331449
2453 17:34:55.335018 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2454 17:34:55.335131
2455 17:34:55.337970 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2456 17:34:55.341540 [DutyScan_Calibration_Flow] ====Done====
2457 17:34:55.341672
2458 17:34:55.344755 [DutyScan_Calibration_Flow] k_type=3
2459 17:34:55.361409
2460 17:34:55.361559 ==DQM 0 ==
2461 17:34:55.364937 Final DQM duty delay cell = 0
2462 17:34:55.368132 [0] MAX Duty = 5000%(X100), DQS PI = 22
2463 17:34:55.371652 [0] MIN Duty = 4844%(X100), DQS PI = 54
2464 17:34:55.375060 [0] AVG Duty = 4922%(X100)
2465 17:34:55.375258
2466 17:34:55.375435 ==DQM 1 ==
2467 17:34:55.378078 Final DQM duty delay cell = 0
2468 17:34:55.381455 [0] MAX Duty = 5031%(X100), DQS PI = 36
2469 17:34:55.385075 [0] MIN Duty = 4907%(X100), DQS PI = 2
2470 17:34:55.388288 [0] AVG Duty = 4969%(X100)
2471 17:34:55.388668
2472 17:34:55.391775 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2473 17:34:55.392162
2474 17:34:55.395084 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2475 17:34:55.398223 [DutyScan_Calibration_Flow] ====Done====
2476 17:34:55.398746
2477 17:34:55.401934 [DutyScan_Calibration_Flow] k_type=2
2478 17:34:55.417779
2479 17:34:55.417859 ==DQ 0 ==
2480 17:34:55.421073 Final DQ duty delay cell = 0
2481 17:34:55.424609 [0] MAX Duty = 5062%(X100), DQS PI = 20
2482 17:34:55.427791 [0] MIN Duty = 4938%(X100), DQS PI = 52
2483 17:34:55.427891 [0] AVG Duty = 5000%(X100)
2484 17:34:55.431323
2485 17:34:55.431454 ==DQ 1 ==
2486 17:34:55.434780 Final DQ duty delay cell = 0
2487 17:34:55.438013 [0] MAX Duty = 5093%(X100), DQS PI = 18
2488 17:34:55.441425 [0] MIN Duty = 4969%(X100), DQS PI = 26
2489 17:34:55.441532 [0] AVG Duty = 5031%(X100)
2490 17:34:55.441628
2491 17:34:55.444800 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2492 17:34:55.447738
2493 17:34:55.451489 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2494 17:34:55.454485 [DutyScan_Calibration_Flow] ====Done====
2495 17:34:55.457533 nWR fixed to 30
2496 17:34:55.457646 [ModeRegInit_LP4] CH0 RK0
2497 17:34:55.461187 [ModeRegInit_LP4] CH0 RK1
2498 17:34:55.464213 [ModeRegInit_LP4] CH1 RK0
2499 17:34:55.468135 [ModeRegInit_LP4] CH1 RK1
2500 17:34:55.468235 match AC timing 7
2501 17:34:55.470990 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2502 17:34:55.474674 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2503 17:34:55.481145 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2504 17:34:55.484586 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2505 17:34:55.491086 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2506 17:34:55.491196 ==
2507 17:34:55.494749 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 17:34:55.497826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 17:34:55.497934 ==
2510 17:34:55.504216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 17:34:55.511115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2512 17:34:55.518391 [CA 0] Center 40 (10~71) winsize 62
2513 17:34:55.521183 [CA 1] Center 39 (9~70) winsize 62
2514 17:34:55.524341 [CA 2] Center 36 (6~66) winsize 61
2515 17:34:55.527841 [CA 3] Center 35 (5~66) winsize 62
2516 17:34:55.531666 [CA 4] Center 34 (4~65) winsize 62
2517 17:34:55.534388 [CA 5] Center 33 (3~64) winsize 62
2518 17:34:55.534509
2519 17:34:55.538166 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2520 17:34:55.538259
2521 17:34:55.540982 [CATrainingPosCal] consider 1 rank data
2522 17:34:55.544836 u2DelayCellTimex100 = 270/100 ps
2523 17:34:55.547893 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2524 17:34:55.554907 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2525 17:34:55.557884 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2526 17:34:55.561063 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 17:34:55.564347 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2528 17:34:55.567991 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2529 17:34:55.568161
2530 17:34:55.571101 CA PerBit enable=1, Macro0, CA PI delay=33
2531 17:34:55.571367
2532 17:34:55.574735 [CBTSetCACLKResult] CA Dly = 33
2533 17:34:55.578071 CS Dly: 7 (0~38)
2534 17:34:55.578390 ==
2535 17:34:55.581669 Dram Type= 6, Freq= 0, CH_0, rank 1
2536 17:34:55.584594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 17:34:55.584952 ==
2538 17:34:55.587893 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2539 17:34:55.594751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2540 17:34:55.604726 [CA 0] Center 40 (10~70) winsize 61
2541 17:34:55.607438 [CA 1] Center 40 (10~70) winsize 61
2542 17:34:55.611170 [CA 2] Center 35 (5~66) winsize 62
2543 17:34:55.614109 [CA 3] Center 35 (5~66) winsize 62
2544 17:34:55.617751 [CA 4] Center 34 (4~65) winsize 62
2545 17:34:55.620718 [CA 5] Center 33 (3~64) winsize 62
2546 17:34:55.621230
2547 17:34:55.624698 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2548 17:34:55.625208
2549 17:34:55.627452 [CATrainingPosCal] consider 2 rank data
2550 17:34:55.630942 u2DelayCellTimex100 = 270/100 ps
2551 17:34:55.634043 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2552 17:34:55.640744 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2553 17:34:55.644019 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2554 17:34:55.647252 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 17:34:55.651186 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2556 17:34:55.653958 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2557 17:34:55.654474
2558 17:34:55.657498 CA PerBit enable=1, Macro0, CA PI delay=33
2559 17:34:55.657933
2560 17:34:55.661242 [CBTSetCACLKResult] CA Dly = 33
2561 17:34:55.664500 CS Dly: 8 (0~40)
2562 17:34:55.664898
2563 17:34:55.667550 ----->DramcWriteLeveling(PI) begin...
2564 17:34:55.667971 ==
2565 17:34:55.670849 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 17:34:55.674611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 17:34:55.674996 ==
2568 17:34:55.677642 Write leveling (Byte 0): 32 => 32
2569 17:34:55.680914 Write leveling (Byte 1): 28 => 28
2570 17:34:55.684368 DramcWriteLeveling(PI) end<-----
2571 17:34:55.684752
2572 17:34:55.685051 ==
2573 17:34:55.687669 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 17:34:55.690809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 17:34:55.691325 ==
2576 17:34:55.693783 [Gating] SW mode calibration
2577 17:34:55.700481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2578 17:34:55.707215 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2579 17:34:55.710610 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 17:34:55.714128 0 15 4 | B1->B0 | 2524 3232 | 1 1 | (0 0) (1 1)
2581 17:34:55.720623 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 17:34:55.723792 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 17:34:55.727218 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 17:34:55.734024 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 17:34:55.737306 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 17:34:55.740816 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2587 17:34:55.747700 1 0 0 | B1->B0 | 3333 2828 | 1 1 | (0 0) (1 0)
2588 17:34:55.750960 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 17:34:55.754481 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 17:34:55.757592 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 17:34:55.764153 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 17:34:55.767569 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 17:34:55.770863 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 17:34:55.777298 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2595 17:34:55.780751 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2596 17:34:55.784443 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2597 17:34:55.790389 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 17:34:55.794053 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 17:34:55.797695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 17:34:55.804013 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 17:34:55.807427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 17:34:55.810862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2603 17:34:55.817501 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2604 17:34:55.820941 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 17:34:55.824123 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 17:34:55.830382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 17:34:55.833852 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 17:34:55.837544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 17:34:55.843541 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 17:34:55.846935 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 17:34:55.850051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 17:34:55.856513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 17:34:55.860255 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 17:34:55.863282 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 17:34:55.870038 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 17:34:55.873204 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 17:34:55.876624 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 17:34:55.880519 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 17:34:55.886538 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 17:34:55.890404 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 17:34:55.893629 Total UI for P1: 0, mck2ui 16
2622 17:34:55.896523 best dqsien dly found for B0: ( 1, 4, 0)
2623 17:34:55.899917 Total UI for P1: 0, mck2ui 16
2624 17:34:55.903318 best dqsien dly found for B1: ( 1, 4, 2)
2625 17:34:55.907031 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2626 17:34:55.909806 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2627 17:34:55.909913
2628 17:34:55.913229 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2629 17:34:55.917005 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2630 17:34:55.919856 [Gating] SW calibration Done
2631 17:34:55.919955 ==
2632 17:34:55.923416 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 17:34:55.926454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 17:34:55.930077 ==
2635 17:34:55.930176 RX Vref Scan: 0
2636 17:34:55.930266
2637 17:34:55.933708 RX Vref 0 -> 0, step: 1
2638 17:34:55.933781
2639 17:34:55.936511 RX Delay -40 -> 252, step: 8
2640 17:34:55.940149 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2641 17:34:55.943116 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2642 17:34:55.946751 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2643 17:34:55.950064 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2644 17:34:55.956781 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2645 17:34:55.959894 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2646 17:34:55.963293 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2647 17:34:55.966498 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2648 17:34:55.970038 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2649 17:34:55.973278 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2650 17:34:55.979924 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2651 17:34:55.983651 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2652 17:34:55.986848 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2653 17:34:55.990152 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2654 17:34:55.993293 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2655 17:34:56.000024 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2656 17:34:56.000322 ==
2657 17:34:56.003246 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 17:34:56.006642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 17:34:56.006744 ==
2660 17:34:56.006837 DQS Delay:
2661 17:34:56.010071 DQS0 = 0, DQS1 = 0
2662 17:34:56.010174 DQM Delay:
2663 17:34:56.013026 DQM0 = 112, DQM1 = 102
2664 17:34:56.013122 DQ Delay:
2665 17:34:56.016896 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2666 17:34:56.020249 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2667 17:34:56.023313 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2668 17:34:56.026707 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2669 17:34:56.026805
2670 17:34:56.026893
2671 17:34:56.026977 ==
2672 17:34:56.029871 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 17:34:56.036543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 17:34:56.036617 ==
2675 17:34:56.036682
2676 17:34:56.036768
2677 17:34:56.036852 TX Vref Scan disable
2678 17:34:56.040895 == TX Byte 0 ==
2679 17:34:56.043857 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2680 17:34:56.047525 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2681 17:34:56.050299 == TX Byte 1 ==
2682 17:34:56.053690 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2683 17:34:56.061001 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2684 17:34:56.061149 ==
2685 17:34:56.063797 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 17:34:56.066671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 17:34:56.066782 ==
2688 17:34:56.078409 TX Vref=22, minBit 8, minWin=25, winSum=415
2689 17:34:56.082294 TX Vref=24, minBit 12, minWin=25, winSum=421
2690 17:34:56.085277 TX Vref=26, minBit 8, minWin=26, winSum=431
2691 17:34:56.088824 TX Vref=28, minBit 2, minWin=26, winSum=434
2692 17:34:56.091908 TX Vref=30, minBit 8, minWin=25, winSum=434
2693 17:34:56.098869 TX Vref=32, minBit 8, minWin=25, winSum=429
2694 17:34:56.102113 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 28
2695 17:34:56.102675
2696 17:34:56.105468 Final TX Range 1 Vref 28
2697 17:34:56.106044
2698 17:34:56.106530 ==
2699 17:34:56.109269 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 17:34:56.111890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 17:34:56.112349 ==
2702 17:34:56.115489
2703 17:34:56.115940
2704 17:34:56.116288 TX Vref Scan disable
2705 17:34:56.118989 == TX Byte 0 ==
2706 17:34:56.122212 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2707 17:34:56.125608 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2708 17:34:56.128874 == TX Byte 1 ==
2709 17:34:56.132309 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2710 17:34:56.135646 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2711 17:34:56.139067
2712 17:34:56.139661 [DATLAT]
2713 17:34:56.140130 Freq=1200, CH0 RK0
2714 17:34:56.140623
2715 17:34:56.142121 DATLAT Default: 0xd
2716 17:34:56.142698 0, 0xFFFF, sum = 0
2717 17:34:56.145525 1, 0xFFFF, sum = 0
2718 17:34:56.146113 2, 0xFFFF, sum = 0
2719 17:34:56.148527 3, 0xFFFF, sum = 0
2720 17:34:56.149047 4, 0xFFFF, sum = 0
2721 17:34:56.152257 5, 0xFFFF, sum = 0
2722 17:34:56.152829 6, 0xFFFF, sum = 0
2723 17:34:56.155185 7, 0xFFFF, sum = 0
2724 17:34:56.158699 8, 0xFFFF, sum = 0
2725 17:34:56.159182 9, 0xFFFF, sum = 0
2726 17:34:56.162177 10, 0xFFFF, sum = 0
2727 17:34:56.162610 11, 0xFFFF, sum = 0
2728 17:34:56.165663 12, 0x0, sum = 1
2729 17:34:56.166257 13, 0x0, sum = 2
2730 17:34:56.168638 14, 0x0, sum = 3
2731 17:34:56.169096 15, 0x0, sum = 4
2732 17:34:56.169580 best_step = 13
2733 17:34:56.169899
2734 17:34:56.172492 ==
2735 17:34:56.175357 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 17:34:56.178843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 17:34:56.179490 ==
2738 17:34:56.180008 RX Vref Scan: 1
2739 17:34:56.180513
2740 17:34:56.182441 Set Vref Range= 32 -> 127
2741 17:34:56.182876
2742 17:34:56.185298 RX Vref 32 -> 127, step: 1
2743 17:34:56.185806
2744 17:34:56.188940 RX Delay -37 -> 252, step: 4
2745 17:34:56.189382
2746 17:34:56.192137 Set Vref, RX VrefLevel [Byte0]: 32
2747 17:34:56.195293 [Byte1]: 32
2748 17:34:56.195776
2749 17:34:56.198731 Set Vref, RX VrefLevel [Byte0]: 33
2750 17:34:56.201631 [Byte1]: 33
2751 17:34:56.205620
2752 17:34:56.206178 Set Vref, RX VrefLevel [Byte0]: 34
2753 17:34:56.208678 [Byte1]: 34
2754 17:34:56.213401
2755 17:34:56.213854 Set Vref, RX VrefLevel [Byte0]: 35
2756 17:34:56.216497 [Byte1]: 35
2757 17:34:56.221144
2758 17:34:56.221711 Set Vref, RX VrefLevel [Byte0]: 36
2759 17:34:56.224463 [Byte1]: 36
2760 17:34:56.229494
2761 17:34:56.230045 Set Vref, RX VrefLevel [Byte0]: 37
2762 17:34:56.232485 [Byte1]: 37
2763 17:34:56.237119
2764 17:34:56.237570 Set Vref, RX VrefLevel [Byte0]: 38
2765 17:34:56.240447 [Byte1]: 38
2766 17:34:56.245609
2767 17:34:56.246019 Set Vref, RX VrefLevel [Byte0]: 39
2768 17:34:56.248817 [Byte1]: 39
2769 17:34:56.253294
2770 17:34:56.253872 Set Vref, RX VrefLevel [Byte0]: 40
2771 17:34:56.256662 [Byte1]: 40
2772 17:34:56.261362
2773 17:34:56.261851 Set Vref, RX VrefLevel [Byte0]: 41
2774 17:34:56.264475 [Byte1]: 41
2775 17:34:56.269829
2776 17:34:56.270255 Set Vref, RX VrefLevel [Byte0]: 42
2777 17:34:56.272766 [Byte1]: 42
2778 17:34:56.277353
2779 17:34:56.277778 Set Vref, RX VrefLevel [Byte0]: 43
2780 17:34:56.280487 [Byte1]: 43
2781 17:34:56.285588
2782 17:34:56.286016 Set Vref, RX VrefLevel [Byte0]: 44
2783 17:34:56.288574 [Byte1]: 44
2784 17:34:56.293092
2785 17:34:56.293520 Set Vref, RX VrefLevel [Byte0]: 45
2786 17:34:56.296573 [Byte1]: 45
2787 17:34:56.301351
2788 17:34:56.301777 Set Vref, RX VrefLevel [Byte0]: 46
2789 17:34:56.304933 [Byte1]: 46
2790 17:34:56.309411
2791 17:34:56.309848 Set Vref, RX VrefLevel [Byte0]: 47
2792 17:34:56.312405 [Byte1]: 47
2793 17:34:56.317090
2794 17:34:56.320830 Set Vref, RX VrefLevel [Byte0]: 48
2795 17:34:56.324159 [Byte1]: 48
2796 17:34:56.324588
2797 17:34:56.327196 Set Vref, RX VrefLevel [Byte0]: 49
2798 17:34:56.330489 [Byte1]: 49
2799 17:34:56.330907
2800 17:34:56.333869 Set Vref, RX VrefLevel [Byte0]: 50
2801 17:34:56.337450 [Byte1]: 50
2802 17:34:56.341605
2803 17:34:56.342021 Set Vref, RX VrefLevel [Byte0]: 51
2804 17:34:56.344464 [Byte1]: 51
2805 17:34:56.349350
2806 17:34:56.349874 Set Vref, RX VrefLevel [Byte0]: 52
2807 17:34:56.353214 [Byte1]: 52
2808 17:34:56.357615
2809 17:34:56.358075 Set Vref, RX VrefLevel [Byte0]: 53
2810 17:34:56.360500 [Byte1]: 53
2811 17:34:56.365540
2812 17:34:56.366000 Set Vref, RX VrefLevel [Byte0]: 54
2813 17:34:56.368934 [Byte1]: 54
2814 17:34:56.373382
2815 17:34:56.373843 Set Vref, RX VrefLevel [Byte0]: 55
2816 17:34:56.376955 [Byte1]: 55
2817 17:34:56.381322
2818 17:34:56.381795 Set Vref, RX VrefLevel [Byte0]: 56
2819 17:34:56.384833 [Byte1]: 56
2820 17:34:56.389338
2821 17:34:56.389817 Set Vref, RX VrefLevel [Byte0]: 57
2822 17:34:56.393002 [Byte1]: 57
2823 17:34:56.397140
2824 17:34:56.397647 Set Vref, RX VrefLevel [Byte0]: 58
2825 17:34:56.400362 [Byte1]: 58
2826 17:34:56.405454
2827 17:34:56.405995 Set Vref, RX VrefLevel [Byte0]: 59
2828 17:34:56.408480 [Byte1]: 59
2829 17:34:56.413120
2830 17:34:56.413578 Set Vref, RX VrefLevel [Byte0]: 60
2831 17:34:56.416937 [Byte1]: 60
2832 17:34:56.421053
2833 17:34:56.421509 Set Vref, RX VrefLevel [Byte0]: 61
2834 17:34:56.424395 [Byte1]: 61
2835 17:34:56.429433
2836 17:34:56.429904 Set Vref, RX VrefLevel [Byte0]: 62
2837 17:34:56.432703 [Byte1]: 62
2838 17:34:56.437629
2839 17:34:56.438085 Set Vref, RX VrefLevel [Byte0]: 63
2840 17:34:56.440440 [Byte1]: 63
2841 17:34:56.445323
2842 17:34:56.445797 Set Vref, RX VrefLevel [Byte0]: 64
2843 17:34:56.449178 [Byte1]: 64
2844 17:34:56.453020
2845 17:34:56.453471 Set Vref, RX VrefLevel [Byte0]: 65
2846 17:34:56.456829 [Byte1]: 65
2847 17:34:56.461082
2848 17:34:56.461495 Set Vref, RX VrefLevel [Byte0]: 66
2849 17:34:56.464524 [Byte1]: 66
2850 17:34:56.469013
2851 17:34:56.469426 Set Vref, RX VrefLevel [Byte0]: 67
2852 17:34:56.472359 [Byte1]: 67
2853 17:34:56.477149
2854 17:34:56.477578 Set Vref, RX VrefLevel [Byte0]: 68
2855 17:34:56.480730 [Byte1]: 68
2856 17:34:56.485317
2857 17:34:56.485744 Set Vref, RX VrefLevel [Byte0]: 69
2858 17:34:56.488504 [Byte1]: 69
2859 17:34:56.493280
2860 17:34:56.493711 Set Vref, RX VrefLevel [Byte0]: 70
2861 17:34:56.496770 [Byte1]: 70
2862 17:34:56.501117
2863 17:34:56.501583 Set Vref, RX VrefLevel [Byte0]: 71
2864 17:34:56.504471 [Byte1]: 71
2865 17:34:56.509357
2866 17:34:56.509812 Set Vref, RX VrefLevel [Byte0]: 72
2867 17:34:56.512390 [Byte1]: 72
2868 17:34:56.517322
2869 17:34:56.517750 Set Vref, RX VrefLevel [Byte0]: 73
2870 17:34:56.520625 [Byte1]: 73
2871 17:34:56.525323
2872 17:34:56.525852 Final RX Vref Byte 0 = 60 to rank0
2873 17:34:56.528313 Final RX Vref Byte 1 = 47 to rank0
2874 17:34:56.531694 Final RX Vref Byte 0 = 60 to rank1
2875 17:34:56.535129 Final RX Vref Byte 1 = 47 to rank1==
2876 17:34:56.538296 Dram Type= 6, Freq= 0, CH_0, rank 0
2877 17:34:56.544998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 17:34:56.545438 ==
2879 17:34:56.545803 DQS Delay:
2880 17:34:56.546136 DQS0 = 0, DQS1 = 0
2881 17:34:56.548745 DQM Delay:
2882 17:34:56.549204 DQM0 = 112, DQM1 = 98
2883 17:34:56.551862 DQ Delay:
2884 17:34:56.555122 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2885 17:34:56.558271 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =122
2886 17:34:56.561472 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2887 17:34:56.564790 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =108
2888 17:34:56.565018
2889 17:34:56.565193
2890 17:34:56.571311 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2891 17:34:56.574621 CH0 RK0: MR19=303, MR18=F9F9
2892 17:34:56.581685 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2893 17:34:56.581835
2894 17:34:56.584730 ----->DramcWriteLeveling(PI) begin...
2895 17:34:56.584882 ==
2896 17:34:56.588368 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 17:34:56.591977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 17:34:56.594621 ==
2899 17:34:56.594830 Write leveling (Byte 0): 30 => 30
2900 17:34:56.598354 Write leveling (Byte 1): 30 => 30
2901 17:34:56.601749 DramcWriteLeveling(PI) end<-----
2902 17:34:56.601898
2903 17:34:56.602064 ==
2904 17:34:56.605239 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 17:34:56.611110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 17:34:56.611298 ==
2907 17:34:56.611483 [Gating] SW mode calibration
2908 17:34:56.621652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2909 17:34:56.625052 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2910 17:34:56.628389 0 15 0 | B1->B0 | 2d2c 3434 | 1 1 | (1 1) (1 1)
2911 17:34:56.635093 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 17:34:56.638337 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 17:34:56.641825 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 17:34:56.647834 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 17:34:56.651632 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 17:34:56.655272 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 17:34:56.661780 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2918 17:34:56.664801 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2919 17:34:56.668000 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 17:34:56.674842 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 17:34:56.677846 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 17:34:56.681573 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 17:34:56.688009 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 17:34:56.691578 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 17:34:56.694528 1 0 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
2926 17:34:56.701700 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2927 17:34:56.704570 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 17:34:56.708081 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 17:34:56.714818 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 17:34:56.718434 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 17:34:56.721613 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 17:34:56.728224 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 17:34:56.731351 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2934 17:34:56.734823 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2935 17:34:56.738369 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 17:34:56.744817 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 17:34:56.747917 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 17:34:56.751466 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 17:34:56.758696 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 17:34:56.761314 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 17:34:56.764687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 17:34:56.771309 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 17:34:56.775012 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 17:34:56.777975 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 17:34:56.785254 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 17:34:56.788084 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 17:34:56.791612 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 17:34:56.798003 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 17:34:56.801447 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2950 17:34:56.805157 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2951 17:34:56.808586 Total UI for P1: 0, mck2ui 16
2952 17:34:56.811648 best dqsien dly found for B0: ( 1, 3, 28)
2953 17:34:56.814950 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 17:34:56.818006 Total UI for P1: 0, mck2ui 16
2955 17:34:56.821639 best dqsien dly found for B1: ( 1, 3, 30)
2956 17:34:56.824754 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2957 17:34:56.831642 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2958 17:34:56.832046
2959 17:34:56.834794 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2960 17:34:56.838160 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2961 17:34:56.841698 [Gating] SW calibration Done
2962 17:34:56.842085 ==
2963 17:34:56.844916 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 17:34:56.848575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 17:34:56.848976 ==
2966 17:34:56.849284 RX Vref Scan: 0
2967 17:34:56.851898
2968 17:34:56.852281 RX Vref 0 -> 0, step: 1
2969 17:34:56.852583
2970 17:34:56.854859 RX Delay -40 -> 252, step: 8
2971 17:34:56.858029 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2972 17:34:56.861531 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2973 17:34:56.868563 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2974 17:34:56.871542 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2975 17:34:56.874806 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2976 17:34:56.878011 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2977 17:34:56.881763 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2978 17:34:56.887995 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2979 17:34:56.891204 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2980 17:34:56.894911 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2981 17:34:56.898027 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2982 17:34:56.901505 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2983 17:34:56.908380 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2984 17:34:56.911235 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2985 17:34:56.914897 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2986 17:34:56.918208 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2987 17:34:56.918591 ==
2988 17:34:56.921493 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 17:34:56.924704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 17:34:56.928140 ==
2991 17:34:56.928522 DQS Delay:
2992 17:34:56.928821 DQS0 = 0, DQS1 = 0
2993 17:34:56.931345 DQM Delay:
2994 17:34:56.931778 DQM0 = 113, DQM1 = 101
2995 17:34:56.934947 DQ Delay:
2996 17:34:56.938452 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2997 17:34:56.941155 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2998 17:34:56.944735 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2999 17:34:56.948063 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
3000 17:34:56.948449
3001 17:34:56.948979
3002 17:34:56.949294 ==
3003 17:34:56.951251 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 17:34:56.954755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 17:34:56.955144 ==
3006 17:34:56.955598
3007 17:34:56.955890
3008 17:34:56.958314 TX Vref Scan disable
3009 17:34:56.961607 == TX Byte 0 ==
3010 17:34:56.964879 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3011 17:34:56.968378 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3012 17:34:56.971296 == TX Byte 1 ==
3013 17:34:56.974808 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3014 17:34:56.978278 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3015 17:34:56.978658 ==
3016 17:34:56.981339 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 17:34:56.985271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 17:34:56.988091 ==
3019 17:34:56.997975 TX Vref=22, minBit 0, minWin=26, winSum=423
3020 17:34:57.001310 TX Vref=24, minBit 4, minWin=26, winSum=433
3021 17:34:57.004293 TX Vref=26, minBit 5, minWin=26, winSum=436
3022 17:34:57.007938 TX Vref=28, minBit 8, minWin=26, winSum=439
3023 17:34:57.011744 TX Vref=30, minBit 1, minWin=26, winSum=442
3024 17:34:57.014596 TX Vref=32, minBit 8, minWin=26, winSum=440
3025 17:34:57.021471 [TxChooseVref] Worse bit 1, Min win 26, Win sum 442, Final Vref 30
3026 17:34:57.021573
3027 17:34:57.024650 Final TX Range 1 Vref 30
3028 17:34:57.024782
3029 17:34:57.024864 ==
3030 17:34:57.027926 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 17:34:57.031044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 17:34:57.031162 ==
3033 17:34:57.031308
3034 17:34:57.034286
3035 17:34:57.034446 TX Vref Scan disable
3036 17:34:57.037738 == TX Byte 0 ==
3037 17:34:57.041177 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3038 17:34:57.044406 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3039 17:34:57.047867 == TX Byte 1 ==
3040 17:34:57.050946 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3041 17:34:57.054234 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3042 17:34:57.054434
3043 17:34:57.057662 [DATLAT]
3044 17:34:57.057899 Freq=1200, CH0 RK1
3045 17:34:57.058086
3046 17:34:57.061174 DATLAT Default: 0xd
3047 17:34:57.061460 0, 0xFFFF, sum = 0
3048 17:34:57.064407 1, 0xFFFF, sum = 0
3049 17:34:57.064706 2, 0xFFFF, sum = 0
3050 17:34:57.067926 3, 0xFFFF, sum = 0
3051 17:34:57.068439 4, 0xFFFF, sum = 0
3052 17:34:57.071690 5, 0xFFFF, sum = 0
3053 17:34:57.072269 6, 0xFFFF, sum = 0
3054 17:34:57.074545 7, 0xFFFF, sum = 0
3055 17:34:57.077826 8, 0xFFFF, sum = 0
3056 17:34:57.078404 9, 0xFFFF, sum = 0
3057 17:34:57.081155 10, 0xFFFF, sum = 0
3058 17:34:57.081713 11, 0xFFFF, sum = 0
3059 17:34:57.084517 12, 0x0, sum = 1
3060 17:34:57.085098 13, 0x0, sum = 2
3061 17:34:57.087736 14, 0x0, sum = 3
3062 17:34:57.088352 15, 0x0, sum = 4
3063 17:34:57.088914 best_step = 13
3064 17:34:57.089384
3065 17:34:57.091381 ==
3066 17:34:57.094453 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 17:34:57.097801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 17:34:57.098217 ==
3069 17:34:57.098547 RX Vref Scan: 0
3070 17:34:57.098852
3071 17:34:57.101071 RX Vref 0 -> 0, step: 1
3072 17:34:57.101485
3073 17:34:57.104576 RX Delay -37 -> 252, step: 4
3074 17:34:57.107710 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3075 17:34:57.114529 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3076 17:34:57.117553 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3077 17:34:57.121499 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3078 17:34:57.124222 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3079 17:34:57.127963 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3080 17:34:57.134368 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3081 17:34:57.137675 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3082 17:34:57.141415 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3083 17:34:57.144426 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3084 17:34:57.147626 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3085 17:34:57.150948 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3086 17:34:57.157439 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3087 17:34:57.160890 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3088 17:34:57.164411 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3089 17:34:57.167507 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3090 17:34:57.167928 ==
3091 17:34:57.171007 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 17:34:57.177685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 17:34:57.178120 ==
3094 17:34:57.178634 DQS Delay:
3095 17:34:57.181138 DQS0 = 0, DQS1 = 0
3096 17:34:57.181574 DQM Delay:
3097 17:34:57.184180 DQM0 = 111, DQM1 = 99
3098 17:34:57.184657 DQ Delay:
3099 17:34:57.187854 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3100 17:34:57.190993 DQ4 =112, DQ5 =100, DQ6 =122, DQ7 =120
3101 17:34:57.194212 DQ8 =90, DQ9 =80, DQ10 =100, DQ11 =90
3102 17:34:57.198007 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3103 17:34:57.198421
3104 17:34:57.198748
3105 17:34:57.207299 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3106 17:34:57.207781 CH0 RK1: MR19=403, MR18=13FB
3107 17:34:57.213933 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3108 17:34:57.217599 [RxdqsGatingPostProcess] freq 1200
3109 17:34:57.224383 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3110 17:34:57.227315 best DQS0 dly(2T, 0.5T) = (0, 12)
3111 17:34:57.230845 best DQS1 dly(2T, 0.5T) = (0, 12)
3112 17:34:57.234593 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3113 17:34:57.237431 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3114 17:34:57.237727 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 17:34:57.240689 best DQS1 dly(2T, 0.5T) = (0, 11)
3116 17:34:57.244248 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 17:34:57.247329 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3118 17:34:57.250336 Pre-setting of DQS Precalculation
3119 17:34:57.257142 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3120 17:34:57.257396 ==
3121 17:34:57.260730 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 17:34:57.263765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 17:34:57.264048 ==
3124 17:34:57.270362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 17:34:57.277321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3126 17:34:57.284066 [CA 0] Center 37 (7~67) winsize 61
3127 17:34:57.287085 [CA 1] Center 37 (7~68) winsize 62
3128 17:34:57.290166 [CA 2] Center 34 (5~64) winsize 60
3129 17:34:57.293471 [CA 3] Center 33 (3~64) winsize 62
3130 17:34:57.297369 [CA 4] Center 34 (4~64) winsize 61
3131 17:34:57.300427 [CA 5] Center 33 (3~63) winsize 61
3132 17:34:57.300516
3133 17:34:57.303555 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3134 17:34:57.303636
3135 17:34:57.307037 [CATrainingPosCal] consider 1 rank data
3136 17:34:57.310514 u2DelayCellTimex100 = 270/100 ps
3137 17:34:57.313562 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3138 17:34:57.317111 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 17:34:57.323770 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3140 17:34:57.326867 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 17:34:57.330645 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 17:34:57.333858 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3143 17:34:57.333953
3144 17:34:57.337453 CA PerBit enable=1, Macro0, CA PI delay=33
3145 17:34:57.337557
3146 17:34:57.340563 [CBTSetCACLKResult] CA Dly = 33
3147 17:34:57.340667 CS Dly: 5 (0~36)
3148 17:34:57.340790 ==
3149 17:34:57.343948 Dram Type= 6, Freq= 0, CH_1, rank 1
3150 17:34:57.350896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 17:34:57.351327 ==
3152 17:34:57.353825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 17:34:57.360328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3154 17:34:57.369336 [CA 0] Center 37 (8~67) winsize 60
3155 17:34:57.372667 [CA 1] Center 37 (7~68) winsize 62
3156 17:34:57.376199 [CA 2] Center 34 (4~65) winsize 62
3157 17:34:57.379958 [CA 3] Center 33 (3~64) winsize 62
3158 17:34:57.382835 [CA 4] Center 34 (4~65) winsize 62
3159 17:34:57.386357 [CA 5] Center 33 (3~63) winsize 61
3160 17:34:57.386771
3161 17:34:57.389430 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3162 17:34:57.389850
3163 17:34:57.392516 [CATrainingPosCal] consider 2 rank data
3164 17:34:57.396681 u2DelayCellTimex100 = 270/100 ps
3165 17:34:57.399750 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3166 17:34:57.402728 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3167 17:34:57.410160 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3168 17:34:57.413005 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3169 17:34:57.416740 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 17:34:57.420276 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3171 17:34:57.420758
3172 17:34:57.422855 CA PerBit enable=1, Macro0, CA PI delay=33
3173 17:34:57.422935
3174 17:34:57.426238 [CBTSetCACLKResult] CA Dly = 33
3175 17:34:57.426319 CS Dly: 7 (0~40)
3176 17:34:57.426381
3177 17:34:57.429478 ----->DramcWriteLeveling(PI) begin...
3178 17:34:57.432502 ==
3179 17:34:57.432598 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 17:34:57.439275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 17:34:57.439399 ==
3182 17:34:57.442903 Write leveling (Byte 0): 27 => 27
3183 17:34:57.445911 Write leveling (Byte 1): 28 => 28
3184 17:34:57.445991 DramcWriteLeveling(PI) end<-----
3185 17:34:57.449406
3186 17:34:57.449502 ==
3187 17:34:57.452909 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 17:34:57.456126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 17:34:57.456201 ==
3190 17:34:57.459270 [Gating] SW mode calibration
3191 17:34:57.466194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3192 17:34:57.469166 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3193 17:34:57.475822 0 15 0 | B1->B0 | 2d2d 2423 | 1 1 | (0 0) (0 0)
3194 17:34:57.479660 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 17:34:57.482694 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 17:34:57.489517 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 17:34:57.492851 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 17:34:57.496260 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 17:34:57.503176 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 17:34:57.505964 0 15 28 | B1->B0 | 2d2d 3434 | 0 0 | (0 1) (0 1)
3201 17:34:57.509123 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3202 17:34:57.515900 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 17:34:57.519586 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 17:34:57.522875 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 17:34:57.529574 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 17:34:57.532368 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 17:34:57.536046 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3208 17:34:57.542723 1 0 28 | B1->B0 | 3f3f 3c3c | 0 1 | (0 0) (0 0)
3209 17:34:57.545684 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 17:34:57.548902 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 17:34:57.552438 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 17:34:57.559216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 17:34:57.562410 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 17:34:57.565820 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 17:34:57.572711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 17:34:57.575711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3217 17:34:57.579194 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3218 17:34:57.585677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 17:34:57.589180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 17:34:57.592292 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 17:34:57.599122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 17:34:57.602474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 17:34:57.605704 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 17:34:57.612143 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 17:34:57.615673 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 17:34:57.619424 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 17:34:57.625495 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 17:34:57.629334 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 17:34:57.632017 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 17:34:57.639366 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 17:34:57.642339 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 17:34:57.646058 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3233 17:34:57.652797 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3234 17:34:57.655662 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 17:34:57.659050 Total UI for P1: 0, mck2ui 16
3236 17:34:57.662254 best dqsien dly found for B0: ( 1, 3, 30)
3237 17:34:57.665674 Total UI for P1: 0, mck2ui 16
3238 17:34:57.668939 best dqsien dly found for B1: ( 1, 3, 30)
3239 17:34:57.672077 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3240 17:34:57.675547 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3241 17:34:57.675642
3242 17:34:57.679118 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3243 17:34:57.682223 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3244 17:34:57.685747 [Gating] SW calibration Done
3245 17:34:57.685860 ==
3246 17:34:57.688921 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 17:34:57.692553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 17:34:57.692651 ==
3249 17:34:57.695515 RX Vref Scan: 0
3250 17:34:57.695598
3251 17:34:57.699110 RX Vref 0 -> 0, step: 1
3252 17:34:57.699196
3253 17:34:57.699263 RX Delay -40 -> 252, step: 8
3254 17:34:57.705589 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3255 17:34:57.708882 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3256 17:34:57.712165 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3257 17:34:57.715553 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3258 17:34:57.718843 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3259 17:34:57.725811 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3260 17:34:57.728922 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3261 17:34:57.732497 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3262 17:34:57.735892 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3263 17:34:57.738775 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3264 17:34:57.742513 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3265 17:34:57.749257 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3266 17:34:57.752533 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3267 17:34:57.755909 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3268 17:34:57.758743 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3269 17:34:57.762443 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3270 17:34:57.765440 ==
3271 17:34:57.769234 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 17:34:57.772230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 17:34:57.772311 ==
3274 17:34:57.772375 DQS Delay:
3275 17:34:57.776008 DQS0 = 0, DQS1 = 0
3276 17:34:57.776089 DQM Delay:
3277 17:34:57.778886 DQM0 = 116, DQM1 = 108
3278 17:34:57.778966 DQ Delay:
3279 17:34:57.782587 DQ0 =123, DQ1 =115, DQ2 =99, DQ3 =119
3280 17:34:57.785619 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =119
3281 17:34:57.788970 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3282 17:34:57.792569 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3283 17:34:57.792649
3284 17:34:57.792713
3285 17:34:57.792772 ==
3286 17:34:57.795633 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 17:34:57.802590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 17:34:57.802672 ==
3289 17:34:57.802736
3290 17:34:57.802795
3291 17:34:57.802852 TX Vref Scan disable
3292 17:34:57.806020 == TX Byte 0 ==
3293 17:34:57.809045 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3294 17:34:57.812427 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3295 17:34:57.816071 == TX Byte 1 ==
3296 17:34:57.819082 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3297 17:34:57.822384 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3298 17:34:57.825722 ==
3299 17:34:57.829422 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 17:34:57.832825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 17:34:57.832966 ==
3302 17:34:57.844097 TX Vref=22, minBit 10, minWin=24, winSum=406
3303 17:34:57.846999 TX Vref=24, minBit 10, minWin=24, winSum=411
3304 17:34:57.850673 TX Vref=26, minBit 9, minWin=24, winSum=414
3305 17:34:57.853686 TX Vref=28, minBit 10, minWin=25, winSum=421
3306 17:34:57.857355 TX Vref=30, minBit 9, minWin=24, winSum=422
3307 17:34:57.863654 TX Vref=32, minBit 9, minWin=24, winSum=419
3308 17:34:57.867374 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 28
3309 17:34:57.868005
3310 17:34:57.870454 Final TX Range 1 Vref 28
3311 17:34:57.870956
3312 17:34:57.871439 ==
3313 17:34:57.874084 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 17:34:57.877575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 17:34:57.877994 ==
3316 17:34:57.880700
3317 17:34:57.881189
3318 17:34:57.881519 TX Vref Scan disable
3319 17:34:57.883991 == TX Byte 0 ==
3320 17:34:57.887276 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3321 17:34:57.890280 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3322 17:34:57.893878 == TX Byte 1 ==
3323 17:34:57.897703 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3324 17:34:57.903732 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3325 17:34:57.904151
3326 17:34:57.904478 [DATLAT]
3327 17:34:57.904781 Freq=1200, CH1 RK0
3328 17:34:57.905073
3329 17:34:57.906916 DATLAT Default: 0xd
3330 17:34:57.907422 0, 0xFFFF, sum = 0
3331 17:34:57.910608 1, 0xFFFF, sum = 0
3332 17:34:57.911028 2, 0xFFFF, sum = 0
3333 17:34:57.913488 3, 0xFFFF, sum = 0
3334 17:34:57.917155 4, 0xFFFF, sum = 0
3335 17:34:57.917578 5, 0xFFFF, sum = 0
3336 17:34:57.920580 6, 0xFFFF, sum = 0
3337 17:34:57.921001 7, 0xFFFF, sum = 0
3338 17:34:57.924206 8, 0xFFFF, sum = 0
3339 17:34:57.924761 9, 0xFFFF, sum = 0
3340 17:34:57.927075 10, 0xFFFF, sum = 0
3341 17:34:57.927527 11, 0xFFFF, sum = 0
3342 17:34:57.930484 12, 0x0, sum = 1
3343 17:34:57.930907 13, 0x0, sum = 2
3344 17:34:57.933883 14, 0x0, sum = 3
3345 17:34:57.934337 15, 0x0, sum = 4
3346 17:34:57.934672 best_step = 13
3347 17:34:57.936966
3348 17:34:57.937374 ==
3349 17:34:57.940536 Dram Type= 6, Freq= 0, CH_1, rank 0
3350 17:34:57.943885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3351 17:34:57.944346 ==
3352 17:34:57.944672 RX Vref Scan: 1
3353 17:34:57.944975
3354 17:34:57.946868 Set Vref Range= 32 -> 127
3355 17:34:57.947310
3356 17:34:57.950639 RX Vref 32 -> 127, step: 1
3357 17:34:57.951074
3358 17:34:57.953703 RX Delay -21 -> 252, step: 4
3359 17:34:57.954119
3360 17:34:57.957232 Set Vref, RX VrefLevel [Byte0]: 32
3361 17:34:57.960255 [Byte1]: 32
3362 17:34:57.960753
3363 17:34:57.963635 Set Vref, RX VrefLevel [Byte0]: 33
3364 17:34:57.967092 [Byte1]: 33
3365 17:34:57.970636
3366 17:34:57.971041 Set Vref, RX VrefLevel [Byte0]: 34
3367 17:34:57.973517 [Byte1]: 34
3368 17:34:57.978150
3369 17:34:57.978573 Set Vref, RX VrefLevel [Byte0]: 35
3370 17:34:57.981894 [Byte1]: 35
3371 17:34:57.986017
3372 17:34:57.986423 Set Vref, RX VrefLevel [Byte0]: 36
3373 17:34:57.989530 [Byte1]: 36
3374 17:34:57.994280
3375 17:34:57.994695 Set Vref, RX VrefLevel [Byte0]: 37
3376 17:34:57.997473 [Byte1]: 37
3377 17:34:58.002320
3378 17:34:58.002742 Set Vref, RX VrefLevel [Byte0]: 38
3379 17:34:58.005595 [Byte1]: 38
3380 17:34:58.010356
3381 17:34:58.010809 Set Vref, RX VrefLevel [Byte0]: 39
3382 17:34:58.013194 [Byte1]: 39
3383 17:34:58.018042
3384 17:34:58.018450 Set Vref, RX VrefLevel [Byte0]: 40
3385 17:34:58.021129 [Byte1]: 40
3386 17:34:58.025835
3387 17:34:58.026325 Set Vref, RX VrefLevel [Byte0]: 41
3388 17:34:58.028924 [Byte1]: 41
3389 17:34:58.033788
3390 17:34:58.034232 Set Vref, RX VrefLevel [Byte0]: 42
3391 17:34:58.037237 [Byte1]: 42
3392 17:34:58.041509
3393 17:34:58.041953 Set Vref, RX VrefLevel [Byte0]: 43
3394 17:34:58.045167 [Byte1]: 43
3395 17:34:58.049376
3396 17:34:58.049820 Set Vref, RX VrefLevel [Byte0]: 44
3397 17:34:58.053151 [Byte1]: 44
3398 17:34:58.057831
3399 17:34:58.058253 Set Vref, RX VrefLevel [Byte0]: 45
3400 17:34:58.060797 [Byte1]: 45
3401 17:34:58.065259
3402 17:34:58.065665 Set Vref, RX VrefLevel [Byte0]: 46
3403 17:34:58.068672 [Byte1]: 46
3404 17:34:58.073638
3405 17:34:58.074047 Set Vref, RX VrefLevel [Byte0]: 47
3406 17:34:58.076441 [Byte1]: 47
3407 17:34:58.081367
3408 17:34:58.081775 Set Vref, RX VrefLevel [Byte0]: 48
3409 17:34:58.084882 [Byte1]: 48
3410 17:34:58.089151
3411 17:34:58.089568 Set Vref, RX VrefLevel [Byte0]: 49
3412 17:34:58.092548 [Byte1]: 49
3413 17:34:58.096979
3414 17:34:58.097479 Set Vref, RX VrefLevel [Byte0]: 50
3415 17:34:58.100306 [Byte1]: 50
3416 17:34:58.105295
3417 17:34:58.105712 Set Vref, RX VrefLevel [Byte0]: 51
3418 17:34:58.108166 [Byte1]: 51
3419 17:34:58.113234
3420 17:34:58.113683 Set Vref, RX VrefLevel [Byte0]: 52
3421 17:34:58.116206 [Byte1]: 52
3422 17:34:58.120829
3423 17:34:58.121238 Set Vref, RX VrefLevel [Byte0]: 53
3424 17:34:58.124242 [Byte1]: 53
3425 17:34:58.128726
3426 17:34:58.129268 Set Vref, RX VrefLevel [Byte0]: 54
3427 17:34:58.132254 [Byte1]: 54
3428 17:34:58.136564
3429 17:34:58.136972 Set Vref, RX VrefLevel [Byte0]: 55
3430 17:34:58.139895 [Byte1]: 55
3431 17:34:58.144864
3432 17:34:58.145270 Set Vref, RX VrefLevel [Byte0]: 56
3433 17:34:58.147931 [Byte1]: 56
3434 17:34:58.152448
3435 17:34:58.152860 Set Vref, RX VrefLevel [Byte0]: 57
3436 17:34:58.155627 [Byte1]: 57
3437 17:34:58.160364
3438 17:34:58.160865 Set Vref, RX VrefLevel [Byte0]: 58
3439 17:34:58.163816 [Byte1]: 58
3440 17:34:58.168623
3441 17:34:58.169051 Set Vref, RX VrefLevel [Byte0]: 59
3442 17:34:58.171743 [Byte1]: 59
3443 17:34:58.176385
3444 17:34:58.176793 Set Vref, RX VrefLevel [Byte0]: 60
3445 17:34:58.179646 [Byte1]: 60
3446 17:34:58.184481
3447 17:34:58.184893 Set Vref, RX VrefLevel [Byte0]: 61
3448 17:34:58.187968 [Byte1]: 61
3449 17:34:58.191892
3450 17:34:58.192300 Set Vref, RX VrefLevel [Byte0]: 62
3451 17:34:58.195343 [Byte1]: 62
3452 17:34:58.200037
3453 17:34:58.200457 Set Vref, RX VrefLevel [Byte0]: 63
3454 17:34:58.203279 [Byte1]: 63
3455 17:34:58.208009
3456 17:34:58.208426 Set Vref, RX VrefLevel [Byte0]: 64
3457 17:34:58.211714 [Byte1]: 64
3458 17:34:58.215771
3459 17:34:58.216186 Set Vref, RX VrefLevel [Byte0]: 65
3460 17:34:58.218995 [Byte1]: 65
3461 17:34:58.224017
3462 17:34:58.224432 Set Vref, RX VrefLevel [Byte0]: 66
3463 17:34:58.227377 [Byte1]: 66
3464 17:34:58.231685
3465 17:34:58.232106 Final RX Vref Byte 0 = 56 to rank0
3466 17:34:58.235095 Final RX Vref Byte 1 = 52 to rank0
3467 17:34:58.238787 Final RX Vref Byte 0 = 56 to rank1
3468 17:34:58.241420 Final RX Vref Byte 1 = 52 to rank1==
3469 17:34:58.245259 Dram Type= 6, Freq= 0, CH_1, rank 0
3470 17:34:58.251795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 17:34:58.252232 ==
3472 17:34:58.252567 DQS Delay:
3473 17:34:58.252931 DQS0 = 0, DQS1 = 0
3474 17:34:58.255054 DQM Delay:
3475 17:34:58.255511 DQM0 = 114, DQM1 = 106
3476 17:34:58.258338 DQ Delay:
3477 17:34:58.261972 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3478 17:34:58.264924 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3479 17:34:58.268316 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =100
3480 17:34:58.272081 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =112
3481 17:34:58.272505
3482 17:34:58.272835
3483 17:34:58.278509 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3484 17:34:58.281233 CH1 RK0: MR19=303, MR18=F0F7
3485 17:34:58.288508 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3486 17:34:58.288930
3487 17:34:58.291279 ----->DramcWriteLeveling(PI) begin...
3488 17:34:58.291754 ==
3489 17:34:58.294771 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 17:34:58.297992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 17:34:58.301544 ==
3492 17:34:58.301989 Write leveling (Byte 0): 25 => 25
3493 17:34:58.305324 Write leveling (Byte 1): 29 => 29
3494 17:34:58.308039 DramcWriteLeveling(PI) end<-----
3495 17:34:58.308461
3496 17:34:58.308795 ==
3497 17:34:58.311493 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 17:34:58.318465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 17:34:58.318888 ==
3500 17:34:58.319222 [Gating] SW mode calibration
3501 17:34:58.328098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3502 17:34:58.331726 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3503 17:34:58.334937 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3504 17:34:58.341619 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 17:34:58.345330 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 17:34:58.348188 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 17:34:58.354650 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 17:34:58.358440 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 17:34:58.361351 0 15 24 | B1->B0 | 3333 2424 | 1 0 | (1 1) (0 0)
3510 17:34:58.368258 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3511 17:34:58.371241 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 17:34:58.374869 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 17:34:58.381894 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 17:34:58.385422 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 17:34:58.388330 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 17:34:58.394691 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3517 17:34:58.397948 1 0 24 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
3518 17:34:58.401320 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3519 17:34:58.408305 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 17:34:58.411654 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 17:34:58.414876 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 17:34:58.421844 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 17:34:58.425041 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 17:34:58.428587 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 17:34:58.431737 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3526 17:34:58.438131 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3527 17:34:58.441866 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 17:34:58.444970 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 17:34:58.451334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 17:34:58.454827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 17:34:58.458281 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 17:34:58.464603 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 17:34:58.468349 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 17:34:58.471778 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 17:34:58.478102 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 17:34:58.481618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 17:34:58.484711 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 17:34:58.490953 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 17:34:58.494693 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 17:34:58.498021 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 17:34:58.504610 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3542 17:34:58.507753 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 17:34:58.510923 Total UI for P1: 0, mck2ui 16
3544 17:34:58.514162 best dqsien dly found for B0: ( 1, 3, 24)
3545 17:34:58.517919 Total UI for P1: 0, mck2ui 16
3546 17:34:58.521100 best dqsien dly found for B1: ( 1, 3, 24)
3547 17:34:58.524143 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3548 17:34:58.527203 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3549 17:34:58.527787
3550 17:34:58.530898 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3551 17:34:58.537313 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3552 17:34:58.537767 [Gating] SW calibration Done
3553 17:34:58.538123 ==
3554 17:34:58.541003 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 17:34:58.547729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 17:34:58.548226 ==
3557 17:34:58.548624 RX Vref Scan: 0
3558 17:34:58.548934
3559 17:34:58.550461 RX Vref 0 -> 0, step: 1
3560 17:34:58.550888
3561 17:34:58.553755 RX Delay -40 -> 252, step: 8
3562 17:34:58.557552 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3563 17:34:58.560173 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3564 17:34:58.564067 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3565 17:34:58.570787 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3566 17:34:58.573771 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3567 17:34:58.577022 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3568 17:34:58.580090 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3569 17:34:58.583342 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3570 17:34:58.587003 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3571 17:34:58.593283 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3572 17:34:58.596418 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3573 17:34:58.599872 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3574 17:34:58.603485 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3575 17:34:58.609835 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3576 17:34:58.613474 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3577 17:34:58.616629 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3578 17:34:58.617086 ==
3579 17:34:58.620000 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 17:34:58.623346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 17:34:58.623963 ==
3582 17:34:58.626547 DQS Delay:
3583 17:34:58.626963 DQS0 = 0, DQS1 = 0
3584 17:34:58.629469 DQM Delay:
3585 17:34:58.630033 DQM0 = 110, DQM1 = 108
3586 17:34:58.633047 DQ Delay:
3587 17:34:58.636669 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3588 17:34:58.639661 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3589 17:34:58.643215 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3590 17:34:58.646685 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3591 17:34:58.647102
3592 17:34:58.647484
3593 17:34:58.647884 ==
3594 17:34:58.649868 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 17:34:58.653105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 17:34:58.653526 ==
3597 17:34:58.653855
3598 17:34:58.654158
3599 17:34:58.656625 TX Vref Scan disable
3600 17:34:58.659913 == TX Byte 0 ==
3601 17:34:58.662624 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3602 17:34:58.666143 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3603 17:34:58.669447 == TX Byte 1 ==
3604 17:34:58.672836 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3605 17:34:58.676428 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3606 17:34:58.676847 ==
3607 17:34:58.679477 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 17:34:58.682595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 17:34:58.686039 ==
3610 17:34:58.696170 TX Vref=22, minBit 8, minWin=25, winSum=421
3611 17:34:58.699870 TX Vref=24, minBit 9, minWin=25, winSum=427
3612 17:34:58.702966 TX Vref=26, minBit 8, minWin=26, winSum=436
3613 17:34:58.706566 TX Vref=28, minBit 0, minWin=27, winSum=437
3614 17:34:58.709585 TX Vref=30, minBit 8, minWin=26, winSum=433
3615 17:34:58.716621 TX Vref=32, minBit 8, minWin=25, winSum=432
3616 17:34:58.719455 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
3617 17:34:58.719896
3618 17:34:58.722974 Final TX Range 1 Vref 28
3619 17:34:58.723429
3620 17:34:58.723777 ==
3621 17:34:58.726486 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 17:34:58.729525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 17:34:58.729990 ==
3624 17:34:58.732952
3625 17:34:58.733408
3626 17:34:58.733944 TX Vref Scan disable
3627 17:34:58.735989 == TX Byte 0 ==
3628 17:34:58.739659 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3629 17:34:58.742698 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3630 17:34:58.745946 == TX Byte 1 ==
3631 17:34:58.749603 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3632 17:34:58.752865 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3633 17:34:58.756466
3634 17:34:58.756885 [DATLAT]
3635 17:34:58.757218 Freq=1200, CH1 RK1
3636 17:34:58.757528
3637 17:34:58.759341 DATLAT Default: 0xd
3638 17:34:58.759801 0, 0xFFFF, sum = 0
3639 17:34:58.763072 1, 0xFFFF, sum = 0
3640 17:34:58.763537 2, 0xFFFF, sum = 0
3641 17:34:58.766286 3, 0xFFFF, sum = 0
3642 17:34:58.769660 4, 0xFFFF, sum = 0
3643 17:34:58.770085 5, 0xFFFF, sum = 0
3644 17:34:58.772874 6, 0xFFFF, sum = 0
3645 17:34:58.773423 7, 0xFFFF, sum = 0
3646 17:34:58.776260 8, 0xFFFF, sum = 0
3647 17:34:58.776712 9, 0xFFFF, sum = 0
3648 17:34:58.779175 10, 0xFFFF, sum = 0
3649 17:34:58.779650 11, 0xFFFF, sum = 0
3650 17:34:58.782598 12, 0x0, sum = 1
3651 17:34:58.783019 13, 0x0, sum = 2
3652 17:34:58.785550 14, 0x0, sum = 3
3653 17:34:58.785970 15, 0x0, sum = 4
3654 17:34:58.789331 best_step = 13
3655 17:34:58.789743
3656 17:34:58.790070 ==
3657 17:34:58.792692 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 17:34:58.795507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 17:34:58.795961 ==
3660 17:34:58.796296 RX Vref Scan: 0
3661 17:34:58.799333
3662 17:34:58.799807 RX Vref 0 -> 0, step: 1
3663 17:34:58.800136
3664 17:34:58.802816 RX Delay -21 -> 252, step: 4
3665 17:34:58.809100 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3666 17:34:58.812237 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3667 17:34:58.815279 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3668 17:34:58.818799 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3669 17:34:58.822211 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3670 17:34:58.828549 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3671 17:34:58.832214 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3672 17:34:58.835263 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3673 17:34:58.838908 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3674 17:34:58.842043 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3675 17:34:58.845505 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3676 17:34:58.851793 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3677 17:34:58.855586 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3678 17:34:58.859015 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3679 17:34:58.862067 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3680 17:34:58.868107 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3681 17:34:58.868408 ==
3682 17:34:58.871727 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 17:34:58.875136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 17:34:58.875565 ==
3685 17:34:58.875810 DQS Delay:
3686 17:34:58.878420 DQS0 = 0, DQS1 = 0
3687 17:34:58.878715 DQM Delay:
3688 17:34:58.881566 DQM0 = 110, DQM1 = 110
3689 17:34:58.881941 DQ Delay:
3690 17:34:58.884677 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3691 17:34:58.888091 DQ4 =108, DQ5 =118, DQ6 =120, DQ7 =110
3692 17:34:58.891622 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3693 17:34:58.895068 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =118
3694 17:34:58.895366
3695 17:34:58.898136
3696 17:34:58.904555 [DQSOSCAuto] RK1, (LSB)MR18= 0xf404, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3697 17:34:58.907885 CH1 RK1: MR19=304, MR18=F404
3698 17:34:58.914644 CH1_RK1: MR19=0x304, MR18=0xF404, DQSOSC=408, MR23=63, INC=39, DEC=26
3699 17:34:58.917885 [RxdqsGatingPostProcess] freq 1200
3700 17:34:58.921304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3701 17:34:58.924749 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 17:34:58.928063 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 17:34:58.931079 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 17:34:58.934890 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 17:34:58.938172 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 17:34:58.941571 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 17:34:58.944930 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 17:34:58.948359 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 17:34:58.951435 Pre-setting of DQS Precalculation
3710 17:34:58.954611 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3711 17:34:58.961322 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3712 17:34:58.971002 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3713 17:34:58.971455
3714 17:34:58.971754
3715 17:34:58.974176 [Calibration Summary] 2400 Mbps
3716 17:34:58.974587 CH 0, Rank 0
3717 17:34:58.977940 SW Impedance : PASS
3718 17:34:58.978237 DUTY Scan : NO K
3719 17:34:58.980802 ZQ Calibration : PASS
3720 17:34:58.984330 Jitter Meter : NO K
3721 17:34:58.984628 CBT Training : PASS
3722 17:34:58.987728 Write leveling : PASS
3723 17:34:58.988105 RX DQS gating : PASS
3724 17:34:58.990678 RX DQ/DQS(RDDQC) : PASS
3725 17:34:58.994340 TX DQ/DQS : PASS
3726 17:34:58.994769 RX DATLAT : PASS
3727 17:34:58.997609 RX DQ/DQS(Engine): PASS
3728 17:34:59.001094 TX OE : NO K
3729 17:34:59.001508 All Pass.
3730 17:34:59.001850
3731 17:34:59.002176 CH 0, Rank 1
3732 17:34:59.004282 SW Impedance : PASS
3733 17:34:59.007211 DUTY Scan : NO K
3734 17:34:59.007605 ZQ Calibration : PASS
3735 17:34:59.010757 Jitter Meter : NO K
3736 17:34:59.014449 CBT Training : PASS
3737 17:34:59.014749 Write leveling : PASS
3738 17:34:59.017434 RX DQS gating : PASS
3739 17:34:59.020938 RX DQ/DQS(RDDQC) : PASS
3740 17:34:59.021236 TX DQ/DQS : PASS
3741 17:34:59.023849 RX DATLAT : PASS
3742 17:34:59.027351 RX DQ/DQS(Engine): PASS
3743 17:34:59.027712 TX OE : NO K
3744 17:34:59.030764 All Pass.
3745 17:34:59.031058
3746 17:34:59.031290 CH 1, Rank 0
3747 17:34:59.034487 SW Impedance : PASS
3748 17:34:59.034889 DUTY Scan : NO K
3749 17:34:59.037127 ZQ Calibration : PASS
3750 17:34:59.040900 Jitter Meter : NO K
3751 17:34:59.041195 CBT Training : PASS
3752 17:34:59.043936 Write leveling : PASS
3753 17:34:59.044230 RX DQS gating : PASS
3754 17:34:59.047649 RX DQ/DQS(RDDQC) : PASS
3755 17:34:59.050286 TX DQ/DQS : PASS
3756 17:34:59.050584 RX DATLAT : PASS
3757 17:34:59.053641 RX DQ/DQS(Engine): PASS
3758 17:34:59.057147 TX OE : NO K
3759 17:34:59.057443 All Pass.
3760 17:34:59.057676
3761 17:34:59.057892 CH 1, Rank 1
3762 17:34:59.060200 SW Impedance : PASS
3763 17:34:59.063743 DUTY Scan : NO K
3764 17:34:59.064038 ZQ Calibration : PASS
3765 17:34:59.066842 Jitter Meter : NO K
3766 17:34:59.070316 CBT Training : PASS
3767 17:34:59.070610 Write leveling : PASS
3768 17:34:59.073659 RX DQS gating : PASS
3769 17:34:59.077163 RX DQ/DQS(RDDQC) : PASS
3770 17:34:59.077520 TX DQ/DQS : PASS
3771 17:34:59.080520 RX DATLAT : PASS
3772 17:34:59.083419 RX DQ/DQS(Engine): PASS
3773 17:34:59.083720 TX OE : NO K
3774 17:34:59.087077 All Pass.
3775 17:34:59.087492
3776 17:34:59.087817 DramC Write-DBI off
3777 17:34:59.090139 PER_BANK_REFRESH: Hybrid Mode
3778 17:34:59.090605 TX_TRACKING: ON
3779 17:34:59.100474 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3780 17:34:59.103434 [FAST_K] Save calibration result to emmc
3781 17:34:59.106478 dramc_set_vcore_voltage set vcore to 650000
3782 17:34:59.109905 Read voltage for 600, 5
3783 17:34:59.110202 Vio18 = 0
3784 17:34:59.113122 Vcore = 650000
3785 17:34:59.113428 Vdram = 0
3786 17:34:59.113754 Vddq = 0
3787 17:34:59.116898 Vmddr = 0
3788 17:34:59.119994 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3789 17:34:59.126574 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3790 17:34:59.127008 MEM_TYPE=3, freq_sel=19
3791 17:34:59.129909 sv_algorithm_assistance_LP4_1600
3792 17:34:59.136600 ============ PULL DRAM RESETB DOWN ============
3793 17:34:59.139789 ========== PULL DRAM RESETB DOWN end =========
3794 17:34:59.142937 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3795 17:34:59.146639 ===================================
3796 17:34:59.150048 LPDDR4 DRAM CONFIGURATION
3797 17:34:59.153096 ===================================
3798 17:34:59.153471 EX_ROW_EN[0] = 0x0
3799 17:34:59.156439 EX_ROW_EN[1] = 0x0
3800 17:34:59.160106 LP4Y_EN = 0x0
3801 17:34:59.160509 WORK_FSP = 0x0
3802 17:34:59.163104 WL = 0x2
3803 17:34:59.163522 RL = 0x2
3804 17:34:59.166274 BL = 0x2
3805 17:34:59.166702 RPST = 0x0
3806 17:34:59.169697 RD_PRE = 0x0
3807 17:34:59.170101 WR_PRE = 0x1
3808 17:34:59.173030 WR_PST = 0x0
3809 17:34:59.173327 DBI_WR = 0x0
3810 17:34:59.176565 DBI_RD = 0x0
3811 17:34:59.176861 OTF = 0x1
3812 17:34:59.179457 ===================================
3813 17:34:59.182817 ===================================
3814 17:34:59.185991 ANA top config
3815 17:34:59.189593 ===================================
3816 17:34:59.190043 DLL_ASYNC_EN = 0
3817 17:34:59.192688 ALL_SLAVE_EN = 1
3818 17:34:59.196439 NEW_RANK_MODE = 1
3819 17:34:59.199297 DLL_IDLE_MODE = 1
3820 17:34:59.202879 LP45_APHY_COMB_EN = 1
3821 17:34:59.203301 TX_ODT_DIS = 1
3822 17:34:59.206248 NEW_8X_MODE = 1
3823 17:34:59.209286 ===================================
3824 17:34:59.212469 ===================================
3825 17:34:59.216290 data_rate = 1200
3826 17:34:59.219277 CKR = 1
3827 17:34:59.222354 DQ_P2S_RATIO = 8
3828 17:34:59.225744 ===================================
3829 17:34:59.226049 CA_P2S_RATIO = 8
3830 17:34:59.229248 DQ_CA_OPEN = 0
3831 17:34:59.232892 DQ_SEMI_OPEN = 0
3832 17:34:59.235867 CA_SEMI_OPEN = 0
3833 17:34:59.239007 CA_FULL_RATE = 0
3834 17:34:59.242492 DQ_CKDIV4_EN = 1
3835 17:34:59.242858 CA_CKDIV4_EN = 1
3836 17:34:59.245600 CA_PREDIV_EN = 0
3837 17:34:59.249000 PH8_DLY = 0
3838 17:34:59.252555 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3839 17:34:59.255588 DQ_AAMCK_DIV = 4
3840 17:34:59.258877 CA_AAMCK_DIV = 4
3841 17:34:59.259337 CA_ADMCK_DIV = 4
3842 17:34:59.262745 DQ_TRACK_CA_EN = 0
3843 17:34:59.266016 CA_PICK = 600
3844 17:34:59.268915 CA_MCKIO = 600
3845 17:34:59.272384 MCKIO_SEMI = 0
3846 17:34:59.275429 PLL_FREQ = 2288
3847 17:34:59.279000 DQ_UI_PI_RATIO = 32
3848 17:34:59.282637 CA_UI_PI_RATIO = 0
3849 17:34:59.285244 ===================================
3850 17:34:59.288811 ===================================
3851 17:34:59.289111 memory_type:LPDDR4
3852 17:34:59.291995 GP_NUM : 10
3853 17:34:59.295415 SRAM_EN : 1
3854 17:34:59.295731 MD32_EN : 0
3855 17:34:59.298521 ===================================
3856 17:34:59.302323 [ANA_INIT] >>>>>>>>>>>>>>
3857 17:34:59.305138 <<<<<< [CONFIGURE PHASE]: ANA_TX
3858 17:34:59.308700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3859 17:34:59.312249 ===================================
3860 17:34:59.315475 data_rate = 1200,PCW = 0X5800
3861 17:34:59.318260 ===================================
3862 17:34:59.321463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3863 17:34:59.324890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 17:34:59.331528 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 17:34:59.334910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3866 17:34:59.338849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3867 17:34:59.341681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3868 17:34:59.344928 [ANA_INIT] flow start
3869 17:34:59.348558 [ANA_INIT] PLL >>>>>>>>
3870 17:34:59.348958 [ANA_INIT] PLL <<<<<<<<
3871 17:34:59.351341 [ANA_INIT] MIDPI >>>>>>>>
3872 17:34:59.354640 [ANA_INIT] MIDPI <<<<<<<<
3873 17:34:59.358089 [ANA_INIT] DLL >>>>>>>>
3874 17:34:59.358473 [ANA_INIT] flow end
3875 17:34:59.361190 ============ LP4 DIFF to SE enter ============
3876 17:34:59.368009 ============ LP4 DIFF to SE exit ============
3877 17:34:59.368396 [ANA_INIT] <<<<<<<<<<<<<
3878 17:34:59.371488 [Flow] Enable top DCM control >>>>>
3879 17:34:59.374652 [Flow] Enable top DCM control <<<<<
3880 17:34:59.377972 Enable DLL master slave shuffle
3881 17:34:59.384919 ==============================================================
3882 17:34:59.385377 Gating Mode config
3883 17:34:59.391164 ==============================================================
3884 17:34:59.394158 Config description:
3885 17:34:59.404604 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3886 17:34:59.410991 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3887 17:34:59.414562 SELPH_MODE 0: By rank 1: By Phase
3888 17:34:59.420890 ==============================================================
3889 17:34:59.424562 GAT_TRACK_EN = 1
3890 17:34:59.427743 RX_GATING_MODE = 2
3891 17:34:59.428132 RX_GATING_TRACK_MODE = 2
3892 17:34:59.430522 SELPH_MODE = 1
3893 17:34:59.434126 PICG_EARLY_EN = 1
3894 17:34:59.437445 VALID_LAT_VALUE = 1
3895 17:34:59.444195 ==============================================================
3896 17:34:59.447784 Enter into Gating configuration >>>>
3897 17:34:59.450901 Exit from Gating configuration <<<<
3898 17:34:59.453515 Enter into DVFS_PRE_config >>>>>
3899 17:34:59.464038 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3900 17:34:59.467308 Exit from DVFS_PRE_config <<<<<
3901 17:34:59.470137 Enter into PICG configuration >>>>
3902 17:34:59.473402 Exit from PICG configuration <<<<
3903 17:34:59.476893 [RX_INPUT] configuration >>>>>
3904 17:34:59.479992 [RX_INPUT] configuration <<<<<
3905 17:34:59.483400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3906 17:34:59.490161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3907 17:34:59.496638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 17:34:59.503305 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 17:34:59.506640 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 17:34:59.513852 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 17:34:59.519920 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3912 17:34:59.523430 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3913 17:34:59.527115 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3914 17:34:59.530037 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3915 17:34:59.533781 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3916 17:34:59.540004 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 17:34:59.543501 ===================================
3918 17:34:59.546935 LPDDR4 DRAM CONFIGURATION
3919 17:34:59.550468 ===================================
3920 17:34:59.550889 EX_ROW_EN[0] = 0x0
3921 17:34:59.553687 EX_ROW_EN[1] = 0x0
3922 17:34:59.554106 LP4Y_EN = 0x0
3923 17:34:59.556886 WORK_FSP = 0x0
3924 17:34:59.557310 WL = 0x2
3925 17:34:59.560196 RL = 0x2
3926 17:34:59.560615 BL = 0x2
3927 17:34:59.563797 RPST = 0x0
3928 17:34:59.564230 RD_PRE = 0x0
3929 17:34:59.566709 WR_PRE = 0x1
3930 17:34:59.567076 WR_PST = 0x0
3931 17:34:59.570372 DBI_WR = 0x0
3932 17:34:59.570799 DBI_RD = 0x0
3933 17:34:59.573372 OTF = 0x1
3934 17:34:59.577071 ===================================
3935 17:34:59.579995 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3936 17:34:59.582969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3937 17:34:59.589603 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 17:34:59.593382 ===================================
3939 17:34:59.593802 LPDDR4 DRAM CONFIGURATION
3940 17:34:59.596094 ===================================
3941 17:34:59.599673 EX_ROW_EN[0] = 0x10
3942 17:34:59.602864 EX_ROW_EN[1] = 0x0
3943 17:34:59.603298 LP4Y_EN = 0x0
3944 17:34:59.606588 WORK_FSP = 0x0
3945 17:34:59.607006 WL = 0x2
3946 17:34:59.609460 RL = 0x2
3947 17:34:59.609882 BL = 0x2
3948 17:34:59.613149 RPST = 0x0
3949 17:34:59.613568 RD_PRE = 0x0
3950 17:34:59.616393 WR_PRE = 0x1
3951 17:34:59.616814 WR_PST = 0x0
3952 17:34:59.619579 DBI_WR = 0x0
3953 17:34:59.619661 DBI_RD = 0x0
3954 17:34:59.622389 OTF = 0x1
3955 17:34:59.626089 ===================================
3956 17:34:59.632146 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3957 17:34:59.635659 nWR fixed to 30
3958 17:34:59.638786 [ModeRegInit_LP4] CH0 RK0
3959 17:34:59.638897 [ModeRegInit_LP4] CH0 RK1
3960 17:34:59.642161 [ModeRegInit_LP4] CH1 RK0
3961 17:34:59.645744 [ModeRegInit_LP4] CH1 RK1
3962 17:34:59.645831 match AC timing 17
3963 17:34:59.652198 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3964 17:34:59.655340 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3965 17:34:59.658656 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3966 17:34:59.665463 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3967 17:34:59.668713 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3968 17:34:59.668849 ==
3969 17:34:59.672302 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 17:34:59.675397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 17:34:59.675598 ==
3972 17:34:59.682132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 17:34:59.688885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 17:34:59.692779 [CA 0] Center 37 (7~67) winsize 61
3975 17:34:59.695631 [CA 1] Center 37 (7~67) winsize 61
3976 17:34:59.699019 [CA 2] Center 35 (5~65) winsize 61
3977 17:34:59.702314 [CA 3] Center 35 (5~65) winsize 61
3978 17:34:59.705734 [CA 4] Center 34 (4~65) winsize 62
3979 17:34:59.708876 [CA 5] Center 34 (4~65) winsize 62
3980 17:34:59.709262
3981 17:34:59.712203 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 17:34:59.712704
3983 17:34:59.715475 [CATrainingPosCal] consider 1 rank data
3984 17:34:59.718794 u2DelayCellTimex100 = 270/100 ps
3985 17:34:59.722257 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3986 17:34:59.725301 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3987 17:34:59.728440 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3988 17:34:59.731648 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3989 17:34:59.734882 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3990 17:34:59.741473 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
3991 17:34:59.741562
3992 17:34:59.745198 CA PerBit enable=1, Macro0, CA PI delay=34
3993 17:34:59.745275
3994 17:34:59.748573 [CBTSetCACLKResult] CA Dly = 34
3995 17:34:59.748655 CS Dly: 6 (0~37)
3996 17:34:59.748724 ==
3997 17:34:59.751706 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 17:34:59.755162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 17:34:59.758362 ==
4000 17:34:59.761359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4001 17:34:59.768039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4002 17:34:59.771541 [CA 0] Center 37 (7~67) winsize 61
4003 17:34:59.775301 [CA 1] Center 36 (6~67) winsize 62
4004 17:34:59.778295 [CA 2] Center 35 (5~65) winsize 61
4005 17:34:59.781467 [CA 3] Center 35 (5~65) winsize 61
4006 17:34:59.784571 [CA 4] Center 34 (4~65) winsize 62
4007 17:34:59.787962 [CA 5] Center 33 (3~64) winsize 62
4008 17:34:59.788201
4009 17:34:59.791471 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4010 17:34:59.791771
4011 17:34:59.794860 [CATrainingPosCal] consider 2 rank data
4012 17:34:59.798636 u2DelayCellTimex100 = 270/100 ps
4013 17:34:59.801884 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4014 17:34:59.804738 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4015 17:34:59.811806 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4016 17:34:59.814645 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4017 17:34:59.818263 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4018 17:34:59.821513 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4019 17:34:59.822012
4020 17:34:59.824986 CA PerBit enable=1, Macro0, CA PI delay=34
4021 17:34:59.825382
4022 17:34:59.828504 [CBTSetCACLKResult] CA Dly = 34
4023 17:34:59.828962 CS Dly: 6 (0~38)
4024 17:34:59.829277
4025 17:34:59.831157 ----->DramcWriteLeveling(PI) begin...
4026 17:34:59.834266 ==
4027 17:34:59.837698 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 17:34:59.841367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 17:34:59.841876 ==
4030 17:34:59.844626 Write leveling (Byte 0): 33 => 33
4031 17:34:59.847643 Write leveling (Byte 1): 30 => 30
4032 17:34:59.850926 DramcWriteLeveling(PI) end<-----
4033 17:34:59.851328
4034 17:34:59.851837 ==
4035 17:34:59.854372 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 17:34:59.857671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 17:34:59.858058 ==
4038 17:34:59.861165 [Gating] SW mode calibration
4039 17:34:59.867822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4040 17:34:59.874346 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4041 17:34:59.877472 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 17:34:59.881199 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 17:34:59.887756 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 17:34:59.890890 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4045 17:34:59.894243 0 9 16 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 0)
4046 17:34:59.897460 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 17:34:59.904040 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 17:34:59.907587 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 17:34:59.910792 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 17:34:59.917499 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 17:34:59.920745 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 17:34:59.927037 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4053 17:34:59.930923 0 10 16 | B1->B0 | 2a2a 3d3d | 0 0 | (0 0) (0 0)
4054 17:34:59.933748 0 10 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4055 17:34:59.937221 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 17:34:59.943456 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 17:34:59.947260 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 17:34:59.950045 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 17:34:59.956951 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 17:34:59.960270 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 17:34:59.963650 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4062 17:34:59.970239 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 17:34:59.973432 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 17:34:59.976489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 17:34:59.983359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 17:34:59.987080 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 17:34:59.990457 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 17:34:59.996829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 17:34:59.999791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 17:35:00.003452 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 17:35:00.009614 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 17:35:00.013179 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 17:35:00.016204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 17:35:00.022845 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 17:35:00.026424 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 17:35:00.029790 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 17:35:00.036150 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4078 17:35:00.039555 Total UI for P1: 0, mck2ui 16
4079 17:35:00.043368 best dqsien dly found for B0: ( 0, 13, 14)
4080 17:35:00.046245 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 17:35:00.049613 Total UI for P1: 0, mck2ui 16
4082 17:35:00.052660 best dqsien dly found for B1: ( 0, 13, 16)
4083 17:35:00.056124 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4084 17:35:00.059848 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4085 17:35:00.060389
4086 17:35:00.062517 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4087 17:35:00.069253 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4088 17:35:00.069652 [Gating] SW calibration Done
4089 17:35:00.070057 ==
4090 17:35:00.072684 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 17:35:00.079307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 17:35:00.079746 ==
4093 17:35:00.080149 RX Vref Scan: 0
4094 17:35:00.080530
4095 17:35:00.082440 RX Vref 0 -> 0, step: 1
4096 17:35:00.082836
4097 17:35:00.085626 RX Delay -230 -> 252, step: 16
4098 17:35:00.089111 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4099 17:35:00.092636 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4100 17:35:00.096402 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4101 17:35:00.102251 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4102 17:35:00.105513 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4103 17:35:00.108881 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4104 17:35:00.111979 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4105 17:35:00.118898 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4106 17:35:00.122189 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4107 17:35:00.125063 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4108 17:35:00.128540 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4109 17:35:00.135820 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4110 17:35:00.138848 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4111 17:35:00.141619 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4112 17:35:00.145246 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4113 17:35:00.151793 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4114 17:35:00.152202 ==
4115 17:35:00.154795 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 17:35:00.158059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 17:35:00.158454 ==
4118 17:35:00.158856 DQS Delay:
4119 17:35:00.161402 DQS0 = 0, DQS1 = 0
4120 17:35:00.161796 DQM Delay:
4121 17:35:00.165179 DQM0 = 37, DQM1 = 30
4122 17:35:00.165571 DQ Delay:
4123 17:35:00.168126 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4124 17:35:00.171309 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4125 17:35:00.174746 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4126 17:35:00.178573 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4127 17:35:00.178971
4128 17:35:00.179370
4129 17:35:00.179789 ==
4130 17:35:00.181625 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 17:35:00.185145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 17:35:00.185540 ==
4133 17:35:00.187901
4134 17:35:00.188417
4135 17:35:00.188871 TX Vref Scan disable
4136 17:35:00.191262 == TX Byte 0 ==
4137 17:35:00.194349 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4138 17:35:00.197939 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4139 17:35:00.200800 == TX Byte 1 ==
4140 17:35:00.204131 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4141 17:35:00.207329 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4142 17:35:00.211185 ==
4143 17:35:00.211295 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 17:35:00.217523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 17:35:00.217632 ==
4146 17:35:00.217725
4147 17:35:00.217815
4148 17:35:00.221123 TX Vref Scan disable
4149 17:35:00.221204 == TX Byte 0 ==
4150 17:35:00.227748 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4151 17:35:00.230883 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4152 17:35:00.230979 == TX Byte 1 ==
4153 17:35:00.237669 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4154 17:35:00.241014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4155 17:35:00.241116
4156 17:35:00.241196 [DATLAT]
4157 17:35:00.244191 Freq=600, CH0 RK0
4158 17:35:00.244335
4159 17:35:00.244469 DATLAT Default: 0x9
4160 17:35:00.247371 0, 0xFFFF, sum = 0
4161 17:35:00.247506 1, 0xFFFF, sum = 0
4162 17:35:00.250971 2, 0xFFFF, sum = 0
4163 17:35:00.254102 3, 0xFFFF, sum = 0
4164 17:35:00.254237 4, 0xFFFF, sum = 0
4165 17:35:00.257359 5, 0xFFFF, sum = 0
4166 17:35:00.257512 6, 0xFFFF, sum = 0
4167 17:35:00.260565 7, 0xFFFF, sum = 0
4168 17:35:00.260718 8, 0x0, sum = 1
4169 17:35:00.263723 9, 0x0, sum = 2
4170 17:35:00.263903 10, 0x0, sum = 3
4171 17:35:00.264088 11, 0x0, sum = 4
4172 17:35:00.267298 best_step = 9
4173 17:35:00.267586
4174 17:35:00.267797 ==
4175 17:35:00.270878 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 17:35:00.273957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 17:35:00.274204 ==
4178 17:35:00.277723 RX Vref Scan: 1
4179 17:35:00.278026
4180 17:35:00.278341 RX Vref 0 -> 0, step: 1
4181 17:35:00.280535
4182 17:35:00.280839 RX Delay -195 -> 252, step: 8
4183 17:35:00.281149
4184 17:35:00.283809 Set Vref, RX VrefLevel [Byte0]: 60
4185 17:35:00.287436 [Byte1]: 47
4186 17:35:00.291499
4187 17:35:00.291933 Final RX Vref Byte 0 = 60 to rank0
4188 17:35:00.294897 Final RX Vref Byte 1 = 47 to rank0
4189 17:35:00.298839 Final RX Vref Byte 0 = 60 to rank1
4190 17:35:00.301607 Final RX Vref Byte 1 = 47 to rank1==
4191 17:35:00.304759 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 17:35:00.311489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 17:35:00.312083 ==
4194 17:35:00.312651 DQS Delay:
4195 17:35:00.313178 DQS0 = 0, DQS1 = 0
4196 17:35:00.314842 DQM Delay:
4197 17:35:00.315463 DQM0 = 34, DQM1 = 29
4198 17:35:00.318295 DQ Delay:
4199 17:35:00.321343 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4200 17:35:00.324948 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4201 17:35:00.328644 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4202 17:35:00.331460 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4203 17:35:00.331878
4204 17:35:00.332205
4205 17:35:00.337980 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4206 17:35:00.341778 CH0 RK0: MR19=808, MR18=3D3D
4207 17:35:00.348298 CH0_RK0: MR19=0x808, MR18=0x3D3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4208 17:35:00.348796
4209 17:35:00.351039 ----->DramcWriteLeveling(PI) begin...
4210 17:35:00.351121 ==
4211 17:35:00.354317 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 17:35:00.357983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 17:35:00.358064 ==
4214 17:35:00.361037 Write leveling (Byte 0): 32 => 32
4215 17:35:00.364747 Write leveling (Byte 1): 32 => 32
4216 17:35:00.367628 DramcWriteLeveling(PI) end<-----
4217 17:35:00.367709
4218 17:35:00.367773 ==
4219 17:35:00.371160 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 17:35:00.373828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 17:35:00.373915 ==
4222 17:35:00.377242 [Gating] SW mode calibration
4223 17:35:00.384206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4224 17:35:00.390509 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4225 17:35:00.393828 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 17:35:00.400604 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 17:35:00.403615 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 17:35:00.407333 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4229 17:35:00.413639 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4230 17:35:00.417209 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 17:35:00.420789 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 17:35:00.427027 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 17:35:00.430355 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 17:35:00.433902 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 17:35:00.440545 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 17:35:00.443531 0 10 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
4237 17:35:00.447137 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (1 1) (0 0)
4238 17:35:00.453770 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 17:35:00.457677 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 17:35:00.460594 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 17:35:00.466669 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 17:35:00.470279 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 17:35:00.474044 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 17:35:00.480166 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4245 17:35:00.483627 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4246 17:35:00.486795 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 17:35:00.493696 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 17:35:00.496490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 17:35:00.500024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 17:35:00.506484 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 17:35:00.510195 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 17:35:00.513466 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 17:35:00.516905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 17:35:00.523487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 17:35:00.526532 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 17:35:00.530145 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 17:35:00.536535 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 17:35:00.539914 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 17:35:00.543609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 17:35:00.549772 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4261 17:35:00.553450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 17:35:00.556304 Total UI for P1: 0, mck2ui 16
4263 17:35:00.559344 best dqsien dly found for B0: ( 0, 13, 12)
4264 17:35:00.563169 Total UI for P1: 0, mck2ui 16
4265 17:35:00.566029 best dqsien dly found for B1: ( 0, 13, 14)
4266 17:35:00.569636 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4267 17:35:00.572723 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4268 17:35:00.573151
4269 17:35:00.576297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4270 17:35:00.583157 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4271 17:35:00.583793 [Gating] SW calibration Done
4272 17:35:00.584299 ==
4273 17:35:00.585883 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 17:35:00.592650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 17:35:00.593221 ==
4276 17:35:00.593769 RX Vref Scan: 0
4277 17:35:00.594312
4278 17:35:00.596258 RX Vref 0 -> 0, step: 1
4279 17:35:00.596850
4280 17:35:00.599783 RX Delay -230 -> 252, step: 16
4281 17:35:00.602889 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4282 17:35:00.605997 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4283 17:35:00.612625 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4284 17:35:00.615823 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4285 17:35:00.619026 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4286 17:35:00.622296 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4287 17:35:00.625757 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4288 17:35:00.632139 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4289 17:35:00.635498 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4290 17:35:00.638884 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4291 17:35:00.642144 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4292 17:35:00.648732 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4293 17:35:00.652235 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4294 17:35:00.655426 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4295 17:35:00.658844 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4296 17:35:00.665785 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4297 17:35:00.666211 ==
4298 17:35:00.668671 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 17:35:00.672688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 17:35:00.673116 ==
4301 17:35:00.673455 DQS Delay:
4302 17:35:00.675294 DQS0 = 0, DQS1 = 0
4303 17:35:00.675756 DQM Delay:
4304 17:35:00.678513 DQM0 = 36, DQM1 = 28
4305 17:35:00.678930 DQ Delay:
4306 17:35:00.682259 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4307 17:35:00.685714 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4308 17:35:00.688742 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4309 17:35:00.691918 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4310 17:35:00.692339
4311 17:35:00.692669
4312 17:35:00.692978 ==
4313 17:35:00.695978 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 17:35:00.698208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 17:35:00.698752 ==
4316 17:35:00.699096
4317 17:35:00.702123
4318 17:35:00.702539 TX Vref Scan disable
4319 17:35:00.705002 == TX Byte 0 ==
4320 17:35:00.708717 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4321 17:35:00.712076 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4322 17:35:00.715321 == TX Byte 1 ==
4323 17:35:00.718448 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4324 17:35:00.721997 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4325 17:35:00.722421 ==
4326 17:35:00.725313 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 17:35:00.731975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 17:35:00.732447 ==
4329 17:35:00.732869
4330 17:35:00.733217
4331 17:35:00.733546 TX Vref Scan disable
4332 17:35:00.736166 == TX Byte 0 ==
4333 17:35:00.739497 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4334 17:35:00.743078 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4335 17:35:00.746329 == TX Byte 1 ==
4336 17:35:00.749733 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4337 17:35:00.753390 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4338 17:35:00.756505
4339 17:35:00.757029 [DATLAT]
4340 17:35:00.757431 Freq=600, CH0 RK1
4341 17:35:00.757842
4342 17:35:00.759525 DATLAT Default: 0x9
4343 17:35:00.760088 0, 0xFFFF, sum = 0
4344 17:35:00.762734 1, 0xFFFF, sum = 0
4345 17:35:00.763199 2, 0xFFFF, sum = 0
4346 17:35:00.766190 3, 0xFFFF, sum = 0
4347 17:35:00.766653 4, 0xFFFF, sum = 0
4348 17:35:00.769393 5, 0xFFFF, sum = 0
4349 17:35:00.772547 6, 0xFFFF, sum = 0
4350 17:35:00.773008 7, 0xFFFF, sum = 0
4351 17:35:00.773368 8, 0x0, sum = 1
4352 17:35:00.775947 9, 0x0, sum = 2
4353 17:35:00.776411 10, 0x0, sum = 3
4354 17:35:00.779304 11, 0x0, sum = 4
4355 17:35:00.779811 best_step = 9
4356 17:35:00.780173
4357 17:35:00.780507 ==
4358 17:35:00.782877 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 17:35:00.789601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 17:35:00.790058 ==
4361 17:35:00.790419 RX Vref Scan: 0
4362 17:35:00.790759
4363 17:35:00.792708 RX Vref 0 -> 0, step: 1
4364 17:35:00.793029
4365 17:35:00.795674 RX Delay -195 -> 252, step: 8
4366 17:35:00.799340 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4367 17:35:00.805397 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4368 17:35:00.809116 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4369 17:35:00.812003 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4370 17:35:00.815668 iDelay=205, Bit 4, Center 32 (-131 ~ 196) 328
4371 17:35:00.822079 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4372 17:35:00.825430 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4373 17:35:00.828587 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4374 17:35:00.832073 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4375 17:35:00.838468 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4376 17:35:00.841639 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4377 17:35:00.845206 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4378 17:35:00.848626 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4379 17:35:00.851799 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4380 17:35:00.858495 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4381 17:35:00.861558 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4382 17:35:00.862004 ==
4383 17:35:00.865106 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 17:35:00.868216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 17:35:00.868539 ==
4386 17:35:00.871819 DQS Delay:
4387 17:35:00.872139 DQS0 = 0, DQS1 = 0
4388 17:35:00.874985 DQM Delay:
4389 17:35:00.875469 DQM0 = 33, DQM1 = 28
4390 17:35:00.875863 DQ Delay:
4391 17:35:00.877883 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4392 17:35:00.881678 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4393 17:35:00.884531 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4394 17:35:00.888062 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4395 17:35:00.888541
4396 17:35:00.888956
4397 17:35:00.898148 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4398 17:35:00.901326 CH0 RK1: MR19=808, MR18=6B3A
4399 17:35:00.907729 CH0_RK1: MR19=0x808, MR18=0x6B3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4400 17:35:00.911679 [RxdqsGatingPostProcess] freq 600
4401 17:35:00.914346 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4402 17:35:00.918160 Pre-setting of DQS Precalculation
4403 17:35:00.924844 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4404 17:35:00.925245 ==
4405 17:35:00.927741 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 17:35:00.931362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 17:35:00.931718 ==
4408 17:35:00.937631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 17:35:00.940648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4410 17:35:00.944966 [CA 0] Center 36 (6~66) winsize 61
4411 17:35:00.948543 [CA 1] Center 35 (5~66) winsize 62
4412 17:35:00.951516 [CA 2] Center 34 (4~65) winsize 62
4413 17:35:00.954906 [CA 3] Center 34 (4~65) winsize 62
4414 17:35:00.958390 [CA 4] Center 34 (4~65) winsize 62
4415 17:35:00.961435 [CA 5] Center 33 (3~64) winsize 62
4416 17:35:00.961760
4417 17:35:00.965117 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4418 17:35:00.965525
4419 17:35:00.968190 [CATrainingPosCal] consider 1 rank data
4420 17:35:00.971522 u2DelayCellTimex100 = 270/100 ps
4421 17:35:00.974794 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4422 17:35:00.981823 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4423 17:35:00.984959 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 17:35:00.987850 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 17:35:00.991155 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 17:35:00.994546 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 17:35:00.994884
4428 17:35:00.997955 CA PerBit enable=1, Macro0, CA PI delay=33
4429 17:35:00.998308
4430 17:35:01.001241 [CBTSetCACLKResult] CA Dly = 33
4431 17:35:01.004280 CS Dly: 4 (0~35)
4432 17:35:01.004576 ==
4433 17:35:01.008368 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 17:35:01.010903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 17:35:01.011227 ==
4436 17:35:01.018162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4437 17:35:01.021313 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4438 17:35:01.024923 [CA 0] Center 36 (6~66) winsize 61
4439 17:35:01.028507 [CA 1] Center 36 (6~67) winsize 62
4440 17:35:01.031528 [CA 2] Center 34 (4~65) winsize 62
4441 17:35:01.035238 [CA 3] Center 34 (4~65) winsize 62
4442 17:35:01.038309 [CA 4] Center 34 (4~65) winsize 62
4443 17:35:01.042044 [CA 5] Center 33 (3~64) winsize 62
4444 17:35:01.042372
4445 17:35:01.044942 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4446 17:35:01.045271
4447 17:35:01.048488 [CATrainingPosCal] consider 2 rank data
4448 17:35:01.051677 u2DelayCellTimex100 = 270/100 ps
4449 17:35:01.054709 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4450 17:35:01.061403 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4451 17:35:01.065106 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4452 17:35:01.068371 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 17:35:01.071618 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 17:35:01.074619 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4455 17:35:01.075063
4456 17:35:01.078521 CA PerBit enable=1, Macro0, CA PI delay=33
4457 17:35:01.078850
4458 17:35:01.081240 [CBTSetCACLKResult] CA Dly = 33
4459 17:35:01.081606 CS Dly: 4 (0~36)
4460 17:35:01.085189
4461 17:35:01.088087 ----->DramcWriteLeveling(PI) begin...
4462 17:35:01.088500 ==
4463 17:35:01.091456 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 17:35:01.094670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 17:35:01.095115 ==
4466 17:35:01.098214 Write leveling (Byte 0): 27 => 27
4467 17:35:01.101245 Write leveling (Byte 1): 31 => 31
4468 17:35:01.104640 DramcWriteLeveling(PI) end<-----
4469 17:35:01.105009
4470 17:35:01.105269 ==
4471 17:35:01.107985 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 17:35:01.111048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 17:35:01.111373 ==
4474 17:35:01.114400 [Gating] SW mode calibration
4475 17:35:01.120961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 17:35:01.127766 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 17:35:01.130676 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 17:35:01.134293 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 17:35:01.141220 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 17:35:01.144091 0 9 12 | B1->B0 | 3030 3232 | 1 1 | (1 1) (1 1)
4481 17:35:01.147876 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
4482 17:35:01.154469 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 17:35:01.157812 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 17:35:01.160792 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 17:35:01.167582 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 17:35:01.171020 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 17:35:01.174135 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 17:35:01.180961 0 10 12 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
4489 17:35:01.184132 0 10 16 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
4490 17:35:01.187564 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 17:35:01.194000 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 17:35:01.197560 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 17:35:01.200993 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 17:35:01.204216 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 17:35:01.210548 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 17:35:01.214203 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4497 17:35:01.217723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4498 17:35:01.224142 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 17:35:01.227286 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 17:35:01.230691 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 17:35:01.237282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 17:35:01.240500 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 17:35:01.243661 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 17:35:01.250566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 17:35:01.254093 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 17:35:01.257566 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 17:35:01.263423 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 17:35:01.266779 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 17:35:01.270340 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 17:35:01.276877 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 17:35:01.280130 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 17:35:01.283784 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4513 17:35:01.290002 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 17:35:01.293244 Total UI for P1: 0, mck2ui 16
4515 17:35:01.297086 best dqsien dly found for B0: ( 0, 13, 12)
4516 17:35:01.297446 Total UI for P1: 0, mck2ui 16
4517 17:35:01.303153 best dqsien dly found for B1: ( 0, 13, 12)
4518 17:35:01.306387 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4519 17:35:01.310035 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4520 17:35:01.310369
4521 17:35:01.313267 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4522 17:35:01.316383 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4523 17:35:01.319598 [Gating] SW calibration Done
4524 17:35:01.319932 ==
4525 17:35:01.322806 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 17:35:01.326471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 17:35:01.326805 ==
4528 17:35:01.329670 RX Vref Scan: 0
4529 17:35:01.330003
4530 17:35:01.333103 RX Vref 0 -> 0, step: 1
4531 17:35:01.333435
4532 17:35:01.333774 RX Delay -230 -> 252, step: 16
4533 17:35:01.339319 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4534 17:35:01.343166 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4535 17:35:01.346084 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4536 17:35:01.349201 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4537 17:35:01.356153 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4538 17:35:01.359111 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4539 17:35:01.362725 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4540 17:35:01.365835 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4541 17:35:01.372603 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4542 17:35:01.375866 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4543 17:35:01.378966 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4544 17:35:01.382578 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4545 17:35:01.389048 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4546 17:35:01.392551 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4547 17:35:01.395734 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4548 17:35:01.399104 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4549 17:35:01.399473 ==
4550 17:35:01.402316 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 17:35:01.409368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 17:35:01.409703 ==
4553 17:35:01.410044 DQS Delay:
4554 17:35:01.410368 DQS0 = 0, DQS1 = 0
4555 17:35:01.412201 DQM Delay:
4556 17:35:01.412533 DQM0 = 38, DQM1 = 28
4557 17:35:01.415367 DQ Delay:
4558 17:35:01.419129 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4559 17:35:01.422473 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4560 17:35:01.425730 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4561 17:35:01.428828 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4562 17:35:01.429134
4563 17:35:01.429431
4564 17:35:01.429689 ==
4565 17:35:01.432574 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 17:35:01.435313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 17:35:01.435717 ==
4568 17:35:01.435978
4569 17:35:01.436240
4570 17:35:01.439074 TX Vref Scan disable
4571 17:35:01.439457 == TX Byte 0 ==
4572 17:35:01.445570 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4573 17:35:01.448697 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4574 17:35:01.451926 == TX Byte 1 ==
4575 17:35:01.455437 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4576 17:35:01.458386 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4577 17:35:01.458713 ==
4578 17:35:01.461910 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 17:35:01.465630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 17:35:01.466044 ==
4581 17:35:01.468430
4582 17:35:01.468751
4583 17:35:01.469004 TX Vref Scan disable
4584 17:35:01.471902 == TX Byte 0 ==
4585 17:35:01.475476 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4586 17:35:01.482502 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4587 17:35:01.482855 == TX Byte 1 ==
4588 17:35:01.485430 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4589 17:35:01.492195 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4590 17:35:01.492559
4591 17:35:01.492948 [DATLAT]
4592 17:35:01.493282 Freq=600, CH1 RK0
4593 17:35:01.493549
4594 17:35:01.494976 DATLAT Default: 0x9
4595 17:35:01.498413 0, 0xFFFF, sum = 0
4596 17:35:01.498743 1, 0xFFFF, sum = 0
4597 17:35:01.501686 2, 0xFFFF, sum = 0
4598 17:35:01.502019 3, 0xFFFF, sum = 0
4599 17:35:01.505540 4, 0xFFFF, sum = 0
4600 17:35:01.505967 5, 0xFFFF, sum = 0
4601 17:35:01.508720 6, 0xFFFF, sum = 0
4602 17:35:01.509090 7, 0xFFFF, sum = 0
4603 17:35:01.511728 8, 0x0, sum = 1
4604 17:35:01.512085 9, 0x0, sum = 2
4605 17:35:01.512420 10, 0x0, sum = 3
4606 17:35:01.515298 11, 0x0, sum = 4
4607 17:35:01.515792 best_step = 9
4608 17:35:01.516060
4609 17:35:01.518156 ==
4610 17:35:01.518545 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 17:35:01.524816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 17:35:01.525146 ==
4613 17:35:01.525455 RX Vref Scan: 1
4614 17:35:01.525820
4615 17:35:01.528413 RX Vref 0 -> 0, step: 1
4616 17:35:01.528775
4617 17:35:01.531476 RX Delay -195 -> 252, step: 8
4618 17:35:01.531952
4619 17:35:01.535016 Set Vref, RX VrefLevel [Byte0]: 56
4620 17:35:01.538271 [Byte1]: 52
4621 17:35:01.538352
4622 17:35:01.541518 Final RX Vref Byte 0 = 56 to rank0
4623 17:35:01.544773 Final RX Vref Byte 1 = 52 to rank0
4624 17:35:01.548056 Final RX Vref Byte 0 = 56 to rank1
4625 17:35:01.551631 Final RX Vref Byte 1 = 52 to rank1==
4626 17:35:01.554737 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 17:35:01.557950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 17:35:01.558057 ==
4629 17:35:01.561143 DQS Delay:
4630 17:35:01.561245 DQS0 = 0, DQS1 = 0
4631 17:35:01.564654 DQM Delay:
4632 17:35:01.564780 DQM0 = 40, DQM1 = 28
4633 17:35:01.564853 DQ Delay:
4634 17:35:01.568007 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4635 17:35:01.571154 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4636 17:35:01.574526 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4637 17:35:01.578412 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4638 17:35:01.578499
4639 17:35:01.578568
4640 17:35:01.588321 [DQSOSCAuto] RK0, (LSB)MR18= 0x212e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4641 17:35:01.591489 CH1 RK0: MR19=808, MR18=212E
4642 17:35:01.597857 CH1_RK0: MR19=0x808, MR18=0x212E, DQSOSC=401, MR23=63, INC=163, DEC=108
4643 17:35:01.597945
4644 17:35:01.601063 ----->DramcWriteLeveling(PI) begin...
4645 17:35:01.601151 ==
4646 17:35:01.604148 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 17:35:01.607771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 17:35:01.607873 ==
4649 17:35:01.610826 Write leveling (Byte 0): 31 => 31
4650 17:35:01.614312 Write leveling (Byte 1): 32 => 32
4651 17:35:01.617487 DramcWriteLeveling(PI) end<-----
4652 17:35:01.617608
4653 17:35:01.617704 ==
4654 17:35:01.620691 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 17:35:01.624417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 17:35:01.624557 ==
4657 17:35:01.627893 [Gating] SW mode calibration
4658 17:35:01.634468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4659 17:35:01.640631 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4660 17:35:01.644016 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 17:35:01.647642 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 17:35:01.653953 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 17:35:01.657268 0 9 12 | B1->B0 | 3333 2c2c | 0 0 | (1 1) (1 1)
4664 17:35:01.660997 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4665 17:35:01.667495 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 17:35:01.670257 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 17:35:01.673461 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 17:35:01.680246 0 10 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4669 17:35:01.684114 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 17:35:01.687001 0 10 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
4671 17:35:01.693383 0 10 12 | B1->B0 | 3030 3b3b | 0 1 | (0 0) (0 0)
4672 17:35:01.696772 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4673 17:35:01.700252 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 17:35:01.706566 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 17:35:01.710645 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 17:35:01.713270 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 17:35:01.719855 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 17:35:01.723638 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 17:35:01.726722 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 17:35:01.733432 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 17:35:01.736636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 17:35:01.740039 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 17:35:01.746395 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 17:35:01.749793 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 17:35:01.753647 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 17:35:01.760342 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 17:35:01.763166 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 17:35:01.766918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 17:35:01.773438 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 17:35:01.776808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 17:35:01.779797 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 17:35:01.786594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 17:35:01.789884 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 17:35:01.793519 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4695 17:35:01.799849 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 17:35:01.800272 Total UI for P1: 0, mck2ui 16
4697 17:35:01.806453 best dqsien dly found for B0: ( 0, 13, 8)
4698 17:35:01.806869 Total UI for P1: 0, mck2ui 16
4699 17:35:01.812912 best dqsien dly found for B1: ( 0, 13, 10)
4700 17:35:01.816218 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4701 17:35:01.819613 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4702 17:35:01.820040
4703 17:35:01.823208 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4704 17:35:01.826311 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4705 17:35:01.829378 [Gating] SW calibration Done
4706 17:35:01.829680 ==
4707 17:35:01.832575 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 17:35:01.835738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 17:35:01.836040 ==
4710 17:35:01.839044 RX Vref Scan: 0
4711 17:35:01.839353
4712 17:35:01.839711 RX Vref 0 -> 0, step: 1
4713 17:35:01.840008
4714 17:35:01.842599 RX Delay -230 -> 252, step: 16
4715 17:35:01.849303 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4716 17:35:01.852370 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4717 17:35:01.855983 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4718 17:35:01.859203 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4719 17:35:01.862117 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4720 17:35:01.869256 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4721 17:35:01.872132 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4722 17:35:01.875280 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4723 17:35:01.878864 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4724 17:35:01.885534 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4725 17:35:01.889038 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4726 17:35:01.892141 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4727 17:35:01.895734 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4728 17:35:01.902602 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4729 17:35:01.905639 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4730 17:35:01.908586 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4731 17:35:01.908891 ==
4732 17:35:01.911822 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 17:35:01.915781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 17:35:01.916084 ==
4735 17:35:01.918929 DQS Delay:
4736 17:35:01.919229 DQS0 = 0, DQS1 = 0
4737 17:35:01.922247 DQM Delay:
4738 17:35:01.922547 DQM0 = 36, DQM1 = 29
4739 17:35:01.922852 DQ Delay:
4740 17:35:01.925243 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4741 17:35:01.928575 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4742 17:35:01.931816 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4743 17:35:01.935278 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4744 17:35:01.935603
4745 17:35:01.935839
4746 17:35:01.938396 ==
4747 17:35:01.941699 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 17:35:01.945043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 17:35:01.945339 ==
4750 17:35:01.945575
4751 17:35:01.945792
4752 17:35:01.948561 TX Vref Scan disable
4753 17:35:01.948981 == TX Byte 0 ==
4754 17:35:01.954751 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4755 17:35:01.958397 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4756 17:35:01.958692 == TX Byte 1 ==
4757 17:35:01.964895 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4758 17:35:01.967929 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4759 17:35:01.968234 ==
4760 17:35:01.971417 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 17:35:01.974975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 17:35:01.975270 ==
4763 17:35:01.975539
4764 17:35:01.975760
4765 17:35:01.978016 TX Vref Scan disable
4766 17:35:01.981190 == TX Byte 0 ==
4767 17:35:01.984800 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4768 17:35:01.987744 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4769 17:35:01.991532 == TX Byte 1 ==
4770 17:35:01.994412 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4771 17:35:01.997824 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4772 17:35:01.998125
4773 17:35:02.001418 [DATLAT]
4774 17:35:02.001717 Freq=600, CH1 RK1
4775 17:35:02.001955
4776 17:35:02.004596 DATLAT Default: 0x9
4777 17:35:02.004944 0, 0xFFFF, sum = 0
4778 17:35:02.008111 1, 0xFFFF, sum = 0
4779 17:35:02.008414 2, 0xFFFF, sum = 0
4780 17:35:02.011219 3, 0xFFFF, sum = 0
4781 17:35:02.011558 4, 0xFFFF, sum = 0
4782 17:35:02.014909 5, 0xFFFF, sum = 0
4783 17:35:02.015212 6, 0xFFFF, sum = 0
4784 17:35:02.017947 7, 0xFFFF, sum = 0
4785 17:35:02.018251 8, 0x0, sum = 1
4786 17:35:02.021312 9, 0x0, sum = 2
4787 17:35:02.021619 10, 0x0, sum = 3
4788 17:35:02.024662 11, 0x0, sum = 4
4789 17:35:02.025033 best_step = 9
4790 17:35:02.025333
4791 17:35:02.025685 ==
4792 17:35:02.027787 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 17:35:02.034273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 17:35:02.034702 ==
4795 17:35:02.034954 RX Vref Scan: 0
4796 17:35:02.035182
4797 17:35:02.037811 RX Vref 0 -> 0, step: 1
4798 17:35:02.038110
4799 17:35:02.041163 RX Delay -195 -> 252, step: 8
4800 17:35:02.044445 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4801 17:35:02.050827 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4802 17:35:02.054288 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4803 17:35:02.057469 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4804 17:35:02.060687 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4805 17:35:02.064207 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4806 17:35:02.070900 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4807 17:35:02.073860 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4808 17:35:02.077573 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4809 17:35:02.080611 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4810 17:35:02.087169 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4811 17:35:02.090473 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4812 17:35:02.093854 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4813 17:35:02.097501 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4814 17:35:02.104034 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4815 17:35:02.106983 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4816 17:35:02.107422 ==
4817 17:35:02.110866 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 17:35:02.113819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 17:35:02.114245 ==
4820 17:35:02.116947 DQS Delay:
4821 17:35:02.117349 DQS0 = 0, DQS1 = 0
4822 17:35:02.117714 DQM Delay:
4823 17:35:02.121072 DQM0 = 36, DQM1 = 30
4824 17:35:02.121462 DQ Delay:
4825 17:35:02.124149 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4826 17:35:02.127212 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4827 17:35:02.130909 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4828 17:35:02.133735 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4829 17:35:02.134037
4830 17:35:02.134274
4831 17:35:02.143783 [DQSOSCAuto] RK1, (LSB)MR18= 0x3253, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4832 17:35:02.147236 CH1 RK1: MR19=808, MR18=3253
4833 17:35:02.150105 CH1_RK1: MR19=0x808, MR18=0x3253, DQSOSC=394, MR23=63, INC=168, DEC=112
4834 17:35:02.153508 [RxdqsGatingPostProcess] freq 600
4835 17:35:02.160435 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4836 17:35:02.163211 Pre-setting of DQS Precalculation
4837 17:35:02.166778 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4838 17:35:02.173745 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4839 17:35:02.183094 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4840 17:35:02.183176
4841 17:35:02.183255
4842 17:35:02.186944 [Calibration Summary] 1200 Mbps
4843 17:35:02.187018 CH 0, Rank 0
4844 17:35:02.190036 SW Impedance : PASS
4845 17:35:02.190134 DUTY Scan : NO K
4846 17:35:02.192889 ZQ Calibration : PASS
4847 17:35:02.196172 Jitter Meter : NO K
4848 17:35:02.196246 CBT Training : PASS
4849 17:35:02.199669 Write leveling : PASS
4850 17:35:02.203517 RX DQS gating : PASS
4851 17:35:02.203590 RX DQ/DQS(RDDQC) : PASS
4852 17:35:02.206332 TX DQ/DQS : PASS
4853 17:35:02.209523 RX DATLAT : PASS
4854 17:35:02.209598 RX DQ/DQS(Engine): PASS
4855 17:35:02.212978 TX OE : NO K
4856 17:35:02.213049 All Pass.
4857 17:35:02.213110
4858 17:35:02.216243 CH 0, Rank 1
4859 17:35:02.216314 SW Impedance : PASS
4860 17:35:02.219436 DUTY Scan : NO K
4861 17:35:02.219513 ZQ Calibration : PASS
4862 17:35:02.222697 Jitter Meter : NO K
4863 17:35:02.226217 CBT Training : PASS
4864 17:35:02.226291 Write leveling : PASS
4865 17:35:02.229494 RX DQS gating : PASS
4866 17:35:02.232737 RX DQ/DQS(RDDQC) : PASS
4867 17:35:02.232813 TX DQ/DQS : PASS
4868 17:35:02.236250 RX DATLAT : PASS
4869 17:35:02.239349 RX DQ/DQS(Engine): PASS
4870 17:35:02.239487 TX OE : NO K
4871 17:35:02.242840 All Pass.
4872 17:35:02.242921
4873 17:35:02.242991 CH 1, Rank 0
4874 17:35:02.245984 SW Impedance : PASS
4875 17:35:02.246068 DUTY Scan : NO K
4876 17:35:02.249050 ZQ Calibration : PASS
4877 17:35:02.252537 Jitter Meter : NO K
4878 17:35:02.252617 CBT Training : PASS
4879 17:35:02.255814 Write leveling : PASS
4880 17:35:02.259133 RX DQS gating : PASS
4881 17:35:02.259217 RX DQ/DQS(RDDQC) : PASS
4882 17:35:02.262498 TX DQ/DQS : PASS
4883 17:35:02.266169 RX DATLAT : PASS
4884 17:35:02.266276 RX DQ/DQS(Engine): PASS
4885 17:35:02.269015 TX OE : NO K
4886 17:35:02.269090 All Pass.
4887 17:35:02.269152
4888 17:35:02.272523 CH 1, Rank 1
4889 17:35:02.272623 SW Impedance : PASS
4890 17:35:02.275461 DUTY Scan : NO K
4891 17:35:02.279168 ZQ Calibration : PASS
4892 17:35:02.279281 Jitter Meter : NO K
4893 17:35:02.282037 CBT Training : PASS
4894 17:35:02.282119 Write leveling : PASS
4895 17:35:02.285949 RX DQS gating : PASS
4896 17:35:02.288652 RX DQ/DQS(RDDQC) : PASS
4897 17:35:02.288754 TX DQ/DQS : PASS
4898 17:35:02.292403 RX DATLAT : PASS
4899 17:35:02.295618 RX DQ/DQS(Engine): PASS
4900 17:35:02.295713 TX OE : NO K
4901 17:35:02.298861 All Pass.
4902 17:35:02.298951
4903 17:35:02.299045 DramC Write-DBI off
4904 17:35:02.302522 PER_BANK_REFRESH: Hybrid Mode
4905 17:35:02.305493 TX_TRACKING: ON
4906 17:35:02.312236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4907 17:35:02.315238 [FAST_K] Save calibration result to emmc
4908 17:35:02.318980 dramc_set_vcore_voltage set vcore to 662500
4909 17:35:02.321798 Read voltage for 933, 3
4910 17:35:02.321879 Vio18 = 0
4911 17:35:02.325454 Vcore = 662500
4912 17:35:02.325569 Vdram = 0
4913 17:35:02.325662 Vddq = 0
4914 17:35:02.329238 Vmddr = 0
4915 17:35:02.331917 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4916 17:35:02.338666 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4917 17:35:02.338748 MEM_TYPE=3, freq_sel=17
4918 17:35:02.342556 sv_algorithm_assistance_LP4_1600
4919 17:35:02.348636 ============ PULL DRAM RESETB DOWN ============
4920 17:35:02.352057 ========== PULL DRAM RESETB DOWN end =========
4921 17:35:02.355507 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4922 17:35:02.358542 ===================================
4923 17:35:02.363015 LPDDR4 DRAM CONFIGURATION
4924 17:35:02.365263 ===================================
4925 17:35:02.368971 EX_ROW_EN[0] = 0x0
4926 17:35:02.369080 EX_ROW_EN[1] = 0x0
4927 17:35:02.371748 LP4Y_EN = 0x0
4928 17:35:02.371860 WORK_FSP = 0x0
4929 17:35:02.374775 WL = 0x3
4930 17:35:02.374885 RL = 0x3
4931 17:35:02.378478 BL = 0x2
4932 17:35:02.378589 RPST = 0x0
4933 17:35:02.381353 RD_PRE = 0x0
4934 17:35:02.381433 WR_PRE = 0x1
4935 17:35:02.385117 WR_PST = 0x0
4936 17:35:02.385229 DBI_WR = 0x0
4937 17:35:02.388161 DBI_RD = 0x0
4938 17:35:02.388241 OTF = 0x1
4939 17:35:02.391972 ===================================
4940 17:35:02.394916 ===================================
4941 17:35:02.398084 ANA top config
4942 17:35:02.401897 ===================================
4943 17:35:02.404601 DLL_ASYNC_EN = 0
4944 17:35:02.404700 ALL_SLAVE_EN = 1
4945 17:35:02.408068 NEW_RANK_MODE = 1
4946 17:35:02.411238 DLL_IDLE_MODE = 1
4947 17:35:02.414478 LP45_APHY_COMB_EN = 1
4948 17:35:02.414558 TX_ODT_DIS = 1
4949 17:35:02.417865 NEW_8X_MODE = 1
4950 17:35:02.421599 ===================================
4951 17:35:02.424533 ===================================
4952 17:35:02.427785 data_rate = 1866
4953 17:35:02.431271 CKR = 1
4954 17:35:02.434249 DQ_P2S_RATIO = 8
4955 17:35:02.437729 ===================================
4956 17:35:02.441051 CA_P2S_RATIO = 8
4957 17:35:02.441132 DQ_CA_OPEN = 0
4958 17:35:02.444587 DQ_SEMI_OPEN = 0
4959 17:35:02.447514 CA_SEMI_OPEN = 0
4960 17:35:02.451033 CA_FULL_RATE = 0
4961 17:35:02.454131 DQ_CKDIV4_EN = 1
4962 17:35:02.457409 CA_CKDIV4_EN = 1
4963 17:35:02.461091 CA_PREDIV_EN = 0
4964 17:35:02.461172 PH8_DLY = 0
4965 17:35:02.464520 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4966 17:35:02.467303 DQ_AAMCK_DIV = 4
4967 17:35:02.470505 CA_AAMCK_DIV = 4
4968 17:35:02.474121 CA_ADMCK_DIV = 4
4969 17:35:02.477697 DQ_TRACK_CA_EN = 0
4970 17:35:02.477778 CA_PICK = 933
4971 17:35:02.481138 CA_MCKIO = 933
4972 17:35:02.484056 MCKIO_SEMI = 0
4973 17:35:02.487319 PLL_FREQ = 3732
4974 17:35:02.490599 DQ_UI_PI_RATIO = 32
4975 17:35:02.494025 CA_UI_PI_RATIO = 0
4976 17:35:02.497658 ===================================
4977 17:35:02.500414 ===================================
4978 17:35:02.500507 memory_type:LPDDR4
4979 17:35:02.504114 GP_NUM : 10
4980 17:35:02.507302 SRAM_EN : 1
4981 17:35:02.507449 MD32_EN : 0
4982 17:35:02.510409 ===================================
4983 17:35:02.513944 [ANA_INIT] >>>>>>>>>>>>>>
4984 17:35:02.517200 <<<<<< [CONFIGURE PHASE]: ANA_TX
4985 17:35:02.520637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4986 17:35:02.523656 ===================================
4987 17:35:02.527328 data_rate = 1866,PCW = 0X8f00
4988 17:35:02.530288 ===================================
4989 17:35:02.533879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4990 17:35:02.537234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 17:35:02.543764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 17:35:02.547261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4993 17:35:02.550557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4994 17:35:02.554048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4995 17:35:02.557692 [ANA_INIT] flow start
4996 17:35:02.560801 [ANA_INIT] PLL >>>>>>>>
4997 17:35:02.561220 [ANA_INIT] PLL <<<<<<<<
4998 17:35:02.563856 [ANA_INIT] MIDPI >>>>>>>>
4999 17:35:02.567348 [ANA_INIT] MIDPI <<<<<<<<
5000 17:35:02.570997 [ANA_INIT] DLL >>>>>>>>
5001 17:35:02.571455 [ANA_INIT] flow end
5002 17:35:02.574021 ============ LP4 DIFF to SE enter ============
5003 17:35:02.580308 ============ LP4 DIFF to SE exit ============
5004 17:35:02.580727 [ANA_INIT] <<<<<<<<<<<<<
5005 17:35:02.583763 [Flow] Enable top DCM control >>>>>
5006 17:35:02.586885 [Flow] Enable top DCM control <<<<<
5007 17:35:02.590468 Enable DLL master slave shuffle
5008 17:35:02.597064 ==============================================================
5009 17:35:02.597485 Gating Mode config
5010 17:35:02.603668 ==============================================================
5011 17:35:02.607180 Config description:
5012 17:35:02.617527 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5013 17:35:02.623353 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5014 17:35:02.627031 SELPH_MODE 0: By rank 1: By Phase
5015 17:35:02.633593 ==============================================================
5016 17:35:02.637200 GAT_TRACK_EN = 1
5017 17:35:02.640182 RX_GATING_MODE = 2
5018 17:35:02.640597 RX_GATING_TRACK_MODE = 2
5019 17:35:02.643464 SELPH_MODE = 1
5020 17:35:02.646914 PICG_EARLY_EN = 1
5021 17:35:02.649782 VALID_LAT_VALUE = 1
5022 17:35:02.656570 ==============================================================
5023 17:35:02.660020 Enter into Gating configuration >>>>
5024 17:35:02.663238 Exit from Gating configuration <<<<
5025 17:35:02.666709 Enter into DVFS_PRE_config >>>>>
5026 17:35:02.676649 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5027 17:35:02.680450 Exit from DVFS_PRE_config <<<<<
5028 17:35:02.683418 Enter into PICG configuration >>>>
5029 17:35:02.686603 Exit from PICG configuration <<<<
5030 17:35:02.689775 [RX_INPUT] configuration >>>>>
5031 17:35:02.693192 [RX_INPUT] configuration <<<<<
5032 17:35:02.696524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5033 17:35:02.703610 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5034 17:35:02.709590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5035 17:35:02.716592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5036 17:35:02.719686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5037 17:35:02.726394 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5038 17:35:02.729878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5039 17:35:02.736241 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5040 17:35:02.739884 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5041 17:35:02.742954 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5042 17:35:02.746604 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5043 17:35:02.752879 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 17:35:02.756065 ===================================
5045 17:35:02.756478 LPDDR4 DRAM CONFIGURATION
5046 17:35:02.759662 ===================================
5047 17:35:02.762933 EX_ROW_EN[0] = 0x0
5048 17:35:02.765882 EX_ROW_EN[1] = 0x0
5049 17:35:02.766425 LP4Y_EN = 0x0
5050 17:35:02.769662 WORK_FSP = 0x0
5051 17:35:02.770076 WL = 0x3
5052 17:35:02.772771 RL = 0x3
5053 17:35:02.773183 BL = 0x2
5054 17:35:02.776258 RPST = 0x0
5055 17:35:02.776687 RD_PRE = 0x0
5056 17:35:02.779633 WR_PRE = 0x1
5057 17:35:02.780047 WR_PST = 0x0
5058 17:35:02.782919 DBI_WR = 0x0
5059 17:35:02.783329 DBI_RD = 0x0
5060 17:35:02.786052 OTF = 0x1
5061 17:35:02.789159 ===================================
5062 17:35:02.792428 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5063 17:35:02.795678 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5064 17:35:02.802599 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 17:35:02.805694 ===================================
5066 17:35:02.806114 LPDDR4 DRAM CONFIGURATION
5067 17:35:02.809205 ===================================
5068 17:35:02.812641 EX_ROW_EN[0] = 0x10
5069 17:35:02.815678 EX_ROW_EN[1] = 0x0
5070 17:35:02.816093 LP4Y_EN = 0x0
5071 17:35:02.818866 WORK_FSP = 0x0
5072 17:35:02.819376 WL = 0x3
5073 17:35:02.822134 RL = 0x3
5074 17:35:02.822684 BL = 0x2
5075 17:35:02.825805 RPST = 0x0
5076 17:35:02.826232 RD_PRE = 0x0
5077 17:35:02.829004 WR_PRE = 0x1
5078 17:35:02.829512 WR_PST = 0x0
5079 17:35:02.832593 DBI_WR = 0x0
5080 17:35:02.833006 DBI_RD = 0x0
5081 17:35:02.835549 OTF = 0x1
5082 17:35:02.839288 ===================================
5083 17:35:02.845675 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5084 17:35:02.848826 nWR fixed to 30
5085 17:35:02.852058 [ModeRegInit_LP4] CH0 RK0
5086 17:35:02.852478 [ModeRegInit_LP4] CH0 RK1
5087 17:35:02.855641 [ModeRegInit_LP4] CH1 RK0
5088 17:35:02.859349 [ModeRegInit_LP4] CH1 RK1
5089 17:35:02.859812 match AC timing 9
5090 17:35:02.865176 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5091 17:35:02.868627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5092 17:35:02.871855 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5093 17:35:02.878624 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5094 17:35:02.881987 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5095 17:35:02.882408 ==
5096 17:35:02.885769 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 17:35:02.888760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 17:35:02.889183 ==
5099 17:35:02.895286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 17:35:02.901694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5101 17:35:02.905553 [CA 0] Center 38 (8~69) winsize 62
5102 17:35:02.908580 [CA 1] Center 38 (8~69) winsize 62
5103 17:35:02.911926 [CA 2] Center 35 (5~66) winsize 62
5104 17:35:02.915443 [CA 3] Center 35 (5~65) winsize 61
5105 17:35:02.918339 [CA 4] Center 34 (4~64) winsize 61
5106 17:35:02.922051 [CA 5] Center 33 (3~64) winsize 62
5107 17:35:02.922491
5108 17:35:02.925021 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5109 17:35:02.925443
5110 17:35:02.928344 [CATrainingPosCal] consider 1 rank data
5111 17:35:02.931931 u2DelayCellTimex100 = 270/100 ps
5112 17:35:02.934970 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5113 17:35:02.938278 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5114 17:35:02.941255 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5115 17:35:02.944802 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5116 17:35:02.948107 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5117 17:35:02.951246 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5118 17:35:02.954765
5119 17:35:02.957920 CA PerBit enable=1, Macro0, CA PI delay=33
5120 17:35:02.958004
5121 17:35:02.961134 [CBTSetCACLKResult] CA Dly = 33
5122 17:35:02.961217 CS Dly: 7 (0~38)
5123 17:35:02.961283 ==
5124 17:35:02.964826 Dram Type= 6, Freq= 0, CH_0, rank 1
5125 17:35:02.967642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 17:35:02.967727 ==
5127 17:35:02.974387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5128 17:35:02.980906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5129 17:35:02.984113 [CA 0] Center 38 (8~69) winsize 62
5130 17:35:02.987588 [CA 1] Center 38 (8~69) winsize 62
5131 17:35:02.991191 [CA 2] Center 35 (5~66) winsize 62
5132 17:35:02.994214 [CA 3] Center 35 (5~65) winsize 61
5133 17:35:02.997587 [CA 4] Center 34 (4~65) winsize 62
5134 17:35:03.000933 [CA 5] Center 33 (3~64) winsize 62
5135 17:35:03.001017
5136 17:35:03.003989 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5137 17:35:03.004073
5138 17:35:03.007627 [CATrainingPosCal] consider 2 rank data
5139 17:35:03.011079 u2DelayCellTimex100 = 270/100 ps
5140 17:35:03.014620 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5141 17:35:03.018018 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5142 17:35:03.021221 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5143 17:35:03.027468 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5144 17:35:03.031329 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5145 17:35:03.034112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5146 17:35:03.034572
5147 17:35:03.037403 CA PerBit enable=1, Macro0, CA PI delay=33
5148 17:35:03.037863
5149 17:35:03.041078 [CBTSetCACLKResult] CA Dly = 33
5150 17:35:03.041618 CS Dly: 7 (0~39)
5151 17:35:03.042039
5152 17:35:03.044473 ----->DramcWriteLeveling(PI) begin...
5153 17:35:03.044936 ==
5154 17:35:03.047844 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 17:35:03.054094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 17:35:03.054558 ==
5157 17:35:03.057931 Write leveling (Byte 0): 30 => 30
5158 17:35:03.061176 Write leveling (Byte 1): 30 => 30
5159 17:35:03.061631 DramcWriteLeveling(PI) end<-----
5160 17:35:03.064458
5161 17:35:03.064872 ==
5162 17:35:03.067437 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 17:35:03.071047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 17:35:03.071494 ==
5165 17:35:03.073873 [Gating] SW mode calibration
5166 17:35:03.080560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5167 17:35:03.084144 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5168 17:35:03.091006 0 14 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5169 17:35:03.094678 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5170 17:35:03.097623 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 17:35:03.103946 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 17:35:03.107267 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 17:35:03.110772 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 17:35:03.117451 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 17:35:03.120773 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 17:35:03.123631 0 15 0 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5177 17:35:03.130619 0 15 4 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
5178 17:35:03.133561 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 17:35:03.137010 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 17:35:03.143793 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 17:35:03.146933 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 17:35:03.150337 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 17:35:03.157091 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5184 17:35:03.160159 1 0 0 | B1->B0 | 2f2f 4343 | 0 0 | (1 1) (0 0)
5185 17:35:03.163540 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 17:35:03.170250 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 17:35:03.173356 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 17:35:03.176788 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 17:35:03.183285 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 17:35:03.187042 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 17:35:03.189967 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5192 17:35:03.196309 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5193 17:35:03.199477 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5194 17:35:03.203211 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 17:35:03.209793 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 17:35:03.213201 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 17:35:03.216322 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 17:35:03.223005 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 17:35:03.226048 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 17:35:03.229676 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 17:35:03.235900 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 17:35:03.239485 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 17:35:03.242918 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 17:35:03.249830 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 17:35:03.252776 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 17:35:03.255908 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 17:35:03.262931 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 17:35:03.266475 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5209 17:35:03.269446 Total UI for P1: 0, mck2ui 16
5210 17:35:03.272375 best dqsien dly found for B0: ( 1, 2, 30)
5211 17:35:03.275702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5212 17:35:03.279343 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 17:35:03.282011 Total UI for P1: 0, mck2ui 16
5214 17:35:03.285350 best dqsien dly found for B1: ( 1, 3, 4)
5215 17:35:03.292019 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5216 17:35:03.295114 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5217 17:35:03.295247
5218 17:35:03.298889 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5219 17:35:03.301910 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5220 17:35:03.305880 [Gating] SW calibration Done
5221 17:35:03.305984 ==
5222 17:35:03.308656 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 17:35:03.312181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 17:35:03.312264 ==
5225 17:35:03.315207 RX Vref Scan: 0
5226 17:35:03.315315
5227 17:35:03.315446 RX Vref 0 -> 0, step: 1
5228 17:35:03.315510
5229 17:35:03.318162 RX Delay -80 -> 252, step: 8
5230 17:35:03.321793 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5231 17:35:03.328214 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5232 17:35:03.332049 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5233 17:35:03.334791 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5234 17:35:03.338220 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5235 17:35:03.341737 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5236 17:35:03.344502 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5237 17:35:03.351317 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5238 17:35:03.354715 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5239 17:35:03.358347 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5240 17:35:03.361514 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5241 17:35:03.364821 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5242 17:35:03.371702 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5243 17:35:03.374892 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5244 17:35:03.377791 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5245 17:35:03.381474 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5246 17:35:03.381555 ==
5247 17:35:03.384367 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 17:35:03.391045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 17:35:03.391131 ==
5250 17:35:03.391196 DQS Delay:
5251 17:35:03.391255 DQS0 = 0, DQS1 = 0
5252 17:35:03.394239 DQM Delay:
5253 17:35:03.394319 DQM0 = 93, DQM1 = 82
5254 17:35:03.397937 DQ Delay:
5255 17:35:03.401116 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5256 17:35:03.404530 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5257 17:35:03.407579 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5258 17:35:03.410724 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5259 17:35:03.410804
5260 17:35:03.410868
5261 17:35:03.410927 ==
5262 17:35:03.414263 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 17:35:03.417192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 17:35:03.417274 ==
5265 17:35:03.417339
5266 17:35:03.417398
5267 17:35:03.420869 TX Vref Scan disable
5268 17:35:03.420950 == TX Byte 0 ==
5269 17:35:03.427657 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5270 17:35:03.430473 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5271 17:35:03.430554 == TX Byte 1 ==
5272 17:35:03.437324 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5273 17:35:03.440646 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5274 17:35:03.440727 ==
5275 17:35:03.444395 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 17:35:03.447566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 17:35:03.447649 ==
5278 17:35:03.447743
5279 17:35:03.447830
5280 17:35:03.450742 TX Vref Scan disable
5281 17:35:03.454121 == TX Byte 0 ==
5282 17:35:03.457777 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5283 17:35:03.460430 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5284 17:35:03.464071 == TX Byte 1 ==
5285 17:35:03.467299 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5286 17:35:03.470360 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5287 17:35:03.470438
5288 17:35:03.473459 [DATLAT]
5289 17:35:03.473525 Freq=933, CH0 RK0
5290 17:35:03.473585
5291 17:35:03.476892 DATLAT Default: 0xd
5292 17:35:03.476961 0, 0xFFFF, sum = 0
5293 17:35:03.480226 1, 0xFFFF, sum = 0
5294 17:35:03.480308 2, 0xFFFF, sum = 0
5295 17:35:03.483863 3, 0xFFFF, sum = 0
5296 17:35:03.483950 4, 0xFFFF, sum = 0
5297 17:35:03.486721 5, 0xFFFF, sum = 0
5298 17:35:03.490185 6, 0xFFFF, sum = 0
5299 17:35:03.490295 7, 0xFFFF, sum = 0
5300 17:35:03.493607 8, 0xFFFF, sum = 0
5301 17:35:03.493742 9, 0xFFFF, sum = 0
5302 17:35:03.497331 10, 0x0, sum = 1
5303 17:35:03.497439 11, 0x0, sum = 2
5304 17:35:03.497526 12, 0x0, sum = 3
5305 17:35:03.500322 13, 0x0, sum = 4
5306 17:35:03.500432 best_step = 11
5307 17:35:03.500518
5308 17:35:03.503706 ==
5309 17:35:03.506771 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 17:35:03.510147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 17:35:03.510328 ==
5312 17:35:03.510481 RX Vref Scan: 1
5313 17:35:03.510590
5314 17:35:03.513792 RX Vref 0 -> 0, step: 1
5315 17:35:03.513976
5316 17:35:03.516687 RX Delay -77 -> 252, step: 4
5317 17:35:03.516923
5318 17:35:03.520546 Set Vref, RX VrefLevel [Byte0]: 60
5319 17:35:03.523343 [Byte1]: 47
5320 17:35:03.523619
5321 17:35:03.526583 Final RX Vref Byte 0 = 60 to rank0
5322 17:35:03.530117 Final RX Vref Byte 1 = 47 to rank0
5323 17:35:03.533446 Final RX Vref Byte 0 = 60 to rank1
5324 17:35:03.537141 Final RX Vref Byte 1 = 47 to rank1==
5325 17:35:03.539794 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 17:35:03.543542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 17:35:03.546486 ==
5328 17:35:03.546863 DQS Delay:
5329 17:35:03.547243 DQS0 = 0, DQS1 = 0
5330 17:35:03.550017 DQM Delay:
5331 17:35:03.550398 DQM0 = 95, DQM1 = 82
5332 17:35:03.553606 DQ Delay:
5333 17:35:03.556691 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5334 17:35:03.559756 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5335 17:35:03.563056 DQ8 =72, DQ9 =70, DQ10 =84, DQ11 =76
5336 17:35:03.566412 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =92
5337 17:35:03.566905
5338 17:35:03.567361
5339 17:35:03.573222 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5340 17:35:03.576315 CH0 RK0: MR19=505, MR18=F0F
5341 17:35:03.582996 CH0_RK0: MR19=0x505, MR18=0xF0F, DQSOSC=417, MR23=63, INC=62, DEC=41
5342 17:35:03.583353
5343 17:35:03.586143 ----->DramcWriteLeveling(PI) begin...
5344 17:35:03.586633 ==
5345 17:35:03.589343 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 17:35:03.592773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 17:35:03.593125 ==
5348 17:35:03.596083 Write leveling (Byte 0): 32 => 32
5349 17:35:03.599461 Write leveling (Byte 1): 31 => 31
5350 17:35:03.602817 DramcWriteLeveling(PI) end<-----
5351 17:35:03.603308
5352 17:35:03.603787 ==
5353 17:35:03.605833 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 17:35:03.609140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 17:35:03.609525 ==
5356 17:35:03.612646 [Gating] SW mode calibration
5357 17:35:03.618979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 17:35:03.626097 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5359 17:35:03.629218 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5360 17:35:03.635513 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5361 17:35:03.638937 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 17:35:03.642217 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 17:35:03.645827 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 17:35:03.652455 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 17:35:03.655439 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 17:35:03.659037 0 14 28 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (1 0)
5367 17:35:03.665684 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5368 17:35:03.668615 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 17:35:03.672168 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 17:35:03.679043 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 17:35:03.681878 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 17:35:03.685788 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 17:35:03.691830 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 17:35:03.695583 0 15 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5375 17:35:03.698654 1 0 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5376 17:35:03.705435 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 17:35:03.708324 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 17:35:03.711616 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 17:35:03.718180 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 17:35:03.722029 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 17:35:03.724997 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 17:35:03.732236 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5383 17:35:03.735157 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5384 17:35:03.738389 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 17:35:03.744859 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 17:35:03.748241 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 17:35:03.751665 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 17:35:03.758692 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 17:35:03.761487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 17:35:03.764759 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 17:35:03.771477 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 17:35:03.775304 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 17:35:03.778287 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 17:35:03.784734 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 17:35:03.788286 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 17:35:03.791418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 17:35:03.798386 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 17:35:03.802133 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5399 17:35:03.805085 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 17:35:03.807995 Total UI for P1: 0, mck2ui 16
5401 17:35:03.811429 best dqsien dly found for B0: ( 1, 2, 28)
5402 17:35:03.814731 Total UI for P1: 0, mck2ui 16
5403 17:35:03.818061 best dqsien dly found for B1: ( 1, 2, 30)
5404 17:35:03.821540 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5405 17:35:03.825035 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5406 17:35:03.825343
5407 17:35:03.831326 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5408 17:35:03.834281 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5409 17:35:03.834661 [Gating] SW calibration Done
5410 17:35:03.837819 ==
5411 17:35:03.838110 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 17:35:03.844416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 17:35:03.844705 ==
5414 17:35:03.844935 RX Vref Scan: 0
5415 17:35:03.845150
5416 17:35:03.847734 RX Vref 0 -> 0, step: 1
5417 17:35:03.848079
5418 17:35:03.851204 RX Delay -80 -> 252, step: 8
5419 17:35:03.854487 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5420 17:35:03.858123 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5421 17:35:03.861021 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5422 17:35:03.864580 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5423 17:35:03.871363 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5424 17:35:03.874646 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5425 17:35:03.877723 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5426 17:35:03.881419 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5427 17:35:03.884658 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5428 17:35:03.890794 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5429 17:35:03.894207 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5430 17:35:03.897448 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5431 17:35:03.900701 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5432 17:35:03.904296 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5433 17:35:03.910924 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5434 17:35:03.914460 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5435 17:35:03.914764 ==
5436 17:35:03.917485 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 17:35:03.920910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 17:35:03.920988 ==
5439 17:35:03.923654 DQS Delay:
5440 17:35:03.923750 DQS0 = 0, DQS1 = 0
5441 17:35:03.923837 DQM Delay:
5442 17:35:03.927156 DQM0 = 92, DQM1 = 81
5443 17:35:03.927256 DQ Delay:
5444 17:35:03.930543 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5445 17:35:03.933492 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5446 17:35:03.937090 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5447 17:35:03.940169 DQ12 =91, DQ13 =87, DQ14 =95, DQ15 =87
5448 17:35:03.940257
5449 17:35:03.940349
5450 17:35:03.940434 ==
5451 17:35:03.943908 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 17:35:03.950687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 17:35:03.950770 ==
5454 17:35:03.950836
5455 17:35:03.950897
5456 17:35:03.950961 TX Vref Scan disable
5457 17:35:03.953953 == TX Byte 0 ==
5458 17:35:03.957080 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5459 17:35:03.963701 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5460 17:35:03.963850 == TX Byte 1 ==
5461 17:35:03.967218 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5462 17:35:03.973532 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5463 17:35:03.973708 ==
5464 17:35:03.976930 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 17:35:03.980503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 17:35:03.980637 ==
5467 17:35:03.980749
5468 17:35:03.980854
5469 17:35:03.983407 TX Vref Scan disable
5470 17:35:03.983553 == TX Byte 0 ==
5471 17:35:03.990510 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5472 17:35:03.993500 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5473 17:35:03.993788 == TX Byte 1 ==
5474 17:35:04.000401 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5475 17:35:04.003849 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5476 17:35:04.004336
5477 17:35:04.004682 [DATLAT]
5478 17:35:04.006789 Freq=933, CH0 RK1
5479 17:35:04.007300
5480 17:35:04.007718 DATLAT Default: 0xb
5481 17:35:04.010220 0, 0xFFFF, sum = 0
5482 17:35:04.010741 1, 0xFFFF, sum = 0
5483 17:35:04.013885 2, 0xFFFF, sum = 0
5484 17:35:04.014408 3, 0xFFFF, sum = 0
5485 17:35:04.016765 4, 0xFFFF, sum = 0
5486 17:35:04.020357 5, 0xFFFF, sum = 0
5487 17:35:04.020821 6, 0xFFFF, sum = 0
5488 17:35:04.023668 7, 0xFFFF, sum = 0
5489 17:35:04.024085 8, 0xFFFF, sum = 0
5490 17:35:04.027016 9, 0xFFFF, sum = 0
5491 17:35:04.027474 10, 0x0, sum = 1
5492 17:35:04.030565 11, 0x0, sum = 2
5493 17:35:04.030982 12, 0x0, sum = 3
5494 17:35:04.031359 13, 0x0, sum = 4
5495 17:35:04.033989 best_step = 11
5496 17:35:04.034431
5497 17:35:04.034990 ==
5498 17:35:04.037179 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 17:35:04.040823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 17:35:04.041238 ==
5501 17:35:04.043553 RX Vref Scan: 0
5502 17:35:04.043962
5503 17:35:04.047266 RX Vref 0 -> 0, step: 1
5504 17:35:04.047725
5505 17:35:04.048052 RX Delay -77 -> 252, step: 4
5506 17:35:04.054581 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5507 17:35:04.058294 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5508 17:35:04.061185 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5509 17:35:04.064169 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5510 17:35:04.067921 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5511 17:35:04.074202 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5512 17:35:04.077492 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5513 17:35:04.081153 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5514 17:35:04.083816 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5515 17:35:04.087647 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5516 17:35:04.094444 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5517 17:35:04.097148 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5518 17:35:04.100513 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5519 17:35:04.103764 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5520 17:35:04.107218 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5521 17:35:04.114096 iDelay=199, Bit 15, Center 90 (3 ~ 178) 176
5522 17:35:04.114656 ==
5523 17:35:04.117057 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 17:35:04.120475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 17:35:04.121084 ==
5526 17:35:04.121599 DQS Delay:
5527 17:35:04.123661 DQS0 = 0, DQS1 = 0
5528 17:35:04.124084 DQM Delay:
5529 17:35:04.127092 DQM0 = 92, DQM1 = 84
5530 17:35:04.127695 DQ Delay:
5531 17:35:04.130135 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5532 17:35:04.133537 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =102
5533 17:35:04.137078 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =78
5534 17:35:04.140380 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5535 17:35:04.140935
5536 17:35:04.141438
5537 17:35:04.146553 [DQSOSCAuto] RK1, (LSB)MR18= 0x290a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5538 17:35:04.150423 CH0 RK1: MR19=505, MR18=290A
5539 17:35:04.157021 CH0_RK1: MR19=0x505, MR18=0x290A, DQSOSC=408, MR23=63, INC=65, DEC=43
5540 17:35:04.160610 [RxdqsGatingPostProcess] freq 933
5541 17:35:04.166623 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5542 17:35:04.170626 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 17:35:04.173623 best DQS1 dly(2T, 0.5T) = (0, 11)
5544 17:35:04.176361 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 17:35:04.180030 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5546 17:35:04.180442 best DQS0 dly(2T, 0.5T) = (0, 10)
5547 17:35:04.183352 best DQS1 dly(2T, 0.5T) = (0, 10)
5548 17:35:04.186417 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5549 17:35:04.189829 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5550 17:35:04.193144 Pre-setting of DQS Precalculation
5551 17:35:04.199603 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5552 17:35:04.200037 ==
5553 17:35:04.203046 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 17:35:04.206231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 17:35:04.206852 ==
5556 17:35:04.212924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 17:35:04.220012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5558 17:35:04.222704 [CA 0] Center 37 (7~68) winsize 62
5559 17:35:04.226674 [CA 1] Center 37 (7~68) winsize 62
5560 17:35:04.229562 [CA 2] Center 34 (5~64) winsize 60
5561 17:35:04.232709 [CA 3] Center 34 (5~64) winsize 60
5562 17:35:04.236335 [CA 4] Center 34 (5~64) winsize 60
5563 17:35:04.236774 [CA 5] Center 34 (4~64) winsize 61
5564 17:35:04.239499
5565 17:35:04.242621 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5566 17:35:04.243154
5567 17:35:04.246350 [CATrainingPosCal] consider 1 rank data
5568 17:35:04.249171 u2DelayCellTimex100 = 270/100 ps
5569 17:35:04.252873 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5570 17:35:04.255948 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5571 17:35:04.259544 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5572 17:35:04.262570 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5573 17:35:04.265757 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5574 17:35:04.269358 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5575 17:35:04.269877
5576 17:35:04.273158 CA PerBit enable=1, Macro0, CA PI delay=34
5577 17:35:04.276080
5578 17:35:04.276518 [CBTSetCACLKResult] CA Dly = 34
5579 17:35:04.279817 CS Dly: 5 (0~36)
5580 17:35:04.280255 ==
5581 17:35:04.282666 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 17:35:04.286131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 17:35:04.286655 ==
5584 17:35:04.292527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 17:35:04.298913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5586 17:35:04.302575 [CA 0] Center 37 (8~67) winsize 60
5587 17:35:04.305617 [CA 1] Center 38 (7~69) winsize 63
5588 17:35:04.308880 [CA 2] Center 35 (6~65) winsize 60
5589 17:35:04.312326 [CA 3] Center 34 (4~64) winsize 61
5590 17:35:04.315741 [CA 4] Center 35 (5~65) winsize 61
5591 17:35:04.318686 [CA 5] Center 34 (4~64) winsize 61
5592 17:35:04.319162
5593 17:35:04.322161 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5594 17:35:04.322779
5595 17:35:04.325869 [CATrainingPosCal] consider 2 rank data
5596 17:35:04.328931 u2DelayCellTimex100 = 270/100 ps
5597 17:35:04.332506 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5598 17:35:04.335456 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5599 17:35:04.338500 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5600 17:35:04.341848 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5601 17:35:04.345528 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5602 17:35:04.348943 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5603 17:35:04.349468
5604 17:35:04.355473 CA PerBit enable=1, Macro0, CA PI delay=34
5605 17:35:04.356062
5606 17:35:04.358977 [CBTSetCACLKResult] CA Dly = 34
5607 17:35:04.359441 CS Dly: 6 (0~39)
5608 17:35:04.359851
5609 17:35:04.361620 ----->DramcWriteLeveling(PI) begin...
5610 17:35:04.362185 ==
5611 17:35:04.365491 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 17:35:04.368406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 17:35:04.371523 ==
5614 17:35:04.371934 Write leveling (Byte 0): 23 => 23
5615 17:35:04.375016 Write leveling (Byte 1): 29 => 29
5616 17:35:04.378932 DramcWriteLeveling(PI) end<-----
5617 17:35:04.379433
5618 17:35:04.379778 ==
5619 17:35:04.381645 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 17:35:04.388321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 17:35:04.388765 ==
5622 17:35:04.391367 [Gating] SW mode calibration
5623 17:35:04.398522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5624 17:35:04.401796 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5625 17:35:04.408151 0 14 0 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
5626 17:35:04.411611 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 17:35:04.414787 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 17:35:04.422023 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 17:35:04.424780 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 17:35:04.428427 0 14 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5631 17:35:04.434544 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5632 17:35:04.438355 0 14 28 | B1->B0 | 2e2e 2e2e | 0 0 | (1 0) (0 1)
5633 17:35:04.441332 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5634 17:35:04.447923 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 17:35:04.450936 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 17:35:04.454530 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 17:35:04.457521 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 17:35:04.464035 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 17:35:04.467614 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 17:35:04.474039 0 15 28 | B1->B0 | 3232 3131 | 0 0 | (0 0) (1 1)
5641 17:35:04.477692 1 0 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
5642 17:35:04.480952 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 17:35:04.484108 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 17:35:04.490500 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 17:35:04.494246 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 17:35:04.497578 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 17:35:04.503702 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 17:35:04.506939 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5649 17:35:04.510430 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5650 17:35:04.517307 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 17:35:04.520345 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 17:35:04.523370 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 17:35:04.530547 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 17:35:04.533338 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 17:35:04.536634 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 17:35:04.543639 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 17:35:04.546998 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 17:35:04.550434 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 17:35:04.556664 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 17:35:04.560312 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 17:35:04.563620 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 17:35:04.570191 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 17:35:04.573538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 17:35:04.576805 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5665 17:35:04.583159 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5666 17:35:04.586692 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 17:35:04.589692 Total UI for P1: 0, mck2ui 16
5668 17:35:04.593340 best dqsien dly found for B0: ( 1, 2, 30)
5669 17:35:04.596344 Total UI for P1: 0, mck2ui 16
5670 17:35:04.599771 best dqsien dly found for B1: ( 1, 2, 30)
5671 17:35:04.602902 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5672 17:35:04.606431 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5673 17:35:04.606723
5674 17:35:04.609454 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5675 17:35:04.613308 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5676 17:35:04.616557 [Gating] SW calibration Done
5677 17:35:04.616849 ==
5678 17:35:04.619765 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 17:35:04.626141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 17:35:04.626436 ==
5681 17:35:04.626668 RX Vref Scan: 0
5682 17:35:04.626885
5683 17:35:04.629523 RX Vref 0 -> 0, step: 1
5684 17:35:04.629816
5685 17:35:04.633193 RX Delay -80 -> 252, step: 8
5686 17:35:04.636329 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5687 17:35:04.639297 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5688 17:35:04.642764 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5689 17:35:04.645991 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5690 17:35:04.652828 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5691 17:35:04.656104 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5692 17:35:04.659308 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5693 17:35:04.662592 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5694 17:35:04.665742 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5695 17:35:04.672828 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5696 17:35:04.675631 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5697 17:35:04.678817 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5698 17:35:04.682334 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5699 17:35:04.685587 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5700 17:35:04.692232 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5701 17:35:04.695223 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5702 17:35:04.695666 ==
5703 17:35:04.699002 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 17:35:04.702037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 17:35:04.702443 ==
5706 17:35:04.702811 DQS Delay:
5707 17:35:04.705266 DQS0 = 0, DQS1 = 0
5708 17:35:04.705584 DQM Delay:
5709 17:35:04.708819 DQM0 = 95, DQM1 = 87
5710 17:35:04.709246 DQ Delay:
5711 17:35:04.711833 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5712 17:35:04.715674 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5713 17:35:04.718460 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5714 17:35:04.721852 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5715 17:35:04.722180
5716 17:35:04.722526
5717 17:35:04.722884 ==
5718 17:35:04.725242 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 17:35:04.731910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 17:35:04.732295 ==
5721 17:35:04.732606
5722 17:35:04.732958
5723 17:35:04.733283 TX Vref Scan disable
5724 17:35:04.735467 == TX Byte 0 ==
5725 17:35:04.738672 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5726 17:35:04.745064 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5727 17:35:04.745460 == TX Byte 1 ==
5728 17:35:04.748699 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5729 17:35:04.755236 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5730 17:35:04.755675 ==
5731 17:35:04.758405 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 17:35:04.761822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 17:35:04.762252 ==
5734 17:35:04.762604
5735 17:35:04.762986
5736 17:35:04.764819 TX Vref Scan disable
5737 17:35:04.765175 == TX Byte 0 ==
5738 17:35:04.771447 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5739 17:35:04.774807 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5740 17:35:04.778252 == TX Byte 1 ==
5741 17:35:04.781359 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5742 17:35:04.784972 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5743 17:35:04.785279
5744 17:35:04.785556 [DATLAT]
5745 17:35:04.788395 Freq=933, CH1 RK0
5746 17:35:04.788807
5747 17:35:04.789161 DATLAT Default: 0xd
5748 17:35:04.791735 0, 0xFFFF, sum = 0
5749 17:35:04.794891 1, 0xFFFF, sum = 0
5750 17:35:04.795283 2, 0xFFFF, sum = 0
5751 17:35:04.798076 3, 0xFFFF, sum = 0
5752 17:35:04.798515 4, 0xFFFF, sum = 0
5753 17:35:04.801192 5, 0xFFFF, sum = 0
5754 17:35:04.801617 6, 0xFFFF, sum = 0
5755 17:35:04.805053 7, 0xFFFF, sum = 0
5756 17:35:04.805382 8, 0xFFFF, sum = 0
5757 17:35:04.808212 9, 0xFFFF, sum = 0
5758 17:35:04.808542 10, 0x0, sum = 1
5759 17:35:04.811105 11, 0x0, sum = 2
5760 17:35:04.811535 12, 0x0, sum = 3
5761 17:35:04.814977 13, 0x0, sum = 4
5762 17:35:04.815381 best_step = 11
5763 17:35:04.815757
5764 17:35:04.816053 ==
5765 17:35:04.817954 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 17:35:04.820867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 17:35:04.820973 ==
5768 17:35:04.824239 RX Vref Scan: 1
5769 17:35:04.824319
5770 17:35:04.827604 RX Vref 0 -> 0, step: 1
5771 17:35:04.827689
5772 17:35:04.827782 RX Delay -61 -> 252, step: 4
5773 17:35:04.827870
5774 17:35:04.830968 Set Vref, RX VrefLevel [Byte0]: 56
5775 17:35:04.833994 [Byte1]: 52
5776 17:35:04.839484
5777 17:35:04.839591 Final RX Vref Byte 0 = 56 to rank0
5778 17:35:04.842254 Final RX Vref Byte 1 = 52 to rank0
5779 17:35:04.845476 Final RX Vref Byte 0 = 56 to rank1
5780 17:35:04.848923 Final RX Vref Byte 1 = 52 to rank1==
5781 17:35:04.852710 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 17:35:04.859501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 17:35:04.859584 ==
5784 17:35:04.859649 DQS Delay:
5785 17:35:04.862109 DQS0 = 0, DQS1 = 0
5786 17:35:04.862191 DQM Delay:
5787 17:35:04.862255 DQM0 = 96, DQM1 = 89
5788 17:35:04.865572 DQ Delay:
5789 17:35:04.868590 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =94
5790 17:35:04.872219 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5791 17:35:04.875192 DQ8 =78, DQ9 =82, DQ10 =86, DQ11 =84
5792 17:35:04.878890 DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =94
5793 17:35:04.878972
5794 17:35:04.879037
5795 17:35:04.885145 [DQSOSCAuto] RK0, (LSB)MR18= 0x10a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5796 17:35:04.888762 CH1 RK0: MR19=505, MR18=10A
5797 17:35:04.895185 CH1_RK0: MR19=0x505, MR18=0x10A, DQSOSC=418, MR23=63, INC=62, DEC=41
5798 17:35:04.895268
5799 17:35:04.898474 ----->DramcWriteLeveling(PI) begin...
5800 17:35:04.898557 ==
5801 17:35:04.901492 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 17:35:04.905188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 17:35:04.905296 ==
5804 17:35:04.908422 Write leveling (Byte 0): 29 => 29
5805 17:35:04.911349 Write leveling (Byte 1): 27 => 27
5806 17:35:04.914883 DramcWriteLeveling(PI) end<-----
5807 17:35:04.914982
5808 17:35:04.915079 ==
5809 17:35:04.918372 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 17:35:04.921606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 17:35:04.924533 ==
5812 17:35:04.924645 [Gating] SW mode calibration
5813 17:35:04.934600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5814 17:35:04.937764 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5815 17:35:04.941318 0 14 0 | B1->B0 | 3434 3535 | 0 1 | (0 0) (0 0)
5816 17:35:04.948146 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 17:35:04.951663 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 17:35:04.954740 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 17:35:04.961394 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 17:35:04.964622 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5821 17:35:04.967694 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5822 17:35:04.974258 0 14 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
5823 17:35:04.977793 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 17:35:04.980654 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 17:35:04.987821 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 17:35:04.990828 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 17:35:04.994537 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 17:35:05.001380 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 17:35:05.004336 0 15 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5830 17:35:05.007218 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5831 17:35:05.014362 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5832 17:35:05.017383 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 17:35:05.020589 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 17:35:05.027333 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 17:35:05.030817 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 17:35:05.033704 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 17:35:05.040605 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5838 17:35:05.043820 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5839 17:35:05.047322 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 17:35:05.053773 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 17:35:05.057049 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 17:35:05.060599 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 17:35:05.067333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 17:35:05.069984 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 17:35:05.073604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 17:35:05.080376 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 17:35:05.083552 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 17:35:05.086498 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 17:35:05.093776 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 17:35:05.096475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 17:35:05.100218 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 17:35:05.107133 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 17:35:05.109966 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5854 17:35:05.113332 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5855 17:35:05.117056 Total UI for P1: 0, mck2ui 16
5856 17:35:05.119909 best dqsien dly found for B0: ( 1, 2, 24)
5857 17:35:05.126653 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 17:35:05.127211 Total UI for P1: 0, mck2ui 16
5859 17:35:05.130079 best dqsien dly found for B1: ( 1, 2, 28)
5860 17:35:05.136606 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5861 17:35:05.139597 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5862 17:35:05.139679
5863 17:35:05.142499 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5864 17:35:05.145825 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5865 17:35:05.149133 [Gating] SW calibration Done
5866 17:35:05.149259 ==
5867 17:35:05.153262 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 17:35:05.156242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 17:35:05.156879 ==
5870 17:35:05.159950 RX Vref Scan: 0
5871 17:35:05.160370
5872 17:35:05.160711 RX Vref 0 -> 0, step: 1
5873 17:35:05.161022
5874 17:35:05.162888 RX Delay -80 -> 252, step: 8
5875 17:35:05.166028 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5876 17:35:05.172635 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5877 17:35:05.175996 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5878 17:35:05.179466 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5879 17:35:05.182479 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5880 17:35:05.186151 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5881 17:35:05.192443 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5882 17:35:05.195883 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5883 17:35:05.199451 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5884 17:35:05.202527 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5885 17:35:05.206052 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5886 17:35:05.209115 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5887 17:35:05.215729 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5888 17:35:05.219323 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5889 17:35:05.222611 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5890 17:35:05.226145 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5891 17:35:05.226565 ==
5892 17:35:05.229103 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 17:35:05.236015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 17:35:05.236438 ==
5895 17:35:05.236772 DQS Delay:
5896 17:35:05.239038 DQS0 = 0, DQS1 = 0
5897 17:35:05.239513 DQM Delay:
5898 17:35:05.239859 DQM0 = 93, DQM1 = 88
5899 17:35:05.242226 DQ Delay:
5900 17:35:05.245521 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5901 17:35:05.248648 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5902 17:35:05.252038 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5903 17:35:05.255244 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =99
5904 17:35:05.255759
5905 17:35:05.256093
5906 17:35:05.256492 ==
5907 17:35:05.258354 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 17:35:05.261470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 17:35:05.261895 ==
5910 17:35:05.262231
5911 17:35:05.262541
5912 17:35:05.265309 TX Vref Scan disable
5913 17:35:05.268553 == TX Byte 0 ==
5914 17:35:05.271910 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5915 17:35:05.275457 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5916 17:35:05.278311 == TX Byte 1 ==
5917 17:35:05.281823 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5918 17:35:05.284781 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5919 17:35:05.285194 ==
5920 17:35:05.288386 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 17:35:05.291453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 17:35:05.294933 ==
5923 17:35:05.295341
5924 17:35:05.295717
5925 17:35:05.296136 TX Vref Scan disable
5926 17:35:05.298555 == TX Byte 0 ==
5927 17:35:05.301800 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5928 17:35:05.308657 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5929 17:35:05.309170 == TX Byte 1 ==
5930 17:35:05.311826 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5931 17:35:05.318606 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5932 17:35:05.319017
5933 17:35:05.319336 [DATLAT]
5934 17:35:05.319725 Freq=933, CH1 RK1
5935 17:35:05.320027
5936 17:35:05.321820 DATLAT Default: 0xb
5937 17:35:05.322231 0, 0xFFFF, sum = 0
5938 17:35:05.324801 1, 0xFFFF, sum = 0
5939 17:35:05.325215 2, 0xFFFF, sum = 0
5940 17:35:05.328364 3, 0xFFFF, sum = 0
5941 17:35:05.331921 4, 0xFFFF, sum = 0
5942 17:35:05.332337 5, 0xFFFF, sum = 0
5943 17:35:05.335080 6, 0xFFFF, sum = 0
5944 17:35:05.335539 7, 0xFFFF, sum = 0
5945 17:35:05.338580 8, 0xFFFF, sum = 0
5946 17:35:05.338998 9, 0xFFFF, sum = 0
5947 17:35:05.341567 10, 0x0, sum = 1
5948 17:35:05.341984 11, 0x0, sum = 2
5949 17:35:05.345384 12, 0x0, sum = 3
5950 17:35:05.345892 13, 0x0, sum = 4
5951 17:35:05.346296 best_step = 11
5952 17:35:05.346701
5953 17:35:05.348231 ==
5954 17:35:05.351970 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 17:35:05.354801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 17:35:05.355245 ==
5957 17:35:05.355630 RX Vref Scan: 0
5958 17:35:05.355941
5959 17:35:05.358110 RX Vref 0 -> 0, step: 1
5960 17:35:05.358517
5961 17:35:05.361741 RX Delay -69 -> 252, step: 4
5962 17:35:05.365107 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5963 17:35:05.371447 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5964 17:35:05.374541 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5965 17:35:05.378182 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5966 17:35:05.381475 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5967 17:35:05.384808 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5968 17:35:05.391438 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5969 17:35:05.394877 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5970 17:35:05.397543 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5971 17:35:05.401017 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5972 17:35:05.404537 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5973 17:35:05.411254 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5974 17:35:05.414218 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5975 17:35:05.417986 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5976 17:35:05.421113 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5977 17:35:05.424213 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5978 17:35:05.424639 ==
5979 17:35:05.427778 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 17:35:05.434432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 17:35:05.434860 ==
5982 17:35:05.435294 DQS Delay:
5983 17:35:05.437509 DQS0 = 0, DQS1 = 0
5984 17:35:05.437961 DQM Delay:
5985 17:35:05.440373 DQM0 = 92, DQM1 = 90
5986 17:35:05.440455 DQ Delay:
5987 17:35:05.443848 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5988 17:35:05.446970 DQ4 =90, DQ5 =102, DQ6 =106, DQ7 =88
5989 17:35:05.450815 DQ8 =78, DQ9 =80, DQ10 =90, DQ11 =82
5990 17:35:05.453784 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =98
5991 17:35:05.453866
5992 17:35:05.453949
5993 17:35:05.460105 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5994 17:35:05.463647 CH1 RK1: MR19=505, MR18=B1F
5995 17:35:05.470668 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5996 17:35:05.473407 [RxdqsGatingPostProcess] freq 933
5997 17:35:05.480664 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5998 17:35:05.480776 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 17:35:05.483616 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 17:35:05.486915 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 17:35:05.490327 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 17:35:05.493542 best DQS0 dly(2T, 0.5T) = (0, 10)
6003 17:35:05.496976 best DQS1 dly(2T, 0.5T) = (0, 10)
6004 17:35:05.500392 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6005 17:35:05.503297 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6006 17:35:05.506779 Pre-setting of DQS Precalculation
6007 17:35:05.510382 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6008 17:35:05.519980 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6009 17:35:05.526712 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6010 17:35:05.527014
6011 17:35:05.527254
6012 17:35:05.529802 [Calibration Summary] 1866 Mbps
6013 17:35:05.529884 CH 0, Rank 0
6014 17:35:05.532841 SW Impedance : PASS
6015 17:35:05.536299 DUTY Scan : NO K
6016 17:35:05.536397 ZQ Calibration : PASS
6017 17:35:05.539698 Jitter Meter : NO K
6018 17:35:05.539781 CBT Training : PASS
6019 17:35:05.542938 Write leveling : PASS
6020 17:35:05.546432 RX DQS gating : PASS
6021 17:35:05.546556 RX DQ/DQS(RDDQC) : PASS
6022 17:35:05.549648 TX DQ/DQS : PASS
6023 17:35:05.553107 RX DATLAT : PASS
6024 17:35:05.553208 RX DQ/DQS(Engine): PASS
6025 17:35:05.556318 TX OE : NO K
6026 17:35:05.556430 All Pass.
6027 17:35:05.556519
6028 17:35:05.559897 CH 0, Rank 1
6029 17:35:05.560008 SW Impedance : PASS
6030 17:35:05.563377 DUTY Scan : NO K
6031 17:35:05.566421 ZQ Calibration : PASS
6032 17:35:05.566837 Jitter Meter : NO K
6033 17:35:05.569915 CBT Training : PASS
6034 17:35:05.573087 Write leveling : PASS
6035 17:35:05.573507 RX DQS gating : PASS
6036 17:35:05.576462 RX DQ/DQS(RDDQC) : PASS
6037 17:35:05.579515 TX DQ/DQS : PASS
6038 17:35:05.580097 RX DATLAT : PASS
6039 17:35:05.582983 RX DQ/DQS(Engine): PASS
6040 17:35:05.586389 TX OE : NO K
6041 17:35:05.586900 All Pass.
6042 17:35:05.587236
6043 17:35:05.587631 CH 1, Rank 0
6044 17:35:05.589876 SW Impedance : PASS
6045 17:35:05.592875 DUTY Scan : NO K
6046 17:35:05.593296 ZQ Calibration : PASS
6047 17:35:05.595943 Jitter Meter : NO K
6048 17:35:05.599445 CBT Training : PASS
6049 17:35:05.599874 Write leveling : PASS
6050 17:35:05.602834 RX DQS gating : PASS
6051 17:35:05.603259 RX DQ/DQS(RDDQC) : PASS
6052 17:35:05.606483 TX DQ/DQS : PASS
6053 17:35:05.609369 RX DATLAT : PASS
6054 17:35:05.609793 RX DQ/DQS(Engine): PASS
6055 17:35:05.612962 TX OE : NO K
6056 17:35:05.613443 All Pass.
6057 17:35:05.613871
6058 17:35:05.615801 CH 1, Rank 1
6059 17:35:05.616229 SW Impedance : PASS
6060 17:35:05.619204 DUTY Scan : NO K
6061 17:35:05.622596 ZQ Calibration : PASS
6062 17:35:05.623016 Jitter Meter : NO K
6063 17:35:05.626235 CBT Training : PASS
6064 17:35:05.629252 Write leveling : PASS
6065 17:35:05.629793 RX DQS gating : PASS
6066 17:35:05.632543 RX DQ/DQS(RDDQC) : PASS
6067 17:35:05.636053 TX DQ/DQS : PASS
6068 17:35:05.636478 RX DATLAT : PASS
6069 17:35:05.638972 RX DQ/DQS(Engine): PASS
6070 17:35:05.642641 TX OE : NO K
6071 17:35:05.643247 All Pass.
6072 17:35:05.643818
6073 17:35:05.644337 DramC Write-DBI off
6074 17:35:05.645820 PER_BANK_REFRESH: Hybrid Mode
6075 17:35:05.649058 TX_TRACKING: ON
6076 17:35:05.655631 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6077 17:35:05.662251 [FAST_K] Save calibration result to emmc
6078 17:35:05.665963 dramc_set_vcore_voltage set vcore to 650000
6079 17:35:05.666561 Read voltage for 400, 6
6080 17:35:05.668850 Vio18 = 0
6081 17:35:05.669353 Vcore = 650000
6082 17:35:05.669781 Vdram = 0
6083 17:35:05.672440 Vddq = 0
6084 17:35:05.672864 Vmddr = 0
6085 17:35:05.676152 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6086 17:35:05.682426 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6087 17:35:05.685513 MEM_TYPE=3, freq_sel=20
6088 17:35:05.688651 sv_algorithm_assistance_LP4_800
6089 17:35:05.692286 ============ PULL DRAM RESETB DOWN ============
6090 17:35:05.695749 ========== PULL DRAM RESETB DOWN end =========
6091 17:35:05.698829 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6092 17:35:05.702181 ===================================
6093 17:35:05.705513 LPDDR4 DRAM CONFIGURATION
6094 17:35:05.708806 ===================================
6095 17:35:05.712314 EX_ROW_EN[0] = 0x0
6096 17:35:05.712614 EX_ROW_EN[1] = 0x0
6097 17:35:05.715168 LP4Y_EN = 0x0
6098 17:35:05.715510 WORK_FSP = 0x0
6099 17:35:05.718423 WL = 0x2
6100 17:35:05.718811 RL = 0x2
6101 17:35:05.721944 BL = 0x2
6102 17:35:05.722335 RPST = 0x0
6103 17:35:05.725328 RD_PRE = 0x0
6104 17:35:05.728316 WR_PRE = 0x1
6105 17:35:05.728715 WR_PST = 0x0
6106 17:35:05.731608 DBI_WR = 0x0
6107 17:35:05.731909 DBI_RD = 0x0
6108 17:35:05.734915 OTF = 0x1
6109 17:35:05.738234 ===================================
6110 17:35:05.741882 ===================================
6111 17:35:05.742187 ANA top config
6112 17:35:05.744763 ===================================
6113 17:35:05.748292 DLL_ASYNC_EN = 0
6114 17:35:05.751814 ALL_SLAVE_EN = 1
6115 17:35:05.752117 NEW_RANK_MODE = 1
6116 17:35:05.754848 DLL_IDLE_MODE = 1
6117 17:35:05.758305 LP45_APHY_COMB_EN = 1
6118 17:35:05.761886 TX_ODT_DIS = 1
6119 17:35:05.762189 NEW_8X_MODE = 1
6120 17:35:05.765024 ===================================
6121 17:35:05.768542 ===================================
6122 17:35:05.771832 data_rate = 800
6123 17:35:05.774612 CKR = 1
6124 17:35:05.778106 DQ_P2S_RATIO = 4
6125 17:35:05.781825 ===================================
6126 17:35:05.784564 CA_P2S_RATIO = 4
6127 17:35:05.788150 DQ_CA_OPEN = 0
6128 17:35:05.788448 DQ_SEMI_OPEN = 1
6129 17:35:05.791838 CA_SEMI_OPEN = 1
6130 17:35:05.794882 CA_FULL_RATE = 0
6131 17:35:05.797924 DQ_CKDIV4_EN = 0
6132 17:35:05.801437 CA_CKDIV4_EN = 1
6133 17:35:05.804516 CA_PREDIV_EN = 0
6134 17:35:05.804815 PH8_DLY = 0
6135 17:35:05.808561 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6136 17:35:05.811307 DQ_AAMCK_DIV = 0
6137 17:35:05.814471 CA_AAMCK_DIV = 0
6138 17:35:05.818063 CA_ADMCK_DIV = 4
6139 17:35:05.821469 DQ_TRACK_CA_EN = 0
6140 17:35:05.824606 CA_PICK = 800
6141 17:35:05.824909 CA_MCKIO = 400
6142 17:35:05.828187 MCKIO_SEMI = 400
6143 17:35:05.831098 PLL_FREQ = 3016
6144 17:35:05.834873 DQ_UI_PI_RATIO = 32
6145 17:35:05.837834 CA_UI_PI_RATIO = 32
6146 17:35:05.841443 ===================================
6147 17:35:05.844896 ===================================
6148 17:35:05.847708 memory_type:LPDDR4
6149 17:35:05.848025 GP_NUM : 10
6150 17:35:05.851277 SRAM_EN : 1
6151 17:35:05.851635 MD32_EN : 0
6152 17:35:05.854606 ===================================
6153 17:35:05.857868 [ANA_INIT] >>>>>>>>>>>>>>
6154 17:35:05.861256 <<<<<< [CONFIGURE PHASE]: ANA_TX
6155 17:35:05.864673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6156 17:35:05.867763 ===================================
6157 17:35:05.870857 data_rate = 800,PCW = 0X7400
6158 17:35:05.874085 ===================================
6159 17:35:05.877836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6160 17:35:05.884360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 17:35:05.894295 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 17:35:05.897440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6163 17:35:05.901088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6164 17:35:05.903924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6165 17:35:05.907735 [ANA_INIT] flow start
6166 17:35:05.910721 [ANA_INIT] PLL >>>>>>>>
6167 17:35:05.911024 [ANA_INIT] PLL <<<<<<<<
6168 17:35:05.914128 [ANA_INIT] MIDPI >>>>>>>>
6169 17:35:05.917173 [ANA_INIT] MIDPI <<<<<<<<
6170 17:35:05.920572 [ANA_INIT] DLL >>>>>>>>
6171 17:35:05.920874 [ANA_INIT] flow end
6172 17:35:05.923820 ============ LP4 DIFF to SE enter ============
6173 17:35:05.930853 ============ LP4 DIFF to SE exit ============
6174 17:35:05.931159 [ANA_INIT] <<<<<<<<<<<<<
6175 17:35:05.933959 [Flow] Enable top DCM control >>>>>
6176 17:35:05.937491 [Flow] Enable top DCM control <<<<<
6177 17:35:05.940438 Enable DLL master slave shuffle
6178 17:35:05.947087 ==============================================================
6179 17:35:05.947512 Gating Mode config
6180 17:35:05.953858 ==============================================================
6181 17:35:05.957185 Config description:
6182 17:35:05.967432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6183 17:35:05.973670 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6184 17:35:05.976817 SELPH_MODE 0: By rank 1: By Phase
6185 17:35:05.984108 ==============================================================
6186 17:35:05.986867 GAT_TRACK_EN = 0
6187 17:35:05.990585 RX_GATING_MODE = 2
6188 17:35:05.991020 RX_GATING_TRACK_MODE = 2
6189 17:35:05.993462 SELPH_MODE = 1
6190 17:35:05.996907 PICG_EARLY_EN = 1
6191 17:35:06.000347 VALID_LAT_VALUE = 1
6192 17:35:06.007193 ==============================================================
6193 17:35:06.010236 Enter into Gating configuration >>>>
6194 17:35:06.013302 Exit from Gating configuration <<<<
6195 17:35:06.016700 Enter into DVFS_PRE_config >>>>>
6196 17:35:06.026855 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6197 17:35:06.029587 Exit from DVFS_PRE_config <<<<<
6198 17:35:06.033066 Enter into PICG configuration >>>>
6199 17:35:06.036518 Exit from PICG configuration <<<<
6200 17:35:06.039652 [RX_INPUT] configuration >>>>>
6201 17:35:06.042973 [RX_INPUT] configuration <<<<<
6202 17:35:06.046364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6203 17:35:06.053198 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6204 17:35:06.059254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 17:35:06.065861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 17:35:06.072475 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 17:35:06.076044 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 17:35:06.082710 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6209 17:35:06.085917 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6210 17:35:06.089108 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6211 17:35:06.092852 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6212 17:35:06.099323 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6213 17:35:06.102795 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 17:35:06.105672 ===================================
6215 17:35:06.109366 LPDDR4 DRAM CONFIGURATION
6216 17:35:06.112231 ===================================
6217 17:35:06.112710 EX_ROW_EN[0] = 0x0
6218 17:35:06.116088 EX_ROW_EN[1] = 0x0
6219 17:35:06.116500 LP4Y_EN = 0x0
6220 17:35:06.119115 WORK_FSP = 0x0
6221 17:35:06.119593 WL = 0x2
6222 17:35:06.122284 RL = 0x2
6223 17:35:06.122698 BL = 0x2
6224 17:35:06.125652 RPST = 0x0
6225 17:35:06.128659 RD_PRE = 0x0
6226 17:35:06.129202 WR_PRE = 0x1
6227 17:35:06.132231 WR_PST = 0x0
6228 17:35:06.132810 DBI_WR = 0x0
6229 17:35:06.135749 DBI_RD = 0x0
6230 17:35:06.136198 OTF = 0x1
6231 17:35:06.139298 ===================================
6232 17:35:06.142003 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6233 17:35:06.148561 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6234 17:35:06.151820 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 17:35:06.155527 ===================================
6236 17:35:06.158230 LPDDR4 DRAM CONFIGURATION
6237 17:35:06.161518 ===================================
6238 17:35:06.162095 EX_ROW_EN[0] = 0x10
6239 17:35:06.165150 EX_ROW_EN[1] = 0x0
6240 17:35:06.165572 LP4Y_EN = 0x0
6241 17:35:06.168779 WORK_FSP = 0x0
6242 17:35:06.169332 WL = 0x2
6243 17:35:06.172064 RL = 0x2
6244 17:35:06.174997 BL = 0x2
6245 17:35:06.175466 RPST = 0x0
6246 17:35:06.178214 RD_PRE = 0x0
6247 17:35:06.178643 WR_PRE = 0x1
6248 17:35:06.181666 WR_PST = 0x0
6249 17:35:06.182088 DBI_WR = 0x0
6250 17:35:06.184807 DBI_RD = 0x0
6251 17:35:06.185227 OTF = 0x1
6252 17:35:06.188327 ===================================
6253 17:35:06.195227 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6254 17:35:06.198587 nWR fixed to 30
6255 17:35:06.202453 [ModeRegInit_LP4] CH0 RK0
6256 17:35:06.202873 [ModeRegInit_LP4] CH0 RK1
6257 17:35:06.205469 [ModeRegInit_LP4] CH1 RK0
6258 17:35:06.208879 [ModeRegInit_LP4] CH1 RK1
6259 17:35:06.209471 match AC timing 19
6260 17:35:06.215519 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6261 17:35:06.218661 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6262 17:35:06.221735 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6263 17:35:06.228149 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6264 17:35:06.232076 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6265 17:35:06.232303 ==
6266 17:35:06.235045 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 17:35:06.237987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 17:35:06.238217 ==
6269 17:35:06.244614 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 17:35:06.251328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6271 17:35:06.254870 [CA 0] Center 36 (8~64) winsize 57
6272 17:35:06.257770 [CA 1] Center 36 (8~64) winsize 57
6273 17:35:06.261194 [CA 2] Center 36 (8~64) winsize 57
6274 17:35:06.264229 [CA 3] Center 36 (8~64) winsize 57
6275 17:35:06.267971 [CA 4] Center 36 (8~64) winsize 57
6276 17:35:06.268053 [CA 5] Center 36 (8~64) winsize 57
6277 17:35:06.271308
6278 17:35:06.274256 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6279 17:35:06.274347
6280 17:35:06.277904 [CATrainingPosCal] consider 1 rank data
6281 17:35:06.281461 u2DelayCellTimex100 = 270/100 ps
6282 17:35:06.284674 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 17:35:06.287445 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 17:35:06.291171 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 17:35:06.294238 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 17:35:06.297985 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 17:35:06.301047 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 17:35:06.301151
6289 17:35:06.304077 CA PerBit enable=1, Macro0, CA PI delay=36
6290 17:35:06.304199
6291 17:35:06.307680 [CBTSetCACLKResult] CA Dly = 36
6292 17:35:06.310724 CS Dly: 1 (0~32)
6293 17:35:06.310858 ==
6294 17:35:06.314271 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 17:35:06.317735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 17:35:06.317910 ==
6297 17:35:06.324169 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 17:35:06.331068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6299 17:35:06.334131 [CA 0] Center 36 (8~64) winsize 57
6300 17:35:06.334304 [CA 1] Center 36 (8~64) winsize 57
6301 17:35:06.337693 [CA 2] Center 36 (8~64) winsize 57
6302 17:35:06.340731 [CA 3] Center 36 (8~64) winsize 57
6303 17:35:06.344259 [CA 4] Center 36 (8~64) winsize 57
6304 17:35:06.347229 [CA 5] Center 36 (8~64) winsize 57
6305 17:35:06.347464
6306 17:35:06.351084 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6307 17:35:06.351257
6308 17:35:06.357296 [CATrainingPosCal] consider 2 rank data
6309 17:35:06.357476 u2DelayCellTimex100 = 270/100 ps
6310 17:35:06.360980 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 17:35:06.367696 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 17:35:06.370802 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 17:35:06.374429 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 17:35:06.377393 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 17:35:06.380566 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 17:35:06.380746
6317 17:35:06.383691 CA PerBit enable=1, Macro0, CA PI delay=36
6318 17:35:06.383900
6319 17:35:06.387446 [CBTSetCACLKResult] CA Dly = 36
6320 17:35:06.387689 CS Dly: 1 (0~32)
6321 17:35:06.390533
6322 17:35:06.394153 ----->DramcWriteLeveling(PI) begin...
6323 17:35:06.394399 ==
6324 17:35:06.397720 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 17:35:06.400342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 17:35:06.400585 ==
6327 17:35:06.403896 Write leveling (Byte 0): 40 => 8
6328 17:35:06.407312 Write leveling (Byte 1): 40 => 8
6329 17:35:06.410595 DramcWriteLeveling(PI) end<-----
6330 17:35:06.410835
6331 17:35:06.411025 ==
6332 17:35:06.413893 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 17:35:06.417400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 17:35:06.417641 ==
6335 17:35:06.420898 [Gating] SW mode calibration
6336 17:35:06.427169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6337 17:35:06.433841 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6338 17:35:06.437209 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 17:35:06.440214 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 17:35:06.447193 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 17:35:06.450339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 17:35:06.453777 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 17:35:06.460991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 17:35:06.463520 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 17:35:06.466995 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 17:35:06.473818 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 17:35:06.474199 Total UI for P1: 0, mck2ui 16
6348 17:35:06.476998 best dqsien dly found for B0: ( 0, 14, 24)
6349 17:35:06.480700 Total UI for P1: 0, mck2ui 16
6350 17:35:06.483683 best dqsien dly found for B1: ( 0, 14, 24)
6351 17:35:06.486847 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6352 17:35:06.493415 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6353 17:35:06.493753
6354 17:35:06.497207 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 17:35:06.499824 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 17:35:06.503634 [Gating] SW calibration Done
6357 17:35:06.503907 ==
6358 17:35:06.506724 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 17:35:06.510343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 17:35:06.510614 ==
6361 17:35:06.513347 RX Vref Scan: 0
6362 17:35:06.513616
6363 17:35:06.513826 RX Vref 0 -> 0, step: 1
6364 17:35:06.514027
6365 17:35:06.516547 RX Delay -410 -> 252, step: 16
6366 17:35:06.523478 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6367 17:35:06.526572 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6368 17:35:06.529862 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6369 17:35:06.532934 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6370 17:35:06.536555 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6371 17:35:06.542992 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6372 17:35:06.546475 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6373 17:35:06.550375 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6374 17:35:06.552988 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6375 17:35:06.559846 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6376 17:35:06.562824 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6377 17:35:06.566083 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6378 17:35:06.572757 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6379 17:35:06.576042 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6380 17:35:06.579638 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6381 17:35:06.583033 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6382 17:35:06.583142 ==
6383 17:35:06.586606 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 17:35:06.593146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 17:35:06.593256 ==
6386 17:35:06.593343 DQS Delay:
6387 17:35:06.596187 DQS0 = 59, DQS1 = 59
6388 17:35:06.596314 DQM Delay:
6389 17:35:06.599671 DQM0 = 18, DQM1 = 10
6390 17:35:06.599828 DQ Delay:
6391 17:35:06.602733 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6392 17:35:06.606439 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6393 17:35:06.609470 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6394 17:35:06.612670 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6395 17:35:06.612883
6396 17:35:06.613046
6397 17:35:06.613185 ==
6398 17:35:06.616186 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 17:35:06.619377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 17:35:06.619599 ==
6401 17:35:06.619756
6402 17:35:06.619901
6403 17:35:06.622781 TX Vref Scan disable
6404 17:35:06.623156 == TX Byte 0 ==
6405 17:35:06.629913 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 17:35:06.632971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 17:35:06.633275 == TX Byte 1 ==
6408 17:35:06.635981 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 17:35:06.642828 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 17:35:06.643209 ==
6411 17:35:06.646055 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 17:35:06.649591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 17:35:06.650040 ==
6414 17:35:06.650354
6415 17:35:06.650637
6416 17:35:06.652777 TX Vref Scan disable
6417 17:35:06.653161 == TX Byte 0 ==
6418 17:35:06.659474 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 17:35:06.662961 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 17:35:06.663559 == TX Byte 1 ==
6421 17:35:06.669567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 17:35:06.672669 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 17:35:06.673072
6424 17:35:06.673391 [DATLAT]
6425 17:35:06.676328 Freq=400, CH0 RK0
6426 17:35:06.676748
6427 17:35:06.677087 DATLAT Default: 0xf
6428 17:35:06.679137 0, 0xFFFF, sum = 0
6429 17:35:06.679551 1, 0xFFFF, sum = 0
6430 17:35:06.683092 2, 0xFFFF, sum = 0
6431 17:35:06.683514 3, 0xFFFF, sum = 0
6432 17:35:06.686012 4, 0xFFFF, sum = 0
6433 17:35:06.686397 5, 0xFFFF, sum = 0
6434 17:35:06.689385 6, 0xFFFF, sum = 0
6435 17:35:06.689771 7, 0xFFFF, sum = 0
6436 17:35:06.693057 8, 0xFFFF, sum = 0
6437 17:35:06.693444 9, 0xFFFF, sum = 0
6438 17:35:06.696006 10, 0xFFFF, sum = 0
6439 17:35:06.699189 11, 0xFFFF, sum = 0
6440 17:35:06.699624 12, 0xFFFF, sum = 0
6441 17:35:06.702173 13, 0x0, sum = 1
6442 17:35:06.702553 14, 0x0, sum = 2
6443 17:35:06.702855 15, 0x0, sum = 3
6444 17:35:06.705921 16, 0x0, sum = 4
6445 17:35:06.706302 best_step = 14
6446 17:35:06.706602
6447 17:35:06.706881 ==
6448 17:35:06.709374 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 17:35:06.716122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 17:35:06.716516 ==
6451 17:35:06.716843 RX Vref Scan: 1
6452 17:35:06.717128
6453 17:35:06.719435 RX Vref 0 -> 0, step: 1
6454 17:35:06.719817
6455 17:35:06.722402 RX Delay -359 -> 252, step: 8
6456 17:35:06.722779
6457 17:35:06.725893 Set Vref, RX VrefLevel [Byte0]: 60
6458 17:35:06.729483 [Byte1]: 47
6459 17:35:06.732465
6460 17:35:06.732842 Final RX Vref Byte 0 = 60 to rank0
6461 17:35:06.735842 Final RX Vref Byte 1 = 47 to rank0
6462 17:35:06.739207 Final RX Vref Byte 0 = 60 to rank1
6463 17:35:06.742406 Final RX Vref Byte 1 = 47 to rank1==
6464 17:35:06.745594 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 17:35:06.752635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 17:35:06.753017 ==
6467 17:35:06.753319 DQS Delay:
6468 17:35:06.755712 DQS0 = 60, DQS1 = 68
6469 17:35:06.756089 DQM Delay:
6470 17:35:06.756387 DQM0 = 14, DQM1 = 13
6471 17:35:06.758878 DQ Delay:
6472 17:35:06.762553 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6473 17:35:06.765841 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6474 17:35:06.766225 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6475 17:35:06.768682 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6476 17:35:06.772624
6477 17:35:06.773005
6478 17:35:06.779052 [DQSOSCAuto] RK0, (LSB)MR18= 0x8181, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6479 17:35:06.782220 CH0 RK0: MR19=C0C, MR18=8181
6480 17:35:06.789083 CH0_RK0: MR19=0xC0C, MR18=0x8181, DQSOSC=393, MR23=63, INC=382, DEC=254
6481 17:35:06.789478 ==
6482 17:35:06.791962 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 17:35:06.796008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 17:35:06.796543 ==
6485 17:35:06.798790 [Gating] SW mode calibration
6486 17:35:06.805493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6487 17:35:06.811972 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6488 17:35:06.815752 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 17:35:06.818756 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 17:35:06.825216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 17:35:06.828943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 17:35:06.831847 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 17:35:06.838578 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 17:35:06.841725 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 17:35:06.844909 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 17:35:06.851935 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 17:35:06.852421 Total UI for P1: 0, mck2ui 16
6498 17:35:06.858220 best dqsien dly found for B0: ( 0, 14, 24)
6499 17:35:06.858758 Total UI for P1: 0, mck2ui 16
6500 17:35:06.861371 best dqsien dly found for B1: ( 0, 14, 24)
6501 17:35:06.868511 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6502 17:35:06.871379 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6503 17:35:06.871849
6504 17:35:06.874893 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 17:35:06.878007 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 17:35:06.881546 [Gating] SW calibration Done
6507 17:35:06.881934 ==
6508 17:35:06.884674 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 17:35:06.888316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 17:35:06.888731 ==
6511 17:35:06.891438 RX Vref Scan: 0
6512 17:35:06.891837
6513 17:35:06.892235 RX Vref 0 -> 0, step: 1
6514 17:35:06.892616
6515 17:35:06.894936 RX Delay -410 -> 252, step: 16
6516 17:35:06.901452 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6517 17:35:06.904566 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6518 17:35:06.907852 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6519 17:35:06.910975 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6520 17:35:06.917844 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6521 17:35:06.920976 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6522 17:35:06.924380 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6523 17:35:06.927977 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6524 17:35:06.934494 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6525 17:35:06.937623 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6526 17:35:06.941126 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6527 17:35:06.944469 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6528 17:35:06.950930 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6529 17:35:06.954028 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6530 17:35:06.957474 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6531 17:35:06.961086 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6532 17:35:06.964119 ==
6533 17:35:06.967729 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 17:35:06.970689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 17:35:06.971077 ==
6536 17:35:06.971379 DQS Delay:
6537 17:35:06.974054 DQS0 = 59, DQS1 = 59
6538 17:35:06.974436 DQM Delay:
6539 17:35:06.977419 DQM0 = 15, DQM1 = 10
6540 17:35:06.978008 DQ Delay:
6541 17:35:06.980696 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6542 17:35:06.983746 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6543 17:35:06.987374 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6544 17:35:06.990720 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6545 17:35:06.991355
6546 17:35:06.991883
6547 17:35:06.992393 ==
6548 17:35:06.993645 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 17:35:06.997580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 17:35:06.998175 ==
6551 17:35:06.998706
6552 17:35:06.999203
6553 17:35:07.000724 TX Vref Scan disable
6554 17:35:07.001274 == TX Byte 0 ==
6555 17:35:07.007287 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6556 17:35:07.010477 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6557 17:35:07.011075 == TX Byte 1 ==
6558 17:35:07.016913 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6559 17:35:07.020208 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6560 17:35:07.020756 ==
6561 17:35:07.023337 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 17:35:07.027003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 17:35:07.027647 ==
6564 17:35:07.028241
6565 17:35:07.028783
6566 17:35:07.030052 TX Vref Scan disable
6567 17:35:07.033763 == TX Byte 0 ==
6568 17:35:07.036768 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6569 17:35:07.040386 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6570 17:35:07.040791 == TX Byte 1 ==
6571 17:35:07.046926 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6572 17:35:07.049984 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6573 17:35:07.050357
6574 17:35:07.050450 [DATLAT]
6575 17:35:07.053233 Freq=400, CH0 RK1
6576 17:35:07.053306
6577 17:35:07.053367 DATLAT Default: 0xe
6578 17:35:07.056453 0, 0xFFFF, sum = 0
6579 17:35:07.056526 1, 0xFFFF, sum = 0
6580 17:35:07.059788 2, 0xFFFF, sum = 0
6581 17:35:07.059872 3, 0xFFFF, sum = 0
6582 17:35:07.063043 4, 0xFFFF, sum = 0
6583 17:35:07.063144 5, 0xFFFF, sum = 0
6584 17:35:07.066397 6, 0xFFFF, sum = 0
6585 17:35:07.070022 7, 0xFFFF, sum = 0
6586 17:35:07.070122 8, 0xFFFF, sum = 0
6587 17:35:07.072830 9, 0xFFFF, sum = 0
6588 17:35:07.072908 10, 0xFFFF, sum = 0
6589 17:35:07.076605 11, 0xFFFF, sum = 0
6590 17:35:07.076690 12, 0xFFFF, sum = 0
6591 17:35:07.079831 13, 0x0, sum = 1
6592 17:35:07.079922 14, 0x0, sum = 2
6593 17:35:07.082970 15, 0x0, sum = 3
6594 17:35:07.083049 16, 0x0, sum = 4
6595 17:35:07.085993 best_step = 14
6596 17:35:07.086085
6597 17:35:07.086166 ==
6598 17:35:07.089798 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 17:35:07.092883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 17:35:07.092985 ==
6601 17:35:07.093080 RX Vref Scan: 0
6602 17:35:07.096350
6603 17:35:07.096464 RX Vref 0 -> 0, step: 1
6604 17:35:07.096554
6605 17:35:07.099373 RX Delay -359 -> 252, step: 8
6606 17:35:07.106981 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6607 17:35:07.110050 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6608 17:35:07.113873 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6609 17:35:07.120719 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6610 17:35:07.123612 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6611 17:35:07.126819 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6612 17:35:07.130525 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6613 17:35:07.133851 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6614 17:35:07.140505 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6615 17:35:07.143622 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6616 17:35:07.147056 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6617 17:35:07.153380 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6618 17:35:07.156854 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6619 17:35:07.160070 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6620 17:35:07.163663 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6621 17:35:07.170617 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6622 17:35:07.171258 ==
6623 17:35:07.173382 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 17:35:07.176443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 17:35:07.176523 ==
6626 17:35:07.176604 DQS Delay:
6627 17:35:07.180046 DQS0 = 60, DQS1 = 72
6628 17:35:07.180148 DQM Delay:
6629 17:35:07.183355 DQM0 = 11, DQM1 = 17
6630 17:35:07.183446 DQ Delay:
6631 17:35:07.186588 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6632 17:35:07.190325 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6633 17:35:07.193302 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6634 17:35:07.196474 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6635 17:35:07.196562
6636 17:35:07.196628
6637 17:35:07.203213 [DQSOSCAuto] RK1, (LSB)MR18= 0xc177, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6638 17:35:07.206733 CH0 RK1: MR19=C0C, MR18=C177
6639 17:35:07.213668 CH0_RK1: MR19=0xC0C, MR18=0xC177, DQSOSC=385, MR23=63, INC=398, DEC=265
6640 17:35:07.216653 [RxdqsGatingPostProcess] freq 400
6641 17:35:07.222964 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6642 17:35:07.223114 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 17:35:07.226195 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 17:35:07.229891 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 17:35:07.232806 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 17:35:07.236287 best DQS0 dly(2T, 0.5T) = (0, 10)
6647 17:35:07.239425 best DQS1 dly(2T, 0.5T) = (0, 10)
6648 17:35:07.243257 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6649 17:35:07.246040 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6650 17:35:07.249764 Pre-setting of DQS Precalculation
6651 17:35:07.256079 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6652 17:35:07.256334 ==
6653 17:35:07.259373 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 17:35:07.262892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 17:35:07.263243 ==
6656 17:35:07.269696 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 17:35:07.272791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6658 17:35:07.275931 [CA 0] Center 36 (8~64) winsize 57
6659 17:35:07.279348 [CA 1] Center 36 (8~64) winsize 57
6660 17:35:07.282985 [CA 2] Center 36 (8~64) winsize 57
6661 17:35:07.286112 [CA 3] Center 36 (8~64) winsize 57
6662 17:35:07.289347 [CA 4] Center 36 (8~64) winsize 57
6663 17:35:07.292470 [CA 5] Center 36 (8~64) winsize 57
6664 17:35:07.292728
6665 17:35:07.296227 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6666 17:35:07.296492
6667 17:35:07.298912 [CATrainingPosCal] consider 1 rank data
6668 17:35:07.302219 u2DelayCellTimex100 = 270/100 ps
6669 17:35:07.305859 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 17:35:07.308885 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 17:35:07.315724 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 17:35:07.319261 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 17:35:07.322126 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 17:35:07.325772 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 17:35:07.326085
6676 17:35:07.328701 CA PerBit enable=1, Macro0, CA PI delay=36
6677 17:35:07.329017
6678 17:35:07.332938 [CBTSetCACLKResult] CA Dly = 36
6679 17:35:07.333201 CS Dly: 1 (0~32)
6680 17:35:07.335342 ==
6681 17:35:07.338704 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 17:35:07.342206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 17:35:07.342467 ==
6684 17:35:07.345498 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 17:35:07.352400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6686 17:35:07.355448 [CA 0] Center 36 (8~64) winsize 57
6687 17:35:07.358740 [CA 1] Center 36 (8~64) winsize 57
6688 17:35:07.361760 [CA 2] Center 36 (8~64) winsize 57
6689 17:35:07.365225 [CA 3] Center 36 (8~64) winsize 57
6690 17:35:07.368875 [CA 4] Center 36 (8~64) winsize 57
6691 17:35:07.371837 [CA 5] Center 36 (8~64) winsize 57
6692 17:35:07.372099
6693 17:35:07.375324 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6694 17:35:07.375617
6695 17:35:07.378737 [CATrainingPosCal] consider 2 rank data
6696 17:35:07.382099 u2DelayCellTimex100 = 270/100 ps
6697 17:35:07.385109 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 17:35:07.388455 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 17:35:07.391789 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 17:35:07.395511 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 17:35:07.402143 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 17:35:07.405188 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 17:35:07.405460
6704 17:35:07.408607 CA PerBit enable=1, Macro0, CA PI delay=36
6705 17:35:07.408871
6706 17:35:07.411725 [CBTSetCACLKResult] CA Dly = 36
6707 17:35:07.411989 CS Dly: 1 (0~32)
6708 17:35:07.412254
6709 17:35:07.414777 ----->DramcWriteLeveling(PI) begin...
6710 17:35:07.415044 ==
6711 17:35:07.418346 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 17:35:07.425122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 17:35:07.425381 ==
6714 17:35:07.428598 Write leveling (Byte 0): 40 => 8
6715 17:35:07.428901 Write leveling (Byte 1): 40 => 8
6716 17:35:07.431712 DramcWriteLeveling(PI) end<-----
6717 17:35:07.431970
6718 17:35:07.434727 ==
6719 17:35:07.434983 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 17:35:07.441549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 17:35:07.441810 ==
6722 17:35:07.444859 [Gating] SW mode calibration
6723 17:35:07.451368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6724 17:35:07.455048 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6725 17:35:07.461290 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 17:35:07.464908 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 17:35:07.467693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 17:35:07.474494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 17:35:07.477893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 17:35:07.481392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 17:35:07.488290 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 17:35:07.491348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 17:35:07.494406 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 17:35:07.497837 Total UI for P1: 0, mck2ui 16
6735 17:35:07.500888 best dqsien dly found for B0: ( 0, 14, 24)
6736 17:35:07.504105 Total UI for P1: 0, mck2ui 16
6737 17:35:07.507633 best dqsien dly found for B1: ( 0, 14, 24)
6738 17:35:07.511066 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6739 17:35:07.514219 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6740 17:35:07.514646
6741 17:35:07.520985 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 17:35:07.524080 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 17:35:07.524401 [Gating] SW calibration Done
6744 17:35:07.527654 ==
6745 17:35:07.531168 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 17:35:07.534255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 17:35:07.534676 ==
6748 17:35:07.535037 RX Vref Scan: 0
6749 17:35:07.535380
6750 17:35:07.538016 RX Vref 0 -> 0, step: 1
6751 17:35:07.538346
6752 17:35:07.541018 RX Delay -410 -> 252, step: 16
6753 17:35:07.544507 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6754 17:35:07.547849 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6755 17:35:07.554754 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6756 17:35:07.557601 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6757 17:35:07.560756 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6758 17:35:07.564513 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6759 17:35:07.570649 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6760 17:35:07.574076 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6761 17:35:07.577837 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6762 17:35:07.581014 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6763 17:35:07.587458 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6764 17:35:07.590715 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6765 17:35:07.594372 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6766 17:35:07.600796 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6767 17:35:07.604208 iDelay=230, Bit 14, Center -51 (-314 ~ 213) 528
6768 17:35:07.607309 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6769 17:35:07.607940 ==
6770 17:35:07.610710 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 17:35:07.614321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 17:35:07.614739 ==
6773 17:35:07.617605 DQS Delay:
6774 17:35:07.618034 DQS0 = 51, DQS1 = 67
6775 17:35:07.620744 DQM Delay:
6776 17:35:07.621326 DQM0 = 13, DQM1 = 17
6777 17:35:07.623820 DQ Delay:
6778 17:35:07.624411 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6779 17:35:07.627375 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6780 17:35:07.630910 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6781 17:35:07.633824 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6782 17:35:07.634332
6783 17:35:07.634656
6784 17:35:07.634959 ==
6785 17:35:07.637317 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 17:35:07.643835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 17:35:07.644287 ==
6788 17:35:07.644617
6789 17:35:07.644919
6790 17:35:07.645209 TX Vref Scan disable
6791 17:35:07.647489 == TX Byte 0 ==
6792 17:35:07.650988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 17:35:07.653563 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 17:35:07.657327 == TX Byte 1 ==
6795 17:35:07.660734 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 17:35:07.663702 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 17:35:07.666942 ==
6798 17:35:07.667382 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 17:35:07.673931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 17:35:07.674361 ==
6801 17:35:07.674800
6802 17:35:07.675212
6803 17:35:07.677509 TX Vref Scan disable
6804 17:35:07.677937 == TX Byte 0 ==
6805 17:35:07.680408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 17:35:07.687361 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 17:35:07.687840 == TX Byte 1 ==
6808 17:35:07.690172 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 17:35:07.693415 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 17:35:07.697020
6811 17:35:07.697444 [DATLAT]
6812 17:35:07.697877 Freq=400, CH1 RK0
6813 17:35:07.698286
6814 17:35:07.700705 DATLAT Default: 0xf
6815 17:35:07.701134 0, 0xFFFF, sum = 0
6816 17:35:07.703674 1, 0xFFFF, sum = 0
6817 17:35:07.704139 2, 0xFFFF, sum = 0
6818 17:35:07.707327 3, 0xFFFF, sum = 0
6819 17:35:07.710159 4, 0xFFFF, sum = 0
6820 17:35:07.710582 5, 0xFFFF, sum = 0
6821 17:35:07.713261 6, 0xFFFF, sum = 0
6822 17:35:07.713949 7, 0xFFFF, sum = 0
6823 17:35:07.716585 8, 0xFFFF, sum = 0
6824 17:35:07.717111 9, 0xFFFF, sum = 0
6825 17:35:07.720334 10, 0xFFFF, sum = 0
6826 17:35:07.721040 11, 0xFFFF, sum = 0
6827 17:35:07.723517 12, 0xFFFF, sum = 0
6828 17:35:07.724128 13, 0x0, sum = 1
6829 17:35:07.726545 14, 0x0, sum = 2
6830 17:35:07.727202 15, 0x0, sum = 3
6831 17:35:07.730028 16, 0x0, sum = 4
6832 17:35:07.730640 best_step = 14
6833 17:35:07.731224
6834 17:35:07.731743 ==
6835 17:35:07.733164 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 17:35:07.736638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 17:35:07.739770 ==
6838 17:35:07.740258 RX Vref Scan: 1
6839 17:35:07.740776
6840 17:35:07.743440 RX Vref 0 -> 0, step: 1
6841 17:35:07.743999
6842 17:35:07.746389 RX Delay -375 -> 252, step: 8
6843 17:35:07.746918
6844 17:35:07.749549 Set Vref, RX VrefLevel [Byte0]: 56
6845 17:35:07.753203 [Byte1]: 52
6846 17:35:07.753737
6847 17:35:07.756605 Final RX Vref Byte 0 = 56 to rank0
6848 17:35:07.759330 Final RX Vref Byte 1 = 52 to rank0
6849 17:35:07.762792 Final RX Vref Byte 0 = 56 to rank1
6850 17:35:07.765896 Final RX Vref Byte 1 = 52 to rank1==
6851 17:35:07.768949 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 17:35:07.772752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 17:35:07.772853 ==
6854 17:35:07.775709 DQS Delay:
6855 17:35:07.775790 DQS0 = 56, DQS1 = 64
6856 17:35:07.779133 DQM Delay:
6857 17:35:07.779217 DQM0 = 13, DQM1 = 10
6858 17:35:07.782735 DQ Delay:
6859 17:35:07.782824 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6860 17:35:07.786166 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6861 17:35:07.789276 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6862 17:35:07.792525 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6863 17:35:07.792634
6864 17:35:07.792740
6865 17:35:07.802572 [DQSOSCAuto] RK0, (LSB)MR18= 0x576b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6866 17:35:07.805987 CH1 RK0: MR19=C0C, MR18=576B
6867 17:35:07.808882 CH1_RK0: MR19=0xC0C, MR18=0x576B, DQSOSC=396, MR23=63, INC=376, DEC=251
6868 17:35:07.812215 ==
6869 17:35:07.815459 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 17:35:07.818873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 17:35:07.818981 ==
6872 17:35:07.822044 [Gating] SW mode calibration
6873 17:35:07.829287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6874 17:35:07.832339 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6875 17:35:07.838917 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 17:35:07.842241 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 17:35:07.845417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 17:35:07.851973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 17:35:07.855321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 17:35:07.858877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 17:35:07.865044 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 17:35:07.868590 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 17:35:07.872123 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 17:35:07.875703 Total UI for P1: 0, mck2ui 16
6885 17:35:07.878481 best dqsien dly found for B0: ( 0, 14, 24)
6886 17:35:07.881986 Total UI for P1: 0, mck2ui 16
6887 17:35:07.885339 best dqsien dly found for B1: ( 0, 14, 24)
6888 17:35:07.888471 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6889 17:35:07.891666 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6890 17:35:07.891748
6891 17:35:07.898373 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 17:35:07.901799 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 17:35:07.904884 [Gating] SW calibration Done
6894 17:35:07.904966 ==
6895 17:35:07.908795 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 17:35:07.911742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 17:35:07.911825 ==
6898 17:35:07.911889 RX Vref Scan: 0
6899 17:35:07.911949
6900 17:35:07.915077 RX Vref 0 -> 0, step: 1
6901 17:35:07.915158
6902 17:35:07.918295 RX Delay -410 -> 252, step: 16
6903 17:35:07.921569 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6904 17:35:07.928772 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6905 17:35:07.931460 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6906 17:35:07.935078 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6907 17:35:07.937924 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6908 17:35:07.944712 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6909 17:35:07.948218 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6910 17:35:07.951273 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6911 17:35:07.954386 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6912 17:35:07.961394 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6913 17:35:07.964507 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6914 17:35:07.968156 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6915 17:35:07.970944 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6916 17:35:07.978074 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6917 17:35:07.981084 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6918 17:35:07.984541 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6919 17:35:07.984623 ==
6920 17:35:07.987255 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 17:35:07.994122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 17:35:07.994205 ==
6923 17:35:07.994269 DQS Delay:
6924 17:35:07.997624 DQS0 = 59, DQS1 = 59
6925 17:35:07.997705 DQM Delay:
6926 17:35:07.997769 DQM0 = 19, DQM1 = 15
6927 17:35:08.001241 DQ Delay:
6928 17:35:08.004561 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6929 17:35:08.007421 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6930 17:35:08.007517 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6931 17:35:08.014152 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6932 17:35:08.014234
6933 17:35:08.014297
6934 17:35:08.014356 ==
6935 17:35:08.017765 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 17:35:08.020657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 17:35:08.020746 ==
6938 17:35:08.020816
6939 17:35:08.020881
6940 17:35:08.024533 TX Vref Scan disable
6941 17:35:08.024613 == TX Byte 0 ==
6942 17:35:08.027613 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6943 17:35:08.034167 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6944 17:35:08.034249 == TX Byte 1 ==
6945 17:35:08.037412 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6946 17:35:08.044151 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6947 17:35:08.044271 ==
6948 17:35:08.047453 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 17:35:08.050566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 17:35:08.050642 ==
6951 17:35:08.050705
6952 17:35:08.050763
6953 17:35:08.053905 TX Vref Scan disable
6954 17:35:08.053987 == TX Byte 0 ==
6955 17:35:08.060421 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6956 17:35:08.064124 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6957 17:35:08.064205 == TX Byte 1 ==
6958 17:35:08.071037 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6959 17:35:08.074016 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6960 17:35:08.074097
6961 17:35:08.074161 [DATLAT]
6962 17:35:08.076904 Freq=400, CH1 RK1
6963 17:35:08.076986
6964 17:35:08.077049 DATLAT Default: 0xe
6965 17:35:08.080363 0, 0xFFFF, sum = 0
6966 17:35:08.080446 1, 0xFFFF, sum = 0
6967 17:35:08.083559 2, 0xFFFF, sum = 0
6968 17:35:08.083640 3, 0xFFFF, sum = 0
6969 17:35:08.086825 4, 0xFFFF, sum = 0
6970 17:35:08.086907 5, 0xFFFF, sum = 0
6971 17:35:08.090255 6, 0xFFFF, sum = 0
6972 17:35:08.090338 7, 0xFFFF, sum = 0
6973 17:35:08.093658 8, 0xFFFF, sum = 0
6974 17:35:08.093741 9, 0xFFFF, sum = 0
6975 17:35:08.097301 10, 0xFFFF, sum = 0
6976 17:35:08.097384 11, 0xFFFF, sum = 0
6977 17:35:08.100081 12, 0xFFFF, sum = 0
6978 17:35:08.100162 13, 0x0, sum = 1
6979 17:35:08.103567 14, 0x0, sum = 2
6980 17:35:08.103650 15, 0x0, sum = 3
6981 17:35:08.106720 16, 0x0, sum = 4
6982 17:35:08.106802 best_step = 14
6983 17:35:08.106866
6984 17:35:08.106925 ==
6985 17:35:08.110104 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 17:35:08.116910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 17:35:08.116993 ==
6988 17:35:08.117058 RX Vref Scan: 0
6989 17:35:08.117118
6990 17:35:08.120158 RX Vref 0 -> 0, step: 1
6991 17:35:08.120239
6992 17:35:08.124157 RX Delay -359 -> 252, step: 8
6993 17:35:08.130143 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6994 17:35:08.133736 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6995 17:35:08.136754 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6996 17:35:08.140692 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6997 17:35:08.147081 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6998 17:35:08.150130 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6999 17:35:08.153750 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7000 17:35:08.157276 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7001 17:35:08.163426 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7002 17:35:08.167005 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7003 17:35:08.170348 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7004 17:35:08.173753 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7005 17:35:08.180007 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7006 17:35:08.183273 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7007 17:35:08.186425 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7008 17:35:08.193360 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7009 17:35:08.193475 ==
7010 17:35:08.196562 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 17:35:08.199849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 17:35:08.199934 ==
7013 17:35:08.199998 DQS Delay:
7014 17:35:08.203041 DQS0 = 60, DQS1 = 64
7015 17:35:08.203146 DQM Delay:
7016 17:35:08.206161 DQM0 = 12, DQM1 = 10
7017 17:35:08.206267 DQ Delay:
7018 17:35:08.209728 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7019 17:35:08.213312 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7020 17:35:08.216175 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7021 17:35:08.219575 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7022 17:35:08.219655
7023 17:35:08.219717
7024 17:35:08.225966 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7025 17:35:08.229255 CH1 RK1: MR19=C0C, MR18=76A7
7026 17:35:08.236013 CH1_RK1: MR19=0xC0C, MR18=0x76A7, DQSOSC=389, MR23=63, INC=390, DEC=260
7027 17:35:08.239574 [RxdqsGatingPostProcess] freq 400
7028 17:35:08.246367 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7029 17:35:08.249346 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 17:35:08.249430 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 17:35:08.252879 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 17:35:08.255757 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 17:35:08.259312 best DQS0 dly(2T, 0.5T) = (0, 10)
7034 17:35:08.262168 best DQS1 dly(2T, 0.5T) = (0, 10)
7035 17:35:08.265670 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7036 17:35:08.269351 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7037 17:35:08.272377 Pre-setting of DQS Precalculation
7038 17:35:08.279373 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7039 17:35:08.285673 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7040 17:35:08.292266 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7041 17:35:08.292380
7042 17:35:08.292479
7043 17:35:08.295538 [Calibration Summary] 800 Mbps
7044 17:35:08.295620 CH 0, Rank 0
7045 17:35:08.298736 SW Impedance : PASS
7046 17:35:08.301818 DUTY Scan : NO K
7047 17:35:08.301931 ZQ Calibration : PASS
7048 17:35:08.305208 Jitter Meter : NO K
7049 17:35:08.308908 CBT Training : PASS
7050 17:35:08.308990 Write leveling : PASS
7051 17:35:08.311758 RX DQS gating : PASS
7052 17:35:08.315247 RX DQ/DQS(RDDQC) : PASS
7053 17:35:08.315328 TX DQ/DQS : PASS
7054 17:35:08.318697 RX DATLAT : PASS
7055 17:35:08.321918 RX DQ/DQS(Engine): PASS
7056 17:35:08.321999 TX OE : NO K
7057 17:35:08.322064 All Pass.
7058 17:35:08.325362
7059 17:35:08.325443 CH 0, Rank 1
7060 17:35:08.328507 SW Impedance : PASS
7061 17:35:08.328588 DUTY Scan : NO K
7062 17:35:08.332389 ZQ Calibration : PASS
7063 17:35:08.334840 Jitter Meter : NO K
7064 17:35:08.334922 CBT Training : PASS
7065 17:35:08.338534 Write leveling : NO K
7066 17:35:08.338615 RX DQS gating : PASS
7067 17:35:08.342027 RX DQ/DQS(RDDQC) : PASS
7068 17:35:08.344797 TX DQ/DQS : PASS
7069 17:35:08.344885 RX DATLAT : PASS
7070 17:35:08.348279 RX DQ/DQS(Engine): PASS
7071 17:35:08.352240 TX OE : NO K
7072 17:35:08.352342 All Pass.
7073 17:35:08.352422
7074 17:35:08.352497 CH 1, Rank 0
7075 17:35:08.355146 SW Impedance : PASS
7076 17:35:08.358581 DUTY Scan : NO K
7077 17:35:08.358691 ZQ Calibration : PASS
7078 17:35:08.361902 Jitter Meter : NO K
7079 17:35:08.364676 CBT Training : PASS
7080 17:35:08.364844 Write leveling : PASS
7081 17:35:08.368145 RX DQS gating : PASS
7082 17:35:08.371437 RX DQ/DQS(RDDQC) : PASS
7083 17:35:08.371590 TX DQ/DQS : PASS
7084 17:35:08.374553 RX DATLAT : PASS
7085 17:35:08.377838 RX DQ/DQS(Engine): PASS
7086 17:35:08.378010 TX OE : NO K
7087 17:35:08.381417 All Pass.
7088 17:35:08.381615
7089 17:35:08.381770 CH 1, Rank 1
7090 17:35:08.385175 SW Impedance : PASS
7091 17:35:08.385375 DUTY Scan : NO K
7092 17:35:08.387824 ZQ Calibration : PASS
7093 17:35:08.391725 Jitter Meter : NO K
7094 17:35:08.392026 CBT Training : PASS
7095 17:35:08.395152 Write leveling : NO K
7096 17:35:08.398288 RX DQS gating : PASS
7097 17:35:08.398673 RX DQ/DQS(RDDQC) : PASS
7098 17:35:08.401199 TX DQ/DQS : PASS
7099 17:35:08.404499 RX DATLAT : PASS
7100 17:35:08.404884 RX DQ/DQS(Engine): PASS
7101 17:35:08.407800 TX OE : NO K
7102 17:35:08.408185 All Pass.
7103 17:35:08.408488
7104 17:35:08.411598 DramC Write-DBI off
7105 17:35:08.412113 PER_BANK_REFRESH: Hybrid Mode
7106 17:35:08.414776 TX_TRACKING: ON
7107 17:35:08.424779 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7108 17:35:08.428284 [FAST_K] Save calibration result to emmc
7109 17:35:08.431150 dramc_set_vcore_voltage set vcore to 725000
7110 17:35:08.434419 Read voltage for 1600, 0
7111 17:35:08.434823 Vio18 = 0
7112 17:35:08.435119 Vcore = 725000
7113 17:35:08.437627 Vdram = 0
7114 17:35:08.438040 Vddq = 0
7115 17:35:08.438395 Vmddr = 0
7116 17:35:08.444411 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7117 17:35:08.447697 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7118 17:35:08.451232 MEM_TYPE=3, freq_sel=13
7119 17:35:08.454194 sv_algorithm_assistance_LP4_3733
7120 17:35:08.457403 ============ PULL DRAM RESETB DOWN ============
7121 17:35:08.461020 ========== PULL DRAM RESETB DOWN end =========
7122 17:35:08.467547 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7123 17:35:08.471026 ===================================
7124 17:35:08.471626 LPDDR4 DRAM CONFIGURATION
7125 17:35:08.474559 ===================================
7126 17:35:08.477722 EX_ROW_EN[0] = 0x0
7127 17:35:08.480531 EX_ROW_EN[1] = 0x0
7128 17:35:08.480989 LP4Y_EN = 0x0
7129 17:35:08.484396 WORK_FSP = 0x1
7130 17:35:08.484784 WL = 0x5
7131 17:35:08.487414 RL = 0x5
7132 17:35:08.487509 BL = 0x2
7133 17:35:08.490220 RPST = 0x0
7134 17:35:08.490303 RD_PRE = 0x0
7135 17:35:08.494075 WR_PRE = 0x1
7136 17:35:08.494156 WR_PST = 0x1
7137 17:35:08.497145 DBI_WR = 0x0
7138 17:35:08.497225 DBI_RD = 0x0
7139 17:35:08.500189 OTF = 0x1
7140 17:35:08.503713 ===================================
7141 17:35:08.506877 ===================================
7142 17:35:08.506984 ANA top config
7143 17:35:08.510185 ===================================
7144 17:35:08.513405 DLL_ASYNC_EN = 0
7145 17:35:08.517159 ALL_SLAVE_EN = 0
7146 17:35:08.520085 NEW_RANK_MODE = 1
7147 17:35:08.520172 DLL_IDLE_MODE = 1
7148 17:35:08.523548 LP45_APHY_COMB_EN = 1
7149 17:35:08.526790 TX_ODT_DIS = 0
7150 17:35:08.530002 NEW_8X_MODE = 1
7151 17:35:08.533493 ===================================
7152 17:35:08.537041 ===================================
7153 17:35:08.540371 data_rate = 3200
7154 17:35:08.540492 CKR = 1
7155 17:35:08.543628 DQ_P2S_RATIO = 8
7156 17:35:08.546789 ===================================
7157 17:35:08.549734 CA_P2S_RATIO = 8
7158 17:35:08.553733 DQ_CA_OPEN = 0
7159 17:35:08.556986 DQ_SEMI_OPEN = 0
7160 17:35:08.559730 CA_SEMI_OPEN = 0
7161 17:35:08.559929 CA_FULL_RATE = 0
7162 17:35:08.563769 DQ_CKDIV4_EN = 0
7163 17:35:08.566539 CA_CKDIV4_EN = 0
7164 17:35:08.569575 CA_PREDIV_EN = 0
7165 17:35:08.572835 PH8_DLY = 12
7166 17:35:08.576347 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7167 17:35:08.576428 DQ_AAMCK_DIV = 4
7168 17:35:08.579826 CA_AAMCK_DIV = 4
7169 17:35:08.583137 CA_ADMCK_DIV = 4
7170 17:35:08.586103 DQ_TRACK_CA_EN = 0
7171 17:35:08.589347 CA_PICK = 1600
7172 17:35:08.592866 CA_MCKIO = 1600
7173 17:35:08.596525 MCKIO_SEMI = 0
7174 17:35:08.599492 PLL_FREQ = 3068
7175 17:35:08.599573 DQ_UI_PI_RATIO = 32
7176 17:35:08.602720 CA_UI_PI_RATIO = 0
7177 17:35:08.606397 ===================================
7178 17:35:08.609467 ===================================
7179 17:35:08.613169 memory_type:LPDDR4
7180 17:35:08.616007 GP_NUM : 10
7181 17:35:08.616115 SRAM_EN : 1
7182 17:35:08.619606 MD32_EN : 0
7183 17:35:08.622529 ===================================
7184 17:35:08.626280 [ANA_INIT] >>>>>>>>>>>>>>
7185 17:35:08.626401 <<<<<< [CONFIGURE PHASE]: ANA_TX
7186 17:35:08.632556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7187 17:35:08.635655 ===================================
7188 17:35:08.635810 data_rate = 3200,PCW = 0X7600
7189 17:35:08.639227 ===================================
7190 17:35:08.642510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7191 17:35:08.649062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 17:35:08.655525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 17:35:08.659095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7194 17:35:08.662183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7195 17:35:08.665621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7196 17:35:08.668991 [ANA_INIT] flow start
7197 17:35:08.669420 [ANA_INIT] PLL >>>>>>>>
7198 17:35:08.672464 [ANA_INIT] PLL <<<<<<<<
7199 17:35:08.675474 [ANA_INIT] MIDPI >>>>>>>>
7200 17:35:08.678864 [ANA_INIT] MIDPI <<<<<<<<
7201 17:35:08.679278 [ANA_INIT] DLL >>>>>>>>
7202 17:35:08.682613 [ANA_INIT] DLL <<<<<<<<
7203 17:35:08.685369 [ANA_INIT] flow end
7204 17:35:08.689125 ============ LP4 DIFF to SE enter ============
7205 17:35:08.692039 ============ LP4 DIFF to SE exit ============
7206 17:35:08.695770 [ANA_INIT] <<<<<<<<<<<<<
7207 17:35:08.698549 [Flow] Enable top DCM control >>>>>
7208 17:35:08.702204 [Flow] Enable top DCM control <<<<<
7209 17:35:08.705327 Enable DLL master slave shuffle
7210 17:35:08.708872 ==============================================================
7211 17:35:08.711890 Gating Mode config
7212 17:35:08.718564 ==============================================================
7213 17:35:08.718979 Config description:
7214 17:35:08.728143 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7215 17:35:08.735367 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7216 17:35:08.738213 SELPH_MODE 0: By rank 1: By Phase
7217 17:35:08.745122 ==============================================================
7218 17:35:08.747986 GAT_TRACK_EN = 1
7219 17:35:08.751493 RX_GATING_MODE = 2
7220 17:35:08.755262 RX_GATING_TRACK_MODE = 2
7221 17:35:08.758014 SELPH_MODE = 1
7222 17:35:08.761457 PICG_EARLY_EN = 1
7223 17:35:08.765088 VALID_LAT_VALUE = 1
7224 17:35:08.768520 ==============================================================
7225 17:35:08.771889 Enter into Gating configuration >>>>
7226 17:35:08.774605 Exit from Gating configuration <<<<
7227 17:35:08.778107 Enter into DVFS_PRE_config >>>>>
7228 17:35:08.791857 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7229 17:35:08.792286 Exit from DVFS_PRE_config <<<<<
7230 17:35:08.794704 Enter into PICG configuration >>>>
7231 17:35:08.798341 Exit from PICG configuration <<<<
7232 17:35:08.801586 [RX_INPUT] configuration >>>>>
7233 17:35:08.804797 [RX_INPUT] configuration <<<<<
7234 17:35:08.811649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7235 17:35:08.814363 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7236 17:35:08.821132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 17:35:08.827784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 17:35:08.834077 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 17:35:08.840825 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 17:35:08.844626 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7241 17:35:08.847693 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7242 17:35:08.851121 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7243 17:35:08.857558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7244 17:35:08.861059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7245 17:35:08.864051 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 17:35:08.867490 ===================================
7247 17:35:08.870642 LPDDR4 DRAM CONFIGURATION
7248 17:35:08.874482 ===================================
7249 17:35:08.877488 EX_ROW_EN[0] = 0x0
7250 17:35:08.878068 EX_ROW_EN[1] = 0x0
7251 17:35:08.880801 LP4Y_EN = 0x0
7252 17:35:08.881390 WORK_FSP = 0x1
7253 17:35:08.883971 WL = 0x5
7254 17:35:08.884565 RL = 0x5
7255 17:35:08.887672 BL = 0x2
7256 17:35:08.888224 RPST = 0x0
7257 17:35:08.890422 RD_PRE = 0x0
7258 17:35:08.891007 WR_PRE = 0x1
7259 17:35:08.893852 WR_PST = 0x1
7260 17:35:08.894417 DBI_WR = 0x0
7261 17:35:08.897383 DBI_RD = 0x0
7262 17:35:08.897957 OTF = 0x1
7263 17:35:08.900351 ===================================
7264 17:35:08.907514 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7265 17:35:08.910392 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7266 17:35:08.913894 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 17:35:08.916807 ===================================
7268 17:35:08.920541 LPDDR4 DRAM CONFIGURATION
7269 17:35:08.923464 ===================================
7270 17:35:08.927298 EX_ROW_EN[0] = 0x10
7271 17:35:08.927625 EX_ROW_EN[1] = 0x0
7272 17:35:08.930405 LP4Y_EN = 0x0
7273 17:35:08.930702 WORK_FSP = 0x1
7274 17:35:08.933502 WL = 0x5
7275 17:35:08.933799 RL = 0x5
7276 17:35:08.936763 BL = 0x2
7277 17:35:08.937060 RPST = 0x0
7278 17:35:08.940344 RD_PRE = 0x0
7279 17:35:08.940642 WR_PRE = 0x1
7280 17:35:08.943370 WR_PST = 0x1
7281 17:35:08.943718 DBI_WR = 0x0
7282 17:35:08.946966 DBI_RD = 0x0
7283 17:35:08.947262 OTF = 0x1
7284 17:35:08.950079 ===================================
7285 17:35:08.956876 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7286 17:35:08.957190 ==
7287 17:35:08.959766 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 17:35:08.966991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 17:35:08.967294 ==
7290 17:35:08.967578 [Duty_Offset_Calibration]
7291 17:35:08.970057 B0:2 B1:0 CA:3
7292 17:35:08.970352
7293 17:35:08.973101 [DutyScan_Calibration_Flow] k_type=0
7294 17:35:08.981961
7295 17:35:08.982258 ==CLK 0==
7296 17:35:08.985541 Final CLK duty delay cell = 0
7297 17:35:08.988639 [0] MAX Duty = 5031%(X100), DQS PI = 12
7298 17:35:08.991974 [0] MIN Duty = 4907%(X100), DQS PI = 6
7299 17:35:08.995430 [0] AVG Duty = 4969%(X100)
7300 17:35:08.995736
7301 17:35:08.998773 CH0 CLK Duty spec in!! Max-Min= 124%
7302 17:35:09.002090 [DutyScan_Calibration_Flow] ====Done====
7303 17:35:09.002454
7304 17:35:09.005258 [DutyScan_Calibration_Flow] k_type=1
7305 17:35:09.021652
7306 17:35:09.021754 ==DQS 0 ==
7307 17:35:09.025151 Final DQS duty delay cell = 0
7308 17:35:09.028659 [0] MAX Duty = 5125%(X100), DQS PI = 32
7309 17:35:09.032564 [0] MIN Duty = 4875%(X100), DQS PI = 48
7310 17:35:09.035369 [0] AVG Duty = 5000%(X100)
7311 17:35:09.035474
7312 17:35:09.035537 ==DQS 1 ==
7313 17:35:09.038969 Final DQS duty delay cell = 0
7314 17:35:09.041729 [0] MAX Duty = 5156%(X100), DQS PI = 32
7315 17:35:09.045323 [0] MIN Duty = 5031%(X100), DQS PI = 14
7316 17:35:09.048273 [0] AVG Duty = 5093%(X100)
7317 17:35:09.048359
7318 17:35:09.051520 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7319 17:35:09.051613
7320 17:35:09.055169 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7321 17:35:09.058190 [DutyScan_Calibration_Flow] ====Done====
7322 17:35:09.058289
7323 17:35:09.061837 [DutyScan_Calibration_Flow] k_type=3
7324 17:35:09.079821
7325 17:35:09.079985 ==DQM 0 ==
7326 17:35:09.082826 Final DQM duty delay cell = 0
7327 17:35:09.086716 [0] MAX Duty = 5156%(X100), DQS PI = 30
7328 17:35:09.089947 [0] MIN Duty = 4875%(X100), DQS PI = 48
7329 17:35:09.093372 [0] AVG Duty = 5015%(X100)
7330 17:35:09.093661
7331 17:35:09.093919 ==DQM 1 ==
7332 17:35:09.096434 Final DQM duty delay cell = 4
7333 17:35:09.100200 [4] MAX Duty = 5156%(X100), DQS PI = 48
7334 17:35:09.103367 [4] MIN Duty = 5031%(X100), DQS PI = 12
7335 17:35:09.106358 [4] AVG Duty = 5093%(X100)
7336 17:35:09.106828
7337 17:35:09.109735 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7338 17:35:09.110128
7339 17:35:09.113594 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7340 17:35:09.116296 [DutyScan_Calibration_Flow] ====Done====
7341 17:35:09.116692
7342 17:35:09.119803 [DutyScan_Calibration_Flow] k_type=2
7343 17:35:09.136721
7344 17:35:09.137127 ==DQ 0 ==
7345 17:35:09.139730 Final DQ duty delay cell = -4
7346 17:35:09.142963 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7347 17:35:09.146766 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7348 17:35:09.149675 [-4] AVG Duty = 4938%(X100)
7349 17:35:09.150143
7350 17:35:09.150509 ==DQ 1 ==
7351 17:35:09.152854 Final DQ duty delay cell = 0
7352 17:35:09.156382 [0] MAX Duty = 5156%(X100), DQS PI = 60
7353 17:35:09.159558 [0] MIN Duty = 5000%(X100), DQS PI = 14
7354 17:35:09.162871 [0] AVG Duty = 5078%(X100)
7355 17:35:09.163197
7356 17:35:09.166113 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7357 17:35:09.166379
7358 17:35:09.169678 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7359 17:35:09.172345 [DutyScan_Calibration_Flow] ====Done====
7360 17:35:09.172610 ==
7361 17:35:09.175835 Dram Type= 6, Freq= 0, CH_1, rank 0
7362 17:35:09.179216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7363 17:35:09.179514 ==
7364 17:35:09.182432 [Duty_Offset_Calibration]
7365 17:35:09.182697 B0:1 B1:-2 CA:0
7366 17:35:09.182905
7367 17:35:09.185844 [DutyScan_Calibration_Flow] k_type=0
7368 17:35:09.196379
7369 17:35:09.196458 ==CLK 0==
7370 17:35:09.199668 Final CLK duty delay cell = 0
7371 17:35:09.203238 [0] MAX Duty = 5062%(X100), DQS PI = 20
7372 17:35:09.206830 [0] MIN Duty = 4813%(X100), DQS PI = 60
7373 17:35:09.210241 [0] AVG Duty = 4937%(X100)
7374 17:35:09.210312
7375 17:35:09.213549 CH1 CLK Duty spec in!! Max-Min= 249%
7376 17:35:09.216231 [DutyScan_Calibration_Flow] ====Done====
7377 17:35:09.216336
7378 17:35:09.219801 [DutyScan_Calibration_Flow] k_type=1
7379 17:35:09.235075
7380 17:35:09.235166 ==DQS 0 ==
7381 17:35:09.239069 Final DQS duty delay cell = -4
7382 17:35:09.242001 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7383 17:35:09.245426 [-4] MIN Duty = 4844%(X100), DQS PI = 44
7384 17:35:09.248687 [-4] AVG Duty = 4906%(X100)
7385 17:35:09.248806
7386 17:35:09.248899 ==DQS 1 ==
7387 17:35:09.252305 Final DQS duty delay cell = 0
7388 17:35:09.255725 [0] MAX Duty = 5093%(X100), DQS PI = 60
7389 17:35:09.259029 [0] MIN Duty = 4844%(X100), DQS PI = 24
7390 17:35:09.261824 [0] AVG Duty = 4968%(X100)
7391 17:35:09.262234
7392 17:35:09.265536 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7393 17:35:09.265943
7394 17:35:09.269003 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7395 17:35:09.271982 [DutyScan_Calibration_Flow] ====Done====
7396 17:35:09.272397
7397 17:35:09.275522 [DutyScan_Calibration_Flow] k_type=3
7398 17:35:09.293103
7399 17:35:09.293514 ==DQM 0 ==
7400 17:35:09.296560 Final DQM duty delay cell = 0
7401 17:35:09.299603 [0] MAX Duty = 5031%(X100), DQS PI = 24
7402 17:35:09.303223 [0] MIN Duty = 4813%(X100), DQS PI = 54
7403 17:35:09.306257 [0] AVG Duty = 4922%(X100)
7404 17:35:09.306666
7405 17:35:09.306986 ==DQM 1 ==
7406 17:35:09.309355 Final DQM duty delay cell = 0
7407 17:35:09.312989 [0] MAX Duty = 5062%(X100), DQS PI = 34
7408 17:35:09.315824 [0] MIN Duty = 4875%(X100), DQS PI = 24
7409 17:35:09.319693 [0] AVG Duty = 4968%(X100)
7410 17:35:09.320133
7411 17:35:09.322703 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7412 17:35:09.323113
7413 17:35:09.325827 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7414 17:35:09.329098 [DutyScan_Calibration_Flow] ====Done====
7415 17:35:09.329510
7416 17:35:09.332689 [DutyScan_Calibration_Flow] k_type=2
7417 17:35:09.349614
7418 17:35:09.349921 ==DQ 0 ==
7419 17:35:09.352910 Final DQ duty delay cell = 0
7420 17:35:09.356187 [0] MAX Duty = 5093%(X100), DQS PI = 22
7421 17:35:09.359261 [0] MIN Duty = 4907%(X100), DQS PI = 60
7422 17:35:09.359596 [0] AVG Duty = 5000%(X100)
7423 17:35:09.362625
7424 17:35:09.362920 ==DQ 1 ==
7425 17:35:09.366122 Final DQ duty delay cell = 0
7426 17:35:09.369766 [0] MAX Duty = 5156%(X100), DQS PI = 36
7427 17:35:09.372596 [0] MIN Duty = 4938%(X100), DQS PI = 24
7428 17:35:09.372897 [0] AVG Duty = 5047%(X100)
7429 17:35:09.376769
7430 17:35:09.379331 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7431 17:35:09.379662
7432 17:35:09.382629 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7433 17:35:09.386016 [DutyScan_Calibration_Flow] ====Done====
7434 17:35:09.389314 nWR fixed to 30
7435 17:35:09.389609 [ModeRegInit_LP4] CH0 RK0
7436 17:35:09.392567 [ModeRegInit_LP4] CH0 RK1
7437 17:35:09.396125 [ModeRegInit_LP4] CH1 RK0
7438 17:35:09.399465 [ModeRegInit_LP4] CH1 RK1
7439 17:35:09.399772 match AC timing 5
7440 17:35:09.405928 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7441 17:35:09.409002 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7442 17:35:09.412752 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7443 17:35:09.419009 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7444 17:35:09.422438 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7445 17:35:09.422731 [MiockJmeterHQA]
7446 17:35:09.422961
7447 17:35:09.425539 [DramcMiockJmeter] u1RxGatingPI = 0
7448 17:35:09.428951 0 : 4262, 4031
7449 17:35:09.429248 4 : 4255, 4029
7450 17:35:09.432470 8 : 4257, 4029
7451 17:35:09.432793 12 : 4258, 4029
7452 17:35:09.433027 16 : 4258, 4029
7453 17:35:09.435462 20 : 4257, 4032
7454 17:35:09.435761 24 : 4258, 4029
7455 17:35:09.439134 28 : 4257, 4029
7456 17:35:09.439476 32 : 4259, 4031
7457 17:35:09.442830 36 : 4255, 4029
7458 17:35:09.443128 40 : 4254, 4029
7459 17:35:09.445417 44 : 4255, 4029
7460 17:35:09.445728 48 : 4252, 4029
7461 17:35:09.445964 52 : 4368, 4142
7462 17:35:09.448748 56 : 4250, 4027
7463 17:35:09.449044 60 : 4253, 4029
7464 17:35:09.452280 64 : 4255, 4029
7465 17:35:09.452593 68 : 4250, 4026
7466 17:35:09.455230 72 : 4365, 4140
7467 17:35:09.455568 76 : 4363, 4140
7468 17:35:09.458723 80 : 4252, 4029
7469 17:35:09.459020 84 : 4253, 4029
7470 17:35:09.459257 88 : 4252, 4030
7471 17:35:09.461679 92 : 4254, 4029
7472 17:35:09.462005 96 : 4253, 4029
7473 17:35:09.465522 100 : 4252, 4030
7474 17:35:09.465824 104 : 4366, 3848
7475 17:35:09.468597 108 : 4363, 2
7476 17:35:09.468951 112 : 4250, 0
7477 17:35:09.469195 116 : 4252, 0
7478 17:35:09.471513 120 : 4255, 0
7479 17:35:09.471596 124 : 4368, 0
7480 17:35:09.474776 128 : 4252, 0
7481 17:35:09.474867 132 : 4252, 0
7482 17:35:09.474931 136 : 4257, 0
7483 17:35:09.478074 140 : 4363, 0
7484 17:35:09.478160 144 : 4253, 0
7485 17:35:09.481424 148 : 4363, 0
7486 17:35:09.481506 152 : 4252, 0
7487 17:35:09.481570 156 : 4252, 0
7488 17:35:09.485100 160 : 4363, 0
7489 17:35:09.485182 164 : 4252, 0
7490 17:35:09.488074 168 : 4252, 0
7491 17:35:09.488156 172 : 4363, 0
7492 17:35:09.488221 176 : 4363, 0
7493 17:35:09.491346 180 : 4252, 0
7494 17:35:09.491441 184 : 4252, 0
7495 17:35:09.491506 188 : 4257, 0
7496 17:35:09.494719 192 : 4252, 0
7497 17:35:09.494801 196 : 4363, 0
7498 17:35:09.498296 200 : 4363, 0
7499 17:35:09.498378 204 : 4253, 0
7500 17:35:09.498442 208 : 4252, 0
7501 17:35:09.501725 212 : 4250, 0
7502 17:35:09.501810 216 : 4257, 0
7503 17:35:09.505171 220 : 4363, 0
7504 17:35:09.505254 224 : 4255, 0
7505 17:35:09.505319 228 : 4360, 0
7506 17:35:09.508197 232 : 4253, 2
7507 17:35:09.508280 236 : 4250, 1101
7508 17:35:09.511498 240 : 4363, 4139
7509 17:35:09.511586 244 : 4252, 4029
7510 17:35:09.514564 248 : 4252, 4029
7511 17:35:09.514652 252 : 4255, 4029
7512 17:35:09.518147 256 : 4252, 4030
7513 17:35:09.518241 260 : 4363, 4140
7514 17:35:09.521454 264 : 4254, 4030
7515 17:35:09.521556 268 : 4254, 4029
7516 17:35:09.521638 272 : 4252, 4029
7517 17:35:09.524463 276 : 4252, 4030
7518 17:35:09.524565 280 : 4257, 4032
7519 17:35:09.528254 284 : 4363, 4140
7520 17:35:09.528677 288 : 4253, 4029
7521 17:35:09.531355 292 : 4252, 4029
7522 17:35:09.531826 296 : 4253, 4029
7523 17:35:09.534565 300 : 4257, 4032
7524 17:35:09.535119 304 : 4363, 4140
7525 17:35:09.538297 308 : 4252, 4030
7526 17:35:09.538718 312 : 4253, 4029
7527 17:35:09.541559 316 : 4255, 4029
7528 17:35:09.541982 320 : 4363, 4140
7529 17:35:09.544543 324 : 4361, 4138
7530 17:35:09.545024 328 : 4252, 4030
7531 17:35:09.548095 332 : 4255, 4029
7532 17:35:09.548519 336 : 4363, 4140
7533 17:35:09.548856 340 : 4365, 4139
7534 17:35:09.551274 344 : 4360, 4137
7535 17:35:09.551769 348 : 4253, 4027
7536 17:35:09.554716 352 : 4255, 4013
7537 17:35:09.555153 356 : 4253, 2871
7538 17:35:09.558446 360 : 4363, 0
7539 17:35:09.558868
7540 17:35:09.559243 MIOCK jitter meter ch=0
7541 17:35:09.559670
7542 17:35:09.561650 1T = (360-108) = 252 dly cells
7543 17:35:09.568134 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7544 17:35:09.568642 ==
7545 17:35:09.571052 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 17:35:09.574380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 17:35:09.574798 ==
7548 17:35:09.581203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7549 17:35:09.584884 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7550 17:35:09.591503 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7551 17:35:09.594616 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7552 17:35:09.604891 [CA 0] Center 44 (14~75) winsize 62
7553 17:35:09.607789 [CA 1] Center 43 (13~74) winsize 62
7554 17:35:09.611086 [CA 2] Center 40 (11~69) winsize 59
7555 17:35:09.614541 [CA 3] Center 39 (10~68) winsize 59
7556 17:35:09.617744 [CA 4] Center 37 (8~67) winsize 60
7557 17:35:09.620966 [CA 5] Center 37 (7~67) winsize 61
7558 17:35:09.621462
7559 17:35:09.624887 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7560 17:35:09.625585
7561 17:35:09.631602 [CATrainingPosCal] consider 1 rank data
7562 17:35:09.632116 u2DelayCellTimex100 = 258/100 ps
7563 17:35:09.637566 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7564 17:35:09.641015 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7565 17:35:09.644422 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7566 17:35:09.647504 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7567 17:35:09.651084 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7568 17:35:09.654321 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7569 17:35:09.654740
7570 17:35:09.657742 CA PerBit enable=1, Macro0, CA PI delay=37
7571 17:35:09.658160
7572 17:35:09.660882 [CBTSetCACLKResult] CA Dly = 37
7573 17:35:09.664252 CS Dly: 11 (0~42)
7574 17:35:09.667810 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7575 17:35:09.670646 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7576 17:35:09.671092 ==
7577 17:35:09.674329 Dram Type= 6, Freq= 0, CH_0, rank 1
7578 17:35:09.681241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 17:35:09.681680 ==
7580 17:35:09.684104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7581 17:35:09.691172 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7582 17:35:09.693793 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7583 17:35:09.700550 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7584 17:35:09.708927 [CA 0] Center 44 (14~75) winsize 62
7585 17:35:09.711782 [CA 1] Center 44 (13~75) winsize 63
7586 17:35:09.714917 [CA 2] Center 39 (10~69) winsize 60
7587 17:35:09.718258 [CA 3] Center 39 (10~69) winsize 60
7588 17:35:09.721657 [CA 4] Center 37 (8~67) winsize 60
7589 17:35:09.725024 [CA 5] Center 37 (7~67) winsize 61
7590 17:35:09.725571
7591 17:35:09.728119 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7592 17:35:09.728536
7593 17:35:09.734904 [CATrainingPosCal] consider 2 rank data
7594 17:35:09.735500 u2DelayCellTimex100 = 258/100 ps
7595 17:35:09.741839 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7596 17:35:09.744828 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7597 17:35:09.748352 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7598 17:35:09.751849 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7599 17:35:09.754966 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7600 17:35:09.758464 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7601 17:35:09.758869
7602 17:35:09.761651 CA PerBit enable=1, Macro0, CA PI delay=37
7603 17:35:09.762124
7604 17:35:09.764867 [CBTSetCACLKResult] CA Dly = 37
7605 17:35:09.768188 CS Dly: 11 (0~43)
7606 17:35:09.771507 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7607 17:35:09.774607 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7608 17:35:09.775019
7609 17:35:09.777994 ----->DramcWriteLeveling(PI) begin...
7610 17:35:09.778413 ==
7611 17:35:09.781281 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 17:35:09.788385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 17:35:09.788821 ==
7614 17:35:09.791259 Write leveling (Byte 0): 35 => 35
7615 17:35:09.794526 Write leveling (Byte 1): 28 => 28
7616 17:35:09.798189 DramcWriteLeveling(PI) end<-----
7617 17:35:09.798609
7618 17:35:09.798936 ==
7619 17:35:09.801033 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 17:35:09.804338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 17:35:09.804773 ==
7622 17:35:09.808214 [Gating] SW mode calibration
7623 17:35:09.814854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7624 17:35:09.817827 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7625 17:35:09.824301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 17:35:09.827955 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 17:35:09.830879 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 17:35:09.837646 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 17:35:09.840720 1 4 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7630 17:35:09.844123 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7631 17:35:09.851065 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 17:35:09.854511 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 17:35:09.857665 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 17:35:09.864072 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 17:35:09.867593 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 17:35:09.870784 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 17:35:09.877644 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7638 17:35:09.880743 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7639 17:35:09.884309 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7640 17:35:09.891163 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7641 17:35:09.894064 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 17:35:09.897310 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 17:35:09.904286 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 17:35:09.907153 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7645 17:35:09.910886 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7646 17:35:09.917246 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7647 17:35:09.920267 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7648 17:35:09.923777 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 17:35:09.930136 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 17:35:09.933741 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 17:35:09.936811 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 17:35:09.943311 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 17:35:09.947244 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7654 17:35:09.950135 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7655 17:35:09.956590 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7656 17:35:09.959893 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 17:35:09.963757 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 17:35:09.970489 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 17:35:09.973398 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 17:35:09.976404 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 17:35:09.983374 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 17:35:09.986436 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 17:35:09.989968 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 17:35:09.996335 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 17:35:09.999903 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 17:35:10.003006 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 17:35:10.009873 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 17:35:10.013222 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 17:35:10.016119 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7670 17:35:10.023004 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7671 17:35:10.026076 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7672 17:35:10.029602 Total UI for P1: 0, mck2ui 16
7673 17:35:10.032883 best dqsien dly found for B0: ( 1, 9, 18)
7674 17:35:10.036399 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 17:35:10.039471 Total UI for P1: 0, mck2ui 16
7676 17:35:10.043002 best dqsien dly found for B1: ( 1, 9, 24)
7677 17:35:10.045995 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7678 17:35:10.049553 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7679 17:35:10.049983
7680 17:35:10.052637 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7681 17:35:10.059310 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7682 17:35:10.059781 [Gating] SW calibration Done
7683 17:35:10.062452 ==
7684 17:35:10.065799 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 17:35:10.069005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 17:35:10.069424 ==
7687 17:35:10.069754 RX Vref Scan: 0
7688 17:35:10.070057
7689 17:35:10.072192 RX Vref 0 -> 0, step: 1
7690 17:35:10.072604
7691 17:35:10.076164 RX Delay 0 -> 252, step: 8
7692 17:35:10.079292 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7693 17:35:10.082260 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7694 17:35:10.085892 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7695 17:35:10.092795 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7696 17:35:10.095564 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7697 17:35:10.099156 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7698 17:35:10.102164 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7699 17:35:10.105345 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7700 17:35:10.111937 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7701 17:35:10.115364 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7702 17:35:10.118819 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7703 17:35:10.121880 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7704 17:35:10.128526 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7705 17:35:10.131961 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7706 17:35:10.135508 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7707 17:35:10.138599 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7708 17:35:10.139152 ==
7709 17:35:10.142090 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 17:35:10.148171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 17:35:10.148747 ==
7712 17:35:10.149238 DQS Delay:
7713 17:35:10.149703 DQS0 = 0, DQS1 = 0
7714 17:35:10.152058 DQM Delay:
7715 17:35:10.152504 DQM0 = 127, DQM1 = 123
7716 17:35:10.155150 DQ Delay:
7717 17:35:10.158537 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7718 17:35:10.161661 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7719 17:35:10.164968 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7720 17:35:10.168717 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7721 17:35:10.169273
7722 17:35:10.169604
7723 17:35:10.169965 ==
7724 17:35:10.171809 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 17:35:10.175007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 17:35:10.175494 ==
7727 17:35:10.178434
7728 17:35:10.178926
7729 17:35:10.179298 TX Vref Scan disable
7730 17:35:10.182029 == TX Byte 0 ==
7731 17:35:10.185144 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7732 17:35:10.188669 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7733 17:35:10.191572 == TX Byte 1 ==
7734 17:35:10.194698 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7735 17:35:10.198227 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7736 17:35:10.198732 ==
7737 17:35:10.201144 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 17:35:10.208224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 17:35:10.208707 ==
7740 17:35:10.221032
7741 17:35:10.223950 TX Vref early break, caculate TX vref
7742 17:35:10.227501 TX Vref=16, minBit 8, minWin=21, winSum=357
7743 17:35:10.230800 TX Vref=18, minBit 8, minWin=21, winSum=369
7744 17:35:10.233840 TX Vref=20, minBit 9, minWin=22, winSum=379
7745 17:35:10.237164 TX Vref=22, minBit 8, minWin=23, winSum=389
7746 17:35:10.240875 TX Vref=24, minBit 4, minWin=24, winSum=396
7747 17:35:10.247109 TX Vref=26, minBit 4, minWin=23, winSum=405
7748 17:35:10.250530 TX Vref=28, minBit 0, minWin=24, winSum=404
7749 17:35:10.253905 TX Vref=30, minBit 8, minWin=23, winSum=398
7750 17:35:10.257126 TX Vref=32, minBit 8, minWin=23, winSum=389
7751 17:35:10.260701 TX Vref=34, minBit 8, minWin=22, winSum=383
7752 17:35:10.267487 [TxChooseVref] Worse bit 0, Min win 24, Win sum 404, Final Vref 28
7753 17:35:10.267904
7754 17:35:10.270450 Final TX Range 0 Vref 28
7755 17:35:10.270874
7756 17:35:10.271193 ==
7757 17:35:10.274034 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 17:35:10.276929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 17:35:10.277354 ==
7760 17:35:10.277680
7761 17:35:10.278030
7762 17:35:10.280671 TX Vref Scan disable
7763 17:35:10.286599 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7764 17:35:10.287060 == TX Byte 0 ==
7765 17:35:10.290337 u2DelayCellOfst[0]=15 cells (4 PI)
7766 17:35:10.293267 u2DelayCellOfst[1]=22 cells (6 PI)
7767 17:35:10.296777 u2DelayCellOfst[2]=15 cells (4 PI)
7768 17:35:10.300370 u2DelayCellOfst[3]=15 cells (4 PI)
7769 17:35:10.303099 u2DelayCellOfst[4]=11 cells (3 PI)
7770 17:35:10.306957 u2DelayCellOfst[5]=0 cells (0 PI)
7771 17:35:10.309658 u2DelayCellOfst[6]=22 cells (6 PI)
7772 17:35:10.313479 u2DelayCellOfst[7]=22 cells (6 PI)
7773 17:35:10.316446 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7774 17:35:10.320216 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7775 17:35:10.323170 == TX Byte 1 ==
7776 17:35:10.326377 u2DelayCellOfst[8]=0 cells (0 PI)
7777 17:35:10.329626 u2DelayCellOfst[9]=0 cells (0 PI)
7778 17:35:10.330038 u2DelayCellOfst[10]=7 cells (2 PI)
7779 17:35:10.333498 u2DelayCellOfst[11]=7 cells (2 PI)
7780 17:35:10.336260 u2DelayCellOfst[12]=15 cells (4 PI)
7781 17:35:10.339906 u2DelayCellOfst[13]=11 cells (3 PI)
7782 17:35:10.343304 u2DelayCellOfst[14]=15 cells (4 PI)
7783 17:35:10.346355 u2DelayCellOfst[15]=11 cells (3 PI)
7784 17:35:10.353270 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7785 17:35:10.356128 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7786 17:35:10.356553 DramC Write-DBI on
7787 17:35:10.357010 ==
7788 17:35:10.359463 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 17:35:10.365873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 17:35:10.366287 ==
7791 17:35:10.366609
7792 17:35:10.366995
7793 17:35:10.367298 TX Vref Scan disable
7794 17:35:10.370181 == TX Byte 0 ==
7795 17:35:10.373793 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7796 17:35:10.376949 == TX Byte 1 ==
7797 17:35:10.380160 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7798 17:35:10.383633 DramC Write-DBI off
7799 17:35:10.384043
7800 17:35:10.384362 [DATLAT]
7801 17:35:10.384657 Freq=1600, CH0 RK0
7802 17:35:10.384945
7803 17:35:10.386648 DATLAT Default: 0xf
7804 17:35:10.390066 0, 0xFFFF, sum = 0
7805 17:35:10.390484 1, 0xFFFF, sum = 0
7806 17:35:10.393382 2, 0xFFFF, sum = 0
7807 17:35:10.393804 3, 0xFFFF, sum = 0
7808 17:35:10.396826 4, 0xFFFF, sum = 0
7809 17:35:10.397244 5, 0xFFFF, sum = 0
7810 17:35:10.400471 6, 0xFFFF, sum = 0
7811 17:35:10.400884 7, 0xFFFF, sum = 0
7812 17:35:10.403564 8, 0xFFFF, sum = 0
7813 17:35:10.404071 9, 0xFFFF, sum = 0
7814 17:35:10.406852 10, 0xFFFF, sum = 0
7815 17:35:10.407270 11, 0xFFFF, sum = 0
7816 17:35:10.409869 12, 0xFFFF, sum = 0
7817 17:35:10.410519 13, 0xEFFF, sum = 0
7818 17:35:10.413681 14, 0x0, sum = 1
7819 17:35:10.414099 15, 0x0, sum = 2
7820 17:35:10.416685 16, 0x0, sum = 3
7821 17:35:10.417105 17, 0x0, sum = 4
7822 17:35:10.420138 best_step = 15
7823 17:35:10.420562
7824 17:35:10.421053 ==
7825 17:35:10.423358 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 17:35:10.427071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 17:35:10.427533 ==
7828 17:35:10.429873 RX Vref Scan: 1
7829 17:35:10.430283
7830 17:35:10.430607 Set Vref Range= 24 -> 127
7831 17:35:10.430912
7832 17:35:10.433350 RX Vref 24 -> 127, step: 1
7833 17:35:10.433760
7834 17:35:10.436940 RX Delay 11 -> 252, step: 4
7835 17:35:10.437358
7836 17:35:10.439951 Set Vref, RX VrefLevel [Byte0]: 24
7837 17:35:10.443270 [Byte1]: 24
7838 17:35:10.443723
7839 17:35:10.446396 Set Vref, RX VrefLevel [Byte0]: 25
7840 17:35:10.449623 [Byte1]: 25
7841 17:35:10.453101
7842 17:35:10.453543 Set Vref, RX VrefLevel [Byte0]: 26
7843 17:35:10.456473 [Byte1]: 26
7844 17:35:10.460742
7845 17:35:10.461158 Set Vref, RX VrefLevel [Byte0]: 27
7846 17:35:10.464353 [Byte1]: 27
7847 17:35:10.468744
7848 17:35:10.469160 Set Vref, RX VrefLevel [Byte0]: 28
7849 17:35:10.471510 [Byte1]: 28
7850 17:35:10.476312
7851 17:35:10.476727 Set Vref, RX VrefLevel [Byte0]: 29
7852 17:35:10.479469 [Byte1]: 29
7853 17:35:10.483577
7854 17:35:10.483986 Set Vref, RX VrefLevel [Byte0]: 30
7855 17:35:10.487067 [Byte1]: 30
7856 17:35:10.491431
7857 17:35:10.491849 Set Vref, RX VrefLevel [Byte0]: 31
7858 17:35:10.494693 [Byte1]: 31
7859 17:35:10.499415
7860 17:35:10.500000 Set Vref, RX VrefLevel [Byte0]: 32
7861 17:35:10.502138 [Byte1]: 32
7862 17:35:10.506459
7863 17:35:10.506966 Set Vref, RX VrefLevel [Byte0]: 33
7864 17:35:10.509461 [Byte1]: 33
7865 17:35:10.514222
7866 17:35:10.514635 Set Vref, RX VrefLevel [Byte0]: 34
7867 17:35:10.517567 [Byte1]: 34
7868 17:35:10.521543
7869 17:35:10.521956 Set Vref, RX VrefLevel [Byte0]: 35
7870 17:35:10.525166 [Byte1]: 35
7871 17:35:10.529226
7872 17:35:10.529639 Set Vref, RX VrefLevel [Byte0]: 36
7873 17:35:10.536006 [Byte1]: 36
7874 17:35:10.536432
7875 17:35:10.539113 Set Vref, RX VrefLevel [Byte0]: 37
7876 17:35:10.542567 [Byte1]: 37
7877 17:35:10.543111
7878 17:35:10.545820 Set Vref, RX VrefLevel [Byte0]: 38
7879 17:35:10.548948 [Byte1]: 38
7880 17:35:10.549431
7881 17:35:10.552670 Set Vref, RX VrefLevel [Byte0]: 39
7882 17:35:10.556025 [Byte1]: 39
7883 17:35:10.559677
7884 17:35:10.560095 Set Vref, RX VrefLevel [Byte0]: 40
7885 17:35:10.563053 [Byte1]: 40
7886 17:35:10.567141
7887 17:35:10.567608 Set Vref, RX VrefLevel [Byte0]: 41
7888 17:35:10.570602 [Byte1]: 41
7889 17:35:10.575147
7890 17:35:10.575608 Set Vref, RX VrefLevel [Byte0]: 42
7891 17:35:10.578095 [Byte1]: 42
7892 17:35:10.582676
7893 17:35:10.583104 Set Vref, RX VrefLevel [Byte0]: 43
7894 17:35:10.585912 [Byte1]: 43
7895 17:35:10.590128
7896 17:35:10.590541 Set Vref, RX VrefLevel [Byte0]: 44
7897 17:35:10.593878 [Byte1]: 44
7898 17:35:10.597936
7899 17:35:10.598349 Set Vref, RX VrefLevel [Byte0]: 45
7900 17:35:10.601434 [Byte1]: 45
7901 17:35:10.605376
7902 17:35:10.605787 Set Vref, RX VrefLevel [Byte0]: 46
7903 17:35:10.608692 [Byte1]: 46
7904 17:35:10.612963
7905 17:35:10.613419 Set Vref, RX VrefLevel [Byte0]: 47
7906 17:35:10.616158 [Byte1]: 47
7907 17:35:10.620851
7908 17:35:10.621265 Set Vref, RX VrefLevel [Byte0]: 48
7909 17:35:10.623748 [Byte1]: 48
7910 17:35:10.628558
7911 17:35:10.628968 Set Vref, RX VrefLevel [Byte0]: 49
7912 17:35:10.631519 [Byte1]: 49
7913 17:35:10.635808
7914 17:35:10.636291 Set Vref, RX VrefLevel [Byte0]: 50
7915 17:35:10.638946 [Byte1]: 50
7916 17:35:10.643281
7917 17:35:10.643890 Set Vref, RX VrefLevel [Byte0]: 51
7918 17:35:10.646927 [Byte1]: 51
7919 17:35:10.651283
7920 17:35:10.651786 Set Vref, RX VrefLevel [Byte0]: 52
7921 17:35:10.654178 [Byte1]: 52
7922 17:35:10.658819
7923 17:35:10.659251 Set Vref, RX VrefLevel [Byte0]: 53
7924 17:35:10.662114 [Byte1]: 53
7925 17:35:10.666277
7926 17:35:10.666699 Set Vref, RX VrefLevel [Byte0]: 54
7927 17:35:10.669611 [Byte1]: 54
7928 17:35:10.673815
7929 17:35:10.674226 Set Vref, RX VrefLevel [Byte0]: 55
7930 17:35:10.677603 [Byte1]: 55
7931 17:35:10.681537
7932 17:35:10.681948 Set Vref, RX VrefLevel [Byte0]: 56
7933 17:35:10.684990 [Byte1]: 56
7934 17:35:10.689230
7935 17:35:10.689642 Set Vref, RX VrefLevel [Byte0]: 57
7936 17:35:10.692387 [Byte1]: 57
7937 17:35:10.696571
7938 17:35:10.696983 Set Vref, RX VrefLevel [Byte0]: 58
7939 17:35:10.700051 [Byte1]: 58
7940 17:35:10.704444
7941 17:35:10.704856 Set Vref, RX VrefLevel [Byte0]: 59
7942 17:35:10.707718 [Byte1]: 59
7943 17:35:10.711803
7944 17:35:10.712200 Set Vref, RX VrefLevel [Byte0]: 60
7945 17:35:10.715148 [Byte1]: 60
7946 17:35:10.719566
7947 17:35:10.719860 Set Vref, RX VrefLevel [Byte0]: 61
7948 17:35:10.722484 [Byte1]: 61
7949 17:35:10.726897
7950 17:35:10.727119 Set Vref, RX VrefLevel [Byte0]: 62
7951 17:35:10.730281 [Byte1]: 62
7952 17:35:10.734806
7953 17:35:10.735028 Set Vref, RX VrefLevel [Byte0]: 63
7954 17:35:10.737837 [Byte1]: 63
7955 17:35:10.741924
7956 17:35:10.742146 Set Vref, RX VrefLevel [Byte0]: 64
7957 17:35:10.745563 [Byte1]: 64
7958 17:35:10.750200
7959 17:35:10.750421 Set Vref, RX VrefLevel [Byte0]: 65
7960 17:35:10.753284 [Byte1]: 65
7961 17:35:10.757450
7962 17:35:10.757689 Set Vref, RX VrefLevel [Byte0]: 66
7963 17:35:10.760673 [Byte1]: 66
7964 17:35:10.765408
7965 17:35:10.765724 Set Vref, RX VrefLevel [Byte0]: 67
7966 17:35:10.768551 [Byte1]: 67
7967 17:35:10.772509
7968 17:35:10.772746 Set Vref, RX VrefLevel [Byte0]: 68
7969 17:35:10.775691 [Byte1]: 68
7970 17:35:10.780624
7971 17:35:10.780935 Set Vref, RX VrefLevel [Byte0]: 69
7972 17:35:10.783566 [Byte1]: 69
7973 17:35:10.788156
7974 17:35:10.788395 Set Vref, RX VrefLevel [Byte0]: 70
7975 17:35:10.790951 [Byte1]: 70
7976 17:35:10.795368
7977 17:35:10.795615 Set Vref, RX VrefLevel [Byte0]: 71
7978 17:35:10.799070 [Byte1]: 71
7979 17:35:10.802987
7980 17:35:10.803214 Set Vref, RX VrefLevel [Byte0]: 72
7981 17:35:10.806266 [Byte1]: 72
7982 17:35:10.811019
7983 17:35:10.811325 Set Vref, RX VrefLevel [Byte0]: 73
7984 17:35:10.814329 [Byte1]: 73
7985 17:35:10.818560
7986 17:35:10.818800 Set Vref, RX VrefLevel [Byte0]: 74
7987 17:35:10.821461 [Byte1]: 74
7988 17:35:10.826199
7989 17:35:10.826512 Set Vref, RX VrefLevel [Byte0]: 75
7990 17:35:10.829128 [Byte1]: 75
7991 17:35:10.833646
7992 17:35:10.833885 Final RX Vref Byte 0 = 63 to rank0
7993 17:35:10.836919 Final RX Vref Byte 1 = 59 to rank0
7994 17:35:10.840704 Final RX Vref Byte 0 = 63 to rank1
7995 17:35:10.843770 Final RX Vref Byte 1 = 59 to rank1==
7996 17:35:10.846703 Dram Type= 6, Freq= 0, CH_0, rank 0
7997 17:35:10.853555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 17:35:10.853798 ==
7999 17:35:10.853999 DQS Delay:
8000 17:35:10.854195 DQS0 = 0, DQS1 = 0
8001 17:35:10.856621 DQM Delay:
8002 17:35:10.856864 DQM0 = 126, DQM1 = 119
8003 17:35:10.860177 DQ Delay:
8004 17:35:10.863378 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8005 17:35:10.866458 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8006 17:35:10.870165 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8007 17:35:10.872988 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8008 17:35:10.873068
8009 17:35:10.873139
8010 17:35:10.873214
8011 17:35:10.876187 [DramC_TX_OE_Calibration] TA2
8012 17:35:10.879634 Original DQ_B0 (3 6) =30, OEN = 27
8013 17:35:10.883095 Original DQ_B1 (3 6) =30, OEN = 27
8014 17:35:10.886512 24, 0x0, End_B0=24 End_B1=24
8015 17:35:10.886611 25, 0x0, End_B0=25 End_B1=25
8016 17:35:10.889865 26, 0x0, End_B0=26 End_B1=26
8017 17:35:10.893062 27, 0x0, End_B0=27 End_B1=27
8018 17:35:10.896232 28, 0x0, End_B0=28 End_B1=28
8019 17:35:10.899507 29, 0x0, End_B0=29 End_B1=29
8020 17:35:10.899601 30, 0x0, End_B0=30 End_B1=30
8021 17:35:10.903164 31, 0x4141, End_B0=30 End_B1=30
8022 17:35:10.905968 Byte0 end_step=30 best_step=27
8023 17:35:10.909405 Byte1 end_step=30 best_step=27
8024 17:35:10.912800 Byte0 TX OE(2T, 0.5T) = (3, 3)
8025 17:35:10.916310 Byte1 TX OE(2T, 0.5T) = (3, 3)
8026 17:35:10.916486
8027 17:35:10.916634
8028 17:35:10.922966 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8029 17:35:10.926169 CH0 RK0: MR19=303, MR18=1313
8030 17:35:10.932664 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
8031 17:35:10.932875
8032 17:35:10.936395 ----->DramcWriteLeveling(PI) begin...
8033 17:35:10.936635 ==
8034 17:35:10.939273 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 17:35:10.943194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 17:35:10.943519 ==
8037 17:35:10.946087 Write leveling (Byte 0): 34 => 34
8038 17:35:10.949654 Write leveling (Byte 1): 26 => 26
8039 17:35:10.952605 DramcWriteLeveling(PI) end<-----
8040 17:35:10.953063
8041 17:35:10.953424 ==
8042 17:35:10.956352 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 17:35:10.959846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 17:35:10.960264 ==
8045 17:35:10.962984 [Gating] SW mode calibration
8046 17:35:10.969545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8047 17:35:10.975979 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8048 17:35:10.979382 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 17:35:10.985893 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 17:35:10.989038 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 17:35:10.992594 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8052 17:35:10.998906 1 4 16 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
8053 17:35:11.002361 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 17:35:11.005626 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 17:35:11.012392 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 17:35:11.015350 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 17:35:11.019029 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 17:35:11.025242 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8059 17:35:11.028745 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8060 17:35:11.031838 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8061 17:35:11.038680 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8062 17:35:11.042432 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 17:35:11.045544 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 17:35:11.052031 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 17:35:11.055209 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 17:35:11.058861 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8067 17:35:11.065148 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8068 17:35:11.068698 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8069 17:35:11.071871 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8070 17:35:11.078432 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 17:35:11.082097 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 17:35:11.085182 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 17:35:11.091857 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 17:35:11.095038 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8075 17:35:11.098065 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8076 17:35:11.104889 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8077 17:35:11.108442 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8078 17:35:11.111777 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 17:35:11.114838 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 17:35:11.121478 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 17:35:11.125171 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 17:35:11.128127 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 17:35:11.134844 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 17:35:11.137814 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 17:35:11.141260 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 17:35:11.148112 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 17:35:11.151255 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 17:35:11.154380 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 17:35:11.161029 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8090 17:35:11.164161 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8091 17:35:11.168018 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8092 17:35:11.171123 Total UI for P1: 0, mck2ui 16
8093 17:35:11.174170 best dqsien dly found for B0: ( 1, 9, 6)
8094 17:35:11.181010 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8095 17:35:11.184577 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 17:35:11.187663 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 17:35:11.190691 Total UI for P1: 0, mck2ui 16
8098 17:35:11.194159 best dqsien dly found for B1: ( 1, 9, 18)
8099 17:35:11.197576 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8100 17:35:11.200897 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8101 17:35:11.204088
8102 17:35:11.207198 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8103 17:35:11.210761 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8104 17:35:11.213680 [Gating] SW calibration Done
8105 17:35:11.214277 ==
8106 17:35:11.217351 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 17:35:11.220443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 17:35:11.220881 ==
8109 17:35:11.221240 RX Vref Scan: 0
8110 17:35:11.224133
8111 17:35:11.224577 RX Vref 0 -> 0, step: 1
8112 17:35:11.225100
8113 17:35:11.227448 RX Delay 0 -> 252, step: 8
8114 17:35:11.230339 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8115 17:35:11.233501 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8116 17:35:11.240241 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8117 17:35:11.243830 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8118 17:35:11.246844 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8119 17:35:11.250510 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8120 17:35:11.253702 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8121 17:35:11.260390 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8122 17:35:11.263797 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8123 17:35:11.267063 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8124 17:35:11.270472 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8125 17:35:11.273687 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8126 17:35:11.280544 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8127 17:35:11.283339 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8128 17:35:11.286738 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8129 17:35:11.289980 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8130 17:35:11.290394 ==
8131 17:35:11.293552 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 17:35:11.300388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 17:35:11.300804 ==
8134 17:35:11.301217 DQS Delay:
8135 17:35:11.303176 DQS0 = 0, DQS1 = 0
8136 17:35:11.303677 DQM Delay:
8137 17:35:11.304067 DQM0 = 128, DQM1 = 121
8138 17:35:11.306720 DQ Delay:
8139 17:35:11.310159 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8140 17:35:11.313139 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8141 17:35:11.316573 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8142 17:35:11.319890 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8143 17:35:11.320302
8144 17:35:11.320625
8145 17:35:11.320927 ==
8146 17:35:11.323502 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 17:35:11.326472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 17:35:11.330409 ==
8149 17:35:11.330825
8150 17:35:11.331150
8151 17:35:11.331503 TX Vref Scan disable
8152 17:35:11.333752 == TX Byte 0 ==
8153 17:35:11.336668 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8154 17:35:11.340166 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8155 17:35:11.343347 == TX Byte 1 ==
8156 17:35:11.346511 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8157 17:35:11.349687 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8158 17:35:11.353667 ==
8159 17:35:11.356420 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 17:35:11.359629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 17:35:11.360202 ==
8162 17:35:11.372649
8163 17:35:11.376347 TX Vref early break, caculate TX vref
8164 17:35:11.379520 TX Vref=16, minBit 0, minWin=22, winSum=368
8165 17:35:11.383249 TX Vref=18, minBit 9, minWin=22, winSum=374
8166 17:35:11.385993 TX Vref=20, minBit 8, minWin=22, winSum=382
8167 17:35:11.389437 TX Vref=22, minBit 2, minWin=23, winSum=393
8168 17:35:11.393087 TX Vref=24, minBit 0, minWin=24, winSum=398
8169 17:35:11.399293 TX Vref=26, minBit 1, minWin=25, winSum=409
8170 17:35:11.402906 TX Vref=28, minBit 13, minWin=24, winSum=408
8171 17:35:11.405843 TX Vref=30, minBit 9, minWin=24, winSum=405
8172 17:35:11.409356 TX Vref=32, minBit 8, minWin=23, winSum=397
8173 17:35:11.412577 TX Vref=34, minBit 8, minWin=23, winSum=387
8174 17:35:11.419595 [TxChooseVref] Worse bit 1, Min win 25, Win sum 409, Final Vref 26
8175 17:35:11.420013
8176 17:35:11.422589 Final TX Range 0 Vref 26
8177 17:35:11.423019
8178 17:35:11.423505 ==
8179 17:35:11.426043 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 17:35:11.429139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 17:35:11.429698 ==
8182 17:35:11.430182
8183 17:35:11.430660
8184 17:35:11.432399 TX Vref Scan disable
8185 17:35:11.439089 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8186 17:35:11.439672 == TX Byte 0 ==
8187 17:35:11.442764 u2DelayCellOfst[0]=11 cells (3 PI)
8188 17:35:11.445934 u2DelayCellOfst[1]=18 cells (5 PI)
8189 17:35:11.448997 u2DelayCellOfst[2]=11 cells (3 PI)
8190 17:35:11.452387 u2DelayCellOfst[3]=11 cells (3 PI)
8191 17:35:11.455811 u2DelayCellOfst[4]=7 cells (2 PI)
8192 17:35:11.459297 u2DelayCellOfst[5]=0 cells (0 PI)
8193 17:35:11.462215 u2DelayCellOfst[6]=18 cells (5 PI)
8194 17:35:11.465309 u2DelayCellOfst[7]=18 cells (5 PI)
8195 17:35:11.468844 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8196 17:35:11.472015 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8197 17:35:11.475101 == TX Byte 1 ==
8198 17:35:11.478292 u2DelayCellOfst[8]=0 cells (0 PI)
8199 17:35:11.482042 u2DelayCellOfst[9]=0 cells (0 PI)
8200 17:35:11.482440 u2DelayCellOfst[10]=7 cells (2 PI)
8201 17:35:11.484823 u2DelayCellOfst[11]=7 cells (2 PI)
8202 17:35:11.488603 u2DelayCellOfst[12]=11 cells (3 PI)
8203 17:35:11.492109 u2DelayCellOfst[13]=11 cells (3 PI)
8204 17:35:11.495220 u2DelayCellOfst[14]=15 cells (4 PI)
8205 17:35:11.498568 u2DelayCellOfst[15]=11 cells (3 PI)
8206 17:35:11.505407 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8207 17:35:11.508020 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8208 17:35:11.508382 DramC Write-DBI on
8209 17:35:11.508706 ==
8210 17:35:11.511828 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 17:35:11.518018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 17:35:11.518437 ==
8213 17:35:11.518704
8214 17:35:11.518936
8215 17:35:11.519162 TX Vref Scan disable
8216 17:35:11.522575 == TX Byte 0 ==
8217 17:35:11.525713 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8218 17:35:11.529477 == TX Byte 1 ==
8219 17:35:11.532398 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8220 17:35:11.535691 DramC Write-DBI off
8221 17:35:11.535981
8222 17:35:11.536208 [DATLAT]
8223 17:35:11.536421 Freq=1600, CH0 RK1
8224 17:35:11.536630
8225 17:35:11.538823 DATLAT Default: 0xf
8226 17:35:11.539129 0, 0xFFFF, sum = 0
8227 17:35:11.542512 1, 0xFFFF, sum = 0
8228 17:35:11.545783 2, 0xFFFF, sum = 0
8229 17:35:11.546096 3, 0xFFFF, sum = 0
8230 17:35:11.549332 4, 0xFFFF, sum = 0
8231 17:35:11.549654 5, 0xFFFF, sum = 0
8232 17:35:11.552344 6, 0xFFFF, sum = 0
8233 17:35:11.552656 7, 0xFFFF, sum = 0
8234 17:35:11.555479 8, 0xFFFF, sum = 0
8235 17:35:11.555795 9, 0xFFFF, sum = 0
8236 17:35:11.559000 10, 0xFFFF, sum = 0
8237 17:35:11.559312 11, 0xFFFF, sum = 0
8238 17:35:11.562105 12, 0xFFFF, sum = 0
8239 17:35:11.562417 13, 0xCFFF, sum = 0
8240 17:35:11.565503 14, 0x0, sum = 1
8241 17:35:11.565814 15, 0x0, sum = 2
8242 17:35:11.568916 16, 0x0, sum = 3
8243 17:35:11.569227 17, 0x0, sum = 4
8244 17:35:11.571873 best_step = 15
8245 17:35:11.572181
8246 17:35:11.572353 ==
8247 17:35:11.575319 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 17:35:11.578736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 17:35:11.578820 ==
8250 17:35:11.581863 RX Vref Scan: 0
8251 17:35:11.581946
8252 17:35:11.582031 RX Vref 0 -> 0, step: 1
8253 17:35:11.582111
8254 17:35:11.585134 RX Delay 3 -> 252, step: 4
8255 17:35:11.588778 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8256 17:35:11.595029 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8257 17:35:11.598549 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8258 17:35:11.601506 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8259 17:35:11.604811 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8260 17:35:11.608617 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8261 17:35:11.615311 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8262 17:35:11.619115 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8263 17:35:11.621925 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8264 17:35:11.625131 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8265 17:35:11.628487 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8266 17:35:11.635747 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8267 17:35:11.638723 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8268 17:35:11.641547 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8269 17:35:11.645169 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8270 17:35:11.648655 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8271 17:35:11.652069 ==
8272 17:35:11.655049 Dram Type= 6, Freq= 0, CH_0, rank 1
8273 17:35:11.658435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 17:35:11.658513 ==
8275 17:35:11.658600 DQS Delay:
8276 17:35:11.661403 DQS0 = 0, DQS1 = 0
8277 17:35:11.661487 DQM Delay:
8278 17:35:11.665298 DQM0 = 124, DQM1 = 118
8279 17:35:11.665381 DQ Delay:
8280 17:35:11.668387 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8281 17:35:11.671266 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8282 17:35:11.675213 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8283 17:35:11.678020 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8284 17:35:11.678104
8285 17:35:11.678257
8286 17:35:11.678337
8287 17:35:11.681700 [DramC_TX_OE_Calibration] TA2
8288 17:35:11.684493 Original DQ_B0 (3 6) =30, OEN = 27
8289 17:35:11.687770 Original DQ_B1 (3 6) =30, OEN = 27
8290 17:35:11.691715 24, 0x0, End_B0=24 End_B1=24
8291 17:35:11.694848 25, 0x0, End_B0=25 End_B1=25
8292 17:35:11.694930 26, 0x0, End_B0=26 End_B1=26
8293 17:35:11.698283 27, 0x0, End_B0=27 End_B1=27
8294 17:35:11.701302 28, 0x0, End_B0=28 End_B1=28
8295 17:35:11.704468 29, 0x0, End_B0=29 End_B1=29
8296 17:35:11.708163 30, 0x0, End_B0=30 End_B1=30
8297 17:35:11.708247 31, 0x4141, End_B0=30 End_B1=30
8298 17:35:11.711302 Byte0 end_step=30 best_step=27
8299 17:35:11.715087 Byte1 end_step=30 best_step=27
8300 17:35:11.718432 Byte0 TX OE(2T, 0.5T) = (3, 3)
8301 17:35:11.721994 Byte1 TX OE(2T, 0.5T) = (3, 3)
8302 17:35:11.722078
8303 17:35:11.722163
8304 17:35:11.727908 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8305 17:35:11.731798 CH0 RK1: MR19=303, MR18=2210
8306 17:35:11.738053 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8307 17:35:11.741237 [RxdqsGatingPostProcess] freq 1600
8308 17:35:11.747841 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8309 17:35:11.747936 best DQS0 dly(2T, 0.5T) = (1, 1)
8310 17:35:11.751351 best DQS1 dly(2T, 0.5T) = (1, 1)
8311 17:35:11.754410 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8312 17:35:11.757845 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8313 17:35:11.761291 best DQS0 dly(2T, 0.5T) = (1, 1)
8314 17:35:11.764266 best DQS1 dly(2T, 0.5T) = (1, 1)
8315 17:35:11.767952 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8316 17:35:11.771174 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8317 17:35:11.774641 Pre-setting of DQS Precalculation
8318 17:35:11.777878 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8319 17:35:11.777975 ==
8320 17:35:11.781312 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 17:35:11.787622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 17:35:11.787725 ==
8323 17:35:11.790890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 17:35:11.797400 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 17:35:11.800736 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 17:35:11.807374 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 17:35:11.815420 [CA 0] Center 42 (13~71) winsize 59
8328 17:35:11.818367 [CA 1] Center 42 (12~72) winsize 61
8329 17:35:11.821551 [CA 2] Center 38 (9~67) winsize 59
8330 17:35:11.825316 [CA 3] Center 37 (8~66) winsize 59
8331 17:35:11.828558 [CA 4] Center 37 (8~67) winsize 60
8332 17:35:11.832328 [CA 5] Center 36 (7~66) winsize 60
8333 17:35:11.832446
8334 17:35:11.835158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8335 17:35:11.835234
8336 17:35:11.838243 [CATrainingPosCal] consider 1 rank data
8337 17:35:11.841770 u2DelayCellTimex100 = 258/100 ps
8338 17:35:11.845590 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8339 17:35:11.851773 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8340 17:35:11.855189 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8341 17:35:11.858551 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8342 17:35:11.861898 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8343 17:35:11.865047 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8344 17:35:11.865126
8345 17:35:11.868372 CA PerBit enable=1, Macro0, CA PI delay=36
8346 17:35:11.868462
8347 17:35:11.871448 [CBTSetCACLKResult] CA Dly = 36
8348 17:35:11.874857 CS Dly: 9 (0~40)
8349 17:35:11.877996 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 17:35:11.881271 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 17:35:11.881356 ==
8352 17:35:11.885004 Dram Type= 6, Freq= 0, CH_1, rank 1
8353 17:35:11.888429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 17:35:11.891648 ==
8355 17:35:11.895315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8356 17:35:11.898087 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8357 17:35:11.904929 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8358 17:35:11.911640 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8359 17:35:11.918515 [CA 0] Center 41 (12~71) winsize 60
8360 17:35:11.921595 [CA 1] Center 42 (12~72) winsize 61
8361 17:35:11.925242 [CA 2] Center 38 (9~67) winsize 59
8362 17:35:11.928232 [CA 3] Center 36 (7~66) winsize 60
8363 17:35:11.931725 [CA 4] Center 38 (8~68) winsize 61
8364 17:35:11.934875 [CA 5] Center 36 (6~66) winsize 61
8365 17:35:11.934967
8366 17:35:11.938867 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8367 17:35:11.938947
8368 17:35:11.941606 [CATrainingPosCal] consider 2 rank data
8369 17:35:11.944879 u2DelayCellTimex100 = 258/100 ps
8370 17:35:11.951332 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8371 17:35:11.955143 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8372 17:35:11.958161 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8373 17:35:11.961724 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8374 17:35:11.964780 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8375 17:35:11.967855 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8376 17:35:11.967946
8377 17:35:11.971358 CA PerBit enable=1, Macro0, CA PI delay=36
8378 17:35:11.971483
8379 17:35:11.974566 [CBTSetCACLKResult] CA Dly = 36
8380 17:35:11.977973 CS Dly: 10 (0~43)
8381 17:35:11.981071 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8382 17:35:11.984792 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8383 17:35:11.984878
8384 17:35:11.988118 ----->DramcWriteLeveling(PI) begin...
8385 17:35:11.988198 ==
8386 17:35:11.991381 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 17:35:11.997883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 17:35:11.997965 ==
8389 17:35:12.001299 Write leveling (Byte 0): 25 => 25
8390 17:35:12.004454 Write leveling (Byte 1): 26 => 26
8391 17:35:12.004534 DramcWriteLeveling(PI) end<-----
8392 17:35:12.004597
8393 17:35:12.008010 ==
8394 17:35:12.011130 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 17:35:12.014628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 17:35:12.014708 ==
8397 17:35:12.017693 [Gating] SW mode calibration
8398 17:35:12.024116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8399 17:35:12.027605 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8400 17:35:12.034387 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 17:35:12.037398 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 17:35:12.040850 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 17:35:12.047855 1 4 12 | B1->B0 | 2524 2323 | 1 0 | (1 0) (0 0)
8404 17:35:12.050625 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8405 17:35:12.053664 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 17:35:12.060876 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 17:35:12.063835 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 17:35:12.067509 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 17:35:12.073854 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 17:35:12.077140 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 17:35:12.080294 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 17:35:12.087261 1 5 16 | B1->B0 | 2525 2626 | 0 0 | (0 1) (0 1)
8413 17:35:12.090345 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 17:35:12.093914 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 17:35:12.100127 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 17:35:12.103293 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 17:35:12.106716 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 17:35:12.113470 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 17:35:12.116583 1 6 12 | B1->B0 | 2f2f 2525 | 1 0 | (0 0) (0 0)
8420 17:35:12.120019 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 17:35:12.126721 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 17:35:12.129729 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 17:35:12.133757 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 17:35:12.140345 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 17:35:12.143309 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 17:35:12.146885 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 17:35:12.153587 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 17:35:12.156699 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8429 17:35:12.159856 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8430 17:35:12.167203 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 17:35:12.169975 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 17:35:12.174042 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 17:35:12.180342 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 17:35:12.183445 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 17:35:12.186827 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 17:35:12.193305 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 17:35:12.196623 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 17:35:12.199697 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 17:35:12.206993 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 17:35:12.210082 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 17:35:12.213037 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 17:35:12.216855 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 17:35:12.222831 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8444 17:35:12.226243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8445 17:35:12.229407 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 17:35:12.232930 Total UI for P1: 0, mck2ui 16
8447 17:35:12.235907 best dqsien dly found for B0: ( 1, 9, 16)
8448 17:35:12.239371 Total UI for P1: 0, mck2ui 16
8449 17:35:12.242531 best dqsien dly found for B1: ( 1, 9, 14)
8450 17:35:12.245965 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8451 17:35:12.252418 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8452 17:35:12.252528
8453 17:35:12.255888 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8454 17:35:12.259606 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8455 17:35:12.262709 [Gating] SW calibration Done
8456 17:35:12.262927 ==
8457 17:35:12.265869 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 17:35:12.269292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 17:35:12.269402 ==
8460 17:35:12.272261 RX Vref Scan: 0
8461 17:35:12.272374
8462 17:35:12.272462 RX Vref 0 -> 0, step: 1
8463 17:35:12.272545
8464 17:35:12.275504 RX Delay 0 -> 252, step: 8
8465 17:35:12.279132 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8466 17:35:12.282418 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8467 17:35:12.288769 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8468 17:35:12.292439 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8469 17:35:12.295637 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8470 17:35:12.298858 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8471 17:35:12.302236 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8472 17:35:12.309249 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8473 17:35:12.312330 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8474 17:35:12.315720 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8475 17:35:12.319060 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8476 17:35:12.322663 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8477 17:35:12.329256 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8478 17:35:12.332037 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8479 17:35:12.335461 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8480 17:35:12.338784 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8481 17:35:12.339362 ==
8482 17:35:12.342165 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 17:35:12.349017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 17:35:12.349632 ==
8485 17:35:12.350216 DQS Delay:
8486 17:35:12.352522 DQS0 = 0, DQS1 = 0
8487 17:35:12.353132 DQM Delay:
8488 17:35:12.355533 DQM0 = 132, DQM1 = 126
8489 17:35:12.356143 DQ Delay:
8490 17:35:12.358562 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8491 17:35:12.365441 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8492 17:35:12.365893 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8493 17:35:12.368657 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8494 17:35:12.369269
8495 17:35:12.369686
8496 17:35:12.370044 ==
8497 17:35:12.371911 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 17:35:12.378410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 17:35:12.378895 ==
8500 17:35:12.379255
8501 17:35:12.379638
8502 17:35:12.379963 TX Vref Scan disable
8503 17:35:12.381709 == TX Byte 0 ==
8504 17:35:12.385447 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8505 17:35:12.392367 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8506 17:35:12.392834 == TX Byte 1 ==
8507 17:35:12.395185 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8508 17:35:12.401815 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8509 17:35:12.402423 ==
8510 17:35:12.404932 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 17:35:12.408585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 17:35:12.409101 ==
8513 17:35:12.421882
8514 17:35:12.425577 TX Vref early break, caculate TX vref
8515 17:35:12.428683 TX Vref=16, minBit 1, minWin=22, winSum=364
8516 17:35:12.432344 TX Vref=18, minBit 5, minWin=22, winSum=374
8517 17:35:12.435057 TX Vref=20, minBit 0, minWin=23, winSum=380
8518 17:35:12.438952 TX Vref=22, minBit 0, minWin=24, winSum=391
8519 17:35:12.441744 TX Vref=24, minBit 1, minWin=24, winSum=400
8520 17:35:12.448127 TX Vref=26, minBit 0, minWin=25, winSum=412
8521 17:35:12.451668 TX Vref=28, minBit 6, minWin=24, winSum=417
8522 17:35:12.455186 TX Vref=30, minBit 6, minWin=24, winSum=416
8523 17:35:12.458457 TX Vref=32, minBit 0, minWin=24, winSum=404
8524 17:35:12.461289 TX Vref=34, minBit 0, minWin=23, winSum=401
8525 17:35:12.468188 TX Vref=36, minBit 6, minWin=22, winSum=383
8526 17:35:12.471155 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 26
8527 17:35:12.471619
8528 17:35:12.474611 Final TX Range 0 Vref 26
8529 17:35:12.475021
8530 17:35:12.475343 ==
8531 17:35:12.477834 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 17:35:12.481015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 17:35:12.484357 ==
8534 17:35:12.484766
8535 17:35:12.485137
8536 17:35:12.485451 TX Vref Scan disable
8537 17:35:12.491371 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8538 17:35:12.491895 == TX Byte 0 ==
8539 17:35:12.494209 u2DelayCellOfst[0]=18 cells (5 PI)
8540 17:35:12.497909 u2DelayCellOfst[1]=11 cells (3 PI)
8541 17:35:12.501336 u2DelayCellOfst[2]=0 cells (0 PI)
8542 17:35:12.504338 u2DelayCellOfst[3]=3 cells (1 PI)
8543 17:35:12.507947 u2DelayCellOfst[4]=7 cells (2 PI)
8544 17:35:12.511001 u2DelayCellOfst[5]=18 cells (5 PI)
8545 17:35:12.514047 u2DelayCellOfst[6]=18 cells (5 PI)
8546 17:35:12.517738 u2DelayCellOfst[7]=3 cells (1 PI)
8547 17:35:12.520670 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8548 17:35:12.524414 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8549 17:35:12.527351 == TX Byte 1 ==
8550 17:35:12.531141 u2DelayCellOfst[8]=0 cells (0 PI)
8551 17:35:12.534165 u2DelayCellOfst[9]=7 cells (2 PI)
8552 17:35:12.537808 u2DelayCellOfst[10]=11 cells (3 PI)
8553 17:35:12.540924 u2DelayCellOfst[11]=7 cells (2 PI)
8554 17:35:12.544129 u2DelayCellOfst[12]=15 cells (4 PI)
8555 17:35:12.546963 u2DelayCellOfst[13]=18 cells (5 PI)
8556 17:35:12.550552 u2DelayCellOfst[14]=18 cells (5 PI)
8557 17:35:12.550968 u2DelayCellOfst[15]=18 cells (5 PI)
8558 17:35:12.557245 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8559 17:35:12.560161 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8560 17:35:12.563975 DramC Write-DBI on
8561 17:35:12.564399 ==
8562 17:35:12.567254 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 17:35:12.570978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 17:35:12.571561 ==
8565 17:35:12.572057
8566 17:35:12.572517
8567 17:35:12.574198 TX Vref Scan disable
8568 17:35:12.574744 == TX Byte 0 ==
8569 17:35:12.580326 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8570 17:35:12.580772 == TX Byte 1 ==
8571 17:35:12.583713 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8572 17:35:12.586667 DramC Write-DBI off
8573 17:35:12.587260
8574 17:35:12.587842 [DATLAT]
8575 17:35:12.590202 Freq=1600, CH1 RK0
8576 17:35:12.590775
8577 17:35:12.591295 DATLAT Default: 0xf
8578 17:35:12.593321 0, 0xFFFF, sum = 0
8579 17:35:12.593739 1, 0xFFFF, sum = 0
8580 17:35:12.597093 2, 0xFFFF, sum = 0
8581 17:35:12.597640 3, 0xFFFF, sum = 0
8582 17:35:12.599911 4, 0xFFFF, sum = 0
8583 17:35:12.603466 5, 0xFFFF, sum = 0
8584 17:35:12.603910 6, 0xFFFF, sum = 0
8585 17:35:12.606945 7, 0xFFFF, sum = 0
8586 17:35:12.607459 8, 0xFFFF, sum = 0
8587 17:35:12.610142 9, 0xFFFF, sum = 0
8588 17:35:12.610650 10, 0xFFFF, sum = 0
8589 17:35:12.613457 11, 0xFFFF, sum = 0
8590 17:35:12.614047 12, 0xFFFF, sum = 0
8591 17:35:12.616662 13, 0x8FFF, sum = 0
8592 17:35:12.617083 14, 0x0, sum = 1
8593 17:35:12.619629 15, 0x0, sum = 2
8594 17:35:12.620054 16, 0x0, sum = 3
8595 17:35:12.623343 17, 0x0, sum = 4
8596 17:35:12.623804 best_step = 15
8597 17:35:12.624132
8598 17:35:12.624451 ==
8599 17:35:12.626376 Dram Type= 6, Freq= 0, CH_1, rank 0
8600 17:35:12.630052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8601 17:35:12.633293 ==
8602 17:35:12.633707 RX Vref Scan: 1
8603 17:35:12.634032
8604 17:35:12.636528 Set Vref Range= 24 -> 127
8605 17:35:12.637037
8606 17:35:12.639537 RX Vref 24 -> 127, step: 1
8607 17:35:12.639959
8608 17:35:12.640363 RX Delay 11 -> 252, step: 4
8609 17:35:12.640873
8610 17:35:12.643346 Set Vref, RX VrefLevel [Byte0]: 24
8611 17:35:12.646643 [Byte1]: 24
8612 17:35:12.650444
8613 17:35:12.650859 Set Vref, RX VrefLevel [Byte0]: 25
8614 17:35:12.653851 [Byte1]: 25
8615 17:35:12.658252
8616 17:35:12.658769 Set Vref, RX VrefLevel [Byte0]: 26
8617 17:35:12.661007 [Byte1]: 26
8618 17:35:12.665240
8619 17:35:12.665688 Set Vref, RX VrefLevel [Byte0]: 27
8620 17:35:12.669030 [Byte1]: 27
8621 17:35:12.672856
8622 17:35:12.673284 Set Vref, RX VrefLevel [Byte0]: 28
8623 17:35:12.676543 [Byte1]: 28
8624 17:35:12.680572
8625 17:35:12.681067 Set Vref, RX VrefLevel [Byte0]: 29
8626 17:35:12.684093 [Byte1]: 29
8627 17:35:12.688235
8628 17:35:12.688651 Set Vref, RX VrefLevel [Byte0]: 30
8629 17:35:12.691827 [Byte1]: 30
8630 17:35:12.695922
8631 17:35:12.696437 Set Vref, RX VrefLevel [Byte0]: 31
8632 17:35:12.698993 [Byte1]: 31
8633 17:35:12.703503
8634 17:35:12.703947 Set Vref, RX VrefLevel [Byte0]: 32
8635 17:35:12.706796 [Byte1]: 32
8636 17:35:12.711444
8637 17:35:12.711865 Set Vref, RX VrefLevel [Byte0]: 33
8638 17:35:12.714532 [Byte1]: 33
8639 17:35:12.718701
8640 17:35:12.719118 Set Vref, RX VrefLevel [Byte0]: 34
8641 17:35:12.722335 [Byte1]: 34
8642 17:35:12.726535
8643 17:35:12.727078 Set Vref, RX VrefLevel [Byte0]: 35
8644 17:35:12.729436 [Byte1]: 35
8645 17:35:12.733804
8646 17:35:12.734233 Set Vref, RX VrefLevel [Byte0]: 36
8647 17:35:12.737300 [Byte1]: 36
8648 17:35:12.741665
8649 17:35:12.742096 Set Vref, RX VrefLevel [Byte0]: 37
8650 17:35:12.744755 [Byte1]: 37
8651 17:35:12.749473
8652 17:35:12.749897 Set Vref, RX VrefLevel [Byte0]: 38
8653 17:35:12.752555 [Byte1]: 38
8654 17:35:12.756677
8655 17:35:12.757109 Set Vref, RX VrefLevel [Byte0]: 39
8656 17:35:12.760329 [Byte1]: 39
8657 17:35:12.764315
8658 17:35:12.764740 Set Vref, RX VrefLevel [Byte0]: 40
8659 17:35:12.767695 [Byte1]: 40
8660 17:35:12.771957
8661 17:35:12.772384 Set Vref, RX VrefLevel [Byte0]: 41
8662 17:35:12.775371 [Byte1]: 41
8663 17:35:12.779463
8664 17:35:12.780059 Set Vref, RX VrefLevel [Byte0]: 42
8665 17:35:12.783152 [Byte1]: 42
8666 17:35:12.787473
8667 17:35:12.788062 Set Vref, RX VrefLevel [Byte0]: 43
8668 17:35:12.790590 [Byte1]: 43
8669 17:35:12.794544
8670 17:35:12.795114 Set Vref, RX VrefLevel [Byte0]: 44
8671 17:35:12.798221 [Byte1]: 44
8672 17:35:12.802561
8673 17:35:12.803035 Set Vref, RX VrefLevel [Byte0]: 45
8674 17:35:12.805390 [Byte1]: 45
8675 17:35:12.810011
8676 17:35:12.810553 Set Vref, RX VrefLevel [Byte0]: 46
8677 17:35:12.813500 [Byte1]: 46
8678 17:35:12.817558
8679 17:35:12.818084 Set Vref, RX VrefLevel [Byte0]: 47
8680 17:35:12.821109 [Byte1]: 47
8681 17:35:12.825274
8682 17:35:12.825827 Set Vref, RX VrefLevel [Byte0]: 48
8683 17:35:12.828833 [Byte1]: 48
8684 17:35:12.833084
8685 17:35:12.833544 Set Vref, RX VrefLevel [Byte0]: 49
8686 17:35:12.836422 [Byte1]: 49
8687 17:35:12.840603
8688 17:35:12.841050 Set Vref, RX VrefLevel [Byte0]: 50
8689 17:35:12.843711 [Byte1]: 50
8690 17:35:12.848374
8691 17:35:12.848811 Set Vref, RX VrefLevel [Byte0]: 51
8692 17:35:12.851333 [Byte1]: 51
8693 17:35:12.855747
8694 17:35:12.856313 Set Vref, RX VrefLevel [Byte0]: 52
8695 17:35:12.859216 [Byte1]: 52
8696 17:35:12.863002
8697 17:35:12.863622 Set Vref, RX VrefLevel [Byte0]: 53
8698 17:35:12.866888 [Byte1]: 53
8699 17:35:12.871087
8700 17:35:12.871711 Set Vref, RX VrefLevel [Byte0]: 54
8701 17:35:12.874475 [Byte1]: 54
8702 17:35:12.878669
8703 17:35:12.879120 Set Vref, RX VrefLevel [Byte0]: 55
8704 17:35:12.882130 [Byte1]: 55
8705 17:35:12.886532
8706 17:35:12.886978 Set Vref, RX VrefLevel [Byte0]: 56
8707 17:35:12.889563 [Byte1]: 56
8708 17:35:12.893835
8709 17:35:12.894396 Set Vref, RX VrefLevel [Byte0]: 57
8710 17:35:12.896891 [Byte1]: 57
8711 17:35:12.901405
8712 17:35:12.901982 Set Vref, RX VrefLevel [Byte0]: 58
8713 17:35:12.905045 [Byte1]: 58
8714 17:35:12.908814
8715 17:35:12.909309 Set Vref, RX VrefLevel [Byte0]: 59
8716 17:35:12.912253 [Byte1]: 59
8717 17:35:12.916328
8718 17:35:12.916743 Set Vref, RX VrefLevel [Byte0]: 60
8719 17:35:12.919908 [Byte1]: 60
8720 17:35:12.924442
8721 17:35:12.925046 Set Vref, RX VrefLevel [Byte0]: 61
8722 17:35:12.927498 [Byte1]: 61
8723 17:35:12.931624
8724 17:35:12.932093 Set Vref, RX VrefLevel [Byte0]: 62
8725 17:35:12.935500 [Byte1]: 62
8726 17:35:12.939295
8727 17:35:12.939845 Set Vref, RX VrefLevel [Byte0]: 63
8728 17:35:12.942784 [Byte1]: 63
8729 17:35:12.947010
8730 17:35:12.947611 Set Vref, RX VrefLevel [Byte0]: 64
8731 17:35:12.950749 [Byte1]: 64
8732 17:35:12.954882
8733 17:35:12.955486 Set Vref, RX VrefLevel [Byte0]: 65
8734 17:35:12.957920 [Byte1]: 65
8735 17:35:12.962370
8736 17:35:12.962843 Set Vref, RX VrefLevel [Byte0]: 66
8737 17:35:12.965397 [Byte1]: 66
8738 17:35:12.970286
8739 17:35:12.970731 Set Vref, RX VrefLevel [Byte0]: 67
8740 17:35:12.973621 [Byte1]: 67
8741 17:35:12.977386
8742 17:35:12.977867 Set Vref, RX VrefLevel [Byte0]: 68
8743 17:35:12.980616 [Byte1]: 68
8744 17:35:12.985106
8745 17:35:12.985687 Set Vref, RX VrefLevel [Byte0]: 69
8746 17:35:12.988841 [Byte1]: 69
8747 17:35:12.992924
8748 17:35:12.993539 Final RX Vref Byte 0 = 57 to rank0
8749 17:35:12.996054 Final RX Vref Byte 1 = 55 to rank0
8750 17:35:12.999888 Final RX Vref Byte 0 = 57 to rank1
8751 17:35:13.002642 Final RX Vref Byte 1 = 55 to rank1==
8752 17:35:13.005784 Dram Type= 6, Freq= 0, CH_1, rank 0
8753 17:35:13.012319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 17:35:13.012843 ==
8755 17:35:13.013276 DQS Delay:
8756 17:35:13.016080 DQS0 = 0, DQS1 = 0
8757 17:35:13.016592 DQM Delay:
8758 17:35:13.017113 DQM0 = 130, DQM1 = 123
8759 17:35:13.018988 DQ Delay:
8760 17:35:13.022707 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8761 17:35:13.025873 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8762 17:35:13.029146 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8763 17:35:13.032799 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8764 17:35:13.033384
8765 17:35:13.033920
8766 17:35:13.034435
8767 17:35:13.035444 [DramC_TX_OE_Calibration] TA2
8768 17:35:13.039280 Original DQ_B0 (3 6) =30, OEN = 27
8769 17:35:13.042217 Original DQ_B1 (3 6) =30, OEN = 27
8770 17:35:13.045709 24, 0x0, End_B0=24 End_B1=24
8771 17:35:13.046274 25, 0x0, End_B0=25 End_B1=25
8772 17:35:13.049301 26, 0x0, End_B0=26 End_B1=26
8773 17:35:13.052125 27, 0x0, End_B0=27 End_B1=27
8774 17:35:13.055273 28, 0x0, End_B0=28 End_B1=28
8775 17:35:13.058808 29, 0x0, End_B0=29 End_B1=29
8776 17:35:13.059282 30, 0x0, End_B0=30 End_B1=30
8777 17:35:13.061990 31, 0x4141, End_B0=30 End_B1=30
8778 17:35:13.065541 Byte0 end_step=30 best_step=27
8779 17:35:13.068639 Byte1 end_step=30 best_step=27
8780 17:35:13.072454 Byte0 TX OE(2T, 0.5T) = (3, 3)
8781 17:35:13.075375 Byte1 TX OE(2T, 0.5T) = (3, 3)
8782 17:35:13.075887
8783 17:35:13.076349
8784 17:35:13.082200 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8785 17:35:13.085648 CH1 RK0: MR19=303, MR18=90E
8786 17:35:13.092315 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8787 17:35:13.092793
8788 17:35:13.095270 ----->DramcWriteLeveling(PI) begin...
8789 17:35:13.095775 ==
8790 17:35:13.098586 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 17:35:13.102220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 17:35:13.102716 ==
8793 17:35:13.105437 Write leveling (Byte 0): 22 => 22
8794 17:35:13.108509 Write leveling (Byte 1): 27 => 27
8795 17:35:13.112243 DramcWriteLeveling(PI) end<-----
8796 17:35:13.112671
8797 17:35:13.113105 ==
8798 17:35:13.115251 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 17:35:13.118310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 17:35:13.118740 ==
8801 17:35:13.122131 [Gating] SW mode calibration
8802 17:35:13.128980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8803 17:35:13.134853 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8804 17:35:13.138235 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 17:35:13.142167 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8806 17:35:13.148486 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
8807 17:35:13.151489 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8808 17:35:13.158469 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 17:35:13.162402 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 17:35:13.164969 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 17:35:13.171117 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 17:35:13.174531 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 17:35:13.177952 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 17:35:13.184427 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
8815 17:35:13.187724 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8816 17:35:13.191454 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 17:35:13.194399 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 17:35:13.200841 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 17:35:13.204301 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 17:35:13.207747 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 17:35:13.214358 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8822 17:35:13.217832 1 6 8 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
8823 17:35:13.220902 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8824 17:35:13.227630 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 17:35:13.231139 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 17:35:13.234417 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 17:35:13.240994 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 17:35:13.244162 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 17:35:13.247840 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 17:35:13.254246 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8831 17:35:13.257824 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8832 17:35:13.260619 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 17:35:13.267105 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 17:35:13.270472 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 17:35:13.273845 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 17:35:13.280629 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 17:35:13.284167 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 17:35:13.287236 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 17:35:13.293802 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 17:35:13.296873 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 17:35:13.300221 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 17:35:13.306946 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 17:35:13.310546 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 17:35:13.313221 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 17:35:13.320217 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 17:35:13.323303 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8847 17:35:13.326655 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8848 17:35:13.329995 Total UI for P1: 0, mck2ui 16
8849 17:35:13.333061 best dqsien dly found for B0: ( 1, 9, 8)
8850 17:35:13.340169 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8851 17:35:13.343735 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 17:35:13.346483 Total UI for P1: 0, mck2ui 16
8853 17:35:13.350306 best dqsien dly found for B1: ( 1, 9, 14)
8854 17:35:13.353239 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8855 17:35:13.356446 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8856 17:35:13.356546
8857 17:35:13.359783 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8858 17:35:13.363399 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8859 17:35:13.366392 [Gating] SW calibration Done
8860 17:35:13.366500 ==
8861 17:35:13.369864 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 17:35:13.373171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 17:35:13.376362 ==
8864 17:35:13.376493 RX Vref Scan: 0
8865 17:35:13.376595
8866 17:35:13.379880 RX Vref 0 -> 0, step: 1
8867 17:35:13.380013
8868 17:35:13.380115 RX Delay 0 -> 252, step: 8
8869 17:35:13.386284 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8870 17:35:13.389616 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8871 17:35:13.392640 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8872 17:35:13.396321 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8873 17:35:13.399583 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8874 17:35:13.405999 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8875 17:35:13.409454 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8876 17:35:13.412669 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8877 17:35:13.415900 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8878 17:35:13.419158 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8879 17:35:13.426026 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8880 17:35:13.429421 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8881 17:35:13.432680 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8882 17:35:13.435888 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8883 17:35:13.442867 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8884 17:35:13.445822 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8885 17:35:13.445922 ==
8886 17:35:13.449352 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 17:35:13.452211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 17:35:13.452290 ==
8889 17:35:13.455821 DQS Delay:
8890 17:35:13.455900 DQS0 = 0, DQS1 = 0
8891 17:35:13.455990 DQM Delay:
8892 17:35:13.459105 DQM0 = 129, DQM1 = 127
8893 17:35:13.459209 DQ Delay:
8894 17:35:13.462638 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8895 17:35:13.465533 DQ4 =123, DQ5 =143, DQ6 =143, DQ7 =127
8896 17:35:13.469264 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8897 17:35:13.475218 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8898 17:35:13.475320
8899 17:35:13.475430
8900 17:35:13.475530 ==
8901 17:35:13.478910 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 17:35:13.481899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 17:35:13.482006 ==
8904 17:35:13.482094
8905 17:35:13.482179
8906 17:35:13.485781 TX Vref Scan disable
8907 17:35:13.485877 == TX Byte 0 ==
8908 17:35:13.492197 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8909 17:35:13.495769 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8910 17:35:13.495849 == TX Byte 1 ==
8911 17:35:13.501869 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8912 17:35:13.505582 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8913 17:35:13.505663 ==
8914 17:35:13.508575 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 17:35:13.512375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 17:35:13.512456 ==
8917 17:35:13.527506
8918 17:35:13.530691 TX Vref early break, caculate TX vref
8919 17:35:13.534270 TX Vref=16, minBit 0, minWin=22, winSum=381
8920 17:35:13.537543 TX Vref=18, minBit 0, minWin=22, winSum=386
8921 17:35:13.540964 TX Vref=20, minBit 0, minWin=23, winSum=400
8922 17:35:13.544310 TX Vref=22, minBit 0, minWin=23, winSum=403
8923 17:35:13.547154 TX Vref=24, minBit 0, minWin=24, winSum=414
8924 17:35:13.554019 TX Vref=26, minBit 5, minWin=24, winSum=418
8925 17:35:13.557440 TX Vref=28, minBit 0, minWin=25, winSum=422
8926 17:35:13.560957 TX Vref=30, minBit 5, minWin=23, winSum=414
8927 17:35:13.563700 TX Vref=32, minBit 1, minWin=23, winSum=405
8928 17:35:13.567217 TX Vref=34, minBit 1, minWin=22, winSum=400
8929 17:35:13.570668 TX Vref=36, minBit 5, minWin=22, winSum=390
8930 17:35:13.577184 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8931 17:35:13.577266
8932 17:35:13.580670 Final TX Range 0 Vref 28
8933 17:35:13.580776
8934 17:35:13.580871 ==
8935 17:35:13.584138 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 17:35:13.587090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 17:35:13.587171 ==
8938 17:35:13.587234
8939 17:35:13.590483
8940 17:35:13.590563 TX Vref Scan disable
8941 17:35:13.596719 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8942 17:35:13.596800 == TX Byte 0 ==
8943 17:35:13.600314 u2DelayCellOfst[0]=18 cells (5 PI)
8944 17:35:13.603863 u2DelayCellOfst[1]=11 cells (3 PI)
8945 17:35:13.607320 u2DelayCellOfst[2]=0 cells (0 PI)
8946 17:35:13.610162 u2DelayCellOfst[3]=7 cells (2 PI)
8947 17:35:13.613632 u2DelayCellOfst[4]=7 cells (2 PI)
8948 17:35:13.616495 u2DelayCellOfst[5]=22 cells (6 PI)
8949 17:35:13.620159 u2DelayCellOfst[6]=22 cells (6 PI)
8950 17:35:13.623880 u2DelayCellOfst[7]=7 cells (2 PI)
8951 17:35:13.626423 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8952 17:35:13.630007 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8953 17:35:13.633517 == TX Byte 1 ==
8954 17:35:13.636678 u2DelayCellOfst[8]=0 cells (0 PI)
8955 17:35:13.640140 u2DelayCellOfst[9]=7 cells (2 PI)
8956 17:35:13.643209 u2DelayCellOfst[10]=15 cells (4 PI)
8957 17:35:13.646645 u2DelayCellOfst[11]=7 cells (2 PI)
8958 17:35:13.646728 u2DelayCellOfst[12]=15 cells (4 PI)
8959 17:35:13.650029 u2DelayCellOfst[13]=18 cells (5 PI)
8960 17:35:13.653043 u2DelayCellOfst[14]=22 cells (6 PI)
8961 17:35:13.656349 u2DelayCellOfst[15]=18 cells (5 PI)
8962 17:35:13.663076 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8963 17:35:13.666503 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8964 17:35:13.666599 DramC Write-DBI on
8965 17:35:13.666707 ==
8966 17:35:13.669947 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 17:35:13.676323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 17:35:13.676430 ==
8969 17:35:13.676565
8970 17:35:13.676656
8971 17:35:13.679704 TX Vref Scan disable
8972 17:35:13.679784 == TX Byte 0 ==
8973 17:35:13.686218 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8974 17:35:13.686298 == TX Byte 1 ==
8975 17:35:13.689749 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8976 17:35:13.693063 DramC Write-DBI off
8977 17:35:13.693174
8978 17:35:13.693268 [DATLAT]
8979 17:35:13.696341 Freq=1600, CH1 RK1
8980 17:35:13.696445
8981 17:35:13.696535 DATLAT Default: 0xf
8982 17:35:13.699227 0, 0xFFFF, sum = 0
8983 17:35:13.699307 1, 0xFFFF, sum = 0
8984 17:35:13.702883 2, 0xFFFF, sum = 0
8985 17:35:13.702963 3, 0xFFFF, sum = 0
8986 17:35:13.705851 4, 0xFFFF, sum = 0
8987 17:35:13.705931 5, 0xFFFF, sum = 0
8988 17:35:13.709607 6, 0xFFFF, sum = 0
8989 17:35:13.709715 7, 0xFFFF, sum = 0
8990 17:35:13.712726 8, 0xFFFF, sum = 0
8991 17:35:13.715763 9, 0xFFFF, sum = 0
8992 17:35:13.715881 10, 0xFFFF, sum = 0
8993 17:35:13.719188 11, 0xFFFF, sum = 0
8994 17:35:13.719309 12, 0xFFFF, sum = 0
8995 17:35:13.722268 13, 0x8FFF, sum = 0
8996 17:35:13.722349 14, 0x0, sum = 1
8997 17:35:13.726086 15, 0x0, sum = 2
8998 17:35:13.726167 16, 0x0, sum = 3
8999 17:35:13.729076 17, 0x0, sum = 4
9000 17:35:13.729178 best_step = 15
9001 17:35:13.729283
9002 17:35:13.729372 ==
9003 17:35:13.732395 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 17:35:13.735456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 17:35:13.739229 ==
9006 17:35:13.739308 RX Vref Scan: 0
9007 17:35:13.739370
9008 17:35:13.742072 RX Vref 0 -> 0, step: 1
9009 17:35:13.742151
9010 17:35:13.742214 RX Delay 3 -> 252, step: 4
9011 17:35:13.749357 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9012 17:35:13.753215 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9013 17:35:13.756408 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9014 17:35:13.759352 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9015 17:35:13.762873 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9016 17:35:13.769546 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9017 17:35:13.772536 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9018 17:35:13.776127 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9019 17:35:13.779204 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
9020 17:35:13.782515 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9021 17:35:13.789198 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9022 17:35:13.792704 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9023 17:35:13.796170 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9024 17:35:13.798977 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9025 17:35:13.805610 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9026 17:35:13.809207 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9027 17:35:13.809288 ==
9028 17:35:13.812270 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 17:35:13.815582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 17:35:13.815663 ==
9031 17:35:13.818999 DQS Delay:
9032 17:35:13.819117 DQS0 = 0, DQS1 = 0
9033 17:35:13.819208 DQM Delay:
9034 17:35:13.822734 DQM0 = 127, DQM1 = 125
9035 17:35:13.822815 DQ Delay:
9036 17:35:13.825821 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
9037 17:35:13.829513 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9038 17:35:13.832021 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9039 17:35:13.839033 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
9040 17:35:13.839114
9041 17:35:13.839177
9042 17:35:13.839234
9043 17:35:13.842002 [DramC_TX_OE_Calibration] TA2
9044 17:35:13.845673 Original DQ_B0 (3 6) =30, OEN = 27
9045 17:35:13.845781 Original DQ_B1 (3 6) =30, OEN = 27
9046 17:35:13.849019 24, 0x0, End_B0=24 End_B1=24
9047 17:35:13.852174 25, 0x0, End_B0=25 End_B1=25
9048 17:35:13.855277 26, 0x0, End_B0=26 End_B1=26
9049 17:35:13.858639 27, 0x0, End_B0=27 End_B1=27
9050 17:35:13.858746 28, 0x0, End_B0=28 End_B1=28
9051 17:35:13.861779 29, 0x0, End_B0=29 End_B1=29
9052 17:35:13.865260 30, 0x0, End_B0=30 End_B1=30
9053 17:35:13.868809 31, 0x5151, End_B0=30 End_B1=30
9054 17:35:13.872328 Byte0 end_step=30 best_step=27
9055 17:35:13.872430 Byte1 end_step=30 best_step=27
9056 17:35:13.875294 Byte0 TX OE(2T, 0.5T) = (3, 3)
9057 17:35:13.878923 Byte1 TX OE(2T, 0.5T) = (3, 3)
9058 17:35:13.879041
9059 17:35:13.879173
9060 17:35:13.888554 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9061 17:35:13.888640 CH1 RK1: MR19=303, MR18=111D
9062 17:35:13.895185 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9063 17:35:13.898303 [RxdqsGatingPostProcess] freq 1600
9064 17:35:13.905002 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9065 17:35:13.908171 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 17:35:13.911809 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 17:35:13.914789 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 17:35:13.918334 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 17:35:13.921636 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 17:35:13.921718 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 17:35:13.925012 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 17:35:13.928184 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 17:35:13.931488 Pre-setting of DQS Precalculation
9074 17:35:13.938130 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9075 17:35:13.944851 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9076 17:35:13.951612 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 17:35:13.951695
9078 17:35:13.951790
9079 17:35:13.954749 [Calibration Summary] 3200 Mbps
9080 17:35:13.954848 CH 0, Rank 0
9081 17:35:13.958230 SW Impedance : PASS
9082 17:35:13.961583 DUTY Scan : NO K
9083 17:35:13.961690 ZQ Calibration : PASS
9084 17:35:13.965024 Jitter Meter : NO K
9085 17:35:13.968213 CBT Training : PASS
9086 17:35:13.968294 Write leveling : PASS
9087 17:35:13.971425 RX DQS gating : PASS
9088 17:35:13.974986 RX DQ/DQS(RDDQC) : PASS
9089 17:35:13.975067 TX DQ/DQS : PASS
9090 17:35:13.977917 RX DATLAT : PASS
9091 17:35:13.981529 RX DQ/DQS(Engine): PASS
9092 17:35:13.981636 TX OE : PASS
9093 17:35:13.984930 All Pass.
9094 17:35:13.985014
9095 17:35:13.985098 CH 0, Rank 1
9096 17:35:13.987844 SW Impedance : PASS
9097 17:35:13.987925 DUTY Scan : NO K
9098 17:35:13.991421 ZQ Calibration : PASS
9099 17:35:13.994503 Jitter Meter : NO K
9100 17:35:13.994583 CBT Training : PASS
9101 17:35:13.997533 Write leveling : PASS
9102 17:35:14.001366 RX DQS gating : PASS
9103 17:35:14.001446 RX DQ/DQS(RDDQC) : PASS
9104 17:35:14.004782 TX DQ/DQS : PASS
9105 17:35:14.004893 RX DATLAT : PASS
9106 17:35:14.008063 RX DQ/DQS(Engine): PASS
9107 17:35:14.010889 TX OE : PASS
9108 17:35:14.010969 All Pass.
9109 17:35:14.011032
9110 17:35:14.014720 CH 1, Rank 0
9111 17:35:14.014800 SW Impedance : PASS
9112 17:35:14.017570 DUTY Scan : NO K
9113 17:35:14.017650 ZQ Calibration : PASS
9114 17:35:14.020630 Jitter Meter : NO K
9115 17:35:14.024378 CBT Training : PASS
9116 17:35:14.024460 Write leveling : PASS
9117 17:35:14.027370 RX DQS gating : PASS
9118 17:35:14.030907 RX DQ/DQS(RDDQC) : PASS
9119 17:35:14.030987 TX DQ/DQS : PASS
9120 17:35:14.034060 RX DATLAT : PASS
9121 17:35:14.037313 RX DQ/DQS(Engine): PASS
9122 17:35:14.037394 TX OE : PASS
9123 17:35:14.041047 All Pass.
9124 17:35:14.041128
9125 17:35:14.041192 CH 1, Rank 1
9126 17:35:14.044106 SW Impedance : PASS
9127 17:35:14.044186 DUTY Scan : NO K
9128 17:35:14.047320 ZQ Calibration : PASS
9129 17:35:14.051170 Jitter Meter : NO K
9130 17:35:14.051277 CBT Training : PASS
9131 17:35:14.054099 Write leveling : PASS
9132 17:35:14.057459 RX DQS gating : PASS
9133 17:35:14.057540 RX DQ/DQS(RDDQC) : PASS
9134 17:35:14.060396 TX DQ/DQS : PASS
9135 17:35:14.063753 RX DATLAT : PASS
9136 17:35:14.063834 RX DQ/DQS(Engine): PASS
9137 17:35:14.067615 TX OE : PASS
9138 17:35:14.067699 All Pass.
9139 17:35:14.067763
9140 17:35:14.070462 DramC Write-DBI on
9141 17:35:14.073739 PER_BANK_REFRESH: Hybrid Mode
9142 17:35:14.073820 TX_TRACKING: ON
9143 17:35:14.083675 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9144 17:35:14.090320 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9145 17:35:14.096974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 17:35:14.100357 [FAST_K] Save calibration result to emmc
9147 17:35:14.103970 sync common calibartion params.
9148 17:35:14.106887 sync cbt_mode0:1, 1:1
9149 17:35:14.110767 dram_init: ddr_geometry: 2
9150 17:35:14.110848 dram_init: ddr_geometry: 2
9151 17:35:14.113621 dram_init: ddr_geometry: 2
9152 17:35:14.116797 0:dram_rank_size:100000000
9153 17:35:14.116880 1:dram_rank_size:100000000
9154 17:35:14.123777 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9155 17:35:14.127545 DFS_SHUFFLE_HW_MODE: ON
9156 17:35:14.130592 dramc_set_vcore_voltage set vcore to 725000
9157 17:35:14.133749 Read voltage for 1600, 0
9158 17:35:14.134165 Vio18 = 0
9159 17:35:14.134491 Vcore = 725000
9160 17:35:14.137365 Vdram = 0
9161 17:35:14.137783 Vddq = 0
9162 17:35:14.138111 Vmddr = 0
9163 17:35:14.140365 switch to 3200 Mbps bootup
9164 17:35:14.140796 [DramcRunTimeConfig]
9165 17:35:14.143535 PHYPLL
9166 17:35:14.143949 DPM_CONTROL_AFTERK: ON
9167 17:35:14.147015 PER_BANK_REFRESH: ON
9168 17:35:14.150378 REFRESH_OVERHEAD_REDUCTION: ON
9169 17:35:14.150789 CMD_PICG_NEW_MODE: OFF
9170 17:35:14.153639 XRTWTW_NEW_MODE: ON
9171 17:35:14.154054 XRTRTR_NEW_MODE: ON
9172 17:35:14.157252 TX_TRACKING: ON
9173 17:35:14.157671 RDSEL_TRACKING: OFF
9174 17:35:14.160641 DQS Precalculation for DVFS: ON
9175 17:35:14.163825 RX_TRACKING: OFF
9176 17:35:14.164239 HW_GATING DBG: ON
9177 17:35:14.166913 ZQCS_ENABLE_LP4: ON
9178 17:35:14.167332 RX_PICG_NEW_MODE: ON
9179 17:35:14.170607 TX_PICG_NEW_MODE: ON
9180 17:35:14.173774 ENABLE_RX_DCM_DPHY: ON
9181 17:35:14.174188 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9182 17:35:14.176621 DUMMY_READ_FOR_TRACKING: OFF
9183 17:35:14.180165 !!! SPM_CONTROL_AFTERK: OFF
9184 17:35:14.183794 !!! SPM could not control APHY
9185 17:35:14.184277 IMPEDANCE_TRACKING: ON
9186 17:35:14.187014 TEMP_SENSOR: ON
9187 17:35:14.187490 HW_SAVE_FOR_SR: OFF
9188 17:35:14.190506 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9189 17:35:14.193706 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9190 17:35:14.196887 Read ODT Tracking: ON
9191 17:35:14.200594 Refresh Rate DeBounce: ON
9192 17:35:14.201011 DFS_NO_QUEUE_FLUSH: ON
9193 17:35:14.203409 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9194 17:35:14.206676 ENABLE_DFS_RUNTIME_MRW: OFF
9195 17:35:14.210081 DDR_RESERVE_NEW_MODE: ON
9196 17:35:14.210538 MR_CBT_SWITCH_FREQ: ON
9197 17:35:14.213296 =========================
9198 17:35:14.232352 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9199 17:35:14.236091 dram_init: ddr_geometry: 2
9200 17:35:14.254069 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9201 17:35:14.257757 dram_init: dram init end (result: 0)
9202 17:35:14.263879 DRAM-K: Full calibration passed in 24531 msecs
9203 17:35:14.267450 MRC: failed to locate region type 0.
9204 17:35:14.267878 DRAM rank0 size:0x100000000,
9205 17:35:14.270543 DRAM rank1 size=0x100000000
9206 17:35:14.280801 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9207 17:35:14.287365 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9208 17:35:14.293898 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9209 17:35:14.300830 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9210 17:35:14.303582 DRAM rank0 size:0x100000000,
9211 17:35:14.307454 DRAM rank1 size=0x100000000
9212 17:35:14.307895 CBMEM:
9213 17:35:14.310246 IMD: root @ 0xfffff000 254 entries.
9214 17:35:14.313483 IMD: root @ 0xffffec00 62 entries.
9215 17:35:14.317138 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9216 17:35:14.323705 WARNING: RO_VPD is uninitialized or empty.
9217 17:35:14.326918 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9218 17:35:14.334287 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9219 17:35:14.347144 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9220 17:35:14.358233 BS: romstage times (exec / console): total (unknown) / 24004 ms
9221 17:35:14.358707
9222 17:35:14.359079
9223 17:35:14.368382 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9224 17:35:14.371197 ARM64: Exception handlers installed.
9225 17:35:14.374818 ARM64: Testing exception
9226 17:35:14.378399 ARM64: Done test exception
9227 17:35:14.378481 Enumerating buses...
9228 17:35:14.381430 Show all devs... Before device enumeration.
9229 17:35:14.384553 Root Device: enabled 1
9230 17:35:14.387862 CPU_CLUSTER: 0: enabled 1
9231 17:35:14.387943 CPU: 00: enabled 1
9232 17:35:14.390768 Compare with tree...
9233 17:35:14.390848 Root Device: enabled 1
9234 17:35:14.394295 CPU_CLUSTER: 0: enabled 1
9235 17:35:14.397226 CPU: 00: enabled 1
9236 17:35:14.397307 Root Device scanning...
9237 17:35:14.400811 scan_static_bus for Root Device
9238 17:35:14.404052 CPU_CLUSTER: 0 enabled
9239 17:35:14.407611 scan_static_bus for Root Device done
9240 17:35:14.410639 scan_bus: bus Root Device finished in 8 msecs
9241 17:35:14.410720 done
9242 17:35:14.417253 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9243 17:35:14.420474 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9244 17:35:14.426917 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9245 17:35:14.430751 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9246 17:35:14.433837 Allocating resources...
9247 17:35:14.437251 Reading resources...
9248 17:35:14.440776 Root Device read_resources bus 0 link: 0
9249 17:35:14.443669 DRAM rank0 size:0x100000000,
9250 17:35:14.443750 DRAM rank1 size=0x100000000
9251 17:35:14.446913 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9252 17:35:14.450294 CPU: 00 missing read_resources
9253 17:35:14.457613 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9254 17:35:14.460369 Root Device read_resources bus 0 link: 0 done
9255 17:35:14.460451 Done reading resources.
9256 17:35:14.466863 Show resources in subtree (Root Device)...After reading.
9257 17:35:14.470554 Root Device child on link 0 CPU_CLUSTER: 0
9258 17:35:14.473560 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 17:35:14.483339 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 17:35:14.483433 CPU: 00
9261 17:35:14.487195 Root Device assign_resources, bus 0 link: 0
9262 17:35:14.490038 CPU_CLUSTER: 0 missing set_resources
9263 17:35:14.496576 Root Device assign_resources, bus 0 link: 0 done
9264 17:35:14.496658 Done setting resources.
9265 17:35:14.503439 Show resources in subtree (Root Device)...After assigning values.
9266 17:35:14.506744 Root Device child on link 0 CPU_CLUSTER: 0
9267 17:35:14.510275 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 17:35:14.519856 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 17:35:14.519944 CPU: 00
9270 17:35:14.523316 Done allocating resources.
9271 17:35:14.530150 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9272 17:35:14.530262 Enabling resources...
9273 17:35:14.530353 done.
9274 17:35:14.536505 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9275 17:35:14.536589 Initializing devices...
9276 17:35:14.539880 Root Device init
9277 17:35:14.539961 init hardware done!
9278 17:35:14.543117 0x00000018: ctrlr->caps
9279 17:35:14.546596 52.000 MHz: ctrlr->f_max
9280 17:35:14.546678 0.400 MHz: ctrlr->f_min
9281 17:35:14.549824 0x40ff8080: ctrlr->voltages
9282 17:35:14.553366 sclk: 390625
9283 17:35:14.553450 Bus Width = 1
9284 17:35:14.553526 sclk: 390625
9285 17:35:14.556418 Bus Width = 1
9286 17:35:14.556499 Early init status = 3
9287 17:35:14.563180 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9288 17:35:14.566395 in-header: 03 fc 00 00 01 00 00 00
9289 17:35:14.569627 in-data: 00
9290 17:35:14.572776 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9291 17:35:14.578522 in-header: 03 fd 00 00 00 00 00 00
9292 17:35:14.582043 in-data:
9293 17:35:14.585084 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9294 17:35:14.589707 in-header: 03 fc 00 00 01 00 00 00
9295 17:35:14.592704 in-data: 00
9296 17:35:14.596665 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9297 17:35:14.601989 in-header: 03 fd 00 00 00 00 00 00
9298 17:35:14.605176 in-data:
9299 17:35:14.608832 [SSUSB] Setting up USB HOST controller...
9300 17:35:14.612401 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9301 17:35:14.615290 [SSUSB] phy power-on done.
9302 17:35:14.618581 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9303 17:35:14.625063 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9304 17:35:14.628039 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9305 17:35:14.634904 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9306 17:35:14.641312 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9307 17:35:14.648027 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9308 17:35:14.654631 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9309 17:35:14.661140 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9310 17:35:14.665036 SPM: binary array size = 0x9dc
9311 17:35:14.667982 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9312 17:35:14.674290 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9313 17:35:14.680841 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9314 17:35:14.687327 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9315 17:35:14.690570 configure_display: Starting display init
9316 17:35:14.724763 anx7625_power_on_init: Init interface.
9317 17:35:14.728312 anx7625_disable_pd_protocol: Disabled PD feature.
9318 17:35:14.731357 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9319 17:35:14.759856 anx7625_start_dp_work: Secure OCM version=00
9320 17:35:14.762866 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9321 17:35:14.778046 sp_tx_get_edid_block: EDID Block = 1
9322 17:35:14.880350 Extracted contents:
9323 17:35:14.883290 header: 00 ff ff ff ff ff ff 00
9324 17:35:14.886533 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9325 17:35:14.890174 version: 01 04
9326 17:35:14.893157 basic params: 95 1f 11 78 0a
9327 17:35:14.897083 chroma info: 76 90 94 55 54 90 27 21 50 54
9328 17:35:14.900059 established: 00 00 00
9329 17:35:14.907020 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9330 17:35:14.913381 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9331 17:35:14.916784 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9332 17:35:14.923074 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9333 17:35:14.929740 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9334 17:35:14.932827 extensions: 00
9335 17:35:14.932909 checksum: fb
9336 17:35:14.932972
9337 17:35:14.939342 Manufacturer: IVO Model 57d Serial Number 0
9338 17:35:14.939453 Made week 0 of 2020
9339 17:35:14.942667 EDID version: 1.4
9340 17:35:14.942752 Digital display
9341 17:35:14.946021 6 bits per primary color channel
9342 17:35:14.946104 DisplayPort interface
9343 17:35:14.949557 Maximum image size: 31 cm x 17 cm
9344 17:35:14.952539 Gamma: 220%
9345 17:35:14.952620 Check DPMS levels
9346 17:35:14.956357 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9347 17:35:14.962551 First detailed timing is preferred timing
9348 17:35:14.962633 Established timings supported:
9349 17:35:14.966023 Standard timings supported:
9350 17:35:14.969150 Detailed timings
9351 17:35:14.972428 Hex of detail: 383680a07038204018303c0035ae10000019
9352 17:35:14.979407 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9353 17:35:14.982376 0780 0798 07c8 0820 hborder 0
9354 17:35:14.985563 0438 043b 0447 0458 vborder 0
9355 17:35:14.988909 -hsync -vsync
9356 17:35:14.989059 Did detailed timing
9357 17:35:14.995756 Hex of detail: 000000000000000000000000000000000000
9358 17:35:14.998733 Manufacturer-specified data, tag 0
9359 17:35:15.002385 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9360 17:35:15.005474 ASCII string: InfoVision
9361 17:35:15.008733 Hex of detail: 000000fe00523134304e574635205248200a
9362 17:35:15.012473 ASCII string: R140NWF5 RH
9363 17:35:15.012553 Checksum
9364 17:35:15.015276 Checksum: 0xfb (valid)
9365 17:35:15.018561 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9366 17:35:15.022359 DSI data_rate: 832800000 bps
9367 17:35:15.028544 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9368 17:35:15.032013 anx7625_parse_edid: pixelclock(138800).
9369 17:35:15.035092 hactive(1920), hsync(48), hfp(24), hbp(88)
9370 17:35:15.038707 vactive(1080), vsync(12), vfp(3), vbp(17)
9371 17:35:15.041802 anx7625_dsi_config: config dsi.
9372 17:35:15.048672 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9373 17:35:15.062343 anx7625_dsi_config: success to config DSI
9374 17:35:15.065758 anx7625_dp_start: MIPI phy setup OK.
9375 17:35:15.068866 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9376 17:35:15.072326 mtk_ddp_mode_set invalid vrefresh 60
9377 17:35:15.075540 main_disp_path_setup
9378 17:35:15.075647 ovl_layer_smi_id_en
9379 17:35:15.078612 ovl_layer_smi_id_en
9380 17:35:15.078692 ccorr_config
9381 17:35:15.078756 aal_config
9382 17:35:15.082049 gamma_config
9383 17:35:15.082129 postmask_config
9384 17:35:15.085251 dither_config
9385 17:35:15.088468 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9386 17:35:15.095166 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9387 17:35:15.098317 Root Device init finished in 555 msecs
9388 17:35:15.102008 CPU_CLUSTER: 0 init
9389 17:35:15.108217 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9390 17:35:15.114700 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9391 17:35:15.114782 APU_MBOX 0x190000b0 = 0x10001
9392 17:35:15.118384 APU_MBOX 0x190001b0 = 0x10001
9393 17:35:15.121426 APU_MBOX 0x190005b0 = 0x10001
9394 17:35:15.124761 APU_MBOX 0x190006b0 = 0x10001
9395 17:35:15.131516 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9396 17:35:15.141108 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9397 17:35:15.153731 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9398 17:35:15.159790 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9399 17:35:15.171962 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9400 17:35:15.180889 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9401 17:35:15.185104 CPU_CLUSTER: 0 init finished in 81 msecs
9402 17:35:15.187311 Devices initialized
9403 17:35:15.190928 Show all devs... After init.
9404 17:35:15.191008 Root Device: enabled 1
9405 17:35:15.194194 CPU_CLUSTER: 0: enabled 1
9406 17:35:15.197496 CPU: 00: enabled 1
9407 17:35:15.200936 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9408 17:35:15.204063 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9409 17:35:15.207361 ELOG: NV offset 0x57f000 size 0x1000
9410 17:35:15.214208 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9411 17:35:15.220877 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9412 17:35:15.224026 ELOG: Event(17) added with size 13 at 2023-09-13 17:35:14 UTC
9413 17:35:15.230736 out: cmd=0x121: 03 db 21 01 00 00 00 00
9414 17:35:15.233770 in-header: 03 82 00 00 2c 00 00 00
9415 17:35:15.243863 in-data: dd 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9416 17:35:15.250329 ELOG: Event(A1) added with size 10 at 2023-09-13 17:35:14 UTC
9417 17:35:15.257233 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9418 17:35:15.263514 ELOG: Event(A0) added with size 9 at 2023-09-13 17:35:14 UTC
9419 17:35:15.266804 elog_add_boot_reason: Logged dev mode boot
9420 17:35:15.273192 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9421 17:35:15.273277 Finalize devices...
9422 17:35:15.276656 Devices finalized
9423 17:35:15.280279 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9424 17:35:15.283363 Writing coreboot table at 0xffe64000
9425 17:35:15.286869 0. 000000000010a000-0000000000113fff: RAMSTAGE
9426 17:35:15.293435 1. 0000000040000000-00000000400fffff: RAM
9427 17:35:15.296411 2. 0000000040100000-000000004032afff: RAMSTAGE
9428 17:35:15.299588 3. 000000004032b000-00000000545fffff: RAM
9429 17:35:15.303022 4. 0000000054600000-000000005465ffff: BL31
9430 17:35:15.306375 5. 0000000054660000-00000000ffe63fff: RAM
9431 17:35:15.313040 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9432 17:35:15.316164 7. 0000000100000000-000000023fffffff: RAM
9433 17:35:15.319378 Passing 5 GPIOs to payload:
9434 17:35:15.323555 NAME | PORT | POLARITY | VALUE
9435 17:35:15.329851 EC in RW | 0x000000aa | low | undefined
9436 17:35:15.332594 EC interrupt | 0x00000005 | low | undefined
9437 17:35:15.336350 TPM interrupt | 0x000000ab | high | undefined
9438 17:35:15.343021 SD card detect | 0x00000011 | high | undefined
9439 17:35:15.346263 speaker enable | 0x00000093 | high | undefined
9440 17:35:15.349556 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9441 17:35:15.352997 in-header: 03 f9 00 00 02 00 00 00
9442 17:35:15.355852 in-data: 02 00
9443 17:35:15.359219 ADC[4]: Raw value=894081 ID=7
9444 17:35:15.359359 ADC[3]: Raw value=213070 ID=1
9445 17:35:15.362657 RAM Code: 0x71
9446 17:35:15.366183 ADC[6]: Raw value=74722 ID=0
9447 17:35:15.366335 ADC[5]: Raw value=212700 ID=1
9448 17:35:15.369397 SKU Code: 0x1
9449 17:35:15.375747 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9450 17:35:15.375902 coreboot table: 964 bytes.
9451 17:35:15.379329 IMD ROOT 0. 0xfffff000 0x00001000
9452 17:35:15.382430 IMD SMALL 1. 0xffffe000 0x00001000
9453 17:35:15.385821 RO MCACHE 2. 0xffffc000 0x00001104
9454 17:35:15.389173 CONSOLE 3. 0xfff7c000 0x00080000
9455 17:35:15.392305 FMAP 4. 0xfff7b000 0x00000452
9456 17:35:15.395505 TIME STAMP 5. 0xfff7a000 0x00000910
9457 17:35:15.399161 VBOOT WORK 6. 0xfff66000 0x00014000
9458 17:35:15.402643 RAMOOPS 7. 0xffe66000 0x00100000
9459 17:35:15.405861 COREBOOT 8. 0xffe64000 0x00002000
9460 17:35:15.409463 IMD small region:
9461 17:35:15.412344 IMD ROOT 0. 0xffffec00 0x00000400
9462 17:35:15.415436 VPD 1. 0xffffeb80 0x0000006c
9463 17:35:15.418957 MMC STATUS 2. 0xffffeb60 0x00000004
9464 17:35:15.421983 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9465 17:35:15.425823 Probing TPM: done!
9466 17:35:15.429141 Connected to device vid:did:rid of 1ae0:0028:00
9467 17:35:15.440582 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9468 17:35:15.443669 Initialized TPM device CR50 revision 0
9469 17:35:15.447099 Checking cr50 for pending updates
9470 17:35:15.451069 Reading cr50 TPM mode
9471 17:35:15.459460 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9472 17:35:15.466480 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9473 17:35:15.506184 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9474 17:35:15.509176 Checking segment from ROM address 0x40100000
9475 17:35:15.512706 Checking segment from ROM address 0x4010001c
9476 17:35:15.519395 Loading segment from ROM address 0x40100000
9477 17:35:15.519506 code (compression=0)
9478 17:35:15.529246 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9479 17:35:15.535833 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9480 17:35:15.535926 it's not compressed!
9481 17:35:15.542402 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9482 17:35:15.548976 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9483 17:35:15.566401 Loading segment from ROM address 0x4010001c
9484 17:35:15.566520 Entry Point 0x80000000
9485 17:35:15.569699 Loaded segments
9486 17:35:15.573323 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9487 17:35:15.579765 Jumping to boot code at 0x80000000(0xffe64000)
9488 17:35:15.586043 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9489 17:35:15.592972 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9490 17:35:15.600852 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9491 17:35:15.604536 Checking segment from ROM address 0x40100000
9492 17:35:15.607729 Checking segment from ROM address 0x4010001c
9493 17:35:15.614030 Loading segment from ROM address 0x40100000
9494 17:35:15.614129 code (compression=1)
9495 17:35:15.621088 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9496 17:35:15.631127 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9497 17:35:15.631210 using LZMA
9498 17:35:15.639634 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9499 17:35:15.645719 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9500 17:35:15.649320 Loading segment from ROM address 0x4010001c
9501 17:35:15.649402 Entry Point 0x54601000
9502 17:35:15.652365 Loaded segments
9503 17:35:15.655690 NOTICE: MT8192 bl31_setup
9504 17:35:15.662985 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9505 17:35:15.666706 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9506 17:35:15.669413 WARNING: region 0:
9507 17:35:15.672852 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 17:35:15.672958 WARNING: region 1:
9509 17:35:15.679624 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9510 17:35:15.683010 WARNING: region 2:
9511 17:35:15.686187 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9512 17:35:15.689727 WARNING: region 3:
9513 17:35:15.692798 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9514 17:35:15.696152 WARNING: region 4:
9515 17:35:15.699781 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9516 17:35:15.702824 WARNING: region 5:
9517 17:35:15.706286 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 17:35:15.709819 WARNING: region 6:
9519 17:35:15.713078 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 17:35:15.713153 WARNING: region 7:
9521 17:35:15.720007 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 17:35:15.726007 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9523 17:35:15.729475 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9524 17:35:15.733201 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9525 17:35:15.739626 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9526 17:35:15.742724 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9527 17:35:15.746023 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9528 17:35:15.752843 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9529 17:35:15.756146 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9530 17:35:15.762646 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9531 17:35:15.766517 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9532 17:35:15.769310 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9533 17:35:15.776074 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9534 17:35:15.779249 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9535 17:35:15.782729 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9536 17:35:15.789886 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9537 17:35:15.792798 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9538 17:35:15.799423 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9539 17:35:15.802714 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9540 17:35:15.805836 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9541 17:35:15.812654 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9542 17:35:15.816235 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9543 17:35:15.819298 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9544 17:35:15.826053 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9545 17:35:15.829246 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9546 17:35:15.835847 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9547 17:35:15.839245 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9548 17:35:15.842661 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9549 17:35:15.849395 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9550 17:35:15.852774 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9551 17:35:15.859756 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9552 17:35:15.862688 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9553 17:35:15.866028 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9554 17:35:15.872348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9555 17:35:15.875975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9556 17:35:15.879140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9557 17:35:15.882728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9558 17:35:15.889106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9559 17:35:15.892643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9560 17:35:15.896148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9561 17:35:15.899090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9562 17:35:15.905741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9563 17:35:15.909434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9564 17:35:15.912855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9565 17:35:15.916508 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9566 17:35:15.922868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9567 17:35:15.926315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9568 17:35:15.929265 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9569 17:35:15.932337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9570 17:35:15.939328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9571 17:35:15.942532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9572 17:35:15.949309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9573 17:35:15.952647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9574 17:35:15.959242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9575 17:35:15.962292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9576 17:35:15.965932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9577 17:35:15.972492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9578 17:35:15.975887 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9579 17:35:15.982608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9580 17:35:15.986282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9581 17:35:15.992103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9582 17:35:15.995741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9583 17:35:15.999127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9584 17:35:16.005731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9585 17:35:16.009053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9586 17:35:16.015343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9587 17:35:16.018864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9588 17:35:16.025929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9589 17:35:16.029035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9590 17:35:16.032040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9591 17:35:16.038784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9592 17:35:16.042160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9593 17:35:16.048992 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9594 17:35:16.052401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9595 17:35:16.058886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9596 17:35:16.062200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9597 17:35:16.068972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9598 17:35:16.072378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9599 17:35:16.075866 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9600 17:35:16.082465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9601 17:35:16.085499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9602 17:35:16.092191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9603 17:35:16.095917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9604 17:35:16.102201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9605 17:35:16.105572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9606 17:35:16.108870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9607 17:35:16.116125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9608 17:35:16.118754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9609 17:35:16.125716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9610 17:35:16.128784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9611 17:35:16.136162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9612 17:35:16.139006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9613 17:35:16.142365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9614 17:35:16.148870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9615 17:35:16.152281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9616 17:35:16.158844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9617 17:35:16.162050 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9618 17:35:16.165563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9619 17:35:16.171832 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9620 17:35:16.175185 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9621 17:35:16.179021 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9622 17:35:16.181864 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9623 17:35:16.188575 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9624 17:35:16.191866 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9625 17:35:16.198545 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9626 17:35:16.202159 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9627 17:35:16.205637 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9628 17:35:16.212242 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9629 17:35:16.215187 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9630 17:35:16.222153 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9631 17:35:16.225663 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9632 17:35:16.229186 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9633 17:35:16.235817 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9634 17:35:16.239050 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9635 17:35:16.245732 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9636 17:35:16.249183 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9637 17:35:16.252308 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9638 17:35:16.258734 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9639 17:35:16.262405 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9640 17:35:16.265519 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9641 17:35:16.272207 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9642 17:35:16.275457 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9643 17:35:16.279010 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9644 17:35:16.282648 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9645 17:35:16.288851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9646 17:35:16.292307 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9647 17:35:16.295563 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9648 17:35:16.302144 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9649 17:35:16.305753 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9650 17:35:16.312055 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9651 17:35:16.315566 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9652 17:35:16.318515 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9653 17:35:16.325217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9654 17:35:16.328810 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9655 17:35:16.332462 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9656 17:35:16.338618 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9657 17:35:16.341912 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9658 17:35:16.348954 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9659 17:35:16.352240 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9660 17:35:16.355363 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9661 17:35:16.361704 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9662 17:35:16.365027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9663 17:35:16.371793 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9664 17:35:16.375137 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9665 17:35:16.378369 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9666 17:35:16.385258 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9667 17:35:16.388929 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9668 17:35:16.395231 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9669 17:35:16.398228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9670 17:35:16.401917 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9671 17:35:16.408074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9672 17:35:16.411418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9673 17:35:16.414840 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9674 17:35:16.421564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9675 17:35:16.424467 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9676 17:35:16.431520 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9677 17:35:16.434638 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9678 17:35:16.438220 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9679 17:35:16.444619 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9680 17:35:16.448320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9681 17:35:16.454595 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9682 17:35:16.457952 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9683 17:35:16.461297 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9684 17:35:16.467870 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9685 17:35:16.471364 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9686 17:35:16.477678 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9687 17:35:16.481071 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9688 17:35:16.484387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9689 17:35:16.490856 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9690 17:35:16.494640 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9691 17:35:16.500971 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9692 17:35:16.504519 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9693 17:35:16.507543 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9694 17:35:16.514136 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9695 17:35:16.517999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9696 17:35:16.524006 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9697 17:35:16.527668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9698 17:35:16.531134 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9699 17:35:16.537521 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9700 17:35:16.540806 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9701 17:35:16.544175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9702 17:35:16.550518 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9703 17:35:16.554104 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9704 17:35:16.560481 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9705 17:35:16.563706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9706 17:35:16.567245 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9707 17:35:16.573668 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9708 17:35:16.576959 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9709 17:35:16.583653 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9710 17:35:16.586890 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9711 17:35:16.593673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9712 17:35:16.597061 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9713 17:35:16.600045 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9714 17:35:16.606710 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9715 17:35:16.610371 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9716 17:35:16.617228 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9717 17:35:16.620110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9718 17:35:16.623272 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9719 17:35:16.629777 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9720 17:35:16.633528 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9721 17:35:16.639943 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9722 17:35:16.643524 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9723 17:35:16.650044 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9724 17:35:16.653005 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9725 17:35:16.656291 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9726 17:35:16.663245 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9727 17:35:16.666315 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9728 17:35:16.673102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9729 17:35:16.676158 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9730 17:35:16.682783 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9731 17:35:16.686251 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9732 17:35:16.689581 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9733 17:35:16.695913 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9734 17:35:16.699405 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9735 17:35:16.705879 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9736 17:35:16.709097 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9737 17:35:16.715960 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9738 17:35:16.719349 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9739 17:35:16.722555 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9740 17:35:16.729009 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9741 17:35:16.732691 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9742 17:35:16.738714 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9743 17:35:16.742149 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9744 17:35:16.745802 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9745 17:35:16.752580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9746 17:35:16.755893 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9747 17:35:16.762353 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9748 17:35:16.765320 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9749 17:35:16.772474 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9750 17:35:16.775534 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9751 17:35:16.778741 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9752 17:35:16.782064 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9753 17:35:16.788586 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9754 17:35:16.791840 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9755 17:35:16.795641 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9756 17:35:16.798816 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9757 17:35:16.805323 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9758 17:35:16.808970 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9759 17:35:16.815275 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9760 17:35:16.818417 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9761 17:35:16.821624 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9762 17:35:16.828542 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9763 17:35:16.831594 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9764 17:35:16.838733 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9765 17:35:16.841972 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9766 17:35:16.845388 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9767 17:35:16.851498 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9768 17:35:16.855239 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9769 17:35:16.858235 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9770 17:35:16.864727 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9771 17:35:16.867878 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9772 17:35:16.871785 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9773 17:35:16.878269 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9774 17:35:16.881305 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9775 17:35:16.884502 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9776 17:35:16.890997 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9777 17:35:16.894719 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9778 17:35:16.901147 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9779 17:35:16.904924 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9780 17:35:16.907916 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9781 17:35:16.914175 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9782 17:35:16.917635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9783 17:35:16.924183 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9784 17:35:16.927625 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9785 17:35:16.930891 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9786 17:35:16.937706 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9787 17:35:16.940982 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9788 17:35:16.944141 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9789 17:35:16.950606 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9790 17:35:16.954169 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9791 17:35:16.957158 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9792 17:35:16.964009 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9793 17:35:16.967421 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9794 17:35:16.970763 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9795 17:35:16.974211 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9796 17:35:16.977493 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9797 17:35:16.984187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9798 17:35:16.987371 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9799 17:35:16.990535 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9800 17:35:16.994118 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9801 17:35:17.000481 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9802 17:35:17.003821 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9803 17:35:17.007060 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9804 17:35:17.013623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9805 17:35:17.017411 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9806 17:35:17.023507 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9807 17:35:17.027035 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9808 17:35:17.030847 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9809 17:35:17.037053 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9810 17:35:17.040456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9811 17:35:17.046643 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9812 17:35:17.050436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9813 17:35:17.053663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9814 17:35:17.060138 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9815 17:35:17.063296 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9816 17:35:17.070774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9817 17:35:17.073636 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9818 17:35:17.079838 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9819 17:35:17.083604 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9820 17:35:17.086500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9821 17:35:17.093060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9822 17:35:17.096430 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9823 17:35:17.102890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9824 17:35:17.106720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9825 17:35:17.113355 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9826 17:35:17.116580 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9827 17:35:17.119518 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9828 17:35:17.126294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9829 17:35:17.129595 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9830 17:35:17.136281 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9831 17:35:17.139275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9832 17:35:17.142798 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9833 17:35:17.149358 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9834 17:35:17.152611 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9835 17:35:17.159413 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9836 17:35:17.163004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9837 17:35:17.166070 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9838 17:35:17.172574 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9839 17:35:17.175572 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9840 17:35:17.182483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9841 17:35:17.185368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9842 17:35:17.192514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9843 17:35:17.195543 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9844 17:35:17.198748 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9845 17:35:17.205363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9846 17:35:17.208899 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9847 17:35:17.215541 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9848 17:35:17.218592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9849 17:35:17.221831 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9850 17:35:17.228812 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9851 17:35:17.232138 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9852 17:35:17.238577 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9853 17:35:17.241715 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9854 17:35:17.245324 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9855 17:35:17.251867 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9856 17:35:17.254909 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9857 17:35:17.262253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9858 17:35:17.265162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9859 17:35:17.268293 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9860 17:35:17.274665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9861 17:35:17.278519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9862 17:35:17.285209 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9863 17:35:17.288263 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9864 17:35:17.294592 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9865 17:35:17.297655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9866 17:35:17.304757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9867 17:35:17.308032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9868 17:35:17.311139 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9869 17:35:17.317487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9870 17:35:17.321041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9871 17:35:17.327710 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9872 17:35:17.330988 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9873 17:35:17.334358 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9874 17:35:17.340978 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9875 17:35:17.344355 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9876 17:35:17.350903 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9877 17:35:17.353946 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9878 17:35:17.357305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9879 17:35:17.364095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9880 17:35:17.367218 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9881 17:35:17.374043 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9882 17:35:17.377505 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9883 17:35:17.383978 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9884 17:35:17.387148 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9885 17:35:17.393928 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9886 17:35:17.397580 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9887 17:35:17.400535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9888 17:35:17.407167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9889 17:35:17.410658 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9890 17:35:17.416860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9891 17:35:17.420201 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9892 17:35:17.426675 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9893 17:35:17.430435 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9894 17:35:17.437146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9895 17:35:17.439985 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9896 17:35:17.443816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9897 17:35:17.449972 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9898 17:35:17.453094 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9899 17:35:17.459959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9900 17:35:17.463030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9901 17:35:17.469718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9902 17:35:17.473462 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9903 17:35:17.480369 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9904 17:35:17.483038 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9905 17:35:17.486191 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9906 17:35:17.492986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9907 17:35:17.496366 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9908 17:35:17.503025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9909 17:35:17.506144 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9910 17:35:17.513506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9911 17:35:17.516120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9912 17:35:17.519352 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9913 17:35:17.525950 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9914 17:35:17.529425 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9915 17:35:17.536211 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9916 17:35:17.539375 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9917 17:35:17.545786 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9918 17:35:17.549305 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9919 17:35:17.555823 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9920 17:35:17.559270 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9921 17:35:17.562441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9922 17:35:17.569225 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9923 17:35:17.572529 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9924 17:35:17.579586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9925 17:35:17.582299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9926 17:35:17.585997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9927 17:35:17.592401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9928 17:35:17.595858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9929 17:35:17.602296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9930 17:35:17.605765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9931 17:35:17.612696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9932 17:35:17.615588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9933 17:35:17.622188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9934 17:35:17.625875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9935 17:35:17.632611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9936 17:35:17.635321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9937 17:35:17.642064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9938 17:35:17.645667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9939 17:35:17.652116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9940 17:35:17.655643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9941 17:35:17.662137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9942 17:35:17.665337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9943 17:35:17.671912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9944 17:35:17.675253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9945 17:35:17.682154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9946 17:35:17.685144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9947 17:35:17.691857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9948 17:35:17.695065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9949 17:35:17.702124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9950 17:35:17.704993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9951 17:35:17.711624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9952 17:35:17.714822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9953 17:35:17.721469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9954 17:35:17.724413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9955 17:35:17.731117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9956 17:35:17.734708 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9957 17:35:17.737743 INFO: [APUAPC] vio 0
9958 17:35:17.741392 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9959 17:35:17.748062 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9960 17:35:17.751017 INFO: [APUAPC] D0_APC_0: 0x400510
9961 17:35:17.751119 INFO: [APUAPC] D0_APC_1: 0x0
9962 17:35:17.754399 INFO: [APUAPC] D0_APC_2: 0x1540
9963 17:35:17.757820 INFO: [APUAPC] D0_APC_3: 0x0
9964 17:35:17.761023 INFO: [APUAPC] D1_APC_0: 0xffffffff
9965 17:35:17.764373 INFO: [APUAPC] D1_APC_1: 0xffffffff
9966 17:35:17.767604 INFO: [APUAPC] D1_APC_2: 0x3fffff
9967 17:35:17.771509 INFO: [APUAPC] D1_APC_3: 0x0
9968 17:35:17.774788 INFO: [APUAPC] D2_APC_0: 0xffffffff
9969 17:35:17.777734 INFO: [APUAPC] D2_APC_1: 0xffffffff
9970 17:35:17.781100 INFO: [APUAPC] D2_APC_2: 0x3fffff
9971 17:35:17.784438 INFO: [APUAPC] D2_APC_3: 0x0
9972 17:35:17.787356 INFO: [APUAPC] D3_APC_0: 0xffffffff
9973 17:35:17.791133 INFO: [APUAPC] D3_APC_1: 0xffffffff
9974 17:35:17.794149 INFO: [APUAPC] D3_APC_2: 0x3fffff
9975 17:35:17.797339 INFO: [APUAPC] D3_APC_3: 0x0
9976 17:35:17.800794 INFO: [APUAPC] D4_APC_0: 0xffffffff
9977 17:35:17.804005 INFO: [APUAPC] D4_APC_1: 0xffffffff
9978 17:35:17.807625 INFO: [APUAPC] D4_APC_2: 0x3fffff
9979 17:35:17.810930 INFO: [APUAPC] D4_APC_3: 0x0
9980 17:35:17.813948 INFO: [APUAPC] D5_APC_0: 0xffffffff
9981 17:35:17.817387 INFO: [APUAPC] D5_APC_1: 0xffffffff
9982 17:35:17.820607 INFO: [APUAPC] D5_APC_2: 0x3fffff
9983 17:35:17.823975 INFO: [APUAPC] D5_APC_3: 0x0
9984 17:35:17.827205 INFO: [APUAPC] D6_APC_0: 0xffffffff
9985 17:35:17.830458 INFO: [APUAPC] D6_APC_1: 0xffffffff
9986 17:35:17.833694 INFO: [APUAPC] D6_APC_2: 0x3fffff
9987 17:35:17.837314 INFO: [APUAPC] D6_APC_3: 0x0
9988 17:35:17.840453 INFO: [APUAPC] D7_APC_0: 0xffffffff
9989 17:35:17.844102 INFO: [APUAPC] D7_APC_1: 0xffffffff
9990 17:35:17.847058 INFO: [APUAPC] D7_APC_2: 0x3fffff
9991 17:35:17.850468 INFO: [APUAPC] D7_APC_3: 0x0
9992 17:35:17.853963 INFO: [APUAPC] D8_APC_0: 0xffffffff
9993 17:35:17.857606 INFO: [APUAPC] D8_APC_1: 0xffffffff
9994 17:35:17.860313 INFO: [APUAPC] D8_APC_2: 0x3fffff
9995 17:35:17.863812 INFO: [APUAPC] D8_APC_3: 0x0
9996 17:35:17.866992 INFO: [APUAPC] D9_APC_0: 0xffffffff
9997 17:35:17.870347 INFO: [APUAPC] D9_APC_1: 0xffffffff
9998 17:35:17.873684 INFO: [APUAPC] D9_APC_2: 0x3fffff
9999 17:35:17.876912 INFO: [APUAPC] D9_APC_3: 0x0
10000 17:35:17.880698 INFO: [APUAPC] D10_APC_0: 0xffffffff
10001 17:35:17.883832 INFO: [APUAPC] D10_APC_1: 0xffffffff
10002 17:35:17.887106 INFO: [APUAPC] D10_APC_2: 0x3fffff
10003 17:35:17.890135 INFO: [APUAPC] D10_APC_3: 0x0
10004 17:35:17.893542 INFO: [APUAPC] D11_APC_0: 0xffffffff
10005 17:35:17.896633 INFO: [APUAPC] D11_APC_1: 0xffffffff
10006 17:35:17.899859 INFO: [APUAPC] D11_APC_2: 0x3fffff
10007 17:35:17.903127 INFO: [APUAPC] D11_APC_3: 0x0
10008 17:35:17.906549 INFO: [APUAPC] D12_APC_0: 0xffffffff
10009 17:35:17.909994 INFO: [APUAPC] D12_APC_1: 0xffffffff
10010 17:35:17.913285 INFO: [APUAPC] D12_APC_2: 0x3fffff
10011 17:35:17.916524 INFO: [APUAPC] D12_APC_3: 0x0
10012 17:35:17.919760 INFO: [APUAPC] D13_APC_0: 0xffffffff
10013 17:35:17.923026 INFO: [APUAPC] D13_APC_1: 0xffffffff
10014 17:35:17.926379 INFO: [APUAPC] D13_APC_2: 0x3fffff
10015 17:35:17.929990 INFO: [APUAPC] D13_APC_3: 0x0
10016 17:35:17.932901 INFO: [APUAPC] D14_APC_0: 0xffffffff
10017 17:35:17.936549 INFO: [APUAPC] D14_APC_1: 0xffffffff
10018 17:35:17.939473 INFO: [APUAPC] D14_APC_2: 0x3fffff
10019 17:35:17.942789 INFO: [APUAPC] D14_APC_3: 0x0
10020 17:35:17.946233 INFO: [APUAPC] D15_APC_0: 0xffffffff
10021 17:35:17.950075 INFO: [APUAPC] D15_APC_1: 0xffffffff
10022 17:35:17.952974 INFO: [APUAPC] D15_APC_2: 0x3fffff
10023 17:35:17.956186 INFO: [APUAPC] D15_APC_3: 0x0
10024 17:35:17.959818 INFO: [APUAPC] APC_CON: 0x4
10025 17:35:17.962698 INFO: [NOCDAPC] D0_APC_0: 0x0
10026 17:35:17.962828 INFO: [NOCDAPC] D0_APC_1: 0x0
10027 17:35:17.966167 INFO: [NOCDAPC] D1_APC_0: 0x0
10028 17:35:17.969544 INFO: [NOCDAPC] D1_APC_1: 0xfff
10029 17:35:17.972635 INFO: [NOCDAPC] D2_APC_0: 0x0
10030 17:35:17.976243 INFO: [NOCDAPC] D2_APC_1: 0xfff
10031 17:35:17.979158 INFO: [NOCDAPC] D3_APC_0: 0x0
10032 17:35:17.982680 INFO: [NOCDAPC] D3_APC_1: 0xfff
10033 17:35:17.986133 INFO: [NOCDAPC] D4_APC_0: 0x0
10034 17:35:17.989266 INFO: [NOCDAPC] D4_APC_1: 0xfff
10035 17:35:17.992399 INFO: [NOCDAPC] D5_APC_0: 0x0
10036 17:35:17.995820 INFO: [NOCDAPC] D5_APC_1: 0xfff
10037 17:35:17.999350 INFO: [NOCDAPC] D6_APC_0: 0x0
10038 17:35:17.999494 INFO: [NOCDAPC] D6_APC_1: 0xfff
10039 17:35:18.002728 INFO: [NOCDAPC] D7_APC_0: 0x0
10040 17:35:18.005660 INFO: [NOCDAPC] D7_APC_1: 0xfff
10041 17:35:18.009529 INFO: [NOCDAPC] D8_APC_0: 0x0
10042 17:35:18.012562 INFO: [NOCDAPC] D8_APC_1: 0xfff
10043 17:35:18.016090 INFO: [NOCDAPC] D9_APC_0: 0x0
10044 17:35:18.018797 INFO: [NOCDAPC] D9_APC_1: 0xfff
10045 17:35:18.022476 INFO: [NOCDAPC] D10_APC_0: 0x0
10046 17:35:18.025693 INFO: [NOCDAPC] D10_APC_1: 0xfff
10047 17:35:18.028585 INFO: [NOCDAPC] D11_APC_0: 0x0
10048 17:35:18.032074 INFO: [NOCDAPC] D11_APC_1: 0xfff
10049 17:35:18.035483 INFO: [NOCDAPC] D12_APC_0: 0x0
10050 17:35:18.039014 INFO: [NOCDAPC] D12_APC_1: 0xfff
10051 17:35:18.042112 INFO: [NOCDAPC] D13_APC_0: 0x0
10052 17:35:18.042231 INFO: [NOCDAPC] D13_APC_1: 0xfff
10053 17:35:18.045699 INFO: [NOCDAPC] D14_APC_0: 0x0
10054 17:35:18.049033 INFO: [NOCDAPC] D14_APC_1: 0xfff
10055 17:35:18.051887 INFO: [NOCDAPC] D15_APC_0: 0x0
10056 17:35:18.055362 INFO: [NOCDAPC] D15_APC_1: 0xfff
10057 17:35:18.058479 INFO: [NOCDAPC] APC_CON: 0x4
10058 17:35:18.062176 INFO: [APUAPC] set_apusys_apc done
10059 17:35:18.064980 INFO: [DEVAPC] devapc_init done
10060 17:35:18.068692 INFO: GICv3 without legacy support detected.
10061 17:35:18.072119 INFO: ARM GICv3 driver initialized in EL3
10062 17:35:18.078382 INFO: Maximum SPI INTID supported: 639
10063 17:35:18.081565 INFO: BL31: Initializing runtime services
10064 17:35:18.088607 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10065 17:35:18.088758 INFO: SPM: enable CPC mode
10066 17:35:18.095093 INFO: mcdi ready for mcusys-off-idle and system suspend
10067 17:35:18.098473 INFO: BL31: Preparing for EL3 exit to normal world
10068 17:35:18.102036 INFO: Entry point address = 0x80000000
10069 17:35:18.105152 INFO: SPSR = 0x8
10070 17:35:18.111190
10071 17:35:18.111326
10072 17:35:18.111433
10073 17:35:18.114407 Starting depthcharge on Spherion...
10074 17:35:18.114507
10075 17:35:18.114603 Wipe memory regions:
10076 17:35:18.114691
10077 17:35:18.115568 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10078 17:35:18.115677 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10079 17:35:18.116018 Setting prompt string to ['asurada:']
10080 17:35:18.116101 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10081 17:35:18.117542 [0x00000040000000, 0x00000054600000)
10082 17:35:18.239609
10083 17:35:18.239770 [0x00000054660000, 0x00000080000000)
10084 17:35:18.500881
10085 17:35:18.501017 [0x000000821a7280, 0x000000ffe64000)
10086 17:35:19.245298
10087 17:35:19.245452 [0x00000100000000, 0x00000240000000)
10088 17:35:21.135703
10089 17:35:21.138499 Initializing XHCI USB controller at 0x11200000.
10090 17:35:22.177455
10091 17:35:22.180886 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10092 17:35:22.180983
10093 17:35:22.181045
10094 17:35:22.181105
10095 17:35:22.181390 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 17:35:22.281761 asurada: tftpboot 192.168.201.1 11518300/tftp-deploy-6ezufo9_/kernel/image.itb 11518300/tftp-deploy-6ezufo9_/kernel/cmdline
10098 17:35:22.281938 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 17:35:22.282051 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10100 17:35:22.286495 tftpboot 192.168.201.1 11518300/tftp-deploy-6ezufo9_/kernel/image.itp-deploy-6ezufo9_/kernel/cmdline
10101 17:35:22.286592
10102 17:35:22.286658 Waiting for link
10103 17:35:22.446885
10104 17:35:22.447072 R8152: Initializing
10105 17:35:22.447170
10106 17:35:22.450084 Version 6 (ocp_data = 5c30)
10107 17:35:22.450168
10108 17:35:22.453390 R8152: Done initializing
10109 17:35:22.453475
10110 17:35:22.453540 Adding net device
10111 17:35:24.309517
10112 17:35:24.309671 done.
10113 17:35:24.309743
10114 17:35:24.309803 MAC: 00:24:32:30:78:ff
10115 17:35:24.309861
10116 17:35:24.312917 Sending DHCP discover... done.
10117 17:35:24.313000
10118 17:35:24.316194 Waiting for reply... done.
10119 17:35:24.316275
10120 17:35:24.319348 Sending DHCP request... done.
10121 17:35:24.319465
10122 17:35:24.319607 Waiting for reply... done.
10123 17:35:24.319669
10124 17:35:24.322892 My ip is 192.168.201.21
10125 17:35:24.322973
10126 17:35:24.326097 The DHCP server ip is 192.168.201.1
10127 17:35:24.326178
10128 17:35:24.329314 TFTP server IP predefined by user: 192.168.201.1
10129 17:35:24.329395
10130 17:35:24.336246 Bootfile predefined by user: 11518300/tftp-deploy-6ezufo9_/kernel/image.itb
10131 17:35:24.336330
10132 17:35:24.339607 Sending tftp read request... done.
10133 17:35:24.339688
10134 17:35:24.342868 Waiting for the transfer...
10135 17:35:24.342950
10136 17:35:24.942000 00000000 ################################################################
10137 17:35:24.942187
10138 17:35:25.566852 00080000 ################################################################
10139 17:35:25.566996
10140 17:35:26.159913 00100000 ################################################################
10141 17:35:26.160062
10142 17:35:26.752255 00180000 ################################################################
10143 17:35:26.752398
10144 17:35:27.351008 00200000 ################################################################
10145 17:35:27.351157
10146 17:35:27.952252 00280000 ################################################################
10147 17:35:27.952405
10148 17:35:28.551394 00300000 ################################################################
10149 17:35:28.551546
10150 17:35:29.135261 00380000 ################################################################
10151 17:35:29.135478
10152 17:35:29.693082 00400000 ################################################################
10153 17:35:29.693229
10154 17:35:30.289559 00480000 ################################################################
10155 17:35:30.289714
10156 17:35:30.888722 00500000 ################################################################
10157 17:35:30.888865
10158 17:35:31.484734 00580000 ################################################################
10159 17:35:31.484972
10160 17:35:32.081046 00600000 ################################################################
10161 17:35:32.081201
10162 17:35:32.670306 00680000 ################################################################
10163 17:35:32.670474
10164 17:35:33.218722 00700000 ################################################################
10165 17:35:33.218884
10166 17:35:33.762375 00780000 ################################################################
10167 17:35:33.762532
10168 17:35:34.358368 00800000 ################################################################
10169 17:35:34.358799
10170 17:35:34.917637 00880000 ################################################################
10171 17:35:34.917937
10172 17:35:35.546983 00900000 ################################################################
10173 17:35:35.547138
10174 17:35:36.171364 00980000 ################################################################
10175 17:35:36.171776
10176 17:35:36.876894 00a00000 ################################################################
10177 17:35:36.877397
10178 17:35:37.586908 00a80000 ################################################################
10179 17:35:37.587460
10180 17:35:38.311046 00b00000 ################################################################
10181 17:35:38.311198
10182 17:35:38.941430 00b80000 ################################################################
10183 17:35:38.941961
10184 17:35:39.648846 00c00000 ################################################################
10185 17:35:39.648995
10186 17:35:40.197448 00c80000 ################################################################
10187 17:35:40.197603
10188 17:35:40.766879 00d00000 ################################################################
10189 17:35:40.767378
10190 17:35:41.493290 00d80000 ################################################################
10191 17:35:41.493810
10192 17:35:42.230664 00e00000 ################################################################
10193 17:35:42.231207
10194 17:35:42.964617 00e80000 ################################################################
10195 17:35:42.965138
10196 17:35:43.666396 00f00000 ################################################################
10197 17:35:43.666969
10198 17:35:44.404056 00f80000 ################################################################
10199 17:35:44.404594
10200 17:35:45.018519 01000000 ################################################################
10201 17:35:45.018670
10202 17:35:45.727423 01080000 ################################################################
10203 17:35:45.727958
10204 17:35:46.460212 01100000 ################################################################
10205 17:35:46.460742
10206 17:35:47.187023 01180000 ################################################################
10207 17:35:47.187544
10208 17:35:47.906654 01200000 ################################################################
10209 17:35:47.907196
10210 17:35:48.636430 01280000 ################################################################
10211 17:35:48.636940
10212 17:35:49.293372 01300000 ################################################################
10213 17:35:49.293918
10214 17:35:49.992201 01380000 ################################################################
10215 17:35:49.992712
10216 17:35:50.716343 01400000 ################################################################
10217 17:35:50.716876
10218 17:35:51.442247 01480000 ################################################################
10219 17:35:51.442750
10220 17:35:52.143091 01500000 ################################################################
10221 17:35:52.143622
10222 17:35:52.862760 01580000 ################################################################
10223 17:35:52.863269
10224 17:35:53.563909 01600000 ################################################################
10225 17:35:53.564403
10226 17:35:54.281273 01680000 ################################################################
10227 17:35:54.281775
10228 17:35:55.012008 01700000 ################################################################
10229 17:35:55.012523
10230 17:35:55.574429 01780000 ################################################################
10231 17:35:55.574575
10232 17:35:56.122481 01800000 ################################################################
10233 17:35:56.122619
10234 17:35:56.672829 01880000 ################################################################
10235 17:35:56.673003
10236 17:35:57.221630 01900000 ################################################################
10237 17:35:57.221793
10238 17:35:57.784241 01980000 ################################################################
10239 17:35:57.784395
10240 17:35:58.350139 01a00000 ################################################################
10241 17:35:58.350289
10242 17:35:58.911854 01a80000 ################################################################
10243 17:35:58.911999
10244 17:35:59.476573 01b00000 ################################################################
10245 17:35:59.476725
10246 17:35:59.522391 01b80000 ###### done.
10247 17:35:59.522492
10248 17:35:59.525854 The bootfile was 28877010 bytes long.
10249 17:35:59.525940
10250 17:35:59.529107 Sending tftp read request... done.
10251 17:35:59.529221
10252 17:35:59.529286 Waiting for the transfer...
10253 17:35:59.529346
10254 17:35:59.532559 00000000 # done.
10255 17:35:59.532643
10256 17:35:59.538811 Command line loaded dynamically from TFTP file: 11518300/tftp-deploy-6ezufo9_/kernel/cmdline
10257 17:35:59.538895
10258 17:35:59.562350 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10259 17:35:59.562440
10260 17:35:59.562506 Loading FIT.
10261 17:35:59.562566
10262 17:35:59.565190 Image ramdisk-1 has 17788448 bytes.
10263 17:35:59.565272
10264 17:35:59.568463 Image fdt-1 has 47278 bytes.
10265 17:35:59.568544
10266 17:35:59.572279 Image kernel-1 has 11039249 bytes.
10267 17:35:59.572361
10268 17:35:59.582204 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10269 17:35:59.582287
10270 17:35:59.598547 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10271 17:35:59.598635
10272 17:35:59.604909 Choosing best match conf-1 for compat google,spherion-rev2.
10273 17:35:59.604990
10274 17:35:59.612696 Connected to device vid:did:rid of 1ae0:0028:00
10275 17:35:59.620906
10276 17:35:59.624460 tpm_get_response: command 0x17b, return code 0x0
10277 17:35:59.624542
10278 17:35:59.627607 ec_init: CrosEC protocol v3 supported (256, 248)
10279 17:35:59.631610
10280 17:35:59.634990 tpm_cleanup: add release locality here.
10281 17:35:59.635070
10282 17:35:59.635134 Shutting down all USB controllers.
10283 17:35:59.637879
10284 17:35:59.637961 Removing current net device
10285 17:35:59.638025
10286 17:35:59.644888 Exiting depthcharge with code 4 at timestamp: 70803079
10287 17:35:59.644969
10288 17:35:59.648248 LZMA decompressing kernel-1 to 0x821a6718
10289 17:35:59.648394
10290 17:35:59.651258 LZMA decompressing kernel-1 to 0x40000000
10291 17:36:01.042137
10292 17:36:01.042275 jumping to kernel
10293 17:36:01.042719 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10294 17:36:01.042829 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10295 17:36:01.042908 Setting prompt string to ['Linux version [0-9]']
10296 17:36:01.042979 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10297 17:36:01.043048 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10298 17:36:01.124417
10299 17:36:01.127227 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10300 17:36:01.130539 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10301 17:36:01.130707 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10302 17:36:01.130811 Setting prompt string to []
10303 17:36:01.130914 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10304 17:36:01.131001 Using line separator: #'\n'#
10305 17:36:01.131077 No login prompt set.
10306 17:36:01.131176 Parsing kernel messages
10307 17:36:01.131271 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10308 17:36:01.131501 [login-action] Waiting for messages, (timeout 00:03:42)
10309 17:36:01.150180 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j44859-arm64-gcc-10-defconfig-arm64-chromebook-gptb4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023
10310 17:36:01.153568 [ 0.000000] random: crng init done
10311 17:36:01.160041 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 17:36:01.163562 [ 0.000000] efi: UEFI not found.
10313 17:36:01.170297 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 17:36:01.176741 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 17:36:01.186791 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 17:36:01.196629 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 17:36:01.203221 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 17:36:01.209684 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 17:36:01.216984 [ 0.000000] NUMA: No NUMA configuration found
10320 17:36:01.223144 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 17:36:01.226138 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10322 17:36:01.229864 [ 0.000000] Zone ranges:
10323 17:36:01.236436 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 17:36:01.239354 [ 0.000000] DMA32 empty
10325 17:36:01.246416 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 17:36:01.249486 [ 0.000000] Movable zone start for each node
10327 17:36:01.253113 [ 0.000000] Early memory node ranges
10328 17:36:01.259558 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 17:36:01.266152 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 17:36:01.272743 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 17:36:01.279359 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 17:36:01.282383 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 17:36:01.293001 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 17:36:01.348450 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 17:36:01.355177 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 17:36:01.361694 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 17:36:01.364809 [ 0.000000] psci: probing for conduit method from DT.
10338 17:36:01.371711 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 17:36:01.374533 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 17:36:01.381095 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 17:36:01.384633 [ 0.000000] psci: SMC Calling Convention v1.2
10342 17:36:01.390986 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10343 17:36:01.394360 [ 0.000000] Detected VIPT I-cache on CPU0
10344 17:36:01.400947 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 17:36:01.407911 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 17:36:01.414350 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 17:36:01.420942 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 17:36:01.431146 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 17:36:01.437546 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 17:36:01.440596 [ 0.000000] alternatives: applying boot alternatives
10351 17:36:01.447155 [ 0.000000] Fallback order for Node 0: 0
10352 17:36:01.453710 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 17:36:01.457306 [ 0.000000] Policy zone: Normal
10354 17:36:01.480142 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10355 17:36:01.489944 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 17:36:01.500607 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 17:36:01.510885 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 17:36:01.516985 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 17:36:01.520482 <6>[ 0.000000] software IO TLB: area num 8.
10360 17:36:01.576873 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 17:36:01.726506 <6>[ 0.000000] Memory: 7952120K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 400648K reserved, 32768K cma-reserved)
10362 17:36:01.732856 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 17:36:01.739873 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 17:36:01.742948 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 17:36:01.749474 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 17:36:01.756222 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 17:36:01.759749 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 17:36:01.769377 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 17:36:01.776042 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 17:36:01.783094 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 17:36:01.789358 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 17:36:01.792965 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 17:36:01.796296 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 17:36:01.802729 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 17:36:01.806104 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 17:36:01.812404 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 17:36:01.826024 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 17:36:01.839275 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 17:36:01.845660 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 17:36:01.853043 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 17:36:01.866384 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 17:36:01.872855 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 17:36:01.879820 <6>[ 0.009182] Console: colour dummy device 80x25
10384 17:36:01.889258 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 17:36:01.896316 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10386 17:36:01.899488 <6>[ 0.029223] LSM: Security Framework initializing
10387 17:36:01.905914 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 17:36:01.915716 <6>[ 0.042005] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 17:36:01.925498 <6>[ 0.051417] cblist_init_generic: Setting adjustable number of callback queues.
10390 17:36:01.928918 <6>[ 0.058859] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 17:36:01.938973 <6>[ 0.065198] cblist_init_generic: Setting adjustable number of callback queues.
10392 17:36:01.945642 <6>[ 0.072625] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 17:36:01.949098 <6>[ 0.079026] rcu: Hierarchical SRCU implementation.
10394 17:36:01.955761 <6>[ 0.084041] rcu: Max phase no-delay instances is 1000.
10395 17:36:01.961862 <6>[ 0.091062] EFI services will not be available.
10396 17:36:01.965122 <6>[ 0.096017] smp: Bringing up secondary CPUs ...
10397 17:36:01.974037 <6>[ 0.101065] Detected VIPT I-cache on CPU1
10398 17:36:01.980319 <6>[ 0.101134] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10399 17:36:01.986921 <6>[ 0.101163] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10400 17:36:01.990308 <6>[ 0.101498] Detected VIPT I-cache on CPU2
10401 17:36:01.996808 <6>[ 0.101552] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10402 17:36:02.003595 <6>[ 0.101568] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10403 17:36:02.010344 <6>[ 0.101824] Detected VIPT I-cache on CPU3
10404 17:36:02.016998 <6>[ 0.101869] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10405 17:36:02.023139 <6>[ 0.101883] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10406 17:36:02.026779 <6>[ 0.102183] CPU features: detected: Spectre-v4
10407 17:36:02.033406 <6>[ 0.102189] CPU features: detected: Spectre-BHB
10408 17:36:02.036885 <6>[ 0.102194] Detected PIPT I-cache on CPU4
10409 17:36:02.043342 <6>[ 0.102251] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10410 17:36:02.049930 <6>[ 0.102269] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10411 17:36:02.056775 <6>[ 0.102562] Detected PIPT I-cache on CPU5
10412 17:36:02.063373 <6>[ 0.102625] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10413 17:36:02.069505 <6>[ 0.102641] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10414 17:36:02.072844 <6>[ 0.102919] Detected PIPT I-cache on CPU6
10415 17:36:02.079976 <6>[ 0.102983] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10416 17:36:02.086084 <6>[ 0.102999] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10417 17:36:02.092659 <6>[ 0.103294] Detected PIPT I-cache on CPU7
10418 17:36:02.099571 <6>[ 0.103358] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10419 17:36:02.106079 <6>[ 0.103375] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10420 17:36:02.109126 <6>[ 0.103422] smp: Brought up 1 node, 8 CPUs
10421 17:36:02.116119 <6>[ 0.244748] SMP: Total of 8 processors activated.
10422 17:36:02.119140 <6>[ 0.249699] CPU features: detected: 32-bit EL0 Support
10423 17:36:02.129143 <6>[ 0.255095] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10424 17:36:02.135728 <6>[ 0.263895] CPU features: detected: Common not Private translations
10425 17:36:02.142508 <6>[ 0.270371] CPU features: detected: CRC32 instructions
10426 17:36:02.145547 <6>[ 0.275723] CPU features: detected: RCpc load-acquire (LDAPR)
10427 17:36:02.152555 <6>[ 0.281683] CPU features: detected: LSE atomic instructions
10428 17:36:02.159109 <6>[ 0.287464] CPU features: detected: Privileged Access Never
10429 17:36:02.165582 <6>[ 0.293244] CPU features: detected: RAS Extension Support
10430 17:36:02.172523 <6>[ 0.298853] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10431 17:36:02.175824 <6>[ 0.306117] CPU: All CPU(s) started at EL2
10432 17:36:02.182331 <6>[ 0.310434] alternatives: applying system-wide alternatives
10433 17:36:02.191296 <6>[ 0.321152] devtmpfs: initialized
10434 17:36:02.206758 <6>[ 0.330046] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10435 17:36:02.213361 <6>[ 0.340006] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10436 17:36:02.220386 <6>[ 0.348021] pinctrl core: initialized pinctrl subsystem
10437 17:36:02.223328 <6>[ 0.354679] DMI not present or invalid.
10438 17:36:02.230089 <6>[ 0.359089] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10439 17:36:02.240129 <6>[ 0.365954] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10440 17:36:02.246326 <6>[ 0.373536] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10441 17:36:02.256324 <6>[ 0.381750] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10442 17:36:02.259822 <6>[ 0.389994] audit: initializing netlink subsys (disabled)
10443 17:36:02.269700 <5>[ 0.395684] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10444 17:36:02.276653 <6>[ 0.396394] thermal_sys: Registered thermal governor 'step_wise'
10445 17:36:02.282879 <6>[ 0.403652] thermal_sys: Registered thermal governor 'power_allocator'
10446 17:36:02.286388 <6>[ 0.409908] cpuidle: using governor menu
10447 17:36:02.293025 <6>[ 0.420871] NET: Registered PF_QIPCRTR protocol family
10448 17:36:02.299278 <6>[ 0.426364] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10449 17:36:02.305916 <6>[ 0.433468] ASID allocator initialised with 32768 entries
10450 17:36:02.309043 <6>[ 0.440045] Serial: AMBA PL011 UART driver
10451 17:36:02.319418 <4>[ 0.448815] Trying to register duplicate clock ID: 134
10452 17:36:02.373604 <6>[ 0.506187] KASLR enabled
10453 17:36:02.387360 <6>[ 0.513887] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 17:36:02.394546 <6>[ 0.520899] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 17:36:02.401077 <6>[ 0.527389] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 17:36:02.407363 <6>[ 0.534395] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 17:36:02.413941 <6>[ 0.540882] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 17:36:02.420622 <6>[ 0.547887] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 17:36:02.427360 <6>[ 0.554376] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 17:36:02.433853 <6>[ 0.561381] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 17:36:02.436838 <6>[ 0.568831] ACPI: Interpreter disabled.
10462 17:36:02.445590 <6>[ 0.575282] iommu: Default domain type: Translated
10463 17:36:02.452196 <6>[ 0.580396] iommu: DMA domain TLB invalidation policy: strict mode
10464 17:36:02.455735 <5>[ 0.587054] SCSI subsystem initialized
10465 17:36:02.461954 <6>[ 0.591300] usbcore: registered new interface driver usbfs
10466 17:36:02.468718 <6>[ 0.597030] usbcore: registered new interface driver hub
10467 17:36:02.471774 <6>[ 0.602583] usbcore: registered new device driver usb
10468 17:36:02.478782 <6>[ 0.608699] pps_core: LinuxPPS API ver. 1 registered
10469 17:36:02.488802 <6>[ 0.613892] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10470 17:36:02.492062 <6>[ 0.623235] PTP clock support registered
10471 17:36:02.495216 <6>[ 0.627478] EDAC MC: Ver: 3.0.0
10472 17:36:02.503300 <6>[ 0.632671] FPGA manager framework
10473 17:36:02.509576 <6>[ 0.636349] Advanced Linux Sound Architecture Driver Initialized.
10474 17:36:02.512665 <6>[ 0.643116] vgaarb: loaded
10475 17:36:02.519763 <6>[ 0.646272] clocksource: Switched to clocksource arch_sys_counter
10476 17:36:02.522630 <5>[ 0.652718] VFS: Disk quotas dquot_6.6.0
10477 17:36:02.529549 <6>[ 0.656907] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10478 17:36:02.532541 <6>[ 0.664100] pnp: PnP ACPI: disabled
10479 17:36:02.541465 <6>[ 0.670798] NET: Registered PF_INET protocol family
10480 17:36:02.550804 <6>[ 0.676388] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10481 17:36:02.562396 <6>[ 0.688703] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10482 17:36:02.571933 <6>[ 0.697516] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10483 17:36:02.578536 <6>[ 0.705488] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10484 17:36:02.588679 <6>[ 0.714186] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10485 17:36:02.595607 <6>[ 0.723930] TCP: Hash tables configured (established 65536 bind 65536)
10486 17:36:02.601614 <6>[ 0.730795] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 17:36:02.611511 <6>[ 0.737995] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 17:36:02.618034 <6>[ 0.745699] NET: Registered PF_UNIX/PF_LOCAL protocol family
10489 17:36:02.625221 <6>[ 0.751877] RPC: Registered named UNIX socket transport module.
10490 17:36:02.628074 <6>[ 0.758031] RPC: Registered udp transport module.
10491 17:36:02.635130 <6>[ 0.762964] RPC: Registered tcp transport module.
10492 17:36:02.641480 <6>[ 0.767895] RPC: Registered tcp NFSv4.1 backchannel transport module.
10493 17:36:02.644971 <6>[ 0.774565] PCI: CLS 0 bytes, default 64
10494 17:36:02.647611 <6>[ 0.778974] Unpacking initramfs...
10495 17:36:02.672075 <6>[ 0.798384] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10496 17:36:02.681974 <6>[ 0.807055] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10497 17:36:02.685095 <6>[ 0.815918] kvm [1]: IPA Size Limit: 40 bits
10498 17:36:02.692221 <6>[ 0.820443] kvm [1]: GICv3: no GICV resource entry
10499 17:36:02.695155 <6>[ 0.825467] kvm [1]: disabling GICv2 emulation
10500 17:36:02.701703 <6>[ 0.830151] kvm [1]: GIC system register CPU interface enabled
10501 17:36:02.704979 <6>[ 0.836309] kvm [1]: vgic interrupt IRQ18
10502 17:36:02.712279 <6>[ 0.840665] kvm [1]: VHE mode initialized successfully
10503 17:36:02.718266 <5>[ 0.847118] Initialise system trusted keyrings
10504 17:36:02.724772 <6>[ 0.851992] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10505 17:36:02.732463 <6>[ 0.862049] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10506 17:36:02.739446 <5>[ 0.868466] NFS: Registering the id_resolver key type
10507 17:36:02.742414 <5>[ 0.873770] Key type id_resolver registered
10508 17:36:02.748995 <5>[ 0.878184] Key type id_legacy registered
10509 17:36:02.755367 <6>[ 0.882458] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10510 17:36:02.762262 <6>[ 0.889381] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10511 17:36:02.768701 <6>[ 0.897081] 9p: Installing v9fs 9p2000 file system support
10512 17:36:02.804716 <5>[ 0.934217] Key type asymmetric registered
10513 17:36:02.808230 <5>[ 0.938548] Asymmetric key parser 'x509' registered
10514 17:36:02.818352 <6>[ 0.943702] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10515 17:36:02.821249 <6>[ 0.951335] io scheduler mq-deadline registered
10516 17:36:02.824803 <6>[ 0.956098] io scheduler kyber registered
10517 17:36:02.843450 <6>[ 0.972938] EINJ: ACPI disabled.
10518 17:36:02.875580 <4>[ 0.998244] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 17:36:02.885492 <4>[ 1.008875] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 17:36:02.899812 <6>[ 1.029283] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10521 17:36:02.908090 <6>[ 1.037191] printk: console [ttyS0] disabled
10522 17:36:02.936078 <6>[ 1.061840] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10523 17:36:02.942051 <6>[ 1.071314] printk: console [ttyS0] enabled
10524 17:36:02.945843 <6>[ 1.071314] printk: console [ttyS0] enabled
10525 17:36:02.952617 <6>[ 1.080210] printk: bootconsole [mtk8250] disabled
10526 17:36:02.955543 <6>[ 1.080210] printk: bootconsole [mtk8250] disabled
10527 17:36:02.962388 <6>[ 1.091455] SuperH (H)SCI(F) driver initialized
10528 17:36:02.965868 <6>[ 1.096734] msm_serial: driver initialized
10529 17:36:02.979513 <6>[ 1.105704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10530 17:36:02.989840 <6>[ 1.114254] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10531 17:36:02.996014 <6>[ 1.122794] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10532 17:36:03.006475 <6>[ 1.131423] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10533 17:36:03.016273 <6>[ 1.140130] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10534 17:36:03.022514 <6>[ 1.148842] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10535 17:36:03.032776 <6>[ 1.157393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10536 17:36:03.039347 <6>[ 1.166187] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10537 17:36:03.049321 <6>[ 1.174731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10538 17:36:03.061122 <6>[ 1.190538] loop: module loaded
10539 17:36:03.067493 <6>[ 1.196545] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10540 17:36:03.090390 <4>[ 1.219886] mtk-pmic-keys: Failed to locate of_node [id: -1]
10541 17:36:03.097207 <6>[ 1.226783] megasas: 07.719.03.00-rc1
10542 17:36:03.107083 <6>[ 1.236413] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10543 17:36:03.120349 <6>[ 1.249655] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10544 17:36:03.137097 <6>[ 1.266260] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10545 17:36:03.193145 <6>[ 1.315681] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10546 17:36:03.402177 <6>[ 1.531798] Freeing initrd memory: 17368K
10547 17:36:03.413016 <6>[ 1.542203] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10548 17:36:03.423978 <6>[ 1.553155] tun: Universal TUN/TAP device driver, 1.6
10549 17:36:03.427291 <6>[ 1.559233] thunder_xcv, ver 1.0
10550 17:36:03.430154 <6>[ 1.562740] thunder_bgx, ver 1.0
10551 17:36:03.433686 <6>[ 1.566230] nicpf, ver 1.0
10552 17:36:03.443863 <6>[ 1.570255] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10553 17:36:03.447343 <6>[ 1.577731] hns3: Copyright (c) 2017 Huawei Corporation.
10554 17:36:03.454037 <6>[ 1.583319] hclge is initializing
10555 17:36:03.456984 <6>[ 1.586901] e1000: Intel(R) PRO/1000 Network Driver
10556 17:36:03.464092 <6>[ 1.592030] e1000: Copyright (c) 1999-2006 Intel Corporation.
10557 17:36:03.466795 <6>[ 1.598042] e1000e: Intel(R) PRO/1000 Network Driver
10558 17:36:03.473887 <6>[ 1.603258] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10559 17:36:03.480128 <6>[ 1.609447] igb: Intel(R) Gigabit Ethernet Network Driver
10560 17:36:03.486789 <6>[ 1.615096] igb: Copyright (c) 2007-2014 Intel Corporation.
10561 17:36:03.493616 <6>[ 1.620936] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 17:36:03.499888 <6>[ 1.627454] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 17:36:03.503201 <6>[ 1.633914] sky2: driver version 1.30
10564 17:36:03.510306 <6>[ 1.638914] VFIO - User Level meta-driver version: 0.3
10565 17:36:03.517815 <6>[ 1.647155] usbcore: registered new interface driver usb-storage
10566 17:36:03.524287 <6>[ 1.653604] usbcore: registered new device driver onboard-usb-hub
10567 17:36:03.532957 <6>[ 1.662725] mt6397-rtc mt6359-rtc: registered as rtc0
10568 17:36:03.543217 <6>[ 1.668187] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-13T17:36:03 UTC (1694626563)
10569 17:36:03.546690 <6>[ 1.677768] i2c_dev: i2c /dev entries driver
10570 17:36:03.563478 <6>[ 1.689427] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10571 17:36:03.583174 <6>[ 1.712418] cpu cpu0: EM: created perf domain
10572 17:36:03.586018 <6>[ 1.717335] cpu cpu4: EM: created perf domain
10573 17:36:03.593524 <6>[ 1.722957] sdhci: Secure Digital Host Controller Interface driver
10574 17:36:03.599885 <6>[ 1.729388] sdhci: Copyright(c) Pierre Ossman
10575 17:36:03.607157 <6>[ 1.734334] Synopsys Designware Multimedia Card Interface Driver
10576 17:36:03.613556 <6>[ 1.740964] sdhci-pltfm: SDHCI platform and OF driver helper
10577 17:36:03.616942 <6>[ 1.741012] mmc0: CQHCI version 5.10
10578 17:36:03.623579 <6>[ 1.750966] ledtrig-cpu: registered to indicate activity on CPUs
10579 17:36:03.630025 <6>[ 1.757957] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10580 17:36:03.636460 <6>[ 1.765010] usbcore: registered new interface driver usbhid
10581 17:36:03.639905 <6>[ 1.770832] usbhid: USB HID core driver
10582 17:36:03.646737 <6>[ 1.775050] spi_master spi0: will run message pump with realtime priority
10583 17:36:03.691749 <6>[ 1.814713] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10584 17:36:03.711487 <6>[ 1.830824] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10585 17:36:03.718510 <6>[ 1.845556] cros-ec-spi spi0.0: Chrome EC device registered
10586 17:36:03.721704 <6>[ 1.845651] mmc0: Command Queue Engine enabled
10587 17:36:03.728744 <6>[ 1.856123] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10588 17:36:03.734949 <6>[ 1.863377] mmcblk0: mmc0:0001 DA4128 116 GiB
10589 17:36:03.745047 <6>[ 1.869530] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10590 17:36:03.751527 <6>[ 1.874504] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10591 17:36:03.755063 <6>[ 1.879970] NET: Registered PF_PACKET protocol family
10592 17:36:03.762168 <6>[ 1.885633] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10593 17:36:03.764863 <6>[ 1.890143] 9pnet: Installing 9P2000 support
10594 17:36:03.771479 <6>[ 1.895879] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10595 17:36:03.774809 <5>[ 1.899842] Key type dns_resolver registered
10596 17:36:03.781917 <6>[ 1.905568] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10597 17:36:03.784930 <6>[ 1.910029] registered taskstats version 1
10598 17:36:03.791258 <5>[ 1.920442] Loading compiled-in X.509 certificates
10599 17:36:03.819496 <4>[ 1.942112] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 17:36:03.829425 <4>[ 1.952806] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 17:36:03.836364 <3>[ 1.963335] debugfs: File 'uA_load' in directory '/' already present!
10602 17:36:03.842745 <3>[ 1.970033] debugfs: File 'min_uV' in directory '/' already present!
10603 17:36:03.849345 <3>[ 1.976639] debugfs: File 'max_uV' in directory '/' already present!
10604 17:36:03.855842 <3>[ 1.983302] debugfs: File 'constraint_flags' in directory '/' already present!
10605 17:36:03.866122 <3>[ 1.992701] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10606 17:36:03.875996 <6>[ 2.005621] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10607 17:36:03.883290 <6>[ 2.012565] xhci-mtk 11200000.usb: xHCI Host Controller
10608 17:36:03.889858 <6>[ 2.018085] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10609 17:36:03.900084 <6>[ 2.025934] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10610 17:36:03.906709 <6>[ 2.035356] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10611 17:36:03.913394 <6>[ 2.041420] xhci-mtk 11200000.usb: xHCI Host Controller
10612 17:36:03.919567 <6>[ 2.046897] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10613 17:36:03.926336 <6>[ 2.054543] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10614 17:36:03.932845 <6>[ 2.062145] hub 1-0:1.0: USB hub found
10615 17:36:03.936534 <6>[ 2.066153] hub 1-0:1.0: 1 port detected
10616 17:36:03.942925 <6>[ 2.070420] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10617 17:36:03.949696 <6>[ 2.078975] hub 2-0:1.0: USB hub found
10618 17:36:03.953011 <6>[ 2.082979] hub 2-0:1.0: 1 port detected
10619 17:36:03.960510 <6>[ 2.090052] mtk-msdc 11f70000.mmc: Got CD GPIO
10620 17:36:03.970976 <6>[ 2.096816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10621 17:36:03.977494 <6>[ 2.104896] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10622 17:36:03.987229 <4>[ 2.112894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10623 17:36:03.997369 <6>[ 2.122428] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10624 17:36:04.003875 <6>[ 2.130523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10625 17:36:04.011229 <6>[ 2.138651] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10626 17:36:04.020609 <6>[ 2.146613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10627 17:36:04.027297 <6>[ 2.154433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10628 17:36:04.037180 <6>[ 2.162250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10629 17:36:04.047460 <6>[ 2.172368] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10630 17:36:04.053922 <6>[ 2.180744] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10631 17:36:04.063674 <6>[ 2.189087] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10632 17:36:04.070076 <6>[ 2.197425] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10633 17:36:04.080297 <6>[ 2.205763] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10634 17:36:04.087155 <6>[ 2.214101] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10635 17:36:04.097502 <6>[ 2.222439] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10636 17:36:04.103463 <6>[ 2.230777] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10637 17:36:04.113651 <6>[ 2.239114] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10638 17:36:04.120382 <6>[ 2.247452] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10639 17:36:04.130347 <6>[ 2.255798] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10640 17:36:04.137162 <6>[ 2.264151] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10641 17:36:04.147056 <6>[ 2.272489] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10642 17:36:04.153440 <6>[ 2.280830] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10643 17:36:04.163882 <6>[ 2.289167] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10644 17:36:04.170171 <6>[ 2.297900] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10645 17:36:04.176895 <6>[ 2.305038] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10646 17:36:04.183077 <6>[ 2.311813] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10647 17:36:04.190171 <6>[ 2.318583] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10648 17:36:04.196954 <6>[ 2.325519] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10649 17:36:04.206870 <6>[ 2.332360] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10650 17:36:04.216538 <6>[ 2.341491] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10651 17:36:04.226489 <6>[ 2.350611] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10652 17:36:04.236323 <6>[ 2.359906] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10653 17:36:04.243277 <6>[ 2.369376] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10654 17:36:04.252645 <6>[ 2.378844] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10655 17:36:04.263076 <6>[ 2.387964] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10656 17:36:04.272839 <6>[ 2.397431] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10657 17:36:04.282313 <6>[ 2.406550] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10658 17:36:04.292257 <6>[ 2.415846] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10659 17:36:04.301920 <6>[ 2.426005] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10660 17:36:04.312025 <6>[ 2.437550] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10661 17:36:04.318639 <6>[ 2.447175] Trying to probe devices needed for running init ...
10662 17:36:04.368215 <6>[ 2.494566] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10663 17:36:04.522526 <6>[ 2.652360] hub 1-1:1.0: USB hub found
10664 17:36:04.526176 <6>[ 2.656871] hub 1-1:1.0: 4 ports detected
10665 17:36:04.648531 <6>[ 2.774822] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10666 17:36:04.674048 <6>[ 2.803798] hub 2-1:1.0: USB hub found
10667 17:36:04.677114 <6>[ 2.808274] hub 2-1:1.0: 3 ports detected
10668 17:36:04.848521 <6>[ 2.974546] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10669 17:36:04.980835 <6>[ 3.110407] hub 1-1.4:1.0: USB hub found
10670 17:36:04.984232 <6>[ 3.115067] hub 1-1.4:1.0: 2 ports detected
10671 17:36:05.060255 <6>[ 3.186723] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10672 17:36:05.279846 <6>[ 3.406596] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10673 17:36:05.472060 <6>[ 3.598622] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10674 17:36:16.600967 <6>[ 14.735573] ALSA device list:
10675 17:36:16.607086 <6>[ 14.738865] No soundcards found.
10676 17:36:16.615410 <6>[ 14.746791] Freeing unused kernel memory: 8384K
10677 17:36:16.618827 <6>[ 14.751799] Run /init as init process
10678 17:36:16.630213 Loading, please wait...
10679 17:36:16.650860 Starting version 247.3-7+deb11u2
10680 17:36:16.846959 <6>[ 14.974750] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10681 17:36:16.874490 <6>[ 15.005876] remoteproc remoteproc0: scp is available
10682 17:36:16.881622 <6>[ 15.011452] remoteproc remoteproc0: powering up scp
10683 17:36:16.888266 <6>[ 15.016596] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10684 17:36:16.897762 <6>[ 15.017089] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10685 17:36:16.901322 <6>[ 15.025044] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10686 17:36:16.910774 <3>[ 15.037177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 17:36:16.917403 <6>[ 15.038320] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10688 17:36:16.927540 <3>[ 15.047628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 17:36:16.934113 <6>[ 15.055082] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10690 17:36:16.944195 <3>[ 15.063215] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 17:36:16.955845 <3>[ 15.083505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 17:36:16.959210 <6>[ 15.083763] mc: Linux media interface: v0.10
10693 17:36:16.968402 <6>[ 15.083997] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10694 17:36:16.975187 <3>[ 15.091633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 17:36:16.985246 <3>[ 15.091638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 17:36:16.991821 <3>[ 15.091643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 17:36:16.998452 <3>[ 15.091649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 17:36:17.008634 <4>[ 15.097260] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10699 17:36:17.015244 <3>[ 15.105927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 17:36:17.021732 <4>[ 15.112285] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10701 17:36:17.031219 <3>[ 15.120250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 17:36:17.038023 <6>[ 15.132660] videodev: Linux video capture interface: v2.00
10703 17:36:17.041543 <6>[ 15.133000] usbcore: registered new interface driver r8152
10704 17:36:17.051334 <3>[ 15.136421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 17:36:17.057930 <6>[ 15.150256] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10706 17:36:17.064785 <6>[ 15.150296] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10707 17:36:17.074543 <3>[ 15.151760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 17:36:17.080964 <6>[ 15.159061] remoteproc remoteproc0: remote processor scp is now up
10709 17:36:17.088072 <3>[ 15.167205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 17:36:17.098241 <6>[ 15.174130] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10711 17:36:17.105006 <3>[ 15.178615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 17:36:17.111105 <3>[ 15.178623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 17:36:17.121340 <3>[ 15.178631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 17:36:17.128037 <3>[ 15.178636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 17:36:17.138156 <3>[ 15.178673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 17:36:17.144676 <6>[ 15.188675] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10717 17:36:17.151198 <6>[ 15.191856] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10718 17:36:17.157484 <6>[ 15.191860] pci_bus 0000:00: root bus resource [bus 00-ff]
10719 17:36:17.164582 <6>[ 15.191865] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10720 17:36:17.174366 <6>[ 15.191867] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10721 17:36:17.181523 <6>[ 15.191896] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10722 17:36:17.188103 <6>[ 15.191909] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10723 17:36:17.194636 <6>[ 15.191977] pci 0000:00:00.0: supports D1 D2
10724 17:36:17.201117 <6>[ 15.191979] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10725 17:36:17.208124 <6>[ 15.192956] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10726 17:36:17.214406 <6>[ 15.193024] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10727 17:36:17.220847 <6>[ 15.193048] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10728 17:36:17.230873 <6>[ 15.193063] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10729 17:36:17.237545 <6>[ 15.193078] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10730 17:36:17.240988 <6>[ 15.193180] pci 0000:01:00.0: supports D1 D2
10731 17:36:17.247635 <6>[ 15.193182] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10732 17:36:17.257886 <4>[ 15.200509] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10733 17:36:17.260856 <4>[ 15.200509] Fallback method does not support PEC.
10734 17:36:17.270823 <6>[ 15.202329] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10735 17:36:17.280655 <6>[ 15.203419] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10736 17:36:17.286981 <6>[ 15.203714] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10737 17:36:17.297112 <3>[ 15.229685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 17:36:17.303691 <6>[ 15.230613] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10739 17:36:17.313273 <6>[ 15.232989] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10740 17:36:17.320069 <6>[ 15.233188] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10741 17:36:17.329868 <4>[ 15.253875] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10742 17:36:17.339823 <6>[ 15.257641] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10743 17:36:17.346358 <4>[ 15.265515] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10744 17:36:17.352884 <6>[ 15.267348] usbcore: registered new interface driver cdc_ether
10745 17:36:17.359654 <6>[ 15.273611] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10746 17:36:17.366096 <6>[ 15.284208] usbcore: registered new interface driver r8153_ecm
10747 17:36:17.369542 <6>[ 15.285143] Bluetooth: Core ver 2.22
10748 17:36:17.376088 <6>[ 15.285218] NET: Registered PF_BLUETOOTH protocol family
10749 17:36:17.382991 <6>[ 15.285220] Bluetooth: HCI device and connection manager initialized
10750 17:36:17.385865 <6>[ 15.285249] Bluetooth: HCI socket layer initialized
10751 17:36:17.392842 <6>[ 15.285255] Bluetooth: L2CAP socket layer initialized
10752 17:36:17.399334 <6>[ 15.285265] Bluetooth: SCO socket layer initialized
10753 17:36:17.405843 <6>[ 15.288723] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10754 17:36:17.412447 <6>[ 15.288738] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10755 17:36:17.422740 <6>[ 15.289744] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10756 17:36:17.432638 <6>[ 15.290754] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10757 17:36:17.439001 <6>[ 15.290832] usbcore: registered new interface driver uvcvideo
10758 17:36:17.449129 <3>[ 15.329739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10759 17:36:17.452663 <6>[ 15.330443] r8152 2-1.3:1.0 eth0: v1.12.13
10760 17:36:17.459267 <6>[ 15.336605] pci 0000:00:00.0: PCI bridge to [bus 01]
10761 17:36:17.462412 <6>[ 15.337355] usbcore: registered new interface driver btusb
10762 17:36:17.468942 <6>[ 15.337529] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10763 17:36:17.482194 <4>[ 15.338114] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10764 17:36:17.485173 <3>[ 15.338138] Bluetooth: hci0: Failed to load firmware file (-2)
10765 17:36:17.491984 <3>[ 15.338142] Bluetooth: hci0: Failed to set up firmware (-2)
10766 17:36:17.502055 <4>[ 15.338148] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10767 17:36:17.508079 <6>[ 15.340522] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10768 17:36:17.518394 <6>[ 15.645387] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10769 17:36:17.524969 <6>[ 15.653537] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10770 17:36:17.531756 <6>[ 15.660371] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10771 17:36:17.537858 <6>[ 15.666976] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10772 17:36:17.559792 <5>[ 15.687993] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10773 17:36:17.577899 <5>[ 15.705869] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10774 17:36:17.584490 <4>[ 15.712804] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10775 17:36:17.590905 <6>[ 15.721685] cfg80211: failed to load regulatory.db
10776 17:36:17.641219 <6>[ 15.769624] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10777 17:36:17.648126 <6>[ 15.777168] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10778 17:36:17.672516 <6>[ 15.803839] mt7921e 0000:01:00.0: ASIC revision: 79610010
10779 17:36:17.778116 <4>[ 15.902715] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 17:36:17.797385 Begin: Loading essential drivers ... done.
10781 17:36:17.800690 Begin: Running /scripts/init-premount ... done.
10782 17:36:17.807170 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10783 17:36:17.816968 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10784 17:36:17.820651 Device /sys/class/net/enx0024323078ff found
10785 17:36:17.820724 done.
10786 17:36:17.902178 <4>[ 16.026855] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 17:36:17.926721 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10788 17:36:18.021487 <4>[ 16.146200] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 17:36:18.141039 <4>[ 16.265840] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 17:36:18.261092 <4>[ 16.385963] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 17:36:18.380971 <4>[ 16.505849] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 17:36:18.501234 <4>[ 16.625942] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 17:36:18.620926 <4>[ 16.745817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 17:36:18.741060 <4>[ 16.865866] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10795 17:36:18.846112 <6>[ 16.977709] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10796 17:36:18.860922 <4>[ 16.985821] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 17:36:18.972239 <3>[ 17.103770] mt7921e 0000:01:00.0: hardware init failed
10798 17:36:19.036733 IP-Config: no response after 2 secs - giving up
10799 17:36:19.094805 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10800 17:36:19.097675 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10801 17:36:19.104201 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10802 17:36:19.114205 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10803 17:36:19.120657 host : mt8192-asurada-spherion-r0-cbg-8
10804 17:36:19.127287 domain : lava-rack
10805 17:36:19.130542 rootserver: 192.168.201.1 rootpath:
10806 17:36:19.130647 filename :
10807 17:36:19.202889 done.
10808 17:36:19.209979 Begin: Running /scripts/nfs-bottom ... done.
10809 17:36:19.230126 Begin: Running /scripts/init-bottom ... done.
10810 17:36:20.428330 <6>[ 18.560348] NET: Registered PF_INET6 protocol family
10811 17:36:20.436324 <6>[ 18.567636] Segment Routing with IPv6
10812 17:36:20.439230 <6>[ 18.571674] In-situ OAM (IOAM) with IPv6
10813 17:36:20.568176 <30>[ 18.680363] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10814 17:36:20.574631 <30>[ 18.704857] systemd[1]: Detected architecture arm64.
10815 17:36:20.593633
10816 17:36:20.596924 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10817 17:36:20.597004
10818 17:36:20.613557 <30>[ 18.745140] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10819 17:36:21.420658 <30>[ 19.549083] systemd[1]: Queued start job for default target Graphical Interface.
10820 17:36:21.453012 <30>[ 19.584863] systemd[1]: Created slice system-getty.slice.
10821 17:36:21.459258 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10822 17:36:21.475997 <30>[ 19.607936] systemd[1]: Created slice system-modprobe.slice.
10823 17:36:21.482511 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10824 17:36:21.499883 <30>[ 19.631770] systemd[1]: Created slice system-serial\x2dgetty.slice.
10825 17:36:21.509866 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10826 17:36:21.523555 <30>[ 19.655608] systemd[1]: Created slice User and Session Slice.
10827 17:36:21.530101 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10828 17:36:21.550639 <30>[ 19.679418] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10829 17:36:21.560631 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10830 17:36:21.578925 <30>[ 19.707325] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10831 17:36:21.585221 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10832 17:36:21.609299 <30>[ 19.734720] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10833 17:36:21.615802 <30>[ 19.746894] systemd[1]: Reached target Local Encrypted Volumes.
10834 17:36:21.622433 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10835 17:36:21.639177 <30>[ 19.771150] systemd[1]: Reached target Paths.
10836 17:36:21.642653 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10837 17:36:21.658718 <30>[ 19.790569] systemd[1]: Reached target Remote File Systems.
10838 17:36:21.665331 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10839 17:36:21.683175 <30>[ 19.814950] systemd[1]: Reached target Slices.
10840 17:36:21.689804 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10841 17:36:21.702292 <30>[ 19.834587] systemd[1]: Reached target Swap.
10842 17:36:21.705740 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10843 17:36:21.726161 <30>[ 19.855032] systemd[1]: Listening on initctl Compatibility Named Pipe.
10844 17:36:21.732716 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10845 17:36:21.739796 <30>[ 19.871145] systemd[1]: Listening on Journal Audit Socket.
10846 17:36:21.745866 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10847 17:36:21.764103 <30>[ 19.895802] systemd[1]: Listening on Journal Socket (/dev/log).
10848 17:36:21.770284 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10849 17:36:21.786980 <30>[ 19.919153] systemd[1]: Listening on Journal Socket.
10850 17:36:21.794062 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10851 17:36:21.811283 <30>[ 19.940055] systemd[1]: Listening on Network Service Netlink Socket.
10852 17:36:21.817659 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10853 17:36:21.833368 <30>[ 19.965368] systemd[1]: Listening on udev Control Socket.
10854 17:36:21.839667 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10855 17:36:21.854722 <30>[ 19.987000] systemd[1]: Listening on udev Kernel Socket.
10856 17:36:21.861400 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10857 17:36:21.918694 <30>[ 20.050812] systemd[1]: Mounting Huge Pages File System...
10858 17:36:21.925512 Mounting [0;1;39mHuge Pages File System[0m...
10859 17:36:21.943175 <30>[ 20.075008] systemd[1]: Mounting POSIX Message Queue File System...
10860 17:36:21.949526 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10861 17:36:21.969890 <30>[ 20.101848] systemd[1]: Mounting Kernel Debug File System...
10862 17:36:21.976183 Mounting [0;1;39mKernel Debug File System[0m...
10863 17:36:21.993715 <30>[ 20.122682] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10864 17:36:22.038544 <30>[ 20.167317] systemd[1]: Starting Create list of static device nodes for the current kernel...
10865 17:36:22.045213 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10866 17:36:22.067034 <30>[ 20.199260] systemd[1]: Starting Load Kernel Module configfs...
10867 17:36:22.073517 Starting [0;1;39mLoad Kernel Module configfs[0m...
10868 17:36:22.089801 <30>[ 20.221933] systemd[1]: Starting Load Kernel Module drm...
10869 17:36:22.096520 Starting [0;1;39mLoad Kernel Module drm[0m...
10870 17:36:22.113723 <30>[ 20.245917] systemd[1]: Starting Load Kernel Module fuse...
10871 17:36:22.120769 Starting [0;1;39mLoad Kernel Module fuse[0m...
10872 17:36:22.156451 <30>[ 20.285300] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10873 17:36:22.163550 <6>[ 20.295695] fuse: init (API version 7.37)
10874 17:36:22.191036 <30>[ 20.323093] systemd[1]: Starting Journal Service...
10875 17:36:22.194462 Starting [0;1;39mJournal Service[0m...
10876 17:36:22.219194 <30>[ 20.350988] systemd[1]: Starting Load Kernel Modules...
10877 17:36:22.225823 Starting [0;1;39mLoad Kernel Modules[0m...
10878 17:36:22.245102 <30>[ 20.373875] systemd[1]: Starting Remount Root and Kernel File Systems...
10879 17:36:22.251618 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10880 17:36:22.270751 <30>[ 20.403029] systemd[1]: Starting Coldplug All udev Devices...
10881 17:36:22.277823 Starting [0;1;39mColdplug All udev Devices[0m...
10882 17:36:22.296293 <30>[ 20.428264] systemd[1]: Mounted Huge Pages File System.
10883 17:36:22.302967 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10884 17:36:22.319719 <30>[ 20.451387] systemd[1]: Mounted POSIX Message Queue File System.
10885 17:36:22.326001 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10886 17:36:22.343172 <30>[ 20.475489] systemd[1]: Mounted Kernel Debug File System.
10887 17:36:22.349934 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10888 17:36:22.371844 <30>[ 20.499477] systemd[1]: Finished Create list of static device nodes for the current kernel.
10889 17:36:22.381406 <3>[ 20.501703] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 17:36:22.388030 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10891 17:36:22.403423 <30>[ 20.535252] systemd[1]: modprobe@configfs.service: Succeeded.
10892 17:36:22.410471 <30>[ 20.542399] systemd[1]: Finished Load Kernel Module configfs.
10893 17:36:22.420528 <3>[ 20.543983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 17:36:22.426901 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10895 17:36:22.443553 <30>[ 20.575371] systemd[1]: modprobe@drm.service: Succeeded.
10896 17:36:22.449800 <30>[ 20.581679] systemd[1]: Finished Load Kernel Module drm.
10897 17:36:22.457042 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10898 17:36:22.467030 <3>[ 20.595014] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 17:36:22.473738 <30>[ 20.604684] systemd[1]: modprobe@fuse.service: Succeeded.
10900 17:36:22.480396 <30>[ 20.611534] systemd[1]: Finished Load Kernel Module fuse.
10901 17:36:22.487188 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10902 17:36:22.497131 <3>[ 20.624885] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 17:36:22.504966 <30>[ 20.637020] systemd[1]: Finished Load Kernel Modules.
10904 17:36:22.511567 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10905 17:36:22.525843 <3>[ 20.654568] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 17:36:22.536818 <30>[ 20.665526] systemd[1]: Finished Remount Root and Kernel File Systems.
10907 17:36:22.543560 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10908 17:36:22.555800 <3>[ 20.684071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 17:36:22.585694 <3>[ 20.714356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 17:36:22.598565 <30>[ 20.730501] systemd[1]: Mounting FUSE Control File System...
10911 17:36:22.605152 Mounting [0;1;39mFUSE Control File System[0m...
10912 17:36:22.624171 <30>[ 20.752980] systemd[1]: Mounting Kernel Configuration File System...
10913 17:36:22.630891 <3>[ 20.753799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 17:36:22.637440 Mounting [0;1;39mKernel Configuration File System[0m...
10915 17:36:22.659814 <3>[ 20.788590] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 17:36:22.670015 <30>[ 20.791404] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10917 17:36:22.680120 <30>[ 20.806636] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10918 17:36:22.690544 <3>[ 20.817960] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 17:36:22.697307 <30>[ 20.819269] systemd[1]: Starting Load/Save Random Seed...
10920 17:36:22.700086 Starting [0;1;39mLoad/Save Random Seed[0m...
10921 17:36:22.718052 <30>[ 20.849857] systemd[1]: Starting Apply Kernel Variables...
10922 17:36:22.725191 Starting [0;1;39mApply Kernel Variables[0m...
10923 17:36:22.742604 <30>[ 20.873877] systemd[1]: Starting Create System Users...
10924 17:36:22.748742 Starting [0;1;39mCreate System Users[0m...
10925 17:36:22.765352 <30>[ 20.896436] systemd[1]: Started Journal Service.
10926 17:36:22.781723 [[0;32m OK [0m] Started [0;<4>[ 20.904438] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10927 17:36:22.791242 1;39mJournal Ser<3>[ 20.920209] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10928 17:36:22.791332 vice[0m.
10929 17:36:22.813866 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10930 17:36:22.837123 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10931 17:36:22.855196 See 'systemctl status systemd-udev-trigger.service' for details.
10932 17:36:22.871279 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10933 17:36:22.888597 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10934 17:36:22.904900 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10935 17:36:22.924261 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10936 17:36:22.987706 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10937 17:36:23.008828 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10938 17:36:23.056507 <46>[ 21.185014] systemd-journald[301]: Received client request to flush runtime journal.
10939 17:36:23.107655 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10940 17:36:23.119191 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10941 17:36:23.135067 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10942 17:36:23.179100 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10943 17:36:24.462892 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10944 17:36:24.503578 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10945 17:36:24.563343 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10946 17:36:24.619740 Starting [0;1;39mNetwork Service[0m...
10947 17:36:24.907995 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10948 17:36:24.975340 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10949 17:36:24.996742 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10950 17:36:25.283294 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10951 17:36:25.301845 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10952 17:36:25.339814 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10953 17:36:25.387714 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10954 17:36:25.403074 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10955 17:36:25.422948 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10956 17:36:25.439157 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10957 17:36:25.487102 Starting [0;1;39mNetwork Name Resolution[0m...
10958 17:36:25.516979 Starting [0;1;39mNetwork Time Synchronization[0m...
10959 17:36:25.535313 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10960 17:36:25.611407 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10961 17:36:25.766563 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10962 17:36:25.783139 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10963 17:36:25.803035 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10964 17:36:25.818170 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10965 17:36:25.834509 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10966 17:36:25.953907 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10967 17:36:25.993417 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10968 17:36:26.018845 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10969 17:36:26.051953 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10970 17:36:26.066232 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10971 17:36:26.088910 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10972 17:36:26.101986 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10973 17:36:26.117858 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10974 17:36:26.162877 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10975 17:36:26.242343 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10976 17:36:26.338671 Starting [0;1;39mUser Login Management[0m...
10977 17:36:26.359455 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10978 17:36:26.375000 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10979 17:36:26.392711 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10980 17:36:26.429970 Starting [0;1;39mPermit User Sessions[0m...
10981 17:36:26.531526 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10982 17:36:26.549131 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10983 17:36:26.618163 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10984 17:36:26.636238 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10985 17:36:26.657322 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10986 17:36:26.674599 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10987 17:36:26.690907 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10988 17:36:26.710346 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10989 17:36:26.749813 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10990 17:36:26.797472 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10991 17:36:26.867286
10992 17:36:26.867489
10993 17:36:26.870199 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10994 17:36:26.870315
10995 17:36:26.873750 debian-bullseye-arm64 login: root (automatic login)
10996 17:36:26.873829
10997 17:36:26.873898
10998 17:36:27.200222 Linux debian-bullseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023 aarch64
10999 17:36:27.200377
11000 17:36:27.206616 The programs included with the Debian GNU/Linux system are free software;
11001 17:36:27.213309 the exact distribution terms for each program are described in the
11002 17:36:27.216684 individual files in /usr/share/doc/*/copyright.
11003 17:36:27.216790
11004 17:36:27.223342 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11005 17:36:27.226384 permitted by applicable law.
11006 17:36:27.299580 Matched prompt #10: / #
11008 17:36:27.300045 Setting prompt string to ['/ #']
11009 17:36:27.300181 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11011 17:36:27.300413 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11012 17:36:27.300505 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
11013 17:36:27.300595 Setting prompt string to ['/ #']
11014 17:36:27.300687 Forcing a shell prompt, looking for ['/ #']
11016 17:36:27.350950 / #
11017 17:36:27.351094 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11018 17:36:27.351262 Waiting using forced prompt support (timeout 00:02:30)
11019 17:36:27.355874
11020 17:36:27.356150 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11021 17:36:27.356242 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11023 17:36:27.456556 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu'
11024 17:36:27.461493 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11518300/extract-nfsrootfs-yez_sfxu'
11026 17:36:27.562016 / # export NFS_SERVER_IP='192.168.201.1'
11027 17:36:27.567706 export NFS_SERVER_IP='192.168.201.1'
11028 17:36:27.568011 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 17:36:27.568123 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11030 17:36:27.568247 end: 2 depthcharge-action (duration 00:01:44) [common]
11031 17:36:27.568358 start: 3 lava-test-retry (timeout 00:01:00) [common]
11032 17:36:27.568464 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11033 17:36:27.568543 Using namespace: common
11035 17:36:27.668836 / # #
11036 17:36:27.669030 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11037 17:36:27.673638 #
11038 17:36:27.673948 Using /lava-11518300
11040 17:36:27.774296 / # export SHELL=/bin/sh
11041 17:36:27.779114 export SHELL=/bin/sh
11043 17:36:27.879691 / # . /lava-11518300/environment
11044 17:36:27.884378 . /lava-11518300/environment
11046 17:36:27.990718 / # /lava-11518300/bin/lava-test-runner /lava-11518300/0
11047 17:36:27.990950 Test shell timeout: 10s (minimum of the action and connection timeout)
11048 17:36:27.996177 /lava-11518300/bin/lava-test-runner /lava-11518300/0
11049 17:36:28.248682 + export TESTRUN_ID=0_dmesg
11050 17:36:28.252136 + cd /lava-11518300/0/tests/0_dmesg
11051 17:36:28.255003 + cat uuid
11052 17:36:28.270154 + UUID=11518300_<8>[ 26.399647] <LAVA_SIGNAL_STARTRUN 0_dmesg 11518300_1.6.2.3.1>
11053 17:36:28.270244 1.6.2.3.1
11054 17:36:28.270311 + set +x
11055 17:36:28.270553 Received signal: <STARTRUN> 0_dmesg 11518300_1.6.2.3.1
11056 17:36:28.270629 Starting test lava.0_dmesg (11518300_1.6.2.3.1)
11057 17:36:28.270715 Skipping test definition patterns.
11058 17:36:28.276487 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11059 17:36:28.381857 <8>[ 26.511016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11060 17:36:28.382179 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11062 17:36:28.463105 <8>[ 26.592239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11063 17:36:28.463480 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11065 17:36:28.542077 <8>[ 26.671487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11066 17:36:28.542391 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11068 17:36:28.548813 + <8>[ 26.681070] <LAVA_SIGNAL_ENDRUN 0_dmesg 11518300_1.6.2.3.1>
11069 17:36:28.548913 set +x
11070 17:36:28.549176 Received signal: <ENDRUN> 0_dmesg 11518300_1.6.2.3.1
11071 17:36:28.549275 Ending use of test pattern.
11072 17:36:28.549342 Ending test lava.0_dmesg (11518300_1.6.2.3.1), duration 0.28
11074 17:36:28.556885 <LAVA_TEST_RUNNER EXIT>
11075 17:36:28.557137 ok: lava_test_shell seems to have completed
11076 17:36:28.557253 alert: pass
crit: pass
emerg: pass
11077 17:36:28.557351 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11078 17:36:28.557447 end: 3 lava-test-retry (duration 00:00:01) [common]
11079 17:36:28.557539 start: 4 lava-test-retry (timeout 00:01:00) [common]
11080 17:36:28.557630 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11081 17:36:28.557698 Using namespace: common
11083 17:36:28.658004 / # #
11084 17:36:28.658140 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11085 17:36:28.658259 Using /lava-11518300
11087 17:36:28.758533 export SHELL=/bin/sh
11088 17:36:28.758735 #
11090 17:36:28.859218 / # export SHELL=/bin/sh. /lava-11518300/environment
11091 17:36:28.859484
11093 17:36:28.959993 / # . /lava-11518300/environment/lava-11518300/bin/lava-test-runner /lava-11518300/1
11094 17:36:28.960152 Test shell timeout: 10s (minimum of the action and connection timeout)
11095 17:36:28.960300
11096 17:36:28.965312 / # /lava-11518300/bin/lava-test-runner /lava-11518300/1
11097 17:36:29.103949 + export TESTRUN_ID=1_bootrr
11098 17:36:29.106859 + cd /lava-11518300/1/tests/1_bootrr
11099 17:36:29.110252 + cat uuid
11100 17:36:29.125404 + UUID=11518300_<8>[ 27.255027] <LAVA_SIGNAL_STARTRUN 1_bootrr 11518300_1.6.2.3.5>
11101 17:36:29.125526 1.6.2.3.5
11102 17:36:29.125625 + set +x
11103 17:36:29.125875 Received signal: <STARTRUN> 1_bootrr 11518300_1.6.2.3.5
11104 17:36:29.125951 Starting test lava.1_bootrr (11518300_1.6.2.3.5)
11105 17:36:29.126036 Skipping test definition patterns.
11106 17:36:29.138933 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11518300/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11107 17:36:29.141942 + cd /opt/bootrr/libexec/bootrr
11108 17:36:29.142026 + sh helpers/bootrr-auto
11109 17:36:29.220031 /lava-11518300/1/../bin/lava-test-case
11110 17:36:29.255013 <8>[ 27.384774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11111 17:36:29.255312 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11113 17:36:29.304054 /lava-11518300/1/../bin/lava-test-case
11114 17:36:29.332388 <8>[ 27.462031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11115 17:36:29.332677 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11117 17:36:29.359447 /lava-11518300/1/../bin/lava-test-case
11118 17:36:29.389214 <8>[ 27.518709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11119 17:36:29.389484 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11121 17:36:29.457697 /lava-11518300/1/../bin/lava-test-case
11122 17:36:29.487178 <8>[ 27.616756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11123 17:36:29.487440 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11125 17:36:29.525934 /lava-11518300/1/../bin/lava-test-case
11126 17:36:29.556055 <8>[ 27.685376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11127 17:36:29.556339 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11129 17:36:29.592081 /lava-11518300/1/../bin/lava-test-case
11130 17:36:29.621451 <8>[ 27.750910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11131 17:36:29.621726 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11133 17:36:29.661620 /lava-11518300/1/../bin/lava-test-case
11134 17:36:29.695336 <8>[ 27.825208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11135 17:36:29.695653 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11137 17:36:29.733374 /lava-11518300/1/../bin/lava-test-case
11138 17:36:29.761563 <8>[ 27.891198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11139 17:36:29.761843 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11141 17:36:29.791713 /lava-11518300/1/../bin/lava-test-case
11142 17:36:29.825355 <8>[ 27.955167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11143 17:36:29.825642 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11145 17:36:29.867874 /lava-11518300/1/../bin/lava-test-case
11146 17:36:29.899602 <8>[ 28.028960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11147 17:36:29.899902 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11149 17:36:29.926143 /lava-11518300/1/../bin/lava-test-case
11150 17:36:29.961763 <8>[ 28.091279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11151 17:36:29.962033 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11153 17:36:30.008414 /lava-11518300/1/../bin/lava-test-case
11154 17:36:30.041130 <8>[ 28.170813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11155 17:36:30.041437 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11157 17:36:30.086299 /lava-11518300/1/../bin/lava-test-case
11158 17:36:30.119545 <8>[ 28.249467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11159 17:36:30.119819 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11161 17:36:30.161046 /lava-11518300/1/../bin/lava-test-case
11162 17:36:30.193320 <8>[ 28.323190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11163 17:36:30.193632 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11165 17:36:30.237987 /lava-11518300/1/../bin/lava-test-case
11166 17:36:30.270212 <8>[ 28.399699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11167 17:36:30.270480 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11169 17:36:30.296303 /lava-11518300/1/../bin/lava-test-case
11170 17:36:30.326063 <8>[ 28.456021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11171 17:36:30.326332 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11173 17:36:30.370340 /lava-11518300/1/../bin/lava-test-case
11174 17:36:30.404370 <8>[ 28.533765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11175 17:36:30.404648 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11177 17:36:30.437405 /lava-11518300/1/../bin/lava-test-case
11178 17:36:30.473872 <8>[ 28.603483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11179 17:36:30.474150 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11181 17:36:30.516045 /lava-11518300/1/../bin/lava-test-case
11182 17:36:30.547749 <8>[ 28.677306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11183 17:36:30.548019 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11185 17:36:30.573216 /lava-11518300/1/../bin/lava-test-case
11186 17:36:30.606133 <8>[ 28.735956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11187 17:36:30.606407 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11189 17:36:30.649772 /lava-11518300/1/../bin/lava-test-case
11190 17:36:30.684632 <8>[ 28.814119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11191 17:36:30.684909 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11193 17:36:30.722985 /lava-11518300/1/../bin/lava-test-case
11194 17:36:30.752494 <8>[ 28.882385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11195 17:36:30.752788 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11197 17:36:30.789807 /lava-11518300/1/../bin/lava-test-case
11198 17:36:30.818499 <8>[ 28.948376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11199 17:36:30.818797 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11201 17:36:30.845062 /lava-11518300/1/../bin/lava-test-case
11202 17:36:30.874514 <8>[ 29.004080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11203 17:36:30.874809 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11205 17:36:30.913072 /lava-11518300/1/../bin/lava-test-case
11206 17:36:30.943223 <8>[ 29.072743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11207 17:36:30.943540 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11209 17:36:30.980558 /lava-11518300/1/../bin/lava-test-case
11210 17:36:31.013033 <8>[ 29.142927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11211 17:36:31.013320 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11213 17:36:31.041155 /lava-11518300/1/../bin/lava-test-case
11214 17:36:31.070502 <8>[ 29.200467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11215 17:36:31.070779 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11217 17:36:31.108725 /lava-11518300/1/../bin/lava-test-case
11218 17:36:31.137552 <8>[ 29.267057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11219 17:36:31.137843 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11221 17:36:31.161535 /lava-11518300/1/../bin/lava-test-case
11222 17:36:31.190511 <8>[ 29.320224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11223 17:36:31.190786 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11225 17:36:31.228916 /lava-11518300/1/../bin/lava-test-case
11226 17:36:31.262050 <8>[ 29.391906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11227 17:36:31.262330 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11229 17:36:31.297072 /lava-11518300/1/../bin/lava-test-case
11230 17:36:31.324830 <8>[ 29.454697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11231 17:36:31.325107 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11233 17:36:31.371298 /lava-11518300/1/../bin/lava-test-case
11234 17:36:31.402421 <8>[ 29.532311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11235 17:36:31.402740 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11237 17:36:31.439542 /lava-11518300/1/../bin/lava-test-case
11238 17:36:31.468795 <8>[ 29.598469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11239 17:36:31.469107 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11241 17:36:31.491840 /lava-11518300/1/../bin/lava-test-case
11242 17:36:31.523075 <8>[ 29.652823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11243 17:36:31.523356 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11245 17:36:31.563860 /lava-11518300/1/../bin/lava-test-case
11246 17:36:31.597154 <8>[ 29.726675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11247 17:36:31.597444 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11249 17:36:31.636507 /lava-11518300/1/../bin/lava-test-case
11250 17:36:31.668854 <8>[ 29.798628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11251 17:36:31.669141 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11253 17:36:31.702188 /lava-11518300/1/../bin/lava-test-case
11254 17:36:31.733936 <8>[ 29.863947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11255 17:36:31.734219 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11257 17:36:31.775960 /lava-11518300/1/../bin/lava-test-case
11258 17:36:31.809697 <8>[ 29.939181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11259 17:36:31.809978 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11261 17:36:31.835546 /lava-11518300/1/../bin/lava-test-case
11262 17:36:31.865123 <8>[ 29.994614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11263 17:36:31.865474 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11265 17:36:31.903570 /lava-11518300/1/../bin/lava-test-case
11266 17:36:31.937946 <8>[ 30.067886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11267 17:36:31.938224 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11269 17:36:31.964174 /lava-11518300/1/../bin/lava-test-case
11270 17:36:31.994929 <8>[ 30.124981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11271 17:36:31.995240 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11273 17:36:32.040363 /lava-11518300/1/../bin/lava-test-case
11274 17:36:32.070130 <8>[ 30.200013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11275 17:36:32.070435 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11277 17:36:32.094908 /lava-11518300/1/../bin/lava-test-case
11278 17:36:32.124447 <8>[ 30.254407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11279 17:36:32.124749 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11281 17:36:32.162118 /lava-11518300/1/../bin/lava-test-case
11282 17:36:32.190927 <8>[ 30.320530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11283 17:36:32.191203 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11285 17:36:32.217792 /lava-11518300/1/../bin/lava-test-case
11286 17:36:32.251776 <8>[ 30.381850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11287 17:36:32.252062 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11289 17:36:32.291512 /lava-11518300/1/../bin/lava-test-case
11290 17:36:32.320919 <8>[ 30.450956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11291 17:36:32.321203 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11293 17:36:32.351759 /lava-11518300/1/../bin/lava-test-case
11294 17:36:32.384555 <8>[ 30.514391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11295 17:36:32.384871 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11297 17:36:32.425952 /lava-11518300/1/../bin/lava-test-case
11298 17:36:32.458419 <8>[ 30.588285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11299 17:36:32.458701 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11301 17:36:32.481694 /lava-11518300/1/../bin/lava-test-case
11302 17:36:32.509412 <8>[ 30.639174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11303 17:36:32.509703 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11305 17:36:32.546795 /lava-11518300/1/../bin/lava-test-case
11306 17:36:32.576218 <8>[ 30.706213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11307 17:36:32.576505 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11309 17:36:32.613070 /lava-11518300/1/../bin/lava-test-case
11310 17:36:32.642125 <8>[ 30.772134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11311 17:36:32.642398 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11313 17:36:32.674980 /lava-11518300/1/../bin/lava-test-case
11314 17:36:32.705469 <8>[ 30.835251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11315 17:36:32.705745 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11317 17:36:32.745076 /lava-11518300/1/../bin/lava-test-case
11318 17:36:32.775065 <8>[ 30.904734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11319 17:36:32.775366 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11321 17:36:32.799823 /lava-11518300/1/../bin/lava-test-case
11322 17:36:32.829813 <8>[ 30.959909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11323 17:36:32.830152 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11325 17:36:32.868089 /lava-11518300/1/../bin/lava-test-case
11326 17:36:32.901667 <8>[ 31.031564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11327 17:36:32.901975 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11329 17:36:32.940851 /lava-11518300/1/../bin/lava-test-case
11330 17:36:32.974349 <8>[ 31.104323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11331 17:36:32.974634 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11333 17:36:33.022425 /lava-11518300/1/../bin/lava-test-case
11334 17:36:33.054700 <8>[ 31.184413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11335 17:36:33.054985 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11337 17:36:33.093123 /lava-11518300/1/../bin/lava-test-case
11338 17:36:33.121317 <8>[ 31.251347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11339 17:36:33.121619 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11341 17:36:33.161745 /lava-11518300/1/../bin/lava-test-case
11342 17:36:33.195887 <8>[ 31.325527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11343 17:36:33.196167 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11345 17:36:33.220461 /lava-11518300/1/../bin/lava-test-case
11346 17:36:33.249562 <8>[ 31.379545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11347 17:36:33.249865 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11349 17:36:33.289981 /lava-11518300/1/../bin/lava-test-case
11350 17:36:33.322374 <8>[ 31.452624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11351 17:36:33.322655 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11353 17:36:33.365904 /lava-11518300/1/../bin/lava-test-case
11354 17:36:33.394069 <8>[ 31.524033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11355 17:36:33.394345 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11357 17:36:33.417327 /lava-11518300/1/../bin/lava-test-case
11358 17:36:33.448019 <8>[ 31.578171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11359 17:36:33.448288 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11361 17:36:33.485998 /lava-11518300/1/../bin/lava-test-case
11362 17:36:33.515684 <8>[ 31.646004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11363 17:36:33.516016 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11365 17:36:33.542280 /lava-11518300/1/../bin/lava-test-case
11366 17:36:33.572548 <8>[ 31.702475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11367 17:36:33.572864 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11369 17:36:33.613172 /lava-11518300/1/../bin/lava-test-case
11370 17:36:33.645795 <8>[ 31.775527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11371 17:36:33.646129 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11373 17:36:33.676530 /lava-11518300/1/../bin/lava-test-case
11374 17:36:33.706364 <8>[ 31.836115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11375 17:36:33.706667 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11377 17:36:33.743111 /lava-11518300/1/../bin/lava-test-case
11378 17:36:33.772002 <8>[ 31.902032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11379 17:36:33.772279 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11381 17:36:33.810633 /lava-11518300/1/../bin/lava-test-case
11382 17:36:33.839821 <8>[ 31.970092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11383 17:36:33.840124 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11385 17:36:33.877146 /lava-11518300/1/../bin/lava-test-case
11386 17:36:33.907514 <8>[ 32.037594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11387 17:36:33.907822 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11389 17:36:33.945086 /lava-11518300/1/../bin/lava-test-case
11390 17:36:33.974395 <8>[ 32.104812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11391 17:36:33.974693 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11393 17:36:34.038616 /lava-11518300/1/../bin/lava-test-case
11394 17:36:34.071631 <8>[ 32.201395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11395 17:36:34.071929 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11397 17:36:34.109282 /lava-11518300/1/../bin/lava-test-case
11398 17:36:34.142974 <8>[ 32.272903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11399 17:36:34.143250 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11401 17:36:34.187256 /lava-11518300/1/../bin/lava-test-case
11402 17:36:34.220452 <8>[ 32.350408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11403 17:36:34.220747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11405 17:36:34.259242 /lava-11518300/1/../bin/lava-test-case
11406 17:36:34.290371 <8>[ 32.420297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11407 17:36:34.290654 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11409 17:36:34.324906 /lava-11518300/1/../bin/lava-test-case
11410 17:36:34.355327 <8>[ 32.485625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11411 17:36:34.355688 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11413 17:36:34.401587 /lava-11518300/1/../bin/lava-test-case
11414 17:36:34.432167 <8>[ 32.562244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11415 17:36:34.432445 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11417 17:36:34.467504 /lava-11518300/1/../bin/lava-test-case
11418 17:36:34.495900 <8>[ 32.626164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11419 17:36:34.496184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11421 17:36:34.532849 /lava-11518300/1/../bin/lava-test-case
11422 17:36:34.564651 <8>[ 32.694908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11423 17:36:34.564933 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11425 17:36:34.604324 /lava-11518300/1/../bin/lava-test-case
11426 17:36:34.635310 <8>[ 32.765705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11427 17:36:34.635609 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11429 17:36:34.672813 /lava-11518300/1/../bin/lava-test-case
11430 17:36:34.703690 <8>[ 32.833706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11431 17:36:34.703996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11433 17:36:34.751133 /lava-11518300/1/../bin/lava-test-case
11434 17:36:34.781875 <8>[ 32.912043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11435 17:36:34.782190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11437 17:36:34.808089 /lava-11518300/1/../bin/lava-test-case
11438 17:36:34.837885 <8>[ 32.968182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11439 17:36:34.838185 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11441 17:36:34.877677 /lava-11518300/1/../bin/lava-test-case
11442 17:36:34.906481 <8>[ 33.036775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11443 17:36:34.906765 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11445 17:36:34.929167 /lava-11518300/1/../bin/lava-test-case
11446 17:36:34.960445 <8>[ 33.090643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11447 17:36:34.960720 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11449 17:36:34.999154 /lava-11518300/1/../bin/lava-test-case
11450 17:36:35.031710 <8>[ 33.161650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11451 17:36:35.031985 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11453 17:36:35.055915 /lava-11518300/1/../bin/lava-test-case
11454 17:36:35.087673 <8>[ 33.217974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11455 17:36:35.087948 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11457 17:36:35.137438 /lava-11518300/1/../bin/lava-test-case
11458 17:36:35.170177 <8>[ 33.300376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11459 17:36:35.170484 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11461 17:36:35.196726 /lava-11518300/1/../bin/lava-test-case
11462 17:36:35.225708 <8>[ 33.355777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11463 17:36:35.225974 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11465 17:36:35.261357 /lava-11518300/1/../bin/lava-test-case
11466 17:36:35.291241 <8>[ 33.421694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11467 17:36:35.291537 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11469 17:36:35.318146 /lava-11518300/1/../bin/lava-test-case
11470 17:36:35.350418 <8>[ 33.480538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11471 17:36:35.350679 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11473 17:36:35.391285 /lava-11518300/1/../bin/lava-test-case
11474 17:36:35.425316 <8>[ 33.555296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11475 17:36:35.425603 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11477 17:36:35.453750 /lava-11518300/1/../bin/lava-test-case
11478 17:36:35.487284 <8>[ 33.617553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11479 17:36:35.487616 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11481 17:36:35.524944 /lava-11518300/1/../bin/lava-test-case
11482 17:36:35.556768 <8>[ 33.687003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11483 17:36:35.557062 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11485 17:36:35.596403 /lava-11518300/1/../bin/lava-test-case
11486 17:36:35.626700 <8>[ 33.756946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11487 17:36:35.626998 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11489 17:36:35.653439 /lava-11518300/1/../bin/lava-test-case
11490 17:36:35.684747 <8>[ 33.814858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11491 17:36:35.685025 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11493 17:36:35.723446 /lava-11518300/1/../bin/lava-test-case
11494 17:36:35.753343 <8>[ 33.883353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11495 17:36:35.753632 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11497 17:36:35.782993 /lava-11518300/1/../bin/lava-test-case
11498 17:36:35.813084 <8>[ 33.943659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11499 17:36:35.813377 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11501 17:36:35.853515 /lava-11518300/1/../bin/lava-test-case
11502 17:36:35.887108 <8>[ 34.017579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11503 17:36:35.887411 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11505 17:36:35.912156 /lava-11518300/1/../bin/lava-test-case
11506 17:36:35.945256 <8>[ 34.075511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11507 17:36:35.945561 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11509 17:36:37.005244 /lava-11518300/1/../bin/lava-test-case
11510 17:36:37.041519 <8>[ 35.171969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11511 17:36:37.041824 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11513 17:36:37.070959 /lava-11518300/1/../bin/lava-test-case
11514 17:36:37.111457 <8>[ 35.241799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11515 17:36:37.111769 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11517 17:36:38.174391 /lava-11518300/1/../bin/lava-test-case
11518 17:36:38.209055 <8>[ 36.339579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11519 17:36:38.209349 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11521 17:36:38.233042 /lava-11518300/1/../bin/lava-test-case
11522 17:36:38.264659 <8>[ 36.395089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11523 17:36:38.264940 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11525 17:36:39.314353 /lava-11518300/1/../bin/lava-test-case
11526 17:36:39.345782 <8>[ 37.476418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11527 17:36:39.346072 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11529 17:36:39.371676 /lava-11518300/1/../bin/lava-test-case
11530 17:36:39.405043 <8>[ 37.535430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11531 17:36:39.405341 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11533 17:36:40.458117 /lava-11518300/1/../bin/lava-test-case
11534 17:36:40.491181 <8>[ 38.622287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11535 17:36:40.491495 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11537 17:36:40.518662 /lava-11518300/1/../bin/lava-test-case
11538 17:36:40.554816 <8>[ 38.685621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11539 17:36:40.555117 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11541 17:36:41.612348 /lava-11518300/1/../bin/lava-test-case
11542 17:36:41.650440 <8>[ 39.781601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11543 17:36:41.650749 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11545 17:36:41.676279 /lava-11518300/1/../bin/lava-test-case
11546 17:36:41.709938 <8>[ 39.840780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11547 17:36:41.710256 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11549 17:36:42.765004 /lava-11518300/1/../bin/lava-test-case
11550 17:36:42.800399 <8>[ 40.931492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11551 17:36:42.800690 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11553 17:36:42.825500 /lava-11518300/1/../bin/lava-test-case
11554 17:36:42.859850 <8>[ 40.991167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11555 17:36:42.860145 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11557 17:36:43.913341 /lava-11518300/1/../bin/lava-test-case
11558 17:36:43.947645 <8>[ 42.078841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11559 17:36:43.947965 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11561 17:36:43.971626 /lava-11518300/1/../bin/lava-test-case
11562 17:36:44.002655 <8>[ 42.134145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11563 17:36:44.002951 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11565 17:36:44.027121 /lava-11518300/1/../bin/lava-test-case
11566 17:36:44.056274 <8>[ 42.187489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11567 17:36:44.056579 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11569 17:36:45.106054 /lava-11518300/1/../bin/lava-test-case
11570 17:36:45.139289 <8>[ 43.270663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11571 17:36:45.139651 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11573 17:36:45.165540 /lava-11518300/1/../bin/lava-test-case
11574 17:36:45.196086 <8>[ 43.327498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11575 17:36:45.196364 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11577 17:36:45.231313 /lava-11518300/1/../bin/lava-test-case
11578 17:36:45.260543 <8>[ 43.391788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11579 17:36:45.260819 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11581 17:36:45.285115 /lava-11518300/1/../bin/lava-test-case
11582 17:36:45.318520 <8>[ 43.449995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11583 17:36:45.318823 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11585 17:36:45.357907 /lava-11518300/1/../bin/lava-test-case
11586 17:36:45.385695 <8>[ 43.517101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11587 17:36:45.385977 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11589 17:36:45.424274 /lava-11518300/1/../bin/lava-test-case
11590 17:36:45.456884 <8>[ 43.588129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11591 17:36:45.457162 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11593 17:36:45.502158 /lava-11518300/1/../bin/lava-test-case
11594 17:36:45.530832 <8>[ 43.662060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11595 17:36:45.531105 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11597 17:36:45.554612 /lava-11518300/1/../bin/lava-test-case
11598 17:36:45.582391 <8>[ 43.713883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11599 17:36:45.582687 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11601 17:36:45.618370 /lava-11518300/1/../bin/lava-test-case
11602 17:36:45.648735 <8>[ 43.780366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11603 17:36:45.649009 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11605 17:36:45.686466 /lava-11518300/1/../bin/lava-test-case
11606 17:36:45.715619 <8>[ 43.846903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11607 17:36:45.715925 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11609 17:36:45.739758 /lava-11518300/1/../bin/lava-test-case
11610 17:36:45.768224 <8>[ 43.899857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11611 17:36:45.768530 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11613 17:36:45.804983 /lava-11518300/1/../bin/lava-test-case
11614 17:36:45.835164 <8>[ 43.966808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11615 17:36:45.835482 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11617 17:36:45.866242 /lava-11518300/1/../bin/lava-test-case
11618 17:36:45.897329 <8>[ 44.028773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11619 17:36:45.897611 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11621 17:36:45.938897 /lava-11518300/1/../bin/lava-test-case
11622 17:36:45.968468 <8>[ 44.100042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11623 17:36:45.968744 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11625 17:36:45.993036 /lava-11518300/1/../bin/lava-test-case
11626 17:36:46.023003 <8>[ 44.154606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11627 17:36:46.023272 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11629 17:36:46.062762 /lava-11518300/1/../bin/lava-test-case
11630 17:36:46.091868 <8>[ 44.223080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11631 17:36:46.092147 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11633 17:36:46.115001 /lava-11518300/1/../bin/lava-test-case
11634 17:36:46.145039 <8>[ 44.276214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11635 17:36:46.145306 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11637 17:36:46.181564 /lava-11518300/1/../bin/lava-test-case
11638 17:36:46.210652 <8>[ 44.342061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11639 17:36:46.210969 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11641 17:36:46.243738 /lava-11518300/1/../bin/lava-test-case
11642 17:36:46.272788 <8>[ 44.404080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11643 17:36:46.273108 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11645 17:36:46.311344 /lava-11518300/1/../bin/lava-test-case
11646 17:36:46.344261 <8>[ 44.475846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11647 17:36:46.344577 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11649 17:36:46.367822 /lava-11518300/1/../bin/lava-test-case
11650 17:36:46.397311 <8>[ 44.528931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11651 17:36:46.397630 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11653 17:36:47.444652 /lava-11518300/1/../bin/lava-test-case
11654 17:36:47.481290 <8>[ 45.612866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11655 17:36:47.481597 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11657 17:36:47.999956 <6>[ 46.137922] vpu: disabling
11658 17:36:48.002927 <6>[ 46.141038] vproc2: disabling
11659 17:36:48.006447 <6>[ 46.144376] vproc1: disabling
11660 17:36:48.009989 <6>[ 46.147686] vaud18: disabling
11661 17:36:48.016090 <6>[ 46.151202] vsram_others: disabling
11662 17:36:48.019466 <6>[ 46.155161] va09: disabling
11663 17:36:48.022758 <6>[ 46.158329] vsram_md: disabling
11664 17:36:48.026176 <6>[ 46.161891] Vgpu: disabling
11665 17:36:48.526762 /lava-11518300/1/../bin/lava-test-case
11666 17:36:48.558888 <8>[ 46.690397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11667 17:36:48.559172 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11669 17:36:48.585778 /lava-11518300/1/../bin/lava-test-case
11670 17:36:48.621453 <8>[ 46.753302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11671 17:36:48.621720 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11673 17:36:48.663542 /lava-11518300/1/../bin/lava-test-case
11674 17:36:48.700737 <8>[ 46.832444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11675 17:36:48.701005 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11677 17:36:48.729046 /lava-11518300/1/../bin/lava-test-case
11678 17:36:48.763325 <8>[ 46.895187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11679 17:36:48.763605 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11681 17:36:48.804318 /lava-11518300/1/../bin/lava-test-case
11682 17:36:48.842283 <8>[ 46.974083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11683 17:36:48.842588 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11685 17:36:48.876801 /lava-11518300/1/../bin/lava-test-case
11686 17:36:48.907310 <8>[ 47.039206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11687 17:36:48.907636 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11689 17:36:48.945265 /lava-11518300/1/../bin/lava-test-case
11690 17:36:48.980456 <8>[ 47.112275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11691 17:36:48.980780 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11693 17:36:49.005763 /lava-11518300/1/../bin/lava-test-case
11694 17:36:49.039996 <8>[ 47.172032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11695 17:36:49.040282 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11697 17:36:49.079690 /lava-11518300/1/../bin/lava-test-case
11698 17:36:49.110279 <8>[ 47.241921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11699 17:36:49.110557 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11701 17:36:49.135455 /lava-11518300/1/../bin/lava-test-case
11702 17:36:49.168733 <8>[ 47.300042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11703 17:36:49.169019 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11705 17:36:49.215165 /lava-11518300/1/../bin/lava-test-case
11706 17:36:49.249661 <8>[ 47.381647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11707 17:36:49.249947 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11709 17:36:49.274715 /lava-11518300/1/../bin/lava-test-case
11710 17:36:49.308851 <8>[ 47.440641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11711 17:36:49.309136 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11713 17:36:49.350182 /lava-11518300/1/../bin/lava-test-case
11714 17:36:49.383321 <8>[ 47.515261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11715 17:36:49.383632 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11717 17:36:49.409089 /lava-11518300/1/../bin/lava-test-case
11718 17:36:49.442417 <8>[ 47.574268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11719 17:36:49.442691 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11721 17:36:49.483867 /lava-11518300/1/../bin/lava-test-case
11722 17:36:49.516501 <8>[ 47.648397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11723 17:36:49.516780 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11725 17:36:49.550631 /lava-11518300/1/../bin/lava-test-case
11726 17:36:49.581005 <8>[ 47.712601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11727 17:36:49.581277 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11729 17:36:49.621111 /lava-11518300/1/../bin/lava-test-case
11730 17:36:49.655224 <8>[ 47.787317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11731 17:36:49.655525 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11733 17:36:49.679784 /lava-11518300/1/../bin/lava-test-case
11734 17:36:49.711026 <8>[ 47.842909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11735 17:36:49.711313 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11737 17:36:49.749432 /lava-11518300/1/../bin/lava-test-case
11738 17:36:49.783252 <8>[ 47.915154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11739 17:36:49.783587 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11741 17:36:49.807187 /lava-11518300/1/../bin/lava-test-case
11742 17:36:49.837127 <8>[ 47.968520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11743 17:36:49.837399 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11745 17:36:49.879686 /lava-11518300/1/../bin/lava-test-case
11746 17:36:49.911786 <8>[ 48.043599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11747 17:36:49.912068 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11749 17:36:50.947514 /lava-11518300/1/../bin/lava-test-case
11750 17:36:50.979960 <8>[ 49.111664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11751 17:36:50.980243 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11753 17:36:52.018309 /lava-11518300/1/../bin/lava-test-case
11754 17:36:52.051329 <8>[ 50.183225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11755 17:36:52.051665 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11756 17:36:52.051762 Bad test result: blocked
11757 17:36:52.078321 /lava-11518300/1/../bin/lava-test-case
11758 17:36:52.108947 <8>[ 50.241093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11759 17:36:52.109249 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11761 17:36:53.162633 /lava-11518300/1/../bin/lava-test-case
11762 17:36:53.197730 <8>[ 51.330066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11763 17:36:53.198030 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11765 17:36:53.225935 /lava-11518300/1/../bin/lava-test-case
11766 17:36:53.262686 <8>[ 51.394947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11767 17:36:53.262981 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11769 17:36:53.303178 /lava-11518300/1/../bin/lava-test-case
11770 17:36:53.334821 <8>[ 51.467143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11771 17:36:53.335106 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11773 17:36:53.373740 /lava-11518300/1/../bin/lava-test-case
11774 17:36:53.409213 <8>[ 51.541444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11775 17:36:53.409532 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11777 17:36:53.433875 /lava-11518300/1/../bin/lava-test-case
11778 17:36:53.462822 <8>[ 51.595267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11779 17:36:53.463104 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11781 17:36:53.503842 /lava-11518300/1/../bin/lava-test-case
11782 17:36:53.532921 <8>[ 51.665376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11783 17:36:53.533225 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11785 17:36:53.557387 /lava-11518300/1/../bin/lava-test-case
11786 17:36:53.588139 <8>[ 51.720074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11787 17:36:53.588436 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11789 17:36:54.642800 /lava-11518300/1/../bin/lava-test-case
11790 17:36:54.675577 <8>[ 52.808132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11791 17:36:54.675875 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11793 17:36:54.699432 /lava-11518300/1/../bin/lava-test-case
11794 17:36:54.731819 <8>[ 52.864543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11795 17:36:54.732118 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11797 17:36:55.786979 /lava-11518300/1/../bin/lava-test-case
11798 17:36:55.819579 <8>[ 53.952379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11799 17:36:55.819876 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11801 17:36:55.843340 /lava-11518300/1/../bin/lava-test-case
11802 17:36:55.874869 <8>[ 54.007469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11803 17:36:55.875192 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11805 17:36:56.924867 /lava-11518300/1/../bin/lava-test-case
11806 17:36:56.960990 <8>[ 55.093891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11807 17:36:56.961277 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11809 17:36:56.985865 /lava-11518300/1/../bin/lava-test-case
11810 17:36:57.026607 <8>[ 55.158866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11811 17:36:57.027563 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11813 17:36:58.087530 /lava-11518300/1/../bin/lava-test-case
11814 17:36:58.129758 <8>[ 56.262239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11815 17:36:58.130072 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11817 17:36:58.154219 /lava-11518300/1/../bin/lava-test-case
11818 17:36:58.183936 <8>[ 56.316691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11819 17:36:58.184205 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11821 17:36:58.222565 /lava-11518300/1/../bin/lava-test-case
11822 17:36:58.253707 <8>[ 56.386729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11823 17:36:58.254002 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11825 17:36:58.292920 /lava-11518300/1/../bin/lava-test-case
11826 17:36:58.325970 <8>[ 56.458882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11827 17:36:58.326239 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11829 17:36:58.351245 /lava-11518300/1/../bin/lava-test-case
11830 17:36:58.382362 <8>[ 56.514629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11831 17:36:58.382687 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11833 17:36:58.424915 /lava-11518300/1/../bin/lava-test-case
11834 17:36:58.458126 <8>[ 56.590925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11835 17:36:58.458423 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11837 17:36:58.483585 /lava-11518300/1/../bin/lava-test-case
11838 17:36:58.513627 <8>[ 56.646278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11839 17:36:58.513891 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11841 17:36:58.557450 /lava-11518300/1/../bin/lava-test-case
11842 17:36:58.588642 <8>[ 56.721657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11843 17:36:58.588908 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11845 17:36:58.614995 /lava-11518300/1/../bin/lava-test-case
11846 17:36:58.649423 <8>[ 56.782263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11847 17:36:58.649692 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11849 17:36:58.688976 /lava-11518300/1/../bin/lava-test-case
11850 17:36:58.719887 <8>[ 56.852697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11851 17:36:58.720170 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11853 17:36:58.735616 + <8>[ 56.871761] <LAVA_SIGNAL_ENDRUN 1_bootrr 11518300_1.6.2.3.5>
11854 17:36:58.735871 Received signal: <ENDRUN> 1_bootrr 11518300_1.6.2.3.5
11855 17:36:58.735949 Ending use of test pattern.
11856 17:36:58.736024 Ending test lava.1_bootrr (11518300_1.6.2.3.5), duration 29.61
11858 17:36:58.738651 set +x
11859 17:36:58.743324 <LAVA_TEST_RUNNER EXIT>
11860 17:36:58.743630 ok: lava_test_shell seems to have completed
11861 17:36:58.744633 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11862 17:36:58.744776 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11863 17:36:58.744860 end: 4 lava-test-retry (duration 00:00:30) [common]
11864 17:36:58.744945 start: 5 finalize (timeout 00:07:19) [common]
11865 17:36:58.745029 start: 5.1 power-off (timeout 00:00:30) [common]
11866 17:36:58.745178 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11867 17:36:58.821452 >> Command sent successfully.
11868 17:36:58.824066 Returned 0 in 0 seconds
11869 17:36:58.924473 end: 5.1 power-off (duration 00:00:00) [common]
11871 17:36:58.924919 start: 5.2 read-feedback (timeout 00:07:19) [common]
11872 17:36:58.925236 Listened to connection for namespace 'common' for up to 1s
11873 17:36:59.926153 Finalising connection for namespace 'common'
11874 17:36:59.926360 Disconnecting from shell: Finalise
11875 17:36:59.926464 / #
11876 17:37:00.026763 end: 5.2 read-feedback (duration 00:00:01) [common]
11877 17:37:00.026952 end: 5 finalize (duration 00:00:01) [common]
11878 17:37:00.027093 Cleaning after the job
11879 17:37:00.027225 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/ramdisk
11880 17:37:00.030168 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/kernel
11881 17:37:00.042980 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/dtb
11882 17:37:00.043237 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/nfsrootfs
11883 17:37:00.118007 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518300/tftp-deploy-6ezufo9_/modules
11884 17:37:00.125222 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11518300
11885 17:37:00.535226 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11518300
11886 17:37:00.535433 Job finished correctly