Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 136
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 17:40:56.502462 lava-dispatcher, installed at version: 2023.06
2 17:40:56.502717 start: 0 validate
3 17:40:56.502901 Start time: 2023-09-13 17:40:56.502893+00:00 (UTC)
4 17:40:56.503041 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:40:56.503193 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 17:40:56.761536 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:40:56.761764 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:40:57.011531 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:40:57.011697 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:40:57.261468 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:40:57.261622 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 17:40:57.766234 validate duration: 1.26
14 17:40:57.766490 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:40:57.766588 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:40:57.766678 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:40:57.766867 Not decompressing ramdisk as can be used compressed.
18 17:40:57.766953 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 17:40:57.767018 saving as /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/ramdisk/rootfs.cpio.gz
20 17:40:57.767083 total size: 84918747 (80 MB)
21 17:40:57.768285 progress 0 % (0 MB)
22 17:40:57.791032 progress 5 % (4 MB)
23 17:40:57.813730 progress 10 % (8 MB)
24 17:40:57.836372 progress 15 % (12 MB)
25 17:40:57.859463 progress 20 % (16 MB)
26 17:40:57.882893 progress 25 % (20 MB)
27 17:40:57.905869 progress 30 % (24 MB)
28 17:40:57.929211 progress 35 % (28 MB)
29 17:40:57.952281 progress 40 % (32 MB)
30 17:40:57.974927 progress 45 % (36 MB)
31 17:40:57.997258 progress 50 % (40 MB)
32 17:40:58.019856 progress 55 % (44 MB)
33 17:40:58.042498 progress 60 % (48 MB)
34 17:40:58.064995 progress 65 % (52 MB)
35 17:40:58.088192 progress 70 % (56 MB)
36 17:40:58.110406 progress 75 % (60 MB)
37 17:40:58.132866 progress 80 % (64 MB)
38 17:40:58.155221 progress 85 % (68 MB)
39 17:40:58.177556 progress 90 % (72 MB)
40 17:40:58.199708 progress 95 % (76 MB)
41 17:40:58.222331 progress 100 % (80 MB)
42 17:40:58.222636 80 MB downloaded in 0.46 s (177.77 MB/s)
43 17:40:58.222915 end: 1.1.1 http-download (duration 00:00:00) [common]
45 17:40:58.223300 end: 1.1 download-retry (duration 00:00:00) [common]
46 17:40:58.223418 start: 1.2 download-retry (timeout 00:10:00) [common]
47 17:40:58.223505 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 17:40:58.223641 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 17:40:58.223723 saving as /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/kernel/Image
50 17:40:58.223815 total size: 49220096 (46 MB)
51 17:40:58.223910 No compression specified
52 17:40:58.225552 progress 0 % (0 MB)
53 17:40:58.239107 progress 5 % (2 MB)
54 17:40:58.252493 progress 10 % (4 MB)
55 17:40:58.265788 progress 15 % (7 MB)
56 17:40:58.278839 progress 20 % (9 MB)
57 17:40:58.292108 progress 25 % (11 MB)
58 17:40:58.304941 progress 30 % (14 MB)
59 17:40:58.317984 progress 35 % (16 MB)
60 17:40:58.331081 progress 40 % (18 MB)
61 17:40:58.343942 progress 45 % (21 MB)
62 17:40:58.357451 progress 50 % (23 MB)
63 17:40:58.370694 progress 55 % (25 MB)
64 17:40:58.383965 progress 60 % (28 MB)
65 17:40:58.397268 progress 65 % (30 MB)
66 17:40:58.410227 progress 70 % (32 MB)
67 17:40:58.423707 progress 75 % (35 MB)
68 17:40:58.437624 progress 80 % (37 MB)
69 17:40:58.452268 progress 85 % (39 MB)
70 17:40:58.465856 progress 90 % (42 MB)
71 17:40:58.478991 progress 95 % (44 MB)
72 17:40:58.492587 progress 100 % (46 MB)
73 17:40:58.492766 46 MB downloaded in 0.27 s (174.53 MB/s)
74 17:40:58.492969 end: 1.2.1 http-download (duration 00:00:00) [common]
76 17:40:58.493341 end: 1.2 download-retry (duration 00:00:00) [common]
77 17:40:58.493458 start: 1.3 download-retry (timeout 00:09:59) [common]
78 17:40:58.493583 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 17:40:58.493752 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 17:40:58.493846 saving as /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/dtb/mt8192-asurada-spherion-r0.dtb
81 17:40:58.493936 total size: 47278 (0 MB)
82 17:40:58.494026 No compression specified
83 17:40:58.495577 progress 69 % (0 MB)
84 17:40:58.495892 progress 100 % (0 MB)
85 17:40:58.496073 0 MB downloaded in 0.00 s (21.13 MB/s)
86 17:40:58.496248 end: 1.3.1 http-download (duration 00:00:00) [common]
88 17:40:58.496606 end: 1.3 download-retry (duration 00:00:00) [common]
89 17:40:58.496725 start: 1.4 download-retry (timeout 00:09:59) [common]
90 17:40:58.496839 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 17:40:58.496991 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 17:40:58.497090 saving as /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/modules/modules.tar
93 17:40:58.497181 total size: 8628656 (8 MB)
94 17:40:58.497271 Using unxz to decompress xz
95 17:40:58.502327 progress 0 % (0 MB)
96 17:40:58.524651 progress 5 % (0 MB)
97 17:40:58.546859 progress 10 % (0 MB)
98 17:40:58.573709 progress 15 % (1 MB)
99 17:40:58.600688 progress 20 % (1 MB)
100 17:40:58.626646 progress 25 % (2 MB)
101 17:40:58.652943 progress 30 % (2 MB)
102 17:40:58.680096 progress 35 % (2 MB)
103 17:40:58.705169 progress 40 % (3 MB)
104 17:40:58.729623 progress 45 % (3 MB)
105 17:40:58.756456 progress 50 % (4 MB)
106 17:40:58.781966 progress 55 % (4 MB)
107 17:40:58.806891 progress 60 % (4 MB)
108 17:40:58.831861 progress 65 % (5 MB)
109 17:40:58.856891 progress 70 % (5 MB)
110 17:40:58.880857 progress 75 % (6 MB)
111 17:40:58.907504 progress 80 % (6 MB)
112 17:40:58.937498 progress 85 % (7 MB)
113 17:40:58.964735 progress 90 % (7 MB)
114 17:40:58.991002 progress 95 % (7 MB)
115 17:40:59.014189 progress 100 % (8 MB)
116 17:40:59.019416 8 MB downloaded in 0.52 s (15.76 MB/s)
117 17:40:59.019674 end: 1.4.1 http-download (duration 00:00:01) [common]
119 17:40:59.019942 end: 1.4 download-retry (duration 00:00:01) [common]
120 17:40:59.020035 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 17:40:59.020143 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 17:40:59.020228 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 17:40:59.020325 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 17:40:59.020589 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31
125 17:40:59.020760 makedir: /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin
126 17:40:59.020899 makedir: /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/tests
127 17:40:59.021029 makedir: /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/results
128 17:40:59.021178 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-add-keys
129 17:40:59.021361 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-add-sources
130 17:40:59.021525 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-background-process-start
131 17:40:59.021703 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-background-process-stop
132 17:40:59.021873 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-common-functions
133 17:40:59.022031 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-echo-ipv4
134 17:40:59.022193 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-install-packages
135 17:40:59.022354 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-installed-packages
136 17:40:59.022509 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-os-build
137 17:40:59.022669 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-probe-channel
138 17:40:59.022879 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-probe-ip
139 17:40:59.023039 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-target-ip
140 17:40:59.023178 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-target-mac
141 17:40:59.023310 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-target-storage
142 17:40:59.023440 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-case
143 17:40:59.023588 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-event
144 17:40:59.023810 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-feedback
145 17:40:59.023984 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-raise
146 17:40:59.024116 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-reference
147 17:40:59.024248 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-runner
148 17:40:59.024374 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-set
149 17:40:59.024511 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-test-shell
150 17:40:59.024674 Updating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-install-packages (oe)
151 17:40:59.024865 Updating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/bin/lava-installed-packages (oe)
152 17:40:59.025028 Creating /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/environment
153 17:40:59.025161 LAVA metadata
154 17:40:59.025264 - LAVA_JOB_ID=11518283
155 17:40:59.025359 - LAVA_DISPATCHER_IP=192.168.201.1
156 17:40:59.025496 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 17:40:59.025604 skipped lava-vland-overlay
158 17:40:59.025716 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 17:40:59.025839 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 17:40:59.025905 skipped lava-multinode-overlay
161 17:40:59.025981 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 17:40:59.026066 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 17:40:59.026172 Loading test definitions
164 17:40:59.026295 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 17:40:59.026411 Using /lava-11518283 at stage 0
166 17:40:59.026549 Fetching tests from https://github.com/kernelci/kernelci-core
167 17:40:59.026663 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/0/tests/0_sleep'
168 17:40:59.683156 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/0/tests/0_sleep
169 17:40:59.684496 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 17:40:59.684893 uuid=11518283_1.5.2.3.1 testdef=None
171 17:40:59.685040 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 17:40:59.685294 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 17:40:59.685864 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 17:40:59.686095 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 17:40:59.686946 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 17:40:59.687191 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 17:40:59.687889 runner path: /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/0/tests/0_sleep test_uuid 11518283_1.5.2.3.1
181 17:40:59.687972 sleep_params='mem freeze'
182 17:40:59.688114 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 17:40:59.688322 Creating lava-test-runner.conf files
185 17:40:59.688387 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11518283/lava-overlay-8y97pq31/lava-11518283/0 for stage 0
186 17:40:59.688478 - 0_sleep
187 17:40:59.688584 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 17:40:59.688669 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 17:40:59.816362 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 17:40:59.816515 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 17:40:59.816638 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 17:40:59.816758 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 17:40:59.816851 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 17:41:02.274997 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 17:41:02.275390 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 17:41:02.275503 extracting modules file /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11518283/extract-overlay-ramdisk-i4rkqlh6/ramdisk
197 17:41:02.527429 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 17:41:02.527599 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 17:41:02.527693 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518283/compress-overlay-k3tqynsy/overlay-1.5.2.4.tar.gz to ramdisk
200 17:41:02.527771 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518283/compress-overlay-k3tqynsy/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11518283/extract-overlay-ramdisk-i4rkqlh6/ramdisk
201 17:41:02.635428 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 17:41:02.635605 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 17:41:02.635731 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 17:41:02.635857 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 17:41:02.635967 Building ramdisk /var/lib/lava/dispatcher/tmp/11518283/extract-overlay-ramdisk-i4rkqlh6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11518283/extract-overlay-ramdisk-i4rkqlh6/ramdisk
206 17:41:04.211908 >> 563437 blocks
207 17:41:13.819462 rename /var/lib/lava/dispatcher/tmp/11518283/extract-overlay-ramdisk-i4rkqlh6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/ramdisk/ramdisk.cpio.gz
208 17:41:13.819897 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 17:41:13.820020 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 17:41:13.820116 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 17:41:13.820235 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/kernel/Image'
212 17:41:25.992642 Returned 0 in 12 seconds
213 17:41:26.093805 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/kernel/image.itb
214 17:41:27.440983 output: FIT description: Kernel Image image with one or more FDT blobs
215 17:41:27.441364 output: Created: Wed Sep 13 18:41:27 2023
216 17:41:27.441439 output: Image 0 (kernel-1)
217 17:41:27.441509 output: Description:
218 17:41:27.441575 output: Created: Wed Sep 13 18:41:27 2023
219 17:41:27.441637 output: Type: Kernel Image
220 17:41:27.441699 output: Compression: lzma compressed
221 17:41:27.441758 output: Data Size: 11039249 Bytes = 10780.52 KiB = 10.53 MiB
222 17:41:27.441820 output: Architecture: AArch64
223 17:41:27.441881 output: OS: Linux
224 17:41:27.441935 output: Load Address: 0x00000000
225 17:41:27.441989 output: Entry Point: 0x00000000
226 17:41:27.442042 output: Hash algo: crc32
227 17:41:27.442138 output: Hash value: 2ab54ae9
228 17:41:27.442223 output: Image 1 (fdt-1)
229 17:41:27.442276 output: Description: mt8192-asurada-spherion-r0
230 17:41:27.442330 output: Created: Wed Sep 13 18:41:27 2023
231 17:41:27.442384 output: Type: Flat Device Tree
232 17:41:27.442437 output: Compression: uncompressed
233 17:41:27.442490 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 17:41:27.442544 output: Architecture: AArch64
235 17:41:27.442596 output: Hash algo: crc32
236 17:41:27.442649 output: Hash value: cc4352de
237 17:41:27.442702 output: Image 2 (ramdisk-1)
238 17:41:27.442804 output: Description: unavailable
239 17:41:27.442857 output: Created: Wed Sep 13 18:41:27 2023
240 17:41:27.442911 output: Type: RAMDisk Image
241 17:41:27.442964 output: Compression: Unknown Compression
242 17:41:27.443017 output: Data Size: 98336475 Bytes = 96031.71 KiB = 93.78 MiB
243 17:41:27.443071 output: Architecture: AArch64
244 17:41:27.443124 output: OS: Linux
245 17:41:27.443178 output: Load Address: unavailable
246 17:41:27.443231 output: Entry Point: unavailable
247 17:41:27.443283 output: Hash algo: crc32
248 17:41:27.443336 output: Hash value: de79475e
249 17:41:27.443388 output: Default Configuration: 'conf-1'
250 17:41:27.443441 output: Configuration 0 (conf-1)
251 17:41:27.443493 output: Description: mt8192-asurada-spherion-r0
252 17:41:27.443546 output: Kernel: kernel-1
253 17:41:27.443599 output: Init Ramdisk: ramdisk-1
254 17:41:27.443652 output: FDT: fdt-1
255 17:41:27.443704 output: Loadables: kernel-1
256 17:41:27.443756 output:
257 17:41:27.443960 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 17:41:27.444056 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 17:41:27.444163 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 17:41:27.444262 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:30) [common]
261 17:41:27.444342 No LXC device requested
262 17:41:27.444441 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 17:41:27.444529 start: 1.7 deploy-device-env (timeout 00:09:30) [common]
264 17:41:27.444610 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 17:41:27.444680 Checking files for TFTP limit of 4294967296 bytes.
266 17:41:27.445186 end: 1 tftp-deploy (duration 00:00:30) [common]
267 17:41:27.445291 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 17:41:27.445386 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 17:41:27.445513 substitutions:
270 17:41:27.445582 - {DTB}: 11518283/tftp-deploy-ox_jgt1_/dtb/mt8192-asurada-spherion-r0.dtb
271 17:41:27.445647 - {INITRD}: 11518283/tftp-deploy-ox_jgt1_/ramdisk/ramdisk.cpio.gz
272 17:41:27.445707 - {KERNEL}: 11518283/tftp-deploy-ox_jgt1_/kernel/Image
273 17:41:27.445765 - {LAVA_MAC}: None
274 17:41:27.445823 - {PRESEED_CONFIG}: None
275 17:41:27.445879 - {PRESEED_LOCAL}: None
276 17:41:27.445936 - {RAMDISK}: 11518283/tftp-deploy-ox_jgt1_/ramdisk/ramdisk.cpio.gz
277 17:41:27.445991 - {ROOT_PART}: None
278 17:41:27.446046 - {ROOT}: None
279 17:41:27.446101 - {SERVER_IP}: 192.168.201.1
280 17:41:27.446156 - {TEE}: None
281 17:41:27.446210 Parsed boot commands:
282 17:41:27.446266 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 17:41:27.446468 Parsed boot commands: tftpboot 192.168.201.1 11518283/tftp-deploy-ox_jgt1_/kernel/image.itb 11518283/tftp-deploy-ox_jgt1_/kernel/cmdline
284 17:41:27.446564 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 17:41:27.446653 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 17:41:27.446776 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 17:41:27.446878 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 17:41:27.446952 Not connected, no need to disconnect.
289 17:41:27.447027 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 17:41:27.447107 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 17:41:27.447177 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
292 17:41:27.451259 Setting prompt string to ['lava-test: # ']
293 17:41:27.451631 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 17:41:27.451737 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 17:41:27.451839 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 17:41:27.451929 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 17:41:27.452140 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
298 17:41:32.586748 >> Command sent successfully.
299 17:41:32.589193 Returned 0 in 5 seconds
300 17:41:32.689594 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 17:41:32.689922 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 17:41:32.690048 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 17:41:32.690168 Setting prompt string to 'Starting depthcharge on Spherion...'
305 17:41:32.690256 Changing prompt to 'Starting depthcharge on Spherion...'
306 17:41:32.690326 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 17:41:32.690599 [Enter `^Ec?' for help]
308 17:41:32.864665
309 17:41:32.864806
310 17:41:32.864883 F0: 102B 0000
311 17:41:32.864948
312 17:41:32.865014 F3: 1001 0000 [0200]
313 17:41:32.867403
314 17:41:32.867520 F3: 1001 0000
315 17:41:32.867618
316 17:41:32.867712 F7: 102D 0000
317 17:41:32.867803
318 17:41:32.871228 F1: 0000 0000
319 17:41:32.871317
320 17:41:32.871385 V0: 0000 0000 [0001]
321 17:41:32.871451
322 17:41:32.874118 00: 0007 8000
323 17:41:32.874226
324 17:41:32.874318 01: 0000 0000
325 17:41:32.874415
326 17:41:32.877555 BP: 0C00 0209 [0000]
327 17:41:32.877661
328 17:41:32.877756 G0: 1182 0000
329 17:41:32.877845
330 17:41:32.881339 EC: 0000 0021 [4000]
331 17:41:32.881440
332 17:41:32.881537 S7: 0000 0000 [0000]
333 17:41:32.881627
334 17:41:32.884878 CC: 0000 0000 [0001]
335 17:41:32.884955
336 17:41:32.885017 T0: 0000 0040 [010F]
337 17:41:32.885077
338 17:41:32.885147 Jump to BL
339 17:41:32.885235
340 17:41:32.911082
341 17:41:32.911202
342 17:41:32.911301
343 17:41:32.918464 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 17:41:32.922663 ARM64: Exception handlers installed.
345 17:41:32.926212 ARM64: Testing exception
346 17:41:32.929566 ARM64: Done test exception
347 17:41:32.935966 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 17:41:32.946617 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 17:41:32.952940 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 17:41:32.962989 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 17:41:32.969592 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 17:41:32.976235 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 17:41:32.988253 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 17:41:32.995021 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 17:41:33.014425 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 17:41:33.017388 WDT: Last reset was cold boot
357 17:41:33.021094 SPI1(PAD0) initialized at 2873684 Hz
358 17:41:33.024042 SPI5(PAD0) initialized at 992727 Hz
359 17:41:33.027798 VBOOT: Loading verstage.
360 17:41:33.034223 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 17:41:33.037610 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 17:41:33.040931 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 17:41:33.044068 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 17:41:33.051374 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 17:41:33.058486 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 17:41:33.069113 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
367 17:41:33.069202
368 17:41:33.069268
369 17:41:33.079554 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 17:41:33.082524 ARM64: Exception handlers installed.
371 17:41:33.086079 ARM64: Testing exception
372 17:41:33.086162 ARM64: Done test exception
373 17:41:33.092878 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 17:41:33.095867 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 17:41:33.110295 Probing TPM: . done!
376 17:41:33.110377 TPM ready after 0 ms
377 17:41:33.117183 Connected to device vid:did:rid of 1ae0:0028:00
378 17:41:33.123989 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 17:41:33.191113 Initialized TPM device CR50 revision 0
380 17:41:33.203164 tlcl_send_startup: Startup return code is 0
381 17:41:33.203263 TPM: setup succeeded
382 17:41:33.214806 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 17:41:33.223656 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 17:41:33.238212 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 17:41:33.246318 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 17:41:33.249352 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 17:41:33.253048 in-header: 03 07 00 00 08 00 00 00
388 17:41:33.256828 in-data: aa e4 47 04 13 02 00 00
389 17:41:33.256912 Chrome EC: UHEPI supported
390 17:41:33.264308 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 17:41:33.267887 in-header: 03 ad 00 00 08 00 00 00
392 17:41:33.271665 in-data: 00 20 20 08 00 00 00 00
393 17:41:33.271749 Phase 1
394 17:41:33.275640 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 17:41:33.283087 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 17:41:33.290483 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 17:41:33.290621 Recovery requested (1009000e)
398 17:41:33.300395 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 17:41:33.305813 tlcl_extend: response is 0
400 17:41:33.315054 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 17:41:33.320623 tlcl_extend: response is 0
402 17:41:33.327739 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 17:41:33.347716 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
404 17:41:33.354504 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 17:41:33.354588
406 17:41:33.354698
407 17:41:33.365310 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 17:41:33.368927 ARM64: Exception handlers installed.
409 17:41:33.369010 ARM64: Testing exception
410 17:41:33.372090 ARM64: Done test exception
411 17:41:33.390222 pmic_efuse_setting: Set efuses in 11 msecs
412 17:41:33.398589 pmwrap_interface_init: Select PMIF_VLD_RDY
413 17:41:33.401541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 17:41:33.408331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 17:41:33.411885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 17:41:33.416213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 17:41:33.423131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 17:41:33.426925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 17:41:33.431130 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 17:41:33.434827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 17:41:33.441786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 17:41:33.445335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 17:41:33.449008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 17:41:33.452835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 17:41:33.460216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 17:41:33.464434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 17:41:33.471728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 17:41:33.475333 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 17:41:33.482380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 17:41:33.490508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 17:41:33.493600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 17:41:33.501261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 17:41:33.505231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 17:41:33.512404 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 17:41:33.516233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 17:41:33.519946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 17:41:33.526889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 17:41:33.531172 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 17:41:33.538056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 17:41:33.542354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 17:41:33.545971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 17:41:33.552976 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 17:41:33.556601 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 17:41:33.560420 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 17:41:33.567884 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 17:41:33.571565 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 17:41:33.578927 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 17:41:33.582567 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 17:41:33.586376 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 17:41:33.593755 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 17:41:33.597444 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 17:41:33.601095 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 17:41:33.604602 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 17:41:33.608265 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 17:41:33.615516 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 17:41:33.619875 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 17:41:33.623381 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 17:41:33.626853 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 17:41:33.630830 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 17:41:33.634315 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 17:41:33.642233 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 17:41:33.645449 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 17:41:33.649658 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 17:41:33.656987 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 17:41:33.664928 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 17:41:33.668228 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 17:41:33.675595 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 17:41:33.686658 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 17:41:33.690213 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 17:41:33.694010 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 17:41:33.697562 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 17:41:33.706144 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x10
473 17:41:33.709869 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 17:41:33.718134 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 17:41:33.721363 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 17:41:33.730408 [RTC]rtc_get_frequency_meter,154: input=15, output=789
477 17:41:33.740397 [RTC]rtc_get_frequency_meter,154: input=23, output=978
478 17:41:33.750080 [RTC]rtc_get_frequency_meter,154: input=19, output=884
479 17:41:33.758888 [RTC]rtc_get_frequency_meter,154: input=17, output=836
480 17:41:33.768426 [RTC]rtc_get_frequency_meter,154: input=16, output=813
481 17:41:33.778456 [RTC]rtc_get_frequency_meter,154: input=15, output=789
482 17:41:33.787922 [RTC]rtc_get_frequency_meter,154: input=16, output=813
483 17:41:33.791040 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
484 17:41:33.798285 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
485 17:41:33.802014 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 17:41:33.806206 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 17:41:33.809256 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 17:41:33.813313 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 17:41:33.817155 ADC[4]: Raw value=901697 ID=7
490 17:41:33.820496 ADC[3]: Raw value=213336 ID=1
491 17:41:33.820574 RAM Code: 0x71
492 17:41:33.824289 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 17:41:33.831391 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 17:41:33.839175 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 17:41:33.846441 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 17:41:33.850044 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 17:41:33.853713 in-header: 03 07 00 00 08 00 00 00
498 17:41:33.853794 in-data: aa e4 47 04 13 02 00 00
499 17:41:33.857329 Chrome EC: UHEPI supported
500 17:41:33.864626 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 17:41:33.868346 in-header: 03 ed 00 00 08 00 00 00
502 17:41:33.871951 in-data: 80 20 60 08 00 00 00 00
503 17:41:33.875578 MRC: failed to locate region type 0.
504 17:41:33.883484 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 17:41:33.883608 DRAM-K: Running full calibration
506 17:41:33.890563 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 17:41:33.894385 header.status = 0x0
508 17:41:33.894486 header.version = 0x6 (expected: 0x6)
509 17:41:33.897961 header.size = 0xd00 (expected: 0xd00)
510 17:41:33.901644 header.flags = 0x0
511 17:41:33.909039 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 17:41:33.925250 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
513 17:41:33.933099 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 17:41:33.933313 dram_init: ddr_geometry: 2
515 17:41:33.937014 [EMI] MDL number = 2
516 17:41:33.940350 [EMI] Get MDL freq = 0
517 17:41:33.940463 dram_init: ddr_type: 0
518 17:41:33.944132 is_discrete_lpddr4: 1
519 17:41:33.947856 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 17:41:33.947946
521 17:41:33.948009
522 17:41:33.948068 [Bian_co] ETT version 0.0.0.1
523 17:41:33.955686 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 17:41:33.955772
525 17:41:33.959309 dramc_set_vcore_voltage set vcore to 650000
526 17:41:33.959402 Read voltage for 800, 4
527 17:41:33.959467 Vio18 = 0
528 17:41:33.963068 Vcore = 650000
529 17:41:33.963147 Vdram = 0
530 17:41:33.963220 Vddq = 0
531 17:41:33.966533 Vmddr = 0
532 17:41:33.966635 dram_init: config_dvfs: 1
533 17:41:33.973613 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 17:41:33.977471 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 17:41:33.980447 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
536 17:41:33.984040 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
537 17:41:33.990628 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
538 17:41:33.993746 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
539 17:41:33.993820 MEM_TYPE=3, freq_sel=18
540 17:41:33.997322 sv_algorithm_assistance_LP4_1600
541 17:41:34.003745 ============ PULL DRAM RESETB DOWN ============
542 17:41:34.007219 ========== PULL DRAM RESETB DOWN end =========
543 17:41:34.010824 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 17:41:34.013836 ===================================
545 17:41:34.017660 LPDDR4 DRAM CONFIGURATION
546 17:41:34.020778 ===================================
547 17:41:34.020860 EX_ROW_EN[0] = 0x0
548 17:41:34.024400 EX_ROW_EN[1] = 0x0
549 17:41:34.024471 LP4Y_EN = 0x0
550 17:41:34.027479 WORK_FSP = 0x0
551 17:41:34.030588 WL = 0x2
552 17:41:34.030666 RL = 0x2
553 17:41:34.034343 BL = 0x2
554 17:41:34.034427 RPST = 0x0
555 17:41:34.037387 RD_PRE = 0x0
556 17:41:34.037480 WR_PRE = 0x1
557 17:41:34.040923 WR_PST = 0x0
558 17:41:34.040996 DBI_WR = 0x0
559 17:41:34.043802 DBI_RD = 0x0
560 17:41:34.043900 OTF = 0x1
561 17:41:34.047338 ===================================
562 17:41:34.050962 ===================================
563 17:41:34.054438 ANA top config
564 17:41:34.057429 ===================================
565 17:41:34.057501 DLL_ASYNC_EN = 0
566 17:41:34.060983 ALL_SLAVE_EN = 1
567 17:41:34.064030 NEW_RANK_MODE = 1
568 17:41:34.067578 DLL_IDLE_MODE = 1
569 17:41:34.067651 LP45_APHY_COMB_EN = 1
570 17:41:34.071110 TX_ODT_DIS = 1
571 17:41:34.074467 NEW_8X_MODE = 1
572 17:41:34.077943 ===================================
573 17:41:34.081359 ===================================
574 17:41:34.084409 data_rate = 1600
575 17:41:34.088016 CKR = 1
576 17:41:34.088099 DQ_P2S_RATIO = 8
577 17:41:34.090999 ===================================
578 17:41:34.094623 CA_P2S_RATIO = 8
579 17:41:34.097655 DQ_CA_OPEN = 0
580 17:41:34.101304 DQ_SEMI_OPEN = 0
581 17:41:34.104309 CA_SEMI_OPEN = 0
582 17:41:34.104385 CA_FULL_RATE = 0
583 17:41:34.107853 DQ_CKDIV4_EN = 1
584 17:41:34.111409 CA_CKDIV4_EN = 1
585 17:41:34.114372 CA_PREDIV_EN = 0
586 17:41:34.117797 PH8_DLY = 0
587 17:41:34.121339 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 17:41:34.121413 DQ_AAMCK_DIV = 4
589 17:41:34.124358 CA_AAMCK_DIV = 4
590 17:41:34.128096 CA_ADMCK_DIV = 4
591 17:41:34.131133 DQ_TRACK_CA_EN = 0
592 17:41:34.134875 CA_PICK = 800
593 17:41:34.138319 CA_MCKIO = 800
594 17:41:34.138422 MCKIO_SEMI = 0
595 17:41:34.142457 PLL_FREQ = 3068
596 17:41:34.146181 DQ_UI_PI_RATIO = 32
597 17:41:34.150253 CA_UI_PI_RATIO = 0
598 17:41:34.150333 ===================================
599 17:41:34.153441 ===================================
600 17:41:34.157708 memory_type:LPDDR4
601 17:41:34.161339 GP_NUM : 10
602 17:41:34.161422 SRAM_EN : 1
603 17:41:34.165203 MD32_EN : 0
604 17:41:34.165281 ===================================
605 17:41:34.168997 [ANA_INIT] >>>>>>>>>>>>>>
606 17:41:34.172653 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 17:41:34.175576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 17:41:34.179190 ===================================
609 17:41:34.182584 data_rate = 1600,PCW = 0X7600
610 17:41:34.185650 ===================================
611 17:41:34.189083 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 17:41:34.192515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 17:41:34.199376 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 17:41:34.202387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 17:41:34.206239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 17:41:34.209194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 17:41:34.212879 [ANA_INIT] flow start
618 17:41:34.215999 [ANA_INIT] PLL >>>>>>>>
619 17:41:34.216077 [ANA_INIT] PLL <<<<<<<<
620 17:41:34.219578 [ANA_INIT] MIDPI >>>>>>>>
621 17:41:34.222583 [ANA_INIT] MIDPI <<<<<<<<
622 17:41:34.222691 [ANA_INIT] DLL >>>>>>>>
623 17:41:34.226122 [ANA_INIT] flow end
624 17:41:34.229809 ============ LP4 DIFF to SE enter ============
625 17:41:34.232924 ============ LP4 DIFF to SE exit ============
626 17:41:34.236107 [ANA_INIT] <<<<<<<<<<<<<
627 17:41:34.239616 [Flow] Enable top DCM control >>>>>
628 17:41:34.243280 [Flow] Enable top DCM control <<<<<
629 17:41:34.246152 Enable DLL master slave shuffle
630 17:41:34.252992 ==============================================================
631 17:41:34.253071 Gating Mode config
632 17:41:34.259788 ==============================================================
633 17:41:34.259871 Config description:
634 17:41:34.269919 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 17:41:34.276537 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 17:41:34.283464 SELPH_MODE 0: By rank 1: By Phase
637 17:41:34.295925 ==============================================================
638 17:41:34.296013 GAT_TRACK_EN = 1
639 17:41:34.296079 RX_GATING_MODE = 2
640 17:41:34.296563 RX_GATING_TRACK_MODE = 2
641 17:41:34.299773 SELPH_MODE = 1
642 17:41:34.303353 PICG_EARLY_EN = 1
643 17:41:34.307093 VALID_LAT_VALUE = 1
644 17:41:34.310175 ==============================================================
645 17:41:34.313342 Enter into Gating configuration >>>>
646 17:41:34.317002 Exit from Gating configuration <<<<
647 17:41:34.320110 Enter into DVFS_PRE_config >>>>>
648 17:41:34.333550 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 17:41:34.333704 Exit from DVFS_PRE_config <<<<<
650 17:41:34.337024 Enter into PICG configuration >>>>
651 17:41:34.340408 Exit from PICG configuration <<<<
652 17:41:34.344104 [RX_INPUT] configuration >>>>>
653 17:41:34.347090 [RX_INPUT] configuration <<<<<
654 17:41:34.354108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 17:41:34.358221 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 17:41:34.365078 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 17:41:34.371812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 17:41:34.375410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 17:41:34.382199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 17:41:34.385027 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 17:41:34.388389 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 17:41:34.395321 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 17:41:34.398778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 17:41:34.401987 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 17:41:34.409050 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 17:41:34.411752 ===================================
667 17:41:34.412061 LPDDR4 DRAM CONFIGURATION
668 17:41:34.415417 ===================================
669 17:41:34.418427 EX_ROW_EN[0] = 0x0
670 17:41:34.418683 EX_ROW_EN[1] = 0x0
671 17:41:34.422030 LP4Y_EN = 0x0
672 17:41:34.422214 WORK_FSP = 0x0
673 17:41:34.425035 WL = 0x2
674 17:41:34.428695 RL = 0x2
675 17:41:34.428849 BL = 0x2
676 17:41:34.431516 RPST = 0x0
677 17:41:34.431648 RD_PRE = 0x0
678 17:41:34.434964 WR_PRE = 0x1
679 17:41:34.435098 WR_PST = 0x0
680 17:41:34.438580 DBI_WR = 0x0
681 17:41:34.438696 DBI_RD = 0x0
682 17:41:34.441929 OTF = 0x1
683 17:41:34.445408 ===================================
684 17:41:34.448701 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 17:41:34.451755 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 17:41:34.455335 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 17:41:34.458306 ===================================
688 17:41:34.461787 LPDDR4 DRAM CONFIGURATION
689 17:41:34.465411 ===================================
690 17:41:34.468590 EX_ROW_EN[0] = 0x10
691 17:41:34.468698 EX_ROW_EN[1] = 0x0
692 17:41:34.472058 LP4Y_EN = 0x0
693 17:41:34.472142 WORK_FSP = 0x0
694 17:41:34.474988 WL = 0x2
695 17:41:34.475071 RL = 0x2
696 17:41:34.478535 BL = 0x2
697 17:41:34.478642 RPST = 0x0
698 17:41:34.481685 RD_PRE = 0x0
699 17:41:34.481771 WR_PRE = 0x1
700 17:41:34.485029 WR_PST = 0x0
701 17:41:34.485112 DBI_WR = 0x0
702 17:41:34.488781 DBI_RD = 0x0
703 17:41:34.488866 OTF = 0x1
704 17:41:34.491817 ===================================
705 17:41:34.498673 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 17:41:34.503211 nWR fixed to 40
707 17:41:34.506697 [ModeRegInit_LP4] CH0 RK0
708 17:41:34.506825 [ModeRegInit_LP4] CH0 RK1
709 17:41:34.510368 [ModeRegInit_LP4] CH1 RK0
710 17:41:34.513251 [ModeRegInit_LP4] CH1 RK1
711 17:41:34.513336 match AC timing 13
712 17:41:34.520005 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 17:41:34.523545 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 17:41:34.527153 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 17:41:34.533851 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 17:41:34.537025 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 17:41:34.537109 [EMI DOE] emi_dcm 0
718 17:41:34.544234 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 17:41:34.544319 ==
720 17:41:34.547127 Dram Type= 6, Freq= 0, CH_0, rank 0
721 17:41:34.550382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 17:41:34.550493 ==
723 17:41:34.556854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 17:41:34.560385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 17:41:34.571007 [CA 0] Center 37 (7~68) winsize 62
726 17:41:34.574588 [CA 1] Center 37 (6~68) winsize 63
727 17:41:34.577852 [CA 2] Center 35 (5~65) winsize 61
728 17:41:34.581032 [CA 3] Center 34 (4~65) winsize 62
729 17:41:34.584705 [CA 4] Center 34 (4~65) winsize 62
730 17:41:34.587958 [CA 5] Center 33 (3~64) winsize 62
731 17:41:34.588044
732 17:41:34.591395 [CmdBusTrainingLP45] Vref(ca) range 1: 32
733 17:41:34.591480
734 17:41:34.594238 [CATrainingPosCal] consider 1 rank data
735 17:41:34.597770 u2DelayCellTimex100 = 270/100 ps
736 17:41:34.601272 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 17:41:34.604583 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 17:41:34.608048 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
739 17:41:34.615048 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 17:41:34.617922 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
741 17:41:34.621353 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 17:41:34.621438
743 17:41:34.624529 CA PerBit enable=1, Macro0, CA PI delay=33
744 17:41:34.624612
745 17:41:34.628194 [CBTSetCACLKResult] CA Dly = 33
746 17:41:34.628278 CS Dly: 5 (0~36)
747 17:41:34.628343 ==
748 17:41:34.631832 Dram Type= 6, Freq= 0, CH_0, rank 1
749 17:41:34.637957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 17:41:34.638042 ==
751 17:41:34.641362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 17:41:34.648113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 17:41:34.657160 [CA 0] Center 37 (6~68) winsize 63
754 17:41:34.660383 [CA 1] Center 37 (6~68) winsize 63
755 17:41:34.663899 [CA 2] Center 35 (5~66) winsize 62
756 17:41:34.667357 [CA 3] Center 34 (4~65) winsize 62
757 17:41:34.670938 [CA 4] Center 34 (3~65) winsize 63
758 17:41:34.673926 [CA 5] Center 33 (3~64) winsize 62
759 17:41:34.674010
760 17:41:34.677490 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 17:41:34.677575
762 17:41:34.680484 [CATrainingPosCal] consider 2 rank data
763 17:41:34.684064 u2DelayCellTimex100 = 270/100 ps
764 17:41:34.687371 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 17:41:34.690828 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
766 17:41:34.697545 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
767 17:41:34.700569 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 17:41:34.704202 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
769 17:41:34.707155 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 17:41:34.707239
771 17:41:34.710827 CA PerBit enable=1, Macro0, CA PI delay=33
772 17:41:34.710911
773 17:41:34.714346 [CBTSetCACLKResult] CA Dly = 33
774 17:41:34.714430 CS Dly: 5 (0~37)
775 17:41:34.714496
776 17:41:34.717500 ----->DramcWriteLeveling(PI) begin...
777 17:41:34.717586 ==
778 17:41:34.720918 Dram Type= 6, Freq= 0, CH_0, rank 0
779 17:41:34.724904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 17:41:34.728283 ==
781 17:41:34.728369 Write leveling (Byte 0): 28 => 28
782 17:41:34.732620 Write leveling (Byte 1): 28 => 28
783 17:41:34.735617 DramcWriteLeveling(PI) end<-----
784 17:41:34.735701
785 17:41:34.735767 ==
786 17:41:34.739350 Dram Type= 6, Freq= 0, CH_0, rank 0
787 17:41:34.742299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 17:41:34.742384 ==
789 17:41:34.746125 [Gating] SW mode calibration
790 17:41:34.753212 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 17:41:34.760044 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 17:41:34.763173 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 17:41:34.766604 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 17:41:34.773239 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 17:41:34.776651 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 17:41:34.779791 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 17:41:34.786561 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 17:41:34.789603 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 17:41:34.793270 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 17:41:34.796292 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 17:41:34.803459 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 17:41:34.806345 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 17:41:34.810134 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 17:41:34.816478 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 17:41:34.819874 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 17:41:34.823545 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 17:41:34.830146 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 17:41:34.833651 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 17:41:34.837020 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 17:41:34.844022 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
811 17:41:34.847277 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
812 17:41:34.850112 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 17:41:34.857206 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 17:41:34.860357 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 17:41:34.863933 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 17:41:34.867094 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 17:41:34.873814 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 17:41:34.877221 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 17:41:34.880386 0 9 12 | B1->B0 | 2828 3030 | 0 0 | (0 0) (1 1)
820 17:41:34.887511 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 17:41:34.890336 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 17:41:34.894007 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 17:41:34.900584 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 17:41:34.904105 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 17:41:34.907567 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
826 17:41:34.914263 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
827 17:41:34.917941 0 10 12 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
828 17:41:34.920866 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 17:41:34.927488 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 17:41:34.930827 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 17:41:34.934463 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 17:41:34.937705 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 17:41:34.944320 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 17:41:34.947349 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
835 17:41:34.950601 0 11 12 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
836 17:41:34.957520 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
837 17:41:34.960878 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 17:41:34.964347 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 17:41:34.971198 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 17:41:34.974260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 17:41:34.977904 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 17:41:34.984249 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
843 17:41:34.987816 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 17:41:34.990921 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 17:41:34.994456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 17:41:35.001161 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 17:41:35.004949 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 17:41:35.007888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 17:41:35.015021 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 17:41:35.017909 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 17:41:35.021744 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 17:41:35.028178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 17:41:35.031628 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 17:41:35.034810 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 17:41:35.041550 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 17:41:35.045085 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 17:41:35.048346 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 17:41:35.055272 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 17:41:35.055692 Total UI for P1: 0, mck2ui 16
860 17:41:35.058459 best dqsien dly found for B0: ( 0, 14, 6)
861 17:41:35.065107 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 17:41:35.068391 Total UI for P1: 0, mck2ui 16
863 17:41:35.072201 best dqsien dly found for B1: ( 0, 14, 8)
864 17:41:35.075452 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
865 17:41:35.078504 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 17:41:35.078969
867 17:41:35.082372 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
868 17:41:35.085074 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 17:41:35.088683 [Gating] SW calibration Done
870 17:41:35.089154 ==
871 17:41:35.091715 Dram Type= 6, Freq= 0, CH_0, rank 0
872 17:41:35.095185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 17:41:35.095619 ==
874 17:41:35.098847 RX Vref Scan: 0
875 17:41:35.099282
876 17:41:35.099621 RX Vref 0 -> 0, step: 1
877 17:41:35.099934
878 17:41:35.102132 RX Delay -130 -> 252, step: 16
879 17:41:35.105610 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 17:41:35.112492 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 17:41:35.115760 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 17:41:35.118840 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 17:41:35.122012 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
884 17:41:35.125748 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 17:41:35.132302 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
886 17:41:35.135486 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
887 17:41:35.138839 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 17:41:35.142555 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 17:41:35.145517 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 17:41:35.152004 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 17:41:35.155594 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 17:41:35.159231 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 17:41:35.162358 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 17:41:35.165354 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 17:41:35.165882 ==
896 17:41:35.168854 Dram Type= 6, Freq= 0, CH_0, rank 0
897 17:41:35.175563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 17:41:35.175994 ==
899 17:41:35.176346 DQS Delay:
900 17:41:35.178972 DQS0 = 0, DQS1 = 0
901 17:41:35.179403 DQM Delay:
902 17:41:35.179739 DQM0 = 85, DQM1 = 78
903 17:41:35.182430 DQ Delay:
904 17:41:35.185651 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 17:41:35.188988 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
906 17:41:35.192181 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
907 17:41:35.195794 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
908 17:41:35.196225
909 17:41:35.196563
910 17:41:35.196872 ==
911 17:41:35.199133 Dram Type= 6, Freq= 0, CH_0, rank 0
912 17:41:35.202229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 17:41:35.202666 ==
914 17:41:35.203059
915 17:41:35.203379
916 17:41:35.205731 TX Vref Scan disable
917 17:41:35.206322 == TX Byte 0 ==
918 17:41:35.212576 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
919 17:41:35.215900 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
920 17:41:35.216328 == TX Byte 1 ==
921 17:41:35.222677 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
922 17:41:35.226293 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
923 17:41:35.226755 ==
924 17:41:35.229715 Dram Type= 6, Freq= 0, CH_0, rank 0
925 17:41:35.233045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 17:41:35.233580 ==
927 17:41:35.246324 TX Vref=22, minBit 7, minWin=26, winSum=438
928 17:41:35.249800 TX Vref=24, minBit 3, minWin=27, winSum=443
929 17:41:35.252877 TX Vref=26, minBit 5, minWin=27, winSum=447
930 17:41:35.256407 TX Vref=28, minBit 12, minWin=27, winSum=449
931 17:41:35.260395 TX Vref=30, minBit 5, minWin=27, winSum=452
932 17:41:35.263273 TX Vref=32, minBit 0, minWin=28, winSum=451
933 17:41:35.270173 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
934 17:41:35.270794
935 17:41:35.273479 Final TX Range 1 Vref 32
936 17:41:35.273945
937 17:41:35.274309 ==
938 17:41:35.276482 Dram Type= 6, Freq= 0, CH_0, rank 0
939 17:41:35.280262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 17:41:35.280836 ==
941 17:41:35.281348
942 17:41:35.281707
943 17:41:35.283164 TX Vref Scan disable
944 17:41:35.286803 == TX Byte 0 ==
945 17:41:35.290302 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 17:41:35.293651 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 17:41:35.297385 == TX Byte 1 ==
948 17:41:35.300189 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 17:41:35.303652 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 17:41:35.304121
951 17:41:35.307205 [DATLAT]
952 17:41:35.307859 Freq=800, CH0 RK0
953 17:41:35.308283
954 17:41:35.310056 DATLAT Default: 0xa
955 17:41:35.310521 0, 0xFFFF, sum = 0
956 17:41:35.313929 1, 0xFFFF, sum = 0
957 17:41:35.314539 2, 0xFFFF, sum = 0
958 17:41:35.316865 3, 0xFFFF, sum = 0
959 17:41:35.317342 4, 0xFFFF, sum = 0
960 17:41:35.320532 5, 0xFFFF, sum = 0
961 17:41:35.321450 6, 0xFFFF, sum = 0
962 17:41:35.323278 7, 0xFFFF, sum = 0
963 17:41:35.323751 8, 0xFFFF, sum = 0
964 17:41:35.326533 9, 0x0, sum = 1
965 17:41:35.327082 10, 0x0, sum = 2
966 17:41:35.329993 11, 0x0, sum = 3
967 17:41:35.330464 12, 0x0, sum = 4
968 17:41:35.333779 best_step = 10
969 17:41:35.334196
970 17:41:35.334524 ==
971 17:41:35.336674 Dram Type= 6, Freq= 0, CH_0, rank 0
972 17:41:35.340068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 17:41:35.340490 ==
974 17:41:35.343430 RX Vref Scan: 1
975 17:41:35.343847
976 17:41:35.344177 Set Vref Range= 32 -> 127
977 17:41:35.344483
978 17:41:35.347215 RX Vref 32 -> 127, step: 1
979 17:41:35.347816
980 17:41:35.350193 RX Delay -95 -> 252, step: 8
981 17:41:35.350611
982 17:41:35.353481 Set Vref, RX VrefLevel [Byte0]: 32
983 17:41:35.356783 [Byte1]: 32
984 17:41:35.357203
985 17:41:35.360814 Set Vref, RX VrefLevel [Byte0]: 33
986 17:41:35.364759 [Byte1]: 33
987 17:41:35.365282
988 17:41:35.367505 Set Vref, RX VrefLevel [Byte0]: 34
989 17:41:35.370506 [Byte1]: 34
990 17:41:35.374216
991 17:41:35.374642 Set Vref, RX VrefLevel [Byte0]: 35
992 17:41:35.377724 [Byte1]: 35
993 17:41:35.381958
994 17:41:35.382398 Set Vref, RX VrefLevel [Byte0]: 36
995 17:41:35.385430 [Byte1]: 36
996 17:41:35.390485
997 17:41:35.391013 Set Vref, RX VrefLevel [Byte0]: 37
998 17:41:35.393345 [Byte1]: 37
999 17:41:35.397399
1000 17:41:35.397893 Set Vref, RX VrefLevel [Byte0]: 38
1001 17:41:35.400306 [Byte1]: 38
1002 17:41:35.404987
1003 17:41:35.405513 Set Vref, RX VrefLevel [Byte0]: 39
1004 17:41:35.408116 [Byte1]: 39
1005 17:41:35.412729
1006 17:41:35.413153 Set Vref, RX VrefLevel [Byte0]: 40
1007 17:41:35.415854 [Byte1]: 40
1008 17:41:35.420147
1009 17:41:35.420569 Set Vref, RX VrefLevel [Byte0]: 41
1010 17:41:35.423184 [Byte1]: 41
1011 17:41:35.427541
1012 17:41:35.428102 Set Vref, RX VrefLevel [Byte0]: 42
1013 17:41:35.430977 [Byte1]: 42
1014 17:41:35.435354
1015 17:41:35.435900 Set Vref, RX VrefLevel [Byte0]: 43
1016 17:41:35.438498 [Byte1]: 43
1017 17:41:35.442795
1018 17:41:35.443231 Set Vref, RX VrefLevel [Byte0]: 44
1019 17:41:35.445995 [Byte1]: 44
1020 17:41:35.450090
1021 17:41:35.450517 Set Vref, RX VrefLevel [Byte0]: 45
1022 17:41:35.453279 [Byte1]: 45
1023 17:41:35.458080
1024 17:41:35.458603 Set Vref, RX VrefLevel [Byte0]: 46
1025 17:41:35.461377 [Byte1]: 46
1026 17:41:35.465580
1027 17:41:35.466198 Set Vref, RX VrefLevel [Byte0]: 47
1028 17:41:35.468540 [Byte1]: 47
1029 17:41:35.472800
1030 17:41:35.473357 Set Vref, RX VrefLevel [Byte0]: 48
1031 17:41:35.476542 [Byte1]: 48
1032 17:41:35.480607
1033 17:41:35.481029 Set Vref, RX VrefLevel [Byte0]: 49
1034 17:41:35.483871 [Byte1]: 49
1035 17:41:35.487906
1036 17:41:35.488326 Set Vref, RX VrefLevel [Byte0]: 50
1037 17:41:35.491937 [Byte1]: 50
1038 17:41:35.495913
1039 17:41:35.496438 Set Vref, RX VrefLevel [Byte0]: 51
1040 17:41:35.499405 [Byte1]: 51
1041 17:41:35.503500
1042 17:41:35.503922 Set Vref, RX VrefLevel [Byte0]: 52
1043 17:41:35.507219 [Byte1]: 52
1044 17:41:35.511429
1045 17:41:35.511956 Set Vref, RX VrefLevel [Byte0]: 53
1046 17:41:35.514362 [Byte1]: 53
1047 17:41:35.518849
1048 17:41:35.519274 Set Vref, RX VrefLevel [Byte0]: 54
1049 17:41:35.521840 [Byte1]: 54
1050 17:41:35.526339
1051 17:41:35.526913 Set Vref, RX VrefLevel [Byte0]: 55
1052 17:41:35.529365 [Byte1]: 55
1053 17:41:35.533772
1054 17:41:35.534307 Set Vref, RX VrefLevel [Byte0]: 56
1055 17:41:35.537726 [Byte1]: 56
1056 17:41:35.541525
1057 17:41:35.542055 Set Vref, RX VrefLevel [Byte0]: 57
1058 17:41:35.544485 [Byte1]: 57
1059 17:41:35.548933
1060 17:41:35.549409 Set Vref, RX VrefLevel [Byte0]: 58
1061 17:41:35.552247 [Byte1]: 58
1062 17:41:35.556385
1063 17:41:35.556808 Set Vref, RX VrefLevel [Byte0]: 59
1064 17:41:35.559856 [Byte1]: 59
1065 17:41:35.564082
1066 17:41:35.564605 Set Vref, RX VrefLevel [Byte0]: 60
1067 17:41:35.567769 [Byte1]: 60
1068 17:41:35.571463
1069 17:41:35.571887 Set Vref, RX VrefLevel [Byte0]: 61
1070 17:41:35.575078 [Byte1]: 61
1071 17:41:35.579661
1072 17:41:35.580192 Set Vref, RX VrefLevel [Byte0]: 62
1073 17:41:35.583175 [Byte1]: 62
1074 17:41:35.587083
1075 17:41:35.587557 Set Vref, RX VrefLevel [Byte0]: 63
1076 17:41:35.590115 [Byte1]: 63
1077 17:41:35.594476
1078 17:41:35.595082 Set Vref, RX VrefLevel [Byte0]: 64
1079 17:41:35.598105 [Byte1]: 64
1080 17:41:35.602449
1081 17:41:35.603061 Set Vref, RX VrefLevel [Byte0]: 65
1082 17:41:35.606047 [Byte1]: 65
1083 17:41:35.610179
1084 17:41:35.610799 Set Vref, RX VrefLevel [Byte0]: 66
1085 17:41:35.612919 [Byte1]: 66
1086 17:41:35.617207
1087 17:41:35.617667 Set Vref, RX VrefLevel [Byte0]: 67
1088 17:41:35.620997 [Byte1]: 67
1089 17:41:35.625489
1090 17:41:35.626004 Set Vref, RX VrefLevel [Byte0]: 68
1091 17:41:35.628433 [Byte1]: 68
1092 17:41:35.632528
1093 17:41:35.633087 Set Vref, RX VrefLevel [Byte0]: 69
1094 17:41:35.635633 [Byte1]: 69
1095 17:41:35.640557
1096 17:41:35.641224 Set Vref, RX VrefLevel [Byte0]: 70
1097 17:41:35.643532 [Byte1]: 70
1098 17:41:35.648001
1099 17:41:35.648485 Set Vref, RX VrefLevel [Byte0]: 71
1100 17:41:35.650775 [Byte1]: 71
1101 17:41:35.655669
1102 17:41:35.656229 Set Vref, RX VrefLevel [Byte0]: 72
1103 17:41:35.658622 [Byte1]: 72
1104 17:41:35.663199
1105 17:41:35.663825 Set Vref, RX VrefLevel [Byte0]: 73
1106 17:41:35.666324 [Byte1]: 73
1107 17:41:35.670664
1108 17:41:35.671179 Set Vref, RX VrefLevel [Byte0]: 74
1109 17:41:35.673810 [Byte1]: 74
1110 17:41:35.678147
1111 17:41:35.678711 Set Vref, RX VrefLevel [Byte0]: 75
1112 17:41:35.681847 [Byte1]: 75
1113 17:41:35.685828
1114 17:41:35.686401 Set Vref, RX VrefLevel [Byte0]: 76
1115 17:41:35.689523 [Byte1]: 76
1116 17:41:35.693389
1117 17:41:35.693974 Set Vref, RX VrefLevel [Byte0]: 77
1118 17:41:35.697258 [Byte1]: 77
1119 17:41:35.701109
1120 17:41:35.701576 Set Vref, RX VrefLevel [Byte0]: 78
1121 17:41:35.704420 [Byte1]: 78
1122 17:41:35.708438
1123 17:41:35.708903 Final RX Vref Byte 0 = 63 to rank0
1124 17:41:35.712119 Final RX Vref Byte 1 = 58 to rank0
1125 17:41:35.715109 Final RX Vref Byte 0 = 63 to rank1
1126 17:41:35.718891 Final RX Vref Byte 1 = 58 to rank1==
1127 17:41:35.722314 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 17:41:35.725741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 17:41:35.729245 ==
1130 17:41:35.729812 DQS Delay:
1131 17:41:35.730181 DQS0 = 0, DQS1 = 0
1132 17:41:35.731841 DQM Delay:
1133 17:41:35.732349 DQM0 = 87, DQM1 = 78
1134 17:41:35.735476 DQ Delay:
1135 17:41:35.735898 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1136 17:41:35.738637 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1137 17:41:35.742309 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1138 17:41:35.745463 DQ12 =80, DQ13 =80, DQ14 =92, DQ15 =88
1139 17:41:35.746116
1140 17:41:35.746576
1141 17:41:35.755270 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1142 17:41:35.758648 CH0 RK0: MR19=606, MR18=280F
1143 17:41:35.765480 CH0_RK0: MR19=0x606, MR18=0x280F, DQSOSC=399, MR23=63, INC=92, DEC=61
1144 17:41:35.766063
1145 17:41:35.768731 ----->DramcWriteLeveling(PI) begin...
1146 17:41:35.769178 ==
1147 17:41:35.772222 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 17:41:35.775464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 17:41:35.775896 ==
1150 17:41:35.779019 Write leveling (Byte 0): 29 => 29
1151 17:41:35.782513 Write leveling (Byte 1): 28 => 28
1152 17:41:35.785675 DramcWriteLeveling(PI) end<-----
1153 17:41:35.786111
1154 17:41:35.786448 ==
1155 17:41:35.788623 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 17:41:35.792128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 17:41:35.792622 ==
1158 17:41:35.795824 [Gating] SW mode calibration
1159 17:41:35.839694 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 17:41:35.840318 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 17:41:35.840697 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 17:41:35.841049 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 17:41:35.841719 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1164 17:41:35.842083 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 17:41:35.842416 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 17:41:35.842767 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 17:41:35.843096 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 17:41:35.883945 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 17:41:35.884484 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 17:41:35.884860 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 17:41:35.885535 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 17:41:35.885923 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 17:41:35.886261 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 17:41:35.886586 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 17:41:35.886971 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 17:41:35.887296 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 17:41:35.887609 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1178 17:41:35.905392 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1179 17:41:35.905960 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1180 17:41:35.906339 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1181 17:41:35.906688 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 17:41:35.908821 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 17:41:35.912460 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 17:41:35.912947 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 17:41:35.915459 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 17:41:35.922147 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 17:41:35.925889 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1188 17:41:35.929222 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1189 17:41:35.936089 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 17:41:35.939148 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 17:41:35.942381 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 17:41:35.949116 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 17:41:35.952232 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 17:41:35.956041 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1195 17:41:35.962846 0 10 8 | B1->B0 | 3131 2525 | 1 0 | (1 1) (0 0)
1196 17:41:35.966551 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 17:41:35.970815 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 17:41:35.973849 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 17:41:35.978144 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 17:41:35.981835 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 17:41:35.988626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 17:41:35.991844 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1203 17:41:35.995434 0 11 8 | B1->B0 | 2828 4242 | 0 1 | (0 0) (0 0)
1204 17:41:35.999238 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1205 17:41:36.005587 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 17:41:36.009277 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 17:41:36.012542 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 17:41:36.019194 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 17:41:36.022838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 17:41:36.025731 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1211 17:41:36.032790 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1212 17:41:36.036003 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 17:41:36.039212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 17:41:36.046708 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 17:41:36.049599 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 17:41:36.053210 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 17:41:36.056283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 17:41:36.062879 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 17:41:36.066552 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 17:41:36.069459 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 17:41:36.076452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 17:41:36.079625 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 17:41:36.083470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 17:41:36.089464 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 17:41:36.093347 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 17:41:36.096469 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1227 17:41:36.103201 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1228 17:41:36.103636 Total UI for P1: 0, mck2ui 16
1229 17:41:36.110510 best dqsien dly found for B0: ( 0, 14, 4)
1230 17:41:36.113708 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1231 17:41:36.116657 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 17:41:36.120072 Total UI for P1: 0, mck2ui 16
1233 17:41:36.123123 best dqsien dly found for B1: ( 0, 14, 10)
1234 17:41:36.126761 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1235 17:41:36.129895 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1236 17:41:36.130334
1237 17:41:36.133616 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1238 17:41:36.136549 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1239 17:41:36.139951 [Gating] SW calibration Done
1240 17:41:36.140532 ==
1241 17:41:36.143282 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 17:41:36.150882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 17:41:36.151482 ==
1244 17:41:36.151828 RX Vref Scan: 0
1245 17:41:36.152144
1246 17:41:36.153315 RX Vref 0 -> 0, step: 1
1247 17:41:36.153737
1248 17:41:36.157380 RX Delay -130 -> 252, step: 16
1249 17:41:36.160873 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1250 17:41:36.163463 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1251 17:41:36.167466 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1252 17:41:36.170417 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1253 17:41:36.176981 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1254 17:41:36.180534 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1255 17:41:36.183673 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1256 17:41:36.186953 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1257 17:41:36.190452 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1258 17:41:36.197079 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1259 17:41:36.200430 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1260 17:41:36.203845 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1261 17:41:36.206749 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1262 17:41:36.210511 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1263 17:41:36.219590 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1264 17:41:36.220749 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1265 17:41:36.221174 ==
1266 17:41:36.223963 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 17:41:36.227264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 17:41:36.227690 ==
1269 17:41:36.228021 DQS Delay:
1270 17:41:36.230344 DQS0 = 0, DQS1 = 0
1271 17:41:36.230797 DQM Delay:
1272 17:41:36.233715 DQM0 = 84, DQM1 = 76
1273 17:41:36.234137 DQ Delay:
1274 17:41:36.237104 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1275 17:41:36.240335 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1276 17:41:36.243650 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1277 17:41:36.247443 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1278 17:41:36.247868
1279 17:41:36.248345
1280 17:41:36.248751 ==
1281 17:41:36.250741 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 17:41:36.253762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 17:41:36.254187 ==
1284 17:41:36.257451
1285 17:41:36.257882
1286 17:41:36.258207 TX Vref Scan disable
1287 17:41:36.261048 == TX Byte 0 ==
1288 17:41:36.263870 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1289 17:41:36.267946 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1290 17:41:36.271120 == TX Byte 1 ==
1291 17:41:36.274448 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1292 17:41:36.277551 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1293 17:41:36.278073 ==
1294 17:41:36.280811 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 17:41:36.287457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 17:41:36.287966 ==
1297 17:41:36.299687 TX Vref=22, minBit 0, minWin=27, winSum=440
1298 17:41:36.302530 TX Vref=24, minBit 3, minWin=27, winSum=444
1299 17:41:36.306120 TX Vref=26, minBit 9, minWin=27, winSum=452
1300 17:41:36.309443 TX Vref=28, minBit 3, minWin=27, winSum=454
1301 17:41:36.312284 TX Vref=30, minBit 12, minWin=27, winSum=452
1302 17:41:36.318944 TX Vref=32, minBit 13, minWin=27, winSum=453
1303 17:41:36.322467 [TxChooseVref] Worse bit 3, Min win 27, Win sum 454, Final Vref 28
1304 17:41:36.322910
1305 17:41:36.326367 Final TX Range 1 Vref 28
1306 17:41:36.326664
1307 17:41:36.326972 ==
1308 17:41:36.329668 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 17:41:36.333017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 17:41:36.333248 ==
1311 17:41:36.333427
1312 17:41:36.333591
1313 17:41:36.335955 TX Vref Scan disable
1314 17:41:36.339697 == TX Byte 0 ==
1315 17:41:36.343080 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1316 17:41:36.346292 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1317 17:41:36.349686 == TX Byte 1 ==
1318 17:41:36.353020 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1319 17:41:36.356959 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1320 17:41:36.357627
1321 17:41:36.359576 [DATLAT]
1322 17:41:36.360125 Freq=800, CH0 RK1
1323 17:41:36.360639
1324 17:41:36.363244 DATLAT Default: 0xa
1325 17:41:36.363930 0, 0xFFFF, sum = 0
1326 17:41:36.367112 1, 0xFFFF, sum = 0
1327 17:41:36.367787 2, 0xFFFF, sum = 0
1328 17:41:36.369729 3, 0xFFFF, sum = 0
1329 17:41:36.370298 4, 0xFFFF, sum = 0
1330 17:41:36.373408 5, 0xFFFF, sum = 0
1331 17:41:36.374116 6, 0xFFFF, sum = 0
1332 17:41:36.376323 7, 0xFFFF, sum = 0
1333 17:41:36.376904 8, 0xFFFF, sum = 0
1334 17:41:36.380032 9, 0x0, sum = 1
1335 17:41:36.380858 10, 0x0, sum = 2
1336 17:41:36.383107 11, 0x0, sum = 3
1337 17:41:36.383679 12, 0x0, sum = 4
1338 17:41:36.386421 best_step = 10
1339 17:41:36.387022
1340 17:41:36.387487 ==
1341 17:41:36.390128 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 17:41:36.393584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 17:41:36.394141 ==
1344 17:41:36.394636 RX Vref Scan: 0
1345 17:41:36.396788
1346 17:41:36.397221 RX Vref 0 -> 0, step: 1
1347 17:41:36.397567
1348 17:41:36.400069 RX Delay -95 -> 252, step: 8
1349 17:41:36.403380 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1350 17:41:36.410604 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1351 17:41:36.413876 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1352 17:41:36.416887 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1353 17:41:36.420755 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1354 17:41:36.423603 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1355 17:41:36.427140 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1356 17:41:36.433838 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1357 17:41:36.437276 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1358 17:41:36.440143 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1359 17:41:36.443627 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1360 17:41:36.447329 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1361 17:41:36.453708 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1362 17:41:36.456931 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1363 17:41:36.460367 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1364 17:41:36.464180 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1365 17:41:36.464689 ==
1366 17:41:36.467264 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 17:41:36.474203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 17:41:36.474934 ==
1369 17:41:36.475288 DQS Delay:
1370 17:41:36.477215 DQS0 = 0, DQS1 = 0
1371 17:41:36.477632 DQM Delay:
1372 17:41:36.477961 DQM0 = 87, DQM1 = 77
1373 17:41:36.480826 DQ Delay:
1374 17:41:36.483835 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1375 17:41:36.487433 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1376 17:41:36.491213 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1377 17:41:36.494062 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1378 17:41:36.494482
1379 17:41:36.494851
1380 17:41:36.500746 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1381 17:41:36.504504 CH0 RK1: MR19=606, MR18=2B14
1382 17:41:36.511016 CH0_RK1: MR19=0x606, MR18=0x2B14, DQSOSC=398, MR23=63, INC=93, DEC=62
1383 17:41:36.514231 [RxdqsGatingPostProcess] freq 800
1384 17:41:36.517349 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 17:41:36.520780 Pre-setting of DQS Precalculation
1386 17:41:36.527917 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 17:41:36.528446 ==
1388 17:41:36.530901 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 17:41:36.534542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 17:41:36.535154 ==
1391 17:41:36.537500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 17:41:36.544770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 17:41:36.553949 [CA 0] Center 36 (6~66) winsize 61
1394 17:41:36.557201 [CA 1] Center 36 (6~66) winsize 61
1395 17:41:36.560759 [CA 2] Center 34 (4~65) winsize 62
1396 17:41:36.564407 [CA 3] Center 33 (3~64) winsize 62
1397 17:41:36.567418 [CA 4] Center 34 (4~65) winsize 62
1398 17:41:36.571198 [CA 5] Center 33 (3~64) winsize 62
1399 17:41:36.571615
1400 17:41:36.574664 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 17:41:36.575129
1402 17:41:36.578131 [CATrainingPosCal] consider 1 rank data
1403 17:41:36.580700 u2DelayCellTimex100 = 270/100 ps
1404 17:41:36.584156 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1405 17:41:36.587793 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1406 17:41:36.591015 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1407 17:41:36.597995 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1408 17:41:36.601199 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1409 17:41:36.604252 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1410 17:41:36.604669
1411 17:41:36.607895 CA PerBit enable=1, Macro0, CA PI delay=33
1412 17:41:36.608312
1413 17:41:36.610887 [CBTSetCACLKResult] CA Dly = 33
1414 17:41:36.611308 CS Dly: 4 (0~35)
1415 17:41:36.611640 ==
1416 17:41:36.614579 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 17:41:36.621425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 17:41:36.621987 ==
1419 17:41:36.624662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 17:41:36.631374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 17:41:36.640348 [CA 0] Center 36 (6~66) winsize 61
1422 17:41:36.644335 [CA 1] Center 36 (6~66) winsize 61
1423 17:41:36.648040 [CA 2] Center 34 (4~65) winsize 62
1424 17:41:36.652058 [CA 3] Center 33 (3~64) winsize 62
1425 17:41:36.655616 [CA 4] Center 34 (4~65) winsize 62
1426 17:41:36.656036 [CA 5] Center 33 (3~64) winsize 62
1427 17:41:36.656362
1428 17:41:36.659143 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 17:41:36.663447
1430 17:41:36.663938 [CATrainingPosCal] consider 2 rank data
1431 17:41:36.667155 u2DelayCellTimex100 = 270/100 ps
1432 17:41:36.670706 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1433 17:41:36.674400 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1434 17:41:36.677273 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1435 17:41:36.681069 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1436 17:41:36.687456 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 17:41:36.690661 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1438 17:41:36.691140
1439 17:41:36.694088 CA PerBit enable=1, Macro0, CA PI delay=33
1440 17:41:36.694507
1441 17:41:36.697589 [CBTSetCACLKResult] CA Dly = 33
1442 17:41:36.698004 CS Dly: 5 (0~37)
1443 17:41:36.698333
1444 17:41:36.701206 ----->DramcWriteLeveling(PI) begin...
1445 17:41:36.701644 ==
1446 17:41:36.704258 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 17:41:36.707416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 17:41:36.710796 ==
1449 17:41:36.711219 Write leveling (Byte 0): 27 => 27
1450 17:41:36.714259 Write leveling (Byte 1): 32 => 32
1451 17:41:36.717482 DramcWriteLeveling(PI) end<-----
1452 17:41:36.717971
1453 17:41:36.718441 ==
1454 17:41:36.721038 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 17:41:36.727517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 17:41:36.727992 ==
1457 17:41:36.728486 [Gating] SW mode calibration
1458 17:41:36.737461 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 17:41:36.740899 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 17:41:36.744557 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 17:41:36.751195 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 17:41:36.754585 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 17:41:36.758270 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 17:41:36.764881 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 17:41:36.768486 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 17:41:36.771676 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 17:41:36.777873 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 17:41:36.781223 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1469 17:41:36.784947 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 17:41:36.791469 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 17:41:36.795043 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1472 17:41:36.798291 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1473 17:41:36.801633 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1474 17:41:36.808162 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 17:41:36.811807 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1476 17:41:36.814817 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 17:41:36.821900 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1478 17:41:36.825105 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1479 17:41:36.828593 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 17:41:36.835045 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 17:41:36.838214 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 17:41:36.841784 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 17:41:36.848657 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 17:41:36.851729 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 17:41:36.855145 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 17:41:36.858813 0 9 8 | B1->B0 | 2525 2525 | 0 1 | (0 0) (1 1)
1487 17:41:36.865324 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1488 17:41:36.868943 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 17:41:36.871841 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1490 17:41:36.878443 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 17:41:36.882077 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 17:41:36.885537 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 17:41:36.892623 0 10 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 0)
1494 17:41:36.895620 0 10 8 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
1495 17:41:36.899162 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 17:41:36.902170 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 17:41:36.908928 0 10 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1498 17:41:36.912250 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1499 17:41:36.915619 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 17:41:36.922392 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 17:41:36.926241 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 17:41:36.929234 0 11 8 | B1->B0 | 3636 3232 | 1 0 | (0 0) (0 0)
1503 17:41:36.935811 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 17:41:36.939412 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 17:41:36.942673 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 17:41:36.949268 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 17:41:36.952550 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 17:41:36.956174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 17:41:36.963083 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1510 17:41:36.966059 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1511 17:41:36.969508 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 17:41:36.973158 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 17:41:36.979216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 17:41:36.982711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 17:41:36.986262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 17:41:36.992862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 17:41:36.996249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 17:41:36.999570 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 17:41:37.006214 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 17:41:37.009719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 17:41:37.012805 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 17:41:37.016190 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 17:41:37.023187 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 17:41:37.026785 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 17:41:37.030225 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1526 17:41:37.036614 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1527 17:41:37.040058 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 17:41:37.043651 Total UI for P1: 0, mck2ui 16
1529 17:41:37.046480 best dqsien dly found for B0: ( 0, 14, 6)
1530 17:41:37.050154 Total UI for P1: 0, mck2ui 16
1531 17:41:37.053137 best dqsien dly found for B1: ( 0, 14, 6)
1532 17:41:37.056975 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1533 17:41:37.059944 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1534 17:41:37.060051
1535 17:41:37.063840 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1536 17:41:37.067051 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1537 17:41:37.070378 [Gating] SW calibration Done
1538 17:41:37.070589 ==
1539 17:41:37.073438 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 17:41:37.077062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 17:41:37.077270 ==
1542 17:41:37.080227 RX Vref Scan: 0
1543 17:41:37.080452
1544 17:41:37.084002 RX Vref 0 -> 0, step: 1
1545 17:41:37.084262
1546 17:41:37.084432 RX Delay -130 -> 252, step: 16
1547 17:41:37.090307 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1548 17:41:37.093759 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1549 17:41:37.097006 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1550 17:41:37.100642 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1551 17:41:37.103851 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1552 17:41:37.110684 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1553 17:41:37.114122 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1554 17:41:37.117666 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1555 17:41:37.120747 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1556 17:41:37.124344 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1557 17:41:37.127416 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1558 17:41:37.134158 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1559 17:41:37.137813 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1560 17:41:37.140830 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1561 17:41:37.144416 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1562 17:41:37.151061 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1563 17:41:37.151519 ==
1564 17:41:37.154140 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 17:41:37.158047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 17:41:37.158678 ==
1567 17:41:37.159145 DQS Delay:
1568 17:41:37.160718 DQS0 = 0, DQS1 = 0
1569 17:41:37.161204 DQM Delay:
1570 17:41:37.164235 DQM0 = 82, DQM1 = 75
1571 17:41:37.164650 DQ Delay:
1572 17:41:37.167490 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1573 17:41:37.170892 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1574 17:41:37.174285 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1575 17:41:37.177864 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1576 17:41:37.178337
1577 17:41:37.178664
1578 17:41:37.179050 ==
1579 17:41:37.180881 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 17:41:37.184259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 17:41:37.184807 ==
1582 17:41:37.185146
1583 17:41:37.185455
1584 17:41:37.187725 TX Vref Scan disable
1585 17:41:37.191398 == TX Byte 0 ==
1586 17:41:37.194281 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1587 17:41:37.197675 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1588 17:41:37.201414 == TX Byte 1 ==
1589 17:41:37.204313 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1590 17:41:37.207940 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1591 17:41:37.208368 ==
1592 17:41:37.210915 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 17:41:37.214515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 17:41:37.214981 ==
1595 17:41:37.229402 TX Vref=22, minBit 11, minWin=26, winSum=439
1596 17:41:37.232768 TX Vref=24, minBit 0, minWin=27, winSum=443
1597 17:41:37.236171 TX Vref=26, minBit 7, minWin=27, winSum=445
1598 17:41:37.239148 TX Vref=28, minBit 8, minWin=27, winSum=451
1599 17:41:37.242502 TX Vref=30, minBit 1, minWin=28, winSum=454
1600 17:41:37.245600 TX Vref=32, minBit 1, minWin=28, winSum=456
1601 17:41:37.252784 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
1602 17:41:37.253221
1603 17:41:37.255836 Final TX Range 1 Vref 32
1604 17:41:37.256346
1605 17:41:37.256746 ==
1606 17:41:37.259515 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 17:41:37.262379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 17:41:37.262859 ==
1609 17:41:37.263306
1610 17:41:37.263723
1611 17:41:37.266210 TX Vref Scan disable
1612 17:41:37.269652 == TX Byte 0 ==
1613 17:41:37.272558 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1614 17:41:37.276221 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1615 17:41:37.279510 == TX Byte 1 ==
1616 17:41:37.282810 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1617 17:41:37.286270 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1618 17:41:37.286949
1619 17:41:37.289608 [DATLAT]
1620 17:41:37.290220 Freq=800, CH1 RK0
1621 17:41:37.290792
1622 17:41:37.292861 DATLAT Default: 0xa
1623 17:41:37.293476 0, 0xFFFF, sum = 0
1624 17:41:37.295693 1, 0xFFFF, sum = 0
1625 17:41:37.296080 2, 0xFFFF, sum = 0
1626 17:41:37.299620 3, 0xFFFF, sum = 0
1627 17:41:37.299931 4, 0xFFFF, sum = 0
1628 17:41:37.302984 5, 0xFFFF, sum = 0
1629 17:41:37.303346 6, 0xFFFF, sum = 0
1630 17:41:37.306096 7, 0xFFFF, sum = 0
1631 17:41:37.306533 8, 0xFFFF, sum = 0
1632 17:41:37.309445 9, 0x0, sum = 1
1633 17:41:37.309890 10, 0x0, sum = 2
1634 17:41:37.312682 11, 0x0, sum = 3
1635 17:41:37.313113 12, 0x0, sum = 4
1636 17:41:37.316126 best_step = 10
1637 17:41:37.316616
1638 17:41:37.317053 ==
1639 17:41:37.319450 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 17:41:37.323274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 17:41:37.323591 ==
1642 17:41:37.326248 RX Vref Scan: 1
1643 17:41:37.326573
1644 17:41:37.326957 Set Vref Range= 32 -> 127
1645 17:41:37.327269
1646 17:41:37.329335 RX Vref 32 -> 127, step: 1
1647 17:41:37.329727
1648 17:41:37.333021 RX Delay -95 -> 252, step: 8
1649 17:41:37.333393
1650 17:41:37.336230 Set Vref, RX VrefLevel [Byte0]: 32
1651 17:41:37.339677 [Byte1]: 32
1652 17:41:37.340001
1653 17:41:37.342947 Set Vref, RX VrefLevel [Byte0]: 33
1654 17:41:37.346401 [Byte1]: 33
1655 17:41:37.346937
1656 17:41:37.349583 Set Vref, RX VrefLevel [Byte0]: 34
1657 17:41:37.352655 [Byte1]: 34
1658 17:41:37.356993
1659 17:41:37.357265 Set Vref, RX VrefLevel [Byte0]: 35
1660 17:41:37.360063 [Byte1]: 35
1661 17:41:37.364307
1662 17:41:37.364472 Set Vref, RX VrefLevel [Byte0]: 36
1663 17:41:37.368110 [Byte1]: 36
1664 17:41:37.371738
1665 17:41:37.371823 Set Vref, RX VrefLevel [Byte0]: 37
1666 17:41:37.375219 [Byte1]: 37
1667 17:41:37.379261
1668 17:41:37.379345 Set Vref, RX VrefLevel [Byte0]: 38
1669 17:41:37.382876 [Byte1]: 38
1670 17:41:37.387050
1671 17:41:37.387134 Set Vref, RX VrefLevel [Byte0]: 39
1672 17:41:37.390642 [Byte1]: 39
1673 17:41:37.394713
1674 17:41:37.394811 Set Vref, RX VrefLevel [Byte0]: 40
1675 17:41:37.398429 [Byte1]: 40
1676 17:41:37.402252
1677 17:41:37.402336 Set Vref, RX VrefLevel [Byte0]: 41
1678 17:41:37.405402 [Byte1]: 41
1679 17:41:37.409859
1680 17:41:37.409942 Set Vref, RX VrefLevel [Byte0]: 42
1681 17:41:37.413054 [Byte1]: 42
1682 17:41:37.417516
1683 17:41:37.417599 Set Vref, RX VrefLevel [Byte0]: 43
1684 17:41:37.420632 [Byte1]: 43
1685 17:41:37.425269
1686 17:41:37.425352 Set Vref, RX VrefLevel [Byte0]: 44
1687 17:41:37.428126 [Byte1]: 44
1688 17:41:37.432595
1689 17:41:37.432678 Set Vref, RX VrefLevel [Byte0]: 45
1690 17:41:37.435878 [Byte1]: 45
1691 17:41:37.440711
1692 17:41:37.440822 Set Vref, RX VrefLevel [Byte0]: 46
1693 17:41:37.443525 [Byte1]: 46
1694 17:41:37.447683
1695 17:41:37.447766 Set Vref, RX VrefLevel [Byte0]: 47
1696 17:41:37.451399 [Byte1]: 47
1697 17:41:37.455758
1698 17:41:37.455841 Set Vref, RX VrefLevel [Byte0]: 48
1699 17:41:37.458627 [Byte1]: 48
1700 17:41:37.462976
1701 17:41:37.463115 Set Vref, RX VrefLevel [Byte0]: 49
1702 17:41:37.466613 [Byte1]: 49
1703 17:41:37.470751
1704 17:41:37.470943 Set Vref, RX VrefLevel [Byte0]: 50
1705 17:41:37.473803 [Byte1]: 50
1706 17:41:37.478642
1707 17:41:37.478755 Set Vref, RX VrefLevel [Byte0]: 51
1708 17:41:37.481658 [Byte1]: 51
1709 17:41:37.486117
1710 17:41:37.486197 Set Vref, RX VrefLevel [Byte0]: 52
1711 17:41:37.489178 [Byte1]: 52
1712 17:41:37.493543
1713 17:41:37.493617 Set Vref, RX VrefLevel [Byte0]: 53
1714 17:41:37.496962 [Byte1]: 53
1715 17:41:37.501322
1716 17:41:37.501399 Set Vref, RX VrefLevel [Byte0]: 54
1717 17:41:37.504173 [Byte1]: 54
1718 17:41:37.510437
1719 17:41:37.510580 Set Vref, RX VrefLevel [Byte0]: 55
1720 17:41:37.511894 [Byte1]: 55
1721 17:41:37.516370
1722 17:41:37.516444 Set Vref, RX VrefLevel [Byte0]: 56
1723 17:41:37.519366 [Byte1]: 56
1724 17:41:37.523957
1725 17:41:37.524095 Set Vref, RX VrefLevel [Byte0]: 57
1726 17:41:37.527256 [Byte1]: 57
1727 17:41:37.531422
1728 17:41:37.531510 Set Vref, RX VrefLevel [Byte0]: 58
1729 17:41:37.535165 [Byte1]: 58
1730 17:41:37.539500
1731 17:41:37.539640 Set Vref, RX VrefLevel [Byte0]: 59
1732 17:41:37.542317 [Byte1]: 59
1733 17:41:37.546596
1734 17:41:37.546759 Set Vref, RX VrefLevel [Byte0]: 60
1735 17:41:37.550133 [Byte1]: 60
1736 17:41:37.554484
1737 17:41:37.554609 Set Vref, RX VrefLevel [Byte0]: 61
1738 17:41:37.557310 [Byte1]: 61
1739 17:41:37.561757
1740 17:41:37.561933 Set Vref, RX VrefLevel [Byte0]: 62
1741 17:41:37.564980 [Byte1]: 62
1742 17:41:37.569588
1743 17:41:37.569673 Set Vref, RX VrefLevel [Byte0]: 63
1744 17:41:37.573084 [Byte1]: 63
1745 17:41:37.577207
1746 17:41:37.577289 Set Vref, RX VrefLevel [Byte0]: 64
1747 17:41:37.580188 [Byte1]: 64
1748 17:41:37.584454
1749 17:41:37.584536 Set Vref, RX VrefLevel [Byte0]: 65
1750 17:41:37.588195 [Byte1]: 65
1751 17:41:37.592011
1752 17:41:37.595780 Set Vref, RX VrefLevel [Byte0]: 66
1753 17:41:37.598717 [Byte1]: 66
1754 17:41:37.598822
1755 17:41:37.602238 Set Vref, RX VrefLevel [Byte0]: 67
1756 17:41:37.605262 [Byte1]: 67
1757 17:41:37.605373
1758 17:41:37.608960 Set Vref, RX VrefLevel [Byte0]: 68
1759 17:41:37.612508 [Byte1]: 68
1760 17:41:37.612632
1761 17:41:37.615756 Set Vref, RX VrefLevel [Byte0]: 69
1762 17:41:37.619352 [Byte1]: 69
1763 17:41:37.622851
1764 17:41:37.623003 Set Vref, RX VrefLevel [Byte0]: 70
1765 17:41:37.626208 [Byte1]: 70
1766 17:41:37.630207
1767 17:41:37.630480 Set Vref, RX VrefLevel [Byte0]: 71
1768 17:41:37.633504 [Byte1]: 71
1769 17:41:37.637853
1770 17:41:37.637934 Set Vref, RX VrefLevel [Byte0]: 72
1771 17:41:37.641248 [Byte1]: 72
1772 17:41:37.645249
1773 17:41:37.645330 Set Vref, RX VrefLevel [Byte0]: 73
1774 17:41:37.648804 [Byte1]: 73
1775 17:41:37.653091
1776 17:41:37.653173 Set Vref, RX VrefLevel [Byte0]: 74
1777 17:41:37.656098 [Byte1]: 74
1778 17:41:37.660868
1779 17:41:37.660955 Set Vref, RX VrefLevel [Byte0]: 75
1780 17:41:37.664018 [Byte1]: 75
1781 17:41:37.668276
1782 17:41:37.668438 Set Vref, RX VrefLevel [Byte0]: 76
1783 17:41:37.671568 [Byte1]: 76
1784 17:41:37.675761
1785 17:41:37.675955 Final RX Vref Byte 0 = 62 to rank0
1786 17:41:37.678882 Final RX Vref Byte 1 = 58 to rank0
1787 17:41:37.682579 Final RX Vref Byte 0 = 62 to rank1
1788 17:41:37.685679 Final RX Vref Byte 1 = 58 to rank1==
1789 17:41:37.689294 Dram Type= 6, Freq= 0, CH_1, rank 0
1790 17:41:37.696061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 17:41:37.696192 ==
1792 17:41:37.696261 DQS Delay:
1793 17:41:37.696348 DQS0 = 0, DQS1 = 0
1794 17:41:37.699633 DQM Delay:
1795 17:41:37.699720 DQM0 = 82, DQM1 = 75
1796 17:41:37.702471 DQ Delay:
1797 17:41:37.706203 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1798 17:41:37.706291 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1799 17:41:37.709077 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1800 17:41:37.712961 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1801 17:41:37.715933
1802 17:41:37.716016
1803 17:41:37.722618 [DQSOSCAuto] RK0, (LSB)MR18= 0x25fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1804 17:41:37.726143 CH1 RK0: MR19=605, MR18=25FB
1805 17:41:37.733045 CH1_RK0: MR19=0x605, MR18=0x25FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1806 17:41:37.733134
1807 17:41:37.735928 ----->DramcWriteLeveling(PI) begin...
1808 17:41:37.736033 ==
1809 17:41:37.739444 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 17:41:37.742612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 17:41:37.742716 ==
1812 17:41:37.746036 Write leveling (Byte 0): 30 => 30
1813 17:41:37.749548 Write leveling (Byte 1): 27 => 27
1814 17:41:37.752873 DramcWriteLeveling(PI) end<-----
1815 17:41:37.752995
1816 17:41:37.753092 ==
1817 17:41:37.756360 Dram Type= 6, Freq= 0, CH_1, rank 1
1818 17:41:37.759860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1819 17:41:37.759973 ==
1820 17:41:37.762824 [Gating] SW mode calibration
1821 17:41:37.769797 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1822 17:41:37.776434 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1823 17:41:37.779734 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1824 17:41:37.783164 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1825 17:41:37.786116 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 17:41:37.793331 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 17:41:37.796492 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 17:41:37.799916 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 17:41:37.807019 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 17:41:37.809792 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 17:41:37.813441 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 17:41:37.820015 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 17:41:37.823668 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 17:41:37.826918 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 17:41:37.833162 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1836 17:41:37.836734 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 17:41:37.840231 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1838 17:41:37.843216 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 17:41:37.850509 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1840 17:41:37.853552 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1841 17:41:37.857049 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 17:41:37.863596 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 17:41:37.866979 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1844 17:41:37.870082 0 8 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1845 17:41:37.876733 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 17:41:37.880186 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 17:41:37.883752 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1848 17:41:37.890417 0 9 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
1849 17:41:37.893563 0 9 8 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
1850 17:41:37.896960 0 9 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1851 17:41:37.903175 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 17:41:37.906939 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 17:41:37.910390 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1854 17:41:37.916693 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 17:41:37.920523 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1856 17:41:37.923502 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (1 0)
1857 17:41:37.926973 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
1858 17:41:37.933740 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 17:41:37.936804 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 17:41:37.940720 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 17:41:37.947198 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 17:41:37.950316 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 17:41:37.953808 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 17:41:37.960155 0 11 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (0 0)
1865 17:41:37.963805 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1866 17:41:37.967500 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 17:41:37.973884 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 17:41:37.977540 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 17:41:37.980289 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 17:41:37.987302 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 17:41:37.990677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 17:41:37.994087 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1873 17:41:37.997003 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1874 17:41:38.004199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 17:41:38.007303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 17:41:38.010945 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 17:41:38.017185 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 17:41:38.020555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 17:41:38.024229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 17:41:38.030948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 17:41:38.034629 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 17:41:38.037514 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 17:41:38.044246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 17:41:38.047578 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 17:41:38.051120 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 17:41:38.054136 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 17:41:38.060882 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 17:41:38.064510 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1889 17:41:38.067470 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1890 17:41:38.071275 Total UI for P1: 0, mck2ui 16
1891 17:41:38.074778 best dqsien dly found for B0: ( 0, 14, 4)
1892 17:41:38.081630 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 17:41:38.081705 Total UI for P1: 0, mck2ui 16
1894 17:41:38.088151 best dqsien dly found for B1: ( 0, 14, 6)
1895 17:41:38.091065 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1896 17:41:38.094625 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1897 17:41:38.094707
1898 17:41:38.098047 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 17:41:38.101331 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1900 17:41:38.104813 [Gating] SW calibration Done
1901 17:41:38.104895 ==
1902 17:41:38.107831 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 17:41:38.111461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 17:41:38.111559 ==
1905 17:41:38.114578 RX Vref Scan: 0
1906 17:41:38.114660
1907 17:41:38.114732 RX Vref 0 -> 0, step: 1
1908 17:41:38.114827
1909 17:41:38.118225 RX Delay -130 -> 252, step: 16
1910 17:41:38.121677 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1911 17:41:38.124853 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1912 17:41:38.131775 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1913 17:41:38.135045 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1914 17:41:38.138213 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1915 17:41:38.141574 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1916 17:41:38.144886 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1917 17:41:38.151856 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1918 17:41:38.154694 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1919 17:41:38.158337 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1920 17:41:38.161419 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1921 17:41:38.165007 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1922 17:41:38.171709 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1923 17:41:38.174827 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1924 17:41:38.178585 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1925 17:41:38.182019 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1926 17:41:38.182089 ==
1927 17:41:38.185306 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 17:41:38.191272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 17:41:38.191344 ==
1930 17:41:38.191403 DQS Delay:
1931 17:41:38.194886 DQS0 = 0, DQS1 = 0
1932 17:41:38.194954 DQM Delay:
1933 17:41:38.195012 DQM0 = 82, DQM1 = 78
1934 17:41:38.198311 DQ Delay:
1935 17:41:38.201923 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1936 17:41:38.204920 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1937 17:41:38.208213 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1938 17:41:38.211500 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1939 17:41:38.211569
1940 17:41:38.211627
1941 17:41:38.211690 ==
1942 17:41:38.214868 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 17:41:38.218634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 17:41:38.218709 ==
1945 17:41:38.218793
1946 17:41:38.218851
1947 17:41:38.221917 TX Vref Scan disable
1948 17:41:38.221983 == TX Byte 0 ==
1949 17:41:38.228454 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1950 17:41:38.232116 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1951 17:41:38.232224 == TX Byte 1 ==
1952 17:41:38.238632 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1953 17:41:38.241853 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1954 17:41:38.241953 ==
1955 17:41:38.245428 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 17:41:38.248489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 17:41:38.248565 ==
1958 17:41:38.262208 TX Vref=22, minBit 1, minWin=27, winSum=439
1959 17:41:38.265909 TX Vref=24, minBit 0, minWin=27, winSum=441
1960 17:41:38.269142 TX Vref=26, minBit 3, minWin=27, winSum=444
1961 17:41:38.272546 TX Vref=28, minBit 1, minWin=28, winSum=450
1962 17:41:38.275545 TX Vref=30, minBit 7, minWin=27, winSum=447
1963 17:41:38.279401 TX Vref=32, minBit 0, minWin=28, winSum=450
1964 17:41:38.285928 [TxChooseVref] Worse bit 1, Min win 28, Win sum 450, Final Vref 28
1965 17:41:38.286000
1966 17:41:38.288957 Final TX Range 1 Vref 28
1967 17:41:38.289026
1968 17:41:38.289089 ==
1969 17:41:38.292616 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 17:41:38.296153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 17:41:38.296228 ==
1972 17:41:38.296286
1973 17:41:38.296341
1974 17:41:38.299063 TX Vref Scan disable
1975 17:41:38.302595 == TX Byte 0 ==
1976 17:41:38.306065 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1977 17:41:38.309264 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1978 17:41:38.312893 == TX Byte 1 ==
1979 17:41:38.315957 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1980 17:41:38.319418 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1981 17:41:38.319497
1982 17:41:38.322448 [DATLAT]
1983 17:41:38.322522 Freq=800, CH1 RK1
1984 17:41:38.322580
1985 17:41:38.325968 DATLAT Default: 0xa
1986 17:41:38.326040 0, 0xFFFF, sum = 0
1987 17:41:38.329440 1, 0xFFFF, sum = 0
1988 17:41:38.329508 2, 0xFFFF, sum = 0
1989 17:41:38.332573 3, 0xFFFF, sum = 0
1990 17:41:38.332647 4, 0xFFFF, sum = 0
1991 17:41:38.336164 5, 0xFFFF, sum = 0
1992 17:41:38.336253 6, 0xFFFF, sum = 0
1993 17:41:38.339579 7, 0xFFFF, sum = 0
1994 17:41:38.339649 8, 0xFFFF, sum = 0
1995 17:41:38.342532 9, 0x0, sum = 1
1996 17:41:38.342600 10, 0x0, sum = 2
1997 17:41:38.345873 11, 0x0, sum = 3
1998 17:41:38.345959 12, 0x0, sum = 4
1999 17:41:38.349170 best_step = 10
2000 17:41:38.349243
2001 17:41:38.349311 ==
2002 17:41:38.352553 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 17:41:38.356025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 17:41:38.356100 ==
2005 17:41:38.356162 RX Vref Scan: 0
2006 17:41:38.359537
2007 17:41:38.359615 RX Vref 0 -> 0, step: 1
2008 17:41:38.359676
2009 17:41:38.362850 RX Delay -95 -> 252, step: 8
2010 17:41:38.366042 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2011 17:41:38.372694 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2012 17:41:38.376200 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2013 17:41:38.379353 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2014 17:41:38.383030 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
2015 17:41:38.386551 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2016 17:41:38.393285 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2017 17:41:38.396772 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2018 17:41:38.399754 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2019 17:41:38.403327 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2020 17:41:38.406645 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2021 17:41:38.413311 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2022 17:41:38.416418 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2023 17:41:38.419953 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2024 17:41:38.422947 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2025 17:41:38.426388 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2026 17:41:38.429465 ==
2027 17:41:38.429548 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 17:41:38.436653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 17:41:38.436839 ==
2030 17:41:38.436945 DQS Delay:
2031 17:41:38.439667 DQS0 = 0, DQS1 = 0
2032 17:41:38.439740 DQM Delay:
2033 17:41:38.439808 DQM0 = 79, DQM1 = 75
2034 17:41:38.443155 DQ Delay:
2035 17:41:38.446681 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2036 17:41:38.449928 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
2037 17:41:38.453089 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2038 17:41:38.456524 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2039 17:41:38.456634
2040 17:41:38.456728
2041 17:41:38.463107 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2042 17:41:38.466563 CH1 RK1: MR19=606, MR18=1E2A
2043 17:41:38.473272 CH1_RK1: MR19=0x606, MR18=0x1E2A, DQSOSC=399, MR23=63, INC=92, DEC=61
2044 17:41:38.476841 [RxdqsGatingPostProcess] freq 800
2045 17:41:38.479841 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 17:41:38.483067 Pre-setting of DQS Precalculation
2047 17:41:38.489743 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 17:41:38.496769 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 17:41:38.503520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 17:41:38.503609
2051 17:41:38.503674
2052 17:41:38.506477 [Calibration Summary] 1600 Mbps
2053 17:41:38.506555 CH 0, Rank 0
2054 17:41:38.510060 SW Impedance : PASS
2055 17:41:38.513071 DUTY Scan : NO K
2056 17:41:38.513146 ZQ Calibration : PASS
2057 17:41:38.516656 Jitter Meter : NO K
2058 17:41:38.520251 CBT Training : PASS
2059 17:41:38.520324 Write leveling : PASS
2060 17:41:38.523247 RX DQS gating : PASS
2061 17:41:38.526979 RX DQ/DQS(RDDQC) : PASS
2062 17:41:38.527051 TX DQ/DQS : PASS
2063 17:41:38.529933 RX DATLAT : PASS
2064 17:41:38.530010 RX DQ/DQS(Engine): PASS
2065 17:41:38.533532 TX OE : NO K
2066 17:41:38.533606 All Pass.
2067 17:41:38.533665
2068 17:41:38.536746 CH 0, Rank 1
2069 17:41:38.536819 SW Impedance : PASS
2070 17:41:38.540482 DUTY Scan : NO K
2071 17:41:38.543359 ZQ Calibration : PASS
2072 17:41:38.543434 Jitter Meter : NO K
2073 17:41:38.546461 CBT Training : PASS
2074 17:41:38.550101 Write leveling : PASS
2075 17:41:38.550174 RX DQS gating : PASS
2076 17:41:38.553107 RX DQ/DQS(RDDQC) : PASS
2077 17:41:38.556701 TX DQ/DQS : PASS
2078 17:41:38.556801 RX DATLAT : PASS
2079 17:41:38.559991 RX DQ/DQS(Engine): PASS
2080 17:41:38.560066 TX OE : NO K
2081 17:41:38.563588 All Pass.
2082 17:41:38.563661
2083 17:41:38.563721 CH 1, Rank 0
2084 17:41:38.566639 SW Impedance : PASS
2085 17:41:38.566711 DUTY Scan : NO K
2086 17:41:38.570097 ZQ Calibration : PASS
2087 17:41:38.573644 Jitter Meter : NO K
2088 17:41:38.573718 CBT Training : PASS
2089 17:41:38.576612 Write leveling : PASS
2090 17:41:38.580556 RX DQS gating : PASS
2091 17:41:38.580632 RX DQ/DQS(RDDQC) : PASS
2092 17:41:38.583621 TX DQ/DQS : PASS
2093 17:41:38.587068 RX DATLAT : PASS
2094 17:41:38.587145 RX DQ/DQS(Engine): PASS
2095 17:41:38.590496 TX OE : NO K
2096 17:41:38.590570 All Pass.
2097 17:41:38.590638
2098 17:41:38.593829 CH 1, Rank 1
2099 17:41:38.593929 SW Impedance : PASS
2100 17:41:38.597047 DUTY Scan : NO K
2101 17:41:38.597122 ZQ Calibration : PASS
2102 17:41:38.600454 Jitter Meter : NO K
2103 17:41:38.603824 CBT Training : PASS
2104 17:41:38.603901 Write leveling : PASS
2105 17:41:38.606973 RX DQS gating : PASS
2106 17:41:38.610534 RX DQ/DQS(RDDQC) : PASS
2107 17:41:38.610610 TX DQ/DQS : PASS
2108 17:41:38.613770 RX DATLAT : PASS
2109 17:41:38.617013 RX DQ/DQS(Engine): PASS
2110 17:41:38.617088 TX OE : NO K
2111 17:41:38.620664 All Pass.
2112 17:41:38.620738
2113 17:41:38.620800 DramC Write-DBI off
2114 17:41:38.623861 PER_BANK_REFRESH: Hybrid Mode
2115 17:41:38.623937 TX_TRACKING: ON
2116 17:41:38.627325 [GetDramInforAfterCalByMRR] Vendor 6.
2117 17:41:38.633997 [GetDramInforAfterCalByMRR] Revision 606.
2118 17:41:38.637565 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 17:41:38.637641 MR0 0x3b3b
2120 17:41:38.637710 MR8 0x5151
2121 17:41:38.640835 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 17:41:38.640928
2123 17:41:38.643774 MR0 0x3b3b
2124 17:41:38.643850 MR8 0x5151
2125 17:41:38.647398 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 17:41:38.647475
2127 17:41:38.657219 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 17:41:38.660827 [FAST_K] Save calibration result to emmc
2129 17:41:38.664068 [FAST_K] Save calibration result to emmc
2130 17:41:38.667531 dram_init: config_dvfs: 1
2131 17:41:38.671187 dramc_set_vcore_voltage set vcore to 662500
2132 17:41:38.671263 Read voltage for 1200, 2
2133 17:41:38.674070 Vio18 = 0
2134 17:41:38.674182 Vcore = 662500
2135 17:41:38.674263 Vdram = 0
2136 17:41:38.677415 Vddq = 0
2137 17:41:38.677489 Vmddr = 0
2138 17:41:38.680638 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 17:41:38.688125 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 17:41:38.691181 MEM_TYPE=3, freq_sel=15
2141 17:41:38.694578 sv_algorithm_assistance_LP4_1600
2142 17:41:38.698026 ============ PULL DRAM RESETB DOWN ============
2143 17:41:38.701011 ========== PULL DRAM RESETB DOWN end =========
2144 17:41:38.704324 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 17:41:38.707766 ===================================
2146 17:41:38.711104 LPDDR4 DRAM CONFIGURATION
2147 17:41:38.714952 ===================================
2148 17:41:38.718256 EX_ROW_EN[0] = 0x0
2149 17:41:38.718328 EX_ROW_EN[1] = 0x0
2150 17:41:38.721328 LP4Y_EN = 0x0
2151 17:41:38.721408 WORK_FSP = 0x0
2152 17:41:38.724449 WL = 0x4
2153 17:41:38.724524 RL = 0x4
2154 17:41:38.728045 BL = 0x2
2155 17:41:38.728121 RPST = 0x0
2156 17:41:38.731602 RD_PRE = 0x0
2157 17:41:38.731683 WR_PRE = 0x1
2158 17:41:38.734891 WR_PST = 0x0
2159 17:41:38.734964 DBI_WR = 0x0
2160 17:41:38.737746 DBI_RD = 0x0
2161 17:41:38.737814 OTF = 0x1
2162 17:41:38.741564 ===================================
2163 17:41:38.744960 ===================================
2164 17:41:38.748157 ANA top config
2165 17:41:38.751040 ===================================
2166 17:41:38.754777 DLL_ASYNC_EN = 0
2167 17:41:38.754854 ALL_SLAVE_EN = 0
2168 17:41:38.758269 NEW_RANK_MODE = 1
2169 17:41:38.761282 DLL_IDLE_MODE = 1
2170 17:41:38.764920 LP45_APHY_COMB_EN = 1
2171 17:41:38.764991 TX_ODT_DIS = 1
2172 17:41:38.768109 NEW_8X_MODE = 1
2173 17:41:38.771622 ===================================
2174 17:41:38.775240 ===================================
2175 17:41:38.778117 data_rate = 2400
2176 17:41:38.781658 CKR = 1
2177 17:41:38.785139 DQ_P2S_RATIO = 8
2178 17:41:38.788631 ===================================
2179 17:41:38.788712 CA_P2S_RATIO = 8
2180 17:41:38.792111 DQ_CA_OPEN = 0
2181 17:41:38.795313 DQ_SEMI_OPEN = 0
2182 17:41:38.798725 CA_SEMI_OPEN = 0
2183 17:41:38.801979 CA_FULL_RATE = 0
2184 17:41:38.805360 DQ_CKDIV4_EN = 0
2185 17:41:38.805436 CA_CKDIV4_EN = 0
2186 17:41:38.808694 CA_PREDIV_EN = 0
2187 17:41:38.811801 PH8_DLY = 17
2188 17:41:38.815455 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 17:41:38.818389 DQ_AAMCK_DIV = 4
2190 17:41:38.822010 CA_AAMCK_DIV = 4
2191 17:41:38.822114 CA_ADMCK_DIV = 4
2192 17:41:38.825201 DQ_TRACK_CA_EN = 0
2193 17:41:38.828913 CA_PICK = 1200
2194 17:41:38.832045 CA_MCKIO = 1200
2195 17:41:38.835584 MCKIO_SEMI = 0
2196 17:41:38.838446 PLL_FREQ = 2366
2197 17:41:38.842018 DQ_UI_PI_RATIO = 32
2198 17:41:38.842100 CA_UI_PI_RATIO = 0
2199 17:41:38.845512 ===================================
2200 17:41:38.848527 ===================================
2201 17:41:38.852381 memory_type:LPDDR4
2202 17:41:38.855246 GP_NUM : 10
2203 17:41:38.855320 SRAM_EN : 1
2204 17:41:38.858485 MD32_EN : 0
2205 17:41:38.862021 ===================================
2206 17:41:38.865629 [ANA_INIT] >>>>>>>>>>>>>>
2207 17:41:38.865738 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 17:41:38.872069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 17:41:38.875700 ===================================
2210 17:41:38.875785 data_rate = 2400,PCW = 0X5b00
2211 17:41:38.878745 ===================================
2212 17:41:38.882557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 17:41:38.888729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 17:41:38.895805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 17:41:38.898827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 17:41:38.902463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 17:41:38.905601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 17:41:38.909199 [ANA_INIT] flow start
2219 17:41:38.909281 [ANA_INIT] PLL >>>>>>>>
2220 17:41:38.912282 [ANA_INIT] PLL <<<<<<<<
2221 17:41:38.915794 [ANA_INIT] MIDPI >>>>>>>>
2222 17:41:38.915876 [ANA_INIT] MIDPI <<<<<<<<
2223 17:41:38.918949 [ANA_INIT] DLL >>>>>>>>
2224 17:41:38.922508 [ANA_INIT] DLL <<<<<<<<
2225 17:41:38.922590 [ANA_INIT] flow end
2226 17:41:38.929517 ============ LP4 DIFF to SE enter ============
2227 17:41:38.932637 ============ LP4 DIFF to SE exit ============
2228 17:41:38.932723 [ANA_INIT] <<<<<<<<<<<<<
2229 17:41:38.935528 [Flow] Enable top DCM control >>>>>
2230 17:41:38.938896 [Flow] Enable top DCM control <<<<<
2231 17:41:38.942214 Enable DLL master slave shuffle
2232 17:41:38.949021 ==============================================================
2233 17:41:38.949104 Gating Mode config
2234 17:41:38.955576 ==============================================================
2235 17:41:38.959011 Config description:
2236 17:41:38.969390 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 17:41:38.976116 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 17:41:38.979645 SELPH_MODE 0: By rank 1: By Phase
2239 17:41:38.985815 ==============================================================
2240 17:41:38.989320 GAT_TRACK_EN = 1
2241 17:41:38.989402 RX_GATING_MODE = 2
2242 17:41:38.992543 RX_GATING_TRACK_MODE = 2
2243 17:41:38.995888 SELPH_MODE = 1
2244 17:41:38.999423 PICG_EARLY_EN = 1
2245 17:41:39.002310 VALID_LAT_VALUE = 1
2246 17:41:39.009074 ==============================================================
2247 17:41:39.012799 Enter into Gating configuration >>>>
2248 17:41:39.015905 Exit from Gating configuration <<<<
2249 17:41:39.019448 Enter into DVFS_PRE_config >>>>>
2250 17:41:39.029536 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 17:41:39.033048 Exit from DVFS_PRE_config <<<<<
2252 17:41:39.035947 Enter into PICG configuration >>>>
2253 17:41:39.039709 Exit from PICG configuration <<<<
2254 17:41:39.042631 [RX_INPUT] configuration >>>>>
2255 17:41:39.042714 [RX_INPUT] configuration <<<<<
2256 17:41:39.049656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 17:41:39.056132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 17:41:39.059640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 17:41:39.066293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 17:41:39.073429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 17:41:39.079840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 17:41:39.083521 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 17:41:39.086682 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 17:41:39.093186 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 17:41:39.096787 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 17:41:39.100222 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 17:41:39.103516 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 17:41:39.106381 ===================================
2269 17:41:39.110119 LPDDR4 DRAM CONFIGURATION
2270 17:41:39.113151 ===================================
2271 17:41:39.116787 EX_ROW_EN[0] = 0x0
2272 17:41:39.116869 EX_ROW_EN[1] = 0x0
2273 17:41:39.120549 LP4Y_EN = 0x0
2274 17:41:39.120631 WORK_FSP = 0x0
2275 17:41:39.123405 WL = 0x4
2276 17:41:39.123487 RL = 0x4
2277 17:41:39.126862 BL = 0x2
2278 17:41:39.126944 RPST = 0x0
2279 17:41:39.130159 RD_PRE = 0x0
2280 17:41:39.130240 WR_PRE = 0x1
2281 17:41:39.133568 WR_PST = 0x0
2282 17:41:39.133650 DBI_WR = 0x0
2283 17:41:39.136604 DBI_RD = 0x0
2284 17:41:39.136686 OTF = 0x1
2285 17:41:39.140258 ===================================
2286 17:41:39.146917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 17:41:39.150287 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 17:41:39.153219 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 17:41:39.156567 ===================================
2290 17:41:39.160349 LPDDR4 DRAM CONFIGURATION
2291 17:41:39.163834 ===================================
2292 17:41:39.163916 EX_ROW_EN[0] = 0x10
2293 17:41:39.166828 EX_ROW_EN[1] = 0x0
2294 17:41:39.170329 LP4Y_EN = 0x0
2295 17:41:39.170411 WORK_FSP = 0x0
2296 17:41:39.173873 WL = 0x4
2297 17:41:39.173955 RL = 0x4
2298 17:41:39.177072 BL = 0x2
2299 17:41:39.177154 RPST = 0x0
2300 17:41:39.180065 RD_PRE = 0x0
2301 17:41:39.180153 WR_PRE = 0x1
2302 17:41:39.183302 WR_PST = 0x0
2303 17:41:39.183389 DBI_WR = 0x0
2304 17:41:39.186732 DBI_RD = 0x0
2305 17:41:39.186830 OTF = 0x1
2306 17:41:39.190474 ===================================
2307 17:41:39.196959 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 17:41:39.197071 ==
2309 17:41:39.200409 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 17:41:39.203491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 17:41:39.203615 ==
2312 17:41:39.207051 [Duty_Offset_Calibration]
2313 17:41:39.210677 B0:2 B1:-1 CA:1
2314 17:41:39.210857
2315 17:41:39.213736 [DutyScan_Calibration_Flow] k_type=0
2316 17:41:39.221188
2317 17:41:39.221407 ==CLK 0==
2318 17:41:39.224008 Final CLK duty delay cell = -4
2319 17:41:39.227992 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2320 17:41:39.231387 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2321 17:41:39.234455 [-4] AVG Duty = 4953%(X100)
2322 17:41:39.234871
2323 17:41:39.238198 CH0 CLK Duty spec in!! Max-Min= 156%
2324 17:41:39.241161 [DutyScan_Calibration_Flow] ====Done====
2325 17:41:39.241581
2326 17:41:39.244808 [DutyScan_Calibration_Flow] k_type=1
2327 17:41:39.259879
2328 17:41:39.260295 ==DQS 0 ==
2329 17:41:39.262785 Final DQS duty delay cell = -4
2330 17:41:39.266297 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2331 17:41:39.269533 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2332 17:41:39.272986 [-4] AVG Duty = 4938%(X100)
2333 17:41:39.273406
2334 17:41:39.273735 ==DQS 1 ==
2335 17:41:39.276062 Final DQS duty delay cell = -4
2336 17:41:39.279313 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2337 17:41:39.282714 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2338 17:41:39.286086 [-4] AVG Duty = 5062%(X100)
2339 17:41:39.286555
2340 17:41:39.289217 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2341 17:41:39.289642
2342 17:41:39.292957 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2343 17:41:39.296288 [DutyScan_Calibration_Flow] ====Done====
2344 17:41:39.296722
2345 17:41:39.299546 [DutyScan_Calibration_Flow] k_type=3
2346 17:41:39.316862
2347 17:41:39.317281 ==DQM 0 ==
2348 17:41:39.319747 Final DQM duty delay cell = 0
2349 17:41:39.323448 [0] MAX Duty = 5031%(X100), DQS PI = 54
2350 17:41:39.326528 [0] MIN Duty = 4907%(X100), DQS PI = 2
2351 17:41:39.327019 [0] AVG Duty = 4969%(X100)
2352 17:41:39.330013
2353 17:41:39.330433 ==DQM 1 ==
2354 17:41:39.333487 Final DQM duty delay cell = 0
2355 17:41:39.336474 [0] MAX Duty = 5156%(X100), DQS PI = 62
2356 17:41:39.340208 [0] MIN Duty = 4969%(X100), DQS PI = 58
2357 17:41:39.340629 [0] AVG Duty = 5062%(X100)
2358 17:41:39.343365
2359 17:41:39.346963 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2360 17:41:39.347386
2361 17:41:39.349783 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2362 17:41:39.353559 [DutyScan_Calibration_Flow] ====Done====
2363 17:41:39.353973
2364 17:41:39.356880 [DutyScan_Calibration_Flow] k_type=2
2365 17:41:39.372656
2366 17:41:39.373072 ==DQ 0 ==
2367 17:41:39.375688 Final DQ duty delay cell = -4
2368 17:41:39.379194 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2369 17:41:39.382334 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2370 17:41:39.386106 [-4] AVG Duty = 4969%(X100)
2371 17:41:39.386536
2372 17:41:39.387005 ==DQ 1 ==
2373 17:41:39.389085 Final DQ duty delay cell = 0
2374 17:41:39.392155 [0] MAX Duty = 5031%(X100), DQS PI = 26
2375 17:41:39.396045 [0] MIN Duty = 4907%(X100), DQS PI = 46
2376 17:41:39.396463 [0] AVG Duty = 4969%(X100)
2377 17:41:39.396791
2378 17:41:39.399006 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2379 17:41:39.402362
2380 17:41:39.405699 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2381 17:41:39.409237 [DutyScan_Calibration_Flow] ====Done====
2382 17:41:39.409656 ==
2383 17:41:39.412947 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 17:41:39.416309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 17:41:39.416904 ==
2386 17:41:39.419537 [Duty_Offset_Calibration]
2387 17:41:39.419954 B0:1 B1:1 CA:2
2388 17:41:39.420287
2389 17:41:39.422771 [DutyScan_Calibration_Flow] k_type=0
2390 17:41:39.432767
2391 17:41:39.433189 ==CLK 0==
2392 17:41:39.436115 Final CLK duty delay cell = 0
2393 17:41:39.439032 [0] MAX Duty = 5125%(X100), DQS PI = 24
2394 17:41:39.442649 [0] MIN Duty = 4969%(X100), DQS PI = 38
2395 17:41:39.443109 [0] AVG Duty = 5047%(X100)
2396 17:41:39.446256
2397 17:41:39.449308 CH1 CLK Duty spec in!! Max-Min= 156%
2398 17:41:39.452978 [DutyScan_Calibration_Flow] ====Done====
2399 17:41:39.453436
2400 17:41:39.455914 [DutyScan_Calibration_Flow] k_type=1
2401 17:41:39.471903
2402 17:41:39.472326 ==DQS 0 ==
2403 17:41:39.475467 Final DQS duty delay cell = 0
2404 17:41:39.479013 [0] MAX Duty = 5031%(X100), DQS PI = 18
2405 17:41:39.481765 [0] MIN Duty = 4875%(X100), DQS PI = 28
2406 17:41:39.485670 [0] AVG Duty = 4953%(X100)
2407 17:41:39.486092
2408 17:41:39.486420 ==DQS 1 ==
2409 17:41:39.488767 Final DQS duty delay cell = 0
2410 17:41:39.492642 [0] MAX Duty = 5062%(X100), DQS PI = 36
2411 17:41:39.495392 [0] MIN Duty = 4907%(X100), DQS PI = 16
2412 17:41:39.495818 [0] AVG Duty = 4984%(X100)
2413 17:41:39.498560
2414 17:41:39.502233 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2415 17:41:39.502657
2416 17:41:39.505748 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2417 17:41:39.508633 [DutyScan_Calibration_Flow] ====Done====
2418 17:41:39.509055
2419 17:41:39.512181 [DutyScan_Calibration_Flow] k_type=3
2420 17:41:39.528570
2421 17:41:39.528992 ==DQM 0 ==
2422 17:41:39.531848 Final DQM duty delay cell = 0
2423 17:41:39.535211 [0] MAX Duty = 5093%(X100), DQS PI = 16
2424 17:41:39.538444 [0] MIN Duty = 4907%(X100), DQS PI = 48
2425 17:41:39.538917 [0] AVG Duty = 5000%(X100)
2426 17:41:39.542032
2427 17:41:39.542455 ==DQM 1 ==
2428 17:41:39.545459 Final DQM duty delay cell = 0
2429 17:41:39.549214 [0] MAX Duty = 5156%(X100), DQS PI = 62
2430 17:41:39.552111 [0] MIN Duty = 4938%(X100), DQS PI = 24
2431 17:41:39.552584 [0] AVG Duty = 5047%(X100)
2432 17:41:39.553140
2433 17:41:39.555134 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2434 17:41:39.558968
2435 17:41:39.562500 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2436 17:41:39.565454 [DutyScan_Calibration_Flow] ====Done====
2437 17:41:39.565898
2438 17:41:39.569269 [DutyScan_Calibration_Flow] k_type=2
2439 17:41:39.585074
2440 17:41:39.585498 ==DQ 0 ==
2441 17:41:39.588577 Final DQ duty delay cell = 0
2442 17:41:39.591714 [0] MAX Duty = 5156%(X100), DQS PI = 18
2443 17:41:39.595232 [0] MIN Duty = 4938%(X100), DQS PI = 50
2444 17:41:39.595664 [0] AVG Duty = 5047%(X100)
2445 17:41:39.595997
2446 17:41:39.598329 ==DQ 1 ==
2447 17:41:39.601958 Final DQ duty delay cell = 0
2448 17:41:39.604921 [0] MAX Duty = 5093%(X100), DQS PI = 12
2449 17:41:39.608367 [0] MIN Duty = 5031%(X100), DQS PI = 2
2450 17:41:39.608788 [0] AVG Duty = 5062%(X100)
2451 17:41:39.609125
2452 17:41:39.611882 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2453 17:41:39.612304
2454 17:41:39.615116 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2455 17:41:39.621487 [DutyScan_Calibration_Flow] ====Done====
2456 17:41:39.625237 nWR fixed to 30
2457 17:41:39.625663 [ModeRegInit_LP4] CH0 RK0
2458 17:41:39.628177 [ModeRegInit_LP4] CH0 RK1
2459 17:41:39.631942 [ModeRegInit_LP4] CH1 RK0
2460 17:41:39.632365 [ModeRegInit_LP4] CH1 RK1
2461 17:41:39.635571 match AC timing 7
2462 17:41:39.638378 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 17:41:39.641869 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 17:41:39.648450 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 17:41:39.652081 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 17:41:39.658585 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 17:41:39.659043 ==
2468 17:41:39.661537 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 17:41:39.664994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 17:41:39.665076 ==
2471 17:41:39.668424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 17:41:39.675013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2473 17:41:39.684600 [CA 0] Center 40 (10~71) winsize 62
2474 17:41:39.688373 [CA 1] Center 39 (9~70) winsize 62
2475 17:41:39.691517 [CA 2] Center 36 (6~67) winsize 62
2476 17:41:39.694804 [CA 3] Center 36 (5~67) winsize 63
2477 17:41:39.697729 [CA 4] Center 35 (5~65) winsize 61
2478 17:41:39.701541 [CA 5] Center 34 (4~65) winsize 62
2479 17:41:39.701662
2480 17:41:39.704660 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2481 17:41:39.704734
2482 17:41:39.708307 [CATrainingPosCal] consider 1 rank data
2483 17:41:39.711254 u2DelayCellTimex100 = 270/100 ps
2484 17:41:39.714905 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2485 17:41:39.718420 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2486 17:41:39.724928 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2487 17:41:39.728133 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2488 17:41:39.731607 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2489 17:41:39.734839 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2490 17:41:39.734913
2491 17:41:39.738176 CA PerBit enable=1, Macro0, CA PI delay=34
2492 17:41:39.738250
2493 17:41:39.741398 [CBTSetCACLKResult] CA Dly = 34
2494 17:41:39.741473 CS Dly: 7 (0~38)
2495 17:41:39.741534 ==
2496 17:41:39.745144 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 17:41:39.751579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 17:41:39.751677 ==
2499 17:41:39.755042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 17:41:39.761639 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2501 17:41:39.770380 [CA 0] Center 39 (9~70) winsize 62
2502 17:41:39.773667 [CA 1] Center 40 (10~70) winsize 61
2503 17:41:39.777381 [CA 2] Center 36 (6~67) winsize 62
2504 17:41:39.780334 [CA 3] Center 36 (5~67) winsize 63
2505 17:41:39.783997 [CA 4] Center 34 (4~65) winsize 62
2506 17:41:39.787089 [CA 5] Center 34 (4~64) winsize 61
2507 17:41:39.787171
2508 17:41:39.790660 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 17:41:39.790812
2510 17:41:39.794202 [CATrainingPosCal] consider 2 rank data
2511 17:41:39.797157 u2DelayCellTimex100 = 270/100 ps
2512 17:41:39.800526 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2513 17:41:39.807173 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2514 17:41:39.810375 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2515 17:41:39.814130 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2516 17:41:39.817499 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2517 17:41:39.820472 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2518 17:41:39.820555
2519 17:41:39.824075 CA PerBit enable=1, Macro0, CA PI delay=34
2520 17:41:39.824157
2521 17:41:39.827147 [CBTSetCACLKResult] CA Dly = 34
2522 17:41:39.827229 CS Dly: 8 (0~41)
2523 17:41:39.827294
2524 17:41:39.830934 ----->DramcWriteLeveling(PI) begin...
2525 17:41:39.834564 ==
2526 17:41:39.834647 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 17:41:39.841183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 17:41:39.841266 ==
2529 17:41:39.844027 Write leveling (Byte 0): 30 => 30
2530 17:41:39.847448 Write leveling (Byte 1): 29 => 29
2531 17:41:39.847530 DramcWriteLeveling(PI) end<-----
2532 17:41:39.850847
2533 17:41:39.850929 ==
2534 17:41:39.854419 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 17:41:39.857412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 17:41:39.857495 ==
2537 17:41:39.860993 [Gating] SW mode calibration
2538 17:41:39.867528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 17:41:39.871079 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 17:41:39.877784 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 17:41:39.881147 0 15 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2542 17:41:39.884245 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2543 17:41:39.891423 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 17:41:39.894544 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 17:41:39.897954 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 17:41:39.904414 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 17:41:39.908048 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 17:41:39.911152 1 0 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2549 17:41:39.914587 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
2550 17:41:39.921242 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 17:41:39.924609 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 17:41:39.928193 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 17:41:39.934952 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 17:41:39.938044 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 17:41:39.941563 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 17:41:39.948257 1 1 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2557 17:41:39.951327 1 1 4 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2558 17:41:39.954851 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 17:41:39.961072 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 17:41:39.964746 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 17:41:39.968080 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 17:41:39.974666 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 17:41:39.978266 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 17:41:39.981201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 17:41:39.984772 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 17:41:39.991503 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 17:41:39.994732 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 17:41:39.998312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 17:41:40.005096 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 17:41:40.008430 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 17:41:40.012155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 17:41:40.018861 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 17:41:40.021586 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 17:41:40.025111 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 17:41:40.032047 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 17:41:40.035328 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 17:41:40.038228 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 17:41:40.044893 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 17:41:40.048294 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 17:41:40.052032 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2581 17:41:40.055009 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 17:41:40.058266 Total UI for P1: 0, mck2ui 16
2583 17:41:40.062018 best dqsien dly found for B0: ( 1, 4, 0)
2584 17:41:40.068356 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 17:41:40.071798 Total UI for P1: 0, mck2ui 16
2586 17:41:40.075159 best dqsien dly found for B1: ( 1, 4, 4)
2587 17:41:40.078163 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2588 17:41:40.081814 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2589 17:41:40.081897
2590 17:41:40.084717 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2591 17:41:40.088310 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2592 17:41:40.091824 [Gating] SW calibration Done
2593 17:41:40.091907 ==
2594 17:41:40.095322 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 17:41:40.098362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 17:41:40.098445 ==
2597 17:41:40.102028 RX Vref Scan: 0
2598 17:41:40.102111
2599 17:41:40.102206 RX Vref 0 -> 0, step: 1
2600 17:41:40.102267
2601 17:41:40.105195 RX Delay -40 -> 252, step: 8
2602 17:41:40.108382 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2603 17:41:40.115674 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2604 17:41:40.119101 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2605 17:41:40.121827 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2606 17:41:40.125604 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2607 17:41:40.128932 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2608 17:41:40.132001 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2609 17:41:40.138781 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2610 17:41:40.142259 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2611 17:41:40.145407 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2612 17:41:40.148999 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2613 17:41:40.152072 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2614 17:41:40.158747 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2615 17:41:40.162127 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2616 17:41:40.165769 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2617 17:41:40.168699 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2618 17:41:40.168782 ==
2619 17:41:40.172206 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 17:41:40.175515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 17:41:40.179065 ==
2622 17:41:40.179149 DQS Delay:
2623 17:41:40.179213 DQS0 = 0, DQS1 = 0
2624 17:41:40.182584 DQM Delay:
2625 17:41:40.182672 DQM0 = 115, DQM1 = 107
2626 17:41:40.186110 DQ Delay:
2627 17:41:40.188911 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2628 17:41:40.192399 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2629 17:41:40.195487 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2630 17:41:40.198854 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2631 17:41:40.198928
2632 17:41:40.198991
2633 17:41:40.199071 ==
2634 17:41:40.202253 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 17:41:40.206159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 17:41:40.206266 ==
2637 17:41:40.206368
2638 17:41:40.206471
2639 17:41:40.209547 TX Vref Scan disable
2640 17:41:40.212324 == TX Byte 0 ==
2641 17:41:40.215592 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2642 17:41:40.219140 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2643 17:41:40.222615 == TX Byte 1 ==
2644 17:41:40.225900 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2645 17:41:40.229006 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2646 17:41:40.229113 ==
2647 17:41:40.232536 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 17:41:40.236107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 17:41:40.238987 ==
2650 17:41:40.249000 TX Vref=22, minBit 7, minWin=24, winSum=415
2651 17:41:40.252826 TX Vref=24, minBit 1, minWin=24, winSum=417
2652 17:41:40.256324 TX Vref=26, minBit 0, minWin=26, winSum=425
2653 17:41:40.259276 TX Vref=28, minBit 0, minWin=26, winSum=431
2654 17:41:40.262764 TX Vref=30, minBit 0, minWin=26, winSum=432
2655 17:41:40.265719 TX Vref=32, minBit 0, minWin=26, winSum=428
2656 17:41:40.273064 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2657 17:41:40.273162
2658 17:41:40.275918 Final TX Range 1 Vref 30
2659 17:41:40.276002
2660 17:41:40.276066 ==
2661 17:41:40.279422 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 17:41:40.282612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 17:41:40.282715 ==
2664 17:41:40.282834
2665 17:41:40.282899
2666 17:41:40.286108 TX Vref Scan disable
2667 17:41:40.289250 == TX Byte 0 ==
2668 17:41:40.292799 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2669 17:41:40.296177 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2670 17:41:40.299922 == TX Byte 1 ==
2671 17:41:40.302811 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2672 17:41:40.306347 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2673 17:41:40.306422
2674 17:41:40.309735 [DATLAT]
2675 17:41:40.309832 Freq=1200, CH0 RK0
2676 17:41:40.309922
2677 17:41:40.313147 DATLAT Default: 0xd
2678 17:41:40.313242 0, 0xFFFF, sum = 0
2679 17:41:40.316213 1, 0xFFFF, sum = 0
2680 17:41:40.316298 2, 0xFFFF, sum = 0
2681 17:41:40.319500 3, 0xFFFF, sum = 0
2682 17:41:40.319584 4, 0xFFFF, sum = 0
2683 17:41:40.322941 5, 0xFFFF, sum = 0
2684 17:41:40.323025 6, 0xFFFF, sum = 0
2685 17:41:40.326318 7, 0xFFFF, sum = 0
2686 17:41:40.326430 8, 0xFFFF, sum = 0
2687 17:41:40.329752 9, 0xFFFF, sum = 0
2688 17:41:40.329837 10, 0xFFFF, sum = 0
2689 17:41:40.332958 11, 0xFFFF, sum = 0
2690 17:41:40.333034 12, 0x0, sum = 1
2691 17:41:40.336304 13, 0x0, sum = 2
2692 17:41:40.336389 14, 0x0, sum = 3
2693 17:41:40.339611 15, 0x0, sum = 4
2694 17:41:40.339686 best_step = 13
2695 17:41:40.339748
2696 17:41:40.339817 ==
2697 17:41:40.342993 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 17:41:40.346276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 17:41:40.349858 ==
2700 17:41:40.349941 RX Vref Scan: 1
2701 17:41:40.350005
2702 17:41:40.353262 Set Vref Range= 32 -> 127
2703 17:41:40.353345
2704 17:41:40.356498 RX Vref 32 -> 127, step: 1
2705 17:41:40.356581
2706 17:41:40.356647 RX Delay -21 -> 252, step: 4
2707 17:41:40.356707
2708 17:41:40.359733 Set Vref, RX VrefLevel [Byte0]: 32
2709 17:41:40.363399 [Byte1]: 32
2710 17:41:40.367257
2711 17:41:40.367340 Set Vref, RX VrefLevel [Byte0]: 33
2712 17:41:40.370468 [Byte1]: 33
2713 17:41:40.375012
2714 17:41:40.375093 Set Vref, RX VrefLevel [Byte0]: 34
2715 17:41:40.378672 [Byte1]: 34
2716 17:41:40.382886
2717 17:41:40.382968 Set Vref, RX VrefLevel [Byte0]: 35
2718 17:41:40.386199 [Byte1]: 35
2719 17:41:40.390929
2720 17:41:40.391028 Set Vref, RX VrefLevel [Byte0]: 36
2721 17:41:40.394199 [Byte1]: 36
2722 17:41:40.398992
2723 17:41:40.399075 Set Vref, RX VrefLevel [Byte0]: 37
2724 17:41:40.402208 [Byte1]: 37
2725 17:41:40.407018
2726 17:41:40.407101 Set Vref, RX VrefLevel [Byte0]: 38
2727 17:41:40.410136 [Byte1]: 38
2728 17:41:40.414673
2729 17:41:40.414797 Set Vref, RX VrefLevel [Byte0]: 39
2730 17:41:40.418158 [Byte1]: 39
2731 17:41:40.422894
2732 17:41:40.422977 Set Vref, RX VrefLevel [Byte0]: 40
2733 17:41:40.426488 [Byte1]: 40
2734 17:41:40.430575
2735 17:41:40.430657 Set Vref, RX VrefLevel [Byte0]: 41
2736 17:41:40.433889 [Byte1]: 41
2737 17:41:40.438700
2738 17:41:40.438812 Set Vref, RX VrefLevel [Byte0]: 42
2739 17:41:40.441790 [Byte1]: 42
2740 17:41:40.446805
2741 17:41:40.446889 Set Vref, RX VrefLevel [Byte0]: 43
2742 17:41:40.449785 [Byte1]: 43
2743 17:41:40.454311
2744 17:41:40.454397 Set Vref, RX VrefLevel [Byte0]: 44
2745 17:41:40.457898 [Byte1]: 44
2746 17:41:40.462618
2747 17:41:40.462701 Set Vref, RX VrefLevel [Byte0]: 45
2748 17:41:40.465852 [Byte1]: 45
2749 17:41:40.470546
2750 17:41:40.470628 Set Vref, RX VrefLevel [Byte0]: 46
2751 17:41:40.474084 [Byte1]: 46
2752 17:41:40.478076
2753 17:41:40.478163 Set Vref, RX VrefLevel [Byte0]: 47
2754 17:41:40.481646 [Byte1]: 47
2755 17:41:40.486342
2756 17:41:40.486424 Set Vref, RX VrefLevel [Byte0]: 48
2757 17:41:40.489792 [Byte1]: 48
2758 17:41:40.493872
2759 17:41:40.493951 Set Vref, RX VrefLevel [Byte0]: 49
2760 17:41:40.497452 [Byte1]: 49
2761 17:41:40.501944
2762 17:41:40.502026 Set Vref, RX VrefLevel [Byte0]: 50
2763 17:41:40.505349 [Byte1]: 50
2764 17:41:40.510075
2765 17:41:40.510156 Set Vref, RX VrefLevel [Byte0]: 51
2766 17:41:40.513472 [Byte1]: 51
2767 17:41:40.518380
2768 17:41:40.518461 Set Vref, RX VrefLevel [Byte0]: 52
2769 17:41:40.521200 [Byte1]: 52
2770 17:41:40.525871
2771 17:41:40.525985 Set Vref, RX VrefLevel [Byte0]: 53
2772 17:41:40.528905 [Byte1]: 53
2773 17:41:40.533560
2774 17:41:40.533647 Set Vref, RX VrefLevel [Byte0]: 54
2775 17:41:40.537193 [Byte1]: 54
2776 17:41:40.541493
2777 17:41:40.541596 Set Vref, RX VrefLevel [Byte0]: 55
2778 17:41:40.545081 [Byte1]: 55
2779 17:41:40.549641
2780 17:41:40.549749 Set Vref, RX VrefLevel [Byte0]: 56
2781 17:41:40.553322 [Byte1]: 56
2782 17:41:40.557457
2783 17:41:40.557560 Set Vref, RX VrefLevel [Byte0]: 57
2784 17:41:40.560793 [Byte1]: 57
2785 17:41:40.565393
2786 17:41:40.565468 Set Vref, RX VrefLevel [Byte0]: 58
2787 17:41:40.568730 [Byte1]: 58
2788 17:41:40.573343
2789 17:41:40.573418 Set Vref, RX VrefLevel [Byte0]: 59
2790 17:41:40.576977 [Byte1]: 59
2791 17:41:40.581181
2792 17:41:40.581281 Set Vref, RX VrefLevel [Byte0]: 60
2793 17:41:40.584789 [Byte1]: 60
2794 17:41:40.589137
2795 17:41:40.589294 Set Vref, RX VrefLevel [Byte0]: 61
2796 17:41:40.592974 [Byte1]: 61
2797 17:41:40.596998
2798 17:41:40.597151 Set Vref, RX VrefLevel [Byte0]: 62
2799 17:41:40.600600 [Byte1]: 62
2800 17:41:40.605212
2801 17:41:40.608411 Set Vref, RX VrefLevel [Byte0]: 63
2802 17:41:40.608527 [Byte1]: 63
2803 17:41:40.613020
2804 17:41:40.613123 Set Vref, RX VrefLevel [Byte0]: 64
2805 17:41:40.616130 [Byte1]: 64
2806 17:41:40.621462
2807 17:41:40.621579 Set Vref, RX VrefLevel [Byte0]: 65
2808 17:41:40.624229 [Byte1]: 65
2809 17:41:40.628981
2810 17:41:40.629062 Set Vref, RX VrefLevel [Byte0]: 66
2811 17:41:40.632615 [Byte1]: 66
2812 17:41:40.636603
2813 17:41:40.636685 Set Vref, RX VrefLevel [Byte0]: 67
2814 17:41:40.640133 [Byte1]: 67
2815 17:41:40.644997
2816 17:41:40.645079 Set Vref, RX VrefLevel [Byte0]: 68
2817 17:41:40.647919 [Byte1]: 68
2818 17:41:40.652640
2819 17:41:40.652721 Final RX Vref Byte 0 = 55 to rank0
2820 17:41:40.655955 Final RX Vref Byte 1 = 52 to rank0
2821 17:41:40.659569 Final RX Vref Byte 0 = 55 to rank1
2822 17:41:40.662683 Final RX Vref Byte 1 = 52 to rank1==
2823 17:41:40.666213 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 17:41:40.669696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 17:41:40.672775 ==
2826 17:41:40.672935 DQS Delay:
2827 17:41:40.673000 DQS0 = 0, DQS1 = 0
2828 17:41:40.675995 DQM Delay:
2829 17:41:40.676077 DQM0 = 115, DQM1 = 105
2830 17:41:40.679881 DQ Delay:
2831 17:41:40.682650 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2832 17:41:40.686354 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2833 17:41:40.689777 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2834 17:41:40.692917 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2835 17:41:40.693028
2836 17:41:40.693111
2837 17:41:40.699555 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9e9, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2838 17:41:40.703083 CH0 RK0: MR19=303, MR18=F9E9
2839 17:41:40.709580 CH0_RK0: MR19=0x303, MR18=0xF9E9, DQSOSC=412, MR23=63, INC=38, DEC=25
2840 17:41:40.709663
2841 17:41:40.713109 ----->DramcWriteLeveling(PI) begin...
2842 17:41:40.713193 ==
2843 17:41:40.716526 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 17:41:40.719507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 17:41:40.719589 ==
2846 17:41:40.722848 Write leveling (Byte 0): 32 => 32
2847 17:41:40.726035 Write leveling (Byte 1): 28 => 28
2848 17:41:40.729715 DramcWriteLeveling(PI) end<-----
2849 17:41:40.729797
2850 17:41:40.729861 ==
2851 17:41:40.733074 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 17:41:40.736115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 17:41:40.739651 ==
2854 17:41:40.739748 [Gating] SW mode calibration
2855 17:41:40.746244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 17:41:40.753132 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 17:41:40.756770 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2858 17:41:40.763112 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2859 17:41:40.766907 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 17:41:40.770563 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 17:41:40.773242 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 17:41:40.780037 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 17:41:40.783492 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2864 17:41:40.786540 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2865 17:41:40.793326 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2866 17:41:40.797005 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2867 17:41:40.799884 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 17:41:40.807162 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 17:41:40.810006 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 17:41:40.813578 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 17:41:40.820095 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2872 17:41:40.823443 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2873 17:41:40.826502 1 1 0 | B1->B0 | 3333 3f3f | 0 1 | (0 0) (0 0)
2874 17:41:40.833615 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 17:41:40.837204 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 17:41:40.839918 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 17:41:40.846660 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 17:41:40.850111 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 17:41:40.853566 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 17:41:40.856516 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2881 17:41:40.863557 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2882 17:41:40.867216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2883 17:41:40.870008 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 17:41:40.876712 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 17:41:40.879946 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 17:41:40.883471 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 17:41:40.890264 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 17:41:40.893753 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 17:41:40.897076 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 17:41:40.903797 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 17:41:40.907347 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 17:41:40.910345 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 17:41:40.913801 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 17:41:40.920796 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 17:41:40.923640 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 17:41:40.927299 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 17:41:40.934303 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2898 17:41:40.937371 Total UI for P1: 0, mck2ui 16
2899 17:41:40.940854 best dqsien dly found for B0: ( 1, 3, 26)
2900 17:41:40.943864 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2901 17:41:40.947409 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 17:41:40.950502 Total UI for P1: 0, mck2ui 16
2903 17:41:40.953933 best dqsien dly found for B1: ( 1, 4, 2)
2904 17:41:40.957670 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2905 17:41:40.960616 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2906 17:41:40.960714
2907 17:41:40.964188 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2908 17:41:40.970938 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2909 17:41:40.971013 [Gating] SW calibration Done
2910 17:41:40.971076 ==
2911 17:41:40.974419 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 17:41:40.981075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 17:41:40.981157 ==
2914 17:41:40.981219 RX Vref Scan: 0
2915 17:41:40.981277
2916 17:41:40.984326 RX Vref 0 -> 0, step: 1
2917 17:41:40.984398
2918 17:41:40.987787 RX Delay -40 -> 252, step: 8
2919 17:41:40.991024 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2920 17:41:40.994845 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2921 17:41:40.997786 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2922 17:41:41.001315 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2923 17:41:41.007578 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2924 17:41:41.011156 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2925 17:41:41.014707 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2926 17:41:41.018093 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 17:41:41.021196 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2928 17:41:41.028195 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2929 17:41:41.031093 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2930 17:41:41.034685 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2931 17:41:41.037894 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2932 17:41:41.041125 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2933 17:41:41.047870 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2934 17:41:41.051414 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2935 17:41:41.051494 ==
2936 17:41:41.055079 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 17:41:41.057916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 17:41:41.057998 ==
2939 17:41:41.058061 DQS Delay:
2940 17:41:41.061516 DQS0 = 0, DQS1 = 0
2941 17:41:41.061597 DQM Delay:
2942 17:41:41.065031 DQM0 = 116, DQM1 = 106
2943 17:41:41.065111 DQ Delay:
2944 17:41:41.068009 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2945 17:41:41.071719 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2946 17:41:41.074808 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2947 17:41:41.078323 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2948 17:41:41.078404
2949 17:41:41.078467
2950 17:41:41.082030 ==
2951 17:41:41.082111 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 17:41:41.088450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 17:41:41.088531 ==
2954 17:41:41.088594
2955 17:41:41.088652
2956 17:41:41.091562 TX Vref Scan disable
2957 17:41:41.091644 == TX Byte 0 ==
2958 17:41:41.095102 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2959 17:41:41.101935 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2960 17:41:41.102016 == TX Byte 1 ==
2961 17:41:41.105279 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2962 17:41:41.111595 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2963 17:41:41.111675 ==
2964 17:41:41.115047 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 17:41:41.118403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 17:41:41.118484 ==
2967 17:41:41.130827 TX Vref=22, minBit 4, minWin=25, winSum=429
2968 17:41:41.133639 TX Vref=24, minBit 2, minWin=26, winSum=431
2969 17:41:41.137189 TX Vref=26, minBit 0, minWin=26, winSum=430
2970 17:41:41.140521 TX Vref=28, minBit 0, minWin=27, winSum=435
2971 17:41:41.143728 TX Vref=30, minBit 3, minWin=26, winSum=436
2972 17:41:41.147088 TX Vref=32, minBit 4, minWin=26, winSum=434
2973 17:41:41.153774 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 28
2974 17:41:41.153856
2975 17:41:41.157295 Final TX Range 1 Vref 28
2976 17:41:41.157375
2977 17:41:41.157438 ==
2978 17:41:41.161017 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 17:41:41.163845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 17:41:41.163926 ==
2981 17:41:41.163998
2982 17:41:41.164059
2983 17:41:41.167498 TX Vref Scan disable
2984 17:41:41.170876 == TX Byte 0 ==
2985 17:41:41.173983 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 17:41:41.177427 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 17:41:41.180880 == TX Byte 1 ==
2988 17:41:41.184481 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2989 17:41:41.187483 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2990 17:41:41.187557
2991 17:41:41.190707 [DATLAT]
2992 17:41:41.190816 Freq=1200, CH0 RK1
2993 17:41:41.190876
2994 17:41:41.194320 DATLAT Default: 0xd
2995 17:41:41.194402 0, 0xFFFF, sum = 0
2996 17:41:41.197947 1, 0xFFFF, sum = 0
2997 17:41:41.198029 2, 0xFFFF, sum = 0
2998 17:41:41.200870 3, 0xFFFF, sum = 0
2999 17:41:41.200952 4, 0xFFFF, sum = 0
3000 17:41:41.204408 5, 0xFFFF, sum = 0
3001 17:41:41.204491 6, 0xFFFF, sum = 0
3002 17:41:41.207999 7, 0xFFFF, sum = 0
3003 17:41:41.208103 8, 0xFFFF, sum = 0
3004 17:41:41.211564 9, 0xFFFF, sum = 0
3005 17:41:41.211635 10, 0xFFFF, sum = 0
3006 17:41:41.214500 11, 0xFFFF, sum = 0
3007 17:41:41.214581 12, 0x0, sum = 1
3008 17:41:41.217989 13, 0x0, sum = 2
3009 17:41:41.218070 14, 0x0, sum = 3
3010 17:41:41.221187 15, 0x0, sum = 4
3011 17:41:41.221270 best_step = 13
3012 17:41:41.221334
3013 17:41:41.221393 ==
3014 17:41:41.224644 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 17:41:41.228292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 17:41:41.231763 ==
3017 17:41:41.231844 RX Vref Scan: 0
3018 17:41:41.231908
3019 17:41:41.235243 RX Vref 0 -> 0, step: 1
3020 17:41:41.235361
3021 17:41:41.235440 RX Delay -21 -> 252, step: 4
3022 17:41:41.242625 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3023 17:41:41.245664 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3024 17:41:41.249354 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3025 17:41:41.252725 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3026 17:41:41.256037 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3027 17:41:41.262598 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3028 17:41:41.266152 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3029 17:41:41.269126 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3030 17:41:41.272685 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3031 17:41:41.275892 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3032 17:41:41.279481 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3033 17:41:41.286157 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3034 17:41:41.289297 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3035 17:41:41.292880 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3036 17:41:41.296258 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3037 17:41:41.299867 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3038 17:41:41.302685 ==
3039 17:41:41.306518 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 17:41:41.309359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 17:41:41.309440 ==
3042 17:41:41.309503 DQS Delay:
3043 17:41:41.313044 DQS0 = 0, DQS1 = 0
3044 17:41:41.313124 DQM Delay:
3045 17:41:41.316476 DQM0 = 114, DQM1 = 104
3046 17:41:41.316557 DQ Delay:
3047 17:41:41.319874 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3048 17:41:41.322642 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3049 17:41:41.326028 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3050 17:41:41.329359 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3051 17:41:41.329440
3052 17:41:41.329503
3053 17:41:41.339399 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3054 17:41:41.339481 CH0 RK1: MR19=403, MR18=2F4
3055 17:41:41.346048 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3056 17:41:41.349568 [RxdqsGatingPostProcess] freq 1200
3057 17:41:41.356502 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 17:41:41.359583 best DQS0 dly(2T, 0.5T) = (0, 12)
3059 17:41:41.363127 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 17:41:41.363207 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3061 17:41:41.366497 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 17:41:41.369766 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 17:41:41.373579 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 17:41:41.376461 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 17:41:41.379853 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 17:41:41.383438 Pre-setting of DQS Precalculation
3067 17:41:41.390179 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 17:41:41.390258 ==
3069 17:41:41.393117 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 17:41:41.396666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 17:41:41.396739 ==
3072 17:41:41.400196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 17:41:41.406652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 17:41:41.415759 [CA 0] Center 38 (9~68) winsize 60
3075 17:41:41.419435 [CA 1] Center 38 (8~68) winsize 61
3076 17:41:41.422846 [CA 2] Center 35 (5~65) winsize 61
3077 17:41:41.425935 [CA 3] Center 34 (4~65) winsize 62
3078 17:41:41.429257 [CA 4] Center 34 (4~65) winsize 62
3079 17:41:41.432872 [CA 5] Center 34 (4~64) winsize 61
3080 17:41:41.432943
3081 17:41:41.436241 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3082 17:41:41.436318
3083 17:41:41.439635 [CATrainingPosCal] consider 1 rank data
3084 17:41:41.443068 u2DelayCellTimex100 = 270/100 ps
3085 17:41:41.446287 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3086 17:41:41.449998 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3087 17:41:41.452638 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3088 17:41:41.459840 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3089 17:41:41.462965 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3090 17:41:41.466220 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3091 17:41:41.466301
3092 17:41:41.469684 CA PerBit enable=1, Macro0, CA PI delay=34
3093 17:41:41.469765
3094 17:41:41.473168 [CBTSetCACLKResult] CA Dly = 34
3095 17:41:41.473280 CS Dly: 5 (0~36)
3096 17:41:41.473380 ==
3097 17:41:41.476179 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 17:41:41.483344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 17:41:41.483436 ==
3100 17:41:41.486620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 17:41:41.493121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3102 17:41:41.501903 [CA 0] Center 38 (8~68) winsize 61
3103 17:41:41.504784 [CA 1] Center 38 (9~68) winsize 60
3104 17:41:41.508196 [CA 2] Center 34 (4~65) winsize 62
3105 17:41:41.511792 [CA 3] Center 34 (4~65) winsize 62
3106 17:41:41.514675 [CA 4] Center 34 (4~65) winsize 62
3107 17:41:41.518180 [CA 5] Center 33 (3~63) winsize 61
3108 17:41:41.518268
3109 17:41:41.521780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3110 17:41:41.521860
3111 17:41:41.524780 [CATrainingPosCal] consider 2 rank data
3112 17:41:41.528337 u2DelayCellTimex100 = 270/100 ps
3113 17:41:41.531805 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3114 17:41:41.534891 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3115 17:41:41.538345 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3116 17:41:41.545427 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3117 17:41:41.548749 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3118 17:41:41.551746 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3119 17:41:41.551854
3120 17:41:41.555637 CA PerBit enable=1, Macro0, CA PI delay=33
3121 17:41:41.555717
3122 17:41:41.558612 [CBTSetCACLKResult] CA Dly = 33
3123 17:41:41.558693 CS Dly: 7 (0~40)
3124 17:41:41.558800
3125 17:41:41.562030 ----->DramcWriteLeveling(PI) begin...
3126 17:41:41.562111 ==
3127 17:41:41.565523 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 17:41:41.572282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 17:41:41.572364 ==
3130 17:41:41.575261 Write leveling (Byte 0): 25 => 25
3131 17:41:41.575342 Write leveling (Byte 1): 29 => 29
3132 17:41:41.578692 DramcWriteLeveling(PI) end<-----
3133 17:41:41.578825
3134 17:41:41.582132 ==
3135 17:41:41.582212 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 17:41:41.588499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 17:41:41.588587 ==
3138 17:41:41.591992 [Gating] SW mode calibration
3139 17:41:41.598860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 17:41:41.602126 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 17:41:41.608903 0 15 0 | B1->B0 | 2626 2323 | 1 1 | (1 1) (1 1)
3142 17:41:41.612126 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 17:41:41.615989 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 17:41:41.619137 0 15 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3145 17:41:41.625604 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 17:41:41.629003 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 17:41:41.632695 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 17:41:41.639119 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3149 17:41:41.642546 1 0 0 | B1->B0 | 2424 2d2d | 0 0 | (1 0) (1 0)
3150 17:41:41.645749 1 0 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3151 17:41:41.652666 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 17:41:41.656130 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 17:41:41.659314 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 17:41:41.666114 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 17:41:41.669527 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 17:41:41.672767 1 0 28 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
3157 17:41:41.675893 1 1 0 | B1->B0 | 3f3f 2b2b | 0 1 | (1 1) (0 0)
3158 17:41:41.682816 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 17:41:41.686410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 17:41:41.689623 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 17:41:41.695977 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 17:41:41.699457 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 17:41:41.703037 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 17:41:41.709811 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3165 17:41:41.712888 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3166 17:41:41.716241 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 17:41:41.722942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 17:41:41.726223 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 17:41:41.729941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 17:41:41.736333 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 17:41:41.739881 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 17:41:41.743279 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 17:41:41.746305 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 17:41:41.753452 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 17:41:41.756458 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 17:41:41.759650 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 17:41:41.766602 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 17:41:41.769684 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 17:41:41.773147 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3180 17:41:41.779611 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3181 17:41:41.783300 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 17:41:41.786459 Total UI for P1: 0, mck2ui 16
3183 17:41:41.790227 best dqsien dly found for B0: ( 1, 3, 26)
3184 17:41:41.793316 Total UI for P1: 0, mck2ui 16
3185 17:41:41.796646 best dqsien dly found for B1: ( 1, 3, 28)
3186 17:41:41.799788 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3187 17:41:41.803136 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3188 17:41:41.803209
3189 17:41:41.807017 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3190 17:41:41.809864 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3191 17:41:41.813328 [Gating] SW calibration Done
3192 17:41:41.813400 ==
3193 17:41:41.816689 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 17:41:41.820058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 17:41:41.820129 ==
3196 17:41:41.823306 RX Vref Scan: 0
3197 17:41:41.823375
3198 17:41:41.826933 RX Vref 0 -> 0, step: 1
3199 17:41:41.827003
3200 17:41:41.827070 RX Delay -40 -> 252, step: 8
3201 17:41:41.833181 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3202 17:41:41.836325 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3203 17:41:41.839828 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3204 17:41:41.843239 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3205 17:41:41.846425 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3206 17:41:41.853367 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3207 17:41:41.856792 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3208 17:41:41.859765 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3209 17:41:41.863386 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3210 17:41:41.866733 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3211 17:41:41.873287 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3212 17:41:41.876597 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3213 17:41:41.880216 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3214 17:41:41.883549 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3215 17:41:41.886640 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3216 17:41:41.893333 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3217 17:41:41.893408 ==
3218 17:41:41.897101 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 17:41:41.900138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 17:41:41.900232 ==
3221 17:41:41.900314 DQS Delay:
3222 17:41:41.903580 DQS0 = 0, DQS1 = 0
3223 17:41:41.903656 DQM Delay:
3224 17:41:41.906834 DQM0 = 116, DQM1 = 108
3225 17:41:41.906907 DQ Delay:
3226 17:41:41.910382 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3227 17:41:41.913708 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3228 17:41:41.916732 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3229 17:41:41.920093 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3230 17:41:41.920164
3231 17:41:41.920225
3232 17:41:41.920289 ==
3233 17:41:41.923905 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 17:41:41.929988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 17:41:41.930065 ==
3236 17:41:41.930128
3237 17:41:41.930193
3238 17:41:41.930250 TX Vref Scan disable
3239 17:41:41.933897 == TX Byte 0 ==
3240 17:41:41.937045 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 17:41:41.940370 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 17:41:41.944346 == TX Byte 1 ==
3243 17:41:41.947273 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3244 17:41:41.950974 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3245 17:41:41.953864 ==
3246 17:41:41.953935 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 17:41:41.960321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 17:41:41.960393 ==
3249 17:41:41.971610 TX Vref=22, minBit 1, minWin=24, winSum=410
3250 17:41:41.974914 TX Vref=24, minBit 1, minWin=25, winSum=414
3251 17:41:41.978918 TX Vref=26, minBit 1, minWin=26, winSum=422
3252 17:41:41.981588 TX Vref=28, minBit 15, minWin=25, winSum=423
3253 17:41:41.985179 TX Vref=30, minBit 0, minWin=26, winSum=427
3254 17:41:41.988704 TX Vref=32, minBit 13, minWin=25, winSum=426
3255 17:41:41.995251 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
3256 17:41:41.995324
3257 17:41:41.998761 Final TX Range 1 Vref 30
3258 17:41:41.998850
3259 17:41:41.998918 ==
3260 17:41:42.001857 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 17:41:42.005879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 17:41:42.005957 ==
3263 17:41:42.006016
3264 17:41:42.006073
3265 17:41:42.008888 TX Vref Scan disable
3266 17:41:42.011907 == TX Byte 0 ==
3267 17:41:42.015253 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3268 17:41:42.018513 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3269 17:41:42.022103 == TX Byte 1 ==
3270 17:41:42.025764 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3271 17:41:42.028887 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3272 17:41:42.028959
3273 17:41:42.032185 [DATLAT]
3274 17:41:42.032255 Freq=1200, CH1 RK0
3275 17:41:42.032315
3276 17:41:42.035568 DATLAT Default: 0xd
3277 17:41:42.035638 0, 0xFFFF, sum = 0
3278 17:41:42.038699 1, 0xFFFF, sum = 0
3279 17:41:42.038797 2, 0xFFFF, sum = 0
3280 17:41:42.042352 3, 0xFFFF, sum = 0
3281 17:41:42.042432 4, 0xFFFF, sum = 0
3282 17:41:42.045383 5, 0xFFFF, sum = 0
3283 17:41:42.045457 6, 0xFFFF, sum = 0
3284 17:41:42.049212 7, 0xFFFF, sum = 0
3285 17:41:42.049286 8, 0xFFFF, sum = 0
3286 17:41:42.052120 9, 0xFFFF, sum = 0
3287 17:41:42.052198 10, 0xFFFF, sum = 0
3288 17:41:42.055675 11, 0xFFFF, sum = 0
3289 17:41:42.055745 12, 0x0, sum = 1
3290 17:41:42.058697 13, 0x0, sum = 2
3291 17:41:42.058823 14, 0x0, sum = 3
3292 17:41:42.062149 15, 0x0, sum = 4
3293 17:41:42.062220 best_step = 13
3294 17:41:42.062279
3295 17:41:42.062336 ==
3296 17:41:42.065764 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 17:41:42.072378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 17:41:42.072456 ==
3299 17:41:42.072517 RX Vref Scan: 1
3300 17:41:42.072575
3301 17:41:42.075895 Set Vref Range= 32 -> 127
3302 17:41:42.075963
3303 17:41:42.079318 RX Vref 32 -> 127, step: 1
3304 17:41:42.079390
3305 17:41:42.079449 RX Delay -21 -> 252, step: 4
3306 17:41:42.079506
3307 17:41:42.082400 Set Vref, RX VrefLevel [Byte0]: 32
3308 17:41:42.085812 [Byte1]: 32
3309 17:41:42.089995
3310 17:41:42.090067 Set Vref, RX VrefLevel [Byte0]: 33
3311 17:41:42.093573 [Byte1]: 33
3312 17:41:42.098089
3313 17:41:42.098160 Set Vref, RX VrefLevel [Byte0]: 34
3314 17:41:42.101563 [Byte1]: 34
3315 17:41:42.105831
3316 17:41:42.105902 Set Vref, RX VrefLevel [Byte0]: 35
3317 17:41:42.109321 [Byte1]: 35
3318 17:41:42.114111
3319 17:41:42.114181 Set Vref, RX VrefLevel [Byte0]: 36
3320 17:41:42.117055 [Byte1]: 36
3321 17:41:42.121639
3322 17:41:42.121721 Set Vref, RX VrefLevel [Byte0]: 37
3323 17:41:42.125154 [Byte1]: 37
3324 17:41:42.129675
3325 17:41:42.129745 Set Vref, RX VrefLevel [Byte0]: 38
3326 17:41:42.132892 [Byte1]: 38
3327 17:41:42.137836
3328 17:41:42.137907 Set Vref, RX VrefLevel [Byte0]: 39
3329 17:41:42.141274 [Byte1]: 39
3330 17:41:42.145821
3331 17:41:42.145892 Set Vref, RX VrefLevel [Byte0]: 40
3332 17:41:42.148791 [Byte1]: 40
3333 17:41:42.153513
3334 17:41:42.153584 Set Vref, RX VrefLevel [Byte0]: 41
3335 17:41:42.156745 [Byte1]: 41
3336 17:41:42.161731
3337 17:41:42.161804 Set Vref, RX VrefLevel [Byte0]: 42
3338 17:41:42.164775 [Byte1]: 42
3339 17:41:42.169384
3340 17:41:42.169461 Set Vref, RX VrefLevel [Byte0]: 43
3341 17:41:42.172967 [Byte1]: 43
3342 17:41:42.177123
3343 17:41:42.177193 Set Vref, RX VrefLevel [Byte0]: 44
3344 17:41:42.180780 [Byte1]: 44
3345 17:41:42.185351
3346 17:41:42.185422 Set Vref, RX VrefLevel [Byte0]: 45
3347 17:41:42.188428 [Byte1]: 45
3348 17:41:42.193101
3349 17:41:42.193171 Set Vref, RX VrefLevel [Byte0]: 46
3350 17:41:42.196619 [Byte1]: 46
3351 17:41:42.201570
3352 17:41:42.201640 Set Vref, RX VrefLevel [Byte0]: 47
3353 17:41:42.204372 [Byte1]: 47
3354 17:41:42.208850
3355 17:41:42.208939 Set Vref, RX VrefLevel [Byte0]: 48
3356 17:41:42.212557 [Byte1]: 48
3357 17:41:42.217334
3358 17:41:42.217409 Set Vref, RX VrefLevel [Byte0]: 49
3359 17:41:42.220434 [Byte1]: 49
3360 17:41:42.224975
3361 17:41:42.225046 Set Vref, RX VrefLevel [Byte0]: 50
3362 17:41:42.228585 [Byte1]: 50
3363 17:41:42.232561
3364 17:41:42.232630 Set Vref, RX VrefLevel [Byte0]: 51
3365 17:41:42.235929 [Byte1]: 51
3366 17:41:42.240491
3367 17:41:42.240567 Set Vref, RX VrefLevel [Byte0]: 52
3368 17:41:42.244007 [Byte1]: 52
3369 17:41:42.248456
3370 17:41:42.248529 Set Vref, RX VrefLevel [Byte0]: 53
3371 17:41:42.251689 [Byte1]: 53
3372 17:41:42.256226
3373 17:41:42.256295 Set Vref, RX VrefLevel [Byte0]: 54
3374 17:41:42.259839 [Byte1]: 54
3375 17:41:42.264650
3376 17:41:42.264720 Set Vref, RX VrefLevel [Byte0]: 55
3377 17:41:42.267768 [Byte1]: 55
3378 17:41:42.272129
3379 17:41:42.272205 Set Vref, RX VrefLevel [Byte0]: 56
3380 17:41:42.275741 [Byte1]: 56
3381 17:41:42.280471
3382 17:41:42.280543 Set Vref, RX VrefLevel [Byte0]: 57
3383 17:41:42.283362 [Byte1]: 57
3384 17:41:42.288243
3385 17:41:42.288318 Set Vref, RX VrefLevel [Byte0]: 58
3386 17:41:42.291837 [Byte1]: 58
3387 17:41:42.296021
3388 17:41:42.296088 Set Vref, RX VrefLevel [Byte0]: 59
3389 17:41:42.299191 [Byte1]: 59
3390 17:41:42.304152
3391 17:41:42.304228 Set Vref, RX VrefLevel [Byte0]: 60
3392 17:41:42.307143 [Byte1]: 60
3393 17:41:42.312044
3394 17:41:42.312128 Set Vref, RX VrefLevel [Byte0]: 61
3395 17:41:42.314981 [Byte1]: 61
3396 17:41:42.320049
3397 17:41:42.320120 Set Vref, RX VrefLevel [Byte0]: 62
3398 17:41:42.323561 [Byte1]: 62
3399 17:41:42.327754
3400 17:41:42.327827 Set Vref, RX VrefLevel [Byte0]: 63
3401 17:41:42.330925 [Byte1]: 63
3402 17:41:42.335563
3403 17:41:42.335635 Set Vref, RX VrefLevel [Byte0]: 64
3404 17:41:42.338680 [Byte1]: 64
3405 17:41:42.343579
3406 17:41:42.343660 Set Vref, RX VrefLevel [Byte0]: 65
3407 17:41:42.347111 [Byte1]: 65
3408 17:41:42.351178
3409 17:41:42.351250 Set Vref, RX VrefLevel [Byte0]: 66
3410 17:41:42.354986 [Byte1]: 66
3411 17:41:42.359137
3412 17:41:42.359210 Set Vref, RX VrefLevel [Byte0]: 67
3413 17:41:42.362522 [Byte1]: 67
3414 17:41:42.367233
3415 17:41:42.367312 Set Vref, RX VrefLevel [Byte0]: 68
3416 17:41:42.370854 [Byte1]: 68
3417 17:41:42.375473
3418 17:41:42.375545 Set Vref, RX VrefLevel [Byte0]: 69
3419 17:41:42.378675 [Byte1]: 69
3420 17:41:42.383404
3421 17:41:42.383476 Final RX Vref Byte 0 = 57 to rank0
3422 17:41:42.386780 Final RX Vref Byte 1 = 46 to rank0
3423 17:41:42.389673 Final RX Vref Byte 0 = 57 to rank1
3424 17:41:42.393002 Final RX Vref Byte 1 = 46 to rank1==
3425 17:41:42.396592 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 17:41:42.400048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 17:41:42.403576 ==
3428 17:41:42.403648 DQS Delay:
3429 17:41:42.403717 DQS0 = 0, DQS1 = 0
3430 17:41:42.406528 DQM Delay:
3431 17:41:42.406597 DQM0 = 115, DQM1 = 107
3432 17:41:42.410307 DQ Delay:
3433 17:41:42.413748 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3434 17:41:42.416685 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3435 17:41:42.420314 DQ8 =94, DQ9 =94, DQ10 =110, DQ11 =102
3436 17:41:42.423706 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3437 17:41:42.423777
3438 17:41:42.423845
3439 17:41:42.430186 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3440 17:41:42.433825 CH1 RK0: MR19=303, MR18=FEE3
3441 17:41:42.440215 CH1_RK0: MR19=0x303, MR18=0xFEE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3442 17:41:42.440294
3443 17:41:42.443622 ----->DramcWriteLeveling(PI) begin...
3444 17:41:42.443696 ==
3445 17:41:42.446979 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 17:41:42.450435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 17:41:42.450510 ==
3448 17:41:42.453544 Write leveling (Byte 0): 26 => 26
3449 17:41:42.456893 Write leveling (Byte 1): 30 => 30
3450 17:41:42.460197 DramcWriteLeveling(PI) end<-----
3451 17:41:42.460270
3452 17:41:42.460331 ==
3453 17:41:42.463865 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 17:41:42.467253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 17:41:42.467324 ==
3456 17:41:42.470670 [Gating] SW mode calibration
3457 17:41:42.477253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 17:41:42.484230 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 17:41:42.487798 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3460 17:41:42.490623 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 17:41:42.497739 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 17:41:42.500698 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3463 17:41:42.504069 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 17:41:42.511054 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3465 17:41:42.514035 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3466 17:41:42.517721 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3467 17:41:42.524440 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 17:41:42.527904 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 17:41:42.530900 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 17:41:42.537510 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 17:41:42.541056 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 17:41:42.544214 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 17:41:42.548117 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
3474 17:41:42.554777 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3475 17:41:42.558147 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 17:41:42.561094 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 17:41:42.567729 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 17:41:42.571165 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 17:41:42.574740 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 17:41:42.581576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 17:41:42.584441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 17:41:42.587817 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3483 17:41:42.594822 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 17:41:42.598263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 17:41:42.601420 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 17:41:42.608356 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 17:41:42.611366 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 17:41:42.614999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 17:41:42.621521 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 17:41:42.624955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 17:41:42.628284 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 17:41:42.631340 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 17:41:42.638194 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 17:41:42.641357 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 17:41:42.644909 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 17:41:42.651268 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3497 17:41:42.654987 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3498 17:41:42.657821 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3499 17:41:42.661184 Total UI for P1: 0, mck2ui 16
3500 17:41:42.664532 best dqsien dly found for B0: ( 1, 3, 22)
3501 17:41:42.671385 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 17:41:42.671462 Total UI for P1: 0, mck2ui 16
3503 17:41:42.678334 best dqsien dly found for B1: ( 1, 3, 28)
3504 17:41:42.681557 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3505 17:41:42.684761 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3506 17:41:42.684834
3507 17:41:42.687857 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3508 17:41:42.691088 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3509 17:41:42.694623 [Gating] SW calibration Done
3510 17:41:42.694697 ==
3511 17:41:42.698070 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 17:41:42.701252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 17:41:42.701332 ==
3514 17:41:42.704455 RX Vref Scan: 0
3515 17:41:42.704529
3516 17:41:42.704596 RX Vref 0 -> 0, step: 1
3517 17:41:42.704654
3518 17:41:42.707954 RX Delay -40 -> 252, step: 8
3519 17:41:42.711838 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3520 17:41:42.717837 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3521 17:41:42.721290 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3522 17:41:42.724979 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3523 17:41:42.727945 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3524 17:41:42.731494 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3525 17:41:42.738047 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3526 17:41:42.741566 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3527 17:41:42.744644 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3528 17:41:42.748372 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3529 17:41:42.751759 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3530 17:41:42.754802 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3531 17:41:42.761517 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3532 17:41:42.764592 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3533 17:41:42.768550 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3534 17:41:42.771711 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3535 17:41:42.771783 ==
3536 17:41:42.775049 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 17:41:42.781793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 17:41:42.781878 ==
3539 17:41:42.781945 DQS Delay:
3540 17:41:42.784898 DQS0 = 0, DQS1 = 0
3541 17:41:42.784975 DQM Delay:
3542 17:41:42.785039 DQM0 = 113, DQM1 = 108
3543 17:41:42.788397 DQ Delay:
3544 17:41:42.791785 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3545 17:41:42.794870 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3546 17:41:42.798118 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3547 17:41:42.801444 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3548 17:41:42.801522
3549 17:41:42.801584
3550 17:41:42.801641 ==
3551 17:41:42.805103 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 17:41:42.808549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 17:41:42.808627 ==
3554 17:41:42.808688
3555 17:41:42.811408
3556 17:41:42.811479 TX Vref Scan disable
3557 17:41:42.814902 == TX Byte 0 ==
3558 17:41:42.818298 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3559 17:41:42.821383 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3560 17:41:42.825238 == TX Byte 1 ==
3561 17:41:42.828273 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3562 17:41:42.831944 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3563 17:41:42.832017 ==
3564 17:41:42.834848 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 17:41:42.841827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 17:41:42.841901 ==
3567 17:41:42.852640 TX Vref=22, minBit 0, minWin=25, winSum=414
3568 17:41:42.855557 TX Vref=24, minBit 0, minWin=25, winSum=420
3569 17:41:42.858975 TX Vref=26, minBit 1, minWin=26, winSum=431
3570 17:41:42.861904 TX Vref=28, minBit 4, minWin=26, winSum=431
3571 17:41:42.865462 TX Vref=30, minBit 13, minWin=26, winSum=432
3572 17:41:42.868773 TX Vref=32, minBit 2, minWin=26, winSum=429
3573 17:41:42.875395 [TxChooseVref] Worse bit 13, Min win 26, Win sum 432, Final Vref 30
3574 17:41:42.875471
3575 17:41:42.879130 Final TX Range 1 Vref 30
3576 17:41:42.879202
3577 17:41:42.879261 ==
3578 17:41:42.882464 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 17:41:42.885534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 17:41:42.885620 ==
3581 17:41:42.885681
3582 17:41:42.888657
3583 17:41:42.888729 TX Vref Scan disable
3584 17:41:42.892683 == TX Byte 0 ==
3585 17:41:42.895425 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3586 17:41:42.898827 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3587 17:41:42.902324 == TX Byte 1 ==
3588 17:41:42.905503 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3589 17:41:42.908885 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3590 17:41:42.908960
3591 17:41:42.912346 [DATLAT]
3592 17:41:42.912421 Freq=1200, CH1 RK1
3593 17:41:42.912483
3594 17:41:42.915824 DATLAT Default: 0xd
3595 17:41:42.915894 0, 0xFFFF, sum = 0
3596 17:41:42.919087 1, 0xFFFF, sum = 0
3597 17:41:42.919180 2, 0xFFFF, sum = 0
3598 17:41:42.922314 3, 0xFFFF, sum = 0
3599 17:41:42.922385 4, 0xFFFF, sum = 0
3600 17:41:42.926153 5, 0xFFFF, sum = 0
3601 17:41:42.926225 6, 0xFFFF, sum = 0
3602 17:41:42.929409 7, 0xFFFF, sum = 0
3603 17:41:42.929487 8, 0xFFFF, sum = 0
3604 17:41:42.932093 9, 0xFFFF, sum = 0
3605 17:41:42.935420 10, 0xFFFF, sum = 0
3606 17:41:42.935498 11, 0xFFFF, sum = 0
3607 17:41:42.938957 12, 0x0, sum = 1
3608 17:41:42.939030 13, 0x0, sum = 2
3609 17:41:42.939091 14, 0x0, sum = 3
3610 17:41:42.942541 15, 0x0, sum = 4
3611 17:41:42.942610 best_step = 13
3612 17:41:42.942670
3613 17:41:42.942733 ==
3614 17:41:42.946031 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 17:41:42.952455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 17:41:42.952534 ==
3617 17:41:42.952595 RX Vref Scan: 0
3618 17:41:42.952653
3619 17:41:42.955408 RX Vref 0 -> 0, step: 1
3620 17:41:42.955477
3621 17:41:42.958967 RX Delay -21 -> 252, step: 4
3622 17:41:42.962626 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3623 17:41:42.965399 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3624 17:41:42.972619 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3625 17:41:42.975745 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3626 17:41:42.978727 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3627 17:41:42.982312 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3628 17:41:42.985637 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3629 17:41:42.992081 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3630 17:41:42.995548 iDelay=191, Bit 8, Center 94 (27 ~ 162) 136
3631 17:41:42.998886 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3632 17:41:43.002223 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3633 17:41:43.005355 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3634 17:41:43.012188 iDelay=191, Bit 12, Center 116 (55 ~ 178) 124
3635 17:41:43.015550 iDelay=191, Bit 13, Center 116 (51 ~ 182) 132
3636 17:41:43.019290 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3637 17:41:43.022201 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3638 17:41:43.022280 ==
3639 17:41:43.025453 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 17:41:43.032690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 17:41:43.032766 ==
3642 17:41:43.032828 DQS Delay:
3643 17:41:43.032895 DQS0 = 0, DQS1 = 0
3644 17:41:43.035436 DQM Delay:
3645 17:41:43.035506 DQM0 = 113, DQM1 = 108
3646 17:41:43.039410 DQ Delay:
3647 17:41:43.042130 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3648 17:41:43.045575 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3649 17:41:43.048875 DQ8 =94, DQ9 =98, DQ10 =110, DQ11 =100
3650 17:41:43.052460 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =116
3651 17:41:43.052533
3652 17:41:43.052594
3653 17:41:43.059092 [DQSOSCAuto] RK1, (LSB)MR18= 0xf800, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3654 17:41:43.062530 CH1 RK1: MR19=304, MR18=F800
3655 17:41:43.069012 CH1_RK1: MR19=0x304, MR18=0xF800, DQSOSC=410, MR23=63, INC=39, DEC=26
3656 17:41:43.072425 [RxdqsGatingPostProcess] freq 1200
3657 17:41:43.078827 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3658 17:41:43.082278 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 17:41:43.082358 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 17:41:43.085782 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 17:41:43.088945 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 17:41:43.092220 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 17:41:43.095598 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 17:41:43.099000 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 17:41:43.102191 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 17:41:43.105827 Pre-setting of DQS Precalculation
3667 17:41:43.112441 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3668 17:41:43.118988 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3669 17:41:43.125796 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3670 17:41:43.125876
3671 17:41:43.125940
3672 17:41:43.129223 [Calibration Summary] 2400 Mbps
3673 17:41:43.129295 CH 0, Rank 0
3674 17:41:43.132381 SW Impedance : PASS
3675 17:41:43.135789 DUTY Scan : NO K
3676 17:41:43.135861 ZQ Calibration : PASS
3677 17:41:43.139284 Jitter Meter : NO K
3678 17:41:43.139355 CBT Training : PASS
3679 17:41:43.142567 Write leveling : PASS
3680 17:41:43.145797 RX DQS gating : PASS
3681 17:41:43.145880 RX DQ/DQS(RDDQC) : PASS
3682 17:41:43.149099 TX DQ/DQS : PASS
3683 17:41:43.152812 RX DATLAT : PASS
3684 17:41:43.152895 RX DQ/DQS(Engine): PASS
3685 17:41:43.155624 TX OE : NO K
3686 17:41:43.155696 All Pass.
3687 17:41:43.155756
3688 17:41:43.159370 CH 0, Rank 1
3689 17:41:43.159439 SW Impedance : PASS
3690 17:41:43.162840 DUTY Scan : NO K
3691 17:41:43.165676 ZQ Calibration : PASS
3692 17:41:43.165747 Jitter Meter : NO K
3693 17:41:43.169209 CBT Training : PASS
3694 17:41:43.172896 Write leveling : PASS
3695 17:41:43.172967 RX DQS gating : PASS
3696 17:41:43.175583 RX DQ/DQS(RDDQC) : PASS
3697 17:41:43.175653 TX DQ/DQS : PASS
3698 17:41:43.179156 RX DATLAT : PASS
3699 17:41:43.182284 RX DQ/DQS(Engine): PASS
3700 17:41:43.182354 TX OE : NO K
3701 17:41:43.185785 All Pass.
3702 17:41:43.185855
3703 17:41:43.185915 CH 1, Rank 0
3704 17:41:43.189221 SW Impedance : PASS
3705 17:41:43.189292 DUTY Scan : NO K
3706 17:41:43.192583 ZQ Calibration : PASS
3707 17:41:43.195607 Jitter Meter : NO K
3708 17:41:43.195682 CBT Training : PASS
3709 17:41:43.199230 Write leveling : PASS
3710 17:41:43.202266 RX DQS gating : PASS
3711 17:41:43.202337 RX DQ/DQS(RDDQC) : PASS
3712 17:41:43.205782 TX DQ/DQS : PASS
3713 17:41:43.209464 RX DATLAT : PASS
3714 17:41:43.209535 RX DQ/DQS(Engine): PASS
3715 17:41:43.212699 TX OE : NO K
3716 17:41:43.212770 All Pass.
3717 17:41:43.212830
3718 17:41:43.215931 CH 1, Rank 1
3719 17:41:43.216010 SW Impedance : PASS
3720 17:41:43.219358 DUTY Scan : NO K
3721 17:41:43.219428 ZQ Calibration : PASS
3722 17:41:43.222392 Jitter Meter : NO K
3723 17:41:43.225743 CBT Training : PASS
3724 17:41:43.225820 Write leveling : PASS
3725 17:41:43.229324 RX DQS gating : PASS
3726 17:41:43.232460 RX DQ/DQS(RDDQC) : PASS
3727 17:41:43.232536 TX DQ/DQS : PASS
3728 17:41:43.236102 RX DATLAT : PASS
3729 17:41:43.239538 RX DQ/DQS(Engine): PASS
3730 17:41:43.239616 TX OE : NO K
3731 17:41:43.242535 All Pass.
3732 17:41:43.242604
3733 17:41:43.242670 DramC Write-DBI off
3734 17:41:43.246041 PER_BANK_REFRESH: Hybrid Mode
3735 17:41:43.246111 TX_TRACKING: ON
3736 17:41:43.256023 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3737 17:41:43.259544 [FAST_K] Save calibration result to emmc
3738 17:41:43.262540 dramc_set_vcore_voltage set vcore to 650000
3739 17:41:43.265693 Read voltage for 600, 5
3740 17:41:43.265775 Vio18 = 0
3741 17:41:43.269253 Vcore = 650000
3742 17:41:43.269331 Vdram = 0
3743 17:41:43.269393 Vddq = 0
3744 17:41:43.269451 Vmddr = 0
3745 17:41:43.275842 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3746 17:41:43.282413 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3747 17:41:43.282487 MEM_TYPE=3, freq_sel=19
3748 17:41:43.286262 sv_algorithm_assistance_LP4_1600
3749 17:41:43.289615 ============ PULL DRAM RESETB DOWN ============
3750 17:41:43.296202 ========== PULL DRAM RESETB DOWN end =========
3751 17:41:43.299467 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 17:41:43.302866 ===================================
3753 17:41:43.306348 LPDDR4 DRAM CONFIGURATION
3754 17:41:43.309418 ===================================
3755 17:41:43.309493 EX_ROW_EN[0] = 0x0
3756 17:41:43.312768 EX_ROW_EN[1] = 0x0
3757 17:41:43.312844 LP4Y_EN = 0x0
3758 17:41:43.315961 WORK_FSP = 0x0
3759 17:41:43.316033 WL = 0x2
3760 17:41:43.319535 RL = 0x2
3761 17:41:43.319613 BL = 0x2
3762 17:41:43.322656 RPST = 0x0
3763 17:41:43.322733 RD_PRE = 0x0
3764 17:41:43.326402 WR_PRE = 0x1
3765 17:41:43.326472 WR_PST = 0x0
3766 17:41:43.329877 DBI_WR = 0x0
3767 17:41:43.332942 DBI_RD = 0x0
3768 17:41:43.333026 OTF = 0x1
3769 17:41:43.336405 ===================================
3770 17:41:43.339693 ===================================
3771 17:41:43.339766 ANA top config
3772 17:41:43.342710 ===================================
3773 17:41:43.346060 DLL_ASYNC_EN = 0
3774 17:41:43.349705 ALL_SLAVE_EN = 1
3775 17:41:43.353092 NEW_RANK_MODE = 1
3776 17:41:43.353165 DLL_IDLE_MODE = 1
3777 17:41:43.356141 LP45_APHY_COMB_EN = 1
3778 17:41:43.359415 TX_ODT_DIS = 1
3779 17:41:43.363247 NEW_8X_MODE = 1
3780 17:41:43.366258 ===================================
3781 17:41:43.369809 ===================================
3782 17:41:43.373369 data_rate = 1200
3783 17:41:43.373441 CKR = 1
3784 17:41:43.376190 DQ_P2S_RATIO = 8
3785 17:41:43.379867 ===================================
3786 17:41:43.382845 CA_P2S_RATIO = 8
3787 17:41:43.386420 DQ_CA_OPEN = 0
3788 17:41:43.389307 DQ_SEMI_OPEN = 0
3789 17:41:43.393037 CA_SEMI_OPEN = 0
3790 17:41:43.393110 CA_FULL_RATE = 0
3791 17:41:43.396221 DQ_CKDIV4_EN = 1
3792 17:41:43.399790 CA_CKDIV4_EN = 1
3793 17:41:43.403210 CA_PREDIV_EN = 0
3794 17:41:43.406067 PH8_DLY = 0
3795 17:41:43.409767 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3796 17:41:43.409841 DQ_AAMCK_DIV = 4
3797 17:41:43.413353 CA_AAMCK_DIV = 4
3798 17:41:43.416470 CA_ADMCK_DIV = 4
3799 17:41:43.420073 DQ_TRACK_CA_EN = 0
3800 17:41:43.422930 CA_PICK = 600
3801 17:41:43.426588 CA_MCKIO = 600
3802 17:41:43.426687 MCKIO_SEMI = 0
3803 17:41:43.430123 PLL_FREQ = 2288
3804 17:41:43.433159 DQ_UI_PI_RATIO = 32
3805 17:41:43.436564 CA_UI_PI_RATIO = 0
3806 17:41:43.440059 ===================================
3807 17:41:43.443338 ===================================
3808 17:41:43.446351 memory_type:LPDDR4
3809 17:41:43.446422 GP_NUM : 10
3810 17:41:43.449840 SRAM_EN : 1
3811 17:41:43.453202 MD32_EN : 0
3812 17:41:43.453274 ===================================
3813 17:41:43.456951 [ANA_INIT] >>>>>>>>>>>>>>
3814 17:41:43.459962 <<<<<< [CONFIGURE PHASE]: ANA_TX
3815 17:41:43.462998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3816 17:41:43.466540 ===================================
3817 17:41:43.469865 data_rate = 1200,PCW = 0X5800
3818 17:41:43.473179 ===================================
3819 17:41:43.476777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3820 17:41:43.483368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 17:41:43.487125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 17:41:43.493319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3823 17:41:43.497034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3824 17:41:43.500082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3825 17:41:43.500156 [ANA_INIT] flow start
3826 17:41:43.503491 [ANA_INIT] PLL >>>>>>>>
3827 17:41:43.506427 [ANA_INIT] PLL <<<<<<<<
3828 17:41:43.506500 [ANA_INIT] MIDPI >>>>>>>>
3829 17:41:43.509778 [ANA_INIT] MIDPI <<<<<<<<
3830 17:41:43.512995 [ANA_INIT] DLL >>>>>>>>
3831 17:41:43.513067 [ANA_INIT] flow end
3832 17:41:43.520211 ============ LP4 DIFF to SE enter ============
3833 17:41:43.523350 ============ LP4 DIFF to SE exit ============
3834 17:41:43.523432 [ANA_INIT] <<<<<<<<<<<<<
3835 17:41:43.526681 [Flow] Enable top DCM control >>>>>
3836 17:41:43.530530 [Flow] Enable top DCM control <<<<<
3837 17:41:43.533222 Enable DLL master slave shuffle
3838 17:41:43.539977 ==============================================================
3839 17:41:43.540052 Gating Mode config
3840 17:41:43.546480 ==============================================================
3841 17:41:43.550017 Config description:
3842 17:41:43.560064 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3843 17:41:43.566800 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3844 17:41:43.569968 SELPH_MODE 0: By rank 1: By Phase
3845 17:41:43.577035 ==============================================================
3846 17:41:43.580056 GAT_TRACK_EN = 1
3847 17:41:43.583134 RX_GATING_MODE = 2
3848 17:41:43.583217 RX_GATING_TRACK_MODE = 2
3849 17:41:43.586695 SELPH_MODE = 1
3850 17:41:43.590199 PICG_EARLY_EN = 1
3851 17:41:43.593129 VALID_LAT_VALUE = 1
3852 17:41:43.599726 ==============================================================
3853 17:41:43.603335 Enter into Gating configuration >>>>
3854 17:41:43.606907 Exit from Gating configuration <<<<
3855 17:41:43.609874 Enter into DVFS_PRE_config >>>>>
3856 17:41:43.620164 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3857 17:41:43.623245 Exit from DVFS_PRE_config <<<<<
3858 17:41:43.626546 Enter into PICG configuration >>>>
3859 17:41:43.630143 Exit from PICG configuration <<<<
3860 17:41:43.633064 [RX_INPUT] configuration >>>>>
3861 17:41:43.636723 [RX_INPUT] configuration <<<<<
3862 17:41:43.640131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3863 17:41:43.646689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3864 17:41:43.653464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 17:41:43.656491 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 17:41:43.663304 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 17:41:43.669737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 17:41:43.673435 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3869 17:41:43.676795 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3870 17:41:43.683129 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3871 17:41:43.686522 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3872 17:41:43.689768 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3873 17:41:43.696330 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 17:41:43.700004 ===================================
3875 17:41:43.700081 LPDDR4 DRAM CONFIGURATION
3876 17:41:43.703495 ===================================
3877 17:41:43.706531 EX_ROW_EN[0] = 0x0
3878 17:41:43.706629 EX_ROW_EN[1] = 0x0
3879 17:41:43.710021 LP4Y_EN = 0x0
3880 17:41:43.713442 WORK_FSP = 0x0
3881 17:41:43.713517 WL = 0x2
3882 17:41:43.716365 RL = 0x2
3883 17:41:43.716439 BL = 0x2
3884 17:41:43.719729 RPST = 0x0
3885 17:41:43.719804 RD_PRE = 0x0
3886 17:41:43.723473 WR_PRE = 0x1
3887 17:41:43.723544 WR_PST = 0x0
3888 17:41:43.726958 DBI_WR = 0x0
3889 17:41:43.727030 DBI_RD = 0x0
3890 17:41:43.730039 OTF = 0x1
3891 17:41:43.733274 ===================================
3892 17:41:43.736670 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3893 17:41:43.740198 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3894 17:41:43.743158 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 17:41:43.746941 ===================================
3896 17:41:43.750525 LPDDR4 DRAM CONFIGURATION
3897 17:41:43.753894 ===================================
3898 17:41:43.756688 EX_ROW_EN[0] = 0x10
3899 17:41:43.756763 EX_ROW_EN[1] = 0x0
3900 17:41:43.760243 LP4Y_EN = 0x0
3901 17:41:43.760323 WORK_FSP = 0x0
3902 17:41:43.763442 WL = 0x2
3903 17:41:43.763521 RL = 0x2
3904 17:41:43.766963 BL = 0x2
3905 17:41:43.767044 RPST = 0x0
3906 17:41:43.770265 RD_PRE = 0x0
3907 17:41:43.770344 WR_PRE = 0x1
3908 17:41:43.774029 WR_PST = 0x0
3909 17:41:43.774110 DBI_WR = 0x0
3910 17:41:43.776946 DBI_RD = 0x0
3911 17:41:43.777018 OTF = 0x1
3912 17:41:43.780483 ===================================
3913 17:41:43.786845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3914 17:41:43.791836 nWR fixed to 30
3915 17:41:43.795585 [ModeRegInit_LP4] CH0 RK0
3916 17:41:43.795656 [ModeRegInit_LP4] CH0 RK1
3917 17:41:43.798492 [ModeRegInit_LP4] CH1 RK0
3918 17:41:43.801911 [ModeRegInit_LP4] CH1 RK1
3919 17:41:43.801985 match AC timing 17
3920 17:41:43.808651 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3921 17:41:43.811526 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3922 17:41:43.815343 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3923 17:41:43.821549 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3924 17:41:43.825092 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3925 17:41:43.825167 ==
3926 17:41:43.828097 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 17:41:43.831665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 17:41:43.831738 ==
3929 17:41:43.838600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 17:41:43.845206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3931 17:41:43.848902 [CA 0] Center 36 (6~66) winsize 61
3932 17:41:43.851841 [CA 1] Center 36 (6~66) winsize 61
3933 17:41:43.855510 [CA 2] Center 34 (4~65) winsize 62
3934 17:41:43.858021 [CA 3] Center 34 (4~65) winsize 62
3935 17:41:43.861671 [CA 4] Center 33 (3~64) winsize 62
3936 17:41:43.865208 [CA 5] Center 33 (3~64) winsize 62
3937 17:41:43.865281
3938 17:41:43.868307 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3939 17:41:43.868373
3940 17:41:43.871652 [CATrainingPosCal] consider 1 rank data
3941 17:41:43.874870 u2DelayCellTimex100 = 270/100 ps
3942 17:41:43.878706 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3943 17:41:43.882023 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3944 17:41:43.884998 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3945 17:41:43.888460 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 17:41:43.892019 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3947 17:41:43.895250 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 17:41:43.895323
3949 17:41:43.901899 CA PerBit enable=1, Macro0, CA PI delay=33
3950 17:41:43.901978
3951 17:41:43.902042 [CBTSetCACLKResult] CA Dly = 33
3952 17:41:43.905093 CS Dly: 5 (0~36)
3953 17:41:43.905164 ==
3954 17:41:43.908289 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 17:41:43.912123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 17:41:43.912194 ==
3957 17:41:43.918524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 17:41:43.925015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3959 17:41:43.928491 [CA 0] Center 36 (6~67) winsize 62
3960 17:41:43.932264 [CA 1] Center 36 (6~66) winsize 61
3961 17:41:43.935224 [CA 2] Center 34 (4~65) winsize 62
3962 17:41:43.938461 [CA 3] Center 34 (4~65) winsize 62
3963 17:41:43.941459 [CA 4] Center 33 (3~64) winsize 62
3964 17:41:43.945111 [CA 5] Center 33 (3~64) winsize 62
3965 17:41:43.945180
3966 17:41:43.948734 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3967 17:41:43.948801
3968 17:41:43.951670 [CATrainingPosCal] consider 2 rank data
3969 17:41:43.955009 u2DelayCellTimex100 = 270/100 ps
3970 17:41:43.958458 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3971 17:41:43.961900 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3972 17:41:43.965337 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3973 17:41:43.968281 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3974 17:41:43.971854 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 17:41:43.975459 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 17:41:43.975564
3977 17:41:43.981941 CA PerBit enable=1, Macro0, CA PI delay=33
3978 17:41:43.982077
3979 17:41:43.982144 [CBTSetCACLKResult] CA Dly = 33
3980 17:41:43.984997 CS Dly: 5 (0~36)
3981 17:41:43.985081
3982 17:41:43.988238 ----->DramcWriteLeveling(PI) begin...
3983 17:41:43.988325 ==
3984 17:41:43.992147 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 17:41:43.994959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 17:41:43.995147 ==
3987 17:41:43.998116 Write leveling (Byte 0): 31 => 31
3988 17:41:44.001861 Write leveling (Byte 1): 31 => 31
3989 17:41:44.005122 DramcWriteLeveling(PI) end<-----
3990 17:41:44.005221
3991 17:41:44.005310 ==
3992 17:41:44.008634 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 17:41:44.012214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 17:41:44.015234 ==
3995 17:41:44.015310 [Gating] SW mode calibration
3996 17:41:44.021802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3997 17:41:44.028823 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3998 17:41:44.031698 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 17:41:44.038571 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 17:41:44.041579 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 17:41:44.045150 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4002 17:41:44.052049 0 9 16 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
4003 17:41:44.055095 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4004 17:41:44.058250 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 17:41:44.064904 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 17:41:44.068590 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 17:41:44.071881 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 17:41:44.075366 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 17:41:44.081878 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 17:41:44.085407 0 10 16 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
4011 17:41:44.088239 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 17:41:44.094995 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 17:41:44.098340 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 17:41:44.101612 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 17:41:44.108459 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 17:41:44.112008 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 17:41:44.115284 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4018 17:41:44.121491 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 17:41:44.125059 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 17:41:44.128672 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 17:41:44.134903 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 17:41:44.138176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 17:41:44.141665 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 17:41:44.148179 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 17:41:44.151408 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 17:41:44.155055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 17:41:44.161489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 17:41:44.165352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 17:41:44.168519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 17:41:44.171912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 17:41:44.178214 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 17:41:44.181836 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 17:41:44.185469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 17:41:44.191859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4035 17:41:44.194864 Total UI for P1: 0, mck2ui 16
4036 17:41:44.198289 best dqsien dly found for B0: ( 0, 13, 14)
4037 17:41:44.202022 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 17:41:44.205383 Total UI for P1: 0, mck2ui 16
4039 17:41:44.208557 best dqsien dly found for B1: ( 0, 13, 16)
4040 17:41:44.212061 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4041 17:41:44.215345 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4042 17:41:44.215419
4043 17:41:44.218414 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4044 17:41:44.221685 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4045 17:41:44.225182 [Gating] SW calibration Done
4046 17:41:44.225255 ==
4047 17:41:44.228433 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 17:41:44.235272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 17:41:44.235347 ==
4050 17:41:44.235414 RX Vref Scan: 0
4051 17:41:44.235474
4052 17:41:44.238448 RX Vref 0 -> 0, step: 1
4053 17:41:44.238516
4054 17:41:44.241927 RX Delay -230 -> 252, step: 16
4055 17:41:44.245396 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4056 17:41:44.248267 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4057 17:41:44.251786 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4058 17:41:44.258392 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4059 17:41:44.262056 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 17:41:44.264924 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4061 17:41:44.268487 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4062 17:41:44.272164 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 17:41:44.278488 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4064 17:41:44.281555 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 17:41:44.285296 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4066 17:41:44.288575 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4067 17:41:44.295135 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4068 17:41:44.298581 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4069 17:41:44.301643 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4070 17:41:44.304835 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4071 17:41:44.304910 ==
4072 17:41:44.308362 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 17:41:44.315123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 17:41:44.315202 ==
4075 17:41:44.315265 DQS Delay:
4076 17:41:44.318356 DQS0 = 0, DQS1 = 0
4077 17:41:44.318427 DQM Delay:
4078 17:41:44.318486 DQM0 = 42, DQM1 = 35
4079 17:41:44.321776 DQ Delay:
4080 17:41:44.325112 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4081 17:41:44.328462 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4082 17:41:44.331939 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4083 17:41:44.335399 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4084 17:41:44.335473
4085 17:41:44.335533
4086 17:41:44.335590 ==
4087 17:41:44.338537 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 17:41:44.341671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 17:41:44.341741 ==
4090 17:41:44.341800
4091 17:41:44.341860
4092 17:41:44.345711 TX Vref Scan disable
4093 17:41:44.345778 == TX Byte 0 ==
4094 17:41:44.352044 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4095 17:41:44.355463 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4096 17:41:44.355533 == TX Byte 1 ==
4097 17:41:44.361853 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4098 17:41:44.365598 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4099 17:41:44.365668 ==
4100 17:41:44.368478 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 17:41:44.372011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 17:41:44.372080 ==
4103 17:41:44.372142
4104 17:41:44.372198
4105 17:41:44.374934 TX Vref Scan disable
4106 17:41:44.378675 == TX Byte 0 ==
4107 17:41:44.381508 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4108 17:41:44.385147 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4109 17:41:44.388278 == TX Byte 1 ==
4110 17:41:44.391851 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4111 17:41:44.395428 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4112 17:41:44.399120
4113 17:41:44.399194 [DATLAT]
4114 17:41:44.399254 Freq=600, CH0 RK0
4115 17:41:44.399312
4116 17:41:44.401865 DATLAT Default: 0x9
4117 17:41:44.401935 0, 0xFFFF, sum = 0
4118 17:41:44.405209 1, 0xFFFF, sum = 0
4119 17:41:44.405277 2, 0xFFFF, sum = 0
4120 17:41:44.408774 3, 0xFFFF, sum = 0
4121 17:41:44.408848 4, 0xFFFF, sum = 0
4122 17:41:44.411745 5, 0xFFFF, sum = 0
4123 17:41:44.411844 6, 0xFFFF, sum = 0
4124 17:41:44.415463 7, 0xFFFF, sum = 0
4125 17:41:44.415536 8, 0x0, sum = 1
4126 17:41:44.418768 9, 0x0, sum = 2
4127 17:41:44.418858 10, 0x0, sum = 3
4128 17:41:44.422267 11, 0x0, sum = 4
4129 17:41:44.422345 best_step = 9
4130 17:41:44.422405
4131 17:41:44.422462 ==
4132 17:41:44.425094 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 17:41:44.432098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 17:41:44.432173 ==
4135 17:41:44.432235 RX Vref Scan: 1
4136 17:41:44.432293
4137 17:41:44.435206 RX Vref 0 -> 0, step: 1
4138 17:41:44.435278
4139 17:41:44.438570 RX Delay -195 -> 252, step: 8
4140 17:41:44.438640
4141 17:41:44.441803 Set Vref, RX VrefLevel [Byte0]: 55
4142 17:41:44.445152 [Byte1]: 52
4143 17:41:44.445222
4144 17:41:44.448303 Final RX Vref Byte 0 = 55 to rank0
4145 17:41:44.451826 Final RX Vref Byte 1 = 52 to rank0
4146 17:41:44.455590 Final RX Vref Byte 0 = 55 to rank1
4147 17:41:44.458229 Final RX Vref Byte 1 = 52 to rank1==
4148 17:41:44.461636 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 17:41:44.465270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 17:41:44.465341 ==
4151 17:41:44.468356 DQS Delay:
4152 17:41:44.468423 DQS0 = 0, DQS1 = 0
4153 17:41:44.468487 DQM Delay:
4154 17:41:44.471954 DQM0 = 42, DQM1 = 34
4155 17:41:44.472019 DQ Delay:
4156 17:41:44.475401 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4157 17:41:44.478212 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4158 17:41:44.481982 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4159 17:41:44.485343 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4160 17:41:44.485414
4161 17:41:44.485473
4162 17:41:44.495016 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a19, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4163 17:41:44.495094 CH0 RK0: MR19=808, MR18=3A19
4164 17:41:44.501855 CH0_RK0: MR19=0x808, MR18=0x3A19, DQSOSC=398, MR23=63, INC=165, DEC=110
4165 17:41:44.501978
4166 17:41:44.505162 ----->DramcWriteLeveling(PI) begin...
4167 17:41:44.505241 ==
4168 17:41:44.508173 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 17:41:44.514864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 17:41:44.514951 ==
4171 17:41:44.518614 Write leveling (Byte 0): 30 => 30
4172 17:41:44.521933 Write leveling (Byte 1): 30 => 30
4173 17:41:44.522008 DramcWriteLeveling(PI) end<-----
4174 17:41:44.525155
4175 17:41:44.525226 ==
4176 17:41:44.528604 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 17:41:44.531721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 17:41:44.531793 ==
4179 17:41:44.534978 [Gating] SW mode calibration
4180 17:41:44.541688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 17:41:44.544804 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 17:41:44.551915 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 17:41:44.555118 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 17:41:44.558236 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 17:41:44.565014 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4186 17:41:44.568506 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 1)
4187 17:41:44.571919 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 17:41:44.578391 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 17:41:44.582081 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 17:41:44.584899 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 17:41:44.591987 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 17:41:44.595095 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 17:41:44.598585 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4194 17:41:44.602257 0 10 16 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
4195 17:41:44.608344 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 17:41:44.612130 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 17:41:44.615300 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 17:41:44.621841 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 17:41:44.625357 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 17:41:44.628263 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 17:41:44.635235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4202 17:41:44.638645 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4203 17:41:44.641957 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 17:41:44.648294 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 17:41:44.651610 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 17:41:44.655591 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 17:41:44.661691 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 17:41:44.665222 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 17:41:44.668452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 17:41:44.675484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 17:41:44.678435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 17:41:44.681979 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 17:41:44.685592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 17:41:44.692037 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 17:41:44.695210 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 17:41:44.698534 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 17:41:44.705212 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4218 17:41:44.708624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 17:41:44.712132 Total UI for P1: 0, mck2ui 16
4220 17:41:44.715680 best dqsien dly found for B0: ( 0, 13, 12)
4221 17:41:44.718466 Total UI for P1: 0, mck2ui 16
4222 17:41:44.721927 best dqsien dly found for B1: ( 0, 13, 12)
4223 17:41:44.725286 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4224 17:41:44.728466 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4225 17:41:44.728539
4226 17:41:44.732204 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4227 17:41:44.735289 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4228 17:41:44.738833 [Gating] SW calibration Done
4229 17:41:44.738913 ==
4230 17:41:44.742396 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 17:41:44.748507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 17:41:44.748589 ==
4233 17:41:44.748654 RX Vref Scan: 0
4234 17:41:44.748717
4235 17:41:44.751849 RX Vref 0 -> 0, step: 1
4236 17:41:44.751918
4237 17:41:44.755192 RX Delay -230 -> 252, step: 16
4238 17:41:44.758527 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4239 17:41:44.762153 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4240 17:41:44.765466 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4241 17:41:44.771838 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4242 17:41:44.775338 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4243 17:41:44.778391 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4244 17:41:44.782159 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4245 17:41:44.785481 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4246 17:41:44.791993 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4247 17:41:44.795006 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4248 17:41:44.798478 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 17:41:44.802157 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4250 17:41:44.808366 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 17:41:44.811974 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4252 17:41:44.815534 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4253 17:41:44.818387 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4254 17:41:44.818461 ==
4255 17:41:44.822251 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 17:41:44.828521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 17:41:44.828624 ==
4258 17:41:44.828738 DQS Delay:
4259 17:41:44.831964 DQS0 = 0, DQS1 = 0
4260 17:41:44.832139 DQM Delay:
4261 17:41:44.832209 DQM0 = 39, DQM1 = 33
4262 17:41:44.835298 DQ Delay:
4263 17:41:44.838498 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4264 17:41:44.841859 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4265 17:41:44.845358 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4266 17:41:44.848919 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4267 17:41:44.849000
4268 17:41:44.849063
4269 17:41:44.849123 ==
4270 17:41:44.851935 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 17:41:44.855270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 17:41:44.855342 ==
4273 17:41:44.855402
4274 17:41:44.855458
4275 17:41:44.859025 TX Vref Scan disable
4276 17:41:44.859097 == TX Byte 0 ==
4277 17:41:44.865451 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4278 17:41:44.868589 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4279 17:41:44.868679 == TX Byte 1 ==
4280 17:41:44.875581 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4281 17:41:44.879189 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4282 17:41:44.879266 ==
4283 17:41:44.882356 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 17:41:44.885914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 17:41:44.885985 ==
4286 17:41:44.886045
4287 17:41:44.886102
4288 17:41:44.889189 TX Vref Scan disable
4289 17:41:44.892378 == TX Byte 0 ==
4290 17:41:44.895482 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4291 17:41:44.898894 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4292 17:41:44.902432 == TX Byte 1 ==
4293 17:41:44.905454 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4294 17:41:44.908924 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4295 17:41:44.909002
4296 17:41:44.912388 [DATLAT]
4297 17:41:44.912460 Freq=600, CH0 RK1
4298 17:41:44.912524
4299 17:41:44.915576 DATLAT Default: 0x9
4300 17:41:44.915644 0, 0xFFFF, sum = 0
4301 17:41:44.918898 1, 0xFFFF, sum = 0
4302 17:41:44.918969 2, 0xFFFF, sum = 0
4303 17:41:44.922409 3, 0xFFFF, sum = 0
4304 17:41:44.922493 4, 0xFFFF, sum = 0
4305 17:41:44.925549 5, 0xFFFF, sum = 0
4306 17:41:44.925633 6, 0xFFFF, sum = 0
4307 17:41:44.928830 7, 0xFFFF, sum = 0
4308 17:41:44.928904 8, 0x0, sum = 1
4309 17:41:44.932568 9, 0x0, sum = 2
4310 17:41:44.932642 10, 0x0, sum = 3
4311 17:41:44.935794 11, 0x0, sum = 4
4312 17:41:44.935868 best_step = 9
4313 17:41:44.935944
4314 17:41:44.936002 ==
4315 17:41:44.938854 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 17:41:44.942057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 17:41:44.945413 ==
4318 17:41:44.945513 RX Vref Scan: 0
4319 17:41:44.945577
4320 17:41:44.948714 RX Vref 0 -> 0, step: 1
4321 17:41:44.948803
4322 17:41:44.952152 RX Delay -195 -> 252, step: 8
4323 17:41:44.955553 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4324 17:41:44.958878 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4325 17:41:44.965296 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4326 17:41:44.968736 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4327 17:41:44.972244 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4328 17:41:44.975914 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4329 17:41:44.978753 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4330 17:41:44.985282 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4331 17:41:44.989088 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4332 17:41:44.991998 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4333 17:41:44.995420 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4334 17:41:45.002005 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4335 17:41:45.005512 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4336 17:41:45.009036 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4337 17:41:45.012534 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4338 17:41:45.019247 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4339 17:41:45.019354 ==
4340 17:41:45.022142 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 17:41:45.025538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 17:41:45.025618 ==
4343 17:41:45.025679 DQS Delay:
4344 17:41:45.029045 DQS0 = 0, DQS1 = 0
4345 17:41:45.029121 DQM Delay:
4346 17:41:45.031949 DQM0 = 39, DQM1 = 32
4347 17:41:45.032020 DQ Delay:
4348 17:41:45.035424 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4349 17:41:45.039055 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4350 17:41:45.042367 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4351 17:41:45.045395 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4352 17:41:45.045471
4353 17:41:45.045533
4354 17:41:45.052453 [DQSOSCAuto] RK1, (LSB)MR18= 0x4526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4355 17:41:45.055743 CH0 RK1: MR19=808, MR18=4526
4356 17:41:45.062343 CH0_RK1: MR19=0x808, MR18=0x4526, DQSOSC=396, MR23=63, INC=167, DEC=111
4357 17:41:45.065798 [RxdqsGatingPostProcess] freq 600
4358 17:41:45.072064 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 17:41:45.075455 Pre-setting of DQS Precalculation
4360 17:41:45.079012 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 17:41:45.079090 ==
4362 17:41:45.082310 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 17:41:45.085799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 17:41:45.085874 ==
4365 17:41:45.092043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 17:41:45.099114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 17:41:45.101975 [CA 0] Center 35 (5~65) winsize 61
4368 17:41:45.105671 [CA 1] Center 35 (5~66) winsize 62
4369 17:41:45.109005 [CA 2] Center 33 (3~64) winsize 62
4370 17:41:45.112065 [CA 3] Center 33 (3~64) winsize 62
4371 17:41:45.115277 [CA 4] Center 34 (3~65) winsize 63
4372 17:41:45.119329 [CA 5] Center 33 (3~64) winsize 62
4373 17:41:45.119405
4374 17:41:45.122127 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 17:41:45.122199
4376 17:41:45.125670 [CATrainingPosCal] consider 1 rank data
4377 17:41:45.128813 u2DelayCellTimex100 = 270/100 ps
4378 17:41:45.132050 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4379 17:41:45.135561 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 17:41:45.138487 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4381 17:41:45.142020 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4382 17:41:45.145679 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4383 17:41:45.149113 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 17:41:45.149187
4385 17:41:45.155767 CA PerBit enable=1, Macro0, CA PI delay=33
4386 17:41:45.155840
4387 17:41:45.158809 [CBTSetCACLKResult] CA Dly = 33
4388 17:41:45.158879 CS Dly: 5 (0~36)
4389 17:41:45.158944 ==
4390 17:41:45.162356 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 17:41:45.165834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 17:41:45.165909 ==
4393 17:41:45.172245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 17:41:45.178651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4395 17:41:45.182344 [CA 0] Center 35 (5~66) winsize 62
4396 17:41:45.185490 [CA 1] Center 36 (6~66) winsize 61
4397 17:41:45.188764 [CA 2] Center 34 (4~65) winsize 62
4398 17:41:45.192346 [CA 3] Center 34 (3~65) winsize 63
4399 17:41:45.195149 [CA 4] Center 34 (3~65) winsize 63
4400 17:41:45.198686 [CA 5] Center 33 (3~64) winsize 62
4401 17:41:45.198815
4402 17:41:45.202075 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4403 17:41:45.202219
4404 17:41:45.205640 [CATrainingPosCal] consider 2 rank data
4405 17:41:45.209224 u2DelayCellTimex100 = 270/100 ps
4406 17:41:45.212437 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4407 17:41:45.215848 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 17:41:45.219165 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4409 17:41:45.222209 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 17:41:45.225465 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4411 17:41:45.228521 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 17:41:45.228603
4413 17:41:45.235638 CA PerBit enable=1, Macro0, CA PI delay=33
4414 17:41:45.235717
4415 17:41:45.239183 [CBTSetCACLKResult] CA Dly = 33
4416 17:41:45.239261 CS Dly: 4 (0~35)
4417 17:41:45.239322
4418 17:41:45.242141 ----->DramcWriteLeveling(PI) begin...
4419 17:41:45.242218 ==
4420 17:41:45.245666 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 17:41:45.248510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 17:41:45.248588 ==
4423 17:41:45.252198 Write leveling (Byte 0): 29 => 29
4424 17:41:45.255791 Write leveling (Byte 1): 29 => 29
4425 17:41:45.258580 DramcWriteLeveling(PI) end<-----
4426 17:41:45.258651
4427 17:41:45.258711 ==
4428 17:41:45.262278 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 17:41:45.265355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 17:41:45.268751 ==
4431 17:41:45.268830 [Gating] SW mode calibration
4432 17:41:45.278942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 17:41:45.282422 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 17:41:45.285542 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4435 17:41:45.292643 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 17:41:45.295306 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 17:41:45.298964 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4438 17:41:45.306151 0 9 16 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
4439 17:41:45.308938 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 17:41:45.312664 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 17:41:45.318671 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 17:41:45.322254 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 17:41:45.325810 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 17:41:45.332222 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 17:41:45.335545 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (1 1) (0 0)
4446 17:41:45.339198 0 10 16 | B1->B0 | 3e3e 4040 | 0 0 | (0 0) (0 0)
4447 17:41:45.342064 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 17:41:45.349214 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 17:41:45.352354 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 17:41:45.355536 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 17:41:45.362922 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 17:41:45.365691 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 17:41:45.369457 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4454 17:41:45.376026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 17:41:45.379007 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 17:41:45.382381 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 17:41:45.389149 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 17:41:45.392729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 17:41:45.395951 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 17:41:45.402390 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 17:41:45.405779 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 17:41:45.409131 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 17:41:45.415639 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 17:41:45.419349 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 17:41:45.422454 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 17:41:45.428830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 17:41:45.432657 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 17:41:45.436094 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 17:41:45.439230 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4470 17:41:45.445479 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4471 17:41:45.448802 Total UI for P1: 0, mck2ui 16
4472 17:41:45.452385 best dqsien dly found for B1: ( 0, 13, 14)
4473 17:41:45.455562 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 17:41:45.459580 Total UI for P1: 0, mck2ui 16
4475 17:41:45.462298 best dqsien dly found for B0: ( 0, 13, 14)
4476 17:41:45.465702 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4477 17:41:45.468808 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4478 17:41:45.468881
4479 17:41:45.472524 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4480 17:41:45.475524 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4481 17:41:45.479167 [Gating] SW calibration Done
4482 17:41:45.479238 ==
4483 17:41:45.482450 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 17:41:45.489007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 17:41:45.489108 ==
4486 17:41:45.489205 RX Vref Scan: 0
4487 17:41:45.489292
4488 17:41:45.492419 RX Vref 0 -> 0, step: 1
4489 17:41:45.492497
4490 17:41:45.495545 RX Delay -230 -> 252, step: 16
4491 17:41:45.499037 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4492 17:41:45.502810 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4493 17:41:45.505340 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4494 17:41:45.512705 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4495 17:41:45.515795 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4496 17:41:45.518831 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4497 17:41:45.522298 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4498 17:41:45.525396 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4499 17:41:45.531986 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 17:41:45.535361 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4501 17:41:45.538918 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4502 17:41:45.542353 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4503 17:41:45.549551 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4504 17:41:45.552545 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4505 17:41:45.555410 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4506 17:41:45.558864 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4507 17:41:45.558964 ==
4508 17:41:45.562491 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 17:41:45.569232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 17:41:45.569337 ==
4511 17:41:45.569417 DQS Delay:
4512 17:41:45.572916 DQS0 = 0, DQS1 = 0
4513 17:41:45.573096 DQM Delay:
4514 17:41:45.573187 DQM0 = 45, DQM1 = 35
4515 17:41:45.575733 DQ Delay:
4516 17:41:45.579375 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4517 17:41:45.582444 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4518 17:41:45.585815 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4519 17:41:45.589828 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4520 17:41:45.590046
4521 17:41:45.590165
4522 17:41:45.590271 ==
4523 17:41:45.592382 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 17:41:45.596180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 17:41:45.596355 ==
4526 17:41:45.596491
4527 17:41:45.596617
4528 17:41:45.599755 TX Vref Scan disable
4529 17:41:45.600012 == TX Byte 0 ==
4530 17:41:45.606474 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4531 17:41:45.609502 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4532 17:41:45.609766 == TX Byte 1 ==
4533 17:41:45.616298 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 17:41:45.619315 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 17:41:45.619907 ==
4536 17:41:45.622642 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 17:41:45.625966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 17:41:45.626452 ==
4539 17:41:45.627020
4540 17:41:45.627438
4541 17:41:45.629601 TX Vref Scan disable
4542 17:41:45.632971 == TX Byte 0 ==
4543 17:41:45.636562 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 17:41:45.639679 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 17:41:45.642926 == TX Byte 1 ==
4546 17:41:45.646214 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4547 17:41:45.649782 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4548 17:41:45.650300
4549 17:41:45.653103 [DATLAT]
4550 17:41:45.653683 Freq=600, CH1 RK0
4551 17:41:45.654249
4552 17:41:45.655981 DATLAT Default: 0x9
4553 17:41:45.656401 0, 0xFFFF, sum = 0
4554 17:41:45.659929 1, 0xFFFF, sum = 0
4555 17:41:45.660355 2, 0xFFFF, sum = 0
4556 17:41:45.662804 3, 0xFFFF, sum = 0
4557 17:41:45.663235 4, 0xFFFF, sum = 0
4558 17:41:45.666355 5, 0xFFFF, sum = 0
4559 17:41:45.666937 6, 0xFFFF, sum = 0
4560 17:41:45.669642 7, 0xFFFF, sum = 0
4561 17:41:45.670065 8, 0x0, sum = 1
4562 17:41:45.673593 9, 0x0, sum = 2
4563 17:41:45.674126 10, 0x0, sum = 3
4564 17:41:45.676607 11, 0x0, sum = 4
4565 17:41:45.677130 best_step = 9
4566 17:41:45.677468
4567 17:41:45.677775 ==
4568 17:41:45.679584 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 17:41:45.683050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 17:41:45.686671 ==
4571 17:41:45.687236 RX Vref Scan: 1
4572 17:41:45.687572
4573 17:41:45.690196 RX Vref 0 -> 0, step: 1
4574 17:41:45.690717
4575 17:41:45.692794 RX Delay -195 -> 252, step: 8
4576 17:41:45.693212
4577 17:41:45.696840 Set Vref, RX VrefLevel [Byte0]: 57
4578 17:41:45.700228 [Byte1]: 46
4579 17:41:45.700744
4580 17:41:45.702819 Final RX Vref Byte 0 = 57 to rank0
4581 17:41:45.705965 Final RX Vref Byte 1 = 46 to rank0
4582 17:41:45.709493 Final RX Vref Byte 0 = 57 to rank1
4583 17:41:45.713183 Final RX Vref Byte 1 = 46 to rank1==
4584 17:41:45.716153 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 17:41:45.719999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 17:41:45.720516 ==
4587 17:41:45.722830 DQS Delay:
4588 17:41:45.723248 DQS0 = 0, DQS1 = 0
4589 17:41:45.723598 DQM Delay:
4590 17:41:45.726239 DQM0 = 41, DQM1 = 32
4591 17:41:45.726846 DQ Delay:
4592 17:41:45.729702 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4593 17:41:45.733186 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4594 17:41:45.736182 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4595 17:41:45.739457 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =36
4596 17:41:45.739874
4597 17:41:45.740199
4598 17:41:45.749707 [DQSOSCAuto] RK0, (LSB)MR18= 0x4007, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4599 17:41:45.750301 CH1 RK0: MR19=808, MR18=4007
4600 17:41:45.756713 CH1_RK0: MR19=0x808, MR18=0x4007, DQSOSC=397, MR23=63, INC=166, DEC=110
4601 17:41:45.757293
4602 17:41:45.759501 ----->DramcWriteLeveling(PI) begin...
4603 17:41:45.759988 ==
4604 17:41:45.762908 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 17:41:45.769713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 17:41:45.770194 ==
4607 17:41:45.772901 Write leveling (Byte 0): 27 => 27
4608 17:41:45.776239 Write leveling (Byte 1): 29 => 29
4609 17:41:45.776706 DramcWriteLeveling(PI) end<-----
4610 17:41:45.777071
4611 17:41:45.779841 ==
4612 17:41:45.782774 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 17:41:45.786205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 17:41:45.786627 ==
4615 17:41:45.789375 [Gating] SW mode calibration
4616 17:41:45.796505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 17:41:45.799328 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 17:41:45.806623 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4619 17:41:45.809663 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 17:41:45.813091 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4621 17:41:45.819994 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (1 0)
4622 17:41:45.823356 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4623 17:41:45.826543 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 17:41:45.832880 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4625 17:41:45.836445 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 17:41:45.839710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 17:41:45.843124 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 17:41:45.849373 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4629 17:41:45.853090 0 10 12 | B1->B0 | 3232 3f3f | 0 0 | (1 1) (0 0)
4630 17:41:45.856933 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4631 17:41:45.862960 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 17:41:45.866302 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 17:41:45.869467 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 17:41:45.876417 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 17:41:45.879670 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 17:41:45.883114 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 17:41:45.889851 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4638 17:41:45.892917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 17:41:45.896408 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 17:41:45.902794 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 17:41:45.906358 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 17:41:45.909318 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 17:41:45.916349 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 17:41:45.919420 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 17:41:45.922795 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 17:41:45.929822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 17:41:45.932861 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 17:41:45.936039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 17:41:45.939255 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 17:41:45.945657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 17:41:45.949228 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 17:41:45.952477 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 17:41:45.958985 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4654 17:41:45.962412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 17:41:45.965749 Total UI for P1: 0, mck2ui 16
4656 17:41:45.969079 best dqsien dly found for B0: ( 0, 13, 12)
4657 17:41:45.972479 Total UI for P1: 0, mck2ui 16
4658 17:41:45.975912 best dqsien dly found for B1: ( 0, 13, 14)
4659 17:41:45.978942 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4660 17:41:45.982988 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4661 17:41:45.983150
4662 17:41:45.985680 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 17:41:45.989231 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4664 17:41:45.992149 [Gating] SW calibration Done
4665 17:41:45.992313 ==
4666 17:41:45.995687 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 17:41:46.002108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 17:41:46.002242 ==
4669 17:41:46.002309 RX Vref Scan: 0
4670 17:41:46.002370
4671 17:41:46.005575 RX Vref 0 -> 0, step: 1
4672 17:41:46.005658
4673 17:41:46.009280 RX Delay -230 -> 252, step: 16
4674 17:41:46.012631 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4675 17:41:46.016151 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4676 17:41:46.019129 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4677 17:41:46.026169 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4678 17:41:46.029163 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4679 17:41:46.032704 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4680 17:41:46.036104 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4681 17:41:46.039715 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4682 17:41:46.046036 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4683 17:41:46.049317 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4684 17:41:46.052730 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4685 17:41:46.056163 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4686 17:41:46.062967 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4687 17:41:46.066013 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4688 17:41:46.069496 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4689 17:41:46.072549 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4690 17:41:46.072872 ==
4691 17:41:46.076124 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 17:41:46.082519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 17:41:46.082840 ==
4694 17:41:46.083042 DQS Delay:
4695 17:41:46.085919 DQS0 = 0, DQS1 = 0
4696 17:41:46.086402 DQM Delay:
4697 17:41:46.086654 DQM0 = 41, DQM1 = 36
4698 17:41:46.088872 DQ Delay:
4699 17:41:46.092493 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4700 17:41:46.096022 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4701 17:41:46.099197 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4702 17:41:46.102503 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4703 17:41:46.102629
4704 17:41:46.102742
4705 17:41:46.102813 ==
4706 17:41:46.106182 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 17:41:46.108946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 17:41:46.109037 ==
4709 17:41:46.109109
4710 17:41:46.109175
4711 17:41:46.112346 TX Vref Scan disable
4712 17:41:46.112437 == TX Byte 0 ==
4713 17:41:46.118947 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4714 17:41:46.122363 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4715 17:41:46.122454 == TX Byte 1 ==
4716 17:41:46.129204 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4717 17:41:46.132527 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4718 17:41:46.132625 ==
4719 17:41:46.136383 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 17:41:46.139246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 17:41:46.139353 ==
4722 17:41:46.139437
4723 17:41:46.139514
4724 17:41:46.142760 TX Vref Scan disable
4725 17:41:46.145885 == TX Byte 0 ==
4726 17:41:46.149186 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4727 17:41:46.155508 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4728 17:41:46.155719 == TX Byte 1 ==
4729 17:41:46.159066 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4730 17:41:46.162607 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4731 17:41:46.165913
4732 17:41:46.166113 [DATLAT]
4733 17:41:46.166295 Freq=600, CH1 RK1
4734 17:41:46.166441
4735 17:41:46.169327 DATLAT Default: 0x9
4736 17:41:46.169521 0, 0xFFFF, sum = 0
4737 17:41:46.172480 1, 0xFFFF, sum = 0
4738 17:41:46.172675 2, 0xFFFF, sum = 0
4739 17:41:46.176296 3, 0xFFFF, sum = 0
4740 17:41:46.176494 4, 0xFFFF, sum = 0
4741 17:41:46.179530 5, 0xFFFF, sum = 0
4742 17:41:46.182611 6, 0xFFFF, sum = 0
4743 17:41:46.182838 7, 0xFFFF, sum = 0
4744 17:41:46.182995 8, 0x0, sum = 1
4745 17:41:46.185788 9, 0x0, sum = 2
4746 17:41:46.186005 10, 0x0, sum = 3
4747 17:41:46.189552 11, 0x0, sum = 4
4748 17:41:46.189749 best_step = 9
4749 17:41:46.189900
4750 17:41:46.190038 ==
4751 17:41:46.192492 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 17:41:46.199009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 17:41:46.199229 ==
4754 17:41:46.199376 RX Vref Scan: 0
4755 17:41:46.199542
4756 17:41:46.202268 RX Vref 0 -> 0, step: 1
4757 17:41:46.202435
4758 17:41:46.205612 RX Delay -179 -> 252, step: 8
4759 17:41:46.209257 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4760 17:41:46.215613 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4761 17:41:46.219028 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4762 17:41:46.222802 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4763 17:41:46.225627 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4764 17:41:46.229281 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4765 17:41:46.235535 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4766 17:41:46.239087 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4767 17:41:46.242547 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4768 17:41:46.246158 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4769 17:41:46.249423 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4770 17:41:46.255763 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4771 17:41:46.259110 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4772 17:41:46.262283 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4773 17:41:46.265637 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4774 17:41:46.272532 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4775 17:41:46.272679 ==
4776 17:41:46.275619 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 17:41:46.279700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 17:41:46.279793 ==
4779 17:41:46.279861 DQS Delay:
4780 17:41:46.282632 DQS0 = 0, DQS1 = 0
4781 17:41:46.282751 DQM Delay:
4782 17:41:46.286101 DQM0 = 38, DQM1 = 33
4783 17:41:46.286185 DQ Delay:
4784 17:41:46.289545 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4785 17:41:46.292659 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4786 17:41:46.295882 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4787 17:41:46.299763 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4788 17:41:46.299930
4789 17:41:46.300009
4790 17:41:46.306212 [DQSOSCAuto] RK1, (LSB)MR18= 0x3242, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4791 17:41:46.309933 CH1 RK1: MR19=808, MR18=3242
4792 17:41:46.316401 CH1_RK1: MR19=0x808, MR18=0x3242, DQSOSC=397, MR23=63, INC=166, DEC=110
4793 17:41:46.319620 [RxdqsGatingPostProcess] freq 600
4794 17:41:46.326033 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4795 17:41:46.329675 Pre-setting of DQS Precalculation
4796 17:41:46.332858 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4797 17:41:46.339225 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4798 17:41:46.346539 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4799 17:41:46.346890
4800 17:41:46.347063
4801 17:41:46.349659 [Calibration Summary] 1200 Mbps
4802 17:41:46.353067 CH 0, Rank 0
4803 17:41:46.353382 SW Impedance : PASS
4804 17:41:46.355801 DUTY Scan : NO K
4805 17:41:46.359285 ZQ Calibration : PASS
4806 17:41:46.359560 Jitter Meter : NO K
4807 17:41:46.362902 CBT Training : PASS
4808 17:41:46.363256 Write leveling : PASS
4809 17:41:46.365926 RX DQS gating : PASS
4810 17:41:46.369179 RX DQ/DQS(RDDQC) : PASS
4811 17:41:46.369619 TX DQ/DQS : PASS
4812 17:41:46.372645 RX DATLAT : PASS
4813 17:41:46.376060 RX DQ/DQS(Engine): PASS
4814 17:41:46.376479 TX OE : NO K
4815 17:41:46.379213 All Pass.
4816 17:41:46.379628
4817 17:41:46.379957 CH 0, Rank 1
4818 17:41:46.382474 SW Impedance : PASS
4819 17:41:46.382940 DUTY Scan : NO K
4820 17:41:46.386205 ZQ Calibration : PASS
4821 17:41:46.389328 Jitter Meter : NO K
4822 17:41:46.389750 CBT Training : PASS
4823 17:41:46.392561 Write leveling : PASS
4824 17:41:46.396241 RX DQS gating : PASS
4825 17:41:46.396740 RX DQ/DQS(RDDQC) : PASS
4826 17:41:46.399458 TX DQ/DQS : PASS
4827 17:41:46.402589 RX DATLAT : PASS
4828 17:41:46.402932 RX DQ/DQS(Engine): PASS
4829 17:41:46.405882 TX OE : NO K
4830 17:41:46.406129 All Pass.
4831 17:41:46.406324
4832 17:41:46.408860 CH 1, Rank 0
4833 17:41:46.409086 SW Impedance : PASS
4834 17:41:46.412259 DUTY Scan : NO K
4835 17:41:46.415894 ZQ Calibration : PASS
4836 17:41:46.416064 Jitter Meter : NO K
4837 17:41:46.418853 CBT Training : PASS
4838 17:41:46.419028 Write leveling : PASS
4839 17:41:46.422078 RX DQS gating : PASS
4840 17:41:46.425742 RX DQ/DQS(RDDQC) : PASS
4841 17:41:46.425902 TX DQ/DQS : PASS
4842 17:41:46.429202 RX DATLAT : PASS
4843 17:41:46.432432 RX DQ/DQS(Engine): PASS
4844 17:41:46.432570 TX OE : NO K
4845 17:41:46.435718 All Pass.
4846 17:41:46.435847
4847 17:41:46.435949 CH 1, Rank 1
4848 17:41:46.438576 SW Impedance : PASS
4849 17:41:46.438808 DUTY Scan : NO K
4850 17:41:46.442129 ZQ Calibration : PASS
4851 17:41:46.445730 Jitter Meter : NO K
4852 17:41:46.445919 CBT Training : PASS
4853 17:41:46.448743 Write leveling : PASS
4854 17:41:46.452376 RX DQS gating : PASS
4855 17:41:46.452587 RX DQ/DQS(RDDQC) : PASS
4856 17:41:46.455783 TX DQ/DQS : PASS
4857 17:41:46.458872 RX DATLAT : PASS
4858 17:41:46.459017 RX DQ/DQS(Engine): PASS
4859 17:41:46.462283 TX OE : NO K
4860 17:41:46.462457 All Pass.
4861 17:41:46.462605
4862 17:41:46.465702 DramC Write-DBI off
4863 17:41:46.468632 PER_BANK_REFRESH: Hybrid Mode
4864 17:41:46.468857 TX_TRACKING: ON
4865 17:41:46.479133 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4866 17:41:46.482137 [FAST_K] Save calibration result to emmc
4867 17:41:46.485604 dramc_set_vcore_voltage set vcore to 662500
4868 17:41:46.485846 Read voltage for 933, 3
4869 17:41:46.489027 Vio18 = 0
4870 17:41:46.489245 Vcore = 662500
4871 17:41:46.489395 Vdram = 0
4872 17:41:46.492279 Vddq = 0
4873 17:41:46.492446 Vmddr = 0
4874 17:41:46.495695 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4875 17:41:46.502464 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4876 17:41:46.506163 MEM_TYPE=3, freq_sel=17
4877 17:41:46.509219 sv_algorithm_assistance_LP4_1600
4878 17:41:46.512606 ============ PULL DRAM RESETB DOWN ============
4879 17:41:46.515883 ========== PULL DRAM RESETB DOWN end =========
4880 17:41:46.522674 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 17:41:46.525678 ===================================
4882 17:41:46.526097 LPDDR4 DRAM CONFIGURATION
4883 17:41:46.529790 ===================================
4884 17:41:46.532563 EX_ROW_EN[0] = 0x0
4885 17:41:46.533038 EX_ROW_EN[1] = 0x0
4886 17:41:46.536223 LP4Y_EN = 0x0
4887 17:41:46.536784 WORK_FSP = 0x0
4888 17:41:46.539425 WL = 0x3
4889 17:41:46.539894 RL = 0x3
4890 17:41:46.542447 BL = 0x2
4891 17:41:46.546367 RPST = 0x0
4892 17:41:46.546982 RD_PRE = 0x0
4893 17:41:46.549288 WR_PRE = 0x1
4894 17:41:46.549756 WR_PST = 0x0
4895 17:41:46.552600 DBI_WR = 0x0
4896 17:41:46.553058 DBI_RD = 0x0
4897 17:41:46.556162 OTF = 0x1
4898 17:41:46.559060 ===================================
4899 17:41:46.562484 ===================================
4900 17:41:46.562961 ANA top config
4901 17:41:46.566279 ===================================
4902 17:41:46.569495 DLL_ASYNC_EN = 0
4903 17:41:46.573163 ALL_SLAVE_EN = 1
4904 17:41:46.573686 NEW_RANK_MODE = 1
4905 17:41:46.576601 DLL_IDLE_MODE = 1
4906 17:41:46.579358 LP45_APHY_COMB_EN = 1
4907 17:41:46.583093 TX_ODT_DIS = 1
4908 17:41:46.583618 NEW_8X_MODE = 1
4909 17:41:46.586633 ===================================
4910 17:41:46.589464 ===================================
4911 17:41:46.593135 data_rate = 1866
4912 17:41:46.596226 CKR = 1
4913 17:41:46.599961 DQ_P2S_RATIO = 8
4914 17:41:46.603524 ===================================
4915 17:41:46.606574 CA_P2S_RATIO = 8
4916 17:41:46.609928 DQ_CA_OPEN = 0
4917 17:41:46.610485 DQ_SEMI_OPEN = 0
4918 17:41:46.613055 CA_SEMI_OPEN = 0
4919 17:41:46.616116 CA_FULL_RATE = 0
4920 17:41:46.619769 DQ_CKDIV4_EN = 1
4921 17:41:46.623323 CA_CKDIV4_EN = 1
4922 17:41:46.623883 CA_PREDIV_EN = 0
4923 17:41:46.626269 PH8_DLY = 0
4924 17:41:46.630022 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4925 17:41:46.632943 DQ_AAMCK_DIV = 4
4926 17:41:46.636160 CA_AAMCK_DIV = 4
4927 17:41:46.639401 CA_ADMCK_DIV = 4
4928 17:41:46.639870 DQ_TRACK_CA_EN = 0
4929 17:41:46.642788 CA_PICK = 933
4930 17:41:46.646028 CA_MCKIO = 933
4931 17:41:46.649694 MCKIO_SEMI = 0
4932 17:41:46.653264 PLL_FREQ = 3732
4933 17:41:46.656367 DQ_UI_PI_RATIO = 32
4934 17:41:46.660045 CA_UI_PI_RATIO = 0
4935 17:41:46.663204 ===================================
4936 17:41:46.666703 ===================================
4937 17:41:46.667268 memory_type:LPDDR4
4938 17:41:46.669558 GP_NUM : 10
4939 17:41:46.669985 SRAM_EN : 1
4940 17:41:46.673191 MD32_EN : 0
4941 17:41:46.676338 ===================================
4942 17:41:46.679602 [ANA_INIT] >>>>>>>>>>>>>>
4943 17:41:46.682691 <<<<<< [CONFIGURE PHASE]: ANA_TX
4944 17:41:46.686035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4945 17:41:46.689681 ===================================
4946 17:41:46.690106 data_rate = 1866,PCW = 0X8f00
4947 17:41:46.693303 ===================================
4948 17:41:46.696383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4949 17:41:46.703108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 17:41:46.709654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 17:41:46.713330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4952 17:41:46.716107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4953 17:41:46.719930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4954 17:41:46.723236 [ANA_INIT] flow start
4955 17:41:46.726208 [ANA_INIT] PLL >>>>>>>>
4956 17:41:46.726634 [ANA_INIT] PLL <<<<<<<<
4957 17:41:46.729952 [ANA_INIT] MIDPI >>>>>>>>
4958 17:41:46.733002 [ANA_INIT] MIDPI <<<<<<<<
4959 17:41:46.733428 [ANA_INIT] DLL >>>>>>>>
4960 17:41:46.736604 [ANA_INIT] flow end
4961 17:41:46.739617 ============ LP4 DIFF to SE enter ============
4962 17:41:46.743492 ============ LP4 DIFF to SE exit ============
4963 17:41:46.747288 [ANA_INIT] <<<<<<<<<<<<<
4964 17:41:46.749843 [Flow] Enable top DCM control >>>>>
4965 17:41:46.753232 [Flow] Enable top DCM control <<<<<
4966 17:41:46.756495 Enable DLL master slave shuffle
4967 17:41:46.762964 ==============================================================
4968 17:41:46.763560 Gating Mode config
4969 17:41:46.769738 ==============================================================
4970 17:41:46.770166 Config description:
4971 17:41:46.779699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4972 17:41:46.786772 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4973 17:41:46.793028 SELPH_MODE 0: By rank 1: By Phase
4974 17:41:46.796674 ==============================================================
4975 17:41:46.799865 GAT_TRACK_EN = 1
4976 17:41:46.803278 RX_GATING_MODE = 2
4977 17:41:46.806847 RX_GATING_TRACK_MODE = 2
4978 17:41:46.809812 SELPH_MODE = 1
4979 17:41:46.813014 PICG_EARLY_EN = 1
4980 17:41:46.816283 VALID_LAT_VALUE = 1
4981 17:41:46.819422 ==============================================================
4982 17:41:46.822947 Enter into Gating configuration >>>>
4983 17:41:46.826576 Exit from Gating configuration <<<<
4984 17:41:46.829909 Enter into DVFS_PRE_config >>>>>
4985 17:41:46.842903 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4986 17:41:46.846473 Exit from DVFS_PRE_config <<<<<
4987 17:41:46.850161 Enter into PICG configuration >>>>
4988 17:41:46.850718 Exit from PICG configuration <<<<
4989 17:41:46.853734 [RX_INPUT] configuration >>>>>
4990 17:41:46.856158 [RX_INPUT] configuration <<<<<
4991 17:41:46.863169 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4992 17:41:46.866136 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4993 17:41:46.873333 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 17:41:46.880202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 17:41:46.886348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 17:41:46.892956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 17:41:46.896558 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4998 17:41:46.899443 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4999 17:41:46.903284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5000 17:41:46.909574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5001 17:41:46.912915 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5002 17:41:46.916656 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 17:41:46.919935 ===================================
5004 17:41:46.923057 LPDDR4 DRAM CONFIGURATION
5005 17:41:46.927092 ===================================
5006 17:41:46.927773 EX_ROW_EN[0] = 0x0
5007 17:41:46.930235 EX_ROW_EN[1] = 0x0
5008 17:41:46.933084 LP4Y_EN = 0x0
5009 17:41:46.933505 WORK_FSP = 0x0
5010 17:41:46.936853 WL = 0x3
5011 17:41:46.937382 RL = 0x3
5012 17:41:46.940138 BL = 0x2
5013 17:41:46.940561 RPST = 0x0
5014 17:41:46.942972 RD_PRE = 0x0
5015 17:41:46.943393 WR_PRE = 0x1
5016 17:41:46.946320 WR_PST = 0x0
5017 17:41:46.946902 DBI_WR = 0x0
5018 17:41:46.949765 DBI_RD = 0x0
5019 17:41:46.950188 OTF = 0x1
5020 17:41:46.952776 ===================================
5021 17:41:46.956482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5022 17:41:46.963192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5023 17:41:46.966446 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 17:41:46.969726 ===================================
5025 17:41:46.973376 LPDDR4 DRAM CONFIGURATION
5026 17:41:46.976368 ===================================
5027 17:41:46.976790 EX_ROW_EN[0] = 0x10
5028 17:41:46.979669 EX_ROW_EN[1] = 0x0
5029 17:41:46.980097 LP4Y_EN = 0x0
5030 17:41:46.982952 WORK_FSP = 0x0
5031 17:41:46.983385 WL = 0x3
5032 17:41:46.986226 RL = 0x3
5033 17:41:46.989774 BL = 0x2
5034 17:41:46.990204 RPST = 0x0
5035 17:41:46.992660 RD_PRE = 0x0
5036 17:41:46.993043 WR_PRE = 0x1
5037 17:41:46.996539 WR_PST = 0x0
5038 17:41:46.996966 DBI_WR = 0x0
5039 17:41:46.999498 DBI_RD = 0x0
5040 17:41:46.999942 OTF = 0x1
5041 17:41:47.002839 ===================================
5042 17:41:47.009946 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5043 17:41:47.013245 nWR fixed to 30
5044 17:41:47.016748 [ModeRegInit_LP4] CH0 RK0
5045 17:41:47.017219 [ModeRegInit_LP4] CH0 RK1
5046 17:41:47.019859 [ModeRegInit_LP4] CH1 RK0
5047 17:41:47.023135 [ModeRegInit_LP4] CH1 RK1
5048 17:41:47.023538 match AC timing 9
5049 17:41:47.030355 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5050 17:41:47.033119 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5051 17:41:47.036412 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5052 17:41:47.043398 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5053 17:41:47.047033 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5054 17:41:47.047243 ==
5055 17:41:47.049809 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 17:41:47.053291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 17:41:47.053461 ==
5058 17:41:47.059591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 17:41:47.066314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5060 17:41:47.069751 [CA 0] Center 38 (8~69) winsize 62
5061 17:41:47.073120 [CA 1] Center 38 (8~68) winsize 61
5062 17:41:47.077023 [CA 2] Center 35 (5~66) winsize 62
5063 17:41:47.079905 [CA 3] Center 35 (4~66) winsize 63
5064 17:41:47.083123 [CA 4] Center 34 (4~64) winsize 61
5065 17:41:47.086506 [CA 5] Center 34 (4~64) winsize 61
5066 17:41:47.086637
5067 17:41:47.090067 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5068 17:41:47.090318
5069 17:41:47.093625 [CATrainingPosCal] consider 1 rank data
5070 17:41:47.096677 u2DelayCellTimex100 = 270/100 ps
5071 17:41:47.100054 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5072 17:41:47.103078 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5073 17:41:47.106466 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5074 17:41:47.110327 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5075 17:41:47.113367 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5076 17:41:47.116845 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5077 17:41:47.117243
5078 17:41:47.119931 CA PerBit enable=1, Macro0, CA PI delay=34
5079 17:41:47.123383
5080 17:41:47.123818 [CBTSetCACLKResult] CA Dly = 34
5081 17:41:47.126809 CS Dly: 6 (0~37)
5082 17:41:47.127443 ==
5083 17:41:47.130491 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 17:41:47.134297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 17:41:47.134763 ==
5086 17:41:47.140730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 17:41:47.147099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5088 17:41:47.150476 [CA 0] Center 38 (8~69) winsize 62
5089 17:41:47.153284 [CA 1] Center 38 (7~69) winsize 63
5090 17:41:47.157130 [CA 2] Center 35 (5~66) winsize 62
5091 17:41:47.160517 [CA 3] Center 34 (4~65) winsize 62
5092 17:41:47.163539 [CA 4] Center 34 (3~65) winsize 63
5093 17:41:47.167215 [CA 5] Center 33 (3~64) winsize 62
5094 17:41:47.167864
5095 17:41:47.170381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5096 17:41:47.170984
5097 17:41:47.174003 [CATrainingPosCal] consider 2 rank data
5098 17:41:47.176931 u2DelayCellTimex100 = 270/100 ps
5099 17:41:47.180528 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5100 17:41:47.183453 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5101 17:41:47.187314 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5102 17:41:47.190959 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5103 17:41:47.193895 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5104 17:41:47.196986 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5105 17:41:47.197545
5106 17:41:47.200695 CA PerBit enable=1, Macro0, CA PI delay=34
5107 17:41:47.201209
5108 17:41:47.203926 [CBTSetCACLKResult] CA Dly = 34
5109 17:41:47.206892 CS Dly: 7 (0~39)
5110 17:41:47.207319
5111 17:41:47.210394 ----->DramcWriteLeveling(PI) begin...
5112 17:41:47.210872 ==
5113 17:41:47.213951 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 17:41:47.216838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 17:41:47.217428 ==
5116 17:41:47.220860 Write leveling (Byte 0): 33 => 33
5117 17:41:47.223756 Write leveling (Byte 1): 25 => 25
5118 17:41:47.227172 DramcWriteLeveling(PI) end<-----
5119 17:41:47.227598
5120 17:41:47.227930 ==
5121 17:41:47.230201 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 17:41:47.233573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 17:41:47.233999 ==
5124 17:41:47.237148 [Gating] SW mode calibration
5125 17:41:47.243548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5126 17:41:47.250811 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5127 17:41:47.254139 0 14 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5128 17:41:47.260976 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5129 17:41:47.263621 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 17:41:47.267258 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 17:41:47.270701 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 17:41:47.276533 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 17:41:47.280317 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 17:41:47.283620 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5135 17:41:47.290666 0 15 0 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 0)
5136 17:41:47.294213 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5137 17:41:47.297059 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 17:41:47.303987 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 17:41:47.307039 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 17:41:47.310168 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 17:41:47.317159 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 17:41:47.320593 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5143 17:41:47.323844 1 0 0 | B1->B0 | 3030 3e3e | 1 0 | (0 0) (0 0)
5144 17:41:47.330419 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5145 17:41:47.333807 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 17:41:47.337180 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 17:41:47.343926 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 17:41:47.347407 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 17:41:47.350687 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 17:41:47.354283 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5151 17:41:47.361033 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5152 17:41:47.364354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5153 17:41:47.367798 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 17:41:47.374118 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 17:41:47.377190 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 17:41:47.381022 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 17:41:47.387434 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 17:41:47.390687 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 17:41:47.393926 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 17:41:47.400725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 17:41:47.404241 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 17:41:47.407055 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 17:41:47.413773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 17:41:47.417175 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 17:41:47.420963 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 17:41:47.427628 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5167 17:41:47.430341 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5168 17:41:47.434063 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 17:41:47.437578 Total UI for P1: 0, mck2ui 16
5170 17:41:47.440782 best dqsien dly found for B0: ( 1, 2, 30)
5171 17:41:47.444472 Total UI for P1: 0, mck2ui 16
5172 17:41:47.447122 best dqsien dly found for B1: ( 1, 3, 2)
5173 17:41:47.450619 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5174 17:41:47.454329 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5175 17:41:47.454881
5176 17:41:47.457103 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5177 17:41:47.460750 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5178 17:41:47.464338 [Gating] SW calibration Done
5179 17:41:47.464775 ==
5180 17:41:47.467336 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 17:41:47.470758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 17:41:47.473958 ==
5183 17:41:47.474365 RX Vref Scan: 0
5184 17:41:47.474693
5185 17:41:47.477154 RX Vref 0 -> 0, step: 1
5186 17:41:47.477639
5187 17:41:47.480449 RX Delay -80 -> 252, step: 8
5188 17:41:47.483919 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5189 17:41:47.487662 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5190 17:41:47.490572 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5191 17:41:47.494241 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5192 17:41:47.497163 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5193 17:41:47.500649 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5194 17:41:47.507621 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5195 17:41:47.510535 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5196 17:41:47.513966 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5197 17:41:47.517145 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5198 17:41:47.520425 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5199 17:41:47.527172 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5200 17:41:47.530486 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5201 17:41:47.533873 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5202 17:41:47.537190 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5203 17:41:47.540356 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5204 17:41:47.540584 ==
5205 17:41:47.543892 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 17:41:47.550793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 17:41:47.551091 ==
5208 17:41:47.551276 DQS Delay:
5209 17:41:47.553306 DQS0 = 0, DQS1 = 0
5210 17:41:47.553626 DQM Delay:
5211 17:41:47.553909 DQM0 = 97, DQM1 = 87
5212 17:41:47.556659 DQ Delay:
5213 17:41:47.560461 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5214 17:41:47.563591 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5215 17:41:47.566798 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5216 17:41:47.570431 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5217 17:41:47.570658
5218 17:41:47.570872
5219 17:41:47.571043 ==
5220 17:41:47.574281 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 17:41:47.577038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 17:41:47.577319 ==
5223 17:41:47.577539
5224 17:41:47.577742
5225 17:41:47.581154 TX Vref Scan disable
5226 17:41:47.581639 == TX Byte 0 ==
5227 17:41:47.587329 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5228 17:41:47.590974 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5229 17:41:47.591515 == TX Byte 1 ==
5230 17:41:47.597381 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5231 17:41:47.601089 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5232 17:41:47.601518 ==
5233 17:41:47.603865 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 17:41:47.607435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 17:41:47.607862 ==
5236 17:41:47.608196
5237 17:41:47.608518
5238 17:41:47.611190 TX Vref Scan disable
5239 17:41:47.613842 == TX Byte 0 ==
5240 17:41:47.617845 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5241 17:41:47.620672 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5242 17:41:47.623680 == TX Byte 1 ==
5243 17:41:47.627315 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5244 17:41:47.630338 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5245 17:41:47.634136
5246 17:41:47.634555 [DATLAT]
5247 17:41:47.634974 Freq=933, CH0 RK0
5248 17:41:47.635302
5249 17:41:47.637252 DATLAT Default: 0xd
5250 17:41:47.637837 0, 0xFFFF, sum = 0
5251 17:41:47.640506 1, 0xFFFF, sum = 0
5252 17:41:47.641027 2, 0xFFFF, sum = 0
5253 17:41:47.643885 3, 0xFFFF, sum = 0
5254 17:41:47.644318 4, 0xFFFF, sum = 0
5255 17:41:47.647431 5, 0xFFFF, sum = 0
5256 17:41:47.650408 6, 0xFFFF, sum = 0
5257 17:41:47.650897 7, 0xFFFF, sum = 0
5258 17:41:47.653895 8, 0xFFFF, sum = 0
5259 17:41:47.654327 9, 0xFFFF, sum = 0
5260 17:41:47.656781 10, 0x0, sum = 1
5261 17:41:47.657214 11, 0x0, sum = 2
5262 17:41:47.660257 12, 0x0, sum = 3
5263 17:41:47.660710 13, 0x0, sum = 4
5264 17:41:47.661054 best_step = 11
5265 17:41:47.661366
5266 17:41:47.663708 ==
5267 17:41:47.666963 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 17:41:47.669943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 17:41:47.670384 ==
5270 17:41:47.670719 RX Vref Scan: 1
5271 17:41:47.671108
5272 17:41:47.673953 RX Vref 0 -> 0, step: 1
5273 17:41:47.674450
5274 17:41:47.677527 RX Delay -61 -> 252, step: 4
5275 17:41:47.677949
5276 17:41:47.680222 Set Vref, RX VrefLevel [Byte0]: 55
5277 17:41:47.683971 [Byte1]: 52
5278 17:41:47.684613
5279 17:41:47.686818 Final RX Vref Byte 0 = 55 to rank0
5280 17:41:47.690163 Final RX Vref Byte 1 = 52 to rank0
5281 17:41:47.693704 Final RX Vref Byte 0 = 55 to rank1
5282 17:41:47.696471 Final RX Vref Byte 1 = 52 to rank1==
5283 17:41:47.700068 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 17:41:47.703562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 17:41:47.704147 ==
5286 17:41:47.706700 DQS Delay:
5287 17:41:47.707184 DQS0 = 0, DQS1 = 0
5288 17:41:47.710122 DQM Delay:
5289 17:41:47.710426 DQM0 = 97, DQM1 = 88
5290 17:41:47.710665 DQ Delay:
5291 17:41:47.713187 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5292 17:41:47.716629 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5293 17:41:47.720232 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =82
5294 17:41:47.723703 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5295 17:41:47.724006
5296 17:41:47.724246
5297 17:41:47.733490 [DQSOSCAuto] RK0, (LSB)MR18= 0x1501, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 415 ps
5298 17:41:47.736735 CH0 RK0: MR19=505, MR18=1501
5299 17:41:47.743658 CH0_RK0: MR19=0x505, MR18=0x1501, DQSOSC=415, MR23=63, INC=62, DEC=41
5300 17:41:47.743960
5301 17:41:47.746694 ----->DramcWriteLeveling(PI) begin...
5302 17:41:47.747031 ==
5303 17:41:47.750424 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 17:41:47.753294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 17:41:47.753752 ==
5306 17:41:47.756771 Write leveling (Byte 0): 30 => 30
5307 17:41:47.759708 Write leveling (Byte 1): 28 => 28
5308 17:41:47.763226 DramcWriteLeveling(PI) end<-----
5309 17:41:47.763519
5310 17:41:47.763754 ==
5311 17:41:47.766772 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 17:41:47.770236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 17:41:47.770578 ==
5314 17:41:47.773346 [Gating] SW mode calibration
5315 17:41:47.780275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 17:41:47.786818 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 17:41:47.790371 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5318 17:41:47.793311 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 17:41:47.797159 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 17:41:47.803723 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 17:41:47.807367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 17:41:47.810178 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 17:41:47.816795 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5324 17:41:47.820481 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
5325 17:41:47.823923 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (1 0)
5326 17:41:47.830455 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 17:41:47.833486 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 17:41:47.837124 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 17:41:47.843642 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 17:41:47.847255 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 17:41:47.850826 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 17:41:47.856890 0 15 28 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
5333 17:41:47.860704 1 0 0 | B1->B0 | 3635 4646 | 1 0 | (0 0) (0 0)
5334 17:41:47.863893 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 17:41:47.870440 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 17:41:47.873769 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 17:41:47.877424 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 17:41:47.884042 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 17:41:47.887040 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 17:41:47.890400 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5341 17:41:47.893658 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5342 17:41:47.900335 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5343 17:41:47.904381 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 17:41:47.907381 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 17:41:47.913713 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 17:41:47.917253 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 17:41:47.920944 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 17:41:47.927583 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 17:41:47.930534 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 17:41:47.934190 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 17:41:47.941117 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 17:41:47.944441 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 17:41:47.947365 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 17:41:47.954152 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 17:41:47.957373 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 17:41:47.960459 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 17:41:47.964307 Total UI for P1: 0, mck2ui 16
5358 17:41:47.967335 best dqsien dly found for B0: ( 1, 2, 24)
5359 17:41:47.970349 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5360 17:41:47.977256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 17:41:47.980565 Total UI for P1: 0, mck2ui 16
5362 17:41:47.983722 best dqsien dly found for B1: ( 1, 3, 2)
5363 17:41:47.987294 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5364 17:41:47.990375 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5365 17:41:47.990844
5366 17:41:47.993816 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5367 17:41:47.997264 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5368 17:41:48.000635 [Gating] SW calibration Done
5369 17:41:48.001134 ==
5370 17:41:48.003629 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 17:41:48.007442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 17:41:48.007861 ==
5373 17:41:48.010619 RX Vref Scan: 0
5374 17:41:48.011105
5375 17:41:48.011433 RX Vref 0 -> 0, step: 1
5376 17:41:48.013721
5377 17:41:48.014131 RX Delay -80 -> 252, step: 8
5378 17:41:48.020431 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5379 17:41:48.024230 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5380 17:41:48.027221 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5381 17:41:48.030636 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5382 17:41:48.033603 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5383 17:41:48.037177 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5384 17:41:48.041031 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5385 17:41:48.046963 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5386 17:41:48.050320 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5387 17:41:48.054028 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5388 17:41:48.057308 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5389 17:41:48.060218 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5390 17:41:48.066931 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5391 17:41:48.070376 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5392 17:41:48.074021 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5393 17:41:48.077062 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5394 17:41:48.077487 ==
5395 17:41:48.080585 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 17:41:48.083742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 17:41:48.084171 ==
5398 17:41:48.087383 DQS Delay:
5399 17:41:48.087846 DQS0 = 0, DQS1 = 0
5400 17:41:48.090342 DQM Delay:
5401 17:41:48.090847 DQM0 = 97, DQM1 = 87
5402 17:41:48.091201 DQ Delay:
5403 17:41:48.093692 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5404 17:41:48.097060 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5405 17:41:48.100220 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5406 17:41:48.103924 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5407 17:41:48.104349
5408 17:41:48.104674
5409 17:41:48.107092 ==
5410 17:41:48.110311 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 17:41:48.113722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 17:41:48.114140 ==
5413 17:41:48.114465
5414 17:41:48.114846
5415 17:41:48.116964 TX Vref Scan disable
5416 17:41:48.117377 == TX Byte 0 ==
5417 17:41:48.123408 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5418 17:41:48.126694 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5419 17:41:48.127172 == TX Byte 1 ==
5420 17:41:48.133448 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5421 17:41:48.136910 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5422 17:41:48.137360 ==
5423 17:41:48.141099 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 17:41:48.143667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 17:41:48.144087 ==
5426 17:41:48.144415
5427 17:41:48.144718
5428 17:41:48.147245 TX Vref Scan disable
5429 17:41:48.150132 == TX Byte 0 ==
5430 17:41:48.153792 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5431 17:41:48.157136 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5432 17:41:48.159983 == TX Byte 1 ==
5433 17:41:48.163664 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5434 17:41:48.167106 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5435 17:41:48.167638
5436 17:41:48.168139 [DATLAT]
5437 17:41:48.170696 Freq=933, CH0 RK1
5438 17:41:48.171174
5439 17:41:48.173891 DATLAT Default: 0xb
5440 17:41:48.174305 0, 0xFFFF, sum = 0
5441 17:41:48.177331 1, 0xFFFF, sum = 0
5442 17:41:48.177749 2, 0xFFFF, sum = 0
5443 17:41:48.180557 3, 0xFFFF, sum = 0
5444 17:41:48.180982 4, 0xFFFF, sum = 0
5445 17:41:48.184232 5, 0xFFFF, sum = 0
5446 17:41:48.184756 6, 0xFFFF, sum = 0
5447 17:41:48.187217 7, 0xFFFF, sum = 0
5448 17:41:48.187637 8, 0xFFFF, sum = 0
5449 17:41:48.190923 9, 0xFFFF, sum = 0
5450 17:41:48.191351 10, 0x0, sum = 1
5451 17:41:48.193693 11, 0x0, sum = 2
5452 17:41:48.194116 12, 0x0, sum = 3
5453 17:41:48.197204 13, 0x0, sum = 4
5454 17:41:48.197626 best_step = 11
5455 17:41:48.197952
5456 17:41:48.198284 ==
5457 17:41:48.200854 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 17:41:48.203687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 17:41:48.204274 ==
5460 17:41:48.207047 RX Vref Scan: 0
5461 17:41:48.207507
5462 17:41:48.210031 RX Vref 0 -> 0, step: 1
5463 17:41:48.210578
5464 17:41:48.211114 RX Delay -61 -> 252, step: 4
5465 17:41:48.218013 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5466 17:41:48.221860 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 17:41:48.225169 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 17:41:48.228303 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 17:41:48.231438 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5470 17:41:48.235236 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5471 17:41:48.241463 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5472 17:41:48.245028 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5473 17:41:48.248565 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5474 17:41:48.251464 iDelay=199, Bit 9, Center 80 (-5 ~ 166) 172
5475 17:41:48.255090 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5476 17:41:48.261832 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5477 17:41:48.264828 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5478 17:41:48.268243 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5479 17:41:48.271772 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5480 17:41:48.274858 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5481 17:41:48.275366 ==
5482 17:41:48.278507 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 17:41:48.281551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 17:41:48.284631 ==
5485 17:41:48.285065 DQS Delay:
5486 17:41:48.285412 DQS0 = 0, DQS1 = 0
5487 17:41:48.287971 DQM Delay:
5488 17:41:48.288387 DQM0 = 96, DQM1 = 88
5489 17:41:48.291521 DQ Delay:
5490 17:41:48.291997 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5491 17:41:48.294832 DQ4 =94, DQ5 =86, DQ6 =108, DQ7 =104
5492 17:41:48.298611 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =80
5493 17:41:48.305020 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5494 17:41:48.305437
5495 17:41:48.305758
5496 17:41:48.311696 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5497 17:41:48.315227 CH0 RK1: MR19=505, MR18=1906
5498 17:41:48.322201 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5499 17:41:48.325024 [RxdqsGatingPostProcess] freq 933
5500 17:41:48.328522 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 17:41:48.331808 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 17:41:48.335012 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 17:41:48.338202 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 17:41:48.341608 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 17:41:48.344837 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 17:41:48.347997 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 17:41:48.351486 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 17:41:48.355050 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 17:41:48.358160 Pre-setting of DQS Precalculation
5510 17:41:48.361650 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 17:41:48.362068 ==
5512 17:41:48.365208 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 17:41:48.368697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 17:41:48.371860 ==
5515 17:41:48.374760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 17:41:48.381777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 17:41:48.384696 [CA 0] Center 36 (6~67) winsize 62
5518 17:41:48.388585 [CA 1] Center 36 (6~67) winsize 62
5519 17:41:48.391351 [CA 2] Center 34 (4~64) winsize 61
5520 17:41:48.394999 [CA 3] Center 34 (4~64) winsize 61
5521 17:41:48.397946 [CA 4] Center 34 (4~65) winsize 62
5522 17:41:48.401156 [CA 5] Center 33 (3~64) winsize 62
5523 17:41:48.401703
5524 17:41:48.404896 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 17:41:48.405314
5526 17:41:48.407760 [CATrainingPosCal] consider 1 rank data
5527 17:41:48.411360 u2DelayCellTimex100 = 270/100 ps
5528 17:41:48.414789 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 17:41:48.418177 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 17:41:48.421224 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 17:41:48.424810 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5532 17:41:48.431130 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 17:41:48.434916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 17:41:48.435424
5535 17:41:48.438328 CA PerBit enable=1, Macro0, CA PI delay=33
5536 17:41:48.438832
5537 17:41:48.441611 [CBTSetCACLKResult] CA Dly = 33
5538 17:41:48.442028 CS Dly: 4 (0~35)
5539 17:41:48.442356 ==
5540 17:41:48.444678 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 17:41:48.447693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 17:41:48.451204 ==
5543 17:41:48.454366 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 17:41:48.461608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 17:41:48.464445 [CA 0] Center 36 (6~67) winsize 62
5546 17:41:48.468254 [CA 1] Center 36 (6~67) winsize 62
5547 17:41:48.471909 [CA 2] Center 33 (3~64) winsize 62
5548 17:41:48.474699 [CA 3] Center 33 (3~64) winsize 62
5549 17:41:48.478304 [CA 4] Center 34 (4~64) winsize 61
5550 17:41:48.481321 [CA 5] Center 32 (2~63) winsize 62
5551 17:41:48.481745
5552 17:41:48.484923 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 17:41:48.485347
5554 17:41:48.488773 [CATrainingPosCal] consider 2 rank data
5555 17:41:48.491752 u2DelayCellTimex100 = 270/100 ps
5556 17:41:48.495001 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 17:41:48.497995 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5558 17:41:48.501445 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5559 17:41:48.504722 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5560 17:41:48.507833 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 17:41:48.514541 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5562 17:41:48.515002
5563 17:41:48.518216 CA PerBit enable=1, Macro0, CA PI delay=33
5564 17:41:48.518632
5565 17:41:48.521191 [CBTSetCACLKResult] CA Dly = 33
5566 17:41:48.521610 CS Dly: 5 (0~38)
5567 17:41:48.521936
5568 17:41:48.524720 ----->DramcWriteLeveling(PI) begin...
5569 17:41:48.525142 ==
5570 17:41:48.528270 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 17:41:48.534620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 17:41:48.535074 ==
5573 17:41:48.537968 Write leveling (Byte 0): 27 => 27
5574 17:41:48.538410 Write leveling (Byte 1): 28 => 28
5575 17:41:48.541612 DramcWriteLeveling(PI) end<-----
5576 17:41:48.542036
5577 17:41:48.542365 ==
5578 17:41:48.545023 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 17:41:48.551737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 17:41:48.552411 ==
5581 17:41:48.554704 [Gating] SW mode calibration
5582 17:41:48.561178 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 17:41:48.564670 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 17:41:48.571220 0 14 0 | B1->B0 | 3030 3131 | 0 1 | (0 0) (1 1)
5585 17:41:48.574994 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5586 17:41:48.578043 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 17:41:48.581871 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5588 17:41:48.588146 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5589 17:41:48.591273 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5590 17:41:48.594922 0 14 24 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5591 17:41:48.601714 0 14 28 | B1->B0 | 2e2e 3030 | 0 0 | (0 0) (0 0)
5592 17:41:48.605044 0 15 0 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
5593 17:41:48.608293 0 15 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5594 17:41:48.615046 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5595 17:41:48.617900 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 17:41:48.621595 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 17:41:48.628002 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 17:41:48.631752 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 17:41:48.635290 0 15 28 | B1->B0 | 3535 2e2e | 0 1 | (0 0) (0 0)
5600 17:41:48.641661 1 0 0 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
5601 17:41:48.644856 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 17:41:48.648106 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 17:41:48.654855 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 17:41:48.658374 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 17:41:48.661308 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 17:41:48.667994 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 17:41:48.671631 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 17:41:48.674919 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 17:41:48.678336 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 17:41:48.684604 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 17:41:48.688110 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 17:41:48.691856 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 17:41:48.698410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 17:41:48.701926 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 17:41:48.704864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 17:41:48.711768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 17:41:48.714953 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 17:41:48.718281 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 17:41:48.724721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 17:41:48.728151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 17:41:48.731910 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 17:41:48.737916 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 17:41:48.741480 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5624 17:41:48.745118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 17:41:48.748199 Total UI for P1: 0, mck2ui 16
5626 17:41:48.751577 best dqsien dly found for B0: ( 1, 2, 30)
5627 17:41:48.754539 Total UI for P1: 0, mck2ui 16
5628 17:41:48.758229 best dqsien dly found for B1: ( 1, 2, 28)
5629 17:41:48.761327 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5630 17:41:48.764580 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5631 17:41:48.764806
5632 17:41:48.768366 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5633 17:41:48.774595 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5634 17:41:48.774700 [Gating] SW calibration Done
5635 17:41:48.774811 ==
5636 17:41:48.778117 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 17:41:48.784926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 17:41:48.785101 ==
5639 17:41:48.785189 RX Vref Scan: 0
5640 17:41:48.785264
5641 17:41:48.787968 RX Vref 0 -> 0, step: 1
5642 17:41:48.788133
5643 17:41:48.791246 RX Delay -80 -> 252, step: 8
5644 17:41:48.794777 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5645 17:41:48.798257 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5646 17:41:48.801627 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5647 17:41:48.804816 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5648 17:41:48.807901 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5649 17:41:48.814621 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5650 17:41:48.818342 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5651 17:41:48.821741 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5652 17:41:48.825382 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5653 17:41:48.828358 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5654 17:41:48.835041 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5655 17:41:48.838123 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5656 17:41:48.841845 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5657 17:41:48.845146 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5658 17:41:48.849104 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5659 17:41:48.851916 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5660 17:41:48.855030 ==
5661 17:41:48.855455 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 17:41:48.862348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 17:41:48.862925 ==
5664 17:41:48.863274 DQS Delay:
5665 17:41:48.865093 DQS0 = 0, DQS1 = 0
5666 17:41:48.865516 DQM Delay:
5667 17:41:48.868799 DQM0 = 96, DQM1 = 88
5668 17:41:48.869318 DQ Delay:
5669 17:41:48.871605 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5670 17:41:48.875229 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5671 17:41:48.878418 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5672 17:41:48.881443 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5673 17:41:48.881876
5674 17:41:48.882315
5675 17:41:48.882746 ==
5676 17:41:48.884821 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 17:41:48.888479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 17:41:48.888922 ==
5679 17:41:48.889359
5680 17:41:48.889775
5681 17:41:48.891600 TX Vref Scan disable
5682 17:41:48.894967 == TX Byte 0 ==
5683 17:41:48.898050 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5684 17:41:48.901304 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5685 17:41:48.904757 == TX Byte 1 ==
5686 17:41:48.908337 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5687 17:41:48.911323 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5688 17:41:48.911570 ==
5689 17:41:48.914575 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 17:41:48.918050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 17:41:48.921469 ==
5692 17:41:48.922259
5693 17:41:48.922936
5694 17:41:48.923359 TX Vref Scan disable
5695 17:41:48.925801 == TX Byte 0 ==
5696 17:41:48.928592 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5697 17:41:48.932133 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5698 17:41:48.935093 == TX Byte 1 ==
5699 17:41:48.938681 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5700 17:41:48.942241 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5701 17:41:48.945499
5702 17:41:48.946015 [DATLAT]
5703 17:41:48.946353 Freq=933, CH1 RK0
5704 17:41:48.946662
5705 17:41:48.948648 DATLAT Default: 0xd
5706 17:41:48.949140 0, 0xFFFF, sum = 0
5707 17:41:48.952158 1, 0xFFFF, sum = 0
5708 17:41:48.952583 2, 0xFFFF, sum = 0
5709 17:41:48.955142 3, 0xFFFF, sum = 0
5710 17:41:48.955590 4, 0xFFFF, sum = 0
5711 17:41:48.958780 5, 0xFFFF, sum = 0
5712 17:41:48.959205 6, 0xFFFF, sum = 0
5713 17:41:48.961800 7, 0xFFFF, sum = 0
5714 17:41:48.965365 8, 0xFFFF, sum = 0
5715 17:41:48.965880 9, 0xFFFF, sum = 0
5716 17:41:48.966219 10, 0x0, sum = 1
5717 17:41:48.968604 11, 0x0, sum = 2
5718 17:41:48.969134 12, 0x0, sum = 3
5719 17:41:48.971703 13, 0x0, sum = 4
5720 17:41:48.972150 best_step = 11
5721 17:41:48.972482
5722 17:41:48.972786 ==
5723 17:41:48.975239 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 17:41:48.981715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 17:41:48.982140 ==
5726 17:41:48.982470 RX Vref Scan: 1
5727 17:41:48.982828
5728 17:41:48.985091 RX Vref 0 -> 0, step: 1
5729 17:41:48.985690
5730 17:41:48.988591 RX Delay -69 -> 252, step: 4
5731 17:41:48.989015
5732 17:41:48.992216 Set Vref, RX VrefLevel [Byte0]: 57
5733 17:41:48.995279 [Byte1]: 46
5734 17:41:48.995703
5735 17:41:48.998919 Final RX Vref Byte 0 = 57 to rank0
5736 17:41:49.001985 Final RX Vref Byte 1 = 46 to rank0
5737 17:41:49.005018 Final RX Vref Byte 0 = 57 to rank1
5738 17:41:49.008825 Final RX Vref Byte 1 = 46 to rank1==
5739 17:41:49.011898 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 17:41:49.015155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 17:41:49.015582 ==
5742 17:41:49.018532 DQS Delay:
5743 17:41:49.019442 DQS0 = 0, DQS1 = 0
5744 17:41:49.021852 DQM Delay:
5745 17:41:49.022269 DQM0 = 98, DQM1 = 90
5746 17:41:49.022663 DQ Delay:
5747 17:41:49.025438 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =98
5748 17:41:49.028463 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5749 17:41:49.032283 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =84
5750 17:41:49.035112 DQ12 =102, DQ13 =96, DQ14 =100, DQ15 =94
5751 17:41:49.035532
5752 17:41:49.035862
5753 17:41:49.045589 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5754 17:41:49.048796 CH1 RK0: MR19=504, MR18=11EE
5755 17:41:49.051936 CH1_RK0: MR19=0x504, MR18=0x11EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5756 17:41:49.055457
5757 17:41:49.058319 ----->DramcWriteLeveling(PI) begin...
5758 17:41:49.058896 ==
5759 17:41:49.061904 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 17:41:49.065536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 17:41:49.066051 ==
5762 17:41:49.068890 Write leveling (Byte 0): 28 => 28
5763 17:41:49.071823 Write leveling (Byte 1): 29 => 29
5764 17:41:49.075366 DramcWriteLeveling(PI) end<-----
5765 17:41:49.075786
5766 17:41:49.076114 ==
5767 17:41:49.078414 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 17:41:49.082052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 17:41:49.082475 ==
5770 17:41:49.085551 [Gating] SW mode calibration
5771 17:41:49.091931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 17:41:49.098682 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 17:41:49.102386 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5774 17:41:49.105470 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 17:41:49.108556 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 17:41:49.115575 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 17:41:49.118910 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 17:41:49.122316 0 14 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5779 17:41:49.128830 0 14 24 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 0)
5780 17:41:49.132338 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5781 17:41:49.135263 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 17:41:49.142111 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 17:41:49.145472 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 17:41:49.148452 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 17:41:49.155133 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 17:41:49.158369 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 17:41:49.162162 0 15 24 | B1->B0 | 2a2a 3131 | 0 0 | (0 0) (0 0)
5788 17:41:49.168425 0 15 28 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
5789 17:41:49.171902 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 17:41:49.175002 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 17:41:49.181846 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 17:41:49.185091 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 17:41:49.188342 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 17:41:49.195780 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 17:41:49.198534 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5796 17:41:49.201759 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 17:41:49.205396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 17:41:49.211990 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 17:41:49.215241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 17:41:49.218812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 17:41:49.225182 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 17:41:49.228592 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 17:41:49.232159 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 17:41:49.238915 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 17:41:49.242217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 17:41:49.245436 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 17:41:49.251876 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 17:41:49.255733 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 17:41:49.259219 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 17:41:49.265485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5811 17:41:49.269133 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5812 17:41:49.271994 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 17:41:49.275782 Total UI for P1: 0, mck2ui 16
5814 17:41:49.278860 best dqsien dly found for B0: ( 1, 2, 22)
5815 17:41:49.282040 Total UI for P1: 0, mck2ui 16
5816 17:41:49.285665 best dqsien dly found for B1: ( 1, 2, 24)
5817 17:41:49.288679 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5818 17:41:49.292293 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5819 17:41:49.292717
5820 17:41:49.295412 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5821 17:41:49.302120 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5822 17:41:49.302549 [Gating] SW calibration Done
5823 17:41:49.302923 ==
5824 17:41:49.305370 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 17:41:49.311936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 17:41:49.312365 ==
5827 17:41:49.312699 RX Vref Scan: 0
5828 17:41:49.313004
5829 17:41:49.315136 RX Vref 0 -> 0, step: 1
5830 17:41:49.315556
5831 17:41:49.318814 RX Delay -80 -> 252, step: 8
5832 17:41:49.322050 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5833 17:41:49.325563 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5834 17:41:49.328730 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5835 17:41:49.332154 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5836 17:41:49.338642 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5837 17:41:49.342281 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5838 17:41:49.345678 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5839 17:41:49.348918 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5840 17:41:49.352199 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5841 17:41:49.355621 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5842 17:41:49.361934 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5843 17:41:49.365352 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5844 17:41:49.368732 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5845 17:41:49.372071 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5846 17:41:49.375550 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5847 17:41:49.378634 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5848 17:41:49.382189 ==
5849 17:41:49.385016 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 17:41:49.388642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 17:41:49.389066 ==
5852 17:41:49.389756 DQS Delay:
5853 17:41:49.392356 DQS0 = 0, DQS1 = 0
5854 17:41:49.392786 DQM Delay:
5855 17:41:49.395036 DQM0 = 94, DQM1 = 89
5856 17:41:49.395515 DQ Delay:
5857 17:41:49.398512 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5858 17:41:49.402176 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5859 17:41:49.405255 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5860 17:41:49.408500 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5861 17:41:49.408921
5862 17:41:49.409314
5863 17:41:49.409631 ==
5864 17:41:49.412430 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 17:41:49.415445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 17:41:49.415866 ==
5867 17:41:49.416196
5868 17:41:49.416500
5869 17:41:49.418396 TX Vref Scan disable
5870 17:41:49.422059 == TX Byte 0 ==
5871 17:41:49.425444 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5872 17:41:49.428565 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5873 17:41:49.432370 == TX Byte 1 ==
5874 17:41:49.435254 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5875 17:41:49.438438 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5876 17:41:49.438900 ==
5877 17:41:49.441935 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 17:41:49.445594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 17:41:49.448738 ==
5880 17:41:49.449157
5881 17:41:49.449486
5882 17:41:49.449791 TX Vref Scan disable
5883 17:41:49.452452 == TX Byte 0 ==
5884 17:41:49.455544 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5885 17:41:49.458786 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5886 17:41:49.462319 == TX Byte 1 ==
5887 17:41:49.465923 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5888 17:41:49.468713 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5889 17:41:49.472233
5890 17:41:49.472692 [DATLAT]
5891 17:41:49.473031 Freq=933, CH1 RK1
5892 17:41:49.473345
5893 17:41:49.475895 DATLAT Default: 0xb
5894 17:41:49.476314 0, 0xFFFF, sum = 0
5895 17:41:49.478836 1, 0xFFFF, sum = 0
5896 17:41:49.479264 2, 0xFFFF, sum = 0
5897 17:41:49.481992 3, 0xFFFF, sum = 0
5898 17:41:49.482470 4, 0xFFFF, sum = 0
5899 17:41:49.485680 5, 0xFFFF, sum = 0
5900 17:41:49.486103 6, 0xFFFF, sum = 0
5901 17:41:49.489097 7, 0xFFFF, sum = 0
5902 17:41:49.489619 8, 0xFFFF, sum = 0
5903 17:41:49.492674 9, 0xFFFF, sum = 0
5904 17:41:49.493102 10, 0x0, sum = 1
5905 17:41:49.495439 11, 0x0, sum = 2
5906 17:41:49.495863 12, 0x0, sum = 3
5907 17:41:49.499217 13, 0x0, sum = 4
5908 17:41:49.499645 best_step = 11
5909 17:41:49.499973
5910 17:41:49.500279 ==
5911 17:41:49.502269 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 17:41:49.509155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 17:41:49.509699 ==
5914 17:41:49.510040 RX Vref Scan: 0
5915 17:41:49.510347
5916 17:41:49.512210 RX Vref 0 -> 0, step: 1
5917 17:41:49.512628
5918 17:41:49.515322 RX Delay -61 -> 252, step: 4
5919 17:41:49.519714 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5920 17:41:49.522684 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5921 17:41:49.528835 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5922 17:41:49.532235 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5923 17:41:49.535454 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5924 17:41:49.538490 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5925 17:41:49.542062 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5926 17:41:49.545137 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5927 17:41:49.552141 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5928 17:41:49.555075 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5929 17:41:49.558519 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5930 17:41:49.561829 iDelay=199, Bit 11, Center 86 (-1 ~ 174) 176
5931 17:41:49.565296 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5932 17:41:49.571640 iDelay=199, Bit 13, Center 96 (7 ~ 186) 180
5933 17:41:49.574935 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5934 17:41:49.578608 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5935 17:41:49.578773 ==
5936 17:41:49.582024 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 17:41:49.585156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 17:41:49.585261 ==
5939 17:41:49.588466 DQS Delay:
5940 17:41:49.588589 DQS0 = 0, DQS1 = 0
5941 17:41:49.588702 DQM Delay:
5942 17:41:49.591561 DQM0 = 95, DQM1 = 90
5943 17:41:49.591648 DQ Delay:
5944 17:41:49.595239 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
5945 17:41:49.598500 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5946 17:41:49.601590 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =86
5947 17:41:49.605420 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =100
5948 17:41:49.605504
5949 17:41:49.605588
5950 17:41:49.615094 [DQSOSCAuto] RK1, (LSB)MR18= 0xe18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5951 17:41:49.618595 CH1 RK1: MR19=505, MR18=E18
5952 17:41:49.621898 CH1_RK1: MR19=0x505, MR18=0xE18, DQSOSC=414, MR23=63, INC=63, DEC=42
5953 17:41:49.625308 [RxdqsGatingPostProcess] freq 933
5954 17:41:49.631933 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5955 17:41:49.635618 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 17:41:49.638496 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 17:41:49.641860 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 17:41:49.645719 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 17:41:49.648977 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 17:41:49.649520 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 17:41:49.652748 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 17:41:49.655682 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 17:41:49.658715 Pre-setting of DQS Precalculation
5964 17:41:49.665400 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5965 17:41:49.672052 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5966 17:41:49.678973 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5967 17:41:49.679506
5968 17:41:49.679947
5969 17:41:49.682268 [Calibration Summary] 1866 Mbps
5970 17:41:49.685220 CH 0, Rank 0
5971 17:41:49.685648 SW Impedance : PASS
5972 17:41:49.688764 DUTY Scan : NO K
5973 17:41:49.689196 ZQ Calibration : PASS
5974 17:41:49.692465 Jitter Meter : NO K
5975 17:41:49.695371 CBT Training : PASS
5976 17:41:49.695901 Write leveling : PASS
5977 17:41:49.699064 RX DQS gating : PASS
5978 17:41:49.701884 RX DQ/DQS(RDDQC) : PASS
5979 17:41:49.702313 TX DQ/DQS : PASS
5980 17:41:49.705390 RX DATLAT : PASS
5981 17:41:49.708895 RX DQ/DQS(Engine): PASS
5982 17:41:49.709390 TX OE : NO K
5983 17:41:49.712337 All Pass.
5984 17:41:49.712751
5985 17:41:49.713078 CH 0, Rank 1
5986 17:41:49.715495 SW Impedance : PASS
5987 17:41:49.716019 DUTY Scan : NO K
5988 17:41:49.718914 ZQ Calibration : PASS
5989 17:41:49.722011 Jitter Meter : NO K
5990 17:41:49.722515 CBT Training : PASS
5991 17:41:49.725484 Write leveling : PASS
5992 17:41:49.725939 RX DQS gating : PASS
5993 17:41:49.728669 RX DQ/DQS(RDDQC) : PASS
5994 17:41:49.732037 TX DQ/DQS : PASS
5995 17:41:49.732461 RX DATLAT : PASS
5996 17:41:49.735570 RX DQ/DQS(Engine): PASS
5997 17:41:49.738887 TX OE : NO K
5998 17:41:49.739311 All Pass.
5999 17:41:49.739645
6000 17:41:49.739949 CH 1, Rank 0
6001 17:41:49.742477 SW Impedance : PASS
6002 17:41:49.745345 DUTY Scan : NO K
6003 17:41:49.745767 ZQ Calibration : PASS
6004 17:41:49.749116 Jitter Meter : NO K
6005 17:41:49.752414 CBT Training : PASS
6006 17:41:49.752841 Write leveling : PASS
6007 17:41:49.755754 RX DQS gating : PASS
6008 17:41:49.759212 RX DQ/DQS(RDDQC) : PASS
6009 17:41:49.759827 TX DQ/DQS : PASS
6010 17:41:49.762083 RX DATLAT : PASS
6011 17:41:49.762498 RX DQ/DQS(Engine): PASS
6012 17:41:49.765281 TX OE : NO K
6013 17:41:49.765713 All Pass.
6014 17:41:49.766147
6015 17:41:49.768819 CH 1, Rank 1
6016 17:41:49.769247 SW Impedance : PASS
6017 17:41:49.772059 DUTY Scan : NO K
6018 17:41:49.775686 ZQ Calibration : PASS
6019 17:41:49.776119 Jitter Meter : NO K
6020 17:41:49.779072 CBT Training : PASS
6021 17:41:49.782386 Write leveling : PASS
6022 17:41:49.782848 RX DQS gating : PASS
6023 17:41:49.785675 RX DQ/DQS(RDDQC) : PASS
6024 17:41:49.788948 TX DQ/DQS : PASS
6025 17:41:49.789376 RX DATLAT : PASS
6026 17:41:49.792402 RX DQ/DQS(Engine): PASS
6027 17:41:49.795697 TX OE : NO K
6028 17:41:49.796127 All Pass.
6029 17:41:49.796559
6030 17:41:49.796966 DramC Write-DBI off
6031 17:41:49.799026 PER_BANK_REFRESH: Hybrid Mode
6032 17:41:49.801888 TX_TRACKING: ON
6033 17:41:49.809270 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6034 17:41:49.811937 [FAST_K] Save calibration result to emmc
6035 17:41:49.819022 dramc_set_vcore_voltage set vcore to 650000
6036 17:41:49.819539 Read voltage for 400, 6
6037 17:41:49.823107 Vio18 = 0
6038 17:41:49.823815 Vcore = 650000
6039 17:41:49.824417 Vdram = 0
6040 17:41:49.826296 Vddq = 0
6041 17:41:49.827030 Vmddr = 0
6042 17:41:49.828566 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6043 17:41:49.835107 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6044 17:41:49.838402 MEM_TYPE=3, freq_sel=20
6045 17:41:49.841841 sv_algorithm_assistance_LP4_800
6046 17:41:49.845334 ============ PULL DRAM RESETB DOWN ============
6047 17:41:49.848716 ========== PULL DRAM RESETB DOWN end =========
6048 17:41:49.851689 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6049 17:41:49.855502 ===================================
6050 17:41:49.858320 LPDDR4 DRAM CONFIGURATION
6051 17:41:49.861839 ===================================
6052 17:41:49.865117 EX_ROW_EN[0] = 0x0
6053 17:41:49.865539 EX_ROW_EN[1] = 0x0
6054 17:41:49.868433 LP4Y_EN = 0x0
6055 17:41:49.868856 WORK_FSP = 0x0
6056 17:41:49.871842 WL = 0x2
6057 17:41:49.872264 RL = 0x2
6058 17:41:49.874996 BL = 0x2
6059 17:41:49.875475 RPST = 0x0
6060 17:41:49.878600 RD_PRE = 0x0
6061 17:41:49.879218 WR_PRE = 0x1
6062 17:41:49.881887 WR_PST = 0x0
6063 17:41:49.885199 DBI_WR = 0x0
6064 17:41:49.885790 DBI_RD = 0x0
6065 17:41:49.888431 OTF = 0x1
6066 17:41:49.892104 ===================================
6067 17:41:49.895571 ===================================
6068 17:41:49.896049 ANA top config
6069 17:41:49.898624 ===================================
6070 17:41:49.901873 DLL_ASYNC_EN = 0
6071 17:41:49.902413 ALL_SLAVE_EN = 1
6072 17:41:49.905203 NEW_RANK_MODE = 1
6073 17:41:49.908564 DLL_IDLE_MODE = 1
6074 17:41:49.911669 LP45_APHY_COMB_EN = 1
6075 17:41:49.915054 TX_ODT_DIS = 1
6076 17:41:49.915484 NEW_8X_MODE = 1
6077 17:41:49.918338 ===================================
6078 17:41:49.921789 ===================================
6079 17:41:49.925390 data_rate = 800
6080 17:41:49.928509 CKR = 1
6081 17:41:49.931616 DQ_P2S_RATIO = 4
6082 17:41:49.935217 ===================================
6083 17:41:49.938704 CA_P2S_RATIO = 4
6084 17:41:49.939059 DQ_CA_OPEN = 0
6085 17:41:49.942099 DQ_SEMI_OPEN = 1
6086 17:41:49.944822 CA_SEMI_OPEN = 1
6087 17:41:49.948086 CA_FULL_RATE = 0
6088 17:41:49.951636 DQ_CKDIV4_EN = 0
6089 17:41:49.955197 CA_CKDIV4_EN = 1
6090 17:41:49.955360 CA_PREDIV_EN = 0
6091 17:41:49.958166 PH8_DLY = 0
6092 17:41:49.962136 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6093 17:41:49.965023 DQ_AAMCK_DIV = 0
6094 17:41:49.968601 CA_AAMCK_DIV = 0
6095 17:41:49.968733 CA_ADMCK_DIV = 4
6096 17:41:49.971641 DQ_TRACK_CA_EN = 0
6097 17:41:49.974847 CA_PICK = 800
6098 17:41:49.978416 CA_MCKIO = 400
6099 17:41:49.981729 MCKIO_SEMI = 400
6100 17:41:49.985771 PLL_FREQ = 3016
6101 17:41:49.988553 DQ_UI_PI_RATIO = 32
6102 17:41:49.991950 CA_UI_PI_RATIO = 32
6103 17:41:49.995380 ===================================
6104 17:41:49.998329 ===================================
6105 17:41:49.998542 memory_type:LPDDR4
6106 17:41:50.002266 GP_NUM : 10
6107 17:41:50.002665 SRAM_EN : 1
6108 17:41:50.005318 MD32_EN : 0
6109 17:41:50.008317 ===================================
6110 17:41:50.011986 [ANA_INIT] >>>>>>>>>>>>>>
6111 17:41:50.014959 <<<<<< [CONFIGURE PHASE]: ANA_TX
6112 17:41:50.018790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6113 17:41:50.021999 ===================================
6114 17:41:50.022381 data_rate = 800,PCW = 0X7400
6115 17:41:50.025138 ===================================
6116 17:41:50.028547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6117 17:41:50.035819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 17:41:50.048421 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 17:41:50.051727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6120 17:41:50.055150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6121 17:41:50.058629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6122 17:41:50.062426 [ANA_INIT] flow start
6123 17:41:50.062574 [ANA_INIT] PLL >>>>>>>>
6124 17:41:50.065412 [ANA_INIT] PLL <<<<<<<<
6125 17:41:50.068722 [ANA_INIT] MIDPI >>>>>>>>
6126 17:41:50.068880 [ANA_INIT] MIDPI <<<<<<<<
6127 17:41:50.071744 [ANA_INIT] DLL >>>>>>>>
6128 17:41:50.075207 [ANA_INIT] flow end
6129 17:41:50.078632 ============ LP4 DIFF to SE enter ============
6130 17:41:50.082351 ============ LP4 DIFF to SE exit ============
6131 17:41:50.085170 [ANA_INIT] <<<<<<<<<<<<<
6132 17:41:50.088576 [Flow] Enable top DCM control >>>>>
6133 17:41:50.091964 [Flow] Enable top DCM control <<<<<
6134 17:41:50.095301 Enable DLL master slave shuffle
6135 17:41:50.098636 ==============================================================
6136 17:41:50.102039 Gating Mode config
6137 17:41:50.105492 ==============================================================
6138 17:41:50.108752 Config description:
6139 17:41:50.118397 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6140 17:41:50.125187 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6141 17:41:50.129046 SELPH_MODE 0: By rank 1: By Phase
6142 17:41:50.135147 ==============================================================
6143 17:41:50.138424 GAT_TRACK_EN = 0
6144 17:41:50.142049 RX_GATING_MODE = 2
6145 17:41:50.145556 RX_GATING_TRACK_MODE = 2
6146 17:41:50.149502 SELPH_MODE = 1
6147 17:41:50.149691 PICG_EARLY_EN = 1
6148 17:41:50.152389 VALID_LAT_VALUE = 1
6149 17:41:50.158854 ==============================================================
6150 17:41:50.162385 Enter into Gating configuration >>>>
6151 17:41:50.165697 Exit from Gating configuration <<<<
6152 17:41:50.169333 Enter into DVFS_PRE_config >>>>>
6153 17:41:50.178897 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6154 17:41:50.182367 Exit from DVFS_PRE_config <<<<<
6155 17:41:50.185873 Enter into PICG configuration >>>>
6156 17:41:50.188811 Exit from PICG configuration <<<<
6157 17:41:50.192451 [RX_INPUT] configuration >>>>>
6158 17:41:50.195705 [RX_INPUT] configuration <<<<<
6159 17:41:50.198917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6160 17:41:50.205609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6161 17:41:50.212013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 17:41:50.218714 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 17:41:50.225590 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 17:41:50.229136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 17:41:50.235290 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6166 17:41:50.238597 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6167 17:41:50.241942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6168 17:41:50.245278 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6169 17:41:50.252333 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6170 17:41:50.255549 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 17:41:50.258715 ===================================
6172 17:41:50.262122 LPDDR4 DRAM CONFIGURATION
6173 17:41:50.265491 ===================================
6174 17:41:50.265917 EX_ROW_EN[0] = 0x0
6175 17:41:50.268979 EX_ROW_EN[1] = 0x0
6176 17:41:50.269401 LP4Y_EN = 0x0
6177 17:41:50.272559 WORK_FSP = 0x0
6178 17:41:50.272980 WL = 0x2
6179 17:41:50.275710 RL = 0x2
6180 17:41:50.276131 BL = 0x2
6181 17:41:50.279282 RPST = 0x0
6182 17:41:50.279812 RD_PRE = 0x0
6183 17:41:50.282981 WR_PRE = 0x1
6184 17:41:50.283512 WR_PST = 0x0
6185 17:41:50.285748 DBI_WR = 0x0
6186 17:41:50.286275 DBI_RD = 0x0
6187 17:41:50.289408 OTF = 0x1
6188 17:41:50.292729 ===================================
6189 17:41:50.295795 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6190 17:41:50.299498 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6191 17:41:50.305786 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 17:41:50.308831 ===================================
6193 17:41:50.309249 LPDDR4 DRAM CONFIGURATION
6194 17:41:50.312104 ===================================
6195 17:41:50.316045 EX_ROW_EN[0] = 0x10
6196 17:41:50.318777 EX_ROW_EN[1] = 0x0
6197 17:41:50.319205 LP4Y_EN = 0x0
6198 17:41:50.322241 WORK_FSP = 0x0
6199 17:41:50.322681 WL = 0x2
6200 17:41:50.325609 RL = 0x2
6201 17:41:50.325928 BL = 0x2
6202 17:41:50.328604 RPST = 0x0
6203 17:41:50.328829 RD_PRE = 0x0
6204 17:41:50.331877 WR_PRE = 0x1
6205 17:41:50.332063 WR_PST = 0x0
6206 17:41:50.335217 DBI_WR = 0x0
6207 17:41:50.335490 DBI_RD = 0x0
6208 17:41:50.338691 OTF = 0x1
6209 17:41:50.342032 ===================================
6210 17:41:50.348455 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6211 17:41:50.352191 nWR fixed to 30
6212 17:41:50.352466 [ModeRegInit_LP4] CH0 RK0
6213 17:41:50.354958 [ModeRegInit_LP4] CH0 RK1
6214 17:41:50.358692 [ModeRegInit_LP4] CH1 RK0
6215 17:41:50.361995 [ModeRegInit_LP4] CH1 RK1
6216 17:41:50.362185 match AC timing 19
6217 17:41:50.365533 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6218 17:41:50.371978 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6219 17:41:50.375641 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6220 17:41:50.378935 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6221 17:41:50.385177 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6222 17:41:50.385329 ==
6223 17:41:50.388497 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 17:41:50.391961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 17:41:50.392114 ==
6226 17:41:50.398840 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 17:41:50.405470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6228 17:41:50.405669 [CA 0] Center 36 (8~64) winsize 57
6229 17:41:50.409192 [CA 1] Center 36 (8~64) winsize 57
6230 17:41:50.412051 [CA 2] Center 36 (8~64) winsize 57
6231 17:41:50.415425 [CA 3] Center 36 (8~64) winsize 57
6232 17:41:50.419083 [CA 4] Center 36 (8~64) winsize 57
6233 17:41:50.422261 [CA 5] Center 36 (8~64) winsize 57
6234 17:41:50.422583
6235 17:41:50.425002 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6236 17:41:50.425182
6237 17:41:50.428712 [CATrainingPosCal] consider 1 rank data
6238 17:41:50.431811 u2DelayCellTimex100 = 270/100 ps
6239 17:41:50.435392 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 17:41:50.438915 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 17:41:50.442114 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 17:41:50.448701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 17:41:50.452249 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 17:41:50.455666 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 17:41:50.455954
6246 17:41:50.459042 CA PerBit enable=1, Macro0, CA PI delay=36
6247 17:41:50.459369
6248 17:41:50.462482 [CBTSetCACLKResult] CA Dly = 36
6249 17:41:50.462961 CS Dly: 1 (0~32)
6250 17:41:50.463299 ==
6251 17:41:50.465598 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 17:41:50.472232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 17:41:50.472764 ==
6254 17:41:50.475405 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 17:41:50.482650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6256 17:41:50.485881 [CA 0] Center 36 (8~64) winsize 57
6257 17:41:50.489669 [CA 1] Center 36 (8~64) winsize 57
6258 17:41:50.492288 [CA 2] Center 36 (8~64) winsize 57
6259 17:41:50.496091 [CA 3] Center 36 (8~64) winsize 57
6260 17:41:50.499335 [CA 4] Center 36 (8~64) winsize 57
6261 17:41:50.502238 [CA 5] Center 36 (8~64) winsize 57
6262 17:41:50.502658
6263 17:41:50.505883 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6264 17:41:50.506300
6265 17:41:50.509621 [CATrainingPosCal] consider 2 rank data
6266 17:41:50.512845 u2DelayCellTimex100 = 270/100 ps
6267 17:41:50.515870 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 17:41:50.518838 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 17:41:50.522399 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 17:41:50.525839 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 17:41:50.529412 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 17:41:50.532315 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 17:41:50.532815
6274 17:41:50.539072 CA PerBit enable=1, Macro0, CA PI delay=36
6275 17:41:50.539530
6276 17:41:50.539867 [CBTSetCACLKResult] CA Dly = 36
6277 17:41:50.542299 CS Dly: 1 (0~32)
6278 17:41:50.542773
6279 17:41:50.545552 ----->DramcWriteLeveling(PI) begin...
6280 17:41:50.545999 ==
6281 17:41:50.549582 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 17:41:50.552913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 17:41:50.553354 ==
6284 17:41:50.556304 Write leveling (Byte 0): 40 => 8
6285 17:41:50.559283 Write leveling (Byte 1): 32 => 0
6286 17:41:50.562540 DramcWriteLeveling(PI) end<-----
6287 17:41:50.563201
6288 17:41:50.563733 ==
6289 17:41:50.565670 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 17:41:50.569430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 17:41:50.569864 ==
6292 17:41:50.572422 [Gating] SW mode calibration
6293 17:41:50.579546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6294 17:41:50.585733 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6295 17:41:50.589038 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 17:41:50.598472 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 17:41:50.599063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 17:41:50.602393 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 17:41:50.605755 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 17:41:50.612338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 17:41:50.616032 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 17:41:50.619041 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 17:41:50.626131 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 17:41:50.626311 Total UI for P1: 0, mck2ui 16
6305 17:41:50.632557 best dqsien dly found for B0: ( 0, 14, 24)
6306 17:41:50.632741 Total UI for P1: 0, mck2ui 16
6307 17:41:50.639394 best dqsien dly found for B1: ( 0, 14, 24)
6308 17:41:50.642245 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6309 17:41:50.646225 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6310 17:41:50.646316
6311 17:41:50.648923 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 17:41:50.652569 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 17:41:50.656103 [Gating] SW calibration Done
6314 17:41:50.656194 ==
6315 17:41:50.659126 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 17:41:50.662667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 17:41:50.663131 ==
6318 17:41:50.666396 RX Vref Scan: 0
6319 17:41:50.666856
6320 17:41:50.667190 RX Vref 0 -> 0, step: 1
6321 17:41:50.667496
6322 17:41:50.670135 RX Delay -410 -> 252, step: 16
6323 17:41:50.676547 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6324 17:41:50.679275 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6325 17:41:50.683065 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6326 17:41:50.686295 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6327 17:41:50.692656 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6328 17:41:50.696389 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6329 17:41:50.699416 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6330 17:41:50.702979 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6331 17:41:50.709170 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6332 17:41:50.712546 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6333 17:41:50.715796 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6334 17:41:50.719303 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6335 17:41:50.725592 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6336 17:41:50.729277 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6337 17:41:50.732596 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6338 17:41:50.735571 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6339 17:41:50.735779 ==
6340 17:41:50.739087 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 17:41:50.745690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 17:41:50.745858 ==
6343 17:41:50.745949 DQS Delay:
6344 17:41:50.749160 DQS0 = 35, DQS1 = 51
6345 17:41:50.749282 DQM Delay:
6346 17:41:50.749354 DQM0 = 6, DQM1 = 10
6347 17:41:50.752644 DQ Delay:
6348 17:41:50.755708 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6349 17:41:50.755813 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6350 17:41:50.759195 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6351 17:41:50.762316 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6352 17:41:50.762401
6353 17:41:50.762467
6354 17:41:50.765930 ==
6355 17:41:50.769278 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 17:41:50.772326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 17:41:50.772424 ==
6358 17:41:50.772490
6359 17:41:50.772550
6360 17:41:50.775978 TX Vref Scan disable
6361 17:41:50.776062 == TX Byte 0 ==
6362 17:41:50.779568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 17:41:50.785639 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 17:41:50.785727 == TX Byte 1 ==
6365 17:41:50.789233 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6366 17:41:50.796214 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6367 17:41:50.796411 ==
6368 17:41:50.799513 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 17:41:50.802567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 17:41:50.802686 ==
6371 17:41:50.802795
6372 17:41:50.802882
6373 17:41:50.806321 TX Vref Scan disable
6374 17:41:50.806480 == TX Byte 0 ==
6375 17:41:50.809265 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 17:41:50.815696 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 17:41:50.815785 == TX Byte 1 ==
6378 17:41:50.819385 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 17:41:50.825825 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 17:41:50.825933
6381 17:41:50.826007 [DATLAT]
6382 17:41:50.826075 Freq=400, CH0 RK0
6383 17:41:50.829582
6384 17:41:50.829676 DATLAT Default: 0xf
6385 17:41:50.832330 0, 0xFFFF, sum = 0
6386 17:41:50.832434 1, 0xFFFF, sum = 0
6387 17:41:50.836138 2, 0xFFFF, sum = 0
6388 17:41:50.836251 3, 0xFFFF, sum = 0
6389 17:41:50.839278 4, 0xFFFF, sum = 0
6390 17:41:50.839430 5, 0xFFFF, sum = 0
6391 17:41:50.842486 6, 0xFFFF, sum = 0
6392 17:41:50.842611 7, 0xFFFF, sum = 0
6393 17:41:50.846045 8, 0xFFFF, sum = 0
6394 17:41:50.846193 9, 0xFFFF, sum = 0
6395 17:41:50.849172 10, 0xFFFF, sum = 0
6396 17:41:50.849315 11, 0xFFFF, sum = 0
6397 17:41:50.852657 12, 0xFFFF, sum = 0
6398 17:41:50.852894 13, 0x0, sum = 1
6399 17:41:50.855858 14, 0x0, sum = 2
6400 17:41:50.856117 15, 0x0, sum = 3
6401 17:41:50.859414 16, 0x0, sum = 4
6402 17:41:50.859628 best_step = 14
6403 17:41:50.859771
6404 17:41:50.859900 ==
6405 17:41:50.862925 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 17:41:50.865992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 17:41:50.869813 ==
6408 17:41:50.870163 RX Vref Scan: 1
6409 17:41:50.870455
6410 17:41:50.873085 RX Vref 0 -> 0, step: 1
6411 17:41:50.873399
6412 17:41:50.876370 RX Delay -343 -> 252, step: 8
6413 17:41:50.876771
6414 17:41:50.879390 Set Vref, RX VrefLevel [Byte0]: 55
6415 17:41:50.882806 [Byte1]: 52
6416 17:41:50.883213
6417 17:41:50.886264 Final RX Vref Byte 0 = 55 to rank0
6418 17:41:50.889848 Final RX Vref Byte 1 = 52 to rank0
6419 17:41:50.893133 Final RX Vref Byte 0 = 55 to rank1
6420 17:41:50.896086 Final RX Vref Byte 1 = 52 to rank1==
6421 17:41:50.899397 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 17:41:50.902895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 17:41:50.903398 ==
6424 17:41:50.906209 DQS Delay:
6425 17:41:50.906595 DQS0 = 44, DQS1 = 60
6426 17:41:50.909735 DQM Delay:
6427 17:41:50.910122 DQM0 = 12, DQM1 = 16
6428 17:41:50.910427 DQ Delay:
6429 17:41:50.913282 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6430 17:41:50.916369 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6431 17:41:50.919948 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6432 17:41:50.922951 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =28
6433 17:41:50.923482
6434 17:41:50.923814
6435 17:41:50.933485 [DQSOSCAuto] RK0, (LSB)MR18= 0x8554, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6436 17:41:50.934017 CH0 RK0: MR19=C0C, MR18=8554
6437 17:41:50.940160 CH0_RK0: MR19=0xC0C, MR18=0x8554, DQSOSC=393, MR23=63, INC=382, DEC=254
6438 17:41:50.940600 ==
6439 17:41:50.943553 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 17:41:50.950087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 17:41:50.950530 ==
6442 17:41:50.951052 [Gating] SW mode calibration
6443 17:41:50.959634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6444 17:41:50.963172 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6445 17:41:50.966371 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 17:41:50.973027 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 17:41:50.976669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 17:41:50.979638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 17:41:50.986177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 17:41:50.989562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 17:41:50.992884 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 17:41:50.999964 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 17:41:51.002889 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 17:41:51.006151 Total UI for P1: 0, mck2ui 16
6455 17:41:51.010064 best dqsien dly found for B0: ( 0, 14, 24)
6456 17:41:51.013019 Total UI for P1: 0, mck2ui 16
6457 17:41:51.016295 best dqsien dly found for B1: ( 0, 14, 24)
6458 17:41:51.019931 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6459 17:41:51.023108 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6460 17:41:51.023193
6461 17:41:51.026519 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 17:41:51.029716 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 17:41:51.033060 [Gating] SW calibration Done
6464 17:41:51.033141 ==
6465 17:41:51.036624 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 17:41:51.039595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 17:41:51.043122 ==
6468 17:41:51.043205 RX Vref Scan: 0
6469 17:41:51.043269
6470 17:41:51.046916 RX Vref 0 -> 0, step: 1
6471 17:41:51.046998
6472 17:41:51.047062 RX Delay -410 -> 252, step: 16
6473 17:41:51.053339 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6474 17:41:51.056811 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6475 17:41:51.060359 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6476 17:41:51.063266 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6477 17:41:51.069808 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6478 17:41:51.073349 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6479 17:41:51.077101 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6480 17:41:51.079935 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6481 17:41:51.087319 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6482 17:41:51.090495 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6483 17:41:51.093435 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6484 17:41:51.097211 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6485 17:41:51.104060 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6486 17:41:51.107080 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6487 17:41:51.110650 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6488 17:41:51.116936 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6489 17:41:51.117452 ==
6490 17:41:51.120774 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 17:41:51.123732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 17:41:51.124160 ==
6493 17:41:51.124494 DQS Delay:
6494 17:41:51.127201 DQS0 = 51, DQS1 = 51
6495 17:41:51.127621 DQM Delay:
6496 17:41:51.130443 DQM0 = 18, DQM1 = 10
6497 17:41:51.130895 DQ Delay:
6498 17:41:51.133784 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6499 17:41:51.137157 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6500 17:41:51.140242 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6501 17:41:51.144157 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6502 17:41:51.144595
6503 17:41:51.144968
6504 17:41:51.145461 ==
6505 17:41:51.147264 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 17:41:51.150347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 17:41:51.150806 ==
6508 17:41:51.151152
6509 17:41:51.151459
6510 17:41:51.154273 TX Vref Scan disable
6511 17:41:51.154854 == TX Byte 0 ==
6512 17:41:51.160584 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6513 17:41:51.163878 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6514 17:41:51.164304 == TX Byte 1 ==
6515 17:41:51.170447 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6516 17:41:51.173680 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6517 17:41:51.174204 ==
6518 17:41:51.176967 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 17:41:51.180449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 17:41:51.180870 ==
6521 17:41:51.181202
6522 17:41:51.181507
6523 17:41:51.184476 TX Vref Scan disable
6524 17:41:51.185001 == TX Byte 0 ==
6525 17:41:51.190832 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6526 17:41:51.193568 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6527 17:41:51.193993 == TX Byte 1 ==
6528 17:41:51.200322 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6529 17:41:51.203846 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6530 17:41:51.204350
6531 17:41:51.204719 [DATLAT]
6532 17:41:51.207541 Freq=400, CH0 RK1
6533 17:41:51.207961
6534 17:41:51.208290 DATLAT Default: 0xe
6535 17:41:51.210586 0, 0xFFFF, sum = 0
6536 17:41:51.211059 1, 0xFFFF, sum = 0
6537 17:41:51.214084 2, 0xFFFF, sum = 0
6538 17:41:51.214508 3, 0xFFFF, sum = 0
6539 17:41:51.216921 4, 0xFFFF, sum = 0
6540 17:41:51.217350 5, 0xFFFF, sum = 0
6541 17:41:51.220595 6, 0xFFFF, sum = 0
6542 17:41:51.221171 7, 0xFFFF, sum = 0
6543 17:41:51.223808 8, 0xFFFF, sum = 0
6544 17:41:51.224234 9, 0xFFFF, sum = 0
6545 17:41:51.227529 10, 0xFFFF, sum = 0
6546 17:41:51.227957 11, 0xFFFF, sum = 0
6547 17:41:51.230761 12, 0xFFFF, sum = 0
6548 17:41:51.231194 13, 0x0, sum = 1
6549 17:41:51.234333 14, 0x0, sum = 2
6550 17:41:51.234798 15, 0x0, sum = 3
6551 17:41:51.236990 16, 0x0, sum = 4
6552 17:41:51.237446 best_step = 14
6553 17:41:51.237782
6554 17:41:51.238091 ==
6555 17:41:51.240628 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 17:41:51.247489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 17:41:51.248037 ==
6558 17:41:51.248377 RX Vref Scan: 0
6559 17:41:51.248690
6560 17:41:51.250592 RX Vref 0 -> 0, step: 1
6561 17:41:51.251048
6562 17:41:51.254020 RX Delay -343 -> 252, step: 8
6563 17:41:51.260795 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6564 17:41:51.264118 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6565 17:41:51.266977 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6566 17:41:51.270784 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6567 17:41:51.277509 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6568 17:41:51.280704 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6569 17:41:51.283699 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6570 17:41:51.287345 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6571 17:41:51.293833 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6572 17:41:51.297324 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6573 17:41:51.300129 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6574 17:41:51.303535 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6575 17:41:51.310567 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6576 17:41:51.313503 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6577 17:41:51.317028 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6578 17:41:51.320112 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6579 17:41:51.323699 ==
6580 17:41:51.326372 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 17:41:51.330079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 17:41:51.330224 ==
6583 17:41:51.330344 DQS Delay:
6584 17:41:51.333573 DQS0 = 48, DQS1 = 56
6585 17:41:51.333710 DQM Delay:
6586 17:41:51.337026 DQM0 = 13, DQM1 = 10
6587 17:41:51.337110 DQ Delay:
6588 17:41:51.339823 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6589 17:41:51.343512 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6590 17:41:51.347020 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6591 17:41:51.350072 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6592 17:41:51.350159
6593 17:41:51.350223
6594 17:41:51.356784 [DQSOSCAuto] RK1, (LSB)MR18= 0x9165, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6595 17:41:51.360306 CH0 RK1: MR19=C0C, MR18=9165
6596 17:41:51.366989 CH0_RK1: MR19=0xC0C, MR18=0x9165, DQSOSC=391, MR23=63, INC=386, DEC=257
6597 17:41:51.370517 [RxdqsGatingPostProcess] freq 400
6598 17:41:51.374023 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6599 17:41:51.376892 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 17:41:51.380491 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 17:41:51.384237 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 17:41:51.387042 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 17:41:51.390719 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 17:41:51.393868 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 17:41:51.397478 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 17:41:51.400245 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 17:41:51.403542 Pre-setting of DQS Precalculation
6608 17:41:51.407135 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6609 17:41:51.407367 ==
6610 17:41:51.410966 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 17:41:51.417448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 17:41:51.417672 ==
6613 17:41:51.420214 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 17:41:51.427018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 17:41:51.430417 [CA 0] Center 36 (8~64) winsize 57
6616 17:41:51.434363 [CA 1] Center 36 (8~64) winsize 57
6617 17:41:51.437124 [CA 2] Center 36 (8~64) winsize 57
6618 17:41:51.440337 [CA 3] Center 36 (8~64) winsize 57
6619 17:41:51.443753 [CA 4] Center 36 (8~64) winsize 57
6620 17:41:51.447226 [CA 5] Center 36 (8~64) winsize 57
6621 17:41:51.447651
6622 17:41:51.450447 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 17:41:51.451175
6624 17:41:51.453784 [CATrainingPosCal] consider 1 rank data
6625 17:41:51.457258 u2DelayCellTimex100 = 270/100 ps
6626 17:41:51.460665 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 17:41:51.463519 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 17:41:51.467143 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 17:41:51.470808 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 17:41:51.473835 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 17:41:51.477314 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 17:41:51.478017
6633 17:41:51.484032 CA PerBit enable=1, Macro0, CA PI delay=36
6634 17:41:51.484590
6635 17:41:51.485139 [CBTSetCACLKResult] CA Dly = 36
6636 17:41:51.487453 CS Dly: 1 (0~32)
6637 17:41:51.487873 ==
6638 17:41:51.490767 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 17:41:51.493909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 17:41:51.494343 ==
6641 17:41:51.500572 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 17:41:51.506837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 17:41:51.510451 [CA 0] Center 36 (8~64) winsize 57
6644 17:41:51.513545 [CA 1] Center 36 (8~64) winsize 57
6645 17:41:51.517401 [CA 2] Center 36 (8~64) winsize 57
6646 17:41:51.520371 [CA 3] Center 36 (8~64) winsize 57
6647 17:41:51.520798 [CA 4] Center 36 (8~64) winsize 57
6648 17:41:51.523718 [CA 5] Center 36 (8~64) winsize 57
6649 17:41:51.524143
6650 17:41:51.530594 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 17:41:51.531072
6652 17:41:51.533281 [CATrainingPosCal] consider 2 rank data
6653 17:41:51.536915 u2DelayCellTimex100 = 270/100 ps
6654 17:41:51.540303 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 17:41:51.543329 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 17:41:51.546877 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 17:41:51.550340 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 17:41:51.553379 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 17:41:51.556906 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 17:41:51.557345
6661 17:41:51.560735 CA PerBit enable=1, Macro0, CA PI delay=36
6662 17:41:51.561268
6663 17:41:51.563347 [CBTSetCACLKResult] CA Dly = 36
6664 17:41:51.566962 CS Dly: 1 (0~32)
6665 17:41:51.567467
6666 17:41:51.570382 ----->DramcWriteLeveling(PI) begin...
6667 17:41:51.570849 ==
6668 17:41:51.573677 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 17:41:51.576866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 17:41:51.577337 ==
6671 17:41:51.580004 Write leveling (Byte 0): 40 => 8
6672 17:41:51.583425 Write leveling (Byte 1): 40 => 8
6673 17:41:51.587111 DramcWriteLeveling(PI) end<-----
6674 17:41:51.587535
6675 17:41:51.587870 ==
6676 17:41:51.590337 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 17:41:51.593506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 17:41:51.593935 ==
6679 17:41:51.596812 [Gating] SW mode calibration
6680 17:41:51.603462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6681 17:41:51.610207 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6682 17:41:51.613470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 17:41:51.616581 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6684 17:41:51.623335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 17:41:51.626854 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 17:41:51.630077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 17:41:51.637023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 17:41:51.639952 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 17:41:51.643416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 17:41:51.650096 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 17:41:51.650520 Total UI for P1: 0, mck2ui 16
6692 17:41:51.654072 best dqsien dly found for B0: ( 0, 14, 24)
6693 17:41:51.657117 Total UI for P1: 0, mck2ui 16
6694 17:41:51.660568 best dqsien dly found for B1: ( 0, 14, 24)
6695 17:41:51.663399 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6696 17:41:51.670255 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6697 17:41:51.670840
6698 17:41:51.673896 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 17:41:51.676719 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 17:41:51.680253 [Gating] SW calibration Done
6701 17:41:51.680859 ==
6702 17:41:51.683935 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 17:41:51.686655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 17:41:51.687240 ==
6705 17:41:51.690505 RX Vref Scan: 0
6706 17:41:51.691122
6707 17:41:51.691656 RX Vref 0 -> 0, step: 1
6708 17:41:51.692150
6709 17:41:51.693412 RX Delay -410 -> 252, step: 16
6710 17:41:51.696789 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6711 17:41:51.703959 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6712 17:41:51.707024 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6713 17:41:51.710329 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6714 17:41:51.713603 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6715 17:41:51.720145 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6716 17:41:51.723637 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6717 17:41:51.727181 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6718 17:41:51.730096 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6719 17:41:51.736789 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6720 17:41:51.739936 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6721 17:41:51.743765 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6722 17:41:51.746785 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6723 17:41:51.753596 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6724 17:41:51.756864 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6725 17:41:51.760475 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6726 17:41:51.760881 ==
6727 17:41:51.763300 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 17:41:51.770070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 17:41:51.770469 ==
6730 17:41:51.770706 DQS Delay:
6731 17:41:51.770987 DQS0 = 51, DQS1 = 59
6732 17:41:51.773541 DQM Delay:
6733 17:41:51.773836 DQM0 = 19, DQM1 = 16
6734 17:41:51.777334 DQ Delay:
6735 17:41:51.780139 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6736 17:41:51.780522 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6737 17:41:51.783619 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6738 17:41:51.786932 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6739 17:41:51.787379
6740 17:41:51.790113
6741 17:41:51.790528 ==
6742 17:41:51.793734 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 17:41:51.797082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 17:41:51.797505 ==
6745 17:41:51.797831
6746 17:41:51.798133
6747 17:41:51.800451 TX Vref Scan disable
6748 17:41:51.800966 == TX Byte 0 ==
6749 17:41:51.803734 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 17:41:51.810482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 17:41:51.811069 == TX Byte 1 ==
6752 17:41:51.813590 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 17:41:51.820336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 17:41:51.820908 ==
6755 17:41:51.823433 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 17:41:51.826896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 17:41:51.827351 ==
6758 17:41:51.827812
6759 17:41:51.828124
6760 17:41:51.830212 TX Vref Scan disable
6761 17:41:51.830571 == TX Byte 0 ==
6762 17:41:51.833722 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 17:41:51.839853 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 17:41:51.840481 == TX Byte 1 ==
6765 17:41:51.843602 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 17:41:51.850145 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 17:41:51.850573
6768 17:41:51.851002 [DATLAT]
6769 17:41:51.851323 Freq=400, CH1 RK0
6770 17:41:51.851621
6771 17:41:51.853307 DATLAT Default: 0xf
6772 17:41:51.856954 0, 0xFFFF, sum = 0
6773 17:41:51.857374 1, 0xFFFF, sum = 0
6774 17:41:51.860494 2, 0xFFFF, sum = 0
6775 17:41:51.861060 3, 0xFFFF, sum = 0
6776 17:41:51.863602 4, 0xFFFF, sum = 0
6777 17:41:51.864068 5, 0xFFFF, sum = 0
6778 17:41:51.867003 6, 0xFFFF, sum = 0
6779 17:41:51.867429 7, 0xFFFF, sum = 0
6780 17:41:51.870475 8, 0xFFFF, sum = 0
6781 17:41:51.870943 9, 0xFFFF, sum = 0
6782 17:41:51.873380 10, 0xFFFF, sum = 0
6783 17:41:51.873805 11, 0xFFFF, sum = 0
6784 17:41:51.876646 12, 0xFFFF, sum = 0
6785 17:41:51.876944 13, 0x0, sum = 1
6786 17:41:51.880270 14, 0x0, sum = 2
6787 17:41:51.880569 15, 0x0, sum = 3
6788 17:41:51.883869 16, 0x0, sum = 4
6789 17:41:51.884169 best_step = 14
6790 17:41:51.884400
6791 17:41:51.884613 ==
6792 17:41:51.886780 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 17:41:51.890658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 17:41:51.891099 ==
6795 17:41:51.893677 RX Vref Scan: 1
6796 17:41:51.894069
6797 17:41:51.897287 RX Vref 0 -> 0, step: 1
6798 17:41:51.897776
6799 17:41:51.899979 RX Delay -359 -> 252, step: 8
6800 17:41:51.900275
6801 17:41:51.900507 Set Vref, RX VrefLevel [Byte0]: 57
6802 17:41:51.903737 [Byte1]: 46
6803 17:41:51.908923
6804 17:41:51.909240 Final RX Vref Byte 0 = 57 to rank0
6805 17:41:51.912300 Final RX Vref Byte 1 = 46 to rank0
6806 17:41:51.916119 Final RX Vref Byte 0 = 57 to rank1
6807 17:41:51.919198 Final RX Vref Byte 1 = 46 to rank1==
6808 17:41:51.922498 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 17:41:51.926241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 17:41:51.929689 ==
6811 17:41:51.930209 DQS Delay:
6812 17:41:51.930558 DQS0 = 48, DQS1 = 60
6813 17:41:51.932879 DQM Delay:
6814 17:41:51.933405 DQM0 = 12, DQM1 = 12
6815 17:41:51.935960 DQ Delay:
6816 17:41:51.939945 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6817 17:41:51.940366 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6818 17:41:51.942850 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6819 17:41:51.946393 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =16
6820 17:41:51.946956
6821 17:41:51.947290
6822 17:41:51.955832 [DQSOSCAuto] RK0, (LSB)MR18= 0x822a, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6823 17:41:51.959291 CH1 RK0: MR19=C0C, MR18=822A
6824 17:41:51.966132 CH1_RK0: MR19=0xC0C, MR18=0x822A, DQSOSC=393, MR23=63, INC=382, DEC=254
6825 17:41:51.966556 ==
6826 17:41:51.969637 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 17:41:51.972750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 17:41:51.973458 ==
6829 17:41:51.976336 [Gating] SW mode calibration
6830 17:41:51.982777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6831 17:41:51.986155 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6832 17:41:51.993038 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 17:41:51.996324 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6834 17:41:51.999539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 17:41:52.005951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 17:41:52.009710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 17:41:52.013005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 17:41:52.019478 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 17:41:52.022834 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 17:41:52.025865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 17:41:52.029829 Total UI for P1: 0, mck2ui 16
6842 17:41:52.032584 best dqsien dly found for B0: ( 0, 14, 24)
6843 17:41:52.036162 Total UI for P1: 0, mck2ui 16
6844 17:41:52.039453 best dqsien dly found for B1: ( 0, 14, 24)
6845 17:41:52.042828 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6846 17:41:52.046006 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6847 17:41:52.046426
6848 17:41:52.049465 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 17:41:52.055998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 17:41:52.056418 [Gating] SW calibration Done
6851 17:41:52.056745 ==
6852 17:41:52.059371 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 17:41:52.066292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 17:41:52.066717 ==
6855 17:41:52.067123 RX Vref Scan: 0
6856 17:41:52.067436
6857 17:41:52.069833 RX Vref 0 -> 0, step: 1
6858 17:41:52.070251
6859 17:41:52.072744 RX Delay -410 -> 252, step: 16
6860 17:41:52.076287 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6861 17:41:52.079829 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6862 17:41:52.086389 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6863 17:41:52.089544 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6864 17:41:52.092631 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6865 17:41:52.096284 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6866 17:41:52.103088 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6867 17:41:52.106134 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6868 17:41:52.109599 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6869 17:41:52.112665 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6870 17:41:52.120042 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6871 17:41:52.122708 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6872 17:41:52.126064 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6873 17:41:52.129357 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6874 17:41:52.136053 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6875 17:41:52.139782 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6876 17:41:52.140079 ==
6877 17:41:52.142606 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 17:41:52.145988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 17:41:52.146300 ==
6880 17:41:52.149424 DQS Delay:
6881 17:41:52.149723 DQS0 = 43, DQS1 = 51
6882 17:41:52.149958 DQM Delay:
6883 17:41:52.153445 DQM0 = 10, DQM1 = 9
6884 17:41:52.153743 DQ Delay:
6885 17:41:52.156142 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6886 17:41:52.159853 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6887 17:41:52.163030 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6888 17:41:52.166336 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6889 17:41:52.166637
6890 17:41:52.166909
6891 17:41:52.167133 ==
6892 17:41:52.169292 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 17:41:52.173221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 17:41:52.173522 ==
6895 17:41:52.173757
6896 17:41:52.176097
6897 17:41:52.176393 TX Vref Scan disable
6898 17:41:52.179787 == TX Byte 0 ==
6899 17:41:52.182748 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6900 17:41:52.186369 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6901 17:41:52.189478 == TX Byte 1 ==
6902 17:41:52.193177 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6903 17:41:52.196496 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6904 17:41:52.196807 ==
6905 17:41:52.199938 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 17:41:52.202711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 17:41:52.203051 ==
6908 17:41:52.203287
6909 17:41:52.206276
6910 17:41:52.206659 TX Vref Scan disable
6911 17:41:52.209528 == TX Byte 0 ==
6912 17:41:52.212656 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6913 17:41:52.216093 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6914 17:41:52.219616 == TX Byte 1 ==
6915 17:41:52.222804 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 17:41:52.226118 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 17:41:52.226537
6918 17:41:52.226927 [DATLAT]
6919 17:41:52.229719 Freq=400, CH1 RK1
6920 17:41:52.230217
6921 17:41:52.230589 DATLAT Default: 0xe
6922 17:41:52.233068 0, 0xFFFF, sum = 0
6923 17:41:52.233489 1, 0xFFFF, sum = 0
6924 17:41:52.236355 2, 0xFFFF, sum = 0
6925 17:41:52.236779 3, 0xFFFF, sum = 0
6926 17:41:52.239867 4, 0xFFFF, sum = 0
6927 17:41:52.242779 5, 0xFFFF, sum = 0
6928 17:41:52.243206 6, 0xFFFF, sum = 0
6929 17:41:52.246551 7, 0xFFFF, sum = 0
6930 17:41:52.247087 8, 0xFFFF, sum = 0
6931 17:41:52.249770 9, 0xFFFF, sum = 0
6932 17:41:52.250194 10, 0xFFFF, sum = 0
6933 17:41:52.253211 11, 0xFFFF, sum = 0
6934 17:41:52.253634 12, 0xFFFF, sum = 0
6935 17:41:52.256327 13, 0x0, sum = 1
6936 17:41:52.256749 14, 0x0, sum = 2
6937 17:41:52.259482 15, 0x0, sum = 3
6938 17:41:52.259803 16, 0x0, sum = 4
6939 17:41:52.263056 best_step = 14
6940 17:41:52.263349
6941 17:41:52.263580 ==
6942 17:41:52.266761 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 17:41:52.269469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 17:41:52.269769 ==
6945 17:41:52.269999 RX Vref Scan: 0
6946 17:41:52.270214
6947 17:41:52.273041 RX Vref 0 -> 0, step: 1
6948 17:41:52.273363
6949 17:41:52.276347 RX Delay -343 -> 252, step: 8
6950 17:41:52.283006 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6951 17:41:52.286979 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6952 17:41:52.290709 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6953 17:41:52.293625 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6954 17:41:52.300925 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6955 17:41:52.303617 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6956 17:41:52.306786 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6957 17:41:52.310281 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6958 17:41:52.316940 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6959 17:41:52.320288 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6960 17:41:52.323762 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6961 17:41:52.327425 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6962 17:41:52.333662 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6963 17:41:52.337424 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6964 17:41:52.340635 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6965 17:41:52.343928 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6966 17:41:52.346883 ==
6967 17:41:52.347587 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 17:41:52.353590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 17:41:52.354157 ==
6970 17:41:52.354719 DQS Delay:
6971 17:41:52.356659 DQS0 = 52, DQS1 = 60
6972 17:41:52.357211 DQM Delay:
6973 17:41:52.360381 DQM0 = 13, DQM1 = 14
6974 17:41:52.360978 DQ Delay:
6975 17:41:52.363741 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6976 17:41:52.367089 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6977 17:41:52.370591 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6978 17:41:52.373589 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6979 17:41:52.374013
6980 17:41:52.374346
6981 17:41:52.380294 [DQSOSCAuto] RK1, (LSB)MR18= 0x748b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6982 17:41:52.383615 CH1 RK1: MR19=C0C, MR18=748B
6983 17:41:52.390047 CH1_RK1: MR19=0xC0C, MR18=0x748B, DQSOSC=392, MR23=63, INC=384, DEC=256
6984 17:41:52.393672 [RxdqsGatingPostProcess] freq 400
6985 17:41:52.397036 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6986 17:41:52.400840 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 17:41:52.403843 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 17:41:52.406955 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 17:41:52.410898 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 17:41:52.414012 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 17:41:52.417134 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 17:41:52.420493 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 17:41:52.423620 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 17:41:52.426917 Pre-setting of DQS Precalculation
6995 17:41:52.430702 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6996 17:41:52.437309 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6997 17:41:52.446848 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6998 17:41:52.447268
6999 17:41:52.447595
7000 17:41:52.450280 [Calibration Summary] 800 Mbps
7001 17:41:52.450699 CH 0, Rank 0
7002 17:41:52.453724 SW Impedance : PASS
7003 17:41:52.454153 DUTY Scan : NO K
7004 17:41:52.457120 ZQ Calibration : PASS
7005 17:41:52.460151 Jitter Meter : NO K
7006 17:41:52.460569 CBT Training : PASS
7007 17:41:52.463751 Write leveling : PASS
7008 17:41:52.464167 RX DQS gating : PASS
7009 17:41:52.467214 RX DQ/DQS(RDDQC) : PASS
7010 17:41:52.470875 TX DQ/DQS : PASS
7011 17:41:52.471399 RX DATLAT : PASS
7012 17:41:52.473611 RX DQ/DQS(Engine): PASS
7013 17:41:52.477021 TX OE : NO K
7014 17:41:52.477438 All Pass.
7015 17:41:52.477765
7016 17:41:52.478066 CH 0, Rank 1
7017 17:41:52.480635 SW Impedance : PASS
7018 17:41:52.483641 DUTY Scan : NO K
7019 17:41:52.484058 ZQ Calibration : PASS
7020 17:41:52.487289 Jitter Meter : NO K
7021 17:41:52.490418 CBT Training : PASS
7022 17:41:52.490529 Write leveling : NO K
7023 17:41:52.493415 RX DQS gating : PASS
7024 17:41:52.496950 RX DQ/DQS(RDDQC) : PASS
7025 17:41:52.497031 TX DQ/DQS : PASS
7026 17:41:52.500173 RX DATLAT : PASS
7027 17:41:52.500339 RX DQ/DQS(Engine): PASS
7028 17:41:52.503738 TX OE : NO K
7029 17:41:52.503899 All Pass.
7030 17:41:52.503975
7031 17:41:52.507112 CH 1, Rank 0
7032 17:41:52.507219 SW Impedance : PASS
7033 17:41:52.509826 DUTY Scan : NO K
7034 17:41:52.513463 ZQ Calibration : PASS
7035 17:41:52.513552 Jitter Meter : NO K
7036 17:41:52.516612 CBT Training : PASS
7037 17:41:52.519900 Write leveling : PASS
7038 17:41:52.520009 RX DQS gating : PASS
7039 17:41:52.523380 RX DQ/DQS(RDDQC) : PASS
7040 17:41:52.526954 TX DQ/DQS : PASS
7041 17:41:52.527076 RX DATLAT : PASS
7042 17:41:52.530340 RX DQ/DQS(Engine): PASS
7043 17:41:52.533382 TX OE : NO K
7044 17:41:52.533517 All Pass.
7045 17:41:52.533623
7046 17:41:52.533721 CH 1, Rank 1
7047 17:41:52.536991 SW Impedance : PASS
7048 17:41:52.540544 DUTY Scan : NO K
7049 17:41:52.540716 ZQ Calibration : PASS
7050 17:41:52.544027 Jitter Meter : NO K
7051 17:41:52.544199 CBT Training : PASS
7052 17:41:52.546835 Write leveling : NO K
7053 17:41:52.550304 RX DQS gating : PASS
7054 17:41:52.550617 RX DQ/DQS(RDDQC) : PASS
7055 17:41:52.553575 TX DQ/DQS : PASS
7056 17:41:52.557204 RX DATLAT : PASS
7057 17:41:52.557590 RX DQ/DQS(Engine): PASS
7058 17:41:52.560940 TX OE : NO K
7059 17:41:52.561326 All Pass.
7060 17:41:52.561629
7061 17:41:52.563870 DramC Write-DBI off
7062 17:41:52.567350 PER_BANK_REFRESH: Hybrid Mode
7063 17:41:52.567866 TX_TRACKING: ON
7064 17:41:52.577179 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7065 17:41:52.580612 [FAST_K] Save calibration result to emmc
7066 17:41:52.584407 dramc_set_vcore_voltage set vcore to 725000
7067 17:41:52.587683 Read voltage for 1600, 0
7068 17:41:52.588104 Vio18 = 0
7069 17:41:52.588563 Vcore = 725000
7070 17:41:52.590642 Vdram = 0
7071 17:41:52.591090 Vddq = 0
7072 17:41:52.591418 Vmddr = 0
7073 17:41:52.597703 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7074 17:41:52.601290 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7075 17:41:52.604467 MEM_TYPE=3, freq_sel=13
7076 17:41:52.607530 sv_algorithm_assistance_LP4_3733
7077 17:41:52.610678 ============ PULL DRAM RESETB DOWN ============
7078 17:41:52.613955 ========== PULL DRAM RESETB DOWN end =========
7079 17:41:52.620796 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7080 17:41:52.624161 ===================================
7081 17:41:52.624681 LPDDR4 DRAM CONFIGURATION
7082 17:41:52.627757 ===================================
7083 17:41:52.631161 EX_ROW_EN[0] = 0x0
7084 17:41:52.631673 EX_ROW_EN[1] = 0x0
7085 17:41:52.634088 LP4Y_EN = 0x0
7086 17:41:52.637478 WORK_FSP = 0x1
7087 17:41:52.637897 WL = 0x5
7088 17:41:52.640882 RL = 0x5
7089 17:41:52.641297 BL = 0x2
7090 17:41:52.644427 RPST = 0x0
7091 17:41:52.644842 RD_PRE = 0x0
7092 17:41:52.647862 WR_PRE = 0x1
7093 17:41:52.648156 WR_PST = 0x1
7094 17:41:52.650795 DBI_WR = 0x0
7095 17:41:52.651095 DBI_RD = 0x0
7096 17:41:52.654116 OTF = 0x1
7097 17:41:52.657466 ===================================
7098 17:41:52.660565 ===================================
7099 17:41:52.660861 ANA top config
7100 17:41:52.664391 ===================================
7101 17:41:52.668268 DLL_ASYNC_EN = 0
7102 17:41:52.670895 ALL_SLAVE_EN = 0
7103 17:41:52.671203 NEW_RANK_MODE = 1
7104 17:41:52.674469 DLL_IDLE_MODE = 1
7105 17:41:52.677732 LP45_APHY_COMB_EN = 1
7106 17:41:52.680976 TX_ODT_DIS = 0
7107 17:41:52.681434 NEW_8X_MODE = 1
7108 17:41:52.684559 ===================================
7109 17:41:52.688306 ===================================
7110 17:41:52.691684 data_rate = 3200
7111 17:41:52.694351 CKR = 1
7112 17:41:52.698338 DQ_P2S_RATIO = 8
7113 17:41:52.701484 ===================================
7114 17:41:52.705052 CA_P2S_RATIO = 8
7115 17:41:52.707580 DQ_CA_OPEN = 0
7116 17:41:52.708000 DQ_SEMI_OPEN = 0
7117 17:41:52.711110 CA_SEMI_OPEN = 0
7118 17:41:52.715093 CA_FULL_RATE = 0
7119 17:41:52.717708 DQ_CKDIV4_EN = 0
7120 17:41:52.721490 CA_CKDIV4_EN = 0
7121 17:41:52.724503 CA_PREDIV_EN = 0
7122 17:41:52.724955 PH8_DLY = 12
7123 17:41:52.727610 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7124 17:41:52.731018 DQ_AAMCK_DIV = 4
7125 17:41:52.734615 CA_AAMCK_DIV = 4
7126 17:41:52.737896 CA_ADMCK_DIV = 4
7127 17:41:52.740856 DQ_TRACK_CA_EN = 0
7128 17:41:52.741276 CA_PICK = 1600
7129 17:41:52.744192 CA_MCKIO = 1600
7130 17:41:52.747833 MCKIO_SEMI = 0
7131 17:41:52.750785 PLL_FREQ = 3068
7132 17:41:52.754313 DQ_UI_PI_RATIO = 32
7133 17:41:52.757560 CA_UI_PI_RATIO = 0
7134 17:41:52.760731 ===================================
7135 17:41:52.763990 ===================================
7136 17:41:52.767208 memory_type:LPDDR4
7137 17:41:52.767523 GP_NUM : 10
7138 17:41:52.770569 SRAM_EN : 1
7139 17:41:52.770818 MD32_EN : 0
7140 17:41:52.773893 ===================================
7141 17:41:52.777268 [ANA_INIT] >>>>>>>>>>>>>>
7142 17:41:52.780814 <<<<<< [CONFIGURE PHASE]: ANA_TX
7143 17:41:52.783694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7144 17:41:52.787060 ===================================
7145 17:41:52.790673 data_rate = 3200,PCW = 0X7600
7146 17:41:52.793691 ===================================
7147 17:41:52.797186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7148 17:41:52.801110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 17:41:52.807188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 17:41:52.814191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7151 17:41:52.817258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7152 17:41:52.820650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7153 17:41:52.821073 [ANA_INIT] flow start
7154 17:41:52.824155 [ANA_INIT] PLL >>>>>>>>
7155 17:41:52.827056 [ANA_INIT] PLL <<<<<<<<
7156 17:41:52.827478 [ANA_INIT] MIDPI >>>>>>>>
7157 17:41:52.830792 [ANA_INIT] MIDPI <<<<<<<<
7158 17:41:52.834115 [ANA_INIT] DLL >>>>>>>>
7159 17:41:52.834625 [ANA_INIT] DLL <<<<<<<<
7160 17:41:52.837088 [ANA_INIT] flow end
7161 17:41:52.840626 ============ LP4 DIFF to SE enter ============
7162 17:41:52.844143 ============ LP4 DIFF to SE exit ============
7163 17:41:52.848074 [ANA_INIT] <<<<<<<<<<<<<
7164 17:41:52.850819 [Flow] Enable top DCM control >>>>>
7165 17:41:52.853764 [Flow] Enable top DCM control <<<<<
7166 17:41:52.857001 Enable DLL master slave shuffle
7167 17:41:52.863585 ==============================================================
7168 17:41:52.864125 Gating Mode config
7169 17:41:52.870435 ==============================================================
7170 17:41:52.870935 Config description:
7171 17:41:52.880671 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7172 17:41:52.887253 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7173 17:41:52.893496 SELPH_MODE 0: By rank 1: By Phase
7174 17:41:52.897332 ==============================================================
7175 17:41:52.900427 GAT_TRACK_EN = 1
7176 17:41:52.903807 RX_GATING_MODE = 2
7177 17:41:52.907229 RX_GATING_TRACK_MODE = 2
7178 17:41:52.910252 SELPH_MODE = 1
7179 17:41:52.913712 PICG_EARLY_EN = 1
7180 17:41:52.916774 VALID_LAT_VALUE = 1
7181 17:41:52.923592 ==============================================================
7182 17:41:52.926990 Enter into Gating configuration >>>>
7183 17:41:52.930485 Exit from Gating configuration <<<<
7184 17:41:52.930714 Enter into DVFS_PRE_config >>>>>
7185 17:41:52.943639 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7186 17:41:52.947441 Exit from DVFS_PRE_config <<<<<
7187 17:41:52.950406 Enter into PICG configuration >>>>
7188 17:41:52.953693 Exit from PICG configuration <<<<
7189 17:41:52.954118 [RX_INPUT] configuration >>>>>
7190 17:41:52.957489 [RX_INPUT] configuration <<<<<
7191 17:41:52.963722 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7192 17:41:52.967104 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7193 17:41:52.973960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 17:41:52.980175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 17:41:52.987676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 17:41:52.993878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 17:41:52.997214 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7198 17:41:53.000575 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7199 17:41:53.003647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7200 17:41:53.010867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7201 17:41:53.013929 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7202 17:41:53.016629 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 17:41:53.020249 ===================================
7204 17:41:53.023655 LPDDR4 DRAM CONFIGURATION
7205 17:41:53.026853 ===================================
7206 17:41:53.030082 EX_ROW_EN[0] = 0x0
7207 17:41:53.030380 EX_ROW_EN[1] = 0x0
7208 17:41:53.033698 LP4Y_EN = 0x0
7209 17:41:53.033977 WORK_FSP = 0x1
7210 17:41:53.036973 WL = 0x5
7211 17:41:53.037182 RL = 0x5
7212 17:41:53.040245 BL = 0x2
7213 17:41:53.040426 RPST = 0x0
7214 17:41:53.043270 RD_PRE = 0x0
7215 17:41:53.043521 WR_PRE = 0x1
7216 17:41:53.046481 WR_PST = 0x1
7217 17:41:53.046633 DBI_WR = 0x0
7218 17:41:53.050057 DBI_RD = 0x0
7219 17:41:53.050245 OTF = 0x1
7220 17:41:53.053289 ===================================
7221 17:41:53.059882 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7222 17:41:53.063404 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7223 17:41:53.066636 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 17:41:53.070392 ===================================
7225 17:41:53.073225 LPDDR4 DRAM CONFIGURATION
7226 17:41:53.077015 ===================================
7227 17:41:53.077240 EX_ROW_EN[0] = 0x10
7228 17:41:53.080085 EX_ROW_EN[1] = 0x0
7229 17:41:53.083989 LP4Y_EN = 0x0
7230 17:41:53.084266 WORK_FSP = 0x1
7231 17:41:53.086893 WL = 0x5
7232 17:41:53.087162 RL = 0x5
7233 17:41:53.090374 BL = 0x2
7234 17:41:53.090775 RPST = 0x0
7235 17:41:53.094099 RD_PRE = 0x0
7236 17:41:53.094460 WR_PRE = 0x1
7237 17:41:53.097021 WR_PST = 0x1
7238 17:41:53.097385 DBI_WR = 0x0
7239 17:41:53.100493 DBI_RD = 0x0
7240 17:41:53.100900 OTF = 0x1
7241 17:41:53.104003 ===================================
7242 17:41:53.110256 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7243 17:41:53.110826 ==
7244 17:41:53.113967 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 17:41:53.117336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7246 17:41:53.120134 ==
7247 17:41:53.120674 [Duty_Offset_Calibration]
7248 17:41:53.123607 B0:2 B1:-1 CA:1
7249 17:41:53.124190
7250 17:41:53.126694 [DutyScan_Calibration_Flow] k_type=0
7251 17:41:53.134680
7252 17:41:53.135141 ==CLK 0==
7253 17:41:53.137994 Final CLK duty delay cell = -4
7254 17:41:53.141288 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7255 17:41:53.144652 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7256 17:41:53.147962 [-4] AVG Duty = 4937%(X100)
7257 17:41:53.148262
7258 17:41:53.151634 CH0 CLK Duty spec in!! Max-Min= 187%
7259 17:41:53.154650 [DutyScan_Calibration_Flow] ====Done====
7260 17:41:53.154906
7261 17:41:53.157637 [DutyScan_Calibration_Flow] k_type=1
7262 17:41:53.174073
7263 17:41:53.174243 ==DQS 0 ==
7264 17:41:53.177349 Final DQS duty delay cell = 0
7265 17:41:53.180571 [0] MAX Duty = 5125%(X100), DQS PI = 20
7266 17:41:53.184156 [0] MIN Duty = 5000%(X100), DQS PI = 14
7267 17:41:53.184289 [0] AVG Duty = 5062%(X100)
7268 17:41:53.187180
7269 17:41:53.187312 ==DQS 1 ==
7270 17:41:53.190419 Final DQS duty delay cell = -4
7271 17:41:53.193967 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7272 17:41:53.197528 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7273 17:41:53.200523 [-4] AVG Duty = 5062%(X100)
7274 17:41:53.200616
7275 17:41:53.204023 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7276 17:41:53.204108
7277 17:41:53.207067 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7278 17:41:53.210601 [DutyScan_Calibration_Flow] ====Done====
7279 17:41:53.210682
7280 17:41:53.213759 [DutyScan_Calibration_Flow] k_type=3
7281 17:41:53.231264
7282 17:41:53.231371 ==DQM 0 ==
7283 17:41:53.235028 Final DQM duty delay cell = 0
7284 17:41:53.237981 [0] MAX Duty = 5000%(X100), DQS PI = 18
7285 17:41:53.241241 [0] MIN Duty = 4875%(X100), DQS PI = 6
7286 17:41:53.241325 [0] AVG Duty = 4937%(X100)
7287 17:41:53.244577
7288 17:41:53.244659 ==DQM 1 ==
7289 17:41:53.247905 Final DQM duty delay cell = 0
7290 17:41:53.251208 [0] MAX Duty = 5187%(X100), DQS PI = 58
7291 17:41:53.254614 [0] MIN Duty = 4938%(X100), DQS PI = 20
7292 17:41:53.254705 [0] AVG Duty = 5062%(X100)
7293 17:41:53.258194
7294 17:41:53.261022 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7295 17:41:53.261100
7296 17:41:53.265003 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7297 17:41:53.267962 [DutyScan_Calibration_Flow] ====Done====
7298 17:41:53.268044
7299 17:41:53.271524 [DutyScan_Calibration_Flow] k_type=2
7300 17:41:53.288216
7301 17:41:53.288357 ==DQ 0 ==
7302 17:41:53.291464 Final DQ duty delay cell = 0
7303 17:41:53.294629 [0] MAX Duty = 5156%(X100), DQS PI = 0
7304 17:41:53.298336 [0] MIN Duty = 5031%(X100), DQS PI = 12
7305 17:41:53.298444 [0] AVG Duty = 5093%(X100)
7306 17:41:53.298536
7307 17:41:53.301753 ==DQ 1 ==
7308 17:41:53.305036 Final DQ duty delay cell = 0
7309 17:41:53.307954 [0] MAX Duty = 5031%(X100), DQS PI = 30
7310 17:41:53.311604 [0] MIN Duty = 4907%(X100), DQS PI = 18
7311 17:41:53.311687 [0] AVG Duty = 4969%(X100)
7312 17:41:53.311751
7313 17:41:53.315120 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7314 17:41:53.318409
7315 17:41:53.321239 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7316 17:41:53.324657 [DutyScan_Calibration_Flow] ====Done====
7317 17:41:53.324739 ==
7318 17:41:53.328345 Dram Type= 6, Freq= 0, CH_1, rank 0
7319 17:41:53.332103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 17:41:53.332185 ==
7321 17:41:53.335023 [Duty_Offset_Calibration]
7322 17:41:53.335105 B0:1 B1:1 CA:2
7323 17:41:53.335169
7324 17:41:53.338353 [DutyScan_Calibration_Flow] k_type=0
7325 17:41:53.348564
7326 17:41:53.348652 ==CLK 0==
7327 17:41:53.352068 Final CLK duty delay cell = 0
7328 17:41:53.355001 [0] MAX Duty = 5187%(X100), DQS PI = 24
7329 17:41:53.358451 [0] MIN Duty = 4938%(X100), DQS PI = 56
7330 17:41:53.358533 [0] AVG Duty = 5062%(X100)
7331 17:41:53.361802
7332 17:41:53.361883 CH1 CLK Duty spec in!! Max-Min= 249%
7333 17:41:53.368897 [DutyScan_Calibration_Flow] ====Done====
7334 17:41:53.368982
7335 17:41:53.371645 [DutyScan_Calibration_Flow] k_type=1
7336 17:41:53.388224
7337 17:41:53.388345 ==DQS 0 ==
7338 17:41:53.391701 Final DQS duty delay cell = 0
7339 17:41:53.394679 [0] MAX Duty = 5062%(X100), DQS PI = 20
7340 17:41:53.398146 [0] MIN Duty = 4813%(X100), DQS PI = 52
7341 17:41:53.401692 [0] AVG Duty = 4937%(X100)
7342 17:41:53.401777
7343 17:41:53.401841 ==DQS 1 ==
7344 17:41:53.404497 Final DQS duty delay cell = 0
7345 17:41:53.408072 [0] MAX Duty = 5062%(X100), DQS PI = 56
7346 17:41:53.411866 [0] MIN Duty = 4938%(X100), DQS PI = 12
7347 17:41:53.411971 [0] AVG Duty = 5000%(X100)
7348 17:41:53.414894
7349 17:41:53.418581 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7350 17:41:53.418663
7351 17:41:53.421342 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7352 17:41:53.424620 [DutyScan_Calibration_Flow] ====Done====
7353 17:41:53.424701
7354 17:41:53.428293 [DutyScan_Calibration_Flow] k_type=3
7355 17:41:53.445109
7356 17:41:53.445220 ==DQM 0 ==
7357 17:41:53.448594 Final DQM duty delay cell = 0
7358 17:41:53.451970 [0] MAX Duty = 5156%(X100), DQS PI = 18
7359 17:41:53.454746 [0] MIN Duty = 4813%(X100), DQS PI = 52
7360 17:41:53.454845 [0] AVG Duty = 4984%(X100)
7361 17:41:53.458532
7362 17:41:53.458614 ==DQM 1 ==
7363 17:41:53.461544 Final DQM duty delay cell = 0
7364 17:41:53.464939 [0] MAX Duty = 5156%(X100), DQS PI = 60
7365 17:41:53.468599 [0] MIN Duty = 4875%(X100), DQS PI = 20
7366 17:41:53.472062 [0] AVG Duty = 5015%(X100)
7367 17:41:53.472144
7368 17:41:53.474841 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7369 17:41:53.474923
7370 17:41:53.478152 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7371 17:41:53.481434 [DutyScan_Calibration_Flow] ====Done====
7372 17:41:53.481516
7373 17:41:53.485310 [DutyScan_Calibration_Flow] k_type=2
7374 17:41:53.501793
7375 17:41:53.501895 ==DQ 0 ==
7376 17:41:53.505188 Final DQ duty delay cell = 0
7377 17:41:53.508522 [0] MAX Duty = 5156%(X100), DQS PI = 20
7378 17:41:53.512206 [0] MIN Duty = 4907%(X100), DQS PI = 52
7379 17:41:53.512310 [0] AVG Duty = 5031%(X100)
7380 17:41:53.514974
7381 17:41:53.515053 ==DQ 1 ==
7382 17:41:53.518211 Final DQ duty delay cell = 0
7383 17:41:53.521625 [0] MAX Duty = 5093%(X100), DQS PI = 6
7384 17:41:53.525292 [0] MIN Duty = 5031%(X100), DQS PI = 0
7385 17:41:53.525365 [0] AVG Duty = 5062%(X100)
7386 17:41:53.525429
7387 17:41:53.528234 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7388 17:41:53.531703
7389 17:41:53.531816 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7390 17:41:53.538337 [DutyScan_Calibration_Flow] ====Done====
7391 17:41:53.541558 nWR fixed to 30
7392 17:41:53.541640 [ModeRegInit_LP4] CH0 RK0
7393 17:41:53.545164 [ModeRegInit_LP4] CH0 RK1
7394 17:41:53.548722 [ModeRegInit_LP4] CH1 RK0
7395 17:41:53.548806 [ModeRegInit_LP4] CH1 RK1
7396 17:41:53.551591 match AC timing 5
7397 17:41:53.554711 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7398 17:41:53.558226 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7399 17:41:53.565150 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7400 17:41:53.568352 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7401 17:41:53.574733 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7402 17:41:53.574817 [MiockJmeterHQA]
7403 17:41:53.574882
7404 17:41:53.578352 [DramcMiockJmeter] u1RxGatingPI = 0
7405 17:41:53.581547 0 : 4363, 4137
7406 17:41:53.581632 4 : 4368, 4139
7407 17:41:53.581699 8 : 4255, 4029
7408 17:41:53.584780 12 : 4366, 4139
7409 17:41:53.584865 16 : 4253, 4026
7410 17:41:53.588397 20 : 4253, 4026
7411 17:41:53.588480 24 : 4257, 4029
7412 17:41:53.591277 28 : 4254, 4029
7413 17:41:53.591361 32 : 4365, 4140
7414 17:41:53.591426 36 : 4254, 4029
7415 17:41:53.594615 40 : 4255, 4029
7416 17:41:53.594698 44 : 4255, 4029
7417 17:41:53.598260 48 : 4363, 4137
7418 17:41:53.598343 52 : 4363, 4137
7419 17:41:53.601591 56 : 4363, 4137
7420 17:41:53.601675 60 : 4252, 4027
7421 17:41:53.604918 64 : 4252, 4027
7422 17:41:53.605001 68 : 4252, 4030
7423 17:41:53.605067 72 : 4250, 4027
7424 17:41:53.608259 76 : 4250, 4027
7425 17:41:53.608342 80 : 4363, 4140
7426 17:41:53.611915 84 : 4365, 4140
7427 17:41:53.611999 88 : 4253, 4029
7428 17:41:53.614641 92 : 4255, 4029
7429 17:41:53.614730 96 : 4250, 3368
7430 17:41:53.614797 100 : 4255, 0
7431 17:41:53.618238 104 : 4250, 0
7432 17:41:53.618321 108 : 4361, 0
7433 17:41:53.621739 112 : 4361, 0
7434 17:41:53.621822 116 : 4255, 0
7435 17:41:53.621887 120 : 4250, 0
7436 17:41:53.625072 124 : 4255, 0
7437 17:41:53.625155 128 : 4250, 0
7438 17:41:53.628186 132 : 4250, 0
7439 17:41:53.628270 136 : 4257, 0
7440 17:41:53.628336 140 : 4250, 0
7441 17:41:53.631581 144 : 4249, 0
7442 17:41:53.631671 148 : 4363, 0
7443 17:41:53.635068 152 : 4250, 0
7444 17:41:53.635180 156 : 4249, 0
7445 17:41:53.635250 160 : 4255, 0
7446 17:41:53.638203 164 : 4361, 0
7447 17:41:53.638314 168 : 4360, 0
7448 17:41:53.638412 172 : 4365, 0
7449 17:41:53.641471 176 : 4249, 0
7450 17:41:53.641580 180 : 4250, 0
7451 17:41:53.645441 184 : 4255, 0
7452 17:41:53.645521 188 : 4257, 0
7453 17:41:53.645601 192 : 4250, 0
7454 17:41:53.648301 196 : 4366, 0
7455 17:41:53.648375 200 : 4365, 0
7456 17:41:53.651502 204 : 4250, 0
7457 17:41:53.651574 208 : 4360, 0
7458 17:41:53.651634 212 : 4254, 82
7459 17:41:53.654889 216 : 4252, 3621
7460 17:41:53.654971 220 : 4250, 4026
7461 17:41:53.658399 224 : 4255, 4029
7462 17:41:53.658481 228 : 4249, 4027
7463 17:41:53.661612 232 : 4361, 4137
7464 17:41:53.661724 236 : 4363, 4138
7465 17:41:53.664983 240 : 4363, 4140
7466 17:41:53.665105 244 : 4249, 4027
7467 17:41:53.668363 248 : 4252, 4030
7468 17:41:53.668449 252 : 4363, 4140
7469 17:41:53.668520 256 : 4250, 4027
7470 17:41:53.671779 260 : 4255, 4029
7471 17:41:53.671862 264 : 4252, 4030
7472 17:41:53.675025 268 : 4252, 4027
7473 17:41:53.675107 272 : 4252, 4029
7474 17:41:53.678221 276 : 4366, 4142
7475 17:41:53.678303 280 : 4365, 4140
7476 17:41:53.681459 284 : 4249, 4027
7477 17:41:53.681548 288 : 4361, 4137
7478 17:41:53.685206 292 : 4255, 4029
7479 17:41:53.685302 296 : 4250, 4027
7480 17:41:53.688494 300 : 4252, 4030
7481 17:41:53.688589 304 : 4250, 4027
7482 17:41:53.691304 308 : 4255, 4030
7483 17:41:53.691408 312 : 4253, 4029
7484 17:41:53.691489 316 : 4249, 4027
7485 17:41:53.694970 320 : 4253, 4029
7486 17:41:53.695160 324 : 4360, 4138
7487 17:41:53.698361 328 : 4366, 4140
7488 17:41:53.698550 332 : 4255, 3124
7489 17:41:53.701635 336 : 4250, 29
7490 17:41:53.701837
7491 17:41:53.701943 MIOCK jitter meter ch=0
7492 17:41:53.705035
7493 17:41:53.705249 1T = (336-100) = 236 dly cells
7494 17:41:53.711910 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7495 17:41:53.712129 ==
7496 17:41:53.715557 Dram Type= 6, Freq= 0, CH_0, rank 0
7497 17:41:53.718481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 17:41:53.718747 ==
7499 17:41:53.725044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 17:41:53.728826 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 17:41:53.735238 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 17:41:53.738979 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 17:41:53.748904 [CA 0] Center 44 (14~75) winsize 62
7504 17:41:53.751929 [CA 1] Center 44 (14~74) winsize 61
7505 17:41:53.755221 [CA 2] Center 39 (10~68) winsize 59
7506 17:41:53.758442 [CA 3] Center 39 (10~68) winsize 59
7507 17:41:53.761925 [CA 4] Center 37 (7~67) winsize 61
7508 17:41:53.765473 [CA 5] Center 37 (7~67) winsize 61
7509 17:41:53.766012
7510 17:41:53.768605 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 17:41:53.769204
7512 17:41:53.772383 [CATrainingPosCal] consider 1 rank data
7513 17:41:53.775200 u2DelayCellTimex100 = 275/100 ps
7514 17:41:53.778438 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7515 17:41:53.785820 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7516 17:41:53.788839 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7517 17:41:53.792447 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7518 17:41:53.795290 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7519 17:41:53.798925 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7520 17:41:53.799348
7521 17:41:53.802466 CA PerBit enable=1, Macro0, CA PI delay=37
7522 17:41:53.803027
7523 17:41:53.805508 [CBTSetCACLKResult] CA Dly = 37
7524 17:41:53.808552 CS Dly: 10 (0~41)
7525 17:41:53.811706 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 17:41:53.815411 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 17:41:53.815833 ==
7528 17:41:53.818788 Dram Type= 6, Freq= 0, CH_0, rank 1
7529 17:41:53.821860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 17:41:53.825533 ==
7531 17:41:53.828983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 17:41:53.832177 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 17:41:53.838802 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 17:41:53.842493 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 17:41:53.852430 [CA 0] Center 44 (14~75) winsize 62
7536 17:41:53.855778 [CA 1] Center 44 (14~75) winsize 62
7537 17:41:53.859070 [CA 2] Center 40 (11~69) winsize 59
7538 17:41:53.862756 [CA 3] Center 39 (10~69) winsize 60
7539 17:41:53.866081 [CA 4] Center 38 (8~68) winsize 61
7540 17:41:53.868935 [CA 5] Center 37 (7~67) winsize 61
7541 17:41:53.869362
7542 17:41:53.872235 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 17:41:53.872660
7544 17:41:53.875623 [CATrainingPosCal] consider 2 rank data
7545 17:41:53.878952 u2DelayCellTimex100 = 275/100 ps
7546 17:41:53.882399 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7547 17:41:53.889165 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7548 17:41:53.892428 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7549 17:41:53.895979 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7550 17:41:53.899431 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7551 17:41:53.902223 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7552 17:41:53.902866
7553 17:41:53.905632 CA PerBit enable=1, Macro0, CA PI delay=37
7554 17:41:53.906055
7555 17:41:53.909706 [CBTSetCACLKResult] CA Dly = 37
7556 17:41:53.912599 CS Dly: 11 (0~43)
7557 17:41:53.915713 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 17:41:53.919043 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 17:41:53.919728
7560 17:41:53.922578 ----->DramcWriteLeveling(PI) begin...
7561 17:41:53.923076 ==
7562 17:41:53.925542 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 17:41:53.929255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 17:41:53.932492 ==
7565 17:41:53.932927 Write leveling (Byte 0): 33 => 33
7566 17:41:53.935991 Write leveling (Byte 1): 26 => 26
7567 17:41:53.939246 DramcWriteLeveling(PI) end<-----
7568 17:41:53.939914
7569 17:41:53.940210 ==
7570 17:41:53.942581 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 17:41:53.949355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 17:41:53.949640 ==
7573 17:41:53.952278 [Gating] SW mode calibration
7574 17:41:53.958613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7575 17:41:53.962003 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7576 17:41:53.968846 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 17:41:53.972550 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 17:41:53.975386 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 17:41:53.981889 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 17:41:53.985329 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7581 17:41:53.989174 1 4 20 | B1->B0 | 2322 3333 | 1 1 | (0 0) (1 1)
7582 17:41:53.992135 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7583 17:41:53.998780 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 17:41:54.001682 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 17:41:54.005407 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 17:41:54.012123 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 17:41:54.015285 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 17:41:54.018106 1 5 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7589 17:41:54.024993 1 5 20 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 1)
7590 17:41:54.028666 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7591 17:41:54.031540 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 17:41:54.038743 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 17:41:54.042332 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 17:41:54.045175 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 17:41:54.051728 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 17:41:54.055447 1 6 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7597 17:41:54.058610 1 6 20 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
7598 17:41:54.065354 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7599 17:41:54.068634 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 17:41:54.071985 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 17:41:54.078710 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 17:41:54.081952 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 17:41:54.085709 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 17:41:54.092164 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 17:41:54.095322 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7606 17:41:54.099082 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7607 17:41:54.105487 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 17:41:54.108966 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 17:41:54.111713 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 17:41:54.115405 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 17:41:54.122358 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 17:41:54.125532 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 17:41:54.128720 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 17:41:54.135235 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 17:41:54.139054 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 17:41:54.142065 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 17:41:54.148927 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 17:41:54.152140 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 17:41:54.155367 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 17:41:54.161776 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7621 17:41:54.165338 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 17:41:54.168756 Total UI for P1: 0, mck2ui 16
7623 17:41:54.172281 best dqsien dly found for B0: ( 1, 9, 14)
7624 17:41:54.175232 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7625 17:41:54.178423 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 17:41:54.182056 Total UI for P1: 0, mck2ui 16
7627 17:41:54.185445 best dqsien dly found for B1: ( 1, 9, 22)
7628 17:41:54.192108 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7629 17:41:54.195411 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7630 17:41:54.195693
7631 17:41:54.198620 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7632 17:41:54.202032 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7633 17:41:54.205000 [Gating] SW calibration Done
7634 17:41:54.205228 ==
7635 17:41:54.208598 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 17:41:54.212280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 17:41:54.212558 ==
7638 17:41:54.215597 RX Vref Scan: 0
7639 17:41:54.215964
7640 17:41:54.216194 RX Vref 0 -> 0, step: 1
7641 17:41:54.216401
7642 17:41:54.218560 RX Delay 0 -> 252, step: 8
7643 17:41:54.222411 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7644 17:41:54.225967 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7645 17:41:54.232081 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7646 17:41:54.236178 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7647 17:41:54.239319 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7648 17:41:54.242680 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7649 17:41:54.245397 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7650 17:41:54.252922 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7651 17:41:54.255719 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7652 17:41:54.258899 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7653 17:41:54.262194 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7654 17:41:54.265823 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7655 17:41:54.272257 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7656 17:41:54.275641 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7657 17:41:54.279208 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7658 17:41:54.282030 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7659 17:41:54.282596 ==
7660 17:41:54.285397 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 17:41:54.289144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 17:41:54.292699 ==
7663 17:41:54.293119 DQS Delay:
7664 17:41:54.293450 DQS0 = 0, DQS1 = 0
7665 17:41:54.295418 DQM Delay:
7666 17:41:54.295837 DQM0 = 132, DQM1 = 125
7667 17:41:54.298882 DQ Delay:
7668 17:41:54.302334 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7669 17:41:54.305461 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7670 17:41:54.308924 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7671 17:41:54.312282 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7672 17:41:54.312583
7673 17:41:54.312819
7674 17:41:54.313037 ==
7675 17:41:54.315386 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 17:41:54.318897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 17:41:54.319292 ==
7678 17:41:54.319544
7679 17:41:54.319766
7680 17:41:54.322327 TX Vref Scan disable
7681 17:41:54.326044 == TX Byte 0 ==
7682 17:41:54.328841 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7683 17:41:54.332607 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7684 17:41:54.335573 == TX Byte 1 ==
7685 17:41:54.339120 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7686 17:41:54.342230 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7687 17:41:54.342609 ==
7688 17:41:54.345469 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 17:41:54.352214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 17:41:54.352519 ==
7691 17:41:54.365750
7692 17:41:54.369306 TX Vref early break, caculate TX vref
7693 17:41:54.372252 TX Vref=16, minBit 8, minWin=21, winSum=360
7694 17:41:54.375841 TX Vref=18, minBit 2, minWin=22, winSum=368
7695 17:41:54.379405 TX Vref=20, minBit 0, minWin=23, winSum=379
7696 17:41:54.382950 TX Vref=22, minBit 0, minWin=24, winSum=392
7697 17:41:54.385774 TX Vref=24, minBit 8, minWin=24, winSum=401
7698 17:41:54.392686 TX Vref=26, minBit 8, minWin=24, winSum=411
7699 17:41:54.395793 TX Vref=28, minBit 0, minWin=25, winSum=414
7700 17:41:54.399478 TX Vref=30, minBit 0, minWin=25, winSum=416
7701 17:41:54.402575 TX Vref=32, minBit 13, minWin=24, winSum=408
7702 17:41:54.405940 TX Vref=34, minBit 9, minWin=23, winSum=398
7703 17:41:54.408905 TX Vref=36, minBit 9, minWin=23, winSum=389
7704 17:41:54.415858 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
7705 17:41:54.416288
7706 17:41:54.418989 Final TX Range 0 Vref 30
7707 17:41:54.419417
7708 17:41:54.419746 ==
7709 17:41:54.422517 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 17:41:54.425881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 17:41:54.426308 ==
7712 17:41:54.426639
7713 17:41:54.426991
7714 17:41:54.428882 TX Vref Scan disable
7715 17:41:54.435792 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7716 17:41:54.436220 == TX Byte 0 ==
7717 17:41:54.439213 u2DelayCellOfst[0]=17 cells (5 PI)
7718 17:41:54.442454 u2DelayCellOfst[1]=21 cells (6 PI)
7719 17:41:54.445545 u2DelayCellOfst[2]=10 cells (3 PI)
7720 17:41:54.448763 u2DelayCellOfst[3]=17 cells (5 PI)
7721 17:41:54.452201 u2DelayCellOfst[4]=10 cells (3 PI)
7722 17:41:54.455457 u2DelayCellOfst[5]=0 cells (0 PI)
7723 17:41:54.458940 u2DelayCellOfst[6]=21 cells (6 PI)
7724 17:41:54.462564 u2DelayCellOfst[7]=21 cells (6 PI)
7725 17:41:54.465343 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7726 17:41:54.468671 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7727 17:41:54.472326 == TX Byte 1 ==
7728 17:41:54.475643 u2DelayCellOfst[8]=0 cells (0 PI)
7729 17:41:54.475802 u2DelayCellOfst[9]=0 cells (0 PI)
7730 17:41:54.478458 u2DelayCellOfst[10]=7 cells (2 PI)
7731 17:41:54.481830 u2DelayCellOfst[11]=0 cells (0 PI)
7732 17:41:54.485321 u2DelayCellOfst[12]=10 cells (3 PI)
7733 17:41:54.488866 u2DelayCellOfst[13]=10 cells (3 PI)
7734 17:41:54.492011 u2DelayCellOfst[14]=14 cells (4 PI)
7735 17:41:54.495099 u2DelayCellOfst[15]=10 cells (3 PI)
7736 17:41:54.498570 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7737 17:41:54.505657 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7738 17:41:54.505822 DramC Write-DBI on
7739 17:41:54.505898 ==
7740 17:41:54.508813 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 17:41:54.515145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 17:41:54.515298 ==
7743 17:41:54.515378
7744 17:41:54.515447
7745 17:41:54.515511 TX Vref Scan disable
7746 17:41:54.519444 == TX Byte 0 ==
7747 17:41:54.523051 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7748 17:41:54.525939 == TX Byte 1 ==
7749 17:41:54.529441 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7750 17:41:54.529623 DramC Write-DBI off
7751 17:41:54.532908
7752 17:41:54.533082 [DATLAT]
7753 17:41:54.533180 Freq=1600, CH0 RK0
7754 17:41:54.533280
7755 17:41:54.536442 DATLAT Default: 0xf
7756 17:41:54.536625 0, 0xFFFF, sum = 0
7757 17:41:54.539272 1, 0xFFFF, sum = 0
7758 17:41:54.539458 2, 0xFFFF, sum = 0
7759 17:41:54.542922 3, 0xFFFF, sum = 0
7760 17:41:54.543115 4, 0xFFFF, sum = 0
7761 17:41:54.546211 5, 0xFFFF, sum = 0
7762 17:41:54.549004 6, 0xFFFF, sum = 0
7763 17:41:54.549167 7, 0xFFFF, sum = 0
7764 17:41:54.552487 8, 0xFFFF, sum = 0
7765 17:41:54.552631 9, 0xFFFF, sum = 0
7766 17:41:54.556029 10, 0xFFFF, sum = 0
7767 17:41:54.556191 11, 0xFFFF, sum = 0
7768 17:41:54.559108 12, 0xFFFF, sum = 0
7769 17:41:54.559270 13, 0xFFFF, sum = 0
7770 17:41:54.562822 14, 0x0, sum = 1
7771 17:41:54.563011 15, 0x0, sum = 2
7772 17:41:54.566062 16, 0x0, sum = 3
7773 17:41:54.566279 17, 0x0, sum = 4
7774 17:41:54.569774 best_step = 15
7775 17:41:54.570083
7776 17:41:54.570298 ==
7777 17:41:54.573278 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 17:41:54.576339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 17:41:54.576780 ==
7780 17:41:54.577068 RX Vref Scan: 1
7781 17:41:54.577313
7782 17:41:54.579378 Set Vref Range= 24 -> 127
7783 17:41:54.579708
7784 17:41:54.582957 RX Vref 24 -> 127, step: 1
7785 17:41:54.583376
7786 17:41:54.586642 RX Delay 11 -> 252, step: 4
7787 17:41:54.587089
7788 17:41:54.589561 Set Vref, RX VrefLevel [Byte0]: 24
7789 17:41:54.593322 [Byte1]: 24
7790 17:41:54.593741
7791 17:41:54.596725 Set Vref, RX VrefLevel [Byte0]: 25
7792 17:41:54.599569 [Byte1]: 25
7793 17:41:54.599989
7794 17:41:54.603306 Set Vref, RX VrefLevel [Byte0]: 26
7795 17:41:54.606561 [Byte1]: 26
7796 17:41:54.609945
7797 17:41:54.610465 Set Vref, RX VrefLevel [Byte0]: 27
7798 17:41:54.613346 [Byte1]: 27
7799 17:41:54.617521
7800 17:41:54.617942 Set Vref, RX VrefLevel [Byte0]: 28
7801 17:41:54.621025 [Byte1]: 28
7802 17:41:54.625627
7803 17:41:54.626144 Set Vref, RX VrefLevel [Byte0]: 29
7804 17:41:54.628168 [Byte1]: 29
7805 17:41:54.632745
7806 17:41:54.633165 Set Vref, RX VrefLevel [Byte0]: 30
7807 17:41:54.636833 [Byte1]: 30
7808 17:41:54.640539
7809 17:41:54.641055 Set Vref, RX VrefLevel [Byte0]: 31
7810 17:41:54.643363 [Byte1]: 31
7811 17:41:54.648126
7812 17:41:54.648547 Set Vref, RX VrefLevel [Byte0]: 32
7813 17:41:54.651473 [Byte1]: 32
7814 17:41:54.655428
7815 17:41:54.655847 Set Vref, RX VrefLevel [Byte0]: 33
7816 17:41:54.659121 [Byte1]: 33
7817 17:41:54.662918
7818 17:41:54.663336 Set Vref, RX VrefLevel [Byte0]: 34
7819 17:41:54.666165 [Byte1]: 34
7820 17:41:54.670793
7821 17:41:54.671337 Set Vref, RX VrefLevel [Byte0]: 35
7822 17:41:54.674632 [Byte1]: 35
7823 17:41:54.678562
7824 17:41:54.679157 Set Vref, RX VrefLevel [Byte0]: 36
7825 17:41:54.681874 [Byte1]: 36
7826 17:41:54.686297
7827 17:41:54.686865 Set Vref, RX VrefLevel [Byte0]: 37
7828 17:41:54.689585 [Byte1]: 37
7829 17:41:54.694223
7830 17:41:54.694787 Set Vref, RX VrefLevel [Byte0]: 38
7831 17:41:54.697525 [Byte1]: 38
7832 17:41:54.701504
7833 17:41:54.702024 Set Vref, RX VrefLevel [Byte0]: 39
7834 17:41:54.704633 [Byte1]: 39
7835 17:41:54.708989
7836 17:41:54.709506 Set Vref, RX VrefLevel [Byte0]: 40
7837 17:41:54.712131 [Byte1]: 40
7838 17:41:54.716914
7839 17:41:54.717432 Set Vref, RX VrefLevel [Byte0]: 41
7840 17:41:54.720374 [Byte1]: 41
7841 17:41:54.724479
7842 17:41:54.724997 Set Vref, RX VrefLevel [Byte0]: 42
7843 17:41:54.727842 [Byte1]: 42
7844 17:41:54.732148
7845 17:41:54.732668 Set Vref, RX VrefLevel [Byte0]: 43
7846 17:41:54.734866 [Byte1]: 43
7847 17:41:54.739566
7848 17:41:54.740107 Set Vref, RX VrefLevel [Byte0]: 44
7849 17:41:54.742577 [Byte1]: 44
7850 17:41:54.746985
7851 17:41:54.747503 Set Vref, RX VrefLevel [Byte0]: 45
7852 17:41:54.750311 [Byte1]: 45
7853 17:41:54.754484
7854 17:41:54.755085 Set Vref, RX VrefLevel [Byte0]: 46
7855 17:41:54.757847 [Byte1]: 46
7856 17:41:54.762805
7857 17:41:54.763328 Set Vref, RX VrefLevel [Byte0]: 47
7858 17:41:54.765383 [Byte1]: 47
7859 17:41:54.769901
7860 17:41:54.770323 Set Vref, RX VrefLevel [Byte0]: 48
7861 17:41:54.772834 [Byte1]: 48
7862 17:41:54.777279
7863 17:41:54.777704 Set Vref, RX VrefLevel [Byte0]: 49
7864 17:41:54.780454 [Byte1]: 49
7865 17:41:54.785049
7866 17:41:54.785470 Set Vref, RX VrefLevel [Byte0]: 50
7867 17:41:54.788496 [Byte1]: 50
7868 17:41:54.792994
7869 17:41:54.793510 Set Vref, RX VrefLevel [Byte0]: 51
7870 17:41:54.796158 [Byte1]: 51
7871 17:41:54.800214
7872 17:41:54.800661 Set Vref, RX VrefLevel [Byte0]: 52
7873 17:41:54.803941 [Byte1]: 52
7874 17:41:54.808108
7875 17:41:54.808623 Set Vref, RX VrefLevel [Byte0]: 53
7876 17:41:54.811337 [Byte1]: 53
7877 17:41:54.815380
7878 17:41:54.815893 Set Vref, RX VrefLevel [Byte0]: 54
7879 17:41:54.818981 [Byte1]: 54
7880 17:41:54.822877
7881 17:41:54.823392 Set Vref, RX VrefLevel [Byte0]: 55
7882 17:41:54.826560 [Byte1]: 55
7883 17:41:54.830595
7884 17:41:54.831164 Set Vref, RX VrefLevel [Byte0]: 56
7885 17:41:54.834129 [Byte1]: 56
7886 17:41:54.838317
7887 17:41:54.838886 Set Vref, RX VrefLevel [Byte0]: 57
7888 17:41:54.842034 [Byte1]: 57
7889 17:41:54.846035
7890 17:41:54.846597 Set Vref, RX VrefLevel [Byte0]: 58
7891 17:41:54.848920 [Byte1]: 58
7892 17:41:54.853820
7893 17:41:54.854368 Set Vref, RX VrefLevel [Byte0]: 59
7894 17:41:54.856518 [Byte1]: 59
7895 17:41:54.861186
7896 17:41:54.861609 Set Vref, RX VrefLevel [Byte0]: 60
7897 17:41:54.864551 [Byte1]: 60
7898 17:41:54.868912
7899 17:41:54.869336 Set Vref, RX VrefLevel [Byte0]: 61
7900 17:41:54.871987 [Byte1]: 61
7901 17:41:54.875830
7902 17:41:54.875913 Set Vref, RX VrefLevel [Byte0]: 62
7903 17:41:54.879209 [Byte1]: 62
7904 17:41:54.883889
7905 17:41:54.883970 Set Vref, RX VrefLevel [Byte0]: 63
7906 17:41:54.886986 [Byte1]: 63
7907 17:41:54.891020
7908 17:41:54.891102 Set Vref, RX VrefLevel [Byte0]: 64
7909 17:41:54.894267 [Byte1]: 64
7910 17:41:54.898707
7911 17:41:54.898796 Set Vref, RX VrefLevel [Byte0]: 65
7912 17:41:54.901825 [Byte1]: 65
7913 17:41:54.906295
7914 17:41:54.906378 Set Vref, RX VrefLevel [Byte0]: 66
7915 17:41:54.909455 [Byte1]: 66
7916 17:41:54.914210
7917 17:41:54.914295 Set Vref, RX VrefLevel [Byte0]: 67
7918 17:41:54.917008 [Byte1]: 67
7919 17:41:54.921536
7920 17:41:54.921624 Set Vref, RX VrefLevel [Byte0]: 68
7921 17:41:54.924936 [Byte1]: 68
7922 17:41:54.929467
7923 17:41:54.929549 Set Vref, RX VrefLevel [Byte0]: 69
7924 17:41:54.932563 [Byte1]: 69
7925 17:41:54.936687
7926 17:41:54.936774 Set Vref, RX VrefLevel [Byte0]: 70
7927 17:41:54.939874 [Byte1]: 70
7928 17:41:54.944463
7929 17:41:54.944545 Set Vref, RX VrefLevel [Byte0]: 71
7930 17:41:54.947450 [Byte1]: 71
7931 17:41:54.951773
7932 17:41:54.951856 Set Vref, RX VrefLevel [Byte0]: 72
7933 17:41:54.955325 [Byte1]: 72
7934 17:41:54.959575
7935 17:41:54.959657 Set Vref, RX VrefLevel [Byte0]: 73
7936 17:41:54.962761 [Byte1]: 73
7937 17:41:54.966986
7938 17:41:54.967069 Set Vref, RX VrefLevel [Byte0]: 74
7939 17:41:54.970613 [Byte1]: 74
7940 17:41:54.974996
7941 17:41:54.975078 Set Vref, RX VrefLevel [Byte0]: 75
7942 17:41:54.978363 [Byte1]: 75
7943 17:41:54.982501
7944 17:41:54.982583 Set Vref, RX VrefLevel [Byte0]: 76
7945 17:41:54.985947 [Byte1]: 76
7946 17:41:54.989758
7947 17:41:54.989840 Final RX Vref Byte 0 = 63 to rank0
7948 17:41:54.993193 Final RX Vref Byte 1 = 63 to rank0
7949 17:41:54.996767 Final RX Vref Byte 0 = 63 to rank1
7950 17:41:55.000073 Final RX Vref Byte 1 = 63 to rank1==
7951 17:41:55.003261 Dram Type= 6, Freq= 0, CH_0, rank 0
7952 17:41:55.009972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 17:41:55.010056 ==
7954 17:41:55.010121 DQS Delay:
7955 17:41:55.010180 DQS0 = 0, DQS1 = 0
7956 17:41:55.013204 DQM Delay:
7957 17:41:55.013286 DQM0 = 129, DQM1 = 122
7958 17:41:55.016988 DQ Delay:
7959 17:41:55.019898 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7960 17:41:55.023110 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7961 17:41:55.026755 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7962 17:41:55.030119 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
7963 17:41:55.030201
7964 17:41:55.030265
7965 17:41:55.030324
7966 17:41:55.033566 [DramC_TX_OE_Calibration] TA2
7967 17:41:55.036490 Original DQ_B0 (3 6) =30, OEN = 27
7968 17:41:55.039902 Original DQ_B1 (3 6) =30, OEN = 27
7969 17:41:55.043623 24, 0x0, End_B0=24 End_B1=24
7970 17:41:55.043706 25, 0x0, End_B0=25 End_B1=25
7971 17:41:55.046663 26, 0x0, End_B0=26 End_B1=26
7972 17:41:55.050283 27, 0x0, End_B0=27 End_B1=27
7973 17:41:55.053197 28, 0x0, End_B0=28 End_B1=28
7974 17:41:55.053280 29, 0x0, End_B0=29 End_B1=29
7975 17:41:55.056939 30, 0x0, End_B0=30 End_B1=30
7976 17:41:55.059920 31, 0x4141, End_B0=30 End_B1=30
7977 17:41:55.063354 Byte0 end_step=30 best_step=27
7978 17:41:55.066811 Byte1 end_step=30 best_step=27
7979 17:41:55.070100 Byte0 TX OE(2T, 0.5T) = (3, 3)
7980 17:41:55.070183 Byte1 TX OE(2T, 0.5T) = (3, 3)
7981 17:41:55.070247
7982 17:41:55.070307
7983 17:41:55.080042 [DQSOSCAuto] RK0, (LSB)MR18= 0x1004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 401 ps
7984 17:41:55.083827 CH0 RK0: MR19=303, MR18=1004
7985 17:41:55.087434 CH0_RK0: MR19=0x303, MR18=0x1004, DQSOSC=401, MR23=63, INC=22, DEC=15
7986 17:41:55.090421
7987 17:41:55.093651 ----->DramcWriteLeveling(PI) begin...
7988 17:41:55.093747 ==
7989 17:41:55.097003 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 17:41:55.100964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 17:41:55.101154 ==
7992 17:41:55.103684 Write leveling (Byte 0): 33 => 33
7993 17:41:55.106710 Write leveling (Byte 1): 25 => 25
7994 17:41:55.110637 DramcWriteLeveling(PI) end<-----
7995 17:41:55.110867
7996 17:41:55.111026 ==
7997 17:41:55.114264 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 17:41:55.117318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 17:41:55.117552 ==
8000 17:41:55.120484 [Gating] SW mode calibration
8001 17:41:55.126986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8002 17:41:55.133740 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8003 17:41:55.137283 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 17:41:55.140752 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 17:41:55.148190 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8006 17:41:55.150683 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8007 17:41:55.154392 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8008 17:41:55.157244 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8009 17:41:55.164254 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 17:41:55.167732 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 17:41:55.171188 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 17:41:55.177522 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 17:41:55.181531 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8014 17:41:55.184069 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
8015 17:41:55.191418 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8016 17:41:55.194657 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
8017 17:41:55.197520 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8018 17:41:55.204386 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 17:41:55.207164 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 17:41:55.211090 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 17:41:55.217559 1 6 8 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
8022 17:41:55.220771 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8023 17:41:55.223709 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8024 17:41:55.230891 1 6 20 | B1->B0 | 3231 4646 | 1 0 | (0 0) (0 0)
8025 17:41:55.233983 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 17:41:55.237379 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 17:41:55.243967 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 17:41:55.247530 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 17:41:55.250935 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8030 17:41:55.254104 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 17:41:55.261330 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 17:41:55.264020 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 17:41:55.267306 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 17:41:55.274278 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 17:41:55.277527 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 17:41:55.280607 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 17:41:55.287337 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 17:41:55.291229 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 17:41:55.294698 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 17:41:55.300817 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 17:41:55.304455 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 17:41:55.307397 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 17:41:55.314253 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 17:41:55.317946 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 17:41:55.321595 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 17:41:55.327358 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8047 17:41:55.327933 Total UI for P1: 0, mck2ui 16
8048 17:41:55.331128 best dqsien dly found for B0: ( 1, 9, 8)
8049 17:41:55.337214 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 17:41:55.341123 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 17:41:55.344097 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 17:41:55.350398 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 17:41:55.353861 Total UI for P1: 0, mck2ui 16
8054 17:41:55.357145 best dqsien dly found for B1: ( 1, 9, 20)
8055 17:41:55.361268 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8056 17:41:55.363753 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8057 17:41:55.364171
8058 17:41:55.367266 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8059 17:41:55.370980 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8060 17:41:55.374612 [Gating] SW calibration Done
8061 17:41:55.375192 ==
8062 17:41:55.377530 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 17:41:55.380529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 17:41:55.380951 ==
8065 17:41:55.384104 RX Vref Scan: 0
8066 17:41:55.384524
8067 17:41:55.384852 RX Vref 0 -> 0, step: 1
8068 17:41:55.387546
8069 17:41:55.387963 RX Delay 0 -> 252, step: 8
8070 17:41:55.390787 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8071 17:41:55.397216 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8072 17:41:55.401118 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8073 17:41:55.404110 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8074 17:41:55.407533 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8075 17:41:55.411192 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8076 17:41:55.417532 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8077 17:41:55.420880 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8078 17:41:55.423972 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8079 17:41:55.427379 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8080 17:41:55.431081 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8081 17:41:55.437363 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8082 17:41:55.440758 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8083 17:41:55.443957 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8084 17:41:55.447184 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8085 17:41:55.450474 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8086 17:41:55.454112 ==
8087 17:41:55.457488 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 17:41:55.460793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 17:41:55.461324 ==
8090 17:41:55.461656 DQS Delay:
8091 17:41:55.464001 DQS0 = 0, DQS1 = 0
8092 17:41:55.464416 DQM Delay:
8093 17:41:55.467250 DQM0 = 131, DQM1 = 124
8094 17:41:55.467667 DQ Delay:
8095 17:41:55.471060 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8096 17:41:55.474073 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8097 17:41:55.477877 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8098 17:41:55.480919 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8099 17:41:55.481443
8100 17:41:55.481777
8101 17:41:55.482081 ==
8102 17:41:55.484212 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 17:41:55.490804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 17:41:55.491342 ==
8105 17:41:55.491683
8106 17:41:55.491990
8107 17:41:55.492284 TX Vref Scan disable
8108 17:41:55.494002 == TX Byte 0 ==
8109 17:41:55.497485 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8110 17:41:55.501339 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8111 17:41:55.504727 == TX Byte 1 ==
8112 17:41:55.507608 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8113 17:41:55.510810 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8114 17:41:55.514681 ==
8115 17:41:55.517309 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 17:41:55.520845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 17:41:55.521273 ==
8118 17:41:55.535663
8119 17:41:55.539179 TX Vref early break, caculate TX vref
8120 17:41:55.542157 TX Vref=16, minBit 8, minWin=22, winSum=372
8121 17:41:55.545674 TX Vref=18, minBit 9, minWin=22, winSum=378
8122 17:41:55.549005 TX Vref=20, minBit 8, minWin=23, winSum=392
8123 17:41:55.551795 TX Vref=22, minBit 8, minWin=23, winSum=396
8124 17:41:55.555697 TX Vref=24, minBit 9, minWin=24, winSum=407
8125 17:41:55.561962 TX Vref=26, minBit 3, minWin=25, winSum=416
8126 17:41:55.565478 TX Vref=28, minBit 10, minWin=25, winSum=419
8127 17:41:55.568457 TX Vref=30, minBit 4, minWin=25, winSum=419
8128 17:41:55.572178 TX Vref=32, minBit 1, minWin=25, winSum=412
8129 17:41:55.575209 TX Vref=34, minBit 4, minWin=24, winSum=400
8130 17:41:55.578472 TX Vref=36, minBit 13, minWin=23, winSum=391
8131 17:41:55.585277 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 28
8132 17:41:55.585707
8133 17:41:55.588902 Final TX Range 0 Vref 28
8134 17:41:55.589323
8135 17:41:55.589651 ==
8136 17:41:55.591656 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 17:41:55.595012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 17:41:55.595435 ==
8139 17:41:55.595766
8140 17:41:55.598628
8141 17:41:55.599082 TX Vref Scan disable
8142 17:41:55.605532 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8143 17:41:55.605963 == TX Byte 0 ==
8144 17:41:55.608383 u2DelayCellOfst[0]=10 cells (3 PI)
8145 17:41:55.612047 u2DelayCellOfst[1]=17 cells (5 PI)
8146 17:41:55.619407 u2DelayCellOfst[2]=7 cells (2 PI)
8147 17:41:55.619845 u2DelayCellOfst[3]=10 cells (3 PI)
8148 17:41:55.621707 u2DelayCellOfst[4]=7 cells (2 PI)
8149 17:41:55.625677 u2DelayCellOfst[5]=0 cells (0 PI)
8150 17:41:55.628829 u2DelayCellOfst[6]=17 cells (5 PI)
8151 17:41:55.632483 u2DelayCellOfst[7]=17 cells (5 PI)
8152 17:41:55.634914 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8153 17:41:55.638594 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8154 17:41:55.642288 == TX Byte 1 ==
8155 17:41:55.645294 u2DelayCellOfst[8]=0 cells (0 PI)
8156 17:41:55.648641 u2DelayCellOfst[9]=0 cells (0 PI)
8157 17:41:55.649175 u2DelayCellOfst[10]=3 cells (1 PI)
8158 17:41:55.651913 u2DelayCellOfst[11]=0 cells (0 PI)
8159 17:41:55.654902 u2DelayCellOfst[12]=10 cells (3 PI)
8160 17:41:55.658193 u2DelayCellOfst[13]=10 cells (3 PI)
8161 17:41:55.661844 u2DelayCellOfst[14]=14 cells (4 PI)
8162 17:41:55.665257 u2DelayCellOfst[15]=10 cells (3 PI)
8163 17:41:55.668977 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8164 17:41:55.675547 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8165 17:41:55.676093 DramC Write-DBI on
8166 17:41:55.676432 ==
8167 17:41:55.678581 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 17:41:55.685346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 17:41:55.685885 ==
8170 17:41:55.686242
8171 17:41:55.686554
8172 17:41:55.686884 TX Vref Scan disable
8173 17:41:55.688932 == TX Byte 0 ==
8174 17:41:55.692663 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8175 17:41:55.695646 == TX Byte 1 ==
8176 17:41:55.699186 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8177 17:41:55.702612 DramC Write-DBI off
8178 17:41:55.703215
8179 17:41:55.703557 [DATLAT]
8180 17:41:55.703865 Freq=1600, CH0 RK1
8181 17:41:55.704165
8182 17:41:55.705287 DATLAT Default: 0xf
8183 17:41:55.705707 0, 0xFFFF, sum = 0
8184 17:41:55.709201 1, 0xFFFF, sum = 0
8185 17:41:55.709628 2, 0xFFFF, sum = 0
8186 17:41:55.712815 3, 0xFFFF, sum = 0
8187 17:41:55.715988 4, 0xFFFF, sum = 0
8188 17:41:55.716414 5, 0xFFFF, sum = 0
8189 17:41:55.719288 6, 0xFFFF, sum = 0
8190 17:41:55.719819 7, 0xFFFF, sum = 0
8191 17:41:55.722499 8, 0xFFFF, sum = 0
8192 17:41:55.723108 9, 0xFFFF, sum = 0
8193 17:41:55.726114 10, 0xFFFF, sum = 0
8194 17:41:55.726646 11, 0xFFFF, sum = 0
8195 17:41:55.729546 12, 0xFFFF, sum = 0
8196 17:41:55.730076 13, 0xFFFF, sum = 0
8197 17:41:55.732024 14, 0x0, sum = 1
8198 17:41:55.732451 15, 0x0, sum = 2
8199 17:41:55.735607 16, 0x0, sum = 3
8200 17:41:55.736100 17, 0x0, sum = 4
8201 17:41:55.738894 best_step = 15
8202 17:41:55.739316
8203 17:41:55.739645 ==
8204 17:41:55.742183 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 17:41:55.745957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 17:41:55.746499 ==
8207 17:41:55.746883 RX Vref Scan: 0
8208 17:41:55.749162
8209 17:41:55.749693 RX Vref 0 -> 0, step: 1
8210 17:41:55.750031
8211 17:41:55.752257 RX Delay 11 -> 252, step: 4
8212 17:41:55.755595 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8213 17:41:55.762493 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8214 17:41:55.765588 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8215 17:41:55.769237 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8216 17:41:55.772186 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8217 17:41:55.775512 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8218 17:41:55.779148 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8219 17:41:55.785712 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8220 17:41:55.789249 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8221 17:41:55.792611 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8222 17:41:55.795825 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8223 17:41:55.799403 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8224 17:41:55.805949 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8225 17:41:55.808925 iDelay=191, Bit 13, Center 128 (71 ~ 186) 116
8226 17:41:55.812395 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8227 17:41:55.815566 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8228 17:41:55.816000 ==
8229 17:41:55.819121 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 17:41:55.826198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 17:41:55.826765 ==
8232 17:41:55.827113 DQS Delay:
8233 17:41:55.829657 DQS0 = 0, DQS1 = 0
8234 17:41:55.830179 DQM Delay:
8235 17:41:55.830516 DQM0 = 127, DQM1 = 122
8236 17:41:55.832249 DQ Delay:
8237 17:41:55.835295 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8238 17:41:55.838715 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8239 17:41:55.842694 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8240 17:41:55.846140 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8241 17:41:55.846679
8242 17:41:55.847083
8243 17:41:55.847396
8244 17:41:55.849702 [DramC_TX_OE_Calibration] TA2
8245 17:41:55.852453 Original DQ_B0 (3 6) =30, OEN = 27
8246 17:41:55.855775 Original DQ_B1 (3 6) =30, OEN = 27
8247 17:41:55.859073 24, 0x0, End_B0=24 End_B1=24
8248 17:41:55.859504 25, 0x0, End_B0=25 End_B1=25
8249 17:41:55.862074 26, 0x0, End_B0=26 End_B1=26
8250 17:41:55.865465 27, 0x0, End_B0=27 End_B1=27
8251 17:41:55.869252 28, 0x0, End_B0=28 End_B1=28
8252 17:41:55.871960 29, 0x0, End_B0=29 End_B1=29
8253 17:41:55.872392 30, 0x0, End_B0=30 End_B1=30
8254 17:41:55.875691 31, 0x4141, End_B0=30 End_B1=30
8255 17:41:55.879113 Byte0 end_step=30 best_step=27
8256 17:41:55.882065 Byte1 end_step=30 best_step=27
8257 17:41:55.885281 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 17:41:55.888954 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 17:41:55.889381
8260 17:41:55.889711
8261 17:41:55.895257 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8262 17:41:55.898696 CH0 RK1: MR19=303, MR18=180D
8263 17:41:55.905736 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8264 17:41:55.909199 [RxdqsGatingPostProcess] freq 1600
8265 17:41:55.912287 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 17:41:55.915556 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 17:41:55.918937 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 17:41:55.922209 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 17:41:55.925433 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 17:41:55.928577 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 17:41:55.931985 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 17:41:55.935238 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 17:41:55.938505 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 17:41:55.942415 Pre-setting of DQS Precalculation
8275 17:41:55.945246 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 17:41:55.945769 ==
8277 17:41:55.949239 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 17:41:55.952148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 17:41:55.955307 ==
8280 17:41:55.958898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 17:41:55.962162 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 17:41:55.968809 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 17:41:55.972229 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 17:41:55.982541 [CA 0] Center 42 (13~71) winsize 59
8285 17:41:55.985531 [CA 1] Center 42 (13~71) winsize 59
8286 17:41:55.988683 [CA 2] Center 37 (8~66) winsize 59
8287 17:41:55.992071 [CA 3] Center 36 (7~65) winsize 59
8288 17:41:55.995649 [CA 4] Center 37 (8~67) winsize 60
8289 17:41:55.999113 [CA 5] Center 36 (6~66) winsize 61
8290 17:41:55.999643
8291 17:41:56.002051 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 17:41:56.002587
8293 17:41:56.005862 [CATrainingPosCal] consider 1 rank data
8294 17:41:56.008864 u2DelayCellTimex100 = 275/100 ps
8295 17:41:56.012446 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8296 17:41:56.018654 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8297 17:41:56.022170 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8298 17:41:56.025255 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8299 17:41:56.028610 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8300 17:41:56.031870 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8301 17:41:56.032319
8302 17:41:56.035295 CA PerBit enable=1, Macro0, CA PI delay=36
8303 17:41:56.035770
8304 17:41:56.038470 [CBTSetCACLKResult] CA Dly = 36
8305 17:41:56.041837 CS Dly: 9 (0~40)
8306 17:41:56.045281 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 17:41:56.048855 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 17:41:56.049279 ==
8309 17:41:56.052037 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 17:41:56.055267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 17:41:56.055688 ==
8312 17:41:56.061726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 17:41:56.065163 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 17:41:56.072134 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 17:41:56.075098 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 17:41:56.085378 [CA 0] Center 43 (14~72) winsize 59
8317 17:41:56.088281 [CA 1] Center 43 (14~72) winsize 59
8318 17:41:56.092054 [CA 2] Center 38 (10~67) winsize 58
8319 17:41:56.095736 [CA 3] Center 37 (7~67) winsize 61
8320 17:41:56.099090 [CA 4] Center 38 (9~68) winsize 60
8321 17:41:56.102278 [CA 5] Center 37 (8~66) winsize 59
8322 17:41:56.102844
8323 17:41:56.105704 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 17:41:56.106229
8325 17:41:56.108964 [CATrainingPosCal] consider 2 rank data
8326 17:41:56.111703 u2DelayCellTimex100 = 275/100 ps
8327 17:41:56.115584 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8328 17:41:56.121868 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8329 17:41:56.124899 CA2 delay=38 (10~66),Diff = 2 PI (7 cell)
8330 17:41:56.128191 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8331 17:41:56.131661 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8332 17:41:56.135159 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8333 17:41:56.135580
8334 17:41:56.138418 CA PerBit enable=1, Macro0, CA PI delay=36
8335 17:41:56.138944
8336 17:41:56.142195 [CBTSetCACLKResult] CA Dly = 36
8337 17:41:56.145135 CS Dly: 10 (0~43)
8338 17:41:56.148276 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 17:41:56.151546 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 17:41:56.151967
8341 17:41:56.155114 ----->DramcWriteLeveling(PI) begin...
8342 17:41:56.155549 ==
8343 17:41:56.158283 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 17:41:56.161696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 17:41:56.165024 ==
8346 17:41:56.165250 Write leveling (Byte 0): 25 => 25
8347 17:41:56.167983 Write leveling (Byte 1): 29 => 29
8348 17:41:56.171554 DramcWriteLeveling(PI) end<-----
8349 17:41:56.171736
8350 17:41:56.171881 ==
8351 17:41:56.175173 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 17:41:56.181640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 17:41:56.181813 ==
8354 17:41:56.181919 [Gating] SW mode calibration
8355 17:41:56.191274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 17:41:56.194675 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 17:41:56.198258 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 17:41:56.204605 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 17:41:56.208090 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 17:41:56.211243 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 17:41:56.218077 1 4 16 | B1->B0 | 2626 2424 | 1 1 | (1 1) (1 1)
8362 17:41:56.221836 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 17:41:56.225360 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 17:41:56.231652 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 17:41:56.235330 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 17:41:56.238861 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 17:41:56.244924 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 17:41:56.248720 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8369 17:41:56.252398 1 5 16 | B1->B0 | 2f2f 3232 | 0 0 | (1 0) (1 0)
8370 17:41:56.258615 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 17:41:56.261663 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 17:41:56.265062 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 17:41:56.271843 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 17:41:56.275283 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 17:41:56.278489 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 17:41:56.284942 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 17:41:56.288505 1 6 16 | B1->B0 | 4040 3636 | 0 1 | (0 0) (0 0)
8378 17:41:56.291693 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 17:41:56.295382 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 17:41:56.301732 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 17:41:56.305397 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 17:41:56.308613 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 17:41:56.315051 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 17:41:56.318607 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8385 17:41:56.322320 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 17:41:56.328688 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8387 17:41:56.332518 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 17:41:56.335026 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 17:41:56.342248 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 17:41:56.345218 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 17:41:56.348649 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 17:41:56.355385 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 17:41:56.358442 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 17:41:56.362028 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 17:41:56.368840 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 17:41:56.371824 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 17:41:56.375094 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 17:41:56.381647 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 17:41:56.385217 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 17:41:56.388424 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 17:41:56.391973 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8402 17:41:56.398325 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 17:41:56.402114 Total UI for P1: 0, mck2ui 16
8404 17:41:56.405214 best dqsien dly found for B0: ( 1, 9, 16)
8405 17:41:56.408521 Total UI for P1: 0, mck2ui 16
8406 17:41:56.411979 best dqsien dly found for B1: ( 1, 9, 16)
8407 17:41:56.415206 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8408 17:41:56.418645 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8409 17:41:56.418982
8410 17:41:56.422088 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8411 17:41:56.425344 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 17:41:56.427823 [Gating] SW calibration Done
8413 17:41:56.428006 ==
8414 17:41:56.431282 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 17:41:56.434984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 17:41:56.435137 ==
8417 17:41:56.437870 RX Vref Scan: 0
8418 17:41:56.438000
8419 17:41:56.441116 RX Vref 0 -> 0, step: 1
8420 17:41:56.441247
8421 17:41:56.441349 RX Delay 0 -> 252, step: 8
8422 17:41:56.448006 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8423 17:41:56.451582 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8424 17:41:56.454418 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8425 17:41:56.458105 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8426 17:41:56.461740 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8427 17:41:56.465082 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8428 17:41:56.471452 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8429 17:41:56.474605 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8430 17:41:56.477911 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8431 17:41:56.481470 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8432 17:41:56.484680 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8433 17:41:56.491702 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8434 17:41:56.494847 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8435 17:41:56.498246 iDelay=208, Bit 13, Center 135 (72 ~ 199) 128
8436 17:41:56.501727 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8437 17:41:56.504956 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8438 17:41:56.508390 ==
8439 17:41:56.511529 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 17:41:56.514940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 17:41:56.515034 ==
8442 17:41:56.515100 DQS Delay:
8443 17:41:56.518121 DQS0 = 0, DQS1 = 0
8444 17:41:56.518205 DQM Delay:
8445 17:41:56.521277 DQM0 = 135, DQM1 = 127
8446 17:41:56.521360 DQ Delay:
8447 17:41:56.524695 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8448 17:41:56.528443 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8449 17:41:56.531357 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8450 17:41:56.534999 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8451 17:41:56.535087
8452 17:41:56.535151
8453 17:41:56.535210 ==
8454 17:41:56.538373 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 17:41:56.544808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 17:41:56.544902 ==
8457 17:41:56.544969
8458 17:41:56.545028
8459 17:41:56.545084 TX Vref Scan disable
8460 17:41:56.548098 == TX Byte 0 ==
8461 17:41:56.551470 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8462 17:41:56.554874 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8463 17:41:56.558357 == TX Byte 1 ==
8464 17:41:56.561925 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8465 17:41:56.564809 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8466 17:41:56.568393 ==
8467 17:41:56.571705 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 17:41:56.575395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 17:41:56.575490 ==
8470 17:41:56.588552
8471 17:41:56.592079 TX Vref early break, caculate TX vref
8472 17:41:56.595075 TX Vref=16, minBit 8, minWin=21, winSum=362
8473 17:41:56.598217 TX Vref=18, minBit 8, minWin=20, winSum=369
8474 17:41:56.601950 TX Vref=20, minBit 8, minWin=21, winSum=381
8475 17:41:56.604957 TX Vref=22, minBit 9, minWin=23, winSum=391
8476 17:41:56.608348 TX Vref=24, minBit 8, minWin=23, winSum=399
8477 17:41:56.614975 TX Vref=26, minBit 11, minWin=24, winSum=406
8478 17:41:56.618463 TX Vref=28, minBit 8, minWin=25, winSum=415
8479 17:41:56.621525 TX Vref=30, minBit 0, minWin=25, winSum=415
8480 17:41:56.625254 TX Vref=32, minBit 0, minWin=25, winSum=410
8481 17:41:56.628676 TX Vref=34, minBit 8, minWin=23, winSum=394
8482 17:41:56.631879 TX Vref=36, minBit 8, minWin=23, winSum=388
8483 17:41:56.638449 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 28
8484 17:41:56.638541
8485 17:41:56.641683 Final TX Range 0 Vref 28
8486 17:41:56.641767
8487 17:41:56.641832 ==
8488 17:41:56.645163 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 17:41:56.648384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 17:41:56.648469 ==
8491 17:41:56.648535
8492 17:41:56.648594
8493 17:41:56.651998 TX Vref Scan disable
8494 17:41:56.658398 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8495 17:41:56.658485 == TX Byte 0 ==
8496 17:41:56.661890 u2DelayCellOfst[0]=17 cells (5 PI)
8497 17:41:56.664968 u2DelayCellOfst[1]=10 cells (3 PI)
8498 17:41:56.668325 u2DelayCellOfst[2]=0 cells (0 PI)
8499 17:41:56.671596 u2DelayCellOfst[3]=7 cells (2 PI)
8500 17:41:56.674909 u2DelayCellOfst[4]=7 cells (2 PI)
8501 17:41:56.678482 u2DelayCellOfst[5]=21 cells (6 PI)
8502 17:41:56.681986 u2DelayCellOfst[6]=17 cells (5 PI)
8503 17:41:56.684916 u2DelayCellOfst[7]=7 cells (2 PI)
8504 17:41:56.688405 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8505 17:41:56.691699 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8506 17:41:56.695073 == TX Byte 1 ==
8507 17:41:56.695156 u2DelayCellOfst[8]=0 cells (0 PI)
8508 17:41:56.698867 u2DelayCellOfst[9]=7 cells (2 PI)
8509 17:41:56.701801 u2DelayCellOfst[10]=10 cells (3 PI)
8510 17:41:56.704988 u2DelayCellOfst[11]=7 cells (2 PI)
8511 17:41:56.708524 u2DelayCellOfst[12]=14 cells (4 PI)
8512 17:41:56.711794 u2DelayCellOfst[13]=17 cells (5 PI)
8513 17:41:56.714972 u2DelayCellOfst[14]=17 cells (5 PI)
8514 17:41:56.718368 u2DelayCellOfst[15]=17 cells (5 PI)
8515 17:41:56.721591 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8516 17:41:56.728511 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8517 17:41:56.728631 DramC Write-DBI on
8518 17:41:56.728702 ==
8519 17:41:56.732099 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 17:41:56.735304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 17:41:56.735394 ==
8522 17:41:56.738414
8523 17:41:56.738534
8524 17:41:56.738598 TX Vref Scan disable
8525 17:41:56.741504 == TX Byte 0 ==
8526 17:41:56.744918 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8527 17:41:56.748361 == TX Byte 1 ==
8528 17:41:56.751686 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8529 17:41:56.751775 DramC Write-DBI off
8530 17:41:56.755079
8531 17:41:56.755165 [DATLAT]
8532 17:41:56.755231 Freq=1600, CH1 RK0
8533 17:41:56.755292
8534 17:41:56.758366 DATLAT Default: 0xf
8535 17:41:56.758454 0, 0xFFFF, sum = 0
8536 17:41:56.761691 1, 0xFFFF, sum = 0
8537 17:41:56.761783 2, 0xFFFF, sum = 0
8538 17:41:56.765210 3, 0xFFFF, sum = 0
8539 17:41:56.765300 4, 0xFFFF, sum = 0
8540 17:41:56.768853 5, 0xFFFF, sum = 0
8541 17:41:56.768942 6, 0xFFFF, sum = 0
8542 17:41:56.771656 7, 0xFFFF, sum = 0
8543 17:41:56.775024 8, 0xFFFF, sum = 0
8544 17:41:56.775114 9, 0xFFFF, sum = 0
8545 17:41:56.778867 10, 0xFFFF, sum = 0
8546 17:41:56.778954 11, 0xFFFF, sum = 0
8547 17:41:56.781871 12, 0xFFFF, sum = 0
8548 17:41:56.781956 13, 0xFFFF, sum = 0
8549 17:41:56.784989 14, 0x0, sum = 1
8550 17:41:56.785075 15, 0x0, sum = 2
8551 17:41:56.788379 16, 0x0, sum = 3
8552 17:41:56.788466 17, 0x0, sum = 4
8553 17:41:56.788534 best_step = 15
8554 17:41:56.791768
8555 17:41:56.791853 ==
8556 17:41:56.795206 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 17:41:56.798901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 17:41:56.798991 ==
8559 17:41:56.799058 RX Vref Scan: 1
8560 17:41:56.799118
8561 17:41:56.801799 Set Vref Range= 24 -> 127
8562 17:41:56.801883
8563 17:41:56.805365 RX Vref 24 -> 127, step: 1
8564 17:41:56.805462
8565 17:41:56.808516 RX Delay 19 -> 252, step: 4
8566 17:41:56.808599
8567 17:41:56.811752 Set Vref, RX VrefLevel [Byte0]: 24
8568 17:41:56.815354 [Byte1]: 24
8569 17:41:56.815442
8570 17:41:56.818650 Set Vref, RX VrefLevel [Byte0]: 25
8571 17:41:56.821739 [Byte1]: 25
8572 17:41:56.821828
8573 17:41:56.825211 Set Vref, RX VrefLevel [Byte0]: 26
8574 17:41:56.828289 [Byte1]: 26
8575 17:41:56.832079
8576 17:41:56.832171 Set Vref, RX VrefLevel [Byte0]: 27
8577 17:41:56.834959 [Byte1]: 27
8578 17:41:56.839538
8579 17:41:56.839630 Set Vref, RX VrefLevel [Byte0]: 28
8580 17:41:56.842711 [Byte1]: 28
8581 17:41:56.847058
8582 17:41:56.847152 Set Vref, RX VrefLevel [Byte0]: 29
8583 17:41:56.850209 [Byte1]: 29
8584 17:41:56.854543
8585 17:41:56.854637 Set Vref, RX VrefLevel [Byte0]: 30
8586 17:41:56.857981 [Byte1]: 30
8587 17:41:56.862389
8588 17:41:56.862492 Set Vref, RX VrefLevel [Byte0]: 31
8589 17:41:56.865564 [Byte1]: 31
8590 17:41:56.869671
8591 17:41:56.869766 Set Vref, RX VrefLevel [Byte0]: 32
8592 17:41:56.873098 [Byte1]: 32
8593 17:41:56.877539
8594 17:41:56.877633 Set Vref, RX VrefLevel [Byte0]: 33
8595 17:41:56.880395 [Byte1]: 33
8596 17:41:56.884611
8597 17:41:56.884705 Set Vref, RX VrefLevel [Byte0]: 34
8598 17:41:56.888070 [Byte1]: 34
8599 17:41:56.892666
8600 17:41:56.892761 Set Vref, RX VrefLevel [Byte0]: 35
8601 17:41:56.895911 [Byte1]: 35
8602 17:41:56.899929
8603 17:41:56.900027 Set Vref, RX VrefLevel [Byte0]: 36
8604 17:41:56.903439 [Byte1]: 36
8605 17:41:56.907716
8606 17:41:56.907837 Set Vref, RX VrefLevel [Byte0]: 37
8607 17:41:56.910915 [Byte1]: 37
8608 17:41:56.915317
8609 17:41:56.915413 Set Vref, RX VrefLevel [Byte0]: 38
8610 17:41:56.918268 [Byte1]: 38
8611 17:41:56.922633
8612 17:41:56.922794 Set Vref, RX VrefLevel [Byte0]: 39
8613 17:41:56.926122 [Byte1]: 39
8614 17:41:56.930877
8615 17:41:56.930974 Set Vref, RX VrefLevel [Byte0]: 40
8616 17:41:56.933900 [Byte1]: 40
8617 17:41:56.937702
8618 17:41:56.937793 Set Vref, RX VrefLevel [Byte0]: 41
8619 17:41:56.941110 [Byte1]: 41
8620 17:41:56.945211
8621 17:41:56.945302 Set Vref, RX VrefLevel [Byte0]: 42
8622 17:41:56.948826 [Byte1]: 42
8623 17:41:56.952894
8624 17:41:56.952984 Set Vref, RX VrefLevel [Byte0]: 43
8625 17:41:56.956327 [Byte1]: 43
8626 17:41:56.961028
8627 17:41:56.961130 Set Vref, RX VrefLevel [Byte0]: 44
8628 17:41:56.964073 [Byte1]: 44
8629 17:41:56.968138
8630 17:41:56.968236 Set Vref, RX VrefLevel [Byte0]: 45
8631 17:41:56.971568 [Byte1]: 45
8632 17:41:56.975673
8633 17:41:56.975769 Set Vref, RX VrefLevel [Byte0]: 46
8634 17:41:56.979087 [Byte1]: 46
8635 17:41:56.983264
8636 17:41:56.983362 Set Vref, RX VrefLevel [Byte0]: 47
8637 17:41:56.986707 [Byte1]: 47
8638 17:41:56.990784
8639 17:41:56.990879 Set Vref, RX VrefLevel [Byte0]: 48
8640 17:41:56.994172 [Byte1]: 48
8641 17:41:56.998637
8642 17:41:56.998742 Set Vref, RX VrefLevel [Byte0]: 49
8643 17:41:57.001511 [Byte1]: 49
8644 17:41:57.006370
8645 17:41:57.006462 Set Vref, RX VrefLevel [Byte0]: 50
8646 17:41:57.009513 [Byte1]: 50
8647 17:41:57.013884
8648 17:41:57.013974 Set Vref, RX VrefLevel [Byte0]: 51
8649 17:41:57.017227 [Byte1]: 51
8650 17:41:57.021016
8651 17:41:57.021108 Set Vref, RX VrefLevel [Byte0]: 52
8652 17:41:57.024438 [Byte1]: 52
8653 17:41:57.028862
8654 17:41:57.029031 Set Vref, RX VrefLevel [Byte0]: 53
8655 17:41:57.031956 [Byte1]: 53
8656 17:41:57.036232
8657 17:41:57.036345 Set Vref, RX VrefLevel [Byte0]: 54
8658 17:41:57.039525 [Byte1]: 54
8659 17:41:57.043975
8660 17:41:57.044074 Set Vref, RX VrefLevel [Byte0]: 55
8661 17:41:57.046999 [Byte1]: 55
8662 17:41:57.051710
8663 17:41:57.051808 Set Vref, RX VrefLevel [Byte0]: 56
8664 17:41:57.055120 [Byte1]: 56
8665 17:41:57.059290
8666 17:41:57.059387 Set Vref, RX VrefLevel [Byte0]: 57
8667 17:41:57.062599 [Byte1]: 57
8668 17:41:57.066983
8669 17:41:57.067079 Set Vref, RX VrefLevel [Byte0]: 58
8670 17:41:57.070261 [Byte1]: 58
8671 17:41:57.074046
8672 17:41:57.074142 Set Vref, RX VrefLevel [Byte0]: 59
8673 17:41:57.077322 [Byte1]: 59
8674 17:41:57.081809
8675 17:41:57.081906 Set Vref, RX VrefLevel [Byte0]: 60
8676 17:41:57.085207 [Byte1]: 60
8677 17:41:57.089405
8678 17:41:57.089500 Set Vref, RX VrefLevel [Byte0]: 61
8679 17:41:57.092774 [Byte1]: 61
8680 17:41:57.097201
8681 17:41:57.097298 Set Vref, RX VrefLevel [Byte0]: 62
8682 17:41:57.100089 [Byte1]: 62
8683 17:41:57.104508
8684 17:41:57.104601 Set Vref, RX VrefLevel [Byte0]: 63
8685 17:41:57.108244 [Byte1]: 63
8686 17:41:57.111830
8687 17:41:57.111919 Set Vref, RX VrefLevel [Byte0]: 64
8688 17:41:57.115078 [Byte1]: 64
8689 17:41:57.119884
8690 17:41:57.119981 Set Vref, RX VrefLevel [Byte0]: 65
8691 17:41:57.123085 [Byte1]: 65
8692 17:41:57.127213
8693 17:41:57.127352 Set Vref, RX VrefLevel [Byte0]: 66
8694 17:41:57.130346 [Byte1]: 66
8695 17:41:57.135017
8696 17:41:57.135154 Set Vref, RX VrefLevel [Byte0]: 67
8697 17:41:57.138399 [Byte1]: 67
8698 17:41:57.142446
8699 17:41:57.142589 Set Vref, RX VrefLevel [Byte0]: 68
8700 17:41:57.145693 [Byte1]: 68
8701 17:41:57.150124
8702 17:41:57.150273 Set Vref, RX VrefLevel [Byte0]: 69
8703 17:41:57.153217 [Byte1]: 69
8704 17:41:57.157431
8705 17:41:57.157597 Set Vref, RX VrefLevel [Byte0]: 70
8706 17:41:57.160824 [Byte1]: 70
8707 17:41:57.165037
8708 17:41:57.165227 Set Vref, RX VrefLevel [Byte0]: 71
8709 17:41:57.168383 [Byte1]: 71
8710 17:41:57.172542
8711 17:41:57.172648 Set Vref, RX VrefLevel [Byte0]: 72
8712 17:41:57.175638 [Byte1]: 72
8713 17:41:57.179964
8714 17:41:57.180060 Set Vref, RX VrefLevel [Byte0]: 73
8715 17:41:57.183480 [Byte1]: 73
8716 17:41:57.187855
8717 17:41:57.187950 Set Vref, RX VrefLevel [Byte0]: 74
8718 17:41:57.191267 [Byte1]: 74
8719 17:41:57.195092
8720 17:41:57.195182 Final RX Vref Byte 0 = 63 to rank0
8721 17:41:57.198914 Final RX Vref Byte 1 = 59 to rank0
8722 17:41:57.202103 Final RX Vref Byte 0 = 63 to rank1
8723 17:41:57.205042 Final RX Vref Byte 1 = 59 to rank1==
8724 17:41:57.208581 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 17:41:57.215619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 17:41:57.215736 ==
8727 17:41:57.215805 DQS Delay:
8728 17:41:57.215865 DQS0 = 0, DQS1 = 0
8729 17:41:57.218378 DQM Delay:
8730 17:41:57.218461 DQM0 = 131, DQM1 = 124
8731 17:41:57.222001 DQ Delay:
8732 17:41:57.225500 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
8733 17:41:57.228717 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8734 17:41:57.231600 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8735 17:41:57.235330 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8736 17:41:57.235426
8737 17:41:57.235492
8738 17:41:57.235552
8739 17:41:57.238622 [DramC_TX_OE_Calibration] TA2
8740 17:41:57.242012 Original DQ_B0 (3 6) =30, OEN = 27
8741 17:41:57.244958 Original DQ_B1 (3 6) =30, OEN = 27
8742 17:41:57.248404 24, 0x0, End_B0=24 End_B1=24
8743 17:41:57.248495 25, 0x0, End_B0=25 End_B1=25
8744 17:41:57.251757 26, 0x0, End_B0=26 End_B1=26
8745 17:41:57.255450 27, 0x0, End_B0=27 End_B1=27
8746 17:41:57.258553 28, 0x0, End_B0=28 End_B1=28
8747 17:41:57.258674 29, 0x0, End_B0=29 End_B1=29
8748 17:41:57.261942 30, 0x0, End_B0=30 End_B1=30
8749 17:41:57.265360 31, 0x4141, End_B0=30 End_B1=30
8750 17:41:57.268780 Byte0 end_step=30 best_step=27
8751 17:41:57.272316 Byte1 end_step=30 best_step=27
8752 17:41:57.275211 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 17:41:57.275305 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 17:41:57.275381
8755 17:41:57.278811
8756 17:41:57.285512 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fb, (MSB)MR19= 0x302, tDQSOscB0 = 412 ps tDQSOscB1 = 401 ps
8757 17:41:57.289002 CH1 RK0: MR19=302, MR18=11FB
8758 17:41:57.295265 CH1_RK0: MR19=0x302, MR18=0x11FB, DQSOSC=401, MR23=63, INC=22, DEC=15
8759 17:41:57.295376
8760 17:41:57.299050 ----->DramcWriteLeveling(PI) begin...
8761 17:41:57.299140 ==
8762 17:41:57.302374 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 17:41:57.305150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 17:41:57.305239 ==
8765 17:41:57.308754 Write leveling (Byte 0): 26 => 26
8766 17:41:57.312450 Write leveling (Byte 1): 29 => 29
8767 17:41:57.315201 DramcWriteLeveling(PI) end<-----
8768 17:41:57.315317
8769 17:41:57.315390 ==
8770 17:41:57.318883 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 17:41:57.322237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 17:41:57.322325 ==
8773 17:41:57.325698 [Gating] SW mode calibration
8774 17:41:57.332227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 17:41:57.338702 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 17:41:57.341876 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 17:41:57.345504 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 17:41:57.352280 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8779 17:41:57.355663 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
8780 17:41:57.358657 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 17:41:57.362352 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 17:41:57.368784 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 17:41:57.372332 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 17:41:57.375662 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 17:41:57.382024 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8786 17:41:57.386001 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8787 17:41:57.388886 1 5 12 | B1->B0 | 3232 2525 | 0 0 | (1 0) (0 0)
8788 17:41:57.395389 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8789 17:41:57.399143 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 17:41:57.402099 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 17:41:57.408847 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 17:41:57.412740 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 17:41:57.415829 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 17:41:57.422567 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8795 17:41:57.425819 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8796 17:41:57.429207 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 17:41:57.436066 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 17:41:57.439296 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 17:41:57.442523 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 17:41:57.445635 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 17:41:57.452832 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8802 17:41:57.455971 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 17:41:57.459310 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 17:41:57.465725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 17:41:57.469237 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 17:41:57.472556 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 17:41:57.478883 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 17:41:57.482315 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 17:41:57.485720 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 17:41:57.492485 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 17:41:57.495732 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 17:41:57.499078 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 17:41:57.506132 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 17:41:57.509479 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 17:41:57.512613 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 17:41:57.519154 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 17:41:57.522554 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 17:41:57.525685 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8819 17:41:57.529392 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 17:41:57.532941 Total UI for P1: 0, mck2ui 16
8821 17:41:57.536018 best dqsien dly found for B0: ( 1, 9, 6)
8822 17:41:57.542395 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 17:41:57.546109 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 17:41:57.549258 Total UI for P1: 0, mck2ui 16
8825 17:41:57.552872 best dqsien dly found for B1: ( 1, 9, 14)
8826 17:41:57.556099 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8827 17:41:57.559653 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8828 17:41:57.559751
8829 17:41:57.562551 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8830 17:41:57.566038 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8831 17:41:57.569902 [Gating] SW calibration Done
8832 17:41:57.569999 ==
8833 17:41:57.572810 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 17:41:57.576170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 17:41:57.579137 ==
8836 17:41:57.579229 RX Vref Scan: 0
8837 17:41:57.579294
8838 17:41:57.582754 RX Vref 0 -> 0, step: 1
8839 17:41:57.582854
8840 17:41:57.582919 RX Delay 0 -> 252, step: 8
8841 17:41:57.589302 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8842 17:41:57.592754 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8843 17:41:57.595823 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8844 17:41:57.599574 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8845 17:41:57.602603 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8846 17:41:57.609320 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8847 17:41:57.612583 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8848 17:41:57.616126 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8849 17:41:57.619037 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8850 17:41:57.622634 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8851 17:41:57.629357 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8852 17:41:57.632914 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8853 17:41:57.635920 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8854 17:41:57.639305 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8855 17:41:57.646016 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8856 17:41:57.649330 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8857 17:41:57.649433 ==
8858 17:41:57.652822 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 17:41:57.656323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 17:41:57.656412 ==
8861 17:41:57.656477 DQS Delay:
8862 17:41:57.658956 DQS0 = 0, DQS1 = 0
8863 17:41:57.659042 DQM Delay:
8864 17:41:57.662492 DQM0 = 132, DQM1 = 127
8865 17:41:57.662579 DQ Delay:
8866 17:41:57.665984 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8867 17:41:57.669403 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8868 17:41:57.672312 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
8869 17:41:57.675892 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8870 17:41:57.678993
8871 17:41:57.679118
8872 17:41:57.679183 ==
8873 17:41:57.682354 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 17:41:57.686070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 17:41:57.686159 ==
8876 17:41:57.686223
8877 17:41:57.686283
8878 17:41:57.689505 TX Vref Scan disable
8879 17:41:57.689590 == TX Byte 0 ==
8880 17:41:57.695916 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8881 17:41:57.699394 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8882 17:41:57.699487 == TX Byte 1 ==
8883 17:41:57.706137 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8884 17:41:57.709135 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8885 17:41:57.709233 ==
8886 17:41:57.712564 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 17:41:57.715707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 17:41:57.715896 ==
8889 17:41:57.730344
8890 17:41:57.733696 TX Vref early break, caculate TX vref
8891 17:41:57.737078 TX Vref=16, minBit 13, minWin=22, winSum=376
8892 17:41:57.740376 TX Vref=18, minBit 8, minWin=23, winSum=383
8893 17:41:57.743410 TX Vref=20, minBit 8, minWin=23, winSum=392
8894 17:41:57.747186 TX Vref=22, minBit 9, minWin=23, winSum=400
8895 17:41:57.750369 TX Vref=24, minBit 11, minWin=24, winSum=404
8896 17:41:57.757167 TX Vref=26, minBit 6, minWin=25, winSum=415
8897 17:41:57.760232 TX Vref=28, minBit 9, minWin=25, winSum=421
8898 17:41:57.764192 TX Vref=30, minBit 8, minWin=25, winSum=414
8899 17:41:57.766703 TX Vref=32, minBit 9, minWin=24, winSum=411
8900 17:41:57.770214 TX Vref=34, minBit 5, minWin=24, winSum=399
8901 17:41:57.773669 TX Vref=36, minBit 5, minWin=24, winSum=394
8902 17:41:57.780696 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8903 17:41:57.780810
8904 17:41:57.783513 Final TX Range 0 Vref 28
8905 17:41:57.783629
8906 17:41:57.783694 ==
8907 17:41:57.786972 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 17:41:57.790071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 17:41:57.790175 ==
8910 17:41:57.790240
8911 17:41:57.790299
8912 17:41:57.793932 TX Vref Scan disable
8913 17:41:57.800205 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8914 17:41:57.800310 == TX Byte 0 ==
8915 17:41:57.803744 u2DelayCellOfst[0]=21 cells (6 PI)
8916 17:41:57.807096 u2DelayCellOfst[1]=14 cells (4 PI)
8917 17:41:57.810242 u2DelayCellOfst[2]=0 cells (0 PI)
8918 17:41:57.813720 u2DelayCellOfst[3]=10 cells (3 PI)
8919 17:41:57.817219 u2DelayCellOfst[4]=14 cells (4 PI)
8920 17:41:57.820502 u2DelayCellOfst[5]=24 cells (7 PI)
8921 17:41:57.823863 u2DelayCellOfst[6]=21 cells (6 PI)
8922 17:41:57.827111 u2DelayCellOfst[7]=10 cells (3 PI)
8923 17:41:57.829927 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8924 17:41:57.833500 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8925 17:41:57.836833 == TX Byte 1 ==
8926 17:41:57.840272 u2DelayCellOfst[8]=0 cells (0 PI)
8927 17:41:57.840365 u2DelayCellOfst[9]=3 cells (1 PI)
8928 17:41:57.843762 u2DelayCellOfst[10]=7 cells (2 PI)
8929 17:41:57.846950 u2DelayCellOfst[11]=3 cells (1 PI)
8930 17:41:57.850638 u2DelayCellOfst[12]=7 cells (2 PI)
8931 17:41:57.853759 u2DelayCellOfst[13]=14 cells (4 PI)
8932 17:41:57.857094 u2DelayCellOfst[14]=14 cells (4 PI)
8933 17:41:57.860407 u2DelayCellOfst[15]=14 cells (4 PI)
8934 17:41:57.863878 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8935 17:41:57.870517 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8936 17:41:57.870658 DramC Write-DBI on
8937 17:41:57.870796 ==
8938 17:41:57.873538 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 17:41:57.877118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 17:41:57.880600 ==
8941 17:41:57.880694
8942 17:41:57.880765
8943 17:41:57.880826 TX Vref Scan disable
8944 17:41:57.883509 == TX Byte 0 ==
8945 17:41:57.886929 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8946 17:41:57.890419 == TX Byte 1 ==
8947 17:41:57.893447 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8948 17:41:57.896971 DramC Write-DBI off
8949 17:41:57.897067
8950 17:41:57.897134 [DATLAT]
8951 17:41:57.897195 Freq=1600, CH1 RK1
8952 17:41:57.897269
8953 17:41:57.900114 DATLAT Default: 0xf
8954 17:41:57.900198 0, 0xFFFF, sum = 0
8955 17:41:57.903689 1, 0xFFFF, sum = 0
8956 17:41:57.906908 2, 0xFFFF, sum = 0
8957 17:41:57.906996 3, 0xFFFF, sum = 0
8958 17:41:57.910312 4, 0xFFFF, sum = 0
8959 17:41:57.910400 5, 0xFFFF, sum = 0
8960 17:41:57.913718 6, 0xFFFF, sum = 0
8961 17:41:57.913804 7, 0xFFFF, sum = 0
8962 17:41:57.916672 8, 0xFFFF, sum = 0
8963 17:41:57.916763 9, 0xFFFF, sum = 0
8964 17:41:57.920375 10, 0xFFFF, sum = 0
8965 17:41:57.920468 11, 0xFFFF, sum = 0
8966 17:41:57.923260 12, 0xFFFF, sum = 0
8967 17:41:57.923346 13, 0xFFFF, sum = 0
8968 17:41:57.927245 14, 0x0, sum = 1
8969 17:41:57.927333 15, 0x0, sum = 2
8970 17:41:57.929863 16, 0x0, sum = 3
8971 17:41:57.929949 17, 0x0, sum = 4
8972 17:41:57.933279 best_step = 15
8973 17:41:57.933365
8974 17:41:57.933430 ==
8975 17:41:57.936686 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 17:41:57.940446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 17:41:57.940535 ==
8978 17:41:57.943447 RX Vref Scan: 0
8979 17:41:57.943532
8980 17:41:57.943597 RX Vref 0 -> 0, step: 1
8981 17:41:57.943657
8982 17:41:57.946712 RX Delay 11 -> 252, step: 4
8983 17:41:57.950269 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8984 17:41:57.956717 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8985 17:41:57.959900 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8986 17:41:57.963412 iDelay=191, Bit 3, Center 130 (79 ~ 182) 104
8987 17:41:57.966952 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8988 17:41:57.970368 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8989 17:41:57.977434 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8990 17:41:57.980112 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8991 17:41:57.983629 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8992 17:41:57.986549 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8993 17:41:57.990016 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8994 17:41:57.996502 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8995 17:41:58.000394 iDelay=191, Bit 12, Center 132 (79 ~ 186) 108
8996 17:41:58.003393 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8997 17:41:58.007049 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8998 17:41:58.009801 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
8999 17:41:58.013560 ==
9000 17:41:58.013652 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 17:41:58.019905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 17:41:58.020015 ==
9003 17:41:58.020083 DQS Delay:
9004 17:41:58.023228 DQS0 = 0, DQS1 = 0
9005 17:41:58.023315 DQM Delay:
9006 17:41:58.026662 DQM0 = 130, DQM1 = 125
9007 17:41:58.026810 DQ Delay:
9008 17:41:58.029950 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
9009 17:41:58.033487 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9010 17:41:58.036649 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9011 17:41:58.040420 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =136
9012 17:41:58.040519
9013 17:41:58.040585
9014 17:41:58.040646
9015 17:41:58.043626 [DramC_TX_OE_Calibration] TA2
9016 17:41:58.047034 Original DQ_B0 (3 6) =30, OEN = 27
9017 17:41:58.049953 Original DQ_B1 (3 6) =30, OEN = 27
9018 17:41:58.053495 24, 0x0, End_B0=24 End_B1=24
9019 17:41:58.056824 25, 0x0, End_B0=25 End_B1=25
9020 17:41:58.056923 26, 0x0, End_B0=26 End_B1=26
9021 17:41:58.060493 27, 0x0, End_B0=27 End_B1=27
9022 17:41:58.063423 28, 0x0, End_B0=28 End_B1=28
9023 17:41:58.066711 29, 0x0, End_B0=29 End_B1=29
9024 17:41:58.066824 30, 0x0, End_B0=30 End_B1=30
9025 17:41:58.070080 31, 0x4141, End_B0=30 End_B1=30
9026 17:41:58.073495 Byte0 end_step=30 best_step=27
9027 17:41:58.076667 Byte1 end_step=30 best_step=27
9028 17:41:58.080045 Byte0 TX OE(2T, 0.5T) = (3, 3)
9029 17:41:58.083820 Byte1 TX OE(2T, 0.5T) = (3, 3)
9030 17:41:58.083968
9031 17:41:58.084038
9032 17:41:58.089827 [DQSOSCAuto] RK1, (LSB)MR18= 0xd12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9033 17:41:58.093483 CH1 RK1: MR19=303, MR18=D12
9034 17:41:58.100235 CH1_RK1: MR19=0x303, MR18=0xD12, DQSOSC=400, MR23=63, INC=23, DEC=15
9035 17:41:58.103690 [RxdqsGatingPostProcess] freq 1600
9036 17:41:58.106689 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9037 17:41:58.110362 best DQS0 dly(2T, 0.5T) = (1, 1)
9038 17:41:58.113342 best DQS1 dly(2T, 0.5T) = (1, 1)
9039 17:41:58.116496 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9040 17:41:58.119903 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9041 17:41:58.123370 best DQS0 dly(2T, 0.5T) = (1, 1)
9042 17:41:58.126757 best DQS1 dly(2T, 0.5T) = (1, 1)
9043 17:41:58.130146 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9044 17:41:58.133288 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9045 17:41:58.136578 Pre-setting of DQS Precalculation
9046 17:41:58.139894 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9047 17:41:58.146952 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9048 17:41:58.153135 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9049 17:41:58.153285
9050 17:41:58.153386
9051 17:41:58.156815 [Calibration Summary] 3200 Mbps
9052 17:41:58.160266 CH 0, Rank 0
9053 17:41:58.160381 SW Impedance : PASS
9054 17:41:58.163119 DUTY Scan : NO K
9055 17:41:58.166625 ZQ Calibration : PASS
9056 17:41:58.166736 Jitter Meter : NO K
9057 17:41:58.170257 CBT Training : PASS
9058 17:41:58.173087 Write leveling : PASS
9059 17:41:58.173184 RX DQS gating : PASS
9060 17:41:58.176497 RX DQ/DQS(RDDQC) : PASS
9061 17:41:58.180052 TX DQ/DQS : PASS
9062 17:41:58.180148 RX DATLAT : PASS
9063 17:41:58.183175 RX DQ/DQS(Engine): PASS
9064 17:41:58.183293 TX OE : PASS
9065 17:41:58.186877 All Pass.
9066 17:41:58.186973
9067 17:41:58.187040 CH 0, Rank 1
9068 17:41:58.189742 SW Impedance : PASS
9069 17:41:58.189829 DUTY Scan : NO K
9070 17:41:58.193020 ZQ Calibration : PASS
9071 17:41:58.196491 Jitter Meter : NO K
9072 17:41:58.196610 CBT Training : PASS
9073 17:41:58.199926 Write leveling : PASS
9074 17:41:58.202997 RX DQS gating : PASS
9075 17:41:58.203142 RX DQ/DQS(RDDQC) : PASS
9076 17:41:58.206598 TX DQ/DQS : PASS
9077 17:41:58.210139 RX DATLAT : PASS
9078 17:41:58.210262 RX DQ/DQS(Engine): PASS
9079 17:41:58.213253 TX OE : PASS
9080 17:41:58.213373 All Pass.
9081 17:41:58.213468
9082 17:41:58.216204 CH 1, Rank 0
9083 17:41:58.216307 SW Impedance : PASS
9084 17:41:58.219565 DUTY Scan : NO K
9085 17:41:58.223068 ZQ Calibration : PASS
9086 17:41:58.223196 Jitter Meter : NO K
9087 17:41:58.226802 CBT Training : PASS
9088 17:41:58.230058 Write leveling : PASS
9089 17:41:58.230160 RX DQS gating : PASS
9090 17:41:58.233473 RX DQ/DQS(RDDQC) : PASS
9091 17:41:58.233572 TX DQ/DQS : PASS
9092 17:41:58.236489 RX DATLAT : PASS
9093 17:41:58.239591 RX DQ/DQS(Engine): PASS
9094 17:41:58.239697 TX OE : PASS
9095 17:41:58.242958 All Pass.
9096 17:41:58.243055
9097 17:41:58.243123 CH 1, Rank 1
9098 17:41:58.246493 SW Impedance : PASS
9099 17:41:58.246624 DUTY Scan : NO K
9100 17:41:58.250247 ZQ Calibration : PASS
9101 17:41:58.253221 Jitter Meter : NO K
9102 17:41:58.253331 CBT Training : PASS
9103 17:41:58.256676 Write leveling : PASS
9104 17:41:58.259633 RX DQS gating : PASS
9105 17:41:58.259737 RX DQ/DQS(RDDQC) : PASS
9106 17:41:58.262938 TX DQ/DQS : PASS
9107 17:41:58.266514 RX DATLAT : PASS
9108 17:41:58.266632 RX DQ/DQS(Engine): PASS
9109 17:41:58.269828 TX OE : PASS
9110 17:41:58.269921 All Pass.
9111 17:41:58.269987
9112 17:41:58.273539 DramC Write-DBI on
9113 17:41:58.276845 PER_BANK_REFRESH: Hybrid Mode
9114 17:41:58.276948 TX_TRACKING: ON
9115 17:41:58.286388 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9116 17:41:58.293497 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9117 17:41:58.299770 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9118 17:41:58.303058 [FAST_K] Save calibration result to emmc
9119 17:41:58.306923 sync common calibartion params.
9120 17:41:58.310078 sync cbt_mode0:1, 1:1
9121 17:41:58.310178 dram_init: ddr_geometry: 2
9122 17:41:58.313484 dram_init: ddr_geometry: 2
9123 17:41:58.317045 dram_init: ddr_geometry: 2
9124 17:41:58.320033 0:dram_rank_size:100000000
9125 17:41:58.320134 1:dram_rank_size:100000000
9126 17:41:58.326666 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9127 17:41:58.330337 DFS_SHUFFLE_HW_MODE: ON
9128 17:41:58.333437 dramc_set_vcore_voltage set vcore to 725000
9129 17:41:58.333529 Read voltage for 1600, 0
9130 17:41:58.336662 Vio18 = 0
9131 17:41:58.336747 Vcore = 725000
9132 17:41:58.336812 Vdram = 0
9133 17:41:58.340424 Vddq = 0
9134 17:41:58.340509 Vmddr = 0
9135 17:41:58.343685 switch to 3200 Mbps bootup
9136 17:41:58.343772 [DramcRunTimeConfig]
9137 17:41:58.343837 PHYPLL
9138 17:41:58.347021 DPM_CONTROL_AFTERK: ON
9139 17:41:58.350135 PER_BANK_REFRESH: ON
9140 17:41:58.350249 REFRESH_OVERHEAD_REDUCTION: ON
9141 17:41:58.353830 CMD_PICG_NEW_MODE: OFF
9142 17:41:58.357099 XRTWTW_NEW_MODE: ON
9143 17:41:58.357193 XRTRTR_NEW_MODE: ON
9144 17:41:58.360325 TX_TRACKING: ON
9145 17:41:58.360416 RDSEL_TRACKING: OFF
9146 17:41:58.363286 DQS Precalculation for DVFS: ON
9147 17:41:58.363377 RX_TRACKING: OFF
9148 17:41:58.366626 HW_GATING DBG: ON
9149 17:41:58.370213 ZQCS_ENABLE_LP4: ON
9150 17:41:58.370309 RX_PICG_NEW_MODE: ON
9151 17:41:58.373780 TX_PICG_NEW_MODE: ON
9152 17:41:58.373866 ENABLE_RX_DCM_DPHY: ON
9153 17:41:58.376800 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9154 17:41:58.380237 DUMMY_READ_FOR_TRACKING: OFF
9155 17:41:58.383747 !!! SPM_CONTROL_AFTERK: OFF
9156 17:41:58.387050 !!! SPM could not control APHY
9157 17:41:58.387136 IMPEDANCE_TRACKING: ON
9158 17:41:58.389906 TEMP_SENSOR: ON
9159 17:41:58.390016 HW_SAVE_FOR_SR: OFF
9160 17:41:58.393509 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9161 17:41:58.396843 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9162 17:41:58.399989 Read ODT Tracking: ON
9163 17:41:58.400073 Refresh Rate DeBounce: ON
9164 17:41:58.404013 DFS_NO_QUEUE_FLUSH: ON
9165 17:41:58.406671 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9166 17:41:58.410458 ENABLE_DFS_RUNTIME_MRW: OFF
9167 17:41:58.410543 DDR_RESERVE_NEW_MODE: ON
9168 17:41:58.413674 MR_CBT_SWITCH_FREQ: ON
9169 17:41:58.417086 =========================
9170 17:41:58.435005 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9171 17:41:58.438571 dram_init: ddr_geometry: 2
9172 17:41:58.456590 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9173 17:41:58.459892 dram_init: dram init end (result: 0)
9174 17:41:58.466653 DRAM-K: Full calibration passed in 24569 msecs
9175 17:41:58.469898 MRC: failed to locate region type 0.
9176 17:41:58.469997 DRAM rank0 size:0x100000000,
9177 17:41:58.473736 DRAM rank1 size=0x100000000
9178 17:41:58.483271 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9179 17:41:58.489572 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9180 17:41:58.496545 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9181 17:41:58.502974 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9182 17:41:58.506925 DRAM rank0 size:0x100000000,
9183 17:41:58.509795 DRAM rank1 size=0x100000000
9184 17:41:58.509886 CBMEM:
9185 17:41:58.513686 IMD: root @ 0xfffff000 254 entries.
9186 17:41:58.516702 IMD: root @ 0xffffec00 62 entries.
9187 17:41:58.520206 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9188 17:41:58.523198 WARNING: RO_VPD is uninitialized or empty.
9189 17:41:58.529686 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9190 17:41:58.536843 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9191 17:41:58.549121 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9192 17:41:58.560724 BS: romstage times (exec / console): total (unknown) / 24078 ms
9193 17:41:58.560869
9194 17:41:58.560942
9195 17:41:58.570891 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9196 17:41:58.574120 ARM64: Exception handlers installed.
9197 17:41:58.577372 ARM64: Testing exception
9198 17:41:58.577479 ARM64: Done test exception
9199 17:41:58.580731 Enumerating buses...
9200 17:41:58.584487 Show all devs... Before device enumeration.
9201 17:41:58.587824 Root Device: enabled 1
9202 17:41:58.591168 CPU_CLUSTER: 0: enabled 1
9203 17:41:58.591278 CPU: 00: enabled 1
9204 17:41:58.594523 Compare with tree...
9205 17:41:58.594614 Root Device: enabled 1
9206 17:41:58.597449 CPU_CLUSTER: 0: enabled 1
9207 17:41:58.600955 CPU: 00: enabled 1
9208 17:41:58.601050 Root Device scanning...
9209 17:41:58.604261 scan_static_bus for Root Device
9210 17:41:58.607725 CPU_CLUSTER: 0 enabled
9211 17:41:58.611332 scan_static_bus for Root Device done
9212 17:41:58.614214 scan_bus: bus Root Device finished in 8 msecs
9213 17:41:58.614306 done
9214 17:41:58.620730 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9215 17:41:58.624432 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9216 17:41:58.627662 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9217 17:41:58.634378 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9218 17:41:58.637886 Allocating resources...
9219 17:41:58.637996 Reading resources...
9220 17:41:58.641192 Root Device read_resources bus 0 link: 0
9221 17:41:58.645041 DRAM rank0 size:0x100000000,
9222 17:41:58.647752 DRAM rank1 size=0x100000000
9223 17:41:58.651232 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9224 17:41:58.654477 CPU: 00 missing read_resources
9225 17:41:58.657795 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9226 17:41:58.661151 Root Device read_resources bus 0 link: 0 done
9227 17:41:58.664822 Done reading resources.
9228 17:41:58.671554 Show resources in subtree (Root Device)...After reading.
9229 17:41:58.674566 Root Device child on link 0 CPU_CLUSTER: 0
9230 17:41:58.677729 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 17:41:58.684391 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 17:41:58.704871 CPU: 00
9233 17:41:58.705251 Root Device assign_resources, bus 0 link: 0
9234 17:41:58.705564 CPU_CLUSTER: 0 missing set_resources
9235 17:41:58.705948 Root Device assign_resources, bus 0 link: 0 done
9236 17:41:58.706202 Done setting resources.
9237 17:41:58.708043 Show resources in subtree (Root Device)...After assigning values.
9238 17:41:58.711504 Root Device child on link 0 CPU_CLUSTER: 0
9239 17:41:58.714787 CPU_CLUSTER: 0 child on link 0 CPU: 00
9240 17:41:58.721429 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9241 17:41:58.724750 CPU: 00
9242 17:41:58.724912 Done allocating resources.
9243 17:41:58.731286 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9244 17:41:58.734824 Enabling resources...
9245 17:41:58.734952 done.
9246 17:41:58.738223 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9247 17:41:58.741606 Initializing devices...
9248 17:41:58.741716 Root Device init
9249 17:41:58.745020 init hardware done!
9250 17:41:58.748013 0x00000018: ctrlr->caps
9251 17:41:58.748109 52.000 MHz: ctrlr->f_max
9252 17:41:58.751558 0.400 MHz: ctrlr->f_min
9253 17:41:58.754664 0x40ff8080: ctrlr->voltages
9254 17:41:58.754793 sclk: 390625
9255 17:41:58.754861 Bus Width = 1
9256 17:41:58.757855 sclk: 390625
9257 17:41:58.757942 Bus Width = 1
9258 17:41:58.761197 Early init status = 3
9259 17:41:58.764458 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9260 17:41:58.768633 in-header: 03 fc 00 00 01 00 00 00
9261 17:41:58.771665 in-data: 00
9262 17:41:58.774501 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9263 17:41:58.779458 in-header: 03 fd 00 00 00 00 00 00
9264 17:41:58.783226 in-data:
9265 17:41:58.786320 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9266 17:41:58.789557 in-header: 03 fc 00 00 01 00 00 00
9267 17:41:58.793167 in-data: 00
9268 17:41:58.795991 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9269 17:41:58.800522 in-header: 03 fd 00 00 00 00 00 00
9270 17:41:58.804101 in-data:
9271 17:41:58.807288 [SSUSB] Setting up USB HOST controller...
9272 17:41:58.810441 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9273 17:41:58.813878 [SSUSB] phy power-on done.
9274 17:41:58.865417 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9275 17:41:58.865991 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9276 17:41:58.866471 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9277 17:41:58.866946 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9278 17:41:58.867408 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9279 17:41:58.867858 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9280 17:41:58.868335 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9281 17:41:58.868783 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9282 17:41:58.869227 SPM: binary array size = 0x9dc
9283 17:41:58.869997 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9284 17:41:58.874482 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9285 17:41:58.880914 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9286 17:41:58.884627 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9287 17:41:58.887750 configure_display: Starting display init
9288 17:41:58.923971 anx7625_power_on_init: Init interface.
9289 17:41:58.927330 anx7625_disable_pd_protocol: Disabled PD feature.
9290 17:41:58.955217 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9291 17:41:58.958522 anx7625_start_dp_work: Secure OCM version=00
9292 17:41:58.961657 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9293 17:41:58.976911 sp_tx_get_edid_block: EDID Block = 1
9294 17:41:59.079147 Extracted contents:
9295 17:41:59.082530 header: 00 ff ff ff ff ff ff 00
9296 17:41:59.085365 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9297 17:41:59.089028 version: 01 04
9298 17:41:59.092312 basic params: 95 1f 11 78 0a
9299 17:41:59.095655 chroma info: 76 90 94 55 54 90 27 21 50 54
9300 17:41:59.099160 established: 00 00 00
9301 17:41:59.105825 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9302 17:41:59.109239 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9303 17:41:59.115792 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9304 17:41:59.122067 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9305 17:41:59.129616 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9306 17:41:59.132418 extensions: 00
9307 17:41:59.132536 checksum: fb
9308 17:41:59.132604
9309 17:41:59.135598 Manufacturer: IVO Model 57d Serial Number 0
9310 17:41:59.139124 Made week 0 of 2020
9311 17:41:59.139237 EDID version: 1.4
9312 17:41:59.142197 Digital display
9313 17:41:59.145966 6 bits per primary color channel
9314 17:41:59.146109 DisplayPort interface
9315 17:41:59.148840 Maximum image size: 31 cm x 17 cm
9316 17:41:59.148957 Gamma: 220%
9317 17:41:59.152136 Check DPMS levels
9318 17:41:59.155583 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9319 17:41:59.159320 First detailed timing is preferred timing
9320 17:41:59.162354 Established timings supported:
9321 17:41:59.165505 Standard timings supported:
9322 17:41:59.165612 Detailed timings
9323 17:41:59.172521 Hex of detail: 383680a07038204018303c0035ae10000019
9324 17:41:59.175868 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9325 17:41:59.179036 0780 0798 07c8 0820 hborder 0
9326 17:41:59.185804 0438 043b 0447 0458 vborder 0
9327 17:41:59.185924 -hsync -vsync
9328 17:41:59.189371 Did detailed timing
9329 17:41:59.192890 Hex of detail: 000000000000000000000000000000000000
9330 17:41:59.195976 Manufacturer-specified data, tag 0
9331 17:41:59.202491 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9332 17:41:59.202615 ASCII string: InfoVision
9333 17:41:59.209018 Hex of detail: 000000fe00523134304e574635205248200a
9334 17:41:59.209170 ASCII string: R140NWF5 RH
9335 17:41:59.212376 Checksum
9336 17:41:59.212526 Checksum: 0xfb (valid)
9337 17:41:59.219101 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9338 17:41:59.219243 DSI data_rate: 832800000 bps
9339 17:41:59.226841 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9340 17:41:59.230189 anx7625_parse_edid: pixelclock(138800).
9341 17:41:59.233264 hactive(1920), hsync(48), hfp(24), hbp(88)
9342 17:41:59.236474 vactive(1080), vsync(12), vfp(3), vbp(17)
9343 17:41:59.239652 anx7625_dsi_config: config dsi.
9344 17:41:59.246738 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9345 17:41:59.261248 anx7625_dsi_config: success to config DSI
9346 17:41:59.264232 anx7625_dp_start: MIPI phy setup OK.
9347 17:41:59.267892 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9348 17:41:59.271568 mtk_ddp_mode_set invalid vrefresh 60
9349 17:41:59.274678 main_disp_path_setup
9350 17:41:59.274779 ovl_layer_smi_id_en
9351 17:41:59.277510 ovl_layer_smi_id_en
9352 17:41:59.277595 ccorr_config
9353 17:41:59.277661 aal_config
9354 17:41:59.281128 gamma_config
9355 17:41:59.281212 postmask_config
9356 17:41:59.284316 dither_config
9357 17:41:59.287848 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9358 17:41:59.294156 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9359 17:41:59.297863 Root Device init finished in 551 msecs
9360 17:41:59.297968 CPU_CLUSTER: 0 init
9361 17:41:59.307504 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9362 17:41:59.310866 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9363 17:41:59.314289 APU_MBOX 0x190000b0 = 0x10001
9364 17:41:59.317427 APU_MBOX 0x190001b0 = 0x10001
9365 17:41:59.321236 APU_MBOX 0x190005b0 = 0x10001
9366 17:41:59.324251 APU_MBOX 0x190006b0 = 0x10001
9367 17:41:59.327837 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9368 17:41:59.340147 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9369 17:41:59.352839 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9370 17:41:59.359470 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9371 17:41:59.370708 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9372 17:41:59.379594 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9373 17:41:59.383089 CPU_CLUSTER: 0 init finished in 81 msecs
9374 17:41:59.386654 Devices initialized
9375 17:41:59.389793 Show all devs... After init.
9376 17:41:59.389888 Root Device: enabled 1
9377 17:41:59.393318 CPU_CLUSTER: 0: enabled 1
9378 17:41:59.396268 CPU: 00: enabled 1
9379 17:41:59.399725 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9380 17:41:59.403316 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9381 17:41:59.406288 ELOG: NV offset 0x57f000 size 0x1000
9382 17:41:59.413200 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9383 17:41:59.419985 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9384 17:41:59.423395 ELOG: Event(17) added with size 13 at 2023-09-13 17:41:58 UTC
9385 17:41:59.426128 out: cmd=0x121: 03 db 21 01 00 00 00 00
9386 17:41:59.430412 in-header: 03 d3 00 00 2c 00 00 00
9387 17:41:59.443612 in-data: 8c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9388 17:41:59.450257 ELOG: Event(A1) added with size 10 at 2023-09-13 17:41:58 UTC
9389 17:41:59.457210 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9390 17:41:59.463696 ELOG: Event(A0) added with size 9 at 2023-09-13 17:41:58 UTC
9391 17:41:59.466919 elog_add_boot_reason: Logged dev mode boot
9392 17:41:59.470187 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9393 17:41:59.473772 Finalize devices...
9394 17:41:59.473864 Devices finalized
9395 17:41:59.480561 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9396 17:41:59.483701 Writing coreboot table at 0xffe64000
9397 17:41:59.487185 0. 000000000010a000-0000000000113fff: RAMSTAGE
9398 17:41:59.490319 1. 0000000040000000-00000000400fffff: RAM
9399 17:41:59.493595 2. 0000000040100000-000000004032afff: RAMSTAGE
9400 17:41:59.500470 3. 000000004032b000-00000000545fffff: RAM
9401 17:41:59.503836 4. 0000000054600000-000000005465ffff: BL31
9402 17:41:59.506829 5. 0000000054660000-00000000ffe63fff: RAM
9403 17:41:59.510796 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9404 17:41:59.517115 7. 0000000100000000-000000023fffffff: RAM
9405 17:41:59.517222 Passing 5 GPIOs to payload:
9406 17:41:59.523645 NAME | PORT | POLARITY | VALUE
9407 17:41:59.527497 EC in RW | 0x000000aa | low | undefined
9408 17:41:59.530582 EC interrupt | 0x00000005 | low | undefined
9409 17:41:59.537178 TPM interrupt | 0x000000ab | high | undefined
9410 17:41:59.540386 SD card detect | 0x00000011 | high | undefined
9411 17:41:59.547109 speaker enable | 0x00000093 | high | undefined
9412 17:41:59.550215 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9413 17:41:59.553586 in-header: 03 f9 00 00 02 00 00 00
9414 17:41:59.553678 in-data: 02 00
9415 17:41:59.557026 ADC[4]: Raw value=899483 ID=7
9416 17:41:59.560556 ADC[3]: Raw value=213336 ID=1
9417 17:41:59.560647 RAM Code: 0x71
9418 17:41:59.564100 ADC[6]: Raw value=74926 ID=0
9419 17:41:59.567070 ADC[5]: Raw value=212229 ID=1
9420 17:41:59.567166 SKU Code: 0x1
9421 17:41:59.573785 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9422 17:41:59.577120 coreboot table: 964 bytes.
9423 17:41:59.580861 IMD ROOT 0. 0xfffff000 0x00001000
9424 17:41:59.583657 IMD SMALL 1. 0xffffe000 0x00001000
9425 17:41:59.587187 RO MCACHE 2. 0xffffc000 0x00001104
9426 17:41:59.590549 CONSOLE 3. 0xfff7c000 0x00080000
9427 17:41:59.594253 FMAP 4. 0xfff7b000 0x00000452
9428 17:41:59.597561 TIME STAMP 5. 0xfff7a000 0x00000910
9429 17:41:59.600226 VBOOT WORK 6. 0xfff66000 0x00014000
9430 17:41:59.600318 RAMOOPS 7. 0xffe66000 0x00100000
9431 17:41:59.603940 COREBOOT 8. 0xffe64000 0x00002000
9432 17:41:59.607196 IMD small region:
9433 17:41:59.610442 IMD ROOT 0. 0xffffec00 0x00000400
9434 17:41:59.613956 VPD 1. 0xffffeb80 0x0000006c
9435 17:41:59.617121 MMC STATUS 2. 0xffffeb60 0x00000004
9436 17:41:59.623781 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9437 17:41:59.623897 Probing TPM: done!
9438 17:41:59.630970 Connected to device vid:did:rid of 1ae0:0028:00
9439 17:41:59.637829 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9440 17:41:59.640735 Initialized TPM device CR50 revision 0
9441 17:41:59.644060 Checking cr50 for pending updates
9442 17:41:59.650086 Reading cr50 TPM mode
9443 17:41:59.658295 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9444 17:41:59.665112 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9445 17:41:59.704955 read SPI 0x3990ec 0x4f1b0: 34853 us, 9296 KB/s, 74.368 Mbps
9446 17:41:59.708419 Checking segment from ROM address 0x40100000
9447 17:41:59.711716 Checking segment from ROM address 0x4010001c
9448 17:41:59.718549 Loading segment from ROM address 0x40100000
9449 17:41:59.718659 code (compression=0)
9450 17:41:59.725009 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9451 17:41:59.735173 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9452 17:41:59.735309 it's not compressed!
9453 17:41:59.742134 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9454 17:41:59.745566 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9455 17:41:59.765451 Loading segment from ROM address 0x4010001c
9456 17:41:59.765597 Entry Point 0x80000000
9457 17:41:59.768753 Loaded segments
9458 17:41:59.771988 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9459 17:41:59.778660 Jumping to boot code at 0x80000000(0xffe64000)
9460 17:41:59.785426 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9461 17:41:59.792292 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9462 17:41:59.799648 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9463 17:41:59.803281 Checking segment from ROM address 0x40100000
9464 17:41:59.806440 Checking segment from ROM address 0x4010001c
9465 17:41:59.809854 Loading segment from ROM address 0x40100000
9466 17:41:59.813382 code (compression=1)
9467 17:41:59.820327 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9468 17:41:59.830223 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9469 17:41:59.830354 using LZMA
9470 17:41:59.838479 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9471 17:41:59.845205 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9472 17:41:59.848425 Loading segment from ROM address 0x4010001c
9473 17:41:59.848525 Entry Point 0x54601000
9474 17:41:59.851619 Loaded segments
9475 17:41:59.854988 NOTICE: MT8192 bl31_setup
9476 17:41:59.861738 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9477 17:41:59.865462 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9478 17:41:59.868672 WARNING: region 0:
9479 17:41:59.871683 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 17:41:59.871773 WARNING: region 1:
9481 17:41:59.878914 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9482 17:41:59.881944 WARNING: region 2:
9483 17:41:59.885353 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9484 17:41:59.888436 WARNING: region 3:
9485 17:41:59.892068 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9486 17:41:59.895676 WARNING: region 4:
9487 17:41:59.898587 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9488 17:41:59.902492 WARNING: region 5:
9489 17:41:59.905396 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 17:41:59.908792 WARNING: region 6:
9491 17:41:59.912149 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 17:41:59.912244 WARNING: region 7:
9493 17:41:59.919159 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 17:41:59.925526 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9495 17:41:59.929254 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9496 17:41:59.932455 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9497 17:41:59.935830 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9498 17:41:59.942701 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9499 17:41:59.945685 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9500 17:41:59.952894 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9501 17:41:59.955914 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9502 17:41:59.959476 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9503 17:41:59.965736 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9504 17:41:59.969378 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9505 17:41:59.972794 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9506 17:41:59.979880 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9507 17:41:59.982648 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9508 17:41:59.985942 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9509 17:41:59.992695 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9510 17:41:59.995941 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9511 17:42:00.003111 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9512 17:42:00.006255 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9513 17:42:00.009433 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9514 17:42:00.016360 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9515 17:42:00.019757 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9516 17:42:00.023182 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9517 17:42:00.029995 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9518 17:42:00.033406 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9519 17:42:00.040459 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9520 17:42:00.043192 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9521 17:42:00.046645 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9522 17:42:00.053143 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9523 17:42:00.056652 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9524 17:42:00.063258 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9525 17:42:00.066536 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9526 17:42:00.070115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9527 17:42:00.073562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9528 17:42:00.080147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9529 17:42:00.083399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9530 17:42:00.086640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9531 17:42:00.090514 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9532 17:42:00.093409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9533 17:42:00.100421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9534 17:42:00.104002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9535 17:42:00.106949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9536 17:42:00.110622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9537 17:42:00.117398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9538 17:42:00.120627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9539 17:42:00.123880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9540 17:42:00.127235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9541 17:42:00.134098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9542 17:42:00.137626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9543 17:42:00.140861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9544 17:42:00.147479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9545 17:42:00.150971 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9546 17:42:00.157381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9547 17:42:00.160922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9548 17:42:00.164470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9549 17:42:00.170935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9550 17:42:00.174575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9551 17:42:00.181262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9552 17:42:00.184823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9553 17:42:00.190913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9554 17:42:00.194480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9555 17:42:00.198098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9556 17:42:00.204878 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9557 17:42:00.208332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9558 17:42:00.214803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9559 17:42:00.218012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9560 17:42:00.225164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9561 17:42:00.228132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9562 17:42:00.231478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9563 17:42:00.238335 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9564 17:42:00.242054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9565 17:42:00.248269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9566 17:42:00.251869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9567 17:42:00.255142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9568 17:42:00.261701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9569 17:42:00.265175 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9570 17:42:00.272035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9571 17:42:00.275095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9572 17:42:00.281968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9573 17:42:00.285114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9574 17:42:00.291795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9575 17:42:00.295490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9576 17:42:00.298826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9577 17:42:00.305572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9578 17:42:00.308606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9579 17:42:00.315347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9580 17:42:00.318613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9581 17:42:00.322220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9582 17:42:00.328687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9583 17:42:00.332315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9584 17:42:00.338984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9585 17:42:00.342267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9586 17:42:00.348994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9587 17:42:00.352398 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9588 17:42:00.355514 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9589 17:42:00.362282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9590 17:42:00.365883 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9591 17:42:00.368784 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9592 17:42:00.375748 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9593 17:42:00.379255 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9594 17:42:00.382947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9595 17:42:00.385776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9596 17:42:00.392724 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9597 17:42:00.396000 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9598 17:42:00.402303 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9599 17:42:00.405699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9600 17:42:00.409462 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9601 17:42:00.416202 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9602 17:42:00.419292 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9603 17:42:00.425814 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9604 17:42:00.429406 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9605 17:42:00.432915 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9606 17:42:00.439209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9607 17:42:00.442617 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9608 17:42:00.449446 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9609 17:42:00.452655 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9610 17:42:00.456065 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9611 17:42:00.459456 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9612 17:42:00.466077 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9613 17:42:00.469712 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9614 17:42:00.472653 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9615 17:42:00.476158 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9616 17:42:00.483301 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9617 17:42:00.486051 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9618 17:42:00.489636 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9619 17:42:00.496674 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9620 17:42:00.499678 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9621 17:42:00.503105 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9622 17:42:00.509718 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9623 17:42:00.513012 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9624 17:42:00.519662 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9625 17:42:00.522998 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9626 17:42:00.526443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9627 17:42:00.533375 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9628 17:42:00.536553 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9629 17:42:00.539959 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9630 17:42:00.546493 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9631 17:42:00.550146 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9632 17:42:00.556724 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9633 17:42:00.560089 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9634 17:42:00.563527 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9635 17:42:00.570127 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9636 17:42:00.573446 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9637 17:42:00.580198 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9638 17:42:00.583905 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9639 17:42:00.586611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9640 17:42:00.593788 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9641 17:42:00.597123 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9642 17:42:00.600711 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9643 17:42:00.606944 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9644 17:42:00.610432 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9645 17:42:00.613548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9646 17:42:00.620518 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9647 17:42:00.624094 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9648 17:42:00.630516 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9649 17:42:00.633735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9650 17:42:00.637703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9651 17:42:00.644338 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9652 17:42:00.647524 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9653 17:42:00.650650 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9654 17:42:00.657463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9655 17:42:00.660510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9656 17:42:00.667572 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9657 17:42:00.671100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9658 17:42:00.674663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9659 17:42:00.681034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9660 17:42:00.684000 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9661 17:42:00.691346 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9662 17:42:00.694440 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9663 17:42:00.697179 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9664 17:42:00.703950 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9665 17:42:00.707410 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9666 17:42:00.710719 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9667 17:42:00.717106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9668 17:42:00.720677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9669 17:42:00.727355 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9670 17:42:00.730629 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9671 17:42:00.734356 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9672 17:42:00.740597 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9673 17:42:00.743771 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9674 17:42:00.750351 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9675 17:42:00.753651 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9676 17:42:00.757078 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9677 17:42:00.763943 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9678 17:42:00.767396 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9679 17:42:00.773993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9680 17:42:00.777262 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9681 17:42:00.780805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9682 17:42:00.787358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9683 17:42:00.791806 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9684 17:42:00.796778 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9685 17:42:00.800474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9686 17:42:00.803867 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9687 17:42:00.810179 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9688 17:42:00.813708 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9689 17:42:00.820405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9690 17:42:00.823901 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9691 17:42:00.830208 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9692 17:42:00.833476 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9693 17:42:00.837239 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9694 17:42:00.843710 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9695 17:42:00.847019 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9696 17:42:00.853856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9697 17:42:00.857437 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9698 17:42:00.860293 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9699 17:42:00.867013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9700 17:42:00.870317 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9701 17:42:00.876857 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9702 17:42:00.880106 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9703 17:42:00.883707 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9704 17:42:00.890084 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9705 17:42:00.893472 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9706 17:42:00.900130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9707 17:42:00.903691 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9708 17:42:00.910160 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9709 17:42:00.913385 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9710 17:42:00.916807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9711 17:42:00.923376 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9712 17:42:00.927001 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9713 17:42:00.933559 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9714 17:42:00.936715 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9715 17:42:00.940597 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9716 17:42:00.947175 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9717 17:42:00.950292 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9718 17:42:00.956867 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9719 17:42:00.960232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9720 17:42:00.963659 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9721 17:42:00.970556 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9722 17:42:00.973558 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9723 17:42:00.977159 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9724 17:42:00.983483 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9725 17:42:00.986916 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9726 17:42:00.990376 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9727 17:42:00.993727 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9728 17:42:01.000093 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9729 17:42:01.003591 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9730 17:42:01.009961 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9731 17:42:01.013356 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9732 17:42:01.016918 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9733 17:42:01.023668 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9734 17:42:01.026611 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9735 17:42:01.029976 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9736 17:42:01.036841 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9737 17:42:01.040420 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9738 17:42:01.043870 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9739 17:42:01.050350 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9740 17:42:01.053585 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9741 17:42:01.060487 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9742 17:42:01.063749 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9743 17:42:01.067344 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9744 17:42:01.073351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9745 17:42:01.076735 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9746 17:42:01.079910 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9747 17:42:01.086994 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9748 17:42:01.090341 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9749 17:42:01.093376 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9750 17:42:01.100473 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9751 17:42:01.103549 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9752 17:42:01.106714 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9753 17:42:01.113663 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9754 17:42:01.116678 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9755 17:42:01.123714 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9756 17:42:01.126569 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9757 17:42:01.130077 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9758 17:42:01.136864 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9759 17:42:01.139920 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9760 17:42:01.143363 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9761 17:42:01.150085 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9762 17:42:01.153232 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9763 17:42:01.156683 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9764 17:42:01.159913 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9765 17:42:01.166836 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9766 17:42:01.169892 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9767 17:42:01.173553 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9768 17:42:01.176405 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9769 17:42:01.182992 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9770 17:42:01.186374 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9771 17:42:01.190369 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9772 17:42:01.193527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9773 17:42:01.199947 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9774 17:42:01.203370 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9775 17:42:01.206539 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9776 17:42:01.213369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9777 17:42:01.216698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9778 17:42:01.220223 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9779 17:42:01.226743 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9780 17:42:01.230069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9781 17:42:01.236674 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9782 17:42:01.240359 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9783 17:42:01.243568 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9784 17:42:01.250103 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9785 17:42:01.253212 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9786 17:42:01.259908 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9787 17:42:01.263495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9788 17:42:01.267253 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9789 17:42:01.273308 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9790 17:42:01.276453 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9791 17:42:01.283540 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9792 17:42:01.286522 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9793 17:42:01.289904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9794 17:42:01.296622 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9795 17:42:01.299931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9796 17:42:01.306656 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9797 17:42:01.310033 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9798 17:42:01.313197 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9799 17:42:01.320240 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9800 17:42:01.323538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9801 17:42:01.330421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9802 17:42:01.334064 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9803 17:42:01.336836 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9804 17:42:01.344143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9805 17:42:01.347081 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9806 17:42:01.353803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9807 17:42:01.357212 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9808 17:42:01.360164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9809 17:42:01.367060 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9810 17:42:01.370112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9811 17:42:01.376834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9812 17:42:01.380400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9813 17:42:01.383793 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9814 17:42:01.390061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9815 17:42:01.393562 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9816 17:42:01.400361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9817 17:42:01.403432 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9818 17:42:01.406889 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9819 17:42:01.413806 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9820 17:42:01.416991 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9821 17:42:01.423739 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9822 17:42:01.426869 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9823 17:42:01.430197 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9824 17:42:01.437243 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9825 17:42:01.440194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9826 17:42:01.447023 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9827 17:42:01.450187 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9828 17:42:01.453540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9829 17:42:01.460667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9830 17:42:01.463525 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9831 17:42:01.470446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9832 17:42:01.474017 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9833 17:42:01.477062 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9834 17:42:01.483934 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9835 17:42:01.487222 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9836 17:42:01.493504 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9837 17:42:01.497180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9838 17:42:01.503579 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9839 17:42:01.506973 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9840 17:42:01.510603 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9841 17:42:01.516999 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9842 17:42:01.520671 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9843 17:42:01.523981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9844 17:42:01.530292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9845 17:42:01.533916 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9846 17:42:01.540269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9847 17:42:01.543654 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9848 17:42:01.547157 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9849 17:42:01.554219 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9850 17:42:01.556899 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9851 17:42:01.563554 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9852 17:42:01.566967 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9853 17:42:01.573552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9854 17:42:01.577286 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9855 17:42:01.580479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9856 17:42:01.587270 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9857 17:42:01.590286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9858 17:42:01.597270 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9859 17:42:01.600260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9860 17:42:01.607087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9861 17:42:01.610193 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9862 17:42:01.617014 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9863 17:42:01.620660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9864 17:42:01.623561 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9865 17:42:01.630147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9866 17:42:01.633490 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9867 17:42:01.640457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9868 17:42:01.643730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9869 17:42:01.650642 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9870 17:42:01.653393 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9871 17:42:01.657219 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9872 17:42:01.664086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9873 17:42:01.666902 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9874 17:42:01.674118 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9875 17:42:01.677283 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9876 17:42:01.683732 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9877 17:42:01.687094 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9878 17:42:01.690123 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9879 17:42:01.696887 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9880 17:42:01.700045 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9881 17:42:01.706669 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9882 17:42:01.710585 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9883 17:42:01.717041 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9884 17:42:01.720152 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9885 17:42:01.723460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9886 17:42:01.730350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9887 17:42:01.733902 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9888 17:42:01.740066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9889 17:42:01.743452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9890 17:42:01.750428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9891 17:42:01.753606 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9892 17:42:01.756883 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9893 17:42:01.763836 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9894 17:42:01.766689 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9895 17:42:01.773890 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9896 17:42:01.776813 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9897 17:42:01.780055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9898 17:42:01.787126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9899 17:42:01.790483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9900 17:42:01.797033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9901 17:42:01.800722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9902 17:42:01.806682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9903 17:42:01.810398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9904 17:42:01.817090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9905 17:42:01.820554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9906 17:42:01.826926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9907 17:42:01.830411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9908 17:42:01.833672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9909 17:42:01.840328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9910 17:42:01.843965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9911 17:42:01.850509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9912 17:42:01.853655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9913 17:42:01.860744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9914 17:42:01.863423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9915 17:42:01.870539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9916 17:42:01.873764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9917 17:42:01.880099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9918 17:42:01.883613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9919 17:42:01.890455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9920 17:42:01.893383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9921 17:42:01.900084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9922 17:42:01.903851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9923 17:42:01.910002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9924 17:42:01.913329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9925 17:42:01.920289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9926 17:42:01.923340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9927 17:42:01.930264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9928 17:42:01.933354 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9929 17:42:01.936685 INFO: [APUAPC] vio 0
9930 17:42:01.940022 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9931 17:42:01.946616 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9932 17:42:01.950289 INFO: [APUAPC] D0_APC_0: 0x400510
9933 17:42:01.950397 INFO: [APUAPC] D0_APC_1: 0x0
9934 17:42:01.953814 INFO: [APUAPC] D0_APC_2: 0x1540
9935 17:42:01.956855 INFO: [APUAPC] D0_APC_3: 0x0
9936 17:42:01.960398 INFO: [APUAPC] D1_APC_0: 0xffffffff
9937 17:42:01.963659 INFO: [APUAPC] D1_APC_1: 0xffffffff
9938 17:42:01.966995 INFO: [APUAPC] D1_APC_2: 0x3fffff
9939 17:42:01.969825 INFO: [APUAPC] D1_APC_3: 0x0
9940 17:42:01.973640 INFO: [APUAPC] D2_APC_0: 0xffffffff
9941 17:42:01.976854 INFO: [APUAPC] D2_APC_1: 0xffffffff
9942 17:42:01.979791 INFO: [APUAPC] D2_APC_2: 0x3fffff
9943 17:42:01.983313 INFO: [APUAPC] D2_APC_3: 0x0
9944 17:42:01.986621 INFO: [APUAPC] D3_APC_0: 0xffffffff
9945 17:42:01.990086 INFO: [APUAPC] D3_APC_1: 0xffffffff
9946 17:42:01.993740 INFO: [APUAPC] D3_APC_2: 0x3fffff
9947 17:42:01.996954 INFO: [APUAPC] D3_APC_3: 0x0
9948 17:42:01.999974 INFO: [APUAPC] D4_APC_0: 0xffffffff
9949 17:42:02.003599 INFO: [APUAPC] D4_APC_1: 0xffffffff
9950 17:42:02.006381 INFO: [APUAPC] D4_APC_2: 0x3fffff
9951 17:42:02.010333 INFO: [APUAPC] D4_APC_3: 0x0
9952 17:42:02.013763 INFO: [APUAPC] D5_APC_0: 0xffffffff
9953 17:42:02.016723 INFO: [APUAPC] D5_APC_1: 0xffffffff
9954 17:42:02.020293 INFO: [APUAPC] D5_APC_2: 0x3fffff
9955 17:42:02.023704 INFO: [APUAPC] D5_APC_3: 0x0
9956 17:42:02.026868 INFO: [APUAPC] D6_APC_0: 0xffffffff
9957 17:42:02.030001 INFO: [APUAPC] D6_APC_1: 0xffffffff
9958 17:42:02.033502 INFO: [APUAPC] D6_APC_2: 0x3fffff
9959 17:42:02.036778 INFO: [APUAPC] D6_APC_3: 0x0
9960 17:42:02.040666 INFO: [APUAPC] D7_APC_0: 0xffffffff
9961 17:42:02.043451 INFO: [APUAPC] D7_APC_1: 0xffffffff
9962 17:42:02.047108 INFO: [APUAPC] D7_APC_2: 0x3fffff
9963 17:42:02.050206 INFO: [APUAPC] D7_APC_3: 0x0
9964 17:42:02.053554 INFO: [APUAPC] D8_APC_0: 0xffffffff
9965 17:42:02.057136 INFO: [APUAPC] D8_APC_1: 0xffffffff
9966 17:42:02.060508 INFO: [APUAPC] D8_APC_2: 0x3fffff
9967 17:42:02.060604 INFO: [APUAPC] D8_APC_3: 0x0
9968 17:42:02.063939 INFO: [APUAPC] D9_APC_0: 0xffffffff
9969 17:42:02.066929 INFO: [APUAPC] D9_APC_1: 0xffffffff
9970 17:42:02.070705 INFO: [APUAPC] D9_APC_2: 0x3fffff
9971 17:42:02.073548 INFO: [APUAPC] D9_APC_3: 0x0
9972 17:42:02.077141 INFO: [APUAPC] D10_APC_0: 0xffffffff
9973 17:42:02.081041 INFO: [APUAPC] D10_APC_1: 0xffffffff
9974 17:42:02.083850 INFO: [APUAPC] D10_APC_2: 0x3fffff
9975 17:42:02.087236 INFO: [APUAPC] D10_APC_3: 0x0
9976 17:42:02.090645 INFO: [APUAPC] D11_APC_0: 0xffffffff
9977 17:42:02.094216 INFO: [APUAPC] D11_APC_1: 0xffffffff
9978 17:42:02.097426 INFO: [APUAPC] D11_APC_2: 0x3fffff
9979 17:42:02.100973 INFO: [APUAPC] D11_APC_3: 0x0
9980 17:42:02.103764 INFO: [APUAPC] D12_APC_0: 0xffffffff
9981 17:42:02.107448 INFO: [APUAPC] D12_APC_1: 0xffffffff
9982 17:42:02.110450 INFO: [APUAPC] D12_APC_2: 0x3fffff
9983 17:42:02.114263 INFO: [APUAPC] D12_APC_3: 0x0
9984 17:42:02.117348 INFO: [APUAPC] D13_APC_0: 0xffffffff
9985 17:42:02.120823 INFO: [APUAPC] D13_APC_1: 0xffffffff
9986 17:42:02.123698 INFO: [APUAPC] D13_APC_2: 0x3fffff
9987 17:42:02.127143 INFO: [APUAPC] D13_APC_3: 0x0
9988 17:42:02.130832 INFO: [APUAPC] D14_APC_0: 0xffffffff
9989 17:42:02.133789 INFO: [APUAPC] D14_APC_1: 0xffffffff
9990 17:42:02.137274 INFO: [APUAPC] D14_APC_2: 0x3fffff
9991 17:42:02.140493 INFO: [APUAPC] D14_APC_3: 0x0
9992 17:42:02.143900 INFO: [APUAPC] D15_APC_0: 0xffffffff
9993 17:42:02.147185 INFO: [APUAPC] D15_APC_1: 0xffffffff
9994 17:42:02.150556 INFO: [APUAPC] D15_APC_2: 0x3fffff
9995 17:42:02.153681 INFO: [APUAPC] D15_APC_3: 0x0
9996 17:42:02.157458 INFO: [APUAPC] APC_CON: 0x4
9997 17:42:02.160615 INFO: [NOCDAPC] D0_APC_0: 0x0
9998 17:42:02.164288 INFO: [NOCDAPC] D0_APC_1: 0x0
9999 17:42:02.167307 INFO: [NOCDAPC] D1_APC_0: 0x0
10000 17:42:02.170621 INFO: [NOCDAPC] D1_APC_1: 0xfff
10001 17:42:02.173819 INFO: [NOCDAPC] D2_APC_0: 0x0
10002 17:42:02.173929 INFO: [NOCDAPC] D2_APC_1: 0xfff
10003 17:42:02.177039 INFO: [NOCDAPC] D3_APC_0: 0x0
10004 17:42:02.180468 INFO: [NOCDAPC] D3_APC_1: 0xfff
10005 17:42:02.183903 INFO: [NOCDAPC] D4_APC_0: 0x0
10006 17:42:02.187114 INFO: [NOCDAPC] D4_APC_1: 0xfff
10007 17:42:02.190641 INFO: [NOCDAPC] D5_APC_0: 0x0
10008 17:42:02.193879 INFO: [NOCDAPC] D5_APC_1: 0xfff
10009 17:42:02.197502 INFO: [NOCDAPC] D6_APC_0: 0x0
10010 17:42:02.200561 INFO: [NOCDAPC] D6_APC_1: 0xfff
10011 17:42:02.204280 INFO: [NOCDAPC] D7_APC_0: 0x0
10012 17:42:02.204394 INFO: [NOCDAPC] D7_APC_1: 0xfff
10013 17:42:02.207153 INFO: [NOCDAPC] D8_APC_0: 0x0
10014 17:42:02.210677 INFO: [NOCDAPC] D8_APC_1: 0xfff
10015 17:42:02.213989 INFO: [NOCDAPC] D9_APC_0: 0x0
10016 17:42:02.217495 INFO: [NOCDAPC] D9_APC_1: 0xfff
10017 17:42:02.220882 INFO: [NOCDAPC] D10_APC_0: 0x0
10018 17:42:02.224615 INFO: [NOCDAPC] D10_APC_1: 0xfff
10019 17:42:02.227433 INFO: [NOCDAPC] D11_APC_0: 0x0
10020 17:42:02.230505 INFO: [NOCDAPC] D11_APC_1: 0xfff
10021 17:42:02.234116 INFO: [NOCDAPC] D12_APC_0: 0x0
10022 17:42:02.237427 INFO: [NOCDAPC] D12_APC_1: 0xfff
10023 17:42:02.240848 INFO: [NOCDAPC] D13_APC_0: 0x0
10024 17:42:02.244499 INFO: [NOCDAPC] D13_APC_1: 0xfff
10025 17:42:02.244616 INFO: [NOCDAPC] D14_APC_0: 0x0
10026 17:42:02.247394 INFO: [NOCDAPC] D14_APC_1: 0xfff
10027 17:42:02.250568 INFO: [NOCDAPC] D15_APC_0: 0x0
10028 17:42:02.254014 INFO: [NOCDAPC] D15_APC_1: 0xfff
10029 17:42:02.257430 INFO: [NOCDAPC] APC_CON: 0x4
10030 17:42:02.260776 INFO: [APUAPC] set_apusys_apc done
10031 17:42:02.264229 INFO: [DEVAPC] devapc_init done
10032 17:42:02.267335 INFO: GICv3 without legacy support detected.
10033 17:42:02.274386 INFO: ARM GICv3 driver initialized in EL3
10034 17:42:02.277548 INFO: Maximum SPI INTID supported: 639
10035 17:42:02.280912 INFO: BL31: Initializing runtime services
10036 17:42:02.287394 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10037 17:42:02.287531 INFO: SPM: enable CPC mode
10038 17:42:02.294496 INFO: mcdi ready for mcusys-off-idle and system suspend
10039 17:42:02.297796 INFO: BL31: Preparing for EL3 exit to normal world
10040 17:42:02.300818 INFO: Entry point address = 0x80000000
10041 17:42:02.304186 INFO: SPSR = 0x8
10042 17:42:02.309898
10043 17:42:02.310018
10044 17:42:02.310087
10045 17:42:02.310830 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10046 17:42:02.310939 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10047 17:42:02.311023 Setting prompt string to ['asurada:']
10048 17:42:02.311107 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10049 17:42:02.313246 Starting depthcharge on Spherion...
10050 17:42:02.313331
10051 17:42:02.313395 Wipe memory regions:
10052 17:42:02.313455
10053 17:42:02.316707 [0x00000040000000, 0x00000054600000)
10054 17:42:02.439157
10055 17:42:02.439304 [0x00000054660000, 0x00000080000000)
10056 17:42:02.699431
10057 17:42:02.699587 [0x000000821a7280, 0x000000ffe64000)
10058 17:42:03.444561
10059 17:42:03.444716 [0x00000100000000, 0x00000240000000)
10060 17:42:05.333918
10061 17:42:05.337462 Initializing XHCI USB controller at 0x11200000.
10062 17:42:06.374904
10063 17:42:06.378222 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10064 17:42:06.378313
10065 17:42:06.378378
10066 17:42:06.378437
10067 17:42:06.378743 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 17:42:06.479125 asurada: tftpboot 192.168.201.1 11518283/tftp-deploy-ox_jgt1_/kernel/image.itb 11518283/tftp-deploy-ox_jgt1_/kernel/cmdline
10070 17:42:06.479273 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 17:42:06.479356 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10072 17:42:06.484006 tftpboot 192.168.201.1 11518283/tftp-deploy-ox_jgt1_/kernel/image.ittp-deploy-ox_jgt1_/kernel/cmdline
10073 17:42:06.484092
10074 17:42:06.484157 Waiting for link
10075 17:42:06.644786
10076 17:42:06.644929 R8152: Initializing
10077 17:42:06.644998
10078 17:42:06.647997 Version 6 (ocp_data = 5c30)
10079 17:42:06.648082
10080 17:42:06.650701 R8152: Done initializing
10081 17:42:06.650790
10082 17:42:06.650855 Adding net device
10083 17:42:08.522285
10084 17:42:08.522444 done.
10085 17:42:08.522510
10086 17:42:08.522570 MAC: 00:24:32:30:78:52
10087 17:42:08.522629
10088 17:42:08.525639 Sending DHCP discover... done.
10089 17:42:08.525723
10090 17:42:11.606707 Waiting for reply... done.
10091 17:42:11.606884
10092 17:42:11.607001 Sending DHCP request... done.
10093 17:42:11.612580
10094 17:42:11.618234 Waiting for reply... done.
10095 17:42:11.618317
10096 17:42:11.618381 My ip is 192.168.201.14
10097 17:42:11.618439
10098 17:42:11.621331 The DHCP server ip is 192.168.201.1
10099 17:42:11.621412
10100 17:42:11.628415 TFTP server IP predefined by user: 192.168.201.1
10101 17:42:11.628499
10102 17:42:11.635071 Bootfile predefined by user: 11518283/tftp-deploy-ox_jgt1_/kernel/image.itb
10103 17:42:11.635156
10104 17:42:11.635219 Sending tftp read request... done.
10105 17:42:11.637963
10106 17:42:11.641789 Waiting for the transfer...
10107 17:42:11.641901
10108 17:42:12.239053 00000000 ################################################################
10109 17:42:12.239205
10110 17:42:12.835862 00080000 ################################################################
10111 17:42:12.836020
10112 17:42:13.432695 00100000 ################################################################
10113 17:42:13.432858
10114 17:42:14.020300 00180000 ################################################################
10115 17:42:14.020453
10116 17:42:14.620319 00200000 ################################################################
10117 17:42:14.620766
10118 17:42:15.343361 00280000 ################################################################
10119 17:42:15.343895
10120 17:42:16.074046 00300000 ################################################################
10121 17:42:16.074579
10122 17:42:16.779980 00380000 ################################################################
10123 17:42:16.780455
10124 17:42:17.503059 00400000 ################################################################
10125 17:42:17.503584
10126 17:42:18.230968 00480000 ################################################################
10127 17:42:18.231511
10128 17:42:18.963328 00500000 ################################################################
10129 17:42:18.963856
10130 17:42:19.628811 00580000 ################################################################
10131 17:42:19.629525
10132 17:42:20.219823 00600000 ################################################################
10133 17:42:20.220114
10134 17:42:20.822895 00680000 ################################################################
10135 17:42:20.823227
10136 17:42:21.449959 00700000 ################################################################
10137 17:42:21.450111
10138 17:42:21.994503 00780000 ################################################################
10139 17:42:21.995144
10140 17:42:22.621044 00800000 ################################################################
10141 17:42:22.621432
10142 17:42:23.273377 00880000 ################################################################
10143 17:42:23.274070
10144 17:42:24.002573 00900000 ################################################################
10145 17:42:24.003242
10146 17:42:24.708057 00980000 ################################################################
10147 17:42:24.708570
10148 17:42:25.433133 00a00000 ################################################################
10149 17:42:25.433625
10150 17:42:26.151600 00a80000 ################################################################
10151 17:42:26.152088
10152 17:42:26.862865 00b00000 ################################################################
10153 17:42:26.863364
10154 17:42:27.576787 00b80000 ################################################################
10155 17:42:27.577368
10156 17:42:28.286822 00c00000 ################################################################
10157 17:42:28.287339
10158 17:42:29.001659 00c80000 ################################################################
10159 17:42:29.002156
10160 17:42:29.728329 00d00000 ################################################################
10161 17:42:29.729012
10162 17:42:30.348110 00d80000 ################################################################
10163 17:42:30.348245
10164 17:42:30.871591 00e00000 ################################################################
10165 17:42:30.871743
10166 17:42:31.399454 00e80000 ################################################################
10167 17:42:31.399605
10168 17:42:31.933750 00f00000 ################################################################
10169 17:42:31.933902
10170 17:42:32.464553 00f80000 ################################################################
10171 17:42:32.464689
10172 17:42:33.027502 01000000 ################################################################
10173 17:42:33.027653
10174 17:42:33.589277 01080000 ################################################################
10175 17:42:33.589429
10176 17:42:34.122890 01100000 ################################################################
10177 17:42:34.123061
10178 17:42:34.649263 01180000 ################################################################
10179 17:42:34.649392
10180 17:42:35.201281 01200000 ################################################################
10181 17:42:35.201446
10182 17:42:35.804740 01280000 ################################################################
10183 17:42:35.804875
10184 17:42:36.368203 01300000 ################################################################
10185 17:42:36.368349
10186 17:42:37.010522 01380000 ################################################################
10187 17:42:37.011080
10188 17:42:37.742666 01400000 ################################################################
10189 17:42:37.743220
10190 17:42:38.453691 01480000 ################################################################
10191 17:42:38.454242
10192 17:42:39.164194 01500000 ################################################################
10193 17:42:39.164693
10194 17:42:39.875878 01580000 ################################################################
10195 17:42:39.876519
10196 17:42:40.575711 01600000 ################################################################
10197 17:42:40.576246
10198 17:42:41.288044 01680000 ################################################################
10199 17:42:41.288542
10200 17:42:41.923604 01700000 ################################################################
10201 17:42:41.923740
10202 17:42:42.472622 01780000 ################################################################
10203 17:42:42.472773
10204 17:42:43.058832 01800000 ################################################################
10205 17:42:43.058965
10206 17:42:43.630398 01880000 ################################################################
10207 17:42:43.630570
10208 17:42:44.214860 01900000 ################################################################
10209 17:42:44.215012
10210 17:42:44.802784 01980000 ################################################################
10211 17:42:44.802929
10212 17:42:45.396960 01a00000 ################################################################
10213 17:42:45.397093
10214 17:42:45.983658 01a80000 ################################################################
10215 17:42:45.983798
10216 17:42:46.573765 01b00000 ################################################################
10217 17:42:46.573913
10218 17:42:47.165927 01b80000 ################################################################
10219 17:42:47.166074
10220 17:42:47.754012 01c00000 ################################################################
10221 17:42:47.754149
10222 17:42:48.342511 01c80000 ################################################################
10223 17:42:48.342661
10224 17:42:48.909763 01d00000 ################################################################
10225 17:42:48.909916
10226 17:42:49.499427 01d80000 ################################################################
10227 17:42:49.499631
10228 17:42:50.093863 01e00000 ################################################################
10229 17:42:50.094008
10230 17:42:50.685213 01e80000 ################################################################
10231 17:42:50.685361
10232 17:42:51.265846 01f00000 ################################################################
10233 17:42:51.266008
10234 17:42:51.847357 01f80000 ################################################################
10235 17:42:51.847524
10236 17:42:52.404560 02000000 ################################################################
10237 17:42:52.404755
10238 17:42:53.031788 02080000 ################################################################
10239 17:42:53.032311
10240 17:42:53.749903 02100000 ################################################################
10241 17:42:53.750429
10242 17:42:54.485057 02180000 ################################################################
10243 17:42:54.485588
10244 17:42:55.219691 02200000 ################################################################
10245 17:42:55.220216
10246 17:42:55.960467 02280000 ################################################################
10247 17:42:55.960994
10248 17:42:56.687627 02300000 ################################################################
10249 17:42:56.688172
10250 17:42:57.412076 02380000 ################################################################
10251 17:42:57.412665
10252 17:42:58.095477 02400000 ################################################################
10253 17:42:58.095978
10254 17:42:58.718403 02480000 ################################################################
10255 17:42:58.718946
10256 17:42:59.406766 02500000 ################################################################
10257 17:42:59.407279
10258 17:43:00.085381 02580000 ################################################################
10259 17:43:00.085550
10260 17:43:00.623950 02600000 ################################################################
10261 17:43:00.624121
10262 17:43:01.232879 02680000 ################################################################
10263 17:43:01.233397
10264 17:43:01.829806 02700000 ################################################################
10265 17:43:01.829934
10266 17:43:02.407670 02780000 ################################################################
10267 17:43:02.407813
10268 17:43:02.982810 02800000 ################################################################
10269 17:43:02.982969
10270 17:43:03.565835 02880000 ################################################################
10271 17:43:03.565971
10272 17:43:04.128598 02900000 ################################################################
10273 17:43:04.128786
10274 17:43:04.684625 02980000 ################################################################
10275 17:43:04.684763
10276 17:43:05.257681 02a00000 ################################################################
10277 17:43:05.257849
10278 17:43:05.823302 02a80000 ################################################################
10279 17:43:05.823436
10280 17:43:06.436355 02b00000 ################################################################
10281 17:43:06.436515
10282 17:43:07.009876 02b80000 ################################################################
10283 17:43:07.010006
10284 17:43:07.585347 02c00000 ################################################################
10285 17:43:07.585490
10286 17:43:08.148944 02c80000 ################################################################
10287 17:43:08.149085
10288 17:43:08.700724 02d00000 ################################################################
10289 17:43:08.700874
10290 17:43:09.250112 02d80000 ################################################################
10291 17:43:09.250259
10292 17:43:09.811955 02e00000 ################################################################
10293 17:43:09.812102
10294 17:43:10.377301 02e80000 ################################################################
10295 17:43:10.377466
10296 17:43:10.926666 02f00000 ################################################################
10297 17:43:10.926823
10298 17:43:11.461889 02f80000 ################################################################
10299 17:43:11.462043
10300 17:43:12.002702 03000000 ################################################################
10301 17:43:12.002885
10302 17:43:12.542217 03080000 ################################################################
10303 17:43:12.542392
10304 17:43:13.062872 03100000 ################################################################
10305 17:43:13.063034
10306 17:43:13.586675 03180000 ################################################################
10307 17:43:13.586890
10308 17:43:14.126319 03200000 ################################################################
10309 17:43:14.126468
10310 17:43:14.655811 03280000 ################################################################
10311 17:43:14.655991
10312 17:43:15.194572 03300000 ################################################################
10313 17:43:15.194776
10314 17:43:15.752575 03380000 ################################################################
10315 17:43:15.752727
10316 17:43:16.296357 03400000 ################################################################
10317 17:43:16.296503
10318 17:43:16.842869 03480000 ################################################################
10319 17:43:16.843016
10320 17:43:17.375813 03500000 ################################################################
10321 17:43:17.375961
10322 17:43:17.921983 03580000 ################################################################
10323 17:43:17.922156
10324 17:43:18.478042 03600000 ################################################################
10325 17:43:18.478207
10326 17:43:19.037511 03680000 ################################################################
10327 17:43:19.037662
10328 17:43:19.586949 03700000 ################################################################
10329 17:43:19.587100
10330 17:43:20.130225 03780000 ################################################################
10331 17:43:20.130403
10332 17:43:20.681648 03800000 ################################################################
10333 17:43:20.681794
10334 17:43:21.226579 03880000 ################################################################
10335 17:43:21.226764
10336 17:43:21.748170 03900000 ################################################################
10337 17:43:21.748317
10338 17:43:22.279082 03980000 ################################################################
10339 17:43:22.279249
10340 17:43:22.822463 03a00000 ################################################################
10341 17:43:22.822616
10342 17:43:23.378687 03a80000 ################################################################
10343 17:43:23.378866
10344 17:43:23.935758 03b00000 ################################################################
10345 17:43:23.935912
10346 17:43:24.490163 03b80000 ################################################################
10347 17:43:24.490334
10348 17:43:25.039064 03c00000 ################################################################
10349 17:43:25.039212
10350 17:43:25.629453 03c80000 ################################################################
10351 17:43:25.629600
10352 17:43:26.168817 03d00000 ################################################################
10353 17:43:26.168969
10354 17:43:26.767230 03d80000 ################################################################
10355 17:43:26.767738
10356 17:43:27.395959 03e00000 ################################################################
10357 17:43:27.396095
10358 17:43:27.956920 03e80000 ################################################################
10359 17:43:27.957065
10360 17:43:28.501577 03f00000 ################################################################
10361 17:43:28.501718
10362 17:43:29.043941 03f80000 ################################################################
10363 17:43:29.044093
10364 17:43:29.717574 04000000 ################################################################
10365 17:43:29.718097
10366 17:43:30.267483 04080000 ################################################################
10367 17:43:30.267630
10368 17:43:30.808213 04100000 ################################################################
10369 17:43:30.808361
10370 17:43:31.375072 04180000 ################################################################
10371 17:43:31.375224
10372 17:43:31.955306 04200000 ################################################################
10373 17:43:31.955483
10374 17:43:32.514044 04280000 ################################################################
10375 17:43:32.514274
10376 17:43:33.095288 04300000 ################################################################
10377 17:43:33.095461
10378 17:43:33.664980 04380000 ################################################################
10379 17:43:33.665147
10380 17:43:34.214303 04400000 ################################################################
10381 17:43:34.214438
10382 17:43:34.766198 04480000 ################################################################
10383 17:43:34.766333
10384 17:43:35.297708 04500000 ################################################################
10385 17:43:35.297866
10386 17:43:35.856357 04580000 ################################################################
10387 17:43:35.856510
10388 17:43:36.401425 04600000 ################################################################
10389 17:43:36.401578
10390 17:43:36.955708 04680000 ################################################################
10391 17:43:36.955846
10392 17:43:37.508548 04700000 ################################################################
10393 17:43:37.508685
10394 17:43:38.044567 04780000 ################################################################
10395 17:43:38.044721
10396 17:43:38.622947 04800000 ################################################################
10397 17:43:38.623116
10398 17:43:39.177487 04880000 ################################################################
10399 17:43:39.177620
10400 17:43:39.731668 04900000 ################################################################
10401 17:43:39.732167
10402 17:43:40.430791 04980000 ################################################################
10403 17:43:40.431304
10404 17:43:41.154171 04a00000 ################################################################
10405 17:43:41.154706
10406 17:43:41.888778 04a80000 ################################################################
10407 17:43:41.889356
10408 17:43:42.625291 04b00000 ################################################################
10409 17:43:42.625944
10410 17:43:43.336913 04b80000 ################################################################
10411 17:43:43.337439
10412 17:43:44.082628 04c00000 ################################################################
10413 17:43:44.083225
10414 17:43:44.803006 04c80000 ################################################################
10415 17:43:44.803514
10416 17:43:45.524390 04d00000 ################################################################
10417 17:43:45.524973
10418 17:43:46.135949 04d80000 ################################################################
10419 17:43:46.136095
10420 17:43:46.754801 04e00000 ################################################################
10421 17:43:46.755173
10422 17:43:47.440068 04e80000 ################################################################
10423 17:43:47.440212
10424 17:43:48.130525 04f00000 ################################################################
10425 17:43:48.131082
10426 17:43:48.758159 04f80000 ################################################################
10427 17:43:48.758339
10428 17:43:49.328819 05000000 ################################################################
10429 17:43:49.329037
10430 17:43:49.867123 05080000 ################################################################
10431 17:43:49.867266
10432 17:43:50.428338 05100000 ################################################################
10433 17:43:50.428476
10434 17:43:51.032765 05180000 ################################################################
10435 17:43:51.033313
10436 17:43:51.652053 05200000 ################################################################
10437 17:43:51.652193
10438 17:43:52.258074 05280000 ################################################################
10439 17:43:52.258230
10440 17:43:52.932752 05300000 ################################################################
10441 17:43:52.933256
10442 17:43:53.536075 05380000 ################################################################
10443 17:43:53.536647
10444 17:43:54.257171 05400000 ################################################################
10445 17:43:54.257673
10446 17:43:54.963111 05480000 ################################################################
10447 17:43:54.963655
10448 17:43:55.687397 05500000 ################################################################
10449 17:43:55.687922
10450 17:43:56.394040 05580000 ################################################################
10451 17:43:56.394546
10452 17:43:57.119538 05600000 ################################################################
10453 17:43:57.120060
10454 17:43:57.741252 05680000 ################################################################
10455 17:43:57.741419
10456 17:43:58.459470 05700000 ################################################################
10457 17:43:58.460014
10458 17:43:59.185219 05780000 ################################################################
10459 17:43:59.185813
10460 17:43:59.904700 05800000 ################################################################
10461 17:43:59.905217
10462 17:44:00.617988 05880000 ################################################################
10463 17:44:00.618533
10464 17:44:01.323727 05900000 ################################################################
10465 17:44:01.324275
10466 17:44:01.983904 05980000 ################################################################
10467 17:44:01.984286
10468 17:44:02.666972 05a00000 ################################################################
10469 17:44:02.667281
10470 17:44:03.262622 05a80000 ################################################################
10471 17:44:03.262774
10472 17:44:03.887676 05b00000 ################################################################
10473 17:44:03.888038
10474 17:44:04.514227 05b80000 ################################################################
10475 17:44:04.514524
10476 17:44:05.236171 05c00000 ################################################################
10477 17:44:05.236674
10478 17:44:05.858680 05c80000 ################################################################
10479 17:44:05.859252
10480 17:44:06.443971 05d00000 ################################################################
10481 17:44:06.444120
10482 17:44:07.071087 05d80000 ################################################################
10483 17:44:07.071232
10484 17:44:07.741464 05e00000 ################################################################
10485 17:44:07.742179
10486 17:44:08.468445 05e80000 ################################################################
10487 17:44:08.468993
10488 17:44:09.173023 05f00000 ################################################################
10489 17:44:09.173581
10490 17:44:09.879487 05f80000 ################################################################
10491 17:44:09.880073
10492 17:44:10.603600 06000000 ################################################################
10493 17:44:10.604160
10494 17:44:11.317232 06080000 ################################################################
10495 17:44:11.317768
10496 17:44:12.026801 06100000 ################################################################
10497 17:44:12.027331
10498 17:44:12.769842 06180000 ################################################################
10499 17:44:12.770369
10500 17:44:13.477848 06200000 ################################################################
10501 17:44:13.478382
10502 17:44:14.203518 06280000 ################################################################
10503 17:44:14.204052
10504 17:44:14.930069 06300000 ################################################################
10505 17:44:14.930646
10506 17:44:15.637031 06380000 ################################################################
10507 17:44:15.637552
10508 17:44:16.334852 06400000 ################################################################
10509 17:44:16.335388
10510 17:44:17.052133 06480000 ################################################################
10511 17:44:17.052707
10512 17:44:17.762590 06500000 ################################################################
10513 17:44:17.763157
10514 17:44:18.433782 06580000 ################################################################
10515 17:44:18.434354
10516 17:44:19.171607 06600000 ################################################################
10517 17:44:19.172111
10518 17:44:19.889209 06680000 ################################################################
10519 17:44:19.889808
10520 17:44:20.585692 06700000 ################################################################
10521 17:44:20.586237
10522 17:44:21.309015 06780000 ################################################################
10523 17:44:21.309559
10524 17:44:21.809347 06800000 ############################################## done.
10525 17:44:21.809871
10526 17:44:21.812333 The bootfile was 109425038 bytes long.
10527 17:44:21.812761
10528 17:44:21.816048 Sending tftp read request... done.
10529 17:44:21.816475
10530 17:44:21.819499 Waiting for the transfer...
10531 17:44:21.819947
10532 17:44:21.820279 00000000 # done.
10533 17:44:21.820676
10534 17:44:21.826540 Command line loaded dynamically from TFTP file: 11518283/tftp-deploy-ox_jgt1_/kernel/cmdline
10535 17:44:21.827014
10536 17:44:21.839973 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10537 17:44:21.840487
10538 17:44:21.843105 Loading FIT.
10539 17:44:21.843526
10540 17:44:21.846657 Image ramdisk-1 has 98336475 bytes.
10541 17:44:21.847244
10542 17:44:21.847595 Image fdt-1 has 47278 bytes.
10543 17:44:21.849903
10544 17:44:21.850321 Image kernel-1 has 11039249 bytes.
10545 17:44:21.850894
10546 17:44:21.859580 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10547 17:44:21.860010
10548 17:44:21.876132 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10549 17:44:21.876669
10550 17:44:21.882900 Choosing best match conf-1 for compat google,spherion-rev2.
10551 17:44:21.886996
10552 17:44:21.891710 Connected to device vid:did:rid of 1ae0:0028:00
10553 17:44:21.900466
10554 17:44:21.903161 tpm_get_response: command 0x17b, return code 0x0
10555 17:44:21.903602
10556 17:44:21.906766 ec_init: CrosEC protocol v3 supported (256, 248)
10557 17:44:21.910798
10558 17:44:21.914096 tpm_cleanup: add release locality here.
10559 17:44:21.914521
10560 17:44:21.914945 Shutting down all USB controllers.
10561 17:44:21.915277
10562 17:44:21.917271 Removing current net device
10563 17:44:21.917694
10564 17:44:21.923912 Exiting depthcharge with code 4 at timestamp: 169008802
10565 17:44:21.924424
10566 17:44:21.927210 LZMA decompressing kernel-1 to 0x821a6718
10567 17:44:21.927634
10568 17:44:21.930648 LZMA decompressing kernel-1 to 0x40000000
10569 17:44:23.320747
10570 17:44:23.320919 jumping to kernel
10571 17:44:23.321499 end: 2.2.4 bootloader-commands (duration 00:02:21) [common]
10572 17:44:23.321638 start: 2.2.5 auto-login-action (timeout 00:02:04) [common]
10573 17:44:23.321750 Setting prompt string to ['Linux version [0-9]']
10574 17:44:23.321846 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10575 17:44:23.321940 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10576 17:44:23.402549
10577 17:44:23.405926 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10578 17:44:23.409537 start: 2.2.5.1 login-action (timeout 00:02:04) [common]
10579 17:44:23.409998 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10580 17:44:23.410358 Setting prompt string to []
10581 17:44:23.410798 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10582 17:44:23.411163 Using line separator: #'\n'#
10583 17:44:23.411465 No login prompt set.
10584 17:44:23.411773 Parsing kernel messages
10585 17:44:23.412057 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10586 17:44:23.412554 [login-action] Waiting for messages, (timeout 00:02:04)
10587 17:44:23.429631 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j44859-arm64-gcc-10-defconfig-arm64-chromebook-gptb4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023
10588 17:44:23.432518 [ 0.000000] random: crng init done
10589 17:44:23.439481 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10590 17:44:23.439912 [ 0.000000] efi: UEFI not found.
10591 17:44:23.449165 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10592 17:44:23.455952 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10593 17:44:23.466349 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10594 17:44:23.476138 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10595 17:44:23.482652 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10596 17:44:23.486027 [ 0.000000] printk: bootconsole [mtk8250] enabled
10597 17:44:23.494355 [ 0.000000] NUMA: No NUMA configuration found
10598 17:44:23.501486 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10599 17:44:23.508487 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10600 17:44:23.508911 [ 0.000000] Zone ranges:
10601 17:44:23.514595 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10602 17:44:23.517756 [ 0.000000] DMA32 empty
10603 17:44:23.524339 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10604 17:44:23.527727 [ 0.000000] Movable zone start for each node
10605 17:44:23.531140 [ 0.000000] Early memory node ranges
10606 17:44:23.537671 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10607 17:44:23.544315 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10608 17:44:23.551334 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10609 17:44:23.557740 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10610 17:44:23.564584 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10611 17:44:23.571337 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10612 17:44:23.627451 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10613 17:44:23.633584 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10614 17:44:23.640594 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10615 17:44:23.643866 [ 0.000000] psci: probing for conduit method from DT.
10616 17:44:23.650287 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10617 17:44:23.653855 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10618 17:44:23.660416 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10619 17:44:23.663584 [ 0.000000] psci: SMC Calling Convention v1.2
10620 17:44:23.670715 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10621 17:44:23.673914 [ 0.000000] Detected VIPT I-cache on CPU0
10622 17:44:23.680560 [ 0.000000] CPU features: detected: GIC system register CPU interface
10623 17:44:23.687348 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10624 17:44:23.694266 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10625 17:44:23.700335 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10626 17:44:23.707317 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10627 17:44:23.714121 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10628 17:44:23.720562 [ 0.000000] alternatives: applying boot alternatives
10629 17:44:23.723784 [ 0.000000] Fallback order for Node 0: 0
10630 17:44:23.730538 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10631 17:44:23.734204 [ 0.000000] Policy zone: Normal
10632 17:44:23.750810 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10633 17:44:23.760364 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10634 17:44:23.771536 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10635 17:44:23.781286 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10636 17:44:23.788073 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10637 17:44:23.791410 <6>[ 0.000000] software IO TLB: area num 8.
10638 17:44:23.848102 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10639 17:44:23.996686 <6>[ 0.000000] Memory: 7873456K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 479312K reserved, 32768K cma-reserved)
10640 17:44:24.003472 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10641 17:44:24.010273 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10642 17:44:24.013783 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10643 17:44:24.020196 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10644 17:44:24.026870 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10645 17:44:24.030403 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10646 17:44:24.040265 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10647 17:44:24.047213 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10648 17:44:24.050229 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10649 17:44:24.057967 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10650 17:44:24.061114 <6>[ 0.000000] GICv3: 608 SPIs implemented
10651 17:44:24.068298 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10652 17:44:24.071168 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10653 17:44:24.074567 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10654 17:44:24.084334 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10655 17:44:24.094707 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10656 17:44:24.107890 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10657 17:44:24.114374 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10658 17:44:24.123835 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10659 17:44:24.137044 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10660 17:44:24.143673 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10661 17:44:24.150404 <6>[ 0.009185] Console: colour dummy device 80x25
10662 17:44:24.160813 <6>[ 0.013940] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10663 17:44:24.164117 <6>[ 0.024446] pid_max: default: 32768 minimum: 301
10664 17:44:24.170890 <6>[ 0.029319] LSM: Security Framework initializing
10665 17:44:24.177161 <6>[ 0.034287] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10666 17:44:24.186944 <6>[ 0.042101] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10667 17:44:24.193447 <6>[ 0.051568] cblist_init_generic: Setting adjustable number of callback queues.
10668 17:44:24.200011 <6>[ 0.059012] cblist_init_generic: Setting shift to 3 and lim to 1.
10669 17:44:24.210125 <6>[ 0.065388] cblist_init_generic: Setting adjustable number of callback queues.
10670 17:44:24.216645 <6>[ 0.072814] cblist_init_generic: Setting shift to 3 and lim to 1.
10671 17:44:24.219863 <6>[ 0.079251] rcu: Hierarchical SRCU implementation.
10672 17:44:24.226423 <6>[ 0.084298] rcu: Max phase no-delay instances is 1000.
10673 17:44:24.233245 <6>[ 0.091322] EFI services will not be available.
10674 17:44:24.236546 <6>[ 0.096280] smp: Bringing up secondary CPUs ...
10675 17:44:24.245623 <6>[ 0.101330] Detected VIPT I-cache on CPU1
10676 17:44:24.251610 <6>[ 0.101398] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10677 17:44:24.258133 <6>[ 0.101428] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10678 17:44:24.261764 <6>[ 0.101763] Detected VIPT I-cache on CPU2
10679 17:44:24.268631 <6>[ 0.101816] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10680 17:44:24.274532 <6>[ 0.101831] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10681 17:44:24.281519 <6>[ 0.102090] Detected VIPT I-cache on CPU3
10682 17:44:24.288366 <6>[ 0.102136] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10683 17:44:24.294577 <6>[ 0.102149] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10684 17:44:24.298211 <6>[ 0.102453] CPU features: detected: Spectre-v4
10685 17:44:24.305127 <6>[ 0.102459] CPU features: detected: Spectre-BHB
10686 17:44:24.308299 <6>[ 0.102464] Detected PIPT I-cache on CPU4
10687 17:44:24.314670 <6>[ 0.102523] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10688 17:44:24.321816 <6>[ 0.102539] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10689 17:44:24.325218 <6>[ 0.102835] Detected PIPT I-cache on CPU5
10690 17:44:24.335277 <6>[ 0.102898] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10691 17:44:24.341773 <6>[ 0.102914] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10692 17:44:24.345098 <6>[ 0.103194] Detected PIPT I-cache on CPU6
10693 17:44:24.351982 <6>[ 0.103259] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10694 17:44:24.358407 <6>[ 0.103275] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10695 17:44:24.361738 <6>[ 0.103569] Detected PIPT I-cache on CPU7
10696 17:44:24.371397 <6>[ 0.103634] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10697 17:44:24.378289 <6>[ 0.103650] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10698 17:44:24.381372 <6>[ 0.103698] smp: Brought up 1 node, 8 CPUs
10699 17:44:24.385326 <6>[ 0.244894] SMP: Total of 8 processors activated.
10700 17:44:24.391630 <6>[ 0.249815] CPU features: detected: 32-bit EL0 Support
10701 17:44:24.401417 <6>[ 0.255178] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10702 17:44:24.408184 <6>[ 0.264033] CPU features: detected: Common not Private translations
10703 17:44:24.411062 <6>[ 0.270509] CPU features: detected: CRC32 instructions
10704 17:44:24.417674 <6>[ 0.275893] CPU features: detected: RCpc load-acquire (LDAPR)
10705 17:44:24.424662 <6>[ 0.281890] CPU features: detected: LSE atomic instructions
10706 17:44:24.431294 <6>[ 0.287671] CPU features: detected: Privileged Access Never
10707 17:44:24.434628 <6>[ 0.293487] CPU features: detected: RAS Extension Support
10708 17:44:24.441255 <6>[ 0.299095] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10709 17:44:24.447816 <6>[ 0.306317] CPU: All CPU(s) started at EL2
10710 17:44:24.451322 <6>[ 0.310661] alternatives: applying system-wide alternatives
10711 17:44:24.462387 <6>[ 0.321333] devtmpfs: initialized
10712 17:44:24.474859 <6>[ 0.330285] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10713 17:44:24.484676 <6>[ 0.340245] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10714 17:44:24.491178 <6>[ 0.348261] pinctrl core: initialized pinctrl subsystem
10715 17:44:24.494437 <6>[ 0.354935] DMI not present or invalid.
10716 17:44:24.501119 <6>[ 0.359349] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10717 17:44:24.511498 <6>[ 0.366215] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10718 17:44:24.517911 <6>[ 0.373796] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10719 17:44:24.527979 <6>[ 0.382010] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10720 17:44:24.531662 <6>[ 0.390253] audit: initializing netlink subsys (disabled)
10721 17:44:24.541619 <5>[ 0.395944] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10722 17:44:24.548029 <6>[ 0.396646] thermal_sys: Registered thermal governor 'step_wise'
10723 17:44:24.554312 <6>[ 0.403913] thermal_sys: Registered thermal governor 'power_allocator'
10724 17:44:24.557982 <6>[ 0.410170] cpuidle: using governor menu
10725 17:44:24.561181 <6>[ 0.421133] NET: Registered PF_QIPCRTR protocol family
10726 17:44:24.571059 <6>[ 0.426620] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10727 17:44:24.574603 <6>[ 0.433721] ASID allocator initialised with 32768 entries
10728 17:44:24.581314 <6>[ 0.440292] Serial: AMBA PL011 UART driver
10729 17:44:24.590035 <4>[ 0.449086] Trying to register duplicate clock ID: 134
10730 17:44:24.644173 <6>[ 0.506363] KASLR enabled
10731 17:44:24.658805 <6>[ 0.514113] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10732 17:44:24.664976 <6>[ 0.521127] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10733 17:44:24.672245 <6>[ 0.527616] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10734 17:44:24.678838 <6>[ 0.534619] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10735 17:44:24.684901 <6>[ 0.541105] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10736 17:44:24.691861 <6>[ 0.548112] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10737 17:44:24.698638 <6>[ 0.554598] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10738 17:44:24.705018 <6>[ 0.561603] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10739 17:44:24.708619 <6>[ 0.569099] ACPI: Interpreter disabled.
10740 17:44:24.716780 <6>[ 0.575511] iommu: Default domain type: Translated
10741 17:44:24.722947 <6>[ 0.580623] iommu: DMA domain TLB invalidation policy: strict mode
10742 17:44:24.726568 <5>[ 0.587278] SCSI subsystem initialized
10743 17:44:24.733494 <6>[ 0.591443] usbcore: registered new interface driver usbfs
10744 17:44:24.739615 <6>[ 0.597176] usbcore: registered new interface driver hub
10745 17:44:24.743040 <6>[ 0.602728] usbcore: registered new device driver usb
10746 17:44:24.749839 <6>[ 0.608822] pps_core: LinuxPPS API ver. 1 registered
10747 17:44:24.760028 <6>[ 0.614015] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10748 17:44:24.763329 <6>[ 0.623363] PTP clock support registered
10749 17:44:24.766784 <6>[ 0.627606] EDAC MC: Ver: 3.0.0
10750 17:44:24.773922 <6>[ 0.632750] FPGA manager framework
10751 17:44:24.777136 <6>[ 0.636429] Advanced Linux Sound Architecture Driver Initialized.
10752 17:44:24.780896 <6>[ 0.643204] vgaarb: loaded
10753 17:44:24.787439 <6>[ 0.646377] clocksource: Switched to clocksource arch_sys_counter
10754 17:44:24.794158 <5>[ 0.652812] VFS: Disk quotas dquot_6.6.0
10755 17:44:24.800848 <6>[ 0.656998] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10756 17:44:24.804273 <6>[ 0.664187] pnp: PnP ACPI: disabled
10757 17:44:24.811763 <6>[ 0.670844] NET: Registered PF_INET protocol family
10758 17:44:24.821594 <6>[ 0.676428] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10759 17:44:24.833424 <6>[ 0.688747] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10760 17:44:24.843110 <6>[ 0.697560] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10761 17:44:24.850212 <6>[ 0.705529] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10762 17:44:24.856316 <6>[ 0.714227] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10763 17:44:24.868736 <6>[ 0.723972] TCP: Hash tables configured (established 65536 bind 65536)
10764 17:44:24.874910 <6>[ 0.730828] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10765 17:44:24.881384 <6>[ 0.738025] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10766 17:44:24.888586 <6>[ 0.745730] NET: Registered PF_UNIX/PF_LOCAL protocol family
10767 17:44:24.895024 <6>[ 0.751897] RPC: Registered named UNIX socket transport module.
10768 17:44:24.898057 <6>[ 0.758052] RPC: Registered udp transport module.
10769 17:44:24.904494 <6>[ 0.762984] RPC: Registered tcp transport module.
10770 17:44:24.911507 <6>[ 0.767914] RPC: Registered tcp NFSv4.1 backchannel transport module.
10771 17:44:24.915102 <6>[ 0.774583] PCI: CLS 0 bytes, default 64
10772 17:44:24.918527 <6>[ 0.778990] Unpacking initramfs...
10773 17:44:24.942890 <6>[ 0.798521] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10774 17:44:24.952621 <6>[ 0.807191] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10775 17:44:24.956043 <6>[ 0.816063] kvm [1]: IPA Size Limit: 40 bits
10776 17:44:24.962824 <6>[ 0.820595] kvm [1]: GICv3: no GICV resource entry
10777 17:44:24.966308 <6>[ 0.825617] kvm [1]: disabling GICv2 emulation
10778 17:44:24.972620 <6>[ 0.830305] kvm [1]: GIC system register CPU interface enabled
10779 17:44:24.976157 <6>[ 0.836481] kvm [1]: vgic interrupt IRQ18
10780 17:44:24.983239 <6>[ 0.840848] kvm [1]: VHE mode initialized successfully
10781 17:44:24.989280 <5>[ 0.847347] Initialise system trusted keyrings
10782 17:44:24.996292 <6>[ 0.852172] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10783 17:44:25.003004 <6>[ 0.862184] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10784 17:44:25.009872 <5>[ 0.868577] NFS: Registering the id_resolver key type
10785 17:44:25.013142 <5>[ 0.873886] Key type id_resolver registered
10786 17:44:25.019688 <5>[ 0.878303] Key type id_legacy registered
10787 17:44:25.026584 <6>[ 0.882588] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10788 17:44:25.033067 <6>[ 0.889510] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10789 17:44:25.039431 <6>[ 0.897227] 9p: Installing v9fs 9p2000 file system support
10790 17:44:25.075517 <5>[ 0.934984] Key type asymmetric registered
10791 17:44:25.078871 <5>[ 0.939316] Asymmetric key parser 'x509' registered
10792 17:44:25.089219 <6>[ 0.944464] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10793 17:44:25.092217 <6>[ 0.952078] io scheduler mq-deadline registered
10794 17:44:25.095602 <6>[ 0.956861] io scheduler kyber registered
10795 17:44:25.114024 <6>[ 0.973652] EINJ: ACPI disabled.
10796 17:44:25.146093 <4>[ 0.999044] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10797 17:44:25.156068 <4>[ 1.009668] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10798 17:44:25.170974 <6>[ 1.030498] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10799 17:44:25.178860 <6>[ 1.038397] printk: console [ttyS0] disabled
10800 17:44:25.206949 <6>[ 1.063037] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10801 17:44:25.213864 <6>[ 1.072511] printk: console [ttyS0] enabled
10802 17:44:25.217270 <6>[ 1.072511] printk: console [ttyS0] enabled
10803 17:44:25.223587 <6>[ 1.081409] printk: bootconsole [mtk8250] disabled
10804 17:44:25.227513 <6>[ 1.081409] printk: bootconsole [mtk8250] disabled
10805 17:44:25.234079 <6>[ 1.092635] SuperH (H)SCI(F) driver initialized
10806 17:44:25.237783 <6>[ 1.097914] msm_serial: driver initialized
10807 17:44:25.251245 <6>[ 1.106827] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10808 17:44:25.260976 <6>[ 1.115373] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10809 17:44:25.267725 <6>[ 1.123914] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10810 17:44:25.278079 <6>[ 1.132542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10811 17:44:25.287486 <6>[ 1.141249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10812 17:44:25.294692 <6>[ 1.149971] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10813 17:44:25.303986 <6>[ 1.158511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10814 17:44:25.310993 <6>[ 1.167320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10815 17:44:25.321150 <6>[ 1.175865] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10816 17:44:25.332358 <6>[ 1.191255] loop: module loaded
10817 17:44:25.338859 <6>[ 1.197239] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10818 17:44:25.361757 <4>[ 1.220438] mtk-pmic-keys: Failed to locate of_node [id: -1]
10819 17:44:25.368456 <6>[ 1.227250] megasas: 07.719.03.00-rc1
10820 17:44:25.377768 <6>[ 1.236715] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10821 17:44:25.386992 <6>[ 1.245750] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10822 17:44:25.403773 <6>[ 1.262526] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10823 17:44:25.460549 <6>[ 1.312458] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10824 17:44:28.938796 <6>[ 4.798239] Freeing initrd memory: 96028K
10825 17:44:28.949114 <6>[ 4.808420] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10826 17:44:28.960039 <6>[ 4.819313] tun: Universal TUN/TAP device driver, 1.6
10827 17:44:28.963241 <6>[ 4.825355] thunder_xcv, ver 1.0
10828 17:44:28.966644 <6>[ 4.828859] thunder_bgx, ver 1.0
10829 17:44:28.969983 <6>[ 4.832355] nicpf, ver 1.0
10830 17:44:28.979972 <6>[ 4.836352] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10831 17:44:28.983414 <6>[ 4.843828] hns3: Copyright (c) 2017 Huawei Corporation.
10832 17:44:28.990493 <6>[ 4.849413] hclge is initializing
10833 17:44:28.993682 <6>[ 4.852995] e1000: Intel(R) PRO/1000 Network Driver
10834 17:44:29.000357 <6>[ 4.858124] e1000: Copyright (c) 1999-2006 Intel Corporation.
10835 17:44:29.004024 <6>[ 4.864135] e1000e: Intel(R) PRO/1000 Network Driver
10836 17:44:29.010224 <6>[ 4.869350] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10837 17:44:29.016807 <6>[ 4.875538] igb: Intel(R) Gigabit Ethernet Network Driver
10838 17:44:29.023787 <6>[ 4.881188] igb: Copyright (c) 2007-2014 Intel Corporation.
10839 17:44:29.029722 <6>[ 4.887025] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10840 17:44:29.036479 <6>[ 4.893544] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10841 17:44:29.039770 <6>[ 4.900001] sky2: driver version 1.30
10842 17:44:29.046607 <6>[ 4.904979] VFIO - User Level meta-driver version: 0.3
10843 17:44:29.053581 <6>[ 4.913190] usbcore: registered new interface driver usb-storage
10844 17:44:29.060888 <6>[ 4.919636] usbcore: registered new device driver onboard-usb-hub
10845 17:44:29.069157 <6>[ 4.928742] mt6397-rtc mt6359-rtc: registered as rtc0
10846 17:44:29.079327 <6>[ 4.934227] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-13T17:44:28 UTC (1694627068)
10847 17:44:29.082713 <6>[ 4.943807] i2c_dev: i2c /dev entries driver
10848 17:44:29.099202 <6>[ 4.955442] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10849 17:44:29.119119 <6>[ 4.978426] cpu cpu0: EM: created perf domain
10850 17:44:29.122354 <6>[ 4.983357] cpu cpu4: EM: created perf domain
10851 17:44:29.129196 <6>[ 4.988904] sdhci: Secure Digital Host Controller Interface driver
10852 17:44:29.135900 <6>[ 4.995336] sdhci: Copyright(c) Pierre Ossman
10853 17:44:29.142621 <6>[ 5.000284] Synopsys Designware Multimedia Card Interface Driver
10854 17:44:29.149159 <6>[ 5.006909] sdhci-pltfm: SDHCI platform and OF driver helper
10855 17:44:29.153225 <6>[ 5.006955] mmc0: CQHCI version 5.10
10856 17:44:29.159535 <6>[ 5.017144] ledtrig-cpu: registered to indicate activity on CPUs
10857 17:44:29.166096 <6>[ 5.024160] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10858 17:44:29.173033 <6>[ 5.031214] usbcore: registered new interface driver usbhid
10859 17:44:29.175995 <6>[ 5.037036] usbhid: USB HID core driver
10860 17:44:29.182905 <6>[ 5.041245] spi_master spi0: will run message pump with realtime priority
10861 17:44:29.226523 <6>[ 5.079317] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10862 17:44:29.246165 <6>[ 5.095239] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10863 17:44:29.253273 <6>[ 5.109827] cros-ec-spi spi0.0: Chrome EC device registered
10864 17:44:29.256310 <6>[ 5.115920] mmc0: Command Queue Engine enabled
10865 17:44:29.263142 <6>[ 5.120671] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10866 17:44:29.269886 <6>[ 5.128335] mmcblk0: mmc0:0001 DA4128 116 GiB
10867 17:44:29.281179 <6>[ 5.140304] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10868 17:44:29.290903 <6>[ 5.144383] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10869 17:44:29.297622 <6>[ 5.147757] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10870 17:44:29.300556 <6>[ 5.156803] NET: Registered PF_PACKET protocol family
10871 17:44:29.307673 <6>[ 5.161502] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10872 17:44:29.310986 <6>[ 5.166117] 9pnet: Installing 9P2000 support
10873 17:44:29.317455 <6>[ 5.171948] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10874 17:44:29.320604 <5>[ 5.175842] Key type dns_resolver registered
10875 17:44:29.327626 <6>[ 5.187279] registered taskstats version 1
10876 17:44:29.331218 <5>[ 5.191662] Loading compiled-in X.509 certificates
10877 17:44:29.360338 <4>[ 5.212887] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10878 17:44:29.370365 <4>[ 5.223780] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10879 17:44:29.377355 <3>[ 5.234323] debugfs: File 'uA_load' in directory '/' already present!
10880 17:44:29.383442 <3>[ 5.241044] debugfs: File 'min_uV' in directory '/' already present!
10881 17:44:29.389938 <3>[ 5.247713] debugfs: File 'max_uV' in directory '/' already present!
10882 17:44:29.396274 <3>[ 5.254344] debugfs: File 'constraint_flags' in directory '/' already present!
10883 17:44:29.407912 <3>[ 5.264122] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10884 17:44:29.416890 <6>[ 5.276271] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10885 17:44:29.423372 <6>[ 5.283024] xhci-mtk 11200000.usb: xHCI Host Controller
10886 17:44:29.430077 <6>[ 5.288544] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10887 17:44:29.440309 <6>[ 5.296397] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10888 17:44:29.446621 <6>[ 5.305825] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10889 17:44:29.453618 <6>[ 5.311900] xhci-mtk 11200000.usb: xHCI Host Controller
10890 17:44:29.460089 <6>[ 5.317377] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10891 17:44:29.466768 <6>[ 5.325026] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10892 17:44:29.473589 <6>[ 5.332899] hub 1-0:1.0: USB hub found
10893 17:44:29.476870 <6>[ 5.336923] hub 1-0:1.0: 1 port detected
10894 17:44:29.483617 <6>[ 5.341204] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10895 17:44:29.491039 <6>[ 5.349948] hub 2-0:1.0: USB hub found
10896 17:44:29.493689 <6>[ 5.353978] hub 2-0:1.0: 1 port detected
10897 17:44:29.502327 <6>[ 5.361629] mtk-msdc 11f70000.mmc: Got CD GPIO
10898 17:44:29.511931 <6>[ 5.367994] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10899 17:44:29.518838 <6>[ 5.376021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10900 17:44:29.528430 <4>[ 5.383932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10901 17:44:29.538259 <6>[ 5.393463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10902 17:44:29.544930 <6>[ 5.401540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10903 17:44:29.551882 <6>[ 5.409658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10904 17:44:29.561587 <6>[ 5.417643] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10905 17:44:29.568226 <6>[ 5.425465] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10906 17:44:29.578613 <6>[ 5.433295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10907 17:44:29.588185 <6>[ 5.443849] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10908 17:44:29.595115 <6>[ 5.452246] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10909 17:44:29.605330 <6>[ 5.460588] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10910 17:44:29.611751 <6>[ 5.468938] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10911 17:44:29.621916 <6>[ 5.477276] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10912 17:44:29.628025 <6>[ 5.485627] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10913 17:44:29.638127 <6>[ 5.493966] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10914 17:44:29.644898 <6>[ 5.502316] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10915 17:44:29.654991 <6>[ 5.510655] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10916 17:44:29.661846 <6>[ 5.519002] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10917 17:44:29.671403 <6>[ 5.527342] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10918 17:44:29.677927 <6>[ 5.535679] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10919 17:44:29.688151 <6>[ 5.544017] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10920 17:44:29.695273 <6>[ 5.552354] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10921 17:44:29.704505 <6>[ 5.560692] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10922 17:44:29.711313 <6>[ 5.569480] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10923 17:44:29.717967 <6>[ 5.576667] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10924 17:44:29.724887 <6>[ 5.583428] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10925 17:44:29.731348 <6>[ 5.590186] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10926 17:44:29.737727 <6>[ 5.597120] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10927 17:44:29.747620 <6>[ 5.603975] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10928 17:44:29.757641 <6>[ 5.613105] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10929 17:44:29.767718 <6>[ 5.622225] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10930 17:44:29.777540 <6>[ 5.631540] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10931 17:44:29.784400 <6>[ 5.641013] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10932 17:44:29.794197 <6>[ 5.650484] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10933 17:44:29.804624 <6>[ 5.659604] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10934 17:44:29.813590 <6>[ 5.669074] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10935 17:44:29.823782 <6>[ 5.678194] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10936 17:44:29.833954 <6>[ 5.687489] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10937 17:44:29.844234 <6>[ 5.697650] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10938 17:44:29.854070 <6>[ 5.709202] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10939 17:44:29.882550 <6>[ 5.738721] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10940 17:44:29.910845 <6>[ 5.770045] hub 2-1:1.0: USB hub found
10941 17:44:29.914066 <6>[ 5.774534] hub 2-1:1.0: 3 ports detected
10942 17:44:30.034640 <6>[ 5.890641] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10943 17:44:30.189874 <6>[ 6.048644] hub 1-1:1.0: USB hub found
10944 17:44:30.192542 <6>[ 6.053159] hub 1-1:1.0: 4 ports detected
10945 17:44:30.266914 <6>[ 6.122962] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10946 17:44:30.514346 <6>[ 6.370694] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10947 17:44:30.646823 <6>[ 6.506661] hub 1-1.4:1.0: USB hub found
10948 17:44:30.650234 <6>[ 6.511329] hub 1-1.4:1.0: 2 ports detected
10949 17:44:30.946498 <6>[ 6.802665] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10950 17:44:31.137991 <6>[ 6.994669] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10951 17:44:42.135046 <6>[ 17.999694] ALSA device list:
10952 17:44:42.141250 <6>[ 18.002987] No soundcards found.
10953 17:44:42.149866 <6>[ 18.010976] Freeing unused kernel memory: 8384K
10954 17:44:42.152979 <6>[ 18.015985] Run /init as init process
10955 17:44:42.200806 <6>[ 18.062422] NET: Registered PF_INET6 protocol family
10956 17:44:42.207517 <6>[ 18.068520] Segment Routing with IPv6
10957 17:44:42.211168 <6>[ 18.072463] In-situ OAM (IOAM) with IPv6
10958 17:44:42.244728 <30>[ 18.086327] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10959 17:44:42.248614 <30>[ 18.110175] systemd[1]: Detected architecture arm64.
10960 17:44:42.248722
10961 17:44:42.254939 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10962 17:44:42.255050
10963 17:44:42.269027 <30>[ 18.130716] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10964 17:44:42.394573 <30>[ 18.252948] systemd[1]: Queued start job for default target Graphical Interface.
10965 17:44:42.422242 <30>[ 18.283772] systemd[1]: Created slice system-getty.slice.
10966 17:44:42.428673 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10967 17:44:42.445625 <30>[ 18.306989] systemd[1]: Created slice system-modprobe.slice.
10968 17:44:42.451853 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10969 17:44:42.473892 <30>[ 18.335495] systemd[1]: Created slice system-serial\x2dgetty.slice.
10970 17:44:42.484473 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10971 17:44:42.502210 <30>[ 18.363653] systemd[1]: Created slice User and Session Slice.
10972 17:44:42.509290 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10973 17:44:42.529342 <30>[ 18.387306] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10974 17:44:42.539231 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10975 17:44:42.557401 <30>[ 18.415425] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10976 17:44:42.564027 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10977 17:44:42.588102 <30>[ 18.442761] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10978 17:44:42.594504 <30>[ 18.454904] systemd[1]: Reached target Local Encrypted Volumes.
10979 17:44:42.601213 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10980 17:44:42.617645 <30>[ 18.479176] systemd[1]: Reached target Paths.
10981 17:44:42.620934 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10982 17:44:42.637635 <30>[ 18.498653] systemd[1]: Reached target Remote File Systems.
10983 17:44:42.643560 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10984 17:44:42.657053 <30>[ 18.518631] systemd[1]: Reached target Slices.
10985 17:44:42.660440 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10986 17:44:42.677058 <30>[ 18.538661] systemd[1]: Reached target Swap.
10987 17:44:42.680352 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10988 17:44:42.700942 <30>[ 18.559143] systemd[1]: Listening on initctl Compatibility Named Pipe.
10989 17:44:42.707280 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10990 17:44:42.722939 <30>[ 18.584110] systemd[1]: Listening on Journal Audit Socket.
10991 17:44:42.729165 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10992 17:44:42.746743 <30>[ 18.607829] systemd[1]: Listening on Journal Socket (/dev/log).
10993 17:44:42.753000 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10994 17:44:42.770278 <30>[ 18.631857] systemd[1]: Listening on Journal Socket.
10995 17:44:42.777273 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10996 17:44:42.789450 <30>[ 18.651216] systemd[1]: Listening on udev Control Socket.
10997 17:44:42.796315 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10998 17:44:42.814410 <30>[ 18.675722] systemd[1]: Listening on udev Kernel Socket.
10999 17:44:42.820826 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11000 17:44:42.861393 <30>[ 18.722821] systemd[1]: Mounting Huge Pages File System...
11001 17:44:42.868349 Mounting [0;1;39mHuge Pages File System[0m...
11002 17:44:42.885134 <30>[ 18.746060] systemd[1]: Mounting POSIX Message Queue File System...
11003 17:44:42.891603 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11004 17:44:42.912455 <30>[ 18.773896] systemd[1]: Mounting Kernel Debug File System...
11005 17:44:42.919270 Mounting [0;1;39mKernel Debug File System[0m...
11006 17:44:42.936867 <30>[ 18.794821] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11007 17:44:42.984642 <30>[ 18.842929] systemd[1]: Starting Create list of static device nodes for the current kernel...
11008 17:44:42.991536 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11009 17:44:43.013227 <30>[ 18.874756] systemd[1]: Starting Load Kernel Module configfs...
11010 17:44:43.019590 Starting [0;1;39mLoad Kernel Module configfs[0m...
11011 17:44:43.037130 <30>[ 18.898683] systemd[1]: Starting Load Kernel Module drm...
11012 17:44:43.043714 Starting [0;1;39mLoad Kernel Module drm[0m...
11013 17:44:43.060246 <30>[ 18.918731] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11014 17:44:43.105820 <30>[ 18.967251] systemd[1]: Starting Journal Service...
11015 17:44:43.109093 Starting [0;1;39mJournal Service[0m...
11016 17:44:43.128280 <30>[ 18.989629] systemd[1]: Starting Load Kernel Modules...
11017 17:44:43.134975 Starting [0;1;39mLoad Kernel Modules[0m...
11018 17:44:43.156318 <30>[ 19.014071] systemd[1]: Starting Remount Root and Kernel File Systems...
11019 17:44:43.162666 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11020 17:44:43.180354 <30>[ 19.041703] systemd[1]: Starting Coldplug All udev Devices...
11021 17:44:43.187073 Starting [0;1;39mColdplug All udev Devices[0m...
11022 17:44:43.203865 <30>[ 19.065414] systemd[1]: Started Journal Service.
11023 17:44:43.210522 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11024 17:44:43.229251 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11025 17:44:43.245932 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11026 17:44:43.261963 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11027 17:44:43.286756 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11028 17:44:43.304501 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11029 17:44:43.324315 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11030 17:44:43.343058 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11031 17:44:43.363709 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11032 17:44:43.377496 See 'systemctl status systemd-remount-fs.service' for details.
11033 17:44:43.430104 Mounting [0;1;39mKernel Configuration File System[0m...
11034 17:44:43.447672 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11035 17:44:43.464303 <46>[ 19.322513] systemd-journald[174]: Received client request to flush runtime journal.
11036 17:44:43.473241 Starting [0;1;39mLoad/Save Random Seed[0m...
11037 17:44:43.497632 Starting [0;1;39mApply Kernel Variables[0m...
11038 17:44:43.523012 Starting [0;1;39mCreate System Users[0m...
11039 17:44:43.545059 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11040 17:44:43.566532 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11041 17:44:43.590154 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11042 17:44:43.607251 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11043 17:44:43.622969 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11044 17:44:43.637897 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11045 17:44:43.702066 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11046 17:44:43.721776 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11047 17:44:43.733313 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11048 17:44:43.749121 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11049 17:44:43.806247 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11050 17:44:43.829437 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11051 17:44:43.851187 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11052 17:44:43.872216 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11053 17:44:43.915201 Starting [0;1;39mNetwork Time Synchronization[0m...
11054 17:44:43.936881 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11055 17:44:43.991294 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11056 17:44:44.005689 <6>[ 19.864111] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11057 17:44:44.012785 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11058 17:44:44.025259 <6>[ 19.886500] remoteproc remoteproc0: scp is available
11059 17:44:44.031939 <6>[ 19.892457] remoteproc remoteproc0: powering up scp
11060 17:44:44.037964 <6>[ 19.897625] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11061 17:44:44.045074 <6>[ 19.906068] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11062 17:44:44.051523 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11063 17:44:44.069867 <3>[ 19.927934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11064 17:44:44.076318 <6>[ 19.931884] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11065 17:44:44.086033 <3>[ 19.936103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11066 17:44:44.093075 <3>[ 19.936108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11067 17:44:44.102546 <3>[ 19.937629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11068 17:44:44.109249 <6>[ 19.943883] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11069 17:44:44.119522 <3>[ 19.951926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11070 17:44:44.126146 <6>[ 19.960010] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11071 17:44:44.136064 <3>[ 19.967960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11072 17:44:44.142713 <3>[ 19.967966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11073 17:44:44.152660 <3>[ 19.967970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 17:44:44.159189 <4>[ 19.983666] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11075 17:44:44.165623 <3>[ 20.010899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11076 17:44:44.172387 <4>[ 20.022261] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11077 17:44:44.182424 <3>[ 20.027215] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11078 17:44:44.189211 <6>[ 20.027295] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11079 17:44:44.195618 <6>[ 20.027304] remoteproc remoteproc0: remote processor scp is now up
11080 17:44:44.202628 <6>[ 20.027307] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11081 17:44:44.209093 <6>[ 20.030689] mc: Linux media interface: v0.10
11082 17:44:44.215772 <6>[ 20.033756] usbcore: registered new interface driver r8152
11083 17:44:44.222163 <3>[ 20.040676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11084 17:44:44.228605 <6>[ 20.054822] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11085 17:44:44.238941 <3>[ 20.057190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11086 17:44:44.245333 <4>[ 20.084592] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11087 17:44:44.252384 <4>[ 20.084592] Fallback method does not support PEC.
11088 17:44:44.258678 <3>[ 20.089116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11089 17:44:44.264987 <6>[ 20.100591] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11090 17:44:44.275964 <3>[ 20.104736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11091 17:44:44.282673 <3>[ 20.104741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11092 17:44:44.292395 <3>[ 20.104751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11093 17:44:44.299259 <3>[ 20.104756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11094 17:44:44.305578 <3>[ 20.104929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11095 17:44:44.315793 <6>[ 20.111189] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11096 17:44:44.319020 <6>[ 20.118703] pci_bus 0000:00: root bus resource [bus 00-ff]
11097 17:44:44.329342 <4>[ 20.137795] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11098 17:44:44.335864 <6>[ 20.141541] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11099 17:44:44.346008 <6>[ 20.142541] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11100 17:44:44.355760 <6>[ 20.142664] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11101 17:44:44.362451 <6>[ 20.144199] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11102 17:44:44.372770 <3>[ 20.145444] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11103 17:44:44.379444 <4>[ 20.149621] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11104 17:44:44.389192 <6>[ 20.157719] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11105 17:44:44.399395 <6>[ 20.166156] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11106 17:44:44.406592 <6>[ 20.174017] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11107 17:44:44.413434 <6>[ 20.174032] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11108 17:44:44.417122 <6>[ 20.174103] pci 0000:00:00.0: supports D1 D2
11109 17:44:44.423536 <6>[ 20.174104] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11110 17:44:44.433573 <6>[ 20.175146] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11111 17:44:44.440647 <6>[ 20.182563] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11112 17:44:44.448282 <6>[ 20.187356] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11113 17:44:44.455276 <6>[ 20.215177] videodev: Linux video capture interface: v2.00
11114 17:44:44.462028 <6>[ 20.220788] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11115 17:44:44.465414 <6>[ 20.221202] usbcore: registered new interface driver cdc_ether
11116 17:44:44.472884 <6>[ 20.229971] Bluetooth: Core ver 2.22
11117 17:44:44.479573 <6>[ 20.237823] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11118 17:44:44.486005 <6>[ 20.237842] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11119 17:44:44.492906 <6>[ 20.238407] usbcore: registered new interface driver r8153_ecm
11120 17:44:44.496270 <6>[ 20.246027] NET: Registered PF_BLUETOOTH protocol family
11121 17:44:44.503387 <6>[ 20.254681] r8152 2-1.3:1.0 eth0: v1.12.13
11122 17:44:44.506629 <6>[ 20.255930] pci 0000:01:00.0: supports D1 D2
11123 17:44:44.513642 <6>[ 20.264544] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11124 17:44:44.520069 <6>[ 20.265891] Bluetooth: HCI device and connection manager initialized
11125 17:44:44.527245 <6>[ 20.272142] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11126 17:44:44.533843 <6>[ 20.282502] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11127 17:44:44.537089 <6>[ 20.284265] Bluetooth: HCI socket layer initialized
11128 17:44:44.547455 <3>[ 20.288114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11129 17:44:44.554832 <3>[ 20.288864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11130 17:44:44.564872 <6>[ 20.291055] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11131 17:44:44.567753 <6>[ 20.299652] Bluetooth: L2CAP socket layer initialized
11132 17:44:44.578635 <6>[ 20.308345] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11133 17:44:44.585205 <6>[ 20.308359] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11134 17:44:44.592314 <6>[ 20.309624] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11135 17:44:44.605054 <6>[ 20.310876] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11136 17:44:44.611818 <6>[ 20.311075] usbcore: registered new interface driver uvcvideo
11137 17:44:44.615455 <6>[ 20.316039] Bluetooth: SCO socket layer initialized
11138 17:44:44.622399 <6>[ 20.320354] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11139 17:44:44.632823 <3>[ 20.323250] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11140 17:44:44.639006 <3>[ 20.324055] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11141 17:44:44.650506 <3>[ 20.337445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11142 17:44:44.656563 <6>[ 20.337743] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11143 17:44:44.663620 <6>[ 20.346131] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11144 17:44:44.667063 <6>[ 20.352680] pci 0000:00:00.0: PCI bridge to [bus 01]
11145 17:44:44.677364 <3>[ 20.366082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11146 17:44:44.684524 <6>[ 20.368668] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11147 17:44:44.691030 <6>[ 20.368883] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11148 17:44:44.697934 <6>[ 20.369330] usbcore: registered new interface driver btusb
11149 17:44:44.708092 <4>[ 20.373508] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11150 17:44:44.714657 <6>[ 20.379804] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11151 17:44:44.720885 <3>[ 20.385909] Bluetooth: hci0: Failed to load firmware file (-2)
11152 17:44:44.724758 <6>[ 20.393119] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11153 17:44:44.734185 <3>[ 20.396368] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11154 17:44:44.740858 <3>[ 20.399690] Bluetooth: hci0: Failed to set up firmware (-2)
11155 17:44:44.747716 <3>[ 20.418957] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11156 17:44:44.760860 <4>[ 20.422311] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11157 17:44:44.767733 <5>[ 20.424207] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11158 17:44:44.773961 <5>[ 20.439465] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11159 17:44:44.784697 <3>[ 20.451230] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11160 17:44:44.790658 <4>[ 20.451861] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11161 17:44:44.800755 <6>[ 20.561996] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11162 17:44:44.803892 <6>[ 20.564025] cfg80211: failed to load regulatory.db
11163 17:44:44.811016 <6>[ 20.574632] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11164 17:44:44.817375 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11165 17:44:44.836613 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 20.697973] mt7921e 0000:01:00.0: ASIC revision: 79610010
11166 17:44:44.840249 em Time Set[0m.
11167 17:44:44.857270 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11168 17:44:44.889343 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11169 17:44:44.913229 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11170 17:44:44.943180 <4>[ 20.798341] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11171 17:44:45.061261 <4>[ 20.916490] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11172 17:44:45.067872 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11173 17:44:45.081177 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11174 17:44:45.100855 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11175 17:44:45.116284 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11176 17:44:45.133117 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11177 17:44:45.153007 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11178 17:44:45.177845 [[0;32m OK [0m] Reached target [0;1;39mSock<4>[ 21.033533] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11179 17:44:45.177933 ets[0m.
11180 17:44:45.194410 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11181 17:44:45.213157 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11182 17:44:45.258082 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11183 17:44:45.298932 <4>[ 21.153779] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11184 17:44:45.311951 Starting [0;1;39mUser Login Management[0m...
11185 17:44:45.329031 Starting [0;1;39mPermit User Sessions[0m...
11186 17:44:45.350835 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11187 17:44:45.367941 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11188 17:44:45.387492 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11189 17:44:45.417201 [[0;32m OK [<4>[ 21.272988] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11190 17:44:45.424044 0m] Started [0;1;39mUser Login Management[0m.
11191 17:44:45.459129 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11192 17:44:45.514666 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11193 17:44:45.525555 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11194 17:44:45.538673 <4>[ 21.393613] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11195 17:44:45.546237 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11196 17:44:45.561974 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11197 17:44:45.602743 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11198 17:44:45.641047 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11199 17:44:45.658168 <4>[ 21.513406] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11200 17:44:45.699843
11201 17:44:45.699937
11202 17:44:45.702690 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11203 17:44:45.702818
11204 17:44:45.706056 debian-bullseye-arm64 login: root (automatic login)
11205 17:44:45.706140
11206 17:44:45.706205
11207 17:44:45.733608 Linux debian-bullseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023 aarch64
11208 17:44:45.733695
11209 17:44:45.740049 The programs included with the Debian GNU/Linux system are free software;
11210 17:44:45.746642 the exact distribution terms for each program are described in the
11211 17:44:45.750128 individual files in /usr/share/doc/*/copyright.
11212 17:44:45.750211
11213 17:44:45.756984 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11214 17:44:45.759670 permitted by applicable law.
11215 17:44:45.760012 Matched prompt #10: / #
11217 17:44:45.760217 Setting prompt string to ['/ #']
11218 17:44:45.760310 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11220 17:44:45.760504 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11221 17:44:45.760595 start: 2.2.6 expect-shell-connection (timeout 00:01:42) [common]
11222 17:44:45.760666 Setting prompt string to ['/ #']
11223 17:44:45.760726 Forcing a shell prompt, looking for ['/ #']
11225 17:44:45.810910 / #
11226 17:44:45.811025 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11227 17:44:45.811103 Waiting using forced prompt support (timeout 00:02:30)
11228 17:44:45.811200 <4>[ 21.633412] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11229 17:44:45.816421
11230 17:44:45.816694 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11231 17:44:45.816784 start: 2.2.7 export-device-env (timeout 00:01:42) [common]
11232 17:44:45.816884 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11233 17:44:45.816981 end: 2.2 depthcharge-retry (duration 00:03:18) [common]
11234 17:44:45.817072 end: 2 depthcharge-action (duration 00:03:18) [common]
11235 17:44:45.817160 start: 3 lava-test-retry (timeout 00:05:00) [common]
11236 17:44:45.817245 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11237 17:44:45.817318 Using namespace: common
11239 17:44:45.917663 / # #
11240 17:44:45.917822 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11241 17:44:45.917944 #<4>[ 21.753192] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11242 17:44:45.923320
11243 17:44:45.923588 Using /lava-11518283
11245 17:44:46.023925 / # export SHELL=/bin/sh
11246 17:44:46.024101 export SHELL=/bin/sh<4>[ 21.873223] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11247 17:44:46.029518
11249 17:44:46.171343 / # . /lava-11518283/environment
11250 17:44:46.171512 <3>[ 21.991120] mt7921e 0000:01:00.0: hardware init failed
11251 17:44:46.176777 . /lava-11518283/environment
11253 17:44:46.277308 / # /lava-11518283/bin/lava-test-runner /lava-11518283/0
11254 17:44:46.277441 Test shell timeout: 10s (minimum of the action and connection timeout)
11255 17:44:46.282740 /lava-11518283/bin/lava-test-runner /lava-11518283/0
11256 17:44:46.304460 + export TESTRUN_ID=0_sleep
11257 17:44:46.307703 + cd /lava-11518283/0/tests/0_sleep
11258 17:44:46.310878 + cat uuid
11259 17:44:46.310961 + UUID=11518283_1.5.2.3.1
11260 17:44:46.311027 + set +x
11261 17:44:46.317629 <LAVA_SIGNAL_STARTRUN 0_sleep 11518283_1.5.2.3.1>
11262 17:44:46.317889 Received signal: <STARTRUN> 0_sleep 11518283_1.5.2.3.1
11263 17:44:46.317965 Starting test lava.0_sleep (11518283_1.5.2.3.1)
11264 17:44:46.318048 Skipping test definition patterns.
11265 17:44:46.320757 + ./config/lava/sleep/sleep.sh mem freeze
11266 17:44:46.324092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11267 17:44:46.324344 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11269 17:44:46.330670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11270 17:44:46.330977 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11272 17:44:46.334207 rtcwake: assuming RTC uses UTC ...
11273 17:44:46.344271 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:44:51<6>[ 22.206079] PM: suspend entry (deep)
11274 17:44:46.344353 2023
11275 17:44:46.347910 <6>[ 22.210881] Filesystems sync: 0.000 seconds
11276 17:44:46.356850 <6>[ 22.218468] Freezing user space processes
11277 17:44:46.366845 <6>[ 22.224800] Freezing user space processes completed (elapsed 0.002 seconds)
11278 17:44:46.370249 <6>[ 22.232070] OOM killer disabled.
11279 17:44:46.373006 <6>[ 22.235567] Freezing remaining freezable tasks
11280 17:44:46.383428 <6>[ 22.241668] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11281 17:44:46.389832 <6>[ 22.249361] printk: Suspending console(s) (use no_console_suspend to debug)
11282 17:44:49.786607 <3>[ 25.422723] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11283 17:44:49.796068 <3>[ 25.422765] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11284 17:44:49.806215 <3>[ 25.422803] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11285 17:44:49.812917 <3>[ 25.422839] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11286 17:44:49.819379 <3>[ 25.423115] PM: Some devices failed to suspend, or early wake event detected
11287 17:44:49.829756 <4>[ 25.439054] typec port0-partner: PM: parent port0 should not be sleeping
11288 17:44:49.832928 <6>[ 25.695430] OOM killer enabled.
11289 17:44:49.836030 <6>[ 25.698848] Restarting tasks ... done.
11290 17:44:49.842926 <5>[ 25.705006] random: crng reseeded on system resumption
11291 17:44:49.846303 <6>[ 25.711406] PM: suspend exit
11292 17:44:49.849468 rtcwake: write error
11293 17:44:49.857974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11294 17:44:49.858254 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11296 17:44:49.860939 rtcwake: assuming RTC uses UTC ...
11297 17:44:49.867572 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:44:54 2023
11298 17:44:49.881059 <6>[ 25.743271] PM: suspend entry (deep)
11299 17:44:49.884539 <6>[ 25.747181] Filesystems sync: 0.000 seconds
11300 17:44:49.887443 <6>[ 25.752328] Freezing user space processes
11301 17:44:49.899912 <6>[ 25.758698] Freezing user space processes completed (elapsed 0.001 seconds)
11302 17:44:49.903448 <6>[ 25.765930] OOM killer disabled.
11303 17:44:49.906381 <6>[ 25.769420] Freezing remaining freezable tasks
11304 17:44:49.916554 <6>[ 25.775424] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11305 17:44:49.923218 <6>[ 25.783096] printk: Suspending console(s) (use no_console_suspend to debug)
11306 17:44:53.377860 <3>[ 29.006702] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11307 17:44:53.387537 <3>[ 29.006728] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11308 17:44:53.397426 <3>[ 29.006759] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11309 17:44:53.404070 <3>[ 29.006791] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11310 17:44:53.410901 <3>[ 29.007007] PM: Some devices failed to suspend, or early wake event detected
11311 17:44:53.417475 <6>[ 29.280265] OOM killer enabled.
11312 17:44:53.421189 <6>[ 29.283677] Restarting tasks ... done.
11313 17:44:53.428017 <5>[ 29.289990] random: crng reseeded on system resumption
11314 17:44:53.430933 <6>[ 29.296287] PM: suspend exit
11315 17:44:53.434440 rtcwake: write error
11316 17:44:53.440909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11317 17:44:53.441264 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11319 17:44:53.444187 rtcwake: assuming RTC uses UTC ...
11320 17:44:53.451358 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:44:58 2023
11321 17:44:53.464222 <6>[ 29.326983] PM: suspend entry (deep)
11322 17:44:53.467927 <6>[ 29.330902] Filesystems sync: 0.000 seconds
11323 17:44:53.471400 <6>[ 29.336024] Freezing user space processes
11324 17:44:53.483144 <6>[ 29.342306] Freezing user space processes completed (elapsed 0.001 seconds)
11325 17:44:53.486155 <6>[ 29.349607] OOM killer disabled.
11326 17:44:53.489750 <6>[ 29.353101] Freezing remaining freezable tasks
11327 17:44:53.500414 <6>[ 29.359143] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11328 17:44:53.506644 <6>[ 29.366816] printk: Suspending console(s) (use no_console_suspend to debug)
11329 17:44:56.957536 <3>[ 32.590678] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11330 17:44:56.967874 <3>[ 32.590712] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11331 17:44:56.977656 <3>[ 32.590756] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11332 17:44:56.984605 <3>[ 32.590791] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11333 17:44:56.991263 <3>[ 32.591027] PM: Some devices failed to suspend, or early wake event detected
11334 17:44:56.994698 <6>[ 32.860268] OOM killer enabled.
11335 17:44:57.003293 <6>[ 32.863681] Restarting tasks ... done.
11336 17:44:57.009899 <5>[ 32.872602] random: crng reseeded on system resumption
11337 17:44:57.013082 <6>[ 32.878829] PM: suspend exit
11338 17:44:57.016120 rtcwake: write error
11339 17:44:57.024795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11340 17:44:57.025165 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11342 17:44:57.028363 rtcwake: assuming RTC uses UTC ...
11343 17:44:57.034545 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:45:02 2023
11344 17:44:57.047516 <6>[ 32.910466] PM: suspend entry (deep)
11345 17:44:57.051176 <6>[ 32.914337] Filesystems sync: 0.000 seconds
11346 17:44:57.054503 <6>[ 32.919369] Freezing user space processes
11347 17:44:57.066199 <6>[ 32.925380] Freezing user space processes completed (elapsed 0.001 seconds)
11348 17:44:57.069291 <6>[ 32.932635] OOM killer disabled.
11349 17:44:57.072912 <6>[ 32.936117] Freezing remaining freezable tasks
11350 17:44:57.082815 <6>[ 32.942200] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11351 17:44:57.089260 <6>[ 32.949879] printk: Suspending console(s) (use no_console_suspend to debug)
11352 17:45:00.541727 <3>[ 36.174688] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11353 17:45:00.551935 <3>[ 36.174718] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11354 17:45:00.562037 <3>[ 36.174763] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11355 17:45:00.569158 <3>[ 36.174803] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11356 17:45:00.575353 <3>[ 36.175103] PM: Some devices failed to suspend, or early wake event detected
11357 17:45:00.578440 <6>[ 36.444668] OOM killer enabled.
11358 17:45:00.586843 <6>[ 36.448081] Restarting tasks ... done.
11359 17:45:00.590435 <5>[ 36.454085] random: crng reseeded on system resumption
11360 17:45:00.593891 <6>[ 36.460447] PM: suspend exit
11361 17:45:00.597653 rtcwake: write error
11362 17:45:00.605445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11363 17:45:00.606274 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11365 17:45:00.608930 rtcwake: assuming RTC uses UTC ...
11366 17:45:00.615036 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:45:05 2023
11367 17:45:00.627637 <6>[ 36.490682] PM: suspend entry (deep)
11368 17:45:00.630909 <6>[ 36.494571] Filesystems sync: 0.000 seconds
11369 17:45:00.634342 <6>[ 36.499568] Freezing user space processes
11370 17:45:00.645481 <6>[ 36.505450] Freezing user space processes completed (elapsed 0.001 seconds)
11371 17:45:00.649131 <6>[ 36.512672] OOM killer disabled.
11372 17:45:00.652648 <6>[ 36.516153] Freezing remaining freezable tasks
11373 17:45:00.662761 <6>[ 36.522036] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11374 17:45:00.668986 <6>[ 36.529686] printk: Suspending console(s) (use no_console_suspend to debug)
11375 17:45:04.124830 <3>[ 39.758676] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11376 17:45:04.137889 <3>[ 39.758707] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11377 17:45:04.144985 <3>[ 39.758751] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11378 17:45:04.151452 <3>[ 39.758792] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11379 17:45:04.157893 <3>[ 39.759100] PM: Some devices failed to suspend, or early wake event detected
11380 17:45:04.165072 <6>[ 40.028796] OOM killer enabled.
11381 17:45:04.168220 <6>[ 40.032207] Restarting tasks ... done.
11382 17:45:04.175810 <5>[ 40.039963] random: crng reseeded on system resumption
11383 17:45:04.180164 <6>[ 40.047182] PM: suspend exit
11384 17:45:04.183017 rtcwake: write error
11385 17:45:04.191328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11386 17:45:04.191585 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11388 17:45:04.194555 rtcwake: assuming RTC uses UTC ...
11389 17:45:04.201396 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:45:09 2023
11390 17:45:04.214005 <6>[ 40.077813] PM: suspend entry (deep)
11391 17:45:04.217504 <6>[ 40.081711] Filesystems sync: 0.000 seconds
11392 17:45:04.220399 <6>[ 40.086823] Freezing user space processes
11393 17:45:04.232364 <6>[ 40.092668] Freezing user space processes completed (elapsed 0.001 seconds)
11394 17:45:04.235702 <6>[ 40.099894] OOM killer disabled.
11395 17:45:04.238605 <6>[ 40.103377] Freezing remaining freezable tasks
11396 17:45:04.249058 <6>[ 40.109390] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11397 17:45:04.255259 <6>[ 40.117056] printk: Suspending console(s) (use no_console_suspend to debug)
11398 17:45:07.708447 <3>[ 43.342675] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11399 17:45:07.718636 <3>[ 43.342706] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11400 17:45:07.728572 <3>[ 43.342751] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11401 17:45:07.735235 <3>[ 43.342791] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11402 17:45:07.741541 <3>[ 43.343077] PM: Some devices failed to suspend, or early wake event detected
11403 17:45:07.748102 <6>[ 43.612761] OOM killer enabled.
11404 17:45:07.751649 <6>[ 43.616171] Restarting tasks ... done.
11405 17:45:07.759165 <5>[ 43.623772] random: crng reseeded on system resumption
11406 17:45:07.762573 <6>[ 43.630040] PM: suspend exit
11407 17:45:07.766091 rtcwake: write error
11408 17:45:07.773081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11409 17:45:07.773361 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11411 17:45:07.776741 rtcwake: assuming RTC uses UTC ...
11412 17:45:07.783474 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:45:12 2023
11413 17:45:07.796178 <6>[ 43.660291] PM: suspend entry (deep)
11414 17:45:07.799015 <6>[ 43.664190] Filesystems sync: 0.000 seconds
11415 17:45:07.802552 <6>[ 43.669240] Freezing user space processes
11416 17:45:07.813666 <6>[ 43.675044] Freezing user space processes completed (elapsed 0.001 seconds)
11417 17:45:07.817470 <6>[ 43.682263] OOM killer disabled.
11418 17:45:07.820755 <6>[ 43.685742] Freezing remaining freezable tasks
11419 17:45:07.830875 <6>[ 43.691800] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11420 17:45:07.837557 <6>[ 43.699472] printk: Suspending console(s) (use no_console_suspend to debug)
11421 17:45:11.292142 <3>[ 46.926674] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11422 17:45:11.301802 <3>[ 46.926706] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11423 17:45:11.311786 <3>[ 46.926749] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11424 17:45:11.318702 <3>[ 46.926790] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11425 17:45:11.325357 <3>[ 46.927082] PM: Some devices failed to suspend, or early wake event detected
11426 17:45:11.332109 <6>[ 47.196796] OOM killer enabled.
11427 17:45:11.335123 <6>[ 47.200215] Restarting tasks ... done.
11428 17:45:11.342963 <5>[ 47.207815] random: crng reseeded on system resumption
11429 17:45:11.346734 <6>[ 47.215049] PM: suspend exit
11430 17:45:11.350037 rtcwake: write error
11431 17:45:11.358038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11432 17:45:11.358327 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11434 17:45:11.361797 rtcwake: assuming RTC uses UTC ...
11435 17:45:11.368459 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:45:16 2023
11436 17:45:11.380626 <6>[ 47.245435] PM: suspend entry (deep)
11437 17:45:11.384360 <6>[ 47.249331] Filesystems sync: 0.000 seconds
11438 17:45:11.387059 <6>[ 47.254328] Freezing user space processes
11439 17:45:11.398909 <6>[ 47.260328] Freezing user space processes completed (elapsed 0.001 seconds)
11440 17:45:11.402240 <6>[ 47.267558] OOM killer disabled.
11441 17:45:11.405647 <6>[ 47.271042] Freezing remaining freezable tasks
11442 17:45:11.416086 <6>[ 47.277085] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11443 17:45:11.422825 <6>[ 47.284756] printk: Suspending console(s) (use no_console_suspend to debug)
11444 17:45:14.871809 <6>[ 48.206805] vpu: disabling
11445 17:45:14.875405 <6>[ 48.206957] vproc2: disabling
11446 17:45:14.878799 <6>[ 48.207022] vproc1: disabling
11447 17:45:14.882502 <6>[ 48.207077] vaud18: disabling
11448 17:45:14.885215 <6>[ 48.207324] vsram_others: disabling
11449 17:45:14.888851 <6>[ 48.207522] va09: disabling
11450 17:45:14.892158 <6>[ 48.207600] vsram_md: disabling
11451 17:45:14.895451 <6>[ 48.207728] Vgpu: disabling
11452 17:45:14.902331 <3>[ 50.510705] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11453 17:45:14.911917 <3>[ 50.510744] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11454 17:45:14.922300 <3>[ 50.510791] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11455 17:45:14.929001 <3>[ 50.510833] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11456 17:45:14.935957 <3>[ 50.511059] PM: Some devices failed to suspend, or early wake event detected
11457 17:45:14.939554 <6>[ 50.806398] OOM killer enabled.
11458 17:45:14.946597 <6>[ 50.809797] Restarting tasks ... done.
11459 17:45:14.953560 <5>[ 50.817814] random: crng reseeded on system resumption
11460 17:45:14.956849 <6>[ 50.824490] PM: suspend exit
11461 17:45:14.960413 rtcwake: write error
11462 17:45:14.966668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11463 17:45:14.966993 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11465 17:45:14.970274 rtcwake: assuming RTC uses UTC ...
11466 17:45:14.976927 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:45:20 2023
11467 17:45:14.989322 <6>[ 50.854598] PM: suspend entry (deep)
11468 17:45:14.992512 <6>[ 50.858520] Filesystems sync: 0.000 seconds
11469 17:45:14.995979 <6>[ 50.863555] Freezing user space processes
11470 17:45:15.007547 <6>[ 50.869565] Freezing user space processes completed (elapsed 0.001 seconds)
11471 17:45:15.011136 <6>[ 50.876801] OOM killer disabled.
11472 17:45:15.014364 <6>[ 50.880283] Freezing remaining freezable tasks
11473 17:45:15.024692 <6>[ 50.886330] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11474 17:45:15.031140 <6>[ 50.894017] printk: Suspending console(s) (use no_console_suspend to debug)
11475 17:45:18.459160 <3>[ 54.094857] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11476 17:45:18.469062 <3>[ 54.094965] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11477 17:45:18.479046 <3>[ 54.095033] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11478 17:45:18.485621 <3>[ 54.095077] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11479 17:45:18.492456 <3>[ 54.095348] PM: Some devices failed to suspend, or early wake event detected
11480 17:45:18.498913 <6>[ 54.364810] OOM killer enabled.
11481 17:45:18.502485 <6>[ 54.368220] Restarting tasks ... done.
11482 17:45:18.510541 <5>[ 54.375819] random: crng reseeded on system resumption
11483 17:45:18.513341 <6>[ 54.382064] PM: suspend exit
11484 17:45:18.516870 rtcwake: write error
11485 17:45:18.524220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11486 17:45:18.524482 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11488 17:45:18.527894 rtcwake: assuming RTC uses UTC ...
11489 17:45:18.534164 rtcwake: wakeup from "mem" using rtc0 at Wed Sep 13 17:45:23 2023
11490 17:45:18.546802 <6>[ 54.412663] PM: suspend entry (deep)
11491 17:45:18.550202 <6>[ 54.416550] Filesystems sync: 0.000 seconds
11492 17:45:18.553507 <6>[ 54.421583] Freezing user space processes
11493 17:45:18.564747 <6>[ 54.427503] Freezing user space processes completed (elapsed 0.001 seconds)
11494 17:45:18.568076 <6>[ 54.434730] OOM killer disabled.
11495 17:45:18.571646 <6>[ 54.438206] Freezing remaining freezable tasks
11496 17:45:18.582057 <6>[ 54.444306] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11497 17:45:18.588745 <6>[ 54.451978] printk: Suspending console(s) (use no_console_suspend to debug)
11498 17:45:22.043171 <3>[ 57.678675] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11499 17:45:22.053208 <3>[ 57.678707] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11500 17:45:22.063308 <3>[ 57.678751] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11501 17:45:22.070018 <3>[ 57.678792] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11502 17:45:22.076567 <3>[ 57.679035] PM: Some devices failed to suspend, or early wake event detected
11503 17:45:22.079979 <6>[ 57.948769] OOM killer enabled.
11504 17:45:22.088524 <6>[ 57.952179] Restarting tasks ... done.
11505 17:45:22.094800 <5>[ 57.959537] random: crng reseeded on system resumption
11506 17:45:22.098448 <6>[ 57.965775] PM: suspend exit
11507 17:45:22.101534 rtcwake: write error
11508 17:45:22.108514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11509 17:45:22.109387 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11511 17:45:22.111828 rtcwake: assuming RTC uses UTC ...
11512 17:45:22.118380 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:27 2023
11513 17:45:22.132180 <6>[ 57.997593] PM: suspend entry (s2idle)
11514 17:45:22.135665 <6>[ 58.001668] Filesystems sync: 0.000 seconds
11515 17:45:22.138703 <6>[ 58.006821] Freezing user space processes
11516 17:45:22.150226 <6>[ 58.012738] Freezing user space processes completed (elapsed 0.001 seconds)
11517 17:45:22.153826 <6>[ 58.019971] OOM killer disabled.
11518 17:45:22.157133 <6>[ 58.023453] Freezing remaining freezable tasks
11519 17:45:22.167164 <6>[ 58.029466] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11520 17:45:22.174040 <6>[ 58.037137] printk: Suspending console(s) (use no_console_suspend to debug)
11521 17:45:25.630967 <3>[ 61.262677] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11522 17:45:25.640379 <3>[ 61.262709] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11523 17:45:25.650846 <3>[ 61.262753] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11524 17:45:25.657387 <3>[ 61.262795] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11525 17:45:25.663801 <3>[ 61.263093] PM: Some devices failed to suspend, or early wake event detected
11526 17:45:25.667369 <6>[ 61.536695] OOM killer enabled.
11527 17:45:25.675947 <6>[ 61.540108] Restarting tasks ... done.
11528 17:45:25.679340 <5>[ 61.546080] random: crng reseeded on system resumption
11529 17:45:25.683292 <6>[ 61.552270] PM: suspend exit
11530 17:45:25.686251 rtcwake: write error
11531 17:45:25.694176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11532 17:45:25.695224 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11534 17:45:25.697493 rtcwake: assuming RTC uses UTC ...
11535 17:45:25.703942 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:30 2023
11536 17:45:25.716814 <6>[ 61.582645] PM: suspend entry (s2idle)
11537 17:45:25.719698 <6>[ 61.586712] Filesystems sync: 0.000 seconds
11538 17:45:25.726166 <6>[ 61.591720] Freezing user space processes
11539 17:45:25.733149 <6>[ 61.597622] Freezing user space processes completed (elapsed 0.001 seconds)
11540 17:45:25.736505 <6>[ 61.604855] OOM killer disabled.
11541 17:45:25.743063 <6>[ 61.608338] Freezing remaining freezable tasks
11542 17:45:25.749418 <6>[ 61.614455] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11543 17:45:25.759265 <6>[ 61.622130] printk: Suspending console(s) (use no_console_suspend to debug)
11544 17:45:29.214189 <3>[ 64.846674] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11545 17:45:29.224140 <3>[ 64.846705] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11546 17:45:29.234455 <3>[ 64.846751] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11547 17:45:29.240981 <3>[ 64.846792] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11548 17:45:29.247351 <3>[ 64.847031] PM: Some devices failed to suspend, or early wake event detected
11549 17:45:29.250686 <6>[ 65.120683] OOM killer enabled.
11550 17:45:29.259621 <6>[ 65.124095] Restarting tasks ... done.
11551 17:45:29.266670 <5>[ 65.131889] random: crng reseeded on system resumption
11552 17:45:29.269432 <6>[ 65.138116] PM: suspend exit
11553 17:45:29.273067 rtcwake: write error
11554 17:45:29.279906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11555 17:45:29.280169 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11557 17:45:29.283358 rtcwake: assuming RTC uses UTC ...
11558 17:45:29.289489 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:34 2023
11559 17:45:29.301374 <6>[ 65.168374] PM: suspend entry (s2idle)
11560 17:45:29.304736 <6>[ 65.172450] Filesystems sync: 0.000 seconds
11561 17:45:29.308326 <6>[ 65.177456] Freezing user space processes
11562 17:45:29.319481 <6>[ 65.183371] Freezing user space processes completed (elapsed 0.001 seconds)
11563 17:45:29.323394 <6>[ 65.190600] OOM killer disabled.
11564 17:45:29.326432 <6>[ 65.194076] Freezing remaining freezable tasks
11565 17:45:29.336605 <6>[ 65.200105] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11566 17:45:29.343497 <6>[ 65.207794] printk: Suspending console(s) (use no_console_suspend to debug)
11567 17:45:32.797628 <3>[ 68.430676] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11568 17:45:32.807398 <3>[ 68.430707] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11569 17:45:32.817800 <3>[ 68.430752] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11570 17:45:32.824428 <3>[ 68.430793] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11571 17:45:32.831339 <3>[ 68.431081] PM: Some devices failed to suspend, or early wake event detected
11572 17:45:32.834528 <6>[ 68.704683] OOM killer enabled.
11573 17:45:32.842616 <6>[ 68.708095] Restarting tasks ... done.
11574 17:45:32.846403 <5>[ 68.714117] random: crng reseeded on system resumption
11575 17:45:32.849847 <6>[ 68.720599] PM: suspend exit
11576 17:45:32.853619 rtcwake: write error
11577 17:45:32.861756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11578 17:45:32.862049 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11580 17:45:32.865280 rtcwake: assuming RTC uses UTC ...
11581 17:45:32.871920 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:37 2023
11582 17:45:32.884726 <6>[ 68.752024] PM: suspend entry (s2idle)
11583 17:45:32.888109 <6>[ 68.756078] Filesystems sync: 0.000 seconds
11584 17:45:32.891503 <6>[ 68.761087] Freezing user space processes
11585 17:45:32.902776 <6>[ 68.766454] Freezing user space processes completed (elapsed 0.001 seconds)
11586 17:45:32.906256 <6>[ 68.773670] OOM killer disabled.
11587 17:45:32.909475 <6>[ 68.777149] Freezing remaining freezable tasks
11588 17:45:32.919488 <6>[ 68.783020] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11589 17:45:32.926328 <6>[ 68.790671] printk: Suspending console(s) (use no_console_suspend to debug)
11590 17:45:36.381484 <3>[ 72.014677] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11591 17:45:36.391138 <3>[ 72.014708] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11592 17:45:36.401459 <3>[ 72.014753] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11593 17:45:36.407553 <3>[ 72.014794] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11594 17:45:36.506039 <3>[ 72.015034] PM: Some devices failed to suspend, or early wake event detected
11595 17:45:36.506617 <6>[ 72.288705] OOM killer enabled.
11596 17:45:36.507019 <6>[ 72.292117] Restarting tasks ... done.
11597 17:45:36.507343 <5>[ 72.299640] random: crng reseeded on system resumption
11598 17:45:36.507653 <6>[ 72.305870] PM: suspend exit
11599 17:45:36.507953 rtcwake: write error
11600 17:45:36.508244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11601 17:45:36.508537 rtcwake: assuming RTC uses UTC ...
11602 17:45:36.508825 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:41 2023
11603 17:45:36.509112 <6>[ 72.336201] PM: suspend entry (s2idle)
11604 17:45:36.509491 <6>[ 72.340266] Filesystems sync: 0.000 seconds
11605 17:45:36.509987 <6>[ 72.345324] Freezing user space processes
11606 17:45:36.510340 <6>[ 72.351145] Freezing user space processes completed (elapsed 0.001 seconds)
11607 17:45:36.510644 <6>[ 72.358369] OOM killer disabled.
11608 17:45:36.510962 <6>[ 72.361845] Freezing remaining freezable tasks
11609 17:45:36.511249 <6>[ 72.367956] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11610 17:45:36.511605 <6>[ 72.375629] printk: Suspending console(s) (use no_console_suspend to debug)
11611 17:45:36.512208 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11613 17:45:39.961178 <3>[ 75.598677] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11614 17:45:39.971074 <3>[ 75.598708] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11615 17:45:39.981266 <3>[ 75.598752] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11616 17:45:39.988238 <3>[ 75.598793] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11617 17:45:39.994814 <3>[ 75.599101] PM: Some devices failed to suspend, or early wake event detected
11618 17:45:39.997756 <6>[ 75.868715] OOM killer enabled.
11619 17:45:40.006436 <6>[ 75.872128] Restarting tasks ... done.
11620 17:45:40.013064 <5>[ 75.879695] random: crng reseeded on system resumption
11621 17:45:40.016710 <6>[ 75.886157] PM: suspend exit
11622 17:45:40.019589 rtcwake: write error
11623 17:45:40.026645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11624 17:45:40.027516 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11626 17:45:40.029499 rtcwake: assuming RTC uses UTC ...
11627 17:45:40.036698 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:45 2023
11628 17:45:40.048744 <6>[ 75.916752] PM: suspend entry (s2idle)
11629 17:45:40.052662 <6>[ 75.920826] Filesystems sync: 0.000 seconds
11630 17:45:40.056085 <6>[ 75.925811] Freezing user space processes
11631 17:45:40.067284 <6>[ 75.931767] Freezing user space processes completed (elapsed 0.001 seconds)
11632 17:45:40.070781 <6>[ 75.939006] OOM killer disabled.
11633 17:45:40.074437 <6>[ 75.942491] Freezing remaining freezable tasks
11634 17:45:40.084487 <6>[ 75.948513] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11635 17:45:40.090902 <6>[ 75.956188] printk: Suspending console(s) (use no_console_suspend to debug)
11636 17:45:43.544139 <3>[ 79.182759] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11637 17:45:43.554245 <3>[ 79.182797] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11638 17:45:43.564661 <3>[ 79.182849] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11639 17:45:43.570912 <3>[ 79.182889] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11640 17:45:43.578245 <3>[ 79.183144] PM: Some devices failed to suspend, or early wake event detected
11641 17:45:43.580885 <6>[ 79.452691] OOM killer enabled.
11642 17:45:43.589827 <6>[ 79.456103] Restarting tasks ... done.
11643 17:45:43.596713 <5>[ 79.463555] random: crng reseeded on system resumption
11644 17:45:43.599552 <6>[ 79.470506] PM: suspend exit
11645 17:45:43.603170 rtcwake: write error
11646 17:45:43.610269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11647 17:45:43.611260 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11649 17:45:43.613819 rtcwake: assuming RTC uses UTC ...
11650 17:45:43.620547 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:48 2023
11651 17:45:43.633275 <6>[ 79.500814] PM: suspend entry (s2idle)
11652 17:45:43.636301 <6>[ 79.504899] Filesystems sync: 0.000 seconds
11653 17:45:43.639271 <6>[ 79.509901] Freezing user space processes
11654 17:45:43.651263 <6>[ 79.515881] Freezing user space processes completed (elapsed 0.001 seconds)
11655 17:45:43.654850 <6>[ 79.523114] OOM killer disabled.
11656 17:45:43.657992 <6>[ 79.526599] Freezing remaining freezable tasks
11657 17:45:43.667771 <6>[ 79.532707] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11658 17:45:43.674636 <6>[ 79.540380] printk: Suspending console(s) (use no_console_suspend to debug)
11659 17:45:47.127556 <3>[ 82.766710] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11660 17:45:47.137962 <3>[ 82.766751] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11661 17:45:47.148128 <3>[ 82.766801] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11662 17:45:47.154772 <3>[ 82.766846] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11663 17:45:47.161269 <3>[ 82.767162] PM: Some devices failed to suspend, or early wake event detected
11664 17:45:47.164387 <6>[ 83.036663] OOM killer enabled.
11665 17:45:47.177069 <6>[ 83.040074] Restarting tasks ... done.
11666 17:45:47.183474 <5>[ 83.051390] random: crng reseeded on system resumption
11667 17:45:47.187045 <6>[ 83.059477] PM: suspend exit
11668 17:45:47.191346 rtcwake: write error
11669 17:45:47.199814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11670 17:45:47.200091 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11672 17:45:47.203259 rtcwake: assuming RTC uses UTC ...
11673 17:45:47.209662 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:52 2023
11674 17:45:47.222363 <6>[ 83.091647] PM: suspend entry (s2idle)
11675 17:45:47.225823 <6>[ 83.095720] Filesystems sync: 0.000 seconds
11676 17:45:47.229104 <6>[ 83.100758] Freezing user space processes
11677 17:45:47.240663 <6>[ 83.106623] Freezing user space processes completed (elapsed 0.001 seconds)
11678 17:45:47.244205 <6>[ 83.113850] OOM killer disabled.
11679 17:45:47.247287 <6>[ 83.117333] Freezing remaining freezable tasks
11680 17:45:47.257839 <6>[ 83.123405] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11681 17:45:47.264526 <6>[ 83.131084] printk: Suspending console(s) (use no_console_suspend to debug)
11682 17:45:50.711788 <3>[ 86.350749] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11683 17:45:50.721546 <3>[ 86.350783] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11684 17:45:50.731382 <3>[ 86.350832] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11685 17:45:50.738345 <3>[ 86.350871] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11686 17:45:50.744769 <3>[ 86.351131] PM: Some devices failed to suspend, or early wake event detected
11687 17:45:50.748042 <6>[ 86.620715] OOM killer enabled.
11688 17:45:50.756569 <6>[ 86.624131] Restarting tasks ... done.
11689 17:45:50.763528 <5>[ 86.631709] random: crng reseeded on system resumption
11690 17:45:50.766709 <6>[ 86.638897] PM: suspend exit
11691 17:45:50.770364 rtcwake: write error
11692 17:45:50.777772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11693 17:45:50.778033 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11695 17:45:50.781142 rtcwake: assuming RTC uses UTC ...
11696 17:45:50.787622 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:55 2023
11697 17:45:50.801050 <6>[ 86.670025] PM: suspend entry (s2idle)
11698 17:45:50.804309 <6>[ 86.674082] Filesystems sync: 0.000 seconds
11699 17:45:50.807570 <6>[ 86.679051] Freezing user space processes
11700 17:45:50.818948 <6>[ 86.684931] Freezing user space processes completed (elapsed 0.001 seconds)
11701 17:45:50.822324 <6>[ 86.692160] OOM killer disabled.
11702 17:45:50.825393 <6>[ 86.695641] Freezing remaining freezable tasks
11703 17:45:50.835437 <6>[ 86.701703] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11704 17:45:50.842431 <6>[ 86.709373] printk: Suspending console(s) (use no_console_suspend to debug)
11705 17:45:54.294859 <3>[ 89.934687] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11706 17:45:54.304910 <3>[ 89.934717] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11707 17:45:54.315075 <3>[ 89.934762] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11708 17:45:54.321736 <3>[ 89.934803] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11709 17:45:54.328766 <3>[ 89.935040] PM: Some devices failed to suspend, or early wake event detected
11710 17:45:54.331670 <6>[ 90.204682] OOM killer enabled.
11711 17:45:54.339897 <6>[ 90.208094] Restarting tasks ... done.
11712 17:45:54.347634 <5>[ 90.215601] random: crng reseeded on system resumption
11713 17:45:54.350003 <6>[ 90.222828] PM: suspend exit
11714 17:45:54.353412 rtcwake: write error
11715 17:45:54.360887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11716 17:45:54.361174 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11718 17:45:54.364225 rtcwake: assuming RTC uses UTC ...
11719 17:45:54.371437 rtcwake: wakeup from "freeze" using rtc0 at Wed Sep 13 17:45:59 2023
11720 17:45:54.383395 <6>[ 90.253486] PM: suspend entry (s2idle)
11721 17:45:54.386913 <6>[ 90.257549] Filesystems sync: 0.000 seconds
11722 17:45:54.390330 <6>[ 90.262668] Freezing user space processes
11723 17:45:54.402301 <6>[ 90.268591] Freezing user space processes completed (elapsed 0.001 seconds)
11724 17:45:54.405530 <6>[ 90.275822] OOM killer disabled.
11725 17:45:54.408790 <6>[ 90.279301] Freezing remaining freezable tasks
11726 17:45:54.418791 <6>[ 90.285320] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11727 17:45:54.425556 <6>[ 90.292996] printk: Suspending console(s) (use no_console_suspend to debug)
11728 17:45:57.878512 <3>[ 93.518751] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11729 17:45:57.888633 <3>[ 93.518785] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11730 17:45:57.898416 <3>[ 93.518835] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11731 17:45:57.905113 <3>[ 93.518874] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11732 17:45:57.911863 <3>[ 93.519146] PM: Some devices failed to suspend, or early wake event detected
11733 17:45:57.918089 <6>[ 93.788800] OOM killer enabled.
11734 17:45:57.921745 <6>[ 93.792211] Restarting tasks ... done.
11735 17:45:57.929417 <5>[ 93.799690] random: crng reseeded on system resumption
11736 17:45:57.933098 <6>[ 93.807071] PM: suspend exit
11737 17:45:57.936398 rtcwake: write error
11738 17:45:57.944724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11739 17:45:57.944814 + set +x
11740 17:45:57.945057 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11742 17:45:57.951643 <LAVA_SIGNAL_ENDRUN 0_sleep 11518283_1.5.2.3.1>
11743 17:45:57.951720 <LAVA_TEST_RUNNER EXIT>
11744 17:45:57.951952 Received signal: <ENDRUN> 0_sleep 11518283_1.5.2.3.1
11745 17:45:57.952031 Ending use of test pattern.
11746 17:45:57.952091 Ending test lava.0_sleep (11518283_1.5.2.3.1), duration 71.63
11748 17:45:57.952320 ok: lava_test_shell seems to have completed
11749 17:45:57.952512 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11750 17:45:57.952610 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11751 17:45:57.952704 end: 3 lava-test-retry (duration 00:01:12) [common]
11752 17:45:57.952790 start: 4 finalize (timeout 00:05:00) [common]
11753 17:45:57.952904 start: 4.1 power-off (timeout 00:00:30) [common]
11754 17:45:57.953112 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11755 17:45:58.029693 >> Command sent successfully.
11756 17:45:58.032201 Returned 0 in 0 seconds
11757 17:45:58.132600 end: 4.1 power-off (duration 00:00:00) [common]
11759 17:45:58.133056 start: 4.2 read-feedback (timeout 00:05:00) [common]
11760 17:45:58.133385 Listened to connection for namespace 'common' for up to 1s
11761 17:45:58.133712 Listened to connection for namespace 'common' for up to 1s
11762 17:45:59.134289 Finalising connection for namespace 'common'
11763 17:45:59.134506 Disconnecting from shell: Finalise
11764 17:45:59.134618 / #
11765 17:45:59.234978 end: 4.2 read-feedback (duration 00:00:01) [common]
11766 17:45:59.235146 end: 4 finalize (duration 00:00:01) [common]
11767 17:45:59.235263 Cleaning after the job
11768 17:45:59.235361 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/ramdisk
11769 17:45:59.248815 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/kernel
11770 17:45:59.272863 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/dtb
11771 17:45:59.273145 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518283/tftp-deploy-ox_jgt1_/modules
11772 17:45:59.280654 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11518283
11773 17:45:59.458771 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11518283
11774 17:45:59.459021 Job finished correctly