Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 68
1 17:42:39.171606 lava-dispatcher, installed at version: 2023.06
2 17:42:39.171867 start: 0 validate
3 17:42:39.172014 Start time: 2023-09-13 17:42:39.172006+00:00 (UTC)
4 17:42:39.172158 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:42:39.172312 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 17:42:39.422770 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:42:39.422990 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:42:39.672217 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:42:39.672391 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:42:39.920479 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:42:39.920648 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.52-cip5-29-g9fee06894d49%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 17:42:40.179602 validate duration: 1.01
14 17:42:40.180983 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:42:40.181528 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:42:40.182033 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:42:40.182732 Not decompressing ramdisk as can be used compressed.
18 17:42:40.183222 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 17:42:40.183619 saving as /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/ramdisk/rootfs.cpio.gz
20 17:42:40.184033 total size: 26246609 (25 MB)
21 17:42:40.189223 progress 0 % (0 MB)
22 17:42:40.213892 progress 5 % (1 MB)
23 17:42:40.225751 progress 10 % (2 MB)
24 17:42:40.234674 progress 15 % (3 MB)
25 17:42:40.242166 progress 20 % (5 MB)
26 17:42:40.249021 progress 25 % (6 MB)
27 17:42:40.255843 progress 30 % (7 MB)
28 17:42:40.262586 progress 35 % (8 MB)
29 17:42:40.269353 progress 40 % (10 MB)
30 17:42:40.276137 progress 45 % (11 MB)
31 17:42:40.282942 progress 50 % (12 MB)
32 17:42:40.289931 progress 55 % (13 MB)
33 17:42:40.296973 progress 60 % (15 MB)
34 17:42:40.303917 progress 65 % (16 MB)
35 17:42:40.310821 progress 70 % (17 MB)
36 17:42:40.317696 progress 75 % (18 MB)
37 17:42:40.324609 progress 80 % (20 MB)
38 17:42:40.331516 progress 85 % (21 MB)
39 17:42:40.338473 progress 90 % (22 MB)
40 17:42:40.345152 progress 95 % (23 MB)
41 17:42:40.352052 progress 100 % (25 MB)
42 17:42:40.352315 25 MB downloaded in 0.17 s (148.71 MB/s)
43 17:42:40.352473 end: 1.1.1 http-download (duration 00:00:00) [common]
45 17:42:40.352713 end: 1.1 download-retry (duration 00:00:00) [common]
46 17:42:40.352802 start: 1.2 download-retry (timeout 00:10:00) [common]
47 17:42:40.352886 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 17:42:40.353026 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 17:42:40.353100 saving as /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/kernel/Image
50 17:42:40.353163 total size: 49220096 (46 MB)
51 17:42:40.353225 No compression specified
52 17:42:40.354349 progress 0 % (0 MB)
53 17:42:40.367351 progress 5 % (2 MB)
54 17:42:40.380387 progress 10 % (4 MB)
55 17:42:40.393419 progress 15 % (7 MB)
56 17:42:40.406202 progress 20 % (9 MB)
57 17:42:40.418795 progress 25 % (11 MB)
58 17:42:40.431314 progress 30 % (14 MB)
59 17:42:40.444256 progress 35 % (16 MB)
60 17:42:40.457245 progress 40 % (18 MB)
61 17:42:40.470277 progress 45 % (21 MB)
62 17:42:40.483439 progress 50 % (23 MB)
63 17:42:40.496313 progress 55 % (25 MB)
64 17:42:40.509253 progress 60 % (28 MB)
65 17:42:40.521970 progress 65 % (30 MB)
66 17:42:40.535048 progress 70 % (32 MB)
67 17:42:40.548111 progress 75 % (35 MB)
68 17:42:40.560765 progress 80 % (37 MB)
69 17:42:40.573400 progress 85 % (39 MB)
70 17:42:40.585929 progress 90 % (42 MB)
71 17:42:40.598341 progress 95 % (44 MB)
72 17:42:40.610763 progress 100 % (46 MB)
73 17:42:40.610884 46 MB downloaded in 0.26 s (182.14 MB/s)
74 17:42:40.611036 end: 1.2.1 http-download (duration 00:00:00) [common]
76 17:42:40.611274 end: 1.2 download-retry (duration 00:00:00) [common]
77 17:42:40.611360 start: 1.3 download-retry (timeout 00:10:00) [common]
78 17:42:40.611452 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 17:42:40.611598 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 17:42:40.611675 saving as /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/dtb/mt8192-asurada-spherion-r0.dtb
81 17:42:40.611738 total size: 47278 (0 MB)
82 17:42:40.611800 No compression specified
83 17:42:40.612941 progress 69 % (0 MB)
84 17:42:40.613215 progress 100 % (0 MB)
85 17:42:40.613373 0 MB downloaded in 0.00 s (27.63 MB/s)
86 17:42:40.613495 end: 1.3.1 http-download (duration 00:00:00) [common]
88 17:42:40.613714 end: 1.3 download-retry (duration 00:00:00) [common]
89 17:42:40.613798 start: 1.4 download-retry (timeout 00:10:00) [common]
90 17:42:40.613880 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 17:42:40.613996 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.52-cip5-29-g9fee06894d49/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 17:42:40.614064 saving as /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/modules/modules.tar
93 17:42:40.614124 total size: 8628656 (8 MB)
94 17:42:40.614185 Using unxz to decompress xz
95 17:42:40.618179 progress 0 % (0 MB)
96 17:42:40.639863 progress 5 % (0 MB)
97 17:42:40.662200 progress 10 % (0 MB)
98 17:42:40.687711 progress 15 % (1 MB)
99 17:42:40.712570 progress 20 % (1 MB)
100 17:42:40.737833 progress 25 % (2 MB)
101 17:42:40.763827 progress 30 % (2 MB)
102 17:42:40.790346 progress 35 % (2 MB)
103 17:42:40.814691 progress 40 % (3 MB)
104 17:42:40.838782 progress 45 % (3 MB)
105 17:42:40.865300 progress 50 % (4 MB)
106 17:42:40.891140 progress 55 % (4 MB)
107 17:42:40.915982 progress 60 % (4 MB)
108 17:42:40.940680 progress 65 % (5 MB)
109 17:42:40.965982 progress 70 % (5 MB)
110 17:42:40.994060 progress 75 % (6 MB)
111 17:42:41.022115 progress 80 % (6 MB)
112 17:42:41.052066 progress 85 % (7 MB)
113 17:42:41.078911 progress 90 % (7 MB)
114 17:42:41.106540 progress 95 % (7 MB)
115 17:42:41.130839 progress 100 % (8 MB)
116 17:42:41.136179 8 MB downloaded in 0.52 s (15.76 MB/s)
117 17:42:41.136529 end: 1.4.1 http-download (duration 00:00:01) [common]
119 17:42:41.136955 end: 1.4 download-retry (duration 00:00:01) [common]
120 17:42:41.137101 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 17:42:41.137256 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 17:42:41.137390 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 17:42:41.137547 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 17:42:41.137873 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp
125 17:42:41.138083 makedir: /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin
126 17:42:41.138263 makedir: /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/tests
127 17:42:41.138421 makedir: /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/results
128 17:42:41.138591 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-add-keys
129 17:42:41.138818 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-add-sources
130 17:42:41.139032 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-background-process-start
131 17:42:41.139239 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-background-process-stop
132 17:42:41.139431 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-common-functions
133 17:42:41.139625 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-echo-ipv4
134 17:42:41.139825 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-install-packages
135 17:42:41.140017 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-installed-packages
136 17:42:41.140210 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-os-build
137 17:42:41.140403 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-probe-channel
138 17:42:41.140594 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-probe-ip
139 17:42:41.140786 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-target-ip
140 17:42:41.140979 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-target-mac
141 17:42:41.141169 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-target-storage
142 17:42:41.141371 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-case
143 17:42:41.141568 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-event
144 17:42:41.141759 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-feedback
145 17:42:41.141951 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-raise
146 17:42:41.142146 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-reference
147 17:42:41.142344 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-runner
148 17:42:41.142539 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-set
149 17:42:41.142734 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-test-shell
150 17:42:41.142933 Updating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-install-packages (oe)
151 17:42:41.143166 Updating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/bin/lava-installed-packages (oe)
152 17:42:41.143362 Creating /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/environment
153 17:42:41.143521 LAVA metadata
154 17:42:41.143653 - LAVA_JOB_ID=11518285
155 17:42:41.143763 - LAVA_DISPATCHER_IP=192.168.201.1
156 17:42:41.143918 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 17:42:41.144030 skipped lava-vland-overlay
158 17:42:41.144151 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 17:42:41.144285 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 17:42:41.144389 skipped lava-multinode-overlay
161 17:42:41.144512 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 17:42:41.144655 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 17:42:41.144795 Loading test definitions
164 17:42:41.144957 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 17:42:41.145091 Using /lava-11518285 at stage 0
166 17:42:41.145625 uuid=11518285_1.5.2.3.1 testdef=None
167 17:42:41.145770 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 17:42:41.145916 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 17:42:41.146791 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 17:42:41.147204 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 17:42:41.148244 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 17:42:41.148625 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 17:42:41.149554 runner path: /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11518285_1.5.2.3.1
176 17:42:41.149779 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 17:42:41.150123 Creating lava-test-runner.conf files
179 17:42:41.150228 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11518285/lava-overlay-22zru5fp/lava-11518285/0 for stage 0
180 17:42:41.150375 - 0_v4l2-compliance-mtk-vcodec-enc
181 17:42:41.150520 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 17:42:41.150663 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 17:42:41.160924 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 17:42:41.161096 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 17:42:41.161228 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 17:42:41.161367 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 17:42:41.161508 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 17:42:41.882876 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 17:42:41.883272 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 17:42:41.883395 extracting modules file /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11518285/extract-overlay-ramdisk-hpgxbq8k/ramdisk
191 17:42:42.120414 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 17:42:42.120625 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 17:42:42.120725 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518285/compress-overlay-nomxhvpp/overlay-1.5.2.4.tar.gz to ramdisk
194 17:42:42.120799 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11518285/compress-overlay-nomxhvpp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11518285/extract-overlay-ramdisk-hpgxbq8k/ramdisk
195 17:42:42.127757 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 17:42:42.127882 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 17:42:42.127977 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 17:42:42.128104 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 17:42:42.128182 Building ramdisk /var/lib/lava/dispatcher/tmp/11518285/extract-overlay-ramdisk-hpgxbq8k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11518285/extract-overlay-ramdisk-hpgxbq8k/ramdisk
200 17:42:42.713250 >> 228373 blocks
201 17:42:46.695486 rename /var/lib/lava/dispatcher/tmp/11518285/extract-overlay-ramdisk-hpgxbq8k/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/ramdisk/ramdisk.cpio.gz
202 17:42:46.695949 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 17:42:46.696081 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 17:42:46.696188 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 17:42:46.696315 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/kernel/Image'
206 17:43:00.285517 Returned 0 in 13 seconds
207 17:43:00.386174 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/kernel/image.itb
208 17:43:01.013553 output: FIT description: Kernel Image image with one or more FDT blobs
209 17:43:01.013955 output: Created: Wed Sep 13 18:43:00 2023
210 17:43:01.014069 output: Image 0 (kernel-1)
211 17:43:01.014170 output: Description:
212 17:43:01.014267 output: Created: Wed Sep 13 18:43:00 2023
213 17:43:01.014364 output: Type: Kernel Image
214 17:43:01.014458 output: Compression: lzma compressed
215 17:43:01.014551 output: Data Size: 11039249 Bytes = 10780.52 KiB = 10.53 MiB
216 17:43:01.014647 output: Architecture: AArch64
217 17:43:01.014739 output: OS: Linux
218 17:43:01.014830 output: Load Address: 0x00000000
219 17:43:01.014916 output: Entry Point: 0x00000000
220 17:43:01.015005 output: Hash algo: crc32
221 17:43:01.015095 output: Hash value: 2ab54ae9
222 17:43:01.015181 output: Image 1 (fdt-1)
223 17:43:01.015265 output: Description: mt8192-asurada-spherion-r0
224 17:43:01.015353 output: Created: Wed Sep 13 18:43:00 2023
225 17:43:01.015438 output: Type: Flat Device Tree
226 17:43:01.015523 output: Compression: uncompressed
227 17:43:01.015610 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 17:43:01.015706 output: Architecture: AArch64
229 17:43:01.015791 output: Hash algo: crc32
230 17:43:01.015854 output: Hash value: cc4352de
231 17:43:01.015910 output: Image 2 (ramdisk-1)
232 17:43:01.015965 output: Description: unavailable
233 17:43:01.016020 output: Created: Wed Sep 13 18:43:00 2023
234 17:43:01.016074 output: Type: RAMDisk Image
235 17:43:01.016133 output: Compression: Unknown Compression
236 17:43:01.016189 output: Data Size: 39348124 Bytes = 38425.90 KiB = 37.53 MiB
237 17:43:01.016244 output: Architecture: AArch64
238 17:43:01.016298 output: OS: Linux
239 17:43:01.016352 output: Load Address: unavailable
240 17:43:01.016406 output: Entry Point: unavailable
241 17:43:01.016490 output: Hash algo: crc32
242 17:43:01.016574 output: Hash value: 0d16ecea
243 17:43:01.016658 output: Default Configuration: 'conf-1'
244 17:43:01.016744 output: Configuration 0 (conf-1)
245 17:43:01.016823 output: Description: mt8192-asurada-spherion-r0
246 17:43:01.016884 output: Kernel: kernel-1
247 17:43:01.016940 output: Init Ramdisk: ramdisk-1
248 17:43:01.016994 output: FDT: fdt-1
249 17:43:01.017056 output: Loadables: kernel-1
250 17:43:01.017111 output:
251 17:43:01.017323 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 17:43:01.017425 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 17:43:01.017539 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 17:43:01.017669 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 17:43:01.017781 No LXC device requested
256 17:43:01.017898 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 17:43:01.018019 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 17:43:01.018133 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 17:43:01.018236 Checking files for TFTP limit of 4294967296 bytes.
260 17:43:01.018915 end: 1 tftp-deploy (duration 00:00:21) [common]
261 17:43:01.019050 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 17:43:01.019177 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 17:43:01.019347 substitutions:
264 17:43:01.019445 - {DTB}: 11518285/tftp-deploy-09441uta/dtb/mt8192-asurada-spherion-r0.dtb
265 17:43:01.019542 - {INITRD}: 11518285/tftp-deploy-09441uta/ramdisk/ramdisk.cpio.gz
266 17:43:01.019642 - {KERNEL}: 11518285/tftp-deploy-09441uta/kernel/Image
267 17:43:01.019711 - {LAVA_MAC}: None
268 17:43:01.019771 - {PRESEED_CONFIG}: None
269 17:43:01.019833 - {PRESEED_LOCAL}: None
270 17:43:01.019892 - {RAMDISK}: 11518285/tftp-deploy-09441uta/ramdisk/ramdisk.cpio.gz
271 17:43:01.019950 - {ROOT_PART}: None
272 17:43:01.020006 - {ROOT}: None
273 17:43:01.020064 - {SERVER_IP}: 192.168.201.1
274 17:43:01.020152 - {TEE}: None
275 17:43:01.020237 Parsed boot commands:
276 17:43:01.020324 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 17:43:01.020555 Parsed boot commands: tftpboot 192.168.201.1 11518285/tftp-deploy-09441uta/kernel/image.itb 11518285/tftp-deploy-09441uta/kernel/cmdline
278 17:43:01.020652 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 17:43:01.020746 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 17:43:01.020863 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 17:43:01.020966 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 17:43:01.021066 Not connected, no need to disconnect.
283 17:43:01.021147 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 17:43:01.021233 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 17:43:01.021311 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 17:43:01.025328 Setting prompt string to ['lava-test: # ']
287 17:43:01.025757 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 17:43:01.025903 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 17:43:01.026010 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 17:43:01.026110 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 17:43:01.026469 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 17:43:06.167391 >> Command sent successfully.
293 17:43:06.169943 Returned 0 in 5 seconds
294 17:43:06.270326 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 17:43:06.270647 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 17:43:06.270744 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 17:43:06.270832 Setting prompt string to 'Starting depthcharge on Spherion...'
299 17:43:06.270903 Changing prompt to 'Starting depthcharge on Spherion...'
300 17:43:06.270971 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 17:43:06.271236 [Enter `^Ec?' for help]
302 17:43:06.443985
303 17:43:06.444130
304 17:43:06.444201 F0: 102B 0000
305 17:43:06.444266
306 17:43:06.444364 F3: 1001 0000 [0200]
307 17:43:06.444423
308 17:43:06.447887 F3: 1001 0000
309 17:43:06.447972
310 17:43:06.448040 F7: 102D 0000
311 17:43:06.448102
312 17:43:06.448162 F1: 0000 0000
313 17:43:06.448221
314 17:43:06.451325 V0: 0000 0000 [0001]
315 17:43:06.451412
316 17:43:06.451479 00: 0007 8000
317 17:43:06.451545
318 17:43:06.455128 01: 0000 0000
319 17:43:06.455216
320 17:43:06.455283 BP: 0C00 0209 [0000]
321 17:43:06.455346
322 17:43:06.455406 G0: 1182 0000
323 17:43:06.455466
324 17:43:06.458746 EC: 0000 0021 [4000]
325 17:43:06.458830
326 17:43:06.462716 S7: 0000 0000 [0000]
327 17:43:06.462801
328 17:43:06.462868 CC: 0000 0000 [0001]
329 17:43:06.462929
330 17:43:06.462989 T0: 0000 0040 [010F]
331 17:43:06.466056
332 17:43:06.466140 Jump to BL
333 17:43:06.466207
334 17:43:06.489743
335 17:43:06.489842
336 17:43:06.489909
337 17:43:06.496807 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 17:43:06.500504 ARM64: Exception handlers installed.
339 17:43:06.504524 ARM64: Testing exception
340 17:43:06.507847 ARM64: Done test exception
341 17:43:06.515634 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 17:43:06.526420 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 17:43:06.530360 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 17:43:06.541327 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 17:43:06.548045 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 17:43:06.557895 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 17:43:06.568431 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 17:43:06.575572 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 17:43:06.592878 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 17:43:06.596477 WDT: Last reset was cold boot
351 17:43:06.599676 SPI1(PAD0) initialized at 2873684 Hz
352 17:43:06.603154 SPI5(PAD0) initialized at 992727 Hz
353 17:43:06.606448 VBOOT: Loading verstage.
354 17:43:06.612864 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 17:43:06.616538 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 17:43:06.619808 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 17:43:06.623259 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 17:43:06.630266 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 17:43:06.636769 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 17:43:06.647973 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 17:43:06.648065
362 17:43:06.648133
363 17:43:06.659021 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 17:43:06.662383 ARM64: Exception handlers installed.
365 17:43:06.662467 ARM64: Testing exception
366 17:43:06.665780 ARM64: Done test exception
367 17:43:06.669092 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 17:43:06.675570 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 17:43:06.689065 Probing TPM: . done!
370 17:43:06.689152 TPM ready after 0 ms
371 17:43:06.696447 Connected to device vid:did:rid of 1ae0:0028:00
372 17:43:06.702914 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 17:43:06.763143 Initialized TPM device CR50 revision 0
374 17:43:06.774821 tlcl_send_startup: Startup return code is 0
375 17:43:06.774915 TPM: setup succeeded
376 17:43:06.786362 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 17:43:06.795145 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 17:43:06.807523 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 17:43:06.816923 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 17:43:06.820814 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 17:43:06.824126 in-header: 03 07 00 00 08 00 00 00
382 17:43:06.828174 in-data: aa e4 47 04 13 02 00 00
383 17:43:06.832202 Chrome EC: UHEPI supported
384 17:43:06.835578 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 17:43:06.840211 in-header: 03 95 00 00 08 00 00 00
386 17:43:06.843632 in-data: 18 20 20 08 00 00 00 00
387 17:43:06.843755 Phase 1
388 17:43:06.846895 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 17:43:06.854789 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 17:43:06.862556 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 17:43:06.862645 Recovery requested (1009000e)
392 17:43:06.874409 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 17:43:06.878251 tlcl_extend: response is 0
394 17:43:06.887833 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 17:43:06.892761 tlcl_extend: response is 0
396 17:43:06.899883 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 17:43:06.919819 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 17:43:06.926379 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 17:43:06.926474
400 17:43:06.926541
401 17:43:06.936321 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 17:43:06.939809 ARM64: Exception handlers installed.
403 17:43:06.943001 ARM64: Testing exception
404 17:43:06.943084 ARM64: Done test exception
405 17:43:06.965558 pmic_efuse_setting: Set efuses in 11 msecs
406 17:43:06.968906 pmwrap_interface_init: Select PMIF_VLD_RDY
407 17:43:06.975396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 17:43:06.978732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 17:43:06.986414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 17:43:06.990079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 17:43:06.993804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 17:43:06.997245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 17:43:07.004761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 17:43:07.008307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 17:43:07.011958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 17:43:07.019857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 17:43:07.023514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 17:43:07.027139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 17:43:07.030476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 17:43:07.037706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 17:43:07.045077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 17:43:07.049166 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 17:43:07.056586 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 17:43:07.060452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 17:43:07.067870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 17:43:07.071871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 17:43:07.075698 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 17:43:07.083023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 17:43:07.087008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 17:43:07.094999 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 17:43:07.098336 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 17:43:07.105588 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 17:43:07.109211 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 17:43:07.112816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 17:43:07.120110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 17:43:07.123930 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 17:43:07.127820 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 17:43:07.135222 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 17:43:07.138604 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 17:43:07.146401 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 17:43:07.150104 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 17:43:07.154071 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 17:43:07.161772 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 17:43:07.165682 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 17:43:07.168942 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 17:43:07.172270 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 17:43:07.176248 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 17:43:07.183551 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 17:43:07.187459 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 17:43:07.191211 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 17:43:07.195166 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 17:43:07.198647 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 17:43:07.202671 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 17:43:07.209970 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 17:43:07.213665 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 17:43:07.216889 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 17:43:07.220694 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 17:43:07.228515 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 17:43:07.235856 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 17:43:07.239535 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 17:43:07.250816 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 17:43:07.258061 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 17:43:07.262349 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 17:43:07.266567 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 17:43:07.269641 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 17:43:07.278880 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x34
467 17:43:07.282073 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 17:43:07.287181 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 17:43:07.294591 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 17:43:07.303517 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 17:43:07.312867 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 17:43:07.322475 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 17:43:07.331419 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 17:43:07.340974 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 17:43:07.350408 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 17:43:07.361307 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 17:43:07.364667 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 17:43:07.368843 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 17:43:07.372818 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 17:43:07.380364 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 17:43:07.383792 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 17:43:07.387035 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 17:43:07.387122 ADC[4]: Raw value=906203 ID=7
484 17:43:07.390813 ADC[3]: Raw value=213441 ID=1
485 17:43:07.395023 RAM Code: 0x71
486 17:43:07.398588 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 17:43:07.402233 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 17:43:07.410116 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 17:43:07.417504 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 17:43:07.421484 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 17:43:07.425451 in-header: 03 07 00 00 08 00 00 00
492 17:43:07.428894 in-data: aa e4 47 04 13 02 00 00
493 17:43:07.429000 Chrome EC: UHEPI supported
494 17:43:07.435472 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 17:43:07.440000 in-header: 03 95 00 00 08 00 00 00
496 17:43:07.443872 in-data: 18 20 20 08 00 00 00 00
497 17:43:07.447585 MRC: failed to locate region type 0.
498 17:43:07.454510 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 17:43:07.458589 DRAM-K: Running full calibration
500 17:43:07.462038 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 17:43:07.466136 header.status = 0x0
502 17:43:07.469517 header.version = 0x6 (expected: 0x6)
503 17:43:07.473637 header.size = 0xd00 (expected: 0xd00)
504 17:43:07.473723 header.flags = 0x0
505 17:43:07.479959 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 17:43:07.498571 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 17:43:07.505298 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 17:43:07.509463 dram_init: ddr_geometry: 2
509 17:43:07.509549 [EMI] MDL number = 2
510 17:43:07.513100 [EMI] Get MDL freq = 0
511 17:43:07.513185 dram_init: ddr_type: 0
512 17:43:07.516337 is_discrete_lpddr4: 1
513 17:43:07.520610 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 17:43:07.520695
515 17:43:07.520761
516 17:43:07.520824 [Bian_co] ETT version 0.0.0.1
517 17:43:07.528143 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 17:43:07.528228
519 17:43:07.531888 dramc_set_vcore_voltage set vcore to 650000
520 17:43:07.531973 Read voltage for 800, 4
521 17:43:07.532042 Vio18 = 0
522 17:43:07.535967 Vcore = 650000
523 17:43:07.536052 Vdram = 0
524 17:43:07.536119 Vddq = 0
525 17:43:07.536181 Vmddr = 0
526 17:43:07.539631 dram_init: config_dvfs: 1
527 17:43:07.546851 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 17:43:07.550249 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 17:43:07.554199 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 17:43:07.557973 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 17:43:07.561485 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 17:43:07.564549 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 17:43:07.568005 MEM_TYPE=3, freq_sel=18
534 17:43:07.571395 sv_algorithm_assistance_LP4_1600
535 17:43:07.574810 ============ PULL DRAM RESETB DOWN ============
536 17:43:07.578140 ========== PULL DRAM RESETB DOWN end =========
537 17:43:07.585460 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 17:43:07.585549 ===================================
539 17:43:07.589496 LPDDR4 DRAM CONFIGURATION
540 17:43:07.593073 ===================================
541 17:43:07.596526 EX_ROW_EN[0] = 0x0
542 17:43:07.596611 EX_ROW_EN[1] = 0x0
543 17:43:07.600035 LP4Y_EN = 0x0
544 17:43:07.600119 WORK_FSP = 0x0
545 17:43:07.603546 WL = 0x2
546 17:43:07.603632 RL = 0x2
547 17:43:07.606803 BL = 0x2
548 17:43:07.606887 RPST = 0x0
549 17:43:07.610222 RD_PRE = 0x0
550 17:43:07.610306 WR_PRE = 0x1
551 17:43:07.613023 WR_PST = 0x0
552 17:43:07.613107 DBI_WR = 0x0
553 17:43:07.617075 DBI_RD = 0x0
554 17:43:07.617159 OTF = 0x1
555 17:43:07.619684 ===================================
556 17:43:07.623907 ===================================
557 17:43:07.623992 ANA top config
558 17:43:07.627877 ===================================
559 17:43:07.631019 DLL_ASYNC_EN = 0
560 17:43:07.634581 ALL_SLAVE_EN = 1
561 17:43:07.634704 NEW_RANK_MODE = 1
562 17:43:07.637802 DLL_IDLE_MODE = 1
563 17:43:07.641178 LP45_APHY_COMB_EN = 1
564 17:43:07.644477 TX_ODT_DIS = 1
565 17:43:07.648389 NEW_8X_MODE = 1
566 17:43:07.648472 ===================================
567 17:43:07.652008 ===================================
568 17:43:07.655433 data_rate = 1600
569 17:43:07.659076 CKR = 1
570 17:43:07.662462 DQ_P2S_RATIO = 8
571 17:43:07.665259 ===================================
572 17:43:07.668794 CA_P2S_RATIO = 8
573 17:43:07.668882 DQ_CA_OPEN = 0
574 17:43:07.672489 DQ_SEMI_OPEN = 0
575 17:43:07.675313 CA_SEMI_OPEN = 0
576 17:43:07.679131 CA_FULL_RATE = 0
577 17:43:07.682635 DQ_CKDIV4_EN = 1
578 17:43:07.685384 CA_CKDIV4_EN = 1
579 17:43:07.685495 CA_PREDIV_EN = 0
580 17:43:07.688864 PH8_DLY = 0
581 17:43:07.692067 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 17:43:07.695593 DQ_AAMCK_DIV = 4
583 17:43:07.698812 CA_AAMCK_DIV = 4
584 17:43:07.702275 CA_ADMCK_DIV = 4
585 17:43:07.702359 DQ_TRACK_CA_EN = 0
586 17:43:07.705727 CA_PICK = 800
587 17:43:07.709166 CA_MCKIO = 800
588 17:43:07.713340 MCKIO_SEMI = 0
589 17:43:07.716733 PLL_FREQ = 3068
590 17:43:07.716831 DQ_UI_PI_RATIO = 32
591 17:43:07.720208 CA_UI_PI_RATIO = 0
592 17:43:07.724162 ===================================
593 17:43:07.728203 ===================================
594 17:43:07.732142 memory_type:LPDDR4
595 17:43:07.732253 GP_NUM : 10
596 17:43:07.735607 SRAM_EN : 1
597 17:43:07.735752 MD32_EN : 0
598 17:43:07.739004 ===================================
599 17:43:07.742974 [ANA_INIT] >>>>>>>>>>>>>>
600 17:43:07.743064 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 17:43:07.746338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 17:43:07.749720 ===================================
603 17:43:07.753198 data_rate = 1600,PCW = 0X7600
604 17:43:07.756654 ===================================
605 17:43:07.760077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 17:43:07.766646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 17:43:07.773316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 17:43:07.776876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 17:43:07.780245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 17:43:07.783271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 17:43:07.786456 [ANA_INIT] flow start
612 17:43:07.786542 [ANA_INIT] PLL >>>>>>>>
613 17:43:07.789797 [ANA_INIT] PLL <<<<<<<<
614 17:43:07.793234 [ANA_INIT] MIDPI >>>>>>>>
615 17:43:07.793320 [ANA_INIT] MIDPI <<<<<<<<
616 17:43:07.796697 [ANA_INIT] DLL >>>>>>>>
617 17:43:07.799954 [ANA_INIT] flow end
618 17:43:07.803312 ============ LP4 DIFF to SE enter ============
619 17:43:07.806195 ============ LP4 DIFF to SE exit ============
620 17:43:07.809830 [ANA_INIT] <<<<<<<<<<<<<
621 17:43:07.813322 [Flow] Enable top DCM control >>>>>
622 17:43:07.816695 [Flow] Enable top DCM control <<<<<
623 17:43:07.820011 Enable DLL master slave shuffle
624 17:43:07.822996 ==============================================================
625 17:43:07.826447 Gating Mode config
626 17:43:07.833336 ==============================================================
627 17:43:07.833421 Config description:
628 17:43:07.843352 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 17:43:07.849984 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 17:43:07.853369 SELPH_MODE 0: By rank 1: By Phase
631 17:43:07.859503 ==============================================================
632 17:43:07.863013 GAT_TRACK_EN = 1
633 17:43:07.866523 RX_GATING_MODE = 2
634 17:43:07.869728 RX_GATING_TRACK_MODE = 2
635 17:43:07.873559 SELPH_MODE = 1
636 17:43:07.876927 PICG_EARLY_EN = 1
637 17:43:07.877012 VALID_LAT_VALUE = 1
638 17:43:07.883053 ==============================================================
639 17:43:07.886382 Enter into Gating configuration >>>>
640 17:43:07.889802 Exit from Gating configuration <<<<
641 17:43:07.893169 Enter into DVFS_PRE_config >>>>>
642 17:43:07.903772 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 17:43:07.906520 Exit from DVFS_PRE_config <<<<<
644 17:43:07.910407 Enter into PICG configuration >>>>
645 17:43:07.913792 Exit from PICG configuration <<<<
646 17:43:07.916941 [RX_INPUT] configuration >>>>>
647 17:43:07.920068 [RX_INPUT] configuration <<<<<
648 17:43:07.923725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 17:43:07.930391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 17:43:07.936988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 17:43:07.943546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 17:43:07.947151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 17:43:07.953864 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 17:43:07.957162 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 17:43:07.963623 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 17:43:07.966862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 17:43:07.970240 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 17:43:07.973477 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 17:43:07.980659 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 17:43:07.984083 ===================================
661 17:43:07.984175 LPDDR4 DRAM CONFIGURATION
662 17:43:07.986840 ===================================
663 17:43:07.990321 EX_ROW_EN[0] = 0x0
664 17:43:07.993741 EX_ROW_EN[1] = 0x0
665 17:43:07.993828 LP4Y_EN = 0x0
666 17:43:07.996956 WORK_FSP = 0x0
667 17:43:07.997042 WL = 0x2
668 17:43:08.000305 RL = 0x2
669 17:43:08.000391 BL = 0x2
670 17:43:08.003672 RPST = 0x0
671 17:43:08.003772 RD_PRE = 0x0
672 17:43:08.006950 WR_PRE = 0x1
673 17:43:08.007035 WR_PST = 0x0
674 17:43:08.010364 DBI_WR = 0x0
675 17:43:08.010449 DBI_RD = 0x0
676 17:43:08.013855 OTF = 0x1
677 17:43:08.017222 ===================================
678 17:43:08.020510 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 17:43:08.023985 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 17:43:08.030702 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 17:43:08.034045 ===================================
682 17:43:08.034139 LPDDR4 DRAM CONFIGURATION
683 17:43:08.037065 ===================================
684 17:43:08.040857 EX_ROW_EN[0] = 0x10
685 17:43:08.040944 EX_ROW_EN[1] = 0x0
686 17:43:08.043610 LP4Y_EN = 0x0
687 17:43:08.046912 WORK_FSP = 0x0
688 17:43:08.046998 WL = 0x2
689 17:43:08.050212 RL = 0x2
690 17:43:08.050298 BL = 0x2
691 17:43:08.053569 RPST = 0x0
692 17:43:08.053654 RD_PRE = 0x0
693 17:43:08.057255 WR_PRE = 0x1
694 17:43:08.057340 WR_PST = 0x0
695 17:43:08.060831 DBI_WR = 0x0
696 17:43:08.060916 DBI_RD = 0x0
697 17:43:08.063769 OTF = 0x1
698 17:43:08.066975 ===================================
699 17:43:08.070637 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 17:43:08.076258 nWR fixed to 40
701 17:43:08.079587 [ModeRegInit_LP4] CH0 RK0
702 17:43:08.079736 [ModeRegInit_LP4] CH0 RK1
703 17:43:08.082515 [ModeRegInit_LP4] CH1 RK0
704 17:43:08.086159 [ModeRegInit_LP4] CH1 RK1
705 17:43:08.086248 match AC timing 13
706 17:43:08.092496 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 17:43:08.095880 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 17:43:08.099326 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 17:43:08.106089 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 17:43:08.109330 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 17:43:08.109416 [EMI DOE] emi_dcm 0
712 17:43:08.116037 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 17:43:08.116136 ==
714 17:43:08.119326 Dram Type= 6, Freq= 0, CH_0, rank 0
715 17:43:08.122718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 17:43:08.122803 ==
717 17:43:08.129622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 17:43:08.135592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 17:43:08.143677 [CA 0] Center 36 (6~67) winsize 62
720 17:43:08.146358 [CA 1] Center 36 (6~67) winsize 62
721 17:43:08.150359 [CA 2] Center 34 (4~65) winsize 62
722 17:43:08.153709 [CA 3] Center 33 (3~64) winsize 62
723 17:43:08.157007 [CA 4] Center 33 (3~64) winsize 62
724 17:43:08.160518 [CA 5] Center 32 (3~62) winsize 60
725 17:43:08.160604
726 17:43:08.163778 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 17:43:08.163864
728 17:43:08.166971 [CATrainingPosCal] consider 1 rank data
729 17:43:08.170245 u2DelayCellTimex100 = 270/100 ps
730 17:43:08.173484 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 17:43:08.176883 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 17:43:08.183527 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 17:43:08.186955 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 17:43:08.190323 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 17:43:08.193644 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 17:43:08.193732
737 17:43:08.197063 CA PerBit enable=1, Macro0, CA PI delay=32
738 17:43:08.197148
739 17:43:08.200129 [CBTSetCACLKResult] CA Dly = 32
740 17:43:08.200214 CS Dly: 4 (0~35)
741 17:43:08.200282 ==
742 17:43:08.203764 Dram Type= 6, Freq= 0, CH_0, rank 1
743 17:43:08.210367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 17:43:08.210453 ==
745 17:43:08.213543 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 17:43:08.220150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 17:43:08.229545 [CA 0] Center 36 (6~67) winsize 62
748 17:43:08.232838 [CA 1] Center 36 (6~67) winsize 62
749 17:43:08.236228 [CA 2] Center 34 (4~65) winsize 62
750 17:43:08.239529 [CA 3] Center 34 (4~65) winsize 62
751 17:43:08.242818 [CA 4] Center 32 (2~63) winsize 62
752 17:43:08.246220 [CA 5] Center 32 (2~63) winsize 62
753 17:43:08.246305
754 17:43:08.249557 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 17:43:08.249643
756 17:43:08.253014 [CATrainingPosCal] consider 2 rank data
757 17:43:08.256137 u2DelayCellTimex100 = 270/100 ps
758 17:43:08.259515 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 17:43:08.262878 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 17:43:08.269646 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 17:43:08.272957 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 17:43:08.276235 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 17:43:08.279625 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 17:43:08.279761
765 17:43:08.283397 CA PerBit enable=1, Macro0, CA PI delay=32
766 17:43:08.283482
767 17:43:08.286496 [CBTSetCACLKResult] CA Dly = 32
768 17:43:08.286582 CS Dly: 5 (0~37)
769 17:43:08.286649
770 17:43:08.290303 ----->DramcWriteLeveling(PI) begin...
771 17:43:08.290390 ==
772 17:43:08.293829 Dram Type= 6, Freq= 0, CH_0, rank 0
773 17:43:08.297985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 17:43:08.298070 ==
775 17:43:08.301352 Write leveling (Byte 0): 32 => 32
776 17:43:08.305397 Write leveling (Byte 1): 32 => 32
777 17:43:08.308758 DramcWriteLeveling(PI) end<-----
778 17:43:08.308844
779 17:43:08.308910 ==
780 17:43:08.312228 Dram Type= 6, Freq= 0, CH_0, rank 0
781 17:43:08.315460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 17:43:08.315545 ==
783 17:43:08.319295 [Gating] SW mode calibration
784 17:43:08.326504 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 17:43:08.329623 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 17:43:08.336539 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 17:43:08.339532 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 17:43:08.342871 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 17:43:08.349478 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 17:43:08.352889 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 17:43:08.356427 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 17:43:08.362861 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 17:43:08.366167 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 17:43:08.369622 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 17:43:08.376090 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 17:43:08.379513 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 17:43:08.382995 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 17:43:08.389567 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 17:43:08.392658 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 17:43:08.396350 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 17:43:08.403151 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 17:43:08.405908 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 17:43:08.409259 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 17:43:08.416191 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 17:43:08.419400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 17:43:08.422661 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 17:43:08.426188 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 17:43:08.432809 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 17:43:08.436107 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 17:43:08.439530 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 17:43:08.446312 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 17:43:08.449476 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
813 17:43:08.452763 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
814 17:43:08.459847 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 17:43:08.463271 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 17:43:08.466632 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 17:43:08.473388 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 17:43:08.476486 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 17:43:08.479798 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 17:43:08.486756 0 10 8 | B1->B0 | 3131 2727 | 0 0 | (0 1) (0 0)
821 17:43:08.489729 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 17:43:08.493094 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 17:43:08.496390 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 17:43:08.503469 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 17:43:08.506604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 17:43:08.509866 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 17:43:08.516518 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
828 17:43:08.519919 0 11 8 | B1->B0 | 2b2b 3939 | 0 1 | (0 0) (0 0)
829 17:43:08.523056 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
830 17:43:08.529765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 17:43:08.533032 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 17:43:08.536375 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 17:43:08.542970 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 17:43:08.546381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 17:43:08.549752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 17:43:08.556796 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 17:43:08.560152 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 17:43:08.563258 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 17:43:08.570100 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 17:43:08.573477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 17:43:08.576972 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 17:43:08.580303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 17:43:08.586586 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 17:43:08.590355 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 17:43:08.593387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 17:43:08.600008 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 17:43:08.603297 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 17:43:08.606811 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 17:43:08.613158 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 17:43:08.616879 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 17:43:08.619854 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 17:43:08.627126 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 17:43:08.627211 Total UI for P1: 0, mck2ui 16
854 17:43:08.633689 best dqsien dly found for B0: ( 0, 14, 4)
855 17:43:08.637035 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 17:43:08.640332 Total UI for P1: 0, mck2ui 16
857 17:43:08.644381 best dqsien dly found for B1: ( 0, 14, 10)
858 17:43:08.647903 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 17:43:08.651280 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 17:43:08.651364
861 17:43:08.654728 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 17:43:08.657923 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 17:43:08.661230 [Gating] SW calibration Done
864 17:43:08.661314 ==
865 17:43:08.664572 Dram Type= 6, Freq= 0, CH_0, rank 0
866 17:43:08.667915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 17:43:08.668000 ==
868 17:43:08.671087 RX Vref Scan: 0
869 17:43:08.671170
870 17:43:08.671237 RX Vref 0 -> 0, step: 1
871 17:43:08.671300
872 17:43:08.674472 RX Delay -130 -> 252, step: 16
873 17:43:08.677854 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 17:43:08.684763 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 17:43:08.688101 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 17:43:08.691448 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 17:43:08.694878 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 17:43:08.698186 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 17:43:08.701341 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 17:43:08.708100 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 17:43:08.711450 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 17:43:08.714801 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 17:43:08.718172 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 17:43:08.721369 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 17:43:08.727716 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 17:43:08.731229 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 17:43:08.734478 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 17:43:08.737852 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 17:43:08.737936 ==
890 17:43:08.741478 Dram Type= 6, Freq= 0, CH_0, rank 0
891 17:43:08.747964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 17:43:08.748049 ==
893 17:43:08.748116 DQS Delay:
894 17:43:08.751289 DQS0 = 0, DQS1 = 0
895 17:43:08.751372 DQM Delay:
896 17:43:08.751439 DQM0 = 89, DQM1 = 82
897 17:43:08.754473 DQ Delay:
898 17:43:08.757912 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 17:43:08.761179 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 17:43:08.765038 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
901 17:43:08.768281 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
902 17:43:08.768365
903 17:43:08.768430
904 17:43:08.768491 ==
905 17:43:08.771556 Dram Type= 6, Freq= 0, CH_0, rank 0
906 17:43:08.774930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 17:43:08.775013 ==
908 17:43:08.775080
909 17:43:08.775141
910 17:43:08.778351 TX Vref Scan disable
911 17:43:08.778435 == TX Byte 0 ==
912 17:43:08.784427 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 17:43:08.787874 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 17:43:08.787958 == TX Byte 1 ==
915 17:43:08.794813 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 17:43:08.798156 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 17:43:08.798241 ==
918 17:43:08.801331 Dram Type= 6, Freq= 0, CH_0, rank 0
919 17:43:08.804601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 17:43:08.804686 ==
921 17:43:08.818844 TX Vref=22, minBit 8, minWin=27, winSum=444
922 17:43:08.822283 TX Vref=24, minBit 8, minWin=27, winSum=448
923 17:43:08.824933 TX Vref=26, minBit 0, minWin=28, winSum=455
924 17:43:08.828412 TX Vref=28, minBit 0, minWin=28, winSum=455
925 17:43:08.831880 TX Vref=30, minBit 11, minWin=27, winSum=456
926 17:43:08.835244 TX Vref=32, minBit 6, minWin=28, winSum=456
927 17:43:08.841738 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 32
928 17:43:08.841850
929 17:43:08.845777 Final TX Range 1 Vref 32
930 17:43:08.845861
931 17:43:08.845935 ==
932 17:43:08.848569 Dram Type= 6, Freq= 0, CH_0, rank 0
933 17:43:08.851933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 17:43:08.852017 ==
935 17:43:08.852087
936 17:43:08.855558
937 17:43:08.855706 TX Vref Scan disable
938 17:43:08.858744 == TX Byte 0 ==
939 17:43:08.861786 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 17:43:08.864989 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 17:43:08.868710 == TX Byte 1 ==
942 17:43:08.871846 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 17:43:08.875239 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 17:43:08.878713
945 17:43:08.878798 [DATLAT]
946 17:43:08.878866 Freq=800, CH0 RK0
947 17:43:08.878957
948 17:43:08.881849 DATLAT Default: 0xa
949 17:43:08.881960 0, 0xFFFF, sum = 0
950 17:43:08.885044 1, 0xFFFF, sum = 0
951 17:43:08.885132 2, 0xFFFF, sum = 0
952 17:43:08.888452 3, 0xFFFF, sum = 0
953 17:43:08.888540 4, 0xFFFF, sum = 0
954 17:43:08.891771 5, 0xFFFF, sum = 0
955 17:43:08.891870 6, 0xFFFF, sum = 0
956 17:43:08.895042 7, 0xFFFF, sum = 0
957 17:43:08.898464 8, 0xFFFF, sum = 0
958 17:43:08.898556 9, 0x0, sum = 1
959 17:43:08.898641 10, 0x0, sum = 2
960 17:43:08.901752 11, 0x0, sum = 3
961 17:43:08.901840 12, 0x0, sum = 4
962 17:43:08.905213 best_step = 10
963 17:43:08.905295
964 17:43:08.905367 ==
965 17:43:08.908584 Dram Type= 6, Freq= 0, CH_0, rank 0
966 17:43:08.911946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 17:43:08.912051 ==
968 17:43:08.915521 RX Vref Scan: 1
969 17:43:08.915654
970 17:43:08.915768 Set Vref Range= 32 -> 127
971 17:43:08.915859
972 17:43:08.918635 RX Vref 32 -> 127, step: 1
973 17:43:08.918717
974 17:43:08.922200 RX Delay -95 -> 252, step: 8
975 17:43:08.922284
976 17:43:08.925579 Set Vref, RX VrefLevel [Byte0]: 32
977 17:43:08.928866 [Byte1]: 32
978 17:43:08.928949
979 17:43:08.932269 Set Vref, RX VrefLevel [Byte0]: 33
980 17:43:08.935603 [Byte1]: 33
981 17:43:08.938990
982 17:43:08.939072 Set Vref, RX VrefLevel [Byte0]: 34
983 17:43:08.942569 [Byte1]: 34
984 17:43:08.946532
985 17:43:08.949784 Set Vref, RX VrefLevel [Byte0]: 35
986 17:43:08.949867 [Byte1]: 35
987 17:43:08.954481
988 17:43:08.954566 Set Vref, RX VrefLevel [Byte0]: 36
989 17:43:08.957918 [Byte1]: 36
990 17:43:08.961947
991 17:43:08.962029 Set Vref, RX VrefLevel [Byte0]: 37
992 17:43:08.965524 [Byte1]: 37
993 17:43:08.970171
994 17:43:08.970254 Set Vref, RX VrefLevel [Byte0]: 38
995 17:43:08.973393 [Byte1]: 38
996 17:43:08.976914
997 17:43:08.977033 Set Vref, RX VrefLevel [Byte0]: 39
998 17:43:08.980532 [Byte1]: 39
999 17:43:08.984782
1000 17:43:08.984866 Set Vref, RX VrefLevel [Byte0]: 40
1001 17:43:08.987868 [Byte1]: 40
1002 17:43:08.992393
1003 17:43:08.992478 Set Vref, RX VrefLevel [Byte0]: 41
1004 17:43:08.995349 [Byte1]: 41
1005 17:43:08.999346
1006 17:43:08.999443 Set Vref, RX VrefLevel [Byte0]: 42
1007 17:43:09.002765 [Byte1]: 42
1008 17:43:09.007016
1009 17:43:09.007100 Set Vref, RX VrefLevel [Byte0]: 43
1010 17:43:09.010406 [Byte1]: 43
1011 17:43:09.014579
1012 17:43:09.014663 Set Vref, RX VrefLevel [Byte0]: 44
1013 17:43:09.017819 [Byte1]: 44
1014 17:43:09.022524
1015 17:43:09.022607 Set Vref, RX VrefLevel [Byte0]: 45
1016 17:43:09.025905 [Byte1]: 45
1017 17:43:09.030169
1018 17:43:09.030252 Set Vref, RX VrefLevel [Byte0]: 46
1019 17:43:09.033315 [Byte1]: 46
1020 17:43:09.037278
1021 17:43:09.037360 Set Vref, RX VrefLevel [Byte0]: 47
1022 17:43:09.040701 [Byte1]: 47
1023 17:43:09.045546
1024 17:43:09.045630 Set Vref, RX VrefLevel [Byte0]: 48
1025 17:43:09.048938 [Byte1]: 48
1026 17:43:09.052856
1027 17:43:09.052938 Set Vref, RX VrefLevel [Byte0]: 49
1028 17:43:09.056145 [Byte1]: 49
1029 17:43:09.060810
1030 17:43:09.060895 Set Vref, RX VrefLevel [Byte0]: 50
1031 17:43:09.063562 [Byte1]: 50
1032 17:43:09.068323
1033 17:43:09.068404 Set Vref, RX VrefLevel [Byte0]: 51
1034 17:43:09.071075 [Byte1]: 51
1035 17:43:09.075299
1036 17:43:09.075380 Set Vref, RX VrefLevel [Byte0]: 52
1037 17:43:09.078673 [Byte1]: 52
1038 17:43:09.083320
1039 17:43:09.083401 Set Vref, RX VrefLevel [Byte0]: 53
1040 17:43:09.086723 [Byte1]: 53
1041 17:43:09.090792
1042 17:43:09.090878 Set Vref, RX VrefLevel [Byte0]: 54
1043 17:43:09.094105 [Byte1]: 54
1044 17:43:09.098051
1045 17:43:09.098159 Set Vref, RX VrefLevel [Byte0]: 55
1046 17:43:09.102023 [Byte1]: 55
1047 17:43:09.105826
1048 17:43:09.105910 Set Vref, RX VrefLevel [Byte0]: 56
1049 17:43:09.109301 [Byte1]: 56
1050 17:43:09.113463
1051 17:43:09.113546 Set Vref, RX VrefLevel [Byte0]: 57
1052 17:43:09.116762 [Byte1]: 57
1053 17:43:09.121163
1054 17:43:09.121247 Set Vref, RX VrefLevel [Byte0]: 58
1055 17:43:09.124212 [Byte1]: 58
1056 17:43:09.128733
1057 17:43:09.128816 Set Vref, RX VrefLevel [Byte0]: 59
1058 17:43:09.132063 [Byte1]: 59
1059 17:43:09.136115
1060 17:43:09.136198 Set Vref, RX VrefLevel [Byte0]: 60
1061 17:43:09.139583 [Byte1]: 60
1062 17:43:09.144267
1063 17:43:09.144376 Set Vref, RX VrefLevel [Byte0]: 61
1064 17:43:09.147443 [Byte1]: 61
1065 17:43:09.151655
1066 17:43:09.151738 Set Vref, RX VrefLevel [Byte0]: 62
1067 17:43:09.154936 [Byte1]: 62
1068 17:43:09.158938
1069 17:43:09.159021 Set Vref, RX VrefLevel [Byte0]: 63
1070 17:43:09.162298 [Byte1]: 63
1071 17:43:09.166980
1072 17:43:09.167066 Set Vref, RX VrefLevel [Byte0]: 64
1073 17:43:09.169737 [Byte1]: 64
1074 17:43:09.174638
1075 17:43:09.174719 Set Vref, RX VrefLevel [Byte0]: 65
1076 17:43:09.177897 [Byte1]: 65
1077 17:43:09.181965
1078 17:43:09.182046 Set Vref, RX VrefLevel [Byte0]: 66
1079 17:43:09.185369 [Byte1]: 66
1080 17:43:09.189485
1081 17:43:09.189566 Set Vref, RX VrefLevel [Byte0]: 67
1082 17:43:09.192933 [Byte1]: 67
1083 17:43:09.196876
1084 17:43:09.196961 Set Vref, RX VrefLevel [Byte0]: 68
1085 17:43:09.200821 [Byte1]: 68
1086 17:43:09.204697
1087 17:43:09.204782 Set Vref, RX VrefLevel [Byte0]: 69
1088 17:43:09.208125 [Byte1]: 69
1089 17:43:09.212241
1090 17:43:09.212323 Set Vref, RX VrefLevel [Byte0]: 70
1091 17:43:09.215595 [Byte1]: 70
1092 17:43:09.219766
1093 17:43:09.219848 Set Vref, RX VrefLevel [Byte0]: 71
1094 17:43:09.223181 [Byte1]: 71
1095 17:43:09.227626
1096 17:43:09.227749 Set Vref, RX VrefLevel [Byte0]: 72
1097 17:43:09.230974 [Byte1]: 72
1098 17:43:09.235596
1099 17:43:09.235688 Set Vref, RX VrefLevel [Byte0]: 73
1100 17:43:09.238696 [Byte1]: 73
1101 17:43:09.242941
1102 17:43:09.243022 Set Vref, RX VrefLevel [Byte0]: 74
1103 17:43:09.246318 [Byte1]: 74
1104 17:43:09.250385
1105 17:43:09.250467 Set Vref, RX VrefLevel [Byte0]: 75
1106 17:43:09.254017 [Byte1]: 75
1107 17:43:09.258062
1108 17:43:09.258144 Final RX Vref Byte 0 = 59 to rank0
1109 17:43:09.261431 Final RX Vref Byte 1 = 56 to rank0
1110 17:43:09.264604 Final RX Vref Byte 0 = 59 to rank1
1111 17:43:09.268313 Final RX Vref Byte 1 = 56 to rank1==
1112 17:43:09.271464 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 17:43:09.278000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 17:43:09.278096 ==
1115 17:43:09.278171 DQS Delay:
1116 17:43:09.278234 DQS0 = 0, DQS1 = 0
1117 17:43:09.281388 DQM Delay:
1118 17:43:09.281469 DQM0 = 92, DQM1 = 85
1119 17:43:09.284610 DQ Delay:
1120 17:43:09.287797 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1121 17:43:09.287880 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1122 17:43:09.291187 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1123 17:43:09.297842 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1124 17:43:09.297924
1125 17:43:09.297990
1126 17:43:09.310214 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1127 17:43:09.310317 CH0 RK0: MR19=606, MR18=4C42
1128 17:43:09.314332 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1129 17:43:09.314415
1130 17:43:09.317654 ----->DramcWriteLeveling(PI) begin...
1131 17:43:09.317740 ==
1132 17:43:09.321096 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 17:43:09.324510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 17:43:09.324593 ==
1135 17:43:09.327897 Write leveling (Byte 0): 35 => 35
1136 17:43:09.331198 Write leveling (Byte 1): 30 => 30
1137 17:43:09.335001 DramcWriteLeveling(PI) end<-----
1138 17:43:09.335082
1139 17:43:09.335147 ==
1140 17:43:09.338203 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 17:43:09.341350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 17:43:09.341432 ==
1143 17:43:09.344548 [Gating] SW mode calibration
1144 17:43:09.351140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 17:43:09.358216 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 17:43:09.361542 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 17:43:09.405400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1148 17:43:09.405720 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1149 17:43:09.405797 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 17:43:09.405862 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 17:43:09.405935 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 17:43:09.406522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 17:43:09.407131 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 17:43:09.407378 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 17:43:09.407445 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 17:43:09.407516 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 17:43:09.449437 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 17:43:09.450141 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 17:43:09.450738 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 17:43:09.450821 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 17:43:09.451068 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 17:43:09.451135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 17:43:09.451196 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1164 17:43:09.451255 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1165 17:43:09.451313 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 17:43:09.451381 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 17:43:09.461117 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 17:43:09.461385 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 17:43:09.464891 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 17:43:09.468185 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 17:43:09.471607 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 17:43:09.474837 0 9 8 | B1->B0 | 3232 2a2a | 1 1 | (0 0) (0 0)
1173 17:43:09.481071 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 17:43:09.484680 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 17:43:09.488029 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 17:43:09.494660 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 17:43:09.498421 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 17:43:09.501655 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 17:43:09.507958 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 0)
1180 17:43:09.511246 0 10 8 | B1->B0 | 2525 2b2b | 1 1 | (1 1) (1 1)
1181 17:43:09.514451 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 17:43:09.518288 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 17:43:09.524639 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 17:43:09.527929 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 17:43:09.531295 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 17:43:09.538780 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 17:43:09.542832 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 17:43:09.546588 0 11 8 | B1->B0 | 3c3c 3838 | 0 1 | (0 0) (0 0)
1189 17:43:09.550685 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 17:43:09.553886 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 17:43:09.560574 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 17:43:09.564583 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 17:43:09.567707 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 17:43:09.570688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 17:43:09.577864 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 17:43:09.581193 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1197 17:43:09.584600 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 17:43:09.590865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 17:43:09.594642 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 17:43:09.597940 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 17:43:09.604324 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 17:43:09.607626 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 17:43:09.611033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 17:43:09.617697 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 17:43:09.620954 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 17:43:09.624271 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 17:43:09.631060 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 17:43:09.634332 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 17:43:09.637642 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 17:43:09.640880 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 17:43:09.648079 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1212 17:43:09.650871 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1213 17:43:09.654197 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 17:43:09.657899 Total UI for P1: 0, mck2ui 16
1215 17:43:09.661032 best dqsien dly found for B0: ( 0, 14, 6)
1216 17:43:09.664537 Total UI for P1: 0, mck2ui 16
1217 17:43:09.667712 best dqsien dly found for B1: ( 0, 14, 8)
1218 17:43:09.671532 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1219 17:43:09.674783 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1220 17:43:09.674866
1221 17:43:09.680972 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1222 17:43:09.684369 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1223 17:43:09.684453 [Gating] SW calibration Done
1224 17:43:09.687685 ==
1225 17:43:09.687769 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 17:43:09.694347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 17:43:09.694434 ==
1228 17:43:09.694502 RX Vref Scan: 0
1229 17:43:09.694563
1230 17:43:09.698072 RX Vref 0 -> 0, step: 1
1231 17:43:09.698155
1232 17:43:09.701007 RX Delay -130 -> 252, step: 16
1233 17:43:09.704612 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1234 17:43:09.707773 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1235 17:43:09.711493 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1236 17:43:09.718086 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1237 17:43:09.721359 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1238 17:43:09.724678 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1239 17:43:09.727980 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1240 17:43:09.731304 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1241 17:43:09.738059 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1242 17:43:09.741450 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1243 17:43:09.744736 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1244 17:43:09.748122 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1245 17:43:09.752018 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1246 17:43:09.758545 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1247 17:43:09.761777 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1248 17:43:09.765064 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1249 17:43:09.765149 ==
1250 17:43:09.768429 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 17:43:09.771436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1252 17:43:09.771520 ==
1253 17:43:09.774637 DQS Delay:
1254 17:43:09.774720 DQS0 = 0, DQS1 = 0
1255 17:43:09.777974 DQM Delay:
1256 17:43:09.778057 DQM0 = 92, DQM1 = 82
1257 17:43:09.778123 DQ Delay:
1258 17:43:09.781289 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1259 17:43:09.784664 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1260 17:43:09.788295 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1261 17:43:09.791945 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1262 17:43:09.792033
1263 17:43:09.792099
1264 17:43:09.792160 ==
1265 17:43:09.794747 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 17:43:09.801513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 17:43:09.801600 ==
1268 17:43:09.801666
1269 17:43:09.801726
1270 17:43:09.801784 TX Vref Scan disable
1271 17:43:09.805650 == TX Byte 0 ==
1272 17:43:09.808564 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1273 17:43:09.815627 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1274 17:43:09.815750 == TX Byte 1 ==
1275 17:43:09.818670 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1276 17:43:09.822266 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1277 17:43:09.825378 ==
1278 17:43:09.828542 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 17:43:09.831846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 17:43:09.831930 ==
1281 17:43:09.845156 TX Vref=22, minBit 12, minWin=27, winSum=450
1282 17:43:09.848550 TX Vref=24, minBit 10, minWin=27, winSum=450
1283 17:43:09.851882 TX Vref=26, minBit 1, minWin=28, winSum=453
1284 17:43:09.855266 TX Vref=28, minBit 7, minWin=28, winSum=460
1285 17:43:09.858461 TX Vref=30, minBit 1, minWin=28, winSum=458
1286 17:43:09.865104 TX Vref=32, minBit 2, minWin=28, winSum=456
1287 17:43:09.868426 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 28
1288 17:43:09.868510
1289 17:43:09.871755 Final TX Range 1 Vref 28
1290 17:43:09.871839
1291 17:43:09.871904 ==
1292 17:43:09.875086 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 17:43:09.878415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 17:43:09.878496 ==
1295 17:43:09.878560
1296 17:43:09.881656
1297 17:43:09.881737 TX Vref Scan disable
1298 17:43:09.885077 == TX Byte 0 ==
1299 17:43:09.888361 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1300 17:43:09.891608 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1301 17:43:09.895612 == TX Byte 1 ==
1302 17:43:09.898827 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1303 17:43:09.902174 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1304 17:43:09.905405
1305 17:43:09.905503 [DATLAT]
1306 17:43:09.905592 Freq=800, CH0 RK1
1307 17:43:09.905680
1308 17:43:09.908405 DATLAT Default: 0xa
1309 17:43:09.908486 0, 0xFFFF, sum = 0
1310 17:43:09.911856 1, 0xFFFF, sum = 0
1311 17:43:09.911943 2, 0xFFFF, sum = 0
1312 17:43:09.915034 3, 0xFFFF, sum = 0
1313 17:43:09.915119 4, 0xFFFF, sum = 0
1314 17:43:09.918917 5, 0xFFFF, sum = 0
1315 17:43:09.919005 6, 0xFFFF, sum = 0
1316 17:43:09.922111 7, 0xFFFF, sum = 0
1317 17:43:09.925239 8, 0xFFFF, sum = 0
1318 17:43:09.925321 9, 0x0, sum = 1
1319 17:43:09.925392 10, 0x0, sum = 2
1320 17:43:09.928643 11, 0x0, sum = 3
1321 17:43:09.928752 12, 0x0, sum = 4
1322 17:43:09.931823 best_step = 10
1323 17:43:09.931904
1324 17:43:09.931968 ==
1325 17:43:09.935050 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 17:43:09.938505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 17:43:09.938588 ==
1328 17:43:09.942013 RX Vref Scan: 0
1329 17:43:09.942093
1330 17:43:09.942170 RX Vref 0 -> 0, step: 1
1331 17:43:09.942233
1332 17:43:09.945136 RX Delay -95 -> 252, step: 8
1333 17:43:09.951981 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1334 17:43:09.955155 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1335 17:43:09.958841 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1336 17:43:09.962072 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1337 17:43:09.965417 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1338 17:43:09.972060 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1339 17:43:09.975334 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1340 17:43:09.978638 iDelay=209, Bit 7, Center 104 (1 ~ 208) 208
1341 17:43:09.981976 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1342 17:43:09.985244 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1343 17:43:09.988589 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1344 17:43:09.995214 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1345 17:43:09.999054 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1346 17:43:10.002366 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1347 17:43:10.005674 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1348 17:43:10.012338 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1349 17:43:10.012446 ==
1350 17:43:10.015738 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 17:43:10.019120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 17:43:10.019202 ==
1353 17:43:10.019268 DQS Delay:
1354 17:43:10.022286 DQS0 = 0, DQS1 = 0
1355 17:43:10.022368 DQM Delay:
1356 17:43:10.025654 DQM0 = 93, DQM1 = 84
1357 17:43:10.025736 DQ Delay:
1358 17:43:10.029047 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1359 17:43:10.032315 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =104
1360 17:43:10.035494 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1361 17:43:10.038770 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1362 17:43:10.038851
1363 17:43:10.038916
1364 17:43:10.045802 [DQSOSCAuto] RK1, (LSB)MR18= 0x4313, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1365 17:43:10.049025 CH0 RK1: MR19=606, MR18=4313
1366 17:43:10.055128 CH0_RK1: MR19=0x606, MR18=0x4313, DQSOSC=393, MR23=63, INC=95, DEC=63
1367 17:43:10.058628 [RxdqsGatingPostProcess] freq 800
1368 17:43:10.065494 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 17:43:10.065577 Pre-setting of DQS Precalculation
1370 17:43:10.072208 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1371 17:43:10.072289 ==
1372 17:43:10.075492 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 17:43:10.078803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 17:43:10.078885 ==
1375 17:43:10.085742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 17:43:10.092355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 17:43:10.100241 [CA 0] Center 36 (6~67) winsize 62
1378 17:43:10.103978 [CA 1] Center 36 (6~67) winsize 62
1379 17:43:10.107318 [CA 2] Center 35 (4~66) winsize 63
1380 17:43:10.110647 [CA 3] Center 34 (4~65) winsize 62
1381 17:43:10.113970 [CA 4] Center 34 (4~65) winsize 62
1382 17:43:10.117215 [CA 5] Center 34 (4~65) winsize 62
1383 17:43:10.117299
1384 17:43:10.120548 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1385 17:43:10.120627
1386 17:43:10.123298 [CATrainingPosCal] consider 1 rank data
1387 17:43:10.127194 u2DelayCellTimex100 = 270/100 ps
1388 17:43:10.130507 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1389 17:43:10.133921 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1390 17:43:10.140467 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1391 17:43:10.143722 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1392 17:43:10.146917 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1393 17:43:10.150670 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1394 17:43:10.150795
1395 17:43:10.153995 CA PerBit enable=1, Macro0, CA PI delay=34
1396 17:43:10.154107
1397 17:43:10.157344 [CBTSetCACLKResult] CA Dly = 34
1398 17:43:10.157456 CS Dly: 6 (0~37)
1399 17:43:10.157548 ==
1400 17:43:10.160639 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 17:43:10.167315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 17:43:10.167439 ==
1403 17:43:10.170701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 17:43:10.177130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 17:43:10.186129 [CA 0] Center 37 (6~68) winsize 63
1406 17:43:10.190018 [CA 1] Center 36 (6~67) winsize 62
1407 17:43:10.193179 [CA 2] Center 35 (4~66) winsize 63
1408 17:43:10.196957 [CA 3] Center 34 (4~65) winsize 62
1409 17:43:10.200454 [CA 4] Center 35 (5~66) winsize 62
1410 17:43:10.204049 [CA 5] Center 34 (4~65) winsize 62
1411 17:43:10.204137
1412 17:43:10.207814 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1413 17:43:10.207901
1414 17:43:10.211701 [CATrainingPosCal] consider 2 rank data
1415 17:43:10.215028 u2DelayCellTimex100 = 270/100 ps
1416 17:43:10.219581 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 17:43:10.223272 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1418 17:43:10.226835 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1419 17:43:10.226916 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 17:43:10.230654 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 17:43:10.234530 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 17:43:10.237860
1423 17:43:10.241122 CA PerBit enable=1, Macro0, CA PI delay=34
1424 17:43:10.241203
1425 17:43:10.244371 [CBTSetCACLKResult] CA Dly = 34
1426 17:43:10.244453 CS Dly: 6 (0~38)
1427 17:43:10.244518
1428 17:43:10.247744 ----->DramcWriteLeveling(PI) begin...
1429 17:43:10.247827 ==
1430 17:43:10.250984 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 17:43:10.254207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 17:43:10.254289 ==
1433 17:43:10.257299 Write leveling (Byte 0): 26 => 26
1434 17:43:10.260696 Write leveling (Byte 1): 27 => 27
1435 17:43:10.264007 DramcWriteLeveling(PI) end<-----
1436 17:43:10.264089
1437 17:43:10.264153 ==
1438 17:43:10.267160 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 17:43:10.274423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 17:43:10.274505 ==
1441 17:43:10.274570 [Gating] SW mode calibration
1442 17:43:10.284180 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 17:43:10.287225 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 17:43:10.291081 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1445 17:43:10.297764 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1446 17:43:10.300981 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 17:43:10.304162 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 17:43:10.310935 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 17:43:10.314117 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 17:43:10.317161 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 17:43:10.324164 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 17:43:10.327483 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 17:43:10.330576 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 17:43:10.337459 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 17:43:10.340810 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 17:43:10.343889 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 17:43:10.350710 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 17:43:10.353821 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 17:43:10.357585 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 17:43:10.363947 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1461 17:43:10.367308 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1462 17:43:10.370638 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 17:43:10.373996 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 17:43:10.380781 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 17:43:10.384015 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 17:43:10.387276 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 17:43:10.394176 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 17:43:10.397345 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 17:43:10.400589 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1470 17:43:10.407058 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1471 17:43:10.410281 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 17:43:10.413672 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 17:43:10.420277 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 17:43:10.424117 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 17:43:10.427413 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 17:43:10.433908 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1477 17:43:10.437274 0 10 4 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)
1478 17:43:10.440674 0 10 8 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
1479 17:43:10.447013 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 17:43:10.450355 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 17:43:10.453670 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 17:43:10.460644 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 17:43:10.463694 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 17:43:10.467300 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 17:43:10.473876 0 11 4 | B1->B0 | 2828 3636 | 0 1 | (1 1) (0 0)
1486 17:43:10.477107 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1487 17:43:10.480656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 17:43:10.483824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 17:43:10.490369 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 17:43:10.493741 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 17:43:10.497133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 17:43:10.503985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 17:43:10.507616 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1494 17:43:10.510787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 17:43:10.517432 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 17:43:10.520739 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 17:43:10.524129 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 17:43:10.530672 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 17:43:10.533847 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 17:43:10.537439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 17:43:10.544038 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 17:43:10.547273 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 17:43:10.550613 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 17:43:10.557247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 17:43:10.560576 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 17:43:10.563889 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 17:43:10.570556 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 17:43:10.573845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1509 17:43:10.577248 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1510 17:43:10.580658 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 17:43:10.583943 Total UI for P1: 0, mck2ui 16
1512 17:43:10.587116 best dqsien dly found for B0: ( 0, 14, 2)
1513 17:43:10.590744 Total UI for P1: 0, mck2ui 16
1514 17:43:10.593639 best dqsien dly found for B1: ( 0, 14, 4)
1515 17:43:10.596914 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1516 17:43:10.603571 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1517 17:43:10.603705
1518 17:43:10.607242 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1519 17:43:10.610521 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1520 17:43:10.613946 [Gating] SW calibration Done
1521 17:43:10.614051 ==
1522 17:43:10.617429 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 17:43:10.620938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 17:43:10.621019 ==
1525 17:43:10.621083 RX Vref Scan: 0
1526 17:43:10.621143
1527 17:43:10.623713 RX Vref 0 -> 0, step: 1
1528 17:43:10.623794
1529 17:43:10.627165 RX Delay -130 -> 252, step: 16
1530 17:43:10.630610 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1531 17:43:10.633956 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1532 17:43:10.637299 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1533 17:43:10.643765 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1534 17:43:10.647622 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1535 17:43:10.650627 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1536 17:43:10.654441 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1537 17:43:10.657633 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1538 17:43:10.663912 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1539 17:43:10.667759 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1540 17:43:10.671017 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1541 17:43:10.674360 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1542 17:43:10.677756 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1543 17:43:10.684414 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1544 17:43:10.687720 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1545 17:43:10.690979 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1546 17:43:10.691076 ==
1547 17:43:10.694321 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 17:43:10.697638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1549 17:43:10.697717 ==
1550 17:43:10.700948 DQS Delay:
1551 17:43:10.701032 DQS0 = 0, DQS1 = 0
1552 17:43:10.704086 DQM Delay:
1553 17:43:10.704183 DQM0 = 96, DQM1 = 93
1554 17:43:10.704271 DQ Delay:
1555 17:43:10.707884 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1556 17:43:10.711325 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1557 17:43:10.714482 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1558 17:43:10.717532 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1559 17:43:10.721034
1560 17:43:10.721112
1561 17:43:10.721178 ==
1562 17:43:10.724290 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 17:43:10.727574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 17:43:10.727678 ==
1565 17:43:10.727743
1566 17:43:10.727802
1567 17:43:10.730946 TX Vref Scan disable
1568 17:43:10.731042 == TX Byte 0 ==
1569 17:43:10.737447 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1570 17:43:10.741266 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1571 17:43:10.741351 == TX Byte 1 ==
1572 17:43:10.747668 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1573 17:43:10.751073 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1574 17:43:10.751155 ==
1575 17:43:10.754410 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 17:43:10.757371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 17:43:10.757453 ==
1578 17:43:10.771060 TX Vref=22, minBit 0, minWin=26, winSum=434
1579 17:43:10.774384 TX Vref=24, minBit 0, minWin=26, winSum=438
1580 17:43:10.779119 TX Vref=26, minBit 1, minWin=27, winSum=444
1581 17:43:10.782385 TX Vref=28, minBit 1, minWin=27, winSum=448
1582 17:43:10.785790 TX Vref=30, minBit 0, minWin=27, winSum=449
1583 17:43:10.789158 TX Vref=32, minBit 2, minWin=26, winSum=443
1584 17:43:10.795855 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1585 17:43:10.795966
1586 17:43:10.798741 Final TX Range 1 Vref 30
1587 17:43:10.798814
1588 17:43:10.798892 ==
1589 17:43:10.802063 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 17:43:10.805399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 17:43:10.805505 ==
1592 17:43:10.805600
1593 17:43:10.805702
1594 17:43:10.809206 TX Vref Scan disable
1595 17:43:10.812422 == TX Byte 0 ==
1596 17:43:10.815657 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1597 17:43:10.819043 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1598 17:43:10.822607 == TX Byte 1 ==
1599 17:43:10.825747 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1600 17:43:10.829001 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1601 17:43:10.829074
1602 17:43:10.829134 [DATLAT]
1603 17:43:10.832174 Freq=800, CH1 RK0
1604 17:43:10.832277
1605 17:43:10.832366 DATLAT Default: 0xa
1606 17:43:10.835986 0, 0xFFFF, sum = 0
1607 17:43:10.839092 1, 0xFFFF, sum = 0
1608 17:43:10.839204 2, 0xFFFF, sum = 0
1609 17:43:10.842130 3, 0xFFFF, sum = 0
1610 17:43:10.842214 4, 0xFFFF, sum = 0
1611 17:43:10.845589 5, 0xFFFF, sum = 0
1612 17:43:10.845671 6, 0xFFFF, sum = 0
1613 17:43:10.849492 7, 0xFFFF, sum = 0
1614 17:43:10.849575 8, 0xFFFF, sum = 0
1615 17:43:10.852570 9, 0x0, sum = 1
1616 17:43:10.852691 10, 0x0, sum = 2
1617 17:43:10.852785 11, 0x0, sum = 3
1618 17:43:10.856153 12, 0x0, sum = 4
1619 17:43:10.856250 best_step = 10
1620 17:43:10.856337
1621 17:43:10.858940 ==
1622 17:43:10.859021 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 17:43:10.865779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 17:43:10.865860 ==
1625 17:43:10.865924 RX Vref Scan: 1
1626 17:43:10.865984
1627 17:43:10.869093 Set Vref Range= 32 -> 127
1628 17:43:10.869174
1629 17:43:10.872445 RX Vref 32 -> 127, step: 1
1630 17:43:10.872525
1631 17:43:10.875728 RX Delay -63 -> 252, step: 8
1632 17:43:10.875809
1633 17:43:10.878918 Set Vref, RX VrefLevel [Byte0]: 32
1634 17:43:10.882122 [Byte1]: 32
1635 17:43:10.882203
1636 17:43:10.885497 Set Vref, RX VrefLevel [Byte0]: 33
1637 17:43:10.888689 [Byte1]: 33
1638 17:43:10.888768
1639 17:43:10.891881 Set Vref, RX VrefLevel [Byte0]: 34
1640 17:43:10.895377 [Byte1]: 34
1641 17:43:10.898649
1642 17:43:10.898764 Set Vref, RX VrefLevel [Byte0]: 35
1643 17:43:10.901967 [Byte1]: 35
1644 17:43:10.906149
1645 17:43:10.906257 Set Vref, RX VrefLevel [Byte0]: 36
1646 17:43:10.909298 [Byte1]: 36
1647 17:43:10.913841
1648 17:43:10.913915 Set Vref, RX VrefLevel [Byte0]: 37
1649 17:43:10.916997 [Byte1]: 37
1650 17:43:10.920868
1651 17:43:10.920949 Set Vref, RX VrefLevel [Byte0]: 38
1652 17:43:10.924229 [Byte1]: 38
1653 17:43:10.928840
1654 17:43:10.928920 Set Vref, RX VrefLevel [Byte0]: 39
1655 17:43:10.932255 [Byte1]: 39
1656 17:43:10.936156
1657 17:43:10.936236 Set Vref, RX VrefLevel [Byte0]: 40
1658 17:43:10.939263 [Byte1]: 40
1659 17:43:10.943779
1660 17:43:10.943859 Set Vref, RX VrefLevel [Byte0]: 41
1661 17:43:10.946949 [Byte1]: 41
1662 17:43:10.950874
1663 17:43:10.950985 Set Vref, RX VrefLevel [Byte0]: 42
1664 17:43:10.954253 [Byte1]: 42
1665 17:43:10.958965
1666 17:43:10.959046 Set Vref, RX VrefLevel [Byte0]: 43
1667 17:43:10.962185 [Byte1]: 43
1668 17:43:10.966087
1669 17:43:10.966168 Set Vref, RX VrefLevel [Byte0]: 44
1670 17:43:10.969313 [Byte1]: 44
1671 17:43:10.973788
1672 17:43:10.973869 Set Vref, RX VrefLevel [Byte0]: 45
1673 17:43:10.977164 [Byte1]: 45
1674 17:43:10.981129
1675 17:43:10.981209 Set Vref, RX VrefLevel [Byte0]: 46
1676 17:43:10.984172 [Byte1]: 46
1677 17:43:10.988519
1678 17:43:10.988600 Set Vref, RX VrefLevel [Byte0]: 47
1679 17:43:10.991988 [Byte1]: 47
1680 17:43:10.996313
1681 17:43:10.996394 Set Vref, RX VrefLevel [Byte0]: 48
1682 17:43:10.999157 [Byte1]: 48
1683 17:43:11.003596
1684 17:43:11.003701 Set Vref, RX VrefLevel [Byte0]: 49
1685 17:43:11.006840 [Byte1]: 49
1686 17:43:11.010781
1687 17:43:11.014046 Set Vref, RX VrefLevel [Byte0]: 50
1688 17:43:11.014145 [Byte1]: 50
1689 17:43:11.018805
1690 17:43:11.018885 Set Vref, RX VrefLevel [Byte0]: 51
1691 17:43:11.021980 [Byte1]: 51
1692 17:43:11.025800
1693 17:43:11.025881 Set Vref, RX VrefLevel [Byte0]: 52
1694 17:43:11.029144 [Byte1]: 52
1695 17:43:11.033827
1696 17:43:11.033907 Set Vref, RX VrefLevel [Byte0]: 53
1697 17:43:11.037202 [Byte1]: 53
1698 17:43:11.041160
1699 17:43:11.041241 Set Vref, RX VrefLevel [Byte0]: 54
1700 17:43:11.044325 [Byte1]: 54
1701 17:43:11.048782
1702 17:43:11.048862 Set Vref, RX VrefLevel [Byte0]: 55
1703 17:43:11.052040 [Byte1]: 55
1704 17:43:11.055954
1705 17:43:11.056034 Set Vref, RX VrefLevel [Byte0]: 56
1706 17:43:11.059241 [Byte1]: 56
1707 17:43:11.063812
1708 17:43:11.063893 Set Vref, RX VrefLevel [Byte0]: 57
1709 17:43:11.067138 [Byte1]: 57
1710 17:43:11.071090
1711 17:43:11.071170 Set Vref, RX VrefLevel [Byte0]: 58
1712 17:43:11.074253 [Byte1]: 58
1713 17:43:11.078501
1714 17:43:11.078581 Set Vref, RX VrefLevel [Byte0]: 59
1715 17:43:11.081753 [Byte1]: 59
1716 17:43:11.086338
1717 17:43:11.086418 Set Vref, RX VrefLevel [Byte0]: 60
1718 17:43:11.089654 [Byte1]: 60
1719 17:43:11.093430
1720 17:43:11.093510 Set Vref, RX VrefLevel [Byte0]: 61
1721 17:43:11.097153 [Byte1]: 61
1722 17:43:11.100965
1723 17:43:11.101046 Set Vref, RX VrefLevel [Byte0]: 62
1724 17:43:11.104400 [Byte1]: 62
1725 17:43:11.109006
1726 17:43:11.109087 Set Vref, RX VrefLevel [Byte0]: 63
1727 17:43:11.112023 [Byte1]: 63
1728 17:43:11.116166
1729 17:43:11.116247 Set Vref, RX VrefLevel [Byte0]: 64
1730 17:43:11.119103 [Byte1]: 64
1731 17:43:11.123622
1732 17:43:11.123710 Set Vref, RX VrefLevel [Byte0]: 65
1733 17:43:11.126972 [Byte1]: 65
1734 17:43:11.131005
1735 17:43:11.131085 Set Vref, RX VrefLevel [Byte0]: 66
1736 17:43:11.134506 [Byte1]: 66
1737 17:43:11.138439
1738 17:43:11.138520 Set Vref, RX VrefLevel [Byte0]: 67
1739 17:43:11.141755 [Byte1]: 67
1740 17:43:11.145729
1741 17:43:11.145810 Set Vref, RX VrefLevel [Byte0]: 68
1742 17:43:11.149610 [Byte1]: 68
1743 17:43:11.153323
1744 17:43:11.153404 Set Vref, RX VrefLevel [Byte0]: 69
1745 17:43:11.157176 [Byte1]: 69
1746 17:43:11.161150
1747 17:43:11.161230 Set Vref, RX VrefLevel [Byte0]: 70
1748 17:43:11.164295 [Byte1]: 70
1749 17:43:11.168416
1750 17:43:11.168496 Set Vref, RX VrefLevel [Byte0]: 71
1751 17:43:11.171744 [Byte1]: 71
1752 17:43:11.175703
1753 17:43:11.175783 Set Vref, RX VrefLevel [Byte0]: 72
1754 17:43:11.179648 [Byte1]: 72
1755 17:43:11.183546
1756 17:43:11.183626 Set Vref, RX VrefLevel [Byte0]: 73
1757 17:43:11.186648 [Byte1]: 73
1758 17:43:11.191061
1759 17:43:11.191174 Final RX Vref Byte 0 = 55 to rank0
1760 17:43:11.194348 Final RX Vref Byte 1 = 56 to rank0
1761 17:43:11.197616 Final RX Vref Byte 0 = 55 to rank1
1762 17:43:11.201469 Final RX Vref Byte 1 = 56 to rank1==
1763 17:43:11.204674 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 17:43:11.207969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 17:43:11.211311 ==
1766 17:43:11.211407 DQS Delay:
1767 17:43:11.211500 DQS0 = 0, DQS1 = 0
1768 17:43:11.214484 DQM Delay:
1769 17:43:11.214587 DQM0 = 94, DQM1 = 89
1770 17:43:11.217785 DQ Delay:
1771 17:43:11.220941 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1772 17:43:11.221011 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1773 17:43:11.224812 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1774 17:43:11.228085 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1775 17:43:11.231380
1776 17:43:11.231482
1777 17:43:11.237728 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1778 17:43:11.241379 CH1 RK0: MR19=606, MR18=2945
1779 17:43:11.247852 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1780 17:43:11.247927
1781 17:43:11.251344 ----->DramcWriteLeveling(PI) begin...
1782 17:43:11.251445 ==
1783 17:43:11.254603 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 17:43:11.257901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 17:43:11.257974 ==
1786 17:43:11.261674 Write leveling (Byte 0): 29 => 29
1787 17:43:11.265015 Write leveling (Byte 1): 29 => 29
1788 17:43:11.268024 DramcWriteLeveling(PI) end<-----
1789 17:43:11.268106
1790 17:43:11.268171 ==
1791 17:43:11.271354 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 17:43:11.274601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 17:43:11.274693 ==
1794 17:43:11.277857 [Gating] SW mode calibration
1795 17:43:11.284532 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 17:43:11.291036 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 17:43:11.294778 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1798 17:43:11.297665 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1799 17:43:11.304752 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 17:43:11.308013 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 17:43:11.311307 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 17:43:11.318009 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 17:43:11.321273 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 17:43:11.324516 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 17:43:11.331237 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 17:43:11.334540 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 17:43:11.337663 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 17:43:11.341555 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 17:43:11.348142 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 17:43:11.351303 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 17:43:11.354444 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 17:43:11.360994 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 17:43:11.364567 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1814 17:43:11.368242 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1815 17:43:11.374773 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 17:43:11.377809 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 17:43:11.381412 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 17:43:11.388075 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 17:43:11.391561 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 17:43:11.394877 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 17:43:11.401209 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 17:43:11.404391 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1823 17:43:11.408088 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 1)
1824 17:43:11.414956 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 17:43:11.418255 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 17:43:11.421591 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 17:43:11.425016 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 17:43:11.431651 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 17:43:11.434942 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1830 17:43:11.438270 0 10 4 | B1->B0 | 2c2c 3030 | 0 1 | (1 0) (1 0)
1831 17:43:11.445075 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1832 17:43:11.448220 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 17:43:11.451517 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 17:43:11.458705 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 17:43:11.461682 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 17:43:11.464889 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 17:43:11.471804 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 17:43:11.474847 0 11 4 | B1->B0 | 3939 2f2f | 0 0 | (0 0) (1 1)
1839 17:43:11.478065 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 17:43:11.481898 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 17:43:11.488600 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 17:43:11.491606 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 17:43:11.495410 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 17:43:11.501978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 17:43:11.505375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 17:43:11.508664 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1847 17:43:11.515331 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 17:43:11.518954 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 17:43:11.521886 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 17:43:11.528443 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 17:43:11.532260 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 17:43:11.535037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 17:43:11.541760 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 17:43:11.545741 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 17:43:11.548583 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 17:43:11.555751 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 17:43:11.558963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 17:43:11.562247 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 17:43:11.565487 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 17:43:11.572154 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 17:43:11.575339 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1862 17:43:11.579108 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1863 17:43:11.585411 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 17:43:11.588747 Total UI for P1: 0, mck2ui 16
1865 17:43:11.592064 best dqsien dly found for B0: ( 0, 14, 4)
1866 17:43:11.592150 Total UI for P1: 0, mck2ui 16
1867 17:43:11.598591 best dqsien dly found for B1: ( 0, 14, 2)
1868 17:43:11.602168 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1869 17:43:11.605282 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1870 17:43:11.605365
1871 17:43:11.609030 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 17:43:11.612276 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1873 17:43:11.615531 [Gating] SW calibration Done
1874 17:43:11.615614 ==
1875 17:43:11.618959 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 17:43:11.622323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 17:43:11.622405 ==
1878 17:43:11.625507 RX Vref Scan: 0
1879 17:43:11.625590
1880 17:43:11.625656 RX Vref 0 -> 0, step: 1
1881 17:43:11.625716
1882 17:43:11.629114 RX Delay -130 -> 252, step: 16
1883 17:43:11.632036 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1884 17:43:11.638919 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1885 17:43:11.642183 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1886 17:43:11.645610 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1887 17:43:11.648919 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1888 17:43:11.652245 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1889 17:43:11.658864 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1890 17:43:11.662246 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1891 17:43:11.665650 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1892 17:43:11.668848 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1893 17:43:11.671978 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1894 17:43:11.678963 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1895 17:43:11.681877 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1896 17:43:11.685377 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1897 17:43:11.688880 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1898 17:43:11.691918 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1899 17:43:11.692001 ==
1900 17:43:11.695236 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 17:43:11.701885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 17:43:11.701982 ==
1903 17:43:11.702050 DQS Delay:
1904 17:43:11.705705 DQS0 = 0, DQS1 = 0
1905 17:43:11.705787 DQM Delay:
1906 17:43:11.708653 DQM0 = 91, DQM1 = 87
1907 17:43:11.708734 DQ Delay:
1908 17:43:11.712207 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1909 17:43:11.715716 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1910 17:43:11.718548 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1911 17:43:11.722200 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1912 17:43:11.722283
1913 17:43:11.722348
1914 17:43:11.722409 ==
1915 17:43:11.725493 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 17:43:11.728777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 17:43:11.728860 ==
1918 17:43:11.728926
1919 17:43:11.728988
1920 17:43:11.732057 TX Vref Scan disable
1921 17:43:11.735403 == TX Byte 0 ==
1922 17:43:11.739199 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1923 17:43:11.742264 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1924 17:43:11.742347 == TX Byte 1 ==
1925 17:43:11.748837 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1926 17:43:11.752238 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1927 17:43:11.752321 ==
1928 17:43:11.755548 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 17:43:11.758865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 17:43:11.758948 ==
1931 17:43:11.773545 TX Vref=22, minBit 0, minWin=27, winSum=443
1932 17:43:11.776221 TX Vref=24, minBit 2, minWin=27, winSum=449
1933 17:43:11.780038 TX Vref=26, minBit 2, minWin=27, winSum=449
1934 17:43:11.783297 TX Vref=28, minBit 1, minWin=27, winSum=449
1935 17:43:11.786574 TX Vref=30, minBit 2, minWin=27, winSum=450
1936 17:43:11.789666 TX Vref=32, minBit 2, minWin=26, winSum=449
1937 17:43:11.796360 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30
1938 17:43:11.796454
1939 17:43:11.799516 Final TX Range 1 Vref 30
1940 17:43:11.799625
1941 17:43:11.799735 ==
1942 17:43:11.803276 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 17:43:11.806636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 17:43:11.806720 ==
1945 17:43:11.806786
1946 17:43:11.806847
1947 17:43:11.809867 TX Vref Scan disable
1948 17:43:11.813127 == TX Byte 0 ==
1949 17:43:11.816562 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1950 17:43:11.819967 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1951 17:43:11.823065 == TX Byte 1 ==
1952 17:43:11.826702 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1953 17:43:11.829656 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1954 17:43:11.829737
1955 17:43:11.833323 [DATLAT]
1956 17:43:11.833404 Freq=800, CH1 RK1
1957 17:43:11.833470
1958 17:43:11.836705 DATLAT Default: 0xa
1959 17:43:11.836787 0, 0xFFFF, sum = 0
1960 17:43:11.840073 1, 0xFFFF, sum = 0
1961 17:43:11.840156 2, 0xFFFF, sum = 0
1962 17:43:11.843473 3, 0xFFFF, sum = 0
1963 17:43:11.843556 4, 0xFFFF, sum = 0
1964 17:43:11.846746 5, 0xFFFF, sum = 0
1965 17:43:11.846829 6, 0xFFFF, sum = 0
1966 17:43:11.849977 7, 0xFFFF, sum = 0
1967 17:43:11.850060 8, 0xFFFF, sum = 0
1968 17:43:11.853264 9, 0x0, sum = 1
1969 17:43:11.853347 10, 0x0, sum = 2
1970 17:43:11.856429 11, 0x0, sum = 3
1971 17:43:11.856512 12, 0x0, sum = 4
1972 17:43:11.859806 best_step = 10
1973 17:43:11.859887
1974 17:43:11.859952 ==
1975 17:43:11.863464 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 17:43:11.866703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 17:43:11.866786 ==
1978 17:43:11.869946 RX Vref Scan: 0
1979 17:43:11.870028
1980 17:43:11.870093 RX Vref 0 -> 0, step: 1
1981 17:43:11.870153
1982 17:43:11.873228 RX Delay -79 -> 252, step: 8
1983 17:43:11.879916 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1984 17:43:11.883184 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1985 17:43:11.886421 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1986 17:43:11.889858 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1987 17:43:11.893049 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1988 17:43:11.896968 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1989 17:43:11.903289 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1990 17:43:11.906844 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1991 17:43:11.910088 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1992 17:43:11.913097 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1993 17:43:11.916509 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1994 17:43:11.919814 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1995 17:43:11.927085 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1996 17:43:11.930357 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1997 17:43:11.933590 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1998 17:43:11.936681 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
1999 17:43:11.936765 ==
2000 17:43:11.939957 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 17:43:11.946863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 17:43:11.946946 ==
2003 17:43:11.947011 DQS Delay:
2004 17:43:11.950332 DQS0 = 0, DQS1 = 0
2005 17:43:11.950414 DQM Delay:
2006 17:43:11.950480 DQM0 = 97, DQM1 = 91
2007 17:43:11.953453 DQ Delay:
2008 17:43:11.956780 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2009 17:43:11.960142 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2010 17:43:11.963230 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2011 17:43:11.966934 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2012 17:43:11.967016
2013 17:43:11.967081
2014 17:43:11.973326 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2015 17:43:11.976595 CH1 RK1: MR19=606, MR18=4610
2016 17:43:11.983823 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2017 17:43:11.986958 [RxdqsGatingPostProcess] freq 800
2018 17:43:11.990333 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2019 17:43:11.993702 Pre-setting of DQS Precalculation
2020 17:43:12.000221 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2021 17:43:12.006740 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2022 17:43:12.013293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2023 17:43:12.013376
2024 17:43:12.013441
2025 17:43:12.016837 [Calibration Summary] 1600 Mbps
2026 17:43:12.016920 CH 0, Rank 0
2027 17:43:12.020480 SW Impedance : PASS
2028 17:43:12.023656 DUTY Scan : NO K
2029 17:43:12.023753 ZQ Calibration : PASS
2030 17:43:12.026783 Jitter Meter : NO K
2031 17:43:12.030029 CBT Training : PASS
2032 17:43:12.030111 Write leveling : PASS
2033 17:43:12.033278 RX DQS gating : PASS
2034 17:43:12.036646 RX DQ/DQS(RDDQC) : PASS
2035 17:43:12.036728 TX DQ/DQS : PASS
2036 17:43:12.039985 RX DATLAT : PASS
2037 17:43:12.040067 RX DQ/DQS(Engine): PASS
2038 17:43:12.043214 TX OE : NO K
2039 17:43:12.043297 All Pass.
2040 17:43:12.043363
2041 17:43:12.046869 CH 0, Rank 1
2042 17:43:12.046951 SW Impedance : PASS
2043 17:43:12.050420 DUTY Scan : NO K
2044 17:43:12.053778 ZQ Calibration : PASS
2045 17:43:12.053860 Jitter Meter : NO K
2046 17:43:12.056906 CBT Training : PASS
2047 17:43:12.059923 Write leveling : PASS
2048 17:43:12.060005 RX DQS gating : PASS
2049 17:43:12.063820 RX DQ/DQS(RDDQC) : PASS
2050 17:43:12.067035 TX DQ/DQS : PASS
2051 17:43:12.067117 RX DATLAT : PASS
2052 17:43:12.070228 RX DQ/DQS(Engine): PASS
2053 17:43:12.073298 TX OE : NO K
2054 17:43:12.073380 All Pass.
2055 17:43:12.073444
2056 17:43:12.073505 CH 1, Rank 0
2057 17:43:12.077160 SW Impedance : PASS
2058 17:43:12.080331 DUTY Scan : NO K
2059 17:43:12.080413 ZQ Calibration : PASS
2060 17:43:12.083572 Jitter Meter : NO K
2061 17:43:12.083682 CBT Training : PASS
2062 17:43:12.086901 Write leveling : PASS
2063 17:43:12.090288 RX DQS gating : PASS
2064 17:43:12.090370 RX DQ/DQS(RDDQC) : PASS
2065 17:43:12.093978 TX DQ/DQS : PASS
2066 17:43:12.097301 RX DATLAT : PASS
2067 17:43:12.097383 RX DQ/DQS(Engine): PASS
2068 17:43:12.100494 TX OE : NO K
2069 17:43:12.100576 All Pass.
2070 17:43:12.100642
2071 17:43:12.103913 CH 1, Rank 1
2072 17:43:12.103995 SW Impedance : PASS
2073 17:43:12.107094 DUTY Scan : NO K
2074 17:43:12.110384 ZQ Calibration : PASS
2075 17:43:12.110466 Jitter Meter : NO K
2076 17:43:12.113639 CBT Training : PASS
2077 17:43:12.116959 Write leveling : PASS
2078 17:43:12.117041 RX DQS gating : PASS
2079 17:43:12.120197 RX DQ/DQS(RDDQC) : PASS
2080 17:43:12.120279 TX DQ/DQS : PASS
2081 17:43:12.123515 RX DATLAT : PASS
2082 17:43:12.127200 RX DQ/DQS(Engine): PASS
2083 17:43:12.127282 TX OE : NO K
2084 17:43:12.130353 All Pass.
2085 17:43:12.130434
2086 17:43:12.130499 DramC Write-DBI off
2087 17:43:12.133587 PER_BANK_REFRESH: Hybrid Mode
2088 17:43:12.137337 TX_TRACKING: ON
2089 17:43:12.140603 [GetDramInforAfterCalByMRR] Vendor 6.
2090 17:43:12.144061 [GetDramInforAfterCalByMRR] Revision 606.
2091 17:43:12.147372 [GetDramInforAfterCalByMRR] Revision 2 0.
2092 17:43:12.147453 MR0 0x3b3b
2093 17:43:12.147517 MR8 0x5151
2094 17:43:12.154136 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 17:43:12.154218
2096 17:43:12.154286 MR0 0x3b3b
2097 17:43:12.154346 MR8 0x5151
2098 17:43:12.157365 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 17:43:12.157447
2100 17:43:12.167014 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2101 17:43:12.170627 [FAST_K] Save calibration result to emmc
2102 17:43:12.173705 [FAST_K] Save calibration result to emmc
2103 17:43:12.177174 dram_init: config_dvfs: 1
2104 17:43:12.180216 dramc_set_vcore_voltage set vcore to 662500
2105 17:43:12.183939 Read voltage for 1200, 2
2106 17:43:12.184021 Vio18 = 0
2107 17:43:12.184086 Vcore = 662500
2108 17:43:12.187108 Vdram = 0
2109 17:43:12.187189 Vddq = 0
2110 17:43:12.187255 Vmddr = 0
2111 17:43:12.194316 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2112 17:43:12.197647 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2113 17:43:12.200794 MEM_TYPE=3, freq_sel=15
2114 17:43:12.204101 sv_algorithm_assistance_LP4_1600
2115 17:43:12.207407 ============ PULL DRAM RESETB DOWN ============
2116 17:43:12.210592 ========== PULL DRAM RESETB DOWN end =========
2117 17:43:12.217285 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 17:43:12.220659 ===================================
2119 17:43:12.220741 LPDDR4 DRAM CONFIGURATION
2120 17:43:12.224028 ===================================
2121 17:43:12.227317 EX_ROW_EN[0] = 0x0
2122 17:43:12.230633 EX_ROW_EN[1] = 0x0
2123 17:43:12.230715 LP4Y_EN = 0x0
2124 17:43:12.234182 WORK_FSP = 0x0
2125 17:43:12.234263 WL = 0x4
2126 17:43:12.237178 RL = 0x4
2127 17:43:12.237260 BL = 0x2
2128 17:43:12.240474 RPST = 0x0
2129 17:43:12.240555 RD_PRE = 0x0
2130 17:43:12.244229 WR_PRE = 0x1
2131 17:43:12.244310 WR_PST = 0x0
2132 17:43:12.247444 DBI_WR = 0x0
2133 17:43:12.247526 DBI_RD = 0x0
2134 17:43:12.250770 OTF = 0x1
2135 17:43:12.254214 ===================================
2136 17:43:12.257355 ===================================
2137 17:43:12.257438 ANA top config
2138 17:43:12.260838 ===================================
2139 17:43:12.263997 DLL_ASYNC_EN = 0
2140 17:43:12.267379 ALL_SLAVE_EN = 0
2141 17:43:12.267461 NEW_RANK_MODE = 1
2142 17:43:12.270685 DLL_IDLE_MODE = 1
2143 17:43:12.274370 LP45_APHY_COMB_EN = 1
2144 17:43:12.277405 TX_ODT_DIS = 1
2145 17:43:12.280526 NEW_8X_MODE = 1
2146 17:43:12.284213 ===================================
2147 17:43:12.287140 ===================================
2148 17:43:12.287242 data_rate = 2400
2149 17:43:12.290615 CKR = 1
2150 17:43:12.293998 DQ_P2S_RATIO = 8
2151 17:43:12.297192 ===================================
2152 17:43:12.301045 CA_P2S_RATIO = 8
2153 17:43:12.304235 DQ_CA_OPEN = 0
2154 17:43:12.307516 DQ_SEMI_OPEN = 0
2155 17:43:12.307624 CA_SEMI_OPEN = 0
2156 17:43:12.310726 CA_FULL_RATE = 0
2157 17:43:12.314034 DQ_CKDIV4_EN = 0
2158 17:43:12.317285 CA_CKDIV4_EN = 0
2159 17:43:12.320593 CA_PREDIV_EN = 0
2160 17:43:12.323890 PH8_DLY = 17
2161 17:43:12.323972 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2162 17:43:12.327322 DQ_AAMCK_DIV = 4
2163 17:43:12.330706 CA_AAMCK_DIV = 4
2164 17:43:12.334174 CA_ADMCK_DIV = 4
2165 17:43:12.337307 DQ_TRACK_CA_EN = 0
2166 17:43:12.340542 CA_PICK = 1200
2167 17:43:12.340624 CA_MCKIO = 1200
2168 17:43:12.344267 MCKIO_SEMI = 0
2169 17:43:12.347242 PLL_FREQ = 2366
2170 17:43:12.351040 DQ_UI_PI_RATIO = 32
2171 17:43:12.354039 CA_UI_PI_RATIO = 0
2172 17:43:12.357403 ===================================
2173 17:43:12.360723 ===================================
2174 17:43:12.364032 memory_type:LPDDR4
2175 17:43:12.364113 GP_NUM : 10
2176 17:43:12.367872 SRAM_EN : 1
2177 17:43:12.367954 MD32_EN : 0
2178 17:43:12.370627 ===================================
2179 17:43:12.374159 [ANA_INIT] >>>>>>>>>>>>>>
2180 17:43:12.377455 <<<<<< [CONFIGURE PHASE]: ANA_TX
2181 17:43:12.380638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2182 17:43:12.384389 ===================================
2183 17:43:12.387335 data_rate = 2400,PCW = 0X5b00
2184 17:43:12.390996 ===================================
2185 17:43:12.394392 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2186 17:43:12.397619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 17:43:12.403958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 17:43:12.410536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2189 17:43:12.414163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2190 17:43:12.417734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2191 17:43:12.417817 [ANA_INIT] flow start
2192 17:43:12.421004 [ANA_INIT] PLL >>>>>>>>
2193 17:43:12.424232 [ANA_INIT] PLL <<<<<<<<
2194 17:43:12.424314 [ANA_INIT] MIDPI >>>>>>>>
2195 17:43:12.427563 [ANA_INIT] MIDPI <<<<<<<<
2196 17:43:12.430901 [ANA_INIT] DLL >>>>>>>>
2197 17:43:12.430983 [ANA_INIT] DLL <<<<<<<<
2198 17:43:12.434322 [ANA_INIT] flow end
2199 17:43:12.437670 ============ LP4 DIFF to SE enter ============
2200 17:43:12.441009 ============ LP4 DIFF to SE exit ============
2201 17:43:12.444214 [ANA_INIT] <<<<<<<<<<<<<
2202 17:43:12.447433 [Flow] Enable top DCM control >>>>>
2203 17:43:12.450680 [Flow] Enable top DCM control <<<<<
2204 17:43:12.454332 Enable DLL master slave shuffle
2205 17:43:12.461245 ==============================================================
2206 17:43:12.461328 Gating Mode config
2207 17:43:12.467709 ==============================================================
2208 17:43:12.467792 Config description:
2209 17:43:12.477505 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2210 17:43:12.484204 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2211 17:43:12.490783 SELPH_MODE 0: By rank 1: By Phase
2212 17:43:12.494416 ==============================================================
2213 17:43:12.497532 GAT_TRACK_EN = 1
2214 17:43:12.501082 RX_GATING_MODE = 2
2215 17:43:12.504327 RX_GATING_TRACK_MODE = 2
2216 17:43:12.507707 SELPH_MODE = 1
2217 17:43:12.511020 PICG_EARLY_EN = 1
2218 17:43:12.514177 VALID_LAT_VALUE = 1
2219 17:43:12.517749 ==============================================================
2220 17:43:12.520743 Enter into Gating configuration >>>>
2221 17:43:12.524548 Exit from Gating configuration <<<<
2222 17:43:12.527575 Enter into DVFS_PRE_config >>>>>
2223 17:43:12.541404 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2224 17:43:12.541489 Exit from DVFS_PRE_config <<<<<
2225 17:43:12.544412 Enter into PICG configuration >>>>
2226 17:43:12.547681 Exit from PICG configuration <<<<
2227 17:43:12.550992 [RX_INPUT] configuration >>>>>
2228 17:43:12.554251 [RX_INPUT] configuration <<<<<
2229 17:43:12.561214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2230 17:43:12.564951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2231 17:43:12.571266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 17:43:12.577877 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 17:43:12.584546 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 17:43:12.591233 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 17:43:12.594673 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2236 17:43:12.598000 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2237 17:43:12.601045 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2238 17:43:12.608033 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2239 17:43:12.610966 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2240 17:43:12.614750 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2241 17:43:12.617520 ===================================
2242 17:43:12.621204 LPDDR4 DRAM CONFIGURATION
2243 17:43:12.624220 ===================================
2244 17:43:12.624303 EX_ROW_EN[0] = 0x0
2245 17:43:12.628012 EX_ROW_EN[1] = 0x0
2246 17:43:12.628094 LP4Y_EN = 0x0
2247 17:43:12.631230 WORK_FSP = 0x0
2248 17:43:12.634285 WL = 0x4
2249 17:43:12.634371 RL = 0x4
2250 17:43:12.637940 BL = 0x2
2251 17:43:12.638045 RPST = 0x0
2252 17:43:12.641172 RD_PRE = 0x0
2253 17:43:12.641259 WR_PRE = 0x1
2254 17:43:12.644457 WR_PST = 0x0
2255 17:43:12.644531 DBI_WR = 0x0
2256 17:43:12.647594 DBI_RD = 0x0
2257 17:43:12.647729 OTF = 0x1
2258 17:43:12.651064 ===================================
2259 17:43:12.654427 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2260 17:43:12.661192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2261 17:43:12.664319 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 17:43:12.667996 ===================================
2263 17:43:12.671219 LPDDR4 DRAM CONFIGURATION
2264 17:43:12.674322 ===================================
2265 17:43:12.674402 EX_ROW_EN[0] = 0x10
2266 17:43:12.677543 EX_ROW_EN[1] = 0x0
2267 17:43:12.677626 LP4Y_EN = 0x0
2268 17:43:12.681060 WORK_FSP = 0x0
2269 17:43:12.681149 WL = 0x4
2270 17:43:12.684155 RL = 0x4
2271 17:43:12.684238 BL = 0x2
2272 17:43:12.688196 RPST = 0x0
2273 17:43:12.688298 RD_PRE = 0x0
2274 17:43:12.691452 WR_PRE = 0x1
2275 17:43:12.691537 WR_PST = 0x0
2276 17:43:12.694728 DBI_WR = 0x0
2277 17:43:12.698042 DBI_RD = 0x0
2278 17:43:12.698150 OTF = 0x1
2279 17:43:12.701273 ===================================
2280 17:43:12.707970 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2281 17:43:12.708055 ==
2282 17:43:12.711195 Dram Type= 6, Freq= 0, CH_0, rank 0
2283 17:43:12.714529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2284 17:43:12.714612 ==
2285 17:43:12.717650 [Duty_Offset_Calibration]
2286 17:43:12.717748 B0:2 B1:1 CA:1
2287 17:43:12.717853
2288 17:43:12.721345 [DutyScan_Calibration_Flow] k_type=0
2289 17:43:12.732170
2290 17:43:12.732262 ==CLK 0==
2291 17:43:12.735201 Final CLK duty delay cell = 0
2292 17:43:12.738916 [0] MAX Duty = 5187%(X100), DQS PI = 24
2293 17:43:12.742142 [0] MIN Duty = 4844%(X100), DQS PI = 48
2294 17:43:12.742263 [0] AVG Duty = 5015%(X100)
2295 17:43:12.745359
2296 17:43:12.748579 CH0 CLK Duty spec in!! Max-Min= 343%
2297 17:43:12.751616 [DutyScan_Calibration_Flow] ====Done====
2298 17:43:12.751727
2299 17:43:12.755094 [DutyScan_Calibration_Flow] k_type=1
2300 17:43:12.769534
2301 17:43:12.769612 ==DQS 0 ==
2302 17:43:12.773300 Final DQS duty delay cell = -4
2303 17:43:12.776493 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2304 17:43:12.779741 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2305 17:43:12.782993 [-4] AVG Duty = 4937%(X100)
2306 17:43:12.783077
2307 17:43:12.783144 ==DQS 1 ==
2308 17:43:12.786228 Final DQS duty delay cell = -4
2309 17:43:12.789842 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2310 17:43:12.793002 [-4] MIN Duty = 4844%(X100), DQS PI = 34
2311 17:43:12.796256 [-4] AVG Duty = 4906%(X100)
2312 17:43:12.796338
2313 17:43:12.799777 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2314 17:43:12.799865
2315 17:43:12.803095 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2316 17:43:12.806269 [DutyScan_Calibration_Flow] ====Done====
2317 17:43:12.806351
2318 17:43:12.809497 [DutyScan_Calibration_Flow] k_type=3
2319 17:43:12.827134
2320 17:43:12.827212 ==DQM 0 ==
2321 17:43:12.830288 Final DQM duty delay cell = 0
2322 17:43:12.833540 [0] MAX Duty = 5156%(X100), DQS PI = 30
2323 17:43:12.836892 [0] MIN Duty = 4875%(X100), DQS PI = 58
2324 17:43:12.836968 [0] AVG Duty = 5015%(X100)
2325 17:43:12.840037
2326 17:43:12.840112 ==DQM 1 ==
2327 17:43:12.843801 Final DQM duty delay cell = 0
2328 17:43:12.847086 [0] MAX Duty = 5125%(X100), DQS PI = 60
2329 17:43:12.850136 [0] MIN Duty = 5031%(X100), DQS PI = 34
2330 17:43:12.850244 [0] AVG Duty = 5078%(X100)
2331 17:43:12.853796
2332 17:43:12.856904 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2333 17:43:12.856985
2334 17:43:12.860092 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2335 17:43:12.863587 [DutyScan_Calibration_Flow] ====Done====
2336 17:43:12.863730
2337 17:43:12.866751 [DutyScan_Calibration_Flow] k_type=2
2338 17:43:12.883520
2339 17:43:12.883660 ==DQ 0 ==
2340 17:43:12.886675 Final DQ duty delay cell = 0
2341 17:43:12.890046 [0] MAX Duty = 5062%(X100), DQS PI = 32
2342 17:43:12.893334 [0] MIN Duty = 4906%(X100), DQS PI = 0
2343 17:43:12.893412 [0] AVG Duty = 4984%(X100)
2344 17:43:12.893481
2345 17:43:12.896558 ==DQ 1 ==
2346 17:43:12.900457 Final DQ duty delay cell = 0
2347 17:43:12.903710 [0] MAX Duty = 5093%(X100), DQS PI = 24
2348 17:43:12.907014 [0] MIN Duty = 4938%(X100), DQS PI = 36
2349 17:43:12.907091 [0] AVG Duty = 5015%(X100)
2350 17:43:12.907152
2351 17:43:12.910246 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2352 17:43:12.910320
2353 17:43:12.916906 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2354 17:43:12.920205 [DutyScan_Calibration_Flow] ====Done====
2355 17:43:12.920286 ==
2356 17:43:12.923526 Dram Type= 6, Freq= 0, CH_1, rank 0
2357 17:43:12.926681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 17:43:12.926753 ==
2359 17:43:12.930123 [Duty_Offset_Calibration]
2360 17:43:12.930228 B0:1 B1:0 CA:0
2361 17:43:12.930318
2362 17:43:12.933364 [DutyScan_Calibration_Flow] k_type=0
2363 17:43:12.942474
2364 17:43:12.942549 ==CLK 0==
2365 17:43:12.945770 Final CLK duty delay cell = -4
2366 17:43:12.948974 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2367 17:43:12.952895 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2368 17:43:12.956623 [-4] AVG Duty = 4953%(X100)
2369 17:43:12.956700
2370 17:43:12.959111 CH1 CLK Duty spec in!! Max-Min= 156%
2371 17:43:12.962375 [DutyScan_Calibration_Flow] ====Done====
2372 17:43:12.962479
2373 17:43:12.965722 [DutyScan_Calibration_Flow] k_type=1
2374 17:43:12.982007
2375 17:43:12.982117 ==DQS 0 ==
2376 17:43:12.985318 Final DQS duty delay cell = 0
2377 17:43:12.989018 [0] MAX Duty = 5062%(X100), DQS PI = 10
2378 17:43:12.992222 [0] MIN Duty = 4875%(X100), DQS PI = 0
2379 17:43:12.992303 [0] AVG Duty = 4968%(X100)
2380 17:43:12.995745
2381 17:43:12.995842 ==DQS 1 ==
2382 17:43:12.998946 Final DQS duty delay cell = 0
2383 17:43:13.002228 [0] MAX Duty = 5187%(X100), DQS PI = 18
2384 17:43:13.005505 [0] MIN Duty = 4969%(X100), DQS PI = 10
2385 17:43:13.005588 [0] AVG Duty = 5078%(X100)
2386 17:43:13.008655
2387 17:43:13.012556 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2388 17:43:13.012629
2389 17:43:13.015828 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2390 17:43:13.019247 [DutyScan_Calibration_Flow] ====Done====
2391 17:43:13.019350
2392 17:43:13.022519 [DutyScan_Calibration_Flow] k_type=3
2393 17:43:13.038671
2394 17:43:13.038750 ==DQM 0 ==
2395 17:43:13.041903 Final DQM duty delay cell = 0
2396 17:43:13.045658 [0] MAX Duty = 5156%(X100), DQS PI = 6
2397 17:43:13.048737 [0] MIN Duty = 5031%(X100), DQS PI = 0
2398 17:43:13.048810 [0] AVG Duty = 5093%(X100)
2399 17:43:13.048871
2400 17:43:13.052236 ==DQM 1 ==
2401 17:43:13.055816 Final DQM duty delay cell = 0
2402 17:43:13.059141 [0] MAX Duty = 5031%(X100), DQS PI = 16
2403 17:43:13.062451 [0] MIN Duty = 4907%(X100), DQS PI = 36
2404 17:43:13.062530 [0] AVG Duty = 4969%(X100)
2405 17:43:13.062593
2406 17:43:13.069142 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2407 17:43:13.069241
2408 17:43:13.072553 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2409 17:43:13.075432 [DutyScan_Calibration_Flow] ====Done====
2410 17:43:13.075535
2411 17:43:13.078931 [DutyScan_Calibration_Flow] k_type=2
2412 17:43:13.094817
2413 17:43:13.094961 ==DQ 0 ==
2414 17:43:13.098022 Final DQ duty delay cell = -4
2415 17:43:13.101320 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2416 17:43:13.104329 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2417 17:43:13.107578 [-4] AVG Duty = 4984%(X100)
2418 17:43:13.107724
2419 17:43:13.107828 ==DQ 1 ==
2420 17:43:13.111070 Final DQ duty delay cell = 0
2421 17:43:13.114803 [0] MAX Duty = 5125%(X100), DQS PI = 20
2422 17:43:13.118173 [0] MIN Duty = 4969%(X100), DQS PI = 12
2423 17:43:13.118327 [0] AVG Duty = 5047%(X100)
2424 17:43:13.121391
2425 17:43:13.124502 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2426 17:43:13.124707
2427 17:43:13.127779 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2428 17:43:13.131140 [DutyScan_Calibration_Flow] ====Done====
2429 17:43:13.135096 nWR fixed to 30
2430 17:43:13.135400 [ModeRegInit_LP4] CH0 RK0
2431 17:43:13.138337 [ModeRegInit_LP4] CH0 RK1
2432 17:43:13.141791 [ModeRegInit_LP4] CH1 RK0
2433 17:43:13.144774 [ModeRegInit_LP4] CH1 RK1
2434 17:43:13.144857 match AC timing 7
2435 17:43:13.148123 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2436 17:43:13.154698 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2437 17:43:13.157887 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2438 17:43:13.161000 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2439 17:43:13.168064 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2440 17:43:13.168152 ==
2441 17:43:13.171068 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 17:43:13.174445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 17:43:13.174529 ==
2444 17:43:13.181001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2445 17:43:13.187928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2446 17:43:13.194943 [CA 0] Center 39 (8~70) winsize 63
2447 17:43:13.197982 [CA 1] Center 39 (8~70) winsize 63
2448 17:43:13.201201 [CA 2] Center 35 (5~66) winsize 62
2449 17:43:13.205121 [CA 3] Center 34 (4~65) winsize 62
2450 17:43:13.208206 [CA 4] Center 33 (3~64) winsize 62
2451 17:43:13.211298 [CA 5] Center 32 (3~62) winsize 60
2452 17:43:13.211381
2453 17:43:13.214719 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2454 17:43:13.214802
2455 17:43:13.218377 [CATrainingPosCal] consider 1 rank data
2456 17:43:13.221529 u2DelayCellTimex100 = 270/100 ps
2457 17:43:13.224863 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 17:43:13.228156 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2459 17:43:13.234670 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2460 17:43:13.238664 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2461 17:43:13.241987 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2462 17:43:13.245253 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2463 17:43:13.245335
2464 17:43:13.248697 CA PerBit enable=1, Macro0, CA PI delay=32
2465 17:43:13.248778
2466 17:43:13.251400 [CBTSetCACLKResult] CA Dly = 32
2467 17:43:13.251482 CS Dly: 6 (0~37)
2468 17:43:13.251548 ==
2469 17:43:13.254806 Dram Type= 6, Freq= 0, CH_0, rank 1
2470 17:43:13.261519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 17:43:13.261601 ==
2472 17:43:13.264844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 17:43:13.271554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 17:43:13.280514 [CA 0] Center 38 (8~69) winsize 62
2475 17:43:13.284001 [CA 1] Center 38 (8~69) winsize 62
2476 17:43:13.287025 [CA 2] Center 35 (5~66) winsize 62
2477 17:43:13.290984 [CA 3] Center 34 (4~65) winsize 62
2478 17:43:13.293617 [CA 4] Center 33 (3~64) winsize 62
2479 17:43:13.297570 [CA 5] Center 32 (3~62) winsize 60
2480 17:43:13.297653
2481 17:43:13.300709 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 17:43:13.300792
2483 17:43:13.304118 [CATrainingPosCal] consider 2 rank data
2484 17:43:13.307059 u2DelayCellTimex100 = 270/100 ps
2485 17:43:13.310700 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 17:43:13.313780 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2487 17:43:13.320828 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2488 17:43:13.323821 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2489 17:43:13.327296 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2490 17:43:13.330446 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2491 17:43:13.330528
2492 17:43:13.333683 CA PerBit enable=1, Macro0, CA PI delay=32
2493 17:43:13.333765
2494 17:43:13.337404 [CBTSetCACLKResult] CA Dly = 32
2495 17:43:13.337487 CS Dly: 6 (0~38)
2496 17:43:13.337552
2497 17:43:13.340824 ----->DramcWriteLeveling(PI) begin...
2498 17:43:13.344067 ==
2499 17:43:13.344149 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 17:43:13.350676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 17:43:13.350759 ==
2502 17:43:13.353919 Write leveling (Byte 0): 32 => 32
2503 17:43:13.357221 Write leveling (Byte 1): 29 => 29
2504 17:43:13.360684 DramcWriteLeveling(PI) end<-----
2505 17:43:13.360766
2506 17:43:13.360832 ==
2507 17:43:13.364046 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 17:43:13.367712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 17:43:13.367798 ==
2510 17:43:13.370207 [Gating] SW mode calibration
2511 17:43:13.377678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2512 17:43:13.380878 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2513 17:43:13.387186 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2514 17:43:13.390917 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2515 17:43:13.393620 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 17:43:13.400877 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 17:43:13.404118 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 17:43:13.407438 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 17:43:13.414087 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 17:43:13.417365 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2521 17:43:13.420570 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2522 17:43:13.427561 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 17:43:13.430476 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 17:43:13.433752 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 17:43:13.440582 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 17:43:13.443830 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 17:43:13.447069 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2528 17:43:13.454168 1 0 28 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
2529 17:43:13.457743 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2530 17:43:13.460656 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 17:43:13.464031 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 17:43:13.470683 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 17:43:13.473972 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 17:43:13.477241 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 17:43:13.483810 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 17:43:13.487116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2537 17:43:13.490541 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 17:43:13.497120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 17:43:13.500699 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 17:43:13.503796 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 17:43:13.510870 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 17:43:13.514059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 17:43:13.517377 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 17:43:13.524089 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 17:43:13.527358 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 17:43:13.530729 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 17:43:13.537292 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 17:43:13.540755 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 17:43:13.543783 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 17:43:13.547450 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 17:43:13.553968 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 17:43:13.557168 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2553 17:43:13.560781 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2554 17:43:13.564221 Total UI for P1: 0, mck2ui 16
2555 17:43:13.567552 best dqsien dly found for B0: ( 1, 3, 28)
2556 17:43:13.574452 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 17:43:13.574540 Total UI for P1: 0, mck2ui 16
2558 17:43:13.580863 best dqsien dly found for B1: ( 1, 4, 0)
2559 17:43:13.584661 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2560 17:43:13.588092 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2561 17:43:13.588171
2562 17:43:13.591404 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2563 17:43:13.594872 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 17:43:13.598147 [Gating] SW calibration Done
2565 17:43:13.598228 ==
2566 17:43:13.601154 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 17:43:13.604627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 17:43:13.604727 ==
2569 17:43:13.604809 RX Vref Scan: 0
2570 17:43:13.607623
2571 17:43:13.607768 RX Vref 0 -> 0, step: 1
2572 17:43:13.607875
2573 17:43:13.611277 RX Delay -40 -> 252, step: 8
2574 17:43:13.614987 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2575 17:43:13.617989 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2576 17:43:13.624884 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2577 17:43:13.628225 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2578 17:43:13.631734 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2579 17:43:13.635008 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2580 17:43:13.638350 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2581 17:43:13.645006 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 17:43:13.648397 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2583 17:43:13.651706 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2584 17:43:13.654968 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2585 17:43:13.658211 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2586 17:43:13.664993 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2587 17:43:13.668247 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2588 17:43:13.671608 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2589 17:43:13.675036 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2590 17:43:13.675118 ==
2591 17:43:13.677909 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 17:43:13.681610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 17:43:13.684723 ==
2594 17:43:13.684804 DQS Delay:
2595 17:43:13.684868 DQS0 = 0, DQS1 = 0
2596 17:43:13.688401 DQM Delay:
2597 17:43:13.688482 DQM0 = 121, DQM1 = 113
2598 17:43:13.691477 DQ Delay:
2599 17:43:13.694957 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2600 17:43:13.698452 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2601 17:43:13.701729 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2602 17:43:13.704820 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2603 17:43:13.704901
2604 17:43:13.704964
2605 17:43:13.705023 ==
2606 17:43:13.708791 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 17:43:13.712080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 17:43:13.712162 ==
2609 17:43:13.712226
2610 17:43:13.712285
2611 17:43:13.715325 TX Vref Scan disable
2612 17:43:13.718720 == TX Byte 0 ==
2613 17:43:13.721568 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2614 17:43:13.725356 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2615 17:43:13.728441 == TX Byte 1 ==
2616 17:43:13.731592 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2617 17:43:13.735243 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2618 17:43:13.735319 ==
2619 17:43:13.738410 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 17:43:13.741643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 17:43:13.741725 ==
2622 17:43:13.755085 TX Vref=22, minBit 0, minWin=25, winSum=412
2623 17:43:13.758438 TX Vref=24, minBit 0, minWin=25, winSum=413
2624 17:43:13.761686 TX Vref=26, minBit 0, minWin=25, winSum=417
2625 17:43:13.765758 TX Vref=28, minBit 1, minWin=26, winSum=428
2626 17:43:13.768998 TX Vref=30, minBit 1, minWin=26, winSum=429
2627 17:43:13.771972 TX Vref=32, minBit 0, minWin=26, winSum=426
2628 17:43:13.779013 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
2629 17:43:13.779095
2630 17:43:13.782408 Final TX Range 1 Vref 30
2631 17:43:13.782490
2632 17:43:13.782554 ==
2633 17:43:13.785568 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 17:43:13.788599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 17:43:13.788681 ==
2636 17:43:13.788747
2637 17:43:13.788807
2638 17:43:13.791684 TX Vref Scan disable
2639 17:43:13.795002 == TX Byte 0 ==
2640 17:43:13.799104 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2641 17:43:13.802294 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2642 17:43:13.805203 == TX Byte 1 ==
2643 17:43:13.808432 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2644 17:43:13.812044 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2645 17:43:13.812126
2646 17:43:13.815080 [DATLAT]
2647 17:43:13.815161 Freq=1200, CH0 RK0
2648 17:43:13.815226
2649 17:43:13.818728 DATLAT Default: 0xd
2650 17:43:13.818809 0, 0xFFFF, sum = 0
2651 17:43:13.821993 1, 0xFFFF, sum = 0
2652 17:43:13.822076 2, 0xFFFF, sum = 0
2653 17:43:13.825185 3, 0xFFFF, sum = 0
2654 17:43:13.825268 4, 0xFFFF, sum = 0
2655 17:43:13.828942 5, 0xFFFF, sum = 0
2656 17:43:13.829024 6, 0xFFFF, sum = 0
2657 17:43:13.832019 7, 0xFFFF, sum = 0
2658 17:43:13.832101 8, 0xFFFF, sum = 0
2659 17:43:13.835098 9, 0xFFFF, sum = 0
2660 17:43:13.835181 10, 0xFFFF, sum = 0
2661 17:43:13.839059 11, 0xFFFF, sum = 0
2662 17:43:13.839142 12, 0x0, sum = 1
2663 17:43:13.842028 13, 0x0, sum = 2
2664 17:43:13.842111 14, 0x0, sum = 3
2665 17:43:13.845694 15, 0x0, sum = 4
2666 17:43:13.845776 best_step = 13
2667 17:43:13.845841
2668 17:43:13.845900 ==
2669 17:43:13.848968 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 17:43:13.855649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 17:43:13.855732 ==
2672 17:43:13.855796 RX Vref Scan: 1
2673 17:43:13.855857
2674 17:43:13.859049 Set Vref Range= 32 -> 127
2675 17:43:13.859130
2676 17:43:13.862408 RX Vref 32 -> 127, step: 1
2677 17:43:13.862489
2678 17:43:13.865777 RX Delay -13 -> 252, step: 4
2679 17:43:13.865858
2680 17:43:13.865923 Set Vref, RX VrefLevel [Byte0]: 32
2681 17:43:13.869155 [Byte1]: 32
2682 17:43:13.873384
2683 17:43:13.873465 Set Vref, RX VrefLevel [Byte0]: 33
2684 17:43:13.877132 [Byte1]: 33
2685 17:43:13.881586
2686 17:43:13.881667 Set Vref, RX VrefLevel [Byte0]: 34
2687 17:43:13.884732 [Byte1]: 34
2688 17:43:13.889404
2689 17:43:13.889511 Set Vref, RX VrefLevel [Byte0]: 35
2690 17:43:13.892626 [Byte1]: 35
2691 17:43:13.896963
2692 17:43:13.897044 Set Vref, RX VrefLevel [Byte0]: 36
2693 17:43:13.900747 [Byte1]: 36
2694 17:43:13.904755
2695 17:43:13.904863 Set Vref, RX VrefLevel [Byte0]: 37
2696 17:43:13.908669 [Byte1]: 37
2697 17:43:13.912876
2698 17:43:13.912958 Set Vref, RX VrefLevel [Byte0]: 38
2699 17:43:13.916164 [Byte1]: 38
2700 17:43:13.920787
2701 17:43:13.920868 Set Vref, RX VrefLevel [Byte0]: 39
2702 17:43:13.923919 [Byte1]: 39
2703 17:43:13.928729
2704 17:43:13.928809 Set Vref, RX VrefLevel [Byte0]: 40
2705 17:43:13.932233 [Byte1]: 40
2706 17:43:13.936533
2707 17:43:13.936614 Set Vref, RX VrefLevel [Byte0]: 41
2708 17:43:13.939588 [Byte1]: 41
2709 17:43:13.944342
2710 17:43:13.944422 Set Vref, RX VrefLevel [Byte0]: 42
2711 17:43:13.947426 [Byte1]: 42
2712 17:43:13.952495
2713 17:43:13.952602 Set Vref, RX VrefLevel [Byte0]: 43
2714 17:43:13.955755 [Byte1]: 43
2715 17:43:13.960336
2716 17:43:13.960417 Set Vref, RX VrefLevel [Byte0]: 44
2717 17:43:13.963728 [Byte1]: 44
2718 17:43:13.968304
2719 17:43:13.968386 Set Vref, RX VrefLevel [Byte0]: 45
2720 17:43:13.971589 [Byte1]: 45
2721 17:43:13.976245
2722 17:43:13.976326 Set Vref, RX VrefLevel [Byte0]: 46
2723 17:43:13.979545 [Byte1]: 46
2724 17:43:13.983544
2725 17:43:13.983675 Set Vref, RX VrefLevel [Byte0]: 47
2726 17:43:13.987431 [Byte1]: 47
2727 17:43:13.991744
2728 17:43:13.991825 Set Vref, RX VrefLevel [Byte0]: 48
2729 17:43:13.995062 [Byte1]: 48
2730 17:43:13.999727
2731 17:43:13.999807 Set Vref, RX VrefLevel [Byte0]: 49
2732 17:43:14.002836 [Byte1]: 49
2733 17:43:14.007747
2734 17:43:14.007848 Set Vref, RX VrefLevel [Byte0]: 50
2735 17:43:14.011074 [Byte1]: 50
2736 17:43:14.015501
2737 17:43:14.015582 Set Vref, RX VrefLevel [Byte0]: 51
2738 17:43:14.018693 [Byte1]: 51
2739 17:43:14.023272
2740 17:43:14.023353 Set Vref, RX VrefLevel [Byte0]: 52
2741 17:43:14.026670 [Byte1]: 52
2742 17:43:14.031175
2743 17:43:14.031256 Set Vref, RX VrefLevel [Byte0]: 53
2744 17:43:14.034371 [Byte1]: 53
2745 17:43:14.039304
2746 17:43:14.039385 Set Vref, RX VrefLevel [Byte0]: 54
2747 17:43:14.042577 [Byte1]: 54
2748 17:43:14.046690
2749 17:43:14.046772 Set Vref, RX VrefLevel [Byte0]: 55
2750 17:43:14.050508 [Byte1]: 55
2751 17:43:14.055274
2752 17:43:14.055356 Set Vref, RX VrefLevel [Byte0]: 56
2753 17:43:14.058135 [Byte1]: 56
2754 17:43:14.063004
2755 17:43:14.063085 Set Vref, RX VrefLevel [Byte0]: 57
2756 17:43:14.066059 [Byte1]: 57
2757 17:43:14.070778
2758 17:43:14.070860 Set Vref, RX VrefLevel [Byte0]: 58
2759 17:43:14.073948 [Byte1]: 58
2760 17:43:14.078539
2761 17:43:14.078620 Set Vref, RX VrefLevel [Byte0]: 59
2762 17:43:14.081888 [Byte1]: 59
2763 17:43:14.086659
2764 17:43:14.086740 Set Vref, RX VrefLevel [Byte0]: 60
2765 17:43:14.089953 [Byte1]: 60
2766 17:43:14.094332
2767 17:43:14.094413 Set Vref, RX VrefLevel [Byte0]: 61
2768 17:43:14.097603 [Byte1]: 61
2769 17:43:14.102246
2770 17:43:14.102328 Set Vref, RX VrefLevel [Byte0]: 62
2771 17:43:14.105664 [Byte1]: 62
2772 17:43:14.110260
2773 17:43:14.110342 Set Vref, RX VrefLevel [Byte0]: 63
2774 17:43:14.113477 [Byte1]: 63
2775 17:43:14.117904
2776 17:43:14.117986 Set Vref, RX VrefLevel [Byte0]: 64
2777 17:43:14.121194 [Byte1]: 64
2778 17:43:14.126129
2779 17:43:14.126220 Set Vref, RX VrefLevel [Byte0]: 65
2780 17:43:14.129415 [Byte1]: 65
2781 17:43:14.134049
2782 17:43:14.134130 Set Vref, RX VrefLevel [Byte0]: 66
2783 17:43:14.137286 [Byte1]: 66
2784 17:43:14.141874
2785 17:43:14.141956 Set Vref, RX VrefLevel [Byte0]: 67
2786 17:43:14.145047 [Byte1]: 67
2787 17:43:14.149686
2788 17:43:14.149769 Set Vref, RX VrefLevel [Byte0]: 68
2789 17:43:14.152891 [Byte1]: 68
2790 17:43:14.157297
2791 17:43:14.157378 Final RX Vref Byte 0 = 54 to rank0
2792 17:43:14.160929 Final RX Vref Byte 1 = 47 to rank0
2793 17:43:14.163976 Final RX Vref Byte 0 = 54 to rank1
2794 17:43:14.167898 Final RX Vref Byte 1 = 47 to rank1==
2795 17:43:14.170988 Dram Type= 6, Freq= 0, CH_0, rank 0
2796 17:43:14.174061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2797 17:43:14.177602 ==
2798 17:43:14.177684 DQS Delay:
2799 17:43:14.177750 DQS0 = 0, DQS1 = 0
2800 17:43:14.180750 DQM Delay:
2801 17:43:14.180832 DQM0 = 120, DQM1 = 111
2802 17:43:14.184040 DQ Delay:
2803 17:43:14.187687 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2804 17:43:14.191017 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2805 17:43:14.194503 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =104
2806 17:43:14.197892 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2807 17:43:14.197975
2808 17:43:14.198040
2809 17:43:14.204159 [DQSOSCAuto] RK0, (LSB)MR18= 0x110a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2810 17:43:14.207371 CH0 RK0: MR19=404, MR18=110A
2811 17:43:14.214017 CH0_RK0: MR19=0x404, MR18=0x110A, DQSOSC=403, MR23=63, INC=40, DEC=26
2812 17:43:14.214099
2813 17:43:14.217980 ----->DramcWriteLeveling(PI) begin...
2814 17:43:14.218063 ==
2815 17:43:14.221057 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 17:43:14.224095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 17:43:14.224177 ==
2818 17:43:14.227984 Write leveling (Byte 0): 36 => 36
2819 17:43:14.230977 Write leveling (Byte 1): 28 => 28
2820 17:43:14.234323 DramcWriteLeveling(PI) end<-----
2821 17:43:14.234404
2822 17:43:14.234469 ==
2823 17:43:14.237674 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 17:43:14.244427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 17:43:14.244510 ==
2826 17:43:14.244575 [Gating] SW mode calibration
2827 17:43:14.254091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2828 17:43:14.257847 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2829 17:43:14.260696 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
2830 17:43:14.267800 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 17:43:14.271007 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 17:43:14.274675 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 17:43:14.280746 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 17:43:14.284446 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 17:43:14.287859 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2836 17:43:14.293961 0 15 28 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (1 0)
2837 17:43:14.297327 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 17:43:14.300653 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 17:43:14.307221 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 17:43:14.311104 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 17:43:14.314322 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 17:43:14.321066 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 17:43:14.324408 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 17:43:14.327603 1 0 28 | B1->B0 | 3434 3737 | 0 0 | (0 0) (0 0)
2845 17:43:14.334359 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 17:43:14.337381 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 17:43:14.341020 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 17:43:14.344243 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 17:43:14.351020 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 17:43:14.354288 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 17:43:14.357434 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 17:43:14.364393 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2853 17:43:14.367781 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 17:43:14.370642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 17:43:14.377452 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 17:43:14.381211 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 17:43:14.384304 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 17:43:14.391065 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 17:43:14.393990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 17:43:14.397709 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 17:43:14.404432 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 17:43:14.407482 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 17:43:14.410768 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 17:43:14.417272 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 17:43:14.421278 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 17:43:14.424606 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 17:43:14.431254 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 17:43:14.434510 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2869 17:43:14.437563 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2870 17:43:14.441182 Total UI for P1: 0, mck2ui 16
2871 17:43:14.444331 best dqsien dly found for B1: ( 1, 3, 28)
2872 17:43:14.447417 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 17:43:14.451242 Total UI for P1: 0, mck2ui 16
2874 17:43:14.454743 best dqsien dly found for B0: ( 1, 3, 30)
2875 17:43:14.458002 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2876 17:43:14.461294 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2877 17:43:14.461366
2878 17:43:14.467600 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2879 17:43:14.471183 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2880 17:43:14.471284 [Gating] SW calibration Done
2881 17:43:14.474251 ==
2882 17:43:14.477709 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 17:43:14.481023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 17:43:14.481126 ==
2885 17:43:14.481217 RX Vref Scan: 0
2886 17:43:14.481305
2887 17:43:14.484285 RX Vref 0 -> 0, step: 1
2888 17:43:14.484360
2889 17:43:14.488024 RX Delay -40 -> 252, step: 8
2890 17:43:14.491211 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2891 17:43:14.494595 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2892 17:43:14.497763 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2893 17:43:14.504647 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2894 17:43:14.507982 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2895 17:43:14.511218 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2896 17:43:14.514849 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2897 17:43:14.517811 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2898 17:43:14.524471 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2899 17:43:14.528161 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2900 17:43:14.531407 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2901 17:43:14.534728 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2902 17:43:14.538085 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2903 17:43:14.545096 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2904 17:43:14.548048 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2905 17:43:14.551302 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2906 17:43:14.551396 ==
2907 17:43:14.554537 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 17:43:14.558246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 17:43:14.558345 ==
2910 17:43:14.561600 DQS Delay:
2911 17:43:14.561671 DQS0 = 0, DQS1 = 0
2912 17:43:14.564872 DQM Delay:
2913 17:43:14.564944 DQM0 = 122, DQM1 = 112
2914 17:43:14.565004 DQ Delay:
2915 17:43:14.568231 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2916 17:43:14.571426 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2917 17:43:14.577917 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2918 17:43:14.581561 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2919 17:43:14.581663
2920 17:43:14.581754
2921 17:43:14.581843 ==
2922 17:43:14.584613 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 17:43:14.587989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 17:43:14.588061 ==
2925 17:43:14.588122
2926 17:43:14.588180
2927 17:43:14.591281 TX Vref Scan disable
2928 17:43:14.591355 == TX Byte 0 ==
2929 17:43:14.598595 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2930 17:43:14.601964 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2931 17:43:14.602066 == TX Byte 1 ==
2932 17:43:14.608649 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2933 17:43:14.611876 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2934 17:43:14.611949 ==
2935 17:43:14.615100 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 17:43:14.618497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 17:43:14.618596 ==
2938 17:43:14.632051 TX Vref=22, minBit 3, minWin=25, winSum=418
2939 17:43:14.635135 TX Vref=24, minBit 4, minWin=25, winSum=422
2940 17:43:14.638661 TX Vref=26, minBit 1, minWin=26, winSum=428
2941 17:43:14.641635 TX Vref=28, minBit 1, minWin=26, winSum=427
2942 17:43:14.644997 TX Vref=30, minBit 12, minWin=25, winSum=427
2943 17:43:14.651527 TX Vref=32, minBit 1, minWin=25, winSum=428
2944 17:43:14.655183 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 26
2945 17:43:14.655281
2946 17:43:14.658534 Final TX Range 1 Vref 26
2947 17:43:14.658632
2948 17:43:14.658721 ==
2949 17:43:14.661674 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 17:43:14.665382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 17:43:14.665453 ==
2952 17:43:14.668631
2953 17:43:14.668727
2954 17:43:14.668808 TX Vref Scan disable
2955 17:43:14.671879 == TX Byte 0 ==
2956 17:43:14.675115 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2957 17:43:14.678437 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2958 17:43:14.681803 == TX Byte 1 ==
2959 17:43:14.684945 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2960 17:43:14.688609 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2961 17:43:14.691712
2962 17:43:14.691784 [DATLAT]
2963 17:43:14.691846 Freq=1200, CH0 RK1
2964 17:43:14.691905
2965 17:43:14.695077 DATLAT Default: 0xd
2966 17:43:14.695160 0, 0xFFFF, sum = 0
2967 17:43:14.698226 1, 0xFFFF, sum = 0
2968 17:43:14.698309 2, 0xFFFF, sum = 0
2969 17:43:14.702176 3, 0xFFFF, sum = 0
2970 17:43:14.702259 4, 0xFFFF, sum = 0
2971 17:43:14.705574 5, 0xFFFF, sum = 0
2972 17:43:14.705656 6, 0xFFFF, sum = 0
2973 17:43:14.708355 7, 0xFFFF, sum = 0
2974 17:43:14.711674 8, 0xFFFF, sum = 0
2975 17:43:14.711772 9, 0xFFFF, sum = 0
2976 17:43:14.714950 10, 0xFFFF, sum = 0
2977 17:43:14.715033 11, 0xFFFF, sum = 0
2978 17:43:14.718791 12, 0x0, sum = 1
2979 17:43:14.718874 13, 0x0, sum = 2
2980 17:43:14.721765 14, 0x0, sum = 3
2981 17:43:14.721847 15, 0x0, sum = 4
2982 17:43:14.721913 best_step = 13
2983 17:43:14.721973
2984 17:43:14.725135 ==
2985 17:43:14.725217 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 17:43:14.732242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 17:43:14.732324 ==
2988 17:43:14.732389 RX Vref Scan: 0
2989 17:43:14.732449
2990 17:43:14.735619 RX Vref 0 -> 0, step: 1
2991 17:43:14.735735
2992 17:43:14.738565 RX Delay -13 -> 252, step: 4
2993 17:43:14.741881 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2994 17:43:14.745665 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2995 17:43:14.752223 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2996 17:43:14.755172 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2997 17:43:14.758815 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2998 17:43:14.762005 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
2999 17:43:14.765398 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3000 17:43:14.772199 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3001 17:43:14.775525 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3002 17:43:14.778794 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3003 17:43:14.782164 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3004 17:43:14.785599 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3005 17:43:14.791863 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3006 17:43:14.795848 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3007 17:43:14.798748 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3008 17:43:14.802392 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3009 17:43:14.802492 ==
3010 17:43:14.805637 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 17:43:14.812253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 17:43:14.812338 ==
3013 17:43:14.812418 DQS Delay:
3014 17:43:14.812493 DQS0 = 0, DQS1 = 0
3015 17:43:14.815670 DQM Delay:
3016 17:43:14.815767 DQM0 = 120, DQM1 = 109
3017 17:43:14.818976 DQ Delay:
3018 17:43:14.822181 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3019 17:43:14.825423 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3020 17:43:14.828612 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3021 17:43:14.832420 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3022 17:43:14.832495
3023 17:43:14.832585
3024 17:43:14.839086 [DQSOSCAuto] RK1, (LSB)MR18= 0xaeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3025 17:43:14.842308 CH0 RK1: MR19=403, MR18=AEB
3026 17:43:14.848738 CH0_RK1: MR19=0x403, MR18=0xAEB, DQSOSC=406, MR23=63, INC=39, DEC=26
3027 17:43:14.851995 [RxdqsGatingPostProcess] freq 1200
3028 17:43:14.859133 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3029 17:43:14.859210 best DQS0 dly(2T, 0.5T) = (0, 11)
3030 17:43:14.862075 best DQS1 dly(2T, 0.5T) = (0, 12)
3031 17:43:14.865443 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3032 17:43:14.869303 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3033 17:43:14.872633 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 17:43:14.875706 best DQS1 dly(2T, 0.5T) = (0, 11)
3035 17:43:14.878801 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 17:43:14.882325 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3037 17:43:14.885627 Pre-setting of DQS Precalculation
3038 17:43:14.888928 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3039 17:43:14.892221 ==
3040 17:43:14.892296 Dram Type= 6, Freq= 0, CH_1, rank 0
3041 17:43:14.899309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 17:43:14.899414 ==
3043 17:43:14.902663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3044 17:43:14.908893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3045 17:43:14.918439 [CA 0] Center 37 (7~68) winsize 62
3046 17:43:14.921768 [CA 1] Center 37 (7~68) winsize 62
3047 17:43:14.925114 [CA 2] Center 35 (5~65) winsize 61
3048 17:43:14.927811 [CA 3] Center 34 (4~64) winsize 61
3049 17:43:14.931002 [CA 4] Center 34 (4~64) winsize 61
3050 17:43:14.934386 [CA 5] Center 33 (3~63) winsize 61
3051 17:43:14.934485
3052 17:43:14.937981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3053 17:43:14.938079
3054 17:43:14.941285 [CATrainingPosCal] consider 1 rank data
3055 17:43:14.944365 u2DelayCellTimex100 = 270/100 ps
3056 17:43:14.947625 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3057 17:43:14.954780 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3058 17:43:14.958203 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3059 17:43:14.961524 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3060 17:43:14.964803 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3061 17:43:14.967546 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3062 17:43:14.967650
3063 17:43:14.971508 CA PerBit enable=1, Macro0, CA PI delay=33
3064 17:43:14.971608
3065 17:43:14.974621 [CBTSetCACLKResult] CA Dly = 33
3066 17:43:14.974719 CS Dly: 8 (0~39)
3067 17:43:14.978092 ==
3068 17:43:14.978189 Dram Type= 6, Freq= 0, CH_1, rank 1
3069 17:43:14.984761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 17:43:14.984839 ==
3071 17:43:14.987829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 17:43:14.994669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3073 17:43:15.003970 [CA 0] Center 37 (7~68) winsize 62
3074 17:43:15.007249 [CA 1] Center 38 (8~69) winsize 62
3075 17:43:15.010568 [CA 2] Center 35 (5~65) winsize 61
3076 17:43:15.013843 [CA 3] Center 34 (4~65) winsize 62
3077 17:43:15.016959 [CA 4] Center 35 (5~65) winsize 61
3078 17:43:15.020532 [CA 5] Center 34 (4~64) winsize 61
3079 17:43:15.020633
3080 17:43:15.023698 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3081 17:43:15.023795
3082 17:43:15.027187 [CATrainingPosCal] consider 2 rank data
3083 17:43:15.030543 u2DelayCellTimex100 = 270/100 ps
3084 17:43:15.033972 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 17:43:15.037215 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3086 17:43:15.040404 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 17:43:15.047501 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 17:43:15.050500 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3089 17:43:15.053787 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3090 17:43:15.053860
3091 17:43:15.057007 CA PerBit enable=1, Macro0, CA PI delay=33
3092 17:43:15.057104
3093 17:43:15.060820 [CBTSetCACLKResult] CA Dly = 33
3094 17:43:15.060892 CS Dly: 8 (0~40)
3095 17:43:15.060953
3096 17:43:15.063908 ----->DramcWriteLeveling(PI) begin...
3097 17:43:15.063986 ==
3098 17:43:15.067297 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 17:43:15.074053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 17:43:15.074156 ==
3101 17:43:15.077410 Write leveling (Byte 0): 26 => 26
3102 17:43:15.080721 Write leveling (Byte 1): 27 => 27
3103 17:43:15.080795 DramcWriteLeveling(PI) end<-----
3104 17:43:15.080861
3105 17:43:15.083945 ==
3106 17:43:15.087094 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 17:43:15.090733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 17:43:15.090808 ==
3109 17:43:15.093961 [Gating] SW mode calibration
3110 17:43:15.100821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3111 17:43:15.103867 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3112 17:43:15.110861 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 17:43:15.114197 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 17:43:15.117194 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 17:43:15.123896 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 17:43:15.127511 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 17:43:15.130511 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 17:43:15.137163 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
3119 17:43:15.140536 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3120 17:43:15.143871 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 17:43:15.147200 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 17:43:15.153857 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 17:43:15.157244 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 17:43:15.160909 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 17:43:15.167345 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 17:43:15.170534 1 0 24 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (1 1)
3127 17:43:15.174345 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 17:43:15.181065 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 17:43:15.184515 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 17:43:15.187758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 17:43:15.194283 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 17:43:15.197479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 17:43:15.200816 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 17:43:15.207608 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3135 17:43:15.211100 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3136 17:43:15.214401 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 17:43:15.221059 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 17:43:15.224018 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 17:43:15.227551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 17:43:15.234040 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 17:43:15.237458 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 17:43:15.241093 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 17:43:15.244423 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 17:43:15.251036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 17:43:15.254285 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 17:43:15.257698 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 17:43:15.264205 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 17:43:15.267387 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 17:43:15.270568 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 17:43:15.277128 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3151 17:43:15.280992 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 17:43:15.284360 Total UI for P1: 0, mck2ui 16
3153 17:43:15.287615 best dqsien dly found for B0: ( 1, 3, 24)
3154 17:43:15.291086 Total UI for P1: 0, mck2ui 16
3155 17:43:15.294272 best dqsien dly found for B1: ( 1, 3, 24)
3156 17:43:15.297619 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3157 17:43:15.300696 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3158 17:43:15.300771
3159 17:43:15.303951 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3160 17:43:15.307556 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3161 17:43:15.310617 [Gating] SW calibration Done
3162 17:43:15.310719 ==
3163 17:43:15.314057 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 17:43:15.317592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 17:43:15.320776 ==
3166 17:43:15.320875 RX Vref Scan: 0
3167 17:43:15.320965
3168 17:43:15.324034 RX Vref 0 -> 0, step: 1
3169 17:43:15.324132
3170 17:43:15.324220 RX Delay -40 -> 252, step: 8
3171 17:43:15.330823 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3172 17:43:15.334583 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3173 17:43:15.337706 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3174 17:43:15.340891 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3175 17:43:15.344625 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3176 17:43:15.350967 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3177 17:43:15.354613 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3178 17:43:15.357537 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3179 17:43:15.361279 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3180 17:43:15.364544 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3181 17:43:15.371063 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3182 17:43:15.374274 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3183 17:43:15.377857 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3184 17:43:15.381204 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3185 17:43:15.384654 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3186 17:43:15.391597 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3187 17:43:15.391704 ==
3188 17:43:15.394952 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 17:43:15.398272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 17:43:15.398355 ==
3191 17:43:15.398419 DQS Delay:
3192 17:43:15.401665 DQS0 = 0, DQS1 = 0
3193 17:43:15.401747 DQM Delay:
3194 17:43:15.404812 DQM0 = 120, DQM1 = 116
3195 17:43:15.404893 DQ Delay:
3196 17:43:15.408188 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3197 17:43:15.411335 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3198 17:43:15.414486 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3199 17:43:15.418055 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3200 17:43:15.418132
3201 17:43:15.418196
3202 17:43:15.421402 ==
3203 17:43:15.421472 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 17:43:15.428072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 17:43:15.428172 ==
3206 17:43:15.428263
3207 17:43:15.428352
3208 17:43:15.431461 TX Vref Scan disable
3209 17:43:15.431533 == TX Byte 0 ==
3210 17:43:15.434602 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3211 17:43:15.441490 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3212 17:43:15.441591 == TX Byte 1 ==
3213 17:43:15.444451 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3214 17:43:15.450982 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3215 17:43:15.451062 ==
3216 17:43:15.454899 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 17:43:15.458197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 17:43:15.458296 ==
3219 17:43:15.469302 TX Vref=22, minBit 9, minWin=24, winSum=408
3220 17:43:15.472647 TX Vref=24, minBit 9, minWin=24, winSum=416
3221 17:43:15.476455 TX Vref=26, minBit 9, minWin=25, winSum=422
3222 17:43:15.479583 TX Vref=28, minBit 2, minWin=26, winSum=427
3223 17:43:15.482722 TX Vref=30, minBit 9, minWin=25, winSum=429
3224 17:43:15.489274 TX Vref=32, minBit 10, minWin=25, winSum=431
3225 17:43:15.492586 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 28
3226 17:43:15.492662
3227 17:43:15.496421 Final TX Range 1 Vref 28
3228 17:43:15.496492
3229 17:43:15.496554 ==
3230 17:43:15.499560 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 17:43:15.502732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 17:43:15.502810 ==
3233 17:43:15.502873
3234 17:43:15.506074
3235 17:43:15.506145 TX Vref Scan disable
3236 17:43:15.509319 == TX Byte 0 ==
3237 17:43:15.512574 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3238 17:43:15.515898 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3239 17:43:15.519178 == TX Byte 1 ==
3240 17:43:15.522398 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3241 17:43:15.526151 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3242 17:43:15.526223
3243 17:43:15.529167 [DATLAT]
3244 17:43:15.529242 Freq=1200, CH1 RK0
3245 17:43:15.529306
3246 17:43:15.532565 DATLAT Default: 0xd
3247 17:43:15.532661 0, 0xFFFF, sum = 0
3248 17:43:15.535870 1, 0xFFFF, sum = 0
3249 17:43:15.535943 2, 0xFFFF, sum = 0
3250 17:43:15.539207 3, 0xFFFF, sum = 0
3251 17:43:15.539305 4, 0xFFFF, sum = 0
3252 17:43:15.542503 5, 0xFFFF, sum = 0
3253 17:43:15.542602 6, 0xFFFF, sum = 0
3254 17:43:15.545854 7, 0xFFFF, sum = 0
3255 17:43:15.545952 8, 0xFFFF, sum = 0
3256 17:43:15.549454 9, 0xFFFF, sum = 0
3257 17:43:15.552498 10, 0xFFFF, sum = 0
3258 17:43:15.552572 11, 0xFFFF, sum = 0
3259 17:43:15.556489 12, 0x0, sum = 1
3260 17:43:15.556562 13, 0x0, sum = 2
3261 17:43:15.556646 14, 0x0, sum = 3
3262 17:43:15.559569 15, 0x0, sum = 4
3263 17:43:15.559727 best_step = 13
3264 17:43:15.559805
3265 17:43:15.562954 ==
3266 17:43:15.563032 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 17:43:15.569598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 17:43:15.569699 ==
3269 17:43:15.569790 RX Vref Scan: 1
3270 17:43:15.569853
3271 17:43:15.572932 Set Vref Range= 32 -> 127
3272 17:43:15.573030
3273 17:43:15.576255 RX Vref 32 -> 127, step: 1
3274 17:43:15.576330
3275 17:43:15.579184 RX Delay -5 -> 252, step: 4
3276 17:43:15.579282
3277 17:43:15.582736 Set Vref, RX VrefLevel [Byte0]: 32
3278 17:43:15.585871 [Byte1]: 32
3279 17:43:15.585970
3280 17:43:15.589215 Set Vref, RX VrefLevel [Byte0]: 33
3281 17:43:15.592568 [Byte1]: 33
3282 17:43:15.592659
3283 17:43:15.596140 Set Vref, RX VrefLevel [Byte0]: 34
3284 17:43:15.599492 [Byte1]: 34
3285 17:43:15.603366
3286 17:43:15.603468 Set Vref, RX VrefLevel [Byte0]: 35
3287 17:43:15.606350 [Byte1]: 35
3288 17:43:15.610987
3289 17:43:15.611060 Set Vref, RX VrefLevel [Byte0]: 36
3290 17:43:15.614803 [Byte1]: 36
3291 17:43:15.618788
3292 17:43:15.618861 Set Vref, RX VrefLevel [Byte0]: 37
3293 17:43:15.622220 [Byte1]: 37
3294 17:43:15.626830
3295 17:43:15.626929 Set Vref, RX VrefLevel [Byte0]: 38
3296 17:43:15.630006 [Byte1]: 38
3297 17:43:15.634986
3298 17:43:15.635084 Set Vref, RX VrefLevel [Byte0]: 39
3299 17:43:15.638059 [Byte1]: 39
3300 17:43:15.642599
3301 17:43:15.642703 Set Vref, RX VrefLevel [Byte0]: 40
3302 17:43:15.645773 [Byte1]: 40
3303 17:43:15.650388
3304 17:43:15.650486 Set Vref, RX VrefLevel [Byte0]: 41
3305 17:43:15.653567 [Byte1]: 41
3306 17:43:15.657946
3307 17:43:15.658044 Set Vref, RX VrefLevel [Byte0]: 42
3308 17:43:15.661191 [Byte1]: 42
3309 17:43:15.665930
3310 17:43:15.666029 Set Vref, RX VrefLevel [Byte0]: 43
3311 17:43:15.669257 [Byte1]: 43
3312 17:43:15.673932
3313 17:43:15.674031 Set Vref, RX VrefLevel [Byte0]: 44
3314 17:43:15.677377 [Byte1]: 44
3315 17:43:15.681997
3316 17:43:15.682096 Set Vref, RX VrefLevel [Byte0]: 45
3317 17:43:15.685236 [Byte1]: 45
3318 17:43:15.689857
3319 17:43:15.689953 Set Vref, RX VrefLevel [Byte0]: 46
3320 17:43:15.692658 [Byte1]: 46
3321 17:43:15.697388
3322 17:43:15.697458 Set Vref, RX VrefLevel [Byte0]: 47
3323 17:43:15.700956 [Byte1]: 47
3324 17:43:15.705255
3325 17:43:15.705330 Set Vref, RX VrefLevel [Byte0]: 48
3326 17:43:15.708667 [Byte1]: 48
3327 17:43:15.713277
3328 17:43:15.713351 Set Vref, RX VrefLevel [Byte0]: 49
3329 17:43:15.716652 [Byte1]: 49
3330 17:43:15.721082
3331 17:43:15.721186 Set Vref, RX VrefLevel [Byte0]: 50
3332 17:43:15.724422 [Byte1]: 50
3333 17:43:15.728818
3334 17:43:15.728891 Set Vref, RX VrefLevel [Byte0]: 51
3335 17:43:15.732155 [Byte1]: 51
3336 17:43:15.736602
3337 17:43:15.736706 Set Vref, RX VrefLevel [Byte0]: 52
3338 17:43:15.739838 [Byte1]: 52
3339 17:43:15.744501
3340 17:43:15.744618 Set Vref, RX VrefLevel [Byte0]: 53
3341 17:43:15.747542 [Byte1]: 53
3342 17:43:15.752698
3343 17:43:15.752777 Set Vref, RX VrefLevel [Byte0]: 54
3344 17:43:15.755427 [Byte1]: 54
3345 17:43:15.760087
3346 17:43:15.760161 Set Vref, RX VrefLevel [Byte0]: 55
3347 17:43:15.763294 [Byte1]: 55
3348 17:43:15.768513
3349 17:43:15.768588 Set Vref, RX VrefLevel [Byte0]: 56
3350 17:43:15.771491 [Byte1]: 56
3351 17:43:15.776162
3352 17:43:15.776238 Set Vref, RX VrefLevel [Byte0]: 57
3353 17:43:15.779372 [Byte1]: 57
3354 17:43:15.783999
3355 17:43:15.784072 Set Vref, RX VrefLevel [Byte0]: 58
3356 17:43:15.787291 [Byte1]: 58
3357 17:43:15.791789
3358 17:43:15.791880 Set Vref, RX VrefLevel [Byte0]: 59
3359 17:43:15.795098 [Byte1]: 59
3360 17:43:15.799733
3361 17:43:15.799817 Set Vref, RX VrefLevel [Byte0]: 60
3362 17:43:15.803060 [Byte1]: 60
3363 17:43:15.807773
3364 17:43:15.807857 Set Vref, RX VrefLevel [Byte0]: 61
3365 17:43:15.810487 [Byte1]: 61
3366 17:43:15.815065
3367 17:43:15.815163 Set Vref, RX VrefLevel [Byte0]: 62
3368 17:43:15.818400 [Byte1]: 62
3369 17:43:15.823143
3370 17:43:15.823247 Set Vref, RX VrefLevel [Byte0]: 63
3371 17:43:15.826163 [Byte1]: 63
3372 17:43:15.830861
3373 17:43:15.830939 Set Vref, RX VrefLevel [Byte0]: 64
3374 17:43:15.834144 [Byte1]: 64
3375 17:43:15.838820
3376 17:43:15.838896 Set Vref, RX VrefLevel [Byte0]: 65
3377 17:43:15.841944 [Byte1]: 65
3378 17:43:15.846467
3379 17:43:15.846566 Set Vref, RX VrefLevel [Byte0]: 66
3380 17:43:15.849781 [Byte1]: 66
3381 17:43:15.854289
3382 17:43:15.854390 Set Vref, RX VrefLevel [Byte0]: 67
3383 17:43:15.857670 [Byte1]: 67
3384 17:43:15.862446
3385 17:43:15.862547 Set Vref, RX VrefLevel [Byte0]: 68
3386 17:43:15.865641 [Byte1]: 68
3387 17:43:15.870210
3388 17:43:15.870284 Final RX Vref Byte 0 = 52 to rank0
3389 17:43:15.873581 Final RX Vref Byte 1 = 51 to rank0
3390 17:43:15.876701 Final RX Vref Byte 0 = 52 to rank1
3391 17:43:15.880241 Final RX Vref Byte 1 = 51 to rank1==
3392 17:43:15.883432 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 17:43:15.889923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 17:43:15.890024 ==
3395 17:43:15.890115 DQS Delay:
3396 17:43:15.890205 DQS0 = 0, DQS1 = 0
3397 17:43:15.893285 DQM Delay:
3398 17:43:15.893366 DQM0 = 120, DQM1 = 117
3399 17:43:15.896585 DQ Delay:
3400 17:43:15.900033 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3401 17:43:15.903953 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3402 17:43:15.907257 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3403 17:43:15.910524 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3404 17:43:15.910598
3405 17:43:15.910659
3406 17:43:15.917269 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3407 17:43:15.920602 CH1 RK0: MR19=304, MR18=FE11
3408 17:43:15.927160 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3409 17:43:15.927268
3410 17:43:15.930434 ----->DramcWriteLeveling(PI) begin...
3411 17:43:15.930509 ==
3412 17:43:15.933684 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 17:43:15.936978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 17:43:15.940376 ==
3415 17:43:15.940449 Write leveling (Byte 0): 26 => 26
3416 17:43:15.943654 Write leveling (Byte 1): 29 => 29
3417 17:43:15.947063 DramcWriteLeveling(PI) end<-----
3418 17:43:15.947162
3419 17:43:15.947241 ==
3420 17:43:15.950406 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 17:43:15.957233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 17:43:15.957335 ==
3423 17:43:15.957427 [Gating] SW mode calibration
3424 17:43:15.966754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3425 17:43:15.970012 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3426 17:43:15.973440 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3427 17:43:15.980379 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 17:43:15.983568 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 17:43:15.987136 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 17:43:15.993503 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 17:43:15.997064 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 17:43:16.000654 0 15 24 | B1->B0 | 2d2d 3333 | 0 1 | (1 0) (1 0)
3433 17:43:16.007277 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
3434 17:43:16.010613 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 17:43:16.013915 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 17:43:16.020709 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 17:43:16.024091 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 17:43:16.027261 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 17:43:16.033905 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3440 17:43:16.037270 1 0 24 | B1->B0 | 4646 2a2a | 0 0 | (0 0) (0 0)
3441 17:43:16.040593 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3442 17:43:16.043902 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 17:43:16.050597 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 17:43:16.053958 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 17:43:16.057348 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 17:43:16.063875 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 17:43:16.067165 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 17:43:16.070604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3449 17:43:16.077113 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3450 17:43:16.080245 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 17:43:16.083437 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 17:43:16.090298 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 17:43:16.093818 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 17:43:16.096935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 17:43:16.103767 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 17:43:16.106846 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 17:43:16.110668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 17:43:16.116971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 17:43:16.120333 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 17:43:16.123425 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 17:43:16.129986 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 17:43:16.133216 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 17:43:16.136548 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3464 17:43:16.143598 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3465 17:43:16.146853 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3466 17:43:16.150174 Total UI for P1: 0, mck2ui 16
3467 17:43:16.153649 best dqsien dly found for B1: ( 1, 3, 22)
3468 17:43:16.156974 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 17:43:16.160039 Total UI for P1: 0, mck2ui 16
3470 17:43:16.163267 best dqsien dly found for B0: ( 1, 3, 26)
3471 17:43:16.166655 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3472 17:43:16.170581 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3473 17:43:16.170654
3474 17:43:16.174002 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3475 17:43:16.177225 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3476 17:43:16.180297 [Gating] SW calibration Done
3477 17:43:16.180397 ==
3478 17:43:16.183518 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 17:43:16.190529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 17:43:16.190635 ==
3481 17:43:16.190728 RX Vref Scan: 0
3482 17:43:16.190819
3483 17:43:16.193946 RX Vref 0 -> 0, step: 1
3484 17:43:16.194043
3485 17:43:16.197151 RX Delay -40 -> 252, step: 8
3486 17:43:16.200346 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3487 17:43:16.203440 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3488 17:43:16.207122 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3489 17:43:16.210178 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3490 17:43:16.216679 iDelay=200, Bit 4, Center 115 (56 ~ 175) 120
3491 17:43:16.219994 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3492 17:43:16.223926 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3493 17:43:16.227058 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3494 17:43:16.230097 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3495 17:43:16.236813 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3496 17:43:16.240374 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3497 17:43:16.243254 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3498 17:43:16.246874 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3499 17:43:16.253256 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3500 17:43:16.256562 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3501 17:43:16.259931 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3502 17:43:16.260031 ==
3503 17:43:16.263226 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 17:43:16.266556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 17:43:16.266655 ==
3506 17:43:16.269824 DQS Delay:
3507 17:43:16.269922 DQS0 = 0, DQS1 = 0
3508 17:43:16.273221 DQM Delay:
3509 17:43:16.273318 DQM0 = 120, DQM1 = 117
3510 17:43:16.273408 DQ Delay:
3511 17:43:16.276616 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3512 17:43:16.283161 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3513 17:43:16.286467 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3514 17:43:16.289739 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3515 17:43:16.289837
3516 17:43:16.289926
3517 17:43:16.290014 ==
3518 17:43:16.293490 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 17:43:16.296661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 17:43:16.296739 ==
3521 17:43:16.296802
3522 17:43:16.296865
3523 17:43:16.299957 TX Vref Scan disable
3524 17:43:16.303286 == TX Byte 0 ==
3525 17:43:16.306177 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3526 17:43:16.309689 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3527 17:43:16.313421 == TX Byte 1 ==
3528 17:43:16.316535 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3529 17:43:16.319582 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3530 17:43:16.319716 ==
3531 17:43:16.323249 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 17:43:16.326595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 17:43:16.329852 ==
3534 17:43:16.339700 TX Vref=22, minBit 1, minWin=26, winSum=422
3535 17:43:16.342937 TX Vref=24, minBit 1, minWin=26, winSum=425
3536 17:43:16.346377 TX Vref=26, minBit 10, minWin=25, winSum=433
3537 17:43:16.349662 TX Vref=28, minBit 2, minWin=26, winSum=429
3538 17:43:16.352957 TX Vref=30, minBit 9, minWin=26, winSum=436
3539 17:43:16.359705 TX Vref=32, minBit 9, minWin=26, winSum=437
3540 17:43:16.362650 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 32
3541 17:43:16.362723
3542 17:43:16.366233 Final TX Range 1 Vref 32
3543 17:43:16.366331
3544 17:43:16.366423 ==
3545 17:43:16.369164 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 17:43:16.372627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 17:43:16.372703 ==
3548 17:43:16.375935
3549 17:43:16.376017
3550 17:43:16.376083 TX Vref Scan disable
3551 17:43:16.379783 == TX Byte 0 ==
3552 17:43:16.382572 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3553 17:43:16.386524 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3554 17:43:16.389153 == TX Byte 1 ==
3555 17:43:16.392409 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3556 17:43:16.399095 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3557 17:43:16.399199
3558 17:43:16.399290 [DATLAT]
3559 17:43:16.399381 Freq=1200, CH1 RK1
3560 17:43:16.399467
3561 17:43:16.402832 DATLAT Default: 0xd
3562 17:43:16.402905 0, 0xFFFF, sum = 0
3563 17:43:16.405725 1, 0xFFFF, sum = 0
3564 17:43:16.405831 2, 0xFFFF, sum = 0
3565 17:43:16.409005 3, 0xFFFF, sum = 0
3566 17:43:16.413033 4, 0xFFFF, sum = 0
3567 17:43:16.413120 5, 0xFFFF, sum = 0
3568 17:43:16.416096 6, 0xFFFF, sum = 0
3569 17:43:16.416195 7, 0xFFFF, sum = 0
3570 17:43:16.419480 8, 0xFFFF, sum = 0
3571 17:43:16.419580 9, 0xFFFF, sum = 0
3572 17:43:16.422649 10, 0xFFFF, sum = 0
3573 17:43:16.422749 11, 0xFFFF, sum = 0
3574 17:43:16.425845 12, 0x0, sum = 1
3575 17:43:16.425950 13, 0x0, sum = 2
3576 17:43:16.428981 14, 0x0, sum = 3
3577 17:43:16.429081 15, 0x0, sum = 4
3578 17:43:16.432284 best_step = 13
3579 17:43:16.432357
3580 17:43:16.432420 ==
3581 17:43:16.435732 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 17:43:16.438854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 17:43:16.438954 ==
3584 17:43:16.439044 RX Vref Scan: 0
3585 17:43:16.439133
3586 17:43:16.442616 RX Vref 0 -> 0, step: 1
3587 17:43:16.442714
3588 17:43:16.445964 RX Delay -5 -> 252, step: 4
3589 17:43:16.449370 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3590 17:43:16.456036 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3591 17:43:16.459328 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3592 17:43:16.462708 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3593 17:43:16.466049 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3594 17:43:16.469166 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3595 17:43:16.475866 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3596 17:43:16.479013 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3597 17:43:16.482111 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3598 17:43:16.485546 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3599 17:43:16.488622 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3600 17:43:16.495482 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3601 17:43:16.498657 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3602 17:43:16.501866 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3603 17:43:16.505223 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3604 17:43:16.512228 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3605 17:43:16.512304 ==
3606 17:43:16.515196 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 17:43:16.518748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 17:43:16.518823 ==
3609 17:43:16.518889 DQS Delay:
3610 17:43:16.521989 DQS0 = 0, DQS1 = 0
3611 17:43:16.522086 DQM Delay:
3612 17:43:16.525260 DQM0 = 120, DQM1 = 118
3613 17:43:16.525358 DQ Delay:
3614 17:43:16.528511 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3615 17:43:16.532189 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3616 17:43:16.535293 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3617 17:43:16.538645 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3618 17:43:16.538744
3619 17:43:16.538833
3620 17:43:16.548867 [DQSOSCAuto] RK1, (LSB)MR18= 0xeeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3621 17:43:16.552091 CH1 RK1: MR19=403, MR18=EEB
3622 17:43:16.555416 CH1_RK1: MR19=0x403, MR18=0xEEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3623 17:43:16.558657 [RxdqsGatingPostProcess] freq 1200
3624 17:43:16.565455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3625 17:43:16.568693 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 17:43:16.571871 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 17:43:16.575211 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 17:43:16.578610 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 17:43:16.581933 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 17:43:16.585731 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 17:43:16.588516 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 17:43:16.591714 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 17:43:16.591813 Pre-setting of DQS Precalculation
3634 17:43:16.598389 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3635 17:43:16.605267 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3636 17:43:16.611784 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3637 17:43:16.611865
3638 17:43:16.611930
3639 17:43:16.615291 [Calibration Summary] 2400 Mbps
3640 17:43:16.618433 CH 0, Rank 0
3641 17:43:16.618535 SW Impedance : PASS
3642 17:43:16.621711 DUTY Scan : NO K
3643 17:43:16.624803 ZQ Calibration : PASS
3644 17:43:16.624902 Jitter Meter : NO K
3645 17:43:16.628379 CBT Training : PASS
3646 17:43:16.631684 Write leveling : PASS
3647 17:43:16.631785 RX DQS gating : PASS
3648 17:43:16.634658 RX DQ/DQS(RDDQC) : PASS
3649 17:43:16.634758 TX DQ/DQS : PASS
3650 17:43:16.638375 RX DATLAT : PASS
3651 17:43:16.641470 RX DQ/DQS(Engine): PASS
3652 17:43:16.641569 TX OE : NO K
3653 17:43:16.644611 All Pass.
3654 17:43:16.644707
3655 17:43:16.644803 CH 0, Rank 1
3656 17:43:16.648496 SW Impedance : PASS
3657 17:43:16.648593 DUTY Scan : NO K
3658 17:43:16.651716 ZQ Calibration : PASS
3659 17:43:16.654908 Jitter Meter : NO K
3660 17:43:16.655006 CBT Training : PASS
3661 17:43:16.657884 Write leveling : PASS
3662 17:43:16.661909 RX DQS gating : PASS
3663 17:43:16.661981 RX DQ/DQS(RDDQC) : PASS
3664 17:43:16.664584 TX DQ/DQS : PASS
3665 17:43:16.668058 RX DATLAT : PASS
3666 17:43:16.668132 RX DQ/DQS(Engine): PASS
3667 17:43:16.671226 TX OE : NO K
3668 17:43:16.671296 All Pass.
3669 17:43:16.671356
3670 17:43:16.675133 CH 1, Rank 0
3671 17:43:16.675230 SW Impedance : PASS
3672 17:43:16.678438 DUTY Scan : NO K
3673 17:43:16.681749 ZQ Calibration : PASS
3674 17:43:16.681846 Jitter Meter : NO K
3675 17:43:16.684489 CBT Training : PASS
3676 17:43:16.688564 Write leveling : PASS
3677 17:43:16.688638 RX DQS gating : PASS
3678 17:43:16.691228 RX DQ/DQS(RDDQC) : PASS
3679 17:43:16.691325 TX DQ/DQS : PASS
3680 17:43:16.694630 RX DATLAT : PASS
3681 17:43:16.698009 RX DQ/DQS(Engine): PASS
3682 17:43:16.698080 TX OE : NO K
3683 17:43:16.701240 All Pass.
3684 17:43:16.701338
3685 17:43:16.701426 CH 1, Rank 1
3686 17:43:16.704433 SW Impedance : PASS
3687 17:43:16.704513 DUTY Scan : NO K
3688 17:43:16.708441 ZQ Calibration : PASS
3689 17:43:16.711722 Jitter Meter : NO K
3690 17:43:16.711795 CBT Training : PASS
3691 17:43:16.714421 Write leveling : PASS
3692 17:43:16.718032 RX DQS gating : PASS
3693 17:43:16.718135 RX DQ/DQS(RDDQC) : PASS
3694 17:43:16.721220 TX DQ/DQS : PASS
3695 17:43:16.724776 RX DATLAT : PASS
3696 17:43:16.724874 RX DQ/DQS(Engine): PASS
3697 17:43:16.727674 TX OE : NO K
3698 17:43:16.727783 All Pass.
3699 17:43:16.727873
3700 17:43:16.731564 DramC Write-DBI off
3701 17:43:16.734879 PER_BANK_REFRESH: Hybrid Mode
3702 17:43:16.734952 TX_TRACKING: ON
3703 17:43:16.744459 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3704 17:43:16.747838 [FAST_K] Save calibration result to emmc
3705 17:43:16.751058 dramc_set_vcore_voltage set vcore to 650000
3706 17:43:16.754695 Read voltage for 600, 5
3707 17:43:16.754772 Vio18 = 0
3708 17:43:16.754834 Vcore = 650000
3709 17:43:16.757625 Vdram = 0
3710 17:43:16.757724 Vddq = 0
3711 17:43:16.757816 Vmddr = 0
3712 17:43:16.764709 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3713 17:43:16.767523 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3714 17:43:16.770780 MEM_TYPE=3, freq_sel=19
3715 17:43:16.774773 sv_algorithm_assistance_LP4_1600
3716 17:43:16.777960 ============ PULL DRAM RESETB DOWN ============
3717 17:43:16.781278 ========== PULL DRAM RESETB DOWN end =========
3718 17:43:16.787896 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3719 17:43:16.791163 ===================================
3720 17:43:16.791263 LPDDR4 DRAM CONFIGURATION
3721 17:43:16.795787 ===================================
3722 17:43:16.798022 EX_ROW_EN[0] = 0x0
3723 17:43:16.801294 EX_ROW_EN[1] = 0x0
3724 17:43:16.801391 LP4Y_EN = 0x0
3725 17:43:16.804683 WORK_FSP = 0x0
3726 17:43:16.804788 WL = 0x2
3727 17:43:16.807867 RL = 0x2
3728 17:43:16.807937 BL = 0x2
3729 17:43:16.811178 RPST = 0x0
3730 17:43:16.811275 RD_PRE = 0x0
3731 17:43:16.814469 WR_PRE = 0x1
3732 17:43:16.814566 WR_PST = 0x0
3733 17:43:16.817746 DBI_WR = 0x0
3734 17:43:16.817841 DBI_RD = 0x0
3735 17:43:16.820837 OTF = 0x1
3736 17:43:16.824188 ===================================
3737 17:43:16.827453 ===================================
3738 17:43:16.827550 ANA top config
3739 17:43:16.830753 ===================================
3740 17:43:16.834417 DLL_ASYNC_EN = 0
3741 17:43:16.837407 ALL_SLAVE_EN = 1
3742 17:43:16.840967 NEW_RANK_MODE = 1
3743 17:43:16.841063 DLL_IDLE_MODE = 1
3744 17:43:16.844261 LP45_APHY_COMB_EN = 1
3745 17:43:16.847723 TX_ODT_DIS = 1
3746 17:43:16.850904 NEW_8X_MODE = 1
3747 17:43:16.854641 ===================================
3748 17:43:16.857872 ===================================
3749 17:43:16.857972 data_rate = 1200
3750 17:43:16.860835 CKR = 1
3751 17:43:16.864309 DQ_P2S_RATIO = 8
3752 17:43:16.867365 ===================================
3753 17:43:16.871043 CA_P2S_RATIO = 8
3754 17:43:16.873979 DQ_CA_OPEN = 0
3755 17:43:16.877571 DQ_SEMI_OPEN = 0
3756 17:43:16.877669 CA_SEMI_OPEN = 0
3757 17:43:16.880500 CA_FULL_RATE = 0
3758 17:43:16.884052 DQ_CKDIV4_EN = 1
3759 17:43:16.887566 CA_CKDIV4_EN = 1
3760 17:43:16.890826 CA_PREDIV_EN = 0
3761 17:43:16.894078 PH8_DLY = 0
3762 17:43:16.894181 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3763 17:43:16.897373 DQ_AAMCK_DIV = 4
3764 17:43:16.900815 CA_AAMCK_DIV = 4
3765 17:43:16.904066 CA_ADMCK_DIV = 4
3766 17:43:16.907536 DQ_TRACK_CA_EN = 0
3767 17:43:16.910781 CA_PICK = 600
3768 17:43:16.914044 CA_MCKIO = 600
3769 17:43:16.914145 MCKIO_SEMI = 0
3770 17:43:16.917051 PLL_FREQ = 2288
3771 17:43:16.921016 DQ_UI_PI_RATIO = 32
3772 17:43:16.924196 CA_UI_PI_RATIO = 0
3773 17:43:16.927479 ===================================
3774 17:43:16.930835 ===================================
3775 17:43:16.934164 memory_type:LPDDR4
3776 17:43:16.934263 GP_NUM : 10
3777 17:43:16.937501 SRAM_EN : 1
3778 17:43:16.937598 MD32_EN : 0
3779 17:43:16.940861 ===================================
3780 17:43:16.944061 [ANA_INIT] >>>>>>>>>>>>>>
3781 17:43:16.947273 <<<<<< [CONFIGURE PHASE]: ANA_TX
3782 17:43:16.950940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3783 17:43:16.953854 ===================================
3784 17:43:16.956995 data_rate = 1200,PCW = 0X5800
3785 17:43:16.960738 ===================================
3786 17:43:16.963875 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3787 17:43:16.970569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 17:43:16.973804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 17:43:16.980785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3790 17:43:16.984045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3791 17:43:16.987145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3792 17:43:16.987243 [ANA_INIT] flow start
3793 17:43:16.990768 [ANA_INIT] PLL >>>>>>>>
3794 17:43:16.993734 [ANA_INIT] PLL <<<<<<<<
3795 17:43:16.993829 [ANA_INIT] MIDPI >>>>>>>>
3796 17:43:16.996953 [ANA_INIT] MIDPI <<<<<<<<
3797 17:43:17.000501 [ANA_INIT] DLL >>>>>>>>
3798 17:43:17.000620 [ANA_INIT] flow end
3799 17:43:17.007144 ============ LP4 DIFF to SE enter ============
3800 17:43:17.010406 ============ LP4 DIFF to SE exit ============
3801 17:43:17.013778 [ANA_INIT] <<<<<<<<<<<<<
3802 17:43:17.017157 [Flow] Enable top DCM control >>>>>
3803 17:43:17.020467 [Flow] Enable top DCM control <<<<<
3804 17:43:17.020536 Enable DLL master slave shuffle
3805 17:43:17.027079 ==============================================================
3806 17:43:17.030281 Gating Mode config
3807 17:43:17.033722 ==============================================================
3808 17:43:17.037098 Config description:
3809 17:43:17.047165 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3810 17:43:17.054014 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3811 17:43:17.057136 SELPH_MODE 0: By rank 1: By Phase
3812 17:43:17.063229 ==============================================================
3813 17:43:17.066727 GAT_TRACK_EN = 1
3814 17:43:17.070322 RX_GATING_MODE = 2
3815 17:43:17.073248 RX_GATING_TRACK_MODE = 2
3816 17:43:17.076886 SELPH_MODE = 1
3817 17:43:17.076957 PICG_EARLY_EN = 1
3818 17:43:17.079790 VALID_LAT_VALUE = 1
3819 17:43:17.086825 ==============================================================
3820 17:43:17.090029 Enter into Gating configuration >>>>
3821 17:43:17.093215 Exit from Gating configuration <<<<
3822 17:43:17.096338 Enter into DVFS_PRE_config >>>>>
3823 17:43:17.106404 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3824 17:43:17.110038 Exit from DVFS_PRE_config <<<<<
3825 17:43:17.113336 Enter into PICG configuration >>>>
3826 17:43:17.116732 Exit from PICG configuration <<<<
3827 17:43:17.120127 [RX_INPUT] configuration >>>>>
3828 17:43:17.123420 [RX_INPUT] configuration <<<<<
3829 17:43:17.126594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3830 17:43:17.133263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3831 17:43:17.139987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 17:43:17.146662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 17:43:17.153443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 17:43:17.156702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 17:43:17.162723 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3836 17:43:17.166634 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3837 17:43:17.169755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3838 17:43:17.173066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3839 17:43:17.179621 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3840 17:43:17.183200 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3841 17:43:17.186346 ===================================
3842 17:43:17.189298 LPDDR4 DRAM CONFIGURATION
3843 17:43:17.192616 ===================================
3844 17:43:17.192711 EX_ROW_EN[0] = 0x0
3845 17:43:17.196297 EX_ROW_EN[1] = 0x0
3846 17:43:17.196371 LP4Y_EN = 0x0
3847 17:43:17.199504 WORK_FSP = 0x0
3848 17:43:17.199602 WL = 0x2
3849 17:43:17.203061 RL = 0x2
3850 17:43:17.203129 BL = 0x2
3851 17:43:17.205838 RPST = 0x0
3852 17:43:17.205940 RD_PRE = 0x0
3853 17:43:17.209227 WR_PRE = 0x1
3854 17:43:17.212661 WR_PST = 0x0
3855 17:43:17.212733 DBI_WR = 0x0
3856 17:43:17.216224 DBI_RD = 0x0
3857 17:43:17.216363 OTF = 0x1
3858 17:43:17.219435 ===================================
3859 17:43:17.222583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3860 17:43:17.225999 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3861 17:43:17.232538 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 17:43:17.235699 ===================================
3863 17:43:17.239621 LPDDR4 DRAM CONFIGURATION
3864 17:43:17.242296 ===================================
3865 17:43:17.242393 EX_ROW_EN[0] = 0x10
3866 17:43:17.245881 EX_ROW_EN[1] = 0x0
3867 17:43:17.245949 LP4Y_EN = 0x0
3868 17:43:17.249147 WORK_FSP = 0x0
3869 17:43:17.249274 WL = 0x2
3870 17:43:17.252643 RL = 0x2
3871 17:43:17.252716 BL = 0x2
3872 17:43:17.255986 RPST = 0x0
3873 17:43:17.256059 RD_PRE = 0x0
3874 17:43:17.259290 WR_PRE = 0x1
3875 17:43:17.259382 WR_PST = 0x0
3876 17:43:17.262625 DBI_WR = 0x0
3877 17:43:17.262696 DBI_RD = 0x0
3878 17:43:17.266085 OTF = 0x1
3879 17:43:17.269390 ===================================
3880 17:43:17.275353 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3881 17:43:17.279253 nWR fixed to 30
3882 17:43:17.282726 [ModeRegInit_LP4] CH0 RK0
3883 17:43:17.282828 [ModeRegInit_LP4] CH0 RK1
3884 17:43:17.285789 [ModeRegInit_LP4] CH1 RK0
3885 17:43:17.288934 [ModeRegInit_LP4] CH1 RK1
3886 17:43:17.289006 match AC timing 17
3887 17:43:17.296013 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3888 17:43:17.299234 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3889 17:43:17.302438 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3890 17:43:17.308686 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3891 17:43:17.312236 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3892 17:43:17.312313 ==
3893 17:43:17.315783 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 17:43:17.319151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3895 17:43:17.319238 ==
3896 17:43:17.325596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3897 17:43:17.331930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3898 17:43:17.335410 [CA 0] Center 36 (5~67) winsize 63
3899 17:43:17.338890 [CA 1] Center 36 (5~67) winsize 63
3900 17:43:17.342208 [CA 2] Center 33 (3~64) winsize 62
3901 17:43:17.345211 [CA 3] Center 33 (2~64) winsize 63
3902 17:43:17.348848 [CA 4] Center 33 (2~64) winsize 63
3903 17:43:17.352095 [CA 5] Center 32 (2~63) winsize 62
3904 17:43:17.352170
3905 17:43:17.355375 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3906 17:43:17.355448
3907 17:43:17.358685 [CATrainingPosCal] consider 1 rank data
3908 17:43:17.362145 u2DelayCellTimex100 = 270/100 ps
3909 17:43:17.365491 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3910 17:43:17.368749 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3911 17:43:17.372101 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3912 17:43:17.375459 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3913 17:43:17.378732 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3914 17:43:17.385434 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3915 17:43:17.385509
3916 17:43:17.388671 CA PerBit enable=1, Macro0, CA PI delay=32
3917 17:43:17.388743
3918 17:43:17.391958 [CBTSetCACLKResult] CA Dly = 32
3919 17:43:17.392055 CS Dly: 5 (0~36)
3920 17:43:17.392143 ==
3921 17:43:17.395134 Dram Type= 6, Freq= 0, CH_0, rank 1
3922 17:43:17.398206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 17:43:17.401521 ==
3924 17:43:17.405402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 17:43:17.412061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 17:43:17.415283 [CA 0] Center 35 (5~66) winsize 62
3927 17:43:17.418683 [CA 1] Center 35 (5~66) winsize 62
3928 17:43:17.422014 [CA 2] Center 34 (3~65) winsize 63
3929 17:43:17.424752 [CA 3] Center 33 (3~64) winsize 62
3930 17:43:17.428090 [CA 4] Center 33 (2~64) winsize 63
3931 17:43:17.431625 [CA 5] Center 32 (2~63) winsize 62
3932 17:43:17.431715
3933 17:43:17.435155 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 17:43:17.435224
3935 17:43:17.438061 [CATrainingPosCal] consider 2 rank data
3936 17:43:17.441588 u2DelayCellTimex100 = 270/100 ps
3937 17:43:17.444932 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3938 17:43:17.448265 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3939 17:43:17.451589 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3940 17:43:17.454709 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3941 17:43:17.461415 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3942 17:43:17.464812 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3943 17:43:17.464884
3944 17:43:17.468291 CA PerBit enable=1, Macro0, CA PI delay=32
3945 17:43:17.468360
3946 17:43:17.471815 [CBTSetCACLKResult] CA Dly = 32
3947 17:43:17.471916 CS Dly: 5 (0~36)
3948 17:43:17.472009
3949 17:43:17.475187 ----->DramcWriteLeveling(PI) begin...
3950 17:43:17.475291 ==
3951 17:43:17.478482 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 17:43:17.485210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 17:43:17.485290 ==
3954 17:43:17.488690 Write leveling (Byte 0): 36 => 36
3955 17:43:17.488760 Write leveling (Byte 1): 32 => 32
3956 17:43:17.492081 DramcWriteLeveling(PI) end<-----
3957 17:43:17.492174
3958 17:43:17.492264 ==
3959 17:43:17.495309 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 17:43:17.501872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 17:43:17.501951 ==
3962 17:43:17.504837 [Gating] SW mode calibration
3963 17:43:17.511727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 17:43:17.514904 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3965 17:43:17.521465 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 17:43:17.524763 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 17:43:17.528138 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 17:43:17.534807 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3969 17:43:17.538092 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3970 17:43:17.541428 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 17:43:17.547885 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 17:43:17.551611 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 17:43:17.554678 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 17:43:17.561161 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 17:43:17.564890 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 17:43:17.567791 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
3977 17:43:17.571168 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3978 17:43:17.578082 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 17:43:17.581567 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 17:43:17.584916 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 17:43:17.591105 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 17:43:17.594514 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 17:43:17.597796 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 17:43:17.604383 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3985 17:43:17.607755 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3986 17:43:17.611097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 17:43:17.618093 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 17:43:17.621115 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 17:43:17.624648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 17:43:17.631014 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 17:43:17.634374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 17:43:17.637622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 17:43:17.644802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 17:43:17.648177 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 17:43:17.651478 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 17:43:17.657816 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 17:43:17.660924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 17:43:17.664237 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 17:43:17.670904 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4000 17:43:17.674164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4001 17:43:17.677712 Total UI for P1: 0, mck2ui 16
4002 17:43:17.681430 best dqsien dly found for B0: ( 0, 13, 8)
4003 17:43:17.684817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 17:43:17.688083 Total UI for P1: 0, mck2ui 16
4005 17:43:17.691231 best dqsien dly found for B1: ( 0, 13, 14)
4006 17:43:17.694440 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4007 17:43:17.697300 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4008 17:43:17.697375
4009 17:43:17.700798 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4010 17:43:17.707445 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4011 17:43:17.707555 [Gating] SW calibration Done
4012 17:43:17.707692 ==
4013 17:43:17.710923 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 17:43:17.717495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 17:43:17.717618 ==
4016 17:43:17.717713 RX Vref Scan: 0
4017 17:43:17.717802
4018 17:43:17.720801 RX Vref 0 -> 0, step: 1
4019 17:43:17.720897
4020 17:43:17.724159 RX Delay -230 -> 252, step: 16
4021 17:43:17.727435 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4022 17:43:17.730490 iDelay=218, Bit 1, Center 65 (-86 ~ 217) 304
4023 17:43:17.734106 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4024 17:43:17.740777 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4025 17:43:17.743948 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4026 17:43:17.747262 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4027 17:43:17.750639 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4028 17:43:17.753900 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4029 17:43:17.760557 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4030 17:43:17.763757 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4031 17:43:17.767463 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4032 17:43:17.770805 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4033 17:43:17.777557 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4034 17:43:17.780929 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4035 17:43:17.784141 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4036 17:43:17.786986 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4037 17:43:17.787094 ==
4038 17:43:17.790588 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 17:43:17.797136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 17:43:17.797229 ==
4041 17:43:17.797295 DQS Delay:
4042 17:43:17.797354 DQS0 = 0, DQS1 = 0
4043 17:43:17.800432 DQM Delay:
4044 17:43:17.800538 DQM0 = 59, DQM1 = 51
4045 17:43:17.803765 DQ Delay:
4046 17:43:17.806965 DQ0 =57, DQ1 =65, DQ2 =57, DQ3 =57
4047 17:43:17.810942 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4048 17:43:17.811043 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4049 17:43:17.817482 DQ12 =57, DQ13 =57, DQ14 =65, DQ15 =65
4050 17:43:17.817585
4051 17:43:17.817677
4052 17:43:17.817764 ==
4053 17:43:17.820358 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 17:43:17.823901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 17:43:17.824005 ==
4056 17:43:17.824097
4057 17:43:17.824188
4058 17:43:17.826722 TX Vref Scan disable
4059 17:43:17.826795 == TX Byte 0 ==
4060 17:43:17.833554 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4061 17:43:17.836947 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4062 17:43:17.837021 == TX Byte 1 ==
4063 17:43:17.843949 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4064 17:43:17.846975 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4065 17:43:17.847054 ==
4066 17:43:17.850605 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 17:43:17.853888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 17:43:17.854012 ==
4069 17:43:17.854112
4070 17:43:17.854205
4071 17:43:17.857086 TX Vref Scan disable
4072 17:43:17.860444 == TX Byte 0 ==
4073 17:43:17.863716 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4074 17:43:17.867073 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4075 17:43:17.870649 == TX Byte 1 ==
4076 17:43:17.873795 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4077 17:43:17.877091 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4078 17:43:17.877189
4079 17:43:17.880526 [DATLAT]
4080 17:43:17.880621 Freq=600, CH0 RK0
4081 17:43:17.880715
4082 17:43:17.883848 DATLAT Default: 0x9
4083 17:43:17.883919 0, 0xFFFF, sum = 0
4084 17:43:17.887241 1, 0xFFFF, sum = 0
4085 17:43:17.887309 2, 0xFFFF, sum = 0
4086 17:43:17.890664 3, 0xFFFF, sum = 0
4087 17:43:17.890759 4, 0xFFFF, sum = 0
4088 17:43:17.893853 5, 0xFFFF, sum = 0
4089 17:43:17.893949 6, 0xFFFF, sum = 0
4090 17:43:17.897077 7, 0xFFFF, sum = 0
4091 17:43:17.897148 8, 0x0, sum = 1
4092 17:43:17.900567 9, 0x0, sum = 2
4093 17:43:17.900636 10, 0x0, sum = 3
4094 17:43:17.903795 11, 0x0, sum = 4
4095 17:43:17.903898 best_step = 9
4096 17:43:17.903988
4097 17:43:17.904076 ==
4098 17:43:17.907331 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 17:43:17.913890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 17:43:17.913992 ==
4101 17:43:17.914086 RX Vref Scan: 1
4102 17:43:17.914175
4103 17:43:17.917072 RX Vref 0 -> 0, step: 1
4104 17:43:17.917146
4105 17:43:17.920282 RX Delay -163 -> 252, step: 8
4106 17:43:17.920377
4107 17:43:17.923609 Set Vref, RX VrefLevel [Byte0]: 54
4108 17:43:17.926866 [Byte1]: 47
4109 17:43:17.926936
4110 17:43:17.930022 Final RX Vref Byte 0 = 54 to rank0
4111 17:43:17.933718 Final RX Vref Byte 1 = 47 to rank0
4112 17:43:17.936922 Final RX Vref Byte 0 = 54 to rank1
4113 17:43:17.940641 Final RX Vref Byte 1 = 47 to rank1==
4114 17:43:17.943922 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 17:43:17.947173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 17:43:17.947247 ==
4117 17:43:17.950508 DQS Delay:
4118 17:43:17.950604 DQS0 = 0, DQS1 = 0
4119 17:43:17.950693 DQM Delay:
4120 17:43:17.953664 DQM0 = 53, DQM1 = 46
4121 17:43:17.953756 DQ Delay:
4122 17:43:17.956765 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4123 17:43:17.960453 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4124 17:43:17.963560 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4125 17:43:17.966656 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4126 17:43:17.966759
4127 17:43:17.966848
4128 17:43:17.976974 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4129 17:43:17.977083 CH0 RK0: MR19=808, MR18=6E62
4130 17:43:17.983621 CH0_RK0: MR19=0x808, MR18=0x6E62, DQSOSC=389, MR23=63, INC=173, DEC=115
4131 17:43:17.983746
4132 17:43:17.986908 ----->DramcWriteLeveling(PI) begin...
4133 17:43:17.990265 ==
4134 17:43:17.990359 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 17:43:17.997093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 17:43:17.997191 ==
4137 17:43:18.000306 Write leveling (Byte 0): 35 => 35
4138 17:43:18.003580 Write leveling (Byte 1): 32 => 32
4139 17:43:18.006805 DramcWriteLeveling(PI) end<-----
4140 17:43:18.006896
4141 17:43:18.006960 ==
4142 17:43:18.009930 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 17:43:18.013285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 17:43:18.013356 ==
4145 17:43:18.016710 [Gating] SW mode calibration
4146 17:43:18.023263 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4147 17:43:18.026994 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4148 17:43:18.033616 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 17:43:18.036833 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 17:43:18.040210 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 17:43:18.046453 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4152 17:43:18.050141 0 9 16 | B1->B0 | 2c2c 2525 | 0 0 | (1 1) (0 0)
4153 17:43:18.053043 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 17:43:18.059726 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 17:43:18.062899 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 17:43:18.066205 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 17:43:18.072929 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 17:43:18.076740 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 17:43:18.079424 0 10 12 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4160 17:43:18.086399 0 10 16 | B1->B0 | 3c3c 3a3a | 0 0 | (0 0) (0 0)
4161 17:43:18.089608 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 17:43:18.092987 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 17:43:18.099680 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 17:43:18.103039 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 17:43:18.106129 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 17:43:18.113173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 17:43:18.116365 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4168 17:43:18.119683 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4169 17:43:18.126285 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 17:43:18.129570 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 17:43:18.132861 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 17:43:18.139369 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 17:43:18.142703 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 17:43:18.146047 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 17:43:18.150054 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 17:43:18.156500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 17:43:18.159539 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 17:43:18.163152 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 17:43:18.169764 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 17:43:18.173092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 17:43:18.176486 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 17:43:18.183073 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 17:43:18.186106 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4184 17:43:18.189822 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 17:43:18.193007 Total UI for P1: 0, mck2ui 16
4186 17:43:18.196333 best dqsien dly found for B0: ( 0, 13, 12)
4187 17:43:18.199646 Total UI for P1: 0, mck2ui 16
4188 17:43:18.202999 best dqsien dly found for B1: ( 0, 13, 14)
4189 17:43:18.206314 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4190 17:43:18.209640 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4191 17:43:18.209740
4192 17:43:18.216247 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4193 17:43:18.219833 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4194 17:43:18.219912 [Gating] SW calibration Done
4195 17:43:18.223016 ==
4196 17:43:18.226314 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 17:43:18.229580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 17:43:18.229678 ==
4199 17:43:18.229769 RX Vref Scan: 0
4200 17:43:18.229857
4201 17:43:18.233135 RX Vref 0 -> 0, step: 1
4202 17:43:18.233205
4203 17:43:18.236480 RX Delay -230 -> 252, step: 16
4204 17:43:18.239666 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4205 17:43:18.242689 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4206 17:43:18.249944 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4207 17:43:18.253329 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4208 17:43:18.256390 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4209 17:43:18.259678 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4210 17:43:18.262956 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4211 17:43:18.269999 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4212 17:43:18.273052 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4213 17:43:18.276027 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4214 17:43:18.279837 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4215 17:43:18.286325 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4216 17:43:18.289364 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4217 17:43:18.293204 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4218 17:43:18.296224 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4219 17:43:18.299513 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4220 17:43:18.302919 ==
4221 17:43:18.306235 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 17:43:18.309597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 17:43:18.309699 ==
4224 17:43:18.309791 DQS Delay:
4225 17:43:18.312882 DQS0 = 0, DQS1 = 0
4226 17:43:18.312971 DQM Delay:
4227 17:43:18.316208 DQM0 = 54, DQM1 = 46
4228 17:43:18.316308 DQ Delay:
4229 17:43:18.319371 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4230 17:43:18.322642 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4231 17:43:18.326502 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =41
4232 17:43:18.329676 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4233 17:43:18.329776
4234 17:43:18.329867
4235 17:43:18.329955 ==
4236 17:43:18.332970 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 17:43:18.336202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 17:43:18.336304 ==
4239 17:43:18.336395
4240 17:43:18.336483
4241 17:43:18.339551 TX Vref Scan disable
4242 17:43:18.342825 == TX Byte 0 ==
4243 17:43:18.346156 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4244 17:43:18.349303 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4245 17:43:18.352633 == TX Byte 1 ==
4246 17:43:18.355843 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4247 17:43:18.359182 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4248 17:43:18.359279 ==
4249 17:43:18.362405 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 17:43:18.369050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 17:43:18.369125 ==
4252 17:43:18.369188
4253 17:43:18.369253
4254 17:43:18.369310 TX Vref Scan disable
4255 17:43:18.373646 == TX Byte 0 ==
4256 17:43:18.377015 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4257 17:43:18.383824 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4258 17:43:18.383927 == TX Byte 1 ==
4259 17:43:18.386989 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4260 17:43:18.390311 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4261 17:43:18.393569
4262 17:43:18.393640 [DATLAT]
4263 17:43:18.393702 Freq=600, CH0 RK1
4264 17:43:18.393760
4265 17:43:18.396608 DATLAT Default: 0x9
4266 17:43:18.396680 0, 0xFFFF, sum = 0
4267 17:43:18.400403 1, 0xFFFF, sum = 0
4268 17:43:18.400482 2, 0xFFFF, sum = 0
4269 17:43:18.403473 3, 0xFFFF, sum = 0
4270 17:43:18.403572 4, 0xFFFF, sum = 0
4271 17:43:18.407162 5, 0xFFFF, sum = 0
4272 17:43:18.407268 6, 0xFFFF, sum = 0
4273 17:43:18.410581 7, 0xFFFF, sum = 0
4274 17:43:18.410680 8, 0x0, sum = 1
4275 17:43:18.413868 9, 0x0, sum = 2
4276 17:43:18.413968 10, 0x0, sum = 3
4277 17:43:18.416515 11, 0x0, sum = 4
4278 17:43:18.416616 best_step = 9
4279 17:43:18.416707
4280 17:43:18.416768 ==
4281 17:43:18.420478 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 17:43:18.426990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 17:43:18.427089 ==
4284 17:43:18.427182 RX Vref Scan: 0
4285 17:43:18.427268
4286 17:43:18.430229 RX Vref 0 -> 0, step: 1
4287 17:43:18.430328
4288 17:43:18.433456 RX Delay -147 -> 252, step: 8
4289 17:43:18.436705 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4290 17:43:18.440061 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4291 17:43:18.446977 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4292 17:43:18.450178 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4293 17:43:18.453530 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4294 17:43:18.456584 iDelay=197, Bit 5, Center 48 (-91 ~ 188) 280
4295 17:43:18.460284 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4296 17:43:18.466910 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4297 17:43:18.470220 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4298 17:43:18.473619 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4299 17:43:18.476832 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4300 17:43:18.480245 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4301 17:43:18.486951 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4302 17:43:18.489878 iDelay=197, Bit 13, Center 52 (-83 ~ 188) 272
4303 17:43:18.493531 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4304 17:43:18.496807 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4305 17:43:18.496882 ==
4306 17:43:18.500013 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 17:43:18.506803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 17:43:18.506893 ==
4309 17:43:18.506960 DQS Delay:
4310 17:43:18.509938 DQS0 = 0, DQS1 = 0
4311 17:43:18.510040 DQM Delay:
4312 17:43:18.510131 DQM0 = 53, DQM1 = 46
4313 17:43:18.513579 DQ Delay:
4314 17:43:18.516883 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4315 17:43:18.520172 DQ4 =56, DQ5 =48, DQ6 =56, DQ7 =56
4316 17:43:18.523475 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4317 17:43:18.526601 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4318 17:43:18.526699
4319 17:43:18.526789
4320 17:43:18.533365 [DQSOSCAuto] RK1, (LSB)MR18= 0x6424, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4321 17:43:18.536792 CH0 RK1: MR19=808, MR18=6424
4322 17:43:18.543621 CH0_RK1: MR19=0x808, MR18=0x6424, DQSOSC=391, MR23=63, INC=171, DEC=114
4323 17:43:18.546991 [RxdqsGatingPostProcess] freq 600
4324 17:43:18.550211 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4325 17:43:18.553149 Pre-setting of DQS Precalculation
4326 17:43:18.559824 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4327 17:43:18.559902 ==
4328 17:43:18.563027 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 17:43:18.566668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 17:43:18.566768 ==
4331 17:43:18.573640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4332 17:43:18.576369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4333 17:43:18.581552 [CA 0] Center 35 (5~66) winsize 62
4334 17:43:18.584865 [CA 1] Center 36 (5~67) winsize 63
4335 17:43:18.588144 [CA 2] Center 34 (4~65) winsize 62
4336 17:43:18.591549 [CA 3] Center 34 (4~65) winsize 62
4337 17:43:18.594956 [CA 4] Center 34 (4~65) winsize 62
4338 17:43:18.597981 [CA 5] Center 34 (3~65) winsize 63
4339 17:43:18.598051
4340 17:43:18.601171 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4341 17:43:18.601244
4342 17:43:18.604437 [CATrainingPosCal] consider 1 rank data
4343 17:43:18.607691 u2DelayCellTimex100 = 270/100 ps
4344 17:43:18.610856 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4345 17:43:18.614642 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4346 17:43:18.621241 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4347 17:43:18.624148 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4348 17:43:18.628001 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4349 17:43:18.631092 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4350 17:43:18.631169
4351 17:43:18.634400 CA PerBit enable=1, Macro0, CA PI delay=34
4352 17:43:18.634474
4353 17:43:18.637637 [CBTSetCACLKResult] CA Dly = 34
4354 17:43:18.637739 CS Dly: 6 (0~37)
4355 17:43:18.637829 ==
4356 17:43:18.641007 Dram Type= 6, Freq= 0, CH_1, rank 1
4357 17:43:18.647560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 17:43:18.647670 ==
4359 17:43:18.650885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 17:43:18.657589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4361 17:43:18.661233 [CA 0] Center 36 (5~67) winsize 63
4362 17:43:18.664588 [CA 1] Center 36 (5~67) winsize 63
4363 17:43:18.667909 [CA 2] Center 34 (4~65) winsize 62
4364 17:43:18.671106 [CA 3] Center 34 (4~65) winsize 62
4365 17:43:18.674246 [CA 4] Center 34 (4~65) winsize 62
4366 17:43:18.678157 [CA 5] Center 34 (3~65) winsize 63
4367 17:43:18.678238
4368 17:43:18.681144 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4369 17:43:18.681221
4370 17:43:18.684225 [CATrainingPosCal] consider 2 rank data
4371 17:43:18.687986 u2DelayCellTimex100 = 270/100 ps
4372 17:43:18.691355 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4373 17:43:18.694753 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4374 17:43:18.701261 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4375 17:43:18.704680 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4376 17:43:18.707618 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4377 17:43:18.710945 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4378 17:43:18.711021
4379 17:43:18.714278 CA PerBit enable=1, Macro0, CA PI delay=34
4380 17:43:18.714375
4381 17:43:18.717636 [CBTSetCACLKResult] CA Dly = 34
4382 17:43:18.717732 CS Dly: 6 (0~38)
4383 17:43:18.717820
4384 17:43:18.721307 ----->DramcWriteLeveling(PI) begin...
4385 17:43:18.724434 ==
4386 17:43:18.727516 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 17:43:18.731069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 17:43:18.731141 ==
4389 17:43:18.734146 Write leveling (Byte 0): 30 => 30
4390 17:43:18.737508 Write leveling (Byte 1): 30 => 30
4391 17:43:18.740538 DramcWriteLeveling(PI) end<-----
4392 17:43:18.740608
4393 17:43:18.740673 ==
4394 17:43:18.744528 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 17:43:18.747923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 17:43:18.747993 ==
4397 17:43:18.750520 [Gating] SW mode calibration
4398 17:43:18.757748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 17:43:18.764374 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4400 17:43:18.767633 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 17:43:18.770797 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 17:43:18.773972 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 17:43:18.780703 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4404 17:43:18.783854 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 17:43:18.786938 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 17:43:18.793898 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 17:43:18.797098 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 17:43:18.800367 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 17:43:18.806815 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 17:43:18.810189 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 17:43:18.814166 0 10 12 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)
4412 17:43:18.820509 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 17:43:18.823773 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 17:43:18.827160 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 17:43:18.833529 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 17:43:18.837111 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 17:43:18.840172 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 17:43:18.847393 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 17:43:18.850168 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4420 17:43:18.853914 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 17:43:18.860289 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 17:43:18.863545 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 17:43:18.867038 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 17:43:18.873648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 17:43:18.876770 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 17:43:18.880065 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 17:43:18.886799 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 17:43:18.890253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 17:43:18.893281 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 17:43:18.900188 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 17:43:18.903371 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 17:43:18.906566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 17:43:18.913417 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 17:43:18.916640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 17:43:18.919945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4436 17:43:18.923642 Total UI for P1: 0, mck2ui 16
4437 17:43:18.927013 best dqsien dly found for B0: ( 0, 13, 10)
4438 17:43:18.929683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 17:43:18.932984 Total UI for P1: 0, mck2ui 16
4440 17:43:18.936957 best dqsien dly found for B1: ( 0, 13, 12)
4441 17:43:18.940108 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4442 17:43:18.946582 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4443 17:43:18.946670
4444 17:43:18.949921 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4445 17:43:18.953132 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4446 17:43:18.956793 [Gating] SW calibration Done
4447 17:43:18.956889 ==
4448 17:43:18.959817 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 17:43:18.963035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 17:43:18.963132 ==
4451 17:43:18.966899 RX Vref Scan: 0
4452 17:43:18.966994
4453 17:43:18.967085 RX Vref 0 -> 0, step: 1
4454 17:43:18.967170
4455 17:43:18.969883 RX Delay -230 -> 252, step: 16
4456 17:43:18.973529 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4457 17:43:18.979978 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4458 17:43:18.983275 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4459 17:43:18.986649 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4460 17:43:18.989978 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4461 17:43:18.996549 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4462 17:43:18.999738 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4463 17:43:19.003089 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4464 17:43:19.006310 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4465 17:43:19.009693 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4466 17:43:19.016055 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4467 17:43:19.019732 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4468 17:43:19.023091 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4469 17:43:19.026387 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4470 17:43:19.032654 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4471 17:43:19.035943 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4472 17:43:19.036032 ==
4473 17:43:19.039900 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 17:43:19.042581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 17:43:19.042665 ==
4476 17:43:19.045919 DQS Delay:
4477 17:43:19.045995 DQS0 = 0, DQS1 = 0
4478 17:43:19.046058 DQM Delay:
4479 17:43:19.049260 DQM0 = 51, DQM1 = 49
4480 17:43:19.049334 DQ Delay:
4481 17:43:19.052479 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4482 17:43:19.056258 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4483 17:43:19.059503 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4484 17:43:19.062984 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4485 17:43:19.063067
4486 17:43:19.063132
4487 17:43:19.063194 ==
4488 17:43:19.066146 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 17:43:19.072798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 17:43:19.072919 ==
4491 17:43:19.073014
4492 17:43:19.073103
4493 17:43:19.073193 TX Vref Scan disable
4494 17:43:19.076259 == TX Byte 0 ==
4495 17:43:19.079721 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4496 17:43:19.086214 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4497 17:43:19.086315 == TX Byte 1 ==
4498 17:43:19.089283 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4499 17:43:19.096344 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4500 17:43:19.096454 ==
4501 17:43:19.099770 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 17:43:19.102487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 17:43:19.102593 ==
4504 17:43:19.102686
4505 17:43:19.102774
4506 17:43:19.105759 TX Vref Scan disable
4507 17:43:19.109668 == TX Byte 0 ==
4508 17:43:19.113030 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 17:43:19.115728 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 17:43:19.118989 == TX Byte 1 ==
4511 17:43:19.122996 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 17:43:19.125641 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 17:43:19.125747
4514 17:43:19.125840 [DATLAT]
4515 17:43:19.129354 Freq=600, CH1 RK0
4516 17:43:19.129470
4517 17:43:19.132263 DATLAT Default: 0x9
4518 17:43:19.132345 0, 0xFFFF, sum = 0
4519 17:43:19.135982 1, 0xFFFF, sum = 0
4520 17:43:19.136101 2, 0xFFFF, sum = 0
4521 17:43:19.138906 3, 0xFFFF, sum = 0
4522 17:43:19.139014 4, 0xFFFF, sum = 0
4523 17:43:19.142664 5, 0xFFFF, sum = 0
4524 17:43:19.142783 6, 0xFFFF, sum = 0
4525 17:43:19.146073 7, 0xFFFF, sum = 0
4526 17:43:19.146205 8, 0x0, sum = 1
4527 17:43:19.148755 9, 0x0, sum = 2
4528 17:43:19.148854 10, 0x0, sum = 3
4529 17:43:19.152019 11, 0x0, sum = 4
4530 17:43:19.152114 best_step = 9
4531 17:43:19.152179
4532 17:43:19.152237 ==
4533 17:43:19.155450 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 17:43:19.159118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 17:43:19.159205 ==
4536 17:43:19.162402 RX Vref Scan: 1
4537 17:43:19.162515
4538 17:43:19.165621 RX Vref 0 -> 0, step: 1
4539 17:43:19.165697
4540 17:43:19.165758 RX Delay -147 -> 252, step: 8
4541 17:43:19.165817
4542 17:43:19.169085 Set Vref, RX VrefLevel [Byte0]: 52
4543 17:43:19.171803 [Byte1]: 51
4544 17:43:19.176744
4545 17:43:19.176893 Final RX Vref Byte 0 = 52 to rank0
4546 17:43:19.180151 Final RX Vref Byte 1 = 51 to rank0
4547 17:43:19.183268 Final RX Vref Byte 0 = 52 to rank1
4548 17:43:19.186318 Final RX Vref Byte 1 = 51 to rank1==
4549 17:43:19.189934 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 17:43:19.196659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 17:43:19.196771 ==
4552 17:43:19.196889 DQS Delay:
4553 17:43:19.196998 DQS0 = 0, DQS1 = 0
4554 17:43:19.200050 DQM Delay:
4555 17:43:19.200143 DQM0 = 48, DQM1 = 45
4556 17:43:19.203032 DQ Delay:
4557 17:43:19.206656 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4558 17:43:19.206769 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4559 17:43:19.209695 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4560 17:43:19.216804 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4561 17:43:19.216999
4562 17:43:19.217110
4563 17:43:19.222887 [DQSOSCAuto] RK0, (LSB)MR18= 0x4166, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4564 17:43:19.226264 CH1 RK0: MR19=808, MR18=4166
4565 17:43:19.233077 CH1_RK0: MR19=0x808, MR18=0x4166, DQSOSC=390, MR23=63, INC=172, DEC=114
4566 17:43:19.233218
4567 17:43:19.236394 ----->DramcWriteLeveling(PI) begin...
4568 17:43:19.236492 ==
4569 17:43:19.239618 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 17:43:19.243376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 17:43:19.243500 ==
4572 17:43:19.246393 Write leveling (Byte 0): 30 => 30
4573 17:43:19.249681 Write leveling (Byte 1): 30 => 30
4574 17:43:19.253009 DramcWriteLeveling(PI) end<-----
4575 17:43:19.253157
4576 17:43:19.253269 ==
4577 17:43:19.256770 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 17:43:19.259476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 17:43:19.259594 ==
4580 17:43:19.262859 [Gating] SW mode calibration
4581 17:43:19.269448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4582 17:43:19.276211 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4583 17:43:19.279444 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 17:43:19.285991 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 17:43:19.289336 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4586 17:43:19.292662 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (1 0)
4587 17:43:19.296037 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 17:43:19.302954 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 17:43:19.305942 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 17:43:19.309129 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 17:43:19.315923 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 17:43:19.319285 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 17:43:19.322827 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4594 17:43:19.329285 0 10 12 | B1->B0 | 4141 3434 | 1 0 | (0 0) (0 0)
4595 17:43:19.332426 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 17:43:19.335713 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 17:43:19.342643 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 17:43:19.346153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 17:43:19.348781 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 17:43:19.355705 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 17:43:19.358965 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4602 17:43:19.362515 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 17:43:19.368652 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 17:43:19.372475 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 17:43:19.375821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 17:43:19.382410 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 17:43:19.385639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 17:43:19.389028 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 17:43:19.395525 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 17:43:19.399089 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 17:43:19.402323 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 17:43:19.409062 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 17:43:19.411575 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 17:43:19.415487 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 17:43:19.421877 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 17:43:19.425004 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 17:43:19.428838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4618 17:43:19.435563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4619 17:43:19.438637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 17:43:19.441791 Total UI for P1: 0, mck2ui 16
4621 17:43:19.445487 best dqsien dly found for B0: ( 0, 13, 14)
4622 17:43:19.448631 Total UI for P1: 0, mck2ui 16
4623 17:43:19.451896 best dqsien dly found for B1: ( 0, 13, 10)
4624 17:43:19.455446 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4625 17:43:19.458744 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4626 17:43:19.458835
4627 17:43:19.462047 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4628 17:43:19.465204 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4629 17:43:19.468275 [Gating] SW calibration Done
4630 17:43:19.468356 ==
4631 17:43:19.471826 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 17:43:19.474990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 17:43:19.475073 ==
4634 17:43:19.478768 RX Vref Scan: 0
4635 17:43:19.478849
4636 17:43:19.481685 RX Vref 0 -> 0, step: 1
4637 17:43:19.481766
4638 17:43:19.485034 RX Delay -230 -> 252, step: 16
4639 17:43:19.488413 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4640 17:43:19.491584 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4641 17:43:19.494957 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4642 17:43:19.498329 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4643 17:43:19.505142 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4644 17:43:19.508318 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4645 17:43:19.511567 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4646 17:43:19.514697 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4647 17:43:19.521854 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4648 17:43:19.525059 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4649 17:43:19.528326 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4650 17:43:19.531465 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4651 17:43:19.535359 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4652 17:43:19.541820 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4653 17:43:19.545060 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4654 17:43:19.548267 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4655 17:43:19.548342 ==
4656 17:43:19.551562 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 17:43:19.558413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 17:43:19.558497 ==
4659 17:43:19.558564 DQS Delay:
4660 17:43:19.558625 DQS0 = 0, DQS1 = 0
4661 17:43:19.561665 DQM Delay:
4662 17:43:19.561736 DQM0 = 48, DQM1 = 48
4663 17:43:19.565036 DQ Delay:
4664 17:43:19.568253 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4665 17:43:19.568335 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4666 17:43:19.571689 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4667 17:43:19.577937 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4668 17:43:19.578019
4669 17:43:19.578084
4670 17:43:19.578144 ==
4671 17:43:19.581312 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 17:43:19.585063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 17:43:19.585145 ==
4674 17:43:19.585209
4675 17:43:19.585268
4676 17:43:19.588060 TX Vref Scan disable
4677 17:43:19.588141 == TX Byte 0 ==
4678 17:43:19.594777 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4679 17:43:19.598393 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4680 17:43:19.598475 == TX Byte 1 ==
4681 17:43:19.604969 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4682 17:43:19.608303 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4683 17:43:19.608391 ==
4684 17:43:19.611568 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 17:43:19.614910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 17:43:19.614999 ==
4687 17:43:19.615064
4688 17:43:19.615132
4689 17:43:19.618183 TX Vref Scan disable
4690 17:43:19.621445 == TX Byte 0 ==
4691 17:43:19.624602 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4692 17:43:19.627782 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4693 17:43:19.631752 == TX Byte 1 ==
4694 17:43:19.635318 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4695 17:43:19.638301 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4696 17:43:19.638375
4697 17:43:19.641349 [DATLAT]
4698 17:43:19.641418 Freq=600, CH1 RK1
4699 17:43:19.641478
4700 17:43:19.644869 DATLAT Default: 0x9
4701 17:43:19.644941 0, 0xFFFF, sum = 0
4702 17:43:19.647997 1, 0xFFFF, sum = 0
4703 17:43:19.648071 2, 0xFFFF, sum = 0
4704 17:43:19.651133 3, 0xFFFF, sum = 0
4705 17:43:19.651201 4, 0xFFFF, sum = 0
4706 17:43:19.654411 5, 0xFFFF, sum = 0
4707 17:43:19.654486 6, 0xFFFF, sum = 0
4708 17:43:19.657642 7, 0xFFFF, sum = 0
4709 17:43:19.657724 8, 0x0, sum = 1
4710 17:43:19.661558 9, 0x0, sum = 2
4711 17:43:19.661661 10, 0x0, sum = 3
4712 17:43:19.664631 11, 0x0, sum = 4
4713 17:43:19.664705 best_step = 9
4714 17:43:19.664766
4715 17:43:19.664842 ==
4716 17:43:19.667815 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 17:43:19.674553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 17:43:19.674628 ==
4719 17:43:19.674697 RX Vref Scan: 0
4720 17:43:19.674757
4721 17:43:19.678012 RX Vref 0 -> 0, step: 1
4722 17:43:19.678093
4723 17:43:19.681212 RX Delay -163 -> 252, step: 8
4724 17:43:19.684392 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4725 17:43:19.688204 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4726 17:43:19.694805 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4727 17:43:19.698028 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4728 17:43:19.701016 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4729 17:43:19.704101 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4730 17:43:19.707773 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4731 17:43:19.714249 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4732 17:43:19.717677 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4733 17:43:19.721324 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4734 17:43:19.724626 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4735 17:43:19.731076 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4736 17:43:19.734691 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4737 17:43:19.737507 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4738 17:43:19.740868 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4739 17:43:19.744271 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4740 17:43:19.744341 ==
4741 17:43:19.748084 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 17:43:19.754562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 17:43:19.754642 ==
4744 17:43:19.754705 DQS Delay:
4745 17:43:19.757731 DQS0 = 0, DQS1 = 0
4746 17:43:19.757799 DQM Delay:
4747 17:43:19.760888 DQM0 = 49, DQM1 = 46
4748 17:43:19.760958 DQ Delay:
4749 17:43:19.764606 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4750 17:43:19.767803 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4751 17:43:19.770980 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4752 17:43:19.774276 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4753 17:43:19.774351
4754 17:43:19.774422
4755 17:43:19.780828 [DQSOSCAuto] RK1, (LSB)MR18= 0x661d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4756 17:43:19.784209 CH1 RK1: MR19=808, MR18=661D
4757 17:43:19.791212 CH1_RK1: MR19=0x808, MR18=0x661D, DQSOSC=390, MR23=63, INC=172, DEC=114
4758 17:43:19.794713 [RxdqsGatingPostProcess] freq 600
4759 17:43:19.797972 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4760 17:43:19.801162 Pre-setting of DQS Precalculation
4761 17:43:19.807450 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4762 17:43:19.814138 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4763 17:43:19.821006 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4764 17:43:19.821093
4765 17:43:19.821180
4766 17:43:19.824361 [Calibration Summary] 1200 Mbps
4767 17:43:19.824446 CH 0, Rank 0
4768 17:43:19.827675 SW Impedance : PASS
4769 17:43:19.831047 DUTY Scan : NO K
4770 17:43:19.831132 ZQ Calibration : PASS
4771 17:43:19.834270 Jitter Meter : NO K
4772 17:43:19.837331 CBT Training : PASS
4773 17:43:19.837415 Write leveling : PASS
4774 17:43:19.840924 RX DQS gating : PASS
4775 17:43:19.844410 RX DQ/DQS(RDDQC) : PASS
4776 17:43:19.844494 TX DQ/DQS : PASS
4777 17:43:19.847790 RX DATLAT : PASS
4778 17:43:19.851028 RX DQ/DQS(Engine): PASS
4779 17:43:19.851112 TX OE : NO K
4780 17:43:19.851198 All Pass.
4781 17:43:19.851279
4782 17:43:19.854393 CH 0, Rank 1
4783 17:43:19.854477 SW Impedance : PASS
4784 17:43:19.857567 DUTY Scan : NO K
4785 17:43:19.861389 ZQ Calibration : PASS
4786 17:43:19.861478 Jitter Meter : NO K
4787 17:43:19.864387 CBT Training : PASS
4788 17:43:19.867487 Write leveling : PASS
4789 17:43:19.867571 RX DQS gating : PASS
4790 17:43:19.870637 RX DQ/DQS(RDDQC) : PASS
4791 17:43:19.873766 TX DQ/DQS : PASS
4792 17:43:19.873851 RX DATLAT : PASS
4793 17:43:19.877605 RX DQ/DQS(Engine): PASS
4794 17:43:19.880659 TX OE : NO K
4795 17:43:19.880733 All Pass.
4796 17:43:19.880804
4797 17:43:19.880862 CH 1, Rank 0
4798 17:43:19.883758 SW Impedance : PASS
4799 17:43:19.887168 DUTY Scan : NO K
4800 17:43:19.887276 ZQ Calibration : PASS
4801 17:43:19.890621 Jitter Meter : NO K
4802 17:43:19.893844 CBT Training : PASS
4803 17:43:19.893916 Write leveling : PASS
4804 17:43:19.897608 RX DQS gating : PASS
4805 17:43:19.900963 RX DQ/DQS(RDDQC) : PASS
4806 17:43:19.901044 TX DQ/DQS : PASS
4807 17:43:19.904301 RX DATLAT : PASS
4808 17:43:19.907599 RX DQ/DQS(Engine): PASS
4809 17:43:19.907727 TX OE : NO K
4810 17:43:19.907792 All Pass.
4811 17:43:19.910248
4812 17:43:19.910348 CH 1, Rank 1
4813 17:43:19.913577 SW Impedance : PASS
4814 17:43:19.913646 DUTY Scan : NO K
4815 17:43:19.917161 ZQ Calibration : PASS
4816 17:43:19.917241 Jitter Meter : NO K
4817 17:43:19.920341 CBT Training : PASS
4818 17:43:19.923915 Write leveling : PASS
4819 17:43:19.923990 RX DQS gating : PASS
4820 17:43:19.927089 RX DQ/DQS(RDDQC) : PASS
4821 17:43:19.930227 TX DQ/DQS : PASS
4822 17:43:19.930304 RX DATLAT : PASS
4823 17:43:19.933518 RX DQ/DQS(Engine): PASS
4824 17:43:19.936831 TX OE : NO K
4825 17:43:19.936906 All Pass.
4826 17:43:19.936977
4827 17:43:19.940213 DramC Write-DBI off
4828 17:43:19.940329 PER_BANK_REFRESH: Hybrid Mode
4829 17:43:19.943437 TX_TRACKING: ON
4830 17:43:19.950280 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4831 17:43:19.957010 [FAST_K] Save calibration result to emmc
4832 17:43:19.960391 dramc_set_vcore_voltage set vcore to 662500
4833 17:43:19.960475 Read voltage for 933, 3
4834 17:43:19.963784 Vio18 = 0
4835 17:43:19.963868 Vcore = 662500
4836 17:43:19.963954 Vdram = 0
4837 17:43:19.966876 Vddq = 0
4838 17:43:19.966960 Vmddr = 0
4839 17:43:19.970007 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4840 17:43:19.976823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4841 17:43:19.980519 MEM_TYPE=3, freq_sel=17
4842 17:43:19.983626 sv_algorithm_assistance_LP4_1600
4843 17:43:19.986731 ============ PULL DRAM RESETB DOWN ============
4844 17:43:19.990529 ========== PULL DRAM RESETB DOWN end =========
4845 17:43:19.993492 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4846 17:43:19.996673 ===================================
4847 17:43:19.999909 LPDDR4 DRAM CONFIGURATION
4848 17:43:20.003657 ===================================
4849 17:43:20.007056 EX_ROW_EN[0] = 0x0
4850 17:43:20.007164 EX_ROW_EN[1] = 0x0
4851 17:43:20.010319 LP4Y_EN = 0x0
4852 17:43:20.010426 WORK_FSP = 0x0
4853 17:43:20.013627 WL = 0x3
4854 17:43:20.013697 RL = 0x3
4855 17:43:20.017037 BL = 0x2
4856 17:43:20.017109 RPST = 0x0
4857 17:43:20.020393 RD_PRE = 0x0
4858 17:43:20.023517 WR_PRE = 0x1
4859 17:43:20.023611 WR_PST = 0x0
4860 17:43:20.026485 DBI_WR = 0x0
4861 17:43:20.026553 DBI_RD = 0x0
4862 17:43:20.030093 OTF = 0x1
4863 17:43:20.033330 ===================================
4864 17:43:20.036583 ===================================
4865 17:43:20.036652 ANA top config
4866 17:43:20.039845 ===================================
4867 17:43:20.043211 DLL_ASYNC_EN = 0
4868 17:43:20.046523 ALL_SLAVE_EN = 1
4869 17:43:20.046594 NEW_RANK_MODE = 1
4870 17:43:20.049931 DLL_IDLE_MODE = 1
4871 17:43:20.053654 LP45_APHY_COMB_EN = 1
4872 17:43:20.056676 TX_ODT_DIS = 1
4873 17:43:20.056748 NEW_8X_MODE = 1
4874 17:43:20.059960 ===================================
4875 17:43:20.063311 ===================================
4876 17:43:20.066730 data_rate = 1866
4877 17:43:20.070113 CKR = 1
4878 17:43:20.073415 DQ_P2S_RATIO = 8
4879 17:43:20.076617 ===================================
4880 17:43:20.079760 CA_P2S_RATIO = 8
4881 17:43:20.083553 DQ_CA_OPEN = 0
4882 17:43:20.083675 DQ_SEMI_OPEN = 0
4883 17:43:20.086572 CA_SEMI_OPEN = 0
4884 17:43:20.089784 CA_FULL_RATE = 0
4885 17:43:20.093464 DQ_CKDIV4_EN = 1
4886 17:43:20.096581 CA_CKDIV4_EN = 1
4887 17:43:20.099728 CA_PREDIV_EN = 0
4888 17:43:20.099798 PH8_DLY = 0
4889 17:43:20.103414 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4890 17:43:20.106676 DQ_AAMCK_DIV = 4
4891 17:43:20.109762 CA_AAMCK_DIV = 4
4892 17:43:20.113325 CA_ADMCK_DIV = 4
4893 17:43:20.116289 DQ_TRACK_CA_EN = 0
4894 17:43:20.116374 CA_PICK = 933
4895 17:43:20.119760 CA_MCKIO = 933
4896 17:43:20.123050 MCKIO_SEMI = 0
4897 17:43:20.126300 PLL_FREQ = 3732
4898 17:43:20.129585 DQ_UI_PI_RATIO = 32
4899 17:43:20.132898 CA_UI_PI_RATIO = 0
4900 17:43:20.136592 ===================================
4901 17:43:20.140159 ===================================
4902 17:43:20.140239 memory_type:LPDDR4
4903 17:43:20.143059 GP_NUM : 10
4904 17:43:20.146255 SRAM_EN : 1
4905 17:43:20.146323 MD32_EN : 0
4906 17:43:20.149536 ===================================
4907 17:43:20.152911 [ANA_INIT] >>>>>>>>>>>>>>
4908 17:43:20.156216 <<<<<< [CONFIGURE PHASE]: ANA_TX
4909 17:43:20.159452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4910 17:43:20.163161 ===================================
4911 17:43:20.166380 data_rate = 1866,PCW = 0X8f00
4912 17:43:20.169702 ===================================
4913 17:43:20.173000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4914 17:43:20.176300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 17:43:20.182907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 17:43:20.186217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4917 17:43:20.189419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4918 17:43:20.193164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4919 17:43:20.196274 [ANA_INIT] flow start
4920 17:43:20.199497 [ANA_INIT] PLL >>>>>>>>
4921 17:43:20.199610 [ANA_INIT] PLL <<<<<<<<
4922 17:43:20.202762 [ANA_INIT] MIDPI >>>>>>>>
4923 17:43:20.206028 [ANA_INIT] MIDPI <<<<<<<<
4924 17:43:20.209241 [ANA_INIT] DLL >>>>>>>>
4925 17:43:20.209324 [ANA_INIT] flow end
4926 17:43:20.212338 ============ LP4 DIFF to SE enter ============
4927 17:43:20.219558 ============ LP4 DIFF to SE exit ============
4928 17:43:20.219711 [ANA_INIT] <<<<<<<<<<<<<
4929 17:43:20.222848 [Flow] Enable top DCM control >>>>>
4930 17:43:20.225742 [Flow] Enable top DCM control <<<<<
4931 17:43:20.229119 Enable DLL master slave shuffle
4932 17:43:20.235854 ==============================================================
4933 17:43:20.235937 Gating Mode config
4934 17:43:20.242497 ==============================================================
4935 17:43:20.246133 Config description:
4936 17:43:20.255964 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4937 17:43:20.262616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4938 17:43:20.265971 SELPH_MODE 0: By rank 1: By Phase
4939 17:43:20.272202 ==============================================================
4940 17:43:20.275850 GAT_TRACK_EN = 1
4941 17:43:20.279225 RX_GATING_MODE = 2
4942 17:43:20.279308 RX_GATING_TRACK_MODE = 2
4943 17:43:20.282523 SELPH_MODE = 1
4944 17:43:20.285955 PICG_EARLY_EN = 1
4945 17:43:20.288684 VALID_LAT_VALUE = 1
4946 17:43:20.295567 ==============================================================
4947 17:43:20.298836 Enter into Gating configuration >>>>
4948 17:43:20.302070 Exit from Gating configuration <<<<
4949 17:43:20.305699 Enter into DVFS_PRE_config >>>>>
4950 17:43:20.315295 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4951 17:43:20.319164 Exit from DVFS_PRE_config <<<<<
4952 17:43:20.322477 Enter into PICG configuration >>>>
4953 17:43:20.325185 Exit from PICG configuration <<<<
4954 17:43:20.329152 [RX_INPUT] configuration >>>>>
4955 17:43:20.332284 [RX_INPUT] configuration <<<<<
4956 17:43:20.335429 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4957 17:43:20.342112 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4958 17:43:20.348657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4959 17:43:20.355095 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4960 17:43:20.358435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 17:43:20.365577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 17:43:20.368797 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4963 17:43:20.375165 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4964 17:43:20.378422 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4965 17:43:20.382018 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4966 17:43:20.385361 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4967 17:43:20.392037 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4968 17:43:20.395459 ===================================
4969 17:43:20.395553 LPDDR4 DRAM CONFIGURATION
4970 17:43:20.398515 ===================================
4971 17:43:20.402307 EX_ROW_EN[0] = 0x0
4972 17:43:20.405659 EX_ROW_EN[1] = 0x0
4973 17:43:20.405775 LP4Y_EN = 0x0
4974 17:43:20.409082 WORK_FSP = 0x0
4975 17:43:20.409194 WL = 0x3
4976 17:43:20.411961 RL = 0x3
4977 17:43:20.412073 BL = 0x2
4978 17:43:20.415163 RPST = 0x0
4979 17:43:20.415278 RD_PRE = 0x0
4980 17:43:20.418951 WR_PRE = 0x1
4981 17:43:20.419057 WR_PST = 0x0
4982 17:43:20.422202 DBI_WR = 0x0
4983 17:43:20.422325 DBI_RD = 0x0
4984 17:43:20.425345 OTF = 0x1
4985 17:43:20.428606 ===================================
4986 17:43:20.431974 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4987 17:43:20.435743 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4988 17:43:20.441987 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 17:43:20.445373 ===================================
4990 17:43:20.445483 LPDDR4 DRAM CONFIGURATION
4991 17:43:20.448577 ===================================
4992 17:43:20.451983 EX_ROW_EN[0] = 0x10
4993 17:43:20.452101 EX_ROW_EN[1] = 0x0
4994 17:43:20.455245 LP4Y_EN = 0x0
4995 17:43:20.455358 WORK_FSP = 0x0
4996 17:43:20.458653 WL = 0x3
4997 17:43:20.458767 RL = 0x3
4998 17:43:20.462079 BL = 0x2
4999 17:43:20.465479 RPST = 0x0
5000 17:43:20.465590 RD_PRE = 0x0
5001 17:43:20.468702 WR_PRE = 0x1
5002 17:43:20.468813 WR_PST = 0x0
5003 17:43:20.471769 DBI_WR = 0x0
5004 17:43:20.471872 DBI_RD = 0x0
5005 17:43:20.475439 OTF = 0x1
5006 17:43:20.478476 ===================================
5007 17:43:20.484910 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5008 17:43:20.488664 nWR fixed to 30
5009 17:43:20.488784 [ModeRegInit_LP4] CH0 RK0
5010 17:43:20.491863 [ModeRegInit_LP4] CH0 RK1
5011 17:43:20.495279 [ModeRegInit_LP4] CH1 RK0
5012 17:43:20.495392 [ModeRegInit_LP4] CH1 RK1
5013 17:43:20.498664 match AC timing 9
5014 17:43:20.501879 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5015 17:43:20.505043 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5016 17:43:20.511851 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5017 17:43:20.515416 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5018 17:43:20.521651 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5019 17:43:20.521764 ==
5020 17:43:20.524814 Dram Type= 6, Freq= 0, CH_0, rank 0
5021 17:43:20.528045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5022 17:43:20.528153 ==
5023 17:43:20.535169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5024 17:43:20.538619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5025 17:43:20.542768 [CA 0] Center 37 (6~68) winsize 63
5026 17:43:20.546014 [CA 1] Center 37 (6~68) winsize 63
5027 17:43:20.548984 [CA 2] Center 34 (4~65) winsize 62
5028 17:43:20.552575 [CA 3] Center 34 (3~65) winsize 63
5029 17:43:20.556055 [CA 4] Center 33 (3~63) winsize 61
5030 17:43:20.559282 [CA 5] Center 32 (2~62) winsize 61
5031 17:43:20.559464
5032 17:43:20.562641 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5033 17:43:20.562795
5034 17:43:20.565894 [CATrainingPosCal] consider 1 rank data
5035 17:43:20.569235 u2DelayCellTimex100 = 270/100 ps
5036 17:43:20.572593 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5037 17:43:20.578991 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5038 17:43:20.582219 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5039 17:43:20.585853 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5040 17:43:20.588978 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5041 17:43:20.592153 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5042 17:43:20.592241
5043 17:43:20.595908 CA PerBit enable=1, Macro0, CA PI delay=32
5044 17:43:20.595994
5045 17:43:20.598846 [CBTSetCACLKResult] CA Dly = 32
5046 17:43:20.602070 CS Dly: 5 (0~36)
5047 17:43:20.602193 ==
5048 17:43:20.605556 Dram Type= 6, Freq= 0, CH_0, rank 1
5049 17:43:20.608816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 17:43:20.608909 ==
5051 17:43:20.615211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 17:43:20.618537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 17:43:20.622408 [CA 0] Center 37 (6~68) winsize 63
5054 17:43:20.625564 [CA 1] Center 37 (7~68) winsize 62
5055 17:43:20.629454 [CA 2] Center 34 (4~65) winsize 62
5056 17:43:20.632544 [CA 3] Center 34 (4~65) winsize 62
5057 17:43:20.636007 [CA 4] Center 33 (3~63) winsize 61
5058 17:43:20.639179 [CA 5] Center 32 (2~63) winsize 62
5059 17:43:20.639267
5060 17:43:20.642448 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 17:43:20.642535
5062 17:43:20.645811 [CATrainingPosCal] consider 2 rank data
5063 17:43:20.649111 u2DelayCellTimex100 = 270/100 ps
5064 17:43:20.652369 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5065 17:43:20.656199 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5066 17:43:20.662469 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5067 17:43:20.665786 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5068 17:43:20.669129 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5069 17:43:20.672605 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5070 17:43:20.672691
5071 17:43:20.675982 CA PerBit enable=1, Macro0, CA PI delay=32
5072 17:43:20.676067
5073 17:43:20.679255 [CBTSetCACLKResult] CA Dly = 32
5074 17:43:20.679369 CS Dly: 6 (0~38)
5075 17:43:20.679470
5076 17:43:20.682657 ----->DramcWriteLeveling(PI) begin...
5077 17:43:20.685954 ==
5078 17:43:20.689186 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 17:43:20.692301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 17:43:20.692401 ==
5081 17:43:20.695908 Write leveling (Byte 0): 30 => 30
5082 17:43:20.699504 Write leveling (Byte 1): 28 => 28
5083 17:43:20.702580 DramcWriteLeveling(PI) end<-----
5084 17:43:20.702688
5085 17:43:20.702784 ==
5086 17:43:20.705624 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 17:43:20.709249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 17:43:20.709350 ==
5089 17:43:20.712403 [Gating] SW mode calibration
5090 17:43:20.719094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5091 17:43:20.725527 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5092 17:43:20.728840 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
5093 17:43:20.732145 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 17:43:20.738745 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 17:43:20.742522 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 17:43:20.745768 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 17:43:20.749074 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 17:43:20.755847 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5099 17:43:20.758626 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
5100 17:43:20.762561 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5101 17:43:20.768630 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5102 17:43:20.772525 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 17:43:20.775884 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 17:43:20.782566 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 17:43:20.785948 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 17:43:20.789203 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5107 17:43:20.795255 0 15 28 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
5108 17:43:20.798573 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5109 17:43:20.801890 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 17:43:20.808696 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 17:43:20.812111 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 17:43:20.815575 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 17:43:20.821760 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 17:43:20.825256 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 17:43:20.828816 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5116 17:43:20.835043 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5117 17:43:20.838610 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 17:43:20.841745 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 17:43:20.848756 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 17:43:20.852063 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 17:43:20.855222 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 17:43:20.861951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 17:43:20.865213 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 17:43:20.868538 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 17:43:20.871866 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 17:43:20.878619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 17:43:20.881834 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 17:43:20.885194 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 17:43:20.891939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 17:43:20.895296 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 17:43:20.898676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 17:43:20.905333 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 17:43:20.908578 Total UI for P1: 0, mck2ui 16
5134 17:43:20.911907 best dqsien dly found for B0: ( 1, 2, 28)
5135 17:43:20.911999 Total UI for P1: 0, mck2ui 16
5136 17:43:20.918461 best dqsien dly found for B1: ( 1, 2, 30)
5137 17:43:20.922184 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5138 17:43:20.925246 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5139 17:43:20.925371
5140 17:43:20.928450 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5141 17:43:20.931577 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5142 17:43:20.935196 [Gating] SW calibration Done
5143 17:43:20.935312 ==
5144 17:43:20.938666 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 17:43:20.941591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 17:43:20.941699 ==
5147 17:43:20.945088 RX Vref Scan: 0
5148 17:43:20.945174
5149 17:43:20.945241 RX Vref 0 -> 0, step: 1
5150 17:43:20.945305
5151 17:43:20.948818 RX Delay -80 -> 252, step: 8
5152 17:43:20.951799 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5153 17:43:20.958238 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5154 17:43:20.961438 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5155 17:43:20.965247 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5156 17:43:20.968718 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5157 17:43:20.971650 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5158 17:43:20.974948 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5159 17:43:20.981520 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5160 17:43:20.985261 iDelay=208, Bit 8, Center 83 (0 ~ 167) 168
5161 17:43:20.988306 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5162 17:43:20.991559 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5163 17:43:20.994972 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5164 17:43:21.001799 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5165 17:43:21.005356 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5166 17:43:21.008588 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5167 17:43:21.012027 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5168 17:43:21.012116 ==
5169 17:43:21.015397 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 17:43:21.018797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 17:43:21.018882 ==
5172 17:43:21.022072 DQS Delay:
5173 17:43:21.022156 DQS0 = 0, DQS1 = 0
5174 17:43:21.025414 DQM Delay:
5175 17:43:21.025497 DQM0 = 104, DQM1 = 95
5176 17:43:21.025565 DQ Delay:
5177 17:43:21.028534 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5178 17:43:21.031754 DQ4 =103, DQ5 =91, DQ6 =115, DQ7 =115
5179 17:43:21.034969 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5180 17:43:21.041665 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5181 17:43:21.041749
5182 17:43:21.041816
5183 17:43:21.041877 ==
5184 17:43:21.045417 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 17:43:21.048501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 17:43:21.048585 ==
5187 17:43:21.048651
5188 17:43:21.048712
5189 17:43:21.052110 TX Vref Scan disable
5190 17:43:21.052194 == TX Byte 0 ==
5191 17:43:21.058483 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5192 17:43:21.061890 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5193 17:43:21.061975 == TX Byte 1 ==
5194 17:43:21.068068 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5195 17:43:21.071632 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5196 17:43:21.071754 ==
5197 17:43:21.075160 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 17:43:21.078238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 17:43:21.078321 ==
5200 17:43:21.078387
5201 17:43:21.082135
5202 17:43:21.082217 TX Vref Scan disable
5203 17:43:21.084672 == TX Byte 0 ==
5204 17:43:21.087967 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5205 17:43:21.091609 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5206 17:43:21.094815 == TX Byte 1 ==
5207 17:43:21.098220 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5208 17:43:21.101554 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5209 17:43:21.101658
5210 17:43:21.104985 [DATLAT]
5211 17:43:21.105088 Freq=933, CH0 RK0
5212 17:43:21.105179
5213 17:43:21.108302 DATLAT Default: 0xd
5214 17:43:21.108383 0, 0xFFFF, sum = 0
5215 17:43:21.111602 1, 0xFFFF, sum = 0
5216 17:43:21.111723 2, 0xFFFF, sum = 0
5217 17:43:21.115038 3, 0xFFFF, sum = 0
5218 17:43:21.115120 4, 0xFFFF, sum = 0
5219 17:43:21.118390 5, 0xFFFF, sum = 0
5220 17:43:21.118473 6, 0xFFFF, sum = 0
5221 17:43:21.121789 7, 0xFFFF, sum = 0
5222 17:43:21.125043 8, 0xFFFF, sum = 0
5223 17:43:21.125125 9, 0xFFFF, sum = 0
5224 17:43:21.128538 10, 0x0, sum = 1
5225 17:43:21.128621 11, 0x0, sum = 2
5226 17:43:21.128687 12, 0x0, sum = 3
5227 17:43:21.131673 13, 0x0, sum = 4
5228 17:43:21.131770 best_step = 11
5229 17:43:21.131836
5230 17:43:21.131897 ==
5231 17:43:21.134478 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 17:43:21.141373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 17:43:21.141456 ==
5234 17:43:21.141521 RX Vref Scan: 1
5235 17:43:21.141583
5236 17:43:21.144856 RX Vref 0 -> 0, step: 1
5237 17:43:21.144938
5238 17:43:21.148211 RX Delay -45 -> 252, step: 4
5239 17:43:21.148308
5240 17:43:21.151406 Set Vref, RX VrefLevel [Byte0]: 54
5241 17:43:21.154225 [Byte1]: 47
5242 17:43:21.154307
5243 17:43:21.158117 Final RX Vref Byte 0 = 54 to rank0
5244 17:43:21.161261 Final RX Vref Byte 1 = 47 to rank0
5245 17:43:21.164383 Final RX Vref Byte 0 = 54 to rank1
5246 17:43:21.167505 Final RX Vref Byte 1 = 47 to rank1==
5247 17:43:21.171176 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 17:43:21.174318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 17:43:21.174403 ==
5250 17:43:21.177580 DQS Delay:
5251 17:43:21.177661 DQS0 = 0, DQS1 = 0
5252 17:43:21.181259 DQM Delay:
5253 17:43:21.181370 DQM0 = 104, DQM1 = 94
5254 17:43:21.181464 DQ Delay:
5255 17:43:21.188043 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5256 17:43:21.191131 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5257 17:43:21.194072 DQ8 =86, DQ9 =82, DQ10 =96, DQ11 =90
5258 17:43:21.198049 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =102
5259 17:43:21.198132
5260 17:43:21.198259
5261 17:43:21.204653 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5262 17:43:21.207755 CH0 RK0: MR19=505, MR18=2E26
5263 17:43:21.214537 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5264 17:43:21.214627
5265 17:43:21.217842 ----->DramcWriteLeveling(PI) begin...
5266 17:43:21.217928 ==
5267 17:43:21.221233 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 17:43:21.224776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 17:43:21.224860 ==
5270 17:43:21.227396 Write leveling (Byte 0): 34 => 34
5271 17:43:21.230786 Write leveling (Byte 1): 31 => 31
5272 17:43:21.234048 DramcWriteLeveling(PI) end<-----
5273 17:43:21.234130
5274 17:43:21.234196 ==
5275 17:43:21.238015 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 17:43:21.240719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 17:43:21.240802 ==
5278 17:43:21.244024 [Gating] SW mode calibration
5279 17:43:21.251112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5280 17:43:21.257694 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5281 17:43:21.261030 0 14 0 | B1->B0 | 3131 3232 | 1 0 | (1 1) (0 0)
5282 17:43:21.264238 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 17:43:21.270964 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 17:43:21.274289 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 17:43:21.277518 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 17:43:21.284208 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 17:43:21.287378 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 17:43:21.291138 0 14 28 | B1->B0 | 2929 2929 | 0 0 | (0 1) (0 1)
5289 17:43:21.297813 0 15 0 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
5290 17:43:21.301079 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 17:43:21.304055 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 17:43:21.311288 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 17:43:21.314173 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 17:43:21.317903 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 17:43:21.324531 0 15 24 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
5296 17:43:21.327915 0 15 28 | B1->B0 | 3636 3434 | 0 0 | (0 0) (0 0)
5297 17:43:21.330644 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5298 17:43:21.337356 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 17:43:21.340627 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 17:43:21.344111 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 17:43:21.350669 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 17:43:21.354502 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 17:43:21.357878 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 17:43:21.364465 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 17:43:21.367728 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5306 17:43:21.370916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 17:43:21.377417 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 17:43:21.380860 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 17:43:21.384124 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 17:43:21.387441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 17:43:21.394007 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 17:43:21.397054 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 17:43:21.400517 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 17:43:21.407304 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 17:43:21.410645 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 17:43:21.413790 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 17:43:21.420687 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 17:43:21.423607 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 17:43:21.427115 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 17:43:21.433840 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5321 17:43:21.437137 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 17:43:21.440361 Total UI for P1: 0, mck2ui 16
5323 17:43:21.443572 best dqsien dly found for B0: ( 1, 2, 28)
5324 17:43:21.446977 Total UI for P1: 0, mck2ui 16
5325 17:43:21.450301 best dqsien dly found for B1: ( 1, 2, 28)
5326 17:43:21.453540 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5327 17:43:21.456756 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5328 17:43:21.456838
5329 17:43:21.460309 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5330 17:43:21.463449 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5331 17:43:21.466719 [Gating] SW calibration Done
5332 17:43:21.466885 ==
5333 17:43:21.469990 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 17:43:21.473356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 17:43:21.477019 ==
5336 17:43:21.477132 RX Vref Scan: 0
5337 17:43:21.477228
5338 17:43:21.480418 RX Vref 0 -> 0, step: 1
5339 17:43:21.480504
5340 17:43:21.483830 RX Delay -80 -> 252, step: 8
5341 17:43:21.487125 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5342 17:43:21.490468 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5343 17:43:21.493623 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5344 17:43:21.497008 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5345 17:43:21.503452 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5346 17:43:21.506601 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5347 17:43:21.510374 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5348 17:43:21.513284 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5349 17:43:21.516679 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5350 17:43:21.519967 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5351 17:43:21.523145 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5352 17:43:21.530049 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5353 17:43:21.533379 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5354 17:43:21.536642 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5355 17:43:21.540327 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5356 17:43:21.543273 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5357 17:43:21.546661 ==
5358 17:43:21.546771 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 17:43:21.553216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 17:43:21.553300 ==
5361 17:43:21.553366 DQS Delay:
5362 17:43:21.556574 DQS0 = 0, DQS1 = 0
5363 17:43:21.556657 DQM Delay:
5364 17:43:21.560113 DQM0 = 104, DQM1 = 94
5365 17:43:21.560196 DQ Delay:
5366 17:43:21.563387 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5367 17:43:21.566459 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5368 17:43:21.570173 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5369 17:43:21.573301 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5370 17:43:21.573394
5371 17:43:21.573461
5372 17:43:21.573522 ==
5373 17:43:21.576538 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 17:43:21.579794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 17:43:21.583018 ==
5376 17:43:21.583103
5377 17:43:21.583169
5378 17:43:21.583231 TX Vref Scan disable
5379 17:43:21.586261 == TX Byte 0 ==
5380 17:43:21.589516 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5381 17:43:21.592850 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5382 17:43:21.596569 == TX Byte 1 ==
5383 17:43:21.599931 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5384 17:43:21.603211 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5385 17:43:21.603317 ==
5386 17:43:21.606672 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 17:43:21.613150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 17:43:21.613262 ==
5389 17:43:21.613356
5390 17:43:21.613474
5391 17:43:21.615900 TX Vref Scan disable
5392 17:43:21.615975 == TX Byte 0 ==
5393 17:43:21.623001 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5394 17:43:21.625967 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5395 17:43:21.626069 == TX Byte 1 ==
5396 17:43:21.632869 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5397 17:43:21.636506 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5398 17:43:21.636616
5399 17:43:21.636708 [DATLAT]
5400 17:43:21.639626 Freq=933, CH0 RK1
5401 17:43:21.639756
5402 17:43:21.639819 DATLAT Default: 0xb
5403 17:43:21.642904 0, 0xFFFF, sum = 0
5404 17:43:21.643009 1, 0xFFFF, sum = 0
5405 17:43:21.645906 2, 0xFFFF, sum = 0
5406 17:43:21.646012 3, 0xFFFF, sum = 0
5407 17:43:21.649126 4, 0xFFFF, sum = 0
5408 17:43:21.649206 5, 0xFFFF, sum = 0
5409 17:43:21.653068 6, 0xFFFF, sum = 0
5410 17:43:21.653164 7, 0xFFFF, sum = 0
5411 17:43:21.656208 8, 0xFFFF, sum = 0
5412 17:43:21.656300 9, 0xFFFF, sum = 0
5413 17:43:21.659598 10, 0x0, sum = 1
5414 17:43:21.659708 11, 0x0, sum = 2
5415 17:43:21.663053 12, 0x0, sum = 3
5416 17:43:21.663152 13, 0x0, sum = 4
5417 17:43:21.666470 best_step = 11
5418 17:43:21.666551
5419 17:43:21.666615 ==
5420 17:43:21.669128 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 17:43:21.672371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 17:43:21.672454 ==
5423 17:43:21.676261 RX Vref Scan: 0
5424 17:43:21.676343
5425 17:43:21.676407 RX Vref 0 -> 0, step: 1
5426 17:43:21.676468
5427 17:43:21.679235 RX Delay -45 -> 252, step: 4
5428 17:43:21.686343 iDelay=195, Bit 0, Center 104 (15 ~ 194) 180
5429 17:43:21.689371 iDelay=195, Bit 1, Center 108 (23 ~ 194) 172
5430 17:43:21.692647 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5431 17:43:21.695861 iDelay=195, Bit 3, Center 100 (11 ~ 190) 180
5432 17:43:21.699582 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5433 17:43:21.706236 iDelay=195, Bit 5, Center 96 (7 ~ 186) 180
5434 17:43:21.709676 iDelay=195, Bit 6, Center 112 (31 ~ 194) 164
5435 17:43:21.712411 iDelay=195, Bit 7, Center 112 (31 ~ 194) 164
5436 17:43:21.716263 iDelay=195, Bit 8, Center 84 (-1 ~ 170) 172
5437 17:43:21.719500 iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168
5438 17:43:21.726235 iDelay=195, Bit 10, Center 92 (11 ~ 174) 164
5439 17:43:21.729506 iDelay=195, Bit 11, Center 86 (3 ~ 170) 168
5440 17:43:21.732706 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5441 17:43:21.735827 iDelay=195, Bit 13, Center 100 (19 ~ 182) 164
5442 17:43:21.739453 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5443 17:43:21.745893 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5444 17:43:21.746029 ==
5445 17:43:21.749539 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 17:43:21.752876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 17:43:21.752989 ==
5448 17:43:21.753084 DQS Delay:
5449 17:43:21.756247 DQS0 = 0, DQS1 = 0
5450 17:43:21.756323 DQM Delay:
5451 17:43:21.759428 DQM0 = 105, DQM1 = 93
5452 17:43:21.759550 DQ Delay:
5453 17:43:21.762524 DQ0 =104, DQ1 =108, DQ2 =102, DQ3 =100
5454 17:43:21.765863 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5455 17:43:21.769175 DQ8 =84, DQ9 =82, DQ10 =92, DQ11 =86
5456 17:43:21.772548 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5457 17:43:21.772653
5458 17:43:21.772751
5459 17:43:21.782651 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5460 17:43:21.782756 CH0 RK1: MR19=505, MR18=2902
5461 17:43:21.789192 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5462 17:43:21.792855 [RxdqsGatingPostProcess] freq 933
5463 17:43:21.799463 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5464 17:43:21.802453 best DQS0 dly(2T, 0.5T) = (0, 10)
5465 17:43:21.805796 best DQS1 dly(2T, 0.5T) = (0, 10)
5466 17:43:21.809032 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5467 17:43:21.812882 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5468 17:43:21.815559 best DQS0 dly(2T, 0.5T) = (0, 10)
5469 17:43:21.815679 best DQS1 dly(2T, 0.5T) = (0, 10)
5470 17:43:21.819586 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5471 17:43:21.822778 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5472 17:43:21.826020 Pre-setting of DQS Precalculation
5473 17:43:21.832729 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5474 17:43:21.832843 ==
5475 17:43:21.836157 Dram Type= 6, Freq= 0, CH_1, rank 0
5476 17:43:21.838909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 17:43:21.838998 ==
5478 17:43:21.845597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5479 17:43:21.852545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5480 17:43:21.856097 [CA 0] Center 36 (6~67) winsize 62
5481 17:43:21.859044 [CA 1] Center 36 (6~67) winsize 62
5482 17:43:21.862387 [CA 2] Center 34 (4~65) winsize 62
5483 17:43:21.865737 [CA 3] Center 34 (4~65) winsize 62
5484 17:43:21.869200 [CA 4] Center 34 (4~65) winsize 62
5485 17:43:21.872330 [CA 5] Center 33 (3~64) winsize 62
5486 17:43:21.872441
5487 17:43:21.875561 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5488 17:43:21.875704
5489 17:43:21.878850 [CATrainingPosCal] consider 1 rank data
5490 17:43:21.882201 u2DelayCellTimex100 = 270/100 ps
5491 17:43:21.885479 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5492 17:43:21.888854 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 17:43:21.892161 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5494 17:43:21.895513 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 17:43:21.898947 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5496 17:43:21.902011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5497 17:43:21.902149
5498 17:43:21.909091 CA PerBit enable=1, Macro0, CA PI delay=33
5499 17:43:21.909219
5500 17:43:21.909319 [CBTSetCACLKResult] CA Dly = 33
5501 17:43:21.912293 CS Dly: 6 (0~37)
5502 17:43:21.912426 ==
5503 17:43:21.915526 Dram Type= 6, Freq= 0, CH_1, rank 1
5504 17:43:21.919068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 17:43:21.919179 ==
5506 17:43:21.925631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 17:43:21.932190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5508 17:43:21.935482 [CA 0] Center 36 (6~67) winsize 62
5509 17:43:21.938830 [CA 1] Center 37 (6~68) winsize 63
5510 17:43:21.942168 [CA 2] Center 35 (5~65) winsize 61
5511 17:43:21.945314 [CA 3] Center 34 (4~65) winsize 62
5512 17:43:21.948699 [CA 4] Center 34 (4~65) winsize 62
5513 17:43:21.951887 [CA 5] Center 33 (3~64) winsize 62
5514 17:43:21.951963
5515 17:43:21.955180 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5516 17:43:21.955259
5517 17:43:21.958448 [CATrainingPosCal] consider 2 rank data
5518 17:43:21.961900 u2DelayCellTimex100 = 270/100 ps
5519 17:43:21.965119 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 17:43:21.968420 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 17:43:21.972043 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5522 17:43:21.975606 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5523 17:43:21.978431 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5524 17:43:21.982095 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 17:43:21.982175
5526 17:43:21.988474 CA PerBit enable=1, Macro0, CA PI delay=33
5527 17:43:21.988585
5528 17:43:21.991802 [CBTSetCACLKResult] CA Dly = 33
5529 17:43:21.991907 CS Dly: 7 (0~40)
5530 17:43:21.992014
5531 17:43:21.995726 ----->DramcWriteLeveling(PI) begin...
5532 17:43:21.995808 ==
5533 17:43:21.998998 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 17:43:22.001624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 17:43:22.001726 ==
5536 17:43:22.005580 Write leveling (Byte 0): 27 => 27
5537 17:43:22.008813 Write leveling (Byte 1): 28 => 28
5538 17:43:22.012133 DramcWriteLeveling(PI) end<-----
5539 17:43:22.012220
5540 17:43:22.012286 ==
5541 17:43:22.015489 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 17:43:22.022173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 17:43:22.022263 ==
5544 17:43:22.022351 [Gating] SW mode calibration
5545 17:43:22.031783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5546 17:43:22.035270 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5547 17:43:22.038238 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 17:43:22.045230 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 17:43:22.048854 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 17:43:22.052302 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 17:43:22.058926 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 17:43:22.062311 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 17:43:22.065656 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5554 17:43:22.071656 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5555 17:43:22.075656 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 17:43:22.078927 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 17:43:22.085310 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 17:43:22.088501 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 17:43:22.091596 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 17:43:22.098395 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 17:43:22.101673 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
5562 17:43:22.105107 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
5563 17:43:22.111782 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 17:43:22.115049 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 17:43:22.118301 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 17:43:22.124927 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 17:43:22.128264 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 17:43:22.131609 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 17:43:22.138219 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5570 17:43:22.141483 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 17:43:22.144780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 17:43:22.148120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 17:43:22.155027 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 17:43:22.158010 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 17:43:22.161577 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 17:43:22.168080 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 17:43:22.171458 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 17:43:22.174707 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 17:43:22.181525 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 17:43:22.184725 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 17:43:22.188182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 17:43:22.194595 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 17:43:22.198370 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 17:43:22.201576 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5585 17:43:22.208092 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5586 17:43:22.211221 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 17:43:22.214985 Total UI for P1: 0, mck2ui 16
5588 17:43:22.218190 best dqsien dly found for B0: ( 1, 2, 22)
5589 17:43:22.221266 Total UI for P1: 0, mck2ui 16
5590 17:43:22.224974 best dqsien dly found for B1: ( 1, 2, 24)
5591 17:43:22.228014 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5592 17:43:22.231417 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5593 17:43:22.231504
5594 17:43:22.234879 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5595 17:43:22.238215 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5596 17:43:22.241476 [Gating] SW calibration Done
5597 17:43:22.241552 ==
5598 17:43:22.244918 Dram Type= 6, Freq= 0, CH_1, rank 0
5599 17:43:22.248342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 17:43:22.248445 ==
5601 17:43:22.251188 RX Vref Scan: 0
5602 17:43:22.251299
5603 17:43:22.254774 RX Vref 0 -> 0, step: 1
5604 17:43:22.254855
5605 17:43:22.254950 RX Delay -80 -> 252, step: 8
5606 17:43:22.261613 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5607 17:43:22.265048 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5608 17:43:22.267778 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5609 17:43:22.271599 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5610 17:43:22.274839 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5611 17:43:22.277939 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5612 17:43:22.284828 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5613 17:43:22.288021 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5614 17:43:22.291497 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5615 17:43:22.294268 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5616 17:43:22.297575 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5617 17:43:22.300944 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5618 17:43:22.307802 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5619 17:43:22.311453 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5620 17:43:22.314938 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5621 17:43:22.317509 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5622 17:43:22.317598 ==
5623 17:43:22.320821 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 17:43:22.327883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 17:43:22.327975 ==
5626 17:43:22.328044 DQS Delay:
5627 17:43:22.330876 DQS0 = 0, DQS1 = 0
5628 17:43:22.330961 DQM Delay:
5629 17:43:22.334158 DQM0 = 102, DQM1 = 99
5630 17:43:22.334270 DQ Delay:
5631 17:43:22.337817 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5632 17:43:22.341189 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5633 17:43:22.344656 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5634 17:43:22.347865 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5635 17:43:22.347952
5636 17:43:22.348020
5637 17:43:22.348081 ==
5638 17:43:22.350635 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 17:43:22.353950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 17:43:22.354060 ==
5641 17:43:22.354131
5642 17:43:22.357343
5643 17:43:22.357427 TX Vref Scan disable
5644 17:43:22.360946 == TX Byte 0 ==
5645 17:43:22.364200 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5646 17:43:22.367615 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5647 17:43:22.371073 == TX Byte 1 ==
5648 17:43:22.374336 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5649 17:43:22.377706 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5650 17:43:22.377794 ==
5651 17:43:22.380898 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 17:43:22.386999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 17:43:22.387086 ==
5654 17:43:22.387153
5655 17:43:22.387222
5656 17:43:22.387282 TX Vref Scan disable
5657 17:43:22.391074 == TX Byte 0 ==
5658 17:43:22.394535 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 17:43:22.401022 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 17:43:22.401121 == TX Byte 1 ==
5661 17:43:22.404670 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5662 17:43:22.411099 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5663 17:43:22.411215
5664 17:43:22.411285 [DATLAT]
5665 17:43:22.411347 Freq=933, CH1 RK0
5666 17:43:22.411409
5667 17:43:22.414396 DATLAT Default: 0xd
5668 17:43:22.417619 0, 0xFFFF, sum = 0
5669 17:43:22.417731 1, 0xFFFF, sum = 0
5670 17:43:22.421304 2, 0xFFFF, sum = 0
5671 17:43:22.421410 3, 0xFFFF, sum = 0
5672 17:43:22.424393 4, 0xFFFF, sum = 0
5673 17:43:22.424500 5, 0xFFFF, sum = 0
5674 17:43:22.428162 6, 0xFFFF, sum = 0
5675 17:43:22.428248 7, 0xFFFF, sum = 0
5676 17:43:22.430819 8, 0xFFFF, sum = 0
5677 17:43:22.430938 9, 0xFFFF, sum = 0
5678 17:43:22.434625 10, 0x0, sum = 1
5679 17:43:22.434775 11, 0x0, sum = 2
5680 17:43:22.437675 12, 0x0, sum = 3
5681 17:43:22.437768 13, 0x0, sum = 4
5682 17:43:22.437838 best_step = 11
5683 17:43:22.440934
5684 17:43:22.441021 ==
5685 17:43:22.444212 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 17:43:22.447489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 17:43:22.447601 ==
5688 17:43:22.447696 RX Vref Scan: 1
5689 17:43:22.447762
5690 17:43:22.451122 RX Vref 0 -> 0, step: 1
5691 17:43:22.451206
5692 17:43:22.454408 RX Delay -45 -> 252, step: 4
5693 17:43:22.454494
5694 17:43:22.457987 Set Vref, RX VrefLevel [Byte0]: 52
5695 17:43:22.461456 [Byte1]: 51
5696 17:43:22.461542
5697 17:43:22.464701 Final RX Vref Byte 0 = 52 to rank0
5698 17:43:22.467376 Final RX Vref Byte 1 = 51 to rank0
5699 17:43:22.470758 Final RX Vref Byte 0 = 52 to rank1
5700 17:43:22.474122 Final RX Vref Byte 1 = 51 to rank1==
5701 17:43:22.477562 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 17:43:22.480993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 17:43:22.481080 ==
5704 17:43:22.484234 DQS Delay:
5705 17:43:22.484320 DQS0 = 0, DQS1 = 0
5706 17:43:22.487659 DQM Delay:
5707 17:43:22.487736 DQM0 = 103, DQM1 = 99
5708 17:43:22.491237 DQ Delay:
5709 17:43:22.494359 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5710 17:43:22.497755 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5711 17:43:22.501189 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5712 17:43:22.504621 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5713 17:43:22.504706
5714 17:43:22.504772
5715 17:43:22.510659 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5716 17:43:22.514068 CH1 RK0: MR19=505, MR18=1830
5717 17:43:22.521051 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5718 17:43:22.521143
5719 17:43:22.524435 ----->DramcWriteLeveling(PI) begin...
5720 17:43:22.524554 ==
5721 17:43:22.527606 Dram Type= 6, Freq= 0, CH_1, rank 1
5722 17:43:22.530765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 17:43:22.530854 ==
5724 17:43:22.534157 Write leveling (Byte 0): 27 => 27
5725 17:43:22.537308 Write leveling (Byte 1): 29 => 29
5726 17:43:22.540681 DramcWriteLeveling(PI) end<-----
5727 17:43:22.540767
5728 17:43:22.540835 ==
5729 17:43:22.544207 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 17:43:22.546946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 17:43:22.550676 ==
5732 17:43:22.550763 [Gating] SW mode calibration
5733 17:43:22.560613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5734 17:43:22.564015 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5735 17:43:22.567193 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 17:43:22.573732 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 17:43:22.577120 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 17:43:22.580483 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 17:43:22.587090 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 17:43:22.590520 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 17:43:22.593797 0 14 24 | B1->B0 | 2e2e 3131 | 0 0 | (1 0) (1 0)
5742 17:43:22.600598 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5743 17:43:22.604039 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 17:43:22.607363 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 17:43:22.613747 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 17:43:22.617579 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 17:43:22.620391 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 17:43:22.623645 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 17:43:22.630463 0 15 24 | B1->B0 | 3535 2727 | 1 0 | (0 0) (1 1)
5750 17:43:22.633742 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5751 17:43:22.637330 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 17:43:22.644270 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 17:43:22.647432 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 17:43:22.650735 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 17:43:22.657256 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 17:43:22.660648 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 17:43:22.663884 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5758 17:43:22.670485 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5759 17:43:22.673918 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 17:43:22.676938 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 17:43:22.683629 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 17:43:22.686844 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 17:43:22.690584 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 17:43:22.696588 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 17:43:22.699949 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 17:43:22.703370 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 17:43:22.710381 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 17:43:22.713393 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 17:43:22.717495 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 17:43:22.723438 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 17:43:22.726853 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 17:43:22.730194 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 17:43:22.737145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5774 17:43:22.740608 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5775 17:43:22.743955 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 17:43:22.746610 Total UI for P1: 0, mck2ui 16
5777 17:43:22.749944 best dqsien dly found for B0: ( 1, 2, 26)
5778 17:43:22.753699 Total UI for P1: 0, mck2ui 16
5779 17:43:22.757007 best dqsien dly found for B1: ( 1, 2, 26)
5780 17:43:22.759945 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5781 17:43:22.763276 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5782 17:43:22.763362
5783 17:43:22.766574 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5784 17:43:22.773285 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5785 17:43:22.773433 [Gating] SW calibration Done
5786 17:43:22.773535 ==
5787 17:43:22.776647 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 17:43:22.783410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 17:43:22.783530 ==
5790 17:43:22.783631 RX Vref Scan: 0
5791 17:43:22.783740
5792 17:43:22.786828 RX Vref 0 -> 0, step: 1
5793 17:43:22.786936
5794 17:43:22.790352 RX Delay -80 -> 252, step: 8
5795 17:43:22.793574 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5796 17:43:22.796987 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5797 17:43:22.800379 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5798 17:43:22.803688 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5799 17:43:22.809886 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5800 17:43:22.813223 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5801 17:43:22.816762 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5802 17:43:22.819873 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5803 17:43:22.823416 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5804 17:43:22.826745 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5805 17:43:22.829841 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5806 17:43:22.836607 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5807 17:43:22.840033 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5808 17:43:22.843427 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5809 17:43:22.846741 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5810 17:43:22.853530 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5811 17:43:22.853654 ==
5812 17:43:22.856835 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 17:43:22.860051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 17:43:22.860160 ==
5815 17:43:22.860252 DQS Delay:
5816 17:43:22.863355 DQS0 = 0, DQS1 = 0
5817 17:43:22.863461 DQM Delay:
5818 17:43:22.866751 DQM0 = 101, DQM1 = 98
5819 17:43:22.866871 DQ Delay:
5820 17:43:22.870101 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5821 17:43:22.873611 DQ4 =95, DQ5 =115, DQ6 =107, DQ7 =99
5822 17:43:22.876701 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5823 17:43:22.879958 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5824 17:43:22.880068
5825 17:43:22.880162
5826 17:43:22.880268 ==
5827 17:43:22.883265 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 17:43:22.886610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 17:43:22.889958 ==
5830 17:43:22.890070
5831 17:43:22.890170
5832 17:43:22.890255 TX Vref Scan disable
5833 17:43:22.893460 == TX Byte 0 ==
5834 17:43:22.896704 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5835 17:43:22.900185 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5836 17:43:22.903481 == TX Byte 1 ==
5837 17:43:22.906224 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5838 17:43:22.909679 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5839 17:43:22.909795 ==
5840 17:43:22.913095 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 17:43:22.919492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 17:43:22.919619 ==
5843 17:43:22.919724
5844 17:43:22.919831
5845 17:43:22.922772 TX Vref Scan disable
5846 17:43:22.922883 == TX Byte 0 ==
5847 17:43:22.929760 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5848 17:43:22.933089 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5849 17:43:22.933204 == TX Byte 1 ==
5850 17:43:22.939791 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5851 17:43:22.942941 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5852 17:43:22.943063
5853 17:43:22.943157 [DATLAT]
5854 17:43:22.946293 Freq=933, CH1 RK1
5855 17:43:22.946414
5856 17:43:22.946509 DATLAT Default: 0xb
5857 17:43:22.949424 0, 0xFFFF, sum = 0
5858 17:43:22.949544 1, 0xFFFF, sum = 0
5859 17:43:22.952696 2, 0xFFFF, sum = 0
5860 17:43:22.952804 3, 0xFFFF, sum = 0
5861 17:43:22.956015 4, 0xFFFF, sum = 0
5862 17:43:22.956123 5, 0xFFFF, sum = 0
5863 17:43:22.959452 6, 0xFFFF, sum = 0
5864 17:43:22.959559 7, 0xFFFF, sum = 0
5865 17:43:22.962885 8, 0xFFFF, sum = 0
5866 17:43:22.963002 9, 0xFFFF, sum = 0
5867 17:43:22.965959 10, 0x0, sum = 1
5868 17:43:22.966080 11, 0x0, sum = 2
5869 17:43:22.969566 12, 0x0, sum = 3
5870 17:43:22.969715 13, 0x0, sum = 4
5871 17:43:22.972977 best_step = 11
5872 17:43:22.973095
5873 17:43:22.973212 ==
5874 17:43:22.976296 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 17:43:22.979361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 17:43:22.979478 ==
5877 17:43:22.982945 RX Vref Scan: 0
5878 17:43:22.983034
5879 17:43:22.983102 RX Vref 0 -> 0, step: 1
5880 17:43:22.983167
5881 17:43:22.986070 RX Delay -45 -> 252, step: 4
5882 17:43:22.992901 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5883 17:43:22.996276 iDelay=199, Bit 1, Center 98 (15 ~ 182) 168
5884 17:43:22.999523 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5885 17:43:23.002975 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5886 17:43:23.006087 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5887 17:43:23.013218 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5888 17:43:23.016060 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5889 17:43:23.019959 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5890 17:43:23.023347 iDelay=199, Bit 8, Center 88 (3 ~ 174) 172
5891 17:43:23.026663 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5892 17:43:23.029582 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5893 17:43:23.036335 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5894 17:43:23.039643 iDelay=199, Bit 12, Center 112 (27 ~ 198) 172
5895 17:43:23.042990 iDelay=199, Bit 13, Center 108 (27 ~ 190) 164
5896 17:43:23.046346 iDelay=199, Bit 14, Center 108 (27 ~ 190) 164
5897 17:43:23.053227 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5898 17:43:23.053331 ==
5899 17:43:23.055959 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 17:43:23.059433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 17:43:23.059550 ==
5902 17:43:23.059657 DQS Delay:
5903 17:43:23.062885 DQS0 = 0, DQS1 = 0
5904 17:43:23.062974 DQM Delay:
5905 17:43:23.066244 DQM0 = 104, DQM1 = 100
5906 17:43:23.066331 DQ Delay:
5907 17:43:23.069623 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5908 17:43:23.072860 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5909 17:43:23.076056 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5910 17:43:23.079438 DQ12 =112, DQ13 =108, DQ14 =108, DQ15 =110
5911 17:43:23.079556
5912 17:43:23.079666
5913 17:43:23.089191 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5914 17:43:23.089296 CH1 RK1: MR19=504, MR18=2CFF
5915 17:43:23.096097 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5916 17:43:23.099351 [RxdqsGatingPostProcess] freq 933
5917 17:43:23.106209 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5918 17:43:23.109555 best DQS0 dly(2T, 0.5T) = (0, 10)
5919 17:43:23.112579 best DQS1 dly(2T, 0.5T) = (0, 10)
5920 17:43:23.116591 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5921 17:43:23.119394 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5922 17:43:23.122729 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 17:43:23.122808 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 17:43:23.126024 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 17:43:23.129935 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 17:43:23.132635 Pre-setting of DQS Precalculation
5927 17:43:23.139547 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5928 17:43:23.146366 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5929 17:43:23.153073 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5930 17:43:23.153173
5931 17:43:23.153243
5932 17:43:23.156501 [Calibration Summary] 1866 Mbps
5933 17:43:23.156582 CH 0, Rank 0
5934 17:43:23.159784 SW Impedance : PASS
5935 17:43:23.163184 DUTY Scan : NO K
5936 17:43:23.163265 ZQ Calibration : PASS
5937 17:43:23.165850 Jitter Meter : NO K
5938 17:43:23.169326 CBT Training : PASS
5939 17:43:23.169443 Write leveling : PASS
5940 17:43:23.172705 RX DQS gating : PASS
5941 17:43:23.175955 RX DQ/DQS(RDDQC) : PASS
5942 17:43:23.176043 TX DQ/DQS : PASS
5943 17:43:23.179224 RX DATLAT : PASS
5944 17:43:23.182704 RX DQ/DQS(Engine): PASS
5945 17:43:23.182794 TX OE : NO K
5946 17:43:23.185932 All Pass.
5947 17:43:23.186018
5948 17:43:23.186105 CH 0, Rank 1
5949 17:43:23.189461 SW Impedance : PASS
5950 17:43:23.189571 DUTY Scan : NO K
5951 17:43:23.192704 ZQ Calibration : PASS
5952 17:43:23.196012 Jitter Meter : NO K
5953 17:43:23.196100 CBT Training : PASS
5954 17:43:23.199432 Write leveling : PASS
5955 17:43:23.199516 RX DQS gating : PASS
5956 17:43:23.202835 RX DQ/DQS(RDDQC) : PASS
5957 17:43:23.205940 TX DQ/DQS : PASS
5958 17:43:23.206032 RX DATLAT : PASS
5959 17:43:23.209091 RX DQ/DQS(Engine): PASS
5960 17:43:23.212778 TX OE : NO K
5961 17:43:23.212891 All Pass.
5962 17:43:23.212997
5963 17:43:23.213098 CH 1, Rank 0
5964 17:43:23.216100 SW Impedance : PASS
5965 17:43:23.218963 DUTY Scan : NO K
5966 17:43:23.219079 ZQ Calibration : PASS
5967 17:43:23.222623 Jitter Meter : NO K
5968 17:43:23.225747 CBT Training : PASS
5969 17:43:23.225862 Write leveling : PASS
5970 17:43:23.229021 RX DQS gating : PASS
5971 17:43:23.232234 RX DQ/DQS(RDDQC) : PASS
5972 17:43:23.232347 TX DQ/DQS : PASS
5973 17:43:23.235798 RX DATLAT : PASS
5974 17:43:23.238980 RX DQ/DQS(Engine): PASS
5975 17:43:23.239090 TX OE : NO K
5976 17:43:23.239194 All Pass.
5977 17:43:23.242219
5978 17:43:23.242309 CH 1, Rank 1
5979 17:43:23.245631 SW Impedance : PASS
5980 17:43:23.245721 DUTY Scan : NO K
5981 17:43:23.249272 ZQ Calibration : PASS
5982 17:43:23.252680 Jitter Meter : NO K
5983 17:43:23.252776 CBT Training : PASS
5984 17:43:23.255525 Write leveling : PASS
5985 17:43:23.255615 RX DQS gating : PASS
5986 17:43:23.258995 RX DQ/DQS(RDDQC) : PASS
5987 17:43:23.262388 TX DQ/DQS : PASS
5988 17:43:23.262509 RX DATLAT : PASS
5989 17:43:23.265753 RX DQ/DQS(Engine): PASS
5990 17:43:23.268575 TX OE : NO K
5991 17:43:23.268682 All Pass.
5992 17:43:23.268777
5993 17:43:23.271890 DramC Write-DBI off
5994 17:43:23.271966 PER_BANK_REFRESH: Hybrid Mode
5995 17:43:23.275407 TX_TRACKING: ON
5996 17:43:23.285758 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5997 17:43:23.289029 [FAST_K] Save calibration result to emmc
5998 17:43:23.292438 dramc_set_vcore_voltage set vcore to 650000
5999 17:43:23.292532 Read voltage for 400, 6
6000 17:43:23.295261 Vio18 = 0
6001 17:43:23.295365 Vcore = 650000
6002 17:43:23.295449 Vdram = 0
6003 17:43:23.298583 Vddq = 0
6004 17:43:23.298661 Vmddr = 0
6005 17:43:23.305314 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6006 17:43:23.308660 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6007 17:43:23.312004 MEM_TYPE=3, freq_sel=20
6008 17:43:23.315060 sv_algorithm_assistance_LP4_800
6009 17:43:23.318639 ============ PULL DRAM RESETB DOWN ============
6010 17:43:23.322050 ========== PULL DRAM RESETB DOWN end =========
6011 17:43:23.328406 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6012 17:43:23.332169 ===================================
6013 17:43:23.332282 LPDDR4 DRAM CONFIGURATION
6014 17:43:23.335352 ===================================
6015 17:43:23.338670 EX_ROW_EN[0] = 0x0
6016 17:43:23.338779 EX_ROW_EN[1] = 0x0
6017 17:43:23.341766 LP4Y_EN = 0x0
6018 17:43:23.341877 WORK_FSP = 0x0
6019 17:43:23.345356 WL = 0x2
6020 17:43:23.348291 RL = 0x2
6021 17:43:23.348396 BL = 0x2
6022 17:43:23.351512 RPST = 0x0
6023 17:43:23.351625 RD_PRE = 0x0
6024 17:43:23.355340 WR_PRE = 0x1
6025 17:43:23.355447 WR_PST = 0x0
6026 17:43:23.358605 DBI_WR = 0x0
6027 17:43:23.358715 DBI_RD = 0x0
6028 17:43:23.361757 OTF = 0x1
6029 17:43:23.365063 ===================================
6030 17:43:23.368563 ===================================
6031 17:43:23.368679 ANA top config
6032 17:43:23.372020 ===================================
6033 17:43:23.375343 DLL_ASYNC_EN = 0
6034 17:43:23.378695 ALL_SLAVE_EN = 1
6035 17:43:23.378805 NEW_RANK_MODE = 1
6036 17:43:23.381444 DLL_IDLE_MODE = 1
6037 17:43:23.385078 LP45_APHY_COMB_EN = 1
6038 17:43:23.388361 TX_ODT_DIS = 1
6039 17:43:23.388479 NEW_8X_MODE = 1
6040 17:43:23.391782 ===================================
6041 17:43:23.394990 ===================================
6042 17:43:23.398133 data_rate = 800
6043 17:43:23.401801 CKR = 1
6044 17:43:23.405087 DQ_P2S_RATIO = 4
6045 17:43:23.408378 ===================================
6046 17:43:23.411771 CA_P2S_RATIO = 4
6047 17:43:23.415057 DQ_CA_OPEN = 0
6048 17:43:23.418270 DQ_SEMI_OPEN = 1
6049 17:43:23.418385 CA_SEMI_OPEN = 1
6050 17:43:23.421589 CA_FULL_RATE = 0
6051 17:43:23.425047 DQ_CKDIV4_EN = 0
6052 17:43:23.428440 CA_CKDIV4_EN = 1
6053 17:43:23.431826 CA_PREDIV_EN = 0
6054 17:43:23.431946 PH8_DLY = 0
6055 17:43:23.434702 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6056 17:43:23.438533 DQ_AAMCK_DIV = 0
6057 17:43:23.441769 CA_AAMCK_DIV = 0
6058 17:43:23.445085 CA_ADMCK_DIV = 4
6059 17:43:23.448588 DQ_TRACK_CA_EN = 0
6060 17:43:23.448695 CA_PICK = 800
6061 17:43:23.451295 CA_MCKIO = 400
6062 17:43:23.454661 MCKIO_SEMI = 400
6063 17:43:23.457812 PLL_FREQ = 3016
6064 17:43:23.461328 DQ_UI_PI_RATIO = 32
6065 17:43:23.464901 CA_UI_PI_RATIO = 32
6066 17:43:23.468391 ===================================
6067 17:43:23.471611 ===================================
6068 17:43:23.474801 memory_type:LPDDR4
6069 17:43:23.474884 GP_NUM : 10
6070 17:43:23.478218 SRAM_EN : 1
6071 17:43:23.478297 MD32_EN : 0
6072 17:43:23.481365 ===================================
6073 17:43:23.484886 [ANA_INIT] >>>>>>>>>>>>>>
6074 17:43:23.487970 <<<<<< [CONFIGURE PHASE]: ANA_TX
6075 17:43:23.491501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6076 17:43:23.494868 ===================================
6077 17:43:23.498176 data_rate = 800,PCW = 0X7400
6078 17:43:23.501577 ===================================
6079 17:43:23.504522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6080 17:43:23.511171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 17:43:23.521554 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 17:43:23.524721 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6083 17:43:23.527409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6084 17:43:23.531569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6085 17:43:23.534292 [ANA_INIT] flow start
6086 17:43:23.538296 [ANA_INIT] PLL >>>>>>>>
6087 17:43:23.538405 [ANA_INIT] PLL <<<<<<<<
6088 17:43:23.541147 [ANA_INIT] MIDPI >>>>>>>>
6089 17:43:23.544603 [ANA_INIT] MIDPI <<<<<<<<
6090 17:43:23.547870 [ANA_INIT] DLL >>>>>>>>
6091 17:43:23.547972 [ANA_INIT] flow end
6092 17:43:23.551086 ============ LP4 DIFF to SE enter ============
6093 17:43:23.558091 ============ LP4 DIFF to SE exit ============
6094 17:43:23.558203 [ANA_INIT] <<<<<<<<<<<<<
6095 17:43:23.561412 [Flow] Enable top DCM control >>>>>
6096 17:43:23.563954 [Flow] Enable top DCM control <<<<<
6097 17:43:23.567965 Enable DLL master slave shuffle
6098 17:43:23.574572 ==============================================================
6099 17:43:23.574658 Gating Mode config
6100 17:43:23.580803 ==============================================================
6101 17:43:23.584182 Config description:
6102 17:43:23.590801 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6103 17:43:23.601044 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6104 17:43:23.603719 SELPH_MODE 0: By rank 1: By Phase
6105 17:43:23.610534 ==============================================================
6106 17:43:23.613952 GAT_TRACK_EN = 0
6107 17:43:23.614054 RX_GATING_MODE = 2
6108 17:43:23.617055 RX_GATING_TRACK_MODE = 2
6109 17:43:23.620871 SELPH_MODE = 1
6110 17:43:23.624365 PICG_EARLY_EN = 1
6111 17:43:23.627600 VALID_LAT_VALUE = 1
6112 17:43:23.634163 ==============================================================
6113 17:43:23.637547 Enter into Gating configuration >>>>
6114 17:43:23.640944 Exit from Gating configuration <<<<
6115 17:43:23.643837 Enter into DVFS_PRE_config >>>>>
6116 17:43:23.653963 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6117 17:43:23.657168 Exit from DVFS_PRE_config <<<<<
6118 17:43:23.660985 Enter into PICG configuration >>>>
6119 17:43:23.663730 Exit from PICG configuration <<<<
6120 17:43:23.667174 [RX_INPUT] configuration >>>>>
6121 17:43:23.670395 [RX_INPUT] configuration <<<<<
6122 17:43:23.673821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6123 17:43:23.680585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6124 17:43:23.687130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6125 17:43:23.690535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6126 17:43:23.697037 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 17:43:23.703695 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 17:43:23.706912 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6129 17:43:23.710202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6130 17:43:23.717111 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6131 17:43:23.720474 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6132 17:43:23.723739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6133 17:43:23.730238 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 17:43:23.733584 ===================================
6135 17:43:23.733708 LPDDR4 DRAM CONFIGURATION
6136 17:43:23.737021 ===================================
6137 17:43:23.740312 EX_ROW_EN[0] = 0x0
6138 17:43:23.743656 EX_ROW_EN[1] = 0x0
6139 17:43:23.743742 LP4Y_EN = 0x0
6140 17:43:23.747050 WORK_FSP = 0x0
6141 17:43:23.747132 WL = 0x2
6142 17:43:23.750411 RL = 0x2
6143 17:43:23.750491 BL = 0x2
6144 17:43:23.753829 RPST = 0x0
6145 17:43:23.753945 RD_PRE = 0x0
6146 17:43:23.757183 WR_PRE = 0x1
6147 17:43:23.757272 WR_PST = 0x0
6148 17:43:23.760040 DBI_WR = 0x0
6149 17:43:23.760162 DBI_RD = 0x0
6150 17:43:23.763466 OTF = 0x1
6151 17:43:23.766633 ===================================
6152 17:43:23.770421 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6153 17:43:23.773869 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6154 17:43:23.780177 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 17:43:23.783581 ===================================
6156 17:43:23.783710 LPDDR4 DRAM CONFIGURATION
6157 17:43:23.787043 ===================================
6158 17:43:23.790362 EX_ROW_EN[0] = 0x10
6159 17:43:23.790474 EX_ROW_EN[1] = 0x0
6160 17:43:23.793795 LP4Y_EN = 0x0
6161 17:43:23.793881 WORK_FSP = 0x0
6162 17:43:23.796451 WL = 0x2
6163 17:43:23.800015 RL = 0x2
6164 17:43:23.800136 BL = 0x2
6165 17:43:23.803120 RPST = 0x0
6166 17:43:23.803220 RD_PRE = 0x0
6167 17:43:23.806354 WR_PRE = 0x1
6168 17:43:23.806468 WR_PST = 0x0
6169 17:43:23.809828 DBI_WR = 0x0
6170 17:43:23.809947 DBI_RD = 0x0
6171 17:43:23.813580 OTF = 0x1
6172 17:43:23.816649 ===================================
6173 17:43:23.823202 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6174 17:43:23.826774 nWR fixed to 30
6175 17:43:23.826893 [ModeRegInit_LP4] CH0 RK0
6176 17:43:23.830038 [ModeRegInit_LP4] CH0 RK1
6177 17:43:23.833554 [ModeRegInit_LP4] CH1 RK0
6178 17:43:23.833681 [ModeRegInit_LP4] CH1 RK1
6179 17:43:23.836824 match AC timing 19
6180 17:43:23.839594 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6181 17:43:23.843440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6182 17:43:23.849434 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6183 17:43:23.852809 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6184 17:43:23.859776 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6185 17:43:23.859897 ==
6186 17:43:23.863080 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 17:43:23.866549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6188 17:43:23.866675 ==
6189 17:43:23.872885 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6190 17:43:23.876344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6191 17:43:23.879704 [CA 0] Center 36 (8~64) winsize 57
6192 17:43:23.882987 [CA 1] Center 36 (8~64) winsize 57
6193 17:43:23.886490 [CA 2] Center 36 (8~64) winsize 57
6194 17:43:23.889826 [CA 3] Center 36 (8~64) winsize 57
6195 17:43:23.893345 [CA 4] Center 36 (8~64) winsize 57
6196 17:43:23.896113 [CA 5] Center 36 (8~64) winsize 57
6197 17:43:23.896238
6198 17:43:23.899381 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6199 17:43:23.899496
6200 17:43:23.902772 [CATrainingPosCal] consider 1 rank data
6201 17:43:23.906218 u2DelayCellTimex100 = 270/100 ps
6202 17:43:23.909669 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 17:43:23.912964 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 17:43:23.916123 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 17:43:23.922982 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 17:43:23.926041 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 17:43:23.929762 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 17:43:23.929886
6209 17:43:23.932854 CA PerBit enable=1, Macro0, CA PI delay=36
6210 17:43:23.932963
6211 17:43:23.936105 [CBTSetCACLKResult] CA Dly = 36
6212 17:43:23.936227 CS Dly: 1 (0~32)
6213 17:43:23.936327 ==
6214 17:43:23.939170 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 17:43:23.945650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 17:43:23.945783 ==
6217 17:43:23.949513 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 17:43:23.955952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6219 17:43:23.959415 [CA 0] Center 36 (8~64) winsize 57
6220 17:43:23.962868 [CA 1] Center 36 (8~64) winsize 57
6221 17:43:23.966252 [CA 2] Center 36 (8~64) winsize 57
6222 17:43:23.969540 [CA 3] Center 36 (8~64) winsize 57
6223 17:43:23.972344 [CA 4] Center 36 (8~64) winsize 57
6224 17:43:23.975681 [CA 5] Center 36 (8~64) winsize 57
6225 17:43:23.975800
6226 17:43:23.978981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6227 17:43:23.979092
6228 17:43:23.982831 [CATrainingPosCal] consider 2 rank data
6229 17:43:23.985997 u2DelayCellTimex100 = 270/100 ps
6230 17:43:23.989129 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 17:43:23.992267 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 17:43:23.995758 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 17:43:23.999243 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 17:43:24.002870 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 17:43:24.005573 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 17:43:24.009487
6237 17:43:24.012585 CA PerBit enable=1, Macro0, CA PI delay=36
6238 17:43:24.012706
6239 17:43:24.015761 [CBTSetCACLKResult] CA Dly = 36
6240 17:43:24.015884 CS Dly: 1 (0~32)
6241 17:43:24.015990
6242 17:43:24.019279 ----->DramcWriteLeveling(PI) begin...
6243 17:43:24.019399 ==
6244 17:43:24.022622 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 17:43:24.025791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 17:43:24.029217 ==
6247 17:43:24.029334 Write leveling (Byte 0): 40 => 8
6248 17:43:24.032382 Write leveling (Byte 1): 40 => 8
6249 17:43:24.035728 DramcWriteLeveling(PI) end<-----
6250 17:43:24.035850
6251 17:43:24.035951 ==
6252 17:43:24.038912 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 17:43:24.045463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 17:43:24.045586 ==
6255 17:43:24.045684 [Gating] SW mode calibration
6256 17:43:24.055787 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6257 17:43:24.058917 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6258 17:43:24.062073 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 17:43:24.068854 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 17:43:24.072202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 17:43:24.075492 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 17:43:24.082331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 17:43:24.085612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 17:43:24.088949 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 17:43:24.095610 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 17:43:24.098972 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 17:43:24.102431 Total UI for P1: 0, mck2ui 16
6268 17:43:24.105829 best dqsien dly found for B0: ( 0, 14, 24)
6269 17:43:24.108585 Total UI for P1: 0, mck2ui 16
6270 17:43:24.111905 best dqsien dly found for B1: ( 0, 14, 24)
6271 17:43:24.115318 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6272 17:43:24.118739 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6273 17:43:24.118869
6274 17:43:24.121894 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 17:43:24.125466 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 17:43:24.128550 [Gating] SW calibration Done
6277 17:43:24.128671 ==
6278 17:43:24.132349 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 17:43:24.135739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 17:43:24.138937 ==
6281 17:43:24.139054 RX Vref Scan: 0
6282 17:43:24.139158
6283 17:43:24.142123 RX Vref 0 -> 0, step: 1
6284 17:43:24.142238
6285 17:43:24.145528 RX Delay -410 -> 252, step: 16
6286 17:43:24.149009 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6287 17:43:24.152314 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6288 17:43:24.155036 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6289 17:43:24.161774 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6290 17:43:24.165095 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6291 17:43:24.168690 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6292 17:43:24.171995 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6293 17:43:24.178534 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6294 17:43:24.181794 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6295 17:43:24.185119 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6296 17:43:24.188483 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6297 17:43:24.195319 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6298 17:43:24.198650 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6299 17:43:24.201965 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6300 17:43:24.208729 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6301 17:43:24.211567 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6302 17:43:24.211694 ==
6303 17:43:24.215057 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 17:43:24.218411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 17:43:24.218533 ==
6306 17:43:24.221829 DQS Delay:
6307 17:43:24.221942 DQS0 = 27, DQS1 = 35
6308 17:43:24.222046 DQM Delay:
6309 17:43:24.225271 DQM0 = 10, DQM1 = 12
6310 17:43:24.225382 DQ Delay:
6311 17:43:24.228674 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6312 17:43:24.231897 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6313 17:43:24.234957 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6314 17:43:24.238467 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6315 17:43:24.238581
6316 17:43:24.238678
6317 17:43:24.238770 ==
6318 17:43:24.241536 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 17:43:24.244748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 17:43:24.244835 ==
6321 17:43:24.248096
6322 17:43:24.248181
6323 17:43:24.248249 TX Vref Scan disable
6324 17:43:24.251554 == TX Byte 0 ==
6325 17:43:24.255033 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 17:43:24.258093 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 17:43:24.261596 == TX Byte 1 ==
6328 17:43:24.264417 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 17:43:24.267981 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 17:43:24.268088 ==
6331 17:43:24.271256 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 17:43:24.274426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 17:43:24.277669 ==
6334 17:43:24.277759
6335 17:43:24.277825
6336 17:43:24.277886 TX Vref Scan disable
6337 17:43:24.281202 == TX Byte 0 ==
6338 17:43:24.284656 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 17:43:24.287905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 17:43:24.291335 == TX Byte 1 ==
6341 17:43:24.294664 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 17:43:24.297884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 17:43:24.297970
6344 17:43:24.301122 [DATLAT]
6345 17:43:24.301206 Freq=400, CH0 RK0
6346 17:43:24.301276
6347 17:43:24.304600 DATLAT Default: 0xf
6348 17:43:24.304692 0, 0xFFFF, sum = 0
6349 17:43:24.307962 1, 0xFFFF, sum = 0
6350 17:43:24.308042 2, 0xFFFF, sum = 0
6351 17:43:24.311331 3, 0xFFFF, sum = 0
6352 17:43:24.311414 4, 0xFFFF, sum = 0
6353 17:43:24.314165 5, 0xFFFF, sum = 0
6354 17:43:24.314236 6, 0xFFFF, sum = 0
6355 17:43:24.317496 7, 0xFFFF, sum = 0
6356 17:43:24.317590 8, 0xFFFF, sum = 0
6357 17:43:24.321218 9, 0xFFFF, sum = 0
6358 17:43:24.321336 10, 0xFFFF, sum = 0
6359 17:43:24.324525 11, 0xFFFF, sum = 0
6360 17:43:24.324612 12, 0xFFFF, sum = 0
6361 17:43:24.327386 13, 0x0, sum = 1
6362 17:43:24.327500 14, 0x0, sum = 2
6363 17:43:24.330960 15, 0x0, sum = 3
6364 17:43:24.331067 16, 0x0, sum = 4
6365 17:43:24.334325 best_step = 14
6366 17:43:24.334435
6367 17:43:24.334517 ==
6368 17:43:24.337719 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 17:43:24.341063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 17:43:24.341162 ==
6371 17:43:24.344084 RX Vref Scan: 1
6372 17:43:24.344191
6373 17:43:24.344286 RX Vref 0 -> 0, step: 1
6374 17:43:24.344377
6375 17:43:24.347228 RX Delay -311 -> 252, step: 8
6376 17:43:24.347335
6377 17:43:24.350895 Set Vref, RX VrefLevel [Byte0]: 54
6378 17:43:24.354256 [Byte1]: 47
6379 17:43:24.358429
6380 17:43:24.358557 Final RX Vref Byte 0 = 54 to rank0
6381 17:43:24.361865 Final RX Vref Byte 1 = 47 to rank0
6382 17:43:24.365151 Final RX Vref Byte 0 = 54 to rank1
6383 17:43:24.368604 Final RX Vref Byte 1 = 47 to rank1==
6384 17:43:24.371992 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 17:43:24.378647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 17:43:24.378782 ==
6387 17:43:24.378877 DQS Delay:
6388 17:43:24.381889 DQS0 = 28, DQS1 = 36
6389 17:43:24.381979 DQM Delay:
6390 17:43:24.382048 DQM0 = 11, DQM1 = 12
6391 17:43:24.385263 DQ Delay:
6392 17:43:24.388608 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6393 17:43:24.391928 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6394 17:43:24.392053 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6395 17:43:24.395247 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6396 17:43:24.398435
6397 17:43:24.398538
6398 17:43:24.405451 [DQSOSCAuto] RK0, (LSB)MR18= 0xc3b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6399 17:43:24.408572 CH0 RK0: MR19=C0C, MR18=C3B1
6400 17:43:24.415174 CH0_RK0: MR19=0xC0C, MR18=0xC3B1, DQSOSC=385, MR23=63, INC=398, DEC=265
6401 17:43:24.415326 ==
6402 17:43:24.418591 Dram Type= 6, Freq= 0, CH_0, rank 1
6403 17:43:24.421984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 17:43:24.422077 ==
6405 17:43:24.425567 [Gating] SW mode calibration
6406 17:43:24.431662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6407 17:43:24.438518 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6408 17:43:24.441982 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 17:43:24.444684 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 17:43:24.451870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 17:43:24.455310 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 17:43:24.458501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 17:43:24.464698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 17:43:24.468478 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 17:43:24.471520 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 17:43:24.475206 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 17:43:24.478136 Total UI for P1: 0, mck2ui 16
6418 17:43:24.481652 best dqsien dly found for B0: ( 0, 14, 24)
6419 17:43:24.484797 Total UI for P1: 0, mck2ui 16
6420 17:43:24.488108 best dqsien dly found for B1: ( 0, 14, 24)
6421 17:43:24.491468 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6422 17:43:24.498334 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6423 17:43:24.498451
6424 17:43:24.501702 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 17:43:24.505035 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 17:43:24.508162 [Gating] SW calibration Done
6427 17:43:24.508268 ==
6428 17:43:24.511440 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 17:43:24.515094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 17:43:24.515210 ==
6431 17:43:24.515313 RX Vref Scan: 0
6432 17:43:24.518015
6433 17:43:24.518135 RX Vref 0 -> 0, step: 1
6434 17:43:24.518233
6435 17:43:24.521573 RX Delay -410 -> 252, step: 16
6436 17:43:24.524838 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6437 17:43:24.531370 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6438 17:43:24.534678 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6439 17:43:24.538200 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6440 17:43:24.541688 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6441 17:43:24.547774 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6442 17:43:24.551663 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6443 17:43:24.554922 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6444 17:43:24.558263 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6445 17:43:24.564806 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6446 17:43:24.568358 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6447 17:43:24.571474 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6448 17:43:24.574903 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6449 17:43:24.581387 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6450 17:43:24.584363 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6451 17:43:24.588088 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6452 17:43:24.588213 ==
6453 17:43:24.591214 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 17:43:24.594582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 17:43:24.598129 ==
6456 17:43:24.598247 DQS Delay:
6457 17:43:24.598343 DQS0 = 27, DQS1 = 35
6458 17:43:24.600970 DQM Delay:
6459 17:43:24.601074 DQM0 = 12, DQM1 = 11
6460 17:43:24.604350 DQ Delay:
6461 17:43:24.604448 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6462 17:43:24.607834 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6463 17:43:24.611357 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6464 17:43:24.614581 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6465 17:43:24.614669
6466 17:43:24.614734
6467 17:43:24.618090 ==
6468 17:43:24.618187 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 17:43:24.624090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 17:43:24.624175 ==
6471 17:43:24.624251
6472 17:43:24.624319
6473 17:43:24.627516 TX Vref Scan disable
6474 17:43:24.627630 == TX Byte 0 ==
6475 17:43:24.630960 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6476 17:43:24.637190 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6477 17:43:24.637320 == TX Byte 1 ==
6478 17:43:24.640700 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6479 17:43:24.647947 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6480 17:43:24.648070 ==
6481 17:43:24.650708 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 17:43:24.654086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 17:43:24.654204 ==
6484 17:43:24.654301
6485 17:43:24.654391
6486 17:43:24.657504 TX Vref Scan disable
6487 17:43:24.657610 == TX Byte 0 ==
6488 17:43:24.660660 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6489 17:43:24.667295 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6490 17:43:24.667413 == TX Byte 1 ==
6491 17:43:24.670872 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6492 17:43:24.677316 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6493 17:43:24.677417
6494 17:43:24.677486 [DATLAT]
6495 17:43:24.677548 Freq=400, CH0 RK1
6496 17:43:24.677617
6497 17:43:24.680634 DATLAT Default: 0xe
6498 17:43:24.680741 0, 0xFFFF, sum = 0
6499 17:43:24.684222 1, 0xFFFF, sum = 0
6500 17:43:24.684304 2, 0xFFFF, sum = 0
6501 17:43:24.687474 3, 0xFFFF, sum = 0
6502 17:43:24.687590 4, 0xFFFF, sum = 0
6503 17:43:24.690689 5, 0xFFFF, sum = 0
6504 17:43:24.694047 6, 0xFFFF, sum = 0
6505 17:43:24.694164 7, 0xFFFF, sum = 0
6506 17:43:24.697302 8, 0xFFFF, sum = 0
6507 17:43:24.697425 9, 0xFFFF, sum = 0
6508 17:43:24.701072 10, 0xFFFF, sum = 0
6509 17:43:24.701194 11, 0xFFFF, sum = 0
6510 17:43:24.704432 12, 0xFFFF, sum = 0
6511 17:43:24.704525 13, 0x0, sum = 1
6512 17:43:24.707579 14, 0x0, sum = 2
6513 17:43:24.707686 15, 0x0, sum = 3
6514 17:43:24.710892 16, 0x0, sum = 4
6515 17:43:24.710975 best_step = 14
6516 17:43:24.711059
6517 17:43:24.711141 ==
6518 17:43:24.714227 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 17:43:24.717693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 17:43:24.717819 ==
6521 17:43:24.721087 RX Vref Scan: 0
6522 17:43:24.721169
6523 17:43:24.724645 RX Vref 0 -> 0, step: 1
6524 17:43:24.724746
6525 17:43:24.724841 RX Delay -311 -> 252, step: 8
6526 17:43:24.732505 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6527 17:43:24.735829 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6528 17:43:24.739220 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6529 17:43:24.742660 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6530 17:43:24.749053 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6531 17:43:24.752883 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6532 17:43:24.756244 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6533 17:43:24.759353 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6534 17:43:24.766243 iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440
6535 17:43:24.769395 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6536 17:43:24.772612 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6537 17:43:24.776050 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6538 17:43:24.782435 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6539 17:43:24.785860 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6540 17:43:24.789155 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6541 17:43:24.795657 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6542 17:43:24.795789 ==
6543 17:43:24.798950 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 17:43:24.802325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 17:43:24.802406 ==
6546 17:43:24.802473 DQS Delay:
6547 17:43:24.805718 DQS0 = 24, DQS1 = 36
6548 17:43:24.805810 DQM Delay:
6549 17:43:24.808976 DQM0 = 8, DQM1 = 13
6550 17:43:24.809090 DQ Delay:
6551 17:43:24.812835 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6552 17:43:24.816076 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6553 17:43:24.819594 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6554 17:43:24.822225 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6555 17:43:24.822344
6556 17:43:24.822440
6557 17:43:24.829129 [DQSOSCAuto] RK1, (LSB)MR18= 0xb656, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6558 17:43:24.832606 CH0 RK1: MR19=C0C, MR18=B656
6559 17:43:24.839161 CH0_RK1: MR19=0xC0C, MR18=0xB656, DQSOSC=387, MR23=63, INC=394, DEC=262
6560 17:43:24.842453 [RxdqsGatingPostProcess] freq 400
6561 17:43:24.846033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6562 17:43:24.849354 best DQS0 dly(2T, 0.5T) = (0, 10)
6563 17:43:24.852675 best DQS1 dly(2T, 0.5T) = (0, 10)
6564 17:43:24.855383 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6565 17:43:24.858934 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6566 17:43:24.862116 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 17:43:24.866010 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 17:43:24.868712 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 17:43:24.872167 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 17:43:24.875980 Pre-setting of DQS Precalculation
6571 17:43:24.878795 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6572 17:43:24.881902 ==
6573 17:43:24.882019 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 17:43:24.888823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 17:43:24.888914 ==
6576 17:43:24.892136 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6577 17:43:24.898956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6578 17:43:24.902099 [CA 0] Center 36 (8~64) winsize 57
6579 17:43:24.905376 [CA 1] Center 36 (8~64) winsize 57
6580 17:43:24.908581 [CA 2] Center 36 (8~64) winsize 57
6581 17:43:24.912388 [CA 3] Center 36 (8~64) winsize 57
6582 17:43:24.915208 [CA 4] Center 36 (8~64) winsize 57
6583 17:43:24.918675 [CA 5] Center 36 (8~64) winsize 57
6584 17:43:24.918795
6585 17:43:24.921826 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6586 17:43:24.921909
6587 17:43:24.925111 [CATrainingPosCal] consider 1 rank data
6588 17:43:24.928553 u2DelayCellTimex100 = 270/100 ps
6589 17:43:24.932166 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 17:43:24.935482 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 17:43:24.938354 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 17:43:24.942125 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 17:43:24.948680 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 17:43:24.952302 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 17:43:24.952387
6596 17:43:24.954971 CA PerBit enable=1, Macro0, CA PI delay=36
6597 17:43:24.955050
6598 17:43:24.958529 [CBTSetCACLKResult] CA Dly = 36
6599 17:43:24.958608 CS Dly: 1 (0~32)
6600 17:43:24.958680 ==
6601 17:43:24.961722 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 17:43:24.965031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 17:43:24.968307 ==
6604 17:43:24.971552 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 17:43:24.978345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6606 17:43:24.981606 [CA 0] Center 36 (8~64) winsize 57
6607 17:43:24.985258 [CA 1] Center 36 (8~64) winsize 57
6608 17:43:24.988327 [CA 2] Center 36 (8~64) winsize 57
6609 17:43:24.991901 [CA 3] Center 36 (8~64) winsize 57
6610 17:43:24.994864 [CA 4] Center 36 (8~64) winsize 57
6611 17:43:24.998631 [CA 5] Center 36 (8~64) winsize 57
6612 17:43:24.998717
6613 17:43:25.001815 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6614 17:43:25.001900
6615 17:43:25.004818 [CATrainingPosCal] consider 2 rank data
6616 17:43:25.008264 u2DelayCellTimex100 = 270/100 ps
6617 17:43:25.011599 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 17:43:25.015103 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 17:43:25.018253 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 17:43:25.021455 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 17:43:25.024724 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 17:43:25.028453 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 17:43:25.028538
6624 17:43:25.031753 CA PerBit enable=1, Macro0, CA PI delay=36
6625 17:43:25.034652
6626 17:43:25.034738 [CBTSetCACLKResult] CA Dly = 36
6627 17:43:25.037985 CS Dly: 1 (0~32)
6628 17:43:25.038102
6629 17:43:25.041375 ----->DramcWriteLeveling(PI) begin...
6630 17:43:25.041462 ==
6631 17:43:25.044945 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 17:43:25.048218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 17:43:25.048298 ==
6634 17:43:25.051437 Write leveling (Byte 0): 40 => 8
6635 17:43:25.054825 Write leveling (Byte 1): 40 => 8
6636 17:43:25.058349 DramcWriteLeveling(PI) end<-----
6637 17:43:25.058430
6638 17:43:25.058496 ==
6639 17:43:25.061852 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 17:43:25.064747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 17:43:25.064851 ==
6642 17:43:25.068413 [Gating] SW mode calibration
6643 17:43:25.074867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6644 17:43:25.081080 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6645 17:43:25.084591 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 17:43:25.091359 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 17:43:25.094659 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 17:43:25.098091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 17:43:25.104407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 17:43:25.108104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 17:43:25.111046 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 17:43:25.117984 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 17:43:25.121280 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 17:43:25.124458 Total UI for P1: 0, mck2ui 16
6655 17:43:25.127543 best dqsien dly found for B0: ( 0, 14, 24)
6656 17:43:25.131151 Total UI for P1: 0, mck2ui 16
6657 17:43:25.134468 best dqsien dly found for B1: ( 0, 14, 24)
6658 17:43:25.137383 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6659 17:43:25.141079 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6660 17:43:25.141164
6661 17:43:25.144135 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 17:43:25.147879 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 17:43:25.151252 [Gating] SW calibration Done
6664 17:43:25.151338 ==
6665 17:43:25.154086 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 17:43:25.157383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 17:43:25.160713 ==
6668 17:43:25.160797 RX Vref Scan: 0
6669 17:43:25.160864
6670 17:43:25.164134 RX Vref 0 -> 0, step: 1
6671 17:43:25.164248
6672 17:43:25.167403 RX Delay -410 -> 252, step: 16
6673 17:43:25.170966 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6674 17:43:25.174240 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6675 17:43:25.177526 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6676 17:43:25.184232 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6677 17:43:25.187766 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6678 17:43:25.190503 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6679 17:43:25.193913 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6680 17:43:25.200621 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6681 17:43:25.203933 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6682 17:43:25.207432 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6683 17:43:25.210829 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6684 17:43:25.217529 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6685 17:43:25.220932 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6686 17:43:25.224306 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6687 17:43:25.227659 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6688 17:43:25.234128 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6689 17:43:25.234223 ==
6690 17:43:25.237462 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 17:43:25.240551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 17:43:25.240639 ==
6693 17:43:25.240715 DQS Delay:
6694 17:43:25.244134 DQS0 = 35, DQS1 = 35
6695 17:43:25.244219 DQM Delay:
6696 17:43:25.247666 DQM0 = 20, DQM1 = 17
6697 17:43:25.247752 DQ Delay:
6698 17:43:25.250637 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6699 17:43:25.254146 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6700 17:43:25.257469 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6701 17:43:25.260851 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6702 17:43:25.260963
6703 17:43:25.261058
6704 17:43:25.261147 ==
6705 17:43:25.264281 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 17:43:25.267510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 17:43:25.267611 ==
6708 17:43:25.267709
6709 17:43:25.267798
6710 17:43:25.270833 TX Vref Scan disable
6711 17:43:25.270912 == TX Byte 0 ==
6712 17:43:25.277467 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 17:43:25.280981 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 17:43:25.281073 == TX Byte 1 ==
6715 17:43:25.287678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 17:43:25.290958 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 17:43:25.291044 ==
6718 17:43:25.293739 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 17:43:25.297216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 17:43:25.297295 ==
6721 17:43:25.297360
6722 17:43:25.297422
6723 17:43:25.300691 TX Vref Scan disable
6724 17:43:25.300770 == TX Byte 0 ==
6725 17:43:25.307440 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 17:43:25.310958 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 17:43:25.311056 == TX Byte 1 ==
6728 17:43:25.317206 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 17:43:25.320757 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 17:43:25.320880
6731 17:43:25.320979 [DATLAT]
6732 17:43:25.323986 Freq=400, CH1 RK0
6733 17:43:25.324099
6734 17:43:25.324201 DATLAT Default: 0xf
6735 17:43:25.327516 0, 0xFFFF, sum = 0
6736 17:43:25.327647 1, 0xFFFF, sum = 0
6737 17:43:25.330244 2, 0xFFFF, sum = 0
6738 17:43:25.330341 3, 0xFFFF, sum = 0
6739 17:43:25.333730 4, 0xFFFF, sum = 0
6740 17:43:25.333848 5, 0xFFFF, sum = 0
6741 17:43:25.337417 6, 0xFFFF, sum = 0
6742 17:43:25.340129 7, 0xFFFF, sum = 0
6743 17:43:25.340215 8, 0xFFFF, sum = 0
6744 17:43:25.343659 9, 0xFFFF, sum = 0
6745 17:43:25.343752 10, 0xFFFF, sum = 0
6746 17:43:25.347097 11, 0xFFFF, sum = 0
6747 17:43:25.347219 12, 0xFFFF, sum = 0
6748 17:43:25.350414 13, 0x0, sum = 1
6749 17:43:25.350501 14, 0x0, sum = 2
6750 17:43:25.353757 15, 0x0, sum = 3
6751 17:43:25.353868 16, 0x0, sum = 4
6752 17:43:25.356827 best_step = 14
6753 17:43:25.356907
6754 17:43:25.356981 ==
6755 17:43:25.360075 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 17:43:25.363466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 17:43:25.363574 ==
6758 17:43:25.363672 RX Vref Scan: 1
6759 17:43:25.363736
6760 17:43:25.366922 RX Vref 0 -> 0, step: 1
6761 17:43:25.366995
6762 17:43:25.370163 RX Delay -311 -> 252, step: 8
6763 17:43:25.370247
6764 17:43:25.373179 Set Vref, RX VrefLevel [Byte0]: 52
6765 17:43:25.376719 [Byte1]: 51
6766 17:43:25.380596
6767 17:43:25.380710 Final RX Vref Byte 0 = 52 to rank0
6768 17:43:25.383592 Final RX Vref Byte 1 = 51 to rank0
6769 17:43:25.386823 Final RX Vref Byte 0 = 52 to rank1
6770 17:43:25.390468 Final RX Vref Byte 1 = 51 to rank1==
6771 17:43:25.394104 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 17:43:25.400426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 17:43:25.400515 ==
6774 17:43:25.400584 DQS Delay:
6775 17:43:25.403835 DQS0 = 32, DQS1 = 32
6776 17:43:25.403920 DQM Delay:
6777 17:43:25.403988 DQM0 = 13, DQM1 = 10
6778 17:43:25.407279 DQ Delay:
6779 17:43:25.410602 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6780 17:43:25.413853 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6781 17:43:25.413941 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6782 17:43:25.417523 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6783 17:43:25.420621
6784 17:43:25.420710
6785 17:43:25.426793 [DQSOSCAuto] RK0, (LSB)MR18= 0x88c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 392 ps
6786 17:43:25.430755 CH1 RK0: MR19=C0C, MR18=88C0
6787 17:43:25.437038 CH1_RK0: MR19=0xC0C, MR18=0x88C0, DQSOSC=386, MR23=63, INC=396, DEC=264
6788 17:43:25.437132 ==
6789 17:43:25.440576 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 17:43:25.443542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 17:43:25.443631 ==
6792 17:43:25.447386 [Gating] SW mode calibration
6793 17:43:25.453322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6794 17:43:25.460295 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6795 17:43:25.463782 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 17:43:25.467183 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 17:43:25.473748 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 17:43:25.477111 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 17:43:25.480547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 17:43:25.487009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 17:43:25.490306 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 17:43:25.493565 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 17:43:25.496572 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 17:43:25.500546 Total UI for P1: 0, mck2ui 16
6805 17:43:25.503833 best dqsien dly found for B0: ( 0, 14, 24)
6806 17:43:25.507288 Total UI for P1: 0, mck2ui 16
6807 17:43:25.510370 best dqsien dly found for B1: ( 0, 14, 24)
6808 17:43:25.513399 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6809 17:43:25.520202 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6810 17:43:25.520308
6811 17:43:25.523717 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 17:43:25.526638 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 17:43:25.529921 [Gating] SW calibration Done
6814 17:43:25.530013 ==
6815 17:43:25.533113 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 17:43:25.536335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 17:43:25.536425 ==
6818 17:43:25.536494 RX Vref Scan: 0
6819 17:43:25.539788
6820 17:43:25.539873 RX Vref 0 -> 0, step: 1
6821 17:43:25.539940
6822 17:43:25.543236 RX Delay -410 -> 252, step: 16
6823 17:43:25.546701 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6824 17:43:25.553396 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6825 17:43:25.556405 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6826 17:43:25.560014 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6827 17:43:25.563385 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6828 17:43:25.570056 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6829 17:43:25.573542 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6830 17:43:25.576178 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6831 17:43:25.579602 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6832 17:43:25.586396 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6833 17:43:25.589854 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6834 17:43:25.593268 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6835 17:43:25.596214 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6836 17:43:25.603261 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6837 17:43:25.606374 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6838 17:43:25.609768 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6839 17:43:25.609892 ==
6840 17:43:25.613139 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 17:43:25.619669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 17:43:25.619798 ==
6843 17:43:25.619902 DQS Delay:
6844 17:43:25.622833 DQS0 = 35, DQS1 = 35
6845 17:43:25.622948 DQM Delay:
6846 17:43:25.623047 DQM0 = 17, DQM1 = 13
6847 17:43:25.626109 DQ Delay:
6848 17:43:25.629535 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6849 17:43:25.633234 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6850 17:43:25.633354 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6851 17:43:25.636361 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6852 17:43:25.639445
6853 17:43:25.639532
6854 17:43:25.639604 ==
6855 17:43:25.642696 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 17:43:25.646095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 17:43:25.646174 ==
6858 17:43:25.646242
6859 17:43:25.646303
6860 17:43:25.649604 TX Vref Scan disable
6861 17:43:25.649721 == TX Byte 0 ==
6862 17:43:25.652848 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6863 17:43:25.659627 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6864 17:43:25.659762 == TX Byte 1 ==
6865 17:43:25.662989 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6866 17:43:25.669185 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6867 17:43:25.669282 ==
6868 17:43:25.672935 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 17:43:25.676220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 17:43:25.676329 ==
6871 17:43:25.676410
6872 17:43:25.676472
6873 17:43:25.679424 TX Vref Scan disable
6874 17:43:25.679528 == TX Byte 0 ==
6875 17:43:25.682849 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6876 17:43:25.689655 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6877 17:43:25.689744 == TX Byte 1 ==
6878 17:43:25.692421 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6879 17:43:25.699251 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6880 17:43:25.699370
6881 17:43:25.699473 [DATLAT]
6882 17:43:25.702536 Freq=400, CH1 RK1
6883 17:43:25.702650
6884 17:43:25.702755 DATLAT Default: 0xe
6885 17:43:25.705882 0, 0xFFFF, sum = 0
6886 17:43:25.705996 1, 0xFFFF, sum = 0
6887 17:43:25.709342 2, 0xFFFF, sum = 0
6888 17:43:25.709456 3, 0xFFFF, sum = 0
6889 17:43:25.712520 4, 0xFFFF, sum = 0
6890 17:43:25.712636 5, 0xFFFF, sum = 0
6891 17:43:25.715715 6, 0xFFFF, sum = 0
6892 17:43:25.715833 7, 0xFFFF, sum = 0
6893 17:43:25.719013 8, 0xFFFF, sum = 0
6894 17:43:25.719134 9, 0xFFFF, sum = 0
6895 17:43:25.722475 10, 0xFFFF, sum = 0
6896 17:43:25.722593 11, 0xFFFF, sum = 0
6897 17:43:25.726087 12, 0xFFFF, sum = 0
6898 17:43:25.726206 13, 0x0, sum = 1
6899 17:43:25.729177 14, 0x0, sum = 2
6900 17:43:25.729295 15, 0x0, sum = 3
6901 17:43:25.732634 16, 0x0, sum = 4
6902 17:43:25.732749 best_step = 14
6903 17:43:25.732847
6904 17:43:25.732946 ==
6905 17:43:25.735914 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 17:43:25.742180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 17:43:25.742304 ==
6908 17:43:25.742405 RX Vref Scan: 0
6909 17:43:25.742507
6910 17:43:25.745512 RX Vref 0 -> 0, step: 1
6911 17:43:25.745625
6912 17:43:25.748961 RX Delay -311 -> 252, step: 8
6913 17:43:25.755305 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6914 17:43:25.758833 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6915 17:43:25.762300 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6916 17:43:25.765683 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6917 17:43:25.772283 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6918 17:43:25.775364 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6919 17:43:25.779131 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6920 17:43:25.782395 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6921 17:43:25.788509 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6922 17:43:25.791852 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6923 17:43:25.795332 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6924 17:43:25.798690 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6925 17:43:25.805253 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6926 17:43:25.808471 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6927 17:43:25.811942 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6928 17:43:25.815215 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6929 17:43:25.815340 ==
6930 17:43:25.818434 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 17:43:25.825055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 17:43:25.825187 ==
6933 17:43:25.825297 DQS Delay:
6934 17:43:25.828264 DQS0 = 28, DQS1 = 36
6935 17:43:25.828383 DQM Delay:
6936 17:43:25.831793 DQM0 = 10, DQM1 = 15
6937 17:43:25.831910 DQ Delay:
6938 17:43:25.834981 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6939 17:43:25.838187 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6940 17:43:25.841655 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6941 17:43:25.844910 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6942 17:43:25.845026
6943 17:43:25.845131
6944 17:43:25.851889 [DQSOSCAuto] RK1, (LSB)MR18= 0xc152, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6945 17:43:25.855345 CH1 RK1: MR19=C0C, MR18=C152
6946 17:43:25.861463 CH1_RK1: MR19=0xC0C, MR18=0xC152, DQSOSC=385, MR23=63, INC=398, DEC=265
6947 17:43:25.864818 [RxdqsGatingPostProcess] freq 400
6948 17:43:25.868244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6949 17:43:25.871570 best DQS0 dly(2T, 0.5T) = (0, 10)
6950 17:43:25.874818 best DQS1 dly(2T, 0.5T) = (0, 10)
6951 17:43:25.878396 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6952 17:43:25.881912 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6953 17:43:25.884858 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 17:43:25.887952 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 17:43:25.891496 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 17:43:25.895040 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 17:43:25.898382 Pre-setting of DQS Precalculation
6958 17:43:25.901280 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6959 17:43:25.911793 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6960 17:43:25.918269 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6961 17:43:25.918381
6962 17:43:25.918449
6963 17:43:25.921613 [Calibration Summary] 800 Mbps
6964 17:43:25.921724 CH 0, Rank 0
6965 17:43:25.925006 SW Impedance : PASS
6966 17:43:25.925119 DUTY Scan : NO K
6967 17:43:25.928139 ZQ Calibration : PASS
6968 17:43:25.931452 Jitter Meter : NO K
6969 17:43:25.931567 CBT Training : PASS
6970 17:43:25.935338 Write leveling : PASS
6971 17:43:25.938550 RX DQS gating : PASS
6972 17:43:25.938653 RX DQ/DQS(RDDQC) : PASS
6973 17:43:25.941435 TX DQ/DQS : PASS
6974 17:43:25.941520 RX DATLAT : PASS
6975 17:43:25.945105 RX DQ/DQS(Engine): PASS
6976 17:43:25.947927 TX OE : NO K
6977 17:43:25.948012 All Pass.
6978 17:43:25.948102
6979 17:43:25.948183 CH 0, Rank 1
6980 17:43:25.951243 SW Impedance : PASS
6981 17:43:25.954785 DUTY Scan : NO K
6982 17:43:25.954901 ZQ Calibration : PASS
6983 17:43:25.958347 Jitter Meter : NO K
6984 17:43:25.961580 CBT Training : PASS
6985 17:43:25.961670 Write leveling : NO K
6986 17:43:25.964931 RX DQS gating : PASS
6987 17:43:25.968428 RX DQ/DQS(RDDQC) : PASS
6988 17:43:25.968540 TX DQ/DQS : PASS
6989 17:43:25.971850 RX DATLAT : PASS
6990 17:43:25.974547 RX DQ/DQS(Engine): PASS
6991 17:43:25.974658 TX OE : NO K
6992 17:43:25.977889 All Pass.
6993 17:43:25.978002
6994 17:43:25.978101 CH 1, Rank 0
6995 17:43:25.981244 SW Impedance : PASS
6996 17:43:25.981355 DUTY Scan : NO K
6997 17:43:25.985080 ZQ Calibration : PASS
6998 17:43:25.988275 Jitter Meter : NO K
6999 17:43:25.988361 CBT Training : PASS
7000 17:43:25.991439 Write leveling : PASS
7001 17:43:25.991550 RX DQS gating : PASS
7002 17:43:25.994742 RX DQ/DQS(RDDQC) : PASS
7003 17:43:25.997939 TX DQ/DQS : PASS
7004 17:43:25.998024 RX DATLAT : PASS
7005 17:43:26.001221 RX DQ/DQS(Engine): PASS
7006 17:43:26.004401 TX OE : NO K
7007 17:43:26.004486 All Pass.
7008 17:43:26.004553
7009 17:43:26.004615 CH 1, Rank 1
7010 17:43:26.007767 SW Impedance : PASS
7011 17:43:26.011196 DUTY Scan : NO K
7012 17:43:26.011298 ZQ Calibration : PASS
7013 17:43:26.014528 Jitter Meter : NO K
7014 17:43:26.017779 CBT Training : PASS
7015 17:43:26.017852 Write leveling : NO K
7016 17:43:26.021470 RX DQS gating : PASS
7017 17:43:26.024427 RX DQ/DQS(RDDQC) : PASS
7018 17:43:26.024517 TX DQ/DQS : PASS
7019 17:43:26.027596 RX DATLAT : PASS
7020 17:43:26.031092 RX DQ/DQS(Engine): PASS
7021 17:43:26.031177 TX OE : NO K
7022 17:43:26.034615 All Pass.
7023 17:43:26.034707
7024 17:43:26.034781 DramC Write-DBI off
7025 17:43:26.037650 PER_BANK_REFRESH: Hybrid Mode
7026 17:43:26.037737 TX_TRACKING: ON
7027 17:43:26.047726 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7028 17:43:26.051358 [FAST_K] Save calibration result to emmc
7029 17:43:26.054635 dramc_set_vcore_voltage set vcore to 725000
7030 17:43:26.057981 Read voltage for 1600, 0
7031 17:43:26.058100 Vio18 = 0
7032 17:43:26.061301 Vcore = 725000
7033 17:43:26.061415 Vdram = 0
7034 17:43:26.061507 Vddq = 0
7035 17:43:26.064674 Vmddr = 0
7036 17:43:26.067649 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7037 17:43:26.074232 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7038 17:43:26.074351 MEM_TYPE=3, freq_sel=13
7039 17:43:26.077984 sv_algorithm_assistance_LP4_3733
7040 17:43:26.081253 ============ PULL DRAM RESETB DOWN ============
7041 17:43:26.087954 ========== PULL DRAM RESETB DOWN end =========
7042 17:43:26.091416 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7043 17:43:26.094779 ===================================
7044 17:43:26.097438 LPDDR4 DRAM CONFIGURATION
7045 17:43:26.100570 ===================================
7046 17:43:26.100650 EX_ROW_EN[0] = 0x0
7047 17:43:26.103968 EX_ROW_EN[1] = 0x0
7048 17:43:26.107289 LP4Y_EN = 0x0
7049 17:43:26.107370 WORK_FSP = 0x1
7050 17:43:26.110659 WL = 0x5
7051 17:43:26.110763 RL = 0x5
7052 17:43:26.114274 BL = 0x2
7053 17:43:26.114378 RPST = 0x0
7054 17:43:26.117033 RD_PRE = 0x0
7055 17:43:26.117135 WR_PRE = 0x1
7056 17:43:26.120545 WR_PST = 0x1
7057 17:43:26.120678 DBI_WR = 0x0
7058 17:43:26.124051 DBI_RD = 0x0
7059 17:43:26.124156 OTF = 0x1
7060 17:43:26.127245 ===================================
7061 17:43:26.130553 ===================================
7062 17:43:26.133770 ANA top config
7063 17:43:26.137024 ===================================
7064 17:43:26.137140 DLL_ASYNC_EN = 0
7065 17:43:26.140710 ALL_SLAVE_EN = 0
7066 17:43:26.143577 NEW_RANK_MODE = 1
7067 17:43:26.147109 DLL_IDLE_MODE = 1
7068 17:43:26.150477 LP45_APHY_COMB_EN = 1
7069 17:43:26.150593 TX_ODT_DIS = 0
7070 17:43:26.153984 NEW_8X_MODE = 1
7071 17:43:26.157006 ===================================
7072 17:43:26.160061 ===================================
7073 17:43:26.163892 data_rate = 3200
7074 17:43:26.167218 CKR = 1
7075 17:43:26.170197 DQ_P2S_RATIO = 8
7076 17:43:26.173219 ===================================
7077 17:43:26.176669 CA_P2S_RATIO = 8
7078 17:43:26.176784 DQ_CA_OPEN = 0
7079 17:43:26.179814 DQ_SEMI_OPEN = 0
7080 17:43:26.183179 CA_SEMI_OPEN = 0
7081 17:43:26.186586 CA_FULL_RATE = 0
7082 17:43:26.189775 DQ_CKDIV4_EN = 0
7083 17:43:26.193638 CA_CKDIV4_EN = 0
7084 17:43:26.193751 CA_PREDIV_EN = 0
7085 17:43:26.196974 PH8_DLY = 12
7086 17:43:26.199712 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7087 17:43:26.203101 DQ_AAMCK_DIV = 4
7088 17:43:26.206479 CA_AAMCK_DIV = 4
7089 17:43:26.210068 CA_ADMCK_DIV = 4
7090 17:43:26.210181 DQ_TRACK_CA_EN = 0
7091 17:43:26.213399 CA_PICK = 1600
7092 17:43:26.216782 CA_MCKIO = 1600
7093 17:43:26.219555 MCKIO_SEMI = 0
7094 17:43:26.222994 PLL_FREQ = 3068
7095 17:43:26.226427 DQ_UI_PI_RATIO = 32
7096 17:43:26.229896 CA_UI_PI_RATIO = 0
7097 17:43:26.233304 ===================================
7098 17:43:26.236086 ===================================
7099 17:43:26.236163 memory_type:LPDDR4
7100 17:43:26.239377 GP_NUM : 10
7101 17:43:26.243373 SRAM_EN : 1
7102 17:43:26.243486 MD32_EN : 0
7103 17:43:26.246528 ===================================
7104 17:43:26.249776 [ANA_INIT] >>>>>>>>>>>>>>
7105 17:43:26.252985 <<<<<< [CONFIGURE PHASE]: ANA_TX
7106 17:43:26.256362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7107 17:43:26.259774 ===================================
7108 17:43:26.263004 data_rate = 3200,PCW = 0X7600
7109 17:43:26.266166 ===================================
7110 17:43:26.269309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7111 17:43:26.273044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 17:43:26.279154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 17:43:26.282946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7114 17:43:26.286013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7115 17:43:26.289775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7116 17:43:26.292749 [ANA_INIT] flow start
7117 17:43:26.296041 [ANA_INIT] PLL >>>>>>>>
7118 17:43:26.296128 [ANA_INIT] PLL <<<<<<<<
7119 17:43:26.299321 [ANA_INIT] MIDPI >>>>>>>>
7120 17:43:26.302669 [ANA_INIT] MIDPI <<<<<<<<
7121 17:43:26.305713 [ANA_INIT] DLL >>>>>>>>
7122 17:43:26.305828 [ANA_INIT] DLL <<<<<<<<
7123 17:43:26.309416 [ANA_INIT] flow end
7124 17:43:26.312538 ============ LP4 DIFF to SE enter ============
7125 17:43:26.315989 ============ LP4 DIFF to SE exit ============
7126 17:43:26.319355 [ANA_INIT] <<<<<<<<<<<<<
7127 17:43:26.322614 [Flow] Enable top DCM control >>>>>
7128 17:43:26.326015 [Flow] Enable top DCM control <<<<<
7129 17:43:26.329395 Enable DLL master slave shuffle
7130 17:43:26.336372 ==============================================================
7131 17:43:26.336460 Gating Mode config
7132 17:43:26.342470 ==============================================================
7133 17:43:26.342557 Config description:
7134 17:43:26.352465 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7135 17:43:26.358959 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7136 17:43:26.365691 SELPH_MODE 0: By rank 1: By Phase
7137 17:43:26.369167 ==============================================================
7138 17:43:26.372194 GAT_TRACK_EN = 1
7139 17:43:26.375512 RX_GATING_MODE = 2
7140 17:43:26.378762 RX_GATING_TRACK_MODE = 2
7141 17:43:26.382324 SELPH_MODE = 1
7142 17:43:26.385484 PICG_EARLY_EN = 1
7143 17:43:26.389328 VALID_LAT_VALUE = 1
7144 17:43:26.392014 ==============================================================
7145 17:43:26.395485 Enter into Gating configuration >>>>
7146 17:43:26.399001 Exit from Gating configuration <<<<
7147 17:43:26.402475 Enter into DVFS_PRE_config >>>>>
7148 17:43:26.415781 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7149 17:43:26.419168 Exit from DVFS_PRE_config <<<<<
7150 17:43:26.421928 Enter into PICG configuration >>>>
7151 17:43:26.422039 Exit from PICG configuration <<<<
7152 17:43:26.425578 [RX_INPUT] configuration >>>>>
7153 17:43:26.428607 [RX_INPUT] configuration <<<<<
7154 17:43:26.435563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7155 17:43:26.438740 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7156 17:43:26.445946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7157 17:43:26.451958 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7158 17:43:26.458995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 17:43:26.465340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 17:43:26.468638 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7161 17:43:26.472091 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7162 17:43:26.475414 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7163 17:43:26.482432 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7164 17:43:26.485128 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7165 17:43:26.488607 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 17:43:26.491789 ===================================
7167 17:43:26.495363 LPDDR4 DRAM CONFIGURATION
7168 17:43:26.498547 ===================================
7169 17:43:26.501801 EX_ROW_EN[0] = 0x0
7170 17:43:26.501885 EX_ROW_EN[1] = 0x0
7171 17:43:26.505136 LP4Y_EN = 0x0
7172 17:43:26.505218 WORK_FSP = 0x1
7173 17:43:26.508487 WL = 0x5
7174 17:43:26.508569 RL = 0x5
7175 17:43:26.511856 BL = 0x2
7176 17:43:26.511939 RPST = 0x0
7177 17:43:26.515211 RD_PRE = 0x0
7178 17:43:26.515293 WR_PRE = 0x1
7179 17:43:26.518554 WR_PST = 0x1
7180 17:43:26.518637 DBI_WR = 0x0
7181 17:43:26.521689 DBI_RD = 0x0
7182 17:43:26.521777 OTF = 0x1
7183 17:43:26.525629 ===================================
7184 17:43:26.532167 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7185 17:43:26.535046 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7186 17:43:26.538550 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 17:43:26.541675 ===================================
7188 17:43:26.545068 LPDDR4 DRAM CONFIGURATION
7189 17:43:26.548717 ===================================
7190 17:43:26.548804 EX_ROW_EN[0] = 0x10
7191 17:43:26.552150 EX_ROW_EN[1] = 0x0
7192 17:43:26.555411 LP4Y_EN = 0x0
7193 17:43:26.555524 WORK_FSP = 0x1
7194 17:43:26.558760 WL = 0x5
7195 17:43:26.558858 RL = 0x5
7196 17:43:26.561478 BL = 0x2
7197 17:43:26.561592 RPST = 0x0
7198 17:43:26.565385 RD_PRE = 0x0
7199 17:43:26.565469 WR_PRE = 0x1
7200 17:43:26.568493 WR_PST = 0x1
7201 17:43:26.568596 DBI_WR = 0x0
7202 17:43:26.571609 DBI_RD = 0x0
7203 17:43:26.571735 OTF = 0x1
7204 17:43:26.574865 ===================================
7205 17:43:26.581662 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7206 17:43:26.581772 ==
7207 17:43:26.584743 Dram Type= 6, Freq= 0, CH_0, rank 0
7208 17:43:26.587925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7209 17:43:26.591258 ==
7210 17:43:26.591363 [Duty_Offset_Calibration]
7211 17:43:26.594618 B0:2 B1:1 CA:1
7212 17:43:26.594700
7213 17:43:26.597879 [DutyScan_Calibration_Flow] k_type=0
7214 17:43:26.606948
7215 17:43:26.607060 ==CLK 0==
7216 17:43:26.610216 Final CLK duty delay cell = 0
7217 17:43:26.613632 [0] MAX Duty = 5187%(X100), DQS PI = 24
7218 17:43:26.617034 [0] MIN Duty = 4876%(X100), DQS PI = 48
7219 17:43:26.617141 [0] AVG Duty = 5031%(X100)
7220 17:43:26.620386
7221 17:43:26.623722 CH0 CLK Duty spec in!! Max-Min= 311%
7222 17:43:26.627054 [DutyScan_Calibration_Flow] ====Done====
7223 17:43:26.627134
7224 17:43:26.630764 [DutyScan_Calibration_Flow] k_type=1
7225 17:43:26.646024
7226 17:43:26.646139 ==DQS 0 ==
7227 17:43:26.649664 Final DQS duty delay cell = -4
7228 17:43:26.653037 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7229 17:43:26.656477 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7230 17:43:26.659824 [-4] AVG Duty = 4906%(X100)
7231 17:43:26.659904
7232 17:43:26.659969 ==DQS 1 ==
7233 17:43:26.662997 Final DQS duty delay cell = 0
7234 17:43:26.666140 [0] MAX Duty = 5218%(X100), DQS PI = 22
7235 17:43:26.669840 [0] MIN Duty = 5062%(X100), DQS PI = 30
7236 17:43:26.673159 [0] AVG Duty = 5140%(X100)
7237 17:43:26.673237
7238 17:43:26.675982 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7239 17:43:26.676085
7240 17:43:26.679679 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7241 17:43:26.682697 [DutyScan_Calibration_Flow] ====Done====
7242 17:43:26.682800
7243 17:43:26.686265 [DutyScan_Calibration_Flow] k_type=3
7244 17:43:26.703042
7245 17:43:26.703141 ==DQM 0 ==
7246 17:43:26.706449 Final DQM duty delay cell = 0
7247 17:43:26.709596 [0] MAX Duty = 5187%(X100), DQS PI = 26
7248 17:43:26.712740 [0] MIN Duty = 4876%(X100), DQS PI = 60
7249 17:43:26.712825 [0] AVG Duty = 5031%(X100)
7250 17:43:26.716225
7251 17:43:26.716312 ==DQM 1 ==
7252 17:43:26.719877 Final DQM duty delay cell = -4
7253 17:43:26.723181 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7254 17:43:26.726420 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7255 17:43:26.729721 [-4] AVG Duty = 4906%(X100)
7256 17:43:26.729829
7257 17:43:26.733052 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7258 17:43:26.733136
7259 17:43:26.736391 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7260 17:43:26.739586 [DutyScan_Calibration_Flow] ====Done====
7261 17:43:26.739734
7262 17:43:26.742935 [DutyScan_Calibration_Flow] k_type=2
7263 17:43:26.760845
7264 17:43:26.760941 ==DQ 0 ==
7265 17:43:26.764189 Final DQ duty delay cell = 0
7266 17:43:26.767320 [0] MAX Duty = 5062%(X100), DQS PI = 24
7267 17:43:26.770437 [0] MIN Duty = 4907%(X100), DQS PI = 0
7268 17:43:26.770545 [0] AVG Duty = 4984%(X100)
7269 17:43:26.770638
7270 17:43:26.773885 ==DQ 1 ==
7271 17:43:26.776965 Final DQ duty delay cell = 0
7272 17:43:26.780441 [0] MAX Duty = 5156%(X100), DQS PI = 22
7273 17:43:26.783507 [0] MIN Duty = 4907%(X100), DQS PI = 34
7274 17:43:26.783634 [0] AVG Duty = 5031%(X100)
7275 17:43:26.783727
7276 17:43:26.787142 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7277 17:43:26.790432
7278 17:43:26.790518 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7279 17:43:26.797224 [DutyScan_Calibration_Flow] ====Done====
7280 17:43:26.797309 ==
7281 17:43:26.800357 Dram Type= 6, Freq= 0, CH_1, rank 0
7282 17:43:26.803756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 17:43:26.803832 ==
7284 17:43:26.807038 [Duty_Offset_Calibration]
7285 17:43:26.807113 B0:1 B1:0 CA:0
7286 17:43:26.807176
7287 17:43:26.810390 [DutyScan_Calibration_Flow] k_type=0
7288 17:43:26.819585
7289 17:43:26.819712 ==CLK 0==
7290 17:43:26.823231 Final CLK duty delay cell = -4
7291 17:43:26.826273 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7292 17:43:26.830024 [-4] MIN Duty = 4844%(X100), DQS PI = 20
7293 17:43:26.833336 [-4] AVG Duty = 4922%(X100)
7294 17:43:26.833421
7295 17:43:26.836668 CH1 CLK Duty spec in!! Max-Min= 156%
7296 17:43:26.839919 [DutyScan_Calibration_Flow] ====Done====
7297 17:43:26.840000
7298 17:43:26.843317 [DutyScan_Calibration_Flow] k_type=1
7299 17:43:26.859850
7300 17:43:26.859944 ==DQS 0 ==
7301 17:43:26.863630 Final DQS duty delay cell = 0
7302 17:43:26.866905 [0] MAX Duty = 5062%(X100), DQS PI = 24
7303 17:43:26.870292 [0] MIN Duty = 4844%(X100), DQS PI = 16
7304 17:43:26.870374 [0] AVG Duty = 4953%(X100)
7305 17:43:26.873692
7306 17:43:26.873773 ==DQS 1 ==
7307 17:43:26.877013 Final DQS duty delay cell = 0
7308 17:43:26.880034 [0] MAX Duty = 5249%(X100), DQS PI = 48
7309 17:43:26.883050 [0] MIN Duty = 4907%(X100), DQS PI = 40
7310 17:43:26.886483 [0] AVG Duty = 5078%(X100)
7311 17:43:26.886564
7312 17:43:26.889891 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7313 17:43:26.889973
7314 17:43:26.893280 CH1 DQS 1 Duty spec in!! Max-Min= 342%
7315 17:43:26.897293 [DutyScan_Calibration_Flow] ====Done====
7316 17:43:26.897374
7317 17:43:26.899943 [DutyScan_Calibration_Flow] k_type=3
7318 17:43:26.917215
7319 17:43:26.917319 ==DQM 0 ==
7320 17:43:26.920315 Final DQM duty delay cell = 0
7321 17:43:26.923580 [0] MAX Duty = 5187%(X100), DQS PI = 40
7322 17:43:26.926814 [0] MIN Duty = 5031%(X100), DQS PI = 16
7323 17:43:26.930167 [0] AVG Duty = 5109%(X100)
7324 17:43:26.930281
7325 17:43:26.930349 ==DQM 1 ==
7326 17:43:26.933641 Final DQM duty delay cell = 0
7327 17:43:26.936559 [0] MAX Duty = 5093%(X100), DQS PI = 10
7328 17:43:26.939967 [0] MIN Duty = 4907%(X100), DQS PI = 2
7329 17:43:26.943749 [0] AVG Duty = 5000%(X100)
7330 17:43:26.943833
7331 17:43:26.946929 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7332 17:43:26.947010
7333 17:43:26.950230 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7334 17:43:26.953598 [DutyScan_Calibration_Flow] ====Done====
7335 17:43:26.953680
7336 17:43:26.956862 [DutyScan_Calibration_Flow] k_type=2
7337 17:43:26.973278
7338 17:43:26.973407 ==DQ 0 ==
7339 17:43:26.976629 Final DQ duty delay cell = -4
7340 17:43:26.979915 [-4] MAX Duty = 5062%(X100), DQS PI = 26
7341 17:43:26.983178 [-4] MIN Duty = 4875%(X100), DQS PI = 14
7342 17:43:26.986423 [-4] AVG Duty = 4968%(X100)
7343 17:43:26.986529
7344 17:43:26.986629 ==DQ 1 ==
7345 17:43:26.989739 Final DQ duty delay cell = 0
7346 17:43:26.993098 [0] MAX Duty = 5093%(X100), DQS PI = 8
7347 17:43:26.996415 [0] MIN Duty = 4938%(X100), DQS PI = 0
7348 17:43:26.996496 [0] AVG Duty = 5015%(X100)
7349 17:43:26.996579
7350 17:43:27.003118 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7351 17:43:27.003234
7352 17:43:27.006640 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7353 17:43:27.009245 [DutyScan_Calibration_Flow] ====Done====
7354 17:43:27.013071 nWR fixed to 30
7355 17:43:27.013162 [ModeRegInit_LP4] CH0 RK0
7356 17:43:27.016179 [ModeRegInit_LP4] CH0 RK1
7357 17:43:27.019493 [ModeRegInit_LP4] CH1 RK0
7358 17:43:27.022899 [ModeRegInit_LP4] CH1 RK1
7359 17:43:27.022993 match AC timing 5
7360 17:43:27.026179 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7361 17:43:27.033155 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7362 17:43:27.036188 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7363 17:43:27.043113 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7364 17:43:27.045949 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7365 17:43:27.046038 [MiockJmeterHQA]
7366 17:43:27.046124
7367 17:43:27.049385 [DramcMiockJmeter] u1RxGatingPI = 0
7368 17:43:27.052881 0 : 4363, 4137
7369 17:43:27.052970 4 : 4368, 4140
7370 17:43:27.053105 8 : 4252, 4027
7371 17:43:27.056163 12 : 4252, 4027
7372 17:43:27.056249 16 : 4249, 4027
7373 17:43:27.059340 20 : 4363, 4137
7374 17:43:27.059427 24 : 4253, 4027
7375 17:43:27.062562 28 : 4250, 4027
7376 17:43:27.062648 32 : 4253, 4026
7377 17:43:27.066457 36 : 4250, 4027
7378 17:43:27.066544 40 : 4250, 4027
7379 17:43:27.066632 44 : 4361, 4137
7380 17:43:27.069117 48 : 4361, 4137
7381 17:43:27.069202 52 : 4250, 4026
7382 17:43:27.073046 56 : 4250, 4027
7383 17:43:27.073133 60 : 4250, 4027
7384 17:43:27.076281 64 : 4250, 4027
7385 17:43:27.076367 68 : 4250, 4026
7386 17:43:27.079581 72 : 4360, 4138
7387 17:43:27.079705 76 : 4250, 4027
7388 17:43:27.079789 80 : 4250, 4027
7389 17:43:27.082853 84 : 4250, 4026
7390 17:43:27.082955 88 : 4250, 227
7391 17:43:27.085754 92 : 4250, 0
7392 17:43:27.085869 96 : 4250, 0
7393 17:43:27.085960 100 : 4360, 0
7394 17:43:27.089637 104 : 4250, 0
7395 17:43:27.089723 108 : 4250, 0
7396 17:43:27.092914 112 : 4250, 0
7397 17:43:27.093001 116 : 4250, 0
7398 17:43:27.093071 120 : 4250, 0
7399 17:43:27.096281 124 : 4250, 0
7400 17:43:27.096365 128 : 4250, 0
7401 17:43:27.099451 132 : 4361, 0
7402 17:43:27.099578 136 : 4360, 0
7403 17:43:27.099717 140 : 4361, 0
7404 17:43:27.102787 144 : 4250, 0
7405 17:43:27.102870 148 : 4250, 0
7406 17:43:27.105864 152 : 4250, 0
7407 17:43:27.105948 156 : 4250, 0
7408 17:43:27.106016 160 : 4250, 0
7409 17:43:27.108911 164 : 4250, 0
7410 17:43:27.108995 168 : 4250, 0
7411 17:43:27.109062 172 : 4250, 0
7412 17:43:27.112598 176 : 4250, 0
7413 17:43:27.112683 180 : 4252, 0
7414 17:43:27.115961 184 : 4361, 0
7415 17:43:27.116061 188 : 4360, 0
7416 17:43:27.116159 192 : 4250, 0
7417 17:43:27.119184 196 : 4250, 0
7418 17:43:27.119268 200 : 4361, 0
7419 17:43:27.122493 204 : 4361, 1420
7420 17:43:27.122582 208 : 4360, 4117
7421 17:43:27.125708 212 : 4250, 4027
7422 17:43:27.125793 216 : 4250, 4026
7423 17:43:27.129178 220 : 4361, 4137
7424 17:43:27.129263 224 : 4250, 4027
7425 17:43:27.129331 228 : 4250, 4026
7426 17:43:27.132139 232 : 4250, 4027
7427 17:43:27.132227 236 : 4250, 4027
7428 17:43:27.135430 240 : 4250, 4027
7429 17:43:27.135530 244 : 4250, 4026
7430 17:43:27.139085 248 : 4361, 4137
7431 17:43:27.139171 252 : 4250, 4026
7432 17:43:27.142164 256 : 4250, 4027
7433 17:43:27.142252 260 : 4360, 4138
7434 17:43:27.145606 264 : 4250, 4027
7435 17:43:27.145691 268 : 4250, 4027
7436 17:43:27.149279 272 : 4361, 4137
7437 17:43:27.149365 276 : 4250, 4027
7438 17:43:27.152497 280 : 4250, 4026
7439 17:43:27.152582 284 : 4250, 4027
7440 17:43:27.152650 288 : 4250, 4026
7441 17:43:27.155856 292 : 4250, 4027
7442 17:43:27.155940 296 : 4250, 4026
7443 17:43:27.158760 300 : 4361, 4137
7444 17:43:27.158875 304 : 4250, 4026
7445 17:43:27.161971 308 : 4250, 3975
7446 17:43:27.162056 312 : 4360, 2097
7447 17:43:27.162123
7448 17:43:27.165781 MIOCK jitter meter ch=0
7449 17:43:27.165864
7450 17:43:27.168964 1T = (312-88) = 224 dly cells
7451 17:43:27.175716 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7452 17:43:27.175808 ==
7453 17:43:27.178968 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 17:43:27.182222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7455 17:43:27.182308 ==
7456 17:43:27.189105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7457 17:43:27.192426 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7458 17:43:27.195596 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7459 17:43:27.202334 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7460 17:43:27.210989 [CA 0] Center 43 (13~74) winsize 62
7461 17:43:27.213634 [CA 1] Center 43 (13~74) winsize 62
7462 17:43:27.217390 [CA 2] Center 38 (9~68) winsize 60
7463 17:43:27.221023 [CA 3] Center 38 (8~68) winsize 61
7464 17:43:27.223777 [CA 4] Center 37 (7~67) winsize 61
7465 17:43:27.227045 [CA 5] Center 36 (7~65) winsize 59
7466 17:43:27.227158
7467 17:43:27.230405 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7468 17:43:27.230509
7469 17:43:27.233757 [CATrainingPosCal] consider 1 rank data
7470 17:43:27.237577 u2DelayCellTimex100 = 290/100 ps
7471 17:43:27.240551 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7472 17:43:27.247482 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7473 17:43:27.250603 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7474 17:43:27.253583 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7475 17:43:27.256897 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7476 17:43:27.260216 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7477 17:43:27.260300
7478 17:43:27.263881 CA PerBit enable=1, Macro0, CA PI delay=36
7479 17:43:27.263963
7480 17:43:27.266906 [CBTSetCACLKResult] CA Dly = 36
7481 17:43:27.270155 CS Dly: 9 (0~40)
7482 17:43:27.273555 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7483 17:43:27.276882 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7484 17:43:27.276958 ==
7485 17:43:27.280238 Dram Type= 6, Freq= 0, CH_0, rank 1
7486 17:43:27.283569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7487 17:43:27.283690 ==
7488 17:43:27.289914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7489 17:43:27.293623 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7490 17:43:27.300135 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7491 17:43:27.303675 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7492 17:43:27.313719 [CA 0] Center 42 (12~72) winsize 61
7493 17:43:27.317003 [CA 1] Center 42 (12~73) winsize 62
7494 17:43:27.320387 [CA 2] Center 37 (8~67) winsize 60
7495 17:43:27.323970 [CA 3] Center 38 (8~68) winsize 61
7496 17:43:27.327049 [CA 4] Center 35 (6~65) winsize 60
7497 17:43:27.330712 [CA 5] Center 35 (5~65) winsize 61
7498 17:43:27.330845
7499 17:43:27.333632 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7500 17:43:27.333708
7501 17:43:27.336902 [CATrainingPosCal] consider 2 rank data
7502 17:43:27.340253 u2DelayCellTimex100 = 290/100 ps
7503 17:43:27.343629 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
7504 17:43:27.350670 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7505 17:43:27.353599 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7506 17:43:27.357284 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7507 17:43:27.360266 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7508 17:43:27.363850 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7509 17:43:27.363958
7510 17:43:27.366832 CA PerBit enable=1, Macro0, CA PI delay=36
7511 17:43:27.366920
7512 17:43:27.370640 [CBTSetCACLKResult] CA Dly = 36
7513 17:43:27.373682 CS Dly: 10 (0~42)
7514 17:43:27.376749 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7515 17:43:27.380210 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7516 17:43:27.380315
7517 17:43:27.383522 ----->DramcWriteLeveling(PI) begin...
7518 17:43:27.383646 ==
7519 17:43:27.387053 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 17:43:27.390263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 17:43:27.393709 ==
7522 17:43:27.396937 Write leveling (Byte 0): 37 => 37
7523 17:43:27.397012 Write leveling (Byte 1): 28 => 28
7524 17:43:27.400269 DramcWriteLeveling(PI) end<-----
7525 17:43:27.400341
7526 17:43:27.400401 ==
7527 17:43:27.403513 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 17:43:27.409953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 17:43:27.410039 ==
7530 17:43:27.413464 [Gating] SW mode calibration
7531 17:43:27.420224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7532 17:43:27.423794 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7533 17:43:27.430238 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 17:43:27.433406 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 17:43:27.437233 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7536 17:43:27.440516 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7537 17:43:27.446614 1 4 16 | B1->B0 | 2323 3635 | 0 1 | (0 0) (1 1)
7538 17:43:27.450046 1 4 20 | B1->B0 | 3434 3636 | 0 1 | (0 0) (1 1)
7539 17:43:27.453366 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7540 17:43:27.460015 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7541 17:43:27.463680 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 17:43:27.466846 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7543 17:43:27.473419 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7544 17:43:27.476876 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
7545 17:43:27.480244 1 5 16 | B1->B0 | 3434 2727 | 0 0 | (0 0) (1 0)
7546 17:43:27.486819 1 5 20 | B1->B0 | 2727 2726 | 0 1 | (1 0) (0 0)
7547 17:43:27.490283 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
7548 17:43:27.493643 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7549 17:43:27.500247 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7550 17:43:27.503142 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 17:43:27.506436 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7552 17:43:27.513585 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7553 17:43:27.516837 1 6 16 | B1->B0 | 2727 4645 | 0 1 | (0 0) (0 0)
7554 17:43:27.520111 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7555 17:43:27.526667 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 17:43:27.529640 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 17:43:27.533094 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 17:43:27.539563 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 17:43:27.542901 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 17:43:27.546485 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7561 17:43:27.553426 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7562 17:43:27.556676 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7563 17:43:27.560036 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 17:43:27.566139 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 17:43:27.569905 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 17:43:27.572705 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 17:43:27.576090 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 17:43:27.583304 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 17:43:27.586334 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 17:43:27.590008 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 17:43:27.596588 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 17:43:27.599569 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 17:43:27.603304 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 17:43:27.609811 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 17:43:27.613103 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 17:43:27.616388 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7577 17:43:27.623069 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7578 17:43:27.626421 Total UI for P1: 0, mck2ui 16
7579 17:43:27.629701 best dqsien dly found for B0: ( 1, 9, 10)
7580 17:43:27.633089 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7581 17:43:27.636435 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 17:43:27.639557 Total UI for P1: 0, mck2ui 16
7583 17:43:27.643015 best dqsien dly found for B1: ( 1, 9, 20)
7584 17:43:27.646322 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7585 17:43:27.649202 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7586 17:43:27.652267
7587 17:43:27.655777 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7588 17:43:27.659106 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7589 17:43:27.662508 [Gating] SW calibration Done
7590 17:43:27.662680 ==
7591 17:43:27.665527 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 17:43:27.668755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 17:43:27.668838 ==
7594 17:43:27.668904 RX Vref Scan: 0
7595 17:43:27.672114
7596 17:43:27.672195 RX Vref 0 -> 0, step: 1
7597 17:43:27.672259
7598 17:43:27.675882 RX Delay 0 -> 252, step: 8
7599 17:43:27.679300 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7600 17:43:27.682673 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7601 17:43:27.689175 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7602 17:43:27.692593 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7603 17:43:27.695750 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7604 17:43:27.699099 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7605 17:43:27.701928 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7606 17:43:27.708556 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7607 17:43:27.711995 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7608 17:43:27.715539 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7609 17:43:27.718875 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7610 17:43:27.722151 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7611 17:43:27.728919 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7612 17:43:27.732159 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7613 17:43:27.735538 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7614 17:43:27.738754 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7615 17:43:27.738852 ==
7616 17:43:27.742048 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 17:43:27.748655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 17:43:27.748744 ==
7619 17:43:27.748810 DQS Delay:
7620 17:43:27.748870 DQS0 = 0, DQS1 = 0
7621 17:43:27.752037 DQM Delay:
7622 17:43:27.752119 DQM0 = 137, DQM1 = 130
7623 17:43:27.755232 DQ Delay:
7624 17:43:27.758633 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7625 17:43:27.761824 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7626 17:43:27.764913 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7627 17:43:27.768612 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7628 17:43:27.768694
7629 17:43:27.768758
7630 17:43:27.768817 ==
7631 17:43:27.771542 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 17:43:27.775081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 17:43:27.778567 ==
7634 17:43:27.778650
7635 17:43:27.778714
7636 17:43:27.778774 TX Vref Scan disable
7637 17:43:27.781990 == TX Byte 0 ==
7638 17:43:27.784975 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7639 17:43:27.788534 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7640 17:43:27.792012 == TX Byte 1 ==
7641 17:43:27.794921 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7642 17:43:27.798256 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7643 17:43:27.801724 ==
7644 17:43:27.805013 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 17:43:27.808354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 17:43:27.808459 ==
7647 17:43:27.819979
7648 17:43:27.823465 TX Vref early break, caculate TX vref
7649 17:43:27.826500 TX Vref=16, minBit 0, minWin=23, winSum=376
7650 17:43:27.829864 TX Vref=18, minBit 0, minWin=23, winSum=387
7651 17:43:27.833169 TX Vref=20, minBit 0, minWin=23, winSum=393
7652 17:43:27.836656 TX Vref=22, minBit 7, minWin=23, winSum=400
7653 17:43:27.840082 TX Vref=24, minBit 3, minWin=24, winSum=412
7654 17:43:27.846786 TX Vref=26, minBit 2, minWin=25, winSum=425
7655 17:43:27.849871 TX Vref=28, minBit 4, minWin=24, winSum=420
7656 17:43:27.853198 TX Vref=30, minBit 2, minWin=24, winSum=412
7657 17:43:27.856504 TX Vref=32, minBit 0, minWin=24, winSum=401
7658 17:43:27.863168 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 26
7659 17:43:27.863249
7660 17:43:27.866557 Final TX Range 0 Vref 26
7661 17:43:27.866650
7662 17:43:27.866727 ==
7663 17:43:27.869849 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 17:43:27.873202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 17:43:27.873278 ==
7666 17:43:27.873339
7667 17:43:27.873397
7668 17:43:27.876959 TX Vref Scan disable
7669 17:43:27.880084 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7670 17:43:27.883309 == TX Byte 0 ==
7671 17:43:27.886247 u2DelayCellOfst[0]=13 cells (4 PI)
7672 17:43:27.889737 u2DelayCellOfst[1]=16 cells (5 PI)
7673 17:43:27.893458 u2DelayCellOfst[2]=13 cells (4 PI)
7674 17:43:27.896523 u2DelayCellOfst[3]=10 cells (3 PI)
7675 17:43:27.899578 u2DelayCellOfst[4]=10 cells (3 PI)
7676 17:43:27.899704 u2DelayCellOfst[5]=0 cells (0 PI)
7677 17:43:27.903105 u2DelayCellOfst[6]=16 cells (5 PI)
7678 17:43:27.906484 u2DelayCellOfst[7]=16 cells (5 PI)
7679 17:43:27.912790 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7680 17:43:27.916012 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7681 17:43:27.916114 == TX Byte 1 ==
7682 17:43:27.919351 u2DelayCellOfst[8]=3 cells (1 PI)
7683 17:43:27.922761 u2DelayCellOfst[9]=0 cells (0 PI)
7684 17:43:27.925951 u2DelayCellOfst[10]=6 cells (2 PI)
7685 17:43:27.929234 u2DelayCellOfst[11]=6 cells (2 PI)
7686 17:43:27.932654 u2DelayCellOfst[12]=10 cells (3 PI)
7687 17:43:27.936016 u2DelayCellOfst[13]=13 cells (4 PI)
7688 17:43:27.939564 u2DelayCellOfst[14]=16 cells (5 PI)
7689 17:43:27.942676 u2DelayCellOfst[15]=10 cells (3 PI)
7690 17:43:27.946346 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7691 17:43:27.949603 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7692 17:43:27.952742 DramC Write-DBI on
7693 17:43:27.952826 ==
7694 17:43:27.955810 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 17:43:27.959795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 17:43:27.959884 ==
7697 17:43:27.959950
7698 17:43:27.960009
7699 17:43:27.963110 TX Vref Scan disable
7700 17:43:27.965789 == TX Byte 0 ==
7701 17:43:27.969197 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7702 17:43:27.973146 == TX Byte 1 ==
7703 17:43:27.976530 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7704 17:43:27.976613 DramC Write-DBI off
7705 17:43:27.976684
7706 17:43:27.979698 [DATLAT]
7707 17:43:27.979780 Freq=1600, CH0 RK0
7708 17:43:27.979847
7709 17:43:27.982866 DATLAT Default: 0xf
7710 17:43:27.982967 0, 0xFFFF, sum = 0
7711 17:43:27.986055 1, 0xFFFF, sum = 0
7712 17:43:27.986139 2, 0xFFFF, sum = 0
7713 17:43:27.989236 3, 0xFFFF, sum = 0
7714 17:43:27.989358 4, 0xFFFF, sum = 0
7715 17:43:27.992582 5, 0xFFFF, sum = 0
7716 17:43:27.992667 6, 0xFFFF, sum = 0
7717 17:43:27.996389 7, 0xFFFF, sum = 0
7718 17:43:27.996500 8, 0xFFFF, sum = 0
7719 17:43:27.999175 9, 0xFFFF, sum = 0
7720 17:43:28.002461 10, 0xFFFF, sum = 0
7721 17:43:28.002546 11, 0xFFFF, sum = 0
7722 17:43:28.005635 12, 0xFFFF, sum = 0
7723 17:43:28.005745 13, 0xFFFF, sum = 0
7724 17:43:28.009059 14, 0x0, sum = 1
7725 17:43:28.009142 15, 0x0, sum = 2
7726 17:43:28.012342 16, 0x0, sum = 3
7727 17:43:28.012426 17, 0x0, sum = 4
7728 17:43:28.015950 best_step = 15
7729 17:43:28.016032
7730 17:43:28.016113 ==
7731 17:43:28.019037 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 17:43:28.022229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 17:43:28.022311 ==
7734 17:43:28.022428 RX Vref Scan: 1
7735 17:43:28.022576
7736 17:43:28.025602 Set Vref Range= 24 -> 127
7737 17:43:28.025681
7738 17:43:28.029241 RX Vref 24 -> 127, step: 1
7739 17:43:28.029342
7740 17:43:28.032454 RX Delay 19 -> 252, step: 4
7741 17:43:28.032536
7742 17:43:28.035839 Set Vref, RX VrefLevel [Byte0]: 24
7743 17:43:28.039069 [Byte1]: 24
7744 17:43:28.039147
7745 17:43:28.042464 Set Vref, RX VrefLevel [Byte0]: 25
7746 17:43:28.045822 [Byte1]: 25
7747 17:43:28.045923
7748 17:43:28.049239 Set Vref, RX VrefLevel [Byte0]: 26
7749 17:43:28.052628 [Byte1]: 26
7750 17:43:28.056496
7751 17:43:28.056574 Set Vref, RX VrefLevel [Byte0]: 27
7752 17:43:28.059466 [Byte1]: 27
7753 17:43:28.063462
7754 17:43:28.063539 Set Vref, RX VrefLevel [Byte0]: 28
7755 17:43:28.066886 [Byte1]: 28
7756 17:43:28.071277
7757 17:43:28.071384 Set Vref, RX VrefLevel [Byte0]: 29
7758 17:43:28.074260 [Byte1]: 29
7759 17:43:28.078874
7760 17:43:28.078957 Set Vref, RX VrefLevel [Byte0]: 30
7761 17:43:28.081612 [Byte1]: 30
7762 17:43:28.086325
7763 17:43:28.086437 Set Vref, RX VrefLevel [Byte0]: 31
7764 17:43:28.089669 [Byte1]: 31
7765 17:43:28.094231
7766 17:43:28.094316 Set Vref, RX VrefLevel [Byte0]: 32
7767 17:43:28.096905 [Byte1]: 32
7768 17:43:28.101626
7769 17:43:28.101708 Set Vref, RX VrefLevel [Byte0]: 33
7770 17:43:28.104726 [Byte1]: 33
7771 17:43:28.108941
7772 17:43:28.109025 Set Vref, RX VrefLevel [Byte0]: 34
7773 17:43:28.112156 [Byte1]: 34
7774 17:43:28.116806
7775 17:43:28.116892 Set Vref, RX VrefLevel [Byte0]: 35
7776 17:43:28.120064 [Byte1]: 35
7777 17:43:28.124055
7778 17:43:28.124149 Set Vref, RX VrefLevel [Byte0]: 36
7779 17:43:28.127347 [Byte1]: 36
7780 17:43:28.131651
7781 17:43:28.131749 Set Vref, RX VrefLevel [Byte0]: 37
7782 17:43:28.134716 [Byte1]: 37
7783 17:43:28.139348
7784 17:43:28.139437 Set Vref, RX VrefLevel [Byte0]: 38
7785 17:43:28.142725 [Byte1]: 38
7786 17:43:28.146687
7787 17:43:28.146788 Set Vref, RX VrefLevel [Byte0]: 39
7788 17:43:28.149882 [Byte1]: 39
7789 17:43:28.154574
7790 17:43:28.154664 Set Vref, RX VrefLevel [Byte0]: 40
7791 17:43:28.157937 [Byte1]: 40
7792 17:43:28.162004
7793 17:43:28.162079 Set Vref, RX VrefLevel [Byte0]: 41
7794 17:43:28.165277 [Byte1]: 41
7795 17:43:28.169899
7796 17:43:28.169982 Set Vref, RX VrefLevel [Byte0]: 42
7797 17:43:28.173205 [Byte1]: 42
7798 17:43:28.176992
7799 17:43:28.177070 Set Vref, RX VrefLevel [Byte0]: 43
7800 17:43:28.180607 [Byte1]: 43
7801 17:43:28.184682
7802 17:43:28.184757 Set Vref, RX VrefLevel [Byte0]: 44
7803 17:43:28.187869 [Byte1]: 44
7804 17:43:28.192360
7805 17:43:28.192444 Set Vref, RX VrefLevel [Byte0]: 45
7806 17:43:28.195245 [Byte1]: 45
7807 17:43:28.200060
7808 17:43:28.200148 Set Vref, RX VrefLevel [Byte0]: 46
7809 17:43:28.203135 [Byte1]: 46
7810 17:43:28.207649
7811 17:43:28.207731 Set Vref, RX VrefLevel [Byte0]: 47
7812 17:43:28.210957 [Byte1]: 47
7813 17:43:28.215283
7814 17:43:28.215359 Set Vref, RX VrefLevel [Byte0]: 48
7815 17:43:28.218290 [Byte1]: 48
7816 17:43:28.222355
7817 17:43:28.222442 Set Vref, RX VrefLevel [Byte0]: 49
7818 17:43:28.225559 [Byte1]: 49
7819 17:43:28.230237
7820 17:43:28.230325 Set Vref, RX VrefLevel [Byte0]: 50
7821 17:43:28.233424 [Byte1]: 50
7822 17:43:28.237972
7823 17:43:28.238047 Set Vref, RX VrefLevel [Byte0]: 51
7824 17:43:28.241329 [Byte1]: 51
7825 17:43:28.245134
7826 17:43:28.245248 Set Vref, RX VrefLevel [Byte0]: 52
7827 17:43:28.248922 [Byte1]: 52
7828 17:43:28.252702
7829 17:43:28.252841 Set Vref, RX VrefLevel [Byte0]: 53
7830 17:43:28.256361 [Byte1]: 53
7831 17:43:28.260239
7832 17:43:28.260371 Set Vref, RX VrefLevel [Byte0]: 54
7833 17:43:28.264057 [Byte1]: 54
7834 17:43:28.267977
7835 17:43:28.268096 Set Vref, RX VrefLevel [Byte0]: 55
7836 17:43:28.271248 [Byte1]: 55
7837 17:43:28.275782
7838 17:43:28.275912 Set Vref, RX VrefLevel [Byte0]: 56
7839 17:43:28.279137 [Byte1]: 56
7840 17:43:28.283144
7841 17:43:28.283259 Set Vref, RX VrefLevel [Byte0]: 57
7842 17:43:28.286501 [Byte1]: 57
7843 17:43:28.291125
7844 17:43:28.291240 Set Vref, RX VrefLevel [Byte0]: 58
7845 17:43:28.294149 [Byte1]: 58
7846 17:43:28.298334
7847 17:43:28.298450 Set Vref, RX VrefLevel [Byte0]: 59
7848 17:43:28.301773 [Byte1]: 59
7849 17:43:28.306014
7850 17:43:28.306127 Set Vref, RX VrefLevel [Byte0]: 60
7851 17:43:28.309153 [Byte1]: 60
7852 17:43:28.313198
7853 17:43:28.313314 Set Vref, RX VrefLevel [Byte0]: 61
7854 17:43:28.316699 [Byte1]: 61
7855 17:43:28.321235
7856 17:43:28.321351 Set Vref, RX VrefLevel [Byte0]: 62
7857 17:43:28.324578 [Byte1]: 62
7858 17:43:28.328761
7859 17:43:28.328875 Set Vref, RX VrefLevel [Byte0]: 63
7860 17:43:28.332060 [Byte1]: 63
7861 17:43:28.336113
7862 17:43:28.336226 Set Vref, RX VrefLevel [Byte0]: 64
7863 17:43:28.339355 [Byte1]: 64
7864 17:43:28.343905
7865 17:43:28.344021 Set Vref, RX VrefLevel [Byte0]: 65
7866 17:43:28.347303 [Byte1]: 65
7867 17:43:28.351171
7868 17:43:28.351293 Set Vref, RX VrefLevel [Byte0]: 66
7869 17:43:28.354489 [Byte1]: 66
7870 17:43:28.359119
7871 17:43:28.359236 Set Vref, RX VrefLevel [Byte0]: 67
7872 17:43:28.362300 [Byte1]: 67
7873 17:43:28.366423
7874 17:43:28.366544 Set Vref, RX VrefLevel [Byte0]: 68
7875 17:43:28.370024 [Byte1]: 68
7876 17:43:28.374143
7877 17:43:28.374271 Set Vref, RX VrefLevel [Byte0]: 69
7878 17:43:28.377337 [Byte1]: 69
7879 17:43:28.381767
7880 17:43:28.381884 Set Vref, RX VrefLevel [Byte0]: 70
7881 17:43:28.385178 [Byte1]: 70
7882 17:43:28.389186
7883 17:43:28.389301 Set Vref, RX VrefLevel [Byte0]: 71
7884 17:43:28.392577 [Byte1]: 71
7885 17:43:28.396634
7886 17:43:28.396747 Set Vref, RX VrefLevel [Byte0]: 72
7887 17:43:28.400000 [Byte1]: 72
7888 17:43:28.404084
7889 17:43:28.404202 Set Vref, RX VrefLevel [Byte0]: 73
7890 17:43:28.408103 [Byte1]: 73
7891 17:43:28.411936
7892 17:43:28.412048 Set Vref, RX VrefLevel [Byte0]: 74
7893 17:43:28.415198 [Byte1]: 74
7894 17:43:28.419364
7895 17:43:28.419489 Set Vref, RX VrefLevel [Byte0]: 75
7896 17:43:28.422535 [Byte1]: 75
7897 17:43:28.427303
7898 17:43:28.427423 Set Vref, RX VrefLevel [Byte0]: 76
7899 17:43:28.430622 [Byte1]: 76
7900 17:43:28.434314
7901 17:43:28.434432 Final RX Vref Byte 0 = 57 to rank0
7902 17:43:28.437758 Final RX Vref Byte 1 = 61 to rank0
7903 17:43:28.441219 Final RX Vref Byte 0 = 57 to rank1
7904 17:43:28.444562 Final RX Vref Byte 1 = 61 to rank1==
7905 17:43:28.447563 Dram Type= 6, Freq= 0, CH_0, rank 0
7906 17:43:28.454590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7907 17:43:28.454722 ==
7908 17:43:28.454829 DQS Delay:
7909 17:43:28.454930 DQS0 = 0, DQS1 = 0
7910 17:43:28.457856 DQM Delay:
7911 17:43:28.457978 DQM0 = 134, DQM1 = 127
7912 17:43:28.461203 DQ Delay:
7913 17:43:28.464491 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7914 17:43:28.467797 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7915 17:43:28.471119 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7916 17:43:28.474411 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =134
7917 17:43:28.474538
7918 17:43:28.474644
7919 17:43:28.474753
7920 17:43:28.477807 [DramC_TX_OE_Calibration] TA2
7921 17:43:28.480889 Original DQ_B0 (3 6) =30, OEN = 27
7922 17:43:28.484369 Original DQ_B1 (3 6) =30, OEN = 27
7923 17:43:28.487970 24, 0x0, End_B0=24 End_B1=24
7924 17:43:28.488094 25, 0x0, End_B0=25 End_B1=25
7925 17:43:28.490893 26, 0x0, End_B0=26 End_B1=26
7926 17:43:28.494394 27, 0x0, End_B0=27 End_B1=27
7927 17:43:28.497735 28, 0x0, End_B0=28 End_B1=28
7928 17:43:28.501045 29, 0x0, End_B0=29 End_B1=29
7929 17:43:28.501163 30, 0x0, End_B0=30 End_B1=30
7930 17:43:28.504409 31, 0x4141, End_B0=30 End_B1=30
7931 17:43:28.507661 Byte0 end_step=30 best_step=27
7932 17:43:28.511043 Byte1 end_step=30 best_step=27
7933 17:43:28.514355 Byte0 TX OE(2T, 0.5T) = (3, 3)
7934 17:43:28.517601 Byte1 TX OE(2T, 0.5T) = (3, 3)
7935 17:43:28.517726
7936 17:43:28.517835
7937 17:43:28.524110 [DQSOSCAuto] RK0, (LSB)MR18= 0x221d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 392 ps
7938 17:43:28.527419 CH0 RK0: MR19=303, MR18=221D
7939 17:43:28.534181 CH0_RK0: MR19=0x303, MR18=0x221D, DQSOSC=392, MR23=63, INC=24, DEC=16
7940 17:43:28.534292
7941 17:43:28.538022 ----->DramcWriteLeveling(PI) begin...
7942 17:43:28.538105 ==
7943 17:43:28.540937 Dram Type= 6, Freq= 0, CH_0, rank 1
7944 17:43:28.544597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7945 17:43:28.544679 ==
7946 17:43:28.547600 Write leveling (Byte 0): 38 => 38
7947 17:43:28.550886 Write leveling (Byte 1): 26 => 26
7948 17:43:28.554549 DramcWriteLeveling(PI) end<-----
7949 17:43:28.554631
7950 17:43:28.554695 ==
7951 17:43:28.557535 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 17:43:28.560968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 17:43:28.561059 ==
7954 17:43:28.563972 [Gating] SW mode calibration
7955 17:43:28.570581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7956 17:43:28.577234 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7957 17:43:28.580561 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7958 17:43:28.584069 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7959 17:43:28.590602 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 17:43:28.593802 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7961 17:43:28.597075 1 4 16 | B1->B0 | 2a2a 3534 | 1 1 | (0 0) (0 0)
7962 17:43:28.603658 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7963 17:43:28.607029 1 4 24 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7964 17:43:28.610381 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7965 17:43:28.617276 1 5 0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7966 17:43:28.619978 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7967 17:43:28.624059 1 5 8 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7968 17:43:28.630456 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
7969 17:43:28.633808 1 5 16 | B1->B0 | 2d2d 2625 | 0 1 | (0 1) (1 0)
7970 17:43:28.637100 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7971 17:43:28.643588 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7972 17:43:28.646885 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7973 17:43:28.649874 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 17:43:28.656843 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7975 17:43:28.660208 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7976 17:43:28.662926 1 6 12 | B1->B0 | 2525 3938 | 1 1 | (0 0) (0 0)
7977 17:43:28.669425 1 6 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7978 17:43:28.673056 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 17:43:28.676288 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 17:43:28.682986 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 17:43:28.686427 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7982 17:43:28.689895 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 17:43:28.696392 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 17:43:28.699901 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7985 17:43:28.702916 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7986 17:43:28.709288 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7987 17:43:28.713079 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 17:43:28.715961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 17:43:28.722667 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 17:43:28.725868 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 17:43:28.729171 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 17:43:28.736307 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 17:43:28.739661 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 17:43:28.742934 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 17:43:28.749602 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 17:43:28.752773 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 17:43:28.756011 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 17:43:28.762890 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 17:43:28.766101 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 17:43:28.769469 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8001 17:43:28.776133 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8002 17:43:28.779247 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 17:43:28.782649 Total UI for P1: 0, mck2ui 16
8004 17:43:28.785925 best dqsien dly found for B0: ( 1, 9, 14)
8005 17:43:28.789129 Total UI for P1: 0, mck2ui 16
8006 17:43:28.792441 best dqsien dly found for B1: ( 1, 9, 14)
8007 17:43:28.795536 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8008 17:43:28.799403 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8009 17:43:28.799540
8010 17:43:28.802328 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8011 17:43:28.805903 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8012 17:43:28.808892 [Gating] SW calibration Done
8013 17:43:28.808972 ==
8014 17:43:28.812560 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 17:43:28.815352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 17:43:28.819205 ==
8017 17:43:28.819299 RX Vref Scan: 0
8018 17:43:28.819367
8019 17:43:28.822347 RX Vref 0 -> 0, step: 1
8020 17:43:28.822427
8021 17:43:28.822493 RX Delay 0 -> 252, step: 8
8022 17:43:28.829023 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8023 17:43:28.832262 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8024 17:43:28.835970 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8025 17:43:28.839204 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8026 17:43:28.842623 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8027 17:43:28.849376 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8028 17:43:28.852648 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8029 17:43:28.855929 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8030 17:43:28.859076 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8031 17:43:28.862371 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8032 17:43:28.868884 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8033 17:43:28.872648 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8034 17:43:28.875956 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8035 17:43:28.879281 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8036 17:43:28.882425 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8037 17:43:28.889004 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8038 17:43:28.889090 ==
8039 17:43:28.892236 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 17:43:28.895274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 17:43:28.895359 ==
8042 17:43:28.895424 DQS Delay:
8043 17:43:28.899098 DQS0 = 0, DQS1 = 0
8044 17:43:28.899181 DQM Delay:
8045 17:43:28.902479 DQM0 = 137, DQM1 = 130
8046 17:43:28.902563 DQ Delay:
8047 17:43:28.905762 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8048 17:43:28.908896 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8049 17:43:28.912039 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8050 17:43:28.915222 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8051 17:43:28.915326
8052 17:43:28.918462
8053 17:43:28.918539 ==
8054 17:43:28.922122 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 17:43:28.925251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 17:43:28.925338 ==
8057 17:43:28.925407
8058 17:43:28.925469
8059 17:43:28.928646 TX Vref Scan disable
8060 17:43:28.928723 == TX Byte 0 ==
8061 17:43:28.935659 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8062 17:43:28.938767 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8063 17:43:28.938849 == TX Byte 1 ==
8064 17:43:28.945573 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8065 17:43:28.948500 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8066 17:43:28.948579 ==
8067 17:43:28.952390 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 17:43:28.955717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 17:43:28.955823 ==
8070 17:43:28.970056
8071 17:43:28.973427 TX Vref early break, caculate TX vref
8072 17:43:28.977118 TX Vref=16, minBit 2, minWin=23, winSum=383
8073 17:43:28.980458 TX Vref=18, minBit 0, minWin=24, winSum=398
8074 17:43:28.983679 TX Vref=20, minBit 1, minWin=24, winSum=404
8075 17:43:28.986882 TX Vref=22, minBit 3, minWin=24, winSum=408
8076 17:43:28.990102 TX Vref=24, minBit 1, minWin=25, winSum=420
8077 17:43:28.996681 TX Vref=26, minBit 1, minWin=25, winSum=426
8078 17:43:29.000487 TX Vref=28, minBit 3, minWin=25, winSum=424
8079 17:43:29.003609 TX Vref=30, minBit 2, minWin=25, winSum=416
8080 17:43:29.007030 TX Vref=32, minBit 1, minWin=25, winSum=410
8081 17:43:29.010232 TX Vref=34, minBit 0, minWin=24, winSum=401
8082 17:43:29.016623 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8083 17:43:29.016826
8084 17:43:29.019872 Final TX Range 0 Vref 26
8085 17:43:29.020034
8086 17:43:29.020121 ==
8087 17:43:29.023205 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 17:43:29.026318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 17:43:29.026424 ==
8090 17:43:29.026494
8091 17:43:29.026554
8092 17:43:29.030123 TX Vref Scan disable
8093 17:43:29.036336 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8094 17:43:29.036443 == TX Byte 0 ==
8095 17:43:29.039737 u2DelayCellOfst[0]=13 cells (4 PI)
8096 17:43:29.043034 u2DelayCellOfst[1]=16 cells (5 PI)
8097 17:43:29.046924 u2DelayCellOfst[2]=10 cells (3 PI)
8098 17:43:29.050002 u2DelayCellOfst[3]=13 cells (4 PI)
8099 17:43:29.053199 u2DelayCellOfst[4]=10 cells (3 PI)
8100 17:43:29.056272 u2DelayCellOfst[5]=0 cells (0 PI)
8101 17:43:29.059507 u2DelayCellOfst[6]=16 cells (5 PI)
8102 17:43:29.063362 u2DelayCellOfst[7]=16 cells (5 PI)
8103 17:43:29.066584 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8104 17:43:29.069739 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8105 17:43:29.073099 == TX Byte 1 ==
8106 17:43:29.073175 u2DelayCellOfst[8]=0 cells (0 PI)
8107 17:43:29.076492 u2DelayCellOfst[9]=0 cells (0 PI)
8108 17:43:29.079604 u2DelayCellOfst[10]=3 cells (1 PI)
8109 17:43:29.082757 u2DelayCellOfst[11]=3 cells (1 PI)
8110 17:43:29.086751 u2DelayCellOfst[12]=6 cells (2 PI)
8111 17:43:29.089870 u2DelayCellOfst[13]=10 cells (3 PI)
8112 17:43:29.093147 u2DelayCellOfst[14]=10 cells (3 PI)
8113 17:43:29.096369 u2DelayCellOfst[15]=10 cells (3 PI)
8114 17:43:29.099757 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8115 17:43:29.106138 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8116 17:43:29.106225 DramC Write-DBI on
8117 17:43:29.106320 ==
8118 17:43:29.109337 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 17:43:29.113194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 17:43:29.116697 ==
8121 17:43:29.116778
8122 17:43:29.116877
8123 17:43:29.116936 TX Vref Scan disable
8124 17:43:29.119845 == TX Byte 0 ==
8125 17:43:29.123401 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8126 17:43:29.126637 == TX Byte 1 ==
8127 17:43:29.130031 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8128 17:43:29.130114 DramC Write-DBI off
8129 17:43:29.133250
8130 17:43:29.133331 [DATLAT]
8131 17:43:29.133395 Freq=1600, CH0 RK1
8132 17:43:29.133460
8133 17:43:29.136320 DATLAT Default: 0xf
8134 17:43:29.136401 0, 0xFFFF, sum = 0
8135 17:43:29.139974 1, 0xFFFF, sum = 0
8136 17:43:29.140057 2, 0xFFFF, sum = 0
8137 17:43:29.143268 3, 0xFFFF, sum = 0
8138 17:43:29.146558 4, 0xFFFF, sum = 0
8139 17:43:29.146641 5, 0xFFFF, sum = 0
8140 17:43:29.149962 6, 0xFFFF, sum = 0
8141 17:43:29.150071 7, 0xFFFF, sum = 0
8142 17:43:29.153272 8, 0xFFFF, sum = 0
8143 17:43:29.153355 9, 0xFFFF, sum = 0
8144 17:43:29.156537 10, 0xFFFF, sum = 0
8145 17:43:29.156619 11, 0xFFFF, sum = 0
8146 17:43:29.159930 12, 0xFFFF, sum = 0
8147 17:43:29.160012 13, 0xFFFF, sum = 0
8148 17:43:29.163291 14, 0x0, sum = 1
8149 17:43:29.163374 15, 0x0, sum = 2
8150 17:43:29.166483 16, 0x0, sum = 3
8151 17:43:29.166586 17, 0x0, sum = 4
8152 17:43:29.169945 best_step = 15
8153 17:43:29.170023
8154 17:43:29.170086 ==
8155 17:43:29.172843 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 17:43:29.176588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 17:43:29.176712 ==
8158 17:43:29.176777 RX Vref Scan: 0
8159 17:43:29.179871
8160 17:43:29.179948 RX Vref 0 -> 0, step: 1
8161 17:43:29.180014
8162 17:43:29.183182 RX Delay 19 -> 252, step: 4
8163 17:43:29.186392 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8164 17:43:29.192599 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8165 17:43:29.196129 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8166 17:43:29.199613 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8167 17:43:29.202671 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8168 17:43:29.206324 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8169 17:43:29.212960 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8170 17:43:29.216080 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8171 17:43:29.219054 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8172 17:43:29.222447 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8173 17:43:29.226420 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8174 17:43:29.232663 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8175 17:43:29.235963 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8176 17:43:29.239244 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8177 17:43:29.242674 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8178 17:43:29.246252 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8179 17:43:29.249415 ==
8180 17:43:29.252666 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 17:43:29.256052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 17:43:29.256160 ==
8183 17:43:29.256240 DQS Delay:
8184 17:43:29.259282 DQS0 = 0, DQS1 = 0
8185 17:43:29.259376 DQM Delay:
8186 17:43:29.262717 DQM0 = 134, DQM1 = 127
8187 17:43:29.262814 DQ Delay:
8188 17:43:29.265995 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8189 17:43:29.269316 DQ4 =134, DQ5 =126, DQ6 =140, DQ7 =140
8190 17:43:29.272633 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8191 17:43:29.275998 DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =136
8192 17:43:29.276107
8193 17:43:29.276196
8194 17:43:29.276261
8195 17:43:29.279315 [DramC_TX_OE_Calibration] TA2
8196 17:43:29.282758 Original DQ_B0 (3 6) =30, OEN = 27
8197 17:43:29.286056 Original DQ_B1 (3 6) =30, OEN = 27
8198 17:43:29.289181 24, 0x0, End_B0=24 End_B1=24
8199 17:43:29.292287 25, 0x0, End_B0=25 End_B1=25
8200 17:43:29.292372 26, 0x0, End_B0=26 End_B1=26
8201 17:43:29.295803 27, 0x0, End_B0=27 End_B1=27
8202 17:43:29.298760 28, 0x0, End_B0=28 End_B1=28
8203 17:43:29.302378 29, 0x0, End_B0=29 End_B1=29
8204 17:43:29.305442 30, 0x0, End_B0=30 End_B1=30
8205 17:43:29.305551 31, 0x4141, End_B0=30 End_B1=30
8206 17:43:29.308862 Byte0 end_step=30 best_step=27
8207 17:43:29.311964 Byte1 end_step=30 best_step=27
8208 17:43:29.315505 Byte0 TX OE(2T, 0.5T) = (3, 3)
8209 17:43:29.318951 Byte1 TX OE(2T, 0.5T) = (3, 3)
8210 17:43:29.319032
8211 17:43:29.319103
8212 17:43:29.325662 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 395 ps
8213 17:43:29.328584 CH0 RK1: MR19=303, MR18=1D05
8214 17:43:29.335318 CH0_RK1: MR19=0x303, MR18=0x1D05, DQSOSC=395, MR23=63, INC=23, DEC=15
8215 17:43:29.338991 [RxdqsGatingPostProcess] freq 1600
8216 17:43:29.345696 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8217 17:43:29.345814 best DQS0 dly(2T, 0.5T) = (1, 1)
8218 17:43:29.348989 best DQS1 dly(2T, 0.5T) = (1, 1)
8219 17:43:29.352144 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8220 17:43:29.355399 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8221 17:43:29.358758 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 17:43:29.361986 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 17:43:29.365306 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 17:43:29.368486 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 17:43:29.371841 Pre-setting of DQS Precalculation
8226 17:43:29.375245 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8227 17:43:29.375327 ==
8228 17:43:29.378735 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 17:43:29.385295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 17:43:29.385380 ==
8231 17:43:29.388752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8232 17:43:29.395506 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8233 17:43:29.398709 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8234 17:43:29.405110 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8235 17:43:29.412723 [CA 0] Center 41 (12~71) winsize 60
8236 17:43:29.415959 [CA 1] Center 41 (12~71) winsize 60
8237 17:43:29.419842 [CA 2] Center 38 (9~68) winsize 60
8238 17:43:29.422891 [CA 3] Center 37 (8~66) winsize 59
8239 17:43:29.425853 [CA 4] Center 37 (8~67) winsize 60
8240 17:43:29.429771 [CA 5] Center 36 (7~66) winsize 60
8241 17:43:29.429887
8242 17:43:29.432632 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8243 17:43:29.432755
8244 17:43:29.436141 [CATrainingPosCal] consider 1 rank data
8245 17:43:29.439581 u2DelayCellTimex100 = 290/100 ps
8246 17:43:29.442850 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8247 17:43:29.449274 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8248 17:43:29.452599 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8249 17:43:29.456063 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8250 17:43:29.459276 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8251 17:43:29.462851 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8252 17:43:29.462934
8253 17:43:29.466128 CA PerBit enable=1, Macro0, CA PI delay=36
8254 17:43:29.466224
8255 17:43:29.469237 [CBTSetCACLKResult] CA Dly = 36
8256 17:43:29.472525 CS Dly: 11 (0~42)
8257 17:43:29.475830 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8258 17:43:29.479077 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8259 17:43:29.479176 ==
8260 17:43:29.482518 Dram Type= 6, Freq= 0, CH_1, rank 1
8261 17:43:29.485852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 17:43:29.485967 ==
8263 17:43:29.492608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 17:43:29.495938 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 17:43:29.502560 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 17:43:29.505843 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 17:43:29.516184 [CA 0] Center 42 (13~72) winsize 60
8268 17:43:29.519595 [CA 1] Center 42 (13~72) winsize 60
8269 17:43:29.522890 [CA 2] Center 39 (10~69) winsize 60
8270 17:43:29.526135 [CA 3] Center 38 (9~68) winsize 60
8271 17:43:29.529407 [CA 4] Center 39 (9~69) winsize 61
8272 17:43:29.532632 [CA 5] Center 38 (9~67) winsize 59
8273 17:43:29.532745
8274 17:43:29.535930 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8275 17:43:29.536049
8276 17:43:29.542262 [CATrainingPosCal] consider 2 rank data
8277 17:43:29.542448 u2DelayCellTimex100 = 290/100 ps
8278 17:43:29.549427 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8279 17:43:29.552648 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8280 17:43:29.556205 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8281 17:43:29.559281 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8282 17:43:29.562337 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8283 17:43:29.565617 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8284 17:43:29.565766
8285 17:43:29.569543 CA PerBit enable=1, Macro0, CA PI delay=37
8286 17:43:29.569625
8287 17:43:29.572522 [CBTSetCACLKResult] CA Dly = 37
8288 17:43:29.575973 CS Dly: 12 (0~45)
8289 17:43:29.579676 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 17:43:29.582374 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 17:43:29.582454
8292 17:43:29.585612 ----->DramcWriteLeveling(PI) begin...
8293 17:43:29.585711 ==
8294 17:43:29.589101 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 17:43:29.592818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 17:43:29.595994 ==
8297 17:43:29.599290 Write leveling (Byte 0): 27 => 27
8298 17:43:29.599406 Write leveling (Byte 1): 28 => 28
8299 17:43:29.602704 DramcWriteLeveling(PI) end<-----
8300 17:43:29.602789
8301 17:43:29.602853 ==
8302 17:43:29.606000 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 17:43:29.612704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 17:43:29.612816 ==
8305 17:43:29.612886 [Gating] SW mode calibration
8306 17:43:29.622611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8307 17:43:29.625851 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8308 17:43:29.629237 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8309 17:43:29.635828 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8310 17:43:29.639035 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8311 17:43:29.642929 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8312 17:43:29.649397 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 17:43:29.652866 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 17:43:29.656233 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 17:43:29.662448 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 17:43:29.665960 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 17:43:29.669092 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 17:43:29.676480 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8319 17:43:29.679126 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
8320 17:43:29.682445 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8321 17:43:29.689218 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 17:43:29.692958 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 17:43:29.696329 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 17:43:29.702417 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 17:43:29.705942 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 17:43:29.709350 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8327 17:43:29.715756 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 17:43:29.719430 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 17:43:29.722540 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 17:43:29.729115 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 17:43:29.732651 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 17:43:29.735835 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 17:43:29.739221 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 17:43:29.745705 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8335 17:43:29.749335 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8336 17:43:29.752569 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 17:43:29.759256 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 17:43:29.762644 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 17:43:29.766006 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 17:43:29.772402 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 17:43:29.775487 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 17:43:29.778584 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 17:43:29.785610 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 17:43:29.788664 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 17:43:29.791885 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 17:43:29.798878 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 17:43:29.801973 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 17:43:29.805383 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 17:43:29.812347 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 17:43:29.815453 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8351 17:43:29.818911 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8352 17:43:29.825332 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 17:43:29.825466 Total UI for P1: 0, mck2ui 16
8354 17:43:29.832450 best dqsien dly found for B0: ( 1, 9, 10)
8355 17:43:29.832576 Total UI for P1: 0, mck2ui 16
8356 17:43:29.835758 best dqsien dly found for B1: ( 1, 9, 10)
8357 17:43:29.842393 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8358 17:43:29.845705 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8359 17:43:29.845812
8360 17:43:29.849092 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8361 17:43:29.852344 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8362 17:43:29.855556 [Gating] SW calibration Done
8363 17:43:29.855686 ==
8364 17:43:29.858703 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 17:43:29.861906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 17:43:29.862040 ==
8367 17:43:29.865182 RX Vref Scan: 0
8368 17:43:29.865284
8369 17:43:29.865362 RX Vref 0 -> 0, step: 1
8370 17:43:29.865426
8371 17:43:29.868552 RX Delay 0 -> 252, step: 8
8372 17:43:29.871894 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8373 17:43:29.878596 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8374 17:43:29.881854 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8375 17:43:29.885233 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8376 17:43:29.888979 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8377 17:43:29.891928 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8378 17:43:29.898680 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8379 17:43:29.901903 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8380 17:43:29.905029 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8381 17:43:29.908733 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8382 17:43:29.912064 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8383 17:43:29.915283 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8384 17:43:29.921706 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8385 17:43:29.925513 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8386 17:43:29.928512 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8387 17:43:29.932090 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8388 17:43:29.932193 ==
8389 17:43:29.935232 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 17:43:29.941714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 17:43:29.941829 ==
8392 17:43:29.941926 DQS Delay:
8393 17:43:29.944966 DQS0 = 0, DQS1 = 0
8394 17:43:29.945055 DQM Delay:
8395 17:43:29.948942 DQM0 = 136, DQM1 = 132
8396 17:43:29.949061 DQ Delay:
8397 17:43:29.951658 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8398 17:43:29.954925 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8399 17:43:29.958385 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8400 17:43:29.961624 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8401 17:43:29.961745
8402 17:43:29.961850
8403 17:43:29.961952 ==
8404 17:43:29.965533 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 17:43:29.968370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 17:43:29.971533 ==
8407 17:43:29.971655
8408 17:43:29.971738
8409 17:43:29.971817 TX Vref Scan disable
8410 17:43:29.975060 == TX Byte 0 ==
8411 17:43:29.978210 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8412 17:43:29.981633 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8413 17:43:29.985447 == TX Byte 1 ==
8414 17:43:29.988616 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8415 17:43:29.991896 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8416 17:43:29.995262 ==
8417 17:43:29.998331 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 17:43:30.001385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 17:43:30.001467 ==
8420 17:43:30.014616
8421 17:43:30.018096 TX Vref early break, caculate TX vref
8422 17:43:30.021540 TX Vref=16, minBit 1, minWin=22, winSum=374
8423 17:43:30.024199 TX Vref=18, minBit 1, minWin=23, winSum=385
8424 17:43:30.027677 TX Vref=20, minBit 1, minWin=23, winSum=394
8425 17:43:30.031842 TX Vref=22, minBit 1, minWin=23, winSum=404
8426 17:43:30.034434 TX Vref=24, minBit 0, minWin=25, winSum=414
8427 17:43:30.041450 TX Vref=26, minBit 0, minWin=25, winSum=423
8428 17:43:30.044851 TX Vref=28, minBit 0, minWin=25, winSum=423
8429 17:43:30.047808 TX Vref=30, minBit 6, minWin=24, winSum=417
8430 17:43:30.051275 TX Vref=32, minBit 2, minWin=24, winSum=412
8431 17:43:30.054724 TX Vref=34, minBit 0, minWin=24, winSum=401
8432 17:43:30.057871 TX Vref=36, minBit 0, minWin=23, winSum=389
8433 17:43:30.064876 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8434 17:43:30.065007
8435 17:43:30.068137 Final TX Range 0 Vref 26
8436 17:43:30.068229
8437 17:43:30.068294 ==
8438 17:43:30.071382 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 17:43:30.074359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 17:43:30.074484 ==
8441 17:43:30.074582
8442 17:43:30.074672
8443 17:43:30.078076 TX Vref Scan disable
8444 17:43:30.084499 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8445 17:43:30.084622 == TX Byte 0 ==
8446 17:43:30.087912 u2DelayCellOfst[0]=16 cells (5 PI)
8447 17:43:30.091247 u2DelayCellOfst[1]=10 cells (3 PI)
8448 17:43:30.094510 u2DelayCellOfst[2]=0 cells (0 PI)
8449 17:43:30.098227 u2DelayCellOfst[3]=6 cells (2 PI)
8450 17:43:30.101672 u2DelayCellOfst[4]=6 cells (2 PI)
8451 17:43:30.104291 u2DelayCellOfst[5]=16 cells (5 PI)
8452 17:43:30.108254 u2DelayCellOfst[6]=16 cells (5 PI)
8453 17:43:30.108351 u2DelayCellOfst[7]=6 cells (2 PI)
8454 17:43:30.114352 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8455 17:43:30.117873 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8456 17:43:30.121482 == TX Byte 1 ==
8457 17:43:30.121600 u2DelayCellOfst[8]=0 cells (0 PI)
8458 17:43:30.124506 u2DelayCellOfst[9]=0 cells (0 PI)
8459 17:43:30.127550 u2DelayCellOfst[10]=10 cells (3 PI)
8460 17:43:30.131400 u2DelayCellOfst[11]=0 cells (0 PI)
8461 17:43:30.134724 u2DelayCellOfst[12]=13 cells (4 PI)
8462 17:43:30.137986 u2DelayCellOfst[13]=13 cells (4 PI)
8463 17:43:30.141266 u2DelayCellOfst[14]=13 cells (4 PI)
8464 17:43:30.144626 u2DelayCellOfst[15]=13 cells (4 PI)
8465 17:43:30.147988 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8466 17:43:30.154236 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8467 17:43:30.154356 DramC Write-DBI on
8468 17:43:30.154436 ==
8469 17:43:30.157500 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 17:43:30.160720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 17:43:30.163952 ==
8472 17:43:30.164039
8473 17:43:30.164105
8474 17:43:30.164177 TX Vref Scan disable
8475 17:43:30.167465 == TX Byte 0 ==
8476 17:43:30.171004 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8477 17:43:30.174505 == TX Byte 1 ==
8478 17:43:30.177521 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8479 17:43:30.180649 DramC Write-DBI off
8480 17:43:30.180779
8481 17:43:30.180877 [DATLAT]
8482 17:43:30.180968 Freq=1600, CH1 RK0
8483 17:43:30.181057
8484 17:43:30.184591 DATLAT Default: 0xf
8485 17:43:30.184680 0, 0xFFFF, sum = 0
8486 17:43:30.187634 1, 0xFFFF, sum = 0
8487 17:43:30.187742 2, 0xFFFF, sum = 0
8488 17:43:30.190925 3, 0xFFFF, sum = 0
8489 17:43:30.191026 4, 0xFFFF, sum = 0
8490 17:43:30.194223 5, 0xFFFF, sum = 0
8491 17:43:30.197611 6, 0xFFFF, sum = 0
8492 17:43:30.197722 7, 0xFFFF, sum = 0
8493 17:43:30.200801 8, 0xFFFF, sum = 0
8494 17:43:30.200897 9, 0xFFFF, sum = 0
8495 17:43:30.203967 10, 0xFFFF, sum = 0
8496 17:43:30.204082 11, 0xFFFF, sum = 0
8497 17:43:30.207975 12, 0xFFFF, sum = 0
8498 17:43:30.208053 13, 0xFFFF, sum = 0
8499 17:43:30.211251 14, 0x0, sum = 1
8500 17:43:30.211327 15, 0x0, sum = 2
8501 17:43:30.214621 16, 0x0, sum = 3
8502 17:43:30.214705 17, 0x0, sum = 4
8503 17:43:30.217236 best_step = 15
8504 17:43:30.217314
8505 17:43:30.217376 ==
8506 17:43:30.220582 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 17:43:30.224335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 17:43:30.224429 ==
8509 17:43:30.227314 RX Vref Scan: 1
8510 17:43:30.227424
8511 17:43:30.227498 Set Vref Range= 24 -> 127
8512 17:43:30.227562
8513 17:43:30.230914 RX Vref 24 -> 127, step: 1
8514 17:43:30.230997
8515 17:43:30.234039 RX Delay 27 -> 252, step: 4
8516 17:43:30.234123
8517 17:43:30.237561 Set Vref, RX VrefLevel [Byte0]: 24
8518 17:43:30.240408 [Byte1]: 24
8519 17:43:30.240517
8520 17:43:30.243769 Set Vref, RX VrefLevel [Byte0]: 25
8521 17:43:30.247174 [Byte1]: 25
8522 17:43:30.247295
8523 17:43:30.250467 Set Vref, RX VrefLevel [Byte0]: 26
8524 17:43:30.253843 [Byte1]: 26
8525 17:43:30.257607
8526 17:43:30.257727 Set Vref, RX VrefLevel [Byte0]: 27
8527 17:43:30.261399 [Byte1]: 27
8528 17:43:30.265450
8529 17:43:30.265566 Set Vref, RX VrefLevel [Byte0]: 28
8530 17:43:30.268699 [Byte1]: 28
8531 17:43:30.272736
8532 17:43:30.272851 Set Vref, RX VrefLevel [Byte0]: 29
8533 17:43:30.276056 [Byte1]: 29
8534 17:43:30.280447
8535 17:43:30.280532 Set Vref, RX VrefLevel [Byte0]: 30
8536 17:43:30.283561 [Byte1]: 30
8537 17:43:30.287893
8538 17:43:30.288089 Set Vref, RX VrefLevel [Byte0]: 31
8539 17:43:30.291530 [Byte1]: 31
8540 17:43:30.295569
8541 17:43:30.295775 Set Vref, RX VrefLevel [Byte0]: 32
8542 17:43:30.298684 [Byte1]: 32
8543 17:43:30.303370
8544 17:43:30.303547 Set Vref, RX VrefLevel [Byte0]: 33
8545 17:43:30.306643 [Byte1]: 33
8546 17:43:30.310616
8547 17:43:30.310785 Set Vref, RX VrefLevel [Byte0]: 34
8548 17:43:30.314147 [Byte1]: 34
8549 17:43:30.318149
8550 17:43:30.318351 Set Vref, RX VrefLevel [Byte0]: 35
8551 17:43:30.321566 [Byte1]: 35
8552 17:43:30.325697
8553 17:43:30.325883 Set Vref, RX VrefLevel [Byte0]: 36
8554 17:43:30.329090 [Byte1]: 36
8555 17:43:30.333016
8556 17:43:30.333187 Set Vref, RX VrefLevel [Byte0]: 37
8557 17:43:30.336432 [Byte1]: 37
8558 17:43:30.341090
8559 17:43:30.341282 Set Vref, RX VrefLevel [Byte0]: 38
8560 17:43:30.343716 [Byte1]: 38
8561 17:43:30.347957
8562 17:43:30.348134 Set Vref, RX VrefLevel [Byte0]: 39
8563 17:43:30.351258 [Byte1]: 39
8564 17:43:30.356075
8565 17:43:30.356216 Set Vref, RX VrefLevel [Byte0]: 40
8566 17:43:30.358737 [Byte1]: 40
8567 17:43:30.363394
8568 17:43:30.363574 Set Vref, RX VrefLevel [Byte0]: 41
8569 17:43:30.366582 [Byte1]: 41
8570 17:43:30.370634
8571 17:43:30.370776 Set Vref, RX VrefLevel [Byte0]: 42
8572 17:43:30.374056 [Byte1]: 42
8573 17:43:30.378160
8574 17:43:30.378316 Set Vref, RX VrefLevel [Byte0]: 43
8575 17:43:30.381337 [Byte1]: 43
8576 17:43:30.386167
8577 17:43:30.386354 Set Vref, RX VrefLevel [Byte0]: 44
8578 17:43:30.389403 [Byte1]: 44
8579 17:43:30.393348
8580 17:43:30.393501 Set Vref, RX VrefLevel [Byte0]: 45
8581 17:43:30.396712 [Byte1]: 45
8582 17:43:30.400554
8583 17:43:30.400710 Set Vref, RX VrefLevel [Byte0]: 46
8584 17:43:30.404396 [Byte1]: 46
8585 17:43:30.408218
8586 17:43:30.408373 Set Vref, RX VrefLevel [Byte0]: 47
8587 17:43:30.411924 [Byte1]: 47
8588 17:43:30.415706
8589 17:43:30.415874 Set Vref, RX VrefLevel [Byte0]: 48
8590 17:43:30.419502 [Byte1]: 48
8591 17:43:30.423802
8592 17:43:30.423945 Set Vref, RX VrefLevel [Byte0]: 49
8593 17:43:30.426551 [Byte1]: 49
8594 17:43:30.431363
8595 17:43:30.431503 Set Vref, RX VrefLevel [Byte0]: 50
8596 17:43:30.434619 [Byte1]: 50
8597 17:43:30.438626
8598 17:43:30.438753 Set Vref, RX VrefLevel [Byte0]: 51
8599 17:43:30.441857 [Byte1]: 51
8600 17:43:30.445912
8601 17:43:30.446078 Set Vref, RX VrefLevel [Byte0]: 52
8602 17:43:30.449372 [Byte1]: 52
8603 17:43:30.453638
8604 17:43:30.453793 Set Vref, RX VrefLevel [Byte0]: 53
8605 17:43:30.456830 [Byte1]: 53
8606 17:43:30.461530
8607 17:43:30.461627 Set Vref, RX VrefLevel [Byte0]: 54
8608 17:43:30.464222 [Byte1]: 54
8609 17:43:30.469009
8610 17:43:30.469149 Set Vref, RX VrefLevel [Byte0]: 55
8611 17:43:30.472091 [Byte1]: 55
8612 17:43:30.476009
8613 17:43:30.476152 Set Vref, RX VrefLevel [Byte0]: 56
8614 17:43:30.479491 [Byte1]: 56
8615 17:43:30.483470
8616 17:43:30.483611 Set Vref, RX VrefLevel [Byte0]: 57
8617 17:43:30.486793 [Byte1]: 57
8618 17:43:30.491120
8619 17:43:30.491203 Set Vref, RX VrefLevel [Byte0]: 58
8620 17:43:30.494796 [Byte1]: 58
8621 17:43:30.498716
8622 17:43:30.498828 Set Vref, RX VrefLevel [Byte0]: 59
8623 17:43:30.502182 [Byte1]: 59
8624 17:43:30.506045
8625 17:43:30.506132 Set Vref, RX VrefLevel [Byte0]: 60
8626 17:43:30.509576 [Byte1]: 60
8627 17:43:30.514182
8628 17:43:30.514289 Set Vref, RX VrefLevel [Byte0]: 61
8629 17:43:30.517168 [Byte1]: 61
8630 17:43:30.521419
8631 17:43:30.521533 Set Vref, RX VrefLevel [Byte0]: 62
8632 17:43:30.524515 [Byte1]: 62
8633 17:43:30.528981
8634 17:43:30.529119 Set Vref, RX VrefLevel [Byte0]: 63
8635 17:43:30.532442 [Byte1]: 63
8636 17:43:30.536360
8637 17:43:30.536474 Set Vref, RX VrefLevel [Byte0]: 64
8638 17:43:30.539769 [Byte1]: 64
8639 17:43:30.543814
8640 17:43:30.543918 Set Vref, RX VrefLevel [Byte0]: 65
8641 17:43:30.547233 [Byte1]: 65
8642 17:43:30.551858
8643 17:43:30.551952 Set Vref, RX VrefLevel [Byte0]: 66
8644 17:43:30.555112 [Byte1]: 66
8645 17:43:30.559015
8646 17:43:30.559112 Set Vref, RX VrefLevel [Byte0]: 67
8647 17:43:30.562731 [Byte1]: 67
8648 17:43:30.566334
8649 17:43:30.566486 Set Vref, RX VrefLevel [Byte0]: 68
8650 17:43:30.569616 [Byte1]: 68
8651 17:43:30.574396
8652 17:43:30.574518 Set Vref, RX VrefLevel [Byte0]: 69
8653 17:43:30.577092 [Byte1]: 69
8654 17:43:30.581664
8655 17:43:30.581774 Set Vref, RX VrefLevel [Byte0]: 70
8656 17:43:30.584671 [Byte1]: 70
8657 17:43:30.589556
8658 17:43:30.589676 Set Vref, RX VrefLevel [Byte0]: 71
8659 17:43:30.592453 [Byte1]: 71
8660 17:43:30.596407
8661 17:43:30.596524 Set Vref, RX VrefLevel [Byte0]: 72
8662 17:43:30.600460 [Byte1]: 72
8663 17:43:30.604238
8664 17:43:30.604333 Set Vref, RX VrefLevel [Byte0]: 73
8665 17:43:30.607568 [Byte1]: 73
8666 17:43:30.612099
8667 17:43:30.612192 Set Vref, RX VrefLevel [Byte0]: 74
8668 17:43:30.615382 [Byte1]: 74
8669 17:43:30.619472
8670 17:43:30.619557 Set Vref, RX VrefLevel [Byte0]: 75
8671 17:43:30.623115 [Byte1]: 75
8672 17:43:30.626715
8673 17:43:30.626806 Final RX Vref Byte 0 = 58 to rank0
8674 17:43:30.630005 Final RX Vref Byte 1 = 59 to rank0
8675 17:43:30.633785 Final RX Vref Byte 0 = 58 to rank1
8676 17:43:30.636767 Final RX Vref Byte 1 = 59 to rank1==
8677 17:43:30.640299 Dram Type= 6, Freq= 0, CH_1, rank 0
8678 17:43:30.646611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8679 17:43:30.646757 ==
8680 17:43:30.646857 DQS Delay:
8681 17:43:30.646949 DQS0 = 0, DQS1 = 0
8682 17:43:30.649989 DQM Delay:
8683 17:43:30.650077 DQM0 = 134, DQM1 = 131
8684 17:43:30.653380 DQ Delay:
8685 17:43:30.656667 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8686 17:43:30.659912 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8687 17:43:30.663393 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8688 17:43:30.666751 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8689 17:43:30.666915
8690 17:43:30.667023
8691 17:43:30.667089
8692 17:43:30.670027 [DramC_TX_OE_Calibration] TA2
8693 17:43:30.673266 Original DQ_B0 (3 6) =30, OEN = 27
8694 17:43:30.676317 Original DQ_B1 (3 6) =30, OEN = 27
8695 17:43:30.679581 24, 0x0, End_B0=24 End_B1=24
8696 17:43:30.679713 25, 0x0, End_B0=25 End_B1=25
8697 17:43:30.682935 26, 0x0, End_B0=26 End_B1=26
8698 17:43:30.686281 27, 0x0, End_B0=27 End_B1=27
8699 17:43:30.689569 28, 0x0, End_B0=28 End_B1=28
8700 17:43:30.693043 29, 0x0, End_B0=29 End_B1=29
8701 17:43:30.693159 30, 0x0, End_B0=30 End_B1=30
8702 17:43:30.696401 31, 0x4141, End_B0=30 End_B1=30
8703 17:43:30.699608 Byte0 end_step=30 best_step=27
8704 17:43:30.703115 Byte1 end_step=30 best_step=27
8705 17:43:30.706303 Byte0 TX OE(2T, 0.5T) = (3, 3)
8706 17:43:30.709411 Byte1 TX OE(2T, 0.5T) = (3, 3)
8707 17:43:30.709505
8708 17:43:30.709572
8709 17:43:30.716437 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8710 17:43:30.719686 CH1 RK0: MR19=303, MR18=1523
8711 17:43:30.726419 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8712 17:43:30.726533
8713 17:43:30.729946 ----->DramcWriteLeveling(PI) begin...
8714 17:43:30.730071 ==
8715 17:43:30.732601 Dram Type= 6, Freq= 0, CH_1, rank 1
8716 17:43:30.735813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 17:43:30.735930 ==
8718 17:43:30.739293 Write leveling (Byte 0): 26 => 26
8719 17:43:30.742843 Write leveling (Byte 1): 30 => 30
8720 17:43:30.745961 DramcWriteLeveling(PI) end<-----
8721 17:43:30.746071
8722 17:43:30.746172 ==
8723 17:43:30.749226 Dram Type= 6, Freq= 0, CH_1, rank 1
8724 17:43:30.752401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 17:43:30.752542 ==
8726 17:43:30.755838 [Gating] SW mode calibration
8727 17:43:30.762830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8728 17:43:30.769269 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8729 17:43:30.772682 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 17:43:30.779406 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 17:43:30.782642 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8732 17:43:30.785892 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8733 17:43:30.792699 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 17:43:30.796071 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 17:43:30.799376 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 17:43:30.802422 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 17:43:30.809756 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 17:43:30.812817 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 17:43:30.816124 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8740 17:43:30.822659 1 5 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
8741 17:43:30.825719 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 17:43:30.829084 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 17:43:30.836052 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 17:43:30.839489 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 17:43:30.842290 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 17:43:30.849474 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 17:43:30.852646 1 6 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8748 17:43:30.855431 1 6 12 | B1->B0 | 4545 3939 | 0 0 | (0 0) (1 1)
8749 17:43:30.862180 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 17:43:30.865886 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 17:43:30.868935 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 17:43:30.875772 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 17:43:30.878817 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 17:43:30.882097 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8755 17:43:30.888539 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8756 17:43:30.892351 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8757 17:43:30.895920 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8758 17:43:30.901967 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 17:43:30.905265 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 17:43:30.908493 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 17:43:30.915395 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 17:43:30.918731 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 17:43:30.922138 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 17:43:30.928771 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 17:43:30.932006 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 17:43:30.935312 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 17:43:30.942183 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 17:43:30.945699 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 17:43:30.949109 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 17:43:30.952525 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8771 17:43:30.958853 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8772 17:43:30.962345 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8773 17:43:30.965612 Total UI for P1: 0, mck2ui 16
8774 17:43:30.968486 best dqsien dly found for B1: ( 1, 9, 6)
8775 17:43:30.971919 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8776 17:43:30.978553 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 17:43:30.978711 Total UI for P1: 0, mck2ui 16
8778 17:43:30.985196 best dqsien dly found for B0: ( 1, 9, 14)
8779 17:43:30.988340 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8780 17:43:30.991759 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8781 17:43:30.991916
8782 17:43:30.995432 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8783 17:43:30.998297 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8784 17:43:31.001683 [Gating] SW calibration Done
8785 17:43:31.001844 ==
8786 17:43:31.005168 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 17:43:31.008628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 17:43:31.008765 ==
8789 17:43:31.011877 RX Vref Scan: 0
8790 17:43:31.011995
8791 17:43:31.012093 RX Vref 0 -> 0, step: 1
8792 17:43:31.012197
8793 17:43:31.015131 RX Delay 0 -> 252, step: 8
8794 17:43:31.018273 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8795 17:43:31.025053 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8796 17:43:31.028186 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8797 17:43:31.031662 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8798 17:43:31.034943 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8799 17:43:31.038208 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8800 17:43:31.045016 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8801 17:43:31.048535 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8802 17:43:31.051727 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8803 17:43:31.055177 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8804 17:43:31.058462 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8805 17:43:31.064760 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8806 17:43:31.068173 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8807 17:43:31.071543 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8808 17:43:31.074942 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8809 17:43:31.081510 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8810 17:43:31.081658 ==
8811 17:43:31.084858 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 17:43:31.088117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 17:43:31.088215 ==
8814 17:43:31.088284 DQS Delay:
8815 17:43:31.091238 DQS0 = 0, DQS1 = 0
8816 17:43:31.091324 DQM Delay:
8817 17:43:31.094542 DQM0 = 135, DQM1 = 133
8818 17:43:31.094630 DQ Delay:
8819 17:43:31.097888 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8820 17:43:31.101240 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8821 17:43:31.105064 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8822 17:43:31.108203 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8823 17:43:31.108297
8824 17:43:31.108365
8825 17:43:31.108427 ==
8826 17:43:31.111623 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 17:43:31.118214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 17:43:31.118317 ==
8829 17:43:31.118387
8830 17:43:31.118451
8831 17:43:31.121341 TX Vref Scan disable
8832 17:43:31.121429 == TX Byte 0 ==
8833 17:43:31.124922 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8834 17:43:31.131462 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8835 17:43:31.131560 == TX Byte 1 ==
8836 17:43:31.134353 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8837 17:43:31.141101 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8838 17:43:31.141190 ==
8839 17:43:31.144619 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 17:43:31.147974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 17:43:31.148060 ==
8842 17:43:31.160547
8843 17:43:31.163867 TX Vref early break, caculate TX vref
8844 17:43:31.167054 TX Vref=16, minBit 0, minWin=23, winSum=388
8845 17:43:31.170771 TX Vref=18, minBit 1, minWin=23, winSum=392
8846 17:43:31.174024 TX Vref=20, minBit 0, minWin=24, winSum=400
8847 17:43:31.177395 TX Vref=22, minBit 0, minWin=25, winSum=410
8848 17:43:31.180731 TX Vref=24, minBit 0, minWin=25, winSum=421
8849 17:43:31.187454 TX Vref=26, minBit 0, minWin=25, winSum=419
8850 17:43:31.190694 TX Vref=28, minBit 1, minWin=25, winSum=426
8851 17:43:31.193862 TX Vref=30, minBit 0, minWin=25, winSum=420
8852 17:43:31.197101 TX Vref=32, minBit 0, minWin=25, winSum=407
8853 17:43:31.200449 TX Vref=34, minBit 1, minWin=24, winSum=401
8854 17:43:31.207091 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8855 17:43:31.207229
8856 17:43:31.210366 Final TX Range 0 Vref 28
8857 17:43:31.210470
8858 17:43:31.210537 ==
8859 17:43:31.213625 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 17:43:31.217032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 17:43:31.217159 ==
8862 17:43:31.217272
8863 17:43:31.217378
8864 17:43:31.220282 TX Vref Scan disable
8865 17:43:31.227246 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8866 17:43:31.227397 == TX Byte 0 ==
8867 17:43:31.230315 u2DelayCellOfst[0]=16 cells (5 PI)
8868 17:43:31.233707 u2DelayCellOfst[1]=10 cells (3 PI)
8869 17:43:31.237193 u2DelayCellOfst[2]=0 cells (0 PI)
8870 17:43:31.240145 u2DelayCellOfst[3]=6 cells (2 PI)
8871 17:43:31.243740 u2DelayCellOfst[4]=10 cells (3 PI)
8872 17:43:31.246816 u2DelayCellOfst[5]=16 cells (5 PI)
8873 17:43:31.250189 u2DelayCellOfst[6]=20 cells (6 PI)
8874 17:43:31.250308 u2DelayCellOfst[7]=3 cells (1 PI)
8875 17:43:31.256992 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8876 17:43:31.260425 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8877 17:43:31.263834 == TX Byte 1 ==
8878 17:43:31.263957 u2DelayCellOfst[8]=0 cells (0 PI)
8879 17:43:31.267002 u2DelayCellOfst[9]=3 cells (1 PI)
8880 17:43:31.270246 u2DelayCellOfst[10]=10 cells (3 PI)
8881 17:43:31.273492 u2DelayCellOfst[11]=3 cells (1 PI)
8882 17:43:31.277182 u2DelayCellOfst[12]=13 cells (4 PI)
8883 17:43:31.280129 u2DelayCellOfst[13]=16 cells (5 PI)
8884 17:43:31.283323 u2DelayCellOfst[14]=16 cells (5 PI)
8885 17:43:31.286621 u2DelayCellOfst[15]=16 cells (5 PI)
8886 17:43:31.289962 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8887 17:43:31.296531 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8888 17:43:31.296623 DramC Write-DBI on
8889 17:43:31.296691 ==
8890 17:43:31.300387 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 17:43:31.303734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 17:43:31.307025 ==
8893 17:43:31.307110
8894 17:43:31.307176
8895 17:43:31.307237 TX Vref Scan disable
8896 17:43:31.310312 == TX Byte 0 ==
8897 17:43:31.313609 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8898 17:43:31.316846 == TX Byte 1 ==
8899 17:43:31.320253 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8900 17:43:31.323498 DramC Write-DBI off
8901 17:43:31.323608
8902 17:43:31.323698 [DATLAT]
8903 17:43:31.323763 Freq=1600, CH1 RK1
8904 17:43:31.323823
8905 17:43:31.326913 DATLAT Default: 0xf
8906 17:43:31.326997 0, 0xFFFF, sum = 0
8907 17:43:31.330286 1, 0xFFFF, sum = 0
8908 17:43:31.333033 2, 0xFFFF, sum = 0
8909 17:43:31.333158 3, 0xFFFF, sum = 0
8910 17:43:31.336364 4, 0xFFFF, sum = 0
8911 17:43:31.336485 5, 0xFFFF, sum = 0
8912 17:43:31.340148 6, 0xFFFF, sum = 0
8913 17:43:31.340270 7, 0xFFFF, sum = 0
8914 17:43:31.343299 8, 0xFFFF, sum = 0
8915 17:43:31.343421 9, 0xFFFF, sum = 0
8916 17:43:31.346554 10, 0xFFFF, sum = 0
8917 17:43:31.346682 11, 0xFFFF, sum = 0
8918 17:43:31.349694 12, 0xFFFF, sum = 0
8919 17:43:31.349819 13, 0xFFFF, sum = 0
8920 17:43:31.353459 14, 0x0, sum = 1
8921 17:43:31.353582 15, 0x0, sum = 2
8922 17:43:31.356792 16, 0x0, sum = 3
8923 17:43:31.356915 17, 0x0, sum = 4
8924 17:43:31.359849 best_step = 15
8925 17:43:31.359968
8926 17:43:31.360079 ==
8927 17:43:31.363429 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 17:43:31.366662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 17:43:31.366784 ==
8930 17:43:31.369964 RX Vref Scan: 0
8931 17:43:31.370080
8932 17:43:31.370188 RX Vref 0 -> 0, step: 1
8933 17:43:31.370292
8934 17:43:31.373446 RX Delay 19 -> 252, step: 4
8935 17:43:31.376653 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8936 17:43:31.383064 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8937 17:43:31.386520 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8938 17:43:31.389811 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8939 17:43:31.393354 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8940 17:43:31.396584 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8941 17:43:31.399586 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8942 17:43:31.406648 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8943 17:43:31.409919 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8944 17:43:31.413218 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8945 17:43:31.416501 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8946 17:43:31.419876 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8947 17:43:31.426754 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8948 17:43:31.430050 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8949 17:43:31.433389 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8950 17:43:31.436893 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8951 17:43:31.436978 ==
8952 17:43:31.440058 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 17:43:31.446530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 17:43:31.446617 ==
8955 17:43:31.446683 DQS Delay:
8956 17:43:31.449910 DQS0 = 0, DQS1 = 0
8957 17:43:31.449992 DQM Delay:
8958 17:43:31.453137 DQM0 = 134, DQM1 = 130
8959 17:43:31.453219 DQ Delay:
8960 17:43:31.456095 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8961 17:43:31.459530 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8962 17:43:31.463263 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8963 17:43:31.466528 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8964 17:43:31.466611
8965 17:43:31.466676
8966 17:43:31.466736
8967 17:43:31.469517 [DramC_TX_OE_Calibration] TA2
8968 17:43:31.473121 Original DQ_B0 (3 6) =30, OEN = 27
8969 17:43:31.476230 Original DQ_B1 (3 6) =30, OEN = 27
8970 17:43:31.479537 24, 0x0, End_B0=24 End_B1=24
8971 17:43:31.482614 25, 0x0, End_B0=25 End_B1=25
8972 17:43:31.482698 26, 0x0, End_B0=26 End_B1=26
8973 17:43:31.486597 27, 0x0, End_B0=27 End_B1=27
8974 17:43:31.489970 28, 0x0, End_B0=28 End_B1=28
8975 17:43:31.493104 29, 0x0, End_B0=29 End_B1=29
8976 17:43:31.493188 30, 0x0, End_B0=30 End_B1=30
8977 17:43:31.496295 31, 0x4141, End_B0=30 End_B1=30
8978 17:43:31.499421 Byte0 end_step=30 best_step=27
8979 17:43:31.503150 Byte1 end_step=30 best_step=27
8980 17:43:31.506096 Byte0 TX OE(2T, 0.5T) = (3, 3)
8981 17:43:31.509470 Byte1 TX OE(2T, 0.5T) = (3, 3)
8982 17:43:31.509545
8983 17:43:31.509610
8984 17:43:31.516289 [DQSOSCAuto] RK1, (LSB)MR18= 0x2006, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8985 17:43:31.519402 CH1 RK1: MR19=303, MR18=2006
8986 17:43:31.526245 CH1_RK1: MR19=0x303, MR18=0x2006, DQSOSC=393, MR23=63, INC=23, DEC=15
8987 17:43:31.529653 [RxdqsGatingPostProcess] freq 1600
8988 17:43:31.533025 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8989 17:43:31.536236 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 17:43:31.539633 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 17:43:31.542996 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 17:43:31.546361 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 17:43:31.549484 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 17:43:31.552564 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 17:43:31.556248 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 17:43:31.559556 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 17:43:31.562635 Pre-setting of DQS Precalculation
8998 17:43:31.565998 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8999 17:43:31.572992 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9000 17:43:31.579535 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9001 17:43:31.582523
9002 17:43:31.582630
9003 17:43:31.582722 [Calibration Summary] 3200 Mbps
9004 17:43:31.586317 CH 0, Rank 0
9005 17:43:31.586394 SW Impedance : PASS
9006 17:43:31.589499 DUTY Scan : NO K
9007 17:43:31.592854 ZQ Calibration : PASS
9008 17:43:31.592930 Jitter Meter : NO K
9009 17:43:31.596122 CBT Training : PASS
9010 17:43:31.599230 Write leveling : PASS
9011 17:43:31.599330 RX DQS gating : PASS
9012 17:43:31.603077 RX DQ/DQS(RDDQC) : PASS
9013 17:43:31.605746 TX DQ/DQS : PASS
9014 17:43:31.605826 RX DATLAT : PASS
9015 17:43:31.609148 RX DQ/DQS(Engine): PASS
9016 17:43:31.613079 TX OE : PASS
9017 17:43:31.613153 All Pass.
9018 17:43:31.613215
9019 17:43:31.613298 CH 0, Rank 1
9020 17:43:31.616370 SW Impedance : PASS
9021 17:43:31.619722 DUTY Scan : NO K
9022 17:43:31.619833 ZQ Calibration : PASS
9023 17:43:31.623415 Jitter Meter : NO K
9024 17:43:31.623490 CBT Training : PASS
9025 17:43:31.625983 Write leveling : PASS
9026 17:43:31.629581 RX DQS gating : PASS
9027 17:43:31.629683 RX DQ/DQS(RDDQC) : PASS
9028 17:43:31.632928 TX DQ/DQS : PASS
9029 17:43:31.635998 RX DATLAT : PASS
9030 17:43:31.636082 RX DQ/DQS(Engine): PASS
9031 17:43:31.639291 TX OE : PASS
9032 17:43:31.639373 All Pass.
9033 17:43:31.639440
9034 17:43:31.642701 CH 1, Rank 0
9035 17:43:31.642785 SW Impedance : PASS
9036 17:43:31.645989 DUTY Scan : NO K
9037 17:43:31.649276 ZQ Calibration : PASS
9038 17:43:31.649409 Jitter Meter : NO K
9039 17:43:31.652671 CBT Training : PASS
9040 17:43:31.655997 Write leveling : PASS
9041 17:43:31.656124 RX DQS gating : PASS
9042 17:43:31.659559 RX DQ/DQS(RDDQC) : PASS
9043 17:43:31.662764 TX DQ/DQS : PASS
9044 17:43:31.662902 RX DATLAT : PASS
9045 17:43:31.666416 RX DQ/DQS(Engine): PASS
9046 17:43:31.666549 TX OE : PASS
9047 17:43:31.669724 All Pass.
9048 17:43:31.669861
9049 17:43:31.669986 CH 1, Rank 1
9050 17:43:31.672926 SW Impedance : PASS
9051 17:43:31.673043 DUTY Scan : NO K
9052 17:43:31.676241 ZQ Calibration : PASS
9053 17:43:31.679547 Jitter Meter : NO K
9054 17:43:31.679676 CBT Training : PASS
9055 17:43:31.682909 Write leveling : PASS
9056 17:43:31.686136 RX DQS gating : PASS
9057 17:43:31.686245 RX DQ/DQS(RDDQC) : PASS
9058 17:43:31.689103 TX DQ/DQS : PASS
9059 17:43:31.692891 RX DATLAT : PASS
9060 17:43:31.692993 RX DQ/DQS(Engine): PASS
9061 17:43:31.695986 TX OE : PASS
9062 17:43:31.696065 All Pass.
9063 17:43:31.696157
9064 17:43:31.699220 DramC Write-DBI on
9065 17:43:31.702546 PER_BANK_REFRESH: Hybrid Mode
9066 17:43:31.702649 TX_TRACKING: ON
9067 17:43:31.712289 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9068 17:43:31.718918 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9069 17:43:31.726010 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 17:43:31.729337 [FAST_K] Save calibration result to emmc
9071 17:43:31.732551 sync common calibartion params.
9072 17:43:31.735840 sync cbt_mode0:1, 1:1
9073 17:43:31.739170 dram_init: ddr_geometry: 2
9074 17:43:31.739276 dram_init: ddr_geometry: 2
9075 17:43:31.742333 dram_init: ddr_geometry: 2
9076 17:43:31.746026 0:dram_rank_size:100000000
9077 17:43:31.746129 1:dram_rank_size:100000000
9078 17:43:31.752442 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9079 17:43:31.755668 DFS_SHUFFLE_HW_MODE: ON
9080 17:43:31.759077 dramc_set_vcore_voltage set vcore to 725000
9081 17:43:31.762465 Read voltage for 1600, 0
9082 17:43:31.762577 Vio18 = 0
9083 17:43:31.762673 Vcore = 725000
9084 17:43:31.765726 Vdram = 0
9085 17:43:31.765837 Vddq = 0
9086 17:43:31.765930 Vmddr = 0
9087 17:43:31.769022 switch to 3200 Mbps bootup
9088 17:43:31.772253 [DramcRunTimeConfig]
9089 17:43:31.772344 PHYPLL
9090 17:43:31.772421 DPM_CONTROL_AFTERK: ON
9091 17:43:31.775795 PER_BANK_REFRESH: ON
9092 17:43:31.779196 REFRESH_OVERHEAD_REDUCTION: ON
9093 17:43:31.779294 CMD_PICG_NEW_MODE: OFF
9094 17:43:31.782315 XRTWTW_NEW_MODE: ON
9095 17:43:31.782413 XRTRTR_NEW_MODE: ON
9096 17:43:31.785690 TX_TRACKING: ON
9097 17:43:31.785787 RDSEL_TRACKING: OFF
9098 17:43:31.789039 DQS Precalculation for DVFS: ON
9099 17:43:31.792395 RX_TRACKING: OFF
9100 17:43:31.792493 HW_GATING DBG: ON
9101 17:43:31.795571 ZQCS_ENABLE_LP4: ON
9102 17:43:31.795712 RX_PICG_NEW_MODE: ON
9103 17:43:31.798754 TX_PICG_NEW_MODE: ON
9104 17:43:31.802329 ENABLE_RX_DCM_DPHY: ON
9105 17:43:31.805242 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9106 17:43:31.805327 DUMMY_READ_FOR_TRACKING: OFF
9107 17:43:31.809069 !!! SPM_CONTROL_AFTERK: OFF
9108 17:43:31.812321 !!! SPM could not control APHY
9109 17:43:31.815825 IMPEDANCE_TRACKING: ON
9110 17:43:31.815926 TEMP_SENSOR: ON
9111 17:43:31.819040 HW_SAVE_FOR_SR: OFF
9112 17:43:31.819139 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9113 17:43:31.825708 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9114 17:43:31.825839 Read ODT Tracking: ON
9115 17:43:31.828740 Refresh Rate DeBounce: ON
9116 17:43:31.828840 DFS_NO_QUEUE_FLUSH: ON
9117 17:43:31.831840 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9118 17:43:31.835154 ENABLE_DFS_RUNTIME_MRW: OFF
9119 17:43:31.838438 DDR_RESERVE_NEW_MODE: ON
9120 17:43:31.838538 MR_CBT_SWITCH_FREQ: ON
9121 17:43:31.841716 =========================
9122 17:43:31.861527 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9123 17:43:31.864280 dram_init: ddr_geometry: 2
9124 17:43:31.882715 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9125 17:43:31.885945 dram_init: dram init end (result: 0)
9126 17:43:31.893062 DRAM-K: Full calibration passed in 24423 msecs
9127 17:43:31.896245 MRC: failed to locate region type 0.
9128 17:43:31.896351 DRAM rank0 size:0x100000000,
9129 17:43:31.899531 DRAM rank1 size=0x100000000
9130 17:43:31.909434 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9131 17:43:31.915888 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9132 17:43:31.922620 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9133 17:43:31.929140 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9134 17:43:31.932499 DRAM rank0 size:0x100000000,
9135 17:43:31.935649 DRAM rank1 size=0x100000000
9136 17:43:31.935754 CBMEM:
9137 17:43:31.939429 IMD: root @ 0xfffff000 254 entries.
9138 17:43:31.942665 IMD: root @ 0xffffec00 62 entries.
9139 17:43:31.946006 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9140 17:43:31.949398 WARNING: RO_VPD is uninitialized or empty.
9141 17:43:31.955867 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9142 17:43:31.963192 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9143 17:43:31.975758 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9144 17:43:31.987054 BS: romstage times (exec / console): total (unknown) / 23960 ms
9145 17:43:31.987204
9146 17:43:31.987313
9147 17:43:31.996984 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9148 17:43:32.000217 ARM64: Exception handlers installed.
9149 17:43:32.003505 ARM64: Testing exception
9150 17:43:32.006925 ARM64: Done test exception
9151 17:43:32.007016 Enumerating buses...
9152 17:43:32.010241 Show all devs... Before device enumeration.
9153 17:43:32.013632 Root Device: enabled 1
9154 17:43:32.016937 CPU_CLUSTER: 0: enabled 1
9155 17:43:32.017034 CPU: 00: enabled 1
9156 17:43:32.020084 Compare with tree...
9157 17:43:32.020199 Root Device: enabled 1
9158 17:43:32.023175 CPU_CLUSTER: 0: enabled 1
9159 17:43:32.026695 CPU: 00: enabled 1
9160 17:43:32.026792 Root Device scanning...
9161 17:43:32.030094 scan_static_bus for Root Device
9162 17:43:32.033637 CPU_CLUSTER: 0 enabled
9163 17:43:32.036725 scan_static_bus for Root Device done
9164 17:43:32.039981 scan_bus: bus Root Device finished in 8 msecs
9165 17:43:32.040085 done
9166 17:43:32.047065 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9167 17:43:32.049865 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9168 17:43:32.056954 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9169 17:43:32.060330 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9170 17:43:32.062965 Allocating resources...
9171 17:43:32.066931 Reading resources...
9172 17:43:32.069643 Root Device read_resources bus 0 link: 0
9173 17:43:32.069750 DRAM rank0 size:0x100000000,
9174 17:43:32.072922 DRAM rank1 size=0x100000000
9175 17:43:32.076800 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9176 17:43:32.080172 CPU: 00 missing read_resources
9177 17:43:32.083597 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9178 17:43:32.089804 Root Device read_resources bus 0 link: 0 done
9179 17:43:32.089900 Done reading resources.
9180 17:43:32.096242 Show resources in subtree (Root Device)...After reading.
9181 17:43:32.099519 Root Device child on link 0 CPU_CLUSTER: 0
9182 17:43:32.103285 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 17:43:32.113179 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 17:43:32.113284 CPU: 00
9185 17:43:32.116276 Root Device assign_resources, bus 0 link: 0
9186 17:43:32.119475 CPU_CLUSTER: 0 missing set_resources
9187 17:43:32.126374 Root Device assign_resources, bus 0 link: 0 done
9188 17:43:32.126480 Done setting resources.
9189 17:43:32.133030 Show resources in subtree (Root Device)...After assigning values.
9190 17:43:32.136178 Root Device child on link 0 CPU_CLUSTER: 0
9191 17:43:32.139933 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 17:43:32.149456 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 17:43:32.149583 CPU: 00
9194 17:43:32.153293 Done allocating resources.
9195 17:43:32.156449 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9196 17:43:32.159976 Enabling resources...
9197 17:43:32.160071 done.
9198 17:43:32.166390 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9199 17:43:32.166490 Initializing devices...
9200 17:43:32.169693 Root Device init
9201 17:43:32.169785 init hardware done!
9202 17:43:32.173184 0x00000018: ctrlr->caps
9203 17:43:32.176492 52.000 MHz: ctrlr->f_max
9204 17:43:32.176586 0.400 MHz: ctrlr->f_min
9205 17:43:32.179617 0x40ff8080: ctrlr->voltages
9206 17:43:32.179752 sclk: 390625
9207 17:43:32.182828 Bus Width = 1
9208 17:43:32.182931 sclk: 390625
9209 17:43:32.186268 Bus Width = 1
9210 17:43:32.186360 Early init status = 3
9211 17:43:32.192989 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9212 17:43:32.196285 in-header: 03 fc 00 00 01 00 00 00
9213 17:43:32.199914 in-data: 00
9214 17:43:32.203174 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9215 17:43:32.207588 in-header: 03 fd 00 00 00 00 00 00
9216 17:43:32.211319 in-data:
9217 17:43:32.214277 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9218 17:43:32.218750 in-header: 03 fc 00 00 01 00 00 00
9219 17:43:32.222220 in-data: 00
9220 17:43:32.225137 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9221 17:43:32.230735 in-header: 03 fd 00 00 00 00 00 00
9222 17:43:32.234602 in-data:
9223 17:43:32.237853 [SSUSB] Setting up USB HOST controller...
9224 17:43:32.240965 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9225 17:43:32.244397 [SSUSB] phy power-on done.
9226 17:43:32.247682 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9227 17:43:32.254402 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9228 17:43:32.257604 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9229 17:43:32.264215 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9230 17:43:32.270535 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9231 17:43:32.277564 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9232 17:43:32.284036 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9233 17:43:32.290461 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9234 17:43:32.293723 SPM: binary array size = 0x9dc
9235 17:43:32.297605 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9236 17:43:32.303792 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9237 17:43:32.310515 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9238 17:43:32.313903 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9239 17:43:32.320277 configure_display: Starting display init
9240 17:43:32.354441 anx7625_power_on_init: Init interface.
9241 17:43:32.357664 anx7625_disable_pd_protocol: Disabled PD feature.
9242 17:43:32.360928 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9243 17:43:32.388798 anx7625_start_dp_work: Secure OCM version=00
9244 17:43:32.391510 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9245 17:43:32.406916 sp_tx_get_edid_block: EDID Block = 1
9246 17:43:32.509296 Extracted contents:
9247 17:43:32.512330 header: 00 ff ff ff ff ff ff 00
9248 17:43:32.515758 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9249 17:43:32.518951 version: 01 04
9250 17:43:32.522937 basic params: 95 1f 11 78 0a
9251 17:43:32.525597 chroma info: 76 90 94 55 54 90 27 21 50 54
9252 17:43:32.528990 established: 00 00 00
9253 17:43:32.535540 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9254 17:43:32.538980 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9255 17:43:32.545681 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9256 17:43:32.552644 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9257 17:43:32.558831 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9258 17:43:32.562169 extensions: 00
9259 17:43:32.562309 checksum: fb
9260 17:43:32.562383
9261 17:43:32.565642 Manufacturer: IVO Model 57d Serial Number 0
9262 17:43:32.568897 Made week 0 of 2020
9263 17:43:32.569013 EDID version: 1.4
9264 17:43:32.572213 Digital display
9265 17:43:32.575394 6 bits per primary color channel
9266 17:43:32.575483 DisplayPort interface
9267 17:43:32.578800 Maximum image size: 31 cm x 17 cm
9268 17:43:32.582215 Gamma: 220%
9269 17:43:32.582332 Check DPMS levels
9270 17:43:32.585178 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9271 17:43:32.591911 First detailed timing is preferred timing
9272 17:43:32.592005 Established timings supported:
9273 17:43:32.595512 Standard timings supported:
9274 17:43:32.598461 Detailed timings
9275 17:43:32.602051 Hex of detail: 383680a07038204018303c0035ae10000019
9276 17:43:32.605410 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9277 17:43:32.612023 0780 0798 07c8 0820 hborder 0
9278 17:43:32.615222 0438 043b 0447 0458 vborder 0
9279 17:43:32.618354 -hsync -vsync
9280 17:43:32.618436 Did detailed timing
9281 17:43:32.625200 Hex of detail: 000000000000000000000000000000000000
9282 17:43:32.628525 Manufacturer-specified data, tag 0
9283 17:43:32.631859 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9284 17:43:32.635169 ASCII string: InfoVision
9285 17:43:32.638372 Hex of detail: 000000fe00523134304e574635205248200a
9286 17:43:32.641417 ASCII string: R140NWF5 RH
9287 17:43:32.641507 Checksum
9288 17:43:32.644632 Checksum: 0xfb (valid)
9289 17:43:32.647952 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9290 17:43:32.651199 DSI data_rate: 832800000 bps
9291 17:43:32.657863 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9292 17:43:32.661215 anx7625_parse_edid: pixelclock(138800).
9293 17:43:32.664578 hactive(1920), hsync(48), hfp(24), hbp(88)
9294 17:43:32.667908 vactive(1080), vsync(12), vfp(3), vbp(17)
9295 17:43:32.671245 anx7625_dsi_config: config dsi.
9296 17:43:32.677893 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9297 17:43:32.691546 anx7625_dsi_config: success to config DSI
9298 17:43:32.694526 anx7625_dp_start: MIPI phy setup OK.
9299 17:43:32.697664 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9300 17:43:32.701278 mtk_ddp_mode_set invalid vrefresh 60
9301 17:43:32.704251 main_disp_path_setup
9302 17:43:32.704363 ovl_layer_smi_id_en
9303 17:43:32.707541 ovl_layer_smi_id_en
9304 17:43:32.707668 ccorr_config
9305 17:43:32.707740 aal_config
9306 17:43:32.710951 gamma_config
9307 17:43:32.711061 postmask_config
9308 17:43:32.714484 dither_config
9309 17:43:32.717599 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9310 17:43:32.724031 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9311 17:43:32.727358 Root Device init finished in 555 msecs
9312 17:43:32.730712 CPU_CLUSTER: 0 init
9313 17:43:32.737429 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9314 17:43:32.740682 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9315 17:43:32.743918 APU_MBOX 0x190000b0 = 0x10001
9316 17:43:32.747722 APU_MBOX 0x190001b0 = 0x10001
9317 17:43:32.750882 APU_MBOX 0x190005b0 = 0x10001
9318 17:43:32.754202 APU_MBOX 0x190006b0 = 0x10001
9319 17:43:32.757569 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9320 17:43:32.770336 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9321 17:43:32.782273 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9322 17:43:32.789191 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9323 17:43:32.801091 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9324 17:43:32.810401 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9325 17:43:32.813349 CPU_CLUSTER: 0 init finished in 81 msecs
9326 17:43:32.816378 Devices initialized
9327 17:43:32.819979 Show all devs... After init.
9328 17:43:32.820065 Root Device: enabled 1
9329 17:43:32.823487 CPU_CLUSTER: 0: enabled 1
9330 17:43:32.826543 CPU: 00: enabled 1
9331 17:43:32.829910 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9332 17:43:32.833638 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9333 17:43:32.836565 ELOG: NV offset 0x57f000 size 0x1000
9334 17:43:32.843375 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9335 17:43:32.849716 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9336 17:43:32.853505 ELOG: Event(17) added with size 13 at 2023-09-13 17:42:05 UTC
9337 17:43:32.856585 out: cmd=0x121: 03 db 21 01 00 00 00 00
9338 17:43:32.860278 in-header: 03 f7 00 00 2c 00 00 00
9339 17:43:32.873753 in-data: 68 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9340 17:43:32.880603 ELOG: Event(A1) added with size 10 at 2023-09-13 17:42:05 UTC
9341 17:43:32.883938 ELOG: Event(16) added with size 11 at 2023-09-13 17:42:05 UTC
9342 17:43:32.970285 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9343 17:43:32.977078 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9344 17:43:32.983399 ELOG: Event(A0) added with size 9 at 2023-09-13 17:42:05 UTC
9345 17:43:32.986702 elog_add_boot_reason: Logged dev mode boot
9346 17:43:32.990048 BS: BS_POST_DEVICE entry times (exec / console): 82 / 74 ms
9347 17:43:32.993337 Finalize devices...
9348 17:43:32.993442 Devices finalized
9349 17:43:33.000026 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9350 17:43:33.003303 Writing coreboot table at 0xffe64000
9351 17:43:33.006628 0. 000000000010a000-0000000000113fff: RAMSTAGE
9352 17:43:33.009994 1. 0000000040000000-00000000400fffff: RAM
9353 17:43:33.017001 2. 0000000040100000-000000004032afff: RAMSTAGE
9354 17:43:33.020449 3. 000000004032b000-00000000545fffff: RAM
9355 17:43:33.023568 4. 0000000054600000-000000005465ffff: BL31
9356 17:43:33.027197 5. 0000000054660000-00000000ffe63fff: RAM
9357 17:43:33.033592 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9358 17:43:33.036853 7. 0000000100000000-000000023fffffff: RAM
9359 17:43:33.040140 Passing 5 GPIOs to payload:
9360 17:43:33.043413 NAME | PORT | POLARITY | VALUE
9361 17:43:33.046676 EC in RW | 0x000000aa | low | undefined
9362 17:43:33.053641 EC interrupt | 0x00000005 | low | undefined
9363 17:43:33.056301 TPM interrupt | 0x000000ab | high | undefined
9364 17:43:33.063127 SD card detect | 0x00000011 | high | undefined
9365 17:43:33.066179 speaker enable | 0x00000093 | high | undefined
9366 17:43:33.069981 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9367 17:43:33.073547 in-header: 03 f9 00 00 02 00 00 00
9368 17:43:33.076721 in-data: 02 00
9369 17:43:33.076800 ADC[4]: Raw value=904726 ID=7
9370 17:43:33.079746 ADC[3]: Raw value=213810 ID=1
9371 17:43:33.083107 RAM Code: 0x71
9372 17:43:33.083188 ADC[6]: Raw value=75701 ID=0
9373 17:43:33.086148 ADC[5]: Raw value=213072 ID=1
9374 17:43:33.089809 SKU Code: 0x1
9375 17:43:33.093067 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9376 17:43:33.096265 coreboot table: 964 bytes.
9377 17:43:33.099622 IMD ROOT 0. 0xfffff000 0x00001000
9378 17:43:33.103103 IMD SMALL 1. 0xffffe000 0x00001000
9379 17:43:33.106451 RO MCACHE 2. 0xffffc000 0x00001104
9380 17:43:33.109667 CONSOLE 3. 0xfff7c000 0x00080000
9381 17:43:33.112948 FMAP 4. 0xfff7b000 0x00000452
9382 17:43:33.116320 TIME STAMP 5. 0xfff7a000 0x00000910
9383 17:43:33.119512 VBOOT WORK 6. 0xfff66000 0x00014000
9384 17:43:33.123175 RAMOOPS 7. 0xffe66000 0x00100000
9385 17:43:33.126397 COREBOOT 8. 0xffe64000 0x00002000
9386 17:43:33.126487 IMD small region:
9387 17:43:33.129577 IMD ROOT 0. 0xffffec00 0x00000400
9388 17:43:33.132874 VPD 1. 0xffffeb80 0x0000006c
9389 17:43:33.136161 MMC STATUS 2. 0xffffeb60 0x00000004
9390 17:43:33.143431 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9391 17:43:33.146143 Probing TPM: done!
9392 17:43:33.149443 Connected to device vid:did:rid of 1ae0:0028:00
9393 17:43:33.159877 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9394 17:43:33.163120 Initialized TPM device CR50 revision 0
9395 17:43:33.166497 Checking cr50 for pending updates
9396 17:43:33.170575 Reading cr50 TPM mode
9397 17:43:33.178740 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9398 17:43:33.185544 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9399 17:43:33.225870 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9400 17:43:33.228828 Checking segment from ROM address 0x40100000
9401 17:43:33.232607 Checking segment from ROM address 0x4010001c
9402 17:43:33.239004 Loading segment from ROM address 0x40100000
9403 17:43:33.239114 code (compression=0)
9404 17:43:33.248920 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9405 17:43:33.255657 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9406 17:43:33.255795 it's not compressed!
9407 17:43:33.262632 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9408 17:43:33.265677 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9409 17:43:33.286011 Loading segment from ROM address 0x4010001c
9410 17:43:33.286120 Entry Point 0x80000000
9411 17:43:33.289314 Loaded segments
9412 17:43:33.292592 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9413 17:43:33.299690 Jumping to boot code at 0x80000000(0xffe64000)
9414 17:43:33.306161 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9415 17:43:33.312806 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9416 17:43:33.320691 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9417 17:43:33.323831 Checking segment from ROM address 0x40100000
9418 17:43:33.327300 Checking segment from ROM address 0x4010001c
9419 17:43:33.333918 Loading segment from ROM address 0x40100000
9420 17:43:33.334049 code (compression=1)
9421 17:43:33.340710 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9422 17:43:33.350624 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9423 17:43:33.350763 using LZMA
9424 17:43:33.358514 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9425 17:43:33.365139 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9426 17:43:33.369293 Loading segment from ROM address 0x4010001c
9427 17:43:33.369418 Entry Point 0x54601000
9428 17:43:33.372294 Loaded segments
9429 17:43:33.375563 NOTICE: MT8192 bl31_setup
9430 17:43:33.382289 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9431 17:43:33.385598 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9432 17:43:33.389189 WARNING: region 0:
9433 17:43:33.392411 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 17:43:33.392516 WARNING: region 1:
9435 17:43:33.399343 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9436 17:43:33.402402 WARNING: region 2:
9437 17:43:33.405560 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9438 17:43:33.408852 WARNING: region 3:
9439 17:43:33.412221 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 17:43:33.415581 WARNING: region 4:
9441 17:43:33.422203 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9442 17:43:33.422322 WARNING: region 5:
9443 17:43:33.425394 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 17:43:33.428962 WARNING: region 6:
9445 17:43:33.432605 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 17:43:33.435927 WARNING: region 7:
9447 17:43:33.439193 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 17:43:33.446160 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9449 17:43:33.449451 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9450 17:43:33.452609 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9451 17:43:33.459261 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9452 17:43:33.462235 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9453 17:43:33.465947 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9454 17:43:33.472582 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9455 17:43:33.475891 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9456 17:43:33.482229 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9457 17:43:33.485512 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9458 17:43:33.488927 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9459 17:43:33.495882 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9460 17:43:33.498992 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9461 17:43:33.502733 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9462 17:43:33.508930 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9463 17:43:33.512578 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9464 17:43:33.515968 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9465 17:43:33.522703 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9466 17:43:33.525989 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9467 17:43:33.532578 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9468 17:43:33.535731 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9469 17:43:33.539410 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9470 17:43:33.546007 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9471 17:43:33.549128 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9472 17:43:33.552786 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9473 17:43:33.559774 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9474 17:43:33.562390 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9475 17:43:33.569033 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9476 17:43:33.572833 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9477 17:43:33.576111 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9478 17:43:33.582892 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9479 17:43:33.585987 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9480 17:43:33.589805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9481 17:43:33.595910 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9482 17:43:33.599334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9483 17:43:33.602615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9484 17:43:33.606449 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9485 17:43:33.613296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9486 17:43:33.616570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9487 17:43:33.619507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9488 17:43:33.623328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9489 17:43:33.630083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9490 17:43:33.633530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9491 17:43:33.636290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9492 17:43:33.639587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9493 17:43:33.646254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9494 17:43:33.649568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9495 17:43:33.652963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9496 17:43:33.659890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9497 17:43:33.662860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9498 17:43:33.666349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9499 17:43:33.673099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9500 17:43:33.676242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9501 17:43:33.683431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9502 17:43:33.686773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9503 17:43:33.690069 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9504 17:43:33.696307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9505 17:43:33.699566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9506 17:43:33.706425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9507 17:43:33.709777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9508 17:43:33.716679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9509 17:43:33.720054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9510 17:43:33.726666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9511 17:43:33.729783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9512 17:43:33.733108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9513 17:43:33.739830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9514 17:43:33.743252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9515 17:43:33.750060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9516 17:43:33.753240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9517 17:43:33.759819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9518 17:43:33.763146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9519 17:43:33.766297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9520 17:43:33.773160 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9521 17:43:33.776687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9522 17:43:33.783207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9523 17:43:33.786738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9524 17:43:33.793139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9525 17:43:33.796295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9526 17:43:33.799589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9527 17:43:33.806197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9528 17:43:33.810095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9529 17:43:33.816930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9530 17:43:33.820100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9531 17:43:33.826864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9532 17:43:33.829562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9533 17:43:33.833399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9534 17:43:33.839886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9535 17:43:33.843333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9536 17:43:33.849993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9537 17:43:33.853344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9538 17:43:33.860064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9539 17:43:33.863272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9540 17:43:33.866526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9541 17:43:33.873121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9542 17:43:33.876412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9543 17:43:33.883358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9544 17:43:33.886614 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9545 17:43:33.889834 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9546 17:43:33.896416 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9547 17:43:33.900005 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9548 17:43:33.903394 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9549 17:43:33.906351 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9550 17:43:33.913563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9551 17:43:33.916358 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9552 17:43:33.923186 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9553 17:43:33.926502 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9554 17:43:33.929923 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9555 17:43:33.936980 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9556 17:43:33.940258 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9557 17:43:33.946743 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9558 17:43:33.950132 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9559 17:43:33.953469 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9560 17:43:33.960087 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9561 17:43:33.963404 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9562 17:43:33.969963 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9563 17:43:33.973121 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9564 17:43:33.976562 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9565 17:43:33.979803 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9566 17:43:33.986535 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9567 17:43:33.990382 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9568 17:43:33.993687 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9569 17:43:33.997131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9570 17:43:34.003276 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9571 17:43:34.006476 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9572 17:43:34.010091 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9573 17:43:34.016443 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9574 17:43:34.020221 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9575 17:43:34.026374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9576 17:43:34.029807 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9577 17:43:34.033630 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9578 17:43:34.039992 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9579 17:43:34.043225 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9580 17:43:34.046551 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9581 17:43:34.053582 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9582 17:43:34.056352 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9583 17:43:34.063139 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9584 17:43:34.066556 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9585 17:43:34.069895 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9586 17:43:34.076423 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9587 17:43:34.079998 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9588 17:43:34.086456 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9589 17:43:34.089809 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9590 17:43:34.093842 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9591 17:43:34.099962 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9592 17:43:34.103338 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9593 17:43:34.106675 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9594 17:43:34.113446 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9595 17:43:34.116790 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9596 17:43:34.123232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9597 17:43:34.126615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9598 17:43:34.130236 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9599 17:43:34.136926 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9600 17:43:34.140212 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9601 17:43:34.143432 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9602 17:43:34.150609 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9603 17:43:34.153946 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9604 17:43:34.160729 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9605 17:43:34.163946 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9606 17:43:34.167295 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9607 17:43:34.174005 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9608 17:43:34.177356 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9609 17:43:34.183803 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9610 17:43:34.187025 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9611 17:43:34.190118 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9612 17:43:34.197158 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9613 17:43:34.200414 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9614 17:43:34.203578 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9615 17:43:34.210353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9616 17:43:34.213737 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9617 17:43:34.220230 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9618 17:43:34.223662 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9619 17:43:34.229962 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9620 17:43:34.233155 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9621 17:43:34.236440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9622 17:43:34.243111 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9623 17:43:34.246507 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9624 17:43:34.249906 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9625 17:43:34.256622 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9626 17:43:34.259991 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9627 17:43:34.266766 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9628 17:43:34.269836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9629 17:43:34.273263 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9630 17:43:34.279712 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9631 17:43:34.283092 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9632 17:43:34.289703 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9633 17:43:34.293054 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9634 17:43:34.296272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9635 17:43:34.303434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9636 17:43:34.306323 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9637 17:43:34.312813 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9638 17:43:34.316326 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9639 17:43:34.319607 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9640 17:43:34.326213 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9641 17:43:34.329559 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9642 17:43:34.336283 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9643 17:43:34.340040 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9644 17:43:34.342926 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9645 17:43:34.349915 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9646 17:43:34.353197 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9647 17:43:34.359801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9648 17:43:34.363202 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9649 17:43:34.369993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9650 17:43:34.372620 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9651 17:43:34.376552 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9652 17:43:34.382902 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9653 17:43:34.385993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9654 17:43:34.393033 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9655 17:43:34.396244 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9656 17:43:34.399612 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9657 17:43:34.406069 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9658 17:43:34.409432 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9659 17:43:34.416331 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9660 17:43:34.419498 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9661 17:43:34.425977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9662 17:43:34.429870 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9663 17:43:34.433205 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9664 17:43:34.439281 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9665 17:43:34.442687 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9666 17:43:34.449293 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9667 17:43:34.453022 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9668 17:43:34.455884 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9669 17:43:34.462974 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9670 17:43:34.466329 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9671 17:43:34.472970 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9672 17:43:34.476384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9673 17:43:34.479596 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9674 17:43:34.485689 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9675 17:43:34.489591 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9676 17:43:34.495965 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9677 17:43:34.499156 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9678 17:43:34.502661 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9679 17:43:34.506206 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9680 17:43:34.512702 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9681 17:43:34.516258 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9682 17:43:34.519364 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9683 17:43:34.525730 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9684 17:43:34.529451 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9685 17:43:34.532529 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9686 17:43:34.539077 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9687 17:43:34.542496 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9688 17:43:34.545780 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9689 17:43:34.552348 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9690 17:43:34.555621 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9691 17:43:34.558935 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9692 17:43:34.565382 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9693 17:43:34.568946 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9694 17:43:34.575747 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9695 17:43:34.578532 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9696 17:43:34.582419 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9697 17:43:34.588590 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9698 17:43:34.592592 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9699 17:43:34.598778 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9700 17:43:34.602236 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9701 17:43:34.605045 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9702 17:43:34.611816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9703 17:43:34.615143 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9704 17:43:34.618303 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9705 17:43:34.625290 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9706 17:43:34.628828 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9707 17:43:34.632131 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9708 17:43:34.638234 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9709 17:43:34.641957 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9710 17:43:34.648700 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9711 17:43:34.651737 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9712 17:43:34.654952 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9713 17:43:34.661541 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9714 17:43:34.664924 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9715 17:43:34.668249 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9716 17:43:34.674807 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9717 17:43:34.678483 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9718 17:43:34.681629 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9719 17:43:34.685188 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9720 17:43:34.688170 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9721 17:43:34.695475 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9722 17:43:34.698200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9723 17:43:34.701687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9724 17:43:34.705186 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9725 17:43:34.711947 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9726 17:43:34.715094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9727 17:43:34.718514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9728 17:43:34.725279 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9729 17:43:34.728464 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9730 17:43:34.731707 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9731 17:43:34.738468 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9732 17:43:34.741880 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9733 17:43:34.745139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9734 17:43:34.751717 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9735 17:43:34.754859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9736 17:43:34.762028 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9737 17:43:34.765095 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9738 17:43:34.768647 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9739 17:43:34.774995 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9740 17:43:34.778276 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9741 17:43:34.784923 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9742 17:43:34.788083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9743 17:43:34.794780 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9744 17:43:34.798278 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9745 17:43:34.801846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9746 17:43:34.808447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9747 17:43:34.811892 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9748 17:43:34.817906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9749 17:43:34.821221 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9750 17:43:34.824636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9751 17:43:34.831265 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9752 17:43:34.834628 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9753 17:43:34.841664 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9754 17:43:34.844989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9755 17:43:34.848221 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9756 17:43:34.854765 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9757 17:43:34.858153 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9758 17:43:34.864696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9759 17:43:34.867993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9760 17:43:34.871393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9761 17:43:34.877885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9762 17:43:34.881567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9763 17:43:34.888310 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9764 17:43:34.891627 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9765 17:43:34.894934 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9766 17:43:34.901442 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9767 17:43:34.904678 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9768 17:43:34.911610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9769 17:43:34.914462 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9770 17:43:34.918505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9771 17:43:34.924999 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9772 17:43:34.928305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9773 17:43:34.934802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9774 17:43:34.938113 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9775 17:43:34.941497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9776 17:43:34.947957 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9777 17:43:34.951161 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9778 17:43:34.958217 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9779 17:43:34.961421 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9780 17:43:34.964569 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9781 17:43:34.971120 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9782 17:43:34.974596 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9783 17:43:34.981209 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9784 17:43:34.984614 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9785 17:43:34.987850 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9786 17:43:34.994760 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9787 17:43:34.997716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9788 17:43:35.004242 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9789 17:43:35.008191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9790 17:43:35.015013 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9791 17:43:35.018046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9792 17:43:35.021125 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9793 17:43:35.028206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9794 17:43:35.031240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9795 17:43:35.034581 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9796 17:43:35.041257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9797 17:43:35.044594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9798 17:43:35.051106 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9799 17:43:35.054460 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9800 17:43:35.061559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9801 17:43:35.064877 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9802 17:43:35.068112 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9803 17:43:35.074604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9804 17:43:35.078001 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9805 17:43:35.084601 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9806 17:43:35.087983 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9807 17:43:35.094719 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9808 17:43:35.098006 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9809 17:43:35.101207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9810 17:43:35.107943 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9811 17:43:35.110979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9812 17:43:35.117900 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9813 17:43:35.121127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9814 17:43:35.127844 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9815 17:43:35.130945 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9816 17:43:35.137778 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9817 17:43:35.140588 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9818 17:43:35.144259 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9819 17:43:35.151050 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9820 17:43:35.154278 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9821 17:43:35.161088 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9822 17:43:35.164291 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9823 17:43:35.170906 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9824 17:43:35.174215 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9825 17:43:35.177425 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9826 17:43:35.183907 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9827 17:43:35.187743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9828 17:43:35.193873 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9829 17:43:35.197242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9830 17:43:35.204078 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9831 17:43:35.207613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9832 17:43:35.211054 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9833 17:43:35.217280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9834 17:43:35.220465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9835 17:43:35.227238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9836 17:43:35.230795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9837 17:43:35.237063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9838 17:43:35.240606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9839 17:43:35.243628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9840 17:43:35.250513 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9841 17:43:35.253683 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9842 17:43:35.260609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9843 17:43:35.263771 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9844 17:43:35.270729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9845 17:43:35.273782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9846 17:43:35.277102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9847 17:43:35.283995 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9848 17:43:35.287303 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9849 17:43:35.293751 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9850 17:43:35.296917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9851 17:43:35.300330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9852 17:43:35.307159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9853 17:43:35.310455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9854 17:43:35.317252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9855 17:43:35.319963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9856 17:43:35.327244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9857 17:43:35.329933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9858 17:43:35.336411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9859 17:43:35.339634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9860 17:43:35.346689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9861 17:43:35.349800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9862 17:43:35.356201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9863 17:43:35.360137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9864 17:43:35.366101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9865 17:43:35.369706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9866 17:43:35.376130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9867 17:43:35.379089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9868 17:43:35.385826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9869 17:43:35.389224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9870 17:43:35.395915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9871 17:43:35.399243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9872 17:43:35.405858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9873 17:43:35.409299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9874 17:43:35.416157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9875 17:43:35.418862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9876 17:43:35.425590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9877 17:43:35.428955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9878 17:43:35.435599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9879 17:43:35.438979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9880 17:43:35.445767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9881 17:43:35.449038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9882 17:43:35.455711 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9883 17:43:35.455823 INFO: [APUAPC] vio 0
9884 17:43:35.462247 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9885 17:43:35.466144 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9886 17:43:35.469097 INFO: [APUAPC] D0_APC_0: 0x400510
9887 17:43:35.472562 INFO: [APUAPC] D0_APC_1: 0x0
9888 17:43:35.475567 INFO: [APUAPC] D0_APC_2: 0x1540
9889 17:43:35.479228 INFO: [APUAPC] D0_APC_3: 0x0
9890 17:43:35.482638 INFO: [APUAPC] D1_APC_0: 0xffffffff
9891 17:43:35.485847 INFO: [APUAPC] D1_APC_1: 0xffffffff
9892 17:43:35.488902 INFO: [APUAPC] D1_APC_2: 0x3fffff
9893 17:43:35.492430 INFO: [APUAPC] D1_APC_3: 0x0
9894 17:43:35.495999 INFO: [APUAPC] D2_APC_0: 0xffffffff
9895 17:43:35.498915 INFO: [APUAPC] D2_APC_1: 0xffffffff
9896 17:43:35.502363 INFO: [APUAPC] D2_APC_2: 0x3fffff
9897 17:43:35.505773 INFO: [APUAPC] D2_APC_3: 0x0
9898 17:43:35.508738 INFO: [APUAPC] D3_APC_0: 0xffffffff
9899 17:43:35.512314 INFO: [APUAPC] D3_APC_1: 0xffffffff
9900 17:43:35.515878 INFO: [APUAPC] D3_APC_2: 0x3fffff
9901 17:43:35.515973 INFO: [APUAPC] D3_APC_3: 0x0
9902 17:43:35.519108 INFO: [APUAPC] D4_APC_0: 0xffffffff
9903 17:43:35.525624 INFO: [APUAPC] D4_APC_1: 0xffffffff
9904 17:43:35.529021 INFO: [APUAPC] D4_APC_2: 0x3fffff
9905 17:43:35.529117 INFO: [APUAPC] D4_APC_3: 0x0
9906 17:43:35.532309 INFO: [APUAPC] D5_APC_0: 0xffffffff
9907 17:43:35.535690 INFO: [APUAPC] D5_APC_1: 0xffffffff
9908 17:43:35.539113 INFO: [APUAPC] D5_APC_2: 0x3fffff
9909 17:43:35.542517 INFO: [APUAPC] D5_APC_3: 0x0
9910 17:43:35.545886 INFO: [APUAPC] D6_APC_0: 0xffffffff
9911 17:43:35.548557 INFO: [APUAPC] D6_APC_1: 0xffffffff
9912 17:43:35.551970 INFO: [APUAPC] D6_APC_2: 0x3fffff
9913 17:43:35.555938 INFO: [APUAPC] D6_APC_3: 0x0
9914 17:43:35.558602 INFO: [APUAPC] D7_APC_0: 0xffffffff
9915 17:43:35.561999 INFO: [APUAPC] D7_APC_1: 0xffffffff
9916 17:43:35.565297 INFO: [APUAPC] D7_APC_2: 0x3fffff
9917 17:43:35.568628 INFO: [APUAPC] D7_APC_3: 0x0
9918 17:43:35.571983 INFO: [APUAPC] D8_APC_0: 0xffffffff
9919 17:43:35.575254 INFO: [APUAPC] D8_APC_1: 0xffffffff
9920 17:43:35.578482 INFO: [APUAPC] D8_APC_2: 0x3fffff
9921 17:43:35.582215 INFO: [APUAPC] D8_APC_3: 0x0
9922 17:43:35.585354 INFO: [APUAPC] D9_APC_0: 0xffffffff
9923 17:43:35.588660 INFO: [APUAPC] D9_APC_1: 0xffffffff
9924 17:43:35.592402 INFO: [APUAPC] D9_APC_2: 0x3fffff
9925 17:43:35.595756 INFO: [APUAPC] D9_APC_3: 0x0
9926 17:43:35.598966 INFO: [APUAPC] D10_APC_0: 0xffffffff
9927 17:43:35.602300 INFO: [APUAPC] D10_APC_1: 0xffffffff
9928 17:43:35.605649 INFO: [APUAPC] D10_APC_2: 0x3fffff
9929 17:43:35.608901 INFO: [APUAPC] D10_APC_3: 0x0
9930 17:43:35.612015 INFO: [APUAPC] D11_APC_0: 0xffffffff
9931 17:43:35.615554 INFO: [APUAPC] D11_APC_1: 0xffffffff
9932 17:43:35.618997 INFO: [APUAPC] D11_APC_2: 0x3fffff
9933 17:43:35.621967 INFO: [APUAPC] D11_APC_3: 0x0
9934 17:43:35.625589 INFO: [APUAPC] D12_APC_0: 0xffffffff
9935 17:43:35.628623 INFO: [APUAPC] D12_APC_1: 0xffffffff
9936 17:43:35.632228 INFO: [APUAPC] D12_APC_2: 0x3fffff
9937 17:43:35.635396 INFO: [APUAPC] D12_APC_3: 0x0
9938 17:43:35.638712 INFO: [APUAPC] D13_APC_0: 0xffffffff
9939 17:43:35.642113 INFO: [APUAPC] D13_APC_1: 0xffffffff
9940 17:43:35.645448 INFO: [APUAPC] D13_APC_2: 0x3fffff
9941 17:43:35.648694 INFO: [APUAPC] D13_APC_3: 0x0
9942 17:43:35.652100 INFO: [APUAPC] D14_APC_0: 0xffffffff
9943 17:43:35.655572 INFO: [APUAPC] D14_APC_1: 0xffffffff
9944 17:43:35.658660 INFO: [APUAPC] D14_APC_2: 0x3fffff
9945 17:43:35.662037 INFO: [APUAPC] D14_APC_3: 0x0
9946 17:43:35.665319 INFO: [APUAPC] D15_APC_0: 0xffffffff
9947 17:43:35.668755 INFO: [APUAPC] D15_APC_1: 0xffffffff
9948 17:43:35.672188 INFO: [APUAPC] D15_APC_2: 0x3fffff
9949 17:43:35.675477 INFO: [APUAPC] D15_APC_3: 0x0
9950 17:43:35.678689 INFO: [APUAPC] APC_CON: 0x4
9951 17:43:35.681411 INFO: [NOCDAPC] D0_APC_0: 0x0
9952 17:43:35.685362 INFO: [NOCDAPC] D0_APC_1: 0x0
9953 17:43:35.688764 INFO: [NOCDAPC] D1_APC_0: 0x0
9954 17:43:35.688854 INFO: [NOCDAPC] D1_APC_1: 0xfff
9955 17:43:35.691468 INFO: [NOCDAPC] D2_APC_0: 0x0
9956 17:43:35.695190 INFO: [NOCDAPC] D2_APC_1: 0xfff
9957 17:43:35.713771 INFO: [NOCDAPC] D3_APC_0: 0x0
9958 17:43:35.713960 INFO: [NOCDAPC] D3_APC_1: 0xfff
9959 17:43:35.714069 INFO: [NOCDAPC] D4_APC_0: 0x0
9960 17:43:35.714171 INFO: [NOCDAPC] D4_APC_1: 0xfff
9961 17:43:35.714276 INFO: [NOCDAPC] D5_APC_0: 0x0
9962 17:43:35.715280 INFO: [NOCDAPC] D5_APC_1: 0xfff
9963 17:43:35.718345 INFO: [NOCDAPC] D6_APC_0: 0x0
9964 17:43:35.721359 INFO: [NOCDAPC] D6_APC_1: 0xfff
9965 17:43:35.721477 INFO: [NOCDAPC] D7_APC_0: 0x0
9966 17:43:35.724577 INFO: [NOCDAPC] D7_APC_1: 0xfff
9967 17:43:35.728424 INFO: [NOCDAPC] D8_APC_0: 0x0
9968 17:43:35.731521 INFO: [NOCDAPC] D8_APC_1: 0xfff
9969 17:43:35.734612 INFO: [NOCDAPC] D9_APC_0: 0x0
9970 17:43:35.738401 INFO: [NOCDAPC] D9_APC_1: 0xfff
9971 17:43:35.741613 INFO: [NOCDAPC] D10_APC_0: 0x0
9972 17:43:35.744614 INFO: [NOCDAPC] D10_APC_1: 0xfff
9973 17:43:35.748081 INFO: [NOCDAPC] D11_APC_0: 0x0
9974 17:43:35.751367 INFO: [NOCDAPC] D11_APC_1: 0xfff
9975 17:43:35.754574 INFO: [NOCDAPC] D12_APC_0: 0x0
9976 17:43:35.758018 INFO: [NOCDAPC] D12_APC_1: 0xfff
9977 17:43:35.761343 INFO: [NOCDAPC] D13_APC_0: 0x0
9978 17:43:35.761449 INFO: [NOCDAPC] D13_APC_1: 0xfff
9979 17:43:35.764559 INFO: [NOCDAPC] D14_APC_0: 0x0
9980 17:43:35.767932 INFO: [NOCDAPC] D14_APC_1: 0xfff
9981 17:43:35.771191 INFO: [NOCDAPC] D15_APC_0: 0x0
9982 17:43:35.774394 INFO: [NOCDAPC] D15_APC_1: 0xfff
9983 17:43:35.777808 INFO: [NOCDAPC] APC_CON: 0x4
9984 17:43:35.781236 INFO: [APUAPC] set_apusys_apc done
9985 17:43:35.784585 INFO: [DEVAPC] devapc_init done
9986 17:43:35.788013 INFO: GICv3 without legacy support detected.
9987 17:43:35.794472 INFO: ARM GICv3 driver initialized in EL3
9988 17:43:35.797862 INFO: Maximum SPI INTID supported: 639
9989 17:43:35.801293 INFO: BL31: Initializing runtime services
9990 17:43:35.807952 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9991 17:43:35.808056 INFO: SPM: enable CPC mode
9992 17:43:35.814472 INFO: mcdi ready for mcusys-off-idle and system suspend
9993 17:43:35.820559 INFO: BL31: Preparing for EL3 exit to normal world
9994 17:43:35.824243 INFO: Entry point address = 0x80000000
9995 17:43:35.824338 INFO: SPSR = 0x8
9996 17:43:35.830371
9997 17:43:35.830470
9998 17:43:35.830541
9999 17:43:35.833850 Starting depthcharge on Spherion...
10000 17:43:35.833937
10001 17:43:35.834003 Wipe memory regions:
10002 17:43:35.834066
10003 17:43:35.834723 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10004 17:43:35.834826 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10005 17:43:35.834923 Setting prompt string to ['asurada:']
10006 17:43:35.835006 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10007 17:43:35.837132 [0x00000040000000, 0x00000054600000)
10008 17:43:35.959176
10009 17:43:35.959328 [0x00000054660000, 0x00000080000000)
10010 17:43:36.219543
10011 17:43:36.219754 [0x000000821a7280, 0x000000ffe64000)
10012 17:43:36.963572
10013 17:43:36.963782 [0x00000100000000, 0x00000240000000)
10014 17:43:38.852525
10015 17:43:38.856022 Initializing XHCI USB controller at 0x11200000.
10016 17:43:39.894583
10017 17:43:39.897705 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10018 17:43:39.897805
10019 17:43:39.897883
10020 17:43:39.897949
10021 17:43:39.898234 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 17:43:39.998636 asurada: tftpboot 192.168.201.1 11518285/tftp-deploy-09441uta/kernel/image.itb 11518285/tftp-deploy-09441uta/kernel/cmdline
10024 17:43:39.998793 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 17:43:39.998882 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10026 17:43:40.002652 tftpboot 192.168.201.1 11518285/tftp-deploy-09441uta/kernel/image.ittp-deploy-09441uta/kernel/cmdline
10027 17:43:40.002763
10028 17:43:40.002858 Waiting for link
10029 17:43:40.161193
10030 17:43:40.161321 R8152: Initializing
10031 17:43:40.161411
10032 17:43:40.164686 Version 9 (ocp_data = 6010)
10033 17:43:40.164763
10034 17:43:40.167372 R8152: Done initializing
10035 17:43:40.167473
10036 17:43:40.167565 Adding net device
10037 17:43:42.115689
10038 17:43:42.115986 done.
10039 17:43:42.116129
10040 17:43:42.116253 MAC: 00:e0:4c:78:7a:aa
10041 17:43:42.116373
10042 17:43:42.119815 Sending DHCP discover... done.
10043 17:43:42.120057
10044 17:43:42.123508 Waiting for reply... done.
10045 17:43:42.123725
10046 17:43:42.125771 Sending DHCP request... done.
10047 17:43:42.125991
10048 17:43:42.131198 Waiting for reply... done.
10049 17:43:42.131466
10050 17:43:42.131791 My ip is 192.168.201.12
10051 17:43:42.132051
10052 17:43:42.134796 The DHCP server ip is 192.168.201.1
10053 17:43:42.135135
10054 17:43:42.141202 TFTP server IP predefined by user: 192.168.201.1
10055 17:43:42.141291
10056 17:43:42.147316 Bootfile predefined by user: 11518285/tftp-deploy-09441uta/kernel/image.itb
10057 17:43:42.147404
10058 17:43:42.147492 Sending tftp read request... done.
10059 17:43:42.150603
10060 17:43:42.153960 Waiting for the transfer...
10061 17:43:42.154083
10062 17:43:42.407230 00000000 ################################################################
10063 17:43:42.407363
10064 17:43:42.653952 00080000 ################################################################
10065 17:43:42.654115
10066 17:43:42.902072 00100000 ################################################################
10067 17:43:42.902225
10068 17:43:43.149416 00180000 ################################################################
10069 17:43:43.149569
10070 17:43:43.399474 00200000 ################################################################
10071 17:43:43.399609
10072 17:43:43.647319 00280000 ################################################################
10073 17:43:43.647459
10074 17:43:43.895648 00300000 ################################################################
10075 17:43:43.895793
10076 17:43:44.144569 00380000 ################################################################
10077 17:43:44.144850
10078 17:43:44.421220 00400000 ################################################################
10079 17:43:44.421386
10080 17:43:44.672201 00480000 ################################################################
10081 17:43:44.672345
10082 17:43:44.933243 00500000 ################################################################
10083 17:43:44.933375
10084 17:43:45.184658 00580000 ################################################################
10085 17:43:45.184825
10086 17:43:45.436799 00600000 ################################################################
10087 17:43:45.436959
10088 17:43:45.688721 00680000 ################################################################
10089 17:43:45.688861
10090 17:43:45.946552 00700000 ################################################################
10091 17:43:45.946720
10092 17:43:46.198615 00780000 ################################################################
10093 17:43:46.198746
10094 17:43:46.465215 00800000 ################################################################
10095 17:43:46.465353
10096 17:43:46.717997 00880000 ################################################################
10097 17:43:46.718133
10098 17:43:46.981035 00900000 ################################################################
10099 17:43:46.981173
10100 17:43:47.233497 00980000 ################################################################
10101 17:43:47.233638
10102 17:43:47.489578 00a00000 ################################################################
10103 17:43:47.489714
10104 17:43:47.804790 00a80000 ################################################################
10105 17:43:47.804936
10106 17:43:48.082477 00b00000 ################################################################
10107 17:43:48.082616
10108 17:43:48.330632 00b80000 ################################################################
10109 17:43:48.330764
10110 17:43:48.576051 00c00000 ################################################################
10111 17:43:48.576183
10112 17:43:48.821796 00c80000 ################################################################
10113 17:43:48.821959
10114 17:43:49.069593 00d00000 ################################################################
10115 17:43:49.069736
10116 17:43:49.330291 00d80000 ################################################################
10117 17:43:49.330425
10118 17:43:49.596569 00e00000 ################################################################
10119 17:43:49.596701
10120 17:43:49.844039 00e80000 ################################################################
10121 17:43:49.844215
10122 17:43:50.088243 00f00000 ################################################################
10123 17:43:50.088399
10124 17:43:50.333974 00f80000 ################################################################
10125 17:43:50.334137
10126 17:43:50.593778 01000000 ################################################################
10127 17:43:50.593946
10128 17:43:50.846288 01080000 ################################################################
10129 17:43:50.846468
10130 17:43:51.092701 01100000 ################################################################
10131 17:43:51.092879
10132 17:43:51.344133 01180000 ################################################################
10133 17:43:51.344320
10134 17:43:51.609729 01200000 ################################################################
10135 17:43:51.609893
10136 17:43:51.913546 01280000 ################################################################
10137 17:43:51.913710
10138 17:43:52.155315 01300000 ################################################################
10139 17:43:52.155483
10140 17:43:52.400196 01380000 ################################################################
10141 17:43:52.400352
10142 17:43:52.659389 01400000 ################################################################
10143 17:43:52.659561
10144 17:43:52.901169 01480000 ################################################################
10145 17:43:52.901308
10146 17:43:53.142983 01500000 ################################################################
10147 17:43:53.143120
10148 17:43:53.383274 01580000 ################################################################
10149 17:43:53.383414
10150 17:43:53.625710 01600000 ################################################################
10151 17:43:53.625843
10152 17:43:53.879856 01680000 ################################################################
10153 17:43:53.880052
10154 17:43:54.185165 01700000 ################################################################
10155 17:43:54.185331
10156 17:43:54.458739 01780000 ################################################################
10157 17:43:54.458905
10158 17:43:54.698903 01800000 ################################################################
10159 17:43:54.699062
10160 17:43:54.934755 01880000 ################################################################
10161 17:43:54.934902
10162 17:43:55.185743 01900000 ################################################################
10163 17:43:55.185910
10164 17:43:55.437014 01980000 ################################################################
10165 17:43:55.437170
10166 17:43:55.686082 01a00000 ################################################################
10167 17:43:55.686265
10168 17:43:55.973225 01a80000 ################################################################
10169 17:43:55.973402
10170 17:43:56.213761 01b00000 ################################################################
10171 17:43:56.213899
10172 17:43:56.450451 01b80000 ################################################################
10173 17:43:56.450625
10174 17:43:56.694586 01c00000 ################################################################
10175 17:43:56.694753
10176 17:43:56.942894 01c80000 ################################################################
10177 17:43:56.943059
10178 17:43:57.203511 01d00000 ################################################################
10179 17:43:57.203687
10180 17:43:57.452703 01d80000 ################################################################
10181 17:43:57.452866
10182 17:43:57.704142 01e00000 ################################################################
10183 17:43:57.704283
10184 17:43:58.007923 01e80000 ################################################################
10185 17:43:58.008112
10186 17:43:58.267964 01f00000 ################################################################
10187 17:43:58.268127
10188 17:43:58.523103 01f80000 ################################################################
10189 17:43:58.523268
10190 17:43:58.775080 02000000 ################################################################
10191 17:43:58.775240
10192 17:43:59.039009 02080000 ################################################################
10193 17:43:59.039164
10194 17:43:59.282044 02100000 ################################################################
10195 17:43:59.282209
10196 17:43:59.521444 02180000 ################################################################
10197 17:43:59.521611
10198 17:43:59.771068 02200000 ################################################################
10199 17:43:59.771224
10200 17:44:00.039054 02280000 ################################################################
10201 17:44:00.039191
10202 17:44:00.313370 02300000 ################################################################
10203 17:44:00.313508
10204 17:44:00.572420 02380000 ################################################################
10205 17:44:00.572578
10206 17:44:00.816661 02400000 ################################################################
10207 17:44:00.816807
10208 17:44:01.062805 02480000 ################################################################
10209 17:44:01.062938
10210 17:44:01.335236 02500000 ################################################################
10211 17:44:01.335432
10212 17:44:01.595148 02580000 ################################################################
10213 17:44:01.595305
10214 17:44:01.835767 02600000 ################################################################
10215 17:44:01.835956
10216 17:44:02.073557 02680000 ################################################################
10217 17:44:02.073715
10218 17:44:02.309563 02700000 ################################################################
10219 17:44:02.309727
10220 17:44:02.546170 02780000 ################################################################
10221 17:44:02.546380
10222 17:44:02.783940 02800000 ################################################################
10223 17:44:02.784077
10224 17:44:03.027728 02880000 ################################################################
10225 17:44:03.027863
10226 17:44:03.265844 02900000 ################################################################
10227 17:44:03.265980
10228 17:44:03.528253 02980000 ################################################################
10229 17:44:03.528383
10230 17:44:03.777358 02a00000 ################################################################
10231 17:44:03.777520
10232 17:44:04.029637 02a80000 ################################################################
10233 17:44:04.029803
10234 17:44:04.286433 02b00000 ################################################################
10235 17:44:04.286605
10236 17:44:04.550472 02b80000 ################################################################
10237 17:44:04.550642
10238 17:44:04.805063 02c00000 ################################################################
10239 17:44:04.805228
10240 17:44:05.099293 02c80000 ################################################################
10241 17:44:05.099463
10242 17:44:05.421484 02d00000 ################################################################
10243 17:44:05.421622
10244 17:44:05.756479 02d80000 ################################################################
10245 17:44:05.756630
10246 17:44:06.049037 02e00000 ################################################################
10247 17:44:06.049174
10248 17:44:06.317745 02e80000 ################################################################
10249 17:44:06.317924
10250 17:44:06.582127 02f00000 ################################################################
10251 17:44:06.582294
10252 17:44:06.840823 02f80000 ################################################################
10253 17:44:06.840975
10254 17:44:06.890882 03000000 ############# done.
10255 17:44:06.891008
10256 17:44:06.894126 The bootfile was 50436686 bytes long.
10257 17:44:06.894222
10258 17:44:06.897495 Sending tftp read request... done.
10259 17:44:06.897627
10260 17:44:06.897698 Waiting for the transfer...
10261 17:44:06.897803
10262 17:44:06.900567 00000000 # done.
10263 17:44:06.900644
10264 17:44:06.907252 Command line loaded dynamically from TFTP file: 11518285/tftp-deploy-09441uta/kernel/cmdline
10265 17:44:06.907336
10266 17:44:06.920730 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10267 17:44:06.920819
10268 17:44:06.924075 Loading FIT.
10269 17:44:06.924156
10270 17:44:06.927417 Image ramdisk-1 has 39348124 bytes.
10271 17:44:06.927499
10272 17:44:06.927564 Image fdt-1 has 47278 bytes.
10273 17:44:06.927625
10274 17:44:06.930711 Image kernel-1 has 11039249 bytes.
10275 17:44:06.930793
10276 17:44:06.940527 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10277 17:44:06.940610
10278 17:44:06.957164 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10279 17:44:06.957252
10280 17:44:06.963610 Choosing best match conf-1 for compat google,spherion-rev2.
10281 17:44:06.967864
10282 17:44:06.972487 Connected to device vid:did:rid of 1ae0:0028:00
10283 17:44:06.979080
10284 17:44:06.982246 tpm_get_response: command 0x17b, return code 0x0
10285 17:44:06.982334
10286 17:44:06.985640 ec_init: CrosEC protocol v3 supported (256, 248)
10287 17:44:06.989831
10288 17:44:06.993184 tpm_cleanup: add release locality here.
10289 17:44:06.993268
10290 17:44:06.993333 Shutting down all USB controllers.
10291 17:44:06.996614
10292 17:44:06.996702 Removing current net device
10293 17:44:06.996786
10294 17:44:07.003050 Exiting depthcharge with code 4 at timestamp: 60508953
10295 17:44:07.003132
10296 17:44:07.006110 LZMA decompressing kernel-1 to 0x821a6718
10297 17:44:07.006193
10298 17:44:07.009797 LZMA decompressing kernel-1 to 0x40000000
10299 17:44:08.400084
10300 17:44:08.400536 jumping to kernel
10301 17:44:08.401912 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10302 17:44:08.402256 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10303 17:44:08.402548 Setting prompt string to ['Linux version [0-9]']
10304 17:44:08.402818 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10305 17:44:08.403088 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10306 17:44:08.481969
10307 17:44:08.485646 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10308 17:44:08.489124 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10309 17:44:08.489243 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10310 17:44:08.489343 Setting prompt string to []
10311 17:44:08.489452 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10312 17:44:08.489560 Using line separator: #'\n'#
10313 17:44:08.489650 No login prompt set.
10314 17:44:08.489748 Parsing kernel messages
10315 17:44:08.489839 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10316 17:44:08.490012 [login-action] Waiting for messages, (timeout 00:03:53)
10317 17:44:08.508872 [ 0.000000] Linux version 6.1.52-cip5 (KernelCI@build-j44859-arm64-gcc-10-defconfig-arm64-chromebook-gptb4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023
10318 17:44:08.512243 [ 0.000000] random: crng init done
10319 17:44:08.515283 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10320 17:44:08.518408 [ 0.000000] efi: UEFI not found.
10321 17:44:08.528451 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10322 17:44:08.535411 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10323 17:44:08.545404 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10324 17:44:08.555271 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10325 17:44:08.561646 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10326 17:44:08.565405 [ 0.000000] printk: bootconsole [mtk8250] enabled
10327 17:44:08.573817 [ 0.000000] NUMA: No NUMA configuration found
10328 17:44:08.580667 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10329 17:44:08.587136 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10330 17:44:08.587246 [ 0.000000] Zone ranges:
10331 17:44:08.593767 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10332 17:44:08.596666 [ 0.000000] DMA32 empty
10333 17:44:08.603731 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10334 17:44:08.606998 [ 0.000000] Movable zone start for each node
10335 17:44:08.610254 [ 0.000000] Early memory node ranges
10336 17:44:08.617061 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10337 17:44:08.623770 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10338 17:44:08.630450 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10339 17:44:08.636503 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10340 17:44:08.643553 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10341 17:44:08.650320 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10342 17:44:08.706345 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10343 17:44:08.712986 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10344 17:44:08.719465 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10345 17:44:08.722903 [ 0.000000] psci: probing for conduit method from DT.
10346 17:44:08.729678 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10347 17:44:08.732794 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10348 17:44:08.739376 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10349 17:44:08.742954 [ 0.000000] psci: SMC Calling Convention v1.2
10350 17:44:08.749447 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10351 17:44:08.752723 [ 0.000000] Detected VIPT I-cache on CPU0
10352 17:44:08.759772 [ 0.000000] CPU features: detected: GIC system register CPU interface
10353 17:44:08.766085 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10354 17:44:08.772739 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10355 17:44:08.779514 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10356 17:44:08.786237 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10357 17:44:08.792902 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10358 17:44:08.799942 [ 0.000000] alternatives: applying boot alternatives
10359 17:44:08.803188 [ 0.000000] Fallback order for Node 0: 0
10360 17:44:08.809803 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10361 17:44:08.812964 [ 0.000000] Policy zone: Normal
10362 17:44:08.829988 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10363 17:44:08.839999 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10364 17:44:08.851184 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10365 17:44:08.861155 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10366 17:44:08.867531 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10367 17:44:08.870780 <6>[ 0.000000] software IO TLB: area num 8.
10368 17:44:08.927364 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10369 17:44:09.076181 <6>[ 0.000000] Memory: 7931056K/8385536K available (17984K kernel code, 4098K rwdata, 17468K rodata, 8384K init, 616K bss, 421712K reserved, 32768K cma-reserved)
10370 17:44:09.083032 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10371 17:44:09.089663 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10372 17:44:09.092790 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10373 17:44:09.099336 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10374 17:44:09.106327 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10375 17:44:09.109540 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10376 17:44:09.119519 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10377 17:44:09.126167 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10378 17:44:09.129561 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10379 17:44:09.137200 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10380 17:44:09.140588 <6>[ 0.000000] GICv3: 608 SPIs implemented
10381 17:44:09.147693 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10382 17:44:09.150859 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10383 17:44:09.154285 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10384 17:44:09.160507 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10385 17:44:09.174243 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10386 17:44:09.187375 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10387 17:44:09.193748 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10388 17:44:09.202734 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10389 17:44:09.215763 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10390 17:44:09.222240 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10391 17:44:09.228968 <6>[ 0.009233] Console: colour dummy device 80x25
10392 17:44:09.238941 <6>[ 0.013961] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10393 17:44:09.242648 <6>[ 0.024403] pid_max: default: 32768 minimum: 301
10394 17:44:09.249152 <6>[ 0.029304] LSM: Security Framework initializing
10395 17:44:09.255794 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 17:44:09.265484 <6>[ 0.042018] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10397 17:44:09.272186 <6>[ 0.051390] cblist_init_generic: Setting adjustable number of callback queues.
10398 17:44:09.278943 <6>[ 0.058834] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 17:44:09.285900 <6>[ 0.065172] cblist_init_generic: Setting adjustable number of callback queues.
10400 17:44:09.292228 <6>[ 0.072599] cblist_init_generic: Setting shift to 3 and lim to 1.
10401 17:44:09.299055 <6>[ 0.079037] rcu: Hierarchical SRCU implementation.
10402 17:44:09.305543 <6>[ 0.084052] rcu: Max phase no-delay instances is 1000.
10403 17:44:09.308667 <6>[ 0.091108] EFI services will not be available.
10404 17:44:09.315845 <6>[ 0.096064] smp: Bringing up secondary CPUs ...
10405 17:44:09.323095 <6>[ 0.101118] Detected VIPT I-cache on CPU1
10406 17:44:09.329400 <6>[ 0.101188] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10407 17:44:09.336072 <6>[ 0.101211] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10408 17:44:09.339378 <6>[ 0.101523] Detected VIPT I-cache on CPU2
10409 17:44:09.346432 <6>[ 0.101570] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10410 17:44:09.353038 <6>[ 0.101586] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10411 17:44:09.359568 <6>[ 0.101846] Detected VIPT I-cache on CPU3
10412 17:44:09.366388 <6>[ 0.101894] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10413 17:44:09.373020 <6>[ 0.101908] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10414 17:44:09.376252 <6>[ 0.102215] CPU features: detected: Spectre-v4
10415 17:44:09.383061 <6>[ 0.102221] CPU features: detected: Spectre-BHB
10416 17:44:09.386744 <6>[ 0.102225] Detected PIPT I-cache on CPU4
10417 17:44:09.393395 <6>[ 0.102282] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10418 17:44:09.399843 <6>[ 0.102300] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10419 17:44:09.403204 <6>[ 0.102597] Detected PIPT I-cache on CPU5
10420 17:44:09.413290 <6>[ 0.102659] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10421 17:44:09.419673 <6>[ 0.102675] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10422 17:44:09.423397 <6>[ 0.102957] Detected PIPT I-cache on CPU6
10423 17:44:09.430156 <6>[ 0.103021] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10424 17:44:09.436713 <6>[ 0.103037] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10425 17:44:09.439935 <6>[ 0.103334] Detected PIPT I-cache on CPU7
10426 17:44:09.461152 <6>[ 0.103398] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10427 17:44:09.461540 <6>[ 0.103415] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10428 17:44:09.461813 <6>[ 0.103464] smp: Brought up 1 node, 8 CPUs
10429 17:44:09.463298 <6>[ 0.244831] SMP: Total of 8 processors activated.
10430 17:44:09.470075 <6>[ 0.249783] CPU features: detected: 32-bit EL0 Support
10431 17:44:09.480132 <6>[ 0.255146] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10432 17:44:09.486246 <6>[ 0.264000] CPU features: detected: Common not Private translations
10433 17:44:09.489680 <6>[ 0.270476] CPU features: detected: CRC32 instructions
10434 17:44:09.496817 <6>[ 0.275827] CPU features: detected: RCpc load-acquire (LDAPR)
10435 17:44:09.503369 <6>[ 0.281788] CPU features: detected: LSE atomic instructions
10436 17:44:09.510102 <6>[ 0.287569] CPU features: detected: Privileged Access Never
10437 17:44:09.513363 <6>[ 0.293349] CPU features: detected: RAS Extension Support
10438 17:44:09.520132 <6>[ 0.298957] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10439 17:44:09.526594 <6>[ 0.306178] CPU: All CPU(s) started at EL2
10440 17:44:09.529845 <6>[ 0.310495] alternatives: applying system-wide alternatives
10441 17:44:09.540810 <6>[ 0.321168] devtmpfs: initialized
10442 17:44:09.552994 <6>[ 0.330002] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10443 17:44:09.562555 <6>[ 0.339961] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10444 17:44:09.569432 <6>[ 0.347973] pinctrl core: initialized pinctrl subsystem
10445 17:44:09.572921 <6>[ 0.354635] DMI not present or invalid.
10446 17:44:09.579614 <6>[ 0.359046] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10447 17:44:09.589607 <6>[ 0.365896] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10448 17:44:09.596015 <6>[ 0.373480] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10449 17:44:09.606206 <6>[ 0.381691] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10450 17:44:09.610067 <6>[ 0.389935] audit: initializing netlink subsys (disabled)
10451 17:44:09.619438 <5>[ 0.395628] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10452 17:44:09.626336 <6>[ 0.396334] thermal_sys: Registered thermal governor 'step_wise'
10453 17:44:09.632904 <6>[ 0.403594] thermal_sys: Registered thermal governor 'power_allocator'
10454 17:44:09.636647 <6>[ 0.409849] cpuidle: using governor menu
10455 17:44:09.639951 <6>[ 0.420809] NET: Registered PF_QIPCRTR protocol family
10456 17:44:09.649679 <6>[ 0.426295] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10457 17:44:09.652838 <6>[ 0.433401] ASID allocator initialised with 32768 entries
10458 17:44:09.659525 <6>[ 0.439971] Serial: AMBA PL011 UART driver
10459 17:44:09.668785 <4>[ 0.448733] Trying to register duplicate clock ID: 134
10460 17:44:09.722340 <6>[ 0.505938] KASLR enabled
10461 17:44:09.736727 <6>[ 0.513623] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10462 17:44:09.743076 <6>[ 0.520636] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10463 17:44:09.749937 <6>[ 0.527125] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10464 17:44:09.756530 <6>[ 0.534129] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10465 17:44:09.763376 <6>[ 0.540616] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10466 17:44:09.769825 <6>[ 0.547620] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10467 17:44:09.776247 <6>[ 0.554106] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10468 17:44:09.783566 <6>[ 0.561108] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10469 17:44:09.786278 <6>[ 0.568556] ACPI: Interpreter disabled.
10470 17:44:09.795040 <6>[ 0.574998] iommu: Default domain type: Translated
10471 17:44:09.801109 <6>[ 0.580110] iommu: DMA domain TLB invalidation policy: strict mode
10472 17:44:09.805051 <5>[ 0.586765] SCSI subsystem initialized
10473 17:44:09.811585 <6>[ 0.591012] usbcore: registered new interface driver usbfs
10474 17:44:09.817944 <6>[ 0.596739] usbcore: registered new interface driver hub
10475 17:44:09.820963 <6>[ 0.602293] usbcore: registered new device driver usb
10476 17:44:09.827915 <6>[ 0.608407] pps_core: LinuxPPS API ver. 1 registered
10477 17:44:09.837968 <6>[ 0.613602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10478 17:44:09.841148 <6>[ 0.622946] PTP clock support registered
10479 17:44:09.844267 <6>[ 0.627187] EDAC MC: Ver: 3.0.0
10480 17:44:09.851942 <6>[ 0.632371] FPGA manager framework
10481 17:44:09.855539 <6>[ 0.636045] Advanced Linux Sound Architecture Driver Initialized.
10482 17:44:09.859523 <6>[ 0.642803] vgaarb: loaded
10483 17:44:09.865352 <6>[ 0.645972] clocksource: Switched to clocksource arch_sys_counter
10484 17:44:09.872058 <5>[ 0.652414] VFS: Disk quotas dquot_6.6.0
10485 17:44:09.878734 <6>[ 0.656602] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10486 17:44:09.881742 <6>[ 0.663791] pnp: PnP ACPI: disabled
10487 17:44:09.889864 <6>[ 0.670458] NET: Registered PF_INET protocol family
10488 17:44:09.899697 <6>[ 0.676044] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10489 17:44:09.911271 <6>[ 0.688265] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10490 17:44:09.920927 <6>[ 0.697078] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10491 17:44:09.928278 <6>[ 0.705046] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10492 17:44:09.934895 <6>[ 0.713742] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10493 17:44:09.946898 <6>[ 0.723461] TCP: Hash tables configured (established 65536 bind 65536)
10494 17:44:09.953351 <6>[ 0.730321] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10495 17:44:09.959965 <6>[ 0.737520] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10496 17:44:09.966698 <6>[ 0.745218] NET: Registered PF_UNIX/PF_LOCAL protocol family
10497 17:44:09.972985 <6>[ 0.751387] RPC: Registered named UNIX socket transport module.
10498 17:44:09.976603 <6>[ 0.757539] RPC: Registered udp transport module.
10499 17:44:09.983135 <6>[ 0.762470] RPC: Registered tcp transport module.
10500 17:44:09.989683 <6>[ 0.767400] RPC: Registered tcp NFSv4.1 backchannel transport module.
10501 17:44:09.992977 <6>[ 0.774068] PCI: CLS 0 bytes, default 64
10502 17:44:09.996207 <6>[ 0.778463] Unpacking initramfs...
10503 17:44:10.020776 <6>[ 0.798082] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10504 17:44:10.031217 <6>[ 0.806734] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10505 17:44:10.034444 <6>[ 0.815579] kvm [1]: IPA Size Limit: 40 bits
10506 17:44:10.040842 <6>[ 0.820107] kvm [1]: GICv3: no GICV resource entry
10507 17:44:10.044068 <6>[ 0.825129] kvm [1]: disabling GICv2 emulation
10508 17:44:10.050863 <6>[ 0.829815] kvm [1]: GIC system register CPU interface enabled
10509 17:44:10.054077 <6>[ 0.835980] kvm [1]: vgic interrupt IRQ18
10510 17:44:10.060836 <6>[ 0.840335] kvm [1]: VHE mode initialized successfully
10511 17:44:10.067212 <5>[ 0.846799] Initialise system trusted keyrings
10512 17:44:10.073726 <6>[ 0.851600] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10513 17:44:10.081072 <6>[ 0.861592] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10514 17:44:10.087943 <5>[ 0.868034] NFS: Registering the id_resolver key type
10515 17:44:10.091095 <5>[ 0.873347] Key type id_resolver registered
10516 17:44:10.097626 <5>[ 0.877764] Key type id_legacy registered
10517 17:44:10.104482 <6>[ 0.882046] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10518 17:44:10.111143 <6>[ 0.888970] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10519 17:44:10.117368 <6>[ 0.896710] 9p: Installing v9fs 9p2000 file system support
10520 17:44:10.153502 <5>[ 0.933653] Key type asymmetric registered
10521 17:44:10.156860 <5>[ 0.937985] Asymmetric key parser 'x509' registered
10522 17:44:10.166186 <6>[ 0.943128] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10523 17:44:10.169519 <6>[ 0.950742] io scheduler mq-deadline registered
10524 17:44:10.172874 <6>[ 0.955502] io scheduler kyber registered
10525 17:44:10.191884 <6>[ 0.972454] EINJ: ACPI disabled.
10526 17:44:10.223813 <4>[ 0.997792] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10527 17:44:10.233961 <4>[ 1.008481] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10528 17:44:10.248259 <6>[ 1.029004] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10529 17:44:10.256309 <6>[ 1.036985] printk: console [ttyS0] disabled
10530 17:44:10.284346 <6>[ 1.061648] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10531 17:44:10.291023 <6>[ 1.071121] printk: console [ttyS0] enabled
10532 17:44:10.295047 <6>[ 1.071121] printk: console [ttyS0] enabled
10533 17:44:10.301574 <6>[ 1.080015] printk: bootconsole [mtk8250] disabled
10534 17:44:10.304194 <6>[ 1.080015] printk: bootconsole [mtk8250] disabled
10535 17:44:10.311467 <6>[ 1.091009] SuperH (H)SCI(F) driver initialized
10536 17:44:10.314808 <6>[ 1.096277] msm_serial: driver initialized
10537 17:44:10.327861 <6>[ 1.105161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10538 17:44:10.337957 <6>[ 1.113705] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10539 17:44:10.344696 <6>[ 1.122248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10540 17:44:10.354457 <6>[ 1.130875] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10541 17:44:10.364194 <6>[ 1.139582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10542 17:44:10.370964 <6>[ 1.148294] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10543 17:44:10.381291 <6>[ 1.156834] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10544 17:44:10.387851 <6>[ 1.165632] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10545 17:44:10.397811 <6>[ 1.174174] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10546 17:44:10.409206 <6>[ 1.189609] loop: module loaded
10547 17:44:10.415672 <6>[ 1.195488] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10548 17:44:10.437911 <4>[ 1.218744] mtk-pmic-keys: Failed to locate of_node [id: -1]
10549 17:44:10.444779 <6>[ 1.225497] megasas: 07.719.03.00-rc1
10550 17:44:10.454444 <6>[ 1.235126] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10551 17:44:10.464900 <6>[ 1.245349] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10552 17:44:10.481448 <6>[ 1.261976] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10553 17:44:10.538499 <6>[ 1.312113] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10554 17:44:11.582037 <6>[ 2.362744] Freeing initrd memory: 38424K
10555 17:44:11.592530 <6>[ 2.373241] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10556 17:44:11.603621 <6>[ 2.384197] tun: Universal TUN/TAP device driver, 1.6
10557 17:44:11.606902 <6>[ 2.390271] thunder_xcv, ver 1.0
10558 17:44:11.610231 <6>[ 2.393766] thunder_bgx, ver 1.0
10559 17:44:11.613498 <6>[ 2.397263] nicpf, ver 1.0
10560 17:44:11.624354 <6>[ 2.401298] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10561 17:44:11.627533 <6>[ 2.408774] hns3: Copyright (c) 2017 Huawei Corporation.
10562 17:44:11.630910 <6>[ 2.414361] hclge is initializing
10563 17:44:11.637322 <6>[ 2.417933] e1000: Intel(R) PRO/1000 Network Driver
10564 17:44:11.643778 <6>[ 2.423063] e1000: Copyright (c) 1999-2006 Intel Corporation.
10565 17:44:11.647068 <6>[ 2.429077] e1000e: Intel(R) PRO/1000 Network Driver
10566 17:44:11.653680 <6>[ 2.434292] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10567 17:44:11.660162 <6>[ 2.440477] igb: Intel(R) Gigabit Ethernet Network Driver
10568 17:44:11.667185 <6>[ 2.446127] igb: Copyright (c) 2007-2014 Intel Corporation.
10569 17:44:11.673876 <6>[ 2.451962] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10570 17:44:11.680537 <6>[ 2.458481] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10571 17:44:11.683380 <6>[ 2.464943] sky2: driver version 1.30
10572 17:44:11.690288 <6>[ 2.469944] VFIO - User Level meta-driver version: 0.3
10573 17:44:11.697772 <6>[ 2.478175] usbcore: registered new interface driver usb-storage
10574 17:44:11.704183 <6>[ 2.484616] usbcore: registered new device driver onboard-usb-hub
10575 17:44:11.712799 <6>[ 2.493757] mt6397-rtc mt6359-rtc: registered as rtc0
10576 17:44:11.722780 <6>[ 2.499223] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-13T17:42:44 UTC (1694626964)
10577 17:44:11.726014 <6>[ 2.508784] i2c_dev: i2c /dev entries driver
10578 17:44:11.742882 <6>[ 2.520500] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10579 17:44:11.763608 <6>[ 2.544490] cpu cpu0: EM: created perf domain
10580 17:44:11.766838 <6>[ 2.549421] cpu cpu4: EM: created perf domain
10581 17:44:11.774368 <6>[ 2.555041] sdhci: Secure Digital Host Controller Interface driver
10582 17:44:11.780891 <6>[ 2.561473] sdhci: Copyright(c) Pierre Ossman
10583 17:44:11.787558 <6>[ 2.566424] Synopsys Designware Multimedia Card Interface Driver
10584 17:44:11.794466 <6>[ 2.573053] sdhci-pltfm: SDHCI platform and OF driver helper
10585 17:44:11.797734 <6>[ 2.573083] mmc0: CQHCI version 5.10
10586 17:44:11.804377 <6>[ 2.583234] ledtrig-cpu: registered to indicate activity on CPUs
10587 17:44:11.810943 <6>[ 2.590273] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 17:44:11.817617 <6>[ 2.597324] usbcore: registered new interface driver usbhid
10589 17:44:11.820893 <6>[ 2.603146] usbhid: USB HID core driver
10590 17:44:11.827605 <6>[ 2.607349] spi_master spi0: will run message pump with realtime priority
10591 17:44:11.874182 <6>[ 2.648539] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10592 17:44:11.894249 <6>[ 2.664782] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10593 17:44:11.897712 <6>[ 2.678385] mmc0: Command Queue Engine enabled
10594 17:44:11.904908 <6>[ 2.679854] cros-ec-spi spi0.0: Chrome EC device registered
10595 17:44:11.911270 <6>[ 2.683129] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 17:44:11.914635 <6>[ 2.696285] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 17:44:11.924780 <6>[ 2.702012] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10598 17:44:11.930907 <6>[ 2.706022] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10599 17:44:11.937573 <6>[ 2.712482] NET: Registered PF_PACKET protocol family
10600 17:44:11.941093 <6>[ 2.718346] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 17:44:11.947863 <6>[ 2.722622] 9pnet: Installing 9P2000 support
10602 17:44:11.951243 <6>[ 2.728442] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10603 17:44:11.957724 <5>[ 2.732307] Key type dns_resolver registered
10604 17:44:11.964295 <6>[ 2.738201] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10605 17:44:11.967855 <6>[ 2.742566] registered taskstats version 1
10606 17:44:11.971547 <5>[ 2.752937] Loading compiled-in X.509 certificates
10607 17:44:12.000895 <4>[ 2.774915] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 17:44:12.010676 <4>[ 2.785591] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 17:44:12.017614 <3>[ 2.796118] debugfs: File 'uA_load' in directory '/' already present!
10610 17:44:12.024217 <3>[ 2.802816] debugfs: File 'min_uV' in directory '/' already present!
10611 17:44:12.030768 <3>[ 2.809422] debugfs: File 'max_uV' in directory '/' already present!
10612 17:44:12.037599 <3>[ 2.816086] debugfs: File 'constraint_flags' in directory '/' already present!
10613 17:44:12.048371 <3>[ 2.825773] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10614 17:44:12.059609 <6>[ 2.840250] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10615 17:44:12.066439 <6>[ 2.847035] xhci-mtk 11200000.usb: xHCI Host Controller
10616 17:44:12.072846 <6>[ 2.852534] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10617 17:44:12.083154 <6>[ 2.860391] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10618 17:44:12.089452 <6>[ 2.869855] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10619 17:44:12.096013 <6>[ 2.875930] xhci-mtk 11200000.usb: xHCI Host Controller
10620 17:44:12.102981 <6>[ 2.881411] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10621 17:44:12.109591 <6>[ 2.889059] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10622 17:44:12.116263 <6>[ 2.896861] hub 1-0:1.0: USB hub found
10623 17:44:12.119469 <6>[ 2.900882] hub 1-0:1.0: 1 port detected
10624 17:44:12.129216 <6>[ 2.905176] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10625 17:44:12.132575 <6>[ 2.913802] hub 2-0:1.0: USB hub found
10626 17:44:12.135933 <6>[ 2.917810] hub 2-0:1.0: 1 port detected
10627 17:44:12.145101 <6>[ 2.925910] mtk-msdc 11f70000.mmc: Got CD GPIO
10628 17:44:12.155296 <6>[ 2.932287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10629 17:44:12.161626 <6>[ 2.940326] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10630 17:44:12.171814 <4>[ 2.948263] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10631 17:44:12.181510 <6>[ 2.957794] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10632 17:44:12.188110 <6>[ 2.965870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10633 17:44:12.195111 <6>[ 2.973872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10634 17:44:12.204759 <6>[ 2.981790] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10635 17:44:12.211360 <6>[ 2.989607] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10636 17:44:12.221603 <6>[ 2.997425] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10637 17:44:12.231157 <6>[ 3.007881] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10638 17:44:12.237830 <6>[ 3.016240] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10639 17:44:12.248079 <6>[ 3.024584] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10640 17:44:12.254580 <6>[ 3.032926] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10641 17:44:12.264563 <6>[ 3.041265] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10642 17:44:12.270877 <6>[ 3.049603] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10643 17:44:12.280952 <6>[ 3.057941] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10644 17:44:12.287247 <6>[ 3.066280] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10645 17:44:12.297420 <6>[ 3.074618] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10646 17:44:12.303932 <6>[ 3.082957] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10647 17:44:12.314118 <6>[ 3.091295] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10648 17:44:12.320566 <6>[ 3.099635] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10649 17:44:12.330452 <6>[ 3.107974] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10650 17:44:12.340505 <6>[ 3.116313] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10651 17:44:12.347362 <6>[ 3.124651] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10652 17:44:12.353964 <6>[ 3.133381] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10653 17:44:12.360557 <6>[ 3.140513] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10654 17:44:12.367254 <6>[ 3.147292] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10655 17:44:12.374050 <6>[ 3.154047] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10656 17:44:12.380399 <6>[ 3.160983] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10657 17:44:12.390709 <6>[ 3.167833] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10658 17:44:12.400639 <6>[ 3.176963] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10659 17:44:12.410416 <6>[ 3.186084] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10660 17:44:12.420471 <6>[ 3.195380] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10661 17:44:12.430498 <6>[ 3.204847] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10662 17:44:12.436746 <6>[ 3.214315] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10663 17:44:12.446503 <6>[ 3.223436] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10664 17:44:12.456742 <6>[ 3.232903] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10665 17:44:12.466451 <6>[ 3.242026] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10666 17:44:12.476524 <6>[ 3.251321] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10667 17:44:12.486013 <6>[ 3.261482] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10668 17:44:12.495704 <6>[ 3.273030] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10669 17:44:12.544734 <6>[ 3.322248] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10670 17:44:12.699464 <6>[ 3.480294] hub 1-1:1.0: USB hub found
10671 17:44:12.702747 <6>[ 3.484866] hub 1-1:1.0: 4 ports detected
10672 17:44:12.824828 <6>[ 3.602384] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10673 17:44:12.851430 <6>[ 3.631903] hub 2-1:1.0: USB hub found
10674 17:44:12.854413 <6>[ 3.636434] hub 2-1:1.0: 3 ports detected
10675 17:44:13.024564 <6>[ 3.802292] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10676 17:44:13.157210 <6>[ 3.938111] hub 1-1.4:1.0: USB hub found
10677 17:44:13.161027 <6>[ 3.942682] hub 1-1.4:1.0: 2 ports detected
10678 17:44:13.236799 <6>[ 4.014383] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10679 17:44:13.456380 <6>[ 4.234264] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 17:44:13.648638 <6>[ 4.426258] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 17:44:24.781546 <6>[ 15.567254] ALSA device list:
10682 17:44:24.788437 <6>[ 15.570546] No soundcards found.
10683 17:44:24.796626 <6>[ 15.578510] Freeing unused kernel memory: 8384K
10684 17:44:24.799940 <6>[ 15.583499] Run /init as init process
10685 17:44:24.847492 <6>[ 15.629902] NET: Registered PF_INET6 protocol family
10686 17:44:24.854259 <6>[ 15.636313] Segment Routing with IPv6
10687 17:44:24.857550 <6>[ 15.640262] In-situ OAM (IOAM) with IPv6
10688 17:44:24.888039 <30>[ 15.653702] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10689 17:44:24.895373 <30>[ 15.677478] systemd[1]: Detected architecture arm64.
10690 17:44:24.895490
10691 17:44:24.901734 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10692 17:44:24.901841
10693 17:44:24.916016 <30>[ 15.698343] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10694 17:44:25.058962 <30>[ 15.837712] systemd[1]: Queued start job for default target Graphical Interface.
10695 17:44:25.104807 <30>[ 15.887225] systemd[1]: Created slice system-getty.slice.
10696 17:44:25.111853 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10697 17:44:25.128570 <30>[ 15.910900] systemd[1]: Created slice system-modprobe.slice.
10698 17:44:25.135188 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10699 17:44:25.153678 <30>[ 15.935636] systemd[1]: Created slice system-serial\x2dgetty.slice.
10700 17:44:25.163654 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10701 17:44:25.176762 <30>[ 15.958897] systemd[1]: Created slice User and Session Slice.
10702 17:44:25.183104 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10703 17:44:25.204418 <30>[ 15.983073] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10704 17:44:25.214444 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10705 17:44:25.231558 <30>[ 16.010489] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10706 17:44:25.238091 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10707 17:44:25.258755 <30>[ 16.034319] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10708 17:44:25.265665 <30>[ 16.046451] systemd[1]: Reached target Local Encrypted Volumes.
10709 17:44:25.271724 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10710 17:44:25.288167 <30>[ 16.070386] systemd[1]: Reached target Paths.
10711 17:44:25.291154 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10712 17:44:25.307763 <30>[ 16.090257] systemd[1]: Reached target Remote File Systems.
10713 17:44:25.314411 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10714 17:44:25.332297 <30>[ 16.114640] systemd[1]: Reached target Slices.
10715 17:44:25.338980 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10716 17:44:25.352214 <30>[ 16.134278] systemd[1]: Reached target Swap.
10717 17:44:25.355437 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10718 17:44:25.375835 <30>[ 16.154765] systemd[1]: Listening on initctl Compatibility Named Pipe.
10719 17:44:25.382431 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10720 17:44:25.389150 <30>[ 16.169901] systemd[1]: Listening on Journal Audit Socket.
10721 17:44:25.395601 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10722 17:44:25.408255 <30>[ 16.190713] systemd[1]: Listening on Journal Socket (/dev/log).
10723 17:44:25.415124 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10724 17:44:25.433565 <30>[ 16.215516] systemd[1]: Listening on Journal Socket.
10725 17:44:25.439539 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10726 17:44:25.455774 <30>[ 16.234956] systemd[1]: Listening on Network Service Netlink Socket.
10727 17:44:25.462545 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10728 17:44:25.477598 <30>[ 16.259494] systemd[1]: Listening on udev Control Socket.
10729 17:44:25.483805 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10730 17:44:25.501103 <30>[ 16.283342] systemd[1]: Listening on udev Kernel Socket.
10731 17:44:25.507714 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10732 17:44:25.548136 <30>[ 16.330434] systemd[1]: Mounting Huge Pages File System...
10733 17:44:25.554763 Mounting [0;1;39mHuge Pages File System[0m...
10734 17:44:25.570611 <30>[ 16.352685] systemd[1]: Mounting POSIX Message Queue File System...
10735 17:44:25.577679 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10736 17:44:25.596540 <30>[ 16.378485] systemd[1]: Mounting Kernel Debug File System...
10737 17:44:25.603127 Mounting [0;1;39mKernel Debug File System[0m...
10738 17:44:25.619357 <30>[ 16.398423] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10739 17:44:25.630125 <30>[ 16.409280] systemd[1]: Starting Create list of static device nodes for the current kernel...
10740 17:44:25.636990 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10741 17:44:25.654776 <30>[ 16.436984] systemd[1]: Starting Load Kernel Module configfs...
10742 17:44:25.660960 Starting [0;1;39mLoad Kernel Module configfs[0m...
10743 17:44:25.679197 <30>[ 16.461659] systemd[1]: Starting Load Kernel Module drm...
10744 17:44:25.686080 Starting [0;1;39mLoad Kernel Module drm[0m...
10745 17:44:25.703483 <30>[ 16.482687] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10746 17:44:25.737019 <30>[ 16.519487] systemd[1]: Starting Journal Service...
10747 17:44:25.743766 Starting [0;1;39mJournal Service[0m...
10748 17:44:25.761778 <30>[ 16.543827] systemd[1]: Starting Load Kernel Modules...
10749 17:44:25.768168 Starting [0;1;39mLoad Kernel Modules[0m...
10750 17:44:25.791929 <30>[ 16.570946] systemd[1]: Starting Remount Root and Kernel File Systems...
10751 17:44:25.798764 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10752 17:44:25.821612 <30>[ 16.603669] systemd[1]: Starting Coldplug All udev Devices...
10753 17:44:25.828371 Starting [0;1;39mColdplug All udev Devices[0m...
10754 17:44:25.854063 <30>[ 16.636077] systemd[1]: Started Journal Service.
10755 17:44:25.860921 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10756 17:44:25.876124 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10757 17:44:25.893129 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10758 17:44:25.909149 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10759 17:44:25.928564 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10760 17:44:25.951145 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10761 17:44:25.970956 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10762 17:44:25.993888 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10763 17:44:26.013954 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10764 17:44:26.032332 See 'systemctl status systemd-remount-fs.service' for details.
10765 17:44:26.090727 Mounting [0;1;39mKernel Configuration File System[0m...
10766 17:44:26.110908 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10767 17:44:26.129771 <46>[ 16.908256] systemd-journald[180]: Received client request to flush runtime journal.
10768 17:44:26.139275 Starting [0;1;39mLoad/Save Random Seed[0m...
10769 17:44:26.161035 Starting [0;1;39mApply Kernel Variables[0m...
10770 17:44:26.182886 Starting [0;1;39mCreate System Users[0m...
10771 17:44:26.203344 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10772 17:44:26.225527 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10773 17:44:26.249396 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10774 17:44:26.265700 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10775 17:44:26.281879 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10776 17:44:26.296530 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10777 17:44:26.339995 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10778 17:44:26.362319 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10779 17:44:26.376559 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10780 17:44:26.391715 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10781 17:44:26.445510 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10782 17:44:26.469042 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10783 17:44:26.496510 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10784 17:44:26.517607 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10785 17:44:26.583559 Starting [0;1;39mNetwork Service[0m...
10786 17:44:26.611737 Starting [0;1;39mNetwork Time Synchronization[0m...
10787 17:44:26.631175 <6>[ 17.409957] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10788 17:44:26.645136 Startin<6>[ 17.427774] remoteproc remoteproc0: scp is available
10789 17:44:26.651682 g [0;1;39mUpdat<6>[ 17.434162] remoteproc remoteproc0: powering up scp
10790 17:44:26.661197 e UTMP about Sys<6>[ 17.440450] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10791 17:44:26.671317 <6>[ 17.441459] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10792 17:44:26.678041 tem Boot/Shutdow<6>[ 17.450276] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10793 17:44:26.678152 n[0m...
10794 17:44:26.692533 <6>[ 17.471531] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10795 17:44:26.702800 <6>[ 17.480822] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10796 17:44:26.722345 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10797 17:44:26.740087 <3>[ 17.518976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 17:44:26.746973 <3>[ 17.527099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 17:44:26.756683 <3>[ 17.535201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 17:44:26.766850 [[0;32m OK [<3>[ 17.544853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 17:44:26.776331 0m] Found device<3>[ 17.553132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 17:44:26.783044 <3>[ 17.562588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 17:44:26.793109 [0;1;39m/dev/t<3>[ 17.570994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 17:44:26.793268 tyS0[0m.
10805 17:44:26.803228 <3>[ 17.580324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 17:44:26.809471 <6>[ 17.580765] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10807 17:44:26.816310 <6>[ 17.580773] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10808 17:44:26.826683 <4>[ 17.589818] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10809 17:44:26.833284 <6>[ 17.597782] remoteproc remoteproc0: remote processor scp is now up
10810 17:44:26.840017 <3>[ 17.599456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 17:44:26.846476 <4>[ 17.617921] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10812 17:44:26.852782 <6>[ 17.621201] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10813 17:44:26.859805 <6>[ 17.621439] usbcore: registered new interface driver r8152
10814 17:44:26.866093 <3>[ 17.623730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 17:44:26.876552 <3>[ 17.623740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10816 17:44:26.882641 <3>[ 17.623743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 17:44:26.892724 <3>[ 17.630040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 17:44:26.895977 <6>[ 17.634153] pci_bus 0000:00: root bus resource [bus 00-ff]
10819 17:44:26.906114 <3>[ 17.641067] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 17:44:26.913034 <6>[ 17.646732] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10821 17:44:26.919393 <3>[ 17.654811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 17:44:26.929473 <6>[ 17.662887] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10823 17:44:26.939495 <3>[ 17.670970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10824 17:44:26.942757 <6>[ 17.671115] mc: Linux media interface: v0.10
10825 17:44:26.952157 <6>[ 17.674930] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10826 17:44:26.956152 <6>[ 17.679155] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10827 17:44:26.966910 <3>[ 17.684783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 17:44:26.973320 <3>[ 17.684852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 17:44:26.979859 <6>[ 17.692957] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10830 17:44:26.990126 <6>[ 17.698667] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10831 17:44:27.000072 <6>[ 17.699359] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10832 17:44:27.009827 <4>[ 17.701210] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10833 17:44:27.013156 <4>[ 17.701210] Fallback method does not support PEC.
10834 17:44:27.019884 <6>[ 17.708198] pci 0000:00:00.0: supports D1 D2
10835 17:44:27.026589 <6>[ 17.726830] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10836 17:44:27.033247 <6>[ 17.730759] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10837 17:44:27.039837 <6>[ 17.732015] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10838 17:44:27.049705 <6>[ 17.743875] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10839 17:44:27.056432 <6>[ 17.745050] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10840 17:44:27.066090 <3>[ 17.754805] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10841 17:44:27.072869 <6>[ 17.760969] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10842 17:44:27.079571 <6>[ 17.760998] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10843 17:44:27.086238 <6>[ 17.761014] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10844 17:44:27.092931 <6>[ 17.761138] pci 0000:01:00.0: supports D1 D2
10845 17:44:27.102930 <4>[ 17.772243] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10846 17:44:27.109175 <6>[ 17.778578] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10847 17:44:27.112752 <6>[ 17.779518] usbcore: registered new interface driver cdc_ether
10848 17:44:27.119330 <6>[ 17.779975] Bluetooth: Core ver 2.22
10849 17:44:27.122964 <6>[ 17.780042] NET: Registered PF_BLUETOOTH protocol family
10850 17:44:27.129409 <6>[ 17.780045] Bluetooth: HCI device and connection manager initialized
10851 17:44:27.136056 <6>[ 17.780064] Bluetooth: HCI socket layer initialized
10852 17:44:27.139439 <6>[ 17.780070] Bluetooth: L2CAP socket layer initialized
10853 17:44:27.146567 <6>[ 17.780080] Bluetooth: SCO socket layer initialized
10854 17:44:27.153667 <4>[ 17.788173] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10855 17:44:27.160697 <6>[ 17.789787] videodev: Linux video capture interface: v2.00
10856 17:44:27.168457 <6>[ 17.791212] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10857 17:44:27.174563 <6>[ 17.791264] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10858 17:44:27.181633 <6>[ 17.791271] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10859 17:44:27.192440 <6>[ 17.791280] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10860 17:44:27.198822 <6>[ 17.791293] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10861 17:44:27.208820 <6>[ 17.791306] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10862 17:44:27.212218 <6>[ 17.791319] pci 0000:00:00.0: PCI bridge to [bus 01]
10863 17:44:27.218946 <6>[ 17.791325] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10864 17:44:27.225834 <6>[ 17.791582] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10865 17:44:27.232526 <6>[ 17.792229] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10866 17:44:27.239166 <6>[ 17.794114] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10867 17:44:27.245741 <6>[ 17.806473] usbcore: registered new interface driver r8153_ecm
10868 17:44:27.252238 <6>[ 17.813155] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10869 17:44:27.262545 <5>[ 17.831717] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10870 17:44:27.265542 <6>[ 17.839903] usbcore: registered new interface driver btusb
10871 17:44:27.276025 <4>[ 17.840926] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10872 17:44:27.282186 <3>[ 17.840945] Bluetooth: hci0: Failed to load firmware file (-2)
10873 17:44:27.288763 <3>[ 17.840950] Bluetooth: hci0: Failed to set up firmware (-2)
10874 17:44:27.298593 <4>[ 17.840954] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10875 17:44:27.308646 <6>[ 17.841547] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10876 17:44:27.315473 <6>[ 17.853701] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10877 17:44:27.322318 <5>[ 17.856616] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10878 17:44:27.332618 <4>[ 17.856678] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10879 17:44:27.335951 <6>[ 17.856683] cfg80211: failed to load regulatory.db
10880 17:44:27.342879 <6>[ 17.868486] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10881 17:44:27.356487 <6>[ 17.877106] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10882 17:44:27.359819 <6>[ 17.894122] r8152 2-1.3:1.0 eth0: v1.12.13
10883 17:44:27.365938 <6>[ 17.895893] usbcore: registered new interface driver uvcvideo
10884 17:44:27.369310 <6>[ 17.923176] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10885 17:44:27.379587 <6>[ 17.940687] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10886 17:44:27.386019 <3>[ 17.943752] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10887 17:44:27.392776 <6>[ 17.947512] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10888 17:44:27.402731 <3>[ 17.948233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10889 17:44:27.412514 <3>[ 17.954602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 17:44:27.419275 <3>[ 17.955381] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10891 17:44:27.428904 <3>[ 17.977584] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 17:44:27.435573 <6>[ 17.982769] mt7921e 0000:01:00.0: ASIC revision: 79610010
10893 17:44:27.442410 <3>[ 18.007114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 17:44:27.455076 <4>[ 18.101437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10895 17:44:27.461908 <3>[ 18.125095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 17:44:27.476411 <4>[ 18.235729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10897 17:44:27.485864 [[0;32m OK [0m] Started [0;<3>[ 18.264827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 17:44:27.489126 1;39mNetwork Service[0m.
10899 17:44:27.510077 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10900 17:44:27.520003 <3>[ 18.298562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 17:44:27.593424 <4>[ 18.368760] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10902 17:44:27.655092 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10903 17:44:27.668152 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10904 17:44:27.688102 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10905 17:44:27.698159 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10906 17:44:27.713127 <4>[ 18.488801] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10907 17:44:27.723196 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10908 17:44:27.779825 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10909 17:44:27.802463 Starting [0;1;39mNetwork Name Resolution[0m...
10910 17:44:27.834846 [[0;32m OK [0m] Finished [0<4>[ 18.609340] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10911 17:44:27.838116 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10912 17:44:27.856669 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10913 17:44:27.880279 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10914 17:44:27.895241 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10915 17:44:27.908689 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10916 17:44:27.932210 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10917 17:44:27.953190 <4>[ 18.728793] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10918 17:44:27.959169 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10919 17:44:27.980753 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10920 17:44:28.048749 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10921 17:44:28.074057 <4>[ 18.850158] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10922 17:44:28.088147 Starting [0;1;39mUser Login Management[0m...
10923 17:44:28.109167 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10924 17:44:28.125508 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10925 17:44:28.141893 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10926 17:44:28.156612 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10927 17:44:28.175451 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10928 17:44:28.196688 <4>[ 18.972786] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10929 17:44:28.236742 Starting [0;1;39mPermit User Sessions[0m...
10930 17:44:28.254688 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10931 17:44:28.277155 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10932 17:44:28.316591 <4>[ 19.092437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10933 17:44:28.326561 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10934 17:44:28.343863 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10935 17:44:28.361216 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10936 17:44:28.380374 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10937 17:44:28.396473 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10938 17:44:28.437645 <4>[ 19.213590] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10939 17:44:28.469405 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10940 17:44:28.508389 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10941 17:44:28.529963
10942 17:44:28.530165
10943 17:44:28.533171 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10944 17:44:28.533392
10945 17:44:28.536401 debian-bullseye-arm64 login: root (automatic login)
10946 17:44:28.536547
10947 17:44:28.536696
10948 17:44:28.550267 <3>[ 19.332534] mt7921e 0000:01:00.0: hardware init failed
10949 17:44:28.561699 Linux debian-bullseye-arm64 6.1.52-cip5 #1 SMP PREEMPT Wed Sep 13 17:13:26 UTC 2023 aarch64
10950 17:44:28.561885
10951 17:44:28.568380 The programs included with the Debian GNU/Linux system are free software;
10952 17:44:28.575058 the exact distribution terms for each program are described in the
10953 17:44:28.578915 individual files in /usr/share/doc/*/copyright.
10954 17:44:28.579049
10955 17:44:28.585194 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10956 17:44:28.588739 permitted by applicable law.
10957 17:44:28.589187 Matched prompt #10: / #
10959 17:44:28.589504 Setting prompt string to ['/ #']
10960 17:44:28.589639 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10962 17:44:28.589946 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10963 17:44:28.590073 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10964 17:44:28.590180 Setting prompt string to ['/ #']
10965 17:44:28.590276 Forcing a shell prompt, looking for ['/ #']
10967 17:44:28.640554 / #
10968 17:44:28.640789 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10969 17:44:28.640917 Waiting using forced prompt support (timeout 00:02:30)
10970 17:44:28.645483
10971 17:44:28.645819 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10972 17:44:28.645960 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10973 17:44:28.646098 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10974 17:44:28.646225 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10975 17:44:28.646347 end: 2 depthcharge-action (duration 00:01:28) [common]
10976 17:44:28.646474 start: 3 lava-test-retry (timeout 00:08:12) [common]
10977 17:44:28.646604 start: 3.1 lava-test-shell (timeout 00:08:12) [common]
10978 17:44:28.646716 Using namespace: common
10980 17:44:28.747123 / # #
10981 17:44:28.747388 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10982 17:44:28.747583 #<6>[ 19.494415] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10983 17:44:28.747718 <6>[ 19.502466] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10984 17:44:28.752122
10985 17:44:28.752523 Using /lava-11518285
10987 17:44:28.852938 / # export SHELL=/bin/sh
10988 17:44:28.858795 export SHELL=/bin/sh
10990 17:44:28.959453 / # . /lava-11518285/environment
10991 17:44:28.964732 . /lava-11518285/environment
10993 17:44:29.065468 / # /lava-11518285/bin/lava-test-runner /lava-11518285/0
10994 17:44:29.065652 Test shell timeout: 10s (minimum of the action and connection timeout)
10995 17:44:29.071326 /lava-11518285/bin/lava-test-runner /lava-11518285/0
10996 17:44:29.095139 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10997 17:44:29.101312 + cd /lava-11518285/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10998 17:44:29.101446 + cat uuid
10999 17:44:29.105259 + UUID=11518285_1.5.2.3.1
11000 17:44:29.105400 + set +x
11001 17:44:29.111373 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11518285_1.5.2.3.1>
11002 17:44:29.111710 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11518285_1.5.2.3.1
11003 17:44:29.111828 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11518285_1.5.2.3.1)
11004 17:44:29.111953 Skipping test definition patterns.
11005 17:44:29.114875 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11006 17:44:29.118242 Received signal: <TESTCASE> TEST_CASE_ID=device-presence R<4
11007 17:44:29.118413 Ignoring malformed parameter for signal: "R<4".
11008 17:44:29.128031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence R<4>[ 19.905849] use of bytesused == 0 is deprecated and will be removed in the future,
11009 17:44:29.131525 <4>[ 19.914564] use the actual size instead.
11010 17:44:29.131723 ESULT=pass>
11011 17:44:29.138276 device: /dev/video2<4>[ 19.920645] ------------[ cut here ]------------
11012 17:44:29.138477
11013 17:44:29.144650 <4>[ 19.926437] get_vaddr_frames() cannot follow VM_IO mapping
11014 17:44:29.157589 <4>[ 19.926585] WARNING: CPU: 5 PID: 307 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11015 17:44:29.207381 <4>[ 19.944770] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 mtk_vcodec_enc libarc4 mtk_vcodec_common mtk_vpu uvcvideo v4l2_mem2mem btusb videobuf2_vmalloc videobuf2_dma_contig videobuf2_memops cfg80211 btintel videobuf2_v4l2 btmtk r8153_ecm btrtl cros_ec_rpmsg videobuf2_common btbcm cdc_ether videodev usbnet bluetooth crct10dif_ce ecdh_generic mc sbs_battery ecc r8152 elants_i2c rfkill elan_i2c hid_google_hammer cros_ec_chardev cros_ec_typec hid_vivaldi_common pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11016 17:44:29.214150 <4>[ 19.994117] CPU: 5 PID: 307 Comm: v4l2-compliance Not tainted 6.1.52-cip5 #1
11017 17:44:29.220338 <4>[ 20.001412] Hardware name: Google Spherion (rev0 - 3) (DT)
11018 17:44:29.227580 <4>[ 20.007145] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11019 17:44:29.234255 <4>[ 20.014354] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11020 17:44:29.237478 <4>[ 20.020440] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11021 17:44:29.244101 <4>[ 20.026525] sp : ffff8000091b3850
11022 17:44:29.250317 <4>[ 20.030086] x29: ffff8000091b3850 x28: ffffc8c24fad2000 x27: ffffc8c24face238
11023 17:44:29.257017 <4>[ 20.037469] x26: 0000000000000000 x25: ffffc8c284c2d0a0 x24: ffff58ffce3a1298
11024 17:44:29.263569 <4>[ 20.044851] x23: ffff58ffc14f6400 x22: ffff58ffc0d48410 x21: 0000000000000000
11025 17:44:29.270477 <4>[ 20.052233] x20: 00000000fffffff2 x19: ffff58ffce11d100 x18: fffffffffffe9778
11026 17:44:29.280529 <4>[ 20.059615] x17: 0000000000000000 x16: ffffc8c282a8bb90 x15: 0000000000000038
11027 17:44:29.286955 <4>[ 20.066998] x14: ffffc8c2855134a8 x13: 000000000000064e x12: 000000000000021a
11028 17:44:29.293375 <4>[ 20.074380] x11: fffffffffffe9778 x10: fffffffffffe9740 x9 : 00000000fffff21a
11029 17:44:29.300222 <4>[ 20.081762] x8 : ffffc8c2855134a8 x7 : ffffc8c28556b4a8 x6 : 0000000000001938
11030 17:44:29.310083 <4>[ 20.089144] x5 : ffff5900fef7ca18 x4 : 00000000fffff21a x3 : ffff903e7a129000
11031 17:44:29.316784 <4>[ 20.096526] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff58ffce00ac40
11032 17:44:29.320333 <4>[ 20.103910] Call trace:
11033 17:44:29.323055 <4>[ 20.106604] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11034 17:44:29.329777 <4>[ 20.112342] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11035 17:44:29.336384 <4>[ 20.118342] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11036 17:44:29.343506 <4>[ 20.124690] __prepare_userptr+0x280/0x410 [videobuf2_common]
11037 17:44:29.349665 <4>[ 20.130688] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11038 17:44:29.356308 <4>[ 20.136339] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11039 17:44:29.359527 <4>[ 20.142511] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11040 17:44:29.366211 <4>[ 20.147997] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11041 17:44:29.372663 <4>[ 20.153750] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11042 17:44:29.376646 <4>[ 20.160008] v4l_prepare_buf+0x48/0x60 [videodev]
11043 17:44:29.383068 <4>[ 20.165022] __video_do_ioctl+0x184/0x3d0 [videodev]
11044 17:44:29.385925 <4>[ 20.170249] video_usercopy+0x358/0x680 [videodev]
11045 17:44:29.392863 <4>[ 20.175301] video_ioctl2+0x18/0x30 [videodev]
11046 17:44:29.396027 <4>[ 20.180008] v4l2_ioctl+0x40/0x60 [videodev]
11047 17:44:29.402649 <4>[ 20.184540] __arm64_sys_ioctl+0xa8/0xf0
11048 17:44:29.406033 <4>[ 20.188718] invoke_syscall+0x48/0x114
11049 17:44:29.409232 <4>[ 20.192721] el0_svc_common.constprop.0+0x44/0xec
11050 17:44:29.412533 <4>[ 20.197675] do_el0_svc+0x2c/0xd0
11051 17:44:29.415839 <4>[ 20.201238] el0_svc+0x2c/0x84
11052 17:44:29.422465 <4>[ 20.204544] el0t_64_sync_handler+0xb8/0xc0
11053 17:44:29.425875 <4>[ 20.208976] el0t_64_sync+0x18c/0x190
11054 17:44:29.429286 <4>[ 20.212887] ---[ end trace 0000000000000000 ]---
11055 17:44:29.442419 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11056 17:44:29.451016 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11057 17:44:29.458055
11058 17:44:29.532524 Compliance test for mtk-vcodec-enc device /dev/video2:
11059 17:44:29.533020
11060 17:44:29.533333 Driver Info:
11061 17:44:29.533626 Driver name : mtk-vcodec-enc
11062 17:44:29.533910 Card type : MT8192 video encoder
11063 17:44:29.534233 Bus info : platform:17020000.vcodec
11064 17:44:29.536321 Driver version : 6.1.52
11065 17:44:29.546857 Capabilities : 0x84204000
11066 17:44:29.559163 Video Memory-to-Memory Multiplanar
11067 17:44:29.569972 Streaming
11068 17:44:29.583921 Extended Pix Format
11069 17:44:29.594000 Device Capabilities
11070 17:44:29.606468 Device Caps : 0x04204000
11071 17:44:29.619774 Video Memory-to-Memory Multiplanar
11072 17:44:29.632575 Streaming
11073 17:44:29.643268 Extended Pix Format
11074 17:44:29.658432 Detected Stateful Encoder
11075 17:44:29.670272
11076 17:44:29.682914 Required ioctls:
11077 17:44:29.699372 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11078 17:44:29.699527 test VIDIOC_QUERYCAP: OK
11079 17:44:29.699792 Received signal: <TESTSET> START Required-ioctls
11080 17:44:29.699869 Starting test_set Required-ioctls
11081 17:44:29.722911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11082 17:44:29.723229 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11084 17:44:29.726101 test invalid ioctls: OK
11085 17:44:29.748580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11086 17:44:29.748736
11087 17:44:29.748982 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11089 17:44:29.757475 Allow for multiple opens:
11090 17:44:29.765518 <LAVA_SIGNAL_TESTSET STOP>
11091 17:44:29.765847 Received signal: <TESTSET> STOP
11092 17:44:29.765931 Closing test_set Required-ioctls
11093 17:44:29.773950 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11094 17:44:29.774266 Received signal: <TESTSET> START Allow-for-multiple-opens
11095 17:44:29.774349 Starting test_set Allow-for-multiple-opens
11096 17:44:29.777079 test second /dev/video2 open: OK
11097 17:44:29.802910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11098 17:44:29.803251 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11100 17:44:29.805523 test VIDIOC_QUERYCAP: OK
11101 17:44:29.826610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11102 17:44:29.826960 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11104 17:44:29.830042 test VIDIOC_G/S_PRIORITY: OK
11105 17:44:29.850614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11106 17:44:29.850950 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11108 17:44:29.854288 test for unlimited opens: OK
11109 17:44:29.877498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11110 17:44:29.877637
11111 17:44:29.877882 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11113 17:44:29.886971 Debug ioctls:
11114 17:44:29.894591 <LAVA_SIGNAL_TESTSET STOP>
11115 17:44:29.894891 Received signal: <TESTSET> STOP
11116 17:44:29.894967 Closing test_set Allow-for-multiple-opens
11117 17:44:29.904474 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11118 17:44:29.904843 Received signal: <TESTSET> START Debug-ioctls
11119 17:44:29.904966 Starting test_set Debug-ioctls
11120 17:44:29.907132 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11121 17:44:29.929758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11122 17:44:29.930096 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11124 17:44:29.936405 test VIDIOC_LOG_STATUS: OK (Not Supported)
11125 17:44:29.955906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11126 17:44:29.956057
11127 17:44:29.956310 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11129 17:44:29.965851 Input ioctls:
11130 17:44:29.973824 <LAVA_SIGNAL_TESTSET STOP>
11131 17:44:29.974139 Received signal: <TESTSET> STOP
11132 17:44:29.974217 Closing test_set Debug-ioctls
11133 17:44:29.983372 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11134 17:44:29.983664 Received signal: <TESTSET> START Input-ioctls
11135 17:44:29.983739 Starting test_set Input-ioctls
11136 17:44:29.986816 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11137 17:44:30.011752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11138 17:44:30.012079 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11140 17:44:30.015215 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11141 17:44:30.034900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11142 17:44:30.035224 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11144 17:44:30.040780 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11145 17:44:30.062636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11146 17:44:30.062966 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11148 17:44:30.065993 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11149 17:44:30.089291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11150 17:44:30.089619 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11152 17:44:30.092561 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11153 17:44:30.114333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11154 17:44:30.114659 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11156 17:44:30.117544 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11157 17:44:30.138984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11158 17:44:30.139314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11160 17:44:30.141765 Inputs: 0 Audio Inputs: 0 Tuners: 0
11161 17:44:30.149248
11162 17:44:30.166634 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11163 17:44:30.190046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11164 17:44:30.190365 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11166 17:44:30.196490 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11167 17:44:30.214060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11168 17:44:30.214408 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11170 17:44:30.220894 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11171 17:44:30.241024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11172 17:44:30.241338 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11174 17:44:30.247878 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11175 17:44:30.264719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11176 17:44:30.265035 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11178 17:44:30.268502 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11179 17:44:30.289803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11180 17:44:30.289944
11181 17:44:30.290189 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11183 17:44:30.308061 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11184 17:44:30.330442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11185 17:44:30.330771 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11187 17:44:30.337414 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11188 17:44:30.361720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11189 17:44:30.362035 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11191 17:44:30.364451 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11192 17:44:30.388670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11193 17:44:30.389003 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11195 17:44:30.391969 test VIDIOC_G/S_EDID: OK (Not Supported)
11196 17:44:30.413795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11197 17:44:30.413949
11198 17:44:30.414194 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11200 17:44:30.425584 Control ioctls:
11201 17:44:30.437095 <LAVA_SIGNAL_TESTSET STOP>
11202 17:44:30.437433 Received signal: <TESTSET> STOP
11203 17:44:30.437521 Closing test_set Input-ioctls
11204 17:44:30.447198 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11205 17:44:30.447513 Received signal: <TESTSET> START Control-ioctls
11206 17:44:30.447592 Starting test_set Control-ioctls
11207 17:44:30.450617 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11208 17:44:30.477604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11209 17:44:30.477744 test VIDIOC_QUERYCTRL: OK
11210 17:44:30.477994 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11212 17:44:30.498951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11213 17:44:30.499268 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11215 17:44:30.502693 test VIDIOC_G/S_CTRL: OK
11216 17:44:30.528990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11217 17:44:30.529305 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11219 17:44:30.532556 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11220 17:44:30.558139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11221 17:44:30.558459 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11223 17:44:30.567771 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11224 17:44:30.571247 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11225 17:44:30.601310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11226 17:44:30.601636 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11228 17:44:30.604545 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11229 17:44:30.622535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11230 17:44:30.622860 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11232 17:44:30.625821 Standard Controls: 16 Private Controls: 0
11233 17:44:30.633340
11234 17:44:30.644186 Format ioctls:
11235 17:44:30.650218 <LAVA_SIGNAL_TESTSET STOP>
11236 17:44:30.650543 Received signal: <TESTSET> STOP
11237 17:44:30.650649 Closing test_set Control-ioctls
11238 17:44:30.659699 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11239 17:44:30.660026 Received signal: <TESTSET> START Format-ioctls
11240 17:44:30.660109 Starting test_set Format-ioctls
11241 17:44:30.663267 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11242 17:44:30.688730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11243 17:44:30.689052 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11245 17:44:30.692119 test VIDIOC_G/S_PARM: OK
11246 17:44:30.711445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11247 17:44:30.711789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11249 17:44:30.714629 test VIDIOC_G_FBUF: OK (Not Supported)
11250 17:44:30.734744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11251 17:44:30.735053 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11253 17:44:30.738077 test VIDIOC_G_FMT: OK
11254 17:44:30.759051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11255 17:44:30.759397 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11257 17:44:30.762339 test VIDIOC_TRY_FMT: OK
11258 17:44:30.783987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11259 17:44:30.784297 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11261 17:44:30.794058 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11262 17:44:30.794196 test VIDIOC_S_FMT: FAIL
11263 17:44:30.825509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11264 17:44:30.825857 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11266 17:44:30.828141 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11267 17:44:30.852881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11268 17:44:30.853196 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11270 17:44:30.856163 test Cropping: OK
11271 17:44:30.878849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11272 17:44:30.879168 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11274 17:44:30.882154 test Composing: OK (Not Supported)
11275 17:44:30.903797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11276 17:44:30.904111 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11278 17:44:30.907182 test Scaling: OK (Not Supported)
11279 17:44:30.929201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11280 17:44:30.929344
11281 17:44:30.929589 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11283 17:44:30.942785 Codec ioctls:
11284 17:44:30.950333 <LAVA_SIGNAL_TESTSET STOP>
11285 17:44:30.950623 Received signal: <TESTSET> STOP
11286 17:44:30.950696 Closing test_set Format-ioctls
11287 17:44:30.960292 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11288 17:44:30.960580 Received signal: <TESTSET> START Codec-ioctls
11289 17:44:30.960657 Starting test_set Codec-ioctls
11290 17:44:30.962933 test VIDIOC_(TRY_)ENCODER_CMD: OK
11291 17:44:30.984527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11292 17:44:30.984842 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11294 17:44:30.991491 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11295 17:44:31.010036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11296 17:44:31.010377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11298 17:44:31.016451 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11299 17:44:31.038641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11300 17:44:31.038835
11301 17:44:31.039126 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11303 17:44:31.050059 Buffer ioctls:
11304 17:44:31.056254 <LAVA_SIGNAL_TESTSET STOP>
11305 17:44:31.056587 Received signal: <TESTSET> STOP
11306 17:44:31.056697 Closing test_set Codec-ioctls
11307 17:44:31.068812 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11308 17:44:31.069168 Received signal: <TESTSET> START Buffer-ioctls
11309 17:44:31.069284 Starting test_set Buffer-ioctls
11310 17:44:31.072181 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11311 17:44:31.097754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11312 17:44:31.097945 test VIDIOC_EXPBUF: OK
11313 17:44:31.098232 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11315 17:44:31.117836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11316 17:44:31.118206 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11318 17:44:31.121510 test Requests: OK (Not Supported)
11319 17:44:31.141647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11320 17:44:31.141813
11321 17:44:31.142100 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11323 17:44:31.151373 Test input 0:
11324 17:44:31.161567
11325 17:44:31.172631 Streaming ioctls:
11326 17:44:31.181643 <LAVA_SIGNAL_TESTSET STOP>
11327 17:44:31.181997 Received signal: <TESTSET> STOP
11328 17:44:31.182113 Closing test_set Buffer-ioctls
11329 17:44:31.193631 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11330 17:44:31.193967 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11331 17:44:31.194080 Starting test_set Streaming-ioctls_Test-input-0
11332 17:44:31.196853 test read/write: OK (Not Supported)
11333 17:44:31.217416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11334 17:44:31.217788 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11336 17:44:31.224113 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11337 17:44:31.234439 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11338 17:44:31.240401 test blocking wait: FAIL
11339 17:44:31.270763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11340 17:44:31.271140 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11342 17:44:31.280685 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11343 17:44:31.285624 test MMAP (select): FAIL
11344 17:44:31.309725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11345 17:44:31.310074 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11347 17:44:31.316148 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11348 17:44:31.321753 test MMAP (epoll): FAIL
11349 17:44:31.347724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11350 17:44:31.348073 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11352 17:44:31.354432 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11353 17:44:31.364526 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11354 17:44:31.367235 test USERPTR (select): FAIL
11355 17:44:31.392294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11356 17:44:31.392679 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11358 17:44:31.399150 test DMABUF: Cannot test, specify --expbuf-device
11359 17:44:31.404169
11360 17:44:31.426591 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11361 17:44:31.429850 <LAVA_TEST_RUNNER EXIT>
11362 17:44:31.430194 ok: lava_test_shell seems to have completed
11363 17:44:31.430309 Marking unfinished test run as failed
11365 17:44:31.431856 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11366 17:44:31.432034 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11367 17:44:31.432160 end: 3 lava-test-retry (duration 00:00:03) [common]
11368 17:44:31.432286 start: 4 finalize (timeout 00:08:09) [common]
11369 17:44:31.432414 start: 4.1 power-off (timeout 00:00:30) [common]
11370 17:44:31.432650 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11371 17:44:31.510413 >> Command sent successfully.
11372 17:44:31.512882 Returned 0 in 0 seconds
11373 17:44:31.613344 end: 4.1 power-off (duration 00:00:00) [common]
11375 17:44:31.613819 start: 4.2 read-feedback (timeout 00:08:09) [common]
11376 17:44:31.614169 Listened to connection for namespace 'common' for up to 1s
11377 17:44:32.614567 Finalising connection for namespace 'common'
11378 17:44:32.614738 Disconnecting from shell: Finalise
11379 17:44:32.614823 / #
11380 17:44:32.715145 end: 4.2 read-feedback (duration 00:00:01) [common]
11381 17:44:32.715311 end: 4 finalize (duration 00:00:01) [common]
11382 17:44:32.715427 Cleaning after the job
11383 17:44:32.715539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/ramdisk
11384 17:44:32.721176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/kernel
11385 17:44:32.729555 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/dtb
11386 17:44:32.729892 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11518285/tftp-deploy-09441uta/modules
11387 17:44:32.737414 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11518285
11388 17:44:32.806276 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11518285
11389 17:44:32.806438 Job finished correctly