Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 08:04:45.739793 lava-dispatcher, installed at version: 2023.06
2 08:04:45.740006 start: 0 validate
3 08:04:45.740210 Start time: 2023-09-21 08:04:45.740202+00:00 (UTC)
4 08:04:45.740346 Using caching service: 'http://localhost/cache/?uri=%s'
5 08:04:45.740502 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 08:04:46.025660 Using caching service: 'http://localhost/cache/?uri=%s'
7 08:04:46.026466 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 08:04:46.302231 Using caching service: 'http://localhost/cache/?uri=%s'
9 08:04:46.303004 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 08:05:39.313654 Using caching service: 'http://localhost/cache/?uri=%s'
11 08:05:39.314355 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 08:05:39.854749 validate duration: 54.11
14 08:05:39.856085 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:05:39.856648 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:05:39.857149 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:05:39.857786 Not decompressing ramdisk as can be used compressed.
18 08:05:39.858288 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 08:05:39.858667 saving as /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/ramdisk/rootfs.cpio.gz
20 08:05:39.859032 total size: 8181372 (7 MB)
21 08:05:43.285939 progress 0 % (0 MB)
22 08:05:43.291653 progress 5 % (0 MB)
23 08:05:43.293771 progress 10 % (0 MB)
24 08:05:43.296149 progress 15 % (1 MB)
25 08:05:43.298206 progress 20 % (1 MB)
26 08:05:43.300471 progress 25 % (1 MB)
27 08:05:43.302557 progress 30 % (2 MB)
28 08:05:43.304943 progress 35 % (2 MB)
29 08:05:43.307036 progress 40 % (3 MB)
30 08:05:43.309314 progress 45 % (3 MB)
31 08:05:43.311374 progress 50 % (3 MB)
32 08:05:43.313640 progress 55 % (4 MB)
33 08:05:43.315728 progress 60 % (4 MB)
34 08:05:43.317952 progress 65 % (5 MB)
35 08:05:43.320045 progress 70 % (5 MB)
36 08:05:43.322216 progress 75 % (5 MB)
37 08:05:43.324274 progress 80 % (6 MB)
38 08:05:43.326540 progress 85 % (6 MB)
39 08:05:43.328593 progress 90 % (7 MB)
40 08:05:43.330760 progress 95 % (7 MB)
41 08:05:43.332830 progress 100 % (7 MB)
42 08:05:43.333026 7 MB downloaded in 3.47 s (2.25 MB/s)
43 08:05:43.333179 end: 1.1.1 http-download (duration 00:00:03) [common]
45 08:05:43.333412 end: 1.1 download-retry (duration 00:00:03) [common]
46 08:05:43.333495 start: 1.2 download-retry (timeout 00:09:57) [common]
47 08:05:43.333576 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 08:05:43.333710 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 08:05:43.333777 saving as /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/kernel/Image
50 08:05:43.333864 total size: 49304064 (47 MB)
51 08:05:43.333957 No compression specified
52 08:05:43.603549 progress 0 % (0 MB)
53 08:05:43.654187 progress 5 % (2 MB)
54 08:05:43.672124 progress 10 % (4 MB)
55 08:05:43.685461 progress 15 % (7 MB)
56 08:05:43.698140 progress 20 % (9 MB)
57 08:05:43.710840 progress 25 % (11 MB)
58 08:05:43.723318 progress 30 % (14 MB)
59 08:05:43.735870 progress 35 % (16 MB)
60 08:05:43.748554 progress 40 % (18 MB)
61 08:05:43.761431 progress 45 % (21 MB)
62 08:05:43.773999 progress 50 % (23 MB)
63 08:05:43.786730 progress 55 % (25 MB)
64 08:05:43.799323 progress 60 % (28 MB)
65 08:05:43.812063 progress 65 % (30 MB)
66 08:05:43.824708 progress 70 % (32 MB)
67 08:05:43.837199 progress 75 % (35 MB)
68 08:05:43.849887 progress 80 % (37 MB)
69 08:05:43.862561 progress 85 % (39 MB)
70 08:05:43.875218 progress 90 % (42 MB)
71 08:05:43.887596 progress 95 % (44 MB)
72 08:05:43.899983 progress 100 % (47 MB)
73 08:05:43.900185 47 MB downloaded in 0.57 s (83.03 MB/s)
74 08:05:43.900330 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:05:43.900563 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:05:43.900652 start: 1.3 download-retry (timeout 00:09:56) [common]
78 08:05:43.900736 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 08:05:43.900879 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 08:05:43.900948 saving as /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/dtb/mt8192-asurada-spherion-r0.dtb
81 08:05:43.901008 total size: 47278 (0 MB)
82 08:05:43.901068 No compression specified
83 08:05:43.902168 progress 69 % (0 MB)
84 08:05:43.902437 progress 100 % (0 MB)
85 08:05:43.902591 0 MB downloaded in 0.00 s (28.53 MB/s)
86 08:05:43.902709 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:05:43.903049 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:05:43.903149 start: 1.4 download-retry (timeout 00:09:56) [common]
90 08:05:43.903231 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 08:05:43.903348 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 08:05:43.903415 saving as /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/modules/modules.tar
93 08:05:43.903476 total size: 8625188 (8 MB)
94 08:05:43.903536 Using unxz to decompress xz
95 08:05:43.907652 progress 0 % (0 MB)
96 08:05:43.928981 progress 5 % (0 MB)
97 08:05:43.951003 progress 10 % (0 MB)
98 08:05:43.976775 progress 15 % (1 MB)
99 08:05:44.001485 progress 20 % (1 MB)
100 08:05:44.026687 progress 25 % (2 MB)
101 08:05:44.052534 progress 30 % (2 MB)
102 08:05:44.079126 progress 35 % (2 MB)
103 08:05:44.103293 progress 40 % (3 MB)
104 08:05:44.126833 progress 45 % (3 MB)
105 08:05:44.153363 progress 50 % (4 MB)
106 08:05:44.178496 progress 55 % (4 MB)
107 08:05:44.202540 progress 60 % (4 MB)
108 08:05:44.226470 progress 65 % (5 MB)
109 08:05:44.251160 progress 70 % (5 MB)
110 08:05:44.275463 progress 75 % (6 MB)
111 08:05:44.302197 progress 80 % (6 MB)
112 08:05:44.331038 progress 85 % (7 MB)
113 08:05:44.358013 progress 90 % (7 MB)
114 08:05:44.384138 progress 95 % (7 MB)
115 08:05:44.407275 progress 100 % (8 MB)
116 08:05:44.412238 8 MB downloaded in 0.51 s (16.17 MB/s)
117 08:05:44.412480 end: 1.4.1 http-download (duration 00:00:01) [common]
119 08:05:44.412734 end: 1.4 download-retry (duration 00:00:01) [common]
120 08:05:44.412824 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 08:05:44.412918 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 08:05:44.412999 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:05:44.413082 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 08:05:44.413318 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz
125 08:05:44.413450 makedir: /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin
126 08:05:44.413554 makedir: /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/tests
127 08:05:44.413651 makedir: /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/results
128 08:05:44.413769 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-add-keys
129 08:05:44.413916 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-add-sources
130 08:05:44.414051 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-background-process-start
131 08:05:44.414178 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-background-process-stop
132 08:05:44.414302 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-common-functions
133 08:05:44.414424 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-echo-ipv4
134 08:05:44.414550 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-install-packages
135 08:05:44.414675 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-installed-packages
136 08:05:44.414798 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-os-build
137 08:05:44.414922 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-probe-channel
138 08:05:44.415045 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-probe-ip
139 08:05:44.415168 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-target-ip
140 08:05:44.415291 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-target-mac
141 08:05:44.415412 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-target-storage
142 08:05:44.415541 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-case
143 08:05:44.415666 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-event
144 08:05:44.415833 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-feedback
145 08:05:44.415959 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-raise
146 08:05:44.416083 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-reference
147 08:05:44.416205 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-runner
148 08:05:44.416326 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-set
149 08:05:44.416450 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-test-shell
150 08:05:44.416577 Updating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-install-packages (oe)
151 08:05:44.416726 Updating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/bin/lava-installed-packages (oe)
152 08:05:44.416846 Creating /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/environment
153 08:05:44.416944 LAVA metadata
154 08:05:44.417016 - LAVA_JOB_ID=11585986
155 08:05:44.417077 - LAVA_DISPATCHER_IP=192.168.201.1
156 08:05:44.417176 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 08:05:44.417241 skipped lava-vland-overlay
158 08:05:44.417312 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 08:05:44.417390 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 08:05:44.417453 skipped lava-multinode-overlay
161 08:05:44.417523 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 08:05:44.417602 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 08:05:44.417672 Loading test definitions
164 08:05:44.417760 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 08:05:44.417834 Using /lava-11585986 at stage 0
166 08:05:44.418151 uuid=11585986_1.5.2.3.1 testdef=None
167 08:05:44.418237 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 08:05:44.418323 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 08:05:44.418865 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 08:05:44.419081 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 08:05:44.419728 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 08:05:44.419952 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 08:05:44.420572 runner path: /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/0/tests/0_dmesg test_uuid 11585986_1.5.2.3.1
176 08:05:44.420725 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 08:05:44.420944 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:55) [common]
179 08:05:44.421014 Using /lava-11585986 at stage 1
180 08:05:44.421308 uuid=11585986_1.5.2.3.5 testdef=None
181 08:05:44.421392 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 08:05:44.421473 start: 1.5.2.3.6 test-overlay (timeout 00:09:55) [common]
183 08:05:44.421948 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 08:05:44.422159 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:55) [common]
186 08:05:44.423296 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 08:05:44.423522 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:55) [common]
189 08:05:44.424155 runner path: /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/1/tests/1_bootrr test_uuid 11585986_1.5.2.3.5
190 08:05:44.424307 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 08:05:44.424509 Creating lava-test-runner.conf files
193 08:05:44.424571 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/0 for stage 0
194 08:05:44.424660 - 0_dmesg
195 08:05:44.424738 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11585986/lava-overlay-79vw5hsz/lava-11585986/1 for stage 1
196 08:05:44.424827 - 1_bootrr
197 08:05:44.424919 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 08:05:44.425002 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
199 08:05:44.432875 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 08:05:44.432974 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
201 08:05:44.433056 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 08:05:44.433140 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 08:05:44.433221 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
204 08:05:44.682206 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 08:05:44.682602 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
206 08:05:44.682722 extracting modules file /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11585986/extract-overlay-ramdisk-j31gycdh/ramdisk
207 08:05:44.897569 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 08:05:44.897735 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
209 08:05:44.897829 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585986/compress-overlay-kp39ktm5/overlay-1.5.2.4.tar.gz to ramdisk
210 08:05:44.897902 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585986/compress-overlay-kp39ktm5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11585986/extract-overlay-ramdisk-j31gycdh/ramdisk
211 08:05:44.905900 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 08:05:44.906008 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
213 08:05:44.906095 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 08:05:44.906182 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
215 08:05:44.906255 Building ramdisk /var/lib/lava/dispatcher/tmp/11585986/extract-overlay-ramdisk-j31gycdh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11585986/extract-overlay-ramdisk-j31gycdh/ramdisk
216 08:05:45.305983 >> 145262 blocks
217 08:05:47.552929 rename /var/lib/lava/dispatcher/tmp/11585986/extract-overlay-ramdisk-j31gycdh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/ramdisk/ramdisk.cpio.gz
218 08:05:47.553377 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 08:05:47.553505 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
220 08:05:47.553610 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
221 08:05:47.553715 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/kernel/Image'
222 08:05:59.440409 Returned 0 in 11 seconds
223 08:05:59.541591 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/kernel/image.itb
224 08:05:59.968847 output: FIT description: Kernel Image image with one or more FDT blobs
225 08:05:59.969234 output: Created: Thu Sep 21 09:05:59 2023
226 08:05:59.969314 output: Image 0 (kernel-1)
227 08:05:59.969381 output: Description:
228 08:05:59.969444 output: Created: Thu Sep 21 09:05:59 2023
229 08:05:59.969507 output: Type: Kernel Image
230 08:05:59.969567 output: Compression: lzma compressed
231 08:05:59.969626 output: Data Size: 11045265 Bytes = 10786.39 KiB = 10.53 MiB
232 08:05:59.969684 output: Architecture: AArch64
233 08:05:59.969743 output: OS: Linux
234 08:05:59.969799 output: Load Address: 0x00000000
235 08:05:59.969852 output: Entry Point: 0x00000000
236 08:05:59.969925 output: Hash algo: crc32
237 08:05:59.970019 output: Hash value: 886bc8a0
238 08:05:59.970078 output: Image 1 (fdt-1)
239 08:05:59.970132 output: Description: mt8192-asurada-spherion-r0
240 08:05:59.970185 output: Created: Thu Sep 21 09:05:59 2023
241 08:05:59.970238 output: Type: Flat Device Tree
242 08:05:59.970290 output: Compression: uncompressed
243 08:05:59.970343 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 08:05:59.970395 output: Architecture: AArch64
245 08:05:59.970447 output: Hash algo: crc32
246 08:05:59.970499 output: Hash value: cc4352de
247 08:05:59.970551 output: Image 2 (ramdisk-1)
248 08:05:59.970603 output: Description: unavailable
249 08:05:59.970655 output: Created: Thu Sep 21 09:05:59 2023
250 08:05:59.970707 output: Type: RAMDisk Image
251 08:05:59.970759 output: Compression: Unknown Compression
252 08:05:59.970811 output: Data Size: 21395344 Bytes = 20893.89 KiB = 20.40 MiB
253 08:05:59.970864 output: Architecture: AArch64
254 08:05:59.970915 output: OS: Linux
255 08:05:59.970966 output: Load Address: unavailable
256 08:05:59.971018 output: Entry Point: unavailable
257 08:05:59.971070 output: Hash algo: crc32
258 08:05:59.971121 output: Hash value: 14e48731
259 08:05:59.971172 output: Default Configuration: 'conf-1'
260 08:05:59.971223 output: Configuration 0 (conf-1)
261 08:05:59.971275 output: Description: mt8192-asurada-spherion-r0
262 08:05:59.971327 output: Kernel: kernel-1
263 08:05:59.971379 output: Init Ramdisk: ramdisk-1
264 08:05:59.971430 output: FDT: fdt-1
265 08:05:59.971482 output: Loadables: kernel-1
266 08:05:59.971533 output:
267 08:05:59.971763 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 08:05:59.971886 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 08:05:59.971986 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 08:05:59.972077 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
271 08:05:59.972153 No LXC device requested
272 08:05:59.972229 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 08:05:59.972310 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
274 08:05:59.972387 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 08:05:59.972453 Checking files for TFTP limit of 4294967296 bytes.
276 08:05:59.972975 end: 1 tftp-deploy (duration 00:00:20) [common]
277 08:05:59.973073 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 08:05:59.973163 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 08:05:59.973285 substitutions:
280 08:05:59.973350 - {DTB}: 11585986/tftp-deploy-5pxa7njy/dtb/mt8192-asurada-spherion-r0.dtb
281 08:05:59.973415 - {INITRD}: 11585986/tftp-deploy-5pxa7njy/ramdisk/ramdisk.cpio.gz
282 08:05:59.973474 - {KERNEL}: 11585986/tftp-deploy-5pxa7njy/kernel/Image
283 08:05:59.973531 - {LAVA_MAC}: None
284 08:05:59.973586 - {PRESEED_CONFIG}: None
285 08:05:59.973641 - {PRESEED_LOCAL}: None
286 08:05:59.973695 - {RAMDISK}: 11585986/tftp-deploy-5pxa7njy/ramdisk/ramdisk.cpio.gz
287 08:05:59.973749 - {ROOT_PART}: None
288 08:05:59.973802 - {ROOT}: None
289 08:05:59.973855 - {SERVER_IP}: 192.168.201.1
290 08:05:59.973907 - {TEE}: None
291 08:05:59.973960 Parsed boot commands:
292 08:05:59.974012 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 08:05:59.974202 Parsed boot commands: tftpboot 192.168.201.1 11585986/tftp-deploy-5pxa7njy/kernel/image.itb 11585986/tftp-deploy-5pxa7njy/kernel/cmdline
294 08:05:59.974332 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 08:05:59.974423 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 08:05:59.974515 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 08:05:59.974604 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 08:05:59.974675 Not connected, no need to disconnect.
299 08:05:59.974750 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 08:05:59.974827 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 08:05:59.974895 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
302 08:05:59.978842 Setting prompt string to ['lava-test: # ']
303 08:05:59.979203 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 08:05:59.979304 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 08:05:59.979399 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 08:05:59.979696 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 08:05:59.979981 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
308 08:06:05.127924 >> Command sent successfully.
309 08:06:05.138406 Returned 0 in 5 seconds
310 08:06:05.239662 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 08:06:05.241106 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 08:06:05.241599 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 08:06:05.242045 Setting prompt string to 'Starting depthcharge on Spherion...'
315 08:06:05.242395 Changing prompt to 'Starting depthcharge on Spherion...'
316 08:06:05.242748 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 08:06:05.244021 [Enter `^Ec?' for help]
318 08:06:05.404190 e changed from pre-stopping to p
319 08:06:05.404740 F0: 102B 0000
320 08:06:05.405119
321 08:06:05.407507 F3: 1001 0000 [0200]
322 08:06:05.408011
323 08:06:05.408360 F3: 1001 0000
324 08:06:05.408675
325 08:06:05.408970 F7: 102D 0000
326 08:06:05.409264
327 08:06:05.409546 F1: 0000 0000
328 08:06:05.411186
329 08:06:05.411707 V0: 0000 0000 [0001]
330 08:06:05.412095
331 08:06:05.412415 00: 0007 8000
332 08:06:05.412746
333 08:06:05.414884 01: 0000 0000
334 08:06:05.415308
335 08:06:05.415641 BP: 0C00 0209 [0000]
336 08:06:05.416015
337 08:06:05.418051 G0: 1182 0000
338 08:06:05.418470
339 08:06:05.418801 EC: 0000 0021 [4000]
340 08:06:05.419134
341 08:06:05.421654 S7: 0000 0000 [0000]
342 08:06:05.422230
343 08:06:05.424671 CC: 0000 0000 [0001]
344 08:06:05.425095
345 08:06:05.425427 T0: 0000 0040 [010F]
346 08:06:05.425755
347 08:06:05.426052 Jump to BL
348 08:06:05.426346
349 08:06:05.451210
350 08:06:05.451781
351 08:06:05.452155
352 08:06:05.458310 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
353 08:06:05.462147 ARM64: Exception handlers installed.
354 08:06:05.466093 ARM64: Testing exception
355 08:06:05.469091 ARM64: Done test exception
356 08:06:05.476415 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
357 08:06:05.487075 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
358 08:06:05.494015 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
359 08:06:05.501269 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
360 08:06:05.507925 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
361 08:06:05.518899 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
362 08:06:05.528529 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
363 08:06:05.535250 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
364 08:06:05.553798 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
365 08:06:05.557156 WDT: Last reset was cold boot
366 08:06:05.560449 SPI1(PAD0) initialized at 2873684 Hz
367 08:06:05.564148 SPI5(PAD0) initialized at 992727 Hz
368 08:06:05.566901 VBOOT: Loading verstage.
369 08:06:05.573316 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
370 08:06:05.577032 FMAP: Found "FLASH" version 1.1 at 0x20000.
371 08:06:05.580525 FMAP: base = 0x0 size = 0x800000 #areas = 25
372 08:06:05.584033 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
373 08:06:05.591585 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
374 08:06:05.597709 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
375 08:06:05.609492 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
376 08:06:05.610061
377 08:06:05.610438
378 08:06:05.618804 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
379 08:06:05.622253 ARM64: Exception handlers installed.
380 08:06:05.625656 ARM64: Testing exception
381 08:06:05.626256 ARM64: Done test exception
382 08:06:05.632323 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
383 08:06:05.635233 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
384 08:06:05.650137 Probing TPM: . done!
385 08:06:05.650733 TPM ready after 0 ms
386 08:06:05.656418 Connected to device vid:did:rid of 1ae0:0028:00
387 08:06:05.663655 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
388 08:06:05.703806 Initialized TPM device CR50 revision 0
389 08:06:05.715301 tlcl_send_startup: Startup return code is 0
390 08:06:05.715821 TPM: setup succeeded
391 08:06:05.727066 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
392 08:06:05.735716 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
393 08:06:05.742975 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
394 08:06:05.754607 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
395 08:06:05.757912 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
396 08:06:05.761376 in-header: 03 07 00 00 08 00 00 00
397 08:06:05.765108 in-data: aa e4 47 04 13 02 00 00
398 08:06:05.768034 Chrome EC: UHEPI supported
399 08:06:05.774295 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
400 08:06:05.777659 in-header: 03 ad 00 00 08 00 00 00
401 08:06:05.781563 in-data: 00 20 20 08 00 00 00 00
402 08:06:05.782139 Phase 1
403 08:06:05.784287 FMAP: area GBB found @ 3f5000 (12032 bytes)
404 08:06:05.791455 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
405 08:06:05.797392 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
406 08:06:05.801224 Recovery requested (1009000e)
407 08:06:05.804577 TPM: Extending digest for VBOOT: boot mode into PCR 0
408 08:06:05.813559 tlcl_extend: response is 0
409 08:06:05.822067 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
410 08:06:05.826831 tlcl_extend: response is 0
411 08:06:05.833471 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
412 08:06:05.854270 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
413 08:06:05.860444 BS: bootblock times (exec / console): total (unknown) / 148 ms
414 08:06:05.861019
415 08:06:05.861389
416 08:06:05.871318 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
417 08:06:05.874864 ARM64: Exception handlers installed.
418 08:06:05.875447 ARM64: Testing exception
419 08:06:05.878063 ARM64: Done test exception
420 08:06:05.899357 pmic_efuse_setting: Set efuses in 11 msecs
421 08:06:05.902645 pmwrap_interface_init: Select PMIF_VLD_RDY
422 08:06:05.909848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
423 08:06:05.913482 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
424 08:06:05.916424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
425 08:06:05.923683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
426 08:06:05.926521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
427 08:06:05.933526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
428 08:06:05.936424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
429 08:06:05.943552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
430 08:06:05.946963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
431 08:06:05.950227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
432 08:06:05.957331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
433 08:06:05.960294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
434 08:06:05.966938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
435 08:06:05.972966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
436 08:06:05.976556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
437 08:06:05.983050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
438 08:06:05.989592 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
439 08:06:05.993045 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
440 08:06:05.999624 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
441 08:06:06.006475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
442 08:06:06.009544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
443 08:06:06.016393 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
444 08:06:06.023692 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
445 08:06:06.027616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
446 08:06:06.031769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
447 08:06:06.038506 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
448 08:06:06.045125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
449 08:06:06.048860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
450 08:06:06.051812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
451 08:06:06.059293 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
452 08:06:06.062070 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
453 08:06:06.068756 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
454 08:06:06.072727 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
455 08:06:06.079379 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
456 08:06:06.083536 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
457 08:06:06.089209 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
458 08:06:06.092628 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
459 08:06:06.099446 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
460 08:06:06.102428 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
461 08:06:06.106133 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
462 08:06:06.113594 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
463 08:06:06.116992 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
464 08:06:06.120295 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
465 08:06:06.123523 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
466 08:06:06.130553 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
467 08:06:06.134076 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
468 08:06:06.137213 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
469 08:06:06.140280 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
470 08:06:06.147346 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
471 08:06:06.150626 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
472 08:06:06.154090 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
473 08:06:06.163555 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
474 08:06:06.170386 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
475 08:06:06.176848 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
476 08:06:06.183681 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
477 08:06:06.193500 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
478 08:06:06.196997 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
479 08:06:06.199763 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
480 08:06:06.206758 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 08:06:06.214279 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x35
482 08:06:06.216451 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
483 08:06:06.223828 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
484 08:06:06.227025 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
485 08:06:06.236345 [RTC]rtc_get_frequency_meter,154: input=15, output=834
486 08:06:06.246114 [RTC]rtc_get_frequency_meter,154: input=7, output=709
487 08:06:06.255543 [RTC]rtc_get_frequency_meter,154: input=11, output=772
488 08:06:06.264945 [RTC]rtc_get_frequency_meter,154: input=13, output=803
489 08:06:06.274762 [RTC]rtc_get_frequency_meter,154: input=12, output=788
490 08:06:06.283994 [RTC]rtc_get_frequency_meter,154: input=12, output=788
491 08:06:06.295000 [RTC]rtc_get_frequency_meter,154: input=13, output=803
492 08:06:06.297568 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
493 08:06:06.303766 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
494 08:06:06.307310 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
495 08:06:06.310501 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
496 08:06:06.317628 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
497 08:06:06.321018 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
498 08:06:06.323830 ADC[4]: Raw value=903031 ID=7
499 08:06:06.324277 ADC[3]: Raw value=213652 ID=1
500 08:06:06.327515 RAM Code: 0x71
501 08:06:06.330789 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
502 08:06:06.337122 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
503 08:06:06.343764 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
504 08:06:06.350969 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
505 08:06:06.354408 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
506 08:06:06.357188 in-header: 03 07 00 00 08 00 00 00
507 08:06:06.360232 in-data: aa e4 47 04 13 02 00 00
508 08:06:06.363712 Chrome EC: UHEPI supported
509 08:06:06.370406 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
510 08:06:06.374500 in-header: 03 dd 00 00 08 00 00 00
511 08:06:06.377600 in-data: 90 20 60 08 00 00 00 00
512 08:06:06.380009 MRC: failed to locate region type 0.
513 08:06:06.387367 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
514 08:06:06.390411 DRAM-K: Running full calibration
515 08:06:06.396871 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
516 08:06:06.397422 header.status = 0x0
517 08:06:06.399968 header.version = 0x6 (expected: 0x6)
518 08:06:06.403550 header.size = 0xd00 (expected: 0xd00)
519 08:06:06.406792 header.flags = 0x0
520 08:06:06.413335 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
521 08:06:06.430788 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
522 08:06:06.436835 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
523 08:06:06.440276 dram_init: ddr_geometry: 2
524 08:06:06.443651 [EMI] MDL number = 2
525 08:06:06.444272 [EMI] Get MDL freq = 0
526 08:06:06.447319 dram_init: ddr_type: 0
527 08:06:06.447983 is_discrete_lpddr4: 1
528 08:06:06.450469 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
529 08:06:06.451037
530 08:06:06.451407
531 08:06:06.453821 [Bian_co] ETT version 0.0.0.1
532 08:06:06.460474 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
533 08:06:06.461038
534 08:06:06.463717 dramc_set_vcore_voltage set vcore to 650000
535 08:06:06.464315 Read voltage for 800, 4
536 08:06:06.466971 Vio18 = 0
537 08:06:06.467531 Vcore = 650000
538 08:06:06.467938 Vdram = 0
539 08:06:06.470334 Vddq = 0
540 08:06:06.470903 Vmddr = 0
541 08:06:06.473703 dram_init: config_dvfs: 1
542 08:06:06.477340 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
543 08:06:06.483965 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
544 08:06:06.486818 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
545 08:06:06.490468 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
546 08:06:06.493521 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
547 08:06:06.497382 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
548 08:06:06.500283 MEM_TYPE=3, freq_sel=18
549 08:06:06.503545 sv_algorithm_assistance_LP4_1600
550 08:06:06.506929 ============ PULL DRAM RESETB DOWN ============
551 08:06:06.510076 ========== PULL DRAM RESETB DOWN end =========
552 08:06:06.517089 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
553 08:06:06.520754 ===================================
554 08:06:06.523287 LPDDR4 DRAM CONFIGURATION
555 08:06:06.526703 ===================================
556 08:06:06.527178 EX_ROW_EN[0] = 0x0
557 08:06:06.530466 EX_ROW_EN[1] = 0x0
558 08:06:06.531043 LP4Y_EN = 0x0
559 08:06:06.533629 WORK_FSP = 0x0
560 08:06:06.534216 WL = 0x2
561 08:06:06.537693 RL = 0x2
562 08:06:06.538271 BL = 0x2
563 08:06:06.540197 RPST = 0x0
564 08:06:06.540669 RD_PRE = 0x0
565 08:06:06.543571 WR_PRE = 0x1
566 08:06:06.544252 WR_PST = 0x0
567 08:06:06.546747 DBI_WR = 0x0
568 08:06:06.547338 DBI_RD = 0x0
569 08:06:06.550119 OTF = 0x1
570 08:06:06.553700 ===================================
571 08:06:06.556695 ===================================
572 08:06:06.557297 ANA top config
573 08:06:06.560454 ===================================
574 08:06:06.563316 DLL_ASYNC_EN = 0
575 08:06:06.566740 ALL_SLAVE_EN = 1
576 08:06:06.570222 NEW_RANK_MODE = 1
577 08:06:06.570815 DLL_IDLE_MODE = 1
578 08:06:06.573464 LP45_APHY_COMB_EN = 1
579 08:06:06.576648 TX_ODT_DIS = 1
580 08:06:06.579983 NEW_8X_MODE = 1
581 08:06:06.583614 ===================================
582 08:06:06.586741 ===================================
583 08:06:06.589656 data_rate = 1600
584 08:06:06.590100 CKR = 1
585 08:06:06.593341 DQ_P2S_RATIO = 8
586 08:06:06.596862 ===================================
587 08:06:06.599489 CA_P2S_RATIO = 8
588 08:06:06.603342 DQ_CA_OPEN = 0
589 08:06:06.606398 DQ_SEMI_OPEN = 0
590 08:06:06.609848 CA_SEMI_OPEN = 0
591 08:06:06.610388 CA_FULL_RATE = 0
592 08:06:06.612713 DQ_CKDIV4_EN = 1
593 08:06:06.616203 CA_CKDIV4_EN = 1
594 08:06:06.619670 CA_PREDIV_EN = 0
595 08:06:06.623038 PH8_DLY = 0
596 08:06:06.626764 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
597 08:06:06.627355 DQ_AAMCK_DIV = 4
598 08:06:06.629684 CA_AAMCK_DIV = 4
599 08:06:06.632962 CA_ADMCK_DIV = 4
600 08:06:06.636420 DQ_TRACK_CA_EN = 0
601 08:06:06.639873 CA_PICK = 800
602 08:06:06.643843 CA_MCKIO = 800
603 08:06:06.646784 MCKIO_SEMI = 0
604 08:06:06.647351 PLL_FREQ = 3068
605 08:06:06.649797 DQ_UI_PI_RATIO = 32
606 08:06:06.652689 CA_UI_PI_RATIO = 0
607 08:06:06.656231 ===================================
608 08:06:06.660100 ===================================
609 08:06:06.662981 memory_type:LPDDR4
610 08:06:06.663561 GP_NUM : 10
611 08:06:06.666162 SRAM_EN : 1
612 08:06:06.669349 MD32_EN : 0
613 08:06:06.673520 ===================================
614 08:06:06.674042 [ANA_INIT] >>>>>>>>>>>>>>
615 08:06:06.676178 <<<<<< [CONFIGURE PHASE]: ANA_TX
616 08:06:06.679387 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
617 08:06:06.682902 ===================================
618 08:06:06.686775 data_rate = 1600,PCW = 0X7600
619 08:06:06.689540 ===================================
620 08:06:06.693049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
621 08:06:06.699712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
622 08:06:06.703169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 08:06:06.709358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
624 08:06:06.713177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
625 08:06:06.716215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
626 08:06:06.719040 [ANA_INIT] flow start
627 08:06:06.719511 [ANA_INIT] PLL >>>>>>>>
628 08:06:06.722704 [ANA_INIT] PLL <<<<<<<<
629 08:06:06.726104 [ANA_INIT] MIDPI >>>>>>>>
630 08:06:06.726631 [ANA_INIT] MIDPI <<<<<<<<
631 08:06:06.729254 [ANA_INIT] DLL >>>>>>>>
632 08:06:06.733688 [ANA_INIT] flow end
633 08:06:06.735837 ============ LP4 DIFF to SE enter ============
634 08:06:06.739528 ============ LP4 DIFF to SE exit ============
635 08:06:06.742561 [ANA_INIT] <<<<<<<<<<<<<
636 08:06:06.746570 [Flow] Enable top DCM control >>>>>
637 08:06:06.750003 [Flow] Enable top DCM control <<<<<
638 08:06:06.752476 Enable DLL master slave shuffle
639 08:06:06.756140 ==============================================================
640 08:06:06.759519 Gating Mode config
641 08:06:06.762451 ==============================================================
642 08:06:06.765825 Config description:
643 08:06:06.775934 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
644 08:06:06.782269 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
645 08:06:06.785572 SELPH_MODE 0: By rank 1: By Phase
646 08:06:06.792744 ==============================================================
647 08:06:06.795454 GAT_TRACK_EN = 1
648 08:06:06.798777 RX_GATING_MODE = 2
649 08:06:06.802162 RX_GATING_TRACK_MODE = 2
650 08:06:06.806623 SELPH_MODE = 1
651 08:06:06.809310 PICG_EARLY_EN = 1
652 08:06:06.809739 VALID_LAT_VALUE = 1
653 08:06:06.815572 ==============================================================
654 08:06:06.819692 Enter into Gating configuration >>>>
655 08:06:06.822433 Exit from Gating configuration <<<<
656 08:06:06.825982 Enter into DVFS_PRE_config >>>>>
657 08:06:06.835550 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
658 08:06:06.838868 Exit from DVFS_PRE_config <<<<<
659 08:06:06.842044 Enter into PICG configuration >>>>
660 08:06:06.845927 Exit from PICG configuration <<<<
661 08:06:06.849482 [RX_INPUT] configuration >>>>>
662 08:06:06.852741 [RX_INPUT] configuration <<<<<
663 08:06:06.855908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
664 08:06:06.862559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
665 08:06:06.869596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
666 08:06:06.876369 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
667 08:06:06.879965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
668 08:06:06.886635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
669 08:06:06.890750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
670 08:06:06.893548 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
671 08:06:06.900325 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
672 08:06:06.904620 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
673 08:06:06.908072 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
674 08:06:06.911218 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
675 08:06:06.914573 ===================================
676 08:06:06.919076 LPDDR4 DRAM CONFIGURATION
677 08:06:06.922114 ===================================
678 08:06:06.922703 EX_ROW_EN[0] = 0x0
679 08:06:06.925826 EX_ROW_EN[1] = 0x0
680 08:06:06.926289 LP4Y_EN = 0x0
681 08:06:06.929721 WORK_FSP = 0x0
682 08:06:06.930303 WL = 0x2
683 08:06:06.933115 RL = 0x2
684 08:06:06.933698 BL = 0x2
685 08:06:06.936623 RPST = 0x0
686 08:06:06.937088 RD_PRE = 0x0
687 08:06:06.940626 WR_PRE = 0x1
688 08:06:06.941043 WR_PST = 0x0
689 08:06:06.944223 DBI_WR = 0x0
690 08:06:06.944642 DBI_RD = 0x0
691 08:06:06.944973 OTF = 0x1
692 08:06:06.947998 ===================================
693 08:06:06.951652 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
694 08:06:06.955790 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
695 08:06:06.963487 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 08:06:06.966832 ===================================
697 08:06:06.967377 LPDDR4 DRAM CONFIGURATION
698 08:06:06.970792 ===================================
699 08:06:06.974458 EX_ROW_EN[0] = 0x10
700 08:06:06.975010 EX_ROW_EN[1] = 0x0
701 08:06:06.978413 LP4Y_EN = 0x0
702 08:06:06.978957 WORK_FSP = 0x0
703 08:06:06.981580 WL = 0x2
704 08:06:06.982001 RL = 0x2
705 08:06:06.982331 BL = 0x2
706 08:06:06.985702 RPST = 0x0
707 08:06:06.986245 RD_PRE = 0x0
708 08:06:06.989161 WR_PRE = 0x1
709 08:06:06.989745 WR_PST = 0x0
710 08:06:06.993397 DBI_WR = 0x0
711 08:06:06.993978 DBI_RD = 0x0
712 08:06:06.996407 OTF = 0x1
713 08:06:06.999507 ===================================
714 08:06:07.003118 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
715 08:06:07.008687 nWR fixed to 40
716 08:06:07.009108 [ModeRegInit_LP4] CH0 RK0
717 08:06:07.012787 [ModeRegInit_LP4] CH0 RK1
718 08:06:07.016673 [ModeRegInit_LP4] CH1 RK0
719 08:06:07.017094 [ModeRegInit_LP4] CH1 RK1
720 08:06:07.020608 match AC timing 13
721 08:06:07.023959 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
722 08:06:07.028061 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
723 08:06:07.031031 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
724 08:06:07.038265 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
725 08:06:07.041626 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
726 08:06:07.045293 [EMI DOE] emi_dcm 0
727 08:06:07.048414 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
728 08:06:07.048939 ==
729 08:06:07.052190 Dram Type= 6, Freq= 0, CH_0, rank 0
730 08:06:07.055664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
731 08:06:07.056287 ==
732 08:06:07.061612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
733 08:06:07.068295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
734 08:06:07.076107 [CA 0] Center 37 (7~68) winsize 62
735 08:06:07.080034 [CA 1] Center 37 (6~68) winsize 63
736 08:06:07.083324 [CA 2] Center 34 (4~65) winsize 62
737 08:06:07.086233 [CA 3] Center 34 (4~65) winsize 62
738 08:06:07.090196 [CA 4] Center 33 (3~64) winsize 62
739 08:06:07.092781 [CA 5] Center 33 (3~64) winsize 62
740 08:06:07.093338
741 08:06:07.096304 [CmdBusTrainingLP45] Vref(ca) range 1: 34
742 08:06:07.096900
743 08:06:07.100027 [CATrainingPosCal] consider 1 rank data
744 08:06:07.103031 u2DelayCellTimex100 = 270/100 ps
745 08:06:07.106537 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
746 08:06:07.109453 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
747 08:06:07.112786 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
748 08:06:07.116317 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
749 08:06:07.122696 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
750 08:06:07.126185 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
751 08:06:07.126614
752 08:06:07.130133 CA PerBit enable=1, Macro0, CA PI delay=33
753 08:06:07.130656
754 08:06:07.133618 [CBTSetCACLKResult] CA Dly = 33
755 08:06:07.134140 CS Dly: 7 (0~38)
756 08:06:07.134478 ==
757 08:06:07.136313 Dram Type= 6, Freq= 0, CH_0, rank 1
758 08:06:07.143089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
759 08:06:07.143619 ==
760 08:06:07.146602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
761 08:06:07.153258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
762 08:06:07.162403 [CA 0] Center 37 (6~68) winsize 63
763 08:06:07.165435 [CA 1] Center 37 (7~68) winsize 62
764 08:06:07.169071 [CA 2] Center 34 (4~65) winsize 62
765 08:06:07.172354 [CA 3] Center 34 (4~65) winsize 62
766 08:06:07.175968 [CA 4] Center 33 (3~64) winsize 62
767 08:06:07.178946 [CA 5] Center 33 (3~64) winsize 62
768 08:06:07.179508
769 08:06:07.182024 [CmdBusTrainingLP45] Vref(ca) range 1: 34
770 08:06:07.182496
771 08:06:07.185903 [CATrainingPosCal] consider 2 rank data
772 08:06:07.189008 u2DelayCellTimex100 = 270/100 ps
773 08:06:07.192131 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
774 08:06:07.198465 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
775 08:06:07.202115 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
776 08:06:07.206063 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
777 08:06:07.209510 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
778 08:06:07.212581 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
779 08:06:07.213168
780 08:06:07.216327 CA PerBit enable=1, Macro0, CA PI delay=33
781 08:06:07.216903
782 08:06:07.220068 [CBTSetCACLKResult] CA Dly = 33
783 08:06:07.220659 CS Dly: 7 (0~38)
784 08:06:07.221042
785 08:06:07.224157 ----->DramcWriteLeveling(PI) begin...
786 08:06:07.224607 ==
787 08:06:07.227447 Dram Type= 6, Freq= 0, CH_0, rank 0
788 08:06:07.231012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
789 08:06:07.231471 ==
790 08:06:07.234674 Write leveling (Byte 0): 33 => 33
791 08:06:07.238039 Write leveling (Byte 1): 28 => 28
792 08:06:07.241486 DramcWriteLeveling(PI) end<-----
793 08:06:07.242011
794 08:06:07.242353 ==
795 08:06:07.244628 Dram Type= 6, Freq= 0, CH_0, rank 0
796 08:06:07.247896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 08:06:07.248422 ==
798 08:06:07.251177 [Gating] SW mode calibration
799 08:06:07.257672 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
800 08:06:07.264657 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
801 08:06:07.267853 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
802 08:06:07.270873 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 08:06:07.277477 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
804 08:06:07.280701 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 08:06:07.284193 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 08:06:07.290914 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 08:06:07.294372 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 08:06:07.297382 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 08:06:07.304293 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 08:06:07.307809 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 08:06:07.310609 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 08:06:07.317378 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 08:06:07.320972 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 08:06:07.324032 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 08:06:07.330923 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 08:06:07.334165 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 08:06:07.337506 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 08:06:07.344649 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 08:06:07.347461 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
820 08:06:07.351897 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 08:06:07.358227 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 08:06:07.361066 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 08:06:07.364381 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 08:06:07.367567 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 08:06:07.374378 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 08:06:07.377564 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 08:06:07.380631 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
828 08:06:07.387607 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
829 08:06:07.391317 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 08:06:07.393940 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 08:06:07.401013 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 08:06:07.403894 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 08:06:07.407795 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 08:06:07.414737 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
835 08:06:07.417199 0 10 8 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
836 08:06:07.420528 0 10 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
837 08:06:07.427398 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 08:06:07.430910 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 08:06:07.434085 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 08:06:07.440602 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 08:06:07.444211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 08:06:07.447665 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
843 08:06:07.454283 0 11 8 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
844 08:06:07.457448 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
845 08:06:07.461045 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 08:06:07.467353 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 08:06:07.470457 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 08:06:07.474106 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 08:06:07.480515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 08:06:07.484619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 08:06:07.487186 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
852 08:06:07.493897 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 08:06:07.497328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 08:06:07.500446 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 08:06:07.503441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 08:06:07.510660 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 08:06:07.513664 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 08:06:07.516751 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 08:06:07.523758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 08:06:07.527022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 08:06:07.530334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 08:06:07.536922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 08:06:07.540046 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 08:06:07.543128 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 08:06:07.550030 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 08:06:07.553720 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 08:06:07.557471 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 08:06:07.563392 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 08:06:07.566434 Total UI for P1: 0, mck2ui 16
870 08:06:07.570008 best dqsien dly found for B0: ( 0, 14, 8)
871 08:06:07.570580 Total UI for P1: 0, mck2ui 16
872 08:06:07.576682 best dqsien dly found for B1: ( 0, 14, 10)
873 08:06:07.579934 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
874 08:06:07.582997 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
875 08:06:07.583465
876 08:06:07.586997 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
877 08:06:07.589966 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
878 08:06:07.593966 [Gating] SW calibration Done
879 08:06:07.594690 ==
880 08:06:07.597624 Dram Type= 6, Freq= 0, CH_0, rank 0
881 08:06:07.600596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
882 08:06:07.601131 ==
883 08:06:07.601759 RX Vref Scan: 0
884 08:06:07.605431
885 08:06:07.606143 RX Vref 0 -> 0, step: 1
886 08:06:07.606706
887 08:06:07.608186 RX Delay -130 -> 252, step: 16
888 08:06:07.611893 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
889 08:06:07.615791 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
890 08:06:07.618490 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
891 08:06:07.622277 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
892 08:06:07.626261 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
893 08:06:07.629698 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
894 08:06:07.636870 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
895 08:06:07.641354 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
896 08:06:07.644376 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
897 08:06:07.647990 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
898 08:06:07.651606 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
899 08:06:07.655491 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
900 08:06:07.659121 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
901 08:06:07.662745 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
902 08:06:07.666484 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
903 08:06:07.672981 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
904 08:06:07.673495 ==
905 08:06:07.676921 Dram Type= 6, Freq= 0, CH_0, rank 0
906 08:06:07.679803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 08:06:07.680280 ==
908 08:06:07.680621 DQS Delay:
909 08:06:07.683136 DQS0 = 0, DQS1 = 0
910 08:06:07.683564 DQM Delay:
911 08:06:07.686407 DQM0 = 85, DQM1 = 72
912 08:06:07.686930 DQ Delay:
913 08:06:07.689748 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
914 08:06:07.692924 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
915 08:06:07.696674 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
916 08:06:07.700417 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
917 08:06:07.700942
918 08:06:07.701282
919 08:06:07.701596 ==
920 08:06:07.702864 Dram Type= 6, Freq= 0, CH_0, rank 0
921 08:06:07.706649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 08:06:07.707183 ==
923 08:06:07.707525
924 08:06:07.707900
925 08:06:07.710355 TX Vref Scan disable
926 08:06:07.713695 == TX Byte 0 ==
927 08:06:07.717197 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
928 08:06:07.720811 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
929 08:06:07.721245 == TX Byte 1 ==
930 08:06:07.725109 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
931 08:06:07.731638 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
932 08:06:07.732118 ==
933 08:06:07.734796 Dram Type= 6, Freq= 0, CH_0, rank 0
934 08:06:07.738503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 08:06:07.739027 ==
936 08:06:07.752123 TX Vref=22, minBit 13, minWin=26, winSum=440
937 08:06:07.754884 TX Vref=24, minBit 8, minWin=27, winSum=443
938 08:06:07.758230 TX Vref=26, minBit 8, minWin=27, winSum=445
939 08:06:07.761567 TX Vref=28, minBit 10, minWin=27, winSum=449
940 08:06:07.764651 TX Vref=30, minBit 4, minWin=27, winSum=444
941 08:06:07.771541 TX Vref=32, minBit 10, minWin=27, winSum=448
942 08:06:07.774755 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 28
943 08:06:07.775322
944 08:06:07.778940 Final TX Range 1 Vref 28
945 08:06:07.779510
946 08:06:07.779927 ==
947 08:06:07.781554 Dram Type= 6, Freq= 0, CH_0, rank 0
948 08:06:07.784810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
949 08:06:07.787906 ==
950 08:06:07.788474
951 08:06:07.788846
952 08:06:07.789190 TX Vref Scan disable
953 08:06:07.791841 == TX Byte 0 ==
954 08:06:07.796146 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
955 08:06:07.801637 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
956 08:06:07.802201 == TX Byte 1 ==
957 08:06:07.805338 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
958 08:06:07.812192 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
959 08:06:07.812782
960 08:06:07.813158 [DATLAT]
961 08:06:07.813502 Freq=800, CH0 RK0
962 08:06:07.813832
963 08:06:07.814638 DATLAT Default: 0xa
964 08:06:07.815106 0, 0xFFFF, sum = 0
965 08:06:07.817938 1, 0xFFFF, sum = 0
966 08:06:07.821784 2, 0xFFFF, sum = 0
967 08:06:07.822357 3, 0xFFFF, sum = 0
968 08:06:07.825140 4, 0xFFFF, sum = 0
969 08:06:07.825712 5, 0xFFFF, sum = 0
970 08:06:07.828279 6, 0xFFFF, sum = 0
971 08:06:07.828756 7, 0xFFFF, sum = 0
972 08:06:07.831618 8, 0xFFFF, sum = 0
973 08:06:07.832326 9, 0x0, sum = 1
974 08:06:07.834596 10, 0x0, sum = 2
975 08:06:07.835068 11, 0x0, sum = 3
976 08:06:07.835445 12, 0x0, sum = 4
977 08:06:07.838602 best_step = 10
978 08:06:07.839159
979 08:06:07.839530 ==
980 08:06:07.841670 Dram Type= 6, Freq= 0, CH_0, rank 0
981 08:06:07.844707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
982 08:06:07.845177 ==
983 08:06:07.847928 RX Vref Scan: 1
984 08:06:07.848396
985 08:06:07.851448 Set Vref Range= 32 -> 127
986 08:06:07.852069
987 08:06:07.852449 RX Vref 32 -> 127, step: 1
988 08:06:07.852795
989 08:06:07.855718 RX Delay -111 -> 252, step: 8
990 08:06:07.856243
991 08:06:07.858499 Set Vref, RX VrefLevel [Byte0]: 32
992 08:06:07.861417 [Byte1]: 32
993 08:06:07.864366
994 08:06:07.864833 Set Vref, RX VrefLevel [Byte0]: 33
995 08:06:07.868189 [Byte1]: 33
996 08:06:07.872196
997 08:06:07.872762 Set Vref, RX VrefLevel [Byte0]: 34
998 08:06:07.875828 [Byte1]: 34
999 08:06:07.880161
1000 08:06:07.880727 Set Vref, RX VrefLevel [Byte0]: 35
1001 08:06:07.883086 [Byte1]: 35
1002 08:06:07.887874
1003 08:06:07.888341 Set Vref, RX VrefLevel [Byte0]: 36
1004 08:06:07.891126 [Byte1]: 36
1005 08:06:07.895838
1006 08:06:07.896357 Set Vref, RX VrefLevel [Byte0]: 37
1007 08:06:07.899148 [Byte1]: 37
1008 08:06:07.903121
1009 08:06:07.903579 Set Vref, RX VrefLevel [Byte0]: 38
1010 08:06:07.906100 [Byte1]: 38
1011 08:06:07.910574
1012 08:06:07.911096 Set Vref, RX VrefLevel [Byte0]: 39
1013 08:06:07.913692 [Byte1]: 39
1014 08:06:07.917917
1015 08:06:07.918468 Set Vref, RX VrefLevel [Byte0]: 40
1016 08:06:07.921527 [Byte1]: 40
1017 08:06:07.925737
1018 08:06:07.926259 Set Vref, RX VrefLevel [Byte0]: 41
1019 08:06:07.929403 [Byte1]: 41
1020 08:06:07.933436
1021 08:06:07.933861 Set Vref, RX VrefLevel [Byte0]: 42
1022 08:06:07.936303 [Byte1]: 42
1023 08:06:07.941487
1024 08:06:07.942006 Set Vref, RX VrefLevel [Byte0]: 43
1025 08:06:07.944193 [Byte1]: 43
1026 08:06:07.949388
1027 08:06:07.949901 Set Vref, RX VrefLevel [Byte0]: 44
1028 08:06:07.952096 [Byte1]: 44
1029 08:06:07.956458
1030 08:06:07.956975 Set Vref, RX VrefLevel [Byte0]: 45
1031 08:06:07.959844 [Byte1]: 45
1032 08:06:07.964272
1033 08:06:07.964790 Set Vref, RX VrefLevel [Byte0]: 46
1034 08:06:07.967255 [Byte1]: 46
1035 08:06:07.971543
1036 08:06:07.972142 Set Vref, RX VrefLevel [Byte0]: 47
1037 08:06:07.974938 [Byte1]: 47
1038 08:06:07.979188
1039 08:06:07.979705 Set Vref, RX VrefLevel [Byte0]: 48
1040 08:06:07.983035 [Byte1]: 48
1041 08:06:07.987116
1042 08:06:07.987538 Set Vref, RX VrefLevel [Byte0]: 49
1043 08:06:07.990255 [Byte1]: 49
1044 08:06:07.994882
1045 08:06:07.995436 Set Vref, RX VrefLevel [Byte0]: 50
1046 08:06:07.997708 [Byte1]: 50
1047 08:06:08.002220
1048 08:06:08.002792 Set Vref, RX VrefLevel [Byte0]: 51
1049 08:06:08.005734 [Byte1]: 51
1050 08:06:08.009822
1051 08:06:08.010382 Set Vref, RX VrefLevel [Byte0]: 52
1052 08:06:08.013076 [Byte1]: 52
1053 08:06:08.017561
1054 08:06:08.018123 Set Vref, RX VrefLevel [Byte0]: 53
1055 08:06:08.020516 [Byte1]: 53
1056 08:06:08.025041
1057 08:06:08.025598 Set Vref, RX VrefLevel [Byte0]: 54
1058 08:06:08.028453 [Byte1]: 54
1059 08:06:08.032978
1060 08:06:08.033545 Set Vref, RX VrefLevel [Byte0]: 55
1061 08:06:08.036065 [Byte1]: 55
1062 08:06:08.041162
1063 08:06:08.041717 Set Vref, RX VrefLevel [Byte0]: 56
1064 08:06:08.043758 [Byte1]: 56
1065 08:06:08.048079
1066 08:06:08.048641 Set Vref, RX VrefLevel [Byte0]: 57
1067 08:06:08.051819 [Byte1]: 57
1068 08:06:08.055886
1069 08:06:08.056439 Set Vref, RX VrefLevel [Byte0]: 58
1070 08:06:08.059071 [Byte1]: 58
1071 08:06:08.063348
1072 08:06:08.063966 Set Vref, RX VrefLevel [Byte0]: 59
1073 08:06:08.066600 [Byte1]: 59
1074 08:06:08.071031
1075 08:06:08.071587 Set Vref, RX VrefLevel [Byte0]: 60
1076 08:06:08.074160 [Byte1]: 60
1077 08:06:08.079764
1078 08:06:08.080347 Set Vref, RX VrefLevel [Byte0]: 61
1079 08:06:08.082286 [Byte1]: 61
1080 08:06:08.086509
1081 08:06:08.087071 Set Vref, RX VrefLevel [Byte0]: 62
1082 08:06:08.089502 [Byte1]: 62
1083 08:06:08.094016
1084 08:06:08.094575 Set Vref, RX VrefLevel [Byte0]: 63
1085 08:06:08.097095 [Byte1]: 63
1086 08:06:08.101441
1087 08:06:08.102002 Set Vref, RX VrefLevel [Byte0]: 64
1088 08:06:08.104894 [Byte1]: 64
1089 08:06:08.109666
1090 08:06:08.110236 Set Vref, RX VrefLevel [Byte0]: 65
1091 08:06:08.113848 [Byte1]: 65
1092 08:06:08.117250
1093 08:06:08.117809 Set Vref, RX VrefLevel [Byte0]: 66
1094 08:06:08.120729 [Byte1]: 66
1095 08:06:08.124477
1096 08:06:08.124942 Set Vref, RX VrefLevel [Byte0]: 67
1097 08:06:08.128413 [Byte1]: 67
1098 08:06:08.132255
1099 08:06:08.132717 Set Vref, RX VrefLevel [Byte0]: 68
1100 08:06:08.136271 [Byte1]: 68
1101 08:06:08.140569
1102 08:06:08.141069 Set Vref, RX VrefLevel [Byte0]: 69
1103 08:06:08.143607 [Byte1]: 69
1104 08:06:08.147952
1105 08:06:08.148372 Set Vref, RX VrefLevel [Byte0]: 70
1106 08:06:08.150886 [Byte1]: 70
1107 08:06:08.154706
1108 08:06:08.158432 Set Vref, RX VrefLevel [Byte0]: 71
1109 08:06:08.158856 [Byte1]: 71
1110 08:06:08.163229
1111 08:06:08.163660 Set Vref, RX VrefLevel [Byte0]: 72
1112 08:06:08.166445 [Byte1]: 72
1113 08:06:08.170829
1114 08:06:08.171244 Set Vref, RX VrefLevel [Byte0]: 73
1115 08:06:08.174037 [Byte1]: 73
1116 08:06:08.178570
1117 08:06:08.179111 Set Vref, RX VrefLevel [Byte0]: 74
1118 08:06:08.181361 [Byte1]: 74
1119 08:06:08.185425
1120 08:06:08.185838 Set Vref, RX VrefLevel [Byte0]: 75
1121 08:06:08.189070 [Byte1]: 75
1122 08:06:08.193661
1123 08:06:08.194169 Set Vref, RX VrefLevel [Byte0]: 76
1124 08:06:08.196609 [Byte1]: 76
1125 08:06:08.201053
1126 08:06:08.201470 Set Vref, RX VrefLevel [Byte0]: 77
1127 08:06:08.204408 [Byte1]: 77
1128 08:06:08.208329
1129 08:06:08.208751 Set Vref, RX VrefLevel [Byte0]: 78
1130 08:06:08.211963 [Byte1]: 78
1131 08:06:08.216533
1132 08:06:08.219371 Set Vref, RX VrefLevel [Byte0]: 79
1133 08:06:08.219835 [Byte1]: 79
1134 08:06:08.223920
1135 08:06:08.227246 Set Vref, RX VrefLevel [Byte0]: 80
1136 08:06:08.227827 [Byte1]: 80
1137 08:06:08.232271
1138 08:06:08.232782 Set Vref, RX VrefLevel [Byte0]: 81
1139 08:06:08.234887 [Byte1]: 81
1140 08:06:08.239511
1141 08:06:08.240073 Final RX Vref Byte 0 = 68 to rank0
1142 08:06:08.242504 Final RX Vref Byte 1 = 58 to rank0
1143 08:06:08.246645 Final RX Vref Byte 0 = 68 to rank1
1144 08:06:08.250166 Final RX Vref Byte 1 = 58 to rank1==
1145 08:06:08.253526 Dram Type= 6, Freq= 0, CH_0, rank 0
1146 08:06:08.257240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 08:06:08.257672 ==
1148 08:06:08.260874 DQS Delay:
1149 08:06:08.261289 DQS0 = 0, DQS1 = 0
1150 08:06:08.261615 DQM Delay:
1151 08:06:08.264047 DQM0 = 89, DQM1 = 75
1152 08:06:08.264642 DQ Delay:
1153 08:06:08.267405 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1154 08:06:08.270753 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1155 08:06:08.274748 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1156 08:06:08.278828 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1157 08:06:08.279443
1158 08:06:08.279831
1159 08:06:08.285841 [DQSOSCAuto] RK0, (LSB)MR18= 0x4425, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1160 08:06:08.289179 CH0 RK0: MR19=606, MR18=4425
1161 08:06:08.296336 CH0_RK0: MR19=0x606, MR18=0x4425, DQSOSC=392, MR23=63, INC=96, DEC=64
1162 08:06:08.296874
1163 08:06:08.299873 ----->DramcWriteLeveling(PI) begin...
1164 08:06:08.300413 ==
1165 08:06:08.303390 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 08:06:08.307168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1167 08:06:08.307661 ==
1168 08:06:08.310736 Write leveling (Byte 0): 33 => 33
1169 08:06:08.314751 Write leveling (Byte 1): 29 => 29
1170 08:06:08.315369 DramcWriteLeveling(PI) end<-----
1171 08:06:08.315718
1172 08:06:08.316121 ==
1173 08:06:08.318401 Dram Type= 6, Freq= 0, CH_0, rank 1
1174 08:06:08.321173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 08:06:08.324784 ==
1176 08:06:08.325208 [Gating] SW mode calibration
1177 08:06:08.369815 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1178 08:06:08.370731 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1179 08:06:08.371144 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1180 08:06:08.371564 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1181 08:06:08.371985 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1182 08:06:08.372389 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 08:06:08.372729 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 08:06:08.373055 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 08:06:08.373372 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 08:06:08.413702 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 08:06:08.414271 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 08:06:08.414979 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 08:06:08.415354 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 08:06:08.415695 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 08:06:08.416131 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 08:06:08.416463 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 08:06:08.416837 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 08:06:08.417164 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 08:06:08.417532 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 08:06:08.457289 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1197 08:06:08.458187 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1198 08:06:08.458639 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1199 08:06:08.458997 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 08:06:08.459392 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 08:06:08.459773 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 08:06:08.460180 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 08:06:08.460506 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 08:06:08.460816 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 08:06:08.461123 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1206 08:06:08.492385 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1207 08:06:08.493173 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 08:06:08.493669 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 08:06:08.494027 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 08:06:08.494366 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 08:06:08.495027 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 08:06:08.495393 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1213 08:06:08.495719 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
1214 08:06:08.496283 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1215 08:06:08.500423 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 08:06:08.507429 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 08:06:08.510928 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 08:06:08.514641 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 08:06:08.517429 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 08:06:08.524691 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1221 08:06:08.528169 0 11 8 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (1 1)
1222 08:06:08.531925 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
1223 08:06:08.535694 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 08:06:08.539208 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 08:06:08.543636 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 08:06:08.550819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 08:06:08.554294 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 08:06:08.557509 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 08:06:08.561348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1230 08:06:08.569401 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 08:06:08.572977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 08:06:08.576163 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 08:06:08.579913 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 08:06:08.582788 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 08:06:08.590775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 08:06:08.594011 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 08:06:08.597751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 08:06:08.601561 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 08:06:08.605215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 08:06:08.612359 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 08:06:08.616090 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 08:06:08.619608 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 08:06:08.623005 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 08:06:08.629614 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1245 08:06:08.632552 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1246 08:06:08.636009 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 08:06:08.639461 Total UI for P1: 0, mck2ui 16
1248 08:06:08.642886 best dqsien dly found for B0: ( 0, 14, 6)
1249 08:06:08.646761 Total UI for P1: 0, mck2ui 16
1250 08:06:08.649399 best dqsien dly found for B1: ( 0, 14, 10)
1251 08:06:08.652463 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1252 08:06:08.655960 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1253 08:06:08.656510
1254 08:06:08.662709 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1255 08:06:08.666259 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1256 08:06:08.666819 [Gating] SW calibration Done
1257 08:06:08.670021 ==
1258 08:06:08.672433 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 08:06:08.676688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 08:06:08.677247 ==
1261 08:06:08.677615 RX Vref Scan: 0
1262 08:06:08.677957
1263 08:06:08.680105 RX Vref 0 -> 0, step: 1
1264 08:06:08.680660
1265 08:06:08.683401 RX Delay -130 -> 252, step: 16
1266 08:06:08.685885 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1267 08:06:08.689201 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1268 08:06:08.692620 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1269 08:06:08.699251 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1270 08:06:08.703218 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1271 08:06:08.705856 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1272 08:06:08.708926 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1273 08:06:08.715541 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1274 08:06:08.718922 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1275 08:06:08.722187 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1276 08:06:08.725201 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1277 08:06:08.728978 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1278 08:06:08.735820 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1279 08:06:08.738687 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1280 08:06:08.742167 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1281 08:06:08.745537 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1282 08:06:08.746090 ==
1283 08:06:08.748640 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 08:06:08.755383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 08:06:08.755988 ==
1286 08:06:08.756359 DQS Delay:
1287 08:06:08.759054 DQS0 = 0, DQS1 = 0
1288 08:06:08.759607 DQM Delay:
1289 08:06:08.760037 DQM0 = 86, DQM1 = 77
1290 08:06:08.761962 DQ Delay:
1291 08:06:08.765389 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1292 08:06:08.768754 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1293 08:06:08.772227 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1294 08:06:08.775290 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1295 08:06:08.775900
1296 08:06:08.776271
1297 08:06:08.776607 ==
1298 08:06:08.778947 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 08:06:08.782260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 08:06:08.782820 ==
1301 08:06:08.783188
1302 08:06:08.783525
1303 08:06:08.785273 TX Vref Scan disable
1304 08:06:08.785731 == TX Byte 0 ==
1305 08:06:08.792291 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1306 08:06:08.795398 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1307 08:06:08.795988 == TX Byte 1 ==
1308 08:06:08.802370 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1309 08:06:08.805707 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1310 08:06:08.806304 ==
1311 08:06:08.808315 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 08:06:08.811917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 08:06:08.812377 ==
1314 08:06:08.826052 TX Vref=22, minBit 1, minWin=27, winSum=442
1315 08:06:08.829320 TX Vref=24, minBit 9, minWin=27, winSum=447
1316 08:06:08.833142 TX Vref=26, minBit 9, minWin=27, winSum=448
1317 08:06:08.836032 TX Vref=28, minBit 8, minWin=27, winSum=448
1318 08:06:08.839000 TX Vref=30, minBit 9, minWin=27, winSum=448
1319 08:06:08.846111 TX Vref=32, minBit 4, minWin=27, winSum=443
1320 08:06:08.849727 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 26
1321 08:06:08.850040
1322 08:06:08.852423 Final TX Range 1 Vref 26
1323 08:06:08.852654
1324 08:06:08.852834 ==
1325 08:06:08.856335 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 08:06:08.859120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 08:06:08.862371 ==
1328 08:06:08.862733
1329 08:06:08.862950
1330 08:06:08.863147 TX Vref Scan disable
1331 08:06:08.866154 == TX Byte 0 ==
1332 08:06:08.869820 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1333 08:06:08.873484 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1334 08:06:08.876622 == TX Byte 1 ==
1335 08:06:08.879929 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1336 08:06:08.883318 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1337 08:06:08.886479
1338 08:06:08.886931 [DATLAT]
1339 08:06:08.887290 Freq=800, CH0 RK1
1340 08:06:08.887631
1341 08:06:08.890300 DATLAT Default: 0xa
1342 08:06:08.890806 0, 0xFFFF, sum = 0
1343 08:06:08.892995 1, 0xFFFF, sum = 0
1344 08:06:08.893455 2, 0xFFFF, sum = 0
1345 08:06:08.896481 3, 0xFFFF, sum = 0
1346 08:06:08.897058 4, 0xFFFF, sum = 0
1347 08:06:08.900447 5, 0xFFFF, sum = 0
1348 08:06:08.903210 6, 0xFFFF, sum = 0
1349 08:06:08.903815 7, 0xFFFF, sum = 0
1350 08:06:08.906204 8, 0xFFFF, sum = 0
1351 08:06:08.906766 9, 0x0, sum = 1
1352 08:06:08.907137 10, 0x0, sum = 2
1353 08:06:08.909816 11, 0x0, sum = 3
1354 08:06:08.910378 12, 0x0, sum = 4
1355 08:06:08.913196 best_step = 10
1356 08:06:08.913750
1357 08:06:08.914110 ==
1358 08:06:08.916501 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 08:06:08.919560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 08:06:08.920199 ==
1361 08:06:08.923434 RX Vref Scan: 0
1362 08:06:08.924083
1363 08:06:08.924541 RX Vref 0 -> 0, step: 1
1364 08:06:08.926012
1365 08:06:08.926463 RX Delay -111 -> 252, step: 8
1366 08:06:08.933647 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1367 08:06:08.936498 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1368 08:06:08.940202 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1369 08:06:08.943552 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1370 08:06:08.946440 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1371 08:06:08.953141 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1372 08:06:08.956645 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1373 08:06:08.959961 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1374 08:06:08.963230 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1375 08:06:08.967455 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1376 08:06:08.972955 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1377 08:06:08.976671 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1378 08:06:08.979803 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1379 08:06:08.983380 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1380 08:06:08.989808 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1381 08:06:08.993584 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1382 08:06:08.994138 ==
1383 08:06:08.996154 Dram Type= 6, Freq= 0, CH_0, rank 1
1384 08:06:08.999622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 08:06:09.000247 ==
1386 08:06:09.000618 DQS Delay:
1387 08:06:09.003109 DQS0 = 0, DQS1 = 0
1388 08:06:09.003562 DQM Delay:
1389 08:06:09.006919 DQM0 = 86, DQM1 = 77
1390 08:06:09.007388 DQ Delay:
1391 08:06:09.009508 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =84
1392 08:06:09.013520 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1393 08:06:09.016647 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1394 08:06:09.019688 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1395 08:06:09.020331
1396 08:06:09.020880
1397 08:06:09.029444 [DQSOSCAuto] RK1, (LSB)MR18= 0x460c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
1398 08:06:09.029923 CH0 RK1: MR19=606, MR18=460C
1399 08:06:09.036413 CH0_RK1: MR19=0x606, MR18=0x460C, DQSOSC=392, MR23=63, INC=96, DEC=64
1400 08:06:09.039650 [RxdqsGatingPostProcess] freq 800
1401 08:06:09.046626 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1402 08:06:09.049832 Pre-setting of DQS Precalculation
1403 08:06:09.052608 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1404 08:06:09.053071 ==
1405 08:06:09.056065 Dram Type= 6, Freq= 0, CH_1, rank 0
1406 08:06:09.059908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 08:06:09.062814 ==
1408 08:06:09.066900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 08:06:09.072998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 08:06:09.081598 [CA 0] Center 36 (6~67) winsize 62
1411 08:06:09.085028 [CA 1] Center 36 (6~67) winsize 62
1412 08:06:09.088521 [CA 2] Center 34 (4~65) winsize 62
1413 08:06:09.091599 [CA 3] Center 34 (3~65) winsize 63
1414 08:06:09.094848 [CA 4] Center 34 (4~65) winsize 62
1415 08:06:09.098747 [CA 5] Center 34 (3~65) winsize 63
1416 08:06:09.099323
1417 08:06:09.101149 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1418 08:06:09.101612
1419 08:06:09.104915 [CATrainingPosCal] consider 1 rank data
1420 08:06:09.108061 u2DelayCellTimex100 = 270/100 ps
1421 08:06:09.111988 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 08:06:09.118323 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 08:06:09.120989 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 08:06:09.124489 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1425 08:06:09.127623 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 08:06:09.131001 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1427 08:06:09.131476
1428 08:06:09.134599 CA PerBit enable=1, Macro0, CA PI delay=34
1429 08:06:09.135173
1430 08:06:09.137875 [CBTSetCACLKResult] CA Dly = 34
1431 08:06:09.141418 CS Dly: 5 (0~36)
1432 08:06:09.141988 ==
1433 08:06:09.144529 Dram Type= 6, Freq= 0, CH_1, rank 1
1434 08:06:09.147619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 08:06:09.148159 ==
1436 08:06:09.154620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 08:06:09.157194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 08:06:09.167907 [CA 0] Center 36 (6~67) winsize 62
1439 08:06:09.170719 [CA 1] Center 37 (7~68) winsize 62
1440 08:06:09.174008 [CA 2] Center 34 (4~65) winsize 62
1441 08:06:09.177858 [CA 3] Center 34 (3~65) winsize 63
1442 08:06:09.180892 [CA 4] Center 34 (4~65) winsize 62
1443 08:06:09.184375 [CA 5] Center 34 (3~65) winsize 63
1444 08:06:09.185193
1445 08:06:09.187610 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1446 08:06:09.188157
1447 08:06:09.190827 [CATrainingPosCal] consider 2 rank data
1448 08:06:09.193953 u2DelayCellTimex100 = 270/100 ps
1449 08:06:09.197833 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 08:06:09.200945 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1451 08:06:09.207903 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 08:06:09.211544 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1453 08:06:09.214325 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 08:06:09.217984 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 08:06:09.218503
1456 08:06:09.221171 CA PerBit enable=1, Macro0, CA PI delay=34
1457 08:06:09.221585
1458 08:06:09.224747 [CBTSetCACLKResult] CA Dly = 34
1459 08:06:09.225282 CS Dly: 6 (0~38)
1460 08:06:09.225617
1461 08:06:09.227670 ----->DramcWriteLeveling(PI) begin...
1462 08:06:09.230956 ==
1463 08:06:09.234260 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 08:06:09.238285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 08:06:09.238803 ==
1466 08:06:09.242085 Write leveling (Byte 0): 30 => 30
1467 08:06:09.244046 Write leveling (Byte 1): 30 => 30
1468 08:06:09.247908 DramcWriteLeveling(PI) end<-----
1469 08:06:09.248421
1470 08:06:09.248750 ==
1471 08:06:09.251306 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 08:06:09.254340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1473 08:06:09.254854 ==
1474 08:06:09.257663 [Gating] SW mode calibration
1475 08:06:09.264405 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1476 08:06:09.267885 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1477 08:06:09.274097 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1478 08:06:09.277406 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1479 08:06:09.280831 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1480 08:06:09.287613 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 08:06:09.291052 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 08:06:09.294810 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 08:06:09.300603 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 08:06:09.303639 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 08:06:09.307431 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 08:06:09.313917 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 08:06:09.317300 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 08:06:09.320650 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 08:06:09.327485 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 08:06:09.330344 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 08:06:09.333584 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 08:06:09.340629 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 08:06:09.343576 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1494 08:06:09.347193 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1495 08:06:09.353710 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1496 08:06:09.356658 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 08:06:09.360210 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 08:06:09.366925 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 08:06:09.370754 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 08:06:09.373638 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 08:06:09.380088 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 08:06:09.383609 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 08:06:09.386544 0 9 8 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
1504 08:06:09.393525 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 08:06:09.396566 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 08:06:09.400400 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 08:06:09.406523 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 08:06:09.409850 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 08:06:09.413369 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1510 08:06:09.419487 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 0)
1511 08:06:09.423243 0 10 8 | B1->B0 | 2525 2424 | 1 0 | (1 0) (0 0)
1512 08:06:09.426354 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 08:06:09.432887 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 08:06:09.436187 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 08:06:09.439929 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 08:06:09.446985 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 08:06:09.450163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 08:06:09.452633 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1519 08:06:09.459883 0 11 8 | B1->B0 | 3a3a 3e3e | 0 0 | (0 0) (1 1)
1520 08:06:09.463086 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 08:06:09.466471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 08:06:09.472821 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 08:06:09.476485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 08:06:09.479253 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 08:06:09.485749 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1526 08:06:09.489032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1527 08:06:09.492481 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 08:06:09.500118 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 08:06:09.502439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 08:06:09.506045 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 08:06:09.509542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 08:06:09.516368 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 08:06:09.519587 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 08:06:09.522454 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 08:06:09.529208 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 08:06:09.532281 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 08:06:09.535700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 08:06:09.542254 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 08:06:09.546074 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 08:06:09.549446 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 08:06:09.555476 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 08:06:09.559232 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 08:06:09.562603 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 08:06:09.565912 Total UI for P1: 0, mck2ui 16
1545 08:06:09.569826 best dqsien dly found for B0: ( 0, 14, 6)
1546 08:06:09.572494 Total UI for P1: 0, mck2ui 16
1547 08:06:09.576202 best dqsien dly found for B1: ( 0, 14, 6)
1548 08:06:09.579445 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1549 08:06:09.582502 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1550 08:06:09.583052
1551 08:06:09.589459 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1552 08:06:09.592449 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1553 08:06:09.593006 [Gating] SW calibration Done
1554 08:06:09.595875 ==
1555 08:06:09.599033 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 08:06:09.602001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 08:06:09.602557 ==
1558 08:06:09.602917 RX Vref Scan: 0
1559 08:06:09.603253
1560 08:06:09.605544 RX Vref 0 -> 0, step: 1
1561 08:06:09.606268
1562 08:06:09.609022 RX Delay -130 -> 252, step: 16
1563 08:06:09.611892 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1564 08:06:09.615573 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1565 08:06:09.621865 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1566 08:06:09.625869 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1567 08:06:09.628884 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1568 08:06:09.632052 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1569 08:06:09.635859 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1570 08:06:09.642410 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1571 08:06:09.645653 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1572 08:06:09.648810 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1573 08:06:09.652111 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1574 08:06:09.655193 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1575 08:06:09.661980 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1576 08:06:09.665183 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1577 08:06:09.668657 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1578 08:06:09.671888 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1579 08:06:09.672439 ==
1580 08:06:09.675491 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 08:06:09.678502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 08:06:09.681905 ==
1583 08:06:09.682454 DQS Delay:
1584 08:06:09.682816 DQS0 = 0, DQS1 = 0
1585 08:06:09.686063 DQM Delay:
1586 08:06:09.686680 DQM0 = 89, DQM1 = 78
1587 08:06:09.688359 DQ Delay:
1588 08:06:09.691714 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1589 08:06:09.695239 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1590 08:06:09.699213 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1591 08:06:09.701784 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1592 08:06:09.702333
1593 08:06:09.702694
1594 08:06:09.703028 ==
1595 08:06:09.705660 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 08:06:09.708540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 08:06:09.708998 ==
1598 08:06:09.709357
1599 08:06:09.709722
1600 08:06:09.712041 TX Vref Scan disable
1601 08:06:09.712589 == TX Byte 0 ==
1602 08:06:09.718599 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1603 08:06:09.721695 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1604 08:06:09.722254 == TX Byte 1 ==
1605 08:06:09.728481 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 08:06:09.732137 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 08:06:09.732596 ==
1608 08:06:09.735152 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 08:06:09.738517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 08:06:09.738972 ==
1611 08:06:09.752786 TX Vref=22, minBit 11, minWin=26, winSum=440
1612 08:06:09.755983 TX Vref=24, minBit 10, minWin=26, winSum=440
1613 08:06:09.758961 TX Vref=26, minBit 8, minWin=27, winSum=451
1614 08:06:09.762399 TX Vref=28, minBit 9, minWin=27, winSum=448
1615 08:06:09.765842 TX Vref=30, minBit 9, minWin=27, winSum=447
1616 08:06:09.772523 TX Vref=32, minBit 9, minWin=27, winSum=443
1617 08:06:09.775255 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 26
1618 08:06:09.775784
1619 08:06:09.778781 Final TX Range 1 Vref 26
1620 08:06:09.779235
1621 08:06:09.779632 ==
1622 08:06:09.782017 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 08:06:09.785158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 08:06:09.788214 ==
1625 08:06:09.788669
1626 08:06:09.789020
1627 08:06:09.789345 TX Vref Scan disable
1628 08:06:09.792137 == TX Byte 0 ==
1629 08:06:09.795623 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1630 08:06:09.802127 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1631 08:06:09.802682 == TX Byte 1 ==
1632 08:06:09.806561 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1633 08:06:09.812467 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1634 08:06:09.813025
1635 08:06:09.813388 [DATLAT]
1636 08:06:09.813721 Freq=800, CH1 RK0
1637 08:06:09.814046
1638 08:06:09.816207 DATLAT Default: 0xa
1639 08:06:09.816786 0, 0xFFFF, sum = 0
1640 08:06:09.818845 1, 0xFFFF, sum = 0
1641 08:06:09.819396 2, 0xFFFF, sum = 0
1642 08:06:09.821875 3, 0xFFFF, sum = 0
1643 08:06:09.825358 4, 0xFFFF, sum = 0
1644 08:06:09.825827 5, 0xFFFF, sum = 0
1645 08:06:09.828705 6, 0xFFFF, sum = 0
1646 08:06:09.829308 7, 0xFFFF, sum = 0
1647 08:06:09.831808 8, 0xFFFF, sum = 0
1648 08:06:09.832267 9, 0x0, sum = 1
1649 08:06:09.835540 10, 0x0, sum = 2
1650 08:06:09.836080 11, 0x0, sum = 3
1651 08:06:09.836455 12, 0x0, sum = 4
1652 08:06:09.838355 best_step = 10
1653 08:06:09.838806
1654 08:06:09.839164 ==
1655 08:06:09.842291 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 08:06:09.844915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 08:06:09.845404 ==
1658 08:06:09.849149 RX Vref Scan: 1
1659 08:06:09.849706
1660 08:06:09.852388 Set Vref Range= 32 -> 127
1661 08:06:09.852842
1662 08:06:09.853268 RX Vref 32 -> 127, step: 1
1663 08:06:09.853623
1664 08:06:09.854960 RX Delay -95 -> 252, step: 8
1665 08:06:09.855443
1666 08:06:09.858503 Set Vref, RX VrefLevel [Byte0]: 32
1667 08:06:09.862053 [Byte1]: 32
1668 08:06:09.865545
1669 08:06:09.866108 Set Vref, RX VrefLevel [Byte0]: 33
1670 08:06:09.868302 [Byte1]: 33
1671 08:06:09.872403
1672 08:06:09.872956 Set Vref, RX VrefLevel [Byte0]: 34
1673 08:06:09.875843 [Byte1]: 34
1674 08:06:09.880497
1675 08:06:09.881052 Set Vref, RX VrefLevel [Byte0]: 35
1676 08:06:09.884178 [Byte1]: 35
1677 08:06:09.887424
1678 08:06:09.887928 Set Vref, RX VrefLevel [Byte0]: 36
1679 08:06:09.891292 [Byte1]: 36
1680 08:06:09.895219
1681 08:06:09.895815 Set Vref, RX VrefLevel [Byte0]: 37
1682 08:06:09.898546 [Byte1]: 37
1683 08:06:09.903300
1684 08:06:09.903923 Set Vref, RX VrefLevel [Byte0]: 38
1685 08:06:09.906486 [Byte1]: 38
1686 08:06:09.910226
1687 08:06:09.910677 Set Vref, RX VrefLevel [Byte0]: 39
1688 08:06:09.913716 [Byte1]: 39
1689 08:06:09.917946
1690 08:06:09.918508 Set Vref, RX VrefLevel [Byte0]: 40
1691 08:06:09.921390 [Byte1]: 40
1692 08:06:09.926207
1693 08:06:09.926766 Set Vref, RX VrefLevel [Byte0]: 41
1694 08:06:09.928802 [Byte1]: 41
1695 08:06:09.933137
1696 08:06:09.933598 Set Vref, RX VrefLevel [Byte0]: 42
1697 08:06:09.936485 [Byte1]: 42
1698 08:06:09.940952
1699 08:06:09.941502 Set Vref, RX VrefLevel [Byte0]: 43
1700 08:06:09.944534 [Byte1]: 43
1701 08:06:09.948619
1702 08:06:09.949171 Set Vref, RX VrefLevel [Byte0]: 44
1703 08:06:09.951886 [Byte1]: 44
1704 08:06:09.956397
1705 08:06:09.956949 Set Vref, RX VrefLevel [Byte0]: 45
1706 08:06:09.959612 [Byte1]: 45
1707 08:06:09.963636
1708 08:06:09.964315 Set Vref, RX VrefLevel [Byte0]: 46
1709 08:06:09.967363 [Byte1]: 46
1710 08:06:09.971272
1711 08:06:09.971886 Set Vref, RX VrefLevel [Byte0]: 47
1712 08:06:09.974793 [Byte1]: 47
1713 08:06:09.978914
1714 08:06:09.979468 Set Vref, RX VrefLevel [Byte0]: 48
1715 08:06:09.982331 [Byte1]: 48
1716 08:06:09.986378
1717 08:06:09.986926 Set Vref, RX VrefLevel [Byte0]: 49
1718 08:06:09.989893 [Byte1]: 49
1719 08:06:09.994267
1720 08:06:09.994817 Set Vref, RX VrefLevel [Byte0]: 50
1721 08:06:09.997566 [Byte1]: 50
1722 08:06:10.001667
1723 08:06:10.002221 Set Vref, RX VrefLevel [Byte0]: 51
1724 08:06:10.004922 [Byte1]: 51
1725 08:06:10.009214
1726 08:06:10.009735 Set Vref, RX VrefLevel [Byte0]: 52
1727 08:06:10.012296 [Byte1]: 52
1728 08:06:10.016880
1729 08:06:10.017430 Set Vref, RX VrefLevel [Byte0]: 53
1730 08:06:10.020377 [Byte1]: 53
1731 08:06:10.024374
1732 08:06:10.024827 Set Vref, RX VrefLevel [Byte0]: 54
1733 08:06:10.027674 [Byte1]: 54
1734 08:06:10.032243
1735 08:06:10.032697 Set Vref, RX VrefLevel [Byte0]: 55
1736 08:06:10.035383 [Byte1]: 55
1737 08:06:10.039530
1738 08:06:10.040138 Set Vref, RX VrefLevel [Byte0]: 56
1739 08:06:10.042988 [Byte1]: 56
1740 08:06:10.047343
1741 08:06:10.047951 Set Vref, RX VrefLevel [Byte0]: 57
1742 08:06:10.050889 [Byte1]: 57
1743 08:06:10.055240
1744 08:06:10.055874 Set Vref, RX VrefLevel [Byte0]: 58
1745 08:06:10.059339 [Byte1]: 58
1746 08:06:10.062586
1747 08:06:10.063159 Set Vref, RX VrefLevel [Byte0]: 59
1748 08:06:10.065787 [Byte1]: 59
1749 08:06:10.070210
1750 08:06:10.070764 Set Vref, RX VrefLevel [Byte0]: 60
1751 08:06:10.073357 [Byte1]: 60
1752 08:06:10.077963
1753 08:06:10.078519 Set Vref, RX VrefLevel [Byte0]: 61
1754 08:06:10.080651 [Byte1]: 61
1755 08:06:10.085133
1756 08:06:10.085587 Set Vref, RX VrefLevel [Byte0]: 62
1757 08:06:10.088270 [Byte1]: 62
1758 08:06:10.092661
1759 08:06:10.093213 Set Vref, RX VrefLevel [Byte0]: 63
1760 08:06:10.096337 [Byte1]: 63
1761 08:06:10.100784
1762 08:06:10.101334 Set Vref, RX VrefLevel [Byte0]: 64
1763 08:06:10.103653 [Byte1]: 64
1764 08:06:10.108179
1765 08:06:10.108733 Set Vref, RX VrefLevel [Byte0]: 65
1766 08:06:10.111240 [Byte1]: 65
1767 08:06:10.115744
1768 08:06:10.116310 Set Vref, RX VrefLevel [Byte0]: 66
1769 08:06:10.118997 [Byte1]: 66
1770 08:06:10.123527
1771 08:06:10.124141 Set Vref, RX VrefLevel [Byte0]: 67
1772 08:06:10.126712 [Byte1]: 67
1773 08:06:10.130766
1774 08:06:10.131413 Set Vref, RX VrefLevel [Byte0]: 68
1775 08:06:10.134244 [Byte1]: 68
1776 08:06:10.138486
1777 08:06:10.139036 Set Vref, RX VrefLevel [Byte0]: 69
1778 08:06:10.141378 [Byte1]: 69
1779 08:06:10.145897
1780 08:06:10.146350 Set Vref, RX VrefLevel [Byte0]: 70
1781 08:06:10.149285 [Byte1]: 70
1782 08:06:10.153669
1783 08:06:10.154224 Set Vref, RX VrefLevel [Byte0]: 71
1784 08:06:10.157538 [Byte1]: 71
1785 08:06:10.160843
1786 08:06:10.161296 Set Vref, RX VrefLevel [Byte0]: 72
1787 08:06:10.164665 [Byte1]: 72
1788 08:06:10.168675
1789 08:06:10.169227 Set Vref, RX VrefLevel [Byte0]: 73
1790 08:06:10.172603 [Byte1]: 73
1791 08:06:10.176469
1792 08:06:10.177025 Final RX Vref Byte 0 = 56 to rank0
1793 08:06:10.179714 Final RX Vref Byte 1 = 61 to rank0
1794 08:06:10.183257 Final RX Vref Byte 0 = 56 to rank1
1795 08:06:10.187470 Final RX Vref Byte 1 = 61 to rank1==
1796 08:06:10.189801 Dram Type= 6, Freq= 0, CH_1, rank 0
1797 08:06:10.196416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 08:06:10.196970 ==
1799 08:06:10.197330 DQS Delay:
1800 08:06:10.197663 DQS0 = 0, DQS1 = 0
1801 08:06:10.199673 DQM Delay:
1802 08:06:10.200277 DQM0 = 86, DQM1 = 79
1803 08:06:10.203522 DQ Delay:
1804 08:06:10.206182 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1805 08:06:10.209531 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1806 08:06:10.212622 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1807 08:06:10.216077 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1808 08:06:10.216531
1809 08:06:10.216888
1810 08:06:10.223122 [DQSOSCAuto] RK0, (LSB)MR18= 0x321e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1811 08:06:10.226225 CH1 RK0: MR19=606, MR18=321E
1812 08:06:10.232490 CH1_RK0: MR19=0x606, MR18=0x321E, DQSOSC=397, MR23=63, INC=93, DEC=62
1813 08:06:10.232577
1814 08:06:10.236735 ----->DramcWriteLeveling(PI) begin...
1815 08:06:10.236904 ==
1816 08:06:10.239222 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 08:06:10.242728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 08:06:10.242906 ==
1819 08:06:10.245803 Write leveling (Byte 0): 29 => 29
1820 08:06:10.249378 Write leveling (Byte 1): 29 => 29
1821 08:06:10.252330 DramcWriteLeveling(PI) end<-----
1822 08:06:10.252525
1823 08:06:10.252626 ==
1824 08:06:10.255902 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 08:06:10.258791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 08:06:10.259001 ==
1827 08:06:10.262290 [Gating] SW mode calibration
1828 08:06:10.269217 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1829 08:06:10.275926 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1830 08:06:10.278753 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1831 08:06:10.286131 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1832 08:06:10.288527 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1833 08:06:10.292349 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 08:06:10.298920 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 08:06:10.302760 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 08:06:10.305588 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 08:06:10.312044 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 08:06:10.316089 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 08:06:10.318919 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 08:06:10.325361 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 08:06:10.329164 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 08:06:10.331841 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 08:06:10.338621 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 08:06:10.342232 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 08:06:10.345341 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 08:06:10.351692 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 08:06:10.355074 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1848 08:06:10.358437 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 08:06:10.365128 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 08:06:10.368407 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 08:06:10.371824 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 08:06:10.378808 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 08:06:10.382162 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 08:06:10.385148 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 08:06:10.387951 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1856 08:06:10.394941 0 9 8 | B1->B0 | 3232 2626 | 1 0 | (1 1) (0 0)
1857 08:06:10.397831 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 08:06:10.401637 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 08:06:10.408709 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1860 08:06:10.411835 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 08:06:10.414759 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 08:06:10.422050 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 08:06:10.424596 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1864 08:06:10.428444 0 10 8 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
1865 08:06:10.434687 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 08:06:10.438386 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 08:06:10.441457 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 08:06:10.447925 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 08:06:10.451677 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 08:06:10.454418 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 08:06:10.460952 0 11 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1872 08:06:10.464908 0 11 8 | B1->B0 | 3b3b 3737 | 1 0 | (0 0) (0 0)
1873 08:06:10.467894 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 08:06:10.474659 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 08:06:10.478136 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 08:06:10.481409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 08:06:10.487889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 08:06:10.490944 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 08:06:10.494688 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1880 08:06:10.500825 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1881 08:06:10.504394 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 08:06:10.508118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 08:06:10.514508 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 08:06:10.517932 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 08:06:10.521059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 08:06:10.527609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 08:06:10.530656 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 08:06:10.534364 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 08:06:10.537593 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 08:06:10.544557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 08:06:10.547183 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 08:06:10.553889 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 08:06:10.557627 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 08:06:10.560547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 08:06:10.567539 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1896 08:06:10.570559 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1897 08:06:10.574067 Total UI for P1: 0, mck2ui 16
1898 08:06:10.577201 best dqsien dly found for B1: ( 0, 14, 4)
1899 08:06:10.580473 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 08:06:10.584182 Total UI for P1: 0, mck2ui 16
1901 08:06:10.588027 best dqsien dly found for B0: ( 0, 14, 8)
1902 08:06:10.590506 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1903 08:06:10.593625 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1904 08:06:10.594179
1905 08:06:10.597529 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1906 08:06:10.600366 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1907 08:06:10.603461 [Gating] SW calibration Done
1908 08:06:10.603938 ==
1909 08:06:10.606747 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 08:06:10.613431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 08:06:10.613988 ==
1912 08:06:10.614354 RX Vref Scan: 0
1913 08:06:10.614794
1914 08:06:10.617260 RX Vref 0 -> 0, step: 1
1915 08:06:10.617811
1916 08:06:10.620066 RX Delay -130 -> 252, step: 16
1917 08:06:10.623525 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1918 08:06:10.627098 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1919 08:06:10.630063 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1920 08:06:10.636488 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1921 08:06:10.639777 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1922 08:06:10.643444 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1923 08:06:10.646568 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1924 08:06:10.650394 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1925 08:06:10.656739 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1926 08:06:10.659872 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1927 08:06:10.663247 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1928 08:06:10.667193 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1929 08:06:10.670294 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1930 08:06:10.676551 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1931 08:06:10.679608 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1932 08:06:10.682779 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1933 08:06:10.683232 ==
1934 08:06:10.686402 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 08:06:10.689183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 08:06:10.693053 ==
1937 08:06:10.693603 DQS Delay:
1938 08:06:10.693961 DQS0 = 0, DQS1 = 0
1939 08:06:10.696656 DQM Delay:
1940 08:06:10.697213 DQM0 = 88, DQM1 = 79
1941 08:06:10.699605 DQ Delay:
1942 08:06:10.703008 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1943 08:06:10.703561 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1944 08:06:10.706301 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1945 08:06:10.712372 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1946 08:06:10.712830
1947 08:06:10.713186
1948 08:06:10.713520 ==
1949 08:06:10.715838 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 08:06:10.719543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 08:06:10.720155 ==
1952 08:06:10.720681
1953 08:06:10.721133
1954 08:06:10.723152 TX Vref Scan disable
1955 08:06:10.723706 == TX Byte 0 ==
1956 08:06:10.729013 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1957 08:06:10.732957 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1958 08:06:10.733412 == TX Byte 1 ==
1959 08:06:10.739406 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1960 08:06:10.742756 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1961 08:06:10.743311 ==
1962 08:06:10.746054 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 08:06:10.749048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 08:06:10.749510 ==
1965 08:06:10.763046 TX Vref=22, minBit 0, minWin=27, winSum=444
1966 08:06:10.766596 TX Vref=24, minBit 9, minWin=26, winSum=446
1967 08:06:10.769835 TX Vref=26, minBit 9, minWin=27, winSum=452
1968 08:06:10.774082 TX Vref=28, minBit 9, minWin=27, winSum=449
1969 08:06:10.776436 TX Vref=30, minBit 0, minWin=28, winSum=453
1970 08:06:10.783554 TX Vref=32, minBit 8, minWin=27, winSum=448
1971 08:06:10.787119 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1972 08:06:10.787678
1973 08:06:10.789367 Final TX Range 1 Vref 30
1974 08:06:10.789844
1975 08:06:10.790209 ==
1976 08:06:10.793223 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 08:06:10.796075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 08:06:10.799973 ==
1979 08:06:10.800529
1980 08:06:10.800885
1981 08:06:10.801219 TX Vref Scan disable
1982 08:06:10.802900 == TX Byte 0 ==
1983 08:06:10.806504 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1984 08:06:10.809436 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1985 08:06:10.813483 == TX Byte 1 ==
1986 08:06:10.816938 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1987 08:06:10.823021 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1988 08:06:10.823580
1989 08:06:10.823997 [DATLAT]
1990 08:06:10.824335 Freq=800, CH1 RK1
1991 08:06:10.824664
1992 08:06:10.826089 DATLAT Default: 0xa
1993 08:06:10.826576 0, 0xFFFF, sum = 0
1994 08:06:10.830410 1, 0xFFFF, sum = 0
1995 08:06:10.830983 2, 0xFFFF, sum = 0
1996 08:06:10.833168 3, 0xFFFF, sum = 0
1997 08:06:10.835849 4, 0xFFFF, sum = 0
1998 08:06:10.836311 5, 0xFFFF, sum = 0
1999 08:06:10.839040 6, 0xFFFF, sum = 0
2000 08:06:10.839534 7, 0xFFFF, sum = 0
2001 08:06:10.842807 8, 0xFFFF, sum = 0
2002 08:06:10.843368 9, 0x0, sum = 1
2003 08:06:10.846179 10, 0x0, sum = 2
2004 08:06:10.846645 11, 0x0, sum = 3
2005 08:06:10.847015 12, 0x0, sum = 4
2006 08:06:10.849346 best_step = 10
2007 08:06:10.849797
2008 08:06:10.850152 ==
2009 08:06:10.852654 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 08:06:10.856059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 08:06:10.856612 ==
2012 08:06:10.859473 RX Vref Scan: 0
2013 08:06:10.860064
2014 08:06:10.862344 RX Vref 0 -> 0, step: 1
2015 08:06:10.862799
2016 08:06:10.863154 RX Delay -95 -> 252, step: 8
2017 08:06:10.869934 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2018 08:06:10.872916 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2019 08:06:10.876910 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2020 08:06:10.880377 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2021 08:06:10.886847 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2022 08:06:10.889532 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2023 08:06:10.892702 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2024 08:06:10.896673 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2025 08:06:10.900320 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2026 08:06:10.903246 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2027 08:06:10.909930 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2028 08:06:10.913652 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2029 08:06:10.916598 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2030 08:06:10.919702 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2031 08:06:10.926141 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2032 08:06:10.929660 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2033 08:06:10.930213 ==
2034 08:06:10.933386 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 08:06:10.936517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 08:06:10.936977 ==
2037 08:06:10.940437 DQS Delay:
2038 08:06:10.940889 DQS0 = 0, DQS1 = 0
2039 08:06:10.941252 DQM Delay:
2040 08:06:10.943267 DQM0 = 87, DQM1 = 78
2041 08:06:10.943718 DQ Delay:
2042 08:06:10.946096 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2043 08:06:10.949809 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2044 08:06:10.952699 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
2045 08:06:10.956211 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2046 08:06:10.956662
2047 08:06:10.957016
2048 08:06:10.966463 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2049 08:06:10.966986 CH1 RK1: MR19=606, MR18=1F17
2050 08:06:10.972782 CH1_RK1: MR19=0x606, MR18=0x1F17, DQSOSC=402, MR23=63, INC=91, DEC=60
2051 08:06:10.975794 [RxdqsGatingPostProcess] freq 800
2052 08:06:10.982796 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2053 08:06:10.986053 Pre-setting of DQS Precalculation
2054 08:06:10.989230 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2055 08:06:10.996053 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2056 08:06:11.006125 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2057 08:06:11.006634
2058 08:06:11.006959
2059 08:06:11.008968 [Calibration Summary] 1600 Mbps
2060 08:06:11.009376 CH 0, Rank 0
2061 08:06:11.012150 SW Impedance : PASS
2062 08:06:11.012564 DUTY Scan : NO K
2063 08:06:11.016454 ZQ Calibration : PASS
2064 08:06:11.016974 Jitter Meter : NO K
2065 08:06:11.018980 CBT Training : PASS
2066 08:06:11.023085 Write leveling : PASS
2067 08:06:11.023653 RX DQS gating : PASS
2068 08:06:11.026338 RX DQ/DQS(RDDQC) : PASS
2069 08:06:11.029171 TX DQ/DQS : PASS
2070 08:06:11.029732 RX DATLAT : PASS
2071 08:06:11.032674 RX DQ/DQS(Engine): PASS
2072 08:06:11.035464 TX OE : NO K
2073 08:06:11.036188 All Pass.
2074 08:06:11.036567
2075 08:06:11.036908 CH 0, Rank 1
2076 08:06:11.038737 SW Impedance : PASS
2077 08:06:11.042516 DUTY Scan : NO K
2078 08:06:11.043209 ZQ Calibration : PASS
2079 08:06:11.045727 Jitter Meter : NO K
2080 08:06:11.048589 CBT Training : PASS
2081 08:06:11.049046 Write leveling : PASS
2082 08:06:11.052284 RX DQS gating : PASS
2083 08:06:11.056202 RX DQ/DQS(RDDQC) : PASS
2084 08:06:11.056767 TX DQ/DQS : PASS
2085 08:06:11.059105 RX DATLAT : PASS
2086 08:06:11.062869 RX DQ/DQS(Engine): PASS
2087 08:06:11.063419 TX OE : NO K
2088 08:06:11.063831 All Pass.
2089 08:06:11.065815
2090 08:06:11.066362 CH 1, Rank 0
2091 08:06:11.069445 SW Impedance : PASS
2092 08:06:11.070003 DUTY Scan : NO K
2093 08:06:11.071761 ZQ Calibration : PASS
2094 08:06:11.075209 Jitter Meter : NO K
2095 08:06:11.075814 CBT Training : PASS
2096 08:06:11.078730 Write leveling : PASS
2097 08:06:11.079280 RX DQS gating : PASS
2098 08:06:11.081738 RX DQ/DQS(RDDQC) : PASS
2099 08:06:11.085373 TX DQ/DQS : PASS
2100 08:06:11.085925 RX DATLAT : PASS
2101 08:06:11.088666 RX DQ/DQS(Engine): PASS
2102 08:06:11.091600 TX OE : NO K
2103 08:06:11.092093 All Pass.
2104 08:06:11.092458
2105 08:06:11.092792 CH 1, Rank 1
2106 08:06:11.095391 SW Impedance : PASS
2107 08:06:11.098826 DUTY Scan : NO K
2108 08:06:11.099383 ZQ Calibration : PASS
2109 08:06:11.101664 Jitter Meter : NO K
2110 08:06:11.105808 CBT Training : PASS
2111 08:06:11.106318 Write leveling : PASS
2112 08:06:11.108607 RX DQS gating : PASS
2113 08:06:11.111710 RX DQ/DQS(RDDQC) : PASS
2114 08:06:11.112606 TX DQ/DQS : PASS
2115 08:06:11.114926 RX DATLAT : PASS
2116 08:06:11.118554 RX DQ/DQS(Engine): PASS
2117 08:06:11.119083 TX OE : NO K
2118 08:06:11.121656 All Pass.
2119 08:06:11.122164
2120 08:06:11.122490 DramC Write-DBI off
2121 08:06:11.125141 PER_BANK_REFRESH: Hybrid Mode
2122 08:06:11.125557 TX_TRACKING: ON
2123 08:06:11.128600 [GetDramInforAfterCalByMRR] Vendor 6.
2124 08:06:11.135261 [GetDramInforAfterCalByMRR] Revision 606.
2125 08:06:11.137902 [GetDramInforAfterCalByMRR] Revision 2 0.
2126 08:06:11.138314 MR0 0x3b3b
2127 08:06:11.138637 MR8 0x5151
2128 08:06:11.141615 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2129 08:06:11.142028
2130 08:06:11.144974 MR0 0x3b3b
2131 08:06:11.145510 MR8 0x5151
2132 08:06:11.148026 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 08:06:11.148440
2134 08:06:11.158200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2135 08:06:11.161756 [FAST_K] Save calibration result to emmc
2136 08:06:11.165189 [FAST_K] Save calibration result to emmc
2137 08:06:11.168495 dram_init: config_dvfs: 1
2138 08:06:11.171416 dramc_set_vcore_voltage set vcore to 662500
2139 08:06:11.174493 Read voltage for 1200, 2
2140 08:06:11.174903 Vio18 = 0
2141 08:06:11.175232 Vcore = 662500
2142 08:06:11.178245 Vdram = 0
2143 08:06:11.178759 Vddq = 0
2144 08:06:11.179089 Vmddr = 0
2145 08:06:11.184238 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2146 08:06:11.187978 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2147 08:06:11.190957 MEM_TYPE=3, freq_sel=15
2148 08:06:11.194910 sv_algorithm_assistance_LP4_1600
2149 08:06:11.198193 ============ PULL DRAM RESETB DOWN ============
2150 08:06:11.201290 ========== PULL DRAM RESETB DOWN end =========
2151 08:06:11.208152 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2152 08:06:11.211098 ===================================
2153 08:06:11.211518 LPDDR4 DRAM CONFIGURATION
2154 08:06:11.214179 ===================================
2155 08:06:11.217806 EX_ROW_EN[0] = 0x0
2156 08:06:11.221599 EX_ROW_EN[1] = 0x0
2157 08:06:11.222110 LP4Y_EN = 0x0
2158 08:06:11.224737 WORK_FSP = 0x0
2159 08:06:11.225252 WL = 0x4
2160 08:06:11.227754 RL = 0x4
2161 08:06:11.228391 BL = 0x2
2162 08:06:11.231128 RPST = 0x0
2163 08:06:11.231638 RD_PRE = 0x0
2164 08:06:11.234115 WR_PRE = 0x1
2165 08:06:11.234527 WR_PST = 0x0
2166 08:06:11.238227 DBI_WR = 0x0
2167 08:06:11.238637 DBI_RD = 0x0
2168 08:06:11.241047 OTF = 0x1
2169 08:06:11.243963 ===================================
2170 08:06:11.248252 ===================================
2171 08:06:11.248910 ANA top config
2172 08:06:11.250999 ===================================
2173 08:06:11.254170 DLL_ASYNC_EN = 0
2174 08:06:11.257353 ALL_SLAVE_EN = 0
2175 08:06:11.260577 NEW_RANK_MODE = 1
2176 08:06:11.260993 DLL_IDLE_MODE = 1
2177 08:06:11.264491 LP45_APHY_COMB_EN = 1
2178 08:06:11.267379 TX_ODT_DIS = 1
2179 08:06:11.271689 NEW_8X_MODE = 1
2180 08:06:11.274378 ===================================
2181 08:06:11.278136 ===================================
2182 08:06:11.280518 data_rate = 2400
2183 08:06:11.280932 CKR = 1
2184 08:06:11.284561 DQ_P2S_RATIO = 8
2185 08:06:11.287654 ===================================
2186 08:06:11.290756 CA_P2S_RATIO = 8
2187 08:06:11.294156 DQ_CA_OPEN = 0
2188 08:06:11.297177 DQ_SEMI_OPEN = 0
2189 08:06:11.300720 CA_SEMI_OPEN = 0
2190 08:06:11.301230 CA_FULL_RATE = 0
2191 08:06:11.304337 DQ_CKDIV4_EN = 0
2192 08:06:11.307059 CA_CKDIV4_EN = 0
2193 08:06:11.310737 CA_PREDIV_EN = 0
2194 08:06:11.314722 PH8_DLY = 17
2195 08:06:11.317985 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2196 08:06:11.318398 DQ_AAMCK_DIV = 4
2197 08:06:11.321406 CA_AAMCK_DIV = 4
2198 08:06:11.323795 CA_ADMCK_DIV = 4
2199 08:06:11.327583 DQ_TRACK_CA_EN = 0
2200 08:06:11.330847 CA_PICK = 1200
2201 08:06:11.333861 CA_MCKIO = 1200
2202 08:06:11.337196 MCKIO_SEMI = 0
2203 08:06:11.337633 PLL_FREQ = 2366
2204 08:06:11.340648 DQ_UI_PI_RATIO = 32
2205 08:06:11.343694 CA_UI_PI_RATIO = 0
2206 08:06:11.347099 ===================================
2207 08:06:11.351144 ===================================
2208 08:06:11.354292 memory_type:LPDDR4
2209 08:06:11.354808 GP_NUM : 10
2210 08:06:11.357372 SRAM_EN : 1
2211 08:06:11.360198 MD32_EN : 0
2212 08:06:11.363608 ===================================
2213 08:06:11.364191 [ANA_INIT] >>>>>>>>>>>>>>
2214 08:06:11.366623 <<<<<< [CONFIGURE PHASE]: ANA_TX
2215 08:06:11.370207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2216 08:06:11.373672 ===================================
2217 08:06:11.377057 data_rate = 2400,PCW = 0X5b00
2218 08:06:11.380726 ===================================
2219 08:06:11.384309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2220 08:06:11.390228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2221 08:06:11.394023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2222 08:06:11.400710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2223 08:06:11.403538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2224 08:06:11.407174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2225 08:06:11.410747 [ANA_INIT] flow start
2226 08:06:11.411254 [ANA_INIT] PLL >>>>>>>>
2227 08:06:11.413209 [ANA_INIT] PLL <<<<<<<<
2228 08:06:11.416735 [ANA_INIT] MIDPI >>>>>>>>
2229 08:06:11.417253 [ANA_INIT] MIDPI <<<<<<<<
2230 08:06:11.420678 [ANA_INIT] DLL >>>>>>>>
2231 08:06:11.423509 [ANA_INIT] DLL <<<<<<<<
2232 08:06:11.424062 [ANA_INIT] flow end
2233 08:06:11.430230 ============ LP4 DIFF to SE enter ============
2234 08:06:11.433842 ============ LP4 DIFF to SE exit ============
2235 08:06:11.434259 [ANA_INIT] <<<<<<<<<<<<<
2236 08:06:11.436814 [Flow] Enable top DCM control >>>>>
2237 08:06:11.439913 [Flow] Enable top DCM control <<<<<
2238 08:06:11.443380 Enable DLL master slave shuffle
2239 08:06:11.449781 ==============================================================
2240 08:06:11.452976 Gating Mode config
2241 08:06:11.456589 ==============================================================
2242 08:06:11.459508 Config description:
2243 08:06:11.469787 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2244 08:06:11.476627 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2245 08:06:11.479959 SELPH_MODE 0: By rank 1: By Phase
2246 08:06:11.486827 ==============================================================
2247 08:06:11.489861 GAT_TRACK_EN = 1
2248 08:06:11.492829 RX_GATING_MODE = 2
2249 08:06:11.496621 RX_GATING_TRACK_MODE = 2
2250 08:06:11.497233 SELPH_MODE = 1
2251 08:06:11.499869 PICG_EARLY_EN = 1
2252 08:06:11.503196 VALID_LAT_VALUE = 1
2253 08:06:11.509368 ==============================================================
2254 08:06:11.512816 Enter into Gating configuration >>>>
2255 08:06:11.516143 Exit from Gating configuration <<<<
2256 08:06:11.519716 Enter into DVFS_PRE_config >>>>>
2257 08:06:11.529766 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2258 08:06:11.532677 Exit from DVFS_PRE_config <<<<<
2259 08:06:11.536364 Enter into PICG configuration >>>>
2260 08:06:11.539037 Exit from PICG configuration <<<<
2261 08:06:11.542717 [RX_INPUT] configuration >>>>>
2262 08:06:11.546207 [RX_INPUT] configuration <<<<<
2263 08:06:11.549159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2264 08:06:11.556000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2265 08:06:11.562636 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2266 08:06:11.569034 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2267 08:06:11.575940 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2268 08:06:11.579096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2269 08:06:11.585756 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2270 08:06:11.589786 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2271 08:06:11.592366 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2272 08:06:11.595763 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2273 08:06:11.602060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2274 08:06:11.605630 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 08:06:11.609110 ===================================
2276 08:06:11.612264 LPDDR4 DRAM CONFIGURATION
2277 08:06:11.615558 ===================================
2278 08:06:11.616165 EX_ROW_EN[0] = 0x0
2279 08:06:11.618926 EX_ROW_EN[1] = 0x0
2280 08:06:11.619374 LP4Y_EN = 0x0
2281 08:06:11.622365 WORK_FSP = 0x0
2282 08:06:11.622922 WL = 0x4
2283 08:06:11.626120 RL = 0x4
2284 08:06:11.626576 BL = 0x2
2285 08:06:11.628813 RPST = 0x0
2286 08:06:11.629266 RD_PRE = 0x0
2287 08:06:11.632039 WR_PRE = 0x1
2288 08:06:11.635136 WR_PST = 0x0
2289 08:06:11.635546 DBI_WR = 0x0
2290 08:06:11.638734 DBI_RD = 0x0
2291 08:06:11.639145 OTF = 0x1
2292 08:06:11.641711 ===================================
2293 08:06:11.645507 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2294 08:06:11.651997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2295 08:06:11.655536 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 08:06:11.658704 ===================================
2297 08:06:11.662006 LPDDR4 DRAM CONFIGURATION
2298 08:06:11.665198 ===================================
2299 08:06:11.665763 EX_ROW_EN[0] = 0x10
2300 08:06:11.668174 EX_ROW_EN[1] = 0x0
2301 08:06:11.668632 LP4Y_EN = 0x0
2302 08:06:11.671790 WORK_FSP = 0x0
2303 08:06:11.672336 WL = 0x4
2304 08:06:11.675192 RL = 0x4
2305 08:06:11.675603 BL = 0x2
2306 08:06:11.678332 RPST = 0x0
2307 08:06:11.678840 RD_PRE = 0x0
2308 08:06:11.681710 WR_PRE = 0x1
2309 08:06:11.684780 WR_PST = 0x0
2310 08:06:11.685188 DBI_WR = 0x0
2311 08:06:11.688278 DBI_RD = 0x0
2312 08:06:11.688686 OTF = 0x1
2313 08:06:11.691881 ===================================
2314 08:06:11.697986 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2315 08:06:11.698396 ==
2316 08:06:11.701215 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 08:06:11.705022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2318 08:06:11.705532 ==
2319 08:06:11.708246 [Duty_Offset_Calibration]
2320 08:06:11.708756 B0:1 B1:-1 CA:0
2321 08:06:11.711390
2322 08:06:11.714920 [DutyScan_Calibration_Flow] k_type=0
2323 08:06:11.722686
2324 08:06:11.723190 ==CLK 0==
2325 08:06:11.726429 Final CLK duty delay cell = 0
2326 08:06:11.729082 [0] MAX Duty = 5125%(X100), DQS PI = 24
2327 08:06:11.732831 [0] MIN Duty = 4906%(X100), DQS PI = 8
2328 08:06:11.733240 [0] AVG Duty = 5015%(X100)
2329 08:06:11.733563
2330 08:06:11.736193 CH0 CLK Duty spec in!! Max-Min= 219%
2331 08:06:11.742907 [DutyScan_Calibration_Flow] ====Done====
2332 08:06:11.743539
2333 08:06:11.746020 [DutyScan_Calibration_Flow] k_type=1
2334 08:06:11.760127
2335 08:06:11.760636 ==DQS 0 ==
2336 08:06:11.764144 Final DQS duty delay cell = -4
2337 08:06:11.767326 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2338 08:06:11.770650 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2339 08:06:11.773856 [-4] AVG Duty = 4968%(X100)
2340 08:06:11.774404
2341 08:06:11.774760 ==DQS 1 ==
2342 08:06:11.777066 Final DQS duty delay cell = -4
2343 08:06:11.780102 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2344 08:06:11.783932 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2345 08:06:11.787201 [-4] AVG Duty = 4938%(X100)
2346 08:06:11.787781
2347 08:06:11.790624 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2348 08:06:11.791335
2349 08:06:11.793852 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2350 08:06:11.797690 [DutyScan_Calibration_Flow] ====Done====
2351 08:06:11.798245
2352 08:06:11.800315 [DutyScan_Calibration_Flow] k_type=3
2353 08:06:11.818291
2354 08:06:11.818841 ==DQM 0 ==
2355 08:06:11.821559 Final DQM duty delay cell = 0
2356 08:06:11.825081 [0] MAX Duty = 5062%(X100), DQS PI = 18
2357 08:06:11.828172 [0] MIN Duty = 4875%(X100), DQS PI = 8
2358 08:06:11.828623 [0] AVG Duty = 4968%(X100)
2359 08:06:11.831608
2360 08:06:11.832276 ==DQM 1 ==
2361 08:06:11.834561 Final DQM duty delay cell = 4
2362 08:06:11.838174 [4] MAX Duty = 5187%(X100), DQS PI = 14
2363 08:06:11.841287 [4] MIN Duty = 5000%(X100), DQS PI = 24
2364 08:06:11.844931 [4] AVG Duty = 5093%(X100)
2365 08:06:11.845373
2366 08:06:11.848252 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2367 08:06:11.848761
2368 08:06:11.851561 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2369 08:06:11.854549 [DutyScan_Calibration_Flow] ====Done====
2370 08:06:11.855006
2371 08:06:11.858510 [DutyScan_Calibration_Flow] k_type=2
2372 08:06:11.874314
2373 08:06:11.874880 ==DQ 0 ==
2374 08:06:11.877748 Final DQ duty delay cell = -4
2375 08:06:11.880674 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2376 08:06:11.883864 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2377 08:06:11.887263 [-4] AVG Duty = 4969%(X100)
2378 08:06:11.887786
2379 08:06:11.888273 ==DQ 1 ==
2380 08:06:11.890544 Final DQ duty delay cell = 0
2381 08:06:11.893970 [0] MAX Duty = 5125%(X100), DQS PI = 50
2382 08:06:11.897672 [0] MIN Duty = 5000%(X100), DQS PI = 24
2383 08:06:11.900263 [0] AVG Duty = 5062%(X100)
2384 08:06:11.900787
2385 08:06:11.903651 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2386 08:06:11.904223
2387 08:06:11.906702 CH0 DQ 1 Duty spec in!! Max-Min= 125%
2388 08:06:11.910274 [DutyScan_Calibration_Flow] ====Done====
2389 08:06:11.910731 ==
2390 08:06:11.913864 Dram Type= 6, Freq= 0, CH_1, rank 0
2391 08:06:11.916932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2392 08:06:11.917510 ==
2393 08:06:11.920332 [Duty_Offset_Calibration]
2394 08:06:11.920744 B0:-1 B1:1 CA:2
2395 08:06:11.921071
2396 08:06:11.923171 [DutyScan_Calibration_Flow] k_type=0
2397 08:06:11.935009
2398 08:06:11.935513 ==CLK 0==
2399 08:06:11.937662 Final CLK duty delay cell = 0
2400 08:06:11.940732 [0] MAX Duty = 5156%(X100), DQS PI = 6
2401 08:06:11.944113 [0] MIN Duty = 5000%(X100), DQS PI = 28
2402 08:06:11.944548 [0] AVG Duty = 5078%(X100)
2403 08:06:11.947822
2404 08:06:11.951079 CH1 CLK Duty spec in!! Max-Min= 156%
2405 08:06:11.954119 [DutyScan_Calibration_Flow] ====Done====
2406 08:06:11.954596
2407 08:06:11.957504 [DutyScan_Calibration_Flow] k_type=1
2408 08:06:11.973437
2409 08:06:11.974009 ==DQS 0 ==
2410 08:06:11.976588 Final DQS duty delay cell = 0
2411 08:06:11.980686 [0] MAX Duty = 5156%(X100), DQS PI = 16
2412 08:06:11.983598 [0] MIN Duty = 4907%(X100), DQS PI = 38
2413 08:06:11.987444 [0] AVG Duty = 5031%(X100)
2414 08:06:11.988072
2415 08:06:11.988566 ==DQS 1 ==
2416 08:06:11.989840 Final DQS duty delay cell = 0
2417 08:06:11.993507 [0] MAX Duty = 5062%(X100), DQS PI = 0
2418 08:06:11.997116 [0] MIN Duty = 4969%(X100), DQS PI = 26
2419 08:06:11.997687 [0] AVG Duty = 5015%(X100)
2420 08:06:12.000478
2421 08:06:12.003552 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2422 08:06:12.004062
2423 08:06:12.007297 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2424 08:06:12.010194 [DutyScan_Calibration_Flow] ====Done====
2425 08:06:12.010777
2426 08:06:12.013138 [DutyScan_Calibration_Flow] k_type=3
2427 08:06:12.029521
2428 08:06:12.030080 ==DQM 0 ==
2429 08:06:12.032548 Final DQM duty delay cell = -4
2430 08:06:12.035627 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2431 08:06:12.038834 [-4] MIN Duty = 4876%(X100), DQS PI = 38
2432 08:06:12.041986 [-4] AVG Duty = 4969%(X100)
2433 08:06:12.042463
2434 08:06:12.042944 ==DQM 1 ==
2435 08:06:12.045963 Final DQM duty delay cell = 0
2436 08:06:12.048576 [0] MAX Duty = 5187%(X100), DQS PI = 34
2437 08:06:12.052366 [0] MIN Duty = 4969%(X100), DQS PI = 4
2438 08:06:12.055712 [0] AVG Duty = 5078%(X100)
2439 08:06:12.056315
2440 08:06:12.059159 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2441 08:06:12.059772
2442 08:06:12.062106 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2443 08:06:12.065194 [DutyScan_Calibration_Flow] ====Done====
2444 08:06:12.065670
2445 08:06:12.068687 [DutyScan_Calibration_Flow] k_type=2
2446 08:06:12.086214
2447 08:06:12.086777 ==DQ 0 ==
2448 08:06:12.089661 Final DQ duty delay cell = 0
2449 08:06:12.092381 [0] MAX Duty = 5156%(X100), DQS PI = 60
2450 08:06:12.096115 [0] MIN Duty = 4907%(X100), DQS PI = 38
2451 08:06:12.096689 [0] AVG Duty = 5031%(X100)
2452 08:06:12.097175
2453 08:06:12.099609 ==DQ 1 ==
2454 08:06:12.102532 Final DQ duty delay cell = 0
2455 08:06:12.106204 [0] MAX Duty = 5124%(X100), DQS PI = 42
2456 08:06:12.110378 [0] MIN Duty = 4969%(X100), DQS PI = 28
2457 08:06:12.110944 [0] AVG Duty = 5046%(X100)
2458 08:06:12.111427
2459 08:06:12.112910 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2460 08:06:12.115777
2461 08:06:12.119076 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2462 08:06:12.122324 [DutyScan_Calibration_Flow] ====Done====
2463 08:06:12.126226 nWR fixed to 30
2464 08:06:12.126807 [ModeRegInit_LP4] CH0 RK0
2465 08:06:12.128959 [ModeRegInit_LP4] CH0 RK1
2466 08:06:12.132453 [ModeRegInit_LP4] CH1 RK0
2467 08:06:12.136054 [ModeRegInit_LP4] CH1 RK1
2468 08:06:12.136614 match AC timing 7
2469 08:06:12.139150 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2470 08:06:12.145734 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2471 08:06:12.148662 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2472 08:06:12.155784 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2473 08:06:12.159054 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2474 08:06:12.159611 ==
2475 08:06:12.162170 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 08:06:12.165621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 08:06:12.166174 ==
2478 08:06:12.172529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 08:06:12.178601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 08:06:12.186171 [CA 0] Center 39 (9~70) winsize 62
2481 08:06:12.189102 [CA 1] Center 39 (9~69) winsize 61
2482 08:06:12.192334 [CA 2] Center 35 (5~66) winsize 62
2483 08:06:12.195895 [CA 3] Center 35 (5~66) winsize 62
2484 08:06:12.199246 [CA 4] Center 33 (4~63) winsize 60
2485 08:06:12.202788 [CA 5] Center 33 (3~63) winsize 61
2486 08:06:12.203348
2487 08:06:12.206044 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2488 08:06:12.206598
2489 08:06:12.209247 [CATrainingPosCal] consider 1 rank data
2490 08:06:12.212638 u2DelayCellTimex100 = 270/100 ps
2491 08:06:12.215534 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2492 08:06:12.222576 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2493 08:06:12.225712 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 08:06:12.228867 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2495 08:06:12.231910 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2496 08:06:12.235665 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2497 08:06:12.236277
2498 08:06:12.239406 CA PerBit enable=1, Macro0, CA PI delay=33
2499 08:06:12.240024
2500 08:06:12.242343 [CBTSetCACLKResult] CA Dly = 33
2501 08:06:12.245860 CS Dly: 8 (0~39)
2502 08:06:12.246447 ==
2503 08:06:12.249062 Dram Type= 6, Freq= 0, CH_0, rank 1
2504 08:06:12.252409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 08:06:12.252871 ==
2506 08:06:12.258755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 08:06:12.261986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 08:06:12.271654 [CA 0] Center 39 (9~70) winsize 62
2509 08:06:12.274985 [CA 1] Center 39 (9~70) winsize 62
2510 08:06:12.278129 [CA 2] Center 35 (5~66) winsize 62
2511 08:06:12.281751 [CA 3] Center 34 (4~65) winsize 62
2512 08:06:12.285079 [CA 4] Center 33 (3~64) winsize 62
2513 08:06:12.288118 [CA 5] Center 33 (3~63) winsize 61
2514 08:06:12.288586
2515 08:06:12.292226 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 08:06:12.292770
2517 08:06:12.294921 [CATrainingPosCal] consider 2 rank data
2518 08:06:12.298040 u2DelayCellTimex100 = 270/100 ps
2519 08:06:12.301637 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2520 08:06:12.308040 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2521 08:06:12.311524 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 08:06:12.315032 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2523 08:06:12.318515 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2524 08:06:12.321440 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2525 08:06:12.322022
2526 08:06:12.325187 CA PerBit enable=1, Macro0, CA PI delay=33
2527 08:06:12.325764
2528 08:06:12.328114 [CBTSetCACLKResult] CA Dly = 33
2529 08:06:12.328594 CS Dly: 9 (0~41)
2530 08:06:12.329077
2531 08:06:12.331798 ----->DramcWriteLeveling(PI) begin...
2532 08:06:12.335241 ==
2533 08:06:12.338008 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 08:06:12.341823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 08:06:12.342366 ==
2536 08:06:12.344548 Write leveling (Byte 0): 31 => 31
2537 08:06:12.347619 Write leveling (Byte 1): 29 => 29
2538 08:06:12.351251 DramcWriteLeveling(PI) end<-----
2539 08:06:12.351848
2540 08:06:12.352219 ==
2541 08:06:12.354625 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 08:06:12.358103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 08:06:12.358570 ==
2544 08:06:12.361780 [Gating] SW mode calibration
2545 08:06:12.368167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2546 08:06:12.375133 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2547 08:06:12.378522 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2548 08:06:12.381243 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
2549 08:06:12.387918 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 08:06:12.391041 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 08:06:12.394718 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 08:06:12.397949 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 08:06:12.404497 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 08:06:12.407903 0 15 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
2555 08:06:12.411434 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 1) (0 0)
2556 08:06:12.417798 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2557 08:06:12.421159 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 08:06:12.424476 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 08:06:12.431075 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 08:06:12.434594 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 08:06:12.437527 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 08:06:12.444103 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2563 08:06:12.447453 1 1 0 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
2564 08:06:12.450774 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2565 08:06:12.457826 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 08:06:12.461040 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 08:06:12.463970 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 08:06:12.471225 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 08:06:12.474761 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2570 08:06:12.477986 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2571 08:06:12.483914 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2572 08:06:12.487962 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2573 08:06:12.490857 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 08:06:12.497384 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 08:06:12.500875 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 08:06:12.504114 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 08:06:12.510967 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 08:06:12.514060 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 08:06:12.517570 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 08:06:12.523912 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 08:06:12.527409 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 08:06:12.530607 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 08:06:12.537352 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 08:06:12.540834 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 08:06:12.544038 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 08:06:12.550343 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2587 08:06:12.553813 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2588 08:06:12.556868 Total UI for P1: 0, mck2ui 16
2589 08:06:12.560197 best dqsien dly found for B0: ( 1, 3, 28)
2590 08:06:12.563695 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2591 08:06:12.566852 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 08:06:12.570526 Total UI for P1: 0, mck2ui 16
2593 08:06:12.573365 best dqsien dly found for B1: ( 1, 4, 2)
2594 08:06:12.576492 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2595 08:06:12.583499 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2596 08:06:12.584100
2597 08:06:12.587531 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2598 08:06:12.591002 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2599 08:06:12.593652 [Gating] SW calibration Done
2600 08:06:12.594115 ==
2601 08:06:12.597018 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 08:06:12.599947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 08:06:12.600401 ==
2604 08:06:12.600734 RX Vref Scan: 0
2605 08:06:12.601188
2606 08:06:12.603542 RX Vref 0 -> 0, step: 1
2607 08:06:12.604096
2608 08:06:12.606960 RX Delay -40 -> 252, step: 8
2609 08:06:12.610789 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2610 08:06:12.613821 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2611 08:06:12.620309 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2612 08:06:12.623364 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2613 08:06:12.626945 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2614 08:06:12.630258 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2615 08:06:12.633455 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2616 08:06:12.640329 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2617 08:06:12.643838 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2618 08:06:12.646786 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2619 08:06:12.649889 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2620 08:06:12.653710 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2621 08:06:12.659905 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2622 08:06:12.663933 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2623 08:06:12.666612 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2624 08:06:12.670533 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2625 08:06:12.671095 ==
2626 08:06:12.673751 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 08:06:12.679944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 08:06:12.680410 ==
2629 08:06:12.680781 DQS Delay:
2630 08:06:12.683516 DQS0 = 0, DQS1 = 0
2631 08:06:12.684136 DQM Delay:
2632 08:06:12.684512 DQM0 = 119, DQM1 = 107
2633 08:06:12.686059 DQ Delay:
2634 08:06:12.689651 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2635 08:06:12.693100 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2636 08:06:12.696264 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
2637 08:06:12.700266 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2638 08:06:12.700845
2639 08:06:12.701339
2640 08:06:12.701796 ==
2641 08:06:12.702590 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 08:06:12.706581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 08:06:12.709836 ==
2644 08:06:12.710424
2645 08:06:12.710917
2646 08:06:12.711375 TX Vref Scan disable
2647 08:06:12.712716 == TX Byte 0 ==
2648 08:06:12.716388 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2649 08:06:12.719891 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2650 08:06:12.723084 == TX Byte 1 ==
2651 08:06:12.726656 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2652 08:06:12.729125 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2653 08:06:12.732729 ==
2654 08:06:12.733141 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 08:06:12.739507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 08:06:12.740099 ==
2657 08:06:12.750430 TX Vref=22, minBit 5, minWin=25, winSum=418
2658 08:06:12.754053 TX Vref=24, minBit 11, minWin=25, winSum=420
2659 08:06:12.756888 TX Vref=26, minBit 1, minWin=26, winSum=427
2660 08:06:12.760136 TX Vref=28, minBit 4, minWin=26, winSum=429
2661 08:06:12.763472 TX Vref=30, minBit 5, minWin=26, winSum=427
2662 08:06:12.770507 TX Vref=32, minBit 13, minWin=25, winSum=426
2663 08:06:12.773370 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 28
2664 08:06:12.773888
2665 08:06:12.776818 Final TX Range 1 Vref 28
2666 08:06:12.777393
2667 08:06:12.777722 ==
2668 08:06:12.779909 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 08:06:12.783803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 08:06:12.786657 ==
2671 08:06:12.787167
2672 08:06:12.787540
2673 08:06:12.787911 TX Vref Scan disable
2674 08:06:12.790363 == TX Byte 0 ==
2675 08:06:12.793574 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2676 08:06:12.796543 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2677 08:06:12.800320 == TX Byte 1 ==
2678 08:06:12.803418 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2679 08:06:12.809857 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2680 08:06:12.810425
2681 08:06:12.810775 [DATLAT]
2682 08:06:12.811082 Freq=1200, CH0 RK0
2683 08:06:12.811375
2684 08:06:12.813260 DATLAT Default: 0xd
2685 08:06:12.813675 0, 0xFFFF, sum = 0
2686 08:06:12.816971 1, 0xFFFF, sum = 0
2687 08:06:12.817392 2, 0xFFFF, sum = 0
2688 08:06:12.820535 3, 0xFFFF, sum = 0
2689 08:06:12.823403 4, 0xFFFF, sum = 0
2690 08:06:12.823974 5, 0xFFFF, sum = 0
2691 08:06:12.826977 6, 0xFFFF, sum = 0
2692 08:06:12.827396 7, 0xFFFF, sum = 0
2693 08:06:12.830195 8, 0xFFFF, sum = 0
2694 08:06:12.830776 9, 0xFFFF, sum = 0
2695 08:06:12.833882 10, 0xFFFF, sum = 0
2696 08:06:12.834393 11, 0xFFFF, sum = 0
2697 08:06:12.836353 12, 0x0, sum = 1
2698 08:06:12.836769 13, 0x0, sum = 2
2699 08:06:12.840975 14, 0x0, sum = 3
2700 08:06:12.841552 15, 0x0, sum = 4
2701 08:06:12.841896 best_step = 13
2702 08:06:12.843280
2703 08:06:12.843688 ==
2704 08:06:12.847109 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 08:06:12.850238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 08:06:12.850651 ==
2707 08:06:12.850976 RX Vref Scan: 1
2708 08:06:12.851296
2709 08:06:12.853340 Set Vref Range= 32 -> 127
2710 08:06:12.853752
2711 08:06:12.856918 RX Vref 32 -> 127, step: 1
2712 08:06:12.857436
2713 08:06:12.859864 RX Delay -21 -> 252, step: 4
2714 08:06:12.860281
2715 08:06:12.863549 Set Vref, RX VrefLevel [Byte0]: 32
2716 08:06:12.866600 [Byte1]: 32
2717 08:06:12.867018
2718 08:06:12.870383 Set Vref, RX VrefLevel [Byte0]: 33
2719 08:06:12.873828 [Byte1]: 33
2720 08:06:12.876929
2721 08:06:12.877452 Set Vref, RX VrefLevel [Byte0]: 34
2722 08:06:12.880299 [Byte1]: 34
2723 08:06:12.884513
2724 08:06:12.885038 Set Vref, RX VrefLevel [Byte0]: 35
2725 08:06:12.888071 [Byte1]: 35
2726 08:06:12.892617
2727 08:06:12.893143 Set Vref, RX VrefLevel [Byte0]: 36
2728 08:06:12.895605 [Byte1]: 36
2729 08:06:12.900345
2730 08:06:12.900878 Set Vref, RX VrefLevel [Byte0]: 37
2731 08:06:12.903600 [Byte1]: 37
2732 08:06:12.908913
2733 08:06:12.909432 Set Vref, RX VrefLevel [Byte0]: 38
2734 08:06:12.911595 [Byte1]: 38
2735 08:06:12.916301
2736 08:06:12.916937 Set Vref, RX VrefLevel [Byte0]: 39
2737 08:06:12.919952 [Byte1]: 39
2738 08:06:12.924095
2739 08:06:12.927965 Set Vref, RX VrefLevel [Byte0]: 40
2740 08:06:12.928484 [Byte1]: 40
2741 08:06:12.932418
2742 08:06:12.932938 Set Vref, RX VrefLevel [Byte0]: 41
2743 08:06:12.936384 [Byte1]: 41
2744 08:06:12.940168
2745 08:06:12.940684 Set Vref, RX VrefLevel [Byte0]: 42
2746 08:06:12.944114 [Byte1]: 42
2747 08:06:12.948026
2748 08:06:12.948434 Set Vref, RX VrefLevel [Byte0]: 43
2749 08:06:12.950942 [Byte1]: 43
2750 08:06:12.956105
2751 08:06:12.956621 Set Vref, RX VrefLevel [Byte0]: 44
2752 08:06:12.959459 [Byte1]: 44
2753 08:06:12.964311
2754 08:06:12.964826 Set Vref, RX VrefLevel [Byte0]: 45
2755 08:06:12.966946 [Byte1]: 45
2756 08:06:12.972132
2757 08:06:12.972643 Set Vref, RX VrefLevel [Byte0]: 46
2758 08:06:12.974976 [Byte1]: 46
2759 08:06:12.980080
2760 08:06:12.980590 Set Vref, RX VrefLevel [Byte0]: 47
2761 08:06:12.983104 [Byte1]: 47
2762 08:06:12.987705
2763 08:06:12.988280 Set Vref, RX VrefLevel [Byte0]: 48
2764 08:06:12.990990 [Byte1]: 48
2765 08:06:12.995461
2766 08:06:12.995903 Set Vref, RX VrefLevel [Byte0]: 49
2767 08:06:12.998968 [Byte1]: 49
2768 08:06:13.003697
2769 08:06:13.004163 Set Vref, RX VrefLevel [Byte0]: 50
2770 08:06:13.007054 [Byte1]: 50
2771 08:06:13.011371
2772 08:06:13.011935 Set Vref, RX VrefLevel [Byte0]: 51
2773 08:06:13.014949 [Byte1]: 51
2774 08:06:13.019156
2775 08:06:13.019585 Set Vref, RX VrefLevel [Byte0]: 52
2776 08:06:13.022566 [Byte1]: 52
2777 08:06:13.027290
2778 08:06:13.027871 Set Vref, RX VrefLevel [Byte0]: 53
2779 08:06:13.030819 [Byte1]: 53
2780 08:06:13.035246
2781 08:06:13.035661 Set Vref, RX VrefLevel [Byte0]: 54
2782 08:06:13.038529 [Byte1]: 54
2783 08:06:13.043295
2784 08:06:13.043991 Set Vref, RX VrefLevel [Byte0]: 55
2785 08:06:13.046205 [Byte1]: 55
2786 08:06:13.050970
2787 08:06:13.051515 Set Vref, RX VrefLevel [Byte0]: 56
2788 08:06:13.054621 [Byte1]: 56
2789 08:06:13.059098
2790 08:06:13.059616 Set Vref, RX VrefLevel [Byte0]: 57
2791 08:06:13.062325 [Byte1]: 57
2792 08:06:13.067043
2793 08:06:13.067601 Set Vref, RX VrefLevel [Byte0]: 58
2794 08:06:13.070113 [Byte1]: 58
2795 08:06:13.075437
2796 08:06:13.076053 Set Vref, RX VrefLevel [Byte0]: 59
2797 08:06:13.078276 [Byte1]: 59
2798 08:06:13.082690
2799 08:06:13.083252 Set Vref, RX VrefLevel [Byte0]: 60
2800 08:06:13.086265 [Byte1]: 60
2801 08:06:13.090949
2802 08:06:13.091508 Set Vref, RX VrefLevel [Byte0]: 61
2803 08:06:13.093979 [Byte1]: 61
2804 08:06:13.098642
2805 08:06:13.099199 Set Vref, RX VrefLevel [Byte0]: 62
2806 08:06:13.102176 [Byte1]: 62
2807 08:06:13.106289
2808 08:06:13.106741 Set Vref, RX VrefLevel [Byte0]: 63
2809 08:06:13.109667 [Byte1]: 63
2810 08:06:13.114403
2811 08:06:13.114929 Set Vref, RX VrefLevel [Byte0]: 64
2812 08:06:13.117645 [Byte1]: 64
2813 08:06:13.122525
2814 08:06:13.123037 Set Vref, RX VrefLevel [Byte0]: 65
2815 08:06:13.126115 [Byte1]: 65
2816 08:06:13.130360
2817 08:06:13.130876 Set Vref, RX VrefLevel [Byte0]: 66
2818 08:06:13.133771 [Byte1]: 66
2819 08:06:13.138282
2820 08:06:13.138837 Set Vref, RX VrefLevel [Byte0]: 67
2821 08:06:13.141195 [Byte1]: 67
2822 08:06:13.146080
2823 08:06:13.146597 Set Vref, RX VrefLevel [Byte0]: 68
2824 08:06:13.149116 [Byte1]: 68
2825 08:06:13.154015
2826 08:06:13.154527 Set Vref, RX VrefLevel [Byte0]: 69
2827 08:06:13.157385 [Byte1]: 69
2828 08:06:13.161827
2829 08:06:13.162391 Set Vref, RX VrefLevel [Byte0]: 70
2830 08:06:13.165326 [Byte1]: 70
2831 08:06:13.170047
2832 08:06:13.170605 Set Vref, RX VrefLevel [Byte0]: 71
2833 08:06:13.173141 [Byte1]: 71
2834 08:06:13.177886
2835 08:06:13.178448 Set Vref, RX VrefLevel [Byte0]: 72
2836 08:06:13.181753 [Byte1]: 72
2837 08:06:13.185859
2838 08:06:13.186483 Set Vref, RX VrefLevel [Byte0]: 73
2839 08:06:13.189393 [Byte1]: 73
2840 08:06:13.193997
2841 08:06:13.194600 Set Vref, RX VrefLevel [Byte0]: 74
2842 08:06:13.197284 [Byte1]: 74
2843 08:06:13.201568
2844 08:06:13.202124 Set Vref, RX VrefLevel [Byte0]: 75
2845 08:06:13.204951 [Byte1]: 75
2846 08:06:13.209867
2847 08:06:13.210424 Set Vref, RX VrefLevel [Byte0]: 76
2848 08:06:13.212684 [Byte1]: 76
2849 08:06:13.217886
2850 08:06:13.218441 Final RX Vref Byte 0 = 61 to rank0
2851 08:06:13.220840 Final RX Vref Byte 1 = 48 to rank0
2852 08:06:13.223849 Final RX Vref Byte 0 = 61 to rank1
2853 08:06:13.227880 Final RX Vref Byte 1 = 48 to rank1==
2854 08:06:13.230531 Dram Type= 6, Freq= 0, CH_0, rank 0
2855 08:06:13.237047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 08:06:13.237556 ==
2857 08:06:13.237882 DQS Delay:
2858 08:06:13.240184 DQS0 = 0, DQS1 = 0
2859 08:06:13.240654 DQM Delay:
2860 08:06:13.240985 DQM0 = 119, DQM1 = 106
2861 08:06:13.243642 DQ Delay:
2862 08:06:13.246820 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2863 08:06:13.250116 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2864 08:06:13.253408 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2865 08:06:13.256983 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2866 08:06:13.257396
2867 08:06:13.257776
2868 08:06:13.267642 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2869 08:06:13.268221 CH0 RK0: MR19=403, MR18=10FC
2870 08:06:13.273725 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2871 08:06:13.274234
2872 08:06:13.277377 ----->DramcWriteLeveling(PI) begin...
2873 08:06:13.277891 ==
2874 08:06:13.280269 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 08:06:13.286816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 08:06:13.287331 ==
2877 08:06:13.290048 Write leveling (Byte 0): 32 => 32
2878 08:06:13.293260 Write leveling (Byte 1): 29 => 29
2879 08:06:13.293678 DramcWriteLeveling(PI) end<-----
2880 08:06:13.294117
2881 08:06:13.296603 ==
2882 08:06:13.297019 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 08:06:13.304099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 08:06:13.304610 ==
2885 08:06:13.306681 [Gating] SW mode calibration
2886 08:06:13.313345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2887 08:06:13.317042 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2888 08:06:13.323455 0 15 0 | B1->B0 | 2322 3232 | 1 0 | (0 0) (0 0)
2889 08:06:13.326754 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 08:06:13.329781 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 08:06:13.336342 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 08:06:13.339541 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 08:06:13.342652 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 08:06:13.349730 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2895 08:06:13.353121 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2896 08:06:13.356890 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2897 08:06:13.362998 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 08:06:13.365947 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 08:06:13.369787 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 08:06:13.376369 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 08:06:13.379558 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 08:06:13.383306 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 08:06:13.389849 1 0 28 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
2904 08:06:13.392591 1 1 0 | B1->B0 | 3b3b 4545 | 0 1 | (0 0) (0 0)
2905 08:06:13.395661 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 08:06:13.402654 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 08:06:13.406867 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 08:06:13.409622 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 08:06:13.416330 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 08:06:13.419266 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2911 08:06:13.422586 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2912 08:06:13.429236 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2913 08:06:13.432324 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 08:06:13.436126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 08:06:13.442837 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 08:06:13.445741 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 08:06:13.448837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 08:06:13.456155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 08:06:13.458983 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 08:06:13.462184 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 08:06:13.465721 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 08:06:13.472696 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 08:06:13.476206 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 08:06:13.479179 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 08:06:13.485898 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 08:06:13.488398 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2927 08:06:13.492313 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2928 08:06:13.498639 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2929 08:06:13.502241 Total UI for P1: 0, mck2ui 16
2930 08:06:13.505634 best dqsien dly found for B0: ( 1, 3, 26)
2931 08:06:13.508633 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 08:06:13.512195 Total UI for P1: 0, mck2ui 16
2933 08:06:13.515530 best dqsien dly found for B1: ( 1, 4, 0)
2934 08:06:13.518600 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2935 08:06:13.521952 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2936 08:06:13.522504
2937 08:06:13.525126 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2938 08:06:13.528271 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2939 08:06:13.531891 [Gating] SW calibration Done
2940 08:06:13.532443 ==
2941 08:06:13.535160 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 08:06:13.541801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 08:06:13.542364 ==
2944 08:06:13.542733 RX Vref Scan: 0
2945 08:06:13.543076
2946 08:06:13.544933 RX Vref 0 -> 0, step: 1
2947 08:06:13.545387
2948 08:06:13.548393 RX Delay -40 -> 252, step: 8
2949 08:06:13.551922 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2950 08:06:13.555006 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2951 08:06:13.558425 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2952 08:06:13.561689 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2953 08:06:13.568139 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2954 08:06:13.571289 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2955 08:06:13.575140 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2956 08:06:13.579203 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2957 08:06:13.581454 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2958 08:06:13.588114 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2959 08:06:13.592200 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2960 08:06:13.594961 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2961 08:06:13.597760 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2962 08:06:13.601513 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2963 08:06:13.607601 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2964 08:06:13.611224 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2965 08:06:13.611842 ==
2966 08:06:13.615011 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 08:06:13.617961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 08:06:13.618525 ==
2969 08:06:13.621734 DQS Delay:
2970 08:06:13.622377 DQS0 = 0, DQS1 = 0
2971 08:06:13.622750 DQM Delay:
2972 08:06:13.624789 DQM0 = 117, DQM1 = 108
2973 08:06:13.625349 DQ Delay:
2974 08:06:13.628646 DQ0 =115, DQ1 =123, DQ2 =111, DQ3 =115
2975 08:06:13.631270 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2976 08:06:13.634514 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2977 08:06:13.641676 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2978 08:06:13.642248
2979 08:06:13.642636
2980 08:06:13.642994 ==
2981 08:06:13.644557 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 08:06:13.647836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 08:06:13.648418 ==
2984 08:06:13.648824
2985 08:06:13.649218
2986 08:06:13.650804 TX Vref Scan disable
2987 08:06:13.655021 == TX Byte 0 ==
2988 08:06:13.658123 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2989 08:06:13.661052 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2990 08:06:13.664380 == TX Byte 1 ==
2991 08:06:13.667647 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2992 08:06:13.671118 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2993 08:06:13.671676 ==
2994 08:06:13.674216 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 08:06:13.677804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 08:06:13.680438 ==
2997 08:06:13.690804 TX Vref=22, minBit 10, minWin=25, winSum=416
2998 08:06:13.694061 TX Vref=24, minBit 13, minWin=25, winSum=421
2999 08:06:13.698168 TX Vref=26, minBit 1, minWin=26, winSum=424
3000 08:06:13.700996 TX Vref=28, minBit 13, minWin=25, winSum=428
3001 08:06:13.704210 TX Vref=30, minBit 12, minWin=25, winSum=429
3002 08:06:13.710926 TX Vref=32, minBit 8, minWin=25, winSum=424
3003 08:06:13.714034 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 26
3004 08:06:13.714627
3005 08:06:13.717367 Final TX Range 1 Vref 26
3006 08:06:13.717928
3007 08:06:13.718296 ==
3008 08:06:13.721131 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 08:06:13.724558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 08:06:13.727775 ==
3011 08:06:13.728346
3012 08:06:13.728715
3013 08:06:13.729056 TX Vref Scan disable
3014 08:06:13.730681 == TX Byte 0 ==
3015 08:06:13.734322 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3016 08:06:13.741215 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3017 08:06:13.741782 == TX Byte 1 ==
3018 08:06:13.744349 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3019 08:06:13.750737 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3020 08:06:13.751329
3021 08:06:13.751760 [DATLAT]
3022 08:06:13.752116 Freq=1200, CH0 RK1
3023 08:06:13.752453
3024 08:06:13.754216 DATLAT Default: 0xd
3025 08:06:13.754728 0, 0xFFFF, sum = 0
3026 08:06:13.757355 1, 0xFFFF, sum = 0
3027 08:06:13.761616 2, 0xFFFF, sum = 0
3028 08:06:13.762147 3, 0xFFFF, sum = 0
3029 08:06:13.764244 4, 0xFFFF, sum = 0
3030 08:06:13.764667 5, 0xFFFF, sum = 0
3031 08:06:13.767810 6, 0xFFFF, sum = 0
3032 08:06:13.768347 7, 0xFFFF, sum = 0
3033 08:06:13.770889 8, 0xFFFF, sum = 0
3034 08:06:13.771418 9, 0xFFFF, sum = 0
3035 08:06:13.774247 10, 0xFFFF, sum = 0
3036 08:06:13.774774 11, 0xFFFF, sum = 0
3037 08:06:13.777358 12, 0x0, sum = 1
3038 08:06:13.777891 13, 0x0, sum = 2
3039 08:06:13.781104 14, 0x0, sum = 3
3040 08:06:13.781632 15, 0x0, sum = 4
3041 08:06:13.784000 best_step = 13
3042 08:06:13.784541
3043 08:06:13.784880 ==
3044 08:06:13.787475 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 08:06:13.790916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 08:06:13.791437 ==
3047 08:06:13.791814 RX Vref Scan: 0
3048 08:06:13.792130
3049 08:06:13.794092 RX Vref 0 -> 0, step: 1
3050 08:06:13.794507
3051 08:06:13.797121 RX Delay -21 -> 252, step: 4
3052 08:06:13.800932 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3053 08:06:13.807123 iDelay=195, Bit 1, Center 120 (47 ~ 194) 148
3054 08:06:13.810638 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3055 08:06:13.814377 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3056 08:06:13.817236 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3057 08:06:13.820876 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3058 08:06:13.827207 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3059 08:06:13.831240 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3060 08:06:13.834063 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3061 08:06:13.837427 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3062 08:06:13.841777 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3063 08:06:13.847403 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3064 08:06:13.850172 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3065 08:06:13.853382 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3066 08:06:13.857361 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3067 08:06:13.863793 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3068 08:06:13.864351 ==
3069 08:06:13.867134 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 08:06:13.870187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 08:06:13.870748 ==
3072 08:06:13.871113 DQS Delay:
3073 08:06:13.873724 DQS0 = 0, DQS1 = 0
3074 08:06:13.874282 DQM Delay:
3075 08:06:13.876996 DQM0 = 116, DQM1 = 107
3076 08:06:13.877547 DQ Delay:
3077 08:06:13.880414 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3078 08:06:13.883381 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3079 08:06:13.887266 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3080 08:06:13.890398 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3081 08:06:13.890966
3082 08:06:13.891332
3083 08:06:13.900128 [DQSOSCAuto] RK1, (LSB)MR18= 0x11eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3084 08:06:13.903667 CH0 RK1: MR19=403, MR18=11EB
3085 08:06:13.906783 CH0_RK1: MR19=0x403, MR18=0x11EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3086 08:06:13.910144 [RxdqsGatingPostProcess] freq 1200
3087 08:06:13.917052 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3088 08:06:13.920121 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 08:06:13.923988 best DQS1 dly(2T, 0.5T) = (0, 12)
3090 08:06:13.926119 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 08:06:13.929710 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3092 08:06:13.933122 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 08:06:13.936476 best DQS1 dly(2T, 0.5T) = (0, 12)
3094 08:06:13.940098 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 08:06:13.942960 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3096 08:06:13.946450 Pre-setting of DQS Precalculation
3097 08:06:13.949431 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3098 08:06:13.949892 ==
3099 08:06:13.952812 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 08:06:13.956685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 08:06:13.957253 ==
3102 08:06:13.963559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 08:06:13.969552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3104 08:06:13.977453 [CA 0] Center 37 (7~68) winsize 62
3105 08:06:13.980424 [CA 1] Center 37 (7~68) winsize 62
3106 08:06:13.984465 [CA 2] Center 34 (4~64) winsize 61
3107 08:06:13.987176 [CA 3] Center 33 (3~64) winsize 62
3108 08:06:13.991036 [CA 4] Center 34 (4~64) winsize 61
3109 08:06:13.993913 [CA 5] Center 33 (3~64) winsize 62
3110 08:06:13.994468
3111 08:06:13.997024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 08:06:13.997489
3113 08:06:14.000618 [CATrainingPosCal] consider 1 rank data
3114 08:06:14.004309 u2DelayCellTimex100 = 270/100 ps
3115 08:06:14.007515 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3116 08:06:14.013784 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3117 08:06:14.017406 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 08:06:14.020812 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3119 08:06:14.023891 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 08:06:14.027040 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3121 08:06:14.027497
3122 08:06:14.030302 CA PerBit enable=1, Macro0, CA PI delay=33
3123 08:06:14.030855
3124 08:06:14.033769 [CBTSetCACLKResult] CA Dly = 33
3125 08:06:14.034357 CS Dly: 6 (0~37)
3126 08:06:14.037770 ==
3127 08:06:14.038318 Dram Type= 6, Freq= 0, CH_1, rank 1
3128 08:06:14.043595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 08:06:14.044214 ==
3130 08:06:14.046930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 08:06:14.053566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3132 08:06:14.063359 [CA 0] Center 37 (7~67) winsize 61
3133 08:06:14.067019 [CA 1] Center 38 (8~68) winsize 61
3134 08:06:14.069647 [CA 2] Center 34 (3~65) winsize 63
3135 08:06:14.072924 [CA 3] Center 33 (3~64) winsize 62
3136 08:06:14.076443 [CA 4] Center 34 (3~65) winsize 63
3137 08:06:14.079829 [CA 5] Center 33 (3~64) winsize 62
3138 08:06:14.080391
3139 08:06:14.082771 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3140 08:06:14.083238
3141 08:06:14.086122 [CATrainingPosCal] consider 2 rank data
3142 08:06:14.090051 u2DelayCellTimex100 = 270/100 ps
3143 08:06:14.093023 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3144 08:06:14.096070 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3145 08:06:14.103444 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 08:06:14.106273 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 08:06:14.110145 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 08:06:14.113568 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 08:06:14.114122
3150 08:06:14.116983 CA PerBit enable=1, Macro0, CA PI delay=33
3151 08:06:14.117534
3152 08:06:14.119845 [CBTSetCACLKResult] CA Dly = 33
3153 08:06:14.120399 CS Dly: 7 (0~40)
3154 08:06:14.120781
3155 08:06:14.122528 ----->DramcWriteLeveling(PI) begin...
3156 08:06:14.126251 ==
3157 08:06:14.130217 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 08:06:14.132864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 08:06:14.133327 ==
3160 08:06:14.136063 Write leveling (Byte 0): 23 => 23
3161 08:06:14.140291 Write leveling (Byte 1): 26 => 26
3162 08:06:14.142969 DramcWriteLeveling(PI) end<-----
3163 08:06:14.143523
3164 08:06:14.143937 ==
3165 08:06:14.146560 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 08:06:14.149560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 08:06:14.150022 ==
3168 08:06:14.152448 [Gating] SW mode calibration
3169 08:06:14.159495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3170 08:06:14.166012 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3171 08:06:14.169217 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3172 08:06:14.172956 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 08:06:14.175646 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 08:06:14.182653 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 08:06:14.186626 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 08:06:14.189497 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 08:06:14.195842 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
3178 08:06:14.199212 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3179 08:06:14.202731 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 08:06:14.208967 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 08:06:14.212294 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 08:06:14.215939 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 08:06:14.222380 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 08:06:14.225687 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 08:06:14.229010 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
3186 08:06:14.235922 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3187 08:06:14.239254 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3188 08:06:14.242205 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 08:06:14.249073 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 08:06:14.252691 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 08:06:14.255271 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 08:06:14.262199 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 08:06:14.265603 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3194 08:06:14.268707 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3195 08:06:14.275297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 08:06:14.278851 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 08:06:14.282206 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 08:06:14.289310 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 08:06:14.292398 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 08:06:14.295333 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 08:06:14.302252 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 08:06:14.305764 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 08:06:14.309008 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 08:06:14.315248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 08:06:14.318801 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 08:06:14.321403 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 08:06:14.328481 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 08:06:14.331635 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 08:06:14.335543 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3210 08:06:14.341856 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 08:06:14.345162 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 08:06:14.348467 Total UI for P1: 0, mck2ui 16
3213 08:06:14.351977 best dqsien dly found for B0: ( 1, 3, 26)
3214 08:06:14.354931 Total UI for P1: 0, mck2ui 16
3215 08:06:14.358438 best dqsien dly found for B1: ( 1, 3, 26)
3216 08:06:14.361695 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3217 08:06:14.364735 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3218 08:06:14.365212
3219 08:06:14.368132 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3220 08:06:14.371232 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3221 08:06:14.374805 [Gating] SW calibration Done
3222 08:06:14.375298 ==
3223 08:06:14.378069 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 08:06:14.381911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 08:06:14.382451 ==
3226 08:06:14.384530 RX Vref Scan: 0
3227 08:06:14.384956
3228 08:06:14.388044 RX Vref 0 -> 0, step: 1
3229 08:06:14.388474
3230 08:06:14.388913 RX Delay -40 -> 252, step: 8
3231 08:06:14.394860 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3232 08:06:14.397630 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3233 08:06:14.401130 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3234 08:06:14.404264 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3235 08:06:14.407669 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3236 08:06:14.414816 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3237 08:06:14.418157 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3238 08:06:14.421095 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3239 08:06:14.424450 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3240 08:06:14.427994 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3241 08:06:14.434603 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3242 08:06:14.437996 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3243 08:06:14.440856 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3244 08:06:14.444297 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3245 08:06:14.448438 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3246 08:06:14.453997 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3247 08:06:14.454457 ==
3248 08:06:14.457813 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 08:06:14.460911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 08:06:14.461468 ==
3251 08:06:14.461841 DQS Delay:
3252 08:06:14.465483 DQS0 = 0, DQS1 = 0
3253 08:06:14.466036 DQM Delay:
3254 08:06:14.467329 DQM0 = 119, DQM1 = 110
3255 08:06:14.467833 DQ Delay:
3256 08:06:14.471443 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3257 08:06:14.474431 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3258 08:06:14.477564 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3259 08:06:14.480899 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3260 08:06:14.481365
3261 08:06:14.481731
3262 08:06:14.484157 ==
3263 08:06:14.487665 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 08:06:14.491164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 08:06:14.491812 ==
3266 08:06:14.492197
3267 08:06:14.492537
3268 08:06:14.494147 TX Vref Scan disable
3269 08:06:14.494698 == TX Byte 0 ==
3270 08:06:14.497333 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3271 08:06:14.504152 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3272 08:06:14.504778 == TX Byte 1 ==
3273 08:06:14.507774 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3274 08:06:14.514085 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3275 08:06:14.514628 ==
3276 08:06:14.517613 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 08:06:14.520381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 08:06:14.520900 ==
3279 08:06:14.532868 TX Vref=22, minBit 13, minWin=25, winSum=418
3280 08:06:14.535915 TX Vref=24, minBit 1, minWin=26, winSum=423
3281 08:06:14.539472 TX Vref=26, minBit 1, minWin=26, winSum=428
3282 08:06:14.543151 TX Vref=28, minBit 0, minWin=26, winSum=428
3283 08:06:14.545871 TX Vref=30, minBit 13, minWin=25, winSum=424
3284 08:06:14.552687 TX Vref=32, minBit 15, minWin=25, winSum=426
3285 08:06:14.556205 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 26
3286 08:06:14.556690
3287 08:06:14.559686 Final TX Range 1 Vref 26
3288 08:06:14.560328
3289 08:06:14.560817 ==
3290 08:06:14.562415 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 08:06:14.565996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 08:06:14.569455 ==
3293 08:06:14.570036
3294 08:06:14.570524
3295 08:06:14.570978 TX Vref Scan disable
3296 08:06:14.572907 == TX Byte 0 ==
3297 08:06:14.576112 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3298 08:06:14.582792 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3299 08:06:14.583379 == TX Byte 1 ==
3300 08:06:14.586199 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3301 08:06:14.592393 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3302 08:06:14.592968
3303 08:06:14.593455 [DATLAT]
3304 08:06:14.593915 Freq=1200, CH1 RK0
3305 08:06:14.594362
3306 08:06:14.596062 DATLAT Default: 0xd
3307 08:06:14.596673 0, 0xFFFF, sum = 0
3308 08:06:14.599210 1, 0xFFFF, sum = 0
3309 08:06:14.602942 2, 0xFFFF, sum = 0
3310 08:06:14.603357 3, 0xFFFF, sum = 0
3311 08:06:14.605958 4, 0xFFFF, sum = 0
3312 08:06:14.606374 5, 0xFFFF, sum = 0
3313 08:06:14.608910 6, 0xFFFF, sum = 0
3314 08:06:14.609330 7, 0xFFFF, sum = 0
3315 08:06:14.612845 8, 0xFFFF, sum = 0
3316 08:06:14.613262 9, 0xFFFF, sum = 0
3317 08:06:14.615915 10, 0xFFFF, sum = 0
3318 08:06:14.616332 11, 0xFFFF, sum = 0
3319 08:06:14.618897 12, 0x0, sum = 1
3320 08:06:14.619313 13, 0x0, sum = 2
3321 08:06:14.622698 14, 0x0, sum = 3
3322 08:06:14.623149 15, 0x0, sum = 4
3323 08:06:14.626157 best_step = 13
3324 08:06:14.626677
3325 08:06:14.627009 ==
3326 08:06:14.629258 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 08:06:14.632414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 08:06:14.632830 ==
3329 08:06:14.633159 RX Vref Scan: 1
3330 08:06:14.633467
3331 08:06:14.635355 Set Vref Range= 32 -> 127
3332 08:06:14.635802
3333 08:06:14.639868 RX Vref 32 -> 127, step: 1
3334 08:06:14.640388
3335 08:06:14.642813 RX Delay -21 -> 252, step: 4
3336 08:06:14.643324
3337 08:06:14.645492 Set Vref, RX VrefLevel [Byte0]: 32
3338 08:06:14.649019 [Byte1]: 32
3339 08:06:14.649534
3340 08:06:14.652227 Set Vref, RX VrefLevel [Byte0]: 33
3341 08:06:14.655578 [Byte1]: 33
3342 08:06:14.659216
3343 08:06:14.659780 Set Vref, RX VrefLevel [Byte0]: 34
3344 08:06:14.663043 [Byte1]: 34
3345 08:06:14.667051
3346 08:06:14.667462 Set Vref, RX VrefLevel [Byte0]: 35
3347 08:06:14.670354 [Byte1]: 35
3348 08:06:14.674955
3349 08:06:14.675473 Set Vref, RX VrefLevel [Byte0]: 36
3350 08:06:14.678327 [Byte1]: 36
3351 08:06:14.683127
3352 08:06:14.683683 Set Vref, RX VrefLevel [Byte0]: 37
3353 08:06:14.686288 [Byte1]: 37
3354 08:06:14.691522
3355 08:06:14.692137 Set Vref, RX VrefLevel [Byte0]: 38
3356 08:06:14.693989 [Byte1]: 38
3357 08:06:14.699496
3358 08:06:14.699995 Set Vref, RX VrefLevel [Byte0]: 39
3359 08:06:14.702453 [Byte1]: 39
3360 08:06:14.706932
3361 08:06:14.707487 Set Vref, RX VrefLevel [Byte0]: 40
3362 08:06:14.713399 [Byte1]: 40
3363 08:06:14.713960
3364 08:06:14.716328 Set Vref, RX VrefLevel [Byte0]: 41
3365 08:06:14.720411 [Byte1]: 41
3366 08:06:14.720968
3367 08:06:14.722727 Set Vref, RX VrefLevel [Byte0]: 42
3368 08:06:14.726596 [Byte1]: 42
3369 08:06:14.730916
3370 08:06:14.731468 Set Vref, RX VrefLevel [Byte0]: 43
3371 08:06:14.734203 [Byte1]: 43
3372 08:06:14.738518
3373 08:06:14.739074 Set Vref, RX VrefLevel [Byte0]: 44
3374 08:06:14.741933 [Byte1]: 44
3375 08:06:14.746434
3376 08:06:14.746985 Set Vref, RX VrefLevel [Byte0]: 45
3377 08:06:14.749926 [Byte1]: 45
3378 08:06:14.754240
3379 08:06:14.754801 Set Vref, RX VrefLevel [Byte0]: 46
3380 08:06:14.757367 [Byte1]: 46
3381 08:06:14.761889
3382 08:06:14.762363 Set Vref, RX VrefLevel [Byte0]: 47
3383 08:06:14.765488 [Byte1]: 47
3384 08:06:14.770603
3385 08:06:14.771162 Set Vref, RX VrefLevel [Byte0]: 48
3386 08:06:14.773059 [Byte1]: 48
3387 08:06:14.778200
3388 08:06:14.778740 Set Vref, RX VrefLevel [Byte0]: 49
3389 08:06:14.780980 [Byte1]: 49
3390 08:06:14.786424
3391 08:06:14.786985 Set Vref, RX VrefLevel [Byte0]: 50
3392 08:06:14.789302 [Byte1]: 50
3393 08:06:14.793951
3394 08:06:14.794511 Set Vref, RX VrefLevel [Byte0]: 51
3395 08:06:14.797720 [Byte1]: 51
3396 08:06:14.801679
3397 08:06:14.802243 Set Vref, RX VrefLevel [Byte0]: 52
3398 08:06:14.805548 [Byte1]: 52
3399 08:06:14.809681
3400 08:06:14.810294 Set Vref, RX VrefLevel [Byte0]: 53
3401 08:06:14.812996 [Byte1]: 53
3402 08:06:14.817594
3403 08:06:14.818153 Set Vref, RX VrefLevel [Byte0]: 54
3404 08:06:14.820954 [Byte1]: 54
3405 08:06:14.825673
3406 08:06:14.826234 Set Vref, RX VrefLevel [Byte0]: 55
3407 08:06:14.829066 [Byte1]: 55
3408 08:06:14.833500
3409 08:06:14.834082 Set Vref, RX VrefLevel [Byte0]: 56
3410 08:06:14.836461 [Byte1]: 56
3411 08:06:14.841335
3412 08:06:14.844614 Set Vref, RX VrefLevel [Byte0]: 57
3413 08:06:14.847691 [Byte1]: 57
3414 08:06:14.848300
3415 08:06:14.850906 Set Vref, RX VrefLevel [Byte0]: 58
3416 08:06:14.854314 [Byte1]: 58
3417 08:06:14.854875
3418 08:06:14.857583 Set Vref, RX VrefLevel [Byte0]: 59
3419 08:06:14.860805 [Byte1]: 59
3420 08:06:14.865120
3421 08:06:14.865678 Set Vref, RX VrefLevel [Byte0]: 60
3422 08:06:14.868198 [Byte1]: 60
3423 08:06:14.872877
3424 08:06:14.873452 Set Vref, RX VrefLevel [Byte0]: 61
3425 08:06:14.876304 [Byte1]: 61
3426 08:06:14.881159
3427 08:06:14.881715 Set Vref, RX VrefLevel [Byte0]: 62
3428 08:06:14.884010 [Byte1]: 62
3429 08:06:14.888740
3430 08:06:14.889293 Set Vref, RX VrefLevel [Byte0]: 63
3431 08:06:14.892162 [Byte1]: 63
3432 08:06:14.896937
3433 08:06:14.897642 Set Vref, RX VrefLevel [Byte0]: 64
3434 08:06:14.899764 [Byte1]: 64
3435 08:06:14.904559
3436 08:06:14.905112 Set Vref, RX VrefLevel [Byte0]: 65
3437 08:06:14.910709 [Byte1]: 65
3438 08:06:14.911254
3439 08:06:14.914238 Set Vref, RX VrefLevel [Byte0]: 66
3440 08:06:14.918078 [Byte1]: 66
3441 08:06:14.918636
3442 08:06:14.920645 Set Vref, RX VrefLevel [Byte0]: 67
3443 08:06:14.924082 [Byte1]: 67
3444 08:06:14.928652
3445 08:06:14.929211 Set Vref, RX VrefLevel [Byte0]: 68
3446 08:06:14.931777 [Byte1]: 68
3447 08:06:14.936834
3448 08:06:14.937389 Set Vref, RX VrefLevel [Byte0]: 69
3449 08:06:14.939573 [Byte1]: 69
3450 08:06:14.944263
3451 08:06:14.944890 Final RX Vref Byte 0 = 50 to rank0
3452 08:06:14.947896 Final RX Vref Byte 1 = 52 to rank0
3453 08:06:14.950954 Final RX Vref Byte 0 = 50 to rank1
3454 08:06:14.954105 Final RX Vref Byte 1 = 52 to rank1==
3455 08:06:14.957538 Dram Type= 6, Freq= 0, CH_1, rank 0
3456 08:06:14.964764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 08:06:14.965336 ==
3458 08:06:14.965703 DQS Delay:
3459 08:06:14.966043 DQS0 = 0, DQS1 = 0
3460 08:06:14.967519 DQM Delay:
3461 08:06:14.968019 DQM0 = 117, DQM1 = 112
3462 08:06:14.971221 DQ Delay:
3463 08:06:14.974597 DQ0 =122, DQ1 =112, DQ2 =110, DQ3 =112
3464 08:06:14.977454 DQ4 =116, DQ5 =128, DQ6 =126, DQ7 =114
3465 08:06:14.980967 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =100
3466 08:06:14.983815 DQ12 =118, DQ13 =120, DQ14 =122, DQ15 =120
3467 08:06:14.984276
3468 08:06:14.984637
3469 08:06:14.991025 [DQSOSCAuto] RK0, (LSB)MR18= 0x7fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3470 08:06:14.994609 CH1 RK0: MR19=403, MR18=7FA
3471 08:06:15.000397 CH1_RK0: MR19=0x403, MR18=0x7FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3472 08:06:15.000855
3473 08:06:15.004438 ----->DramcWriteLeveling(PI) begin...
3474 08:06:15.005005 ==
3475 08:06:15.008048 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 08:06:15.011211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 08:06:15.013951 ==
3478 08:06:15.014585 Write leveling (Byte 0): 25 => 25
3479 08:06:15.017579 Write leveling (Byte 1): 28 => 28
3480 08:06:15.020818 DramcWriteLeveling(PI) end<-----
3481 08:06:15.021374
3482 08:06:15.021739 ==
3483 08:06:15.023646 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 08:06:15.030584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 08:06:15.031141 ==
3486 08:06:15.033876 [Gating] SW mode calibration
3487 08:06:15.040474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3488 08:06:15.043493 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3489 08:06:15.050428 0 15 0 | B1->B0 | 3433 3232 | 1 1 | (0 0) (0 0)
3490 08:06:15.053217 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 08:06:15.056660 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 08:06:15.063948 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 08:06:15.066735 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 08:06:15.069742 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 08:06:15.076496 0 15 24 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
3496 08:06:15.080118 0 15 28 | B1->B0 | 2828 2d2d | 0 0 | (1 1) (1 0)
3497 08:06:15.083499 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3498 08:06:15.090029 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 08:06:15.092782 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 08:06:15.096689 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 08:06:15.102549 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 08:06:15.106412 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 08:06:15.109605 1 0 24 | B1->B0 | 3131 2626 | 1 0 | (0 0) (0 0)
3504 08:06:15.117415 1 0 28 | B1->B0 | 4545 3c3c | 0 0 | (0 0) (0 0)
3505 08:06:15.119401 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 08:06:15.122645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 08:06:15.129912 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 08:06:15.132899 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 08:06:15.136392 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 08:06:15.142849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 08:06:15.145997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3512 08:06:15.149394 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3513 08:06:15.156124 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 08:06:15.158789 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 08:06:15.162333 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 08:06:15.169029 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 08:06:15.172469 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 08:06:15.175908 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 08:06:15.182174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 08:06:15.185366 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 08:06:15.188589 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 08:06:15.195224 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 08:06:15.198754 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 08:06:15.201960 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 08:06:15.208288 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 08:06:15.211302 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 08:06:15.215057 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3528 08:06:15.221646 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3529 08:06:15.222212 Total UI for P1: 0, mck2ui 16
3530 08:06:15.228247 best dqsien dly found for B1: ( 1, 3, 24)
3531 08:06:15.232090 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 08:06:15.235193 Total UI for P1: 0, mck2ui 16
3533 08:06:15.237650 best dqsien dly found for B0: ( 1, 3, 26)
3534 08:06:15.242136 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3535 08:06:15.244485 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3536 08:06:15.245041
3537 08:06:15.247830 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3538 08:06:15.251652 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3539 08:06:15.254532 [Gating] SW calibration Done
3540 08:06:15.254991 ==
3541 08:06:15.259513 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 08:06:15.261470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 08:06:15.264225 ==
3544 08:06:15.264684 RX Vref Scan: 0
3545 08:06:15.265051
3546 08:06:15.268257 RX Vref 0 -> 0, step: 1
3547 08:06:15.268712
3548 08:06:15.271380 RX Delay -40 -> 252, step: 8
3549 08:06:15.274674 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3550 08:06:15.277651 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3551 08:06:15.280998 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3552 08:06:15.284734 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3553 08:06:15.290954 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3554 08:06:15.294081 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3555 08:06:15.297058 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3556 08:06:15.300567 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3557 08:06:15.304208 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3558 08:06:15.310287 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3559 08:06:15.313754 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3560 08:06:15.316844 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3561 08:06:15.320583 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3562 08:06:15.326905 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3563 08:06:15.330304 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3564 08:06:15.333446 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3565 08:06:15.334012 ==
3566 08:06:15.336732 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 08:06:15.340558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 08:06:15.341155 ==
3569 08:06:15.343991 DQS Delay:
3570 08:06:15.344548 DQS0 = 0, DQS1 = 0
3571 08:06:15.346970 DQM Delay:
3572 08:06:15.347524 DQM0 = 117, DQM1 = 110
3573 08:06:15.347949 DQ Delay:
3574 08:06:15.353793 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3575 08:06:15.356659 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3576 08:06:15.359691 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3577 08:06:15.363364 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3578 08:06:15.364097
3579 08:06:15.364480
3580 08:06:15.364820 ==
3581 08:06:15.366659 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 08:06:15.370067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 08:06:15.370631 ==
3584 08:06:15.371002
3585 08:06:15.371340
3586 08:06:15.373320 TX Vref Scan disable
3587 08:06:15.376223 == TX Byte 0 ==
3588 08:06:15.379946 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3589 08:06:15.382765 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3590 08:06:15.386082 == TX Byte 1 ==
3591 08:06:15.390260 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3592 08:06:15.392634 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3593 08:06:15.393097 ==
3594 08:06:15.395913 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 08:06:15.399802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 08:06:15.402902 ==
3597 08:06:15.413124 TX Vref=22, minBit 0, minWin=25, winSum=420
3598 08:06:15.416170 TX Vref=24, minBit 9, minWin=25, winSum=424
3599 08:06:15.419494 TX Vref=26, minBit 0, minWin=26, winSum=430
3600 08:06:15.422596 TX Vref=28, minBit 5, minWin=26, winSum=430
3601 08:06:15.425863 TX Vref=30, minBit 5, minWin=26, winSum=430
3602 08:06:15.432794 TX Vref=32, minBit 5, minWin=26, winSum=427
3603 08:06:15.436156 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
3604 08:06:15.436577
3605 08:06:15.439583 Final TX Range 1 Vref 26
3606 08:06:15.440027
3607 08:06:15.440360 ==
3608 08:06:15.442567 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 08:06:15.446100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 08:06:15.449406 ==
3611 08:06:15.449934
3612 08:06:15.450265
3613 08:06:15.450571 TX Vref Scan disable
3614 08:06:15.452461 == TX Byte 0 ==
3615 08:06:15.455812 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3616 08:06:15.463035 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3617 08:06:15.463632 == TX Byte 1 ==
3618 08:06:15.465774 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3619 08:06:15.472721 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3620 08:06:15.473284
3621 08:06:15.473652 [DATLAT]
3622 08:06:15.473993 Freq=1200, CH1 RK1
3623 08:06:15.475835
3624 08:06:15.476296 DATLAT Default: 0xd
3625 08:06:15.478915 0, 0xFFFF, sum = 0
3626 08:06:15.479485 1, 0xFFFF, sum = 0
3627 08:06:15.482511 2, 0xFFFF, sum = 0
3628 08:06:15.483074 3, 0xFFFF, sum = 0
3629 08:06:15.485981 4, 0xFFFF, sum = 0
3630 08:06:15.486553 5, 0xFFFF, sum = 0
3631 08:06:15.489110 6, 0xFFFF, sum = 0
3632 08:06:15.489576 7, 0xFFFF, sum = 0
3633 08:06:15.492959 8, 0xFFFF, sum = 0
3634 08:06:15.493528 9, 0xFFFF, sum = 0
3635 08:06:15.495895 10, 0xFFFF, sum = 0
3636 08:06:15.496463 11, 0xFFFF, sum = 0
3637 08:06:15.498596 12, 0x0, sum = 1
3638 08:06:15.499063 13, 0x0, sum = 2
3639 08:06:15.502331 14, 0x0, sum = 3
3640 08:06:15.502900 15, 0x0, sum = 4
3641 08:06:15.505899 best_step = 13
3642 08:06:15.506459
3643 08:06:15.506829 ==
3644 08:06:15.508620 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 08:06:15.512053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 08:06:15.512681 ==
3647 08:06:15.515279 RX Vref Scan: 0
3648 08:06:15.515763
3649 08:06:15.516136 RX Vref 0 -> 0, step: 1
3650 08:06:15.516475
3651 08:06:15.518709 RX Delay -21 -> 252, step: 4
3652 08:06:15.524892 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3653 08:06:15.530161 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3654 08:06:15.532379 iDelay=199, Bit 2, Center 108 (47 ~ 170) 124
3655 08:06:15.535015 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3656 08:06:15.538716 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3657 08:06:15.545388 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3658 08:06:15.548502 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3659 08:06:15.551511 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3660 08:06:15.555042 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3661 08:06:15.558366 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3662 08:06:15.564721 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3663 08:06:15.567934 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3664 08:06:15.571082 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3665 08:06:15.574908 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3666 08:06:15.581103 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3667 08:06:15.584153 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3668 08:06:15.584608 ==
3669 08:06:15.587671 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 08:06:15.591413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 08:06:15.592038 ==
3672 08:06:15.594035 DQS Delay:
3673 08:06:15.594492 DQS0 = 0, DQS1 = 0
3674 08:06:15.594855 DQM Delay:
3675 08:06:15.598086 DQM0 = 118, DQM1 = 111
3676 08:06:15.598557 DQ Delay:
3677 08:06:15.600978 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3678 08:06:15.604499 DQ4 =116, DQ5 =128, DQ6 =132, DQ7 =116
3679 08:06:15.607776 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3680 08:06:15.614706 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =118
3681 08:06:15.615263
3682 08:06:15.615626
3683 08:06:15.621154 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3684 08:06:15.623930 CH1 RK1: MR19=303, MR18=F3ED
3685 08:06:15.630896 CH1_RK1: MR19=0x303, MR18=0xF3ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3686 08:06:15.633834 [RxdqsGatingPostProcess] freq 1200
3687 08:06:15.637064 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3688 08:06:15.640639 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 08:06:15.643711 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 08:06:15.647136 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 08:06:15.650122 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 08:06:15.654168 best DQS0 dly(2T, 0.5T) = (0, 11)
3693 08:06:15.656743 best DQS1 dly(2T, 0.5T) = (0, 11)
3694 08:06:15.660650 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3695 08:06:15.664314 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3696 08:06:15.667362 Pre-setting of DQS Precalculation
3697 08:06:15.670842 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3698 08:06:15.680249 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3699 08:06:15.687480 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3700 08:06:15.688133
3701 08:06:15.688624
3702 08:06:15.690646 [Calibration Summary] 2400 Mbps
3703 08:06:15.691200 CH 0, Rank 0
3704 08:06:15.693750 SW Impedance : PASS
3705 08:06:15.694323 DUTY Scan : NO K
3706 08:06:15.697343 ZQ Calibration : PASS
3707 08:06:15.700238 Jitter Meter : NO K
3708 08:06:15.700716 CBT Training : PASS
3709 08:06:15.703788 Write leveling : PASS
3710 08:06:15.707533 RX DQS gating : PASS
3711 08:06:15.708201 RX DQ/DQS(RDDQC) : PASS
3712 08:06:15.710494 TX DQ/DQS : PASS
3713 08:06:15.713991 RX DATLAT : PASS
3714 08:06:15.714563 RX DQ/DQS(Engine): PASS
3715 08:06:15.717058 TX OE : NO K
3716 08:06:15.717540 All Pass.
3717 08:06:15.718024
3718 08:06:15.720052 CH 0, Rank 1
3719 08:06:15.720532 SW Impedance : PASS
3720 08:06:15.723268 DUTY Scan : NO K
3721 08:06:15.727365 ZQ Calibration : PASS
3722 08:06:15.727891 Jitter Meter : NO K
3723 08:06:15.730337 CBT Training : PASS
3724 08:06:15.733309 Write leveling : PASS
3725 08:06:15.733880 RX DQS gating : PASS
3726 08:06:15.736586 RX DQ/DQS(RDDQC) : PASS
3727 08:06:15.739830 TX DQ/DQS : PASS
3728 08:06:15.740314 RX DATLAT : PASS
3729 08:06:15.743388 RX DQ/DQS(Engine): PASS
3730 08:06:15.743957 TX OE : NO K
3731 08:06:15.747063 All Pass.
3732 08:06:15.747603
3733 08:06:15.748096 CH 1, Rank 0
3734 08:06:15.749691 SW Impedance : PASS
3735 08:06:15.753263 DUTY Scan : NO K
3736 08:06:15.753790 ZQ Calibration : PASS
3737 08:06:15.756422 Jitter Meter : NO K
3738 08:06:15.756948 CBT Training : PASS
3739 08:06:15.759713 Write leveling : PASS
3740 08:06:15.762851 RX DQS gating : PASS
3741 08:06:15.763398 RX DQ/DQS(RDDQC) : PASS
3742 08:06:15.765902 TX DQ/DQS : PASS
3743 08:06:15.769327 RX DATLAT : PASS
3744 08:06:15.769859 RX DQ/DQS(Engine): PASS
3745 08:06:15.772649 TX OE : NO K
3746 08:06:15.773082 All Pass.
3747 08:06:15.773524
3748 08:06:15.775675 CH 1, Rank 1
3749 08:06:15.776145 SW Impedance : PASS
3750 08:06:15.779498 DUTY Scan : NO K
3751 08:06:15.782531 ZQ Calibration : PASS
3752 08:06:15.783008 Jitter Meter : NO K
3753 08:06:15.786347 CBT Training : PASS
3754 08:06:15.789498 Write leveling : PASS
3755 08:06:15.790026 RX DQS gating : PASS
3756 08:06:15.792414 RX DQ/DQS(RDDQC) : PASS
3757 08:06:15.795900 TX DQ/DQS : PASS
3758 08:06:15.796426 RX DATLAT : PASS
3759 08:06:15.798673 RX DQ/DQS(Engine): PASS
3760 08:06:15.802199 TX OE : NO K
3761 08:06:15.802625 All Pass.
3762 08:06:15.802965
3763 08:06:15.805619 DramC Write-DBI off
3764 08:06:15.806134 PER_BANK_REFRESH: Hybrid Mode
3765 08:06:15.809602 TX_TRACKING: ON
3766 08:06:15.815811 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3767 08:06:15.822090 [FAST_K] Save calibration result to emmc
3768 08:06:15.825214 dramc_set_vcore_voltage set vcore to 650000
3769 08:06:15.825637 Read voltage for 600, 5
3770 08:06:15.829174 Vio18 = 0
3771 08:06:15.829686 Vcore = 650000
3772 08:06:15.830022 Vdram = 0
3773 08:06:15.831845 Vddq = 0
3774 08:06:15.832210 Vmddr = 0
3775 08:06:15.835619 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3776 08:06:15.841753 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3777 08:06:15.845243 MEM_TYPE=3, freq_sel=19
3778 08:06:15.848460 sv_algorithm_assistance_LP4_1600
3779 08:06:15.851865 ============ PULL DRAM RESETB DOWN ============
3780 08:06:15.854907 ========== PULL DRAM RESETB DOWN end =========
3781 08:06:15.861424 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3782 08:06:15.864593 ===================================
3783 08:06:15.865024 LPDDR4 DRAM CONFIGURATION
3784 08:06:15.867672 ===================================
3785 08:06:15.872721 EX_ROW_EN[0] = 0x0
3786 08:06:15.875479 EX_ROW_EN[1] = 0x0
3787 08:06:15.876031 LP4Y_EN = 0x0
3788 08:06:15.878438 WORK_FSP = 0x0
3789 08:06:15.878953 WL = 0x2
3790 08:06:15.881839 RL = 0x2
3791 08:06:15.882350 BL = 0x2
3792 08:06:15.884575 RPST = 0x0
3793 08:06:15.884997 RD_PRE = 0x0
3794 08:06:15.887839 WR_PRE = 0x1
3795 08:06:15.888399 WR_PST = 0x0
3796 08:06:15.891151 DBI_WR = 0x0
3797 08:06:15.891717 DBI_RD = 0x0
3798 08:06:15.894630 OTF = 0x1
3799 08:06:15.897944 ===================================
3800 08:06:15.901149 ===================================
3801 08:06:15.901581 ANA top config
3802 08:06:15.904374 ===================================
3803 08:06:15.907783 DLL_ASYNC_EN = 0
3804 08:06:15.910980 ALL_SLAVE_EN = 1
3805 08:06:15.914315 NEW_RANK_MODE = 1
3806 08:06:15.914829 DLL_IDLE_MODE = 1
3807 08:06:15.918450 LP45_APHY_COMB_EN = 1
3808 08:06:15.920649 TX_ODT_DIS = 1
3809 08:06:15.924221 NEW_8X_MODE = 1
3810 08:06:15.927596 ===================================
3811 08:06:15.931087 ===================================
3812 08:06:15.934269 data_rate = 1200
3813 08:06:15.934793 CKR = 1
3814 08:06:15.937387 DQ_P2S_RATIO = 8
3815 08:06:15.940829 ===================================
3816 08:06:15.944752 CA_P2S_RATIO = 8
3817 08:06:15.947312 DQ_CA_OPEN = 0
3818 08:06:15.950649 DQ_SEMI_OPEN = 0
3819 08:06:15.953908 CA_SEMI_OPEN = 0
3820 08:06:15.954473 CA_FULL_RATE = 0
3821 08:06:15.957236 DQ_CKDIV4_EN = 1
3822 08:06:15.961081 CA_CKDIV4_EN = 1
3823 08:06:15.963582 CA_PREDIV_EN = 0
3824 08:06:15.967259 PH8_DLY = 0
3825 08:06:15.970940 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3826 08:06:15.971499 DQ_AAMCK_DIV = 4
3827 08:06:15.973647 CA_AAMCK_DIV = 4
3828 08:06:15.977512 CA_ADMCK_DIV = 4
3829 08:06:15.980630 DQ_TRACK_CA_EN = 0
3830 08:06:15.983596 CA_PICK = 600
3831 08:06:15.987621 CA_MCKIO = 600
3832 08:06:15.990030 MCKIO_SEMI = 0
3833 08:06:15.993309 PLL_FREQ = 2288
3834 08:06:15.993867 DQ_UI_PI_RATIO = 32
3835 08:06:15.996568 CA_UI_PI_RATIO = 0
3836 08:06:15.999560 ===================================
3837 08:06:16.003058 ===================================
3838 08:06:16.007922 memory_type:LPDDR4
3839 08:06:16.010162 GP_NUM : 10
3840 08:06:16.010714 SRAM_EN : 1
3841 08:06:16.012941 MD32_EN : 0
3842 08:06:16.016670 ===================================
3843 08:06:16.019620 [ANA_INIT] >>>>>>>>>>>>>>
3844 08:06:16.020214 <<<<<< [CONFIGURE PHASE]: ANA_TX
3845 08:06:16.022919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3846 08:06:16.026251 ===================================
3847 08:06:16.029571 data_rate = 1200,PCW = 0X5800
3848 08:06:16.033091 ===================================
3849 08:06:16.036467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3850 08:06:16.042873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3851 08:06:16.049451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 08:06:16.052631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3853 08:06:16.056368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3854 08:06:16.060158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3855 08:06:16.062899 [ANA_INIT] flow start
3856 08:06:16.063483 [ANA_INIT] PLL >>>>>>>>
3857 08:06:16.065802 [ANA_INIT] PLL <<<<<<<<
3858 08:06:16.070589 [ANA_INIT] MIDPI >>>>>>>>
3859 08:06:16.072427 [ANA_INIT] MIDPI <<<<<<<<
3860 08:06:16.072888 [ANA_INIT] DLL >>>>>>>>
3861 08:06:16.075632 [ANA_INIT] flow end
3862 08:06:16.079171 ============ LP4 DIFF to SE enter ============
3863 08:06:16.082415 ============ LP4 DIFF to SE exit ============
3864 08:06:16.085821 [ANA_INIT] <<<<<<<<<<<<<
3865 08:06:16.089021 [Flow] Enable top DCM control >>>>>
3866 08:06:16.092183 [Flow] Enable top DCM control <<<<<
3867 08:06:16.096433 Enable DLL master slave shuffle
3868 08:06:16.102150 ==============================================================
3869 08:06:16.102697 Gating Mode config
3870 08:06:16.109036 ==============================================================
3871 08:06:16.109596 Config description:
3872 08:06:16.118978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3873 08:06:16.124885 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3874 08:06:16.131632 SELPH_MODE 0: By rank 1: By Phase
3875 08:06:16.135421 ==============================================================
3876 08:06:16.138415 GAT_TRACK_EN = 1
3877 08:06:16.141832 RX_GATING_MODE = 2
3878 08:06:16.144709 RX_GATING_TRACK_MODE = 2
3879 08:06:16.148385 SELPH_MODE = 1
3880 08:06:16.151700 PICG_EARLY_EN = 1
3881 08:06:16.155224 VALID_LAT_VALUE = 1
3882 08:06:16.161475 ==============================================================
3883 08:06:16.164639 Enter into Gating configuration >>>>
3884 08:06:16.167947 Exit from Gating configuration <<<<
3885 08:06:16.172004 Enter into DVFS_PRE_config >>>>>
3886 08:06:16.181354 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3887 08:06:16.184393 Exit from DVFS_PRE_config <<<<<
3888 08:06:16.187662 Enter into PICG configuration >>>>
3889 08:06:16.191031 Exit from PICG configuration <<<<
3890 08:06:16.194452 [RX_INPUT] configuration >>>>>
3891 08:06:16.198308 [RX_INPUT] configuration <<<<<
3892 08:06:16.200915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3893 08:06:16.207617 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3894 08:06:16.213940 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3895 08:06:16.217923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3896 08:06:16.224302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 08:06:16.230570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 08:06:16.234252 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3899 08:06:16.240768 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3900 08:06:16.244599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3901 08:06:16.247551 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3902 08:06:16.251089 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3903 08:06:16.257224 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3904 08:06:16.260741 ===================================
3905 08:06:16.261303 LPDDR4 DRAM CONFIGURATION
3906 08:06:16.264394 ===================================
3907 08:06:16.267361 EX_ROW_EN[0] = 0x0
3908 08:06:16.270471 EX_ROW_EN[1] = 0x0
3909 08:06:16.271028 LP4Y_EN = 0x0
3910 08:06:16.273786 WORK_FSP = 0x0
3911 08:06:16.274251 WL = 0x2
3912 08:06:16.277179 RL = 0x2
3913 08:06:16.277643 BL = 0x2
3914 08:06:16.280416 RPST = 0x0
3915 08:06:16.280880 RD_PRE = 0x0
3916 08:06:16.283874 WR_PRE = 0x1
3917 08:06:16.284421 WR_PST = 0x0
3918 08:06:16.287296 DBI_WR = 0x0
3919 08:06:16.287896 DBI_RD = 0x0
3920 08:06:16.291146 OTF = 0x1
3921 08:06:16.293821 ===================================
3922 08:06:16.297256 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3923 08:06:16.300115 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3924 08:06:16.306616 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 08:06:16.310984 ===================================
3926 08:06:16.311591 LPDDR4 DRAM CONFIGURATION
3927 08:06:16.313552 ===================================
3928 08:06:16.317012 EX_ROW_EN[0] = 0x10
3929 08:06:16.320660 EX_ROW_EN[1] = 0x0
3930 08:06:16.321217 LP4Y_EN = 0x0
3931 08:06:16.323451 WORK_FSP = 0x0
3932 08:06:16.324054 WL = 0x2
3933 08:06:16.326449 RL = 0x2
3934 08:06:16.326913 BL = 0x2
3935 08:06:16.330402 RPST = 0x0
3936 08:06:16.330956 RD_PRE = 0x0
3937 08:06:16.333621 WR_PRE = 0x1
3938 08:06:16.334194 WR_PST = 0x0
3939 08:06:16.336415 DBI_WR = 0x0
3940 08:06:16.336973 DBI_RD = 0x0
3941 08:06:16.340128 OTF = 0x1
3942 08:06:16.342928 ===================================
3943 08:06:16.350141 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3944 08:06:16.353070 nWR fixed to 30
3945 08:06:16.356351 [ModeRegInit_LP4] CH0 RK0
3946 08:06:16.356906 [ModeRegInit_LP4] CH0 RK1
3947 08:06:16.359539 [ModeRegInit_LP4] CH1 RK0
3948 08:06:16.363767 [ModeRegInit_LP4] CH1 RK1
3949 08:06:16.364349 match AC timing 17
3950 08:06:16.369984 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3951 08:06:16.372803 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3952 08:06:16.376924 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3953 08:06:16.383134 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3954 08:06:16.386392 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3955 08:06:16.386951 ==
3956 08:06:16.389428 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 08:06:16.393200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 08:06:16.393842 ==
3959 08:06:16.399561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 08:06:16.406273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3961 08:06:16.409370 [CA 0] Center 36 (6~66) winsize 61
3962 08:06:16.412225 [CA 1] Center 36 (6~66) winsize 61
3963 08:06:16.415863 [CA 2] Center 34 (3~65) winsize 63
3964 08:06:16.419789 [CA 3] Center 34 (3~65) winsize 63
3965 08:06:16.422612 [CA 4] Center 33 (3~64) winsize 62
3966 08:06:16.425561 [CA 5] Center 33 (3~64) winsize 62
3967 08:06:16.426024
3968 08:06:16.428944 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3969 08:06:16.429409
3970 08:06:16.432301 [CATrainingPosCal] consider 1 rank data
3971 08:06:16.435812 u2DelayCellTimex100 = 270/100 ps
3972 08:06:16.438724 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3973 08:06:16.442061 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 08:06:16.445423 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3975 08:06:16.449070 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3976 08:06:16.452209 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 08:06:16.458479 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 08:06:16.458942
3979 08:06:16.462145 CA PerBit enable=1, Macro0, CA PI delay=33
3980 08:06:16.462564
3981 08:06:16.465003 [CBTSetCACLKResult] CA Dly = 33
3982 08:06:16.465477 CS Dly: 4 (0~35)
3983 08:06:16.465845 ==
3984 08:06:16.468492 Dram Type= 6, Freq= 0, CH_0, rank 1
3985 08:06:16.471628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 08:06:16.474985 ==
3987 08:06:16.478397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3988 08:06:16.484926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3989 08:06:16.488137 [CA 0] Center 36 (6~66) winsize 61
3990 08:06:16.492087 [CA 1] Center 36 (6~66) winsize 61
3991 08:06:16.495101 [CA 2] Center 33 (3~64) winsize 62
3992 08:06:16.498081 [CA 3] Center 33 (3~64) winsize 62
3993 08:06:16.501114 [CA 4] Center 33 (3~64) winsize 62
3994 08:06:16.504687 [CA 5] Center 33 (2~64) winsize 63
3995 08:06:16.505203
3996 08:06:16.508211 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3997 08:06:16.508727
3998 08:06:16.512031 [CATrainingPosCal] consider 2 rank data
3999 08:06:16.514417 u2DelayCellTimex100 = 270/100 ps
4000 08:06:16.518030 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4001 08:06:16.521339 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4002 08:06:16.528300 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 08:06:16.531136 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4004 08:06:16.534903 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4005 08:06:16.538406 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 08:06:16.538924
4007 08:06:16.541015 CA PerBit enable=1, Macro0, CA PI delay=33
4008 08:06:16.541438
4009 08:06:16.544162 [CBTSetCACLKResult] CA Dly = 33
4010 08:06:16.544674 CS Dly: 4 (0~36)
4011 08:06:16.547523
4012 08:06:16.551063 ----->DramcWriteLeveling(PI) begin...
4013 08:06:16.551602 ==
4014 08:06:16.554730 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 08:06:16.557521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 08:06:16.558035 ==
4017 08:06:16.561573 Write leveling (Byte 0): 31 => 31
4018 08:06:16.564102 Write leveling (Byte 1): 28 => 28
4019 08:06:16.567372 DramcWriteLeveling(PI) end<-----
4020 08:06:16.567815
4021 08:06:16.568151 ==
4022 08:06:16.570738 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 08:06:16.574005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 08:06:16.574523 ==
4025 08:06:16.577180 [Gating] SW mode calibration
4026 08:06:16.584031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4027 08:06:16.590833 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4028 08:06:16.593769 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 08:06:16.597167 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 08:06:16.603623 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 08:06:16.607632 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4032 08:06:16.610249 0 9 16 | B1->B0 | 2e2e 2828 | 1 0 | (1 0) (0 0)
4033 08:06:16.617225 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 08:06:16.620614 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 08:06:16.623407 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 08:06:16.630182 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 08:06:16.633643 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 08:06:16.636717 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 08:06:16.643367 0 10 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4040 08:06:16.646910 0 10 16 | B1->B0 | 3434 4242 | 0 0 | (0 0) (0 0)
4041 08:06:16.650293 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 08:06:16.656594 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 08:06:16.660148 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 08:06:16.662990 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 08:06:16.669695 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 08:06:16.673906 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 08:06:16.676112 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4048 08:06:16.683151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4049 08:06:16.686139 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 08:06:16.689630 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 08:06:16.696909 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 08:06:16.699700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 08:06:16.702433 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 08:06:16.709400 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 08:06:16.712314 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 08:06:16.716039 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 08:06:16.723014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 08:06:16.725512 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 08:06:16.729609 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 08:06:16.735544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 08:06:16.738793 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 08:06:16.741830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 08:06:16.748609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4064 08:06:16.752405 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4065 08:06:16.755063 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 08:06:16.758380 Total UI for P1: 0, mck2ui 16
4067 08:06:16.761707 best dqsien dly found for B0: ( 0, 13, 16)
4068 08:06:16.764861 Total UI for P1: 0, mck2ui 16
4069 08:06:16.767785 best dqsien dly found for B1: ( 0, 13, 14)
4070 08:06:16.771213 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4071 08:06:16.778424 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4072 08:06:16.778981
4073 08:06:16.781480 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4074 08:06:16.784621 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4075 08:06:16.787847 [Gating] SW calibration Done
4076 08:06:16.788310 ==
4077 08:06:16.791094 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 08:06:16.794823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 08:06:16.795384 ==
4080 08:06:16.797669 RX Vref Scan: 0
4081 08:06:16.798133
4082 08:06:16.798505 RX Vref 0 -> 0, step: 1
4083 08:06:16.798847
4084 08:06:16.801316 RX Delay -230 -> 252, step: 16
4085 08:06:16.804414 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4086 08:06:16.811375 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4087 08:06:16.814493 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4088 08:06:16.817723 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4089 08:06:16.821135 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4090 08:06:16.827591 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4091 08:06:16.830817 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4092 08:06:16.834246 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4093 08:06:16.837503 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4094 08:06:16.840648 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4095 08:06:16.847891 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4096 08:06:16.851961 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4097 08:06:16.854395 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4098 08:06:16.857264 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4099 08:06:16.863882 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4100 08:06:16.867481 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4101 08:06:16.868089 ==
4102 08:06:16.870733 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 08:06:16.873841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 08:06:16.874422 ==
4105 08:06:16.877776 DQS Delay:
4106 08:06:16.878334 DQS0 = 0, DQS1 = 0
4107 08:06:16.880365 DQM Delay:
4108 08:06:16.880825 DQM0 = 42, DQM1 = 30
4109 08:06:16.881195 DQ Delay:
4110 08:06:16.883681 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4111 08:06:16.886720 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4112 08:06:16.890342 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4113 08:06:16.893752 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4114 08:06:16.894346
4115 08:06:16.894720
4116 08:06:16.896639 ==
4117 08:06:16.897106 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 08:06:16.903297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 08:06:16.903859 ==
4120 08:06:16.904257
4121 08:06:16.904608
4122 08:06:16.906761 TX Vref Scan disable
4123 08:06:16.907317 == TX Byte 0 ==
4124 08:06:16.914169 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4125 08:06:16.916396 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4126 08:06:16.916862 == TX Byte 1 ==
4127 08:06:16.923449 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4128 08:06:16.926651 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4129 08:06:16.927118 ==
4130 08:06:16.930727 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 08:06:16.933180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 08:06:16.933739 ==
4133 08:06:16.934114
4134 08:06:16.934460
4135 08:06:16.936531 TX Vref Scan disable
4136 08:06:16.939558 == TX Byte 0 ==
4137 08:06:16.942802 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4138 08:06:16.946269 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4139 08:06:16.949623 == TX Byte 1 ==
4140 08:06:16.953259 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4141 08:06:16.956908 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4142 08:06:16.959903
4143 08:06:16.960457 [DATLAT]
4144 08:06:16.960833 Freq=600, CH0 RK0
4145 08:06:16.961201
4146 08:06:16.962452 DATLAT Default: 0x9
4147 08:06:16.962910 0, 0xFFFF, sum = 0
4148 08:06:16.966210 1, 0xFFFF, sum = 0
4149 08:06:16.966684 2, 0xFFFF, sum = 0
4150 08:06:16.969072 3, 0xFFFF, sum = 0
4151 08:06:16.969548 4, 0xFFFF, sum = 0
4152 08:06:16.972404 5, 0xFFFF, sum = 0
4153 08:06:16.975772 6, 0xFFFF, sum = 0
4154 08:06:16.976245 7, 0xFFFF, sum = 0
4155 08:06:16.979227 8, 0x0, sum = 1
4156 08:06:16.979854 9, 0x0, sum = 2
4157 08:06:16.980245 10, 0x0, sum = 3
4158 08:06:16.982715 11, 0x0, sum = 4
4159 08:06:16.983274 best_step = 9
4160 08:06:16.983640
4161 08:06:16.984027 ==
4162 08:06:16.986110 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 08:06:16.992714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 08:06:16.993279 ==
4165 08:06:16.993650 RX Vref Scan: 1
4166 08:06:16.993992
4167 08:06:16.995639 RX Vref 0 -> 0, step: 1
4168 08:06:16.996127
4169 08:06:16.999162 RX Delay -195 -> 252, step: 8
4170 08:06:16.999713
4171 08:06:17.002519 Set Vref, RX VrefLevel [Byte0]: 61
4172 08:06:17.005598 [Byte1]: 48
4173 08:06:17.006116
4174 08:06:17.009579 Final RX Vref Byte 0 = 61 to rank0
4175 08:06:17.012120 Final RX Vref Byte 1 = 48 to rank0
4176 08:06:17.015509 Final RX Vref Byte 0 = 61 to rank1
4177 08:06:17.018998 Final RX Vref Byte 1 = 48 to rank1==
4178 08:06:17.022246 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 08:06:17.025409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 08:06:17.025968 ==
4181 08:06:17.028887 DQS Delay:
4182 08:06:17.029396 DQS0 = 0, DQS1 = 0
4183 08:06:17.032117 DQM Delay:
4184 08:06:17.032673 DQM0 = 44, DQM1 = 32
4185 08:06:17.033046 DQ Delay:
4186 08:06:17.035652 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4187 08:06:17.038908 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4188 08:06:17.041967 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4189 08:06:17.045305 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4190 08:06:17.045863
4191 08:06:17.048447
4192 08:06:17.055054 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 389 ps
4193 08:06:17.058542 CH0 RK0: MR19=808, MR18=6E45
4194 08:06:17.064952 CH0_RK0: MR19=0x808, MR18=0x6E45, DQSOSC=389, MR23=63, INC=173, DEC=115
4195 08:06:17.065511
4196 08:06:17.068474 ----->DramcWriteLeveling(PI) begin...
4197 08:06:17.068945 ==
4198 08:06:17.071500 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 08:06:17.074645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 08:06:17.075111 ==
4201 08:06:17.077990 Write leveling (Byte 0): 33 => 33
4202 08:06:17.081692 Write leveling (Byte 1): 28 => 28
4203 08:06:17.084366 DramcWriteLeveling(PI) end<-----
4204 08:06:17.084831
4205 08:06:17.085198 ==
4206 08:06:17.087839 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 08:06:17.090964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 08:06:17.091430 ==
4209 08:06:17.094670 [Gating] SW mode calibration
4210 08:06:17.101155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4211 08:06:17.107548 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4212 08:06:17.111117 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 08:06:17.118052 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 08:06:17.121202 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 08:06:17.124574 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 08:06:17.130842 0 9 16 | B1->B0 | 2f2f 2828 | 0 0 | (1 1) (0 0)
4217 08:06:17.134212 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 08:06:17.137576 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 08:06:17.140722 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 08:06:17.147876 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 08:06:17.151072 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 08:06:17.154651 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 08:06:17.160735 0 10 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
4224 08:06:17.164192 0 10 16 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
4225 08:06:17.168198 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 08:06:17.173844 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 08:06:17.177218 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 08:06:17.180676 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 08:06:17.187150 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 08:06:17.190627 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 08:06:17.193731 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 08:06:17.200301 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 08:06:17.203683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 08:06:17.206788 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 08:06:17.214275 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 08:06:17.216844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 08:06:17.220846 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 08:06:17.226678 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 08:06:17.229917 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 08:06:17.233749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 08:06:17.239663 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 08:06:17.243323 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 08:06:17.246824 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 08:06:17.253228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 08:06:17.256409 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 08:06:17.260327 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 08:06:17.266873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4248 08:06:17.269667 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4249 08:06:17.272936 Total UI for P1: 0, mck2ui 16
4250 08:06:17.276246 best dqsien dly found for B0: ( 0, 13, 12)
4251 08:06:17.279583 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 08:06:17.283123 Total UI for P1: 0, mck2ui 16
4253 08:06:17.286127 best dqsien dly found for B1: ( 0, 13, 14)
4254 08:06:17.289725 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4255 08:06:17.296171 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4256 08:06:17.296737
4257 08:06:17.299420 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4258 08:06:17.303041 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4259 08:06:17.306063 [Gating] SW calibration Done
4260 08:06:17.306636 ==
4261 08:06:17.309161 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 08:06:17.312852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 08:06:17.313429 ==
4264 08:06:17.315958 RX Vref Scan: 0
4265 08:06:17.316531
4266 08:06:17.317022 RX Vref 0 -> 0, step: 1
4267 08:06:17.317485
4268 08:06:17.319413 RX Delay -230 -> 252, step: 16
4269 08:06:17.322574 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4270 08:06:17.328998 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4271 08:06:17.332420 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4272 08:06:17.335775 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4273 08:06:17.338871 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4274 08:06:17.345892 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4275 08:06:17.348742 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4276 08:06:17.352116 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4277 08:06:17.355894 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4278 08:06:17.358619 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4279 08:06:17.365295 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4280 08:06:17.368804 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4281 08:06:17.371807 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4282 08:06:17.374892 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4283 08:06:17.382623 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4284 08:06:17.385467 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4285 08:06:17.386042 ==
4286 08:06:17.388246 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 08:06:17.391854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 08:06:17.392425 ==
4289 08:06:17.394950 DQS Delay:
4290 08:06:17.395427 DQS0 = 0, DQS1 = 0
4291 08:06:17.398437 DQM Delay:
4292 08:06:17.398917 DQM0 = 44, DQM1 = 38
4293 08:06:17.399403 DQ Delay:
4294 08:06:17.401331 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4295 08:06:17.405206 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4296 08:06:17.408603 DQ8 =33, DQ9 =17, DQ10 =41, DQ11 =33
4297 08:06:17.411453 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4298 08:06:17.412061
4299 08:06:17.412557
4300 08:06:17.414850 ==
4301 08:06:17.417906 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 08:06:17.421268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 08:06:17.421845 ==
4304 08:06:17.422340
4305 08:06:17.422803
4306 08:06:17.425319 TX Vref Scan disable
4307 08:06:17.425892 == TX Byte 0 ==
4308 08:06:17.431651 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4309 08:06:17.434432 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4310 08:06:17.435024 == TX Byte 1 ==
4311 08:06:17.440795 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4312 08:06:17.444042 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4313 08:06:17.444346 ==
4314 08:06:17.447230 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 08:06:17.450745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 08:06:17.451029 ==
4317 08:06:17.451198
4318 08:06:17.451339
4319 08:06:17.454399 TX Vref Scan disable
4320 08:06:17.457607 == TX Byte 0 ==
4321 08:06:17.461160 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4322 08:06:17.463897 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4323 08:06:17.467749 == TX Byte 1 ==
4324 08:06:17.470735 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4325 08:06:17.473740 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4326 08:06:17.477095
4327 08:06:17.477202 [DATLAT]
4328 08:06:17.477294 Freq=600, CH0 RK1
4329 08:06:17.477383
4330 08:06:17.480358 DATLAT Default: 0x9
4331 08:06:17.480457 0, 0xFFFF, sum = 0
4332 08:06:17.483943 1, 0xFFFF, sum = 0
4333 08:06:17.484026 2, 0xFFFF, sum = 0
4334 08:06:17.487100 3, 0xFFFF, sum = 0
4335 08:06:17.487259 4, 0xFFFF, sum = 0
4336 08:06:17.490580 5, 0xFFFF, sum = 0
4337 08:06:17.494160 6, 0xFFFF, sum = 0
4338 08:06:17.494389 7, 0xFFFF, sum = 0
4339 08:06:17.494510 8, 0x0, sum = 1
4340 08:06:17.496794 9, 0x0, sum = 2
4341 08:06:17.496884 10, 0x0, sum = 3
4342 08:06:17.500788 11, 0x0, sum = 4
4343 08:06:17.500917 best_step = 9
4344 08:06:17.501024
4345 08:06:17.501125 ==
4346 08:06:17.504145 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 08:06:17.510950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 08:06:17.511461 ==
4349 08:06:17.511855 RX Vref Scan: 0
4350 08:06:17.512180
4351 08:06:17.514053 RX Vref 0 -> 0, step: 1
4352 08:06:17.514566
4353 08:06:17.516928 RX Delay -195 -> 252, step: 8
4354 08:06:17.520433 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4355 08:06:17.526996 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4356 08:06:17.530816 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4357 08:06:17.533879 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4358 08:06:17.537056 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4359 08:06:17.543617 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4360 08:06:17.547398 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4361 08:06:17.550295 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4362 08:06:17.553598 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4363 08:06:17.556802 iDelay=205, Bit 9, Center 24 (-123 ~ 172) 296
4364 08:06:17.563317 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4365 08:06:17.566727 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4366 08:06:17.570453 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4367 08:06:17.574003 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4368 08:06:17.580015 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4369 08:06:17.583268 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4370 08:06:17.583808 ==
4371 08:06:17.586553 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 08:06:17.590031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 08:06:17.590587 ==
4374 08:06:17.593042 DQS Delay:
4375 08:06:17.593553 DQS0 = 0, DQS1 = 0
4376 08:06:17.593882 DQM Delay:
4377 08:06:17.596505 DQM0 = 42, DQM1 = 37
4378 08:06:17.597013 DQ Delay:
4379 08:06:17.599910 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4380 08:06:17.603936 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4381 08:06:17.606562 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4382 08:06:17.609838 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4383 08:06:17.610366
4384 08:06:17.610813
4385 08:06:17.619908 [DQSOSCAuto] RK1, (LSB)MR18= 0x6619, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4386 08:06:17.623364 CH0 RK1: MR19=808, MR18=6619
4387 08:06:17.626569 CH0_RK1: MR19=0x808, MR18=0x6619, DQSOSC=390, MR23=63, INC=172, DEC=114
4388 08:06:17.629706 [RxdqsGatingPostProcess] freq 600
4389 08:06:17.636013 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4390 08:06:17.639450 Pre-setting of DQS Precalculation
4391 08:06:17.642943 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4392 08:06:17.646151 ==
4393 08:06:17.646686 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 08:06:17.652617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 08:06:17.653150 ==
4396 08:06:17.656099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4397 08:06:17.662244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4398 08:06:17.666058 [CA 0] Center 35 (5~66) winsize 62
4399 08:06:17.669429 [CA 1] Center 35 (5~66) winsize 62
4400 08:06:17.672813 [CA 2] Center 34 (4~65) winsize 62
4401 08:06:17.675966 [CA 3] Center 33 (3~64) winsize 62
4402 08:06:17.679383 [CA 4] Center 34 (4~64) winsize 61
4403 08:06:17.682542 [CA 5] Center 33 (3~64) winsize 62
4404 08:06:17.683074
4405 08:06:17.685597 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4406 08:06:17.686029
4407 08:06:17.689065 [CATrainingPosCal] consider 1 rank data
4408 08:06:17.692406 u2DelayCellTimex100 = 270/100 ps
4409 08:06:17.695568 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4410 08:06:17.702459 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 08:06:17.706690 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4412 08:06:17.709036 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 08:06:17.712966 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4414 08:06:17.716698 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 08:06:17.717230
4416 08:06:17.719325 CA PerBit enable=1, Macro0, CA PI delay=33
4417 08:06:17.719888
4418 08:06:17.722477 [CBTSetCACLKResult] CA Dly = 33
4419 08:06:17.725575 CS Dly: 4 (0~35)
4420 08:06:17.726101 ==
4421 08:06:17.729153 Dram Type= 6, Freq= 0, CH_1, rank 1
4422 08:06:17.732690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 08:06:17.733220 ==
4424 08:06:17.738996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4425 08:06:17.742569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4426 08:06:17.746482 [CA 0] Center 35 (5~66) winsize 62
4427 08:06:17.749584 [CA 1] Center 36 (6~66) winsize 61
4428 08:06:17.752526 [CA 2] Center 34 (4~65) winsize 62
4429 08:06:17.756487 [CA 3] Center 34 (3~65) winsize 63
4430 08:06:17.759409 [CA 4] Center 34 (4~65) winsize 62
4431 08:06:17.762524 [CA 5] Center 34 (3~65) winsize 63
4432 08:06:17.762962
4433 08:06:17.766091 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4434 08:06:17.766620
4435 08:06:17.769813 [CATrainingPosCal] consider 2 rank data
4436 08:06:17.772690 u2DelayCellTimex100 = 270/100 ps
4437 08:06:17.776160 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 08:06:17.782786 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4439 08:06:17.785603 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4440 08:06:17.788654 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 08:06:17.791913 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4442 08:06:17.795451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 08:06:17.795960
4444 08:06:17.799010 CA PerBit enable=1, Macro0, CA PI delay=33
4445 08:06:17.799568
4446 08:06:17.801910 [CBTSetCACLKResult] CA Dly = 33
4447 08:06:17.805967 CS Dly: 4 (0~36)
4448 08:06:17.806429
4449 08:06:17.809426 ----->DramcWriteLeveling(PI) begin...
4450 08:06:17.809985 ==
4451 08:06:17.811933 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 08:06:17.815456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 08:06:17.815983 ==
4454 08:06:17.818351 Write leveling (Byte 0): 31 => 31
4455 08:06:17.822698 Write leveling (Byte 1): 31 => 31
4456 08:06:17.825493 DramcWriteLeveling(PI) end<-----
4457 08:06:17.826050
4458 08:06:17.826418 ==
4459 08:06:17.828326 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 08:06:17.831882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 08:06:17.832440 ==
4462 08:06:17.835026 [Gating] SW mode calibration
4463 08:06:17.842279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4464 08:06:17.848430 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4465 08:06:17.851601 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4466 08:06:17.855175 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 08:06:17.861807 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4468 08:06:17.864786 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 0)
4469 08:06:17.868410 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4470 08:06:17.874612 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 08:06:17.878243 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 08:06:17.882219 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 08:06:17.888845 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 08:06:17.891435 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 08:06:17.894902 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 08:06:17.901511 0 10 12 | B1->B0 | 2d2d 3535 | 0 0 | (0 0) (0 0)
4477 08:06:17.904320 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 08:06:17.907449 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 08:06:17.914381 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 08:06:17.917729 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 08:06:17.921479 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 08:06:17.928210 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 08:06:17.930844 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 08:06:17.934764 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4485 08:06:17.941202 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 08:06:17.944278 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 08:06:17.947461 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 08:06:17.954237 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 08:06:17.957938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 08:06:17.960979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 08:06:17.967678 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 08:06:17.970866 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 08:06:17.973584 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 08:06:17.980272 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 08:06:17.983816 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 08:06:17.987205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 08:06:17.993832 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 08:06:17.997379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 08:06:17.999973 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 08:06:18.006643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 08:06:18.010140 Total UI for P1: 0, mck2ui 16
4502 08:06:18.013220 best dqsien dly found for B0: ( 0, 13, 10)
4503 08:06:18.013797 Total UI for P1: 0, mck2ui 16
4504 08:06:18.019799 best dqsien dly found for B1: ( 0, 13, 10)
4505 08:06:18.023076 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4506 08:06:18.026611 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4507 08:06:18.027090
4508 08:06:18.029768 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4509 08:06:18.033181 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4510 08:06:18.036655 [Gating] SW calibration Done
4511 08:06:18.037240 ==
4512 08:06:18.039845 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 08:06:18.043057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 08:06:18.043641 ==
4515 08:06:18.046384 RX Vref Scan: 0
4516 08:06:18.046948
4517 08:06:18.049285 RX Vref 0 -> 0, step: 1
4518 08:06:18.049749
4519 08:06:18.050118 RX Delay -230 -> 252, step: 16
4520 08:06:18.056535 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4521 08:06:18.059504 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4522 08:06:18.063209 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4523 08:06:18.066872 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4524 08:06:18.072964 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4525 08:06:18.075912 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4526 08:06:18.079513 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4527 08:06:18.082800 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4528 08:06:18.089283 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4529 08:06:18.092619 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4530 08:06:18.095767 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4531 08:06:18.099700 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4532 08:06:18.106412 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4533 08:06:18.109034 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4534 08:06:18.112503 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4535 08:06:18.116101 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4536 08:06:18.116661 ==
4537 08:06:18.119392 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 08:06:18.125316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 08:06:18.125874 ==
4540 08:06:18.126241 DQS Delay:
4541 08:06:18.128634 DQS0 = 0, DQS1 = 0
4542 08:06:18.129096 DQM Delay:
4543 08:06:18.129469 DQM0 = 46, DQM1 = 38
4544 08:06:18.132431 DQ Delay:
4545 08:06:18.135864 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4546 08:06:18.138931 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4547 08:06:18.142307 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4548 08:06:18.145329 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4549 08:06:18.145796
4550 08:06:18.146160
4551 08:06:18.146499 ==
4552 08:06:18.148755 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 08:06:18.151856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 08:06:18.152324 ==
4555 08:06:18.152775
4556 08:06:18.153247
4557 08:06:18.155288 TX Vref Scan disable
4558 08:06:18.158533 == TX Byte 0 ==
4559 08:06:18.162215 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4560 08:06:18.164990 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4561 08:06:18.168684 == TX Byte 1 ==
4562 08:06:18.172309 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4563 08:06:18.174987 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4564 08:06:18.175548 ==
4565 08:06:18.178535 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 08:06:18.181666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 08:06:18.185235 ==
4568 08:06:18.185793
4569 08:06:18.186163
4570 08:06:18.186499 TX Vref Scan disable
4571 08:06:18.189033 == TX Byte 0 ==
4572 08:06:18.191876 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4573 08:06:18.198610 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4574 08:06:18.199170 == TX Byte 1 ==
4575 08:06:18.201886 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 08:06:18.208351 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 08:06:18.208901
4578 08:06:18.209270 [DATLAT]
4579 08:06:18.209619 Freq=600, CH1 RK0
4580 08:06:18.209955
4581 08:06:18.212117 DATLAT Default: 0x9
4582 08:06:18.215128 0, 0xFFFF, sum = 0
4583 08:06:18.215690 1, 0xFFFF, sum = 0
4584 08:06:18.218589 2, 0xFFFF, sum = 0
4585 08:06:18.219062 3, 0xFFFF, sum = 0
4586 08:06:18.222371 4, 0xFFFF, sum = 0
4587 08:06:18.222932 5, 0xFFFF, sum = 0
4588 08:06:18.225478 6, 0xFFFF, sum = 0
4589 08:06:18.226047 7, 0xFFFF, sum = 0
4590 08:06:18.228409 8, 0x0, sum = 1
4591 08:06:18.228883 9, 0x0, sum = 2
4592 08:06:18.231575 10, 0x0, sum = 3
4593 08:06:18.232079 11, 0x0, sum = 4
4594 08:06:18.232458 best_step = 9
4595 08:06:18.232802
4596 08:06:18.235562 ==
4597 08:06:18.236165 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 08:06:18.241711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 08:06:18.242274 ==
4600 08:06:18.242643 RX Vref Scan: 1
4601 08:06:18.242991
4602 08:06:18.244687 RX Vref 0 -> 0, step: 1
4603 08:06:18.245153
4604 08:06:18.248381 RX Delay -195 -> 252, step: 8
4605 08:06:18.248939
4606 08:06:18.251802 Set Vref, RX VrefLevel [Byte0]: 50
4607 08:06:18.255059 [Byte1]: 52
4608 08:06:18.255614
4609 08:06:18.258088 Final RX Vref Byte 0 = 50 to rank0
4610 08:06:18.261364 Final RX Vref Byte 1 = 52 to rank0
4611 08:06:18.264589 Final RX Vref Byte 0 = 50 to rank1
4612 08:06:18.268094 Final RX Vref Byte 1 = 52 to rank1==
4613 08:06:18.270884 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 08:06:18.277446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 08:06:18.278042 ==
4616 08:06:18.278599 DQS Delay:
4617 08:06:18.278964 DQS0 = 0, DQS1 = 0
4618 08:06:18.280994 DQM Delay:
4619 08:06:18.281459 DQM0 = 48, DQM1 = 36
4620 08:06:18.284326 DQ Delay:
4621 08:06:18.287409 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4622 08:06:18.291086 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4623 08:06:18.294196 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =28
4624 08:06:18.297703 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4625 08:06:18.298275
4626 08:06:18.298640
4627 08:06:18.303856 [DQSOSCAuto] RK0, (LSB)MR18= 0x563b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 393 ps
4628 08:06:18.307316 CH1 RK0: MR19=808, MR18=563B
4629 08:06:18.314519 CH1_RK0: MR19=0x808, MR18=0x563B, DQSOSC=393, MR23=63, INC=169, DEC=113
4630 08:06:18.315078
4631 08:06:18.317934 ----->DramcWriteLeveling(PI) begin...
4632 08:06:18.318507 ==
4633 08:06:18.320448 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 08:06:18.323868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 08:06:18.324423 ==
4636 08:06:18.327558 Write leveling (Byte 0): 30 => 30
4637 08:06:18.330458 Write leveling (Byte 1): 33 => 33
4638 08:06:18.334050 DramcWriteLeveling(PI) end<-----
4639 08:06:18.334608
4640 08:06:18.334978 ==
4641 08:06:18.337977 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 08:06:18.340120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 08:06:18.343986 ==
4644 08:06:18.344550 [Gating] SW mode calibration
4645 08:06:18.354574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4646 08:06:18.357738 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4647 08:06:18.360324 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 08:06:18.366632 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4649 08:06:18.369991 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 08:06:18.373290 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (1 0) (1 0)
4651 08:06:18.379470 0 9 16 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4652 08:06:18.383223 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 08:06:18.386420 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 08:06:18.392966 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 08:06:18.396485 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 08:06:18.399301 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 08:06:18.406588 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 08:06:18.410091 0 10 12 | B1->B0 | 3434 2a2a | 1 1 | (0 0) (0 0)
4659 08:06:18.412914 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4660 08:06:18.419191 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 08:06:18.423166 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 08:06:18.426525 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 08:06:18.432415 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 08:06:18.435584 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 08:06:18.438799 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 08:06:18.445671 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4667 08:06:18.448739 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4668 08:06:18.452332 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 08:06:18.459011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 08:06:18.462322 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 08:06:18.465617 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 08:06:18.472728 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 08:06:18.475285 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 08:06:18.479296 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 08:06:18.485578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 08:06:18.488591 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 08:06:18.491858 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 08:06:18.498507 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 08:06:18.501964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 08:06:18.504954 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 08:06:18.511412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 08:06:18.514841 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4683 08:06:18.518125 Total UI for P1: 0, mck2ui 16
4684 08:06:18.521647 best dqsien dly found for B1: ( 0, 13, 10)
4685 08:06:18.524850 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 08:06:18.528742 Total UI for P1: 0, mck2ui 16
4687 08:06:18.531916 best dqsien dly found for B0: ( 0, 13, 12)
4688 08:06:18.535485 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4689 08:06:18.537876 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4690 08:06:18.538290
4691 08:06:18.544919 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4692 08:06:18.548189 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4693 08:06:18.551806 [Gating] SW calibration Done
4694 08:06:18.552413 ==
4695 08:06:18.554523 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 08:06:18.558116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 08:06:18.558598 ==
4698 08:06:18.559089 RX Vref Scan: 0
4699 08:06:18.559554
4700 08:06:18.561777 RX Vref 0 -> 0, step: 1
4701 08:06:18.562348
4702 08:06:18.565356 RX Delay -230 -> 252, step: 16
4703 08:06:18.568139 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4704 08:06:18.571341 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4705 08:06:18.577719 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4706 08:06:18.582308 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4707 08:06:18.584360 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4708 08:06:18.588297 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4709 08:06:18.594312 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4710 08:06:18.597516 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4711 08:06:18.601163 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4712 08:06:18.604464 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4713 08:06:18.610716 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4714 08:06:18.614086 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4715 08:06:18.617468 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4716 08:06:18.620481 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4717 08:06:18.627230 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4718 08:06:18.630652 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4719 08:06:18.631219 ==
4720 08:06:18.633792 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 08:06:18.637853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 08:06:18.638411 ==
4723 08:06:18.640105 DQS Delay:
4724 08:06:18.640565 DQS0 = 0, DQS1 = 0
4725 08:06:18.640932 DQM Delay:
4726 08:06:18.643871 DQM0 = 41, DQM1 = 37
4727 08:06:18.644430 DQ Delay:
4728 08:06:18.647332 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4729 08:06:18.649963 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4730 08:06:18.653291 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4731 08:06:18.656736 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4732 08:06:18.657293
4733 08:06:18.657662
4734 08:06:18.658000 ==
4735 08:06:18.660225 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 08:06:18.666509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 08:06:18.667049 ==
4738 08:06:18.667416
4739 08:06:18.667791
4740 08:06:18.668121 TX Vref Scan disable
4741 08:06:18.670878 == TX Byte 0 ==
4742 08:06:18.673821 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4743 08:06:18.681048 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4744 08:06:18.681513 == TX Byte 1 ==
4745 08:06:18.683474 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4746 08:06:18.690771 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4747 08:06:18.691326 ==
4748 08:06:18.693563 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 08:06:18.696727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 08:06:18.697193 ==
4751 08:06:18.697562
4752 08:06:18.697902
4753 08:06:18.700120 TX Vref Scan disable
4754 08:06:18.703842 == TX Byte 0 ==
4755 08:06:18.706924 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4756 08:06:18.710115 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4757 08:06:18.713534 == TX Byte 1 ==
4758 08:06:18.716918 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4759 08:06:18.720066 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4760 08:06:18.720633
4761 08:06:18.721002 [DATLAT]
4762 08:06:18.723492 Freq=600, CH1 RK1
4763 08:06:18.724097
4764 08:06:18.726610 DATLAT Default: 0x9
4765 08:06:18.727071 0, 0xFFFF, sum = 0
4766 08:06:18.729938 1, 0xFFFF, sum = 0
4767 08:06:18.730506 2, 0xFFFF, sum = 0
4768 08:06:18.733543 3, 0xFFFF, sum = 0
4769 08:06:18.734109 4, 0xFFFF, sum = 0
4770 08:06:18.736637 5, 0xFFFF, sum = 0
4771 08:06:18.737201 6, 0xFFFF, sum = 0
4772 08:06:18.740500 7, 0xFFFF, sum = 0
4773 08:06:18.740971 8, 0x0, sum = 1
4774 08:06:18.743425 9, 0x0, sum = 2
4775 08:06:18.744072 10, 0x0, sum = 3
4776 08:06:18.746571 11, 0x0, sum = 4
4777 08:06:18.747224 best_step = 9
4778 08:06:18.747601
4779 08:06:18.747988 ==
4780 08:06:18.749856 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 08:06:18.753412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 08:06:18.753877 ==
4783 08:06:18.757340 RX Vref Scan: 0
4784 08:06:18.757893
4785 08:06:18.760332 RX Vref 0 -> 0, step: 1
4786 08:06:18.760886
4787 08:06:18.761253 RX Delay -195 -> 252, step: 8
4788 08:06:18.767917 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4789 08:06:18.771113 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4790 08:06:18.774212 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4791 08:06:18.777833 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4792 08:06:18.783956 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4793 08:06:18.787645 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4794 08:06:18.790909 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4795 08:06:18.794900 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4796 08:06:18.800764 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4797 08:06:18.804699 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4798 08:06:18.807346 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4799 08:06:18.811653 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4800 08:06:18.813819 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4801 08:06:18.820489 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4802 08:06:18.824475 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4803 08:06:18.827147 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4804 08:06:18.827706 ==
4805 08:06:18.830104 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 08:06:18.837032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 08:06:18.837597 ==
4808 08:06:18.837968 DQS Delay:
4809 08:06:18.840444 DQS0 = 0, DQS1 = 0
4810 08:06:18.841006 DQM Delay:
4811 08:06:18.841376 DQM0 = 45, DQM1 = 37
4812 08:06:18.843584 DQ Delay:
4813 08:06:18.846832 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4814 08:06:18.849986 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4815 08:06:18.853294 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4816 08:06:18.856687 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4817 08:06:18.857248
4818 08:06:18.857611
4819 08:06:18.863414 [DQSOSCAuto] RK1, (LSB)MR18= 0x362b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
4820 08:06:18.866455 CH1 RK1: MR19=808, MR18=362B
4821 08:06:18.873444 CH1_RK1: MR19=0x808, MR18=0x362B, DQSOSC=399, MR23=63, INC=164, DEC=109
4822 08:06:18.876437 [RxdqsGatingPostProcess] freq 600
4823 08:06:18.882891 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4824 08:06:18.883464 Pre-setting of DQS Precalculation
4825 08:06:18.889063 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4826 08:06:18.895789 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4827 08:06:18.902497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4828 08:06:18.903072
4829 08:06:18.903560
4830 08:06:18.905308 [Calibration Summary] 1200 Mbps
4831 08:06:18.908558 CH 0, Rank 0
4832 08:06:18.909100 SW Impedance : PASS
4833 08:06:18.912208 DUTY Scan : NO K
4834 08:06:18.915285 ZQ Calibration : PASS
4835 08:06:18.915915 Jitter Meter : NO K
4836 08:06:18.919009 CBT Training : PASS
4837 08:06:18.922144 Write leveling : PASS
4838 08:06:18.922714 RX DQS gating : PASS
4839 08:06:18.925810 RX DQ/DQS(RDDQC) : PASS
4840 08:06:18.929643 TX DQ/DQS : PASS
4841 08:06:18.930218 RX DATLAT : PASS
4842 08:06:18.931816 RX DQ/DQS(Engine): PASS
4843 08:06:18.935119 TX OE : NO K
4844 08:06:18.935690 All Pass.
4845 08:06:18.936235
4846 08:06:18.936691 CH 0, Rank 1
4847 08:06:18.938530 SW Impedance : PASS
4848 08:06:18.942055 DUTY Scan : NO K
4849 08:06:18.942626 ZQ Calibration : PASS
4850 08:06:18.944868 Jitter Meter : NO K
4851 08:06:18.948340 CBT Training : PASS
4852 08:06:18.948900 Write leveling : PASS
4853 08:06:18.951585 RX DQS gating : PASS
4854 08:06:18.952191 RX DQ/DQS(RDDQC) : PASS
4855 08:06:18.955535 TX DQ/DQS : PASS
4856 08:06:18.958363 RX DATLAT : PASS
4857 08:06:18.958913 RX DQ/DQS(Engine): PASS
4858 08:06:18.961785 TX OE : NO K
4859 08:06:18.962343 All Pass.
4860 08:06:18.962706
4861 08:06:18.964687 CH 1, Rank 0
4862 08:06:18.965165 SW Impedance : PASS
4863 08:06:18.967950 DUTY Scan : NO K
4864 08:06:18.971047 ZQ Calibration : PASS
4865 08:06:18.971600 Jitter Meter : NO K
4866 08:06:18.974667 CBT Training : PASS
4867 08:06:18.978400 Write leveling : PASS
4868 08:06:18.978975 RX DQS gating : PASS
4869 08:06:18.981223 RX DQ/DQS(RDDQC) : PASS
4870 08:06:18.984647 TX DQ/DQS : PASS
4871 08:06:18.985109 RX DATLAT : PASS
4872 08:06:18.988202 RX DQ/DQS(Engine): PASS
4873 08:06:18.991269 TX OE : NO K
4874 08:06:18.991861 All Pass.
4875 08:06:18.992237
4876 08:06:18.992574 CH 1, Rank 1
4877 08:06:18.994032 SW Impedance : PASS
4878 08:06:18.997665 DUTY Scan : NO K
4879 08:06:18.998165 ZQ Calibration : PASS
4880 08:06:19.000799 Jitter Meter : NO K
4881 08:06:19.004518 CBT Training : PASS
4882 08:06:19.005096 Write leveling : PASS
4883 08:06:19.007176 RX DQS gating : PASS
4884 08:06:19.010896 RX DQ/DQS(RDDQC) : PASS
4885 08:06:19.011453 TX DQ/DQS : PASS
4886 08:06:19.014110 RX DATLAT : PASS
4887 08:06:19.017382 RX DQ/DQS(Engine): PASS
4888 08:06:19.017933 TX OE : NO K
4889 08:06:19.020447 All Pass.
4890 08:06:19.020909
4891 08:06:19.021277 DramC Write-DBI off
4892 08:06:19.024280 PER_BANK_REFRESH: Hybrid Mode
4893 08:06:19.024848 TX_TRACKING: ON
4894 08:06:19.034466 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4895 08:06:19.038521 [FAST_K] Save calibration result to emmc
4896 08:06:19.041107 dramc_set_vcore_voltage set vcore to 662500
4897 08:06:19.043612 Read voltage for 933, 3
4898 08:06:19.044219 Vio18 = 0
4899 08:06:19.046715 Vcore = 662500
4900 08:06:19.047180 Vdram = 0
4901 08:06:19.047547 Vddq = 0
4902 08:06:19.050431 Vmddr = 0
4903 08:06:19.053868 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4904 08:06:19.060451 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4905 08:06:19.061014 MEM_TYPE=3, freq_sel=17
4906 08:06:19.063415 sv_algorithm_assistance_LP4_1600
4907 08:06:19.070193 ============ PULL DRAM RESETB DOWN ============
4908 08:06:19.073641 ========== PULL DRAM RESETB DOWN end =========
4909 08:06:19.076662 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4910 08:06:19.081241 ===================================
4911 08:06:19.083028 LPDDR4 DRAM CONFIGURATION
4912 08:06:19.086681 ===================================
4913 08:06:19.087289 EX_ROW_EN[0] = 0x0
4914 08:06:19.090065 EX_ROW_EN[1] = 0x0
4915 08:06:19.093511 LP4Y_EN = 0x0
4916 08:06:19.094063 WORK_FSP = 0x0
4917 08:06:19.096455 WL = 0x3
4918 08:06:19.096918 RL = 0x3
4919 08:06:19.099870 BL = 0x2
4920 08:06:19.100337 RPST = 0x0
4921 08:06:19.103046 RD_PRE = 0x0
4922 08:06:19.103603 WR_PRE = 0x1
4923 08:06:19.106371 WR_PST = 0x0
4924 08:06:19.106838 DBI_WR = 0x0
4925 08:06:19.109543 DBI_RD = 0x0
4926 08:06:19.110010 OTF = 0x1
4927 08:06:19.113068 ===================================
4928 08:06:19.116497 ===================================
4929 08:06:19.119616 ANA top config
4930 08:06:19.123184 ===================================
4931 08:06:19.123793 DLL_ASYNC_EN = 0
4932 08:06:19.126215 ALL_SLAVE_EN = 1
4933 08:06:19.129882 NEW_RANK_MODE = 1
4934 08:06:19.132781 DLL_IDLE_MODE = 1
4935 08:06:19.136466 LP45_APHY_COMB_EN = 1
4936 08:06:19.137059 TX_ODT_DIS = 1
4937 08:06:19.139581 NEW_8X_MODE = 1
4938 08:06:19.142846 ===================================
4939 08:06:19.146368 ===================================
4940 08:06:19.149580 data_rate = 1866
4941 08:06:19.152804 CKR = 1
4942 08:06:19.156284 DQ_P2S_RATIO = 8
4943 08:06:19.159405 ===================================
4944 08:06:19.163535 CA_P2S_RATIO = 8
4945 08:06:19.164137 DQ_CA_OPEN = 0
4946 08:06:19.166639 DQ_SEMI_OPEN = 0
4947 08:06:19.169590 CA_SEMI_OPEN = 0
4948 08:06:19.172543 CA_FULL_RATE = 0
4949 08:06:19.175933 DQ_CKDIV4_EN = 1
4950 08:06:19.179295 CA_CKDIV4_EN = 1
4951 08:06:19.179912 CA_PREDIV_EN = 0
4952 08:06:19.182808 PH8_DLY = 0
4953 08:06:19.185803 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4954 08:06:19.189134 DQ_AAMCK_DIV = 4
4955 08:06:19.192299 CA_AAMCK_DIV = 4
4956 08:06:19.195667 CA_ADMCK_DIV = 4
4957 08:06:19.196174 DQ_TRACK_CA_EN = 0
4958 08:06:19.199137 CA_PICK = 933
4959 08:06:19.202722 CA_MCKIO = 933
4960 08:06:19.205689 MCKIO_SEMI = 0
4961 08:06:19.208825 PLL_FREQ = 3732
4962 08:06:19.212320 DQ_UI_PI_RATIO = 32
4963 08:06:19.215848 CA_UI_PI_RATIO = 0
4964 08:06:19.218823 ===================================
4965 08:06:19.222290 ===================================
4966 08:06:19.222844 memory_type:LPDDR4
4967 08:06:19.225702 GP_NUM : 10
4968 08:06:19.229354 SRAM_EN : 1
4969 08:06:19.229917 MD32_EN : 0
4970 08:06:19.232195 ===================================
4971 08:06:19.235433 [ANA_INIT] >>>>>>>>>>>>>>
4972 08:06:19.238629 <<<<<< [CONFIGURE PHASE]: ANA_TX
4973 08:06:19.242126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4974 08:06:19.245459 ===================================
4975 08:06:19.248691 data_rate = 1866,PCW = 0X8f00
4976 08:06:19.252190 ===================================
4977 08:06:19.255057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4978 08:06:19.258363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4979 08:06:19.265180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 08:06:19.268318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4981 08:06:19.274931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4982 08:06:19.278252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4983 08:06:19.278722 [ANA_INIT] flow start
4984 08:06:19.281007 [ANA_INIT] PLL >>>>>>>>
4985 08:06:19.284768 [ANA_INIT] PLL <<<<<<<<
4986 08:06:19.285231 [ANA_INIT] MIDPI >>>>>>>>
4987 08:06:19.287880 [ANA_INIT] MIDPI <<<<<<<<
4988 08:06:19.291721 [ANA_INIT] DLL >>>>>>>>
4989 08:06:19.292327 [ANA_INIT] flow end
4990 08:06:19.294625 ============ LP4 DIFF to SE enter ============
4991 08:06:19.301206 ============ LP4 DIFF to SE exit ============
4992 08:06:19.301767 [ANA_INIT] <<<<<<<<<<<<<
4993 08:06:19.304939 [Flow] Enable top DCM control >>>>>
4994 08:06:19.307833 [Flow] Enable top DCM control <<<<<
4995 08:06:19.311162 Enable DLL master slave shuffle
4996 08:06:19.318178 ==============================================================
4997 08:06:19.320838 Gating Mode config
4998 08:06:19.324691 ==============================================================
4999 08:06:19.327448 Config description:
5000 08:06:19.337630 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5001 08:06:19.344626 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5002 08:06:19.347713 SELPH_MODE 0: By rank 1: By Phase
5003 08:06:19.353957 ==============================================================
5004 08:06:19.357169 GAT_TRACK_EN = 1
5005 08:06:19.360692 RX_GATING_MODE = 2
5006 08:06:19.363813 RX_GATING_TRACK_MODE = 2
5007 08:06:19.367018 SELPH_MODE = 1
5008 08:06:19.367564 PICG_EARLY_EN = 1
5009 08:06:19.370811 VALID_LAT_VALUE = 1
5010 08:06:19.377000 ==============================================================
5011 08:06:19.380428 Enter into Gating configuration >>>>
5012 08:06:19.384159 Exit from Gating configuration <<<<
5013 08:06:19.387047 Enter into DVFS_PRE_config >>>>>
5014 08:06:19.396927 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5015 08:06:19.400617 Exit from DVFS_PRE_config <<<<<
5016 08:06:19.403244 Enter into PICG configuration >>>>
5017 08:06:19.407609 Exit from PICG configuration <<<<
5018 08:06:19.409850 [RX_INPUT] configuration >>>>>
5019 08:06:19.413570 [RX_INPUT] configuration <<<<<
5020 08:06:19.416467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5021 08:06:19.423981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5022 08:06:19.430807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 08:06:19.436562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 08:06:19.443018 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 08:06:19.449899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 08:06:19.452749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5027 08:06:19.457234 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5028 08:06:19.459694 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5029 08:06:19.466687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5030 08:06:19.469593 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5031 08:06:19.472555 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 08:06:19.476347 ===================================
5033 08:06:19.480000 LPDDR4 DRAM CONFIGURATION
5034 08:06:19.482967 ===================================
5035 08:06:19.483476 EX_ROW_EN[0] = 0x0
5036 08:06:19.485922 EX_ROW_EN[1] = 0x0
5037 08:06:19.489327 LP4Y_EN = 0x0
5038 08:06:19.489788 WORK_FSP = 0x0
5039 08:06:19.492275 WL = 0x3
5040 08:06:19.492735 RL = 0x3
5041 08:06:19.495833 BL = 0x2
5042 08:06:19.496290 RPST = 0x0
5043 08:06:19.499225 RD_PRE = 0x0
5044 08:06:19.499869 WR_PRE = 0x1
5045 08:06:19.502547 WR_PST = 0x0
5046 08:06:19.503101 DBI_WR = 0x0
5047 08:06:19.505554 DBI_RD = 0x0
5048 08:06:19.506010 OTF = 0x1
5049 08:06:19.509087 ===================================
5050 08:06:19.512047 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5051 08:06:19.519263 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5052 08:06:19.522120 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 08:06:19.525465 ===================================
5054 08:06:19.528797 LPDDR4 DRAM CONFIGURATION
5055 08:06:19.532222 ===================================
5056 08:06:19.532681 EX_ROW_EN[0] = 0x10
5057 08:06:19.535464 EX_ROW_EN[1] = 0x0
5058 08:06:19.538587 LP4Y_EN = 0x0
5059 08:06:19.539077 WORK_FSP = 0x0
5060 08:06:19.541621 WL = 0x3
5061 08:06:19.542035 RL = 0x3
5062 08:06:19.545271 BL = 0x2
5063 08:06:19.545684 RPST = 0x0
5064 08:06:19.548410 RD_PRE = 0x0
5065 08:06:19.548924 WR_PRE = 0x1
5066 08:06:19.551794 WR_PST = 0x0
5067 08:06:19.552342 DBI_WR = 0x0
5068 08:06:19.554906 DBI_RD = 0x0
5069 08:06:19.555448 OTF = 0x1
5070 08:06:19.558582 ===================================
5071 08:06:19.565278 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5072 08:06:19.570194 nWR fixed to 30
5073 08:06:19.572904 [ModeRegInit_LP4] CH0 RK0
5074 08:06:19.573318 [ModeRegInit_LP4] CH0 RK1
5075 08:06:19.576694 [ModeRegInit_LP4] CH1 RK0
5076 08:06:19.579900 [ModeRegInit_LP4] CH1 RK1
5077 08:06:19.580413 match AC timing 9
5078 08:06:19.585700 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5079 08:06:19.589201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5080 08:06:19.592772 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5081 08:06:19.599196 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5082 08:06:19.602815 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5083 08:06:19.603335 ==
5084 08:06:19.605754 Dram Type= 6, Freq= 0, CH_0, rank 0
5085 08:06:19.609186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 08:06:19.609606 ==
5087 08:06:19.616092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5088 08:06:19.622502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5089 08:06:19.625694 [CA 0] Center 38 (7~69) winsize 63
5090 08:06:19.628742 [CA 1] Center 37 (7~68) winsize 62
5091 08:06:19.632258 [CA 2] Center 34 (4~65) winsize 62
5092 08:06:19.635390 [CA 3] Center 35 (5~65) winsize 61
5093 08:06:19.638788 [CA 4] Center 33 (3~64) winsize 62
5094 08:06:19.641913 [CA 5] Center 33 (3~64) winsize 62
5095 08:06:19.642346
5096 08:06:19.645296 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5097 08:06:19.645809
5098 08:06:19.648497 [CATrainingPosCal] consider 1 rank data
5099 08:06:19.652217 u2DelayCellTimex100 = 270/100 ps
5100 08:06:19.655064 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5101 08:06:19.659111 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5102 08:06:19.661787 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5103 08:06:19.668951 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5104 08:06:19.671964 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5105 08:06:19.675449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5106 08:06:19.676051
5107 08:06:19.679021 CA PerBit enable=1, Macro0, CA PI delay=33
5108 08:06:19.679570
5109 08:06:19.681346 [CBTSetCACLKResult] CA Dly = 33
5110 08:06:19.681804 CS Dly: 7 (0~38)
5111 08:06:19.682167 ==
5112 08:06:19.685026 Dram Type= 6, Freq= 0, CH_0, rank 1
5113 08:06:19.691344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 08:06:19.691851 ==
5115 08:06:19.694880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 08:06:19.701143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5117 08:06:19.705026 [CA 0] Center 37 (7~68) winsize 62
5118 08:06:19.708048 [CA 1] Center 37 (7~68) winsize 62
5119 08:06:19.711435 [CA 2] Center 34 (4~65) winsize 62
5120 08:06:19.715098 [CA 3] Center 34 (4~65) winsize 62
5121 08:06:19.718803 [CA 4] Center 33 (3~64) winsize 62
5122 08:06:19.720931 [CA 5] Center 32 (2~63) winsize 62
5123 08:06:19.721462
5124 08:06:19.724397 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5125 08:06:19.724964
5126 08:06:19.727761 [CATrainingPosCal] consider 2 rank data
5127 08:06:19.731149 u2DelayCellTimex100 = 270/100 ps
5128 08:06:19.734196 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5129 08:06:19.740679 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5130 08:06:19.744307 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5131 08:06:19.747703 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5132 08:06:19.750811 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 08:06:19.753714 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5134 08:06:19.754175
5135 08:06:19.757770 CA PerBit enable=1, Macro0, CA PI delay=33
5136 08:06:19.758333
5137 08:06:19.760957 [CBTSetCACLKResult] CA Dly = 33
5138 08:06:19.763973 CS Dly: 7 (0~39)
5139 08:06:19.764530
5140 08:06:19.767358 ----->DramcWriteLeveling(PI) begin...
5141 08:06:19.767971 ==
5142 08:06:19.770564 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 08:06:19.774476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 08:06:19.775137 ==
5145 08:06:19.777071 Write leveling (Byte 0): 30 => 30
5146 08:06:19.780703 Write leveling (Byte 1): 31 => 31
5147 08:06:19.783397 DramcWriteLeveling(PI) end<-----
5148 08:06:19.784070
5149 08:06:19.784519 ==
5150 08:06:19.787045 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 08:06:19.790969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 08:06:19.791538 ==
5153 08:06:19.793600 [Gating] SW mode calibration
5154 08:06:19.799986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5155 08:06:19.806458 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5156 08:06:19.810378 0 14 0 | B1->B0 | 2322 3232 | 1 1 | (0 0) (1 1)
5157 08:06:19.816753 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5158 08:06:19.819984 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 08:06:19.823313 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 08:06:19.829717 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 08:06:19.833639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 08:06:19.836339 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 08:06:19.843227 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5164 08:06:19.846415 0 15 0 | B1->B0 | 3030 2626 | 0 0 | (1 0) (0 0)
5165 08:06:19.849409 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 08:06:19.856399 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 08:06:19.859423 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 08:06:19.862980 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 08:06:19.869953 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 08:06:19.872452 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 08:06:19.876138 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
5172 08:06:19.882695 1 0 0 | B1->B0 | 2e2e 4242 | 0 0 | (0 0) (1 1)
5173 08:06:19.886327 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 08:06:19.889021 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 08:06:19.895989 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 08:06:19.899306 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 08:06:19.902698 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 08:06:19.906855 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 08:06:19.911857 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5180 08:06:19.915490 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5181 08:06:19.922799 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 08:06:19.925726 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 08:06:19.929096 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 08:06:19.932969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 08:06:19.938535 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 08:06:19.942001 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 08:06:19.945446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 08:06:19.952419 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 08:06:19.955245 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 08:06:19.958638 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 08:06:19.964972 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 08:06:19.968386 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 08:06:19.972723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 08:06:19.978511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 08:06:19.981895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5196 08:06:19.985302 Total UI for P1: 0, mck2ui 16
5197 08:06:19.988301 best dqsien dly found for B0: ( 1, 2, 26)
5198 08:06:19.991503 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5199 08:06:19.998084 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 08:06:20.001508 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 08:06:20.004436 Total UI for P1: 0, mck2ui 16
5202 08:06:20.007901 best dqsien dly found for B1: ( 1, 3, 4)
5203 08:06:20.011123 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5204 08:06:20.014893 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5205 08:06:20.015464
5206 08:06:20.017821 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5207 08:06:20.021187 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5208 08:06:20.024681 [Gating] SW calibration Done
5209 08:06:20.025243 ==
5210 08:06:20.028026 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 08:06:20.034778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 08:06:20.035343 ==
5213 08:06:20.035838 RX Vref Scan: 0
5214 08:06:20.036323
5215 08:06:20.037649 RX Vref 0 -> 0, step: 1
5216 08:06:20.038120
5217 08:06:20.040997 RX Delay -80 -> 252, step: 8
5218 08:06:20.044546 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5219 08:06:20.047421 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5220 08:06:20.050909 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5221 08:06:20.054105 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5222 08:06:20.060885 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5223 08:06:20.064348 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5224 08:06:20.067794 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5225 08:06:20.070693 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5226 08:06:20.074322 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5227 08:06:20.077139 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5228 08:06:20.083979 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5229 08:06:20.087198 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5230 08:06:20.090079 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5231 08:06:20.093378 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5232 08:06:20.100035 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5233 08:06:20.103649 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5234 08:06:20.104293 ==
5235 08:06:20.106821 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 08:06:20.110198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 08:06:20.110757 ==
5238 08:06:20.111126 DQS Delay:
5239 08:06:20.113521 DQS0 = 0, DQS1 = 0
5240 08:06:20.114075 DQM Delay:
5241 08:06:20.116444 DQM0 = 97, DQM1 = 86
5242 08:06:20.116918 DQ Delay:
5243 08:06:20.120319 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5244 08:06:20.123472 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5245 08:06:20.126885 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5246 08:06:20.130064 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5247 08:06:20.130630
5248 08:06:20.131116
5249 08:06:20.131691 ==
5250 08:06:20.133523 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 08:06:20.139628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 08:06:20.140134 ==
5253 08:06:20.140499
5254 08:06:20.140833
5255 08:06:20.141154 TX Vref Scan disable
5256 08:06:20.142988 == TX Byte 0 ==
5257 08:06:20.146594 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5258 08:06:20.153257 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5259 08:06:20.153825 == TX Byte 1 ==
5260 08:06:20.156686 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5261 08:06:20.163987 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5262 08:06:20.164552 ==
5263 08:06:20.166716 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 08:06:20.169277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 08:06:20.169765 ==
5266 08:06:20.170246
5267 08:06:20.170693
5268 08:06:20.173348 TX Vref Scan disable
5269 08:06:20.173922 == TX Byte 0 ==
5270 08:06:20.180843 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5271 08:06:20.182926 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5272 08:06:20.183498 == TX Byte 1 ==
5273 08:06:20.190167 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5274 08:06:20.192752 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5275 08:06:20.193228
5276 08:06:20.193705 [DATLAT]
5277 08:06:20.196477 Freq=933, CH0 RK0
5278 08:06:20.196948
5279 08:06:20.197427 DATLAT Default: 0xd
5280 08:06:20.199420 0, 0xFFFF, sum = 0
5281 08:06:20.199928 1, 0xFFFF, sum = 0
5282 08:06:20.202815 2, 0xFFFF, sum = 0
5283 08:06:20.206192 3, 0xFFFF, sum = 0
5284 08:06:20.206772 4, 0xFFFF, sum = 0
5285 08:06:20.209241 5, 0xFFFF, sum = 0
5286 08:06:20.209717 6, 0xFFFF, sum = 0
5287 08:06:20.213366 7, 0xFFFF, sum = 0
5288 08:06:20.213946 8, 0xFFFF, sum = 0
5289 08:06:20.215677 9, 0xFFFF, sum = 0
5290 08:06:20.216203 10, 0x0, sum = 1
5291 08:06:20.219047 11, 0x0, sum = 2
5292 08:06:20.219527 12, 0x0, sum = 3
5293 08:06:20.222452 13, 0x0, sum = 4
5294 08:06:20.222930 best_step = 11
5295 08:06:20.223407
5296 08:06:20.223989 ==
5297 08:06:20.225532 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 08:06:20.229057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 08:06:20.229627 ==
5300 08:06:20.232521 RX Vref Scan: 1
5301 08:06:20.233094
5302 08:06:20.235631 RX Vref 0 -> 0, step: 1
5303 08:06:20.236223
5304 08:06:20.236717 RX Delay -61 -> 252, step: 4
5305 08:06:20.238787
5306 08:06:20.239256 Set Vref, RX VrefLevel [Byte0]: 61
5307 08:06:20.242286 [Byte1]: 48
5308 08:06:20.246905
5309 08:06:20.247520 Final RX Vref Byte 0 = 61 to rank0
5310 08:06:20.250107 Final RX Vref Byte 1 = 48 to rank0
5311 08:06:20.253533 Final RX Vref Byte 0 = 61 to rank1
5312 08:06:20.257104 Final RX Vref Byte 1 = 48 to rank1==
5313 08:06:20.260452 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 08:06:20.267144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 08:06:20.267383 ==
5316 08:06:20.267513 DQS Delay:
5317 08:06:20.267627 DQS0 = 0, DQS1 = 0
5318 08:06:20.270119 DQM Delay:
5319 08:06:20.270357 DQM0 = 97, DQM1 = 85
5320 08:06:20.273600 DQ Delay:
5321 08:06:20.276842 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5322 08:06:20.279754 DQ4 =98, DQ5 =88, DQ6 =108, DQ7 =106
5323 08:06:20.283779 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5324 08:06:20.286461 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =94
5325 08:06:20.286624
5326 08:06:20.286745
5327 08:06:20.292925 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5328 08:06:20.296209 CH0 RK0: MR19=505, MR18=2B12
5329 08:06:20.303294 CH0_RK0: MR19=0x505, MR18=0x2B12, DQSOSC=408, MR23=63, INC=65, DEC=43
5330 08:06:20.303560
5331 08:06:20.306449 ----->DramcWriteLeveling(PI) begin...
5332 08:06:20.306631 ==
5333 08:06:20.309352 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 08:06:20.312939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 08:06:20.313287 ==
5336 08:06:20.316417 Write leveling (Byte 0): 32 => 32
5337 08:06:20.320418 Write leveling (Byte 1): 29 => 29
5338 08:06:20.323431 DramcWriteLeveling(PI) end<-----
5339 08:06:20.323987
5340 08:06:20.324320 ==
5341 08:06:20.326951 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 08:06:20.329635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 08:06:20.332616 ==
5344 08:06:20.333078 [Gating] SW mode calibration
5345 08:06:20.343362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5346 08:06:20.346997 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5347 08:06:20.349900 0 14 0 | B1->B0 | 2e2e 3434 | 1 0 | (1 1) (1 1)
5348 08:06:20.356267 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 08:06:20.359371 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 08:06:20.362761 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 08:06:20.369935 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 08:06:20.372618 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 08:06:20.376397 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 08:06:20.382523 0 14 28 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
5355 08:06:20.385484 0 15 0 | B1->B0 | 2c2c 2626 | 0 0 | (0 1) (1 1)
5356 08:06:20.388973 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 08:06:20.395496 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 08:06:20.398768 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 08:06:20.402385 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 08:06:20.409315 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 08:06:20.412097 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 08:06:20.416537 0 15 28 | B1->B0 | 2727 3636 | 0 0 | (1 1) (0 0)
5363 08:06:20.422280 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5364 08:06:20.425133 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 08:06:20.428688 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 08:06:20.435417 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 08:06:20.438502 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 08:06:20.442329 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 08:06:20.449113 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 08:06:20.451794 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5371 08:06:20.455040 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 08:06:20.462038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 08:06:20.465091 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 08:06:20.468354 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 08:06:20.475548 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 08:06:20.478569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 08:06:20.481805 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 08:06:20.488136 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 08:06:20.491398 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 08:06:20.494872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 08:06:20.501350 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 08:06:20.504719 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 08:06:20.508065 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 08:06:20.514525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 08:06:20.518325 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 08:06:20.521687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5387 08:06:20.527520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5388 08:06:20.528105 Total UI for P1: 0, mck2ui 16
5389 08:06:20.534641 best dqsien dly found for B0: ( 1, 2, 28)
5390 08:06:20.537593 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 08:06:20.541390 Total UI for P1: 0, mck2ui 16
5392 08:06:20.544629 best dqsien dly found for B1: ( 1, 2, 30)
5393 08:06:20.547618 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5394 08:06:20.551433 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5395 08:06:20.552057
5396 08:06:20.554506 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5397 08:06:20.558126 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5398 08:06:20.561263 [Gating] SW calibration Done
5399 08:06:20.561824 ==
5400 08:06:20.564529 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 08:06:20.567228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 08:06:20.570766 ==
5403 08:06:20.571172 RX Vref Scan: 0
5404 08:06:20.571526
5405 08:06:20.574160 RX Vref 0 -> 0, step: 1
5406 08:06:20.574717
5407 08:06:20.577137 RX Delay -80 -> 252, step: 8
5408 08:06:20.580546 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5409 08:06:20.583978 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5410 08:06:20.587080 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5411 08:06:20.590275 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5412 08:06:20.593701 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5413 08:06:20.600207 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5414 08:06:20.603428 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5415 08:06:20.607082 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5416 08:06:20.610081 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5417 08:06:20.613320 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5418 08:06:20.620328 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5419 08:06:20.624001 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5420 08:06:20.626646 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5421 08:06:20.630258 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5422 08:06:20.633311 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5423 08:06:20.639781 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5424 08:06:20.640224 ==
5425 08:06:20.643385 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 08:06:20.646637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 08:06:20.647184 ==
5428 08:06:20.647628 DQS Delay:
5429 08:06:20.649636 DQS0 = 0, DQS1 = 0
5430 08:06:20.650062 DQM Delay:
5431 08:06:20.653347 DQM0 = 97, DQM1 = 87
5432 08:06:20.653834 DQ Delay:
5433 08:06:20.656591 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5434 08:06:20.659867 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5435 08:06:20.662894 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5436 08:06:20.666068 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5437 08:06:20.666589
5438 08:06:20.667029
5439 08:06:20.667441 ==
5440 08:06:20.669256 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 08:06:20.672820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 08:06:20.676171 ==
5443 08:06:20.676704
5444 08:06:20.677145
5445 08:06:20.677555 TX Vref Scan disable
5446 08:06:20.679693 == TX Byte 0 ==
5447 08:06:20.683582 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5448 08:06:20.686023 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5449 08:06:20.690347 == TX Byte 1 ==
5450 08:06:20.692577 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5451 08:06:20.696834 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5452 08:06:20.699540 ==
5453 08:06:20.702822 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 08:06:20.706331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 08:06:20.706858 ==
5456 08:06:20.707303
5457 08:06:20.707714
5458 08:06:20.709098 TX Vref Scan disable
5459 08:06:20.709514 == TX Byte 0 ==
5460 08:06:20.716133 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5461 08:06:20.719111 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5462 08:06:20.719628 == TX Byte 1 ==
5463 08:06:20.726138 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5464 08:06:20.729054 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5465 08:06:20.729572
5466 08:06:20.729896 [DATLAT]
5467 08:06:20.732600 Freq=933, CH0 RK1
5468 08:06:20.733014
5469 08:06:20.733343 DATLAT Default: 0xb
5470 08:06:20.735446 0, 0xFFFF, sum = 0
5471 08:06:20.735911 1, 0xFFFF, sum = 0
5472 08:06:20.739338 2, 0xFFFF, sum = 0
5473 08:06:20.739898 3, 0xFFFF, sum = 0
5474 08:06:20.742385 4, 0xFFFF, sum = 0
5475 08:06:20.742908 5, 0xFFFF, sum = 0
5476 08:06:20.745570 6, 0xFFFF, sum = 0
5477 08:06:20.749170 7, 0xFFFF, sum = 0
5478 08:06:20.749588 8, 0xFFFF, sum = 0
5479 08:06:20.752179 9, 0xFFFF, sum = 0
5480 08:06:20.752633 10, 0x0, sum = 1
5481 08:06:20.755467 11, 0x0, sum = 2
5482 08:06:20.755918 12, 0x0, sum = 3
5483 08:06:20.756255 13, 0x0, sum = 4
5484 08:06:20.758595 best_step = 11
5485 08:06:20.759011
5486 08:06:20.759337 ==
5487 08:06:20.761713 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 08:06:20.765398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 08:06:20.765814 ==
5490 08:06:20.768401 RX Vref Scan: 0
5491 08:06:20.768847
5492 08:06:20.769182 RX Vref 0 -> 0, step: 1
5493 08:06:20.772198
5494 08:06:20.772761 RX Delay -61 -> 252, step: 4
5495 08:06:20.780472 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5496 08:06:20.782639 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5497 08:06:20.786631 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5498 08:06:20.789252 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5499 08:06:20.792788 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5500 08:06:20.795903 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5501 08:06:20.802770 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5502 08:06:20.806007 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5503 08:06:20.809131 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5504 08:06:20.812611 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5505 08:06:20.815906 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5506 08:06:20.822459 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5507 08:06:20.825633 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5508 08:06:20.829428 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5509 08:06:20.832104 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5510 08:06:20.838755 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5511 08:06:20.839260 ==
5512 08:06:20.842583 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 08:06:20.846033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 08:06:20.846549 ==
5515 08:06:20.846883 DQS Delay:
5516 08:06:20.848982 DQS0 = 0, DQS1 = 0
5517 08:06:20.849495 DQM Delay:
5518 08:06:20.852644 DQM0 = 95, DQM1 = 86
5519 08:06:20.853175 DQ Delay:
5520 08:06:20.855884 DQ0 =94, DQ1 =96, DQ2 =90, DQ3 =94
5521 08:06:20.858829 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5522 08:06:20.862023 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5523 08:06:20.865537 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5524 08:06:20.866051
5525 08:06:20.866383
5526 08:06:20.871557 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5527 08:06:20.875135 CH0 RK1: MR19=504, MR18=2AFA
5528 08:06:20.882022 CH0_RK1: MR19=0x504, MR18=0x2AFA, DQSOSC=408, MR23=63, INC=65, DEC=43
5529 08:06:20.885535 [RxdqsGatingPostProcess] freq 933
5530 08:06:20.891905 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5531 08:06:20.894914 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 08:06:20.895351 best DQS1 dly(2T, 0.5T) = (0, 11)
5533 08:06:20.898039 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 08:06:20.902007 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5535 08:06:20.905717 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 08:06:20.908304 best DQS1 dly(2T, 0.5T) = (0, 10)
5537 08:06:20.911517 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 08:06:20.914487 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5539 08:06:20.918558 Pre-setting of DQS Precalculation
5540 08:06:20.924815 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5541 08:06:20.925330 ==
5542 08:06:20.928637 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 08:06:20.932003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 08:06:20.932524 ==
5545 08:06:20.937814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 08:06:20.945145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5547 08:06:20.948036 [CA 0] Center 36 (6~67) winsize 62
5548 08:06:20.951363 [CA 1] Center 37 (6~68) winsize 63
5549 08:06:20.954993 [CA 2] Center 34 (4~65) winsize 62
5550 08:06:20.957908 [CA 3] Center 33 (3~64) winsize 62
5551 08:06:20.961289 [CA 4] Center 34 (4~64) winsize 61
5552 08:06:20.965464 [CA 5] Center 33 (3~64) winsize 62
5553 08:06:20.965980
5554 08:06:20.967358 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5555 08:06:20.967812
5556 08:06:20.971503 [CATrainingPosCal] consider 1 rank data
5557 08:06:20.974701 u2DelayCellTimex100 = 270/100 ps
5558 08:06:20.978014 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 08:06:20.980595 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5560 08:06:20.984289 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 08:06:20.988107 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5562 08:06:20.991061 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 08:06:20.994848 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 08:06:20.995363
5565 08:06:21.000193 CA PerBit enable=1, Macro0, CA PI delay=33
5566 08:06:21.000605
5567 08:06:21.000932 [CBTSetCACLKResult] CA Dly = 33
5568 08:06:21.003659 CS Dly: 6 (0~37)
5569 08:06:21.004106 ==
5570 08:06:21.006920 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 08:06:21.012755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 08:06:21.013208 ==
5573 08:06:21.016732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 08:06:21.024220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5575 08:06:21.026865 [CA 0] Center 36 (6~67) winsize 62
5576 08:06:21.030124 [CA 1] Center 36 (6~67) winsize 62
5577 08:06:21.033752 [CA 2] Center 34 (4~65) winsize 62
5578 08:06:21.036651 [CA 3] Center 33 (3~64) winsize 62
5579 08:06:21.040315 [CA 4] Center 34 (3~65) winsize 63
5580 08:06:21.044273 [CA 5] Center 33 (3~64) winsize 62
5581 08:06:21.044829
5582 08:06:21.047034 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5583 08:06:21.047590
5584 08:06:21.050409 [CATrainingPosCal] consider 2 rank data
5585 08:06:21.053701 u2DelayCellTimex100 = 270/100 ps
5586 08:06:21.057465 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 08:06:21.060107 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 08:06:21.063890 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5589 08:06:21.067125 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5590 08:06:21.070123 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 08:06:21.076774 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 08:06:21.077336
5593 08:06:21.079939 CA PerBit enable=1, Macro0, CA PI delay=33
5594 08:06:21.080494
5595 08:06:21.083495 [CBTSetCACLKResult] CA Dly = 33
5596 08:06:21.084095 CS Dly: 7 (0~39)
5597 08:06:21.084464
5598 08:06:21.086335 ----->DramcWriteLeveling(PI) begin...
5599 08:06:21.086799 ==
5600 08:06:21.089491 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 08:06:21.096136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 08:06:21.096598 ==
5603 08:06:21.099786 Write leveling (Byte 0): 25 => 25
5604 08:06:21.100250 Write leveling (Byte 1): 31 => 31
5605 08:06:21.103460 DramcWriteLeveling(PI) end<-----
5606 08:06:21.104067
5607 08:06:21.106639 ==
5608 08:06:21.107193 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 08:06:21.112812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 08:06:21.113271 ==
5611 08:06:21.116636 [Gating] SW mode calibration
5612 08:06:21.122777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5613 08:06:21.126070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5614 08:06:21.132487 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5615 08:06:21.136001 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 08:06:21.139584 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 08:06:21.145658 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 08:06:21.149627 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 08:06:21.152136 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 08:06:21.159404 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5621 08:06:21.163039 0 14 28 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
5622 08:06:21.166116 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 08:06:21.172992 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 08:06:21.176433 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 08:06:21.179103 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 08:06:21.185413 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 08:06:21.189355 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 08:06:21.193264 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5629 08:06:21.198701 0 15 28 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
5630 08:06:21.202077 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 08:06:21.205303 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 08:06:21.211623 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 08:06:21.215719 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 08:06:21.218710 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 08:06:21.225704 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 08:06:21.228936 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5637 08:06:21.232329 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 08:06:21.238928 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 08:06:21.241816 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 08:06:21.245470 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 08:06:21.251287 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 08:06:21.254706 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 08:06:21.258097 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 08:06:21.264581 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 08:06:21.267936 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 08:06:21.271531 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 08:06:21.277897 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 08:06:21.281541 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 08:06:21.284840 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 08:06:21.291124 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 08:06:21.294504 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 08:06:21.298186 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5653 08:06:21.304346 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5654 08:06:21.304905 Total UI for P1: 0, mck2ui 16
5655 08:06:21.311102 best dqsien dly found for B0: ( 1, 2, 24)
5656 08:06:21.314468 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 08:06:21.317285 Total UI for P1: 0, mck2ui 16
5658 08:06:21.320638 best dqsien dly found for B1: ( 1, 2, 28)
5659 08:06:21.323919 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5660 08:06:21.327350 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5661 08:06:21.327948
5662 08:06:21.331276 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5663 08:06:21.333667 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5664 08:06:21.337174 [Gating] SW calibration Done
5665 08:06:21.337728 ==
5666 08:06:21.340376 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 08:06:21.347661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 08:06:21.348263 ==
5669 08:06:21.348677 RX Vref Scan: 0
5670 08:06:21.349019
5671 08:06:21.350155 RX Vref 0 -> 0, step: 1
5672 08:06:21.350613
5673 08:06:21.353808 RX Delay -80 -> 252, step: 8
5674 08:06:21.356708 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5675 08:06:21.360267 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5676 08:06:21.363655 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5677 08:06:21.366642 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5678 08:06:21.373550 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5679 08:06:21.376484 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5680 08:06:21.380055 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5681 08:06:21.382966 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5682 08:06:21.386667 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5683 08:06:21.390325 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5684 08:06:21.397124 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5685 08:06:21.399864 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5686 08:06:21.403183 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5687 08:06:21.406717 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5688 08:06:21.409973 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5689 08:06:21.416401 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5690 08:06:21.416958 ==
5691 08:06:21.419635 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 08:06:21.422803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 08:06:21.423365 ==
5694 08:06:21.423788 DQS Delay:
5695 08:06:21.426591 DQS0 = 0, DQS1 = 0
5696 08:06:21.427147 DQM Delay:
5697 08:06:21.429489 DQM0 = 100, DQM1 = 90
5698 08:06:21.430046 DQ Delay:
5699 08:06:21.432493 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5700 08:06:21.435914 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5701 08:06:21.439187 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5702 08:06:21.442721 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5703 08:06:21.443293
5704 08:06:21.443655
5705 08:06:21.444030 ==
5706 08:06:21.445837 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 08:06:21.449291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 08:06:21.452563 ==
5709 08:06:21.453120
5710 08:06:21.453483
5711 08:06:21.453818 TX Vref Scan disable
5712 08:06:21.455989 == TX Byte 0 ==
5713 08:06:21.459461 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5714 08:06:21.462380 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5715 08:06:21.465993 == TX Byte 1 ==
5716 08:06:21.469235 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5717 08:06:21.475835 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5718 08:06:21.476400 ==
5719 08:06:21.478890 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 08:06:21.482174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 08:06:21.482734 ==
5722 08:06:21.483102
5723 08:06:21.483439
5724 08:06:21.485746 TX Vref Scan disable
5725 08:06:21.486305 == TX Byte 0 ==
5726 08:06:21.492157 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5727 08:06:21.494978 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5728 08:06:21.495443 == TX Byte 1 ==
5729 08:06:21.501756 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5730 08:06:21.505330 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5731 08:06:21.505915
5732 08:06:21.506286 [DATLAT]
5733 08:06:21.508409 Freq=933, CH1 RK0
5734 08:06:21.508933
5735 08:06:21.509436 DATLAT Default: 0xd
5736 08:06:21.511478 0, 0xFFFF, sum = 0
5737 08:06:21.515310 1, 0xFFFF, sum = 0
5738 08:06:21.515944 2, 0xFFFF, sum = 0
5739 08:06:21.518342 3, 0xFFFF, sum = 0
5740 08:06:21.518899 4, 0xFFFF, sum = 0
5741 08:06:21.521460 5, 0xFFFF, sum = 0
5742 08:06:21.521924 6, 0xFFFF, sum = 0
5743 08:06:21.525040 7, 0xFFFF, sum = 0
5744 08:06:21.525604 8, 0xFFFF, sum = 0
5745 08:06:21.528266 9, 0xFFFF, sum = 0
5746 08:06:21.528729 10, 0x0, sum = 1
5747 08:06:21.531989 11, 0x0, sum = 2
5748 08:06:21.532582 12, 0x0, sum = 3
5749 08:06:21.534815 13, 0x0, sum = 4
5750 08:06:21.535377 best_step = 11
5751 08:06:21.535796
5752 08:06:21.536155 ==
5753 08:06:21.538193 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 08:06:21.542035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 08:06:21.542595 ==
5756 08:06:21.545385 RX Vref Scan: 1
5757 08:06:21.545938
5758 08:06:21.548177 RX Vref 0 -> 0, step: 1
5759 08:06:21.548732
5760 08:06:21.549097 RX Delay -69 -> 252, step: 4
5761 08:06:21.549438
5762 08:06:21.551555 Set Vref, RX VrefLevel [Byte0]: 50
5763 08:06:21.554570 [Byte1]: 52
5764 08:06:21.559828
5765 08:06:21.560382 Final RX Vref Byte 0 = 50 to rank0
5766 08:06:21.563142 Final RX Vref Byte 1 = 52 to rank0
5767 08:06:21.566438 Final RX Vref Byte 0 = 50 to rank1
5768 08:06:21.569309 Final RX Vref Byte 1 = 52 to rank1==
5769 08:06:21.572728 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 08:06:21.579058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 08:06:21.579615 ==
5772 08:06:21.580052 DQS Delay:
5773 08:06:21.583303 DQS0 = 0, DQS1 = 0
5774 08:06:21.583920 DQM Delay:
5775 08:06:21.584299 DQM0 = 100, DQM1 = 93
5776 08:06:21.585741 DQ Delay:
5777 08:06:21.589461 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5778 08:06:21.592580 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =98
5779 08:06:21.595967 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5780 08:06:21.599165 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5781 08:06:21.599778
5782 08:06:21.600162
5783 08:06:21.606057 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5784 08:06:21.608576 CH1 RK0: MR19=505, MR18=1D0D
5785 08:06:21.615489 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5786 08:06:21.616012
5787 08:06:21.618787 ----->DramcWriteLeveling(PI) begin...
5788 08:06:21.619359 ==
5789 08:06:21.622327 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 08:06:21.626352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 08:06:21.629309 ==
5792 08:06:21.629864 Write leveling (Byte 0): 27 => 27
5793 08:06:21.631893 Write leveling (Byte 1): 27 => 27
5794 08:06:21.635038 DramcWriteLeveling(PI) end<-----
5795 08:06:21.635499
5796 08:06:21.635915 ==
5797 08:06:21.638407 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 08:06:21.645063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 08:06:21.645525 ==
5800 08:06:21.648069 [Gating] SW mode calibration
5801 08:06:21.655180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5802 08:06:21.658763 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5803 08:06:21.665154 0 14 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
5804 08:06:21.668267 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 08:06:21.671954 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 08:06:21.678060 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 08:06:21.681699 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 08:06:21.684563 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 08:06:21.691372 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5810 08:06:21.694215 0 14 28 | B1->B0 | 2d2d 3030 | 0 1 | (0 0) (1 0)
5811 08:06:21.697641 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 08:06:21.704428 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 08:06:21.707794 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 08:06:21.711518 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 08:06:21.717683 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 08:06:21.721562 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 08:06:21.724417 0 15 24 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
5818 08:06:21.730847 0 15 28 | B1->B0 | 4646 3737 | 0 0 | (0 0) (0 0)
5819 08:06:21.734360 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 08:06:21.737653 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 08:06:21.744065 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 08:06:21.747046 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 08:06:21.751121 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 08:06:21.756984 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 08:06:21.761239 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 08:06:21.763787 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5827 08:06:21.770730 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 08:06:21.774067 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 08:06:21.777048 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 08:06:21.783845 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 08:06:21.787498 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 08:06:21.790367 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 08:06:21.796801 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 08:06:21.799943 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 08:06:21.803836 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 08:06:21.810203 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 08:06:21.813492 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 08:06:21.816568 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 08:06:21.823570 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 08:06:21.826993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 08:06:21.829994 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5842 08:06:21.836413 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 08:06:21.839884 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 08:06:21.843390 Total UI for P1: 0, mck2ui 16
5845 08:06:21.846312 best dqsien dly found for B0: ( 1, 2, 26)
5846 08:06:21.849481 Total UI for P1: 0, mck2ui 16
5847 08:06:21.853381 best dqsien dly found for B1: ( 1, 2, 26)
5848 08:06:21.856326 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5849 08:06:21.859567 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5850 08:06:21.860176
5851 08:06:21.862986 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5852 08:06:21.866225 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5853 08:06:21.869543 [Gating] SW calibration Done
5854 08:06:21.870099 ==
5855 08:06:21.872980 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 08:06:21.876417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 08:06:21.876985 ==
5858 08:06:21.879400 RX Vref Scan: 0
5859 08:06:21.880008
5860 08:06:21.882766 RX Vref 0 -> 0, step: 1
5861 08:06:21.883318
5862 08:06:21.883684 RX Delay -80 -> 252, step: 8
5863 08:06:21.889407 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5864 08:06:21.892811 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5865 08:06:21.896246 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5866 08:06:21.899510 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5867 08:06:21.902777 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5868 08:06:21.909399 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5869 08:06:21.912149 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5870 08:06:21.915849 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5871 08:06:21.919034 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5872 08:06:21.922845 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5873 08:06:21.926037 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5874 08:06:21.932414 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5875 08:06:21.935391 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5876 08:06:21.938983 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5877 08:06:21.942398 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5878 08:06:21.945295 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5879 08:06:21.948836 ==
5880 08:06:21.949394 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 08:06:21.955274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 08:06:21.955929 ==
5883 08:06:21.956349 DQS Delay:
5884 08:06:21.958747 DQS0 = 0, DQS1 = 0
5885 08:06:21.959311 DQM Delay:
5886 08:06:21.962055 DQM0 = 99, DQM1 = 90
5887 08:06:21.962614 DQ Delay:
5888 08:06:21.965574 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5889 08:06:21.968912 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5890 08:06:21.971846 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5891 08:06:21.974837 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5892 08:06:21.975396
5893 08:06:21.975803
5894 08:06:21.976150 ==
5895 08:06:21.978627 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 08:06:21.981534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 08:06:21.982088 ==
5898 08:06:21.982451
5899 08:06:21.985117
5900 08:06:21.985569 TX Vref Scan disable
5901 08:06:21.988466 == TX Byte 0 ==
5902 08:06:21.991947 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5903 08:06:21.994830 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5904 08:06:21.998757 == TX Byte 1 ==
5905 08:06:22.001594 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5906 08:06:22.004400 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5907 08:06:22.004860 ==
5908 08:06:22.007761 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 08:06:22.014640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 08:06:22.015199 ==
5911 08:06:22.015570
5912 08:06:22.015972
5913 08:06:22.016304 TX Vref Scan disable
5914 08:06:22.018766 == TX Byte 0 ==
5915 08:06:22.021914 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5916 08:06:22.029726 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5917 08:06:22.030283 == TX Byte 1 ==
5918 08:06:22.031984 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5919 08:06:22.038706 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5920 08:06:22.039262
5921 08:06:22.039629 [DATLAT]
5922 08:06:22.040013 Freq=933, CH1 RK1
5923 08:06:22.040343
5924 08:06:22.041634 DATLAT Default: 0xb
5925 08:06:22.042091 0, 0xFFFF, sum = 0
5926 08:06:22.045977 1, 0xFFFF, sum = 0
5927 08:06:22.048220 2, 0xFFFF, sum = 0
5928 08:06:22.048683 3, 0xFFFF, sum = 0
5929 08:06:22.051903 4, 0xFFFF, sum = 0
5930 08:06:22.052518 5, 0xFFFF, sum = 0
5931 08:06:22.055151 6, 0xFFFF, sum = 0
5932 08:06:22.055713 7, 0xFFFF, sum = 0
5933 08:06:22.058522 8, 0xFFFF, sum = 0
5934 08:06:22.059085 9, 0xFFFF, sum = 0
5935 08:06:22.062286 10, 0x0, sum = 1
5936 08:06:22.062853 11, 0x0, sum = 2
5937 08:06:22.065028 12, 0x0, sum = 3
5938 08:06:22.065588 13, 0x0, sum = 4
5939 08:06:22.065965 best_step = 11
5940 08:06:22.068575
5941 08:06:22.069029 ==
5942 08:06:22.071481 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 08:06:22.075352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 08:06:22.075958 ==
5945 08:06:22.076330 RX Vref Scan: 0
5946 08:06:22.076665
5947 08:06:22.078566 RX Vref 0 -> 0, step: 1
5948 08:06:22.079132
5949 08:06:22.081595 RX Delay -61 -> 252, step: 4
5950 08:06:22.088400 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5951 08:06:22.092003 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5952 08:06:22.094796 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5953 08:06:22.098038 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5954 08:06:22.101297 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5955 08:06:22.104656 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
5956 08:06:22.111153 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5957 08:06:22.114733 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5958 08:06:22.118208 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5959 08:06:22.121422 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5960 08:06:22.124654 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5961 08:06:22.131371 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5962 08:06:22.134579 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5963 08:06:22.138387 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5964 08:06:22.141490 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5965 08:06:22.145085 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
5966 08:06:22.145669 ==
5967 08:06:22.148114 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 08:06:22.154582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 08:06:22.155174 ==
5970 08:06:22.155547 DQS Delay:
5971 08:06:22.157891 DQS0 = 0, DQS1 = 0
5972 08:06:22.158396 DQM Delay:
5973 08:06:22.158766 DQM0 = 101, DQM1 = 92
5974 08:06:22.161010 DQ Delay:
5975 08:06:22.164545 DQ0 =106, DQ1 =96, DQ2 =88, DQ3 =98
5976 08:06:22.167360 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
5977 08:06:22.171504 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
5978 08:06:22.174547 DQ12 =102, DQ13 =98, DQ14 =98, DQ15 =100
5979 08:06:22.175117
5980 08:06:22.175482
5981 08:06:22.180684 [DQSOSCAuto] RK1, (LSB)MR18= 0x903, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5982 08:06:22.184063 CH1 RK1: MR19=505, MR18=903
5983 08:06:22.191022 CH1_RK1: MR19=0x505, MR18=0x903, DQSOSC=419, MR23=63, INC=61, DEC=41
5984 08:06:22.194914 [RxdqsGatingPostProcess] freq 933
5985 08:06:22.200773 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5986 08:06:22.203811 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 08:06:22.204271 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 08:06:22.207245 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 08:06:22.210676 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 08:06:22.213646 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 08:06:22.216861 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 08:06:22.220762 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 08:06:22.223951 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 08:06:22.227472 Pre-setting of DQS Precalculation
5995 08:06:22.233593 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5996 08:06:22.240520 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5997 08:06:22.246871 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5998 08:06:22.247414
5999 08:06:22.247818
6000 08:06:22.250621 [Calibration Summary] 1866 Mbps
6001 08:06:22.251177 CH 0, Rank 0
6002 08:06:22.253952 SW Impedance : PASS
6003 08:06:22.256488 DUTY Scan : NO K
6004 08:06:22.256954 ZQ Calibration : PASS
6005 08:06:22.260132 Jitter Meter : NO K
6006 08:06:22.263773 CBT Training : PASS
6007 08:06:22.264330 Write leveling : PASS
6008 08:06:22.267168 RX DQS gating : PASS
6009 08:06:22.270754 RX DQ/DQS(RDDQC) : PASS
6010 08:06:22.271312 TX DQ/DQS : PASS
6011 08:06:22.273416 RX DATLAT : PASS
6012 08:06:22.273971 RX DQ/DQS(Engine): PASS
6013 08:06:22.276639 TX OE : NO K
6014 08:06:22.277200 All Pass.
6015 08:06:22.277564
6016 08:06:22.280353 CH 0, Rank 1
6017 08:06:22.280906 SW Impedance : PASS
6018 08:06:22.283552 DUTY Scan : NO K
6019 08:06:22.286519 ZQ Calibration : PASS
6020 08:06:22.287070 Jitter Meter : NO K
6021 08:06:22.290219 CBT Training : PASS
6022 08:06:22.293343 Write leveling : PASS
6023 08:06:22.293898 RX DQS gating : PASS
6024 08:06:22.296644 RX DQ/DQS(RDDQC) : PASS
6025 08:06:22.299839 TX DQ/DQS : PASS
6026 08:06:22.300395 RX DATLAT : PASS
6027 08:06:22.303130 RX DQ/DQS(Engine): PASS
6028 08:06:22.306427 TX OE : NO K
6029 08:06:22.307025 All Pass.
6030 08:06:22.307403
6031 08:06:22.307804 CH 1, Rank 0
6032 08:06:22.309669 SW Impedance : PASS
6033 08:06:22.312690 DUTY Scan : NO K
6034 08:06:22.313191 ZQ Calibration : PASS
6035 08:06:22.316368 Jitter Meter : NO K
6036 08:06:22.319841 CBT Training : PASS
6037 08:06:22.320395 Write leveling : PASS
6038 08:06:22.322894 RX DQS gating : PASS
6039 08:06:22.326376 RX DQ/DQS(RDDQC) : PASS
6040 08:06:22.326934 TX DQ/DQS : PASS
6041 08:06:22.329581 RX DATLAT : PASS
6042 08:06:22.333417 RX DQ/DQS(Engine): PASS
6043 08:06:22.333985 TX OE : NO K
6044 08:06:22.334362 All Pass.
6045 08:06:22.336065
6046 08:06:22.336525 CH 1, Rank 1
6047 08:06:22.339560 SW Impedance : PASS
6048 08:06:22.340168 DUTY Scan : NO K
6049 08:06:22.342813 ZQ Calibration : PASS
6050 08:06:22.343276 Jitter Meter : NO K
6051 08:06:22.346233 CBT Training : PASS
6052 08:06:22.349359 Write leveling : PASS
6053 08:06:22.349920 RX DQS gating : PASS
6054 08:06:22.352673 RX DQ/DQS(RDDQC) : PASS
6055 08:06:22.356080 TX DQ/DQS : PASS
6056 08:06:22.356637 RX DATLAT : PASS
6057 08:06:22.359649 RX DQ/DQS(Engine): PASS
6058 08:06:22.362486 TX OE : NO K
6059 08:06:22.363046 All Pass.
6060 08:06:22.363414
6061 08:06:22.365820 DramC Write-DBI off
6062 08:06:22.366373 PER_BANK_REFRESH: Hybrid Mode
6063 08:06:22.369562 TX_TRACKING: ON
6064 08:06:22.380458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6065 08:06:22.382615 [FAST_K] Save calibration result to emmc
6066 08:06:22.385772 dramc_set_vcore_voltage set vcore to 650000
6067 08:06:22.386328 Read voltage for 400, 6
6068 08:06:22.389178 Vio18 = 0
6069 08:06:22.389738 Vcore = 650000
6070 08:06:22.390106 Vdram = 0
6071 08:06:22.392535 Vddq = 0
6072 08:06:22.393002 Vmddr = 0
6073 08:06:22.398921 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6074 08:06:22.402018 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6075 08:06:22.405657 MEM_TYPE=3, freq_sel=20
6076 08:06:22.408444 sv_algorithm_assistance_LP4_800
6077 08:06:22.412322 ============ PULL DRAM RESETB DOWN ============
6078 08:06:22.415561 ========== PULL DRAM RESETB DOWN end =========
6079 08:06:22.422379 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6080 08:06:22.425353 ===================================
6081 08:06:22.425914 LPDDR4 DRAM CONFIGURATION
6082 08:06:22.428419 ===================================
6083 08:06:22.432279 EX_ROW_EN[0] = 0x0
6084 08:06:22.435449 EX_ROW_EN[1] = 0x0
6085 08:06:22.436061 LP4Y_EN = 0x0
6086 08:06:22.438621 WORK_FSP = 0x0
6087 08:06:22.439183 WL = 0x2
6088 08:06:22.441756 RL = 0x2
6089 08:06:22.442429 BL = 0x2
6090 08:06:22.445260 RPST = 0x0
6091 08:06:22.445829 RD_PRE = 0x0
6092 08:06:22.448407 WR_PRE = 0x1
6093 08:06:22.448871 WR_PST = 0x0
6094 08:06:22.452014 DBI_WR = 0x0
6095 08:06:22.452582 DBI_RD = 0x0
6096 08:06:22.455059 OTF = 0x1
6097 08:06:22.458729 ===================================
6098 08:06:22.461556 ===================================
6099 08:06:22.462125 ANA top config
6100 08:06:22.465391 ===================================
6101 08:06:22.468493 DLL_ASYNC_EN = 0
6102 08:06:22.471527 ALL_SLAVE_EN = 1
6103 08:06:22.474813 NEW_RANK_MODE = 1
6104 08:06:22.475385 DLL_IDLE_MODE = 1
6105 08:06:22.478836 LP45_APHY_COMB_EN = 1
6106 08:06:22.481502 TX_ODT_DIS = 1
6107 08:06:22.485269 NEW_8X_MODE = 1
6108 08:06:22.488281 ===================================
6109 08:06:22.491605 ===================================
6110 08:06:22.494749 data_rate = 800
6111 08:06:22.495315 CKR = 1
6112 08:06:22.498214 DQ_P2S_RATIO = 4
6113 08:06:22.501649 ===================================
6114 08:06:22.504944 CA_P2S_RATIO = 4
6115 08:06:22.507920 DQ_CA_OPEN = 0
6116 08:06:22.511422 DQ_SEMI_OPEN = 1
6117 08:06:22.514477 CA_SEMI_OPEN = 1
6118 08:06:22.515043 CA_FULL_RATE = 0
6119 08:06:22.517810 DQ_CKDIV4_EN = 0
6120 08:06:22.521361 CA_CKDIV4_EN = 1
6121 08:06:22.524570 CA_PREDIV_EN = 0
6122 08:06:22.527931 PH8_DLY = 0
6123 08:06:22.531282 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6124 08:06:22.531911 DQ_AAMCK_DIV = 0
6125 08:06:22.534571 CA_AAMCK_DIV = 0
6126 08:06:22.537661 CA_ADMCK_DIV = 4
6127 08:06:22.540764 DQ_TRACK_CA_EN = 0
6128 08:06:22.543904 CA_PICK = 800
6129 08:06:22.547435 CA_MCKIO = 400
6130 08:06:22.550950 MCKIO_SEMI = 400
6131 08:06:22.551514 PLL_FREQ = 3016
6132 08:06:22.554159 DQ_UI_PI_RATIO = 32
6133 08:06:22.557953 CA_UI_PI_RATIO = 32
6134 08:06:22.560805 ===================================
6135 08:06:22.564357 ===================================
6136 08:06:22.567436 memory_type:LPDDR4
6137 08:06:22.571334 GP_NUM : 10
6138 08:06:22.571956 SRAM_EN : 1
6139 08:06:22.574038 MD32_EN : 0
6140 08:06:22.577205 ===================================
6141 08:06:22.577857 [ANA_INIT] >>>>>>>>>>>>>>
6142 08:06:22.580722 <<<<<< [CONFIGURE PHASE]: ANA_TX
6143 08:06:22.583685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6144 08:06:22.587044 ===================================
6145 08:06:22.590465 data_rate = 800,PCW = 0X7400
6146 08:06:22.594268 ===================================
6147 08:06:22.598122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6148 08:06:22.604307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 08:06:22.613488 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 08:06:22.619829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6151 08:06:22.623826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6152 08:06:22.626724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6153 08:06:22.627294 [ANA_INIT] flow start
6154 08:06:22.630040 [ANA_INIT] PLL >>>>>>>>
6155 08:06:22.633502 [ANA_INIT] PLL <<<<<<<<
6156 08:06:22.636861 [ANA_INIT] MIDPI >>>>>>>>
6157 08:06:22.637426 [ANA_INIT] MIDPI <<<<<<<<
6158 08:06:22.640485 [ANA_INIT] DLL >>>>>>>>
6159 08:06:22.643140 [ANA_INIT] flow end
6160 08:06:22.646307 ============ LP4 DIFF to SE enter ============
6161 08:06:22.650073 ============ LP4 DIFF to SE exit ============
6162 08:06:22.652923 [ANA_INIT] <<<<<<<<<<<<<
6163 08:06:22.656054 [Flow] Enable top DCM control >>>>>
6164 08:06:22.660019 [Flow] Enable top DCM control <<<<<
6165 08:06:22.663348 Enable DLL master slave shuffle
6166 08:06:22.666288 ==============================================================
6167 08:06:22.669590 Gating Mode config
6168 08:06:22.676174 ==============================================================
6169 08:06:22.676720 Config description:
6170 08:06:22.686245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6171 08:06:22.692996 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6172 08:06:22.696095 SELPH_MODE 0: By rank 1: By Phase
6173 08:06:22.702545 ==============================================================
6174 08:06:22.705867 GAT_TRACK_EN = 0
6175 08:06:22.709390 RX_GATING_MODE = 2
6176 08:06:22.712484 RX_GATING_TRACK_MODE = 2
6177 08:06:22.715803 SELPH_MODE = 1
6178 08:06:22.718832 PICG_EARLY_EN = 1
6179 08:06:22.722234 VALID_LAT_VALUE = 1
6180 08:06:22.725800 ==============================================================
6181 08:06:22.729236 Enter into Gating configuration >>>>
6182 08:06:22.732436 Exit from Gating configuration <<<<
6183 08:06:22.735883 Enter into DVFS_PRE_config >>>>>
6184 08:06:22.748707 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6185 08:06:22.752299 Exit from DVFS_PRE_config <<<<<
6186 08:06:22.755451 Enter into PICG configuration >>>>
6187 08:06:22.756198 Exit from PICG configuration <<<<
6188 08:06:22.758440 [RX_INPUT] configuration >>>>>
6189 08:06:22.762080 [RX_INPUT] configuration <<<<<
6190 08:06:22.769000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6191 08:06:22.772205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6192 08:06:22.778718 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 08:06:22.785397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 08:06:22.792691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 08:06:22.798059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 08:06:22.801771 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6197 08:06:22.805075 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6198 08:06:22.811442 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6199 08:06:22.814489 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6200 08:06:22.818360 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6201 08:06:22.821477 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 08:06:22.824999 ===================================
6203 08:06:22.827988 LPDDR4 DRAM CONFIGURATION
6204 08:06:22.831490 ===================================
6205 08:06:22.834577 EX_ROW_EN[0] = 0x0
6206 08:06:22.835131 EX_ROW_EN[1] = 0x0
6207 08:06:22.837950 LP4Y_EN = 0x0
6208 08:06:22.838507 WORK_FSP = 0x0
6209 08:06:22.841378 WL = 0x2
6210 08:06:22.841932 RL = 0x2
6211 08:06:22.844531 BL = 0x2
6212 08:06:22.844988 RPST = 0x0
6213 08:06:22.847922 RD_PRE = 0x0
6214 08:06:22.848481 WR_PRE = 0x1
6215 08:06:22.851261 WR_PST = 0x0
6216 08:06:22.855085 DBI_WR = 0x0
6217 08:06:22.855636 DBI_RD = 0x0
6218 08:06:22.857700 OTF = 0x1
6219 08:06:22.861574 ===================================
6220 08:06:22.864942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6221 08:06:22.867496 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6222 08:06:22.871086 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 08:06:22.874092 ===================================
6224 08:06:22.878029 LPDDR4 DRAM CONFIGURATION
6225 08:06:22.881557 ===================================
6226 08:06:22.884380 EX_ROW_EN[0] = 0x10
6227 08:06:22.884948 EX_ROW_EN[1] = 0x0
6228 08:06:22.888418 LP4Y_EN = 0x0
6229 08:06:22.888984 WORK_FSP = 0x0
6230 08:06:22.891076 WL = 0x2
6231 08:06:22.891643 RL = 0x2
6232 08:06:22.894554 BL = 0x2
6233 08:06:22.895123 RPST = 0x0
6234 08:06:22.897450 RD_PRE = 0x0
6235 08:06:22.897917 WR_PRE = 0x1
6236 08:06:22.900437 WR_PST = 0x0
6237 08:06:22.903793 DBI_WR = 0x0
6238 08:06:22.904495 DBI_RD = 0x0
6239 08:06:22.907173 OTF = 0x1
6240 08:06:22.910861 ===================================
6241 08:06:22.914052 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6242 08:06:22.918965 nWR fixed to 30
6243 08:06:22.923004 [ModeRegInit_LP4] CH0 RK0
6244 08:06:22.923573 [ModeRegInit_LP4] CH0 RK1
6245 08:06:22.925375 [ModeRegInit_LP4] CH1 RK0
6246 08:06:22.929456 [ModeRegInit_LP4] CH1 RK1
6247 08:06:22.930021 match AC timing 19
6248 08:06:22.935720 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6249 08:06:22.938989 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6250 08:06:22.942401 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6251 08:06:22.949259 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6252 08:06:22.951920 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6253 08:06:22.952394 ==
6254 08:06:22.955604 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 08:06:22.958893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 08:06:22.959358 ==
6257 08:06:22.965288 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 08:06:22.972203 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6259 08:06:22.975354 [CA 0] Center 36 (8~64) winsize 57
6260 08:06:22.978386 [CA 1] Center 36 (8~64) winsize 57
6261 08:06:22.981853 [CA 2] Center 36 (8~64) winsize 57
6262 08:06:22.985470 [CA 3] Center 36 (8~64) winsize 57
6263 08:06:22.988329 [CA 4] Center 36 (8~64) winsize 57
6264 08:06:22.991881 [CA 5] Center 36 (8~64) winsize 57
6265 08:06:22.992449
6266 08:06:22.995627 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6267 08:06:22.996241
6268 08:06:22.998282 [CATrainingPosCal] consider 1 rank data
6269 08:06:23.001583 u2DelayCellTimex100 = 270/100 ps
6270 08:06:23.004721 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 08:06:23.008703 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 08:06:23.011213 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 08:06:23.015086 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 08:06:23.018129 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 08:06:23.021064 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 08:06:23.021529
6277 08:06:23.024529 CA PerBit enable=1, Macro0, CA PI delay=36
6278 08:06:23.028174
6279 08:06:23.028761 [CBTSetCACLKResult] CA Dly = 36
6280 08:06:23.031305 CS Dly: 1 (0~32)
6281 08:06:23.031924 ==
6282 08:06:23.035021 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 08:06:23.038105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 08:06:23.038679 ==
6285 08:06:23.044387 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 08:06:23.051068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6287 08:06:23.054806 [CA 0] Center 36 (8~64) winsize 57
6288 08:06:23.057859 [CA 1] Center 36 (8~64) winsize 57
6289 08:06:23.061038 [CA 2] Center 36 (8~64) winsize 57
6290 08:06:23.061591 [CA 3] Center 36 (8~64) winsize 57
6291 08:06:23.064034 [CA 4] Center 36 (8~64) winsize 57
6292 08:06:23.067905 [CA 5] Center 36 (8~64) winsize 57
6293 08:06:23.068691
6294 08:06:23.074356 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6295 08:06:23.074921
6296 08:06:23.077695 [CATrainingPosCal] consider 2 rank data
6297 08:06:23.081291 u2DelayCellTimex100 = 270/100 ps
6298 08:06:23.084439 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 08:06:23.087378 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 08:06:23.090831 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 08:06:23.094311 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 08:06:23.097361 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 08:06:23.100574 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 08:06:23.101160
6305 08:06:23.103679 CA PerBit enable=1, Macro0, CA PI delay=36
6306 08:06:23.104170
6307 08:06:23.107138 [CBTSetCACLKResult] CA Dly = 36
6308 08:06:23.110393 CS Dly: 1 (0~32)
6309 08:06:23.110847
6310 08:06:23.113797 ----->DramcWriteLeveling(PI) begin...
6311 08:06:23.114416 ==
6312 08:06:23.117290 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 08:06:23.120184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 08:06:23.120643 ==
6315 08:06:23.123380 Write leveling (Byte 0): 40 => 8
6316 08:06:23.126865 Write leveling (Byte 1): 32 => 0
6317 08:06:23.130542 DramcWriteLeveling(PI) end<-----
6318 08:06:23.131052
6319 08:06:23.131400 ==
6320 08:06:23.133497 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 08:06:23.136981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 08:06:23.137418 ==
6323 08:06:23.140078 [Gating] SW mode calibration
6324 08:06:23.146590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6325 08:06:23.153193 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6326 08:06:23.156618 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 08:06:23.163592 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 08:06:23.166364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 08:06:23.170133 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 08:06:23.176744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 08:06:23.179691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 08:06:23.183194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 08:06:23.186584 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 08:06:23.193218 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 08:06:23.196366 Total UI for P1: 0, mck2ui 16
6336 08:06:23.199509 best dqsien dly found for B0: ( 0, 14, 24)
6337 08:06:23.202597 Total UI for P1: 0, mck2ui 16
6338 08:06:23.206152 best dqsien dly found for B1: ( 0, 14, 24)
6339 08:06:23.209666 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6340 08:06:23.213086 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6341 08:06:23.213542
6342 08:06:23.216291 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 08:06:23.219300 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 08:06:23.223047 [Gating] SW calibration Done
6345 08:06:23.223600 ==
6346 08:06:23.226220 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 08:06:23.229483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 08:06:23.230037 ==
6349 08:06:23.232820 RX Vref Scan: 0
6350 08:06:23.233267
6351 08:06:23.236319 RX Vref 0 -> 0, step: 1
6352 08:06:23.236876
6353 08:06:23.239237 RX Delay -410 -> 252, step: 16
6354 08:06:23.242197 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6355 08:06:23.245879 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6356 08:06:23.249482 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6357 08:06:23.256115 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6358 08:06:23.259340 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6359 08:06:23.262803 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6360 08:06:23.265815 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6361 08:06:23.272971 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6362 08:06:23.275490 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6363 08:06:23.279218 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6364 08:06:23.282283 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6365 08:06:23.288837 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6366 08:06:23.292395 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6367 08:06:23.296053 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6368 08:06:23.299126 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6369 08:06:23.305408 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6370 08:06:23.305863 ==
6371 08:06:23.308401 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 08:06:23.313017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 08:06:23.313577 ==
6374 08:06:23.314932 DQS Delay:
6375 08:06:23.315387 DQS0 = 43, DQS1 = 59
6376 08:06:23.315794 DQM Delay:
6377 08:06:23.318589 DQM0 = 11, DQM1 = 11
6378 08:06:23.319140 DQ Delay:
6379 08:06:23.321739 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6380 08:06:23.324903 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6381 08:06:23.328287 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6382 08:06:23.331582 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6383 08:06:23.332184
6384 08:06:23.332555
6385 08:06:23.332893 ==
6386 08:06:23.335617 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 08:06:23.338852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 08:06:23.342062 ==
6389 08:06:23.342618
6390 08:06:23.342980
6391 08:06:23.343312 TX Vref Scan disable
6392 08:06:23.344934 == TX Byte 0 ==
6393 08:06:23.348251 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 08:06:23.351525 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 08:06:23.355046 == TX Byte 1 ==
6396 08:06:23.358149 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6397 08:06:23.361069 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6398 08:06:23.361528 ==
6399 08:06:23.364594 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 08:06:23.370961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 08:06:23.371522 ==
6402 08:06:23.371931
6403 08:06:23.372268
6404 08:06:23.372589 TX Vref Scan disable
6405 08:06:23.374877 == TX Byte 0 ==
6406 08:06:23.377750 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 08:06:23.381334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 08:06:23.384384 == TX Byte 1 ==
6409 08:06:23.389142 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6410 08:06:23.391234 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6411 08:06:23.394420
6412 08:06:23.394973 [DATLAT]
6413 08:06:23.395342 Freq=400, CH0 RK0
6414 08:06:23.395685
6415 08:06:23.397679 DATLAT Default: 0xf
6416 08:06:23.398228 0, 0xFFFF, sum = 0
6417 08:06:23.401038 1, 0xFFFF, sum = 0
6418 08:06:23.401601 2, 0xFFFF, sum = 0
6419 08:06:23.404169 3, 0xFFFF, sum = 0
6420 08:06:23.407274 4, 0xFFFF, sum = 0
6421 08:06:23.407794 5, 0xFFFF, sum = 0
6422 08:06:23.411667 6, 0xFFFF, sum = 0
6423 08:06:23.412295 7, 0xFFFF, sum = 0
6424 08:06:23.413838 8, 0xFFFF, sum = 0
6425 08:06:23.414322 9, 0xFFFF, sum = 0
6426 08:06:23.417294 10, 0xFFFF, sum = 0
6427 08:06:23.417754 11, 0xFFFF, sum = 0
6428 08:06:23.420581 12, 0xFFFF, sum = 0
6429 08:06:23.421202 13, 0x0, sum = 1
6430 08:06:23.424295 14, 0x0, sum = 2
6431 08:06:23.424784 15, 0x0, sum = 3
6432 08:06:23.426997 16, 0x0, sum = 4
6433 08:06:23.427460 best_step = 14
6434 08:06:23.427875
6435 08:06:23.428220 ==
6436 08:06:23.430265 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 08:06:23.433807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 08:06:23.437366 ==
6439 08:06:23.437925 RX Vref Scan: 1
6440 08:06:23.438284
6441 08:06:23.440242 RX Vref 0 -> 0, step: 1
6442 08:06:23.440699
6443 08:06:23.444207 RX Delay -359 -> 252, step: 8
6444 08:06:23.444927
6445 08:06:23.447304 Set Vref, RX VrefLevel [Byte0]: 61
6446 08:06:23.450301 [Byte1]: 48
6447 08:06:23.450861
6448 08:06:23.453535 Final RX Vref Byte 0 = 61 to rank0
6449 08:06:23.456806 Final RX Vref Byte 1 = 48 to rank0
6450 08:06:23.460098 Final RX Vref Byte 0 = 61 to rank1
6451 08:06:23.463452 Final RX Vref Byte 1 = 48 to rank1==
6452 08:06:23.466976 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 08:06:23.470153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 08:06:23.473337 ==
6455 08:06:23.473892 DQS Delay:
6456 08:06:23.474253 DQS0 = 48, DQS1 = 60
6457 08:06:23.477219 DQM Delay:
6458 08:06:23.477776 DQM0 = 12, DQM1 = 12
6459 08:06:23.480037 DQ Delay:
6460 08:06:23.480492 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6461 08:06:23.483234 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6462 08:06:23.486859 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6463 08:06:23.489573 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6464 08:06:23.490033
6465 08:06:23.490395
6466 08:06:23.500688 [DQSOSCAuto] RK0, (LSB)MR18= 0xc78a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6467 08:06:23.503039 CH0 RK0: MR19=C0C, MR18=C78A
6468 08:06:23.509609 CH0_RK0: MR19=0xC0C, MR18=0xC78A, DQSOSC=385, MR23=63, INC=398, DEC=265
6469 08:06:23.510173 ==
6470 08:06:23.513255 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 08:06:23.516930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 08:06:23.517393 ==
6473 08:06:23.519780 [Gating] SW mode calibration
6474 08:06:23.526538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 08:06:23.533094 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6476 08:06:23.536143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 08:06:23.539262 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 08:06:23.546141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 08:06:23.549623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 08:06:23.553294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 08:06:23.559194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 08:06:23.562422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 08:06:23.566750 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 08:06:23.572336 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 08:06:23.572924 Total UI for P1: 0, mck2ui 16
6486 08:06:23.578867 best dqsien dly found for B0: ( 0, 14, 24)
6487 08:06:23.579428 Total UI for P1: 0, mck2ui 16
6488 08:06:23.582251 best dqsien dly found for B1: ( 0, 14, 24)
6489 08:06:23.589032 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6490 08:06:23.592456 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6491 08:06:23.593015
6492 08:06:23.595762 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 08:06:23.598585 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 08:06:23.602435 [Gating] SW calibration Done
6495 08:06:23.602991 ==
6496 08:06:23.605254 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 08:06:23.608218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 08:06:23.608804 ==
6499 08:06:23.611694 RX Vref Scan: 0
6500 08:06:23.612179
6501 08:06:23.612540 RX Vref 0 -> 0, step: 1
6502 08:06:23.612877
6503 08:06:23.615139 RX Delay -410 -> 252, step: 16
6504 08:06:23.622167 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6505 08:06:23.625275 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6506 08:06:23.628648 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6507 08:06:23.632664 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6508 08:06:23.638849 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6509 08:06:23.641756 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6510 08:06:23.645200 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6511 08:06:23.648091 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6512 08:06:23.654523 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6513 08:06:23.657744 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6514 08:06:23.661345 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6515 08:06:23.664515 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6516 08:06:23.670899 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6517 08:06:23.674655 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6518 08:06:23.677649 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6519 08:06:23.684929 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6520 08:06:23.685510 ==
6521 08:06:23.688159 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 08:06:23.690892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 08:06:23.691463 ==
6524 08:06:23.691878 DQS Delay:
6525 08:06:23.694430 DQS0 = 43, DQS1 = 59
6526 08:06:23.694905 DQM Delay:
6527 08:06:23.697148 DQM0 = 10, DQM1 = 16
6528 08:06:23.697621 DQ Delay:
6529 08:06:23.700759 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6530 08:06:23.704058 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6531 08:06:23.707011 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6532 08:06:23.710306 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6533 08:06:23.710770
6534 08:06:23.711138
6535 08:06:23.711479 ==
6536 08:06:23.713509 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 08:06:23.716794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 08:06:23.717257 ==
6539 08:06:23.717630
6540 08:06:23.717970
6541 08:06:23.720224 TX Vref Scan disable
6542 08:06:23.724355 == TX Byte 0 ==
6543 08:06:23.727167 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6544 08:06:23.730703 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6545 08:06:23.733846 == TX Byte 1 ==
6546 08:06:23.737140 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6547 08:06:23.740715 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6548 08:06:23.741282 ==
6549 08:06:23.743581 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 08:06:23.747562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 08:06:23.748196 ==
6552 08:06:23.750341
6553 08:06:23.750908
6554 08:06:23.751282 TX Vref Scan disable
6555 08:06:23.753442 == TX Byte 0 ==
6556 08:06:23.756910 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6557 08:06:23.760229 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6558 08:06:23.763392 == TX Byte 1 ==
6559 08:06:23.767047 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6560 08:06:23.770236 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6561 08:06:23.770847
6562 08:06:23.771224 [DATLAT]
6563 08:06:23.773020 Freq=400, CH0 RK1
6564 08:06:23.773487
6565 08:06:23.776653 DATLAT Default: 0xe
6566 08:06:23.777132 0, 0xFFFF, sum = 0
6567 08:06:23.780079 1, 0xFFFF, sum = 0
6568 08:06:23.780642 2, 0xFFFF, sum = 0
6569 08:06:23.783419 3, 0xFFFF, sum = 0
6570 08:06:23.784052 4, 0xFFFF, sum = 0
6571 08:06:23.786596 5, 0xFFFF, sum = 0
6572 08:06:23.787373 6, 0xFFFF, sum = 0
6573 08:06:23.789639 7, 0xFFFF, sum = 0
6574 08:06:23.790108 8, 0xFFFF, sum = 0
6575 08:06:23.793268 9, 0xFFFF, sum = 0
6576 08:06:23.793839 10, 0xFFFF, sum = 0
6577 08:06:23.796241 11, 0xFFFF, sum = 0
6578 08:06:23.796737 12, 0xFFFF, sum = 0
6579 08:06:23.799667 13, 0x0, sum = 1
6580 08:06:23.800288 14, 0x0, sum = 2
6581 08:06:23.803390 15, 0x0, sum = 3
6582 08:06:23.804019 16, 0x0, sum = 4
6583 08:06:23.806695 best_step = 14
6584 08:06:23.807160
6585 08:06:23.807524 ==
6586 08:06:23.809554 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 08:06:23.813007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 08:06:23.813576 ==
6589 08:06:23.816033 RX Vref Scan: 0
6590 08:06:23.816540
6591 08:06:23.816914 RX Vref 0 -> 0, step: 1
6592 08:06:23.817261
6593 08:06:23.819250 RX Delay -359 -> 252, step: 8
6594 08:06:23.827580 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6595 08:06:23.830999 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6596 08:06:23.834606 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6597 08:06:23.840826 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6598 08:06:23.844454 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6599 08:06:23.847086 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6600 08:06:23.850627 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6601 08:06:23.857137 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6602 08:06:23.860516 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6603 08:06:23.863658 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6604 08:06:23.867574 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6605 08:06:23.873210 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6606 08:06:23.876521 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6607 08:06:23.879906 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6608 08:06:23.886557 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6609 08:06:23.889403 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6610 08:06:23.889878 ==
6611 08:06:23.892983 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 08:06:23.896316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 08:06:23.896884 ==
6614 08:06:23.899436 DQS Delay:
6615 08:06:23.899921 DQS0 = 44, DQS1 = 60
6616 08:06:23.900287 DQM Delay:
6617 08:06:23.902839 DQM0 = 8, DQM1 = 15
6618 08:06:23.903296 DQ Delay:
6619 08:06:23.905912 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6620 08:06:23.909512 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6621 08:06:23.912648 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6622 08:06:23.915922 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6623 08:06:23.916430
6624 08:06:23.916890
6625 08:06:23.925810 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb47, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6626 08:06:23.926364 CH0 RK1: MR19=C0C, MR18=BB47
6627 08:06:23.932474 CH0_RK1: MR19=0xC0C, MR18=0xBB47, DQSOSC=386, MR23=63, INC=396, DEC=264
6628 08:06:23.935881 [RxdqsGatingPostProcess] freq 400
6629 08:06:23.942825 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6630 08:06:23.945599 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 08:06:23.949602 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 08:06:23.952066 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 08:06:23.956129 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 08:06:23.958789 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 08:06:23.962673 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 08:06:23.965236 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 08:06:23.968830 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 08:06:23.969390 Pre-setting of DQS Precalculation
6639 08:06:23.975536 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6640 08:06:23.976179 ==
6641 08:06:23.978386 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 08:06:23.981851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 08:06:23.982404 ==
6644 08:06:23.988352 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 08:06:23.995075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6646 08:06:23.998384 [CA 0] Center 36 (8~64) winsize 57
6647 08:06:24.001579 [CA 1] Center 36 (8~64) winsize 57
6648 08:06:24.005178 [CA 2] Center 36 (8~64) winsize 57
6649 08:06:24.007880 [CA 3] Center 36 (8~64) winsize 57
6650 08:06:24.011448 [CA 4] Center 36 (8~64) winsize 57
6651 08:06:24.014635 [CA 5] Center 36 (8~64) winsize 57
6652 08:06:24.015197
6653 08:06:24.018054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6654 08:06:24.018618
6655 08:06:24.021683 [CATrainingPosCal] consider 1 rank data
6656 08:06:24.024274 u2DelayCellTimex100 = 270/100 ps
6657 08:06:24.028002 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 08:06:24.031999 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 08:06:24.034466 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 08:06:24.037945 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 08:06:24.041335 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 08:06:24.044243 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 08:06:24.044711
6664 08:06:24.047497 CA PerBit enable=1, Macro0, CA PI delay=36
6665 08:06:24.051441
6666 08:06:24.052054 [CBTSetCACLKResult] CA Dly = 36
6667 08:06:24.054711 CS Dly: 1 (0~32)
6668 08:06:24.055399 ==
6669 08:06:24.057720 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 08:06:24.060907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 08:06:24.061481 ==
6672 08:06:24.067518 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 08:06:24.074310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6674 08:06:24.077668 [CA 0] Center 36 (8~64) winsize 57
6675 08:06:24.080990 [CA 1] Center 36 (8~64) winsize 57
6676 08:06:24.084226 [CA 2] Center 36 (8~64) winsize 57
6677 08:06:24.084781 [CA 3] Center 36 (8~64) winsize 57
6678 08:06:24.087920 [CA 4] Center 36 (8~64) winsize 57
6679 08:06:24.090616 [CA 5] Center 36 (8~64) winsize 57
6680 08:06:24.091087
6681 08:06:24.097398 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6682 08:06:24.097968
6683 08:06:24.101004 [CATrainingPosCal] consider 2 rank data
6684 08:06:24.104014 u2DelayCellTimex100 = 270/100 ps
6685 08:06:24.106855 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 08:06:24.110577 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 08:06:24.113732 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 08:06:24.116979 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 08:06:24.120390 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 08:06:24.123672 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 08:06:24.124292
6692 08:06:24.127248 CA PerBit enable=1, Macro0, CA PI delay=36
6693 08:06:24.127869
6694 08:06:24.130402 [CBTSetCACLKResult] CA Dly = 36
6695 08:06:24.133803 CS Dly: 1 (0~32)
6696 08:06:24.134376
6697 08:06:24.137053 ----->DramcWriteLeveling(PI) begin...
6698 08:06:24.137631 ==
6699 08:06:24.140409 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 08:06:24.143919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 08:06:24.144488 ==
6702 08:06:24.147217 Write leveling (Byte 0): 40 => 8
6703 08:06:24.150760 Write leveling (Byte 1): 40 => 8
6704 08:06:24.153717 DramcWriteLeveling(PI) end<-----
6705 08:06:24.154275
6706 08:06:24.154644 ==
6707 08:06:24.156357 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 08:06:24.160098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 08:06:24.160662 ==
6710 08:06:24.162939 [Gating] SW mode calibration
6711 08:06:24.170183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6712 08:06:24.176679 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6713 08:06:24.180194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 08:06:24.187314 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 08:06:24.190153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 08:06:24.192934 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 08:06:24.199508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 08:06:24.203013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 08:06:24.206510 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 08:06:24.212892 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 08:06:24.216078 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 08:06:24.218927 Total UI for P1: 0, mck2ui 16
6723 08:06:24.222384 best dqsien dly found for B0: ( 0, 14, 24)
6724 08:06:24.226415 Total UI for P1: 0, mck2ui 16
6725 08:06:24.230501 best dqsien dly found for B1: ( 0, 14, 24)
6726 08:06:24.232372 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6727 08:06:24.236258 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6728 08:06:24.236814
6729 08:06:24.239535 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 08:06:24.242626 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 08:06:24.246386 [Gating] SW calibration Done
6732 08:06:24.247231 ==
6733 08:06:24.249907 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 08:06:24.252425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 08:06:24.255458 ==
6736 08:06:24.256095 RX Vref Scan: 0
6737 08:06:24.256580
6738 08:06:24.258957 RX Vref 0 -> 0, step: 1
6739 08:06:24.259532
6740 08:06:24.262063 RX Delay -410 -> 252, step: 16
6741 08:06:24.265640 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6742 08:06:24.269226 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6743 08:06:24.272401 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6744 08:06:24.278846 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6745 08:06:24.282491 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6746 08:06:24.285352 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6747 08:06:24.288714 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6748 08:06:24.295343 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6749 08:06:24.298677 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6750 08:06:24.302469 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6751 08:06:24.306131 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6752 08:06:24.311927 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6753 08:06:24.315647 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6754 08:06:24.318355 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6755 08:06:24.325594 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6756 08:06:24.328631 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6757 08:06:24.329093 ==
6758 08:06:24.332372 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 08:06:24.335095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 08:06:24.335654 ==
6761 08:06:24.338434 DQS Delay:
6762 08:06:24.338987 DQS0 = 43, DQS1 = 51
6763 08:06:24.339349 DQM Delay:
6764 08:06:24.341753 DQM0 = 12, DQM1 = 14
6765 08:06:24.342309 DQ Delay:
6766 08:06:24.344823 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6767 08:06:24.349113 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6768 08:06:24.351830 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6769 08:06:24.355146 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6770 08:06:24.355696
6771 08:06:24.356119
6772 08:06:24.356459 ==
6773 08:06:24.358345 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 08:06:24.361400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 08:06:24.361863 ==
6776 08:06:24.362228
6777 08:06:24.365020
6778 08:06:24.365576 TX Vref Scan disable
6779 08:06:24.368349 == TX Byte 0 ==
6780 08:06:24.371549 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 08:06:24.374850 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 08:06:24.378016 == TX Byte 1 ==
6783 08:06:24.381496 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 08:06:24.385605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 08:06:24.386168 ==
6786 08:06:24.387918 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 08:06:24.391429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 08:06:24.394443 ==
6789 08:06:24.394995
6790 08:06:24.395351
6791 08:06:24.395683 TX Vref Scan disable
6792 08:06:24.398333 == TX Byte 0 ==
6793 08:06:24.401136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 08:06:24.404344 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 08:06:24.407880 == TX Byte 1 ==
6796 08:06:24.411221 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 08:06:24.414655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 08:06:24.415224
6799 08:06:24.417602 [DATLAT]
6800 08:06:24.418071 Freq=400, CH1 RK0
6801 08:06:24.418553
6802 08:06:24.421130 DATLAT Default: 0xf
6803 08:06:24.421706 0, 0xFFFF, sum = 0
6804 08:06:24.424213 1, 0xFFFF, sum = 0
6805 08:06:24.424695 2, 0xFFFF, sum = 0
6806 08:06:24.427924 3, 0xFFFF, sum = 0
6807 08:06:24.428516 4, 0xFFFF, sum = 0
6808 08:06:24.430839 5, 0xFFFF, sum = 0
6809 08:06:24.431416 6, 0xFFFF, sum = 0
6810 08:06:24.434286 7, 0xFFFF, sum = 0
6811 08:06:24.434864 8, 0xFFFF, sum = 0
6812 08:06:24.437097 9, 0xFFFF, sum = 0
6813 08:06:24.440966 10, 0xFFFF, sum = 0
6814 08:06:24.441543 11, 0xFFFF, sum = 0
6815 08:06:24.444485 12, 0xFFFF, sum = 0
6816 08:06:24.445065 13, 0x0, sum = 1
6817 08:06:24.447106 14, 0x0, sum = 2
6818 08:06:24.447674 15, 0x0, sum = 3
6819 08:06:24.448168 16, 0x0, sum = 4
6820 08:06:24.450569 best_step = 14
6821 08:06:24.451119
6822 08:06:24.451484 ==
6823 08:06:24.453723 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 08:06:24.456871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 08:06:24.457432 ==
6826 08:06:24.460748 RX Vref Scan: 1
6827 08:06:24.461304
6828 08:06:24.464044 RX Vref 0 -> 0, step: 1
6829 08:06:24.464501
6830 08:06:24.464860 RX Delay -343 -> 252, step: 8
6831 08:06:24.465199
6832 08:06:24.467147 Set Vref, RX VrefLevel [Byte0]: 50
6833 08:06:24.470307 [Byte1]: 52
6834 08:06:24.476386
6835 08:06:24.476953 Final RX Vref Byte 0 = 50 to rank0
6836 08:06:24.478653 Final RX Vref Byte 1 = 52 to rank0
6837 08:06:24.482345 Final RX Vref Byte 0 = 50 to rank1
6838 08:06:24.485615 Final RX Vref Byte 1 = 52 to rank1==
6839 08:06:24.488854 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 08:06:24.495929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 08:06:24.496492 ==
6842 08:06:24.496861 DQS Delay:
6843 08:06:24.498400 DQS0 = 44, DQS1 = 56
6844 08:06:24.498857 DQM Delay:
6845 08:06:24.499217 DQM0 = 8, DQM1 = 13
6846 08:06:24.502188 DQ Delay:
6847 08:06:24.505713 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6848 08:06:24.506173 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6849 08:06:24.508456 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6850 08:06:24.512952 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6851 08:06:24.513511
6852 08:06:24.514889
6853 08:06:24.522037 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6854 08:06:24.525540 CH1 RK0: MR19=C0C, MR18=9D73
6855 08:06:24.531705 CH1_RK0: MR19=0xC0C, MR18=0x9D73, DQSOSC=390, MR23=63, INC=388, DEC=258
6856 08:06:24.532349 ==
6857 08:06:24.536117 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 08:06:24.538276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 08:06:24.538850 ==
6860 08:06:24.541789 [Gating] SW mode calibration
6861 08:06:24.548209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6862 08:06:24.555098 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6863 08:06:24.558298 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 08:06:24.561497 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 08:06:24.567971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 08:06:24.571932 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 08:06:24.574597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 08:06:24.581116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 08:06:24.584357 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 08:06:24.587961 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 08:06:24.594437 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 08:06:24.595164 Total UI for P1: 0, mck2ui 16
6873 08:06:24.600810 best dqsien dly found for B0: ( 0, 14, 24)
6874 08:06:24.601360 Total UI for P1: 0, mck2ui 16
6875 08:06:24.607235 best dqsien dly found for B1: ( 0, 14, 24)
6876 08:06:24.610273 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6877 08:06:24.613574 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6878 08:06:24.614028
6879 08:06:24.617372 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 08:06:24.621215 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 08:06:24.623760 [Gating] SW calibration Done
6882 08:06:24.624322 ==
6883 08:06:24.627086 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 08:06:24.630220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 08:06:24.630780 ==
6886 08:06:24.633597 RX Vref Scan: 0
6887 08:06:24.634155
6888 08:06:24.637029 RX Vref 0 -> 0, step: 1
6889 08:06:24.637584
6890 08:06:24.637945 RX Delay -410 -> 252, step: 16
6891 08:06:24.643618 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6892 08:06:24.647208 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6893 08:06:24.649993 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6894 08:06:24.653527 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6895 08:06:24.660214 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6896 08:06:24.663536 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6897 08:06:24.666913 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6898 08:06:24.670199 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6899 08:06:24.677139 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6900 08:06:24.680629 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6901 08:06:24.683424 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6902 08:06:24.689771 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6903 08:06:24.693161 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6904 08:06:24.696325 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6905 08:06:24.700168 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6906 08:06:24.706332 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6907 08:06:24.706891 ==
6908 08:06:24.709622 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 08:06:24.713065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 08:06:24.713644 ==
6911 08:06:24.714130 DQS Delay:
6912 08:06:24.716087 DQS0 = 51, DQS1 = 51
6913 08:06:24.716559 DQM Delay:
6914 08:06:24.719378 DQM0 = 19, DQM1 = 14
6915 08:06:24.719947 DQ Delay:
6916 08:06:24.723027 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6917 08:06:24.726119 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6918 08:06:24.729429 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6919 08:06:24.732507 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6920 08:06:24.733022
6921 08:06:24.733414
6922 08:06:24.733759 ==
6923 08:06:24.735885 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 08:06:24.739893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 08:06:24.740445 ==
6926 08:06:24.740813
6927 08:06:24.742653
6928 08:06:24.743106 TX Vref Scan disable
6929 08:06:24.746028 == TX Byte 0 ==
6930 08:06:24.749441 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6931 08:06:24.752934 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6932 08:06:24.755604 == TX Byte 1 ==
6933 08:06:24.759336 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6934 08:06:24.762861 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6935 08:06:24.763480 ==
6936 08:06:24.766165 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 08:06:24.769655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 08:06:24.772390 ==
6939 08:06:24.772949
6940 08:06:24.773311
6941 08:06:24.773645 TX Vref Scan disable
6942 08:06:24.776026 == TX Byte 0 ==
6943 08:06:24.779464 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6944 08:06:24.782392 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6945 08:06:24.785512 == TX Byte 1 ==
6946 08:06:24.788754 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6947 08:06:24.792583 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6948 08:06:24.793140
6949 08:06:24.795689 [DATLAT]
6950 08:06:24.796283 Freq=400, CH1 RK1
6951 08:06:24.796651
6952 08:06:24.799090 DATLAT Default: 0xe
6953 08:06:24.799663 0, 0xFFFF, sum = 0
6954 08:06:24.802417 1, 0xFFFF, sum = 0
6955 08:06:24.802997 2, 0xFFFF, sum = 0
6956 08:06:24.805278 3, 0xFFFF, sum = 0
6957 08:06:24.805862 4, 0xFFFF, sum = 0
6958 08:06:24.809062 5, 0xFFFF, sum = 0
6959 08:06:24.809644 6, 0xFFFF, sum = 0
6960 08:06:24.811868 7, 0xFFFF, sum = 0
6961 08:06:24.812369 8, 0xFFFF, sum = 0
6962 08:06:24.815306 9, 0xFFFF, sum = 0
6963 08:06:24.815885 10, 0xFFFF, sum = 0
6964 08:06:24.818700 11, 0xFFFF, sum = 0
6965 08:06:24.819165 12, 0xFFFF, sum = 0
6966 08:06:24.821756 13, 0x0, sum = 1
6967 08:06:24.822218 14, 0x0, sum = 2
6968 08:06:24.824940 15, 0x0, sum = 3
6969 08:06:24.825405 16, 0x0, sum = 4
6970 08:06:24.828645 best_step = 14
6971 08:06:24.829098
6972 08:06:24.829456 ==
6973 08:06:24.831664 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 08:06:24.835174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 08:06:24.835634 ==
6976 08:06:24.838667 RX Vref Scan: 0
6977 08:06:24.839119
6978 08:06:24.839479 RX Vref 0 -> 0, step: 1
6979 08:06:24.839879
6980 08:06:24.841667 RX Delay -343 -> 252, step: 8
6981 08:06:24.850055 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6982 08:06:24.853374 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6983 08:06:24.856503 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6984 08:06:24.863400 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6985 08:06:24.866593 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6986 08:06:24.869631 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6987 08:06:24.873039 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6988 08:06:24.876560 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6989 08:06:24.882969 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6990 08:06:24.886473 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6991 08:06:24.889837 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6992 08:06:24.896231 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6993 08:06:24.900149 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6994 08:06:24.902421 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6995 08:06:24.906795 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6996 08:06:24.912826 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
6997 08:06:24.913368 ==
6998 08:06:24.915848 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 08:06:24.919217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 08:06:24.919678 ==
7001 08:06:24.920122 DQS Delay:
7002 08:06:24.922712 DQS0 = 44, DQS1 = 56
7003 08:06:24.923265 DQM Delay:
7004 08:06:24.925841 DQM0 = 9, DQM1 = 11
7005 08:06:24.926299 DQ Delay:
7006 08:06:24.929189 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7007 08:06:24.932305 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
7008 08:06:24.935841 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7009 08:06:24.939222 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7010 08:06:24.939852
7011 08:06:24.940227
7012 08:06:24.945732 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7013 08:06:24.949171 CH1 RK1: MR19=C0C, MR18=6E5F
7014 08:06:24.955905 CH1_RK1: MR19=0xC0C, MR18=0x6E5F, DQSOSC=395, MR23=63, INC=378, DEC=252
7015 08:06:24.960319 [RxdqsGatingPostProcess] freq 400
7016 08:06:24.965612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7017 08:06:24.968779 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 08:06:24.969239 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 08:06:24.972241 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 08:06:24.975624 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 08:06:24.979422 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 08:06:24.982189 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 08:06:24.985355 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 08:06:24.988352 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 08:06:24.992122 Pre-setting of DQS Precalculation
7026 08:06:24.998609 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7027 08:06:25.005048 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7028 08:06:25.012485 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7029 08:06:25.013089
7030 08:06:25.013654
7031 08:06:25.014570 [Calibration Summary] 800 Mbps
7032 08:06:25.015023 CH 0, Rank 0
7033 08:06:25.018581 SW Impedance : PASS
7034 08:06:25.021633 DUTY Scan : NO K
7035 08:06:25.022109 ZQ Calibration : PASS
7036 08:06:25.024558 Jitter Meter : NO K
7037 08:06:25.028396 CBT Training : PASS
7038 08:06:25.028851 Write leveling : PASS
7039 08:06:25.031572 RX DQS gating : PASS
7040 08:06:25.034824 RX DQ/DQS(RDDQC) : PASS
7041 08:06:25.035381 TX DQ/DQS : PASS
7042 08:06:25.038231 RX DATLAT : PASS
7043 08:06:25.041364 RX DQ/DQS(Engine): PASS
7044 08:06:25.041822 TX OE : NO K
7045 08:06:25.042190 All Pass.
7046 08:06:25.045092
7047 08:06:25.045648 CH 0, Rank 1
7048 08:06:25.047962 SW Impedance : PASS
7049 08:06:25.048419 DUTY Scan : NO K
7050 08:06:25.051497 ZQ Calibration : PASS
7051 08:06:25.054484 Jitter Meter : NO K
7052 08:06:25.055039 CBT Training : PASS
7053 08:06:25.058403 Write leveling : NO K
7054 08:06:25.060948 RX DQS gating : PASS
7055 08:06:25.061408 RX DQ/DQS(RDDQC) : PASS
7056 08:06:25.064167 TX DQ/DQS : PASS
7057 08:06:25.064626 RX DATLAT : PASS
7058 08:06:25.067848 RX DQ/DQS(Engine): PASS
7059 08:06:25.071039 TX OE : NO K
7060 08:06:25.071611 All Pass.
7061 08:06:25.072067
7062 08:06:25.072411 CH 1, Rank 0
7063 08:06:25.074476 SW Impedance : PASS
7064 08:06:25.077612 DUTY Scan : NO K
7065 08:06:25.078169 ZQ Calibration : PASS
7066 08:06:25.081144 Jitter Meter : NO K
7067 08:06:25.084420 CBT Training : PASS
7068 08:06:25.084873 Write leveling : PASS
7069 08:06:25.087835 RX DQS gating : PASS
7070 08:06:25.090746 RX DQ/DQS(RDDQC) : PASS
7071 08:06:25.091303 TX DQ/DQS : PASS
7072 08:06:25.094899 RX DATLAT : PASS
7073 08:06:25.098010 RX DQ/DQS(Engine): PASS
7074 08:06:25.098570 TX OE : NO K
7075 08:06:25.100886 All Pass.
7076 08:06:25.101435
7077 08:06:25.101796 CH 1, Rank 1
7078 08:06:25.104271 SW Impedance : PASS
7079 08:06:25.104826 DUTY Scan : NO K
7080 08:06:25.108061 ZQ Calibration : PASS
7081 08:06:25.110861 Jitter Meter : NO K
7082 08:06:25.111420 CBT Training : PASS
7083 08:06:25.113484 Write leveling : NO K
7084 08:06:25.117139 RX DQS gating : PASS
7085 08:06:25.117598 RX DQ/DQS(RDDQC) : PASS
7086 08:06:25.121048 TX DQ/DQS : PASS
7087 08:06:25.123693 RX DATLAT : PASS
7088 08:06:25.124194 RX DQ/DQS(Engine): PASS
7089 08:06:25.126987 TX OE : NO K
7090 08:06:25.127539 All Pass.
7091 08:06:25.127967
7092 08:06:25.130416 DramC Write-DBI off
7093 08:06:25.134545 PER_BANK_REFRESH: Hybrid Mode
7094 08:06:25.135107 TX_TRACKING: ON
7095 08:06:25.143880 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7096 08:06:25.146885 [FAST_K] Save calibration result to emmc
7097 08:06:25.150093 dramc_set_vcore_voltage set vcore to 725000
7098 08:06:25.153349 Read voltage for 1600, 0
7099 08:06:25.153909 Vio18 = 0
7100 08:06:25.154273 Vcore = 725000
7101 08:06:25.156825 Vdram = 0
7102 08:06:25.157392 Vddq = 0
7103 08:06:25.157761 Vmddr = 0
7104 08:06:25.163577 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7105 08:06:25.167016 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7106 08:06:25.170449 MEM_TYPE=3, freq_sel=13
7107 08:06:25.173323 sv_algorithm_assistance_LP4_3733
7108 08:06:25.176331 ============ PULL DRAM RESETB DOWN ============
7109 08:06:25.183251 ========== PULL DRAM RESETB DOWN end =========
7110 08:06:25.186262 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7111 08:06:25.189480 ===================================
7112 08:06:25.192976 LPDDR4 DRAM CONFIGURATION
7113 08:06:25.196319 ===================================
7114 08:06:25.196876 EX_ROW_EN[0] = 0x0
7115 08:06:25.199525 EX_ROW_EN[1] = 0x0
7116 08:06:25.200137 LP4Y_EN = 0x0
7117 08:06:25.203144 WORK_FSP = 0x1
7118 08:06:25.203694 WL = 0x5
7119 08:06:25.206183 RL = 0x5
7120 08:06:25.206732 BL = 0x2
7121 08:06:25.209827 RPST = 0x0
7122 08:06:25.210387 RD_PRE = 0x0
7123 08:06:25.212641 WR_PRE = 0x1
7124 08:06:25.215926 WR_PST = 0x1
7125 08:06:25.216483 DBI_WR = 0x0
7126 08:06:25.219588 DBI_RD = 0x0
7127 08:06:25.220096 OTF = 0x1
7128 08:06:25.222322 ===================================
7129 08:06:25.225538 ===================================
7130 08:06:25.225995 ANA top config
7131 08:06:25.229532 ===================================
7132 08:06:25.232638 DLL_ASYNC_EN = 0
7133 08:06:25.235933 ALL_SLAVE_EN = 0
7134 08:06:25.239290 NEW_RANK_MODE = 1
7135 08:06:25.243103 DLL_IDLE_MODE = 1
7136 08:06:25.243656 LP45_APHY_COMB_EN = 1
7137 08:06:25.246160 TX_ODT_DIS = 0
7138 08:06:25.249028 NEW_8X_MODE = 1
7139 08:06:25.252448 ===================================
7140 08:06:25.256004 ===================================
7141 08:06:25.259326 data_rate = 3200
7142 08:06:25.262348 CKR = 1
7143 08:06:25.262932 DQ_P2S_RATIO = 8
7144 08:06:25.265596 ===================================
7145 08:06:25.269075 CA_P2S_RATIO = 8
7146 08:06:25.272105 DQ_CA_OPEN = 0
7147 08:06:25.275781 DQ_SEMI_OPEN = 0
7148 08:06:25.278831 CA_SEMI_OPEN = 0
7149 08:06:25.282318 CA_FULL_RATE = 0
7150 08:06:25.285551 DQ_CKDIV4_EN = 0
7151 08:06:25.286126 CA_CKDIV4_EN = 0
7152 08:06:25.288599 CA_PREDIV_EN = 0
7153 08:06:25.292055 PH8_DLY = 12
7154 08:06:25.295068 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7155 08:06:25.298298 DQ_AAMCK_DIV = 4
7156 08:06:25.301852 CA_AAMCK_DIV = 4
7157 08:06:25.302407 CA_ADMCK_DIV = 4
7158 08:06:25.305081 DQ_TRACK_CA_EN = 0
7159 08:06:25.308586 CA_PICK = 1600
7160 08:06:25.311982 CA_MCKIO = 1600
7161 08:06:25.315037 MCKIO_SEMI = 0
7162 08:06:25.318021 PLL_FREQ = 3068
7163 08:06:25.321196 DQ_UI_PI_RATIO = 32
7164 08:06:25.324720 CA_UI_PI_RATIO = 0
7165 08:06:25.328170 ===================================
7166 08:06:25.331263 ===================================
7167 08:06:25.331888 memory_type:LPDDR4
7168 08:06:25.334692 GP_NUM : 10
7169 08:06:25.337967 SRAM_EN : 1
7170 08:06:25.338524 MD32_EN : 0
7171 08:06:25.341202 ===================================
7172 08:06:25.344538 [ANA_INIT] >>>>>>>>>>>>>>
7173 08:06:25.348508 <<<<<< [CONFIGURE PHASE]: ANA_TX
7174 08:06:25.350985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7175 08:06:25.354666 ===================================
7176 08:06:25.358211 data_rate = 3200,PCW = 0X7600
7177 08:06:25.361206 ===================================
7178 08:06:25.364543 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7179 08:06:25.368163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 08:06:25.375037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 08:06:25.378165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7182 08:06:25.381220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7183 08:06:25.384337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7184 08:06:25.388438 [ANA_INIT] flow start
7185 08:06:25.391094 [ANA_INIT] PLL >>>>>>>>
7186 08:06:25.391645 [ANA_INIT] PLL <<<<<<<<
7187 08:06:25.394107 [ANA_INIT] MIDPI >>>>>>>>
7188 08:06:25.397642 [ANA_INIT] MIDPI <<<<<<<<
7189 08:06:25.398202 [ANA_INIT] DLL >>>>>>>>
7190 08:06:25.400922 [ANA_INIT] DLL <<<<<<<<
7191 08:06:25.404559 [ANA_INIT] flow end
7192 08:06:25.407654 ============ LP4 DIFF to SE enter ============
7193 08:06:25.410689 ============ LP4 DIFF to SE exit ============
7194 08:06:25.414497 [ANA_INIT] <<<<<<<<<<<<<
7195 08:06:25.417386 [Flow] Enable top DCM control >>>>>
7196 08:06:25.420507 [Flow] Enable top DCM control <<<<<
7197 08:06:25.424206 Enable DLL master slave shuffle
7198 08:06:25.427496 ==============================================================
7199 08:06:25.430997 Gating Mode config
7200 08:06:25.438110 ==============================================================
7201 08:06:25.438677 Config description:
7202 08:06:25.447677 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7203 08:06:25.453996 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7204 08:06:25.460299 SELPH_MODE 0: By rank 1: By Phase
7205 08:06:25.464109 ==============================================================
7206 08:06:25.467491 GAT_TRACK_EN = 1
7207 08:06:25.470555 RX_GATING_MODE = 2
7208 08:06:25.473876 RX_GATING_TRACK_MODE = 2
7209 08:06:25.477183 SELPH_MODE = 1
7210 08:06:25.480422 PICG_EARLY_EN = 1
7211 08:06:25.483575 VALID_LAT_VALUE = 1
7212 08:06:25.487414 ==============================================================
7213 08:06:25.490346 Enter into Gating configuration >>>>
7214 08:06:25.493408 Exit from Gating configuration <<<<
7215 08:06:25.496996 Enter into DVFS_PRE_config >>>>>
7216 08:06:25.509855 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7217 08:06:25.513483 Exit from DVFS_PRE_config <<<<<
7218 08:06:25.517386 Enter into PICG configuration >>>>
7219 08:06:25.519627 Exit from PICG configuration <<<<
7220 08:06:25.520120 [RX_INPUT] configuration >>>>>
7221 08:06:25.523073 [RX_INPUT] configuration <<<<<
7222 08:06:25.529930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7223 08:06:25.536081 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7224 08:06:25.539276 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 08:06:25.545953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 08:06:25.552385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 08:06:25.559548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 08:06:25.563167 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7229 08:06:25.566387 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7230 08:06:25.572792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7231 08:06:25.575931 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7232 08:06:25.579116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7233 08:06:25.585702 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 08:06:25.589485 ===================================
7235 08:06:25.590046 LPDDR4 DRAM CONFIGURATION
7236 08:06:25.592274 ===================================
7237 08:06:25.596070 EX_ROW_EN[0] = 0x0
7238 08:06:25.599524 EX_ROW_EN[1] = 0x0
7239 08:06:25.600115 LP4Y_EN = 0x0
7240 08:06:25.602086 WORK_FSP = 0x1
7241 08:06:25.602653 WL = 0x5
7242 08:06:25.605964 RL = 0x5
7243 08:06:25.606518 BL = 0x2
7244 08:06:25.608491 RPST = 0x0
7245 08:06:25.608947 RD_PRE = 0x0
7246 08:06:25.612430 WR_PRE = 0x1
7247 08:06:25.612979 WR_PST = 0x1
7248 08:06:25.615608 DBI_WR = 0x0
7249 08:06:25.616172 DBI_RD = 0x0
7250 08:06:25.618374 OTF = 0x1
7251 08:06:25.622048 ===================================
7252 08:06:25.625410 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7253 08:06:25.628398 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7254 08:06:25.635109 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 08:06:25.638622 ===================================
7256 08:06:25.639180 LPDDR4 DRAM CONFIGURATION
7257 08:06:25.641620 ===================================
7258 08:06:25.645041 EX_ROW_EN[0] = 0x10
7259 08:06:25.648348 EX_ROW_EN[1] = 0x0
7260 08:06:25.648803 LP4Y_EN = 0x0
7261 08:06:25.651609 WORK_FSP = 0x1
7262 08:06:25.652121 WL = 0x5
7263 08:06:25.654736 RL = 0x5
7264 08:06:25.655281 BL = 0x2
7265 08:06:25.658446 RPST = 0x0
7266 08:06:25.659014 RD_PRE = 0x0
7267 08:06:25.661752 WR_PRE = 0x1
7268 08:06:25.662307 WR_PST = 0x1
7269 08:06:25.664680 DBI_WR = 0x0
7270 08:06:25.665135 DBI_RD = 0x0
7271 08:06:25.668720 OTF = 0x1
7272 08:06:25.671523 ===================================
7273 08:06:25.678330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7274 08:06:25.678890 ==
7275 08:06:25.682128 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 08:06:25.684469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 08:06:25.684929 ==
7278 08:06:25.687702 [Duty_Offset_Calibration]
7279 08:06:25.688206 B0:1 B1:-1 CA:0
7280 08:06:25.688569
7281 08:06:25.691870 [DutyScan_Calibration_Flow] k_type=0
7282 08:06:25.701763
7283 08:06:25.702313 ==CLK 0==
7284 08:06:25.705593 Final CLK duty delay cell = 0
7285 08:06:25.709390 [0] MAX Duty = 5125%(X100), DQS PI = 20
7286 08:06:25.712190 [0] MIN Duty = 4907%(X100), DQS PI = 6
7287 08:06:25.712781 [0] AVG Duty = 5016%(X100)
7288 08:06:25.715193
7289 08:06:25.718411 CH0 CLK Duty spec in!! Max-Min= 218%
7290 08:06:25.721754 [DutyScan_Calibration_Flow] ====Done====
7291 08:06:25.722210
7292 08:06:25.725081 [DutyScan_Calibration_Flow] k_type=1
7293 08:06:25.741143
7294 08:06:25.741697 ==DQS 0 ==
7295 08:06:25.744379 Final DQS duty delay cell = -4
7296 08:06:25.747702 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7297 08:06:25.750938 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7298 08:06:25.753855 [-4] AVG Duty = 4922%(X100)
7299 08:06:25.754313
7300 08:06:25.754672 ==DQS 1 ==
7301 08:06:25.758083 Final DQS duty delay cell = 0
7302 08:06:25.760475 [0] MAX Duty = 5187%(X100), DQS PI = 4
7303 08:06:25.763932 [0] MIN Duty = 5031%(X100), DQS PI = 18
7304 08:06:25.767841 [0] AVG Duty = 5109%(X100)
7305 08:06:25.768303
7306 08:06:25.770881 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7307 08:06:25.771362
7308 08:06:25.774239 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7309 08:06:25.777342 [DutyScan_Calibration_Flow] ====Done====
7310 08:06:25.778009
7311 08:06:25.780372 [DutyScan_Calibration_Flow] k_type=3
7312 08:06:25.798960
7313 08:06:25.799473 ==DQM 0 ==
7314 08:06:25.802431 Final DQM duty delay cell = 0
7315 08:06:25.805198 [0] MAX Duty = 5124%(X100), DQS PI = 18
7316 08:06:25.808189 [0] MIN Duty = 4907%(X100), DQS PI = 8
7317 08:06:25.811534 [0] AVG Duty = 5015%(X100)
7318 08:06:25.811976
7319 08:06:25.812302 ==DQM 1 ==
7320 08:06:25.815308 Final DQM duty delay cell = 0
7321 08:06:25.817946 [0] MAX Duty = 5031%(X100), DQS PI = 52
7322 08:06:25.821356 [0] MIN Duty = 4813%(X100), DQS PI = 20
7323 08:06:25.824893 [0] AVG Duty = 4922%(X100)
7324 08:06:25.825373
7325 08:06:25.828041 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7326 08:06:25.828450
7327 08:06:25.831349 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7328 08:06:25.834708 [DutyScan_Calibration_Flow] ====Done====
7329 08:06:25.835259
7330 08:06:25.837928 [DutyScan_Calibration_Flow] k_type=2
7331 08:06:25.855012
7332 08:06:25.855565 ==DQ 0 ==
7333 08:06:25.858033 Final DQ duty delay cell = -4
7334 08:06:25.861388 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7335 08:06:25.865179 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7336 08:06:25.868585 [-4] AVG Duty = 4953%(X100)
7337 08:06:25.869040
7338 08:06:25.869397 ==DQ 1 ==
7339 08:06:25.871005 Final DQ duty delay cell = 0
7340 08:06:25.874620 [0] MAX Duty = 5125%(X100), DQS PI = 48
7341 08:06:25.878048 [0] MIN Duty = 5000%(X100), DQS PI = 38
7342 08:06:25.881218 [0] AVG Duty = 5062%(X100)
7343 08:06:25.881773
7344 08:06:25.884354 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7345 08:06:25.884805
7346 08:06:25.887963 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7347 08:06:25.890934 [DutyScan_Calibration_Flow] ====Done====
7348 08:06:25.891384 ==
7349 08:06:25.894763 Dram Type= 6, Freq= 0, CH_1, rank 0
7350 08:06:25.897922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 08:06:25.898485 ==
7352 08:06:25.901452 [Duty_Offset_Calibration]
7353 08:06:25.902053 B0:-1 B1:1 CA:2
7354 08:06:25.904097
7355 08:06:25.907483 [DutyScan_Calibration_Flow] k_type=0
7356 08:06:25.915544
7357 08:06:25.916157 ==CLK 0==
7358 08:06:25.919211 Final CLK duty delay cell = 0
7359 08:06:25.922017 [0] MAX Duty = 5187%(X100), DQS PI = 22
7360 08:06:25.925235 [0] MIN Duty = 4969%(X100), DQS PI = 0
7361 08:06:25.929157 [0] AVG Duty = 5078%(X100)
7362 08:06:25.929614
7363 08:06:25.931692 CH1 CLK Duty spec in!! Max-Min= 218%
7364 08:06:25.936969 [DutyScan_Calibration_Flow] ====Done====
7365 08:06:25.937529
7366 08:06:25.938289 [DutyScan_Calibration_Flow] k_type=1
7367 08:06:25.955467
7368 08:06:25.956048 ==DQS 0 ==
7369 08:06:25.958684 Final DQS duty delay cell = 0
7370 08:06:25.962437 [0] MAX Duty = 5124%(X100), DQS PI = 18
7371 08:06:25.964881 [0] MIN Duty = 4907%(X100), DQS PI = 8
7372 08:06:25.968104 [0] AVG Duty = 5015%(X100)
7373 08:06:25.968558
7374 08:06:25.968916 ==DQS 1 ==
7375 08:06:25.971775 Final DQS duty delay cell = 0
7376 08:06:25.974795 [0] MAX Duty = 5093%(X100), DQS PI = 24
7377 08:06:25.978265 [0] MIN Duty = 4969%(X100), DQS PI = 56
7378 08:06:25.981679 [0] AVG Duty = 5031%(X100)
7379 08:06:25.982236
7380 08:06:25.984525 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7381 08:06:25.984984
7382 08:06:25.988406 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7383 08:06:25.991262 [DutyScan_Calibration_Flow] ====Done====
7384 08:06:25.991857
7385 08:06:25.994202 [DutyScan_Calibration_Flow] k_type=3
7386 08:06:26.012374
7387 08:06:26.012930 ==DQM 0 ==
7388 08:06:26.015054 Final DQM duty delay cell = 0
7389 08:06:26.018225 [0] MAX Duty = 5218%(X100), DQS PI = 18
7390 08:06:26.021514 [0] MIN Duty = 5031%(X100), DQS PI = 8
7391 08:06:26.025286 [0] AVG Duty = 5124%(X100)
7392 08:06:26.025845
7393 08:06:26.026209 ==DQM 1 ==
7394 08:06:26.028348 Final DQM duty delay cell = 0
7395 08:06:26.031853 [0] MAX Duty = 5156%(X100), DQS PI = 6
7396 08:06:26.035307 [0] MIN Duty = 4969%(X100), DQS PI = 34
7397 08:06:26.038831 [0] AVG Duty = 5062%(X100)
7398 08:06:26.039383
7399 08:06:26.041928 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7400 08:06:26.042483
7401 08:06:26.044979 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7402 08:06:26.048763 [DutyScan_Calibration_Flow] ====Done====
7403 08:06:26.049263
7404 08:06:26.052461 [DutyScan_Calibration_Flow] k_type=2
7405 08:06:26.068794
7406 08:06:26.069343 ==DQ 0 ==
7407 08:06:26.072078 Final DQ duty delay cell = 0
7408 08:06:26.075539 [0] MAX Duty = 5156%(X100), DQS PI = 30
7409 08:06:26.078644 [0] MIN Duty = 4906%(X100), DQS PI = 10
7410 08:06:26.079199 [0] AVG Duty = 5031%(X100)
7411 08:06:26.082021
7412 08:06:26.082590 ==DQ 1 ==
7413 08:06:26.085283 Final DQ duty delay cell = 0
7414 08:06:26.088651 [0] MAX Duty = 5156%(X100), DQS PI = 10
7415 08:06:26.092025 [0] MIN Duty = 4969%(X100), DQS PI = 56
7416 08:06:26.092582 [0] AVG Duty = 5062%(X100)
7417 08:06:26.095155
7418 08:06:26.098302 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7419 08:06:26.098857
7420 08:06:26.101786 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7421 08:06:26.104922 [DutyScan_Calibration_Flow] ====Done====
7422 08:06:26.108199 nWR fixed to 30
7423 08:06:26.111674 [ModeRegInit_LP4] CH0 RK0
7424 08:06:26.112275 [ModeRegInit_LP4] CH0 RK1
7425 08:06:26.114858 [ModeRegInit_LP4] CH1 RK0
7426 08:06:26.118383 [ModeRegInit_LP4] CH1 RK1
7427 08:06:26.118835 match AC timing 5
7428 08:06:26.125020 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7429 08:06:26.127691 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7430 08:06:26.132028 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7431 08:06:26.137956 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7432 08:06:26.141146 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7433 08:06:26.141602 [MiockJmeterHQA]
7434 08:06:26.141964
7435 08:06:26.144960 [DramcMiockJmeter] u1RxGatingPI = 0
7436 08:06:26.148910 0 : 4363, 4137
7437 08:06:26.149536 4 : 4252, 4027
7438 08:06:26.150870 8 : 4363, 4137
7439 08:06:26.151333 12 : 4258, 4030
7440 08:06:26.154344 16 : 4363, 4137
7441 08:06:26.154808 20 : 4363, 4137
7442 08:06:26.155178 24 : 4361, 4137
7443 08:06:26.157526 28 : 4252, 4027
7444 08:06:26.158007 32 : 4252, 4029
7445 08:06:26.161967 36 : 4253, 4029
7446 08:06:26.162530 40 : 4366, 4140
7447 08:06:26.164599 44 : 4363, 4139
7448 08:06:26.165080 48 : 4360, 4138
7449 08:06:26.167536 52 : 4255, 4029
7450 08:06:26.168058 56 : 4253, 4029
7451 08:06:26.168426 60 : 4250, 4027
7452 08:06:26.170661 64 : 4250, 4026
7453 08:06:26.171234 68 : 4366, 4140
7454 08:06:26.174234 72 : 4250, 4027
7455 08:06:26.174700 76 : 4250, 4026
7456 08:06:26.177416 80 : 4252, 4029
7457 08:06:26.177878 84 : 4252, 4029
7458 08:06:26.180565 88 : 4253, 4029
7459 08:06:26.181028 92 : 4361, 785
7460 08:06:26.181395 96 : 4250, 0
7461 08:06:26.185235 100 : 4250, 0
7462 08:06:26.185805 104 : 4363, 0
7463 08:06:26.187569 108 : 4360, 0
7464 08:06:26.188075 112 : 4363, 0
7465 08:06:26.188446 116 : 4250, 0
7466 08:06:26.190720 120 : 4250, 0
7467 08:06:26.191183 124 : 4250, 0
7468 08:06:26.191821 128 : 4250, 0
7469 08:06:26.194343 132 : 4250, 0
7470 08:06:26.194856 136 : 4250, 0
7471 08:06:26.197350 140 : 4253, 0
7472 08:06:26.197813 144 : 4251, 0
7473 08:06:26.198189 148 : 4250, 0
7474 08:06:26.200160 152 : 4255, 0
7475 08:06:26.200579 156 : 4360, 0
7476 08:06:26.203988 160 : 4250, 0
7477 08:06:26.204510 164 : 4361, 0
7478 08:06:26.204850 168 : 4250, 0
7479 08:06:26.206929 172 : 4249, 0
7480 08:06:26.207453 176 : 4250, 0
7481 08:06:26.210238 180 : 4250, 0
7482 08:06:26.210656 184 : 4250, 0
7483 08:06:26.210991 188 : 4361, 0
7484 08:06:26.213358 192 : 4250, 0
7485 08:06:26.213778 196 : 4251, 0
7486 08:06:26.217674 200 : 4250, 0
7487 08:06:26.218221 204 : 4255, 0
7488 08:06:26.218563 208 : 4360, 0
7489 08:06:26.220317 212 : 4250, 0
7490 08:06:26.220740 216 : 4361, 0
7491 08:06:26.223855 220 : 4250, 0
7492 08:06:26.224274 224 : 4250, 238
7493 08:06:26.224612 228 : 4253, 3461
7494 08:06:26.226588 232 : 4360, 4137
7495 08:06:26.227005 236 : 4250, 4027
7496 08:06:26.230201 240 : 4250, 4027
7497 08:06:26.230616 244 : 4250, 4026
7498 08:06:26.233289 248 : 4363, 4140
7499 08:06:26.233707 252 : 4250, 4027
7500 08:06:26.237166 256 : 4250, 4027
7501 08:06:26.237687 260 : 4363, 4140
7502 08:06:26.240279 264 : 4250, 4027
7503 08:06:26.240696 268 : 4250, 4027
7504 08:06:26.243241 272 : 4360, 4138
7505 08:06:26.243659 276 : 4361, 4138
7506 08:06:26.246449 280 : 4250, 4027
7507 08:06:26.246866 284 : 4250, 4026
7508 08:06:26.247198 288 : 4250, 4027
7509 08:06:26.250103 292 : 4250, 4027
7510 08:06:26.250626 296 : 4250, 4026
7511 08:06:26.253430 300 : 4363, 4140
7512 08:06:26.253852 304 : 4250, 4027
7513 08:06:26.256455 308 : 4252, 4027
7514 08:06:26.256873 312 : 4363, 4140
7515 08:06:26.260732 316 : 4250, 4026
7516 08:06:26.261254 320 : 4250, 4027
7517 08:06:26.264168 324 : 4360, 4138
7518 08:06:26.264586 328 : 4361, 4138
7519 08:06:26.267056 332 : 4250, 4027
7520 08:06:26.267583 336 : 4361, 3898
7521 08:06:26.269917 340 : 4250, 2421
7522 08:06:26.270336 344 : 4250, 113
7523 08:06:26.270670
7524 08:06:26.273427 MIOCK jitter meter ch=0
7525 08:06:26.273942
7526 08:06:26.276797 1T = (344-92) = 252 dly cells
7527 08:06:26.280294 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7528 08:06:26.280735 ==
7529 08:06:26.283221 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 08:06:26.290531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 08:06:26.291049 ==
7532 08:06:26.293340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 08:06:26.299453 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 08:06:26.302664 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 08:06:26.309350 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 08:06:26.317487 [CA 0] Center 43 (12~74) winsize 63
7537 08:06:26.320310 [CA 1] Center 43 (13~73) winsize 61
7538 08:06:26.323590 [CA 2] Center 38 (9~68) winsize 60
7539 08:06:26.327022 [CA 3] Center 38 (9~68) winsize 60
7540 08:06:26.330408 [CA 4] Center 36 (7~66) winsize 60
7541 08:06:26.334285 [CA 5] Center 36 (7~66) winsize 60
7542 08:06:26.334861
7543 08:06:26.337192 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7544 08:06:26.337752
7545 08:06:26.343478 [CATrainingPosCal] consider 1 rank data
7546 08:06:26.344060 u2DelayCellTimex100 = 258/100 ps
7547 08:06:26.350140 CA0 delay=43 (12~74),Diff = 7 PI (26 cell)
7548 08:06:26.353714 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7549 08:06:26.357393 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7550 08:06:26.359864 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7551 08:06:26.363654 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7552 08:06:26.366708 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7553 08:06:26.367259
7554 08:06:26.370288 CA PerBit enable=1, Macro0, CA PI delay=36
7555 08:06:26.370852
7556 08:06:26.373690 [CBTSetCACLKResult] CA Dly = 36
7557 08:06:26.377125 CS Dly: 11 (0~42)
7558 08:06:26.380267 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 08:06:26.383627 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 08:06:26.384255 ==
7561 08:06:26.386712 Dram Type= 6, Freq= 0, CH_0, rank 1
7562 08:06:26.393297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 08:06:26.393856 ==
7564 08:06:26.396509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7565 08:06:26.403816 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7566 08:06:26.406683 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7567 08:06:26.412909 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7568 08:06:26.420591 [CA 0] Center 43 (13~74) winsize 62
7569 08:06:26.424042 [CA 1] Center 44 (14~74) winsize 61
7570 08:06:26.427405 [CA 2] Center 38 (9~68) winsize 60
7571 08:06:26.430472 [CA 3] Center 38 (9~68) winsize 60
7572 08:06:26.434032 [CA 4] Center 36 (7~66) winsize 60
7573 08:06:26.437382 [CA 5] Center 36 (6~66) winsize 61
7574 08:06:26.437937
7575 08:06:26.440617 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7576 08:06:26.441098
7577 08:06:26.443434 [CATrainingPosCal] consider 2 rank data
7578 08:06:26.446867 u2DelayCellTimex100 = 258/100 ps
7579 08:06:26.453509 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7580 08:06:26.457183 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7581 08:06:26.460280 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7582 08:06:26.463552 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7583 08:06:26.466960 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7584 08:06:26.470412 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7585 08:06:26.470970
7586 08:06:26.473811 CA PerBit enable=1, Macro0, CA PI delay=36
7587 08:06:26.474364
7588 08:06:26.476432 [CBTSetCACLKResult] CA Dly = 36
7589 08:06:26.480251 CS Dly: 11 (0~43)
7590 08:06:26.483932 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7591 08:06:26.487114 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7592 08:06:26.487669
7593 08:06:26.490147 ----->DramcWriteLeveling(PI) begin...
7594 08:06:26.490709 ==
7595 08:06:26.493171 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 08:06:26.500146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 08:06:26.500704 ==
7598 08:06:26.503603 Write leveling (Byte 0): 35 => 35
7599 08:06:26.506540 Write leveling (Byte 1): 25 => 25
7600 08:06:26.507093 DramcWriteLeveling(PI) end<-----
7601 08:06:26.507459
7602 08:06:26.509948 ==
7603 08:06:26.512908 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 08:06:26.516674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 08:06:26.517237 ==
7606 08:06:26.519857 [Gating] SW mode calibration
7607 08:06:26.526018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7608 08:06:26.529518 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7609 08:06:26.536280 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 08:06:26.540008 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 08:06:26.544141 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 08:06:26.549693 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7613 08:06:26.552585 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7614 08:06:26.555896 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7615 08:06:26.562808 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 08:06:26.565875 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 08:06:26.569420 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 08:06:26.575834 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 08:06:26.579191 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7620 08:06:26.583177 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7621 08:06:26.588736 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7622 08:06:26.592557 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7623 08:06:26.595648 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7624 08:06:26.602669 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 08:06:26.605844 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 08:06:26.608678 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 08:06:26.615604 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 08:06:26.618868 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7629 08:06:26.621706 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7630 08:06:26.628319 1 6 20 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
7631 08:06:26.631915 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7632 08:06:26.635397 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 08:06:26.641857 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 08:06:26.645234 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 08:06:26.648439 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 08:06:26.655032 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 08:06:26.658602 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7638 08:06:26.661474 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 08:06:26.668054 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 08:06:26.671645 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 08:06:26.674682 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 08:06:26.681258 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 08:06:26.684509 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 08:06:26.688165 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 08:06:26.694966 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 08:06:26.698555 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 08:06:26.701507 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 08:06:26.707831 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 08:06:26.710943 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 08:06:26.714542 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 08:06:26.721667 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 08:06:26.723860 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 08:06:26.727914 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7654 08:06:26.730562 Total UI for P1: 0, mck2ui 16
7655 08:06:26.734400 best dqsien dly found for B0: ( 1, 9, 10)
7656 08:06:26.740460 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7657 08:06:26.743941 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 08:06:26.747281 Total UI for P1: 0, mck2ui 16
7659 08:06:26.750280 best dqsien dly found for B1: ( 1, 9, 18)
7660 08:06:26.753526 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7661 08:06:26.756998 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7662 08:06:26.757636
7663 08:06:26.760571 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7664 08:06:26.766805 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7665 08:06:26.767438 [Gating] SW calibration Done
7666 08:06:26.767858 ==
7667 08:06:26.770112 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 08:06:26.776747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 08:06:26.777311 ==
7670 08:06:26.777673 RX Vref Scan: 0
7671 08:06:26.778009
7672 08:06:26.780205 RX Vref 0 -> 0, step: 1
7673 08:06:26.780659
7674 08:06:26.783161 RX Delay 0 -> 252, step: 8
7675 08:06:26.786971 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7676 08:06:26.789906 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7677 08:06:26.793188 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7678 08:06:26.800018 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7679 08:06:26.803082 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7680 08:06:26.806551 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7681 08:06:26.810021 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7682 08:06:26.813378 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7683 08:06:26.816621 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7684 08:06:26.822845 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7685 08:06:26.826630 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7686 08:06:26.830209 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7687 08:06:26.833186 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7688 08:06:26.840072 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7689 08:06:26.842723 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7690 08:06:26.846555 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7691 08:06:26.847110 ==
7692 08:06:26.849624 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 08:06:26.852706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 08:06:26.853234 ==
7695 08:06:26.856428 DQS Delay:
7696 08:06:26.856881 DQS0 = 0, DQS1 = 0
7697 08:06:26.859513 DQM Delay:
7698 08:06:26.860101 DQM0 = 134, DQM1 = 126
7699 08:06:26.862769 DQ Delay:
7700 08:06:26.866516 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7701 08:06:26.870505 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
7702 08:06:26.873026 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7703 08:06:26.876113 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7704 08:06:26.876671
7705 08:06:26.877033
7706 08:06:26.877366 ==
7707 08:06:26.879343 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 08:06:26.883050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 08:06:26.883614 ==
7710 08:06:26.884024
7711 08:06:26.884367
7712 08:06:26.886235 TX Vref Scan disable
7713 08:06:26.889560 == TX Byte 0 ==
7714 08:06:26.892703 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7715 08:06:26.896283 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7716 08:06:26.899419 == TX Byte 1 ==
7717 08:06:26.902647 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7718 08:06:26.906393 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7719 08:06:26.906954 ==
7720 08:06:26.909219 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 08:06:26.915889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 08:06:26.916512 ==
7723 08:06:26.926897
7724 08:06:26.930236 TX Vref early break, caculate TX vref
7725 08:06:26.933933 TX Vref=16, minBit 5, minWin=22, winSum=371
7726 08:06:26.937095 TX Vref=18, minBit 10, minWin=22, winSum=377
7727 08:06:26.940121 TX Vref=20, minBit 7, minWin=23, winSum=391
7728 08:06:26.943340 TX Vref=22, minBit 1, minWin=24, winSum=402
7729 08:06:26.949813 TX Vref=24, minBit 0, minWin=25, winSum=408
7730 08:06:26.953111 TX Vref=26, minBit 6, minWin=25, winSum=417
7731 08:06:26.956339 TX Vref=28, minBit 0, minWin=24, winSum=411
7732 08:06:26.960374 TX Vref=30, minBit 0, minWin=24, winSum=409
7733 08:06:26.963138 TX Vref=32, minBit 7, minWin=23, winSum=394
7734 08:06:26.969901 [TxChooseVref] Worse bit 6, Min win 25, Win sum 417, Final Vref 26
7735 08:06:26.970449
7736 08:06:26.972899 Final TX Range 0 Vref 26
7737 08:06:26.973354
7738 08:06:26.973714 ==
7739 08:06:26.976440 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 08:06:26.979544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 08:06:26.980152 ==
7742 08:06:26.980521
7743 08:06:26.980855
7744 08:06:26.982775 TX Vref Scan disable
7745 08:06:26.989267 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7746 08:06:26.989843 == TX Byte 0 ==
7747 08:06:26.992882 u2DelayCellOfst[0]=15 cells (4 PI)
7748 08:06:26.996123 u2DelayCellOfst[1]=18 cells (5 PI)
7749 08:06:26.999527 u2DelayCellOfst[2]=15 cells (4 PI)
7750 08:06:27.002674 u2DelayCellOfst[3]=15 cells (4 PI)
7751 08:06:27.005762 u2DelayCellOfst[4]=11 cells (3 PI)
7752 08:06:27.009070 u2DelayCellOfst[5]=0 cells (0 PI)
7753 08:06:27.012056 u2DelayCellOfst[6]=22 cells (6 PI)
7754 08:06:27.015832 u2DelayCellOfst[7]=18 cells (5 PI)
7755 08:06:27.019148 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7756 08:06:27.022154 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7757 08:06:27.025153 == TX Byte 1 ==
7758 08:06:27.028630 u2DelayCellOfst[8]=0 cells (0 PI)
7759 08:06:27.032307 u2DelayCellOfst[9]=3 cells (1 PI)
7760 08:06:27.035530 u2DelayCellOfst[10]=7 cells (2 PI)
7761 08:06:27.036129 u2DelayCellOfst[11]=3 cells (1 PI)
7762 08:06:27.039075 u2DelayCellOfst[12]=11 cells (3 PI)
7763 08:06:27.042192 u2DelayCellOfst[13]=11 cells (3 PI)
7764 08:06:27.045879 u2DelayCellOfst[14]=15 cells (4 PI)
7765 08:06:27.049036 u2DelayCellOfst[15]=11 cells (3 PI)
7766 08:06:27.055647 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7767 08:06:27.058812 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7768 08:06:27.059364 DramC Write-DBI on
7769 08:06:27.059761 ==
7770 08:06:27.062051 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 08:06:27.068469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 08:06:27.069034 ==
7773 08:06:27.069431
7774 08:06:27.069836
7775 08:06:27.071447 TX Vref Scan disable
7776 08:06:27.071953 == TX Byte 0 ==
7777 08:06:27.078776 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7778 08:06:27.079331 == TX Byte 1 ==
7779 08:06:27.081911 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7780 08:06:27.084837 DramC Write-DBI off
7781 08:06:27.085391
7782 08:06:27.085753 [DATLAT]
7783 08:06:27.088175 Freq=1600, CH0 RK0
7784 08:06:27.088733
7785 08:06:27.089097 DATLAT Default: 0xf
7786 08:06:27.091647 0, 0xFFFF, sum = 0
7787 08:06:27.092256 1, 0xFFFF, sum = 0
7788 08:06:27.095516 2, 0xFFFF, sum = 0
7789 08:06:27.096126 3, 0xFFFF, sum = 0
7790 08:06:27.098202 4, 0xFFFF, sum = 0
7791 08:06:27.098767 5, 0xFFFF, sum = 0
7792 08:06:27.101214 6, 0xFFFF, sum = 0
7793 08:06:27.104472 7, 0xFFFF, sum = 0
7794 08:06:27.105035 8, 0xFFFF, sum = 0
7795 08:06:27.107624 9, 0xFFFF, sum = 0
7796 08:06:27.108122 10, 0xFFFF, sum = 0
7797 08:06:27.111190 11, 0xFFFF, sum = 0
7798 08:06:27.111789 12, 0xFFFF, sum = 0
7799 08:06:27.115255 13, 0xFFFF, sum = 0
7800 08:06:27.115857 14, 0x0, sum = 1
7801 08:06:27.118300 15, 0x0, sum = 2
7802 08:06:27.118862 16, 0x0, sum = 3
7803 08:06:27.120869 17, 0x0, sum = 4
7804 08:06:27.121369 best_step = 15
7805 08:06:27.121855
7806 08:06:27.122246 ==
7807 08:06:27.124903 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 08:06:27.127556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 08:06:27.131102 ==
7810 08:06:27.131654 RX Vref Scan: 1
7811 08:06:27.132084
7812 08:06:27.134043 Set Vref Range= 24 -> 127
7813 08:06:27.134496
7814 08:06:27.137941 RX Vref 24 -> 127, step: 1
7815 08:06:27.138498
7816 08:06:27.138861 RX Delay 11 -> 252, step: 4
7817 08:06:27.139195
7818 08:06:27.140888 Set Vref, RX VrefLevel [Byte0]: 24
7819 08:06:27.144204 [Byte1]: 24
7820 08:06:27.148348
7821 08:06:27.148904 Set Vref, RX VrefLevel [Byte0]: 25
7822 08:06:27.151018 [Byte1]: 25
7823 08:06:27.156259
7824 08:06:27.156814 Set Vref, RX VrefLevel [Byte0]: 26
7825 08:06:27.158769 [Byte1]: 26
7826 08:06:27.163158
7827 08:06:27.163718 Set Vref, RX VrefLevel [Byte0]: 27
7828 08:06:27.166733 [Byte1]: 27
7829 08:06:27.170571
7830 08:06:27.171022 Set Vref, RX VrefLevel [Byte0]: 28
7831 08:06:27.174691 [Byte1]: 28
7832 08:06:27.178639
7833 08:06:27.179194 Set Vref, RX VrefLevel [Byte0]: 29
7834 08:06:27.181641 [Byte1]: 29
7835 08:06:27.186138
7836 08:06:27.186704 Set Vref, RX VrefLevel [Byte0]: 30
7837 08:06:27.190694 [Byte1]: 30
7838 08:06:27.193609
7839 08:06:27.194166 Set Vref, RX VrefLevel [Byte0]: 31
7840 08:06:27.196773 [Byte1]: 31
7841 08:06:27.201202
7842 08:06:27.201757 Set Vref, RX VrefLevel [Byte0]: 32
7843 08:06:27.204666 [Byte1]: 32
7844 08:06:27.209589
7845 08:06:27.210144 Set Vref, RX VrefLevel [Byte0]: 33
7846 08:06:27.212094 [Byte1]: 33
7847 08:06:27.216652
7848 08:06:27.217211 Set Vref, RX VrefLevel [Byte0]: 34
7849 08:06:27.219702 [Byte1]: 34
7850 08:06:27.224302
7851 08:06:27.227652 Set Vref, RX VrefLevel [Byte0]: 35
7852 08:06:27.230848 [Byte1]: 35
7853 08:06:27.231306
7854 08:06:27.234016 Set Vref, RX VrefLevel [Byte0]: 36
7855 08:06:27.237886 [Byte1]: 36
7856 08:06:27.238443
7857 08:06:27.240497 Set Vref, RX VrefLevel [Byte0]: 37
7858 08:06:27.243622 [Byte1]: 37
7859 08:06:27.244144
7860 08:06:27.247383 Set Vref, RX VrefLevel [Byte0]: 38
7861 08:06:27.250168 [Byte1]: 38
7862 08:06:27.254833
7863 08:06:27.255390 Set Vref, RX VrefLevel [Byte0]: 39
7864 08:06:27.261161 [Byte1]: 39
7865 08:06:27.261723
7866 08:06:27.264359 Set Vref, RX VrefLevel [Byte0]: 40
7867 08:06:27.267832 [Byte1]: 40
7868 08:06:27.268400
7869 08:06:27.270959 Set Vref, RX VrefLevel [Byte0]: 41
7870 08:06:27.274176 [Byte1]: 41
7871 08:06:27.277678
7872 08:06:27.278259 Set Vref, RX VrefLevel [Byte0]: 42
7873 08:06:27.280904 [Byte1]: 42
7874 08:06:27.285396
7875 08:06:27.285981 Set Vref, RX VrefLevel [Byte0]: 43
7876 08:06:27.288034 [Byte1]: 43
7877 08:06:27.293163
7878 08:06:27.293735 Set Vref, RX VrefLevel [Byte0]: 44
7879 08:06:27.295931 [Byte1]: 44
7880 08:06:27.300452
7881 08:06:27.301024 Set Vref, RX VrefLevel [Byte0]: 45
7882 08:06:27.303641 [Byte1]: 45
7883 08:06:27.308633
7884 08:06:27.309259 Set Vref, RX VrefLevel [Byte0]: 46
7885 08:06:27.311524 [Byte1]: 46
7886 08:06:27.315488
7887 08:06:27.316114 Set Vref, RX VrefLevel [Byte0]: 47
7888 08:06:27.318850 [Byte1]: 47
7889 08:06:27.323493
7890 08:06:27.324139 Set Vref, RX VrefLevel [Byte0]: 48
7891 08:06:27.326510 [Byte1]: 48
7892 08:06:27.330682
7893 08:06:27.331449 Set Vref, RX VrefLevel [Byte0]: 49
7894 08:06:27.334597 [Byte1]: 49
7895 08:06:27.338886
7896 08:06:27.339481 Set Vref, RX VrefLevel [Byte0]: 50
7897 08:06:27.341568 [Byte1]: 50
7898 08:06:27.346654
7899 08:06:27.347229 Set Vref, RX VrefLevel [Byte0]: 51
7900 08:06:27.349738 [Byte1]: 51
7901 08:06:27.354009
7902 08:06:27.354581 Set Vref, RX VrefLevel [Byte0]: 52
7903 08:06:27.359718 [Byte1]: 52
7904 08:06:27.360241
7905 08:06:27.363339 Set Vref, RX VrefLevel [Byte0]: 53
7906 08:06:27.366983 [Byte1]: 53
7907 08:06:27.367547
7908 08:06:27.369783 Set Vref, RX VrefLevel [Byte0]: 54
7909 08:06:27.373153 [Byte1]: 54
7910 08:06:27.376034
7911 08:06:27.376489 Set Vref, RX VrefLevel [Byte0]: 55
7912 08:06:27.379685 [Byte1]: 55
7913 08:06:27.384497
7914 08:06:27.385068 Set Vref, RX VrefLevel [Byte0]: 56
7915 08:06:27.387320 [Byte1]: 56
7916 08:06:27.391505
7917 08:06:27.392120 Set Vref, RX VrefLevel [Byte0]: 57
7918 08:06:27.395208 [Byte1]: 57
7919 08:06:27.399204
7920 08:06:27.399809 Set Vref, RX VrefLevel [Byte0]: 58
7921 08:06:27.403068 [Byte1]: 58
7922 08:06:27.406767
7923 08:06:27.407333 Set Vref, RX VrefLevel [Byte0]: 59
7924 08:06:27.410467 [Byte1]: 59
7925 08:06:27.414907
7926 08:06:27.415475 Set Vref, RX VrefLevel [Byte0]: 60
7927 08:06:27.418209 [Byte1]: 60
7928 08:06:27.421944
7929 08:06:27.422516 Set Vref, RX VrefLevel [Byte0]: 61
7930 08:06:27.425658 [Byte1]: 61
7931 08:06:27.429479
7932 08:06:27.430056 Set Vref, RX VrefLevel [Byte0]: 62
7933 08:06:27.433489 [Byte1]: 62
7934 08:06:27.438053
7935 08:06:27.438637 Set Vref, RX VrefLevel [Byte0]: 63
7936 08:06:27.440764 [Byte1]: 63
7937 08:06:27.444901
7938 08:06:27.445493 Set Vref, RX VrefLevel [Byte0]: 64
7939 08:06:27.447989 [Byte1]: 64
7940 08:06:27.452303
7941 08:06:27.452773 Set Vref, RX VrefLevel [Byte0]: 65
7942 08:06:27.458616 [Byte1]: 65
7943 08:06:27.459161
7944 08:06:27.462493 Set Vref, RX VrefLevel [Byte0]: 66
7945 08:06:27.465166 [Byte1]: 66
7946 08:06:27.465624
7947 08:06:27.468716 Set Vref, RX VrefLevel [Byte0]: 67
7948 08:06:27.471763 [Byte1]: 67
7949 08:06:27.475193
7950 08:06:27.475781 Set Vref, RX VrefLevel [Byte0]: 68
7951 08:06:27.479188 [Byte1]: 68
7952 08:06:27.482894
7953 08:06:27.483448 Set Vref, RX VrefLevel [Byte0]: 69
7954 08:06:27.486190 [Byte1]: 69
7955 08:06:27.491249
7956 08:06:27.491844 Set Vref, RX VrefLevel [Byte0]: 70
7957 08:06:27.494110 [Byte1]: 70
7958 08:06:27.498056
7959 08:06:27.498530 Set Vref, RX VrefLevel [Byte0]: 71
7960 08:06:27.501404 [Byte1]: 71
7961 08:06:27.505850
7962 08:06:27.506424 Set Vref, RX VrefLevel [Byte0]: 72
7963 08:06:27.508682 [Byte1]: 72
7964 08:06:27.514015
7965 08:06:27.514588 Set Vref, RX VrefLevel [Byte0]: 73
7966 08:06:27.516515 [Byte1]: 73
7967 08:06:27.521100
7968 08:06:27.521678 Set Vref, RX VrefLevel [Byte0]: 74
7969 08:06:27.524120 [Byte1]: 74
7970 08:06:27.528822
7971 08:06:27.529293 Set Vref, RX VrefLevel [Byte0]: 75
7972 08:06:27.531988 [Byte1]: 75
7973 08:06:27.536468
7974 08:06:27.536945 Set Vref, RX VrefLevel [Byte0]: 76
7975 08:06:27.539690 [Byte1]: 76
7976 08:06:27.544264
7977 08:06:27.544824 Set Vref, RX VrefLevel [Byte0]: 77
7978 08:06:27.547640 [Byte1]: 77
7979 08:06:27.551820
7980 08:06:27.552379 Set Vref, RX VrefLevel [Byte0]: 78
7981 08:06:27.558342 [Byte1]: 78
7982 08:06:27.558911
7983 08:06:27.561028 Set Vref, RX VrefLevel [Byte0]: 79
7984 08:06:27.564785 [Byte1]: 79
7985 08:06:27.565347
7986 08:06:27.568151 Final RX Vref Byte 0 = 67 to rank0
7987 08:06:27.570900 Final RX Vref Byte 1 = 58 to rank0
7988 08:06:27.574239 Final RX Vref Byte 0 = 67 to rank1
7989 08:06:27.577888 Final RX Vref Byte 1 = 58 to rank1==
7990 08:06:27.581375 Dram Type= 6, Freq= 0, CH_0, rank 0
7991 08:06:27.584134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 08:06:27.584698 ==
7993 08:06:27.587480 DQS Delay:
7994 08:06:27.588102 DQS0 = 0, DQS1 = 0
7995 08:06:27.588477 DQM Delay:
7996 08:06:27.591630 DQM0 = 133, DQM1 = 123
7997 08:06:27.592243 DQ Delay:
7998 08:06:27.594110 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
7999 08:06:27.597870 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8000 08:06:27.604662 DQ8 =116, DQ9 =112, DQ10 =122, DQ11 =118
8001 08:06:27.607300 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =128
8002 08:06:27.607931
8003 08:06:27.608309
8004 08:06:27.608648
8005 08:06:27.610562 [DramC_TX_OE_Calibration] TA2
8006 08:06:27.614212 Original DQ_B0 (3 6) =30, OEN = 27
8007 08:06:27.617458 Original DQ_B1 (3 6) =30, OEN = 27
8008 08:06:27.618035 24, 0x0, End_B0=24 End_B1=24
8009 08:06:27.620485 25, 0x0, End_B0=25 End_B1=25
8010 08:06:27.623847 26, 0x0, End_B0=26 End_B1=26
8011 08:06:27.627414 27, 0x0, End_B0=27 End_B1=27
8012 08:06:27.628156 28, 0x0, End_B0=28 End_B1=28
8013 08:06:27.630781 29, 0x0, End_B0=29 End_B1=29
8014 08:06:27.633937 30, 0x0, End_B0=30 End_B1=30
8015 08:06:27.637410 31, 0x4141, End_B0=30 End_B1=30
8016 08:06:27.640238 Byte0 end_step=30 best_step=27
8017 08:06:27.644095 Byte1 end_step=30 best_step=27
8018 08:06:27.644649 Byte0 TX OE(2T, 0.5T) = (3, 3)
8019 08:06:27.646890 Byte1 TX OE(2T, 0.5T) = (3, 3)
8020 08:06:27.647443
8021 08:06:27.647866
8022 08:06:27.657459 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8023 08:06:27.660066 CH0 RK0: MR19=303, MR18=2112
8024 08:06:27.667051 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8025 08:06:27.667615
8026 08:06:27.670252 ----->DramcWriteLeveling(PI) begin...
8027 08:06:27.670811 ==
8028 08:06:27.673872 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 08:06:27.676922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 08:06:27.677480 ==
8031 08:06:27.679907 Write leveling (Byte 0): 34 => 34
8032 08:06:27.683846 Write leveling (Byte 1): 26 => 26
8033 08:06:27.686672 DramcWriteLeveling(PI) end<-----
8034 08:06:27.687222
8035 08:06:27.687588 ==
8036 08:06:27.689825 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 08:06:27.692942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 08:06:27.693502 ==
8039 08:06:27.696374 [Gating] SW mode calibration
8040 08:06:27.703339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8041 08:06:27.709806 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8042 08:06:27.712605 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 08:06:27.716237 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 08:06:27.723237 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 08:06:27.725952 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8046 08:06:27.729350 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8047 08:06:27.736477 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8048 08:06:27.739354 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 08:06:27.742897 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 08:06:27.749191 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 08:06:27.752706 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 08:06:27.756483 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 08:06:27.762419 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 0)
8054 08:06:27.765934 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8055 08:06:27.768753 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8056 08:06:27.775845 1 5 24 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
8057 08:06:27.778570 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 08:06:27.782970 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 08:06:27.789088 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 08:06:27.792387 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 08:06:27.795344 1 6 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8062 08:06:27.801896 1 6 16 | B1->B0 | 2928 4343 | 1 0 | (0 0) (0 0)
8063 08:06:27.805379 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
8064 08:06:27.808297 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 08:06:27.815242 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 08:06:27.818453 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 08:06:27.821058 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 08:06:27.828064 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8069 08:06:27.831068 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8070 08:06:27.834793 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8071 08:06:27.841196 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8072 08:06:27.844428 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 08:06:27.847476 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 08:06:27.854531 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 08:06:27.857602 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 08:06:27.860670 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 08:06:27.867837 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 08:06:27.872130 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 08:06:27.874334 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 08:06:27.881252 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 08:06:27.883918 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 08:06:27.887852 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 08:06:27.894567 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 08:06:27.897308 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 08:06:27.900320 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8086 08:06:27.904061 Total UI for P1: 0, mck2ui 16
8087 08:06:27.907284 best dqsien dly found for B0: ( 1, 9, 10)
8088 08:06:27.913972 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8089 08:06:27.917347 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 08:06:27.920630 Total UI for P1: 0, mck2ui 16
8091 08:06:27.923830 best dqsien dly found for B1: ( 1, 9, 16)
8092 08:06:27.927096 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8093 08:06:27.930007 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8094 08:06:27.930549
8095 08:06:27.933525 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8096 08:06:27.940376 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8097 08:06:27.940926 [Gating] SW calibration Done
8098 08:06:27.941290 ==
8099 08:06:27.943469 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 08:06:27.951002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 08:06:27.951586 ==
8102 08:06:27.952122 RX Vref Scan: 0
8103 08:06:27.952582
8104 08:06:27.953638 RX Vref 0 -> 0, step: 1
8105 08:06:27.954114
8106 08:06:27.956422 RX Delay 0 -> 252, step: 8
8107 08:06:27.959795 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8108 08:06:27.963071 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8109 08:06:27.966767 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8110 08:06:27.972876 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8111 08:06:27.976280 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8112 08:06:27.979963 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8113 08:06:27.982785 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8114 08:06:27.986395 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8115 08:06:27.992772 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8116 08:06:27.996200 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8117 08:06:27.999310 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8118 08:06:28.002546 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8119 08:06:28.009329 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8120 08:06:28.012535 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8121 08:06:28.015991 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8122 08:06:28.019806 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8123 08:06:28.020368 ==
8124 08:06:28.022512 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 08:06:28.028683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 08:06:28.029274 ==
8127 08:06:28.029887 DQS Delay:
8128 08:06:28.032056 DQS0 = 0, DQS1 = 0
8129 08:06:28.032534 DQM Delay:
8130 08:06:28.033014 DQM0 = 133, DQM1 = 128
8131 08:06:28.035918 DQ Delay:
8132 08:06:28.038928 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8133 08:06:28.042653 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8134 08:06:28.045683 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8135 08:06:28.048519 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8136 08:06:28.048995
8137 08:06:28.049472
8138 08:06:28.049923 ==
8139 08:06:28.051843 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 08:06:28.058174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 08:06:28.058761 ==
8142 08:06:28.059245
8143 08:06:28.059702
8144 08:06:28.060198 TX Vref Scan disable
8145 08:06:28.061514 == TX Byte 0 ==
8146 08:06:28.065151 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8147 08:06:28.071854 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8148 08:06:28.072481 == TX Byte 1 ==
8149 08:06:28.074915 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8150 08:06:28.081631 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8151 08:06:28.082200 ==
8152 08:06:28.085564 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 08:06:28.088518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 08:06:28.089103 ==
8155 08:06:28.101723
8156 08:06:28.104697 TX Vref early break, caculate TX vref
8157 08:06:28.108741 TX Vref=16, minBit 1, minWin=22, winSum=371
8158 08:06:28.111492 TX Vref=18, minBit 2, minWin=23, winSum=386
8159 08:06:28.115025 TX Vref=20, minBit 1, minWin=23, winSum=391
8160 08:06:28.118377 TX Vref=22, minBit 1, minWin=24, winSum=399
8161 08:06:28.121375 TX Vref=24, minBit 1, minWin=23, winSum=406
8162 08:06:28.128347 TX Vref=26, minBit 1, minWin=24, winSum=411
8163 08:06:28.131271 TX Vref=28, minBit 1, minWin=24, winSum=405
8164 08:06:28.134799 TX Vref=30, minBit 0, minWin=24, winSum=399
8165 08:06:28.137622 TX Vref=32, minBit 1, minWin=23, winSum=392
8166 08:06:28.140969 TX Vref=34, minBit 1, minWin=23, winSum=386
8167 08:06:28.147714 [TxChooseVref] Worse bit 1, Min win 24, Win sum 411, Final Vref 26
8168 08:06:28.148465
8169 08:06:28.151041 Final TX Range 0 Vref 26
8170 08:06:28.151612
8171 08:06:28.152150 ==
8172 08:06:28.154337 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 08:06:28.158743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 08:06:28.159221 ==
8175 08:06:28.159703
8176 08:06:28.160193
8177 08:06:28.160963 TX Vref Scan disable
8178 08:06:28.167666 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8179 08:06:28.168303 == TX Byte 0 ==
8180 08:06:28.170868 u2DelayCellOfst[0]=15 cells (4 PI)
8181 08:06:28.174466 u2DelayCellOfst[1]=18 cells (5 PI)
8182 08:06:28.177397 u2DelayCellOfst[2]=15 cells (4 PI)
8183 08:06:28.180840 u2DelayCellOfst[3]=18 cells (5 PI)
8184 08:06:28.183869 u2DelayCellOfst[4]=11 cells (3 PI)
8185 08:06:28.187231 u2DelayCellOfst[5]=0 cells (0 PI)
8186 08:06:28.190792 u2DelayCellOfst[6]=18 cells (5 PI)
8187 08:06:28.193823 u2DelayCellOfst[7]=18 cells (5 PI)
8188 08:06:28.197210 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8189 08:06:28.200375 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8190 08:06:28.204098 == TX Byte 1 ==
8191 08:06:28.206822 u2DelayCellOfst[8]=0 cells (0 PI)
8192 08:06:28.210081 u2DelayCellOfst[9]=0 cells (0 PI)
8193 08:06:28.213798 u2DelayCellOfst[10]=7 cells (2 PI)
8194 08:06:28.214379 u2DelayCellOfst[11]=3 cells (1 PI)
8195 08:06:28.216782 u2DelayCellOfst[12]=11 cells (3 PI)
8196 08:06:28.220374 u2DelayCellOfst[13]=11 cells (3 PI)
8197 08:06:28.223286 u2DelayCellOfst[14]=15 cells (4 PI)
8198 08:06:28.226897 u2DelayCellOfst[15]=11 cells (3 PI)
8199 08:06:28.233749 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8200 08:06:28.236535 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8201 08:06:28.236996 DramC Write-DBI on
8202 08:06:28.239580 ==
8203 08:06:28.243120 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 08:06:28.246013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 08:06:28.246480 ==
8206 08:06:28.246843
8207 08:06:28.247179
8208 08:06:28.249533 TX Vref Scan disable
8209 08:06:28.250023 == TX Byte 0 ==
8210 08:06:28.256314 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8211 08:06:28.257020 == TX Byte 1 ==
8212 08:06:28.259706 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8213 08:06:28.263182 DramC Write-DBI off
8214 08:06:28.263795
8215 08:06:28.264185 [DATLAT]
8216 08:06:28.266473 Freq=1600, CH0 RK1
8217 08:06:28.267032
8218 08:06:28.267392 DATLAT Default: 0xf
8219 08:06:28.269426 0, 0xFFFF, sum = 0
8220 08:06:28.269890 1, 0xFFFF, sum = 0
8221 08:06:28.272893 2, 0xFFFF, sum = 0
8222 08:06:28.273361 3, 0xFFFF, sum = 0
8223 08:06:28.276762 4, 0xFFFF, sum = 0
8224 08:06:28.277335 5, 0xFFFF, sum = 0
8225 08:06:28.279805 6, 0xFFFF, sum = 0
8226 08:06:28.280377 7, 0xFFFF, sum = 0
8227 08:06:28.283325 8, 0xFFFF, sum = 0
8228 08:06:28.287104 9, 0xFFFF, sum = 0
8229 08:06:28.287677 10, 0xFFFF, sum = 0
8230 08:06:28.289976 11, 0xFFFF, sum = 0
8231 08:06:28.290543 12, 0xFFFF, sum = 0
8232 08:06:28.293525 13, 0xFFFF, sum = 0
8233 08:06:28.294108 14, 0x0, sum = 1
8234 08:06:28.296447 15, 0x0, sum = 2
8235 08:06:28.297023 16, 0x0, sum = 3
8236 08:06:28.299687 17, 0x0, sum = 4
8237 08:06:28.300205 best_step = 15
8238 08:06:28.300572
8239 08:06:28.300911 ==
8240 08:06:28.302725 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 08:06:28.306185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 08:06:28.309431 ==
8243 08:06:28.309993 RX Vref Scan: 0
8244 08:06:28.310362
8245 08:06:28.312806 RX Vref 0 -> 0, step: 1
8246 08:06:28.313271
8247 08:06:28.313632 RX Delay 11 -> 252, step: 4
8248 08:06:28.320015 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8249 08:06:28.323330 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8250 08:06:28.326523 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8251 08:06:28.329704 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8252 08:06:28.336446 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8253 08:06:28.339618 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8254 08:06:28.342894 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8255 08:06:28.346290 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8256 08:06:28.349959 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8257 08:06:28.355914 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8258 08:06:28.359310 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8259 08:06:28.363285 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8260 08:06:28.366024 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8261 08:06:28.370000 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8262 08:06:28.376200 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8263 08:06:28.379472 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8264 08:06:28.380086 ==
8265 08:06:28.382893 Dram Type= 6, Freq= 0, CH_0, rank 1
8266 08:06:28.386286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 08:06:28.386855 ==
8268 08:06:28.389404 DQS Delay:
8269 08:06:28.389865 DQS0 = 0, DQS1 = 0
8270 08:06:28.390234 DQM Delay:
8271 08:06:28.392283 DQM0 = 130, DQM1 = 125
8272 08:06:28.392745 DQ Delay:
8273 08:06:28.395930 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8274 08:06:28.399262 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8275 08:06:28.406338 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8276 08:06:28.409077 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8277 08:06:28.409642
8278 08:06:28.410013
8279 08:06:28.410358
8280 08:06:28.412063 [DramC_TX_OE_Calibration] TA2
8281 08:06:28.415459 Original DQ_B0 (3 6) =30, OEN = 27
8282 08:06:28.418883 Original DQ_B1 (3 6) =30, OEN = 27
8283 08:06:28.419454 24, 0x0, End_B0=24 End_B1=24
8284 08:06:28.422894 25, 0x0, End_B0=25 End_B1=25
8285 08:06:28.425527 26, 0x0, End_B0=26 End_B1=26
8286 08:06:28.428980 27, 0x0, End_B0=27 End_B1=27
8287 08:06:28.431704 28, 0x0, End_B0=28 End_B1=28
8288 08:06:28.432429 29, 0x0, End_B0=29 End_B1=29
8289 08:06:28.435602 30, 0x0, End_B0=30 End_B1=30
8290 08:06:28.439502 31, 0x4545, End_B0=30 End_B1=30
8291 08:06:28.442292 Byte0 end_step=30 best_step=27
8292 08:06:28.445573 Byte1 end_step=30 best_step=27
8293 08:06:28.446193 Byte0 TX OE(2T, 0.5T) = (3, 3)
8294 08:06:28.448483 Byte1 TX OE(2T, 0.5T) = (3, 3)
8295 08:06:28.448945
8296 08:06:28.449309
8297 08:06:28.458334 [DQSOSCAuto] RK1, (LSB)MR18= 0x2003, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8298 08:06:28.461878 CH0 RK1: MR19=303, MR18=2003
8299 08:06:28.468312 CH0_RK1: MR19=0x303, MR18=0x2003, DQSOSC=393, MR23=63, INC=23, DEC=15
8300 08:06:28.468895 [RxdqsGatingPostProcess] freq 1600
8301 08:06:28.474737 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8302 08:06:28.478054 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 08:06:28.481191 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 08:06:28.485100 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 08:06:28.488445 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 08:06:28.491457 best DQS0 dly(2T, 0.5T) = (1, 1)
8307 08:06:28.494613 best DQS1 dly(2T, 0.5T) = (1, 1)
8308 08:06:28.497682 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8309 08:06:28.501189 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8310 08:06:28.504213 Pre-setting of DQS Precalculation
8311 08:06:28.507898 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8312 08:06:28.508399 ==
8313 08:06:28.511113 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 08:06:28.514146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 08:06:28.514637 ==
8316 08:06:28.520461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 08:06:28.524772 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 08:06:28.530438 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 08:06:28.533989 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 08:06:28.543806 [CA 0] Center 42 (13~72) winsize 60
8321 08:06:28.547667 [CA 1] Center 42 (13~72) winsize 60
8322 08:06:28.550603 [CA 2] Center 38 (9~67) winsize 59
8323 08:06:28.554150 [CA 3] Center 37 (8~66) winsize 59
8324 08:06:28.557714 [CA 4] Center 38 (9~67) winsize 59
8325 08:06:28.560233 [CA 5] Center 37 (7~67) winsize 61
8326 08:06:28.560531
8327 08:06:28.563781 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8328 08:06:28.564001
8329 08:06:28.567056 [CATrainingPosCal] consider 1 rank data
8330 08:06:28.570585 u2DelayCellTimex100 = 258/100 ps
8331 08:06:28.577074 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8332 08:06:28.580521 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8333 08:06:28.583760 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8334 08:06:28.587332 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8335 08:06:28.590487 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8336 08:06:28.594056 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8337 08:06:28.594614
8338 08:06:28.597041 CA PerBit enable=1, Macro0, CA PI delay=37
8339 08:06:28.597601
8340 08:06:28.600385 [CBTSetCACLKResult] CA Dly = 37
8341 08:06:28.604002 CS Dly: 10 (0~41)
8342 08:06:28.606933 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 08:06:28.610544 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 08:06:28.611102 ==
8345 08:06:28.613686 Dram Type= 6, Freq= 0, CH_1, rank 1
8346 08:06:28.619991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 08:06:28.620562 ==
8348 08:06:28.623933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8349 08:06:28.630268 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8350 08:06:28.633529 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8351 08:06:28.639603 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8352 08:06:28.647840 [CA 0] Center 42 (12~72) winsize 61
8353 08:06:28.650610 [CA 1] Center 42 (13~72) winsize 60
8354 08:06:28.654538 [CA 2] Center 37 (8~67) winsize 60
8355 08:06:28.657264 [CA 3] Center 37 (8~66) winsize 59
8356 08:06:28.660584 [CA 4] Center 37 (8~67) winsize 60
8357 08:06:28.663684 [CA 5] Center 36 (7~66) winsize 60
8358 08:06:28.664189
8359 08:06:28.666932 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8360 08:06:28.667392
8361 08:06:28.673371 [CATrainingPosCal] consider 2 rank data
8362 08:06:28.673925 u2DelayCellTimex100 = 258/100 ps
8363 08:06:28.680214 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8364 08:06:28.683185 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8365 08:06:28.686903 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8366 08:06:28.690036 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8367 08:06:28.693368 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8368 08:06:28.697095 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8369 08:06:28.697659
8370 08:06:28.700279 CA PerBit enable=1, Macro0, CA PI delay=36
8371 08:06:28.700739
8372 08:06:28.703279 [CBTSetCACLKResult] CA Dly = 36
8373 08:06:28.706493 CS Dly: 11 (0~43)
8374 08:06:28.709870 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8375 08:06:28.713230 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8376 08:06:28.713791
8377 08:06:28.716262 ----->DramcWriteLeveling(PI) begin...
8378 08:06:28.720320 ==
8379 08:06:28.720883 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 08:06:28.725997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 08:06:28.726478 ==
8382 08:06:28.729770 Write leveling (Byte 0): 24 => 24
8383 08:06:28.732687 Write leveling (Byte 1): 25 => 25
8384 08:06:28.736042 DramcWriteLeveling(PI) end<-----
8385 08:06:28.736505
8386 08:06:28.736864 ==
8387 08:06:28.739263 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 08:06:28.742765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 08:06:28.743326 ==
8390 08:06:28.745750 [Gating] SW mode calibration
8391 08:06:28.752374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8392 08:06:28.759467 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8393 08:06:28.762879 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 08:06:28.765615 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 08:06:28.772391 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 08:06:28.775481 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8397 08:06:28.778769 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 08:06:28.785423 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 08:06:28.788584 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 08:06:28.791918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 08:06:28.799262 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 08:06:28.801914 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 08:06:28.805662 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8404 08:06:28.812396 1 5 12 | B1->B0 | 2626 2626 | 0 0 | (1 0) (1 0)
8405 08:06:28.815187 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8406 08:06:28.818811 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 08:06:28.825542 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 08:06:28.828818 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 08:06:28.831630 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 08:06:28.838587 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 08:06:28.841789 1 6 8 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
8412 08:06:28.844587 1 6 12 | B1->B0 | 3f3f 4545 | 1 0 | (0 0) (0 0)
8413 08:06:28.851557 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 08:06:28.855302 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 08:06:28.858136 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 08:06:28.864331 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 08:06:28.867832 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 08:06:28.872052 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 08:06:28.877481 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 08:06:28.880986 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8421 08:06:28.884227 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8422 08:06:28.891541 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 08:06:28.894218 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 08:06:28.897813 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 08:06:28.904120 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 08:06:28.907582 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 08:06:28.910874 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 08:06:28.918022 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 08:06:28.921589 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 08:06:28.924017 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 08:06:28.930879 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 08:06:28.934494 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 08:06:28.937687 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 08:06:28.941031 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 08:06:28.946952 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8436 08:06:28.950415 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8437 08:06:28.954142 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 08:06:28.956930 Total UI for P1: 0, mck2ui 16
8439 08:06:28.960745 best dqsien dly found for B0: ( 1, 9, 10)
8440 08:06:28.964015 Total UI for P1: 0, mck2ui 16
8441 08:06:28.967121 best dqsien dly found for B1: ( 1, 9, 10)
8442 08:06:28.970659 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8443 08:06:28.976912 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8444 08:06:28.977331
8445 08:06:28.980697 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8446 08:06:28.983808 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8447 08:06:28.986948 [Gating] SW calibration Done
8448 08:06:28.987360 ==
8449 08:06:28.990449 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 08:06:28.993242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 08:06:28.993662 ==
8452 08:06:28.996580 RX Vref Scan: 0
8453 08:06:28.997005
8454 08:06:28.997334 RX Vref 0 -> 0, step: 1
8455 08:06:28.997645
8456 08:06:29.000129 RX Delay 0 -> 252, step: 8
8457 08:06:29.003305 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8458 08:06:29.009967 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8459 08:06:29.013207 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8460 08:06:29.016330 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8461 08:06:29.019907 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8462 08:06:29.023180 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8463 08:06:29.029602 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8464 08:06:29.032799 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8465 08:06:29.037057 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8466 08:06:29.039846 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8467 08:06:29.044294 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8468 08:06:29.049712 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8469 08:06:29.053014 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8470 08:06:29.056390 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8471 08:06:29.059812 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8472 08:06:29.062851 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8473 08:06:29.066792 ==
8474 08:06:29.069986 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 08:06:29.072656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 08:06:29.073182 ==
8477 08:06:29.073512 DQS Delay:
8478 08:06:29.075860 DQS0 = 0, DQS1 = 0
8479 08:06:29.076277 DQM Delay:
8480 08:06:29.079769 DQM0 = 138, DQM1 = 130
8481 08:06:29.080290 DQ Delay:
8482 08:06:29.083133 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8483 08:06:29.086453 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8484 08:06:29.089416 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8485 08:06:29.092603 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8486 08:06:29.093123
8487 08:06:29.093455
8488 08:06:29.095748 ==
8489 08:06:29.096271 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 08:06:29.102132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 08:06:29.102651 ==
8492 08:06:29.102986
8493 08:06:29.103296
8494 08:06:29.105673 TX Vref Scan disable
8495 08:06:29.106187 == TX Byte 0 ==
8496 08:06:29.109151 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8497 08:06:29.115469 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 08:06:29.116042 == TX Byte 1 ==
8499 08:06:29.122577 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8500 08:06:29.125174 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8501 08:06:29.125592 ==
8502 08:06:29.128652 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 08:06:29.131795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 08:06:29.132219 ==
8505 08:06:29.145266
8506 08:06:29.148422 TX Vref early break, caculate TX vref
8507 08:06:29.151291 TX Vref=16, minBit 0, minWin=22, winSum=375
8508 08:06:29.154873 TX Vref=18, minBit 0, minWin=22, winSum=387
8509 08:06:29.158134 TX Vref=20, minBit 0, minWin=24, winSum=397
8510 08:06:29.161454 TX Vref=22, minBit 0, minWin=24, winSum=404
8511 08:06:29.164929 TX Vref=24, minBit 0, minWin=24, winSum=414
8512 08:06:29.171184 TX Vref=26, minBit 0, minWin=25, winSum=421
8513 08:06:29.174723 TX Vref=28, minBit 0, minWin=25, winSum=424
8514 08:06:29.178150 TX Vref=30, minBit 1, minWin=24, winSum=415
8515 08:06:29.181270 TX Vref=32, minBit 0, minWin=23, winSum=406
8516 08:06:29.184438 TX Vref=34, minBit 0, minWin=22, winSum=393
8517 08:06:29.191180 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8518 08:06:29.191761
8519 08:06:29.194702 Final TX Range 0 Vref 28
8520 08:06:29.195254
8521 08:06:29.195617 ==
8522 08:06:29.198253 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 08:06:29.201141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 08:06:29.201618 ==
8525 08:06:29.201978
8526 08:06:29.202310
8527 08:06:29.205062 TX Vref Scan disable
8528 08:06:29.211364 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8529 08:06:29.211973 == TX Byte 0 ==
8530 08:06:29.214541 u2DelayCellOfst[0]=18 cells (5 PI)
8531 08:06:29.217800 u2DelayCellOfst[1]=11 cells (3 PI)
8532 08:06:29.220770 u2DelayCellOfst[2]=0 cells (0 PI)
8533 08:06:29.223990 u2DelayCellOfst[3]=3 cells (1 PI)
8534 08:06:29.227536 u2DelayCellOfst[4]=7 cells (2 PI)
8535 08:06:29.230597 u2DelayCellOfst[5]=22 cells (6 PI)
8536 08:06:29.233876 u2DelayCellOfst[6]=22 cells (6 PI)
8537 08:06:29.237182 u2DelayCellOfst[7]=3 cells (1 PI)
8538 08:06:29.240457 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8539 08:06:29.243848 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8540 08:06:29.247283 == TX Byte 1 ==
8541 08:06:29.251044 u2DelayCellOfst[8]=0 cells (0 PI)
8542 08:06:29.251616 u2DelayCellOfst[9]=3 cells (1 PI)
8543 08:06:29.253597 u2DelayCellOfst[10]=11 cells (3 PI)
8544 08:06:29.257697 u2DelayCellOfst[11]=3 cells (1 PI)
8545 08:06:29.260399 u2DelayCellOfst[12]=15 cells (4 PI)
8546 08:06:29.264220 u2DelayCellOfst[13]=18 cells (5 PI)
8547 08:06:29.267106 u2DelayCellOfst[14]=18 cells (5 PI)
8548 08:06:29.270558 u2DelayCellOfst[15]=18 cells (5 PI)
8549 08:06:29.276531 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8550 08:06:29.280294 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8551 08:06:29.280851 DramC Write-DBI on
8552 08:06:29.281217 ==
8553 08:06:29.283534 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 08:06:29.290003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 08:06:29.290583 ==
8556 08:06:29.290948
8557 08:06:29.291278
8558 08:06:29.291591 TX Vref Scan disable
8559 08:06:29.293897 == TX Byte 0 ==
8560 08:06:29.298042 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8561 08:06:29.300680 == TX Byte 1 ==
8562 08:06:29.304633 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8563 08:06:29.307476 DramC Write-DBI off
8564 08:06:29.308085
8565 08:06:29.308454 [DATLAT]
8566 08:06:29.308790 Freq=1600, CH1 RK0
8567 08:06:29.309114
8568 08:06:29.310499 DATLAT Default: 0xf
8569 08:06:29.310953 0, 0xFFFF, sum = 0
8570 08:06:29.314103 1, 0xFFFF, sum = 0
8571 08:06:29.317295 2, 0xFFFF, sum = 0
8572 08:06:29.317862 3, 0xFFFF, sum = 0
8573 08:06:29.320313 4, 0xFFFF, sum = 0
8574 08:06:29.320778 5, 0xFFFF, sum = 0
8575 08:06:29.323856 6, 0xFFFF, sum = 0
8576 08:06:29.324418 7, 0xFFFF, sum = 0
8577 08:06:29.327781 8, 0xFFFF, sum = 0
8578 08:06:29.328249 9, 0xFFFF, sum = 0
8579 08:06:29.331153 10, 0xFFFF, sum = 0
8580 08:06:29.331713 11, 0xFFFF, sum = 0
8581 08:06:29.333921 12, 0xFFFF, sum = 0
8582 08:06:29.334381 13, 0xBFFF, sum = 0
8583 08:06:29.336601 14, 0x0, sum = 1
8584 08:06:29.337067 15, 0x0, sum = 2
8585 08:06:29.340004 16, 0x0, sum = 3
8586 08:06:29.340465 17, 0x0, sum = 4
8587 08:06:29.343605 best_step = 15
8588 08:06:29.344082
8589 08:06:29.344442 ==
8590 08:06:29.346609 Dram Type= 6, Freq= 0, CH_1, rank 0
8591 08:06:29.349983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8592 08:06:29.350544 ==
8593 08:06:29.353161 RX Vref Scan: 1
8594 08:06:29.353617
8595 08:06:29.353979 Set Vref Range= 24 -> 127
8596 08:06:29.354315
8597 08:06:29.356778 RX Vref 24 -> 127, step: 1
8598 08:06:29.357225
8599 08:06:29.359792 RX Delay 19 -> 252, step: 4
8600 08:06:29.360208
8601 08:06:29.362968 Set Vref, RX VrefLevel [Byte0]: 24
8602 08:06:29.366972 [Byte1]: 24
8603 08:06:29.367490
8604 08:06:29.370278 Set Vref, RX VrefLevel [Byte0]: 25
8605 08:06:29.373108 [Byte1]: 25
8606 08:06:29.376550
8607 08:06:29.376962 Set Vref, RX VrefLevel [Byte0]: 26
8608 08:06:29.379831 [Byte1]: 26
8609 08:06:29.384489
8610 08:06:29.384993 Set Vref, RX VrefLevel [Byte0]: 27
8611 08:06:29.387674 [Byte1]: 27
8612 08:06:29.391983
8613 08:06:29.392393 Set Vref, RX VrefLevel [Byte0]: 28
8614 08:06:29.395225 [Byte1]: 28
8615 08:06:29.399886
8616 08:06:29.400437 Set Vref, RX VrefLevel [Byte0]: 29
8617 08:06:29.402925 [Byte1]: 29
8618 08:06:29.407199
8619 08:06:29.407794 Set Vref, RX VrefLevel [Byte0]: 30
8620 08:06:29.410765 [Byte1]: 30
8621 08:06:29.414778
8622 08:06:29.415328 Set Vref, RX VrefLevel [Byte0]: 31
8623 08:06:29.418326 [Byte1]: 31
8624 08:06:29.423123
8625 08:06:29.423687 Set Vref, RX VrefLevel [Byte0]: 32
8626 08:06:29.425545 [Byte1]: 32
8627 08:06:29.430154
8628 08:06:29.430702 Set Vref, RX VrefLevel [Byte0]: 33
8629 08:06:29.433132 [Byte1]: 33
8630 08:06:29.437150
8631 08:06:29.437604 Set Vref, RX VrefLevel [Byte0]: 34
8632 08:06:29.440831 [Byte1]: 34
8633 08:06:29.445235
8634 08:06:29.445986 Set Vref, RX VrefLevel [Byte0]: 35
8635 08:06:29.448479 [Byte1]: 35
8636 08:06:29.452805
8637 08:06:29.453355 Set Vref, RX VrefLevel [Byte0]: 36
8638 08:06:29.455845 [Byte1]: 36
8639 08:06:29.460509
8640 08:06:29.461060 Set Vref, RX VrefLevel [Byte0]: 37
8641 08:06:29.463710 [Byte1]: 37
8642 08:06:29.467573
8643 08:06:29.468165 Set Vref, RX VrefLevel [Byte0]: 38
8644 08:06:29.471227 [Byte1]: 38
8645 08:06:29.475271
8646 08:06:29.475866 Set Vref, RX VrefLevel [Byte0]: 39
8647 08:06:29.478702 [Byte1]: 39
8648 08:06:29.482908
8649 08:06:29.483462 Set Vref, RX VrefLevel [Byte0]: 40
8650 08:06:29.486817 [Byte1]: 40
8651 08:06:29.490697
8652 08:06:29.491263 Set Vref, RX VrefLevel [Byte0]: 41
8653 08:06:29.494453 [Byte1]: 41
8654 08:06:29.499119
8655 08:06:29.499675 Set Vref, RX VrefLevel [Byte0]: 42
8656 08:06:29.501721 [Byte1]: 42
8657 08:06:29.506278
8658 08:06:29.506831 Set Vref, RX VrefLevel [Byte0]: 43
8659 08:06:29.509137 [Byte1]: 43
8660 08:06:29.513651
8661 08:06:29.514203 Set Vref, RX VrefLevel [Byte0]: 44
8662 08:06:29.516973 [Byte1]: 44
8663 08:06:29.520893
8664 08:06:29.521447 Set Vref, RX VrefLevel [Byte0]: 45
8665 08:06:29.524266 [Byte1]: 45
8666 08:06:29.528456
8667 08:06:29.528909 Set Vref, RX VrefLevel [Byte0]: 46
8668 08:06:29.532299 [Byte1]: 46
8669 08:06:29.536377
8670 08:06:29.536832 Set Vref, RX VrefLevel [Byte0]: 47
8671 08:06:29.539477 [Byte1]: 47
8672 08:06:29.543458
8673 08:06:29.544075 Set Vref, RX VrefLevel [Byte0]: 48
8674 08:06:29.546852 [Byte1]: 48
8675 08:06:29.551038
8676 08:06:29.551587 Set Vref, RX VrefLevel [Byte0]: 49
8677 08:06:29.554053 [Byte1]: 49
8678 08:06:29.558595
8679 08:06:29.559051 Set Vref, RX VrefLevel [Byte0]: 50
8680 08:06:29.561892 [Byte1]: 50
8681 08:06:29.566451
8682 08:06:29.567069 Set Vref, RX VrefLevel [Byte0]: 51
8683 08:06:29.569352 [Byte1]: 51
8684 08:06:29.573790
8685 08:06:29.574246 Set Vref, RX VrefLevel [Byte0]: 52
8686 08:06:29.577338 [Byte1]: 52
8687 08:06:29.581238
8688 08:06:29.581826 Set Vref, RX VrefLevel [Byte0]: 53
8689 08:06:29.584461 [Byte1]: 53
8690 08:06:29.589226
8691 08:06:29.589778 Set Vref, RX VrefLevel [Byte0]: 54
8692 08:06:29.592470 [Byte1]: 54
8693 08:06:29.597036
8694 08:06:29.597602 Set Vref, RX VrefLevel [Byte0]: 55
8695 08:06:29.600058 [Byte1]: 55
8696 08:06:29.603836
8697 08:06:29.604292 Set Vref, RX VrefLevel [Byte0]: 56
8698 08:06:29.607679 [Byte1]: 56
8699 08:06:29.611691
8700 08:06:29.612287 Set Vref, RX VrefLevel [Byte0]: 57
8701 08:06:29.615052 [Byte1]: 57
8702 08:06:29.620433
8703 08:06:29.620988 Set Vref, RX VrefLevel [Byte0]: 58
8704 08:06:29.622967 [Byte1]: 58
8705 08:06:29.627054
8706 08:06:29.627617 Set Vref, RX VrefLevel [Byte0]: 59
8707 08:06:29.630710 [Byte1]: 59
8708 08:06:29.634918
8709 08:06:29.637282 Set Vref, RX VrefLevel [Byte0]: 60
8710 08:06:29.641024 [Byte1]: 60
8711 08:06:29.641488
8712 08:06:29.644210 Set Vref, RX VrefLevel [Byte0]: 61
8713 08:06:29.647003 [Byte1]: 61
8714 08:06:29.647461
8715 08:06:29.651162 Set Vref, RX VrefLevel [Byte0]: 62
8716 08:06:29.653870 [Byte1]: 62
8717 08:06:29.657176
8718 08:06:29.657632 Set Vref, RX VrefLevel [Byte0]: 63
8719 08:06:29.660412 [Byte1]: 63
8720 08:06:29.665546
8721 08:06:29.666111 Set Vref, RX VrefLevel [Byte0]: 64
8722 08:06:29.668277 [Byte1]: 64
8723 08:06:29.672103
8724 08:06:29.672660 Set Vref, RX VrefLevel [Byte0]: 65
8725 08:06:29.675906 [Byte1]: 65
8726 08:06:29.679957
8727 08:06:29.680513 Set Vref, RX VrefLevel [Byte0]: 66
8728 08:06:29.683469 [Byte1]: 66
8729 08:06:29.687628
8730 08:06:29.688234 Set Vref, RX VrefLevel [Byte0]: 67
8731 08:06:29.690557 [Byte1]: 67
8732 08:06:29.695376
8733 08:06:29.695960 Set Vref, RX VrefLevel [Byte0]: 68
8734 08:06:29.698013 [Byte1]: 68
8735 08:06:29.702385
8736 08:06:29.702942 Set Vref, RX VrefLevel [Byte0]: 69
8737 08:06:29.705678 [Byte1]: 69
8738 08:06:29.710308
8739 08:06:29.710862 Set Vref, RX VrefLevel [Byte0]: 70
8740 08:06:29.713551 [Byte1]: 70
8741 08:06:29.717836
8742 08:06:29.718391 Set Vref, RX VrefLevel [Byte0]: 71
8743 08:06:29.720589 [Byte1]: 71
8744 08:06:29.725307
8745 08:06:29.725863 Set Vref, RX VrefLevel [Byte0]: 72
8746 08:06:29.728066 [Byte1]: 72
8747 08:06:29.732783
8748 08:06:29.733381 Set Vref, RX VrefLevel [Byte0]: 73
8749 08:06:29.736062 [Byte1]: 73
8750 08:06:29.740266
8751 08:06:29.740723 Set Vref, RX VrefLevel [Byte0]: 74
8752 08:06:29.743534 [Byte1]: 74
8753 08:06:29.747945
8754 08:06:29.748495 Set Vref, RX VrefLevel [Byte0]: 75
8755 08:06:29.751128 [Byte1]: 75
8756 08:06:29.755660
8757 08:06:29.756261 Set Vref, RX VrefLevel [Byte0]: 76
8758 08:06:29.758711 [Byte1]: 76
8759 08:06:29.763413
8760 08:06:29.764066 Final RX Vref Byte 0 = 51 to rank0
8761 08:06:29.766370 Final RX Vref Byte 1 = 56 to rank0
8762 08:06:29.769340 Final RX Vref Byte 0 = 51 to rank1
8763 08:06:29.772542 Final RX Vref Byte 1 = 56 to rank1==
8764 08:06:29.776425 Dram Type= 6, Freq= 0, CH_1, rank 0
8765 08:06:29.783072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 08:06:29.783627 ==
8767 08:06:29.784033 DQS Delay:
8768 08:06:29.784367 DQS0 = 0, DQS1 = 0
8769 08:06:29.786183 DQM Delay:
8770 08:06:29.786732 DQM0 = 134, DQM1 = 129
8771 08:06:29.789698 DQ Delay:
8772 08:06:29.792749 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130
8773 08:06:29.796247 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8774 08:06:29.799070 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =118
8775 08:06:29.802517 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
8776 08:06:29.802970
8777 08:06:29.803323
8778 08:06:29.803652
8779 08:06:29.806645 [DramC_TX_OE_Calibration] TA2
8780 08:06:29.809064 Original DQ_B0 (3 6) =30, OEN = 27
8781 08:06:29.812629 Original DQ_B1 (3 6) =30, OEN = 27
8782 08:06:29.816329 24, 0x0, End_B0=24 End_B1=24
8783 08:06:29.819144 25, 0x0, End_B0=25 End_B1=25
8784 08:06:29.819707 26, 0x0, End_B0=26 End_B1=26
8785 08:06:29.823364 27, 0x0, End_B0=27 End_B1=27
8786 08:06:29.825708 28, 0x0, End_B0=28 End_B1=28
8787 08:06:29.828744 29, 0x0, End_B0=29 End_B1=29
8788 08:06:29.829206 30, 0x0, End_B0=30 End_B1=30
8789 08:06:29.832200 31, 0x4141, End_B0=30 End_B1=30
8790 08:06:29.835864 Byte0 end_step=30 best_step=27
8791 08:06:29.839044 Byte1 end_step=30 best_step=27
8792 08:06:29.842288 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 08:06:29.845256 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 08:06:29.845725
8795 08:06:29.846088
8796 08:06:29.852314 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8797 08:06:29.855790 CH1 RK0: MR19=303, MR18=1A0F
8798 08:06:29.862194 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8799 08:06:29.862800
8800 08:06:29.865915 ----->DramcWriteLeveling(PI) begin...
8801 08:06:29.866475 ==
8802 08:06:29.868600 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 08:06:29.872221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 08:06:29.872783 ==
8805 08:06:29.875605 Write leveling (Byte 0): 24 => 24
8806 08:06:29.878634 Write leveling (Byte 1): 28 => 28
8807 08:06:29.882474 DramcWriteLeveling(PI) end<-----
8808 08:06:29.883026
8809 08:06:29.883389 ==
8810 08:06:29.885214 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 08:06:29.888304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 08:06:29.891890 ==
8813 08:06:29.892378 [Gating] SW mode calibration
8814 08:06:29.901203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8815 08:06:29.904728 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8816 08:06:29.907672 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 08:06:29.914762 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 08:06:29.917887 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8819 08:06:29.921724 1 4 12 | B1->B0 | 3434 2322 | 1 1 | (1 1) (0 0)
8820 08:06:29.928330 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 08:06:29.931470 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 08:06:29.934811 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 08:06:29.941344 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 08:06:29.944418 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 08:06:29.948239 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 08:06:29.955621 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8827 08:06:29.957973 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8828 08:06:29.960938 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8829 08:06:29.967552 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 08:06:29.970696 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 08:06:29.974878 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 08:06:29.981285 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 08:06:29.984104 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 08:06:29.987929 1 6 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8835 08:06:29.994289 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8836 08:06:29.997479 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 08:06:30.000860 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 08:06:30.007303 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 08:06:30.010476 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 08:06:30.014068 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 08:06:30.020341 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 08:06:30.023806 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8843 08:06:30.027673 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8844 08:06:30.033784 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8845 08:06:30.036669 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 08:06:30.040468 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 08:06:30.046653 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 08:06:30.049874 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 08:06:30.053961 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 08:06:30.060575 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 08:06:30.064168 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 08:06:30.066956 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 08:06:30.074217 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 08:06:30.076489 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 08:06:30.079849 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 08:06:30.086728 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 08:06:30.090036 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 08:06:30.092857 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8859 08:06:30.099693 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8860 08:06:30.102682 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8861 08:06:30.106343 Total UI for P1: 0, mck2ui 16
8862 08:06:30.109466 best dqsien dly found for B1: ( 1, 9, 10)
8863 08:06:30.113111 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 08:06:30.116256 Total UI for P1: 0, mck2ui 16
8865 08:06:30.119603 best dqsien dly found for B0: ( 1, 9, 12)
8866 08:06:30.122743 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8867 08:06:30.126403 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8868 08:06:30.127000
8869 08:06:30.133368 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8870 08:06:30.135715 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8871 08:06:30.139444 [Gating] SW calibration Done
8872 08:06:30.139954 ==
8873 08:06:30.142252 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 08:06:30.145703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 08:06:30.146173 ==
8876 08:06:30.146541 RX Vref Scan: 0
8877 08:06:30.148989
8878 08:06:30.149448 RX Vref 0 -> 0, step: 1
8879 08:06:30.149820
8880 08:06:30.152267 RX Delay 0 -> 252, step: 8
8881 08:06:30.155396 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8882 08:06:30.159410 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8883 08:06:30.165673 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8884 08:06:30.169169 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8885 08:06:30.172425 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8886 08:06:30.175368 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8887 08:06:30.179100 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8888 08:06:30.185657 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8889 08:06:30.188718 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8890 08:06:30.192392 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8891 08:06:30.195555 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8892 08:06:30.198686 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8893 08:06:30.205789 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8894 08:06:30.208606 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8895 08:06:30.211680 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8896 08:06:30.215308 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8897 08:06:30.215919 ==
8898 08:06:30.219120 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 08:06:30.225022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 08:06:30.225582 ==
8901 08:06:30.225951 DQS Delay:
8902 08:06:30.228329 DQS0 = 0, DQS1 = 0
8903 08:06:30.228790 DQM Delay:
8904 08:06:30.229246 DQM0 = 136, DQM1 = 129
8905 08:06:30.231520 DQ Delay:
8906 08:06:30.235076 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8907 08:06:30.238363 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8908 08:06:30.242036 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8909 08:06:30.245341 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8910 08:06:30.245898
8911 08:06:30.246260
8912 08:06:30.246593 ==
8913 08:06:30.248830 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 08:06:30.255076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 08:06:30.255535 ==
8916 08:06:30.255969
8917 08:06:30.256311
8918 08:06:30.256631 TX Vref Scan disable
8919 08:06:30.258752 == TX Byte 0 ==
8920 08:06:30.261873 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8921 08:06:30.264668 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8922 08:06:30.268439 == TX Byte 1 ==
8923 08:06:30.271703 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8924 08:06:30.278088 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 08:06:30.278638 ==
8926 08:06:30.281972 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 08:06:30.285210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 08:06:30.285766 ==
8929 08:06:30.296121
8930 08:06:30.299872 TX Vref early break, caculate TX vref
8931 08:06:30.302603 TX Vref=16, minBit 1, minWin=22, winSum=380
8932 08:06:30.306415 TX Vref=18, minBit 0, minWin=23, winSum=393
8933 08:06:30.309640 TX Vref=20, minBit 0, minWin=24, winSum=399
8934 08:06:30.313059 TX Vref=22, minBit 0, minWin=24, winSum=405
8935 08:06:30.315762 TX Vref=24, minBit 5, minWin=24, winSum=413
8936 08:06:30.322750 TX Vref=26, minBit 5, minWin=25, winSum=423
8937 08:06:30.326155 TX Vref=28, minBit 0, minWin=24, winSum=418
8938 08:06:30.328928 TX Vref=30, minBit 0, minWin=23, winSum=410
8939 08:06:30.332681 TX Vref=32, minBit 0, minWin=23, winSum=400
8940 08:06:30.339120 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 26
8941 08:06:30.339668
8942 08:06:30.342347 Final TX Range 0 Vref 26
8943 08:06:30.342807
8944 08:06:30.343170 ==
8945 08:06:30.346589 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 08:06:30.349047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 08:06:30.349610 ==
8948 08:06:30.349973
8949 08:06:30.350308
8950 08:06:30.352330 TX Vref Scan disable
8951 08:06:30.359218 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8952 08:06:30.359813 == TX Byte 0 ==
8953 08:06:30.362310 u2DelayCellOfst[0]=18 cells (5 PI)
8954 08:06:30.365561 u2DelayCellOfst[1]=11 cells (3 PI)
8955 08:06:30.368584 u2DelayCellOfst[2]=0 cells (0 PI)
8956 08:06:30.372248 u2DelayCellOfst[3]=7 cells (2 PI)
8957 08:06:30.375928 u2DelayCellOfst[4]=7 cells (2 PI)
8958 08:06:30.378807 u2DelayCellOfst[5]=22 cells (6 PI)
8959 08:06:30.382270 u2DelayCellOfst[6]=18 cells (5 PI)
8960 08:06:30.382827 u2DelayCellOfst[7]=7 cells (2 PI)
8961 08:06:30.389008 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8962 08:06:30.391893 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8963 08:06:30.392453 == TX Byte 1 ==
8964 08:06:30.395226 u2DelayCellOfst[8]=0 cells (0 PI)
8965 08:06:30.398230 u2DelayCellOfst[9]=3 cells (1 PI)
8966 08:06:30.401803 u2DelayCellOfst[10]=11 cells (3 PI)
8967 08:06:30.405047 u2DelayCellOfst[11]=7 cells (2 PI)
8968 08:06:30.408357 u2DelayCellOfst[12]=15 cells (4 PI)
8969 08:06:30.411528 u2DelayCellOfst[13]=18 cells (5 PI)
8970 08:06:30.414898 u2DelayCellOfst[14]=18 cells (5 PI)
8971 08:06:30.418293 u2DelayCellOfst[15]=18 cells (5 PI)
8972 08:06:30.421336 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8973 08:06:30.427874 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8974 08:06:30.428418 DramC Write-DBI on
8975 08:06:30.428905 ==
8976 08:06:30.431702 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 08:06:30.435052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 08:06:30.437797 ==
8979 08:06:30.438264
8980 08:06:30.438624
8981 08:06:30.438968 TX Vref Scan disable
8982 08:06:30.441314 == TX Byte 0 ==
8983 08:06:30.445675 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8984 08:06:30.448001 == TX Byte 1 ==
8985 08:06:30.451374 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8986 08:06:30.451916 DramC Write-DBI off
8987 08:06:30.455061
8988 08:06:30.455611 [DATLAT]
8989 08:06:30.456071 Freq=1600, CH1 RK1
8990 08:06:30.456424
8991 08:06:30.457947 DATLAT Default: 0xf
8992 08:06:30.458410 0, 0xFFFF, sum = 0
8993 08:06:30.462070 1, 0xFFFF, sum = 0
8994 08:06:30.462660 2, 0xFFFF, sum = 0
8995 08:06:30.464470 3, 0xFFFF, sum = 0
8996 08:06:30.467822 4, 0xFFFF, sum = 0
8997 08:06:30.468297 5, 0xFFFF, sum = 0
8998 08:06:30.471699 6, 0xFFFF, sum = 0
8999 08:06:30.472318 7, 0xFFFF, sum = 0
9000 08:06:30.474740 8, 0xFFFF, sum = 0
9001 08:06:30.475306 9, 0xFFFF, sum = 0
9002 08:06:30.477590 10, 0xFFFF, sum = 0
9003 08:06:30.478063 11, 0xFFFF, sum = 0
9004 08:06:30.481544 12, 0xFFFF, sum = 0
9005 08:06:30.482107 13, 0xFFFF, sum = 0
9006 08:06:30.484977 14, 0x0, sum = 1
9007 08:06:30.485538 15, 0x0, sum = 2
9008 08:06:30.487959 16, 0x0, sum = 3
9009 08:06:30.488434 17, 0x0, sum = 4
9010 08:06:30.491838 best_step = 15
9011 08:06:30.492383
9012 08:06:30.492752 ==
9013 08:06:30.494187 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 08:06:30.497460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 08:06:30.497930 ==
9016 08:06:30.501183 RX Vref Scan: 0
9017 08:06:30.501736
9018 08:06:30.502099 RX Vref 0 -> 0, step: 1
9019 08:06:30.502445
9020 08:06:30.504030 RX Delay 11 -> 252, step: 4
9021 08:06:30.510772 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9022 08:06:30.514367 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9023 08:06:30.517270 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9024 08:06:30.521599 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9025 08:06:30.524339 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9026 08:06:30.530238 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9027 08:06:30.534616 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9028 08:06:30.537435 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9029 08:06:30.540920 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9030 08:06:30.544015 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9031 08:06:30.550343 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9032 08:06:30.553464 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9033 08:06:30.557355 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9034 08:06:30.560537 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9035 08:06:30.566603 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9036 08:06:30.570554 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9037 08:06:30.571115 ==
9038 08:06:30.573449 Dram Type= 6, Freq= 0, CH_1, rank 1
9039 08:06:30.576273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9040 08:06:30.576740 ==
9041 08:06:30.579927 DQS Delay:
9042 08:06:30.580391 DQS0 = 0, DQS1 = 0
9043 08:06:30.580759 DQM Delay:
9044 08:06:30.584353 DQM0 = 134, DQM1 = 127
9045 08:06:30.584909 DQ Delay:
9046 08:06:30.586359 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9047 08:06:30.589864 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9048 08:06:30.593493 DQ8 =114, DQ9 =116, DQ10 =126, DQ11 =118
9049 08:06:30.599809 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138
9050 08:06:30.600443
9051 08:06:30.600814
9052 08:06:30.601153
9053 08:06:30.602725 [DramC_TX_OE_Calibration] TA2
9054 08:06:30.606826 Original DQ_B0 (3 6) =30, OEN = 27
9055 08:06:30.607387 Original DQ_B1 (3 6) =30, OEN = 27
9056 08:06:30.609700 24, 0x0, End_B0=24 End_B1=24
9057 08:06:30.613255 25, 0x0, End_B0=25 End_B1=25
9058 08:06:30.616750 26, 0x0, End_B0=26 End_B1=26
9059 08:06:30.620442 27, 0x0, End_B0=27 End_B1=27
9060 08:06:30.621033 28, 0x0, End_B0=28 End_B1=28
9061 08:06:30.622859 29, 0x0, End_B0=29 End_B1=29
9062 08:06:30.625994 30, 0x0, End_B0=30 End_B1=30
9063 08:06:30.629520 31, 0x4141, End_B0=30 End_B1=30
9064 08:06:30.632609 Byte0 end_step=30 best_step=27
9065 08:06:30.635990 Byte1 end_step=30 best_step=27
9066 08:06:30.636542 Byte0 TX OE(2T, 0.5T) = (3, 3)
9067 08:06:30.639700 Byte1 TX OE(2T, 0.5T) = (3, 3)
9068 08:06:30.640254
9069 08:06:30.640623
9070 08:06:30.649640 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9071 08:06:30.650203 CH1 RK1: MR19=303, MR18=B07
9072 08:06:30.655556 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9073 08:06:30.659222 [RxdqsGatingPostProcess] freq 1600
9074 08:06:30.665611 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9075 08:06:30.669344 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 08:06:30.672493 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 08:06:30.676331 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 08:06:30.679889 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 08:06:30.680444 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 08:06:30.682989 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 08:06:30.686156 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 08:06:30.689661 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 08:06:30.692699 Pre-setting of DQS Precalculation
9084 08:06:30.698856 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9085 08:06:30.705743 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9086 08:06:30.712456 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9087 08:06:30.713034
9088 08:06:30.713400
9089 08:06:30.715673 [Calibration Summary] 3200 Mbps
9090 08:06:30.716485 CH 0, Rank 0
9091 08:06:30.718722 SW Impedance : PASS
9092 08:06:30.722240 DUTY Scan : NO K
9093 08:06:30.722744 ZQ Calibration : PASS
9094 08:06:30.725484 Jitter Meter : NO K
9095 08:06:30.728724 CBT Training : PASS
9096 08:06:30.729226 Write leveling : PASS
9097 08:06:30.732035 RX DQS gating : PASS
9098 08:06:30.735453 RX DQ/DQS(RDDQC) : PASS
9099 08:06:30.735945 TX DQ/DQS : PASS
9100 08:06:30.739007 RX DATLAT : PASS
9101 08:06:30.741889 RX DQ/DQS(Engine): PASS
9102 08:06:30.742454 TX OE : PASS
9103 08:06:30.745251 All Pass.
9104 08:06:30.745716
9105 08:06:30.746079 CH 0, Rank 1
9106 08:06:30.748476 SW Impedance : PASS
9107 08:06:30.749030 DUTY Scan : NO K
9108 08:06:30.752001 ZQ Calibration : PASS
9109 08:06:30.755676 Jitter Meter : NO K
9110 08:06:30.756189 CBT Training : PASS
9111 08:06:30.758745 Write leveling : PASS
9112 08:06:30.759299 RX DQS gating : PASS
9113 08:06:30.761839 RX DQ/DQS(RDDQC) : PASS
9114 08:06:30.764987 TX DQ/DQS : PASS
9115 08:06:30.765700 RX DATLAT : PASS
9116 08:06:30.768133 RX DQ/DQS(Engine): PASS
9117 08:06:30.771840 TX OE : PASS
9118 08:06:30.772305 All Pass.
9119 08:06:30.772676
9120 08:06:30.773016 CH 1, Rank 0
9121 08:06:30.774747 SW Impedance : PASS
9122 08:06:30.778420 DUTY Scan : NO K
9123 08:06:30.778982 ZQ Calibration : PASS
9124 08:06:30.781889 Jitter Meter : NO K
9125 08:06:30.785205 CBT Training : PASS
9126 08:06:30.785758 Write leveling : PASS
9127 08:06:30.788400 RX DQS gating : PASS
9128 08:06:30.791562 RX DQ/DQS(RDDQC) : PASS
9129 08:06:30.792225 TX DQ/DQS : PASS
9130 08:06:30.795897 RX DATLAT : PASS
9131 08:06:30.798620 RX DQ/DQS(Engine): PASS
9132 08:06:30.799174 TX OE : PASS
9133 08:06:30.801611 All Pass.
9134 08:06:30.802171
9135 08:06:30.802541 CH 1, Rank 1
9136 08:06:30.804801 SW Impedance : PASS
9137 08:06:30.805263 DUTY Scan : NO K
9138 08:06:30.808246 ZQ Calibration : PASS
9139 08:06:30.811414 Jitter Meter : NO K
9140 08:06:30.812014 CBT Training : PASS
9141 08:06:30.814781 Write leveling : PASS
9142 08:06:30.818341 RX DQS gating : PASS
9143 08:06:30.818900 RX DQ/DQS(RDDQC) : PASS
9144 08:06:30.821186 TX DQ/DQS : PASS
9145 08:06:30.824878 RX DATLAT : PASS
9146 08:06:30.825486 RX DQ/DQS(Engine): PASS
9147 08:06:30.827596 TX OE : PASS
9148 08:06:30.828245 All Pass.
9149 08:06:30.828624
9150 08:06:30.830884 DramC Write-DBI on
9151 08:06:30.834580 PER_BANK_REFRESH: Hybrid Mode
9152 08:06:30.835138 TX_TRACKING: ON
9153 08:06:30.844501 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9154 08:06:30.851080 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9155 08:06:30.857355 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9156 08:06:30.861198 [FAST_K] Save calibration result to emmc
9157 08:06:30.864222 sync common calibartion params.
9158 08:06:30.867680 sync cbt_mode0:1, 1:1
9159 08:06:30.870818 dram_init: ddr_geometry: 2
9160 08:06:30.871410 dram_init: ddr_geometry: 2
9161 08:06:30.874270 dram_init: ddr_geometry: 2
9162 08:06:30.877077 0:dram_rank_size:100000000
9163 08:06:30.880732 1:dram_rank_size:100000000
9164 08:06:30.883991 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9165 08:06:30.887133 DFS_SHUFFLE_HW_MODE: ON
9166 08:06:30.890605 dramc_set_vcore_voltage set vcore to 725000
9167 08:06:30.893559 Read voltage for 1600, 0
9168 08:06:30.894111 Vio18 = 0
9169 08:06:30.894483 Vcore = 725000
9170 08:06:30.897263 Vdram = 0
9171 08:06:30.897820 Vddq = 0
9172 08:06:30.898188 Vmddr = 0
9173 08:06:30.900441 switch to 3200 Mbps bootup
9174 08:06:30.904033 [DramcRunTimeConfig]
9175 08:06:30.904500 PHYPLL
9176 08:06:30.904868 DPM_CONTROL_AFTERK: ON
9177 08:06:30.906890 PER_BANK_REFRESH: ON
9178 08:06:30.910919 REFRESH_OVERHEAD_REDUCTION: ON
9179 08:06:30.911478 CMD_PICG_NEW_MODE: OFF
9180 08:06:30.913710 XRTWTW_NEW_MODE: ON
9181 08:06:30.917350 XRTRTR_NEW_MODE: ON
9182 08:06:30.917905 TX_TRACKING: ON
9183 08:06:30.920257 RDSEL_TRACKING: OFF
9184 08:06:30.920816 DQS Precalculation for DVFS: ON
9185 08:06:30.923565 RX_TRACKING: OFF
9186 08:06:30.924193 HW_GATING DBG: ON
9187 08:06:30.927365 ZQCS_ENABLE_LP4: ON
9188 08:06:30.929702 RX_PICG_NEW_MODE: ON
9189 08:06:30.930182 TX_PICG_NEW_MODE: ON
9190 08:06:30.933198 ENABLE_RX_DCM_DPHY: ON
9191 08:06:30.936390 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9192 08:06:30.936850 DUMMY_READ_FOR_TRACKING: OFF
9193 08:06:30.939156 !!! SPM_CONTROL_AFTERK: OFF
9194 08:06:30.942663 !!! SPM could not control APHY
9195 08:06:30.945807 IMPEDANCE_TRACKING: ON
9196 08:06:30.945889 TEMP_SENSOR: ON
9197 08:06:30.949138 HW_SAVE_FOR_SR: OFF
9198 08:06:30.952468 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9199 08:06:30.955879 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9200 08:06:30.956051 Read ODT Tracking: ON
9201 08:06:30.959602 Refresh Rate DeBounce: ON
9202 08:06:30.962447 DFS_NO_QUEUE_FLUSH: ON
9203 08:06:30.965741 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9204 08:06:30.965944 ENABLE_DFS_RUNTIME_MRW: OFF
9205 08:06:30.969603 DDR_RESERVE_NEW_MODE: ON
9206 08:06:30.972732 MR_CBT_SWITCH_FREQ: ON
9207 08:06:30.972933 =========================
9208 08:06:30.992773 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9209 08:06:30.996074 dram_init: ddr_geometry: 2
9210 08:06:31.014400 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9211 08:06:31.017361 dram_init: dram init end (result: 0)
9212 08:06:31.024059 DRAM-K: Full calibration passed in 24622 msecs
9213 08:06:31.027338 MRC: failed to locate region type 0.
9214 08:06:31.027631 DRAM rank0 size:0x100000000,
9215 08:06:31.030496 DRAM rank1 size=0x100000000
9216 08:06:31.040609 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9217 08:06:31.047272 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9218 08:06:31.053499 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9219 08:06:31.063474 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9220 08:06:31.063985 DRAM rank0 size:0x100000000,
9221 08:06:31.066627 DRAM rank1 size=0x100000000
9222 08:06:31.067003 CBMEM:
9223 08:06:31.070316 IMD: root @ 0xfffff000 254 entries.
9224 08:06:31.074116 IMD: root @ 0xffffec00 62 entries.
9225 08:06:31.077086 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9226 08:06:31.084105 WARNING: RO_VPD is uninitialized or empty.
9227 08:06:31.086954 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9228 08:06:31.094628 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9229 08:06:31.107217 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9230 08:06:31.118729 BS: romstage times (exec / console): total (unknown) / 24116 ms
9231 08:06:31.119288
9232 08:06:31.119648
9233 08:06:31.128523 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9234 08:06:31.131575 ARM64: Exception handlers installed.
9235 08:06:31.135238 ARM64: Testing exception
9236 08:06:31.138969 ARM64: Done test exception
9237 08:06:31.139526 Enumerating buses...
9238 08:06:31.141659 Show all devs... Before device enumeration.
9239 08:06:31.145239 Root Device: enabled 1
9240 08:06:31.148248 CPU_CLUSTER: 0: enabled 1
9241 08:06:31.148731 CPU: 00: enabled 1
9242 08:06:31.151569 Compare with tree...
9243 08:06:31.152105 Root Device: enabled 1
9244 08:06:31.154959 CPU_CLUSTER: 0: enabled 1
9245 08:06:31.158922 CPU: 00: enabled 1
9246 08:06:31.159475 Root Device scanning...
9247 08:06:31.161883 scan_static_bus for Root Device
9248 08:06:31.165236 CPU_CLUSTER: 0 enabled
9249 08:06:31.167987 scan_static_bus for Root Device done
9250 08:06:31.171852 scan_bus: bus Root Device finished in 8 msecs
9251 08:06:31.172406 done
9252 08:06:31.177911 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9253 08:06:31.180949 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9254 08:06:31.188165 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9255 08:06:31.191344 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9256 08:06:31.194750 Allocating resources...
9257 08:06:31.197968 Reading resources...
9258 08:06:31.201153 Root Device read_resources bus 0 link: 0
9259 08:06:31.204501 DRAM rank0 size:0x100000000,
9260 08:06:31.205070 DRAM rank1 size=0x100000000
9261 08:06:31.211103 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9262 08:06:31.211677 CPU: 00 missing read_resources
9263 08:06:31.217375 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9264 08:06:31.220687 Root Device read_resources bus 0 link: 0 done
9265 08:06:31.224177 Done reading resources.
9266 08:06:31.227382 Show resources in subtree (Root Device)...After reading.
9267 08:06:31.230537 Root Device child on link 0 CPU_CLUSTER: 0
9268 08:06:31.233855 CPU_CLUSTER: 0 child on link 0 CPU: 00
9269 08:06:31.244325 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9270 08:06:31.244881 CPU: 00
9271 08:06:31.247329 Root Device assign_resources, bus 0 link: 0
9272 08:06:31.250911 CPU_CLUSTER: 0 missing set_resources
9273 08:06:31.256709 Root Device assign_resources, bus 0 link: 0 done
9274 08:06:31.257258 Done setting resources.
9275 08:06:31.264175 Show resources in subtree (Root Device)...After assigning values.
9276 08:06:31.267092 Root Device child on link 0 CPU_CLUSTER: 0
9277 08:06:31.270732 CPU_CLUSTER: 0 child on link 0 CPU: 00
9278 08:06:31.280609 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9279 08:06:31.281160 CPU: 00
9280 08:06:31.283517 Done allocating resources.
9281 08:06:31.289869 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9282 08:06:31.290440 Enabling resources...
9283 08:06:31.293054 done.
9284 08:06:31.296648 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9285 08:06:31.300027 Initializing devices...
9286 08:06:31.300581 Root Device init
9287 08:06:31.302845 init hardware done!
9288 08:06:31.303395 0x00000018: ctrlr->caps
9289 08:06:31.305950 52.000 MHz: ctrlr->f_max
9290 08:06:31.309254 0.400 MHz: ctrlr->f_min
9291 08:06:31.312673 0x40ff8080: ctrlr->voltages
9292 08:06:31.313242 sclk: 390625
9293 08:06:31.313604 Bus Width = 1
9294 08:06:31.316704 sclk: 390625
9295 08:06:31.317324 Bus Width = 1
9296 08:06:31.319490 Early init status = 3
9297 08:06:31.322503 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9298 08:06:31.327428 in-header: 03 fc 00 00 01 00 00 00
9299 08:06:31.330221 in-data: 00
9300 08:06:31.333022 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9301 08:06:31.338845 in-header: 03 fd 00 00 00 00 00 00
9302 08:06:31.342248 in-data:
9303 08:06:31.345781 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9304 08:06:31.349524 in-header: 03 fc 00 00 01 00 00 00
9305 08:06:31.352629 in-data: 00
9306 08:06:31.355913 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9307 08:06:31.361633 in-header: 03 fd 00 00 00 00 00 00
9308 08:06:31.364245 in-data:
9309 08:06:31.367181 [SSUSB] Setting up USB HOST controller...
9310 08:06:31.370591 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9311 08:06:31.374041 [SSUSB] phy power-on done.
9312 08:06:31.377182 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9313 08:06:31.384195 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9314 08:06:31.387540 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9315 08:06:31.393856 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9316 08:06:31.400471 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9317 08:06:31.407183 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9318 08:06:31.413473 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9319 08:06:31.420056 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9320 08:06:31.423488 SPM: binary array size = 0x9dc
9321 08:06:31.426827 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9322 08:06:31.433041 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9323 08:06:31.440273 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9324 08:06:31.446219 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9325 08:06:31.449495 configure_display: Starting display init
9326 08:06:31.484136 anx7625_power_on_init: Init interface.
9327 08:06:31.487491 anx7625_disable_pd_protocol: Disabled PD feature.
9328 08:06:31.490637 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9329 08:06:31.519185 anx7625_start_dp_work: Secure OCM version=00
9330 08:06:31.521942 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9331 08:06:31.536881 sp_tx_get_edid_block: EDID Block = 1
9332 08:06:31.639500 Extracted contents:
9333 08:06:31.642267 header: 00 ff ff ff ff ff ff 00
9334 08:06:31.646173 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9335 08:06:31.649041 version: 01 04
9336 08:06:31.652450 basic params: 95 1f 11 78 0a
9337 08:06:31.656101 chroma info: 76 90 94 55 54 90 27 21 50 54
9338 08:06:31.658687 established: 00 00 00
9339 08:06:31.665330 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9340 08:06:31.669188 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9341 08:06:31.675410 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 08:06:31.682638 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9343 08:06:31.688823 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9344 08:06:31.691768 extensions: 00
9345 08:06:31.692237 checksum: fb
9346 08:06:31.692607
9347 08:06:31.695353 Manufacturer: IVO Model 57d Serial Number 0
9348 08:06:31.699057 Made week 0 of 2020
9349 08:06:31.699618 EDID version: 1.4
9350 08:06:31.702922 Digital display
9351 08:06:31.705414 6 bits per primary color channel
9352 08:06:31.705989 DisplayPort interface
9353 08:06:31.708569 Maximum image size: 31 cm x 17 cm
9354 08:06:31.712669 Gamma: 220%
9355 08:06:31.713239 Check DPMS levels
9356 08:06:31.715581 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9357 08:06:31.721462 First detailed timing is preferred timing
9358 08:06:31.721929 Established timings supported:
9359 08:06:31.725321 Standard timings supported:
9360 08:06:31.728457 Detailed timings
9361 08:06:31.731358 Hex of detail: 383680a07038204018303c0035ae10000019
9362 08:06:31.738225 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9363 08:06:31.741748 0780 0798 07c8 0820 hborder 0
9364 08:06:31.745308 0438 043b 0447 0458 vborder 0
9365 08:06:31.748104 -hsync -vsync
9366 08:06:31.748564 Did detailed timing
9367 08:06:31.755048 Hex of detail: 000000000000000000000000000000000000
9368 08:06:31.757973 Manufacturer-specified data, tag 0
9369 08:06:31.761397 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9370 08:06:31.764640 ASCII string: InfoVision
9371 08:06:31.768421 Hex of detail: 000000fe00523134304e574635205248200a
9372 08:06:31.771591 ASCII string: R140NWF5 RH
9373 08:06:31.772218 Checksum
9374 08:06:31.774765 Checksum: 0xfb (valid)
9375 08:06:31.777971 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9376 08:06:31.781076 DSI data_rate: 832800000 bps
9377 08:06:31.787335 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9378 08:06:31.791064 anx7625_parse_edid: pixelclock(138800).
9379 08:06:31.795264 hactive(1920), hsync(48), hfp(24), hbp(88)
9380 08:06:31.797895 vactive(1080), vsync(12), vfp(3), vbp(17)
9381 08:06:31.801439 anx7625_dsi_config: config dsi.
9382 08:06:31.807802 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9383 08:06:31.821448 anx7625_dsi_config: success to config DSI
9384 08:06:31.824370 anx7625_dp_start: MIPI phy setup OK.
9385 08:06:31.827792 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9386 08:06:31.830981 mtk_ddp_mode_set invalid vrefresh 60
9387 08:06:31.834204 main_disp_path_setup
9388 08:06:31.834679 ovl_layer_smi_id_en
9389 08:06:31.837499 ovl_layer_smi_id_en
9390 08:06:31.838081 ccorr_config
9391 08:06:31.838572 aal_config
9392 08:06:31.840643 gamma_config
9393 08:06:31.841123 postmask_config
9394 08:06:31.844292 dither_config
9395 08:06:31.847403 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9396 08:06:31.853804 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9397 08:06:31.857308 Root Device init finished in 553 msecs
9398 08:06:31.860552 CPU_CLUSTER: 0 init
9399 08:06:31.867399 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9400 08:06:31.874044 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9401 08:06:31.874601 APU_MBOX 0x190000b0 = 0x10001
9402 08:06:31.877262 APU_MBOX 0x190001b0 = 0x10001
9403 08:06:31.880425 APU_MBOX 0x190005b0 = 0x10001
9404 08:06:31.884348 APU_MBOX 0x190006b0 = 0x10001
9405 08:06:31.890482 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9406 08:06:31.900085 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9407 08:06:31.912355 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9408 08:06:31.919118 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9409 08:06:31.931267 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9410 08:06:31.939668 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9411 08:06:31.943226 CPU_CLUSTER: 0 init finished in 81 msecs
9412 08:06:31.946794 Devices initialized
9413 08:06:31.950096 Show all devs... After init.
9414 08:06:31.950558 Root Device: enabled 1
9415 08:06:31.953603 CPU_CLUSTER: 0: enabled 1
9416 08:06:31.956171 CPU: 00: enabled 1
9417 08:06:31.959796 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9418 08:06:31.963180 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9419 08:06:31.966135 ELOG: NV offset 0x57f000 size 0x1000
9420 08:06:31.972945 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9421 08:06:31.979457 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9422 08:06:31.982651 ELOG: Event(17) added with size 13 at 2023-09-21 08:06:33 UTC
9423 08:06:31.989424 out: cmd=0x121: 03 db 21 01 00 00 00 00
9424 08:06:31.993070 in-header: 03 c9 00 00 2c 00 00 00
9425 08:06:32.006145 in-data: 96 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9426 08:06:32.009676 ELOG: Event(A1) added with size 10 at 2023-09-21 08:06:33 UTC
9427 08:06:32.016706 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9428 08:06:32.022297 ELOG: Event(A0) added with size 9 at 2023-09-21 08:06:33 UTC
9429 08:06:32.025468 elog_add_boot_reason: Logged dev mode boot
9430 08:06:32.031981 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9431 08:06:32.032553 Finalize devices...
9432 08:06:32.035556 Devices finalized
9433 08:06:32.039417 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9434 08:06:32.042177 Writing coreboot table at 0xffe64000
9435 08:06:32.048904 0. 000000000010a000-0000000000113fff: RAMSTAGE
9436 08:06:32.051825 1. 0000000040000000-00000000400fffff: RAM
9437 08:06:32.055617 2. 0000000040100000-000000004032afff: RAMSTAGE
9438 08:06:32.059203 3. 000000004032b000-00000000545fffff: RAM
9439 08:06:32.061583 4. 0000000054600000-000000005465ffff: BL31
9440 08:06:32.068841 5. 0000000054660000-00000000ffe63fff: RAM
9441 08:06:32.071785 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9442 08:06:32.075780 7. 0000000100000000-000000023fffffff: RAM
9443 08:06:32.078782 Passing 5 GPIOs to payload:
9444 08:06:32.082023 NAME | PORT | POLARITY | VALUE
9445 08:06:32.088234 EC in RW | 0x000000aa | low | undefined
9446 08:06:32.091675 EC interrupt | 0x00000005 | low | undefined
9447 08:06:32.099121 TPM interrupt | 0x000000ab | high | undefined
9448 08:06:32.101506 SD card detect | 0x00000011 | high | undefined
9449 08:06:32.104895 speaker enable | 0x00000093 | high | undefined
9450 08:06:32.112072 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9451 08:06:32.114852 in-header: 03 f9 00 00 02 00 00 00
9452 08:06:32.115440 in-data: 02 00
9453 08:06:32.118742 ADC[4]: Raw value=901922 ID=7
9454 08:06:32.121313 ADC[3]: Raw value=214021 ID=1
9455 08:06:32.121872 RAM Code: 0x71
9456 08:06:32.124649 ADC[6]: Raw value=75036 ID=0
9457 08:06:32.127954 ADC[5]: Raw value=212543 ID=1
9458 08:06:32.128503 SKU Code: 0x1
9459 08:06:32.134763 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a16d
9460 08:06:32.138260 coreboot table: 964 bytes.
9461 08:06:32.141474 IMD ROOT 0. 0xfffff000 0x00001000
9462 08:06:32.144656 IMD SMALL 1. 0xffffe000 0x00001000
9463 08:06:32.148128 RO MCACHE 2. 0xffffc000 0x00001104
9464 08:06:32.151485 CONSOLE 3. 0xfff7c000 0x00080000
9465 08:06:32.154810 FMAP 4. 0xfff7b000 0x00000452
9466 08:06:32.155358 TIME STAMP 5. 0xfff7a000 0x00000910
9467 08:06:32.157348 VBOOT WORK 6. 0xfff66000 0x00014000
9468 08:06:32.161593 RAMOOPS 7. 0xffe66000 0x00100000
9469 08:06:32.164039 COREBOOT 8. 0xffe64000 0x00002000
9470 08:06:32.167697 IMD small region:
9471 08:06:32.170895 IMD ROOT 0. 0xffffec00 0x00000400
9472 08:06:32.174902 VPD 1. 0xffffeb80 0x0000006c
9473 08:06:32.178137 MMC STATUS 2. 0xffffeb60 0x00000004
9474 08:06:32.183975 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9475 08:06:32.184442 Probing TPM: done!
9476 08:06:32.191195 Connected to device vid:did:rid of 1ae0:0028:00
9477 08:06:32.197559 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9478 08:06:32.201523 Initialized TPM device CR50 revision 0
9479 08:06:32.204793 Checking cr50 for pending updates
9480 08:06:32.210481 Reading cr50 TPM mode
9481 08:06:32.219005 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9482 08:06:32.225162 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 08:06:32.266013 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9484 08:06:32.268499 Checking segment from ROM address 0x40100000
9485 08:06:32.272034 Checking segment from ROM address 0x4010001c
9486 08:06:32.278576 Loading segment from ROM address 0x40100000
9487 08:06:32.279132 code (compression=0)
9488 08:06:32.288433 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 08:06:32.295935 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 08:06:32.296490 it's not compressed!
9491 08:06:32.301910 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 08:06:32.308471 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 08:06:32.326054 Loading segment from ROM address 0x4010001c
9494 08:06:32.326609 Entry Point 0x80000000
9495 08:06:32.328998 Loaded segments
9496 08:06:32.332546 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 08:06:32.339074 Jumping to boot code at 0x80000000(0xffe64000)
9498 08:06:32.345770 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 08:06:32.352292 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 08:06:32.360519 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9501 08:06:32.363588 Checking segment from ROM address 0x40100000
9502 08:06:32.367445 Checking segment from ROM address 0x4010001c
9503 08:06:32.374621 Loading segment from ROM address 0x40100000
9504 08:06:32.375176 code (compression=1)
9505 08:06:32.380240 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 08:06:32.390280 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 08:06:32.390839 using LZMA
9508 08:06:32.399373 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 08:06:32.405434 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 08:06:32.408684 Loading segment from ROM address 0x4010001c
9511 08:06:32.409239 Entry Point 0x54601000
9512 08:06:32.412334 Loaded segments
9513 08:06:32.415264 NOTICE: MT8192 bl31_setup
9514 08:06:32.422449 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 08:06:32.425619 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 08:06:32.429015 WARNING: region 0:
9517 08:06:32.432278 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 08:06:32.432836 WARNING: region 1:
9519 08:06:32.439178 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 08:06:32.442415 WARNING: region 2:
9521 08:06:32.445290 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 08:06:32.448998 WARNING: region 3:
9523 08:06:32.452438 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 08:06:32.455357 WARNING: region 4:
9525 08:06:32.462089 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 08:06:32.462810 WARNING: region 5:
9527 08:06:32.465347 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 08:06:32.469103 WARNING: region 6:
9529 08:06:32.472128 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 08:06:32.475145 WARNING: region 7:
9531 08:06:32.478431 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 08:06:32.485421 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 08:06:32.489131 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 08:06:32.492214 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 08:06:32.498527 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 08:06:32.502198 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 08:06:32.505699 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 08:06:32.512307 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 08:06:32.516363 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 08:06:32.522684 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 08:06:32.525611 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 08:06:32.528694 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 08:06:32.535270 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 08:06:32.538400 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 08:06:32.541751 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 08:06:32.548743 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 08:06:32.551907 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 08:06:32.558798 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 08:06:32.561781 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 08:06:32.565254 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 08:06:32.571849 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 08:06:32.575294 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 08:06:32.581873 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 08:06:32.584771 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 08:06:32.588326 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 08:06:32.594764 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 08:06:32.598225 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 08:06:32.604967 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 08:06:32.608177 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 08:06:32.611618 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 08:06:32.618597 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 08:06:32.622705 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 08:06:32.628141 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 08:06:32.631558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 08:06:32.635229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 08:06:32.638136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 08:06:32.644677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 08:06:32.648108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 08:06:32.651553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 08:06:32.654696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 08:06:32.661392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 08:06:32.665146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 08:06:32.667861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 08:06:32.671317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 08:06:32.678166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 08:06:32.681363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 08:06:32.684393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 08:06:32.687777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 08:06:32.694883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 08:06:32.697789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 08:06:32.705307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 08:06:32.707499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 08:06:32.711773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 08:06:32.718036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 08:06:32.721606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 08:06:32.727885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 08:06:32.731422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 08:06:32.734077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 08:06:32.741299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 08:06:32.744326 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 08:06:32.750913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 08:06:32.754177 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 08:06:32.761035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 08:06:32.764486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 08:06:32.771146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 08:06:32.774164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 08:06:32.780624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 08:06:32.784472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 08:06:32.787517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 08:06:32.794215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 08:06:32.797300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 08:06:32.803882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 08:06:32.807589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 08:06:32.813967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 08:06:32.817256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 08:06:32.820691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 08:06:32.827036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 08:06:32.830601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 08:06:32.837180 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 08:06:32.840554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 08:06:32.848397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 08:06:32.850052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 08:06:32.857171 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 08:06:32.860994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 08:06:32.864112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 08:06:32.870165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 08:06:32.873608 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 08:06:32.880204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 08:06:32.883952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 08:06:32.890217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 08:06:32.893689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 08:06:32.896626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 08:06:32.903122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 08:06:32.906469 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 08:06:32.913412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 08:06:32.916895 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 08:06:32.923586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 08:06:32.926689 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 08:06:32.929983 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 08:06:32.933091 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 08:06:32.940661 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 08:06:32.943076 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 08:06:32.946548 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 08:06:32.953143 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 08:06:32.956284 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 08:06:32.962948 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 08:06:32.966407 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 08:06:32.969866 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 08:06:32.977213 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 08:06:32.979870 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 08:06:32.986280 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 08:06:32.989441 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 08:06:32.993599 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 08:06:32.999983 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 08:06:33.002607 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 08:06:33.009096 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 08:06:33.012697 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 08:06:33.015666 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 08:06:33.022298 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 08:06:33.026002 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 08:06:33.029119 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 08:06:33.032952 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 08:06:33.039381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 08:06:33.042418 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 08:06:33.046252 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 08:06:33.052731 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 08:06:33.055612 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 08:06:33.058822 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 08:06:33.065695 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 08:06:33.069130 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 08:06:33.076221 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 08:06:33.079323 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 08:06:33.082511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 08:06:33.089075 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 08:06:33.092294 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 08:06:33.098947 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 08:06:33.102830 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 08:06:33.105972 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 08:06:33.112967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 08:06:33.115708 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 08:06:33.118948 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 08:06:33.125473 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 08:06:33.128607 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 08:06:33.135413 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 08:06:33.138994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 08:06:33.142005 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 08:06:33.149587 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 08:06:33.151888 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 08:06:33.158367 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 08:06:33.161884 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 08:06:33.165033 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 08:06:33.172092 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 08:06:33.175270 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 08:06:33.181780 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 08:06:33.185314 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 08:06:33.188374 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 08:06:33.195421 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 08:06:33.198555 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 08:06:33.205056 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 08:06:33.208647 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 08:06:33.211470 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 08:06:33.219292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 08:06:33.221727 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 08:06:33.228879 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 08:06:33.231382 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 08:06:33.234943 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 08:06:33.241143 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 08:06:33.244666 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 08:06:33.251400 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 08:06:33.254257 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 08:06:33.257441 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 08:06:33.264506 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 08:06:33.267656 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 08:06:33.274677 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 08:06:33.277588 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 08:06:33.280598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 08:06:33.287545 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 08:06:33.290693 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 08:06:33.297647 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 08:06:33.300677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 08:06:33.304153 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 08:06:33.310109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 08:06:33.313951 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 08:06:33.320781 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 08:06:33.324155 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 08:06:33.327037 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 08:06:33.333811 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 08:06:33.336896 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 08:06:33.344115 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 08:06:33.346485 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 08:06:33.350192 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 08:06:33.356698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 08:06:33.359959 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 08:06:33.366303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 08:06:33.369720 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 08:06:33.376172 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 08:06:33.380028 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 08:06:33.383581 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 08:06:33.389827 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 08:06:33.392635 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 08:06:33.399532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 08:06:33.402449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 08:06:33.409128 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 08:06:33.412701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 08:06:33.415925 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 08:06:33.422826 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 08:06:33.426625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 08:06:33.433366 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 08:06:33.435901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 08:06:33.442392 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 08:06:33.445885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 08:06:33.448905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 08:06:33.455656 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 08:06:33.458827 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 08:06:33.465964 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 08:06:33.469065 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 08:06:33.472122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 08:06:33.478576 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 08:06:33.482223 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 08:06:33.488980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 08:06:33.492736 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 08:06:33.498576 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 08:06:33.502046 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 08:06:33.505100 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 08:06:33.512001 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 08:06:33.515240 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 08:06:33.522312 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 08:06:33.524946 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 08:06:33.532125 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 08:06:33.535261 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 08:06:33.538869 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 08:06:33.541686 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 08:06:33.548385 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 08:06:33.551452 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 08:06:33.554684 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 08:06:33.561244 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 08:06:33.564187 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 08:06:33.567506 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 08:06:33.574304 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 08:06:33.577587 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 08:06:33.580905 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 08:06:33.587352 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 08:06:33.591253 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 08:06:33.597438 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 08:06:33.600718 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 08:06:33.604441 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 08:06:33.610682 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 08:06:33.614332 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 08:06:33.621013 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 08:06:33.623893 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 08:06:33.627176 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 08:06:33.633455 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 08:06:33.636881 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 08:06:33.640369 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 08:06:33.647787 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 08:06:33.650083 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 08:06:33.656687 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 08:06:33.659791 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 08:06:33.663324 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 08:06:33.669726 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 08:06:33.673260 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 08:06:33.677132 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 08:06:33.683083 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 08:06:33.686525 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 08:06:33.689274 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 08:06:33.696211 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 08:06:33.699220 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 08:06:33.706182 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 08:06:33.709493 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 08:06:33.712348 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 08:06:33.719785 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 08:06:33.722866 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 08:06:33.725981 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 08:06:33.729237 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 08:06:33.732427 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 08:06:33.738837 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 08:06:33.743016 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 08:06:33.746191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 08:06:33.749340 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 08:06:33.755901 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 08:06:33.759283 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 08:06:33.762586 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 08:06:33.769557 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 08:06:33.771978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 08:06:33.776198 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 08:06:33.782364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 08:06:33.785848 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 08:06:33.792694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 08:06:33.795466 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 08:06:33.802005 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 08:06:33.805249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 08:06:33.808585 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 08:06:33.815438 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 08:06:33.818798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 08:06:33.825029 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 08:06:33.828658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 08:06:33.835126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 08:06:33.838794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 08:06:33.841582 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 08:06:33.848239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 08:06:33.851325 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 08:06:33.858421 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 08:06:33.861252 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 08:06:33.864732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 08:06:33.871321 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 08:06:33.875603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 08:06:33.880957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 08:06:33.884479 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 08:06:33.887466 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 08:06:33.894881 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 08:06:33.897808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 08:06:33.904399 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 08:06:33.907421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 08:06:33.914133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 08:06:33.917344 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 08:06:33.920446 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 08:06:33.927459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 08:06:33.930434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 08:06:33.937651 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 08:06:33.940498 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 08:06:33.946918 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 08:06:33.950345 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 08:06:33.953567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 08:06:33.960078 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 08:06:33.963346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 08:06:33.970526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 08:06:33.972969 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 08:06:33.980189 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 08:06:33.983136 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 08:06:33.986845 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 08:06:33.993448 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 08:06:33.996573 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 08:06:34.000129 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 08:06:34.006840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 08:06:34.010190 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 08:06:34.016352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 08:06:34.019588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 08:06:34.026854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 08:06:34.029288 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 08:06:34.032605 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 08:06:34.039298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 08:06:34.042487 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 08:06:34.049567 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 08:06:34.052944 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 08:06:34.059341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 08:06:34.062608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 08:06:34.065498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 08:06:34.072345 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 08:06:34.075133 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 08:06:34.082269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 08:06:34.085393 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 08:06:34.089238 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 08:06:34.095590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 08:06:34.098721 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 08:06:34.105872 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 08:06:34.108431 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 08:06:34.115209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 08:06:34.119533 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 08:06:34.121994 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 08:06:34.128727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 08:06:34.131794 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 08:06:34.138123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 08:06:34.141259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 08:06:34.148115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 08:06:34.152006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 08:06:34.158002 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 08:06:34.161952 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 08:06:34.164632 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 08:06:34.171277 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 08:06:34.174408 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 08:06:34.181198 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 08:06:34.184249 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 08:06:34.191277 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 08:06:34.195131 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 08:06:34.201076 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 08:06:34.204566 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 08:06:34.207875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 08:06:34.214892 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 08:06:34.218130 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 08:06:34.224238 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 08:06:34.227315 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 08:06:34.234042 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 08:06:34.237384 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 08:06:34.244525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 08:06:34.247211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 08:06:34.253631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 08:06:34.256596 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 08:06:34.260211 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 08:06:34.266563 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 08:06:34.269923 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 08:06:34.276976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 08:06:34.280000 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 08:06:34.286826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 08:06:34.290484 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 08:06:34.293028 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 08:06:34.299804 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 08:06:34.303359 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 08:06:34.310760 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 08:06:34.313785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 08:06:34.320175 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 08:06:34.323356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 08:06:34.329826 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 08:06:34.332830 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 08:06:34.336805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 08:06:34.343371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 08:06:34.346504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 08:06:34.353436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 08:06:34.356745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 08:06:34.362348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 08:06:34.365870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 08:06:34.372550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 08:06:34.375649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 08:06:34.382655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 08:06:34.385840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 08:06:34.392391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 08:06:34.395879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 08:06:34.398981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 08:06:34.405856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 08:06:34.408769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 08:06:34.415677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 08:06:34.418776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 08:06:34.426119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 08:06:34.428634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 08:06:34.435303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 08:06:34.438581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 08:06:34.445546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 08:06:34.448636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 08:06:34.455596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 08:06:34.458853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 08:06:34.465318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 08:06:34.468437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 08:06:34.475398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 08:06:34.483206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 08:06:34.484732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 08:06:34.491716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 08:06:34.495872 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 08:06:34.496390 INFO: [APUAPC] vio 0
9968 08:06:34.502990 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 08:06:34.505634 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 08:06:34.508916 INFO: [APUAPC] D0_APC_0: 0x400510
9971 08:06:34.512305 INFO: [APUAPC] D0_APC_1: 0x0
9972 08:06:34.515162 INFO: [APUAPC] D0_APC_2: 0x1540
9973 08:06:34.518517 INFO: [APUAPC] D0_APC_3: 0x0
9974 08:06:34.521945 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 08:06:34.525336 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 08:06:34.529441 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 08:06:34.532009 INFO: [APUAPC] D1_APC_3: 0x0
9978 08:06:34.535475 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 08:06:34.538207 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 08:06:34.541736 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 08:06:34.545154 INFO: [APUAPC] D2_APC_3: 0x0
9982 08:06:34.548641 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 08:06:34.551686 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 08:06:34.555900 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 08:06:34.559182 INFO: [APUAPC] D3_APC_3: 0x0
9986 08:06:34.561617 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 08:06:34.564852 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 08:06:34.568075 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 08:06:34.571383 INFO: [APUAPC] D4_APC_3: 0x0
9990 08:06:34.574965 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 08:06:34.577892 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 08:06:34.581284 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 08:06:34.584788 INFO: [APUAPC] D5_APC_3: 0x0
9994 08:06:34.588602 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 08:06:34.591167 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 08:06:34.594528 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 08:06:34.595082 INFO: [APUAPC] D6_APC_3: 0x0
9998 08:06:34.597965 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 08:06:34.604677 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 08:06:34.607930 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 08:06:34.608535 INFO: [APUAPC] D7_APC_3: 0x0
10002 08:06:34.611356 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 08:06:34.614469 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 08:06:34.618117 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 08:06:34.621045 INFO: [APUAPC] D8_APC_3: 0x0
10006 08:06:34.624192 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 08:06:34.627993 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 08:06:34.631435 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 08:06:34.634390 INFO: [APUAPC] D9_APC_3: 0x0
10010 08:06:34.637405 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 08:06:34.640632 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 08:06:34.644384 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 08:06:34.647535 INFO: [APUAPC] D10_APC_3: 0x0
10014 08:06:34.651066 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 08:06:34.654071 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 08:06:34.657489 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 08:06:34.660677 INFO: [APUAPC] D11_APC_3: 0x0
10018 08:06:34.664579 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 08:06:34.667476 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 08:06:34.673700 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 08:06:34.674271 INFO: [APUAPC] D12_APC_3: 0x0
10022 08:06:34.676868 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 08:06:34.683895 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 08:06:34.687416 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 08:06:34.687931 INFO: [APUAPC] D13_APC_3: 0x0
10026 08:06:34.694501 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 08:06:34.696786 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 08:06:34.700389 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 08:06:34.703579 INFO: [APUAPC] D14_APC_3: 0x0
10030 08:06:34.707050 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 08:06:34.710280 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 08:06:34.713966 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 08:06:34.716793 INFO: [APUAPC] D15_APC_3: 0x0
10034 08:06:34.717371 INFO: [APUAPC] APC_CON: 0x4
10035 08:06:34.720367 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 08:06:34.723639 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 08:06:34.727035 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 08:06:34.730548 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 08:06:34.733206 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 08:06:34.736924 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 08:06:34.739694 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 08:06:34.743274 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 08:06:34.746329 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 08:06:34.749526 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 08:06:34.750034 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 08:06:34.752993 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 08:06:34.756722 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 08:06:34.759563 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 08:06:34.763162 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 08:06:34.766256 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 08:06:34.769834 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 08:06:34.772943 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 08:06:34.776110 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 08:06:34.779034 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 08:06:34.782920 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 08:06:34.785968 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 08:06:34.786432 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 08:06:34.789435 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 08:06:34.792543 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 08:06:34.795866 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 08:06:34.799693 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 08:06:34.802754 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 08:06:34.806936 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 08:06:34.809423 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 08:06:34.813503 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 08:06:34.815938 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 08:06:34.820514 INFO: [NOCDAPC] APC_CON: 0x4
10068 08:06:34.823140 INFO: [APUAPC] set_apusys_apc done
10069 08:06:34.825888 INFO: [DEVAPC] devapc_init done
10070 08:06:34.829590 INFO: GICv3 without legacy support detected.
10071 08:06:34.832259 INFO: ARM GICv3 driver initialized in EL3
10072 08:06:34.835483 INFO: Maximum SPI INTID supported: 639
10073 08:06:34.839356 INFO: BL31: Initializing runtime services
10074 08:06:34.845611 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 08:06:34.848793 INFO: SPM: enable CPC mode
10076 08:06:34.855533 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 08:06:34.858729 INFO: BL31: Preparing for EL3 exit to normal world
10078 08:06:34.862015 INFO: Entry point address = 0x80000000
10079 08:06:34.865081 INFO: SPSR = 0x8
10080 08:06:34.870517
10081 08:06:34.871031
10082 08:06:34.871365
10083 08:06:34.874267 Starting depthcharge on Spherion...
10084 08:06:34.874786
10085 08:06:34.875117 Wipe memory regions:
10086 08:06:34.875426
10087 08:06:34.878067 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10088 08:06:34.878610 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10089 08:06:34.879024 Setting prompt string to ['asurada:']
10090 08:06:34.879422 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10091 08:06:34.880128 [0x00000040000000, 0x00000054600000)
10092 08:06:34.999774
10093 08:06:35.000408 [0x00000054660000, 0x00000080000000)
10094 08:06:35.260266
10095 08:06:35.260820 [0x000000821a7280, 0x000000ffe64000)
10096 08:06:36.004705
10097 08:06:36.008338 [0x00000100000000, 0x00000240000000)
10098 08:06:37.896265
10099 08:06:37.898410 Initializing XHCI USB controller at 0x11200000.
10100 08:06:38.880528
10101 08:06:38.881085 R8152: Initializing
10102 08:06:38.881447
10103 08:06:38.883938 Version 9 (ocp_data = 6010)
10104 08:06:38.884488
10105 08:06:38.886661 R8152: Done initializing
10106 08:06:38.887219
10107 08:06:38.887813 Adding net device
10108 08:06:39.408536
10109 08:06:39.411382 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10110 08:06:39.411874
10111 08:06:39.412237
10112 08:06:39.412569
10113 08:06:39.413394 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10115 08:06:39.514826 asurada: tftpboot 192.168.201.1 11585986/tftp-deploy-5pxa7njy/kernel/image.itb 11585986/tftp-deploy-5pxa7njy/kernel/cmdline
10116 08:06:39.515708 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10117 08:06:39.516212 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10118 08:06:39.520434 tftpboot 192.168.201.1 11585986/tftp-deploy-5pxa7njy/kernel/image.itp-deploy-5pxa7njy/kernel/cmdline
10119 08:06:39.520899
10120 08:06:39.521259 Waiting for link
10121 08:06:39.723063
10122 08:06:39.723905 done.
10123 08:06:39.724348
10124 08:06:39.724779 MAC: f4:f5:e8:50:de:0a
10125 08:06:39.725223
10126 08:06:39.726219 Sending DHCP discover... done.
10127 08:06:39.726674
10128 08:06:39.730029 Waiting for reply... done.
10129 08:06:39.730727
10130 08:06:39.732663 Sending DHCP request... done.
10131 08:06:39.733121
10132 08:06:39.738145 Waiting for reply... done.
10133 08:06:39.738700
10134 08:06:39.739066 My ip is 192.168.201.14
10135 08:06:39.739409
10136 08:06:39.741176 The DHCP server ip is 192.168.201.1
10137 08:06:39.741733
10138 08:06:39.747693 TFTP server IP predefined by user: 192.168.201.1
10139 08:06:39.748295
10140 08:06:39.754493 Bootfile predefined by user: 11585986/tftp-deploy-5pxa7njy/kernel/image.itb
10141 08:06:39.755053
10142 08:06:39.757355 Sending tftp read request... done.
10143 08:06:39.757818
10144 08:06:39.764338 Waiting for the transfer...
10145 08:06:39.764904
10146 08:06:40.046173 00000000 ################################################################
10147 08:06:40.046320
10148 08:06:40.315575 00080000 ################################################################
10149 08:06:40.315720
10150 08:06:40.561519 00100000 ################################################################
10151 08:06:40.561662
10152 08:06:40.809472 00180000 ################################################################
10153 08:06:40.809640
10154 08:06:41.071982 00200000 ################################################################
10155 08:06:41.072118
10156 08:06:41.327766 00280000 ################################################################
10157 08:06:41.327909
10158 08:06:41.572377 00300000 ################################################################
10159 08:06:41.572524
10160 08:06:41.836131 00380000 ################################################################
10161 08:06:41.836281
10162 08:06:42.076222 00400000 ################################################################
10163 08:06:42.076362
10164 08:06:42.308639 00480000 ################################################################
10165 08:06:42.308776
10166 08:06:42.560782 00500000 ################################################################
10167 08:06:42.560933
10168 08:06:42.807787 00580000 ################################################################
10169 08:06:42.807938
10170 08:06:43.079311 00600000 ################################################################
10171 08:06:43.079454
10172 08:06:43.334203 00680000 ################################################################
10173 08:06:43.334381
10174 08:06:43.584491 00700000 ################################################################
10175 08:06:43.584641
10176 08:06:43.820036 00780000 ################################################################
10177 08:06:43.820176
10178 08:06:44.069877 00800000 ################################################################
10179 08:06:44.070015
10180 08:06:44.321935 00880000 ################################################################
10181 08:06:44.322087
10182 08:06:44.549835 00900000 ################################################################
10183 08:06:44.549990
10184 08:06:44.804616 00980000 ################################################################
10185 08:06:44.804754
10186 08:06:45.074137 00a00000 ################################################################
10187 08:06:45.074277
10188 08:06:45.326098 00a80000 ################################################################
10189 08:06:45.326238
10190 08:06:45.587787 00b00000 ################################################################
10191 08:06:45.587940
10192 08:06:45.858266 00b80000 ################################################################
10193 08:06:45.858409
10194 08:06:46.121063 00c00000 ################################################################
10195 08:06:46.121203
10196 08:06:46.364048 00c80000 ################################################################
10197 08:06:46.364191
10198 08:06:46.624633 00d00000 ################################################################
10199 08:06:46.624783
10200 08:06:46.895339 00d80000 ################################################################
10201 08:06:46.895480
10202 08:06:47.161274 00e00000 ################################################################
10203 08:06:47.161415
10204 08:06:47.434190 00e80000 ################################################################
10205 08:06:47.434333
10206 08:06:47.704015 00f00000 ################################################################
10207 08:06:47.704162
10208 08:06:47.973557 00f80000 ################################################################
10209 08:06:47.973735
10210 08:06:48.243113 01000000 ################################################################
10211 08:06:48.243259
10212 08:06:48.510777 01080000 ################################################################
10213 08:06:48.510953
10214 08:06:48.776618 01100000 ################################################################
10215 08:06:48.776766
10216 08:06:49.028637 01180000 ################################################################
10217 08:06:49.028774
10218 08:06:49.290708 01200000 ################################################################
10219 08:06:49.290842
10220 08:06:49.561749 01280000 ################################################################
10221 08:06:49.561891
10222 08:06:49.827353 01300000 ################################################################
10223 08:06:49.827501
10224 08:06:50.071965 01380000 ################################################################
10225 08:06:50.072108
10226 08:06:50.319080 01400000 ################################################################
10227 08:06:50.319222
10228 08:06:50.585644 01480000 ################################################################
10229 08:06:50.585788
10230 08:06:50.833042 01500000 ################################################################
10231 08:06:50.833190
10232 08:06:51.087422 01580000 ################################################################
10233 08:06:51.087559
10234 08:06:51.349768 01600000 ################################################################
10235 08:06:51.349914
10236 08:06:51.616562 01680000 ################################################################
10237 08:06:51.616700
10238 08:06:51.871755 01700000 ################################################################
10239 08:06:51.871896
10240 08:06:52.136446 01780000 ################################################################
10241 08:06:52.136591
10242 08:06:52.401155 01800000 ################################################################
10243 08:06:52.401298
10244 08:06:52.669964 01880000 ################################################################
10245 08:06:52.670111
10246 08:06:52.924990 01900000 ################################################################
10247 08:06:52.925133
10248 08:06:53.195664 01980000 ################################################################
10249 08:06:53.195849
10250 08:06:53.462345 01a00000 ################################################################
10251 08:06:53.462484
10252 08:06:53.715118 01a80000 ################################################################
10253 08:06:53.715260
10254 08:06:53.950335 01b00000 ################################################################
10255 08:06:53.950478
10256 08:06:54.221078 01b80000 ################################################################
10257 08:06:54.221216
10258 08:06:54.493886 01c00000 ################################################################
10259 08:06:54.494023
10260 08:06:54.732632 01c80000 ################################################################
10261 08:06:54.732773
10262 08:06:54.994553 01d00000 ################################################################
10263 08:06:54.994693
10264 08:06:55.266913 01d80000 ################################################################
10265 08:06:55.267054
10266 08:06:55.538406 01e00000 ################################################################
10267 08:06:55.538548
10268 08:06:55.798602 01e80000 ############################################################### done.
10269 08:06:55.798745
10270 08:06:55.802115 The bootfile was 32489922 bytes long.
10271 08:06:55.802208
10272 08:06:55.805372 Sending tftp read request... done.
10273 08:06:55.805461
10274 08:06:55.807960 Waiting for the transfer...
10275 08:06:55.808055
10276 08:06:55.808130 00000000 # done.
10277 08:06:55.808202
10278 08:06:55.814744 Command line loaded dynamically from TFTP file: 11585986/tftp-deploy-5pxa7njy/kernel/cmdline
10279 08:06:55.814848
10280 08:06:55.828294 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10281 08:06:55.831400
10282 08:06:55.831576 Loading FIT.
10283 08:06:55.831739
10284 08:06:55.835168 Image ramdisk-1 has 21395344 bytes.
10285 08:06:55.835321
10286 08:06:55.838097 Image fdt-1 has 47278 bytes.
10287 08:06:55.838348
10288 08:06:55.841238 Image kernel-1 has 11045265 bytes.
10289 08:06:55.841417
10290 08:06:55.848176 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10291 08:06:55.848505
10292 08:06:55.868076 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10293 08:06:55.868661
10294 08:06:55.871343 Choosing best match conf-1 for compat google,spherion-rev2.
10295 08:06:55.876417
10296 08:06:55.881296 Connected to device vid:did:rid of 1ae0:0028:00
10297 08:06:55.888027
10298 08:06:55.891488 tpm_get_response: command 0x17b, return code 0x0
10299 08:06:55.892112
10300 08:06:55.897587 ec_init: CrosEC protocol v3 supported (256, 248)
10301 08:06:55.898148
10302 08:06:55.901119 tpm_cleanup: add release locality here.
10303 08:06:55.901680
10304 08:06:55.904261 Shutting down all USB controllers.
10305 08:06:55.904728
10306 08:06:55.907772 Removing current net device
10307 08:06:55.908341
10308 08:06:55.910762 Exiting depthcharge with code 4 at timestamp: 50457975
10309 08:06:55.911225
10310 08:06:55.914671 LZMA decompressing kernel-1 to 0x821a6718
10311 08:06:55.915137
10312 08:06:55.917792 LZMA decompressing kernel-1 to 0x40000000
10313 08:06:57.307956
10314 08:06:57.308512 jumping to kernel
10315 08:06:57.309977 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10316 08:06:57.310499 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10317 08:06:57.310918 Setting prompt string to ['Linux version [0-9]']
10318 08:06:57.311299 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10319 08:06:57.311678 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10320 08:06:57.390177
10321 08:06:57.392993 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10322 08:06:57.396655 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10323 08:06:57.397242 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10324 08:06:57.397639 Setting prompt string to []
10325 08:06:57.398075 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10326 08:06:57.398471 Using line separator: #'\n'#
10327 08:06:57.398810 No login prompt set.
10328 08:06:57.399158 Parsing kernel messages
10329 08:06:57.399476 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10330 08:06:57.400060 [login-action] Waiting for messages, (timeout 00:04:03)
10331 08:06:57.415668 [ 0.000000] Linux version 6.1.54-cip6 (KernelCI@build-j53272-arm64-gcc-10-defconfig-arm64-chromebook-xzlx8) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023
10332 08:06:57.418816 [ 0.000000] random: crng init done
10333 08:06:57.425547 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10334 08:06:57.429234 [ 0.000000] efi: UEFI not found.
10335 08:06:57.435199 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10336 08:06:57.445465 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10337 08:06:57.451718 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10338 08:06:57.461867 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10339 08:06:57.468736 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10340 08:06:57.474886 [ 0.000000] printk: bootconsole [mtk8250] enabled
10341 08:06:57.481606 [ 0.000000] NUMA: No NUMA configuration found
10342 08:06:57.488185 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10343 08:06:57.494713 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10344 08:06:57.495361 [ 0.000000] Zone ranges:
10345 08:06:57.502391 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10346 08:06:57.504447 [ 0.000000] DMA32 empty
10347 08:06:57.512335 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10348 08:06:57.514576 [ 0.000000] Movable zone start for each node
10349 08:06:57.517818 [ 0.000000] Early memory node ranges
10350 08:06:57.524727 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10351 08:06:57.530770 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10352 08:06:57.537546 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10353 08:06:57.544097 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10354 08:06:57.551115 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10355 08:06:57.557332 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10356 08:06:57.613778 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10357 08:06:57.620933 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10358 08:06:57.628301 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10359 08:06:57.630562 [ 0.000000] psci: probing for conduit method from DT.
10360 08:06:57.637175 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10361 08:06:57.640260 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10362 08:06:57.646864 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10363 08:06:57.650426 [ 0.000000] psci: SMC Calling Convention v1.2
10364 08:06:57.657257 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10365 08:06:57.660223 [ 0.000000] Detected VIPT I-cache on CPU0
10366 08:06:57.666883 [ 0.000000] CPU features: detected: GIC system register CPU interface
10367 08:06:57.673178 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10368 08:06:57.680455 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10369 08:06:57.686909 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10370 08:06:57.693214 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10371 08:06:57.703031 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10372 08:06:57.706673 [ 0.000000] alternatives: applying boot alternatives
10373 08:06:57.713393 [ 0.000000] Fallback order for Node 0: 0
10374 08:06:57.719464 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10375 08:06:57.722914 [ 0.000000] Policy zone: Normal
10376 08:06:57.736081 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10377 08:06:57.746252 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10378 08:06:57.757989 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10379 08:06:57.768387 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10380 08:06:57.774713 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10381 08:06:57.777890 <6>[ 0.000000] software IO TLB: area num 8.
10382 08:06:57.834661 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10383 08:06:57.983468 <6>[ 0.000000] Memory: 7948536K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 404232K reserved, 32768K cma-reserved)
10384 08:06:57.990206 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10385 08:06:57.996426 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10386 08:06:57.999921 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10387 08:06:58.007184 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10388 08:06:58.013580 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10389 08:06:58.016370 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10390 08:06:58.026483 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10391 08:06:58.033198 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10392 08:06:58.039796 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10393 08:06:58.046218 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10394 08:06:58.049628 <6>[ 0.000000] GICv3: 608 SPIs implemented
10395 08:06:58.053220 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10396 08:06:58.059613 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10397 08:06:58.063051 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10398 08:06:58.069510 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10399 08:06:58.082909 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10400 08:06:58.095870 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10401 08:06:58.102377 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10402 08:06:58.109950 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10403 08:06:58.123517 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10404 08:06:58.129887 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10405 08:06:58.136250 <6>[ 0.009187] Console: colour dummy device 80x25
10406 08:06:58.145904 <6>[ 0.013914] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10407 08:06:58.152697 <6>[ 0.024357] pid_max: default: 32768 minimum: 301
10408 08:06:58.155935 <6>[ 0.029259] LSM: Security Framework initializing
10409 08:06:58.162466 <6>[ 0.034228] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 08:06:58.172522 <6>[ 0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10411 08:06:58.182955 <6>[ 0.051447] cblist_init_generic: Setting adjustable number of callback queues.
10412 08:06:58.189234 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 08:06:58.195669 <6>[ 0.065291] cblist_init_generic: Setting adjustable number of callback queues.
10414 08:06:58.202586 <6>[ 0.072717] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 08:06:58.205574 <6>[ 0.079118] rcu: Hierarchical SRCU implementation.
10416 08:06:58.212416 <6>[ 0.084140] rcu: Max phase no-delay instances is 1000.
10417 08:06:58.218763 <6>[ 0.091173] EFI services will not be available.
10418 08:06:58.222064 <6>[ 0.096130] smp: Bringing up secondary CPUs ...
10419 08:06:58.231127 <6>[ 0.101211] Detected VIPT I-cache on CPU1
10420 08:06:58.237408 <6>[ 0.101281] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10421 08:06:58.244366 <6>[ 0.101313] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10422 08:06:58.247968 <6>[ 0.101658] Detected VIPT I-cache on CPU2
10423 08:06:58.253641 <6>[ 0.101705] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10424 08:06:58.263842 <6>[ 0.101722] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10425 08:06:58.267255 <6>[ 0.101970] Detected VIPT I-cache on CPU3
10426 08:06:58.273975 <6>[ 0.102012] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10427 08:06:58.280450 <6>[ 0.102026] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10428 08:06:58.283429 <6>[ 0.102319] CPU features: detected: Spectre-v4
10429 08:06:58.290087 <6>[ 0.102327] CPU features: detected: Spectre-BHB
10430 08:06:58.293418 <6>[ 0.102333] Detected PIPT I-cache on CPU4
10431 08:06:58.301095 <6>[ 0.102390] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10432 08:06:58.306752 <6>[ 0.102408] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10433 08:06:58.313613 <6>[ 0.102699] Detected PIPT I-cache on CPU5
10434 08:06:58.319861 <6>[ 0.102761] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10435 08:06:58.326674 <6>[ 0.102778] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10436 08:06:58.330125 <6>[ 0.103058] Detected PIPT I-cache on CPU6
10437 08:06:58.336612 <6>[ 0.103122] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10438 08:06:58.343645 <6>[ 0.103138] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10439 08:06:58.349819 <6>[ 0.103435] Detected PIPT I-cache on CPU7
10440 08:06:58.356313 <6>[ 0.103499] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10441 08:06:58.362911 <6>[ 0.103515] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10442 08:06:58.366355 <6>[ 0.103563] smp: Brought up 1 node, 8 CPUs
10443 08:06:58.372657 <6>[ 0.244907] SMP: Total of 8 processors activated.
10444 08:06:58.376317 <6>[ 0.249828] CPU features: detected: 32-bit EL0 Support
10445 08:06:58.386079 <6>[ 0.255190] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10446 08:06:58.392428 <6>[ 0.263990] CPU features: detected: Common not Private translations
10447 08:06:58.399492 <6>[ 0.270466] CPU features: detected: CRC32 instructions
10448 08:06:58.402602 <6>[ 0.275817] CPU features: detected: RCpc load-acquire (LDAPR)
10449 08:06:58.409500 <6>[ 0.281814] CPU features: detected: LSE atomic instructions
10450 08:06:58.415647 <6>[ 0.287595] CPU features: detected: Privileged Access Never
10451 08:06:58.422420 <6>[ 0.293410] CPU features: detected: RAS Extension Support
10452 08:06:58.428927 <6>[ 0.299019] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10453 08:06:58.432280 <6>[ 0.306282] CPU: All CPU(s) started at EL2
10454 08:06:58.438576 <6>[ 0.310625] alternatives: applying system-wide alternatives
10455 08:06:58.448122 <6>[ 0.321330] devtmpfs: initialized
10456 08:06:58.464406 <6>[ 0.330214] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10457 08:06:58.470390 <6>[ 0.340177] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10458 08:06:58.477980 <6>[ 0.348376] pinctrl core: initialized pinctrl subsystem
10459 08:06:58.480346 <6>[ 0.355017] DMI not present or invalid.
10460 08:06:58.487131 <6>[ 0.359433] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10461 08:06:58.497718 <6>[ 0.366298] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10462 08:06:58.503855 <6>[ 0.373887] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10463 08:06:58.514074 <6>[ 0.382109] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10464 08:06:58.516625 <6>[ 0.390349] audit: initializing netlink subsys (disabled)
10465 08:06:58.526704 <5>[ 0.396041] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10466 08:06:58.533417 <6>[ 0.396739] thermal_sys: Registered thermal governor 'step_wise'
10467 08:06:58.539502 <6>[ 0.404009] thermal_sys: Registered thermal governor 'power_allocator'
10468 08:06:58.542869 <6>[ 0.410264] cpuidle: using governor menu
10469 08:06:58.549678 <6>[ 0.421222] NET: Registered PF_QIPCRTR protocol family
10470 08:06:58.555898 <6>[ 0.426702] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10471 08:06:58.562901 <6>[ 0.433805] ASID allocator initialised with 32768 entries
10472 08:06:58.566164 <6>[ 0.440356] Serial: AMBA PL011 UART driver
10473 08:06:58.576255 <4>[ 0.449113] Trying to register duplicate clock ID: 134
10474 08:06:58.630828 <6>[ 0.506774] KASLR enabled
10475 08:06:58.645093 <6>[ 0.514516] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10476 08:06:58.651790 <6>[ 0.521531] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10477 08:06:58.657961 <6>[ 0.528020] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10478 08:06:58.664493 <6>[ 0.535028] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10479 08:06:58.671496 <6>[ 0.541514] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10480 08:06:58.677809 <6>[ 0.548519] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10481 08:06:58.684416 <6>[ 0.555006] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10482 08:06:58.691471 <6>[ 0.562011] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10483 08:06:58.694166 <6>[ 0.569537] ACPI: Interpreter disabled.
10484 08:06:58.703481 <6>[ 0.575968] iommu: Default domain type: Translated
10485 08:06:58.709876 <6>[ 0.581081] iommu: DMA domain TLB invalidation policy: strict mode
10486 08:06:58.712679 <5>[ 0.587734] SCSI subsystem initialized
10487 08:06:58.719270 <6>[ 0.591899] usbcore: registered new interface driver usbfs
10488 08:06:58.726383 <6>[ 0.597631] usbcore: registered new interface driver hub
10489 08:06:58.729526 <6>[ 0.603182] usbcore: registered new device driver usb
10490 08:06:58.736427 <6>[ 0.609289] pps_core: LinuxPPS API ver. 1 registered
10491 08:06:58.746700 <6>[ 0.614482] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10492 08:06:58.749662 <6>[ 0.623829] PTP clock support registered
10493 08:06:58.753180 <6>[ 0.628074] EDAC MC: Ver: 3.0.0
10494 08:06:58.760700 <6>[ 0.633253] FPGA manager framework
10495 08:06:58.767536 <6>[ 0.636934] Advanced Linux Sound Architecture Driver Initialized.
10496 08:06:58.769804 <6>[ 0.643709] vgaarb: loaded
10497 08:06:58.776523 <6>[ 0.646870] clocksource: Switched to clocksource arch_sys_counter
10498 08:06:58.780110 <5>[ 0.653307] VFS: Disk quotas dquot_6.6.0
10499 08:06:58.786637 <6>[ 0.657494] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10500 08:06:58.790203 <6>[ 0.664686] pnp: PnP ACPI: disabled
10501 08:06:58.798656 <6>[ 0.671367] NET: Registered PF_INET protocol family
10502 08:06:58.808220 <6>[ 0.676965] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10503 08:06:58.819595 <6>[ 0.689287] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10504 08:06:58.829467 <6>[ 0.698102] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10505 08:06:58.836431 <6>[ 0.706077] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10506 08:06:58.846477 <6>[ 0.714777] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10507 08:06:58.853398 <6>[ 0.724535] TCP: Hash tables configured (established 65536 bind 65536)
10508 08:06:58.859620 <6>[ 0.731398] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 08:06:58.869037 <6>[ 0.738596] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10510 08:06:58.875990 <6>[ 0.746297] NET: Registered PF_UNIX/PF_LOCAL protocol family
10511 08:06:58.883400 <6>[ 0.752447] RPC: Registered named UNIX socket transport module.
10512 08:06:58.885816 <6>[ 0.758600] RPC: Registered udp transport module.
10513 08:06:58.893234 <6>[ 0.763532] RPC: Registered tcp transport module.
10514 08:06:58.898843 <6>[ 0.768462] RPC: Registered tcp NFSv4.1 backchannel transport module.
10515 08:06:58.902465 <6>[ 0.775129] PCI: CLS 0 bytes, default 64
10516 08:06:58.905107 <6>[ 0.779452] Unpacking initramfs...
10517 08:06:58.929542 <6>[ 0.798982] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10518 08:06:58.939151 <6>[ 0.807645] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10519 08:06:58.942334 <6>[ 0.816496] kvm [1]: IPA Size Limit: 40 bits
10520 08:06:58.948986 <6>[ 0.821024] kvm [1]: GICv3: no GICV resource entry
10521 08:06:58.952343 <6>[ 0.826048] kvm [1]: disabling GICv2 emulation
10522 08:06:58.958780 <6>[ 0.830733] kvm [1]: GIC system register CPU interface enabled
10523 08:06:58.962140 <6>[ 0.836900] kvm [1]: vgic interrupt IRQ18
10524 08:06:58.969529 <6>[ 0.841253] kvm [1]: VHE mode initialized successfully
10525 08:06:58.975784 <5>[ 0.847738] Initialise system trusted keyrings
10526 08:06:58.982778 <6>[ 0.852591] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10527 08:06:58.989996 <6>[ 0.862557] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10528 08:06:58.996285 <5>[ 0.868970] NFS: Registering the id_resolver key type
10529 08:06:59.000081 <5>[ 0.874271] Key type id_resolver registered
10530 08:06:59.006016 <5>[ 0.878686] Key type id_legacy registered
10531 08:06:59.012905 <6>[ 0.882959] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10532 08:06:59.019486 <6>[ 0.889884] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10533 08:06:59.026210 <6>[ 0.897591] 9p: Installing v9fs 9p2000 file system support
10534 08:06:59.063076 <5>[ 0.935541] Key type asymmetric registered
10535 08:06:59.065892 <5>[ 0.939872] Asymmetric key parser 'x509' registered
10536 08:06:59.076032 <6>[ 0.945022] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10537 08:06:59.079014 <6>[ 0.952661] io scheduler mq-deadline registered
10538 08:06:59.083031 <6>[ 0.957442] io scheduler kyber registered
10539 08:06:59.102198 <6>[ 0.974642] EINJ: ACPI disabled.
10540 08:06:59.134613 <4>[ 1.000371] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 08:06:59.143694 <4>[ 1.011002] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10542 08:06:59.158863 <6>[ 1.031777] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10543 08:06:59.167164 <6>[ 1.039889] printk: console [ttyS0] disabled
10544 08:06:59.194736 <6>[ 1.064542] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10545 08:06:59.201494 <6>[ 1.074010] printk: console [ttyS0] enabled
10546 08:06:59.205183 <6>[ 1.074010] printk: console [ttyS0] enabled
10547 08:06:59.211843 <6>[ 1.082907] printk: bootconsole [mtk8250] disabled
10548 08:06:59.215457 <6>[ 1.082907] printk: bootconsole [mtk8250] disabled
10549 08:06:59.221098 <6>[ 1.094139] SuperH (H)SCI(F) driver initialized
10550 08:06:59.225001 <6>[ 1.099414] msm_serial: driver initialized
10551 08:06:59.239077 <6>[ 1.108434] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10552 08:06:59.248703 <6>[ 1.116984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10553 08:06:59.255639 <6>[ 1.125527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10554 08:06:59.265459 <6>[ 1.134155] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10555 08:06:59.275366 <6>[ 1.142865] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10556 08:06:59.281719 <6>[ 1.151580] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10557 08:06:59.291576 <6>[ 1.160121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10558 08:06:59.297790 <6>[ 1.168943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10559 08:06:59.307951 <6>[ 1.177487] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10560 08:06:59.319464 <6>[ 1.192784] loop: module loaded
10561 08:06:59.326410 <6>[ 1.198708] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10562 08:06:59.349573 <4>[ 1.222289] mtk-pmic-keys: Failed to locate of_node [id: -1]
10563 08:06:59.356416 <6>[ 1.229371] megasas: 07.719.03.00-rc1
10564 08:06:59.366514 <6>[ 1.239162] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10565 08:06:59.373829 <6>[ 1.246248] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10566 08:06:59.390395 <6>[ 1.262875] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10567 08:06:59.450140 <6>[ 1.316577] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10568 08:06:59.813445 <6>[ 1.686571] Freeing initrd memory: 20888K
10569 08:06:59.829427 <6>[ 1.702340] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10570 08:06:59.840625 <6>[ 1.713351] tun: Universal TUN/TAP device driver, 1.6
10571 08:06:59.844113 <6>[ 1.719444] thunder_xcv, ver 1.0
10572 08:06:59.847049 <6>[ 1.722948] thunder_bgx, ver 1.0
10573 08:06:59.850720 <6>[ 1.726437] nicpf, ver 1.0
10574 08:06:59.860668 <6>[ 1.730467] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10575 08:06:59.863863 <6>[ 1.737944] hns3: Copyright (c) 2017 Huawei Corporation.
10576 08:06:59.870710 <6>[ 1.743532] hclge is initializing
10577 08:06:59.873866 <6>[ 1.747114] e1000: Intel(R) PRO/1000 Network Driver
10578 08:06:59.880623 <6>[ 1.752243] e1000: Copyright (c) 1999-2006 Intel Corporation.
10579 08:06:59.884143 <6>[ 1.758254] e1000e: Intel(R) PRO/1000 Network Driver
10580 08:06:59.890979 <6>[ 1.763469] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10581 08:06:59.897435 <6>[ 1.769658] igb: Intel(R) Gigabit Ethernet Network Driver
10582 08:06:59.904149 <6>[ 1.775313] igb: Copyright (c) 2007-2014 Intel Corporation.
10583 08:06:59.910655 <6>[ 1.781151] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10584 08:06:59.917229 <6>[ 1.787668] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10585 08:06:59.920377 <6>[ 1.794138] sky2: driver version 1.30
10586 08:06:59.927183 <6>[ 1.799152] VFIO - User Level meta-driver version: 0.3
10587 08:06:59.934655 <6>[ 1.807419] usbcore: registered new interface driver usb-storage
10588 08:06:59.940985 <6>[ 1.813862] usbcore: registered new device driver onboard-usb-hub
10589 08:06:59.950428 <6>[ 1.823017] mt6397-rtc mt6359-rtc: registered as rtc0
10590 08:06:59.959989 <6>[ 1.828482] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T08:07:01 UTC (1695283621)
10591 08:06:59.963634 <6>[ 1.838051] i2c_dev: i2c /dev entries driver
10592 08:06:59.980134 <6>[ 1.849824] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10593 08:07:00.000248 <6>[ 1.872827] cpu cpu0: EM: created perf domain
10594 08:07:00.003106 <6>[ 1.877777] cpu cpu4: EM: created perf domain
10595 08:07:00.010473 <6>[ 1.883389] sdhci: Secure Digital Host Controller Interface driver
10596 08:07:00.017536 <6>[ 1.889821] sdhci: Copyright(c) Pierre Ossman
10597 08:07:00.023572 <6>[ 1.894779] Synopsys Designware Multimedia Card Interface Driver
10598 08:07:00.030755 <6>[ 1.901426] sdhci-pltfm: SDHCI platform and OF driver helper
10599 08:07:00.034066 <6>[ 1.901481] mmc0: CQHCI version 5.10
10600 08:07:00.040504 <6>[ 1.911663] ledtrig-cpu: registered to indicate activity on CPUs
10601 08:07:00.047198 <6>[ 1.918776] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10602 08:07:00.053556 <6>[ 1.925840] usbcore: registered new interface driver usbhid
10603 08:07:00.057337 <6>[ 1.931665] usbhid: USB HID core driver
10604 08:07:00.063446 <6>[ 1.935857] spi_master spi0: will run message pump with realtime priority
10605 08:07:00.109548 <6>[ 1.975484] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10606 08:07:00.127920 <6>[ 1.990806] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10607 08:07:00.131777 <6>[ 2.004380] mmc0: Command Queue Engine enabled
10608 08:07:00.138449 <6>[ 2.009136] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10609 08:07:00.144549 <6>[ 2.016080] cros-ec-spi spi0.0: Chrome EC device registered
10610 08:07:00.147894 <6>[ 2.016443] mmcblk0: mmc0:0001 DA4128 116 GiB
10611 08:07:00.158726 <6>[ 2.031505] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10612 08:07:00.165903 <6>[ 2.039049] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10613 08:07:00.172554 <6>[ 2.045015] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10614 08:07:00.179038 <6>[ 2.051157] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10615 08:07:00.188917 <6>[ 2.056722] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10616 08:07:00.195872 <6>[ 2.068262] NET: Registered PF_PACKET protocol family
10617 08:07:00.199624 <6>[ 2.073658] 9pnet: Installing 9P2000 support
10618 08:07:00.206216 <5>[ 2.078224] Key type dns_resolver registered
10619 08:07:00.209290 <6>[ 2.083214] registered taskstats version 1
10620 08:07:00.215668 <5>[ 2.087604] Loading compiled-in X.509 certificates
10621 08:07:00.245663 <4>[ 2.111673] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 08:07:00.255468 <4>[ 2.122451] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10623 08:07:00.262297 <3>[ 2.133051] debugfs: File 'uA_load' in directory '/' already present!
10624 08:07:00.268910 <3>[ 2.139765] debugfs: File 'min_uV' in directory '/' already present!
10625 08:07:00.275491 <3>[ 2.146378] debugfs: File 'max_uV' in directory '/' already present!
10626 08:07:00.281840 <3>[ 2.152988] debugfs: File 'constraint_flags' in directory '/' already present!
10627 08:07:00.294512 <3>[ 2.163028] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10628 08:07:00.305688 <6>[ 2.178580] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10629 08:07:00.312395 <6>[ 2.185405] xhci-mtk 11200000.usb: xHCI Host Controller
10630 08:07:00.319064 <6>[ 2.190942] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10631 08:07:00.329208 <6>[ 2.198856] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10632 08:07:00.336118 <6>[ 2.208287] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10633 08:07:00.342781 <6>[ 2.214347] xhci-mtk 11200000.usb: xHCI Host Controller
10634 08:07:00.348940 <6>[ 2.219828] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10635 08:07:00.355964 <6>[ 2.227479] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10636 08:07:00.362540 <6>[ 2.235295] hub 1-0:1.0: USB hub found
10637 08:07:00.365847 <6>[ 2.239315] hub 1-0:1.0: 1 port detected
10638 08:07:00.375474 <6>[ 2.243588] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10639 08:07:00.378673 <6>[ 2.252274] hub 2-0:1.0: USB hub found
10640 08:07:00.381821 <6>[ 2.256293] hub 2-0:1.0: 1 port detected
10641 08:07:00.390349 <6>[ 2.263213] mtk-msdc 11f70000.mmc: Got CD GPIO
10642 08:07:00.401247 <6>[ 2.271013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10643 08:07:00.408641 <6>[ 2.279056] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10644 08:07:00.418007 <4>[ 2.286966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10645 08:07:00.428210 <6>[ 2.296499] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10646 08:07:00.434265 <6>[ 2.304577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10647 08:07:00.441118 <6>[ 2.312710] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10648 08:07:00.450918 <6>[ 2.320642] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10649 08:07:00.457315 <6>[ 2.328459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10650 08:07:00.467642 <6>[ 2.336276] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10651 08:07:00.476884 <6>[ 2.346748] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10652 08:07:00.487166 <6>[ 2.355130] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10653 08:07:00.493433 <6>[ 2.363470] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10654 08:07:00.504051 <6>[ 2.371809] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10655 08:07:00.510365 <6>[ 2.380148] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10656 08:07:00.519875 <6>[ 2.388489] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10657 08:07:00.526231 <6>[ 2.396827] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10658 08:07:00.536275 <6>[ 2.405165] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10659 08:07:00.542915 <6>[ 2.413503] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10660 08:07:00.553268 <6>[ 2.421845] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10661 08:07:00.560256 <6>[ 2.430184] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10662 08:07:00.569876 <6>[ 2.438522] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10663 08:07:00.576065 <6>[ 2.446860] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10664 08:07:00.585714 <6>[ 2.455198] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10665 08:07:00.592321 <6>[ 2.463536] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10666 08:07:00.599300 <6>[ 2.472311] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10667 08:07:00.606376 <6>[ 2.479468] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10668 08:07:00.613154 <6>[ 2.486225] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10669 08:07:00.622855 <6>[ 2.492986] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10670 08:07:00.630243 <6>[ 2.499925] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10671 08:07:00.636633 <6>[ 2.506780] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10672 08:07:00.646426 <6>[ 2.515918] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10673 08:07:00.656493 <6>[ 2.525039] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10674 08:07:00.665776 <6>[ 2.534333] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10675 08:07:00.675979 <6>[ 2.543802] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10676 08:07:00.686560 <6>[ 2.553273] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10677 08:07:00.692502 <6>[ 2.562393] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10678 08:07:00.702434 <6>[ 2.571860] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10679 08:07:00.712445 <6>[ 2.580979] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10680 08:07:00.722608 <6>[ 2.590274] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10681 08:07:00.731794 <6>[ 2.600433] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10682 08:07:00.742479 <6>[ 2.612060] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10683 08:07:00.773416 <6>[ 2.643460] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10684 08:07:00.801974 <6>[ 2.674981] hub 2-1:1.0: USB hub found
10685 08:07:00.805133 <6>[ 2.679450] hub 2-1:1.0: 3 ports detected
10686 08:07:00.924890 <6>[ 2.795052] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10687 08:07:01.080258 <6>[ 2.953395] hub 1-1:1.0: USB hub found
10688 08:07:01.083390 <6>[ 2.957914] hub 1-1:1.0: 4 ports detected
10689 08:07:01.405402 <6>[ 3.275202] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10690 08:07:01.536534 <6>[ 3.409415] hub 1-1.1:1.0: USB hub found
10691 08:07:01.539687 <6>[ 3.413776] hub 1-1.1:1.0: 4 ports detected
10692 08:07:01.653448 <6>[ 3.523239] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10693 08:07:01.785607 <6>[ 3.658676] hub 1-1.4:1.0: USB hub found
10694 08:07:01.789362 <6>[ 3.663352] hub 1-1.4:1.0: 2 ports detected
10695 08:07:01.869345 <6>[ 3.739203] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10696 08:07:02.061214 <6>[ 3.931143] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10697 08:07:02.146848 <3>[ 4.019389] usb 1-1.1.4: device descriptor read/64, error -32
10698 08:07:02.338706 <3>[ 4.211385] usb 1-1.1.4: device descriptor read/64, error -32
10699 08:07:02.533447 <6>[ 4.403201] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10700 08:07:02.721123 <6>[ 4.591200] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10701 08:07:02.806005 <3>[ 4.679245] usb 1-1.1.4: device descriptor read/64, error -32
10702 08:07:02.998018 <3>[ 4.871387] usb 1-1.1.4: device descriptor read/64, error -32
10703 08:07:03.110323 <6>[ 4.983787] usb 1-1.1-port4: attempt power cycle
10704 08:07:03.197080 <6>[ 5.067162] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10705 08:07:03.721564 <6>[ 5.591209] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10706 08:07:03.727539 <4>[ 5.598684] usb 1-1.1.4: Device not responding to setup address.
10707 08:07:03.938160 <4>[ 5.811348] usb 1-1.1.4: Device not responding to setup address.
10708 08:07:04.150145 <3>[ 6.023238] usb 1-1.1.4: device not accepting address 10, error -71
10709 08:07:04.236917 <6>[ 6.107199] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10710 08:07:04.243365 <4>[ 6.114613] usb 1-1.1.4: Device not responding to setup address.
10711 08:07:04.454039 <4>[ 6.327470] usb 1-1.1.4: Device not responding to setup address.
10712 08:07:04.665563 <3>[ 6.539192] usb 1-1.1.4: device not accepting address 11, error -71
10713 08:07:04.672774 <3>[ 6.546251] usb 1-1.1-port4: unable to enumerate USB device
10714 08:07:13.018995 <6>[ 14.896234] ALSA device list:
10715 08:07:13.025203 <6>[ 14.899534] No soundcards found.
10716 08:07:13.033059 <6>[ 14.907657] Freeing unused kernel memory: 8448K
10717 08:07:13.036397 <6>[ 14.912661] Run /init as init process
10718 08:07:13.076043 Starting syslogd: OK
10719 08:07:13.080342 Starting klogd: OK
10720 08:07:13.087407 Running sysctl: OK
10721 08:07:13.094017 Populating /dev using udev: <30>[ 14.969647] udevd[195]: starting version 3.2.9
10722 08:07:13.102845 <27>[ 14.976517] udevd[195]: specified user 'tss' unknown
10723 08:07:13.108948 <27>[ 14.981859] udevd[195]: specified group 'tss' unknown
10724 08:07:13.111811 <30>[ 14.988128] udevd[196]: starting eudev-3.2.9
10725 08:07:13.130054 <27>[ 15.004295] udevd[196]: specified user 'tss' unknown
10726 08:07:13.136590 <27>[ 15.009641] udevd[196]: specified group 'tss' unknown
10727 08:07:13.234766 <6>[ 15.106291] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10728 08:07:13.255288 <6>[ 15.129138] remoteproc remoteproc0: scp is available
10729 08:07:13.261255 <6>[ 15.135118] remoteproc remoteproc0: powering up scp
10730 08:07:13.267962 <6>[ 15.140479] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10731 08:07:13.275797 <6>[ 15.150232] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10732 08:07:13.293108 <6>[ 15.163382] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10733 08:07:13.302444 <6>[ 15.173048] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10734 08:07:13.312639 <6>[ 15.183162] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10735 08:07:13.330939 <4>[ 15.202334] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10736 08:07:13.340962 <4>[ 15.211733] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10737 08:07:13.348185 <6>[ 15.222691] usbcore: registered new interface driver r8152
10738 08:07:13.358616 <3>[ 15.229679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 08:07:13.365323 <3>[ 15.237842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 08:07:13.374970 <3>[ 15.245945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 08:07:13.378578 <6>[ 15.246383] mc: Linux media interface: v0.10
10742 08:07:13.388516 <3>[ 15.254246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 08:07:13.394636 <3>[ 15.266779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 08:07:13.404684 <6>[ 15.268978] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10745 08:07:13.411564 <3>[ 15.275255] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 08:07:13.421390 <6>[ 15.281826] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10747 08:07:13.427892 <6>[ 15.281834] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10748 08:07:13.434058 <6>[ 15.281837] remoteproc remoteproc0: remote processor scp is now up
10749 08:07:13.441583 <4>[ 15.295900] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10750 08:07:13.448078 <4>[ 15.295900] Fallback method does not support PEC.
10751 08:07:13.454713 <3>[ 15.299198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 08:07:13.463279 <6>[ 15.307089] videodev: Linux video capture interface: v2.00
10753 08:07:13.471959 <6>[ 15.309068] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10754 08:07:13.478528 <6>[ 15.311191] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10755 08:07:13.488635 <3>[ 15.312757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 08:07:13.495352 <6>[ 15.319548] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10757 08:07:13.502011 <6>[ 15.319554] pci_bus 0000:00: root bus resource [bus 00-ff]
10758 08:07:13.508112 <6>[ 15.319561] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10759 08:07:13.518052 <6>[ 15.319563] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10760 08:07:13.524714 <6>[ 15.319588] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10761 08:07:13.531388 <6>[ 15.319601] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10762 08:07:13.534411 <6>[ 15.319666] pci 0000:00:00.0: supports D1 D2
10763 08:07:13.544503 <6>[ 15.319668] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10764 08:07:13.550938 <6>[ 15.320552] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10765 08:07:13.557613 <6>[ 15.320621] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10766 08:07:13.564367 <6>[ 15.320645] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10767 08:07:13.570824 <6>[ 15.320661] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10768 08:07:13.580921 <6>[ 15.320676] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10769 08:07:13.584445 <6>[ 15.320780] pci 0000:01:00.0: supports D1 D2
10770 08:07:13.590880 <6>[ 15.320782] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10771 08:07:13.597121 <6>[ 15.323289] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10772 08:07:13.607457 <3>[ 15.325831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10773 08:07:13.616986 <6>[ 15.334933] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10774 08:07:13.623711 <6>[ 15.334959] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10775 08:07:13.630376 <6>[ 15.334996] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10776 08:07:13.639689 <6>[ 15.335000] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10777 08:07:13.647014 <6>[ 15.335009] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10778 08:07:13.656352 <6>[ 15.335022] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10779 08:07:13.663261 <6>[ 15.335035] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10780 08:07:13.669917 <6>[ 15.335047] pci 0000:00:00.0: PCI bridge to [bus 01]
10781 08:07:13.676532 <6>[ 15.335052] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10782 08:07:13.683387 <6>[ 15.335272] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10783 08:07:13.689543 <6>[ 15.337395] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10784 08:07:13.696273 <6>[ 15.337729] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10785 08:07:13.702784 <3>[ 15.340231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 08:07:13.712844 <3>[ 15.347772] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 08:07:13.719697 <5>[ 15.370791] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10788 08:07:13.729248 <6>[ 15.371266] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10789 08:07:13.735589 <6>[ 15.372868] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10790 08:07:13.745414 <3>[ 15.374342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 08:07:13.749171 <6>[ 15.379994] usbcore: registered new interface driver cdc_ether
10792 08:07:13.755868 <6>[ 15.397792] Bluetooth: Core ver 2.22
10793 08:07:13.759367 <6>[ 15.397834] usbcore: registered new interface driver r8153_ecm
10794 08:07:13.769346 <3>[ 15.403368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 08:07:13.775902 <5>[ 15.410441] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10796 08:07:13.785410 <4>[ 15.410528] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10797 08:07:13.788635 <6>[ 15.410536] cfg80211: failed to load regulatory.db
10798 08:07:13.795010 <6>[ 15.410942] NET: Registered PF_BLUETOOTH protocol family
10799 08:07:13.802328 <6>[ 15.411991] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10800 08:07:13.814665 <6>[ 15.413324] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10801 08:07:13.821792 <6>[ 15.413452] usbcore: registered new interface driver uvcvideo
10802 08:07:13.828492 <3>[ 15.415383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 08:07:13.834642 <3>[ 15.415487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 08:07:13.841724 <6>[ 15.422281] Bluetooth: HCI device and connection manager initialized
10805 08:07:13.847918 <6>[ 15.423319] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10806 08:07:13.858222 <4>[ 15.426304] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10807 08:07:13.867455 <4>[ 15.426315] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10808 08:07:13.874211 <3>[ 15.430536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 08:07:13.880972 <6>[ 15.436806] Bluetooth: HCI socket layer initialized
10810 08:07:13.887991 <3>[ 15.444260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 08:07:13.893870 <6>[ 15.451736] Bluetooth: L2CAP socket layer initialized
10812 08:07:13.900955 <3>[ 15.459207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 08:07:13.907237 <6>[ 15.463741] Bluetooth: SCO socket layer initialized
10814 08:07:13.913930 <3>[ 15.470587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 08:07:13.920473 <6>[ 15.487029] r8152 1-1.1.1:1.0 eth0: v1.12.13
10816 08:07:13.927211 <3>[ 15.495966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 08:07:13.934134 <6>[ 15.523819] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10818 08:07:13.940361 <6>[ 15.548746] usbcore: registered new interface driver btusb
10819 08:07:13.950021 <4>[ 15.549582] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10820 08:07:13.956968 <3>[ 15.549601] Bluetooth: hci0: Failed to load firmware file (-2)
10821 08:07:13.963617 <3>[ 15.549609] Bluetooth: hci0: Failed to set up firmware (-2)
10822 08:07:13.973554 <4>[ 15.549617] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10823 08:07:13.980238 <6>[ 15.556575] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10824 08:07:14.004654 <6>[ 15.879154] mt7921e 0000:01:00.0: ASIC revision: 79610010
10825 08:07:14.111108 <4>[ 15.978658] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 08:07:14.119322 done
10827 08:07:14.134530 Saving random seed: OK
10828 08:07:14.147635 Starting network: OK
10829 08:07:14.179161 Starting dropbear sshd: <6>[ 16.054021] NET: Registered PF_INET6 protocol family
10830 08:07:14.185798 <6>[ 16.060636] Segment Routing with IPv6
10831 08:07:14.189411 <6>[ 16.064585] In-situ OAM (IOAM) with IPv6
10832 08:07:14.192967 OK
10833 08:07:14.204285 /bin/sh: can't access tty; job control turned off
10834 08:07:14.205394 Matched prompt #10: / #
10836 08:07:14.206471 Setting prompt string to ['/ #']
10837 08:07:14.206940 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10839 08:07:14.208050 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10840 08:07:14.208531 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
10841 08:07:14.208925 Setting prompt string to ['/ #']
10842 08:07:14.209264 Forcing a shell prompt, looking for ['/ #']
10844 08:07:14.260074 / #
10845 08:07:14.260723 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10846 08:07:14.261180 Waiting using forced prompt support (timeout 00:02:30)
10847 08:07:14.261693 <4>[ 16.097486] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 08:07:14.266349
10849 08:07:14.267428 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10850 08:07:14.267998 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
10851 08:07:14.268543 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10852 08:07:14.269033 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
10853 08:07:14.269506 end: 2 depthcharge-action (duration 00:01:14) [common]
10854 08:07:14.269981 start: 3 lava-test-retry (timeout 00:01:00) [common]
10855 08:07:14.270477 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10856 08:07:14.270875 Using namespace: common
10858 08:07:14.372136 / # #
10859 08:07:14.373020 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10860 08:07:14.373615 #<4>[ 16.221202] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 08:07:14.378870
10862 08:07:14.379791 Using /lava-11585986
10864 08:07:14.480997 / # export SHELL=/bin/sh
10865 08:07:14.481779 export SHELL=/bin/sh<4>[ 16.341467] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10866 08:07:14.487903
10868 08:07:14.589686 / # . /lava-11585986/environment
10869 08:07:14.593398 . /lava-11585986/environment<4>[ 16.461736] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10870 08:07:14.636419
10872 08:07:14.738421 / # /lava-11585986/bin/lava-test-runner /lava-11585986/0
10873 08:07:14.739042 Test shell timeout: 10s (minimum of the action and connection timeout)
10874 08:07:14.740788 /lava-11585986/bin/lava-test-runner /lava-11585986/0<4>[ 16.581816] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10875 08:07:14.745252
10876 08:07:14.788266 + export 'TESTRUN_ID=0_dmesg'
10877 08:07:14.788829 +<8>[ 16.644160] <LAVA_SIGNAL_STARTRUN 0_dmesg 11585986_1.5.2.3.1>
10878 08:07:14.789206 cd /lava-11585986/0/tests/0_dmesg
10879 08:07:14.789546 + cat uuid
10880 08:07:14.789873 + UUID=11585986_1.5.2.3.1
10881 08:07:14.790196 + set +x
10882 08:07:14.790510 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10883 08:07:14.791107 Received signal: <STARTRUN> 0_dmesg 11585986_1.5.2.3.1
10884 08:07:14.791480 Starting test lava.0_dmesg (11585986_1.5.2.3.1)
10885 08:07:14.791940 Skipping test definition patterns.
10886 08:07:14.794165 <8>[ 16.665272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10887 08:07:14.795001 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10889 08:07:14.815783 <8>[ 16.686896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10890 08:07:14.816769 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10892 08:07:14.834077 <4>[ 16.702075] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10893 08:07:14.850396 <8>[ 16.721613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10894 08:07:14.851240 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10896 08:07:14.854150 + set +x
10897 08:07:14.856558 <8>[ 16.731382] <LAVA_SIGNAL_ENDRUN 0_dmesg 11585986_1.5.2.3.1>
10898 08:07:14.857296 Received signal: <ENDRUN> 0_dmesg 11585986_1.5.2.3.1
10899 08:07:14.857799 Ending use of test pattern.
10900 08:07:14.858145 Ending test lava.0_dmesg (11585986_1.5.2.3.1), duration 0.07
10902 08:07:14.861967 <LAVA_TEST_RUNNER EXIT>
10903 08:07:14.862804 ok: lava_test_shell seems to have completed
10904 08:07:14.863380 alert: pass
crit: pass
emerg: pass
10905 08:07:14.864111 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10906 08:07:14.864593 end: 3 lava-test-retry (duration 00:00:01) [common]
10907 08:07:14.865074 start: 4 lava-test-retry (timeout 00:01:00) [common]
10908 08:07:14.865526 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10909 08:07:14.865883 Using namespace: common
10911 08:07:14.966999 / # #
10912 08:07:14.967641 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10913 08:07:14.968245 Using /lava-11585986
10915 08:07:15.069879 export SHELL=/bin/sh
10916 08:07:15.070649 #<4>[ 16.821570] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10917 08:07:15.071181
10919 08:07:15.172811 / # export SHELL=/bin/sh<4>[ 16.941646] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed. /lava-11585986/environment
10920 08:07:15.173632 with error -2
10921 08:07:15.174108
10923 08:07:15.275937 / # . /lava-11585986/environment/lava-11585986/bin/lava-test-runner /lava-11585986/1
10924 08:07:15.276569 Test shell timeout: 10s (minimum of the action and connection timeout)
10925 08:07:15.277161
10926 08:07:15.277539 / # <4>[ 17.061969] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10927 08:07:15.282491 /lava-11585986/bin/lava-test-runner /lava-11585986/1
10928 08:07:15.324256 <3>[ 17.180731] mt7921e 0000:01:00.0: hardware init failed
10929 08:07:15.324815 + export 'TESTRUN_ID=1_bootrr'
10930 08:07:15.325193 + <8>[ 17.189920] <LAVA_SIGNAL_STARTRUN 1_bootrr 11585986_1.5.2.3.5>
10931 08:07:15.325535 cd /lava-11585986/1/tests/1_bootrr
10932 08:07:15.325857 + cat uuid
10933 08:07:15.326179 + UUID=11585986_1.5.2.3.5
10934 08:07:15.326495 + set +x
10935 08:07:15.327088 Received signal: <STARTRUN> 1_bootrr 11585986_1.5.2.3.5
10936 08:07:15.327424 Starting test lava.1_bootrr (11585986_1.5.2.3.5)
10937 08:07:15.327850 Skipping test definition patterns.
10938 08:07:15.339497 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11585986/1/../bin:/sbin:/usr/sbin:/<8>[ 17.211451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10939 08:07:15.340397 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10941 08:07:15.343090 bin:/usr/bin'
10942 08:07:15.343641 + cd /opt/bootrr/libexec/bootrr
10943 08:07:15.345874 + sh helpers/bootrr-auto
10944 08:07:15.355613 /lava-11585986/1/../bin/lava-test-case<8>[ 17.228820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10945 08:07:15.356103
10946 08:07:15.356734 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10948 08:07:15.362243 /lava-11585986/1/../bin/lava-test-case
10949 08:07:15.362800 /usr/bin/tpm2_getcap
10950 08:07:15.400165 /lava-11585986/1/../bin/lava-test-case
10951 08:07:15.406968 <8>[ 17.279646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10952 08:07:15.407853 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10954 08:07:15.427093 /lava-11585986/1/../bin/lava-test-case
10955 08:07:15.433171 <8>[ 17.304980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10956 08:07:15.434027 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10958 08:07:15.444753 /lava-11585986/1/../bin/lava-test-case
10959 08:07:15.451211 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10961 08:07:15.453811 <8>[ 17.324141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10962 08:07:15.463852 /lava-11585986/1/../bin/lava-test-case
10963 08:07:15.470216 <8>[ 17.341613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10964 08:07:15.471147 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10966 08:07:15.488869 /lava-11585986/1/../bin/lava-tes<8>[ 17.359729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10967 08:07:15.489432 t-case
10968 08:07:15.490071 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10970 08:07:15.508687 /lava-11585986/1/../bin/lava-tes<8>[ 17.378793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10971 08:07:15.509256 t-case
10972 08:07:15.509905 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10974 08:07:15.524200 /lava-11585986/1/../bin/lava-tes<8>[ 17.394731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10975 08:07:15.524771 t-case
10976 08:07:15.525421 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10978 08:07:15.534341 /lava-11585986/1/../bin/lava-test-case
10979 08:07:15.540584 <8>[ 17.414072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10980 08:07:15.541431 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10982 08:07:15.552335 /lava-11585986/1/../bin/lava-test-case
10983 08:07:15.559143 <8>[ 17.430718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10984 08:07:15.560043 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10986 08:07:15.571030 /lava-11585986/1/../bin/lava-test-case
10987 08:07:15.577733 <8>[ 17.449649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10988 08:07:15.578584 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10990 08:07:15.589613 /lava-11585986/1/../bin/lava-test-case
10991 08:07:15.595924 <8>[ 17.467886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10992 08:07:15.596779 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10994 08:07:15.607886 /lava-11585986/1/../bin/lava-test-case
10995 08:07:15.613631 <8>[ 17.485360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10996 08:07:15.614476 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10998 08:07:15.626519 /lava-11585986/1/../bin/lava-test-case
10999 08:07:15.633405 <8>[ 17.504059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11000 08:07:15.634242 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11002 08:07:15.653521 /lava-11585986/1/../bin/lava-tes<8>[ 17.524002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11003 08:07:15.654081 t-case
11004 08:07:15.654726 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11006 08:07:15.663471 /lava-11585986/1/../bin/lava-test-case
11007 08:07:15.670257 <8>[ 17.542686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11008 08:07:15.671344 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11010 08:07:15.686858 /lava-11585986/1/../bin/lava-tes<8>[ 17.557767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11011 08:07:15.687426 t-case
11012 08:07:15.688124 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11014 08:07:15.704305 /lava-11585986/1/../bin/lava-tes<8>[ 17.575072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11015 08:07:15.704870 t-case
11016 08:07:15.705508 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11018 08:07:15.715215 /lava-11585986/1/../bin/lava-test-case
11019 08:07:15.722041 <8>[ 17.593045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11020 08:07:15.722908 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11022 08:07:15.734455 /lava-11585986/1/../bin/lava-test-case
11023 08:07:15.740841 <8>[ 17.611835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11024 08:07:15.741579 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11026 08:07:15.748631 /lava-11585986/1/../bin/lava-test-case
11027 08:07:15.754937 <8>[ 17.627134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11028 08:07:15.755645 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11030 08:07:15.770913 /lava-11585986/1/../bin/lava-test-case
11031 08:07:15.777157 <8>[ 17.648162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11032 08:07:15.777856 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11034 08:07:15.785276 /lava-11585986/1/../bin/lava-test-case
11035 08:07:15.792127 <8>[ 17.664490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11036 08:07:15.792801 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11038 08:07:15.811885 /lava-11585986/1/../bin/lava-tes<8>[ 17.682332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11039 08:07:15.812448 t-case
11040 08:07:15.813092 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11042 08:07:15.822332 /lava-11585986/1/../bin/lava-test-case
11043 08:07:15.829283 <8>[ 17.700493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11044 08:07:15.830113 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11046 08:07:15.837815 /lava-11585986/1/../bin/lava-test-case
11047 08:07:15.844272 <8>[ 17.716046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11048 08:07:15.845116 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11050 08:07:15.856044 /lava-11585986/1/../bin/lava-test-case
11051 08:07:15.862821 <8>[ 17.734343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11052 08:07:15.863665 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11054 08:07:15.878531 /lava-11585986/1/../bin/lava-tes<8>[ 17.748919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11055 08:07:15.879102 t-case
11056 08:07:15.879778 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11058 08:07:15.896316 /lava-11585986/1/../bin/lava-tes<8>[ 17.766750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11059 08:07:15.896886 t-case
11060 08:07:15.897529 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11062 08:07:15.907576 /lava-11585986/1/../bin/lava-test-case
11063 08:07:15.913602 <8>[ 17.786048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11064 08:07:15.914454 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11066 08:07:15.926426 /lava-11585986/1/../bin/lava-test-case
11067 08:07:15.932899 <8>[ 17.804576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11068 08:07:15.933754 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11070 08:07:15.943261 /lava-11585986/1/../bin/lava-test-case
11071 08:07:15.949453 <8>[ 17.821677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11072 08:07:15.950281 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11074 08:07:15.962104 /lava-11585986/1/../bin/lava-test-case
11075 08:07:15.968554 <8>[ 17.841026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11076 08:07:15.969398 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11078 08:07:15.980103 /lava-11585986/1/../bin/lava-test-case
11079 08:07:15.986513 <8>[ 17.859537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11080 08:07:15.987352 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11082 08:07:15.998704 /lava-11585986/1/../bin/lava-test-case
11083 08:07:16.004378 <8>[ 17.876950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11084 08:07:16.005226 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11086 08:07:16.015090 /lava-11585986/1/../bin/lava-test-case
11087 08:07:16.022121 <8>[ 17.893172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11088 08:07:16.022965 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11090 08:07:16.033563 /lava-11585986/1/../bin/lava-test-case
11091 08:07:16.040103 <8>[ 17.911119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11092 08:07:16.040953 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11094 08:07:16.060750 /lava-11585986/1/../bin/lava-tes<8>[ 17.931483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11095 08:07:16.061319 t-case
11096 08:07:16.061965 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11098 08:07:16.079870 /lava-11585986/1/../bin/lava-tes<8>[ 17.950407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11099 08:07:16.080423 t-case
11100 08:07:16.081149 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11102 08:07:16.087649 /lava-11585986/1/../bin/lava-test-case
11103 08:07:16.097328 <8>[ 17.967352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11104 08:07:16.098203 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11106 08:07:16.108433 /lava-11585986/1/../bin/lava-test-case
11107 08:07:16.115563 <8>[ 17.986530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11108 08:07:16.116436 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11110 08:07:16.124362 /lava-11585986/1/../bin/lava-test-case
11111 08:07:16.130289 <8>[ 18.001861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11112 08:07:16.131135 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11114 08:07:16.148812 /lava-11585986/1/../bin/lava-tes<8>[ 18.019556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11115 08:07:16.149441 t-case
11116 08:07:16.150095 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11118 08:07:16.159845 /lava-11585986/1/../bin/lava-test-case
11119 08:07:16.166775 <8>[ 18.037796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11120 08:07:16.167615 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11122 08:07:16.177272 /lava-11585986/1/../bin/lava-test-case
11123 08:07:16.183823 <8>[ 18.057535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11124 08:07:16.184721 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11126 08:07:16.194441 /lava-11585986/1/../bin/lava-test-case
11127 08:07:16.200736 <8>[ 18.072604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11128 08:07:16.201580 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11130 08:07:16.215775 /lava-11585986/1/../bin/lava-test-case
11131 08:07:16.222003 <8>[ 18.092979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11132 08:07:16.222878 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11134 08:07:16.229954 /lava-11585986/1/../bin/lava-test-case
11135 08:07:16.236775 <8>[ 18.108348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11136 08:07:16.237617 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11138 08:07:16.248991 /lava-11585986/1/../bin/lava-test-case
11139 08:07:16.255437 <8>[ 18.126632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11140 08:07:16.256328 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11142 08:07:16.264953 /lava-11585986/1/../bin/lava-test-case
11143 08:07:16.271689 <8>[ 18.143670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11144 08:07:16.272765 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11146 08:07:16.280731 /lava-11585986/1/../bin/lava-test-case
11147 08:07:16.287429 <8>[ 18.158756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11148 08:07:16.288321 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11150 08:07:16.304173 /lava-11585986/1/../bin/lava-test-case
11151 08:07:16.310739 <8>[ 18.181789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11152 08:07:16.311582 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11154 08:07:16.319003 /lava-11585986/1/../bin/lava-test-case
11155 08:07:16.325852 <8>[ 18.197481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11156 08:07:16.326689 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11158 08:07:16.344140 /lava-11585986/1/../bin/lava-tes<8>[ 18.214720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11159 08:07:16.344709 t-case
11160 08:07:16.345344 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11162 08:07:16.360686 /lava-11585986/1/../bin/lava-tes<8>[ 18.231289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11163 08:07:16.361247 t-case
11164 08:07:16.361877 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11166 08:07:16.379513 /lava-11585986/1/../bin/lava-tes<8>[ 18.250385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11167 08:07:16.380117 t-case
11168 08:07:16.380765 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11170 08:07:16.391596 /lava-11585986/1/../bin/lava-test-case
11171 08:07:16.398447 <8>[ 18.271201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11172 08:07:16.399293 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11174 08:07:16.410415 /lava-11585986/1/../bin/lava-test-case
11175 08:07:16.416478 <8>[ 18.288082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11176 08:07:16.417324 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11178 08:07:16.428008 /lava-11585986/1/../bin/lava-test-case
11179 08:07:16.434474 <8>[ 18.305415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11180 08:07:16.435315 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11182 08:07:16.444714 /lava-11585986/1/../bin/lava-test-case
11183 08:07:16.450963 <8>[ 18.324430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11184 08:07:16.451901 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11186 08:07:16.463702 /lava-11585986/1/../bin/lava-test-case
11187 08:07:16.470483 <8>[ 18.342179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11188 08:07:16.471343 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11190 08:07:16.478348 /lava-11585986/1/../bin/lava-test-case
11191 08:07:16.485104 <8>[ 18.357419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11192 08:07:16.485946 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11194 08:07:16.503988 /lava-11585986/1/../bin/lava-tes<8>[ 18.375077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11195 08:07:16.504559 t-case
11196 08:07:16.505250 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11198 08:07:16.513726 /lava-11585986/1/../bin/lava-test-case
11199 08:07:16.524543 <8>[ 18.394442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11200 08:07:16.525390 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11202 08:07:16.533615 /lava-11585986/1/../bin/lava-test-case
11203 08:07:16.542988 <8>[ 18.414124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11204 08:07:16.543861 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11206 08:07:16.550722 /lava-11585986/1/../bin/lava-test-case
11207 08:07:16.557212 <8>[ 18.429328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11208 08:07:16.558057 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11210 08:07:16.568525 /lava-11585986/1/../bin/lava-test-case
11211 08:07:16.574959 <8>[ 18.447241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11212 08:07:16.575843 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11214 08:07:16.589795 /lava-11585986/1/../bin/lava-test-case
11215 08:07:16.596204 <8>[ 18.468690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11216 08:07:16.597154 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11218 08:07:16.607125 /lava-11585986/1/../bin/lava-test-case
11219 08:07:16.613206 <8>[ 18.484494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11220 08:07:16.614068 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11222 08:07:16.625902 /lava-11585986/1/../bin/lava-test-case
11223 08:07:16.633081 <8>[ 18.505174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11224 08:07:16.633937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11226 08:07:16.652292 /lava-11585986/1/../bin/lava-tes<8>[ 18.523006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11227 08:07:16.652861 t-case
11228 08:07:16.653516 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11230 08:07:16.660820 /lava-11585986/1/../bin/lava-test-case
11231 08:07:16.667581 <8>[ 18.539413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11232 08:07:16.668479 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11234 08:07:16.678963 /lava-11585986/1/../bin/lava-test-case
11235 08:07:16.685896 <8>[ 18.557032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11236 08:07:16.686758 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11238 08:07:16.701620 /lava-11585986/1/../bin/lava-tes<8>[ 18.572851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11239 08:07:16.702180 t-case
11240 08:07:16.702818 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11242 08:07:16.714938 /lava-11585986/1/../bin/lava-test-case
11243 08:07:16.721126 <8>[ 18.593027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11244 08:07:16.721978 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11246 08:07:16.738366 /lava-11585986/1/../bin/lava-tes<8>[ 18.608877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11247 08:07:16.738944 t-case
11248 08:07:16.739595 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11250 08:07:16.758333 /lava-11585986/1/../bin/lava-tes<8>[ 18.629011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11251 08:07:16.758898 t-case
11252 08:07:16.759538 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11254 08:07:16.770523 /lava-11585986/1/../bin/lava-test-case
11255 08:07:16.776389 <8>[ 18.647393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11256 08:07:16.777138 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11258 08:07:16.787637 /lava-11585986/1/../bin/lava-test-case
11259 08:07:16.794515 <8>[ 18.665833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11260 08:07:16.795374 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11262 08:07:16.804323 /lava-11585986/1/../bin/lava-test-case
11263 08:07:16.810952 <8>[ 18.683934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11264 08:07:16.811852 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11266 08:07:16.825297 /lava-11585986/1/../bin/lava-test-case
11267 08:07:16.831237 <8>[ 18.702431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11268 08:07:16.832155 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11270 08:07:16.839924 /lava-11585986/1/../bin/lava-test-case
11271 08:07:16.846070 <8>[ 18.719223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11272 08:07:16.847016 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11274 08:07:16.859866 /lava-11585986/1/../bin/lava-test-case
11275 08:07:16.866127 <8>[ 18.737689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11276 08:07:16.866992 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11278 08:07:16.880549 /lava-11585986/1/../bin/lava-tes<8>[ 18.751710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11279 08:07:16.881110 t-case
11280 08:07:16.881749 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11282 08:07:16.899144 /lava-11585986/1/../bin/lava-tes<8>[ 18.769968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11283 08:07:16.899709 t-case
11284 08:07:16.900396 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11286 08:07:16.914957 /lava-11585986/1/../bin/lava-tes<8>[ 18.785521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11287 08:07:16.915522 t-case
11288 08:07:16.916210 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11290 08:07:16.924714 /lava-11585986/1/../bin/lava-test-case
11291 08:07:16.931638 <8>[ 18.803378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11292 08:07:16.932515 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11294 08:07:16.947857 /lava-11585986/1/../bin/lava-tes<8>[ 18.818803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11295 08:07:16.948426 t-case
11296 08:07:16.949069 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11298 08:07:16.968914 /lava-11585986/1/../bin/lava-tes<8>[ 18.839363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11299 08:07:16.969498 t-case
11300 08:07:16.970205 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11302 08:07:16.983851 /lava-11585986/1/../bin/lava-tes<8>[ 18.854663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11303 08:07:16.984419 t-case
11304 08:07:16.985059 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11306 08:07:17.004625 /lava-11585986/1/../bin/lava-tes<8>[ 18.875534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11307 08:07:17.005203 t-case
11308 08:07:17.005845 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11310 08:07:17.012287 /lava-11585986/1/../bin/lava-test-case
11311 08:07:17.018306 <8>[ 18.890432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11312 08:07:17.019148 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11314 08:07:17.038002 /lava-11585986/1/../bin/lava-tes<8>[ 18.908326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11315 08:07:17.038567 t-case
11316 08:07:17.039209 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11318 08:07:17.054518 /lava-11585986/1/../bin/lava-tes<8>[ 18.925597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11319 08:07:17.055202 t-case
11320 08:07:17.055875 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11322 08:07:17.071270 /lava-11585986/1/../bin/lava-tes<8>[ 18.942267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11323 08:07:17.071887 t-case
11324 08:07:17.072537 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11326 08:07:17.080931 /lava-11585986/1/../bin/lava-test-case
11327 08:07:17.087364 <8>[ 18.960572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11328 08:07:17.088180 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11330 08:07:17.097253 /lava-11585986/1/../bin/lava-test-case
11331 08:07:17.103769 <8>[ 18.975026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11332 08:07:17.104590 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11334 08:07:17.117410 /lava-11585986/1/../bin/lava-test-case
11335 08:07:17.124288 <8>[ 18.995625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11336 08:07:17.125144 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11338 08:07:17.138681 /lava-11585986/1/../bin/lava-tes<8>[ 19.009176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11339 08:07:17.139246 t-case
11340 08:07:17.139867 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11342 08:07:18.153615 /lava-11585986/1/../bin/lava-test-case
11343 08:07:18.160086 <8>[ 20.031755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11344 08:07:18.160824 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11346 08:07:18.180525 /lava-11585986/1/../bin/lava-tes<8>[ 20.051828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11347 08:07:18.181081 t-case
11348 08:07:18.181713 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11350 08:07:19.194458 /lava-11585986/1/../bin/lava-test-case
11351 08:07:19.201245 <8>[ 21.073767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11352 08:07:19.202089 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11354 08:07:19.211868 /lava-11585986/1/../bin/lava-test-case
11355 08:07:19.217527 <8>[ 21.089375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11356 08:07:19.218313 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11358 08:07:20.232555 /lava-11585986/1/../bin/lava-test-case
11359 08:07:20.238533 <8>[ 22.111618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11360 08:07:20.239137 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11362 08:07:20.247693 /lava-11585986/1/../bin/lava-test-case
11363 08:07:20.254439 <8>[ 22.126811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11364 08:07:20.254798 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11366 08:07:21.270166 /lava-11585986/1/../bin/lava-test-case
11367 08:07:21.276748 <8>[ 23.149127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11368 08:07:21.277594 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11370 08:07:21.294613 /lava-11585986/1/../bin/lava-tes<8>[ 23.166085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11371 08:07:21.295181 t-case
11372 08:07:21.295870 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11374 08:07:22.308628 /lava-11585986/1/../bin/lava-test-case
11375 08:07:22.315345 <8>[ 24.188331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11376 08:07:22.316239 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11378 08:07:22.325537 /lava-11585986/1/../bin/lava-test-case
11379 08:07:22.332480 <8>[ 24.204544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11380 08:07:22.333334 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11382 08:07:23.347536 /lava-11585986/1/../bin/lava-test-case
11383 08:07:23.354904 <8>[ 25.227402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11384 08:07:23.355785 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11386 08:07:23.364361 /lava-11585986/1/../bin/lava-test-case
11387 08:07:23.371050 <8>[ 25.243463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11388 08:07:23.371875 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11390 08:07:24.385461 /lava-11585986/1/../bin/lava-test-case
11391 08:07:24.392634 <8>[ 26.264792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11392 08:07:24.393475 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11394 08:07:24.413221 /lava-11585986/1/../bin/lava-tes<8>[ 26.284980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11395 08:07:24.413875 t-case
11396 08:07:24.414658 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11398 08:07:24.429480 /lava-11585986/1/../bin/lava-tes<8>[ 26.301371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11399 08:07:24.430046 t-case
11400 08:07:24.430689 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11402 08:07:25.444198 /lava-11585986/1/../bin/lava-test-case
11403 08:07:25.451155 <8>[ 27.325006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11404 08:07:25.452039 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11406 08:07:25.461914 /lava-11585986/1/../bin/lava-test-case
11407 08:07:25.468707 <8>[ 27.341285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11408 08:07:25.469547 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11410 08:07:25.489723 /lava-11585986/1/../bin/lava-tes<8>[ 27.361564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11411 08:07:25.490281 t-case
11412 08:07:25.490914 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11414 08:07:25.499477 /lava-11585986/1/../bin/lava-test-case
11415 08:07:25.505795 <8>[ 27.378471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11416 08:07:25.506645 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11418 08:07:25.517897 /lava-11585986/1/../bin/lava-test-case
11419 08:07:25.524288 <8>[ 27.396608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11420 08:07:25.525106 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11422 08:07:25.535274 /lava-11585986/1/../bin/lava-test-case
11423 08:07:25.541851 <8>[ 27.414235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11424 08:07:25.542689 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11426 08:07:25.551920 /lava-11585986/1/../bin/lava-test-case
11427 08:07:25.558672 <8>[ 27.432134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11428 08:07:25.559524 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11430 08:07:25.568654 /lava-11585986/1/../bin/lava-test-case
11431 08:07:25.575418 <8>[ 27.447940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11432 08:07:25.576326 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11434 08:07:25.587497 /lava-11585986/1/../bin/lava-test-case
11435 08:07:25.593896 <8>[ 27.466533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11436 08:07:25.594756 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11438 08:07:25.605283 /lava-11585986/1/../bin/lava-test-case
11439 08:07:25.611677 <8>[ 27.484678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11440 08:07:25.612453 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11442 08:07:25.621068 /lava-11585986/1/../bin/lava-test-case
11443 08:07:25.627360 <8>[ 27.500577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11444 08:07:25.628274 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11446 08:07:25.643531 /lava-11585986/1/../bin/lava-test-case
11447 08:07:25.651063 <8>[ 27.522171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11448 08:07:25.651952 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11450 08:07:25.658322 /lava-11585986/1/../bin/lava-test-case
11451 08:07:25.665616 <8>[ 27.537086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11452 08:07:25.666496 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11454 08:07:25.678687 /lava-11585986/1/../bin/lava-test-case
11455 08:07:25.685168 <8>[ 27.557256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11456 08:07:25.686045 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11458 08:07:25.703381 /lava-11585986/1/../bin/lava-tes<8>[ 27.575077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11459 08:07:25.704008 t-case
11460 08:07:25.704771 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11462 08:07:25.713361 /lava-11585986/1/../bin/lava-test-case
11463 08:07:25.720007 <8>[ 27.594433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11464 08:07:25.720755 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11466 08:07:25.730714 /lava-11585986/1/../bin/lava-test-case
11467 08:07:25.737148 <8>[ 27.610477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11468 08:07:25.738015 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11470 08:07:25.749682 /lava-11585986/1/../bin/lava-test-case
11471 08:07:25.756095 <8>[ 27.628745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11472 08:07:25.756934 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11474 08:07:25.768860 /lava-11585986/1/../bin/lava-test-case
11475 08:07:25.775183 <8>[ 27.647454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11476 08:07:25.776094 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11478 08:07:25.785716 /lava-11585986/1/../bin/lava-test-case
11479 08:07:25.792691 <8>[ 27.665529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11480 08:07:25.793551 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11482 08:07:25.810835 /lava-11585986/1/../bin/lava-tes<8>[ 27.683001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11483 08:07:25.811470 t-case
11484 08:07:25.812173 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11486 08:07:26.822328 /lava-11585986/1/../bin/lava-test-case
11487 08:07:26.829238 <8>[ 28.701724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11488 08:07:26.830095 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11490 08:07:27.844574 /lava-11585986/1/../bin/lava-test-case
11491 08:07:27.850386 <8>[ 29.725302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11492 08:07:27.851219 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11494 08:07:27.867901 /lava-11585986/1/../bin/lava-tes<8>[ 29.739888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11495 08:07:27.868474 t-case
11496 08:07:27.869125 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11498 08:07:27.879681 /lava-11585986/1/../bin/lava-test-case
11499 08:07:27.886427 <8>[ 29.758916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11500 08:07:27.887286 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11502 08:07:27.894945 /lava-11585986/1/../bin/lava-test-case
11503 08:07:27.901435 <8>[ 29.774458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11504 08:07:27.902297 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11506 08:07:27.913510 /lava-11585986/1/../bin/lava-test-case
11507 08:07:27.920344 <8>[ 29.793685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11508 08:07:27.921208 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11510 08:07:27.928694 /lava-11585986/1/../bin/lava-test-case
11511 08:07:27.935631 <8>[ 29.808977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11512 08:07:27.936441 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11514 08:07:27.946471 /lava-11585986/1/../bin/lava-test-case
11515 08:07:27.952851 <8>[ 29.825591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11516 08:07:27.953708 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11518 08:07:27.960491 /lava-11585986/1/../bin/lava-test-case
11519 08:07:27.967046 <8>[ 29.840308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11520 08:07:27.967903 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11522 08:07:27.979819 /lava-11585986/1/../bin/lava-test-case
11523 08:07:27.985060 <8>[ 29.857566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11524 08:07:27.985919 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11526 08:07:27.993473 /lava-11585986/1/../bin/lava-test-case
11527 08:07:28.000418 <8>[ 29.873526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11528 08:07:28.001290 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11530 08:07:28.015214 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11532 08:07:28.018221 /lava-11585986/1/../bin/lava-tes<8>[ 29.890210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11533 08:07:28.018795 t-case
11534 08:07:28.034375 /lava-11585986/1/../bin/lava-tes<8>[ 29.905893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11535 08:07:28.034953 t-case
11536 08:07:28.035609 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11538 08:07:28.051966 /lava-11585986/1/../bin/lava-tes<8>[ 29.923807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11539 08:07:28.052649 t-case
11540 08:07:28.053380 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11542 08:07:28.066656 /lava-11585986/1/../bin/lava-tes<8>[ 29.938894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11543 08:07:28.067233 t-case
11544 08:07:28.067870 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11546 08:07:28.081559 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11548 08:07:28.084557 /lava-11585986/1/../bin/lava-tes<8>[ 29.956441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11549 08:07:28.085136 t-case
11550 08:07:28.091607 /lava-11585986/1/../bin/lava-test-case
11551 08:07:28.102442 <8>[ 29.973581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11552 08:07:28.103308 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11554 08:07:28.111896 /lava-11585986/1/../bin/lava-test-case
11555 08:07:28.118010 <8>[ 29.992639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11556 08:07:28.118846 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11558 08:07:28.134798 /lava-11585986/1/../bin/lava-tes<8>[ 30.007409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11559 08:07:28.135353 t-case
11560 08:07:28.136035 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11562 08:07:28.144422 /lava-11585986/1/../bin/lava-test-case
11563 08:07:28.151227 <8>[ 30.024571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11564 08:07:28.152118 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11566 08:07:28.159768 /lava-11585986/1/../bin/lava-test-case
11567 08:07:28.165715 <8>[ 30.038745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11568 08:07:28.166586 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11570 08:07:28.176669 /lava-11585986/1/../bin/lava-test-case
11571 08:07:28.188484 <8>[ 30.060622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11572 08:07:28.189354 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11574 08:07:29.198761 /lava-11585986/1/../bin/lava-test-case
11575 08:07:29.208725 <8>[ 31.080277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11576 08:07:29.209586 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11578 08:07:30.220272 /lava-11585986/1/../bin/lava-test-case
11579 08:07:30.226787 <8>[ 32.101749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11580 08:07:30.227627 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11581 08:07:30.228149 Bad test result: blocked
11582 08:07:30.237379 /lava-11585986/1/../bin/lava-test-case
11583 08:07:30.243647 <8>[ 32.116770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11584 08:07:30.244433 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11586 08:07:31.259885 /lava-11585986/1/../bin/lava-test-case
11587 08:07:31.266241 <8>[ 33.140974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11588 08:07:31.266543 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11590 08:07:31.282741 /lava-11585986/1/../bin/lava-tes<8>[ 33.155595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11591 08:07:31.282920 t-case
11592 08:07:31.283195 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11594 08:07:31.296695 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11596 08:07:31.299697 /lava-11585986/1/../bin/lava-tes<8>[ 33.172455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11597 08:07:31.299941 t-case
11598 08:07:31.308556 /lava-11585986/1/../bin/lava-test-case
11599 08:07:31.315347 <8>[ 33.188822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11600 08:07:31.316259 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11602 08:07:31.325644 /lava-11585986/1/../bin/lava-test-case
11603 08:07:31.332438 <8>[ 33.206868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11604 08:07:31.333273 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11606 08:07:31.343639 /lava-11585986/1/../bin/lava-test-case
11607 08:07:31.354971 <8>[ 33.228303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11608 08:07:31.355865 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11610 08:07:31.370757 /lava-11585986/1/../bin/lava-tes<8>[ 33.243502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11611 08:07:31.371544 t-case
11612 08:07:31.372282 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11614 08:07:32.385721 /lava-11585986/1/../bin/lava-test-case
11615 08:07:32.391877 <8>[ 34.266519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11616 08:07:32.392737 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11618 08:07:32.402617 /lava-11585986/1/../bin/lava-test-case
11619 08:07:32.409786 <8>[ 34.282680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11620 08:07:32.410638 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11622 08:07:33.423234 /lava-11585986/1/../bin/lava-test-case
11623 08:07:33.429708 <8>[ 35.304719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11624 08:07:33.430454 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11626 08:07:33.446690 /lava-11585986/1/../bin/lava-tes<8>[ 35.319750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11627 08:07:33.447257 t-case
11628 08:07:33.447898 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11630 08:07:34.460426 /lava-11585986/1/../bin/lava-test-case
11631 08:07:34.466597 <8>[ 36.340855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11632 08:07:34.467393 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11634 08:07:34.487241 /lava-11585986/1/../bin/lava-tes<8>[ 36.360361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11635 08:07:34.487843 t-case
11636 08:07:34.488495 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11638 08:07:35.503124 /lava-11585986/1/../bin/lava-test-case
11639 08:07:35.509797 <8>[ 37.384993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11640 08:07:35.510656 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11642 08:07:35.520955 /lava-11585986/1/../bin/lava-test-case
11643 08:07:35.527545 <8>[ 37.401183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11644 08:07:35.528450 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11646 08:07:35.538858 /lava-11585986/1/../bin/lava-test-case
11647 08:07:35.545494 <8>[ 37.418955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11648 08:07:35.546347 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11650 08:07:35.557924 /lava-11585986/1/../bin/lava-tes<8>[ 37.434193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11651 08:07:35.558785 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11653 08:07:35.561022 t-case
11654 08:07:35.577788 /lava-11585986/1/../bin/lava-tes<8>[ 37.450964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11655 08:07:35.578342 t-case
11656 08:07:35.578990 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11658 08:07:35.587420 /lava-11585986/1/../bin/lava-test-case
11659 08:07:35.593723 <8>[ 37.468444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11660 08:07:35.594565 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11662 08:07:35.604090 /lava-11585986/1/../bin/lava-test-case
11663 08:07:35.609862 <8>[ 37.483376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11664 08:07:35.610686 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11666 08:07:35.621815 /lava-11585986/1/../bin/lava-test-case
11667 08:07:35.627291 <8>[ 37.502588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11668 08:07:35.628298 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11670 08:07:35.637174 /lava-11585986/1/../bin/lava-test-case
11671 08:07:35.643857 <8>[ 37.517392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11672 08:07:35.644704 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11674 08:07:35.654317 /lava-11585986/1/../bin/lava-test-case
11675 08:07:35.665100 <8>[ 37.539061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11676 08:07:35.665943 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11678 08:07:35.669321 + set +x
11679 08:07:35.672731 Received signal: <ENDRUN> 1_bootrr 11585986_1.5.2.3.5
11680 08:07:35.673219 Ending use of test pattern.
11681 08:07:35.673590 Ending test lava.1_bootrr (11585986_1.5.2.3.5), duration 20.35
11683 08:07:35.675693 <8>[ 37.549624] <LAVA_SIGNAL_ENDRUN 1_bootrr 11585986_1.5.2.3.5>
11684 08:07:35.676206 <LAVA_TEST_RUNNER EXIT>
11685 08:07:35.677062 ok: lava_test_shell seems to have completed
11686 08:07:35.682556 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11687 08:07:35.683328 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11688 08:07:35.683846 end: 4 lava-test-retry (duration 00:00:21) [common]
11689 08:07:35.684347 start: 5 finalize (timeout 00:08:04) [common]
11690 08:07:35.684832 start: 5.1 power-off (timeout 00:00:30) [common]
11691 08:07:35.685673 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11692 08:07:35.772140 >> Command sent successfully.
11693 08:07:35.776326 Returned 0 in 0 seconds
11694 08:07:35.877297 end: 5.1 power-off (duration 00:00:00) [common]
11696 08:07:35.879210 start: 5.2 read-feedback (timeout 00:08:04) [common]
11697 08:07:35.880582 Listened to connection for namespace 'common' for up to 1s
11698 08:07:35.881447 Listened to connection for namespace 'common' for up to 1s
11699 08:07:36.881241 Finalising connection for namespace 'common'
11700 08:07:36.881954 Disconnecting from shell: Finalise
11701 08:07:36.882383 / #
11702 08:07:36.983394 end: 5.2 read-feedback (duration 00:00:01) [common]
11703 08:07:36.984236 end: 5 finalize (duration 00:00:01) [common]
11704 08:07:36.984835 Cleaning after the job
11705 08:07:36.985416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/ramdisk
11706 08:07:36.999634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/kernel
11707 08:07:37.027718 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/dtb
11708 08:07:37.028117 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585986/tftp-deploy-5pxa7njy/modules
11709 08:07:37.039766 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11585986
11710 08:07:37.089081 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11585986
11711 08:07:37.089260 Job finished correctly