Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 133
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 08:04:55.881696 lava-dispatcher, installed at version: 2023.06
2 08:04:55.881911 start: 0 validate
3 08:04:55.882044 Start time: 2023-09-21 08:04:55.882036+00:00 (UTC)
4 08:04:55.882174 Using caching service: 'http://localhost/cache/?uri=%s'
5 08:04:55.882324 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 08:04:56.159380 Using caching service: 'http://localhost/cache/?uri=%s'
7 08:04:56.159735 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 08:05:23.440511 Using caching service: 'http://localhost/cache/?uri=%s'
9 08:05:23.440767 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 08:05:23.712551 Using caching service: 'http://localhost/cache/?uri=%s'
11 08:05:23.713499 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 08:05:28.482682 validate duration: 32.60
14 08:05:28.484029 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:05:28.484598 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:05:28.485097 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:05:28.485743 Not decompressing ramdisk as can be used compressed.
18 08:05:28.486260 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 08:05:28.486627 saving as /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/ramdisk/rootfs.cpio.gz
20 08:05:28.486987 total size: 84918747 (80 MB)
21 08:05:28.756328 progress 0 % (0 MB)
22 08:05:28.778602 progress 5 % (4 MB)
23 08:05:28.800875 progress 10 % (8 MB)
24 08:05:28.823026 progress 15 % (12 MB)
25 08:05:28.845215 progress 20 % (16 MB)
26 08:05:28.867314 progress 25 % (20 MB)
27 08:05:28.889688 progress 30 % (24 MB)
28 08:05:28.912013 progress 35 % (28 MB)
29 08:05:28.934128 progress 40 % (32 MB)
30 08:05:28.956419 progress 45 % (36 MB)
31 08:05:28.978454 progress 50 % (40 MB)
32 08:05:29.000903 progress 55 % (44 MB)
33 08:05:29.023015 progress 60 % (48 MB)
34 08:05:29.045164 progress 65 % (52 MB)
35 08:05:29.067530 progress 70 % (56 MB)
36 08:05:29.089571 progress 75 % (60 MB)
37 08:05:29.111893 progress 80 % (64 MB)
38 08:05:29.134145 progress 85 % (68 MB)
39 08:05:29.156294 progress 90 % (72 MB)
40 08:05:29.178310 progress 95 % (76 MB)
41 08:05:29.199995 progress 100 % (80 MB)
42 08:05:29.200226 80 MB downloaded in 0.71 s (113.54 MB/s)
43 08:05:29.200389 end: 1.1.1 http-download (duration 00:00:01) [common]
45 08:05:29.200631 end: 1.1 download-retry (duration 00:00:01) [common]
46 08:05:29.200719 start: 1.2 download-retry (timeout 00:09:59) [common]
47 08:05:29.200804 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 08:05:29.200937 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 08:05:29.201008 saving as /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/kernel/Image
50 08:05:29.201070 total size: 49304064 (47 MB)
51 08:05:29.201133 No compression specified
52 08:05:29.202238 progress 0 % (0 MB)
53 08:05:29.215070 progress 5 % (2 MB)
54 08:05:29.227939 progress 10 % (4 MB)
55 08:05:29.241158 progress 15 % (7 MB)
56 08:05:29.254365 progress 20 % (9 MB)
57 08:05:29.267451 progress 25 % (11 MB)
58 08:05:29.280453 progress 30 % (14 MB)
59 08:05:29.293425 progress 35 % (16 MB)
60 08:05:29.306342 progress 40 % (18 MB)
61 08:05:29.319420 progress 45 % (21 MB)
62 08:05:29.332417 progress 50 % (23 MB)
63 08:05:29.345214 progress 55 % (25 MB)
64 08:05:29.358149 progress 60 % (28 MB)
65 08:05:29.371255 progress 65 % (30 MB)
66 08:05:29.384511 progress 70 % (32 MB)
67 08:05:29.397374 progress 75 % (35 MB)
68 08:05:29.410364 progress 80 % (37 MB)
69 08:05:29.423259 progress 85 % (39 MB)
70 08:05:29.436435 progress 90 % (42 MB)
71 08:05:29.449041 progress 95 % (44 MB)
72 08:05:29.461592 progress 100 % (47 MB)
73 08:05:29.461885 47 MB downloaded in 0.26 s (180.28 MB/s)
74 08:05:29.462064 end: 1.2.1 http-download (duration 00:00:00) [common]
76 08:05:29.462330 end: 1.2 download-retry (duration 00:00:00) [common]
77 08:05:29.462436 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:05:29.462546 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:05:29.462707 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 08:05:29.462812 saving as /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/dtb/mt8192-asurada-spherion-r0.dtb
81 08:05:29.462915 total size: 47278 (0 MB)
82 08:05:29.463017 No compression specified
83 08:05:29.464715 progress 69 % (0 MB)
84 08:05:29.465020 progress 100 % (0 MB)
85 08:05:29.465194 0 MB downloaded in 0.00 s (19.80 MB/s)
86 08:05:29.465336 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:05:29.465590 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:05:29.465694 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:05:29.465800 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:05:29.465934 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 08:05:29.466033 saving as /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/modules/modules.tar
93 08:05:29.466133 total size: 8625188 (8 MB)
94 08:05:29.466235 Using unxz to decompress xz
95 08:05:29.470864 progress 0 % (0 MB)
96 08:05:29.493845 progress 5 % (0 MB)
97 08:05:29.517415 progress 10 % (0 MB)
98 08:05:29.544889 progress 15 % (1 MB)
99 08:05:29.571440 progress 20 % (1 MB)
100 08:05:29.598576 progress 25 % (2 MB)
101 08:05:29.626929 progress 30 % (2 MB)
102 08:05:29.654628 progress 35 % (2 MB)
103 08:05:29.679745 progress 40 % (3 MB)
104 08:05:29.705916 progress 45 % (3 MB)
105 08:05:29.735686 progress 50 % (4 MB)
106 08:05:29.761208 progress 55 % (4 MB)
107 08:05:29.789775 progress 60 % (4 MB)
108 08:05:29.816453 progress 65 % (5 MB)
109 08:05:29.845645 progress 70 % (5 MB)
110 08:05:29.871491 progress 75 % (6 MB)
111 08:05:29.898381 progress 80 % (6 MB)
112 08:05:29.927960 progress 85 % (7 MB)
113 08:05:29.955089 progress 90 % (7 MB)
114 08:05:29.981081 progress 95 % (7 MB)
115 08:05:30.004539 progress 100 % (8 MB)
116 08:05:30.009595 8 MB downloaded in 0.54 s (15.14 MB/s)
117 08:05:30.009850 end: 1.4.1 http-download (duration 00:00:01) [common]
119 08:05:30.010109 end: 1.4 download-retry (duration 00:00:01) [common]
120 08:05:30.010203 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 08:05:30.010299 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 08:05:30.010380 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:05:30.010469 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 08:05:30.010710 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z
125 08:05:30.010846 makedir: /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin
126 08:05:30.010952 makedir: /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/tests
127 08:05:30.011051 makedir: /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/results
128 08:05:30.011217 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-add-keys
129 08:05:30.011364 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-add-sources
130 08:05:30.011538 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-background-process-start
131 08:05:30.011670 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-background-process-stop
132 08:05:30.011799 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-common-functions
133 08:05:30.011923 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-echo-ipv4
134 08:05:30.012049 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-install-packages
135 08:05:30.012173 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-installed-packages
136 08:05:30.012296 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-os-build
137 08:05:30.012421 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-probe-channel
138 08:05:30.012544 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-probe-ip
139 08:05:30.012667 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-target-ip
140 08:05:30.012790 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-target-mac
141 08:05:30.012914 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-target-storage
142 08:05:30.013042 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-case
143 08:05:30.013167 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-event
144 08:05:30.013290 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-feedback
145 08:05:30.013412 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-raise
146 08:05:30.013537 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-reference
147 08:05:30.013661 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-runner
148 08:05:30.013783 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-set
149 08:05:30.013909 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-test-shell
150 08:05:30.014036 Updating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-install-packages (oe)
151 08:05:30.014196 Updating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/bin/lava-installed-packages (oe)
152 08:05:30.014323 Creating /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/environment
153 08:05:30.014427 LAVA metadata
154 08:05:30.014505 - LAVA_JOB_ID=11585978
155 08:05:30.014570 - LAVA_DISPATCHER_IP=192.168.201.1
156 08:05:30.014673 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 08:05:30.014738 skipped lava-vland-overlay
158 08:05:30.014811 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 08:05:30.014894 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 08:05:30.014955 skipped lava-multinode-overlay
161 08:05:30.015029 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 08:05:30.015162 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 08:05:30.015251 Loading test definitions
164 08:05:30.015408 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 08:05:30.015511 Using /lava-11585978 at stage 0
166 08:05:30.015637 Fetching tests from https://github.com/kernelci/kernelci-core
167 08:05:30.015732 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/0/tests/0_sleep'
168 08:05:30.879489 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/0/tests/0_sleep
169 08:05:30.880829 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 08:05:30.881240 uuid=11585978_1.5.2.3.1 testdef=None
171 08:05:30.881392 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 08:05:30.881648 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 08:05:30.882228 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 08:05:30.882457 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 08:05:30.883201 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 08:05:30.883476 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 08:05:30.884143 runner path: /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/0/tests/0_sleep test_uuid 11585978_1.5.2.3.1
181 08:05:30.884228 sleep_params='mem freeze'
182 08:05:30.884371 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 08:05:30.884585 Creating lava-test-runner.conf files
185 08:05:30.884651 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11585978/lava-overlay-0ydpja7z/lava-11585978/0 for stage 0
186 08:05:30.884804 - 0_sleep
187 08:05:30.884991 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 08:05:30.885117 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 08:05:31.010576 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 08:05:31.010734 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
191 08:05:31.010828 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 08:05:31.010928 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 08:05:31.011067 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
194 08:05:33.501278 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 08:05:33.501672 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 08:05:33.501798 extracting modules file /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11585978/extract-overlay-ramdisk-_lf5s4bc/ramdisk
197 08:05:33.731862 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 08:05:33.732037 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 08:05:33.732137 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585978/compress-overlay-s1bakry7/overlay-1.5.2.4.tar.gz to ramdisk
200 08:05:33.732214 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585978/compress-overlay-s1bakry7/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11585978/extract-overlay-ramdisk-_lf5s4bc/ramdisk
201 08:05:33.827926 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 08:05:33.828096 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 08:05:33.828191 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 08:05:33.828281 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 08:05:33.828363 Building ramdisk /var/lib/lava/dispatcher/tmp/11585978/extract-overlay-ramdisk-_lf5s4bc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11585978/extract-overlay-ramdisk-_lf5s4bc/ramdisk
206 08:05:35.386965 >> 563443 blocks
207 08:05:44.978628 rename /var/lib/lava/dispatcher/tmp/11585978/extract-overlay-ramdisk-_lf5s4bc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/ramdisk/ramdisk.cpio.gz
208 08:05:44.979116 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 08:05:44.979262 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 08:05:44.979394 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 08:05:44.979524 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/kernel/Image'
212 08:05:57.521945 Returned 0 in 12 seconds
213 08:05:57.622924 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/kernel/image.itb
214 08:05:59.013127 output: FIT description: Kernel Image image with one or more FDT blobs
215 08:05:59.013510 output: Created: Thu Sep 21 09:05:58 2023
216 08:05:59.013608 output: Image 0 (kernel-1)
217 08:05:59.013689 output: Description:
218 08:05:59.013769 output: Created: Thu Sep 21 09:05:58 2023
219 08:05:59.013846 output: Type: Kernel Image
220 08:05:59.013913 output: Compression: lzma compressed
221 08:05:59.013975 output: Data Size: 11045265 Bytes = 10786.39 KiB = 10.53 MiB
222 08:05:59.014038 output: Architecture: AArch64
223 08:05:59.014099 output: OS: Linux
224 08:05:59.014157 output: Load Address: 0x00000000
225 08:05:59.014211 output: Entry Point: 0x00000000
226 08:05:59.014274 output: Hash algo: crc32
227 08:05:59.014329 output: Hash value: 886bc8a0
228 08:05:59.014392 output: Image 1 (fdt-1)
229 08:05:59.014446 output: Description: mt8192-asurada-spherion-r0
230 08:05:59.014501 output: Created: Thu Sep 21 09:05:58 2023
231 08:05:59.014555 output: Type: Flat Device Tree
232 08:05:59.014608 output: Compression: uncompressed
233 08:05:59.014662 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 08:05:59.014726 output: Architecture: AArch64
235 08:05:59.014781 output: Hash algo: crc32
236 08:05:59.014834 output: Hash value: cc4352de
237 08:05:59.014887 output: Image 2 (ramdisk-1)
238 08:05:59.014941 output: Description: unavailable
239 08:05:59.014994 output: Created: Thu Sep 21 09:05:58 2023
240 08:05:59.015048 output: Type: RAMDisk Image
241 08:05:59.015101 output: Compression: Unknown Compression
242 08:05:59.015153 output: Data Size: 98307938 Bytes = 96003.85 KiB = 93.75 MiB
243 08:05:59.015207 output: Architecture: AArch64
244 08:05:59.015261 output: OS: Linux
245 08:05:59.015314 output: Load Address: unavailable
246 08:05:59.015382 output: Entry Point: unavailable
247 08:05:59.015445 output: Hash algo: crc32
248 08:05:59.015498 output: Hash value: 42f17b23
249 08:05:59.015551 output: Default Configuration: 'conf-1'
250 08:05:59.015604 output: Configuration 0 (conf-1)
251 08:05:59.015657 output: Description: mt8192-asurada-spherion-r0
252 08:05:59.015711 output: Kernel: kernel-1
253 08:05:59.015775 output: Init Ramdisk: ramdisk-1
254 08:05:59.015828 output: FDT: fdt-1
255 08:05:59.015881 output: Loadables: kernel-1
256 08:05:59.015934 output:
257 08:05:59.016143 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 08:05:59.016240 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 08:05:59.016349 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 08:05:59.016447 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
261 08:05:59.016530 No LXC device requested
262 08:05:59.016612 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 08:05:59.016698 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
264 08:05:59.016780 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 08:05:59.016857 Checking files for TFTP limit of 4294967296 bytes.
266 08:05:59.017363 end: 1 tftp-deploy (duration 00:00:31) [common]
267 08:05:59.017484 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 08:05:59.017589 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 08:05:59.017714 substitutions:
270 08:05:59.017781 - {DTB}: 11585978/tftp-deploy-wcgepl6x/dtb/mt8192-asurada-spherion-r0.dtb
271 08:05:59.017847 - {INITRD}: 11585978/tftp-deploy-wcgepl6x/ramdisk/ramdisk.cpio.gz
272 08:05:59.017919 - {KERNEL}: 11585978/tftp-deploy-wcgepl6x/kernel/Image
273 08:05:59.017979 - {LAVA_MAC}: None
274 08:05:59.018037 - {PRESEED_CONFIG}: None
275 08:05:59.018094 - {PRESEED_LOCAL}: None
276 08:05:59.018151 - {RAMDISK}: 11585978/tftp-deploy-wcgepl6x/ramdisk/ramdisk.cpio.gz
277 08:05:59.018208 - {ROOT_PART}: None
278 08:05:59.018263 - {ROOT}: None
279 08:05:59.018318 - {SERVER_IP}: 192.168.201.1
280 08:05:59.018373 - {TEE}: None
281 08:05:59.018438 Parsed boot commands:
282 08:05:59.018501 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 08:05:59.018694 Parsed boot commands: tftpboot 192.168.201.1 11585978/tftp-deploy-wcgepl6x/kernel/image.itb 11585978/tftp-deploy-wcgepl6x/kernel/cmdline
284 08:05:59.018789 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 08:05:59.018871 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 08:05:59.018973 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 08:05:59.019061 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 08:05:59.019136 Not connected, no need to disconnect.
289 08:05:59.019210 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 08:05:59.019291 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 08:05:59.019358 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
292 08:05:59.023477 Setting prompt string to ['lava-test: # ']
293 08:05:59.023872 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 08:05:59.023984 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 08:05:59.024087 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 08:05:59.024180 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 08:05:59.024379 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
298 08:06:04.164426 >> Command sent successfully.
299 08:06:04.167034 Returned 0 in 5 seconds
300 08:06:04.267446 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 08:06:04.267787 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 08:06:04.267905 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 08:06:04.267995 Setting prompt string to 'Starting depthcharge on Spherion...'
305 08:06:04.268078 Changing prompt to 'Starting depthcharge on Spherion...'
306 08:06:04.268149 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 08:06:04.268473 [Enter `^Ec?' for help]
308 08:06:04.439351
309 08:06:04.439532
310 08:06:04.439604 F0: 102B 0000
311 08:06:04.439667
312 08:06:04.439727 F3: 1001 0000 [0200]
313 08:06:04.439802
314 08:06:04.443268 F3: 1001 0000
315 08:06:04.443378
316 08:06:04.443468 F7: 102D 0000
317 08:06:04.443546
318 08:06:04.443616 F1: 0000 0000
319 08:06:04.443672
320 08:06:04.446937 V0: 0000 0000 [0001]
321 08:06:04.447036
322 08:06:04.447134 00: 0007 8000
323 08:06:04.447227
324 08:06:04.450800 01: 0000 0000
325 08:06:04.450910
326 08:06:04.451004 BP: 0C00 0209 [0000]
327 08:06:04.451092
328 08:06:04.451186 G0: 1182 0000
329 08:06:04.454376
330 08:06:04.454479 EC: 0000 0021 [4000]
331 08:06:04.454579
332 08:06:04.454643 S7: 0000 0000 [0000]
333 08:06:04.458275
334 08:06:04.458390 CC: 0000 0000 [0001]
335 08:06:04.458494
336 08:06:04.461910 T0: 0000 0040 [010F]
337 08:06:04.462016
338 08:06:04.462124 Jump to BL
339 08:06:04.462198
340 08:06:04.486438
341 08:06:04.486525
342 08:06:04.486590
343 08:06:04.493152 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 08:06:04.496697 ARM64: Exception handlers installed.
345 08:06:04.500526 ARM64: Testing exception
346 08:06:04.504083 ARM64: Done test exception
347 08:06:04.511630 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 08:06:04.522199 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 08:06:04.528957 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 08:06:04.538824 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 08:06:04.545435 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 08:06:04.552344 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 08:06:04.562863 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 08:06:04.569062 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 08:06:04.588812 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 08:06:04.592887 WDT: Last reset was cold boot
357 08:06:04.595554 SPI1(PAD0) initialized at 2873684 Hz
358 08:06:04.598911 SPI5(PAD0) initialized at 992727 Hz
359 08:06:04.602348 VBOOT: Loading verstage.
360 08:06:04.608900 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 08:06:04.612210 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 08:06:04.615838 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 08:06:04.619640 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 08:06:04.626590 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 08:06:04.632825 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 08:06:04.644023 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 08:06:04.644107
368 08:06:04.644174
369 08:06:04.654139 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 08:06:04.657382 ARM64: Exception handlers installed.
371 08:06:04.660719 ARM64: Testing exception
372 08:06:04.660803 ARM64: Done test exception
373 08:06:04.668004 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 08:06:04.671345 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 08:06:04.684935 Probing TPM: . done!
376 08:06:04.685019 TPM ready after 0 ms
377 08:06:04.691512 Connected to device vid:did:rid of 1ae0:0028:00
378 08:06:04.698329 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 08:06:04.739829 Initialized TPM device CR50 revision 0
380 08:06:04.751270 tlcl_send_startup: Startup return code is 0
381 08:06:04.751359 TPM: setup succeeded
382 08:06:04.763099 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 08:06:04.771747 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 08:06:04.784174 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 08:06:04.792320 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 08:06:04.795506 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 08:06:04.800443 in-header: 03 07 00 00 08 00 00 00
388 08:06:04.804400 in-data: aa e4 47 04 13 02 00 00
389 08:06:04.807050 Chrome EC: UHEPI supported
390 08:06:04.814072 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 08:06:04.817542 in-header: 03 9d 00 00 08 00 00 00
392 08:06:04.821331 in-data: 10 20 20 08 00 00 00 00
393 08:06:04.824818 Phase 1
394 08:06:04.829051 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 08:06:04.832202 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 08:06:04.839728 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 08:06:04.843366 Recovery requested (1009000e)
398 08:06:04.849199 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 08:06:04.854343 tlcl_extend: response is 0
400 08:06:04.862461 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 08:06:04.868352 tlcl_extend: response is 0
402 08:06:04.874814 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 08:06:04.895818 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 08:06:04.902704 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 08:06:04.902790
406 08:06:04.902856
407 08:06:04.910074 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 08:06:04.914017 ARM64: Exception handlers installed.
409 08:06:04.917507 ARM64: Testing exception
410 08:06:04.920866 ARM64: Done test exception
411 08:06:04.941063 pmic_efuse_setting: Set efuses in 11 msecs
412 08:06:04.944626 pmwrap_interface_init: Select PMIF_VLD_RDY
413 08:06:04.948357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 08:06:04.956490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 08:06:04.959871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 08:06:04.963518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 08:06:04.971098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 08:06:04.974523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 08:06:04.978574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 08:06:04.982042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 08:06:04.988612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 08:06:04.991861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 08:06:04.998415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 08:06:05.001693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 08:06:05.005140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 08:06:05.011967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 08:06:05.018911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 08:06:05.025543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 08:06:05.028642 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 08:06:05.035372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 08:06:05.042675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 08:06:05.046237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 08:06:05.053971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 08:06:05.057639 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 08:06:05.064450 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 08:06:05.067742 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 08:06:05.075279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 08:06:05.081584 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 08:06:05.085044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 08:06:05.088180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 08:06:05.095135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 08:06:05.098943 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 08:06:05.106506 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 08:06:05.110210 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 08:06:05.113873 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 08:06:05.121374 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 08:06:05.125084 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 08:06:05.128548 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 08:06:05.135659 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 08:06:05.138665 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 08:06:05.145504 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 08:06:05.148980 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 08:06:05.152160 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 08:06:05.155819 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 08:06:05.162340 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 08:06:05.165777 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 08:06:05.169424 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 08:06:05.175516 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 08:06:05.178846 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 08:06:05.182523 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 08:06:05.189039 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 08:06:05.192025 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 08:06:05.195601 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 08:06:05.202300 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 08:06:05.212405 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 08:06:05.215591 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 08:06:05.225979 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 08:06:05.232360 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 08:06:05.238986 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 08:06:05.242330 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 08:06:05.245953 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 08:06:05.253375 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
473 08:06:05.259928 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 08:06:05.263289 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
475 08:06:05.266424 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 08:06:05.278009 [RTC]rtc_get_frequency_meter,154: input=15, output=793
477 08:06:05.281430 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 08:06:05.287830 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 08:06:05.290920 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 08:06:05.294487 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 08:06:05.297770 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 08:06:05.300968 ADC[4]: Raw value=899260 ID=7
483 08:06:05.304456 ADC[3]: Raw value=212700 ID=1
484 08:06:05.307625 RAM Code: 0x71
485 08:06:05.310968 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 08:06:05.314604 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 08:06:05.325200 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 08:06:05.331648 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 08:06:05.335180 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 08:06:05.338431 in-header: 03 07 00 00 08 00 00 00
491 08:06:05.341538 in-data: aa e4 47 04 13 02 00 00
492 08:06:05.341617 Chrome EC: UHEPI supported
493 08:06:05.348729 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 08:06:05.352807 in-header: 03 d5 00 00 08 00 00 00
495 08:06:05.356405 in-data: 98 20 60 08 00 00 00 00
496 08:06:05.359785 MRC: failed to locate region type 0.
497 08:06:05.367498 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 08:06:05.370241 DRAM-K: Running full calibration
499 08:06:05.377567 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 08:06:05.377649 header.status = 0x0
501 08:06:05.380522 header.version = 0x6 (expected: 0x6)
502 08:06:05.383865 header.size = 0xd00 (expected: 0xd00)
503 08:06:05.387563 header.flags = 0x0
504 08:06:05.390828 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 08:06:05.410189 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
506 08:06:05.416694 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 08:06:05.420624 dram_init: ddr_geometry: 2
508 08:06:05.420710 [EMI] MDL number = 2
509 08:06:05.424223 [EMI] Get MDL freq = 0
510 08:06:05.427569 dram_init: ddr_type: 0
511 08:06:05.427665 is_discrete_lpddr4: 1
512 08:06:05.431093 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 08:06:05.431171
514 08:06:05.431235
515 08:06:05.435332 [Bian_co] ETT version 0.0.0.1
516 08:06:05.439018 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 08:06:05.439123
518 08:06:05.442834 dramc_set_vcore_voltage set vcore to 650000
519 08:06:05.446790 Read voltage for 800, 4
520 08:06:05.446877 Vio18 = 0
521 08:06:05.446951 Vcore = 650000
522 08:06:05.450872 Vdram = 0
523 08:06:05.450946 Vddq = 0
524 08:06:05.451011 Vmddr = 0
525 08:06:05.454343 dram_init: config_dvfs: 1
526 08:06:05.457855 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 08:06:05.461677 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 08:06:05.465608 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
529 08:06:05.469457 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
530 08:06:05.472953 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 08:06:05.476267 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 08:06:05.479973 MEM_TYPE=3, freq_sel=18
533 08:06:05.483803 sv_algorithm_assistance_LP4_1600
534 08:06:05.487818 ============ PULL DRAM RESETB DOWN ============
535 08:06:05.491010 ========== PULL DRAM RESETB DOWN end =========
536 08:06:05.494757 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 08:06:05.498836 ===================================
538 08:06:05.502502 LPDDR4 DRAM CONFIGURATION
539 08:06:05.506524 ===================================
540 08:06:05.506601 EX_ROW_EN[0] = 0x0
541 08:06:05.509605 EX_ROW_EN[1] = 0x0
542 08:06:05.509690 LP4Y_EN = 0x0
543 08:06:05.512805 WORK_FSP = 0x0
544 08:06:05.512880 WL = 0x2
545 08:06:05.516252 RL = 0x2
546 08:06:05.516324 BL = 0x2
547 08:06:05.519563 RPST = 0x0
548 08:06:05.519637 RD_PRE = 0x0
549 08:06:05.522789 WR_PRE = 0x1
550 08:06:05.525866 WR_PST = 0x0
551 08:06:05.525939 DBI_WR = 0x0
552 08:06:05.529469 DBI_RD = 0x0
553 08:06:05.529548 OTF = 0x1
554 08:06:05.533305 ===================================
555 08:06:05.536392 ===================================
556 08:06:05.536475 ANA top config
557 08:06:05.539574 ===================================
558 08:06:05.543158 DLL_ASYNC_EN = 0
559 08:06:05.546060 ALL_SLAVE_EN = 1
560 08:06:05.549319 NEW_RANK_MODE = 1
561 08:06:05.552682 DLL_IDLE_MODE = 1
562 08:06:05.552759 LP45_APHY_COMB_EN = 1
563 08:06:05.556270 TX_ODT_DIS = 1
564 08:06:05.559549 NEW_8X_MODE = 1
565 08:06:05.562970 ===================================
566 08:06:05.566090 ===================================
567 08:06:05.569622 data_rate = 1600
568 08:06:05.572820 CKR = 1
569 08:06:05.572900 DQ_P2S_RATIO = 8
570 08:06:05.576290 ===================================
571 08:06:05.579549 CA_P2S_RATIO = 8
572 08:06:05.582852 DQ_CA_OPEN = 0
573 08:06:05.586187 DQ_SEMI_OPEN = 0
574 08:06:05.589595 CA_SEMI_OPEN = 0
575 08:06:05.589684 CA_FULL_RATE = 0
576 08:06:05.592974 DQ_CKDIV4_EN = 1
577 08:06:05.596270 CA_CKDIV4_EN = 1
578 08:06:05.599766 CA_PREDIV_EN = 0
579 08:06:05.603323 PH8_DLY = 0
580 08:06:05.606408 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 08:06:05.606483 DQ_AAMCK_DIV = 4
582 08:06:05.609681 CA_AAMCK_DIV = 4
583 08:06:05.612890 CA_ADMCK_DIV = 4
584 08:06:05.616248 DQ_TRACK_CA_EN = 0
585 08:06:05.619857 CA_PICK = 800
586 08:06:05.622960 CA_MCKIO = 800
587 08:06:05.626090 MCKIO_SEMI = 0
588 08:06:05.626163 PLL_FREQ = 3068
589 08:06:05.629537 DQ_UI_PI_RATIO = 32
590 08:06:05.633303 CA_UI_PI_RATIO = 0
591 08:06:05.636397 ===================================
592 08:06:05.639413 ===================================
593 08:06:05.643286 memory_type:LPDDR4
594 08:06:05.643400 GP_NUM : 10
595 08:06:05.646300 SRAM_EN : 1
596 08:06:05.649888 MD32_EN : 0
597 08:06:05.652720 ===================================
598 08:06:05.652797 [ANA_INIT] >>>>>>>>>>>>>>
599 08:06:05.656626 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 08:06:05.659345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 08:06:05.662806 ===================================
602 08:06:05.666477 data_rate = 1600,PCW = 0X7600
603 08:06:05.669732 ===================================
604 08:06:05.673134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 08:06:05.679643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 08:06:05.682949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 08:06:05.689513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 08:06:05.693164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 08:06:05.697196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 08:06:05.697277 [ANA_INIT] flow start
611 08:06:05.700172 [ANA_INIT] PLL >>>>>>>>
612 08:06:05.703601 [ANA_INIT] PLL <<<<<<<<
613 08:06:05.703675 [ANA_INIT] MIDPI >>>>>>>>
614 08:06:05.707445 [ANA_INIT] MIDPI <<<<<<<<
615 08:06:05.707531 [ANA_INIT] DLL >>>>>>>>
616 08:06:05.710936 [ANA_INIT] flow end
617 08:06:05.714622 ============ LP4 DIFF to SE enter ============
618 08:06:05.718551 ============ LP4 DIFF to SE exit ============
619 08:06:05.721985 [ANA_INIT] <<<<<<<<<<<<<
620 08:06:05.725690 [Flow] Enable top DCM control >>>>>
621 08:06:05.729903 [Flow] Enable top DCM control <<<<<
622 08:06:05.730009 Enable DLL master slave shuffle
623 08:06:05.737382 ==============================================================
624 08:06:05.737473 Gating Mode config
625 08:06:05.744300 ==============================================================
626 08:06:05.747267 Config description:
627 08:06:05.754711 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 08:06:05.761701 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 08:06:05.765254 SELPH_MODE 0: By rank 1: By Phase
630 08:06:05.772612 ==============================================================
631 08:06:05.776529 GAT_TRACK_EN = 1
632 08:06:05.780466 RX_GATING_MODE = 2
633 08:06:05.780551 RX_GATING_TRACK_MODE = 2
634 08:06:05.784056 SELPH_MODE = 1
635 08:06:05.787829 PICG_EARLY_EN = 1
636 08:06:05.791364 VALID_LAT_VALUE = 1
637 08:06:05.794873 ==============================================================
638 08:06:05.798616 Enter into Gating configuration >>>>
639 08:06:05.801746 Exit from Gating configuration <<<<
640 08:06:05.805648 Enter into DVFS_PRE_config >>>>>
641 08:06:05.816821 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 08:06:05.820274 Exit from DVFS_PRE_config <<<<<
643 08:06:05.824341 Enter into PICG configuration >>>>
644 08:06:05.827768 Exit from PICG configuration <<<<
645 08:06:05.827843 [RX_INPUT] configuration >>>>>
646 08:06:05.831418 [RX_INPUT] configuration <<<<<
647 08:06:05.839313 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 08:06:05.842871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 08:06:05.850590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 08:06:05.854113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 08:06:05.861434 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 08:06:05.868589 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 08:06:05.872173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 08:06:05.875937 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 08:06:05.879595 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 08:06:05.883103 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 08:06:05.887106 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 08:06:05.890987 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 08:06:05.894823 ===================================
660 08:06:05.898038 LPDDR4 DRAM CONFIGURATION
661 08:06:05.901743 ===================================
662 08:06:05.901826 EX_ROW_EN[0] = 0x0
663 08:06:05.905781 EX_ROW_EN[1] = 0x0
664 08:06:05.905865 LP4Y_EN = 0x0
665 08:06:05.909130 WORK_FSP = 0x0
666 08:06:05.909214 WL = 0x2
667 08:06:05.913071 RL = 0x2
668 08:06:05.913157 BL = 0x2
669 08:06:05.916427 RPST = 0x0
670 08:06:05.916512 RD_PRE = 0x0
671 08:06:05.920500 WR_PRE = 0x1
672 08:06:05.920588 WR_PST = 0x0
673 08:06:05.924198 DBI_WR = 0x0
674 08:06:05.924284 DBI_RD = 0x0
675 08:06:05.924350 OTF = 0x1
676 08:06:05.927896 ===================================
677 08:06:05.931539 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 08:06:05.938706 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 08:06:05.942362 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 08:06:05.945786 ===================================
681 08:06:05.945870 LPDDR4 DRAM CONFIGURATION
682 08:06:05.949641 ===================================
683 08:06:05.953132 EX_ROW_EN[0] = 0x10
684 08:06:05.953232 EX_ROW_EN[1] = 0x0
685 08:06:05.956708 LP4Y_EN = 0x0
686 08:06:05.956795 WORK_FSP = 0x0
687 08:06:05.960485 WL = 0x2
688 08:06:05.960588 RL = 0x2
689 08:06:05.964273 BL = 0x2
690 08:06:05.964356 RPST = 0x0
691 08:06:05.968335 RD_PRE = 0x0
692 08:06:05.968420 WR_PRE = 0x1
693 08:06:05.971520 WR_PST = 0x0
694 08:06:05.971604 DBI_WR = 0x0
695 08:06:05.975557 DBI_RD = 0x0
696 08:06:05.975641 OTF = 0x1
697 08:06:05.979521 ===================================
698 08:06:05.986708 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 08:06:05.986792 nWR fixed to 40
700 08:06:05.990126 [ModeRegInit_LP4] CH0 RK0
701 08:06:05.993686 [ModeRegInit_LP4] CH0 RK1
702 08:06:05.993772 [ModeRegInit_LP4] CH1 RK0
703 08:06:05.997508 [ModeRegInit_LP4] CH1 RK1
704 08:06:05.997592 match AC timing 13
705 08:06:06.004854 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 08:06:06.008533 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 08:06:06.012076 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 08:06:06.019234 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 08:06:06.023424 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 08:06:06.023537 [EMI DOE] emi_dcm 0
711 08:06:06.026909 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 08:06:06.026993 ==
713 08:06:06.030666 Dram Type= 6, Freq= 0, CH_0, rank 0
714 08:06:06.034831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 08:06:06.034922 ==
716 08:06:06.041783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 08:06:06.045257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 08:06:06.055758 [CA 0] Center 38 (7~69) winsize 63
719 08:06:06.059496 [CA 1] Center 37 (7~68) winsize 62
720 08:06:06.062634 [CA 2] Center 35 (5~66) winsize 62
721 08:06:06.066188 [CA 3] Center 35 (5~66) winsize 62
722 08:06:06.069277 [CA 4] Center 34 (4~65) winsize 62
723 08:06:06.072499 [CA 5] Center 34 (3~65) winsize 63
724 08:06:06.072583
725 08:06:06.075851 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 08:06:06.075936
727 08:06:06.079247 [CATrainingPosCal] consider 1 rank data
728 08:06:06.082755 u2DelayCellTimex100 = 270/100 ps
729 08:06:06.085912 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
730 08:06:06.089469 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 08:06:06.095640 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 08:06:06.099139 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
733 08:06:06.102859 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 08:06:06.105834 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
735 08:06:06.105917
736 08:06:06.108869 CA PerBit enable=1, Macro0, CA PI delay=34
737 08:06:06.108953
738 08:06:06.112733 [CBTSetCACLKResult] CA Dly = 34
739 08:06:06.112849 CS Dly: 6 (0~37)
740 08:06:06.115822 ==
741 08:06:06.115905 Dram Type= 6, Freq= 0, CH_0, rank 1
742 08:06:06.122117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 08:06:06.122196 ==
744 08:06:06.125710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 08:06:06.132503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 08:06:06.142288 [CA 0] Center 38 (7~69) winsize 63
747 08:06:06.145740 [CA 1] Center 38 (7~69) winsize 63
748 08:06:06.149012 [CA 2] Center 35 (5~66) winsize 62
749 08:06:06.152224 [CA 3] Center 35 (5~66) winsize 62
750 08:06:06.155688 [CA 4] Center 34 (4~65) winsize 62
751 08:06:06.158935 [CA 5] Center 34 (4~65) winsize 62
752 08:06:06.159042
753 08:06:06.161964 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 08:06:06.162050
755 08:06:06.165702 [CATrainingPosCal] consider 2 rank data
756 08:06:06.168587 u2DelayCellTimex100 = 270/100 ps
757 08:06:06.171976 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
758 08:06:06.176038 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 08:06:06.182325 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 08:06:06.185735 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
761 08:06:06.189238 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
762 08:06:06.191961 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
763 08:06:06.192042
764 08:06:06.195584 CA PerBit enable=1, Macro0, CA PI delay=34
765 08:06:06.195658
766 08:06:06.199011 [CBTSetCACLKResult] CA Dly = 34
767 08:06:06.199084 CS Dly: 6 (0~37)
768 08:06:06.199153
769 08:06:06.202396 ----->DramcWriteLeveling(PI) begin...
770 08:06:06.205684 ==
771 08:06:06.205764 Dram Type= 6, Freq= 0, CH_0, rank 0
772 08:06:06.212824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 08:06:06.212900 ==
774 08:06:06.215897 Write leveling (Byte 0): 33 => 33
775 08:06:06.218640 Write leveling (Byte 1): 29 => 29
776 08:06:06.218712 DramcWriteLeveling(PI) end<-----
777 08:06:06.222582
778 08:06:06.222666 ==
779 08:06:06.225571 Dram Type= 6, Freq= 0, CH_0, rank 0
780 08:06:06.228823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 08:06:06.228922 ==
782 08:06:06.232114 [Gating] SW mode calibration
783 08:06:06.239089 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 08:06:06.242680 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 08:06:06.249326 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 08:06:06.252066 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 08:06:06.255443 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 08:06:06.262523 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
789 08:06:06.265500 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 08:06:06.268906 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 08:06:06.275823 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 08:06:06.279013 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 08:06:06.282669 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 08:06:06.286370 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 08:06:06.293686 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 08:06:06.297855 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 08:06:06.300646 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 08:06:06.303953 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 08:06:06.311073 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 08:06:06.314487 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 08:06:06.318213 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 08:06:06.321729 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 08:06:06.328157 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 08:06:06.331548 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 08:06:06.334613 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 08:06:06.341585 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 08:06:06.344765 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 08:06:06.348072 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 08:06:06.354876 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 08:06:06.358120 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 08:06:06.361105 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 08:06:06.368407 0 9 12 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
813 08:06:06.371243 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 08:06:06.375143 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 08:06:06.378459 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 08:06:06.384489 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 08:06:06.387868 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 08:06:06.391238 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 08:06:06.398328 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
820 08:06:06.401783 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
821 08:06:06.405058 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 08:06:06.411415 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 08:06:06.414750 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 08:06:06.418195 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 08:06:06.424942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 08:06:06.428586 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 08:06:06.431796 0 11 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
828 08:06:06.437982 0 11 12 | B1->B0 | 3232 4242 | 0 0 | (0 0) (0 0)
829 08:06:06.441423 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 08:06:06.444743 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 08:06:06.451607 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 08:06:06.455186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 08:06:06.458455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 08:06:06.464842 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 08:06:06.468128 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 08:06:06.471285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 08:06:06.474890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 08:06:06.481371 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 08:06:06.484928 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 08:06:06.488037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 08:06:06.494861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 08:06:06.498115 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 08:06:06.501568 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 08:06:06.508243 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 08:06:06.511633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 08:06:06.515045 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 08:06:06.521493 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 08:06:06.525052 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 08:06:06.527923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 08:06:06.534524 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 08:06:06.537650 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 08:06:06.541018 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 08:06:06.544616 Total UI for P1: 0, mck2ui 16
854 08:06:06.547716 best dqsien dly found for B0: ( 0, 14, 6)
855 08:06:06.554673 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 08:06:06.554787 Total UI for P1: 0, mck2ui 16
857 08:06:06.561365 best dqsien dly found for B1: ( 0, 14, 10)
858 08:06:06.564240 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 08:06:06.567816 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 08:06:06.567892
861 08:06:06.571003 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 08:06:06.574284 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 08:06:06.578156 [Gating] SW calibration Done
864 08:06:06.578245 ==
865 08:06:06.580905 Dram Type= 6, Freq= 0, CH_0, rank 0
866 08:06:06.585021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 08:06:06.585097 ==
868 08:06:06.587604 RX Vref Scan: 0
869 08:06:06.587673
870 08:06:06.587742 RX Vref 0 -> 0, step: 1
871 08:06:06.587835
872 08:06:06.590954 RX Delay -130 -> 252, step: 16
873 08:06:06.594457 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
874 08:06:06.601485 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 08:06:06.604645 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
876 08:06:06.608335 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 08:06:06.611151 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
878 08:06:06.614318 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 08:06:06.620953 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
880 08:06:06.624401 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 08:06:06.627811 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 08:06:06.631223 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 08:06:06.634515 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 08:06:06.641206 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
885 08:06:06.644542 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 08:06:06.647628 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 08:06:06.651101 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
888 08:06:06.654408 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 08:06:06.657703 ==
890 08:06:06.657787 Dram Type= 6, Freq= 0, CH_0, rank 0
891 08:06:06.664263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 08:06:06.664349 ==
893 08:06:06.664419 DQS Delay:
894 08:06:06.667801 DQS0 = 0, DQS1 = 0
895 08:06:06.667884 DQM Delay:
896 08:06:06.671567 DQM0 = 80, DQM1 = 69
897 08:06:06.671650 DQ Delay:
898 08:06:06.674304 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
899 08:06:06.677769 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
900 08:06:06.680949 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
901 08:06:06.684815 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
902 08:06:06.684899
903 08:06:06.684966
904 08:06:06.685027 ==
905 08:06:06.688043 Dram Type= 6, Freq= 0, CH_0, rank 0
906 08:06:06.691702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 08:06:06.691787 ==
908 08:06:06.691854
909 08:06:06.691916
910 08:06:06.695520 TX Vref Scan disable
911 08:06:06.695605 == TX Byte 0 ==
912 08:06:06.701470 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 08:06:06.704916 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 08:06:06.704999 == TX Byte 1 ==
915 08:06:06.711288 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 08:06:06.714664 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 08:06:06.714748 ==
918 08:06:06.718259 Dram Type= 6, Freq= 0, CH_0, rank 0
919 08:06:06.721697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 08:06:06.721799 ==
921 08:06:06.735529 TX Vref=22, minBit 14, minWin=26, winSum=435
922 08:06:06.739294 TX Vref=24, minBit 0, minWin=27, winSum=437
923 08:06:06.742451 TX Vref=26, minBit 3, minWin=27, winSum=440
924 08:06:06.745790 TX Vref=28, minBit 10, minWin=27, winSum=443
925 08:06:06.749209 TX Vref=30, minBit 9, minWin=27, winSum=443
926 08:06:06.755724 TX Vref=32, minBit 9, minWin=26, winSum=434
927 08:06:06.759178 [TxChooseVref] Worse bit 10, Min win 27, Win sum 443, Final Vref 28
928 08:06:06.759271
929 08:06:06.762237 Final TX Range 1 Vref 28
930 08:06:06.762317
931 08:06:06.762382 ==
932 08:06:06.765604 Dram Type= 6, Freq= 0, CH_0, rank 0
933 08:06:06.769237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 08:06:06.772464 ==
935 08:06:06.772537
936 08:06:06.772611
937 08:06:06.772709 TX Vref Scan disable
938 08:06:06.775802 == TX Byte 0 ==
939 08:06:06.779562 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 08:06:06.782465 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 08:06:06.785898 == TX Byte 1 ==
942 08:06:06.789265 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 08:06:06.792772 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 08:06:06.796172
945 08:06:06.796271 [DATLAT]
946 08:06:06.796370 Freq=800, CH0 RK0
947 08:06:06.796464
948 08:06:06.799278 DATLAT Default: 0xa
949 08:06:06.799362 0, 0xFFFF, sum = 0
950 08:06:06.802857 1, 0xFFFF, sum = 0
951 08:06:06.802944 2, 0xFFFF, sum = 0
952 08:06:06.805969 3, 0xFFFF, sum = 0
953 08:06:06.806050 4, 0xFFFF, sum = 0
954 08:06:06.809409 5, 0xFFFF, sum = 0
955 08:06:06.809485 6, 0xFFFF, sum = 0
956 08:06:06.812896 7, 0xFFFF, sum = 0
957 08:06:06.816016 8, 0xFFFF, sum = 0
958 08:06:06.816127 9, 0x0, sum = 1
959 08:06:06.816226 10, 0x0, sum = 2
960 08:06:06.819307 11, 0x0, sum = 3
961 08:06:06.819408 12, 0x0, sum = 4
962 08:06:06.822702 best_step = 10
963 08:06:06.822777
964 08:06:06.822839 ==
965 08:06:06.826014 Dram Type= 6, Freq= 0, CH_0, rank 0
966 08:06:06.829505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 08:06:06.829581 ==
968 08:06:06.832462 RX Vref Scan: 1
969 08:06:06.832544
970 08:06:06.832608 Set Vref Range= 32 -> 127
971 08:06:06.832668
972 08:06:06.836238 RX Vref 32 -> 127, step: 1
973 08:06:06.836306
974 08:06:06.839669 RX Delay -111 -> 252, step: 8
975 08:06:06.839742
976 08:06:06.843064 Set Vref, RX VrefLevel [Byte0]: 32
977 08:06:06.845936 [Byte1]: 32
978 08:06:06.846009
979 08:06:06.849233 Set Vref, RX VrefLevel [Byte0]: 33
980 08:06:06.852742 [Byte1]: 33
981 08:06:06.856754
982 08:06:06.856837 Set Vref, RX VrefLevel [Byte0]: 34
983 08:06:06.859682 [Byte1]: 34
984 08:06:06.863903
985 08:06:06.863986 Set Vref, RX VrefLevel [Byte0]: 35
986 08:06:06.867463 [Byte1]: 35
987 08:06:06.871710
988 08:06:06.871794 Set Vref, RX VrefLevel [Byte0]: 36
989 08:06:06.875093 [Byte1]: 36
990 08:06:06.879563
991 08:06:06.879649 Set Vref, RX VrefLevel [Byte0]: 37
992 08:06:06.882991 [Byte1]: 37
993 08:06:06.887166
994 08:06:06.887263 Set Vref, RX VrefLevel [Byte0]: 38
995 08:06:06.890360 [Byte1]: 38
996 08:06:06.894540
997 08:06:06.894623 Set Vref, RX VrefLevel [Byte0]: 39
998 08:06:06.898273 [Byte1]: 39
999 08:06:06.902406
1000 08:06:06.902489 Set Vref, RX VrefLevel [Byte0]: 40
1001 08:06:06.905901 [Byte1]: 40
1002 08:06:06.910049
1003 08:06:06.910151 Set Vref, RX VrefLevel [Byte0]: 41
1004 08:06:06.913586 [Byte1]: 41
1005 08:06:06.917610
1006 08:06:06.917707 Set Vref, RX VrefLevel [Byte0]: 42
1007 08:06:06.921207 [Byte1]: 42
1008 08:06:06.925217
1009 08:06:06.925301 Set Vref, RX VrefLevel [Byte0]: 43
1010 08:06:06.928483 [Byte1]: 43
1011 08:06:06.933049
1012 08:06:06.933125 Set Vref, RX VrefLevel [Byte0]: 44
1013 08:06:06.936366 [Byte1]: 44
1014 08:06:06.940674
1015 08:06:06.940755 Set Vref, RX VrefLevel [Byte0]: 45
1016 08:06:06.944440 [Byte1]: 45
1017 08:06:06.948387
1018 08:06:06.948488 Set Vref, RX VrefLevel [Byte0]: 46
1019 08:06:06.951604 [Byte1]: 46
1020 08:06:06.956042
1021 08:06:06.956127 Set Vref, RX VrefLevel [Byte0]: 47
1022 08:06:06.959459 [Byte1]: 47
1023 08:06:06.963911
1024 08:06:06.963995 Set Vref, RX VrefLevel [Byte0]: 48
1025 08:06:06.967380 [Byte1]: 48
1026 08:06:06.971334
1027 08:06:06.971439 Set Vref, RX VrefLevel [Byte0]: 49
1028 08:06:06.975143 [Byte1]: 49
1029 08:06:06.979381
1030 08:06:06.979503 Set Vref, RX VrefLevel [Byte0]: 50
1031 08:06:06.982293 [Byte1]: 50
1032 08:06:06.986533
1033 08:06:06.986615 Set Vref, RX VrefLevel [Byte0]: 51
1034 08:06:06.989736 [Byte1]: 51
1035 08:06:06.994124
1036 08:06:06.994200 Set Vref, RX VrefLevel [Byte0]: 52
1037 08:06:06.997482 [Byte1]: 52
1038 08:06:07.001602
1039 08:06:07.001684 Set Vref, RX VrefLevel [Byte0]: 53
1040 08:06:07.005047 [Byte1]: 53
1041 08:06:07.009217
1042 08:06:07.009293 Set Vref, RX VrefLevel [Byte0]: 54
1043 08:06:07.012568 [Byte1]: 54
1044 08:06:07.016949
1045 08:06:07.017028 Set Vref, RX VrefLevel [Byte0]: 55
1046 08:06:07.020239 [Byte1]: 55
1047 08:06:07.025054
1048 08:06:07.025129 Set Vref, RX VrefLevel [Byte0]: 56
1049 08:06:07.027715 [Byte1]: 56
1050 08:06:07.032058
1051 08:06:07.032136 Set Vref, RX VrefLevel [Byte0]: 57
1052 08:06:07.035523 [Byte1]: 57
1053 08:06:07.040418
1054 08:06:07.040493 Set Vref, RX VrefLevel [Byte0]: 58
1055 08:06:07.043007 [Byte1]: 58
1056 08:06:07.047661
1057 08:06:07.047735 Set Vref, RX VrefLevel [Byte0]: 59
1058 08:06:07.051193 [Byte1]: 59
1059 08:06:07.055234
1060 08:06:07.055365 Set Vref, RX VrefLevel [Byte0]: 60
1061 08:06:07.058465 [Byte1]: 60
1062 08:06:07.063245
1063 08:06:07.063324 Set Vref, RX VrefLevel [Byte0]: 61
1064 08:06:07.066363 [Byte1]: 61
1065 08:06:07.070660
1066 08:06:07.070740 Set Vref, RX VrefLevel [Byte0]: 62
1067 08:06:07.073998 [Byte1]: 62
1068 08:06:07.078605
1069 08:06:07.078680 Set Vref, RX VrefLevel [Byte0]: 63
1070 08:06:07.081334 [Byte1]: 63
1071 08:06:07.085609
1072 08:06:07.085688 Set Vref, RX VrefLevel [Byte0]: 64
1073 08:06:07.089086 [Byte1]: 64
1074 08:06:07.093504
1075 08:06:07.093589 Set Vref, RX VrefLevel [Byte0]: 65
1076 08:06:07.096744 [Byte1]: 65
1077 08:06:07.100852
1078 08:06:07.100931 Set Vref, RX VrefLevel [Byte0]: 66
1079 08:06:07.104491 [Byte1]: 66
1080 08:06:07.108892
1081 08:06:07.108966 Set Vref, RX VrefLevel [Byte0]: 67
1082 08:06:07.112281 [Byte1]: 67
1083 08:06:07.116417
1084 08:06:07.116493 Set Vref, RX VrefLevel [Byte0]: 68
1085 08:06:07.119671 [Byte1]: 68
1086 08:06:07.124056
1087 08:06:07.124139 Set Vref, RX VrefLevel [Byte0]: 69
1088 08:06:07.127163 [Byte1]: 69
1089 08:06:07.131919
1090 08:06:07.131999 Set Vref, RX VrefLevel [Byte0]: 70
1091 08:06:07.134859 [Byte1]: 70
1092 08:06:07.139519
1093 08:06:07.139596 Set Vref, RX VrefLevel [Byte0]: 71
1094 08:06:07.142770 [Byte1]: 71
1095 08:06:07.146755
1096 08:06:07.146829 Set Vref, RX VrefLevel [Byte0]: 72
1097 08:06:07.150160 [Byte1]: 72
1098 08:06:07.154491
1099 08:06:07.154570 Set Vref, RX VrefLevel [Byte0]: 73
1100 08:06:07.157908 [Byte1]: 73
1101 08:06:07.162541
1102 08:06:07.162625 Set Vref, RX VrefLevel [Byte0]: 74
1103 08:06:07.166000 [Byte1]: 74
1104 08:06:07.169837
1105 08:06:07.169921 Set Vref, RX VrefLevel [Byte0]: 75
1106 08:06:07.173548 [Byte1]: 75
1107 08:06:07.177502
1108 08:06:07.177586 Set Vref, RX VrefLevel [Byte0]: 76
1109 08:06:07.180862 [Byte1]: 76
1110 08:06:07.185258
1111 08:06:07.185341 Set Vref, RX VrefLevel [Byte0]: 77
1112 08:06:07.188521 [Byte1]: 77
1113 08:06:07.192725
1114 08:06:07.192808 Set Vref, RX VrefLevel [Byte0]: 78
1115 08:06:07.196216 [Byte1]: 78
1116 08:06:07.200605
1117 08:06:07.200689 Final RX Vref Byte 0 = 62 to rank0
1118 08:06:07.204008 Final RX Vref Byte 1 = 60 to rank0
1119 08:06:07.206983 Final RX Vref Byte 0 = 62 to rank1
1120 08:06:07.210795 Final RX Vref Byte 1 = 60 to rank1==
1121 08:06:07.213813 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 08:06:07.217173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 08:06:07.220747 ==
1124 08:06:07.220846 DQS Delay:
1125 08:06:07.220950 DQS0 = 0, DQS1 = 0
1126 08:06:07.223930 DQM Delay:
1127 08:06:07.224006 DQM0 = 81, DQM1 = 68
1128 08:06:07.227141 DQ Delay:
1129 08:06:07.230286 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1130 08:06:07.230362 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1131 08:06:07.233987 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1132 08:06:07.236931 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =76
1133 08:06:07.240728
1134 08:06:07.240813
1135 08:06:07.247542 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1136 08:06:07.250621 CH0 RK0: MR19=606, MR18=2424
1137 08:06:07.257149 CH0_RK0: MR19=0x606, MR18=0x2424, DQSOSC=400, MR23=63, INC=92, DEC=61
1138 08:06:07.257254
1139 08:06:07.260850 ----->DramcWriteLeveling(PI) begin...
1140 08:06:07.261028 ==
1141 08:06:07.263813 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 08:06:07.267479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 08:06:07.267564 ==
1144 08:06:07.270698 Write leveling (Byte 0): 32 => 32
1145 08:06:07.273804 Write leveling (Byte 1): 30 => 30
1146 08:06:07.277046 DramcWriteLeveling(PI) end<-----
1147 08:06:07.277131
1148 08:06:07.277197 ==
1149 08:06:07.280604 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 08:06:07.283969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 08:06:07.284054 ==
1152 08:06:07.287508 [Gating] SW mode calibration
1153 08:06:07.293845 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 08:06:07.300687 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 08:06:07.304082 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 08:06:07.307158 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 08:06:07.313856 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 08:06:07.316994 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 08:06:07.320166 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 08:06:07.326958 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 08:06:07.330205 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 08:06:07.334030 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 08:06:07.340214 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 08:06:07.343943 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 08:06:07.347234 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 08:06:07.350618 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 08:06:07.357355 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 08:06:07.360452 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 08:06:07.364110 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 08:06:07.407872 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 08:06:07.408471 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 08:06:07.408764 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 08:06:07.409051 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1174 08:06:07.409150 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 08:06:07.409254 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 08:06:07.409348 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 08:06:07.409451 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 08:06:07.409994 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 08:06:07.410089 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 08:06:07.452252 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 08:06:07.452591 0 9 8 | B1->B0 | 2323 2c2c | 1 1 | (1 1) (1 1)
1182 08:06:07.452854 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1183 08:06:07.453645 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 08:06:07.453783 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 08:06:07.454093 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 08:06:07.454218 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 08:06:07.454776 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 08:06:07.455041 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 08:06:07.455133 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
1190 08:06:07.467039 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 08:06:07.467659 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 08:06:07.470525 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 08:06:07.473463 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 08:06:07.473582 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 08:06:07.480079 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 08:06:07.483461 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1197 08:06:07.486911 0 11 8 | B1->B0 | 2c2c 4141 | 0 0 | (0 0) (0 0)
1198 08:06:07.493746 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1199 08:06:07.497237 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 08:06:07.500432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 08:06:07.506878 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 08:06:07.509978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 08:06:07.513398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 08:06:07.520562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 08:06:07.524304 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 08:06:07.528340 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 08:06:07.532204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 08:06:07.535905 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 08:06:07.542389 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 08:06:07.545823 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 08:06:07.549564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 08:06:07.552906 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 08:06:07.559674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 08:06:07.563076 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 08:06:07.566386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 08:06:07.573120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 08:06:07.576286 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 08:06:07.579986 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 08:06:07.586918 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 08:06:07.589825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 08:06:07.593459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 08:06:07.596863 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 08:06:07.599838 Total UI for P1: 0, mck2ui 16
1224 08:06:07.603864 best dqsien dly found for B0: ( 0, 14, 6)
1225 08:06:07.606460 Total UI for P1: 0, mck2ui 16
1226 08:06:07.610085 best dqsien dly found for B1: ( 0, 14, 8)
1227 08:06:07.613280 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1228 08:06:07.616711 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 08:06:07.620390
1230 08:06:07.623143 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 08:06:07.626774 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 08:06:07.629952 [Gating] SW calibration Done
1233 08:06:07.630065 ==
1234 08:06:07.633724 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 08:06:07.637017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 08:06:07.637151 ==
1237 08:06:07.637278 RX Vref Scan: 0
1238 08:06:07.637399
1239 08:06:07.639993 RX Vref 0 -> 0, step: 1
1240 08:06:07.640076
1241 08:06:07.643929 RX Delay -130 -> 252, step: 16
1242 08:06:07.646571 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1243 08:06:07.649702 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1244 08:06:07.656583 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1245 08:06:07.659756 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1246 08:06:07.663324 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1247 08:06:07.666536 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1248 08:06:07.669823 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1249 08:06:07.673123 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1250 08:06:07.680248 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1251 08:06:07.683409 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1252 08:06:07.686865 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1253 08:06:07.689888 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1254 08:06:07.696491 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1255 08:06:07.699965 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1256 08:06:07.703458 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1257 08:06:07.706857 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1258 08:06:07.706971 ==
1259 08:06:07.710352 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 08:06:07.713699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 08:06:07.716771 ==
1262 08:06:07.716846 DQS Delay:
1263 08:06:07.716910 DQS0 = 0, DQS1 = 0
1264 08:06:07.719893 DQM Delay:
1265 08:06:07.719968 DQM0 = 77, DQM1 = 69
1266 08:06:07.723024 DQ Delay:
1267 08:06:07.723128 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1268 08:06:07.726488 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1269 08:06:07.729837 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1270 08:06:07.733338 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1271 08:06:07.733447
1272 08:06:07.736920
1273 08:06:07.736996 ==
1274 08:06:07.739826 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 08:06:07.743057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 08:06:07.743158 ==
1277 08:06:07.743250
1278 08:06:07.743338
1279 08:06:07.746572 TX Vref Scan disable
1280 08:06:07.746679 == TX Byte 0 ==
1281 08:06:07.753169 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1282 08:06:07.756727 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1283 08:06:07.756811 == TX Byte 1 ==
1284 08:06:07.763437 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1285 08:06:07.766381 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1286 08:06:07.766472 ==
1287 08:06:07.769893 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 08:06:07.772948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 08:06:07.773038 ==
1290 08:06:07.786868 TX Vref=22, minBit 2, minWin=26, winSum=434
1291 08:06:07.790073 TX Vref=24, minBit 12, minWin=26, winSum=438
1292 08:06:07.793932 TX Vref=26, minBit 0, minWin=27, winSum=440
1293 08:06:07.796790 TX Vref=28, minBit 1, minWin=27, winSum=443
1294 08:06:07.800010 TX Vref=30, minBit 1, minWin=27, winSum=444
1295 08:06:07.806823 TX Vref=32, minBit 15, minWin=26, winSum=441
1296 08:06:07.810266 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
1297 08:06:07.810388
1298 08:06:07.813558 Final TX Range 1 Vref 30
1299 08:06:07.813642
1300 08:06:07.813709 ==
1301 08:06:07.817260 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 08:06:07.820084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 08:06:07.820200 ==
1304 08:06:07.823061
1305 08:06:07.823193
1306 08:06:07.823286 TX Vref Scan disable
1307 08:06:07.826894 == TX Byte 0 ==
1308 08:06:07.830291 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1309 08:06:07.833264 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1310 08:06:07.837428 == TX Byte 1 ==
1311 08:06:07.840197 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 08:06:07.843604 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 08:06:07.847163
1314 08:06:07.847245 [DATLAT]
1315 08:06:07.847311 Freq=800, CH0 RK1
1316 08:06:07.847372
1317 08:06:07.850074 DATLAT Default: 0xa
1318 08:06:07.850159 0, 0xFFFF, sum = 0
1319 08:06:07.853508 1, 0xFFFF, sum = 0
1320 08:06:07.853592 2, 0xFFFF, sum = 0
1321 08:06:07.856812 3, 0xFFFF, sum = 0
1322 08:06:07.856896 4, 0xFFFF, sum = 0
1323 08:06:07.860052 5, 0xFFFF, sum = 0
1324 08:06:07.863898 6, 0xFFFF, sum = 0
1325 08:06:07.863983 7, 0xFFFF, sum = 0
1326 08:06:07.867252 8, 0xFFFF, sum = 0
1327 08:06:07.867336 9, 0x0, sum = 1
1328 08:06:07.867411 10, 0x0, sum = 2
1329 08:06:07.870322 11, 0x0, sum = 3
1330 08:06:07.870406 12, 0x0, sum = 4
1331 08:06:07.873580 best_step = 10
1332 08:06:07.873663
1333 08:06:07.873728 ==
1334 08:06:07.876660 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 08:06:07.880313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 08:06:07.880401 ==
1337 08:06:07.883469 RX Vref Scan: 0
1338 08:06:07.883551
1339 08:06:07.883617 RX Vref 0 -> 0, step: 1
1340 08:06:07.883685
1341 08:06:07.887195 RX Delay -111 -> 252, step: 8
1342 08:06:07.893547 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1343 08:06:07.896729 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1344 08:06:07.900515 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1345 08:06:07.903816 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1346 08:06:07.906803 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1347 08:06:07.913474 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1348 08:06:07.917144 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1349 08:06:07.920726 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1350 08:06:07.923877 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1351 08:06:07.927027 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1352 08:06:07.933757 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1353 08:06:07.937117 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1354 08:06:07.940855 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1355 08:06:07.943663 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1356 08:06:07.947232 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1357 08:06:07.953736 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1358 08:06:07.953820 ==
1359 08:06:07.956916 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 08:06:07.960380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 08:06:07.960464 ==
1362 08:06:07.960530 DQS Delay:
1363 08:06:07.963629 DQS0 = 0, DQS1 = 0
1364 08:06:07.963712 DQM Delay:
1365 08:06:07.967252 DQM0 = 78, DQM1 = 70
1366 08:06:07.967359 DQ Delay:
1367 08:06:07.970622 DQ0 =76, DQ1 =80, DQ2 =76, DQ3 =72
1368 08:06:07.973725 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1369 08:06:07.977147 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1370 08:06:07.980674 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1371 08:06:07.980756
1372 08:06:07.980821
1373 08:06:07.986783 [DQSOSCAuto] RK1, (LSB)MR18= 0x4722, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1374 08:06:07.990684 CH0 RK1: MR19=606, MR18=4722
1375 08:06:07.997114 CH0_RK1: MR19=0x606, MR18=0x4722, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 08:06:08.000138 [RxdqsGatingPostProcess] freq 800
1377 08:06:08.007032 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 08:06:08.010142 Pre-setting of DQS Precalculation
1379 08:06:08.013657 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 08:06:08.013740 ==
1381 08:06:08.017029 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 08:06:08.020514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 08:06:08.020596 ==
1384 08:06:08.026800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 08:06:08.033572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 08:06:08.041977 [CA 0] Center 36 (6~66) winsize 61
1387 08:06:08.045467 [CA 1] Center 36 (6~67) winsize 62
1388 08:06:08.048445 [CA 2] Center 34 (5~64) winsize 60
1389 08:06:08.051772 [CA 3] Center 34 (4~64) winsize 61
1390 08:06:08.055108 [CA 4] Center 34 (4~65) winsize 62
1391 08:06:08.058690 [CA 5] Center 34 (4~64) winsize 61
1392 08:06:08.058772
1393 08:06:08.061994 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 08:06:08.062076
1395 08:06:08.065115 [CATrainingPosCal] consider 1 rank data
1396 08:06:08.068817 u2DelayCellTimex100 = 270/100 ps
1397 08:06:08.071898 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1398 08:06:08.075117 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 08:06:08.082361 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1400 08:06:08.085313 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 08:06:08.088433 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 08:06:08.091996 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 08:06:08.092077
1404 08:06:08.095227 CA PerBit enable=1, Macro0, CA PI delay=34
1405 08:06:08.095334
1406 08:06:08.098574 [CBTSetCACLKResult] CA Dly = 34
1407 08:06:08.098655 CS Dly: 5 (0~36)
1408 08:06:08.101960 ==
1409 08:06:08.102088 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 08:06:08.108349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 08:06:08.108431 ==
1412 08:06:08.111753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 08:06:08.118442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 08:06:08.128094 [CA 0] Center 37 (7~67) winsize 61
1415 08:06:08.131135 [CA 1] Center 36 (6~67) winsize 62
1416 08:06:08.134704 [CA 2] Center 34 (4~65) winsize 62
1417 08:06:08.138151 [CA 3] Center 33 (3~64) winsize 62
1418 08:06:08.141340 [CA 4] Center 34 (4~65) winsize 62
1419 08:06:08.144681 [CA 5] Center 33 (3~64) winsize 62
1420 08:06:08.144777
1421 08:06:08.148305 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1422 08:06:08.148387
1423 08:06:08.151174 [CATrainingPosCal] consider 2 rank data
1424 08:06:08.154989 u2DelayCellTimex100 = 270/100 ps
1425 08:06:08.157975 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1426 08:06:08.161550 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 08:06:08.167839 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1428 08:06:08.171161 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 08:06:08.174547 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 08:06:08.178086 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 08:06:08.178168
1432 08:06:08.181594 CA PerBit enable=1, Macro0, CA PI delay=34
1433 08:06:08.181676
1434 08:06:08.185080 [CBTSetCACLKResult] CA Dly = 34
1435 08:06:08.185177 CS Dly: 5 (0~37)
1436 08:06:08.185243
1437 08:06:08.188850 ----->DramcWriteLeveling(PI) begin...
1438 08:06:08.188933 ==
1439 08:06:08.193054 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 08:06:08.196321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 08:06:08.196403 ==
1442 08:06:08.200034 Write leveling (Byte 0): 29 => 29
1443 08:06:08.203687 Write leveling (Byte 1): 29 => 29
1444 08:06:08.207096 DramcWriteLeveling(PI) end<-----
1445 08:06:08.207178
1446 08:06:08.207242 ==
1447 08:06:08.211306 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 08:06:08.214550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 08:06:08.214631 ==
1450 08:06:08.218183 [Gating] SW mode calibration
1451 08:06:08.225653 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 08:06:08.228459 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 08:06:08.235426 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 08:06:08.238382 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1455 08:06:08.242323 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 08:06:08.248839 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 08:06:08.251843 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 08:06:08.254932 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 08:06:08.261729 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 08:06:08.264983 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 08:06:08.268236 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 08:06:08.275223 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 08:06:08.278359 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 08:06:08.281324 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 08:06:08.285188 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 08:06:08.291460 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 08:06:08.294852 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 08:06:08.298163 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 08:06:08.304959 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 08:06:08.308356 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1471 08:06:08.311672 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 08:06:08.318342 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1473 08:06:08.321391 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 08:06:08.325478 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 08:06:08.331318 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 08:06:08.334896 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 08:06:08.338293 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 08:06:08.344678 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 08:06:08.348232 0 9 8 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
1480 08:06:08.351756 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 08:06:08.357998 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 08:06:08.361601 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 08:06:08.364673 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 08:06:08.371425 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 08:06:08.375529 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 08:06:08.378673 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1487 08:06:08.381693 0 10 8 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)
1488 08:06:08.388319 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 08:06:08.391945 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 08:06:08.395224 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 08:06:08.402092 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 08:06:08.404763 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 08:06:08.408204 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 08:06:08.414844 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 08:06:08.418230 0 11 8 | B1->B0 | 3737 3a39 | 0 1 | (0 0) (0 0)
1496 08:06:08.421302 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 08:06:08.428761 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 08:06:08.431639 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 08:06:08.434842 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 08:06:08.441910 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 08:06:08.444992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 08:06:08.447916 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 08:06:08.455094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 08:06:08.458002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 08:06:08.461217 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 08:06:08.468199 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 08:06:08.471422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 08:06:08.474707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 08:06:08.481577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 08:06:08.484865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 08:06:08.488051 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 08:06:08.491340 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 08:06:08.498419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 08:06:08.501556 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 08:06:08.505083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 08:06:08.511683 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 08:06:08.514888 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 08:06:08.518475 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 08:06:08.525433 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 08:06:08.528385 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 08:06:08.531325 Total UI for P1: 0, mck2ui 16
1522 08:06:08.534828 best dqsien dly found for B0: ( 0, 14, 8)
1523 08:06:08.538351 Total UI for P1: 0, mck2ui 16
1524 08:06:08.541693 best dqsien dly found for B1: ( 0, 14, 8)
1525 08:06:08.544872 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1526 08:06:08.548331 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1527 08:06:08.548401
1528 08:06:08.552047 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 08:06:08.555318 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1530 08:06:08.558322 [Gating] SW calibration Done
1531 08:06:08.558394 ==
1532 08:06:08.561789 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 08:06:08.564757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1534 08:06:08.564871 ==
1535 08:06:08.568255 RX Vref Scan: 0
1536 08:06:08.568334
1537 08:06:08.571753 RX Vref 0 -> 0, step: 1
1538 08:06:08.571834
1539 08:06:08.571899 RX Delay -130 -> 252, step: 16
1540 08:06:08.578452 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1541 08:06:08.581640 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1542 08:06:08.584758 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1543 08:06:08.589040 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1544 08:06:08.591951 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1545 08:06:08.598598 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1546 08:06:08.601932 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1547 08:06:08.605035 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1548 08:06:08.608423 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1549 08:06:08.611727 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1550 08:06:08.618346 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1551 08:06:08.621638 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1552 08:06:08.624735 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1553 08:06:08.628479 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1554 08:06:08.631523 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1555 08:06:08.638068 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1556 08:06:08.638150 ==
1557 08:06:08.641519 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 08:06:08.644856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 08:06:08.644939 ==
1560 08:06:08.645004 DQS Delay:
1561 08:06:08.648119 DQS0 = 0, DQS1 = 0
1562 08:06:08.648201 DQM Delay:
1563 08:06:08.651827 DQM0 = 80, DQM1 = 72
1564 08:06:08.651909 DQ Delay:
1565 08:06:08.655019 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1566 08:06:08.658079 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1567 08:06:08.662012 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1568 08:06:08.664837 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1569 08:06:08.664918
1570 08:06:08.664983
1571 08:06:08.665042 ==
1572 08:06:08.668275 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 08:06:08.671348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 08:06:08.671439 ==
1575 08:06:08.674580
1576 08:06:08.674661
1577 08:06:08.674725 TX Vref Scan disable
1578 08:06:08.677970 == TX Byte 0 ==
1579 08:06:08.681550 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1580 08:06:08.684846 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1581 08:06:08.688457 == TX Byte 1 ==
1582 08:06:08.691452 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1583 08:06:08.694708 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1584 08:06:08.694790 ==
1585 08:06:08.698033 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 08:06:08.705259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 08:06:08.705341 ==
1588 08:06:08.716531 TX Vref=22, minBit 1, minWin=26, winSum=438
1589 08:06:08.719995 TX Vref=24, minBit 1, minWin=26, winSum=440
1590 08:06:08.723069 TX Vref=26, minBit 1, minWin=26, winSum=443
1591 08:06:08.726433 TX Vref=28, minBit 1, minWin=27, winSum=450
1592 08:06:08.729776 TX Vref=30, minBit 0, minWin=27, winSum=446
1593 08:06:08.733368 TX Vref=32, minBit 0, minWin=27, winSum=449
1594 08:06:08.739843 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1595 08:06:08.739926
1596 08:06:08.743147 Final TX Range 1 Vref 28
1597 08:06:08.743229
1598 08:06:08.743294 ==
1599 08:06:08.746440 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 08:06:08.749641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 08:06:08.749727 ==
1602 08:06:08.749792
1603 08:06:08.753072
1604 08:06:08.753153 TX Vref Scan disable
1605 08:06:08.756666 == TX Byte 0 ==
1606 08:06:08.760743 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 08:06:08.763946 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 08:06:08.767484 == TX Byte 1 ==
1609 08:06:08.771353 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 08:06:08.774153 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 08:06:08.774234
1612 08:06:08.774299 [DATLAT]
1613 08:06:08.777730 Freq=800, CH1 RK0
1614 08:06:08.777812
1615 08:06:08.780835 DATLAT Default: 0xa
1616 08:06:08.780917 0, 0xFFFF, sum = 0
1617 08:06:08.784335 1, 0xFFFF, sum = 0
1618 08:06:08.784467 2, 0xFFFF, sum = 0
1619 08:06:08.787139 3, 0xFFFF, sum = 0
1620 08:06:08.787238 4, 0xFFFF, sum = 0
1621 08:06:08.790501 5, 0xFFFF, sum = 0
1622 08:06:08.790584 6, 0xFFFF, sum = 0
1623 08:06:08.793895 7, 0xFFFF, sum = 0
1624 08:06:08.793978 8, 0xFFFF, sum = 0
1625 08:06:08.797465 9, 0x0, sum = 1
1626 08:06:08.797575 10, 0x0, sum = 2
1627 08:06:08.800741 11, 0x0, sum = 3
1628 08:06:08.800824 12, 0x0, sum = 4
1629 08:06:08.804154 best_step = 10
1630 08:06:08.804236
1631 08:06:08.804300 ==
1632 08:06:08.807268 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 08:06:08.810911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 08:06:08.810993 ==
1635 08:06:08.811057 RX Vref Scan: 1
1636 08:06:08.811117
1637 08:06:08.813928 Set Vref Range= 32 -> 127
1638 08:06:08.814010
1639 08:06:08.817367 RX Vref 32 -> 127, step: 1
1640 08:06:08.817448
1641 08:06:08.821063 RX Delay -111 -> 252, step: 8
1642 08:06:08.821145
1643 08:06:08.823993 Set Vref, RX VrefLevel [Byte0]: 32
1644 08:06:08.827298 [Byte1]: 32
1645 08:06:08.827442
1646 08:06:08.830701 Set Vref, RX VrefLevel [Byte0]: 33
1647 08:06:08.834439 [Byte1]: 33
1648 08:06:08.834521
1649 08:06:08.837744 Set Vref, RX VrefLevel [Byte0]: 34
1650 08:06:08.840735 [Byte1]: 34
1651 08:06:08.844547
1652 08:06:08.844629 Set Vref, RX VrefLevel [Byte0]: 35
1653 08:06:08.848140 [Byte1]: 35
1654 08:06:08.852525
1655 08:06:08.852606 Set Vref, RX VrefLevel [Byte0]: 36
1656 08:06:08.855536 [Byte1]: 36
1657 08:06:08.860049
1658 08:06:08.860130 Set Vref, RX VrefLevel [Byte0]: 37
1659 08:06:08.863333 [Byte1]: 37
1660 08:06:08.867371
1661 08:06:08.867492 Set Vref, RX VrefLevel [Byte0]: 38
1662 08:06:08.870770 [Byte1]: 38
1663 08:06:08.874974
1664 08:06:08.875056 Set Vref, RX VrefLevel [Byte0]: 39
1665 08:06:08.878491 [Byte1]: 39
1666 08:06:08.883140
1667 08:06:08.883222 Set Vref, RX VrefLevel [Byte0]: 40
1668 08:06:08.886515 [Byte1]: 40
1669 08:06:08.890335
1670 08:06:08.890416 Set Vref, RX VrefLevel [Byte0]: 41
1671 08:06:08.893996 [Byte1]: 41
1672 08:06:08.898066
1673 08:06:08.898148 Set Vref, RX VrefLevel [Byte0]: 42
1674 08:06:08.901262 [Byte1]: 42
1675 08:06:08.905543
1676 08:06:08.905650 Set Vref, RX VrefLevel [Byte0]: 43
1677 08:06:08.909156 [Byte1]: 43
1678 08:06:08.913742
1679 08:06:08.913845 Set Vref, RX VrefLevel [Byte0]: 44
1680 08:06:08.916914 [Byte1]: 44
1681 08:06:08.921151
1682 08:06:08.921232 Set Vref, RX VrefLevel [Byte0]: 45
1683 08:06:08.924681 [Byte1]: 45
1684 08:06:08.929011
1685 08:06:08.929093 Set Vref, RX VrefLevel [Byte0]: 46
1686 08:06:08.932450 [Byte1]: 46
1687 08:06:08.936341
1688 08:06:08.936423 Set Vref, RX VrefLevel [Byte0]: 47
1689 08:06:08.939461 [Byte1]: 47
1690 08:06:08.944248
1691 08:06:08.944329 Set Vref, RX VrefLevel [Byte0]: 48
1692 08:06:08.947391 [Byte1]: 48
1693 08:06:08.951703
1694 08:06:08.951816 Set Vref, RX VrefLevel [Byte0]: 49
1695 08:06:08.955323 [Byte1]: 49
1696 08:06:08.959105
1697 08:06:08.959186 Set Vref, RX VrefLevel [Byte0]: 50
1698 08:06:08.962750 [Byte1]: 50
1699 08:06:08.967110
1700 08:06:08.967212 Set Vref, RX VrefLevel [Byte0]: 51
1701 08:06:08.970597 [Byte1]: 51
1702 08:06:08.974730
1703 08:06:08.974812 Set Vref, RX VrefLevel [Byte0]: 52
1704 08:06:08.978192 [Byte1]: 52
1705 08:06:08.982020
1706 08:06:08.982102 Set Vref, RX VrefLevel [Byte0]: 53
1707 08:06:08.985774 [Byte1]: 53
1708 08:06:08.990212
1709 08:06:08.990366 Set Vref, RX VrefLevel [Byte0]: 54
1710 08:06:08.992911 [Byte1]: 54
1711 08:06:08.997535
1712 08:06:08.997616 Set Vref, RX VrefLevel [Byte0]: 55
1713 08:06:09.000884 [Byte1]: 55
1714 08:06:09.005512
1715 08:06:09.005594 Set Vref, RX VrefLevel [Byte0]: 56
1716 08:06:09.008927 [Byte1]: 56
1717 08:06:09.012635
1718 08:06:09.012716 Set Vref, RX VrefLevel [Byte0]: 57
1719 08:06:09.016134 [Byte1]: 57
1720 08:06:09.020450
1721 08:06:09.020531 Set Vref, RX VrefLevel [Byte0]: 58
1722 08:06:09.023977 [Byte1]: 58
1723 08:06:09.028127
1724 08:06:09.028208 Set Vref, RX VrefLevel [Byte0]: 59
1725 08:06:09.031318 [Byte1]: 59
1726 08:06:09.035538
1727 08:06:09.035620 Set Vref, RX VrefLevel [Byte0]: 60
1728 08:06:09.038966 [Byte1]: 60
1729 08:06:09.043885
1730 08:06:09.043967 Set Vref, RX VrefLevel [Byte0]: 61
1731 08:06:09.047004 [Byte1]: 61
1732 08:06:09.051046
1733 08:06:09.051128 Set Vref, RX VrefLevel [Byte0]: 62
1734 08:06:09.054065 [Byte1]: 62
1735 08:06:09.058883
1736 08:06:09.058964 Set Vref, RX VrefLevel [Byte0]: 63
1737 08:06:09.061932 [Byte1]: 63
1738 08:06:09.066452
1739 08:06:09.066559 Set Vref, RX VrefLevel [Byte0]: 64
1740 08:06:09.069606 [Byte1]: 64
1741 08:06:09.074165
1742 08:06:09.074270 Set Vref, RX VrefLevel [Byte0]: 65
1743 08:06:09.077557 [Byte1]: 65
1744 08:06:09.081628
1745 08:06:09.081710 Set Vref, RX VrefLevel [Byte0]: 66
1746 08:06:09.084688 [Byte1]: 66
1747 08:06:09.088992
1748 08:06:09.089073 Set Vref, RX VrefLevel [Byte0]: 67
1749 08:06:09.092465 [Byte1]: 67
1750 08:06:09.097009
1751 08:06:09.097091 Set Vref, RX VrefLevel [Byte0]: 68
1752 08:06:09.100142 [Byte1]: 68
1753 08:06:09.104865
1754 08:06:09.104946 Set Vref, RX VrefLevel [Byte0]: 69
1755 08:06:09.107569 [Byte1]: 69
1756 08:06:09.112076
1757 08:06:09.112158 Set Vref, RX VrefLevel [Byte0]: 70
1758 08:06:09.115290 [Byte1]: 70
1759 08:06:09.119654
1760 08:06:09.119734 Set Vref, RX VrefLevel [Byte0]: 71
1761 08:06:09.123304 [Byte1]: 71
1762 08:06:09.127598
1763 08:06:09.127680 Set Vref, RX VrefLevel [Byte0]: 72
1764 08:06:09.130752 [Byte1]: 72
1765 08:06:09.135290
1766 08:06:09.135417 Set Vref, RX VrefLevel [Byte0]: 73
1767 08:06:09.138705 [Byte1]: 73
1768 08:06:09.142816
1769 08:06:09.142897 Final RX Vref Byte 0 = 60 to rank0
1770 08:06:09.146151 Final RX Vref Byte 1 = 53 to rank0
1771 08:06:09.149626 Final RX Vref Byte 0 = 60 to rank1
1772 08:06:09.152676 Final RX Vref Byte 1 = 53 to rank1==
1773 08:06:09.156112 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 08:06:09.162317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 08:06:09.162403 ==
1776 08:06:09.162470 DQS Delay:
1777 08:06:09.162546 DQS0 = 0, DQS1 = 0
1778 08:06:09.166159 DQM Delay:
1779 08:06:09.166242 DQM0 = 80, DQM1 = 70
1780 08:06:09.169510 DQ Delay:
1781 08:06:09.172478 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1782 08:06:09.175892 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1783 08:06:09.179098 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1784 08:06:09.182351 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1785 08:06:09.182433
1786 08:06:09.182500
1787 08:06:09.189491 [DQSOSCAuto] RK0, (LSB)MR18= 0x1620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1788 08:06:09.192651 CH1 RK0: MR19=606, MR18=1620
1789 08:06:09.199267 CH1_RK0: MR19=0x606, MR18=0x1620, DQSOSC=401, MR23=63, INC=91, DEC=61
1790 08:06:09.199352
1791 08:06:09.202937 ----->DramcWriteLeveling(PI) begin...
1792 08:06:09.203021 ==
1793 08:06:09.205804 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 08:06:09.209001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 08:06:09.209084 ==
1796 08:06:09.212951 Write leveling (Byte 0): 26 => 26
1797 08:06:09.215671 Write leveling (Byte 1): 32 => 32
1798 08:06:09.219147 DramcWriteLeveling(PI) end<-----
1799 08:06:09.219229
1800 08:06:09.219293 ==
1801 08:06:09.222369 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 08:06:09.225824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 08:06:09.225907 ==
1804 08:06:09.229325 [Gating] SW mode calibration
1805 08:06:09.235697 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 08:06:09.242183 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 08:06:09.245724 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 08:06:09.248692 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1809 08:06:09.255983 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 08:06:09.259217 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 08:06:09.262561 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 08:06:09.269199 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 08:06:09.272194 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 08:06:09.275816 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 08:06:09.282467 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 08:06:09.285730 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 08:06:09.289003 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 08:06:09.295585 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 08:06:09.299004 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 08:06:09.302624 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 08:06:09.309441 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 08:06:09.312348 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 08:06:09.315694 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 08:06:09.322193 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1825 08:06:09.325763 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 08:06:09.329180 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 08:06:09.332428 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 08:06:09.339047 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 08:06:09.342421 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 08:06:09.345675 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 08:06:09.352390 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 08:06:09.355696 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1833 08:06:09.359127 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1834 08:06:09.365641 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 08:06:09.369228 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 08:06:09.372609 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 08:06:09.378916 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 08:06:09.382069 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 08:06:09.385458 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 08:06:09.392156 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (1 1)
1841 08:06:09.395777 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1842 08:06:09.398823 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 08:06:09.405870 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 08:06:09.409305 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 08:06:09.412450 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 08:06:09.419072 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 08:06:09.422309 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1848 08:06:09.425551 0 11 4 | B1->B0 | 2929 3939 | 0 0 | (0 0) (1 1)
1849 08:06:09.428825 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
1850 08:06:09.435696 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 08:06:09.438834 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 08:06:09.442306 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 08:06:09.448801 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 08:06:09.452170 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 08:06:09.455524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 08:06:09.462458 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 08:06:09.465681 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 08:06:09.468834 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 08:06:09.475626 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 08:06:09.478775 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 08:06:09.482352 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 08:06:09.489173 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 08:06:09.492109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 08:06:09.495438 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 08:06:09.502164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 08:06:09.505599 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 08:06:09.508745 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 08:06:09.515731 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 08:06:09.519346 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 08:06:09.522405 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 08:06:09.525571 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 08:06:09.532169 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1873 08:06:09.535713 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1874 08:06:09.538785 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 08:06:09.542569 Total UI for P1: 0, mck2ui 16
1876 08:06:09.545505 best dqsien dly found for B0: ( 0, 14, 6)
1877 08:06:09.548922 Total UI for P1: 0, mck2ui 16
1878 08:06:09.552829 best dqsien dly found for B1: ( 0, 14, 8)
1879 08:06:09.555543 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1880 08:06:09.558918 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1881 08:06:09.559001
1882 08:06:09.565479 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1883 08:06:09.568819 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1884 08:06:09.568902 [Gating] SW calibration Done
1885 08:06:09.572577 ==
1886 08:06:09.576102 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 08:06:09.578817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 08:06:09.578900 ==
1889 08:06:09.578966 RX Vref Scan: 0
1890 08:06:09.579028
1891 08:06:09.582294 RX Vref 0 -> 0, step: 1
1892 08:06:09.582376
1893 08:06:09.585460 RX Delay -130 -> 252, step: 16
1894 08:06:09.589153 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1895 08:06:09.592544 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1896 08:06:09.599141 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1897 08:06:09.602730 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1898 08:06:09.605476 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1899 08:06:09.609050 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1900 08:06:09.612328 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1901 08:06:09.615730 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1902 08:06:09.622695 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1903 08:06:09.626244 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1904 08:06:09.629099 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1905 08:06:09.632613 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1906 08:06:09.635640 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1907 08:06:09.642329 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1908 08:06:09.645905 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1909 08:06:09.649008 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1910 08:06:09.649090 ==
1911 08:06:09.652501 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 08:06:09.655652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 08:06:09.655734 ==
1914 08:06:09.659076 DQS Delay:
1915 08:06:09.659158 DQS0 = 0, DQS1 = 0
1916 08:06:09.662430 DQM Delay:
1917 08:06:09.662531 DQM0 = 77, DQM1 = 71
1918 08:06:09.662636 DQ Delay:
1919 08:06:09.665858 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1920 08:06:09.669303 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1921 08:06:09.672678 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1922 08:06:09.675616 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1923 08:06:09.675699
1924 08:06:09.675764
1925 08:06:09.679154 ==
1926 08:06:09.682080 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 08:06:09.685600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 08:06:09.685683 ==
1929 08:06:09.685749
1930 08:06:09.685810
1931 08:06:09.689054 TX Vref Scan disable
1932 08:06:09.689137 == TX Byte 0 ==
1933 08:06:09.695394 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1934 08:06:09.698831 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1935 08:06:09.698914 == TX Byte 1 ==
1936 08:06:09.702804 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1937 08:06:09.709173 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1938 08:06:09.709255 ==
1939 08:06:09.712406 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 08:06:09.715683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 08:06:09.715793 ==
1942 08:06:09.729581 TX Vref=22, minBit 2, minWin=28, winSum=455
1943 08:06:09.733093 TX Vref=24, minBit 3, minWin=28, winSum=455
1944 08:06:09.736534 TX Vref=26, minBit 0, minWin=28, winSum=454
1945 08:06:09.739891 TX Vref=28, minBit 5, minWin=28, winSum=463
1946 08:06:09.742814 TX Vref=30, minBit 1, minWin=28, winSum=464
1947 08:06:09.749456 TX Vref=32, minBit 1, minWin=28, winSum=463
1948 08:06:09.753067 [TxChooseVref] Worse bit 1, Min win 28, Win sum 464, Final Vref 30
1949 08:06:09.753150
1950 08:06:09.755864 Final TX Range 1 Vref 30
1951 08:06:09.755947
1952 08:06:09.756013 ==
1953 08:06:09.759162 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 08:06:09.762612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 08:06:09.762706 ==
1956 08:06:09.765777
1957 08:06:09.765861
1958 08:06:09.765926 TX Vref Scan disable
1959 08:06:09.769395 == TX Byte 0 ==
1960 08:06:09.773128 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1961 08:06:09.776569 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1962 08:06:09.779353 == TX Byte 1 ==
1963 08:06:09.782904 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1964 08:06:09.786259 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1965 08:06:09.789948
1966 08:06:09.790031 [DATLAT]
1967 08:06:09.790097 Freq=800, CH1 RK1
1968 08:06:09.790159
1969 08:06:09.793115 DATLAT Default: 0xa
1970 08:06:09.793198 0, 0xFFFF, sum = 0
1971 08:06:09.796530 1, 0xFFFF, sum = 0
1972 08:06:09.796615 2, 0xFFFF, sum = 0
1973 08:06:09.799681 3, 0xFFFF, sum = 0
1974 08:06:09.799764 4, 0xFFFF, sum = 0
1975 08:06:09.802944 5, 0xFFFF, sum = 0
1976 08:06:09.803027 6, 0xFFFF, sum = 0
1977 08:06:09.806516 7, 0xFFFF, sum = 0
1978 08:06:09.809936 8, 0xFFFF, sum = 0
1979 08:06:09.810020 9, 0x0, sum = 1
1980 08:06:09.810087 10, 0x0, sum = 2
1981 08:06:09.813148 11, 0x0, sum = 3
1982 08:06:09.813231 12, 0x0, sum = 4
1983 08:06:09.816303 best_step = 10
1984 08:06:09.816385
1985 08:06:09.816451 ==
1986 08:06:09.819562 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 08:06:09.822958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 08:06:09.823043 ==
1989 08:06:09.826497 RX Vref Scan: 0
1990 08:06:09.826618
1991 08:06:09.826721 RX Vref 0 -> 0, step: 1
1992 08:06:09.826832
1993 08:06:09.829662 RX Delay -111 -> 252, step: 8
1994 08:06:09.836471 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1995 08:06:09.839575 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1996 08:06:09.843423 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1997 08:06:09.846313 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
1998 08:06:09.849748 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1999 08:06:09.856437 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2000 08:06:09.860035 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2001 08:06:09.863248 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2002 08:06:09.866230 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2003 08:06:09.870153 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2004 08:06:09.876499 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2005 08:06:09.879545 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2006 08:06:09.882841 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2007 08:06:09.886418 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2008 08:06:09.889787 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2009 08:06:09.896350 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2010 08:06:09.896459 ==
2011 08:06:09.899814 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 08:06:09.903032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 08:06:09.903129 ==
2014 08:06:09.903236 DQS Delay:
2015 08:06:09.906092 DQS0 = 0, DQS1 = 0
2016 08:06:09.906199 DQM Delay:
2017 08:06:09.909567 DQM0 = 78, DQM1 = 74
2018 08:06:09.909668 DQ Delay:
2019 08:06:09.912650 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =76
2020 08:06:09.916180 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2021 08:06:09.919333 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =64
2022 08:06:09.922560 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =80
2023 08:06:09.922664
2024 08:06:09.922753
2025 08:06:09.932874 [DQSOSCAuto] RK1, (LSB)MR18= 0x253e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2026 08:06:09.932955 CH1 RK1: MR19=606, MR18=253E
2027 08:06:09.939437 CH1_RK1: MR19=0x606, MR18=0x253E, DQSOSC=394, MR23=63, INC=95, DEC=63
2028 08:06:09.942554 [RxdqsGatingPostProcess] freq 800
2029 08:06:09.949536 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2030 08:06:09.953106 Pre-setting of DQS Precalculation
2031 08:06:09.956014 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2032 08:06:09.962655 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2033 08:06:09.969488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2034 08:06:09.972709
2035 08:06:09.972785
2036 08:06:09.972848 [Calibration Summary] 1600 Mbps
2037 08:06:09.976196 CH 0, Rank 0
2038 08:06:09.976269 SW Impedance : PASS
2039 08:06:09.979529 DUTY Scan : NO K
2040 08:06:09.982643 ZQ Calibration : PASS
2041 08:06:09.982724 Jitter Meter : NO K
2042 08:06:09.986354 CBT Training : PASS
2043 08:06:09.989537 Write leveling : PASS
2044 08:06:09.989616 RX DQS gating : PASS
2045 08:06:09.992421 RX DQ/DQS(RDDQC) : PASS
2046 08:06:09.995847 TX DQ/DQS : PASS
2047 08:06:09.995952 RX DATLAT : PASS
2048 08:06:09.999146 RX DQ/DQS(Engine): PASS
2049 08:06:10.002950 TX OE : NO K
2050 08:06:10.003025 All Pass.
2051 08:06:10.003095
2052 08:06:10.003159 CH 0, Rank 1
2053 08:06:10.006006 SW Impedance : PASS
2054 08:06:10.009540 DUTY Scan : NO K
2055 08:06:10.009627 ZQ Calibration : PASS
2056 08:06:10.012549 Jitter Meter : NO K
2057 08:06:10.012628 CBT Training : PASS
2058 08:06:10.015982 Write leveling : PASS
2059 08:06:10.019541 RX DQS gating : PASS
2060 08:06:10.019628 RX DQ/DQS(RDDQC) : PASS
2061 08:06:10.022871 TX DQ/DQS : PASS
2062 08:06:10.026238 RX DATLAT : PASS
2063 08:06:10.026318 RX DQ/DQS(Engine): PASS
2064 08:06:10.029697 TX OE : NO K
2065 08:06:10.029773 All Pass.
2066 08:06:10.029836
2067 08:06:10.033017 CH 1, Rank 0
2068 08:06:10.033094 SW Impedance : PASS
2069 08:06:10.036451 DUTY Scan : NO K
2070 08:06:10.039587 ZQ Calibration : PASS
2071 08:06:10.039693 Jitter Meter : NO K
2072 08:06:10.042547 CBT Training : PASS
2073 08:06:10.046204 Write leveling : PASS
2074 08:06:10.046281 RX DQS gating : PASS
2075 08:06:10.049508 RX DQ/DQS(RDDQC) : PASS
2076 08:06:10.049589 TX DQ/DQS : PASS
2077 08:06:10.052602 RX DATLAT : PASS
2078 08:06:10.056088 RX DQ/DQS(Engine): PASS
2079 08:06:10.056194 TX OE : NO K
2080 08:06:10.059205 All Pass.
2081 08:06:10.059307
2082 08:06:10.059426 CH 1, Rank 1
2083 08:06:10.063020 SW Impedance : PASS
2084 08:06:10.063105 DUTY Scan : NO K
2085 08:06:10.066056 ZQ Calibration : PASS
2086 08:06:10.069581 Jitter Meter : NO K
2087 08:06:10.069665 CBT Training : PASS
2088 08:06:10.072773 Write leveling : PASS
2089 08:06:10.076057 RX DQS gating : PASS
2090 08:06:10.076144 RX DQ/DQS(RDDQC) : PASS
2091 08:06:10.079625 TX DQ/DQS : PASS
2092 08:06:10.082663 RX DATLAT : PASS
2093 08:06:10.082741 RX DQ/DQS(Engine): PASS
2094 08:06:10.086236 TX OE : NO K
2095 08:06:10.086318 All Pass.
2096 08:06:10.086400
2097 08:06:10.089666 DramC Write-DBI off
2098 08:06:10.093193 PER_BANK_REFRESH: Hybrid Mode
2099 08:06:10.093279 TX_TRACKING: ON
2100 08:06:10.096423 [GetDramInforAfterCalByMRR] Vendor 6.
2101 08:06:10.099546 [GetDramInforAfterCalByMRR] Revision 606.
2102 08:06:10.102787 [GetDramInforAfterCalByMRR] Revision 2 0.
2103 08:06:10.106227 MR0 0x3b3b
2104 08:06:10.106307 MR8 0x5151
2105 08:06:10.109392 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 08:06:10.109495
2107 08:06:10.109608 MR0 0x3b3b
2108 08:06:10.112809 MR8 0x5151
2109 08:06:10.116261 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 08:06:10.116345
2111 08:06:10.122891 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2112 08:06:10.126284 [FAST_K] Save calibration result to emmc
2113 08:06:10.133189 [FAST_K] Save calibration result to emmc
2114 08:06:10.133269 dram_init: config_dvfs: 1
2115 08:06:10.136037 dramc_set_vcore_voltage set vcore to 662500
2116 08:06:10.139502 Read voltage for 1200, 2
2117 08:06:10.139588 Vio18 = 0
2118 08:06:10.142722 Vcore = 662500
2119 08:06:10.142800 Vdram = 0
2120 08:06:10.142881 Vddq = 0
2121 08:06:10.146157 Vmddr = 0
2122 08:06:10.149826 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2123 08:06:10.155985 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2124 08:06:10.156070 MEM_TYPE=3, freq_sel=15
2125 08:06:10.159421 sv_algorithm_assistance_LP4_1600
2126 08:06:10.166012 ============ PULL DRAM RESETB DOWN ============
2127 08:06:10.169705 ========== PULL DRAM RESETB DOWN end =========
2128 08:06:10.173209 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 08:06:10.175893 ===================================
2130 08:06:10.179502 LPDDR4 DRAM CONFIGURATION
2131 08:06:10.182853 ===================================
2132 08:06:10.185853 EX_ROW_EN[0] = 0x0
2133 08:06:10.185937 EX_ROW_EN[1] = 0x0
2134 08:06:10.189618 LP4Y_EN = 0x0
2135 08:06:10.189693 WORK_FSP = 0x0
2136 08:06:10.192665 WL = 0x4
2137 08:06:10.192745 RL = 0x4
2138 08:06:10.196325 BL = 0x2
2139 08:06:10.196408 RPST = 0x0
2140 08:06:10.199714 RD_PRE = 0x0
2141 08:06:10.199798 WR_PRE = 0x1
2142 08:06:10.202579 WR_PST = 0x0
2143 08:06:10.202661 DBI_WR = 0x0
2144 08:06:10.206240 DBI_RD = 0x0
2145 08:06:10.206322 OTF = 0x1
2146 08:06:10.209474 ===================================
2147 08:06:10.212512 ===================================
2148 08:06:10.216100 ANA top config
2149 08:06:10.219206 ===================================
2150 08:06:10.219288 DLL_ASYNC_EN = 0
2151 08:06:10.223032 ALL_SLAVE_EN = 0
2152 08:06:10.226185 NEW_RANK_MODE = 1
2153 08:06:10.229132 DLL_IDLE_MODE = 1
2154 08:06:10.232734 LP45_APHY_COMB_EN = 1
2155 08:06:10.232817 TX_ODT_DIS = 1
2156 08:06:10.235857 NEW_8X_MODE = 1
2157 08:06:10.239278 ===================================
2158 08:06:10.242478 ===================================
2159 08:06:10.246303 data_rate = 2400
2160 08:06:10.249211 CKR = 1
2161 08:06:10.252715 DQ_P2S_RATIO = 8
2162 08:06:10.256175 ===================================
2163 08:06:10.256254 CA_P2S_RATIO = 8
2164 08:06:10.259645 DQ_CA_OPEN = 0
2165 08:06:10.262719 DQ_SEMI_OPEN = 0
2166 08:06:10.266237 CA_SEMI_OPEN = 0
2167 08:06:10.269410 CA_FULL_RATE = 0
2168 08:06:10.272227 DQ_CKDIV4_EN = 0
2169 08:06:10.272299 CA_CKDIV4_EN = 0
2170 08:06:10.275760 CA_PREDIV_EN = 0
2171 08:06:10.279212 PH8_DLY = 17
2172 08:06:10.282408 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2173 08:06:10.286059 DQ_AAMCK_DIV = 4
2174 08:06:10.289240 CA_AAMCK_DIV = 4
2175 08:06:10.289342 CA_ADMCK_DIV = 4
2176 08:06:10.292489 DQ_TRACK_CA_EN = 0
2177 08:06:10.295988 CA_PICK = 1200
2178 08:06:10.299284 CA_MCKIO = 1200
2179 08:06:10.302718 MCKIO_SEMI = 0
2180 08:06:10.305797 PLL_FREQ = 2366
2181 08:06:10.309085 DQ_UI_PI_RATIO = 32
2182 08:06:10.312349 CA_UI_PI_RATIO = 0
2183 08:06:10.316251 ===================================
2184 08:06:10.319055 ===================================
2185 08:06:10.319159 memory_type:LPDDR4
2186 08:06:10.322095 GP_NUM : 10
2187 08:06:10.322170 SRAM_EN : 1
2188 08:06:10.325502 MD32_EN : 0
2189 08:06:10.328910 ===================================
2190 08:06:10.332514 [ANA_INIT] >>>>>>>>>>>>>>
2191 08:06:10.335637 <<<<<< [CONFIGURE PHASE]: ANA_TX
2192 08:06:10.339138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2193 08:06:10.342012 ===================================
2194 08:06:10.342100 data_rate = 2400,PCW = 0X5b00
2195 08:06:10.345495 ===================================
2196 08:06:10.352318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2197 08:06:10.355348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 08:06:10.362170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 08:06:10.365758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2200 08:06:10.368806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2201 08:06:10.372342 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2202 08:06:10.375575 [ANA_INIT] flow start
2203 08:06:10.379025 [ANA_INIT] PLL >>>>>>>>
2204 08:06:10.379125 [ANA_INIT] PLL <<<<<<<<
2205 08:06:10.382323 [ANA_INIT] MIDPI >>>>>>>>
2206 08:06:10.385480 [ANA_INIT] MIDPI <<<<<<<<
2207 08:06:10.385585 [ANA_INIT] DLL >>>>>>>>
2208 08:06:10.388764 [ANA_INIT] DLL <<<<<<<<
2209 08:06:10.392105 [ANA_INIT] flow end
2210 08:06:10.395928 ============ LP4 DIFF to SE enter ============
2211 08:06:10.399120 ============ LP4 DIFF to SE exit ============
2212 08:06:10.402502 [ANA_INIT] <<<<<<<<<<<<<
2213 08:06:10.406012 [Flow] Enable top DCM control >>>>>
2214 08:06:10.408868 [Flow] Enable top DCM control <<<<<
2215 08:06:10.412028 Enable DLL master slave shuffle
2216 08:06:10.415399 ==============================================================
2217 08:06:10.419017 Gating Mode config
2218 08:06:10.425619 ==============================================================
2219 08:06:10.425707 Config description:
2220 08:06:10.436305 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2221 08:06:10.442354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2222 08:06:10.445529 SELPH_MODE 0: By rank 1: By Phase
2223 08:06:10.452056 ==============================================================
2224 08:06:10.455720 GAT_TRACK_EN = 1
2225 08:06:10.458974 RX_GATING_MODE = 2
2226 08:06:10.462293 RX_GATING_TRACK_MODE = 2
2227 08:06:10.465578 SELPH_MODE = 1
2228 08:06:10.468640 PICG_EARLY_EN = 1
2229 08:06:10.468746 VALID_LAT_VALUE = 1
2230 08:06:10.475336 ==============================================================
2231 08:06:10.479141 Enter into Gating configuration >>>>
2232 08:06:10.481927 Exit from Gating configuration <<<<
2233 08:06:10.485326 Enter into DVFS_PRE_config >>>>>
2234 08:06:10.495501 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2235 08:06:10.498637 Exit from DVFS_PRE_config <<<<<
2236 08:06:10.502357 Enter into PICG configuration >>>>
2237 08:06:10.505340 Exit from PICG configuration <<<<
2238 08:06:10.508820 [RX_INPUT] configuration >>>>>
2239 08:06:10.512230 [RX_INPUT] configuration <<<<<
2240 08:06:10.515237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2241 08:06:10.522217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2242 08:06:10.529253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 08:06:10.535444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 08:06:10.542087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 08:06:10.545861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 08:06:10.552716 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2247 08:06:10.555776 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2248 08:06:10.559116 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2249 08:06:10.562143 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2250 08:06:10.568904 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2251 08:06:10.572763 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2252 08:06:10.576050 ===================================
2253 08:06:10.579004 LPDDR4 DRAM CONFIGURATION
2254 08:06:10.582379 ===================================
2255 08:06:10.582478 EX_ROW_EN[0] = 0x0
2256 08:06:10.585467 EX_ROW_EN[1] = 0x0
2257 08:06:10.585564 LP4Y_EN = 0x0
2258 08:06:10.589301 WORK_FSP = 0x0
2259 08:06:10.589471 WL = 0x4
2260 08:06:10.591986 RL = 0x4
2261 08:06:10.592090 BL = 0x2
2262 08:06:10.595567 RPST = 0x0
2263 08:06:10.595639 RD_PRE = 0x0
2264 08:06:10.599026 WR_PRE = 0x1
2265 08:06:10.599124 WR_PST = 0x0
2266 08:06:10.602323 DBI_WR = 0x0
2267 08:06:10.602418 DBI_RD = 0x0
2268 08:06:10.605705 OTF = 0x1
2269 08:06:10.608628 ===================================
2270 08:06:10.612032 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2271 08:06:10.615558 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2272 08:06:10.622324 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 08:06:10.626076 ===================================
2274 08:06:10.626175 LPDDR4 DRAM CONFIGURATION
2275 08:06:10.629455 ===================================
2276 08:06:10.632601 EX_ROW_EN[0] = 0x10
2277 08:06:10.635986 EX_ROW_EN[1] = 0x0
2278 08:06:10.636086 LP4Y_EN = 0x0
2279 08:06:10.638966 WORK_FSP = 0x0
2280 08:06:10.639037 WL = 0x4
2281 08:06:10.642802 RL = 0x4
2282 08:06:10.642902 BL = 0x2
2283 08:06:10.645726 RPST = 0x0
2284 08:06:10.645821 RD_PRE = 0x0
2285 08:06:10.648828 WR_PRE = 0x1
2286 08:06:10.648922 WR_PST = 0x0
2287 08:06:10.652058 DBI_WR = 0x0
2288 08:06:10.652152 DBI_RD = 0x0
2289 08:06:10.655868 OTF = 0x1
2290 08:06:10.658972 ===================================
2291 08:06:10.665768 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2292 08:06:10.665873 ==
2293 08:06:10.669030 Dram Type= 6, Freq= 0, CH_0, rank 0
2294 08:06:10.672467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2295 08:06:10.672551 ==
2296 08:06:10.675680 [Duty_Offset_Calibration]
2297 08:06:10.675757 B0:2 B1:0 CA:4
2298 08:06:10.675821
2299 08:06:10.678807 [DutyScan_Calibration_Flow] k_type=0
2300 08:06:10.689454
2301 08:06:10.689530 ==CLK 0==
2302 08:06:10.692449 Final CLK duty delay cell = 0
2303 08:06:10.695763 [0] MAX Duty = 5031%(X100), DQS PI = 12
2304 08:06:10.699201 [0] MIN Duty = 4907%(X100), DQS PI = 54
2305 08:06:10.699275 [0] AVG Duty = 4969%(X100)
2306 08:06:10.702231
2307 08:06:10.702300 CH0 CLK Duty spec in!! Max-Min= 124%
2308 08:06:10.708985 [DutyScan_Calibration_Flow] ====Done====
2309 08:06:10.709058
2310 08:06:10.712322 [DutyScan_Calibration_Flow] k_type=1
2311 08:06:10.727757
2312 08:06:10.727859 ==DQS 0 ==
2313 08:06:10.730755 Final DQS duty delay cell = 0
2314 08:06:10.734220 [0] MAX Duty = 5062%(X100), DQS PI = 12
2315 08:06:10.737447 [0] MIN Duty = 4907%(X100), DQS PI = 48
2316 08:06:10.740599 [0] AVG Duty = 4984%(X100)
2317 08:06:10.740694
2318 08:06:10.740756 ==DQS 1 ==
2319 08:06:10.744022 Final DQS duty delay cell = -4
2320 08:06:10.747456 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2321 08:06:10.750876 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2322 08:06:10.754272 [-4] AVG Duty = 4938%(X100)
2323 08:06:10.754369
2324 08:06:10.757786 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2325 08:06:10.757865
2326 08:06:10.760889 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2327 08:06:10.763927 [DutyScan_Calibration_Flow] ====Done====
2328 08:06:10.764026
2329 08:06:10.767817 [DutyScan_Calibration_Flow] k_type=3
2330 08:06:10.784029
2331 08:06:10.784109 ==DQM 0 ==
2332 08:06:10.787881 Final DQM duty delay cell = 0
2333 08:06:10.790953 [0] MAX Duty = 5124%(X100), DQS PI = 28
2334 08:06:10.794125 [0] MIN Duty = 4907%(X100), DQS PI = 0
2335 08:06:10.794216 [0] AVG Duty = 5015%(X100)
2336 08:06:10.798083
2337 08:06:10.798167 ==DQM 1 ==
2338 08:06:10.801214 Final DQM duty delay cell = 0
2339 08:06:10.804090 [0] MAX Duty = 4969%(X100), DQS PI = 50
2340 08:06:10.807655 [0] MIN Duty = 4844%(X100), DQS PI = 24
2341 08:06:10.807738 [0] AVG Duty = 4906%(X100)
2342 08:06:10.810850
2343 08:06:10.814162 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2344 08:06:10.814244
2345 08:06:10.817838 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2346 08:06:10.820860 [DutyScan_Calibration_Flow] ====Done====
2347 08:06:10.820942
2348 08:06:10.824255 [DutyScan_Calibration_Flow] k_type=2
2349 08:06:10.839059
2350 08:06:10.839167 ==DQ 0 ==
2351 08:06:10.842566 Final DQ duty delay cell = -4
2352 08:06:10.846032 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2353 08:06:10.849524 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2354 08:06:10.852775 [-4] AVG Duty = 4969%(X100)
2355 08:06:10.852850
2356 08:06:10.852918 ==DQ 1 ==
2357 08:06:10.855656 Final DQ duty delay cell = -4
2358 08:06:10.858931 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2359 08:06:10.862536 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2360 08:06:10.866012 [-4] AVG Duty = 4938%(X100)
2361 08:06:10.866095
2362 08:06:10.869427 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2363 08:06:10.869513
2364 08:06:10.872624 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2365 08:06:10.875842 [DutyScan_Calibration_Flow] ====Done====
2366 08:06:10.875925 ==
2367 08:06:10.879100 Dram Type= 6, Freq= 0, CH_1, rank 0
2368 08:06:10.882463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 08:06:10.882546 ==
2370 08:06:10.885970 [Duty_Offset_Calibration]
2371 08:06:10.886079 B0:1 B1:-2 CA:0
2372 08:06:10.886170
2373 08:06:10.888949 [DutyScan_Calibration_Flow] k_type=0
2374 08:06:10.899825
2375 08:06:10.899907 ==CLK 0==
2376 08:06:10.903298 Final CLK duty delay cell = 0
2377 08:06:10.906649 [0] MAX Duty = 5062%(X100), DQS PI = 30
2378 08:06:10.909788 [0] MIN Duty = 4876%(X100), DQS PI = 2
2379 08:06:10.909871 [0] AVG Duty = 4969%(X100)
2380 08:06:10.913225
2381 08:06:10.913306 CH1 CLK Duty spec in!! Max-Min= 186%
2382 08:06:10.920008 [DutyScan_Calibration_Flow] ====Done====
2383 08:06:10.920091
2384 08:06:10.922930 [DutyScan_Calibration_Flow] k_type=1
2385 08:06:10.938426
2386 08:06:10.938508 ==DQS 0 ==
2387 08:06:10.941380 Final DQS duty delay cell = -4
2388 08:06:10.944928 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2389 08:06:10.948048 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2390 08:06:10.951497 [-4] AVG Duty = 4953%(X100)
2391 08:06:10.951593
2392 08:06:10.951688 ==DQS 1 ==
2393 08:06:10.955298 Final DQS duty delay cell = 0
2394 08:06:10.958065 [0] MAX Duty = 5093%(X100), DQS PI = 0
2395 08:06:10.961910 [0] MIN Duty = 4875%(X100), DQS PI = 26
2396 08:06:10.965051 [0] AVG Duty = 4984%(X100)
2397 08:06:10.965132
2398 08:06:10.968517 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2399 08:06:10.968599
2400 08:06:10.971816 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2401 08:06:10.975252 [DutyScan_Calibration_Flow] ====Done====
2402 08:06:10.975335
2403 08:06:10.978277 [DutyScan_Calibration_Flow] k_type=3
2404 08:06:10.994827
2405 08:06:10.994909 ==DQM 0 ==
2406 08:06:10.998452 Final DQM duty delay cell = 0
2407 08:06:11.001494 [0] MAX Duty = 5031%(X100), DQS PI = 24
2408 08:06:11.004953 [0] MIN Duty = 4876%(X100), DQS PI = 4
2409 08:06:11.005035 [0] AVG Duty = 4953%(X100)
2410 08:06:11.008177
2411 08:06:11.008259 ==DQM 1 ==
2412 08:06:11.011733 Final DQM duty delay cell = 0
2413 08:06:11.014947 [0] MAX Duty = 5031%(X100), DQS PI = 20
2414 08:06:11.018319 [0] MIN Duty = 4907%(X100), DQS PI = 4
2415 08:06:11.018401 [0] AVG Duty = 4969%(X100)
2416 08:06:11.021508
2417 08:06:11.024984 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2418 08:06:11.025067
2419 08:06:11.028293 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2420 08:06:11.031929 [DutyScan_Calibration_Flow] ====Done====
2421 08:06:11.032011
2422 08:06:11.035165 [DutyScan_Calibration_Flow] k_type=2
2423 08:06:11.051607
2424 08:06:11.051690 ==DQ 0 ==
2425 08:06:11.054836 Final DQ duty delay cell = 0
2426 08:06:11.058263 [0] MAX Duty = 5062%(X100), DQS PI = 12
2427 08:06:11.061343 [0] MIN Duty = 4938%(X100), DQS PI = 56
2428 08:06:11.061426 [0] AVG Duty = 5000%(X100)
2429 08:06:11.064564
2430 08:06:11.064646 ==DQ 1 ==
2431 08:06:11.068565 Final DQ duty delay cell = 0
2432 08:06:11.071428 [0] MAX Duty = 5125%(X100), DQS PI = 46
2433 08:06:11.074940 [0] MIN Duty = 4969%(X100), DQS PI = 26
2434 08:06:11.075053 [0] AVG Duty = 5047%(X100)
2435 08:06:11.075118
2436 08:06:11.078073 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2437 08:06:11.078157
2438 08:06:11.084653 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2439 08:06:11.088203 [DutyScan_Calibration_Flow] ====Done====
2440 08:06:11.091305 nWR fixed to 30
2441 08:06:11.091450 [ModeRegInit_LP4] CH0 RK0
2442 08:06:11.094677 [ModeRegInit_LP4] CH0 RK1
2443 08:06:11.097889 [ModeRegInit_LP4] CH1 RK0
2444 08:06:11.101286 [ModeRegInit_LP4] CH1 RK1
2445 08:06:11.101386 match AC timing 7
2446 08:06:11.104694 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2447 08:06:11.111062 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2448 08:06:11.114591 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2449 08:06:11.118051 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2450 08:06:11.124727 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2451 08:06:11.124802 ==
2452 08:06:11.127668 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 08:06:11.131227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 08:06:11.131340 ==
2455 08:06:11.137474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2456 08:06:11.144729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2457 08:06:11.151369 [CA 0] Center 40 (10~71) winsize 62
2458 08:06:11.154560 [CA 1] Center 39 (9~70) winsize 62
2459 08:06:11.157977 [CA 2] Center 36 (6~66) winsize 61
2460 08:06:11.161896 [CA 3] Center 35 (5~66) winsize 62
2461 08:06:11.164819 [CA 4] Center 34 (4~65) winsize 62
2462 08:06:11.168274 [CA 5] Center 33 (3~63) winsize 61
2463 08:06:11.168354
2464 08:06:11.171545 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2465 08:06:11.171653
2466 08:06:11.174565 [CATrainingPosCal] consider 1 rank data
2467 08:06:11.177969 u2DelayCellTimex100 = 270/100 ps
2468 08:06:11.181095 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2469 08:06:11.187669 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2470 08:06:11.191133 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2471 08:06:11.194787 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2472 08:06:11.198047 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2473 08:06:11.201208 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2474 08:06:11.201318
2475 08:06:11.204623 CA PerBit enable=1, Macro0, CA PI delay=33
2476 08:06:11.204706
2477 08:06:11.208040 [CBTSetCACLKResult] CA Dly = 33
2478 08:06:11.211737 CS Dly: 7 (0~38)
2479 08:06:11.211812 ==
2480 08:06:11.214275 Dram Type= 6, Freq= 0, CH_0, rank 1
2481 08:06:11.217948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 08:06:11.218055 ==
2483 08:06:11.224159 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 08:06:11.227703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2485 08:06:11.237416 [CA 0] Center 40 (10~70) winsize 61
2486 08:06:11.240597 [CA 1] Center 39 (9~70) winsize 62
2487 08:06:11.244667 [CA 2] Center 35 (5~66) winsize 62
2488 08:06:11.247502 [CA 3] Center 35 (5~66) winsize 62
2489 08:06:11.250506 [CA 4] Center 34 (4~65) winsize 62
2490 08:06:11.254149 [CA 5] Center 33 (3~63) winsize 61
2491 08:06:11.254260
2492 08:06:11.257659 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2493 08:06:11.257736
2494 08:06:11.260945 [CATrainingPosCal] consider 2 rank data
2495 08:06:11.264419 u2DelayCellTimex100 = 270/100 ps
2496 08:06:11.267305 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2497 08:06:11.273824 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2498 08:06:11.277315 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2499 08:06:11.280669 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 08:06:11.283993 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2501 08:06:11.287396 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2502 08:06:11.287484
2503 08:06:11.290641 CA PerBit enable=1, Macro0, CA PI delay=33
2504 08:06:11.290738
2505 08:06:11.294105 [CBTSetCACLKResult] CA Dly = 33
2506 08:06:11.294198 CS Dly: 8 (0~40)
2507 08:06:11.297404
2508 08:06:11.300891 ----->DramcWriteLeveling(PI) begin...
2509 08:06:11.300991 ==
2510 08:06:11.304250 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 08:06:11.307344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 08:06:11.307455 ==
2513 08:06:11.310759 Write leveling (Byte 0): 34 => 34
2514 08:06:11.314200 Write leveling (Byte 1): 30 => 30
2515 08:06:11.317520 DramcWriteLeveling(PI) end<-----
2516 08:06:11.317621
2517 08:06:11.317710 ==
2518 08:06:11.320772 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 08:06:11.324350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 08:06:11.324423 ==
2521 08:06:11.327744 [Gating] SW mode calibration
2522 08:06:11.334381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2523 08:06:11.340870 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2524 08:06:11.344015 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 08:06:11.347563 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
2526 08:06:11.350673 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 08:06:11.357384 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 08:06:11.360615 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 08:06:11.364028 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 08:06:11.370678 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 08:06:11.374088 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2532 08:06:11.377753 1 0 0 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 1)
2533 08:06:11.383857 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2534 08:06:11.387296 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 08:06:11.390601 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 08:06:11.397560 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 08:06:11.401188 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 08:06:11.404512 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 08:06:11.410984 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2540 08:06:11.414204 1 1 0 | B1->B0 | 2a2a 3535 | 0 0 | (0 0) (1 1)
2541 08:06:11.417710 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
2542 08:06:11.424042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 08:06:11.427632 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 08:06:11.430888 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 08:06:11.434148 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 08:06:11.440748 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 08:06:11.444049 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 08:06:11.447767 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 08:06:11.454060 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 08:06:11.457438 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 08:06:11.461007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 08:06:11.467717 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 08:06:11.470885 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 08:06:11.474351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 08:06:11.481514 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 08:06:11.484774 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 08:06:11.487916 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 08:06:11.494707 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 08:06:11.497490 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 08:06:11.501286 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 08:06:11.507856 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 08:06:11.511288 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 08:06:11.514534 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 08:06:11.517631 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 08:06:11.521110 Total UI for P1: 0, mck2ui 16
2566 08:06:11.524212 best dqsien dly found for B0: ( 1, 3, 28)
2567 08:06:11.531601 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2568 08:06:11.534310 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 08:06:11.538304 Total UI for P1: 0, mck2ui 16
2570 08:06:11.540947 best dqsien dly found for B1: ( 1, 4, 2)
2571 08:06:11.544515 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2572 08:06:11.547757 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2573 08:06:11.547840
2574 08:06:11.551046 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2575 08:06:11.554504 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2576 08:06:11.557626 [Gating] SW calibration Done
2577 08:06:11.557709 ==
2578 08:06:11.561404 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 08:06:11.564229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 08:06:11.567644 ==
2581 08:06:11.567727 RX Vref Scan: 0
2582 08:06:11.567792
2583 08:06:11.571001 RX Vref 0 -> 0, step: 1
2584 08:06:11.571083
2585 08:06:11.574279 RX Delay -40 -> 252, step: 8
2586 08:06:11.577613 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2587 08:06:11.581123 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2588 08:06:11.584739 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2589 08:06:11.588182 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2590 08:06:11.594819 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2591 08:06:11.598295 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2592 08:06:11.601139 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2593 08:06:11.604514 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2594 08:06:11.608265 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2595 08:06:11.611221 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2596 08:06:11.617798 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2597 08:06:11.621185 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2598 08:06:11.624658 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2599 08:06:11.627743 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2600 08:06:11.631085 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2601 08:06:11.637516 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2602 08:06:11.637598 ==
2603 08:06:11.641071 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 08:06:11.644499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 08:06:11.644582 ==
2606 08:06:11.644648 DQS Delay:
2607 08:06:11.647949 DQS0 = 0, DQS1 = 0
2608 08:06:11.648031 DQM Delay:
2609 08:06:11.651368 DQM0 = 112, DQM1 = 103
2610 08:06:11.651489 DQ Delay:
2611 08:06:11.654208 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2612 08:06:11.658049 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2613 08:06:11.661019 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2614 08:06:11.664495 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2615 08:06:11.664578
2616 08:06:11.664643
2617 08:06:11.664703 ==
2618 08:06:11.667598 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 08:06:11.674352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 08:06:11.674436 ==
2621 08:06:11.674501
2622 08:06:11.674562
2623 08:06:11.674620 TX Vref Scan disable
2624 08:06:11.678316 == TX Byte 0 ==
2625 08:06:11.681576 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2626 08:06:11.684549 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2627 08:06:11.688069 == TX Byte 1 ==
2628 08:06:11.691452 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2629 08:06:11.696789 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2630 08:06:11.698298 ==
2631 08:06:11.701248 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 08:06:11.704523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 08:06:11.704608 ==
2634 08:06:11.716345 TX Vref=22, minBit 0, minWin=25, winSum=412
2635 08:06:11.719704 TX Vref=24, minBit 1, minWin=26, winSum=421
2636 08:06:11.723220 TX Vref=26, minBit 5, minWin=26, winSum=428
2637 08:06:11.726082 TX Vref=28, minBit 2, minWin=26, winSum=432
2638 08:06:11.729368 TX Vref=30, minBit 2, minWin=26, winSum=430
2639 08:06:11.736314 TX Vref=32, minBit 10, minWin=25, winSum=425
2640 08:06:11.739574 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 28
2641 08:06:11.739679
2642 08:06:11.742957 Final TX Range 1 Vref 28
2643 08:06:11.743061
2644 08:06:11.743156 ==
2645 08:06:11.746134 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 08:06:11.749754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 08:06:11.749861 ==
2648 08:06:11.753233
2649 08:06:11.753331
2650 08:06:11.753432 TX Vref Scan disable
2651 08:06:11.756100 == TX Byte 0 ==
2652 08:06:11.759737 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2653 08:06:11.762984 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2654 08:06:11.766543 == TX Byte 1 ==
2655 08:06:11.769690 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2656 08:06:11.773108 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2657 08:06:11.773212
2658 08:06:11.776014 [DATLAT]
2659 08:06:11.776101 Freq=1200, CH0 RK0
2660 08:06:11.776192
2661 08:06:11.779448 DATLAT Default: 0xd
2662 08:06:11.779552 0, 0xFFFF, sum = 0
2663 08:06:11.783002 1, 0xFFFF, sum = 0
2664 08:06:11.783114 2, 0xFFFF, sum = 0
2665 08:06:11.786244 3, 0xFFFF, sum = 0
2666 08:06:11.786355 4, 0xFFFF, sum = 0
2667 08:06:11.789478 5, 0xFFFF, sum = 0
2668 08:06:11.789579 6, 0xFFFF, sum = 0
2669 08:06:11.792858 7, 0xFFFF, sum = 0
2670 08:06:11.796165 8, 0xFFFF, sum = 0
2671 08:06:11.796270 9, 0xFFFF, sum = 0
2672 08:06:11.799806 10, 0xFFFF, sum = 0
2673 08:06:11.799910 11, 0xFFFF, sum = 0
2674 08:06:11.803347 12, 0x0, sum = 1
2675 08:06:11.803470 13, 0x0, sum = 2
2676 08:06:11.806490 14, 0x0, sum = 3
2677 08:06:11.806600 15, 0x0, sum = 4
2678 08:06:11.806695 best_step = 13
2679 08:06:11.806792
2680 08:06:11.809482 ==
2681 08:06:11.809581 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 08:06:11.816199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 08:06:11.816310 ==
2684 08:06:11.816407 RX Vref Scan: 1
2685 08:06:11.816495
2686 08:06:11.819652 Set Vref Range= 32 -> 127
2687 08:06:11.819744
2688 08:06:11.823145 RX Vref 32 -> 127, step: 1
2689 08:06:11.823245
2690 08:06:11.826138 RX Delay -37 -> 252, step: 4
2691 08:06:11.826238
2692 08:06:11.829524 Set Vref, RX VrefLevel [Byte0]: 32
2693 08:06:11.833155 [Byte1]: 32
2694 08:06:11.833263
2695 08:06:11.836274 Set Vref, RX VrefLevel [Byte0]: 33
2696 08:06:11.840212 [Byte1]: 33
2697 08:06:11.840317
2698 08:06:11.842898 Set Vref, RX VrefLevel [Byte0]: 34
2699 08:06:11.846545 [Byte1]: 34
2700 08:06:11.850701
2701 08:06:11.850801 Set Vref, RX VrefLevel [Byte0]: 35
2702 08:06:11.854129 [Byte1]: 35
2703 08:06:11.858677
2704 08:06:11.858781 Set Vref, RX VrefLevel [Byte0]: 36
2705 08:06:11.861805 [Byte1]: 36
2706 08:06:11.866694
2707 08:06:11.866796 Set Vref, RX VrefLevel [Byte0]: 37
2708 08:06:11.869970 [Byte1]: 37
2709 08:06:11.874447
2710 08:06:11.874549 Set Vref, RX VrefLevel [Byte0]: 38
2711 08:06:11.877778 [Byte1]: 38
2712 08:06:11.882500
2713 08:06:11.882599 Set Vref, RX VrefLevel [Byte0]: 39
2714 08:06:11.886071 [Byte1]: 39
2715 08:06:11.890537
2716 08:06:11.890636 Set Vref, RX VrefLevel [Byte0]: 40
2717 08:06:11.894182 [Byte1]: 40
2718 08:06:11.898718
2719 08:06:11.898820 Set Vref, RX VrefLevel [Byte0]: 41
2720 08:06:11.901946 [Byte1]: 41
2721 08:06:11.906654
2722 08:06:11.906756 Set Vref, RX VrefLevel [Byte0]: 42
2723 08:06:11.909967 [Byte1]: 42
2724 08:06:11.914486
2725 08:06:11.914588 Set Vref, RX VrefLevel [Byte0]: 43
2726 08:06:11.918178 [Byte1]: 43
2727 08:06:11.922985
2728 08:06:11.923091 Set Vref, RX VrefLevel [Byte0]: 44
2729 08:06:11.926047 [Byte1]: 44
2730 08:06:11.930459
2731 08:06:11.930559 Set Vref, RX VrefLevel [Byte0]: 45
2732 08:06:11.934316 [Byte1]: 45
2733 08:06:11.938688
2734 08:06:11.938786 Set Vref, RX VrefLevel [Byte0]: 46
2735 08:06:11.941809 [Byte1]: 46
2736 08:06:11.946524
2737 08:06:11.946622 Set Vref, RX VrefLevel [Byte0]: 47
2738 08:06:11.949913 [Byte1]: 47
2739 08:06:11.955060
2740 08:06:11.955160 Set Vref, RX VrefLevel [Byte0]: 48
2741 08:06:11.957745 [Byte1]: 48
2742 08:06:11.962720
2743 08:06:11.962818 Set Vref, RX VrefLevel [Byte0]: 49
2744 08:06:11.965766 [Byte1]: 49
2745 08:06:11.970509
2746 08:06:11.970602 Set Vref, RX VrefLevel [Byte0]: 50
2747 08:06:11.973889 [Byte1]: 50
2748 08:06:11.979013
2749 08:06:11.979112 Set Vref, RX VrefLevel [Byte0]: 51
2750 08:06:11.982017 [Byte1]: 51
2751 08:06:11.986800
2752 08:06:11.986901 Set Vref, RX VrefLevel [Byte0]: 52
2753 08:06:11.990385 [Byte1]: 52
2754 08:06:11.994747
2755 08:06:11.994845 Set Vref, RX VrefLevel [Byte0]: 53
2756 08:06:11.997772 [Byte1]: 53
2757 08:06:12.002681
2758 08:06:12.002755 Set Vref, RX VrefLevel [Byte0]: 54
2759 08:06:12.005815 [Byte1]: 54
2760 08:06:12.010649
2761 08:06:12.010751 Set Vref, RX VrefLevel [Byte0]: 55
2762 08:06:12.014073 [Byte1]: 55
2763 08:06:12.018536
2764 08:06:12.018654 Set Vref, RX VrefLevel [Byte0]: 56
2765 08:06:12.021878 [Byte1]: 56
2766 08:06:12.026847
2767 08:06:12.026957 Set Vref, RX VrefLevel [Byte0]: 57
2768 08:06:12.029723 [Byte1]: 57
2769 08:06:12.034407
2770 08:06:12.034511 Set Vref, RX VrefLevel [Byte0]: 58
2771 08:06:12.038255 [Byte1]: 58
2772 08:06:12.042814
2773 08:06:12.042933 Set Vref, RX VrefLevel [Byte0]: 59
2774 08:06:12.046194 [Byte1]: 59
2775 08:06:12.050559
2776 08:06:12.050633 Set Vref, RX VrefLevel [Byte0]: 60
2777 08:06:12.054254 [Byte1]: 60
2778 08:06:12.059055
2779 08:06:12.059173 Set Vref, RX VrefLevel [Byte0]: 61
2780 08:06:12.062190 [Byte1]: 61
2781 08:06:12.066631
2782 08:06:12.066741 Set Vref, RX VrefLevel [Byte0]: 62
2783 08:06:12.069742 [Byte1]: 62
2784 08:06:12.074621
2785 08:06:12.074730 Set Vref, RX VrefLevel [Byte0]: 63
2786 08:06:12.078069 [Byte1]: 63
2787 08:06:12.082408
2788 08:06:12.082510 Set Vref, RX VrefLevel [Byte0]: 64
2789 08:06:12.086017 [Byte1]: 64
2790 08:06:12.091124
2791 08:06:12.091230 Set Vref, RX VrefLevel [Byte0]: 65
2792 08:06:12.094086 [Byte1]: 65
2793 08:06:12.098478
2794 08:06:12.098579 Set Vref, RX VrefLevel [Byte0]: 66
2795 08:06:12.101764 [Byte1]: 66
2796 08:06:12.106680
2797 08:06:12.106781 Set Vref, RX VrefLevel [Byte0]: 67
2798 08:06:12.109911 [Byte1]: 67
2799 08:06:12.114526
2800 08:06:12.114625 Set Vref, RX VrefLevel [Byte0]: 68
2801 08:06:12.117916 [Byte1]: 68
2802 08:06:12.122540
2803 08:06:12.122647 Set Vref, RX VrefLevel [Byte0]: 69
2804 08:06:12.125948 [Byte1]: 69
2805 08:06:12.130877
2806 08:06:12.130981 Set Vref, RX VrefLevel [Byte0]: 70
2807 08:06:12.134382 [Byte1]: 70
2808 08:06:12.139121
2809 08:06:12.139282 Set Vref, RX VrefLevel [Byte0]: 71
2810 08:06:12.142150 [Byte1]: 71
2811 08:06:12.146770
2812 08:06:12.146881 Set Vref, RX VrefLevel [Byte0]: 72
2813 08:06:12.150079 [Byte1]: 72
2814 08:06:12.154728
2815 08:06:12.154829 Set Vref, RX VrefLevel [Byte0]: 73
2816 08:06:12.158045 [Byte1]: 73
2817 08:06:12.162417
2818 08:06:12.162517 Set Vref, RX VrefLevel [Byte0]: 74
2819 08:06:12.166124 [Byte1]: 74
2820 08:06:12.170803
2821 08:06:12.170913 Final RX Vref Byte 0 = 62 to rank0
2822 08:06:12.174153 Final RX Vref Byte 1 = 48 to rank0
2823 08:06:12.177650 Final RX Vref Byte 0 = 62 to rank1
2824 08:06:12.180554 Final RX Vref Byte 1 = 48 to rank1==
2825 08:06:12.184191 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 08:06:12.187225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 08:06:12.190596 ==
2828 08:06:12.190696 DQS Delay:
2829 08:06:12.190795 DQS0 = 0, DQS1 = 0
2830 08:06:12.194380 DQM Delay:
2831 08:06:12.194482 DQM0 = 112, DQM1 = 100
2832 08:06:12.197285 DQ Delay:
2833 08:06:12.200610 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2834 08:06:12.204034 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2835 08:06:12.207603 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =92
2836 08:06:12.210857 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =108
2837 08:06:12.210958
2838 08:06:12.211049
2839 08:06:12.217381 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2840 08:06:12.220684 CH0 RK0: MR19=303, MR18=FBFB
2841 08:06:12.227485 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2842 08:06:12.227621
2843 08:06:12.230579 ----->DramcWriteLeveling(PI) begin...
2844 08:06:12.230681 ==
2845 08:06:12.233945 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 08:06:12.237553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 08:06:12.237653 ==
2848 08:06:12.240644 Write leveling (Byte 0): 32 => 32
2849 08:06:12.243844 Write leveling (Byte 1): 29 => 29
2850 08:06:12.247231 DramcWriteLeveling(PI) end<-----
2851 08:06:12.247340
2852 08:06:12.247462 ==
2853 08:06:12.250492 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 08:06:12.257227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 08:06:12.257342 ==
2856 08:06:12.257436 [Gating] SW mode calibration
2857 08:06:12.267376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 08:06:12.270516 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 08:06:12.274424 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2860 08:06:12.280948 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 08:06:12.283836 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 08:06:12.287316 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 08:06:12.294341 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 08:06:12.297346 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 08:06:12.300476 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2866 08:06:12.307677 0 15 28 | B1->B0 | 3434 2323 | 0 1 | (0 0) (1 0)
2867 08:06:12.311101 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 08:06:12.314301 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 08:06:12.320690 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 08:06:12.323767 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 08:06:12.327375 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 08:06:12.334260 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 08:06:12.337146 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2874 08:06:12.340376 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2875 08:06:12.347216 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2876 08:06:12.350526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 08:06:12.353720 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 08:06:12.360526 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 08:06:12.363673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 08:06:12.367011 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 08:06:12.370730 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 08:06:12.377305 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 08:06:12.380462 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 08:06:12.383582 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 08:06:12.390245 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 08:06:12.393907 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 08:06:12.396998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 08:06:12.403905 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 08:06:12.407275 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 08:06:12.410703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 08:06:12.417287 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 08:06:12.420334 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 08:06:12.423638 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 08:06:12.430662 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 08:06:12.434144 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 08:06:12.437413 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 08:06:12.443617 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 08:06:12.447049 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 08:06:12.450602 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 08:06:12.453874 Total UI for P1: 0, mck2ui 16
2901 08:06:12.457281 best dqsien dly found for B0: ( 1, 3, 28)
2902 08:06:12.460566 Total UI for P1: 0, mck2ui 16
2903 08:06:12.463810 best dqsien dly found for B1: ( 1, 3, 30)
2904 08:06:12.466985 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2905 08:06:12.470688 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2906 08:06:12.470777
2907 08:06:12.474133 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2908 08:06:12.477382 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2909 08:06:12.480599 [Gating] SW calibration Done
2910 08:06:12.480736 ==
2911 08:06:12.483791 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 08:06:12.490385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 08:06:12.490491 ==
2914 08:06:12.490584 RX Vref Scan: 0
2915 08:06:12.490675
2916 08:06:12.494020 RX Vref 0 -> 0, step: 1
2917 08:06:12.494119
2918 08:06:12.497441 RX Delay -40 -> 252, step: 8
2919 08:06:12.500586 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2920 08:06:12.504073 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2921 08:06:12.507300 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2922 08:06:12.510489 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2923 08:06:12.517213 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2924 08:06:12.520800 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2925 08:06:12.524141 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2926 08:06:12.527747 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 08:06:12.530246 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2928 08:06:12.534269 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2929 08:06:12.540578 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2930 08:06:12.544146 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2931 08:06:12.547098 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2932 08:06:12.551084 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2933 08:06:12.557214 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2934 08:06:12.560871 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2935 08:06:12.560948 ==
2936 08:06:12.564207 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 08:06:12.567319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 08:06:12.567444 ==
2939 08:06:12.567539 DQS Delay:
2940 08:06:12.570883 DQS0 = 0, DQS1 = 0
2941 08:06:12.570965 DQM Delay:
2942 08:06:12.573943 DQM0 = 111, DQM1 = 100
2943 08:06:12.574045 DQ Delay:
2944 08:06:12.577174 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2945 08:06:12.580662 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2946 08:06:12.584022 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2947 08:06:12.587110 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =107
2948 08:06:12.587199
2949 08:06:12.587299
2950 08:06:12.590682 ==
2951 08:06:12.593905 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 08:06:12.597593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 08:06:12.597699 ==
2954 08:06:12.597822
2955 08:06:12.597936
2956 08:06:12.600591 TX Vref Scan disable
2957 08:06:12.600707 == TX Byte 0 ==
2958 08:06:12.604169 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2959 08:06:12.610394 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2960 08:06:12.610475 == TX Byte 1 ==
2961 08:06:12.613792 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2962 08:06:12.620283 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2963 08:06:12.620368 ==
2964 08:06:12.623834 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 08:06:12.627133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 08:06:12.627236 ==
2967 08:06:12.640257 TX Vref=22, minBit 1, minWin=26, winSum=429
2968 08:06:12.642695 TX Vref=24, minBit 1, minWin=26, winSum=435
2969 08:06:12.646334 TX Vref=26, minBit 1, minWin=26, winSum=436
2970 08:06:12.649478 TX Vref=28, minBit 8, minWin=26, winSum=440
2971 08:06:12.653190 TX Vref=30, minBit 8, minWin=26, winSum=441
2972 08:06:12.656400 TX Vref=32, minBit 13, minWin=26, winSum=440
2973 08:06:12.662868 [TxChooseVref] Worse bit 8, Min win 26, Win sum 441, Final Vref 30
2974 08:06:12.662980
2975 08:06:12.666306 Final TX Range 1 Vref 30
2976 08:06:12.666410
2977 08:06:12.666515 ==
2978 08:06:12.669567 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 08:06:12.672962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 08:06:12.673052 ==
2981 08:06:12.673149
2982 08:06:12.673242
2983 08:06:12.676052 TX Vref Scan disable
2984 08:06:12.679398 == TX Byte 0 ==
2985 08:06:12.682753 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2986 08:06:12.686200 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2987 08:06:12.689449 == TX Byte 1 ==
2988 08:06:12.692754 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2989 08:06:12.696325 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2990 08:06:12.696408
2991 08:06:12.699735 [DATLAT]
2992 08:06:12.699839 Freq=1200, CH0 RK1
2993 08:06:12.699937
2994 08:06:12.702715 DATLAT Default: 0xd
2995 08:06:12.702813 0, 0xFFFF, sum = 0
2996 08:06:12.706036 1, 0xFFFF, sum = 0
2997 08:06:12.706139 2, 0xFFFF, sum = 0
2998 08:06:12.709693 3, 0xFFFF, sum = 0
2999 08:06:12.709796 4, 0xFFFF, sum = 0
3000 08:06:12.713170 5, 0xFFFF, sum = 0
3001 08:06:12.713271 6, 0xFFFF, sum = 0
3002 08:06:12.716527 7, 0xFFFF, sum = 0
3003 08:06:12.716631 8, 0xFFFF, sum = 0
3004 08:06:12.720040 9, 0xFFFF, sum = 0
3005 08:06:12.720117 10, 0xFFFF, sum = 0
3006 08:06:12.722938 11, 0xFFFF, sum = 0
3007 08:06:12.723038 12, 0x0, sum = 1
3008 08:06:12.726211 13, 0x0, sum = 2
3009 08:06:12.726312 14, 0x0, sum = 3
3010 08:06:12.729977 15, 0x0, sum = 4
3011 08:06:12.730083 best_step = 13
3012 08:06:12.730173
3013 08:06:12.730272 ==
3014 08:06:12.732710 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 08:06:12.739851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 08:06:12.739942 ==
3017 08:06:12.740031 RX Vref Scan: 0
3018 08:06:12.740129
3019 08:06:12.742996 RX Vref 0 -> 0, step: 1
3020 08:06:12.743114
3021 08:06:12.746436 RX Delay -37 -> 252, step: 4
3022 08:06:12.749358 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3023 08:06:12.753174 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3024 08:06:12.759950 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3025 08:06:12.762644 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3026 08:06:12.766124 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3027 08:06:12.769843 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3028 08:06:12.772805 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3029 08:06:12.779654 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3030 08:06:12.782820 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3031 08:06:12.786301 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3032 08:06:12.789812 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3033 08:06:12.793114 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3034 08:06:12.799588 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3035 08:06:12.802794 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3036 08:06:12.806234 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3037 08:06:12.809290 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3038 08:06:12.809394 ==
3039 08:06:12.812823 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 08:06:12.819521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 08:06:12.819600 ==
3042 08:06:12.819664 DQS Delay:
3043 08:06:12.819730 DQS0 = 0, DQS1 = 0
3044 08:06:12.822543 DQM Delay:
3045 08:06:12.822640 DQM0 = 111, DQM1 = 99
3046 08:06:12.825858 DQ Delay:
3047 08:06:12.829330 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3048 08:06:12.832562 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3049 08:06:12.836201 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
3050 08:06:12.839300 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3051 08:06:12.839423
3052 08:06:12.839527
3053 08:06:12.845890 [DQSOSCAuto] RK1, (LSB)MR18= 0x16fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3054 08:06:12.849169 CH0 RK1: MR19=403, MR18=16FD
3055 08:06:12.856046 CH0_RK1: MR19=0x403, MR18=0x16FD, DQSOSC=401, MR23=63, INC=40, DEC=27
3056 08:06:12.859533 [RxdqsGatingPostProcess] freq 1200
3057 08:06:12.865956 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 08:06:12.869381 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 08:06:12.869483 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 08:06:12.872721 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 08:06:12.876333 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 08:06:12.879774 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 08:06:12.883148 best DQS1 dly(2T, 0.5T) = (0, 11)
3064 08:06:12.886636 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 08:06:12.889120 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3066 08:06:12.892556 Pre-setting of DQS Precalculation
3067 08:06:12.899282 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 08:06:12.899382 ==
3069 08:06:12.902492 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 08:06:12.905812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 08:06:12.905912 ==
3072 08:06:12.912616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 08:06:12.916226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 08:06:12.925252 [CA 0] Center 37 (8~67) winsize 60
3075 08:06:12.928667 [CA 1] Center 37 (7~68) winsize 62
3076 08:06:12.932247 [CA 2] Center 34 (4~64) winsize 61
3077 08:06:12.935501 [CA 3] Center 33 (3~64) winsize 62
3078 08:06:12.938772 [CA 4] Center 34 (4~64) winsize 61
3079 08:06:12.942759 [CA 5] Center 33 (3~63) winsize 61
3080 08:06:12.942861
3081 08:06:12.945462 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3082 08:06:12.945574
3083 08:06:12.948760 [CATrainingPosCal] consider 1 rank data
3084 08:06:12.952235 u2DelayCellTimex100 = 270/100 ps
3085 08:06:12.955532 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3086 08:06:12.959086 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 08:06:12.965832 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 08:06:12.968706 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 08:06:12.972296 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 08:06:12.975719 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3091 08:06:12.975797
3092 08:06:12.979397 CA PerBit enable=1, Macro0, CA PI delay=33
3093 08:06:12.979488
3094 08:06:12.982114 [CBTSetCACLKResult] CA Dly = 33
3095 08:06:12.982212 CS Dly: 5 (0~36)
3096 08:06:12.982311 ==
3097 08:06:12.985431 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 08:06:12.992187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 08:06:12.992291 ==
3100 08:06:12.995456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 08:06:13.001918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3102 08:06:13.011279 [CA 0] Center 37 (7~67) winsize 61
3103 08:06:13.014632 [CA 1] Center 37 (7~68) winsize 62
3104 08:06:13.018051 [CA 2] Center 34 (4~65) winsize 62
3105 08:06:13.020836 [CA 3] Center 33 (3~64) winsize 62
3106 08:06:13.024631 [CA 4] Center 34 (4~65) winsize 62
3107 08:06:13.028034 [CA 5] Center 33 (3~63) winsize 61
3108 08:06:13.028109
3109 08:06:13.030990 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3110 08:06:13.031090
3111 08:06:13.034543 [CATrainingPosCal] consider 2 rank data
3112 08:06:13.038091 u2DelayCellTimex100 = 270/100 ps
3113 08:06:13.041055 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3114 08:06:13.044878 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3115 08:06:13.048198 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 08:06:13.054521 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3117 08:06:13.057767 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 08:06:13.061215 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3119 08:06:13.061320
3120 08:06:13.064705 CA PerBit enable=1, Macro0, CA PI delay=33
3121 08:06:13.064784
3122 08:06:13.067774 [CBTSetCACLKResult] CA Dly = 33
3123 08:06:13.067877 CS Dly: 6 (0~39)
3124 08:06:13.067967
3125 08:06:13.071118 ----->DramcWriteLeveling(PI) begin...
3126 08:06:13.071276 ==
3127 08:06:13.074679 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 08:06:13.081263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 08:06:13.081342 ==
3130 08:06:13.084937 Write leveling (Byte 0): 25 => 25
3131 08:06:13.087915 Write leveling (Byte 1): 27 => 27
3132 08:06:13.087992 DramcWriteLeveling(PI) end<-----
3133 08:06:13.088060
3134 08:06:13.091470 ==
3135 08:06:13.094808 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 08:06:13.098690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 08:06:13.098792 ==
3138 08:06:13.101278 [Gating] SW mode calibration
3139 08:06:13.108365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 08:06:13.111966 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 08:06:13.118027 0 15 0 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
3142 08:06:13.121476 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 08:06:13.124872 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 08:06:13.131485 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 08:06:13.135117 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 08:06:13.138209 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 08:06:13.144649 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 08:06:13.147818 0 15 28 | B1->B0 | 2c2c 2d2d | 0 0 | (0 0) (0 0)
3149 08:06:13.151275 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3150 08:06:13.154610 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 08:06:13.161798 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 08:06:13.164584 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 08:06:13.168108 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 08:06:13.174717 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 08:06:13.178172 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3156 08:06:13.181474 1 0 28 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (0 0)
3157 08:06:13.188250 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 08:06:13.191310 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 08:06:13.194759 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 08:06:13.201746 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 08:06:13.205145 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 08:06:13.208387 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 08:06:13.215237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 08:06:13.218064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 08:06:13.221548 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3166 08:06:13.228569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 08:06:13.231740 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 08:06:13.234952 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 08:06:13.241465 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 08:06:13.244779 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 08:06:13.248211 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 08:06:13.251996 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 08:06:13.258206 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 08:06:13.261626 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 08:06:13.264777 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 08:06:13.271699 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 08:06:13.275132 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 08:06:13.278110 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 08:06:13.285096 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 08:06:13.288518 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3181 08:06:13.291558 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3182 08:06:13.294933 Total UI for P1: 0, mck2ui 16
3183 08:06:13.298127 best dqsien dly found for B0: ( 1, 3, 28)
3184 08:06:13.304857 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 08:06:13.304939 Total UI for P1: 0, mck2ui 16
3186 08:06:13.308039 best dqsien dly found for B1: ( 1, 3, 30)
3187 08:06:13.315094 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3188 08:06:13.318590 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3189 08:06:13.318692
3190 08:06:13.322360 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3191 08:06:13.325460 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3192 08:06:13.328288 [Gating] SW calibration Done
3193 08:06:13.328393 ==
3194 08:06:13.331450 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 08:06:13.334955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 08:06:13.335035 ==
3197 08:06:13.338381 RX Vref Scan: 0
3198 08:06:13.338451
3199 08:06:13.338513 RX Vref 0 -> 0, step: 1
3200 08:06:13.338578
3201 08:06:13.341858 RX Delay -40 -> 252, step: 8
3202 08:06:13.345216 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3203 08:06:13.348753 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3204 08:06:13.355489 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3205 08:06:13.358289 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3206 08:06:13.361963 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3207 08:06:13.365094 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3208 08:06:13.368358 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3209 08:06:13.374785 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3210 08:06:13.378229 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3211 08:06:13.381742 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3212 08:06:13.384888 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3213 08:06:13.388228 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3214 08:06:13.395000 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3215 08:06:13.398152 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3216 08:06:13.401893 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3217 08:06:13.404828 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3218 08:06:13.404929 ==
3219 08:06:13.408232 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 08:06:13.415128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 08:06:13.415232 ==
3222 08:06:13.415323 DQS Delay:
3223 08:06:13.415448 DQS0 = 0, DQS1 = 0
3224 08:06:13.418460 DQM Delay:
3225 08:06:13.418533 DQM0 = 113, DQM1 = 105
3226 08:06:13.421843 DQ Delay:
3227 08:06:13.424781 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3228 08:06:13.428738 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3229 08:06:13.432188 DQ8 =99, DQ9 =95, DQ10 =103, DQ11 =99
3230 08:06:13.435263 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3231 08:06:13.435360
3232 08:06:13.435486
3233 08:06:13.435576 ==
3234 08:06:13.438608 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 08:06:13.441945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 08:06:13.442044 ==
3237 08:06:13.442136
3238 08:06:13.442228
3239 08:06:13.445421 TX Vref Scan disable
3240 08:06:13.448998 == TX Byte 0 ==
3241 08:06:13.451711 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3242 08:06:13.455147 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3243 08:06:13.458425 == TX Byte 1 ==
3244 08:06:13.461820 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3245 08:06:13.465067 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3246 08:06:13.465160 ==
3247 08:06:13.468713 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 08:06:13.471985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 08:06:13.475027 ==
3250 08:06:13.485173 TX Vref=22, minBit 10, minWin=24, winSum=407
3251 08:06:13.488536 TX Vref=24, minBit 10, minWin=24, winSum=410
3252 08:06:13.491859 TX Vref=26, minBit 8, minWin=25, winSum=417
3253 08:06:13.495482 TX Vref=28, minBit 10, minWin=25, winSum=418
3254 08:06:13.498629 TX Vref=30, minBit 9, minWin=24, winSum=419
3255 08:06:13.505563 TX Vref=32, minBit 9, minWin=24, winSum=419
3256 08:06:13.508637 [TxChooseVref] Worse bit 10, Min win 25, Win sum 418, Final Vref 28
3257 08:06:13.508714
3258 08:06:13.511799 Final TX Range 1 Vref 28
3259 08:06:13.511868
3260 08:06:13.511935 ==
3261 08:06:13.515639 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 08:06:13.518757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 08:06:13.518859 ==
3264 08:06:13.521834
3265 08:06:13.521902
3266 08:06:13.521962 TX Vref Scan disable
3267 08:06:13.525013 == TX Byte 0 ==
3268 08:06:13.528745 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 08:06:13.531936 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 08:06:13.535278 == TX Byte 1 ==
3271 08:06:13.538740 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3272 08:06:13.545424 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3273 08:06:13.545518
3274 08:06:13.545586 [DATLAT]
3275 08:06:13.545649 Freq=1200, CH1 RK0
3276 08:06:13.545709
3277 08:06:13.548538 DATLAT Default: 0xd
3278 08:06:13.548612 0, 0xFFFF, sum = 0
3279 08:06:13.551963 1, 0xFFFF, sum = 0
3280 08:06:13.552035 2, 0xFFFF, sum = 0
3281 08:06:13.554971 3, 0xFFFF, sum = 0
3282 08:06:13.558677 4, 0xFFFF, sum = 0
3283 08:06:13.558773 5, 0xFFFF, sum = 0
3284 08:06:13.561847 6, 0xFFFF, sum = 0
3285 08:06:13.561981 7, 0xFFFF, sum = 0
3286 08:06:13.564968 8, 0xFFFF, sum = 0
3287 08:06:13.565050 9, 0xFFFF, sum = 0
3288 08:06:13.568312 10, 0xFFFF, sum = 0
3289 08:06:13.568412 11, 0xFFFF, sum = 0
3290 08:06:13.571638 12, 0x0, sum = 1
3291 08:06:13.571752 13, 0x0, sum = 2
3292 08:06:13.574923 14, 0x0, sum = 3
3293 08:06:13.574998 15, 0x0, sum = 4
3294 08:06:13.578436 best_step = 13
3295 08:06:13.578534
3296 08:06:13.578634 ==
3297 08:06:13.582335 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 08:06:13.584916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 08:06:13.585035 ==
3300 08:06:13.585125 RX Vref Scan: 1
3301 08:06:13.585221
3302 08:06:13.588557 Set Vref Range= 32 -> 127
3303 08:06:13.588660
3304 08:06:13.591693 RX Vref 32 -> 127, step: 1
3305 08:06:13.591763
3306 08:06:13.594989 RX Delay -21 -> 252, step: 4
3307 08:06:13.595085
3308 08:06:13.598472 Set Vref, RX VrefLevel [Byte0]: 32
3309 08:06:13.601542 [Byte1]: 32
3310 08:06:13.601645
3311 08:06:13.604932 Set Vref, RX VrefLevel [Byte0]: 33
3312 08:06:13.608185 [Byte1]: 33
3313 08:06:13.611632
3314 08:06:13.611728 Set Vref, RX VrefLevel [Byte0]: 34
3315 08:06:13.615087 [Byte1]: 34
3316 08:06:13.620289
3317 08:06:13.620388 Set Vref, RX VrefLevel [Byte0]: 35
3318 08:06:13.622958 [Byte1]: 35
3319 08:06:13.627938
3320 08:06:13.628026 Set Vref, RX VrefLevel [Byte0]: 36
3321 08:06:13.631169 [Byte1]: 36
3322 08:06:13.635450
3323 08:06:13.635557 Set Vref, RX VrefLevel [Byte0]: 37
3324 08:06:13.638855 [Byte1]: 37
3325 08:06:13.643327
3326 08:06:13.643461 Set Vref, RX VrefLevel [Byte0]: 38
3327 08:06:13.646778 [Byte1]: 38
3328 08:06:13.651430
3329 08:06:13.651540 Set Vref, RX VrefLevel [Byte0]: 39
3330 08:06:13.655051 [Byte1]: 39
3331 08:06:13.659325
3332 08:06:13.659451 Set Vref, RX VrefLevel [Byte0]: 40
3333 08:06:13.662440 [Byte1]: 40
3334 08:06:13.667667
3335 08:06:13.667767 Set Vref, RX VrefLevel [Byte0]: 41
3336 08:06:13.670344 [Byte1]: 41
3337 08:06:13.675157
3338 08:06:13.675259 Set Vref, RX VrefLevel [Byte0]: 42
3339 08:06:13.678818 [Byte1]: 42
3340 08:06:13.683056
3341 08:06:13.683155 Set Vref, RX VrefLevel [Byte0]: 43
3342 08:06:13.686692 [Byte1]: 43
3343 08:06:13.691033
3344 08:06:13.691138 Set Vref, RX VrefLevel [Byte0]: 44
3345 08:06:13.694566 [Byte1]: 44
3346 08:06:13.699106
3347 08:06:13.699203 Set Vref, RX VrefLevel [Byte0]: 45
3348 08:06:13.702189 [Byte1]: 45
3349 08:06:13.706918
3350 08:06:13.707027 Set Vref, RX VrefLevel [Byte0]: 46
3351 08:06:13.710107 [Byte1]: 46
3352 08:06:13.714918
3353 08:06:13.715023 Set Vref, RX VrefLevel [Byte0]: 47
3354 08:06:13.718411 [Byte1]: 47
3355 08:06:13.723162
3356 08:06:13.723285 Set Vref, RX VrefLevel [Byte0]: 48
3357 08:06:13.725881 [Byte1]: 48
3358 08:06:13.730511
3359 08:06:13.730608 Set Vref, RX VrefLevel [Byte0]: 49
3360 08:06:13.734464 [Byte1]: 49
3361 08:06:13.738740
3362 08:06:13.738838 Set Vref, RX VrefLevel [Byte0]: 50
3363 08:06:13.742295 [Byte1]: 50
3364 08:06:13.746558
3365 08:06:13.746668 Set Vref, RX VrefLevel [Byte0]: 51
3366 08:06:13.750010 [Byte1]: 51
3367 08:06:13.754151
3368 08:06:13.754248 Set Vref, RX VrefLevel [Byte0]: 52
3369 08:06:13.758009 [Byte1]: 52
3370 08:06:13.762586
3371 08:06:13.762685 Set Vref, RX VrefLevel [Byte0]: 53
3372 08:06:13.765525 [Byte1]: 53
3373 08:06:13.770373
3374 08:06:13.770477 Set Vref, RX VrefLevel [Byte0]: 54
3375 08:06:13.773790 [Byte1]: 54
3376 08:06:13.778394
3377 08:06:13.778492 Set Vref, RX VrefLevel [Byte0]: 55
3378 08:06:13.781320 [Byte1]: 55
3379 08:06:13.786008
3380 08:06:13.786118 Set Vref, RX VrefLevel [Byte0]: 56
3381 08:06:13.789149 [Byte1]: 56
3382 08:06:13.794072
3383 08:06:13.794184 Set Vref, RX VrefLevel [Byte0]: 57
3384 08:06:13.797147 [Byte1]: 57
3385 08:06:13.801970
3386 08:06:13.802072 Set Vref, RX VrefLevel [Byte0]: 58
3387 08:06:13.805477 [Byte1]: 58
3388 08:06:13.810131
3389 08:06:13.810228 Set Vref, RX VrefLevel [Byte0]: 59
3390 08:06:13.813347 [Byte1]: 59
3391 08:06:13.817876
3392 08:06:13.817946 Set Vref, RX VrefLevel [Byte0]: 60
3393 08:06:13.821341 [Byte1]: 60
3394 08:06:13.825573
3395 08:06:13.825673 Set Vref, RX VrefLevel [Byte0]: 61
3396 08:06:13.828924 [Byte1]: 61
3397 08:06:13.833667
3398 08:06:13.833750 Set Vref, RX VrefLevel [Byte0]: 62
3399 08:06:13.836859 [Byte1]: 62
3400 08:06:13.841488
3401 08:06:13.841598 Set Vref, RX VrefLevel [Byte0]: 63
3402 08:06:13.844582 [Byte1]: 63
3403 08:06:13.849617
3404 08:06:13.849719 Set Vref, RX VrefLevel [Byte0]: 64
3405 08:06:13.852690 [Byte1]: 64
3406 08:06:13.857198
3407 08:06:13.857308 Set Vref, RX VrefLevel [Byte0]: 65
3408 08:06:13.860770 [Byte1]: 65
3409 08:06:13.865005
3410 08:06:13.865104 Set Vref, RX VrefLevel [Byte0]: 66
3411 08:06:13.868558 [Byte1]: 66
3412 08:06:13.872896
3413 08:06:13.873002 Set Vref, RX VrefLevel [Byte0]: 67
3414 08:06:13.876403 [Byte1]: 67
3415 08:06:13.880806
3416 08:06:13.880881 Set Vref, RX VrefLevel [Byte0]: 68
3417 08:06:13.884451 [Byte1]: 68
3418 08:06:13.888807
3419 08:06:13.888881 Set Vref, RX VrefLevel [Byte0]: 69
3420 08:06:13.892752 [Byte1]: 69
3421 08:06:13.896764
3422 08:06:13.896873 Final RX Vref Byte 0 = 56 to rank0
3423 08:06:13.900012 Final RX Vref Byte 1 = 50 to rank0
3424 08:06:13.903874 Final RX Vref Byte 0 = 56 to rank1
3425 08:06:13.906835 Final RX Vref Byte 1 = 50 to rank1==
3426 08:06:13.910180 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 08:06:13.917255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 08:06:13.917358 ==
3429 08:06:13.917450 DQS Delay:
3430 08:06:13.917543 DQS0 = 0, DQS1 = 0
3431 08:06:13.920162 DQM Delay:
3432 08:06:13.920260 DQM0 = 114, DQM1 = 106
3433 08:06:13.923606 DQ Delay:
3434 08:06:13.927281 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3435 08:06:13.930706 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3436 08:06:13.933774 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3437 08:06:13.937137 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =114
3438 08:06:13.937238
3439 08:06:13.937333
3440 08:06:13.943361 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3441 08:06:13.947003 CH1 RK0: MR19=303, MR18=F0F7
3442 08:06:13.953948 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3443 08:06:13.954066
3444 08:06:13.957407 ----->DramcWriteLeveling(PI) begin...
3445 08:06:13.957524 ==
3446 08:06:13.960228 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 08:06:13.963700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 08:06:13.966939 ==
3449 08:06:13.967042 Write leveling (Byte 0): 23 => 23
3450 08:06:13.970020 Write leveling (Byte 1): 28 => 28
3451 08:06:13.973447 DramcWriteLeveling(PI) end<-----
3452 08:06:13.973563
3453 08:06:13.973712 ==
3454 08:06:13.976849 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 08:06:13.983912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 08:06:13.983991 ==
3457 08:06:13.984056 [Gating] SW mode calibration
3458 08:06:13.994028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 08:06:13.996932 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 08:06:14.000239 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3461 08:06:14.006911 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 08:06:14.010589 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 08:06:14.014026 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 08:06:14.020518 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 08:06:14.023974 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3466 08:06:14.028267 0 15 24 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
3467 08:06:14.034000 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
3468 08:06:14.037434 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 08:06:14.040630 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 08:06:14.047514 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 08:06:14.050641 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 08:06:14.053688 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 08:06:14.060380 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3474 08:06:14.063739 1 0 24 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
3475 08:06:14.067265 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3476 08:06:14.073842 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 08:06:14.077022 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 08:06:14.080250 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 08:06:14.086822 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 08:06:14.090909 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 08:06:14.093585 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 08:06:14.096970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3483 08:06:14.103480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3484 08:06:14.106936 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 08:06:14.109998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 08:06:14.116753 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 08:06:14.120202 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 08:06:14.123734 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 08:06:14.129965 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 08:06:14.133444 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 08:06:14.136833 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 08:06:14.143103 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 08:06:14.146564 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 08:06:14.149910 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 08:06:14.156444 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 08:06:14.159541 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 08:06:14.163132 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 08:06:14.169911 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3499 08:06:14.172873 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3500 08:06:14.176558 Total UI for P1: 0, mck2ui 16
3501 08:06:14.179952 best dqsien dly found for B0: ( 1, 3, 24)
3502 08:06:14.182814 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 08:06:14.186605 Total UI for P1: 0, mck2ui 16
3504 08:06:14.189673 best dqsien dly found for B1: ( 1, 3, 26)
3505 08:06:14.192897 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3506 08:06:14.196170 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3507 08:06:14.196245
3508 08:06:14.203068 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3509 08:06:14.206157 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3510 08:06:14.206258 [Gating] SW calibration Done
3511 08:06:14.209768 ==
3512 08:06:14.212802 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 08:06:14.216313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 08:06:14.216410 ==
3515 08:06:14.216499 RX Vref Scan: 0
3516 08:06:14.216585
3517 08:06:14.219979 RX Vref 0 -> 0, step: 1
3518 08:06:14.220051
3519 08:06:14.222606 RX Delay -40 -> 252, step: 8
3520 08:06:14.225932 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3521 08:06:14.229709 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3522 08:06:14.232717 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3523 08:06:14.239519 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3524 08:06:14.242757 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3525 08:06:14.246313 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3526 08:06:14.249543 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3527 08:06:14.253226 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3528 08:06:14.259351 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3529 08:06:14.262928 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3530 08:06:14.266479 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3531 08:06:14.269946 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3532 08:06:14.272997 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3533 08:06:14.279515 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3534 08:06:14.282976 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3535 08:06:14.286225 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3536 08:06:14.286321 ==
3537 08:06:14.289342 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 08:06:14.292837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 08:06:14.295731 ==
3540 08:06:14.295853 DQS Delay:
3541 08:06:14.295964 DQS0 = 0, DQS1 = 0
3542 08:06:14.299433 DQM Delay:
3543 08:06:14.299542 DQM0 = 110, DQM1 = 107
3544 08:06:14.302690 DQ Delay:
3545 08:06:14.306331 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3546 08:06:14.309468 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3547 08:06:14.312607 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3548 08:06:14.315881 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3549 08:06:14.315959
3550 08:06:14.316027
3551 08:06:14.316087 ==
3552 08:06:14.319136 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 08:06:14.322493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 08:06:14.322601 ==
3555 08:06:14.322698
3556 08:06:14.322786
3557 08:06:14.325957 TX Vref Scan disable
3558 08:06:14.329217 == TX Byte 0 ==
3559 08:06:14.332464 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3560 08:06:14.335932 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3561 08:06:14.339620 == TX Byte 1 ==
3562 08:06:14.342415 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3563 08:06:14.345635 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3564 08:06:14.345742 ==
3565 08:06:14.349127 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 08:06:14.355502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 08:06:14.355625 ==
3568 08:06:14.366042 TX Vref=22, minBit 0, minWin=25, winSum=423
3569 08:06:14.369743 TX Vref=24, minBit 9, minWin=25, winSum=427
3570 08:06:14.372683 TX Vref=26, minBit 8, minWin=26, winSum=435
3571 08:06:14.375984 TX Vref=28, minBit 1, minWin=26, winSum=432
3572 08:06:14.379582 TX Vref=30, minBit 8, minWin=26, winSum=432
3573 08:06:14.383006 TX Vref=32, minBit 8, minWin=25, winSum=430
3574 08:06:14.389665 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 26
3575 08:06:14.389775
3576 08:06:14.392878 Final TX Range 1 Vref 26
3577 08:06:14.392991
3578 08:06:14.393083 ==
3579 08:06:14.396261 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 08:06:14.399247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 08:06:14.399360 ==
3582 08:06:14.402657
3583 08:06:14.402754
3584 08:06:14.402850 TX Vref Scan disable
3585 08:06:14.405907 == TX Byte 0 ==
3586 08:06:14.409221 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3587 08:06:14.412634 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3588 08:06:14.415950 == TX Byte 1 ==
3589 08:06:14.419542 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3590 08:06:14.426265 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3591 08:06:14.426365
3592 08:06:14.426455 [DATLAT]
3593 08:06:14.426555 Freq=1200, CH1 RK1
3594 08:06:14.426644
3595 08:06:14.429105 DATLAT Default: 0xd
3596 08:06:14.429211 0, 0xFFFF, sum = 0
3597 08:06:14.432545 1, 0xFFFF, sum = 0
3598 08:06:14.435535 2, 0xFFFF, sum = 0
3599 08:06:14.435635 3, 0xFFFF, sum = 0
3600 08:06:14.439207 4, 0xFFFF, sum = 0
3601 08:06:14.439320 5, 0xFFFF, sum = 0
3602 08:06:14.442393 6, 0xFFFF, sum = 0
3603 08:06:14.442499 7, 0xFFFF, sum = 0
3604 08:06:14.445793 8, 0xFFFF, sum = 0
3605 08:06:14.445896 9, 0xFFFF, sum = 0
3606 08:06:14.449227 10, 0xFFFF, sum = 0
3607 08:06:14.449326 11, 0xFFFF, sum = 0
3608 08:06:14.452572 12, 0x0, sum = 1
3609 08:06:14.452648 13, 0x0, sum = 2
3610 08:06:14.455699 14, 0x0, sum = 3
3611 08:06:14.455768 15, 0x0, sum = 4
3612 08:06:14.458887 best_step = 13
3613 08:06:14.458981
3614 08:06:14.459068 ==
3615 08:06:14.462292 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 08:06:14.465710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 08:06:14.465810 ==
3618 08:06:14.465899 RX Vref Scan: 0
3619 08:06:14.469096
3620 08:06:14.469194 RX Vref 0 -> 0, step: 1
3621 08:06:14.469286
3622 08:06:14.472297 RX Delay -21 -> 252, step: 4
3623 08:06:14.479439 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3624 08:06:14.482290 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3625 08:06:14.485461 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3626 08:06:14.489084 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3627 08:06:14.492470 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3628 08:06:14.495510 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3629 08:06:14.501813 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3630 08:06:14.505620 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3631 08:06:14.508576 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3632 08:06:14.511959 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3633 08:06:14.515360 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3634 08:06:14.521761 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3635 08:06:14.525453 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3636 08:06:14.528665 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3637 08:06:14.532182 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3638 08:06:14.538539 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3639 08:06:14.538638 ==
3640 08:06:14.541617 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 08:06:14.545451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 08:06:14.545550 ==
3643 08:06:14.545643 DQS Delay:
3644 08:06:14.548470 DQS0 = 0, DQS1 = 0
3645 08:06:14.548562 DQM Delay:
3646 08:06:14.551754 DQM0 = 112, DQM1 = 109
3647 08:06:14.551852 DQ Delay:
3648 08:06:14.555428 DQ0 =114, DQ1 =110, DQ2 =102, DQ3 =110
3649 08:06:14.558282 DQ4 =110, DQ5 =122, DQ6 =122, DQ7 =110
3650 08:06:14.561755 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3651 08:06:14.564833 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3652 08:06:14.564907
3653 08:06:14.564968
3654 08:06:14.575267 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3655 08:06:14.578540 CH1 RK1: MR19=304, MR18=FB0B
3656 08:06:14.581663 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3657 08:06:14.584983 [RxdqsGatingPostProcess] freq 1200
3658 08:06:14.591547 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3659 08:06:14.595025 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 08:06:14.598436 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 08:06:14.601464 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 08:06:14.604718 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 08:06:14.608079 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 08:06:14.611681 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 08:06:14.614621 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 08:06:14.618340 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 08:06:14.621227 Pre-setting of DQS Precalculation
3668 08:06:14.624921 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3669 08:06:14.631208 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3670 08:06:14.637951 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3671 08:06:14.641240
3672 08:06:14.641344
3673 08:06:14.641440 [Calibration Summary] 2400 Mbps
3674 08:06:14.644851 CH 0, Rank 0
3675 08:06:14.644961 SW Impedance : PASS
3676 08:06:14.647984 DUTY Scan : NO K
3677 08:06:14.651576 ZQ Calibration : PASS
3678 08:06:14.651682 Jitter Meter : NO K
3679 08:06:14.654885 CBT Training : PASS
3680 08:06:14.657688 Write leveling : PASS
3681 08:06:14.657789 RX DQS gating : PASS
3682 08:06:14.661347 RX DQ/DQS(RDDQC) : PASS
3683 08:06:14.664176 TX DQ/DQS : PASS
3684 08:06:14.664279 RX DATLAT : PASS
3685 08:06:14.667983 RX DQ/DQS(Engine): PASS
3686 08:06:14.670820 TX OE : NO K
3687 08:06:14.670924 All Pass.
3688 08:06:14.671019
3689 08:06:14.671110 CH 0, Rank 1
3690 08:06:14.674221 SW Impedance : PASS
3691 08:06:14.677632 DUTY Scan : NO K
3692 08:06:14.677732 ZQ Calibration : PASS
3693 08:06:14.681099 Jitter Meter : NO K
3694 08:06:14.684566 CBT Training : PASS
3695 08:06:14.684667 Write leveling : PASS
3696 08:06:14.687460 RX DQS gating : PASS
3697 08:06:14.690831 RX DQ/DQS(RDDQC) : PASS
3698 08:06:14.690932 TX DQ/DQS : PASS
3699 08:06:14.694758 RX DATLAT : PASS
3700 08:06:14.694858 RX DQ/DQS(Engine): PASS
3701 08:06:14.697758 TX OE : NO K
3702 08:06:14.697859 All Pass.
3703 08:06:14.697950
3704 08:06:14.701090 CH 1, Rank 0
3705 08:06:14.701168 SW Impedance : PASS
3706 08:06:14.704199 DUTY Scan : NO K
3707 08:06:14.707626 ZQ Calibration : PASS
3708 08:06:14.707724 Jitter Meter : NO K
3709 08:06:14.711051 CBT Training : PASS
3710 08:06:14.713983 Write leveling : PASS
3711 08:06:14.714079 RX DQS gating : PASS
3712 08:06:14.717829 RX DQ/DQS(RDDQC) : PASS
3713 08:06:14.721026 TX DQ/DQS : PASS
3714 08:06:14.721101 RX DATLAT : PASS
3715 08:06:14.724209 RX DQ/DQS(Engine): PASS
3716 08:06:14.727542 TX OE : NO K
3717 08:06:14.727617 All Pass.
3718 08:06:14.727678
3719 08:06:14.727736 CH 1, Rank 1
3720 08:06:14.730945 SW Impedance : PASS
3721 08:06:14.733846 DUTY Scan : NO K
3722 08:06:14.733919 ZQ Calibration : PASS
3723 08:06:14.737770 Jitter Meter : NO K
3724 08:06:14.740571 CBT Training : PASS
3725 08:06:14.740642 Write leveling : PASS
3726 08:06:14.744219 RX DQS gating : PASS
3727 08:06:14.744290 RX DQ/DQS(RDDQC) : PASS
3728 08:06:14.747670 TX DQ/DQS : PASS
3729 08:06:14.750584 RX DATLAT : PASS
3730 08:06:14.750677 RX DQ/DQS(Engine): PASS
3731 08:06:14.754141 TX OE : NO K
3732 08:06:14.754282 All Pass.
3733 08:06:14.754370
3734 08:06:14.757413 DramC Write-DBI off
3735 08:06:14.760575 PER_BANK_REFRESH: Hybrid Mode
3736 08:06:14.760652 TX_TRACKING: ON
3737 08:06:14.770748 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3738 08:06:14.774256 [FAST_K] Save calibration result to emmc
3739 08:06:14.777780 dramc_set_vcore_voltage set vcore to 650000
3740 08:06:14.780441 Read voltage for 600, 5
3741 08:06:14.780516 Vio18 = 0
3742 08:06:14.780579 Vcore = 650000
3743 08:06:14.784020 Vdram = 0
3744 08:06:14.784094 Vddq = 0
3745 08:06:14.784163 Vmddr = 0
3746 08:06:14.790848 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3747 08:06:14.793765 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3748 08:06:14.797135 MEM_TYPE=3, freq_sel=19
3749 08:06:14.800628 sv_algorithm_assistance_LP4_1600
3750 08:06:14.804393 ============ PULL DRAM RESETB DOWN ============
3751 08:06:14.810384 ========== PULL DRAM RESETB DOWN end =========
3752 08:06:14.814110 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 08:06:14.817335 ===================================
3754 08:06:14.820428 LPDDR4 DRAM CONFIGURATION
3755 08:06:14.823817 ===================================
3756 08:06:14.823914 EX_ROW_EN[0] = 0x0
3757 08:06:14.826978 EX_ROW_EN[1] = 0x0
3758 08:06:14.827080 LP4Y_EN = 0x0
3759 08:06:14.830955 WORK_FSP = 0x0
3760 08:06:14.831060 WL = 0x2
3761 08:06:14.833722 RL = 0x2
3762 08:06:14.833821 BL = 0x2
3763 08:06:14.837207 RPST = 0x0
3764 08:06:14.837331 RD_PRE = 0x0
3765 08:06:14.840183 WR_PRE = 0x1
3766 08:06:14.840291 WR_PST = 0x0
3767 08:06:14.843941 DBI_WR = 0x0
3768 08:06:14.847181 DBI_RD = 0x0
3769 08:06:14.847282 OTF = 0x1
3770 08:06:14.850418 ===================================
3771 08:06:14.853753 ===================================
3772 08:06:14.853854 ANA top config
3773 08:06:14.857028 ===================================
3774 08:06:14.860509 DLL_ASYNC_EN = 0
3775 08:06:14.863329 ALL_SLAVE_EN = 1
3776 08:06:14.867024 NEW_RANK_MODE = 1
3777 08:06:14.870102 DLL_IDLE_MODE = 1
3778 08:06:14.870201 LP45_APHY_COMB_EN = 1
3779 08:06:14.873249 TX_ODT_DIS = 1
3780 08:06:14.876583 NEW_8X_MODE = 1
3781 08:06:14.880048 ===================================
3782 08:06:14.883503 ===================================
3783 08:06:14.886879 data_rate = 1200
3784 08:06:14.890385 CKR = 1
3785 08:06:14.890484 DQ_P2S_RATIO = 8
3786 08:06:14.893355 ===================================
3787 08:06:14.896868 CA_P2S_RATIO = 8
3788 08:06:14.900229 DQ_CA_OPEN = 0
3789 08:06:14.903633 DQ_SEMI_OPEN = 0
3790 08:06:14.906495 CA_SEMI_OPEN = 0
3791 08:06:14.910303 CA_FULL_RATE = 0
3792 08:06:14.910403 DQ_CKDIV4_EN = 1
3793 08:06:14.913592 CA_CKDIV4_EN = 1
3794 08:06:14.916873 CA_PREDIV_EN = 0
3795 08:06:14.919742 PH8_DLY = 0
3796 08:06:14.923336 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3797 08:06:14.926776 DQ_AAMCK_DIV = 4
3798 08:06:14.926882 CA_AAMCK_DIV = 4
3799 08:06:14.930095 CA_ADMCK_DIV = 4
3800 08:06:14.933265 DQ_TRACK_CA_EN = 0
3801 08:06:14.936774 CA_PICK = 600
3802 08:06:14.939647 CA_MCKIO = 600
3803 08:06:14.943405 MCKIO_SEMI = 0
3804 08:06:14.946148 PLL_FREQ = 2288
3805 08:06:14.946253 DQ_UI_PI_RATIO = 32
3806 08:06:14.949536 CA_UI_PI_RATIO = 0
3807 08:06:14.953060 ===================================
3808 08:06:14.956086 ===================================
3809 08:06:14.959336 memory_type:LPDDR4
3810 08:06:14.962915 GP_NUM : 10
3811 08:06:14.963019 SRAM_EN : 1
3812 08:06:14.966419 MD32_EN : 0
3813 08:06:14.969642 ===================================
3814 08:06:14.972901 [ANA_INIT] >>>>>>>>>>>>>>
3815 08:06:14.973010 <<<<<< [CONFIGURE PHASE]: ANA_TX
3816 08:06:14.975978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3817 08:06:14.979601 ===================================
3818 08:06:14.982643 data_rate = 1200,PCW = 0X5800
3819 08:06:14.985878 ===================================
3820 08:06:14.989255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3821 08:06:14.995855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 08:06:15.002816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 08:06:15.006179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3824 08:06:15.009702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3825 08:06:15.013026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3826 08:06:15.016188 [ANA_INIT] flow start
3827 08:06:15.016275 [ANA_INIT] PLL >>>>>>>>
3828 08:06:15.019200 [ANA_INIT] PLL <<<<<<<<
3829 08:06:15.022953 [ANA_INIT] MIDPI >>>>>>>>
3830 08:06:15.023053 [ANA_INIT] MIDPI <<<<<<<<
3831 08:06:15.026018 [ANA_INIT] DLL >>>>>>>>
3832 08:06:15.029249 [ANA_INIT] flow end
3833 08:06:15.032847 ============ LP4 DIFF to SE enter ============
3834 08:06:15.036499 ============ LP4 DIFF to SE exit ============
3835 08:06:15.039546 [ANA_INIT] <<<<<<<<<<<<<
3836 08:06:15.042520 [Flow] Enable top DCM control >>>>>
3837 08:06:15.045801 [Flow] Enable top DCM control <<<<<
3838 08:06:15.049202 Enable DLL master slave shuffle
3839 08:06:15.052547 ==============================================================
3840 08:06:15.055709 Gating Mode config
3841 08:06:15.062568 ==============================================================
3842 08:06:15.062675 Config description:
3843 08:06:15.072422 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3844 08:06:15.079520 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3845 08:06:15.085876 SELPH_MODE 0: By rank 1: By Phase
3846 08:06:15.088888 ==============================================================
3847 08:06:15.092136 GAT_TRACK_EN = 1
3848 08:06:15.095400 RX_GATING_MODE = 2
3849 08:06:15.098780 RX_GATING_TRACK_MODE = 2
3850 08:06:15.102223 SELPH_MODE = 1
3851 08:06:15.105873 PICG_EARLY_EN = 1
3852 08:06:15.108644 VALID_LAT_VALUE = 1
3853 08:06:15.112727 ==============================================================
3854 08:06:15.115416 Enter into Gating configuration >>>>
3855 08:06:15.118664 Exit from Gating configuration <<<<
3856 08:06:15.122182 Enter into DVFS_PRE_config >>>>>
3857 08:06:15.135379 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3858 08:06:15.138555 Exit from DVFS_PRE_config <<<<<
3859 08:06:15.141819 Enter into PICG configuration >>>>
3860 08:06:15.141897 Exit from PICG configuration <<<<
3861 08:06:15.145190 [RX_INPUT] configuration >>>>>
3862 08:06:15.148608 [RX_INPUT] configuration <<<<<
3863 08:06:15.155810 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3864 08:06:15.158759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3865 08:06:15.164884 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 08:06:15.171901 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 08:06:15.178304 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 08:06:15.185063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 08:06:15.188577 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3870 08:06:15.191714 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3871 08:06:15.195527 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3872 08:06:15.201957 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3873 08:06:15.205120 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3874 08:06:15.208193 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 08:06:15.211493 ===================================
3876 08:06:15.215311 LPDDR4 DRAM CONFIGURATION
3877 08:06:15.218757 ===================================
3878 08:06:15.221463 EX_ROW_EN[0] = 0x0
3879 08:06:15.221561 EX_ROW_EN[1] = 0x0
3880 08:06:15.224800 LP4Y_EN = 0x0
3881 08:06:15.224896 WORK_FSP = 0x0
3882 08:06:15.228489 WL = 0x2
3883 08:06:15.228587 RL = 0x2
3884 08:06:15.231658 BL = 0x2
3885 08:06:15.231757 RPST = 0x0
3886 08:06:15.234773 RD_PRE = 0x0
3887 08:06:15.234873 WR_PRE = 0x1
3888 08:06:15.238061 WR_PST = 0x0
3889 08:06:15.238160 DBI_WR = 0x0
3890 08:06:15.241837 DBI_RD = 0x0
3891 08:06:15.241916 OTF = 0x1
3892 08:06:15.244549 ===================================
3893 08:06:15.251326 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3894 08:06:15.254600 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3895 08:06:15.257781 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 08:06:15.261072 ===================================
3897 08:06:15.265220 LPDDR4 DRAM CONFIGURATION
3898 08:06:15.267759 ===================================
3899 08:06:15.271535 EX_ROW_EN[0] = 0x10
3900 08:06:15.271633 EX_ROW_EN[1] = 0x0
3901 08:06:15.274386 LP4Y_EN = 0x0
3902 08:06:15.274484 WORK_FSP = 0x0
3903 08:06:15.277821 WL = 0x2
3904 08:06:15.277909 RL = 0x2
3905 08:06:15.281596 BL = 0x2
3906 08:06:15.281671 RPST = 0x0
3907 08:06:15.284547 RD_PRE = 0x0
3908 08:06:15.284646 WR_PRE = 0x1
3909 08:06:15.287831 WR_PST = 0x0
3910 08:06:15.287907 DBI_WR = 0x0
3911 08:06:15.291310 DBI_RD = 0x0
3912 08:06:15.291426 OTF = 0x1
3913 08:06:15.294169 ===================================
3914 08:06:15.300822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3915 08:06:15.305726 nWR fixed to 30
3916 08:06:15.309003 [ModeRegInit_LP4] CH0 RK0
3917 08:06:15.309077 [ModeRegInit_LP4] CH0 RK1
3918 08:06:15.312375 [ModeRegInit_LP4] CH1 RK0
3919 08:06:15.316046 [ModeRegInit_LP4] CH1 RK1
3920 08:06:15.316125 match AC timing 17
3921 08:06:15.322300 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3922 08:06:15.325396 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3923 08:06:15.329087 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3924 08:06:15.335886 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3925 08:06:15.338759 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3926 08:06:15.338860 ==
3927 08:06:15.342208 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 08:06:15.345486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 08:06:15.345586 ==
3930 08:06:15.352314 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 08:06:15.358575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3932 08:06:15.362438 [CA 0] Center 37 (7~67) winsize 61
3933 08:06:15.365238 [CA 1] Center 36 (6~67) winsize 62
3934 08:06:15.368521 [CA 2] Center 35 (5~65) winsize 61
3935 08:06:15.371853 [CA 3] Center 34 (4~65) winsize 62
3936 08:06:15.375345 [CA 4] Center 34 (4~64) winsize 61
3937 08:06:15.378876 [CA 5] Center 34 (4~64) winsize 61
3938 08:06:15.378978
3939 08:06:15.382520 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3940 08:06:15.382618
3941 08:06:15.385022 [CATrainingPosCal] consider 1 rank data
3942 08:06:15.388833 u2DelayCellTimex100 = 270/100 ps
3943 08:06:15.391767 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3944 08:06:15.394958 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3945 08:06:15.398169 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3946 08:06:15.401517 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3947 08:06:15.408400 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3948 08:06:15.411915 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3949 08:06:15.412027
3950 08:06:15.414915 CA PerBit enable=1, Macro0, CA PI delay=34
3951 08:06:15.415036
3952 08:06:15.418302 [CBTSetCACLKResult] CA Dly = 34
3953 08:06:15.418412 CS Dly: 5 (0~36)
3954 08:06:15.418509 ==
3955 08:06:15.421747 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 08:06:15.425456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 08:06:15.428474 ==
3958 08:06:15.431728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 08:06:15.438371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3960 08:06:15.441528 [CA 0] Center 37 (7~67) winsize 61
3961 08:06:15.444833 [CA 1] Center 37 (7~67) winsize 61
3962 08:06:15.448294 [CA 2] Center 35 (5~65) winsize 61
3963 08:06:15.451927 [CA 3] Center 35 (5~65) winsize 61
3964 08:06:15.454801 [CA 4] Center 34 (3~65) winsize 63
3965 08:06:15.458341 [CA 5] Center 34 (3~65) winsize 63
3966 08:06:15.458440
3967 08:06:15.461470 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3968 08:06:15.461570
3969 08:06:15.464872 [CATrainingPosCal] consider 2 rank data
3970 08:06:15.467975 u2DelayCellTimex100 = 270/100 ps
3971 08:06:15.471087 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3972 08:06:15.474815 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3973 08:06:15.481087 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3974 08:06:15.484547 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3975 08:06:15.487840 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3976 08:06:15.491202 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3977 08:06:15.491301
3978 08:06:15.494990 CA PerBit enable=1, Macro0, CA PI delay=34
3979 08:06:15.495106
3980 08:06:15.497749 [CBTSetCACLKResult] CA Dly = 34
3981 08:06:15.497848 CS Dly: 6 (0~38)
3982 08:06:15.497943
3983 08:06:15.501466 ----->DramcWriteLeveling(PI) begin...
3984 08:06:15.504730 ==
3985 08:06:15.504834 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 08:06:15.511057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 08:06:15.511162 ==
3988 08:06:15.514869 Write leveling (Byte 0): 32 => 32
3989 08:06:15.517866 Write leveling (Byte 1): 30 => 30
3990 08:06:15.521075 DramcWriteLeveling(PI) end<-----
3991 08:06:15.521195
3992 08:06:15.521296 ==
3993 08:06:15.524366 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 08:06:15.527784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 08:06:15.527861 ==
3996 08:06:15.531482 [Gating] SW mode calibration
3997 08:06:15.537435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3998 08:06:15.544606 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3999 08:06:15.547773 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 08:06:15.551205 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 08:06:15.554432 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 08:06:15.560741 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4003 08:06:15.564071 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (1 1)
4004 08:06:15.567739 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 08:06:15.574337 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 08:06:15.577656 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 08:06:15.581191 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 08:06:15.587764 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 08:06:15.591107 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 08:06:15.594301 0 10 12 | B1->B0 | 2626 2d2d | 0 1 | (0 0) (0 0)
4011 08:06:15.601155 0 10 16 | B1->B0 | 3030 3b3b | 0 0 | (1 1) (0 0)
4012 08:06:15.604509 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 08:06:15.607301 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 08:06:15.613889 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 08:06:15.617125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 08:06:15.620655 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 08:06:15.627182 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 08:06:15.630650 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4019 08:06:15.633612 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4020 08:06:15.640281 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 08:06:15.643502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 08:06:15.647050 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 08:06:15.653479 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 08:06:15.656945 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 08:06:15.660293 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 08:06:15.666646 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 08:06:15.670264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 08:06:15.673520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 08:06:15.680264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 08:06:15.683728 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 08:06:15.686828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 08:06:15.693769 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 08:06:15.697039 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 08:06:15.700073 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 08:06:15.703331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 08:06:15.706799 Total UI for P1: 0, mck2ui 16
4037 08:06:15.710446 best dqsien dly found for B0: ( 0, 13, 14)
4038 08:06:15.713332 Total UI for P1: 0, mck2ui 16
4039 08:06:15.716744 best dqsien dly found for B1: ( 0, 13, 14)
4040 08:06:15.720120 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4041 08:06:15.726660 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4042 08:06:15.726757
4043 08:06:15.729940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4044 08:06:15.733215 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4045 08:06:15.736701 [Gating] SW calibration Done
4046 08:06:15.736777 ==
4047 08:06:15.739988 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 08:06:15.743247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 08:06:15.743345 ==
4050 08:06:15.746350 RX Vref Scan: 0
4051 08:06:15.746448
4052 08:06:15.746534 RX Vref 0 -> 0, step: 1
4053 08:06:15.746595
4054 08:06:15.749827 RX Delay -230 -> 252, step: 16
4055 08:06:15.753039 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4056 08:06:15.760676 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4057 08:06:15.762812 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4058 08:06:15.766368 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4059 08:06:15.769828 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 08:06:15.776565 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4061 08:06:15.779534 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4062 08:06:15.782629 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 08:06:15.785912 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4064 08:06:15.789680 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 08:06:15.796070 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4066 08:06:15.799670 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4067 08:06:15.802705 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4068 08:06:15.806186 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4069 08:06:15.812733 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4070 08:06:15.816387 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4071 08:06:15.816480 ==
4072 08:06:15.819028 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 08:06:15.822731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 08:06:15.822827 ==
4075 08:06:15.825891 DQS Delay:
4076 08:06:15.825984 DQS0 = 0, DQS1 = 0
4077 08:06:15.829032 DQM Delay:
4078 08:06:15.829098 DQM0 = 37, DQM1 = 30
4079 08:06:15.829156 DQ Delay:
4080 08:06:15.832521 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4081 08:06:15.836148 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4082 08:06:15.839363 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4083 08:06:15.842618 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4084 08:06:15.842704
4085 08:06:15.842772
4086 08:06:15.845688 ==
4087 08:06:15.845820 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 08:06:15.852617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 08:06:15.852719 ==
4090 08:06:15.852802
4091 08:06:15.852877
4092 08:06:15.855698 TX Vref Scan disable
4093 08:06:15.855809 == TX Byte 0 ==
4094 08:06:15.858952 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4095 08:06:15.865767 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4096 08:06:15.865902 == TX Byte 1 ==
4097 08:06:15.869369 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4098 08:06:15.876105 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4099 08:06:15.876285 ==
4100 08:06:15.879337 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 08:06:15.882447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 08:06:15.882676 ==
4103 08:06:15.882829
4104 08:06:15.882974
4105 08:06:15.885563 TX Vref Scan disable
4106 08:06:15.889273 == TX Byte 0 ==
4107 08:06:15.892626 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4108 08:06:15.895872 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4109 08:06:15.899077 == TX Byte 1 ==
4110 08:06:15.902451 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4111 08:06:15.905834 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4112 08:06:15.906381
4113 08:06:15.909363 [DATLAT]
4114 08:06:15.909962 Freq=600, CH0 RK0
4115 08:06:15.910451
4116 08:06:15.912383 DATLAT Default: 0x9
4117 08:06:15.912829 0, 0xFFFF, sum = 0
4118 08:06:15.915788 1, 0xFFFF, sum = 0
4119 08:06:15.916317 2, 0xFFFF, sum = 0
4120 08:06:15.919022 3, 0xFFFF, sum = 0
4121 08:06:15.919548 4, 0xFFFF, sum = 0
4122 08:06:15.922281 5, 0xFFFF, sum = 0
4123 08:06:15.922824 6, 0xFFFF, sum = 0
4124 08:06:15.925510 7, 0xFFFF, sum = 0
4125 08:06:15.925950 8, 0x0, sum = 1
4126 08:06:15.928928 9, 0x0, sum = 2
4127 08:06:15.929377 10, 0x0, sum = 3
4128 08:06:15.932381 11, 0x0, sum = 4
4129 08:06:15.932820 best_step = 9
4130 08:06:15.933179
4131 08:06:15.933520 ==
4132 08:06:15.935498 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 08:06:15.938878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 08:06:15.942110 ==
4135 08:06:15.942691 RX Vref Scan: 1
4136 08:06:15.943045
4137 08:06:15.945582 RX Vref 0 -> 0, step: 1
4138 08:06:15.946114
4139 08:06:15.949022 RX Delay -195 -> 252, step: 8
4140 08:06:15.949451
4141 08:06:15.952024 Set Vref, RX VrefLevel [Byte0]: 62
4142 08:06:15.955460 [Byte1]: 48
4143 08:06:15.955900
4144 08:06:15.958873 Final RX Vref Byte 0 = 62 to rank0
4145 08:06:15.961880 Final RX Vref Byte 1 = 48 to rank0
4146 08:06:15.965700 Final RX Vref Byte 0 = 62 to rank1
4147 08:06:15.968495 Final RX Vref Byte 1 = 48 to rank1==
4148 08:06:15.971914 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 08:06:15.975284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 08:06:15.975815 ==
4151 08:06:15.978699 DQS Delay:
4152 08:06:15.979149 DQS0 = 0, DQS1 = 0
4153 08:06:15.979542 DQM Delay:
4154 08:06:15.982144 DQM0 = 35, DQM1 = 29
4155 08:06:15.982698 DQ Delay:
4156 08:06:15.985736 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4157 08:06:15.988669 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4158 08:06:15.992029 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4159 08:06:15.995238 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4160 08:06:15.995744
4161 08:06:15.996232
4162 08:06:16.005261 [DQSOSCAuto] RK0, (LSB)MR18= 0x4040, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4163 08:06:16.005705 CH0 RK0: MR19=808, MR18=4040
4164 08:06:16.011883 CH0_RK0: MR19=0x808, MR18=0x4040, DQSOSC=397, MR23=63, INC=166, DEC=110
4165 08:06:16.012346
4166 08:06:16.015037 ----->DramcWriteLeveling(PI) begin...
4167 08:06:16.018243 ==
4168 08:06:16.021677 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 08:06:16.025036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 08:06:16.025476 ==
4171 08:06:16.028357 Write leveling (Byte 0): 33 => 33
4172 08:06:16.031358 Write leveling (Byte 1): 32 => 32
4173 08:06:16.035087 DramcWriteLeveling(PI) end<-----
4174 08:06:16.035568
4175 08:06:16.035923 ==
4176 08:06:16.038233 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 08:06:16.041343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 08:06:16.041903 ==
4179 08:06:16.045198 [Gating] SW mode calibration
4180 08:06:16.051436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 08:06:16.058117 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 08:06:16.061333 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 08:06:16.064934 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 08:06:16.067923 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 08:06:16.074497 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
4186 08:06:16.078257 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (0 0)
4187 08:06:16.081424 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 08:06:16.088190 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 08:06:16.091357 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 08:06:16.095111 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 08:06:16.101292 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 08:06:16.104689 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 08:06:16.108284 0 10 12 | B1->B0 | 2424 3030 | 1 1 | (0 0) (0 0)
4194 08:06:16.114558 0 10 16 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4195 08:06:16.117776 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 08:06:16.121596 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 08:06:16.127849 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 08:06:16.131545 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 08:06:16.134540 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 08:06:16.141247 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 08:06:16.144592 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4202 08:06:16.147914 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 08:06:16.154208 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 08:06:16.157706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 08:06:16.161299 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 08:06:16.167532 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 08:06:16.171003 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 08:06:16.174208 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 08:06:16.181220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 08:06:16.184285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 08:06:16.187851 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 08:06:16.194132 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 08:06:16.197376 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 08:06:16.200810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 08:06:16.207427 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 08:06:16.210895 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 08:06:16.214394 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4218 08:06:16.217694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 08:06:16.220739 Total UI for P1: 0, mck2ui 16
4220 08:06:16.224465 best dqsien dly found for B0: ( 0, 13, 12)
4221 08:06:16.227623 Total UI for P1: 0, mck2ui 16
4222 08:06:16.230668 best dqsien dly found for B1: ( 0, 13, 14)
4223 08:06:16.234128 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4224 08:06:16.241028 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4225 08:06:16.241585
4226 08:06:16.244083 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4227 08:06:16.247475 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4228 08:06:16.251152 [Gating] SW calibration Done
4229 08:06:16.251680 ==
4230 08:06:16.254154 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 08:06:16.257445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 08:06:16.257944 ==
4233 08:06:16.258284 RX Vref Scan: 0
4234 08:06:16.260719
4235 08:06:16.261156 RX Vref 0 -> 0, step: 1
4236 08:06:16.261668
4237 08:06:16.264045 RX Delay -230 -> 252, step: 16
4238 08:06:16.267451 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4239 08:06:16.274268 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4240 08:06:16.277644 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4241 08:06:16.280678 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4242 08:06:16.284054 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4243 08:06:16.287292 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4244 08:06:16.294283 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4245 08:06:16.297934 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4246 08:06:16.300734 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4247 08:06:16.304306 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4248 08:06:16.310617 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 08:06:16.314181 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4250 08:06:16.317305 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 08:06:16.320540 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4252 08:06:16.327627 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4253 08:06:16.330696 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4254 08:06:16.331194 ==
4255 08:06:16.334086 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 08:06:16.337064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 08:06:16.337527 ==
4258 08:06:16.340742 DQS Delay:
4259 08:06:16.341168 DQS0 = 0, DQS1 = 0
4260 08:06:16.341508 DQM Delay:
4261 08:06:16.343814 DQM0 = 34, DQM1 = 27
4262 08:06:16.344236 DQ Delay:
4263 08:06:16.347093 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4264 08:06:16.350186 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4265 08:06:16.353984 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =17
4266 08:06:16.357006 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4267 08:06:16.357433
4268 08:06:16.357768
4269 08:06:16.358078 ==
4270 08:06:16.360769 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 08:06:16.363664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 08:06:16.366859 ==
4273 08:06:16.367283
4274 08:06:16.367671
4275 08:06:16.368156 TX Vref Scan disable
4276 08:06:16.370122 == TX Byte 0 ==
4277 08:06:16.373864 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4278 08:06:16.379995 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4279 08:06:16.380430 == TX Byte 1 ==
4280 08:06:16.383161 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4281 08:06:16.390420 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4282 08:06:16.390884 ==
4283 08:06:16.393351 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 08:06:16.396625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 08:06:16.397058 ==
4286 08:06:16.397395
4287 08:06:16.397718
4288 08:06:16.400232 TX Vref Scan disable
4289 08:06:16.400661 == TX Byte 0 ==
4290 08:06:16.406774 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4291 08:06:16.410170 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4292 08:06:16.413730 == TX Byte 1 ==
4293 08:06:16.417008 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4294 08:06:16.420797 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4295 08:06:16.421228
4296 08:06:16.421563 [DATLAT]
4297 08:06:16.423548 Freq=600, CH0 RK1
4298 08:06:16.423982
4299 08:06:16.424382 DATLAT Default: 0x9
4300 08:06:16.426795 0, 0xFFFF, sum = 0
4301 08:06:16.427225 1, 0xFFFF, sum = 0
4302 08:06:16.430055 2, 0xFFFF, sum = 0
4303 08:06:16.433215 3, 0xFFFF, sum = 0
4304 08:06:16.433875 4, 0xFFFF, sum = 0
4305 08:06:16.436467 5, 0xFFFF, sum = 0
4306 08:06:16.436911 6, 0xFFFF, sum = 0
4307 08:06:16.439712 7, 0xFFFF, sum = 0
4308 08:06:16.440150 8, 0x0, sum = 1
4309 08:06:16.440566 9, 0x0, sum = 2
4310 08:06:16.443114 10, 0x0, sum = 3
4311 08:06:16.443751 11, 0x0, sum = 4
4312 08:06:16.447120 best_step = 9
4313 08:06:16.447609
4314 08:06:16.447945 ==
4315 08:06:16.450144 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 08:06:16.453403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 08:06:16.453734 ==
4318 08:06:16.456901 RX Vref Scan: 0
4319 08:06:16.457226
4320 08:06:16.457483 RX Vref 0 -> 0, step: 1
4321 08:06:16.457725
4322 08:06:16.459702 RX Delay -195 -> 252, step: 8
4323 08:06:16.467198 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4324 08:06:16.471051 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4325 08:06:16.473731 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4326 08:06:16.476901 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4327 08:06:16.483813 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4328 08:06:16.487109 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4329 08:06:16.490465 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4330 08:06:16.493936 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4331 08:06:16.496833 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4332 08:06:16.503634 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4333 08:06:16.507082 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4334 08:06:16.510412 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4335 08:06:16.513831 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4336 08:06:16.520715 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4337 08:06:16.523650 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4338 08:06:16.527447 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4339 08:06:16.527915 ==
4340 08:06:16.530398 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 08:06:16.533704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 08:06:16.537010 ==
4343 08:06:16.537494 DQS Delay:
4344 08:06:16.537890 DQS0 = 0, DQS1 = 0
4345 08:06:16.540738 DQM Delay:
4346 08:06:16.541208 DQM0 = 32, DQM1 = 28
4347 08:06:16.543506 DQ Delay:
4348 08:06:16.546983 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4349 08:06:16.547569 DQ4 =28, DQ5 =20, DQ6 =44, DQ7 =44
4350 08:06:16.550549 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4351 08:06:16.553576 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4352 08:06:16.556754
4353 08:06:16.557185
4354 08:06:16.564230 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4355 08:06:16.567121 CH0 RK1: MR19=808, MR18=6D3B
4356 08:06:16.573342 CH0_RK1: MR19=0x808, MR18=0x6D3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4357 08:06:16.576795 [RxdqsGatingPostProcess] freq 600
4358 08:06:16.580257 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 08:06:16.583297 Pre-setting of DQS Precalculation
4360 08:06:16.590272 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 08:06:16.590726 ==
4362 08:06:16.593963 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 08:06:16.597123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 08:06:16.597618 ==
4365 08:06:16.603520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 08:06:16.606614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4367 08:06:16.611502 [CA 0] Center 35 (5~66) winsize 62
4368 08:06:16.614479 [CA 1] Center 36 (6~66) winsize 61
4369 08:06:16.617367 [CA 2] Center 34 (4~65) winsize 62
4370 08:06:16.620754 [CA 3] Center 34 (3~65) winsize 63
4371 08:06:16.624144 [CA 4] Center 34 (4~65) winsize 62
4372 08:06:16.627474 [CA 5] Center 33 (3~64) winsize 62
4373 08:06:16.627932
4374 08:06:16.630890 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4375 08:06:16.631340
4376 08:06:16.634305 [CATrainingPosCal] consider 1 rank data
4377 08:06:16.637580 u2DelayCellTimex100 = 270/100 ps
4378 08:06:16.640873 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 08:06:16.647639 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4380 08:06:16.650756 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 08:06:16.654124 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4382 08:06:16.657160 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 08:06:16.660859 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 08:06:16.661285
4385 08:06:16.663880 CA PerBit enable=1, Macro0, CA PI delay=33
4386 08:06:16.664305
4387 08:06:16.667838 [CBTSetCACLKResult] CA Dly = 33
4388 08:06:16.668261 CS Dly: 4 (0~35)
4389 08:06:16.670598 ==
4390 08:06:16.673976 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 08:06:16.677461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 08:06:16.678057 ==
4393 08:06:16.680658 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 08:06:16.687312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4395 08:06:16.690951 [CA 0] Center 36 (6~66) winsize 61
4396 08:06:16.694760 [CA 1] Center 36 (6~66) winsize 61
4397 08:06:16.697913 [CA 2] Center 34 (4~65) winsize 62
4398 08:06:16.701147 [CA 3] Center 34 (3~65) winsize 63
4399 08:06:16.704012 [CA 4] Center 34 (3~65) winsize 63
4400 08:06:16.707862 [CA 5] Center 33 (3~64) winsize 62
4401 08:06:16.708289
4402 08:06:16.710778 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4403 08:06:16.711203
4404 08:06:16.714290 [CATrainingPosCal] consider 2 rank data
4405 08:06:16.717547 u2DelayCellTimex100 = 270/100 ps
4406 08:06:16.720711 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 08:06:16.727440 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 08:06:16.730744 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 08:06:16.733888 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4410 08:06:16.737259 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 08:06:16.740705 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 08:06:16.741128
4413 08:06:16.744170 CA PerBit enable=1, Macro0, CA PI delay=33
4414 08:06:16.744595
4415 08:06:16.747247 [CBTSetCACLKResult] CA Dly = 33
4416 08:06:16.747706 CS Dly: 5 (0~37)
4417 08:06:16.750868
4418 08:06:16.753929 ----->DramcWriteLeveling(PI) begin...
4419 08:06:16.754359 ==
4420 08:06:16.757140 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 08:06:16.761003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 08:06:16.761429 ==
4423 08:06:16.763863 Write leveling (Byte 0): 27 => 27
4424 08:06:16.767332 Write leveling (Byte 1): 30 => 30
4425 08:06:16.770639 DramcWriteLeveling(PI) end<-----
4426 08:06:16.771139
4427 08:06:16.771714 ==
4428 08:06:16.773646 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 08:06:16.777130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 08:06:16.777644 ==
4431 08:06:16.780384 [Gating] SW mode calibration
4432 08:06:16.787430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 08:06:16.793529 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 08:06:16.796910 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 08:06:16.800649 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 08:06:16.806734 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 08:06:16.810292 0 9 12 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
4438 08:06:16.813525 0 9 16 | B1->B0 | 2727 2a2a | 0 0 | (1 0) (1 0)
4439 08:06:16.820042 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 08:06:16.823323 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 08:06:16.826538 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 08:06:16.833196 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 08:06:16.836690 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 08:06:16.839991 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 08:06:16.846308 0 10 12 | B1->B0 | 3131 2f2f | 0 0 | (1 1) (0 0)
4446 08:06:16.849550 0 10 16 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
4447 08:06:16.852913 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 08:06:16.859698 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 08:06:16.862843 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 08:06:16.865981 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 08:06:16.872682 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 08:06:16.876039 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 08:06:16.879061 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4454 08:06:16.886114 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4455 08:06:16.889276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 08:06:16.892407 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 08:06:16.899060 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 08:06:16.902228 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 08:06:16.905862 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 08:06:16.912150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 08:06:16.915703 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 08:06:16.919090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 08:06:16.922493 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 08:06:16.929090 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 08:06:16.932077 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 08:06:16.935919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 08:06:16.942548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 08:06:16.945484 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 08:06:16.948794 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 08:06:16.952117 Total UI for P1: 0, mck2ui 16
4471 08:06:16.955277 best dqsien dly found for B0: ( 0, 13, 10)
4472 08:06:16.958434 Total UI for P1: 0, mck2ui 16
4473 08:06:16.962393 best dqsien dly found for B1: ( 0, 13, 10)
4474 08:06:16.965160 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4475 08:06:16.971887 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4476 08:06:16.971962
4477 08:06:16.974960 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4478 08:06:16.978312 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4479 08:06:16.981700 [Gating] SW calibration Done
4480 08:06:16.981778 ==
4481 08:06:16.985436 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 08:06:16.988388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 08:06:16.988462 ==
4484 08:06:16.991632 RX Vref Scan: 0
4485 08:06:16.991713
4486 08:06:16.991776 RX Vref 0 -> 0, step: 1
4487 08:06:16.991835
4488 08:06:16.994877 RX Delay -230 -> 252, step: 16
4489 08:06:16.998194 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4490 08:06:17.004745 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4491 08:06:17.008302 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4492 08:06:17.011645 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4493 08:06:17.014934 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4494 08:06:17.021560 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4495 08:06:17.024559 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4496 08:06:17.028054 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4497 08:06:17.031195 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4498 08:06:17.034685 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4499 08:06:17.041478 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4500 08:06:17.044957 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4501 08:06:17.047862 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4502 08:06:17.051050 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4503 08:06:17.057750 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4504 08:06:17.061078 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4505 08:06:17.061160 ==
4506 08:06:17.064769 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 08:06:17.067852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 08:06:17.067935 ==
4509 08:06:17.071289 DQS Delay:
4510 08:06:17.071371 DQS0 = 0, DQS1 = 0
4511 08:06:17.071448 DQM Delay:
4512 08:06:17.074220 DQM0 = 37, DQM1 = 28
4513 08:06:17.074302 DQ Delay:
4514 08:06:17.077813 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4515 08:06:17.080833 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4516 08:06:17.084550 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4517 08:06:17.087855 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4518 08:06:17.087937
4519 08:06:17.088002
4520 08:06:17.088062 ==
4521 08:06:17.090879 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 08:06:17.097515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 08:06:17.097598 ==
4524 08:06:17.097664
4525 08:06:17.097724
4526 08:06:17.097782 TX Vref Scan disable
4527 08:06:17.101783 == TX Byte 0 ==
4528 08:06:17.105064 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4529 08:06:17.108397 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4530 08:06:17.111639 == TX Byte 1 ==
4531 08:06:17.115244 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4532 08:06:17.118391 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4533 08:06:17.121604 ==
4534 08:06:17.125131 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 08:06:17.128157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 08:06:17.128239 ==
4537 08:06:17.128305
4538 08:06:17.128365
4539 08:06:17.131361 TX Vref Scan disable
4540 08:06:17.135171 == TX Byte 0 ==
4541 08:06:17.137859 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4542 08:06:17.141724 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4543 08:06:17.144761 == TX Byte 1 ==
4544 08:06:17.147742 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4545 08:06:17.151050 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4546 08:06:17.151133
4547 08:06:17.151198 [DATLAT]
4548 08:06:17.154288 Freq=600, CH1 RK0
4549 08:06:17.154371
4550 08:06:17.157722 DATLAT Default: 0x9
4551 08:06:17.157804 0, 0xFFFF, sum = 0
4552 08:06:17.161132 1, 0xFFFF, sum = 0
4553 08:06:17.161216 2, 0xFFFF, sum = 0
4554 08:06:17.164257 3, 0xFFFF, sum = 0
4555 08:06:17.164341 4, 0xFFFF, sum = 0
4556 08:06:17.167659 5, 0xFFFF, sum = 0
4557 08:06:17.167743 6, 0xFFFF, sum = 0
4558 08:06:17.171132 7, 0xFFFF, sum = 0
4559 08:06:17.171216 8, 0x0, sum = 1
4560 08:06:17.174231 9, 0x0, sum = 2
4561 08:06:17.174315 10, 0x0, sum = 3
4562 08:06:17.174383 11, 0x0, sum = 4
4563 08:06:17.177610 best_step = 9
4564 08:06:17.177692
4565 08:06:17.177757 ==
4566 08:06:17.180952 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 08:06:17.184476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 08:06:17.184560 ==
4569 08:06:17.187855 RX Vref Scan: 1
4570 08:06:17.187937
4571 08:06:17.188002 RX Vref 0 -> 0, step: 1
4572 08:06:17.190745
4573 08:06:17.190827 RX Delay -195 -> 252, step: 8
4574 08:06:17.190892
4575 08:06:17.194267 Set Vref, RX VrefLevel [Byte0]: 56
4576 08:06:17.197694 [Byte1]: 50
4577 08:06:17.202388
4578 08:06:17.202470 Final RX Vref Byte 0 = 56 to rank0
4579 08:06:17.205267 Final RX Vref Byte 1 = 50 to rank0
4580 08:06:17.208673 Final RX Vref Byte 0 = 56 to rank1
4581 08:06:17.211849 Final RX Vref Byte 1 = 50 to rank1==
4582 08:06:17.215255 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 08:06:17.222120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 08:06:17.222202 ==
4585 08:06:17.222268 DQS Delay:
4586 08:06:17.222328 DQS0 = 0, DQS1 = 0
4587 08:06:17.225458 DQM Delay:
4588 08:06:17.225541 DQM0 = 37, DQM1 = 28
4589 08:06:17.228726 DQ Delay:
4590 08:06:17.232392 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =32
4591 08:06:17.235113 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4592 08:06:17.238457 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4593 08:06:17.241738 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4594 08:06:17.241820
4595 08:06:17.241885
4596 08:06:17.248416 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4597 08:06:17.251750 CH1 RK0: MR19=808, MR18=2A37
4598 08:06:17.258487 CH1_RK0: MR19=0x808, MR18=0x2A37, DQSOSC=399, MR23=63, INC=164, DEC=109
4599 08:06:17.258571
4600 08:06:17.262099 ----->DramcWriteLeveling(PI) begin...
4601 08:06:17.262183 ==
4602 08:06:17.264878 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 08:06:17.268316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 08:06:17.268417 ==
4605 08:06:17.271628 Write leveling (Byte 0): 32 => 32
4606 08:06:17.275049 Write leveling (Byte 1): 28 => 28
4607 08:06:17.278415 DramcWriteLeveling(PI) end<-----
4608 08:06:17.278497
4609 08:06:17.278562 ==
4610 08:06:17.281659 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 08:06:17.285175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 08:06:17.285258 ==
4613 08:06:17.288601 [Gating] SW mode calibration
4614 08:06:17.294880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4615 08:06:17.301676 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4616 08:06:17.304842 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4617 08:06:17.311643 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 08:06:17.315188 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4619 08:06:17.318567 0 9 12 | B1->B0 | 3030 2727 | 1 0 | (1 0) (0 0)
4620 08:06:17.321453 0 9 16 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
4621 08:06:17.328563 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 08:06:17.331434 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 08:06:17.334561 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 08:06:17.341582 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 08:06:17.344589 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 08:06:17.347610 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 08:06:17.354775 0 10 12 | B1->B0 | 3535 4141 | 0 1 | (0 0) (0 0)
4628 08:06:17.358187 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 08:06:17.361528 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 08:06:17.367588 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 08:06:17.371263 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 08:06:17.374370 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 08:06:17.381049 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 08:06:17.384136 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 08:06:17.387441 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4636 08:06:17.394108 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 08:06:17.397746 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 08:06:17.401069 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 08:06:17.407561 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 08:06:17.410433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 08:06:17.413698 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 08:06:17.420540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 08:06:17.423926 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 08:06:17.427061 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 08:06:17.433874 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 08:06:17.437253 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 08:06:17.440661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 08:06:17.447393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 08:06:17.450926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 08:06:17.453895 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 08:06:17.460334 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4652 08:06:17.460416 Total UI for P1: 0, mck2ui 16
4653 08:06:17.467267 best dqsien dly found for B0: ( 0, 13, 10)
4654 08:06:17.470174 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4655 08:06:17.473383 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 08:06:17.476651 Total UI for P1: 0, mck2ui 16
4657 08:06:17.480192 best dqsien dly found for B1: ( 0, 13, 14)
4658 08:06:17.483965 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4659 08:06:17.487249 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4660 08:06:17.487332
4661 08:06:17.493866 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4662 08:06:17.496799 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4663 08:06:17.500239 [Gating] SW calibration Done
4664 08:06:17.500322 ==
4665 08:06:17.503535 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 08:06:17.507171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 08:06:17.507255 ==
4668 08:06:17.507320 RX Vref Scan: 0
4669 08:06:17.507381
4670 08:06:17.510048 RX Vref 0 -> 0, step: 1
4671 08:06:17.510130
4672 08:06:17.513743 RX Delay -230 -> 252, step: 16
4673 08:06:17.516660 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4674 08:06:17.520499 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4675 08:06:17.526785 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4676 08:06:17.530531 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4677 08:06:17.533564 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4678 08:06:17.536740 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4679 08:06:17.543669 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4680 08:06:17.546302 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4681 08:06:17.549836 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4682 08:06:17.553304 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4683 08:06:17.556644 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4684 08:06:17.563282 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4685 08:06:17.566436 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4686 08:06:17.569804 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4687 08:06:17.573193 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4688 08:06:17.580275 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4689 08:06:17.580356 ==
4690 08:06:17.583065 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 08:06:17.587006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 08:06:17.587083 ==
4693 08:06:17.587146 DQS Delay:
4694 08:06:17.589677 DQS0 = 0, DQS1 = 0
4695 08:06:17.589754 DQM Delay:
4696 08:06:17.593120 DQM0 = 36, DQM1 = 31
4697 08:06:17.593191 DQ Delay:
4698 08:06:17.596472 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4699 08:06:17.599836 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4700 08:06:17.603627 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4701 08:06:17.606281 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4702 08:06:17.606359
4703 08:06:17.606420
4704 08:06:17.606477 ==
4705 08:06:17.609785 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 08:06:17.613264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 08:06:17.616428 ==
4708 08:06:17.616499
4709 08:06:17.616565
4710 08:06:17.616623 TX Vref Scan disable
4711 08:06:17.619777 == TX Byte 0 ==
4712 08:06:17.622914 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4713 08:06:17.626332 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4714 08:06:17.629435 == TX Byte 1 ==
4715 08:06:17.632840 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4716 08:06:17.636432 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4717 08:06:17.639491 ==
4718 08:06:17.642655 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 08:06:17.645915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 08:06:17.646022 ==
4721 08:06:17.646114
4722 08:06:17.646206
4723 08:06:17.649309 TX Vref Scan disable
4724 08:06:17.649391 == TX Byte 0 ==
4725 08:06:17.656108 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4726 08:06:17.659881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4727 08:06:17.659962 == TX Byte 1 ==
4728 08:06:17.666104 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4729 08:06:17.669419 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4730 08:06:17.669500
4731 08:06:17.669564 [DATLAT]
4732 08:06:17.673021 Freq=600, CH1 RK1
4733 08:06:17.673102
4734 08:06:17.673167 DATLAT Default: 0x9
4735 08:06:17.676506 0, 0xFFFF, sum = 0
4736 08:06:17.676588 1, 0xFFFF, sum = 0
4737 08:06:17.679238 2, 0xFFFF, sum = 0
4738 08:06:17.682905 3, 0xFFFF, sum = 0
4739 08:06:17.682987 4, 0xFFFF, sum = 0
4740 08:06:17.686031 5, 0xFFFF, sum = 0
4741 08:06:17.686113 6, 0xFFFF, sum = 0
4742 08:06:17.689278 7, 0xFFFF, sum = 0
4743 08:06:17.689367 8, 0x0, sum = 1
4744 08:06:17.689434 9, 0x0, sum = 2
4745 08:06:17.692491 10, 0x0, sum = 3
4746 08:06:17.692573 11, 0x0, sum = 4
4747 08:06:17.696083 best_step = 9
4748 08:06:17.696164
4749 08:06:17.696227 ==
4750 08:06:17.699613 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 08:06:17.702843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 08:06:17.702924 ==
4753 08:06:17.705630 RX Vref Scan: 0
4754 08:06:17.705718
4755 08:06:17.705781 RX Vref 0 -> 0, step: 1
4756 08:06:17.705841
4757 08:06:17.708888 RX Delay -195 -> 252, step: 8
4758 08:06:17.716512 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4759 08:06:17.719873 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4760 08:06:17.723339 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4761 08:06:17.726542 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4762 08:06:17.733001 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4763 08:06:17.736180 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4764 08:06:17.739480 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4765 08:06:17.743166 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4766 08:06:17.749486 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4767 08:06:17.752834 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4768 08:06:17.756663 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4769 08:06:17.759194 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4770 08:06:17.762868 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4771 08:06:17.769603 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4772 08:06:17.772670 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4773 08:06:17.776068 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4774 08:06:17.776144 ==
4775 08:06:17.779478 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 08:06:17.785771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 08:06:17.785880 ==
4778 08:06:17.785972 DQS Delay:
4779 08:06:17.789347 DQS0 = 0, DQS1 = 0
4780 08:06:17.789444 DQM Delay:
4781 08:06:17.789532 DQM0 = 35, DQM1 = 29
4782 08:06:17.792775 DQ Delay:
4783 08:06:17.796013 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4784 08:06:17.799353 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =28
4785 08:06:17.802902 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4786 08:06:17.805686 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4787 08:06:17.805760
4788 08:06:17.805848
4789 08:06:17.812489 [DQSOSCAuto] RK1, (LSB)MR18= 0x3656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4790 08:06:17.815977 CH1 RK1: MR19=808, MR18=3656
4791 08:06:17.822660 CH1_RK1: MR19=0x808, MR18=0x3656, DQSOSC=393, MR23=63, INC=169, DEC=113
4792 08:06:17.826017 [RxdqsGatingPostProcess] freq 600
4793 08:06:17.829506 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 08:06:17.832341 Pre-setting of DQS Precalculation
4795 08:06:17.838962 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 08:06:17.845960 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 08:06:17.852344 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 08:06:17.852427
4799 08:06:17.852492
4800 08:06:17.855690 [Calibration Summary] 1200 Mbps
4801 08:06:17.855771 CH 0, Rank 0
4802 08:06:17.858917 SW Impedance : PASS
4803 08:06:17.862454 DUTY Scan : NO K
4804 08:06:17.862562 ZQ Calibration : PASS
4805 08:06:17.865588 Jitter Meter : NO K
4806 08:06:17.868866 CBT Training : PASS
4807 08:06:17.868947 Write leveling : PASS
4808 08:06:17.872446 RX DQS gating : PASS
4809 08:06:17.875398 RX DQ/DQS(RDDQC) : PASS
4810 08:06:17.875537 TX DQ/DQS : PASS
4811 08:06:17.879024 RX DATLAT : PASS
4812 08:06:17.879135 RX DQ/DQS(Engine): PASS
4813 08:06:17.882060 TX OE : NO K
4814 08:06:17.882173 All Pass.
4815 08:06:17.882268
4816 08:06:17.885731 CH 0, Rank 1
4817 08:06:17.885837 SW Impedance : PASS
4818 08:06:17.888652 DUTY Scan : NO K
4819 08:06:17.892498 ZQ Calibration : PASS
4820 08:06:17.892611 Jitter Meter : NO K
4821 08:06:17.895496 CBT Training : PASS
4822 08:06:17.899257 Write leveling : PASS
4823 08:06:17.899376 RX DQS gating : PASS
4824 08:06:17.901949 RX DQ/DQS(RDDQC) : PASS
4825 08:06:17.905287 TX DQ/DQS : PASS
4826 08:06:17.905390 RX DATLAT : PASS
4827 08:06:17.908993 RX DQ/DQS(Engine): PASS
4828 08:06:17.912588 TX OE : NO K
4829 08:06:17.912670 All Pass.
4830 08:06:17.912734
4831 08:06:17.912794 CH 1, Rank 0
4832 08:06:17.915842 SW Impedance : PASS
4833 08:06:17.918800 DUTY Scan : NO K
4834 08:06:17.918880 ZQ Calibration : PASS
4835 08:06:17.922246 Jitter Meter : NO K
4836 08:06:17.925466 CBT Training : PASS
4837 08:06:17.925541 Write leveling : PASS
4838 08:06:17.928728 RX DQS gating : PASS
4839 08:06:17.928807 RX DQ/DQS(RDDQC) : PASS
4840 08:06:17.932230 TX DQ/DQS : PASS
4841 08:06:17.935651 RX DATLAT : PASS
4842 08:06:17.935722 RX DQ/DQS(Engine): PASS
4843 08:06:17.938936 TX OE : NO K
4844 08:06:17.939068 All Pass.
4845 08:06:17.939156
4846 08:06:17.941859 CH 1, Rank 1
4847 08:06:17.941957 SW Impedance : PASS
4848 08:06:17.945658 DUTY Scan : NO K
4849 08:06:17.948687 ZQ Calibration : PASS
4850 08:06:17.948761 Jitter Meter : NO K
4851 08:06:17.951980 CBT Training : PASS
4852 08:06:17.955253 Write leveling : PASS
4853 08:06:17.955331 RX DQS gating : PASS
4854 08:06:17.958866 RX DQ/DQS(RDDQC) : PASS
4855 08:06:17.962299 TX DQ/DQS : PASS
4856 08:06:17.962403 RX DATLAT : PASS
4857 08:06:17.965757 RX DQ/DQS(Engine): PASS
4858 08:06:17.968717 TX OE : NO K
4859 08:06:17.968799 All Pass.
4860 08:06:17.968864
4861 08:06:17.968925 DramC Write-DBI off
4862 08:06:17.972060 PER_BANK_REFRESH: Hybrid Mode
4863 08:06:17.975213 TX_TRACKING: ON
4864 08:06:17.982123 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 08:06:17.985604 [FAST_K] Save calibration result to emmc
4866 08:06:17.991733 dramc_set_vcore_voltage set vcore to 662500
4867 08:06:17.991811 Read voltage for 933, 3
4868 08:06:17.995265 Vio18 = 0
4869 08:06:17.995340 Vcore = 662500
4870 08:06:17.995453 Vdram = 0
4871 08:06:17.995516 Vddq = 0
4872 08:06:17.998631 Vmddr = 0
4873 08:06:18.002188 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 08:06:18.008652 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 08:06:18.011796 MEM_TYPE=3, freq_sel=17
4876 08:06:18.011872 sv_algorithm_assistance_LP4_1600
4877 08:06:18.018759 ============ PULL DRAM RESETB DOWN ============
4878 08:06:18.021924 ========== PULL DRAM RESETB DOWN end =========
4879 08:06:18.025063 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 08:06:18.028454 ===================================
4881 08:06:18.031838 LPDDR4 DRAM CONFIGURATION
4882 08:06:18.035249 ===================================
4883 08:06:18.038944 EX_ROW_EN[0] = 0x0
4884 08:06:18.039025 EX_ROW_EN[1] = 0x0
4885 08:06:18.041650 LP4Y_EN = 0x0
4886 08:06:18.041731 WORK_FSP = 0x0
4887 08:06:18.045143 WL = 0x3
4888 08:06:18.045224 RL = 0x3
4889 08:06:18.048064 BL = 0x2
4890 08:06:18.048143 RPST = 0x0
4891 08:06:18.051771 RD_PRE = 0x0
4892 08:06:18.051844 WR_PRE = 0x1
4893 08:06:18.055028 WR_PST = 0x0
4894 08:06:18.055110 DBI_WR = 0x0
4895 08:06:18.058459 DBI_RD = 0x0
4896 08:06:18.061427 OTF = 0x1
4897 08:06:18.064584 ===================================
4898 08:06:18.068077 ===================================
4899 08:06:18.068151 ANA top config
4900 08:06:18.071497 ===================================
4901 08:06:18.074347 DLL_ASYNC_EN = 0
4902 08:06:18.077832 ALL_SLAVE_EN = 1
4903 08:06:18.077907 NEW_RANK_MODE = 1
4904 08:06:18.081824 DLL_IDLE_MODE = 1
4905 08:06:18.084679 LP45_APHY_COMB_EN = 1
4906 08:06:18.087734 TX_ODT_DIS = 1
4907 08:06:18.087846 NEW_8X_MODE = 1
4908 08:06:18.091284 ===================================
4909 08:06:18.095028 ===================================
4910 08:06:18.097596 data_rate = 1866
4911 08:06:18.100891 CKR = 1
4912 08:06:18.104337 DQ_P2S_RATIO = 8
4913 08:06:18.107754 ===================================
4914 08:06:18.111120 CA_P2S_RATIO = 8
4915 08:06:18.114747 DQ_CA_OPEN = 0
4916 08:06:18.114828 DQ_SEMI_OPEN = 0
4917 08:06:18.117480 CA_SEMI_OPEN = 0
4918 08:06:18.120833 CA_FULL_RATE = 0
4919 08:06:18.124014 DQ_CKDIV4_EN = 1
4920 08:06:18.127924 CA_CKDIV4_EN = 1
4921 08:06:18.130893 CA_PREDIV_EN = 0
4922 08:06:18.130966 PH8_DLY = 0
4923 08:06:18.133893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 08:06:18.137660 DQ_AAMCK_DIV = 4
4925 08:06:18.140716 CA_AAMCK_DIV = 4
4926 08:06:18.143999 CA_ADMCK_DIV = 4
4927 08:06:18.147841 DQ_TRACK_CA_EN = 0
4928 08:06:18.150918 CA_PICK = 933
4929 08:06:18.150992 CA_MCKIO = 933
4930 08:06:18.154259 MCKIO_SEMI = 0
4931 08:06:18.157689 PLL_FREQ = 3732
4932 08:06:18.160940 DQ_UI_PI_RATIO = 32
4933 08:06:18.163633 CA_UI_PI_RATIO = 0
4934 08:06:18.167324 ===================================
4935 08:06:18.170650 ===================================
4936 08:06:18.173747 memory_type:LPDDR4
4937 08:06:18.173828 GP_NUM : 10
4938 08:06:18.176945 SRAM_EN : 1
4939 08:06:18.177025 MD32_EN : 0
4940 08:06:18.180389 ===================================
4941 08:06:18.184025 [ANA_INIT] >>>>>>>>>>>>>>
4942 08:06:18.187166 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 08:06:18.190728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 08:06:18.193461 ===================================
4945 08:06:18.196662 data_rate = 1866,PCW = 0X8f00
4946 08:06:18.200012 ===================================
4947 08:06:18.203099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 08:06:18.209989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 08:06:18.212984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 08:06:18.220378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 08:06:18.223695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 08:06:18.227011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 08:06:18.227084 [ANA_INIT] flow start
4954 08:06:18.229985 [ANA_INIT] PLL >>>>>>>>
4955 08:06:18.233463 [ANA_INIT] PLL <<<<<<<<
4956 08:06:18.233562 [ANA_INIT] MIDPI >>>>>>>>
4957 08:06:18.237026 [ANA_INIT] MIDPI <<<<<<<<
4958 08:06:18.240268 [ANA_INIT] DLL >>>>>>>>
4959 08:06:18.240342 [ANA_INIT] flow end
4960 08:06:18.246632 ============ LP4 DIFF to SE enter ============
4961 08:06:18.249824 ============ LP4 DIFF to SE exit ============
4962 08:06:18.253445 [ANA_INIT] <<<<<<<<<<<<<
4963 08:06:18.256381 [Flow] Enable top DCM control >>>>>
4964 08:06:18.259861 [Flow] Enable top DCM control <<<<<
4965 08:06:18.259937 Enable DLL master slave shuffle
4966 08:06:18.266445 ==============================================================
4967 08:06:18.269496 Gating Mode config
4968 08:06:18.273124 ==============================================================
4969 08:06:18.276519 Config description:
4970 08:06:18.286381 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 08:06:18.292975 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 08:06:18.296209 SELPH_MODE 0: By rank 1: By Phase
4973 08:06:18.302955 ==============================================================
4974 08:06:18.306258 GAT_TRACK_EN = 1
4975 08:06:18.309579 RX_GATING_MODE = 2
4976 08:06:18.312825 RX_GATING_TRACK_MODE = 2
4977 08:06:18.315906 SELPH_MODE = 1
4978 08:06:18.316004 PICG_EARLY_EN = 1
4979 08:06:18.319485 VALID_LAT_VALUE = 1
4980 08:06:18.326306 ==============================================================
4981 08:06:18.329381 Enter into Gating configuration >>>>
4982 08:06:18.332603 Exit from Gating configuration <<<<
4983 08:06:18.335732 Enter into DVFS_PRE_config >>>>>
4984 08:06:18.346164 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 08:06:18.349235 Exit from DVFS_PRE_config <<<<<
4986 08:06:18.353003 Enter into PICG configuration >>>>
4987 08:06:18.355607 Exit from PICG configuration <<<<
4988 08:06:18.359252 [RX_INPUT] configuration >>>>>
4989 08:06:18.362479 [RX_INPUT] configuration <<<<<
4990 08:06:18.365738 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 08:06:18.372896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 08:06:18.379617 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 08:06:18.385573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 08:06:18.392195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 08:06:18.399024 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 08:06:18.402437 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 08:06:18.405607 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 08:06:18.409043 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 08:06:18.412208 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 08:06:18.418589 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 08:06:18.422119 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 08:06:18.425849 ===================================
5003 08:06:18.428624 LPDDR4 DRAM CONFIGURATION
5004 08:06:18.431884 ===================================
5005 08:06:18.431957 EX_ROW_EN[0] = 0x0
5006 08:06:18.435202 EX_ROW_EN[1] = 0x0
5007 08:06:18.435299 LP4Y_EN = 0x0
5008 08:06:18.438851 WORK_FSP = 0x0
5009 08:06:18.438929 WL = 0x3
5010 08:06:18.441960 RL = 0x3
5011 08:06:18.445320 BL = 0x2
5012 08:06:18.445393 RPST = 0x0
5013 08:06:18.448560 RD_PRE = 0x0
5014 08:06:18.448636 WR_PRE = 0x1
5015 08:06:18.451907 WR_PST = 0x0
5016 08:06:18.451985 DBI_WR = 0x0
5017 08:06:18.455083 DBI_RD = 0x0
5018 08:06:18.455194 OTF = 0x1
5019 08:06:18.458741 ===================================
5020 08:06:18.461842 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 08:06:18.468772 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 08:06:18.472034 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 08:06:18.475411 ===================================
5024 08:06:18.478593 LPDDR4 DRAM CONFIGURATION
5025 08:06:18.481814 ===================================
5026 08:06:18.481907 EX_ROW_EN[0] = 0x10
5027 08:06:18.484906 EX_ROW_EN[1] = 0x0
5028 08:06:18.484984 LP4Y_EN = 0x0
5029 08:06:18.488390 WORK_FSP = 0x0
5030 08:06:18.488462 WL = 0x3
5031 08:06:18.491523 RL = 0x3
5032 08:06:18.491601 BL = 0x2
5033 08:06:18.494742 RPST = 0x0
5034 08:06:18.498231 RD_PRE = 0x0
5035 08:06:18.498359 WR_PRE = 0x1
5036 08:06:18.501856 WR_PST = 0x0
5037 08:06:18.501998 DBI_WR = 0x0
5038 08:06:18.505049 DBI_RD = 0x0
5039 08:06:18.505188 OTF = 0x1
5040 08:06:18.508269 ===================================
5041 08:06:18.514761 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 08:06:18.518430 nWR fixed to 30
5043 08:06:18.521948 [ModeRegInit_LP4] CH0 RK0
5044 08:06:18.522024 [ModeRegInit_LP4] CH0 RK1
5045 08:06:18.525356 [ModeRegInit_LP4] CH1 RK0
5046 08:06:18.528561 [ModeRegInit_LP4] CH1 RK1
5047 08:06:18.528636 match AC timing 9
5048 08:06:18.535324 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 08:06:18.538671 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 08:06:18.542439 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 08:06:18.548361 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 08:06:18.551933 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 08:06:18.552014 ==
5054 08:06:18.555138 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 08:06:18.558113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 08:06:18.558218 ==
5057 08:06:18.565255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 08:06:18.571986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5059 08:06:18.575185 [CA 0] Center 38 (8~69) winsize 62
5060 08:06:18.578722 [CA 1] Center 38 (7~69) winsize 63
5061 08:06:18.582045 [CA 2] Center 35 (5~66) winsize 62
5062 08:06:18.585005 [CA 3] Center 35 (5~66) winsize 62
5063 08:06:18.588608 [CA 4] Center 34 (4~65) winsize 62
5064 08:06:18.591993 [CA 5] Center 33 (3~64) winsize 62
5065 08:06:18.592079
5066 08:06:18.594981 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5067 08:06:18.595061
5068 08:06:18.598269 [CATrainingPosCal] consider 1 rank data
5069 08:06:18.601669 u2DelayCellTimex100 = 270/100 ps
5070 08:06:18.605363 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5071 08:06:18.608655 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5072 08:06:18.611680 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5073 08:06:18.614670 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5074 08:06:18.618499 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5075 08:06:18.624659 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 08:06:18.624746
5077 08:06:18.627885 CA PerBit enable=1, Macro0, CA PI delay=33
5078 08:06:18.627995
5079 08:06:18.630983 [CBTSetCACLKResult] CA Dly = 33
5080 08:06:18.631055 CS Dly: 6 (0~37)
5081 08:06:18.631125 ==
5082 08:06:18.634735 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 08:06:18.638106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 08:06:18.641214 ==
5085 08:06:18.644384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 08:06:18.651770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5087 08:06:18.655190 [CA 0] Center 38 (8~69) winsize 62
5088 08:06:18.658328 [CA 1] Center 38 (7~69) winsize 63
5089 08:06:18.660945 [CA 2] Center 35 (5~66) winsize 62
5090 08:06:18.664843 [CA 3] Center 35 (5~66) winsize 62
5091 08:06:18.668065 [CA 4] Center 34 (4~65) winsize 62
5092 08:06:18.671045 [CA 5] Center 33 (3~64) winsize 62
5093 08:06:18.671149
5094 08:06:18.674261 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5095 08:06:18.674369
5096 08:06:18.677657 [CATrainingPosCal] consider 2 rank data
5097 08:06:18.680956 u2DelayCellTimex100 = 270/100 ps
5098 08:06:18.684648 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5099 08:06:18.687516 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5100 08:06:18.691015 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5101 08:06:18.697722 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5102 08:06:18.700904 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5103 08:06:18.704100 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5104 08:06:18.704175
5105 08:06:18.707754 CA PerBit enable=1, Macro0, CA PI delay=33
5106 08:06:18.707861
5107 08:06:18.711312 [CBTSetCACLKResult] CA Dly = 33
5108 08:06:18.711455 CS Dly: 7 (0~39)
5109 08:06:18.711521
5110 08:06:18.714529 ----->DramcWriteLeveling(PI) begin...
5111 08:06:18.714637 ==
5112 08:06:18.717997 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 08:06:18.724179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 08:06:18.724349 ==
5115 08:06:18.727300 Write leveling (Byte 0): 29 => 29
5116 08:06:18.731265 Write leveling (Byte 1): 30 => 30
5117 08:06:18.731398 DramcWriteLeveling(PI) end<-----
5118 08:06:18.734219
5119 08:06:18.734317 ==
5120 08:06:18.737406 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 08:06:18.740736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 08:06:18.740817 ==
5123 08:06:18.743847 [Gating] SW mode calibration
5124 08:06:18.750581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 08:06:18.753977 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 08:06:18.760669 0 14 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5127 08:06:18.763752 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5128 08:06:18.767781 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 08:06:18.773830 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 08:06:18.777374 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 08:06:18.780702 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 08:06:18.787075 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5133 08:06:18.790842 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5134 08:06:18.794088 0 15 0 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (1 1)
5135 08:06:18.800303 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5136 08:06:18.803861 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 08:06:18.806852 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 08:06:18.813747 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 08:06:18.816991 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 08:06:18.820457 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 08:06:18.827129 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 08:06:18.830318 1 0 0 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (0 0)
5143 08:06:18.833468 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5144 08:06:18.840309 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 08:06:18.844119 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 08:06:18.847007 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 08:06:18.853263 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 08:06:18.856626 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 08:06:18.860237 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5150 08:06:18.866607 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5151 08:06:18.870415 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 08:06:18.873433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 08:06:18.880160 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 08:06:18.883327 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 08:06:18.886633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 08:06:18.893251 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 08:06:18.896809 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 08:06:18.900007 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 08:06:18.903081 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 08:06:18.909746 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 08:06:18.913290 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 08:06:18.916940 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 08:06:18.923187 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 08:06:18.926499 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 08:06:18.929653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5166 08:06:18.936555 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5167 08:06:18.939545 Total UI for P1: 0, mck2ui 16
5168 08:06:18.942891 best dqsien dly found for B0: ( 1, 2, 28)
5169 08:06:18.946492 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5170 08:06:18.949802 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 08:06:18.953124 Total UI for P1: 0, mck2ui 16
5172 08:06:18.956221 best dqsien dly found for B1: ( 1, 3, 4)
5173 08:06:18.959822 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5174 08:06:18.962856 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5175 08:06:18.966072
5176 08:06:18.969353 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5177 08:06:18.972767 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5178 08:06:18.976202 [Gating] SW calibration Done
5179 08:06:18.976284 ==
5180 08:06:18.979981 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 08:06:18.983137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 08:06:18.983220 ==
5183 08:06:18.983285 RX Vref Scan: 0
5184 08:06:18.983346
5185 08:06:18.985837 RX Vref 0 -> 0, step: 1
5186 08:06:18.985975
5187 08:06:18.989600 RX Delay -80 -> 252, step: 8
5188 08:06:18.992410 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5189 08:06:18.995765 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5190 08:06:18.999105 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5191 08:06:19.006012 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5192 08:06:19.009672 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5193 08:06:19.012427 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5194 08:06:19.015706 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5195 08:06:19.019107 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5196 08:06:19.025909 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5197 08:06:19.028963 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5198 08:06:19.032222 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5199 08:06:19.036121 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5200 08:06:19.039064 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5201 08:06:19.045898 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5202 08:06:19.049151 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5203 08:06:19.052635 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5204 08:06:19.052718 ==
5205 08:06:19.055983 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 08:06:19.059116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 08:06:19.059200 ==
5208 08:06:19.062374 DQS Delay:
5209 08:06:19.062457 DQS0 = 0, DQS1 = 0
5210 08:06:19.065286 DQM Delay:
5211 08:06:19.065369 DQM0 = 94, DQM1 = 84
5212 08:06:19.065449 DQ Delay:
5213 08:06:19.068554 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5214 08:06:19.072272 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5215 08:06:19.075426 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5216 08:06:19.079012 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5217 08:06:19.079096
5218 08:06:19.079162
5219 08:06:19.082057 ==
5220 08:06:19.085267 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 08:06:19.088583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 08:06:19.088667 ==
5223 08:06:19.088734
5224 08:06:19.088795
5225 08:06:19.092021 TX Vref Scan disable
5226 08:06:19.092104 == TX Byte 0 ==
5227 08:06:19.098878 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5228 08:06:19.101750 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5229 08:06:19.101865 == TX Byte 1 ==
5230 08:06:19.108624 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5231 08:06:19.112372 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5232 08:06:19.112455 ==
5233 08:06:19.115338 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 08:06:19.118723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 08:06:19.118805 ==
5236 08:06:19.118869
5237 08:06:19.118928
5238 08:06:19.121624 TX Vref Scan disable
5239 08:06:19.125126 == TX Byte 0 ==
5240 08:06:19.128385 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5241 08:06:19.131557 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5242 08:06:19.134891 == TX Byte 1 ==
5243 08:06:19.138207 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5244 08:06:19.141582 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5245 08:06:19.141694
5246 08:06:19.144875 [DATLAT]
5247 08:06:19.144964 Freq=933, CH0 RK0
5248 08:06:19.145065
5249 08:06:19.148463 DATLAT Default: 0xd
5250 08:06:19.148544 0, 0xFFFF, sum = 0
5251 08:06:19.151669 1, 0xFFFF, sum = 0
5252 08:06:19.151753 2, 0xFFFF, sum = 0
5253 08:06:19.154958 3, 0xFFFF, sum = 0
5254 08:06:19.155040 4, 0xFFFF, sum = 0
5255 08:06:19.158148 5, 0xFFFF, sum = 0
5256 08:06:19.158231 6, 0xFFFF, sum = 0
5257 08:06:19.161710 7, 0xFFFF, sum = 0
5258 08:06:19.161793 8, 0xFFFF, sum = 0
5259 08:06:19.165172 9, 0xFFFF, sum = 0
5260 08:06:19.165255 10, 0x0, sum = 1
5261 08:06:19.168215 11, 0x0, sum = 2
5262 08:06:19.168297 12, 0x0, sum = 3
5263 08:06:19.171669 13, 0x0, sum = 4
5264 08:06:19.171751 best_step = 11
5265 08:06:19.171816
5266 08:06:19.171876 ==
5267 08:06:19.175284 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 08:06:19.181413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 08:06:19.181521 ==
5270 08:06:19.181618 RX Vref Scan: 1
5271 08:06:19.181711
5272 08:06:19.184874 RX Vref 0 -> 0, step: 1
5273 08:06:19.184983
5274 08:06:19.188275 RX Delay -69 -> 252, step: 4
5275 08:06:19.188357
5276 08:06:19.191722 Set Vref, RX VrefLevel [Byte0]: 62
5277 08:06:19.194445 [Byte1]: 48
5278 08:06:19.194551
5279 08:06:19.197714 Final RX Vref Byte 0 = 62 to rank0
5280 08:06:19.201141 Final RX Vref Byte 1 = 48 to rank0
5281 08:06:19.204797 Final RX Vref Byte 0 = 62 to rank1
5282 08:06:19.208306 Final RX Vref Byte 1 = 48 to rank1==
5283 08:06:19.211052 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 08:06:19.214565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 08:06:19.214647 ==
5286 08:06:19.218107 DQS Delay:
5287 08:06:19.218189 DQS0 = 0, DQS1 = 0
5288 08:06:19.218253 DQM Delay:
5289 08:06:19.221529 DQM0 = 95, DQM1 = 83
5290 08:06:19.221611 DQ Delay:
5291 08:06:19.224349 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5292 08:06:19.227589 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5293 08:06:19.231181 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =76
5294 08:06:19.234042 DQ12 =86, DQ13 =88, DQ14 =98, DQ15 =90
5295 08:06:19.234148
5296 08:06:19.234244
5297 08:06:19.244320 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5298 08:06:19.247195 CH0 RK0: MR19=505, MR18=1111
5299 08:06:19.253834 CH0_RK0: MR19=0x505, MR18=0x1111, DQSOSC=416, MR23=63, INC=62, DEC=41
5300 08:06:19.253929
5301 08:06:19.257276 ----->DramcWriteLeveling(PI) begin...
5302 08:06:19.257360 ==
5303 08:06:19.260902 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 08:06:19.263875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 08:06:19.263980 ==
5306 08:06:19.267473 Write leveling (Byte 0): 30 => 30
5307 08:06:19.270918 Write leveling (Byte 1): 30 => 30
5308 08:06:19.273912 DramcWriteLeveling(PI) end<-----
5309 08:06:19.273990
5310 08:06:19.274050 ==
5311 08:06:19.277486 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 08:06:19.280962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 08:06:19.281034 ==
5314 08:06:19.284197 [Gating] SW mode calibration
5315 08:06:19.290650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 08:06:19.297403 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 08:06:19.300879 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5318 08:06:19.304070 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 08:06:19.310660 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 08:06:19.314130 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 08:06:19.317615 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 08:06:19.324354 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 08:06:19.327028 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 08:06:19.330360 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5325 08:06:19.337225 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
5326 08:06:19.340284 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 08:06:19.344248 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 08:06:19.347183 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 08:06:19.353604 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 08:06:19.356963 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 08:06:19.360471 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 08:06:19.367499 0 15 28 | B1->B0 | 2929 3434 | 0 1 | (0 0) (0 0)
5333 08:06:19.370500 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5334 08:06:19.374038 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 08:06:19.380633 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 08:06:19.383623 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 08:06:19.386854 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 08:06:19.393460 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 08:06:19.396818 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 08:06:19.400523 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5341 08:06:19.407173 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 08:06:19.410532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 08:06:19.413378 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 08:06:19.420188 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 08:06:19.423771 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 08:06:19.426974 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 08:06:19.433881 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 08:06:19.436720 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 08:06:19.440015 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 08:06:19.446724 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 08:06:19.449711 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 08:06:19.453391 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 08:06:19.460063 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 08:06:19.463582 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 08:06:19.466636 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 08:06:19.473328 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 08:06:19.473404 Total UI for P1: 0, mck2ui 16
5358 08:06:19.479478 best dqsien dly found for B0: ( 1, 2, 26)
5359 08:06:19.483281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 08:06:19.486883 Total UI for P1: 0, mck2ui 16
5361 08:06:19.489586 best dqsien dly found for B1: ( 1, 2, 28)
5362 08:06:19.493317 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5363 08:06:19.497542 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5364 08:06:19.497616
5365 08:06:19.499655 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5366 08:06:19.503014 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5367 08:06:19.506821 [Gating] SW calibration Done
5368 08:06:19.506903 ==
5369 08:06:19.509628 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 08:06:19.512786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 08:06:19.516477 ==
5372 08:06:19.516552 RX Vref Scan: 0
5373 08:06:19.516615
5374 08:06:19.519340 RX Vref 0 -> 0, step: 1
5375 08:06:19.519466
5376 08:06:19.522378 RX Delay -80 -> 252, step: 8
5377 08:06:19.525754 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5378 08:06:19.529325 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5379 08:06:19.532665 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5380 08:06:19.536037 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5381 08:06:19.539331 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5382 08:06:19.546478 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5383 08:06:19.549121 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5384 08:06:19.552540 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5385 08:06:19.556256 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5386 08:06:19.559321 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5387 08:06:19.566105 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5388 08:06:19.569389 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5389 08:06:19.572793 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5390 08:06:19.575819 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5391 08:06:19.578960 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5392 08:06:19.585812 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5393 08:06:19.585916 ==
5394 08:06:19.589405 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 08:06:19.592276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 08:06:19.592353 ==
5397 08:06:19.592416 DQS Delay:
5398 08:06:19.595698 DQS0 = 0, DQS1 = 0
5399 08:06:19.595806 DQM Delay:
5400 08:06:19.599199 DQM0 = 91, DQM1 = 82
5401 08:06:19.599297 DQ Delay:
5402 08:06:19.602659 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5403 08:06:19.605408 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5404 08:06:19.608669 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5405 08:06:19.612712 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5406 08:06:19.612814
5407 08:06:19.612904
5408 08:06:19.612990 ==
5409 08:06:19.615811 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 08:06:19.618948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 08:06:19.619046 ==
5412 08:06:19.623518
5413 08:06:19.623593
5414 08:06:19.623680 TX Vref Scan disable
5415 08:06:19.625597 == TX Byte 0 ==
5416 08:06:19.629001 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5417 08:06:19.632399 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5418 08:06:19.635291 == TX Byte 1 ==
5419 08:06:19.638894 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5420 08:06:19.642288 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5421 08:06:19.642404 ==
5422 08:06:19.645586 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 08:06:19.652079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 08:06:19.652161 ==
5425 08:06:19.652226
5426 08:06:19.652292
5427 08:06:19.652358 TX Vref Scan disable
5428 08:06:19.656215 == TX Byte 0 ==
5429 08:06:19.659577 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5430 08:06:19.666508 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5431 08:06:19.666600 == TX Byte 1 ==
5432 08:06:19.669404 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5433 08:06:19.676180 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5434 08:06:19.676255
5435 08:06:19.676317 [DATLAT]
5436 08:06:19.676375 Freq=933, CH0 RK1
5437 08:06:19.676458
5438 08:06:19.679516 DATLAT Default: 0xb
5439 08:06:19.679616 0, 0xFFFF, sum = 0
5440 08:06:19.682917 1, 0xFFFF, sum = 0
5441 08:06:19.686128 2, 0xFFFF, sum = 0
5442 08:06:19.686232 3, 0xFFFF, sum = 0
5443 08:06:19.689742 4, 0xFFFF, sum = 0
5444 08:06:19.689881 5, 0xFFFF, sum = 0
5445 08:06:19.693013 6, 0xFFFF, sum = 0
5446 08:06:19.693106 7, 0xFFFF, sum = 0
5447 08:06:19.695898 8, 0xFFFF, sum = 0
5448 08:06:19.696006 9, 0xFFFF, sum = 0
5449 08:06:19.699334 10, 0x0, sum = 1
5450 08:06:19.699461 11, 0x0, sum = 2
5451 08:06:19.702836 12, 0x0, sum = 3
5452 08:06:19.702934 13, 0x0, sum = 4
5453 08:06:19.703024 best_step = 11
5454 08:06:19.703109
5455 08:06:19.706490 ==
5456 08:06:19.709251 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 08:06:19.712524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 08:06:19.712605 ==
5459 08:06:19.712670 RX Vref Scan: 0
5460 08:06:19.712729
5461 08:06:19.716068 RX Vref 0 -> 0, step: 1
5462 08:06:19.716148
5463 08:06:19.719149 RX Delay -77 -> 252, step: 4
5464 08:06:19.725747 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5465 08:06:19.729275 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5466 08:06:19.732654 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5467 08:06:19.736082 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5468 08:06:19.738977 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5469 08:06:19.742362 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5470 08:06:19.748684 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5471 08:06:19.752015 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5472 08:06:19.755354 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5473 08:06:19.758858 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5474 08:06:19.761957 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5475 08:06:19.769180 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5476 08:06:19.772299 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5477 08:06:19.774982 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5478 08:06:19.778984 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5479 08:06:19.782188 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5480 08:06:19.785538 ==
5481 08:06:19.788292 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 08:06:19.791804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 08:06:19.791906 ==
5484 08:06:19.791997 DQS Delay:
5485 08:06:19.795059 DQS0 = 0, DQS1 = 0
5486 08:06:19.795156 DQM Delay:
5487 08:06:19.798553 DQM0 = 92, DQM1 = 84
5488 08:06:19.798626 DQ Delay:
5489 08:06:19.801575 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5490 08:06:19.804999 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5491 08:06:19.808358 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =78
5492 08:06:19.811440 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5493 08:06:19.811514
5494 08:06:19.811577
5495 08:06:19.817976 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5496 08:06:19.821615 CH0 RK1: MR19=505, MR18=2D0F
5497 08:06:19.827986 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5498 08:06:19.831324 [RxdqsGatingPostProcess] freq 933
5499 08:06:19.838018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5500 08:06:19.841722 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 08:06:19.841822 best DQS1 dly(2T, 0.5T) = (0, 11)
5502 08:06:19.844644 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 08:06:19.847677 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5504 08:06:19.851122 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 08:06:19.854815 best DQS1 dly(2T, 0.5T) = (0, 10)
5506 08:06:19.857731 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 08:06:19.860785 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5508 08:06:19.864286 Pre-setting of DQS Precalculation
5509 08:06:19.871278 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5510 08:06:19.871397 ==
5511 08:06:19.874133 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 08:06:19.877577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 08:06:19.877652 ==
5514 08:06:19.884607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 08:06:19.890580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5516 08:06:19.894144 [CA 0] Center 37 (7~68) winsize 62
5517 08:06:19.897457 [CA 1] Center 37 (7~68) winsize 62
5518 08:06:19.901083 [CA 2] Center 34 (5~64) winsize 60
5519 08:06:19.904033 [CA 3] Center 34 (4~64) winsize 61
5520 08:06:19.907048 [CA 4] Center 34 (5~64) winsize 60
5521 08:06:19.910524 [CA 5] Center 34 (4~64) winsize 61
5522 08:06:19.910630
5523 08:06:19.913673 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5524 08:06:19.913773
5525 08:06:19.917332 [CATrainingPosCal] consider 1 rank data
5526 08:06:19.920315 u2DelayCellTimex100 = 270/100 ps
5527 08:06:19.923715 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5528 08:06:19.927187 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5529 08:06:19.930313 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5530 08:06:19.933548 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5531 08:06:19.936899 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5532 08:06:19.940594 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5533 08:06:19.940669
5534 08:06:19.943884 CA PerBit enable=1, Macro0, CA PI delay=34
5535 08:06:19.946958
5536 08:06:19.947033 [CBTSetCACLKResult] CA Dly = 34
5537 08:06:19.950141 CS Dly: 6 (0~37)
5538 08:06:19.950215 ==
5539 08:06:19.953684 Dram Type= 6, Freq= 0, CH_1, rank 1
5540 08:06:19.957317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 08:06:19.957389 ==
5542 08:06:19.963527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 08:06:19.970507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5544 08:06:19.973363 [CA 0] Center 38 (8~68) winsize 61
5545 08:06:19.977123 [CA 1] Center 37 (7~68) winsize 62
5546 08:06:19.980085 [CA 2] Center 35 (5~65) winsize 61
5547 08:06:19.983571 [CA 3] Center 34 (4~64) winsize 61
5548 08:06:19.986566 [CA 4] Center 35 (5~65) winsize 61
5549 08:06:19.989999 [CA 5] Center 33 (3~64) winsize 62
5550 08:06:19.990080
5551 08:06:19.993561 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5552 08:06:19.993643
5553 08:06:19.996213 [CATrainingPosCal] consider 2 rank data
5554 08:06:19.999693 u2DelayCellTimex100 = 270/100 ps
5555 08:06:20.003051 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5556 08:06:20.006546 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5557 08:06:20.009860 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5558 08:06:20.012917 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5559 08:06:20.016278 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5560 08:06:20.019663 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5561 08:06:20.022838
5562 08:06:20.026202 CA PerBit enable=1, Macro0, CA PI delay=34
5563 08:06:20.026315
5564 08:06:20.029654 [CBTSetCACLKResult] CA Dly = 34
5565 08:06:20.029777 CS Dly: 7 (0~39)
5566 08:06:20.029883
5567 08:06:20.032770 ----->DramcWriteLeveling(PI) begin...
5568 08:06:20.032862 ==
5569 08:06:20.036494 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 08:06:20.039251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 08:06:20.042757 ==
5572 08:06:20.042832 Write leveling (Byte 0): 25 => 25
5573 08:06:20.045808 Write leveling (Byte 1): 27 => 27
5574 08:06:20.049222 DramcWriteLeveling(PI) end<-----
5575 08:06:20.049295
5576 08:06:20.049356 ==
5577 08:06:20.052565 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 08:06:20.059124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 08:06:20.059200 ==
5580 08:06:20.062668 [Gating] SW mode calibration
5581 08:06:20.069685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5582 08:06:20.072698 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5583 08:06:20.079025 0 14 0 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
5584 08:06:20.082144 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 08:06:20.085439 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 08:06:20.092354 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 08:06:20.095591 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 08:06:20.099023 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 08:06:20.105474 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 08:06:20.108960 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 1)
5591 08:06:20.112105 0 15 0 | B1->B0 | 2525 2424 | 0 1 | (0 0) (1 0)
5592 08:06:20.118838 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 08:06:20.122128 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 08:06:20.125068 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 08:06:20.132025 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 08:06:20.134875 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 08:06:20.138391 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 08:06:20.144988 0 15 28 | B1->B0 | 3030 3434 | 0 1 | (0 0) (0 0)
5599 08:06:20.148431 1 0 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
5600 08:06:20.151778 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 08:06:20.158584 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 08:06:20.161630 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 08:06:20.165165 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 08:06:20.171657 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 08:06:20.175069 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5606 08:06:20.178468 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5607 08:06:20.184721 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 08:06:20.187966 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 08:06:20.191331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 08:06:20.198050 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 08:06:20.201216 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 08:06:20.204783 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 08:06:20.208057 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 08:06:20.214372 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 08:06:20.217762 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 08:06:20.224429 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 08:06:20.227519 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 08:06:20.230987 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 08:06:20.237608 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 08:06:20.241314 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 08:06:20.244233 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 08:06:20.247585 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5623 08:06:20.250970 Total UI for P1: 0, mck2ui 16
5624 08:06:20.254471 best dqsien dly found for B1: ( 1, 2, 26)
5625 08:06:20.260997 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5626 08:06:20.264358 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 08:06:20.267285 Total UI for P1: 0, mck2ui 16
5628 08:06:20.270732 best dqsien dly found for B0: ( 1, 2, 30)
5629 08:06:20.274172 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5630 08:06:20.277223 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5631 08:06:20.277304
5632 08:06:20.280539 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5633 08:06:20.287022 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5634 08:06:20.287104 [Gating] SW calibration Done
5635 08:06:20.287169 ==
5636 08:06:20.290319 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 08:06:20.297143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 08:06:20.297224 ==
5639 08:06:20.297288 RX Vref Scan: 0
5640 08:06:20.297348
5641 08:06:20.300711 RX Vref 0 -> 0, step: 1
5642 08:06:20.300792
5643 08:06:20.303606 RX Delay -80 -> 252, step: 8
5644 08:06:20.307351 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5645 08:06:20.310065 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5646 08:06:20.313474 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5647 08:06:20.320335 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5648 08:06:20.323779 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5649 08:06:20.326980 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5650 08:06:20.330053 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5651 08:06:20.333246 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5652 08:06:20.336907 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5653 08:06:20.343624 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5654 08:06:20.346748 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5655 08:06:20.350276 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5656 08:06:20.353663 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5657 08:06:20.356504 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5658 08:06:20.363160 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5659 08:06:20.366742 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5660 08:06:20.366849 ==
5661 08:06:20.369898 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 08:06:20.373178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 08:06:20.373263 ==
5664 08:06:20.376834 DQS Delay:
5665 08:06:20.376915 DQS0 = 0, DQS1 = 0
5666 08:06:20.376978 DQM Delay:
5667 08:06:20.379815 DQM0 = 94, DQM1 = 85
5668 08:06:20.379902 DQ Delay:
5669 08:06:20.383129 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5670 08:06:20.386316 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5671 08:06:20.389715 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5672 08:06:20.392930 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5673 08:06:20.393011
5674 08:06:20.393075
5675 08:06:20.393134 ==
5676 08:06:20.396315 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 08:06:20.402630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 08:06:20.402711 ==
5679 08:06:20.402774
5680 08:06:20.402834
5681 08:06:20.402890 TX Vref Scan disable
5682 08:06:20.406932 == TX Byte 0 ==
5683 08:06:20.409954 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5684 08:06:20.413541 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5685 08:06:20.416310 == TX Byte 1 ==
5686 08:06:20.420152 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5687 08:06:20.423254 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5688 08:06:20.426784 ==
5689 08:06:20.429779 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 08:06:20.433098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 08:06:20.433206 ==
5692 08:06:20.433298
5693 08:06:20.433385
5694 08:06:20.436466 TX Vref Scan disable
5695 08:06:20.436546 == TX Byte 0 ==
5696 08:06:20.442961 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5697 08:06:20.446508 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5698 08:06:20.446601 == TX Byte 1 ==
5699 08:06:20.453204 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5700 08:06:20.456572 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5701 08:06:20.456653
5702 08:06:20.456718 [DATLAT]
5703 08:06:20.460039 Freq=933, CH1 RK0
5704 08:06:20.460121
5705 08:06:20.460184 DATLAT Default: 0xd
5706 08:06:20.463291 0, 0xFFFF, sum = 0
5707 08:06:20.463423 1, 0xFFFF, sum = 0
5708 08:06:20.466539 2, 0xFFFF, sum = 0
5709 08:06:20.466621 3, 0xFFFF, sum = 0
5710 08:06:20.469597 4, 0xFFFF, sum = 0
5711 08:06:20.469680 5, 0xFFFF, sum = 0
5712 08:06:20.472784 6, 0xFFFF, sum = 0
5713 08:06:20.475971 7, 0xFFFF, sum = 0
5714 08:06:20.476074 8, 0xFFFF, sum = 0
5715 08:06:20.479687 9, 0xFFFF, sum = 0
5716 08:06:20.479769 10, 0x0, sum = 1
5717 08:06:20.479834 11, 0x0, sum = 2
5718 08:06:20.482767 12, 0x0, sum = 3
5719 08:06:20.482848 13, 0x0, sum = 4
5720 08:06:20.486068 best_step = 11
5721 08:06:20.486149
5722 08:06:20.486213 ==
5723 08:06:20.489272 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 08:06:20.492962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 08:06:20.493044 ==
5726 08:06:20.496242 RX Vref Scan: 1
5727 08:06:20.496370
5728 08:06:20.496469 RX Vref 0 -> 0, step: 1
5729 08:06:20.499121
5730 08:06:20.499237 RX Delay -69 -> 252, step: 4
5731 08:06:20.499330
5732 08:06:20.502496 Set Vref, RX VrefLevel [Byte0]: 56
5733 08:06:20.505878 [Byte1]: 50
5734 08:06:20.510302
5735 08:06:20.510408 Final RX Vref Byte 0 = 56 to rank0
5736 08:06:20.513995 Final RX Vref Byte 1 = 50 to rank0
5737 08:06:20.517140 Final RX Vref Byte 0 = 56 to rank1
5738 08:06:20.520807 Final RX Vref Byte 1 = 50 to rank1==
5739 08:06:20.523978 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 08:06:20.530368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 08:06:20.530468 ==
5742 08:06:20.530558 DQS Delay:
5743 08:06:20.530636 DQS0 = 0, DQS1 = 0
5744 08:06:20.534023 DQM Delay:
5745 08:06:20.534121 DQM0 = 96, DQM1 = 89
5746 08:06:20.537061 DQ Delay:
5747 08:06:20.540496 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =92
5748 08:06:20.544154 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5749 08:06:20.547564 DQ8 =80, DQ9 =82, DQ10 =88, DQ11 =82
5750 08:06:20.550294 DQ12 =100, DQ13 =94, DQ14 =94, DQ15 =94
5751 08:06:20.550390
5752 08:06:20.550459
5753 08:06:20.557227 [DQSOSCAuto] RK0, (LSB)MR18= 0x9, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5754 08:06:20.560259 CH1 RK0: MR19=505, MR18=9
5755 08:06:20.567056 CH1_RK0: MR19=0x505, MR18=0x9, DQSOSC=419, MR23=63, INC=61, DEC=41
5756 08:06:20.567164
5757 08:06:20.570334 ----->DramcWriteLeveling(PI) begin...
5758 08:06:20.570419 ==
5759 08:06:20.573503 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 08:06:20.577093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 08:06:20.577196 ==
5762 08:06:20.580448 Write leveling (Byte 0): 26 => 26
5763 08:06:20.583328 Write leveling (Byte 1): 27 => 27
5764 08:06:20.586881 DramcWriteLeveling(PI) end<-----
5765 08:06:20.586992
5766 08:06:20.587059 ==
5767 08:06:20.590682 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 08:06:20.593879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 08:06:20.593966 ==
5770 08:06:20.596783 [Gating] SW mode calibration
5771 08:06:20.603524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 08:06:20.609862 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 08:06:20.613326 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5774 08:06:20.616937 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 08:06:20.623532 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 08:06:20.626896 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 08:06:20.629971 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 08:06:20.637009 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 08:06:20.639727 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 0)
5780 08:06:20.643379 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
5781 08:06:20.650114 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 08:06:20.653589 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 08:06:20.656945 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 08:06:20.663690 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 08:06:20.666403 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 08:06:20.669882 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 08:06:20.676735 0 15 24 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
5788 08:06:20.679768 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5789 08:06:20.683016 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 08:06:20.689565 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 08:06:20.693105 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 08:06:20.696296 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 08:06:20.700097 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 08:06:20.706506 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 08:06:20.709997 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5796 08:06:20.713083 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5797 08:06:20.719598 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 08:06:20.723057 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 08:06:20.726171 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 08:06:20.733052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 08:06:20.736164 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 08:06:20.739667 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 08:06:20.746093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 08:06:20.749704 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 08:06:20.752848 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 08:06:20.759331 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 08:06:20.763049 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 08:06:20.765900 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 08:06:20.772898 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 08:06:20.776349 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 08:06:20.779277 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5812 08:06:20.785900 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 08:06:20.789174 Total UI for P1: 0, mck2ui 16
5814 08:06:20.792557 best dqsien dly found for B0: ( 1, 2, 24)
5815 08:06:20.792640 Total UI for P1: 0, mck2ui 16
5816 08:06:20.799321 best dqsien dly found for B1: ( 1, 2, 26)
5817 08:06:20.802503 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5818 08:06:20.806097 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5819 08:06:20.806181
5820 08:06:20.809289 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5821 08:06:20.812824 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5822 08:06:20.816289 [Gating] SW calibration Done
5823 08:06:20.816372 ==
5824 08:06:20.819153 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 08:06:20.822324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 08:06:20.822407 ==
5827 08:06:20.826042 RX Vref Scan: 0
5828 08:06:20.826125
5829 08:06:20.826190 RX Vref 0 -> 0, step: 1
5830 08:06:20.826252
5831 08:06:20.828803 RX Delay -80 -> 252, step: 8
5832 08:06:20.832107 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5833 08:06:20.839076 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5834 08:06:20.842193 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5835 08:06:20.845686 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5836 08:06:20.848732 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5837 08:06:20.852157 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5838 08:06:20.855703 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5839 08:06:20.862300 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5840 08:06:20.865229 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5841 08:06:20.868784 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5842 08:06:20.872171 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5843 08:06:20.875646 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5844 08:06:20.882598 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5845 08:06:20.885916 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5846 08:06:20.888718 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5847 08:06:20.892012 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5848 08:06:20.892095 ==
5849 08:06:20.895321 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 08:06:20.898685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 08:06:20.898766 ==
5852 08:06:20.902323 DQS Delay:
5853 08:06:20.902434 DQS0 = 0, DQS1 = 0
5854 08:06:20.905284 DQM Delay:
5855 08:06:20.905391 DQM0 = 94, DQM1 = 88
5856 08:06:20.905481 DQ Delay:
5857 08:06:20.908765 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5858 08:06:20.912450 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5859 08:06:20.915393 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5860 08:06:20.918913 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5861 08:06:20.918999
5862 08:06:20.921972
5863 08:06:20.922043 ==
5864 08:06:20.925194 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 08:06:20.928675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 08:06:20.928747 ==
5867 08:06:20.928808
5868 08:06:20.928865
5869 08:06:20.931842 TX Vref Scan disable
5870 08:06:20.931921 == TX Byte 0 ==
5871 08:06:20.938385 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5872 08:06:20.942086 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5873 08:06:20.942183 == TX Byte 1 ==
5874 08:06:20.948308 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5875 08:06:20.951883 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5876 08:06:20.951956 ==
5877 08:06:20.955025 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 08:06:20.958526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 08:06:20.958596 ==
5880 08:06:20.958665
5881 08:06:20.958776
5882 08:06:20.961889 TX Vref Scan disable
5883 08:06:20.965142 == TX Byte 0 ==
5884 08:06:20.968556 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5885 08:06:20.971449 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5886 08:06:20.975315 == TX Byte 1 ==
5887 08:06:20.978329 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5888 08:06:20.981655 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5889 08:06:20.981728
5890 08:06:20.984953 [DATLAT]
5891 08:06:20.985094 Freq=933, CH1 RK1
5892 08:06:20.985201
5893 08:06:20.988349 DATLAT Default: 0xb
5894 08:06:20.988423 0, 0xFFFF, sum = 0
5895 08:06:20.991821 1, 0xFFFF, sum = 0
5896 08:06:20.991899 2, 0xFFFF, sum = 0
5897 08:06:20.995171 3, 0xFFFF, sum = 0
5898 08:06:20.995248 4, 0xFFFF, sum = 0
5899 08:06:20.998041 5, 0xFFFF, sum = 0
5900 08:06:20.998117 6, 0xFFFF, sum = 0
5901 08:06:21.001443 7, 0xFFFF, sum = 0
5902 08:06:21.001520 8, 0xFFFF, sum = 0
5903 08:06:21.004861 9, 0xFFFF, sum = 0
5904 08:06:21.004966 10, 0x0, sum = 1
5905 08:06:21.008304 11, 0x0, sum = 2
5906 08:06:21.008387 12, 0x0, sum = 3
5907 08:06:21.011675 13, 0x0, sum = 4
5908 08:06:21.011756 best_step = 11
5909 08:06:21.011820
5910 08:06:21.011879 ==
5911 08:06:21.015034 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 08:06:21.021341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 08:06:21.021486 ==
5914 08:06:21.021554 RX Vref Scan: 0
5915 08:06:21.021614
5916 08:06:21.024944 RX Vref 0 -> 0, step: 1
5917 08:06:21.025024
5918 08:06:21.028482 RX Delay -69 -> 252, step: 4
5919 08:06:21.031347 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5920 08:06:21.034838 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5921 08:06:21.041530 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5922 08:06:21.044653 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5923 08:06:21.048149 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5924 08:06:21.051680 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5925 08:06:21.054772 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5926 08:06:21.058046 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5927 08:06:21.064261 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5928 08:06:21.067905 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5929 08:06:21.071332 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5930 08:06:21.074748 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5931 08:06:21.077622 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5932 08:06:21.084547 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5933 08:06:21.087709 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5934 08:06:21.091153 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5935 08:06:21.091259 ==
5936 08:06:21.094716 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 08:06:21.097898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 08:06:21.098009 ==
5939 08:06:21.101370 DQS Delay:
5940 08:06:21.101450 DQS0 = 0, DQS1 = 0
5941 08:06:21.101514 DQM Delay:
5942 08:06:21.104447 DQM0 = 91, DQM1 = 91
5943 08:06:21.104534 DQ Delay:
5944 08:06:21.107716 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
5945 08:06:21.111027 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
5946 08:06:21.114383 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5947 08:06:21.117962 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =98
5948 08:06:21.118042
5949 08:06:21.118105
5950 08:06:21.127766 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5951 08:06:21.127848 CH1 RK1: MR19=505, MR18=D21
5952 08:06:21.134521 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
5953 08:06:21.137320 [RxdqsGatingPostProcess] freq 933
5954 08:06:21.144017 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5955 08:06:21.147668 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 08:06:21.150859 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 08:06:21.153896 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 08:06:21.157382 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 08:06:21.160994 best DQS0 dly(2T, 0.5T) = (0, 10)
5960 08:06:21.163982 best DQS1 dly(2T, 0.5T) = (0, 10)
5961 08:06:21.167470 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5962 08:06:21.167582 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5963 08:06:21.170865 Pre-setting of DQS Precalculation
5964 08:06:21.177394 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5965 08:06:21.183939 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5966 08:06:21.190607 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5967 08:06:21.190689
5968 08:06:21.190753
5969 08:06:21.193820 [Calibration Summary] 1866 Mbps
5970 08:06:21.197247 CH 0, Rank 0
5971 08:06:21.197328 SW Impedance : PASS
5972 08:06:21.200593 DUTY Scan : NO K
5973 08:06:21.203794 ZQ Calibration : PASS
5974 08:06:21.203875 Jitter Meter : NO K
5975 08:06:21.207043 CBT Training : PASS
5976 08:06:21.210356 Write leveling : PASS
5977 08:06:21.210452 RX DQS gating : PASS
5978 08:06:21.213351 RX DQ/DQS(RDDQC) : PASS
5979 08:06:21.213460 TX DQ/DQS : PASS
5980 08:06:21.216612 RX DATLAT : PASS
5981 08:06:21.220134 RX DQ/DQS(Engine): PASS
5982 08:06:21.220215 TX OE : NO K
5983 08:06:21.223326 All Pass.
5984 08:06:21.223443
5985 08:06:21.223508 CH 0, Rank 1
5986 08:06:21.226689 SW Impedance : PASS
5987 08:06:21.226770 DUTY Scan : NO K
5988 08:06:21.230479 ZQ Calibration : PASS
5989 08:06:21.234011 Jitter Meter : NO K
5990 08:06:21.234092 CBT Training : PASS
5991 08:06:21.237024 Write leveling : PASS
5992 08:06:21.240149 RX DQS gating : PASS
5993 08:06:21.240231 RX DQ/DQS(RDDQC) : PASS
5994 08:06:21.243266 TX DQ/DQS : PASS
5995 08:06:21.246673 RX DATLAT : PASS
5996 08:06:21.246756 RX DQ/DQS(Engine): PASS
5997 08:06:21.250072 TX OE : NO K
5998 08:06:21.250155 All Pass.
5999 08:06:21.250220
6000 08:06:21.253249 CH 1, Rank 0
6001 08:06:21.253331 SW Impedance : PASS
6002 08:06:21.256765 DUTY Scan : NO K
6003 08:06:21.259972 ZQ Calibration : PASS
6004 08:06:21.260054 Jitter Meter : NO K
6005 08:06:21.263583 CBT Training : PASS
6006 08:06:21.266991 Write leveling : PASS
6007 08:06:21.267074 RX DQS gating : PASS
6008 08:06:21.270020 RX DQ/DQS(RDDQC) : PASS
6009 08:06:21.270102 TX DQ/DQS : PASS
6010 08:06:21.273266 RX DATLAT : PASS
6011 08:06:21.276746 RX DQ/DQS(Engine): PASS
6012 08:06:21.276828 TX OE : NO K
6013 08:06:21.280134 All Pass.
6014 08:06:21.280216
6015 08:06:21.280281 CH 1, Rank 1
6016 08:06:21.283443 SW Impedance : PASS
6017 08:06:21.283526 DUTY Scan : NO K
6018 08:06:21.286428 ZQ Calibration : PASS
6019 08:06:21.289911 Jitter Meter : NO K
6020 08:06:21.289993 CBT Training : PASS
6021 08:06:21.293640 Write leveling : PASS
6022 08:06:21.296752 RX DQS gating : PASS
6023 08:06:21.296834 RX DQ/DQS(RDDQC) : PASS
6024 08:06:21.299995 TX DQ/DQS : PASS
6025 08:06:21.303093 RX DATLAT : PASS
6026 08:06:21.303175 RX DQ/DQS(Engine): PASS
6027 08:06:21.307084 TX OE : NO K
6028 08:06:21.307167 All Pass.
6029 08:06:21.307233
6030 08:06:21.309757 DramC Write-DBI off
6031 08:06:21.313353 PER_BANK_REFRESH: Hybrid Mode
6032 08:06:21.313436 TX_TRACKING: ON
6033 08:06:21.322956 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6034 08:06:21.326515 [FAST_K] Save calibration result to emmc
6035 08:06:21.329720 dramc_set_vcore_voltage set vcore to 650000
6036 08:06:21.333133 Read voltage for 400, 6
6037 08:06:21.333215 Vio18 = 0
6038 08:06:21.333280 Vcore = 650000
6039 08:06:21.336476 Vdram = 0
6040 08:06:21.336558 Vddq = 0
6041 08:06:21.336623 Vmddr = 0
6042 08:06:21.342900 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6043 08:06:21.346196 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6044 08:06:21.349562 MEM_TYPE=3, freq_sel=20
6045 08:06:21.353216 sv_algorithm_assistance_LP4_800
6046 08:06:21.356377 ============ PULL DRAM RESETB DOWN ============
6047 08:06:21.359906 ========== PULL DRAM RESETB DOWN end =========
6048 08:06:21.366396 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6049 08:06:21.369752 ===================================
6050 08:06:21.369835 LPDDR4 DRAM CONFIGURATION
6051 08:06:21.372878 ===================================
6052 08:06:21.376189 EX_ROW_EN[0] = 0x0
6053 08:06:21.379486 EX_ROW_EN[1] = 0x0
6054 08:06:21.379569 LP4Y_EN = 0x0
6055 08:06:21.382949 WORK_FSP = 0x0
6056 08:06:21.383031 WL = 0x2
6057 08:06:21.386099 RL = 0x2
6058 08:06:21.386181 BL = 0x2
6059 08:06:21.389339 RPST = 0x0
6060 08:06:21.389422 RD_PRE = 0x0
6061 08:06:21.392781 WR_PRE = 0x1
6062 08:06:21.392864 WR_PST = 0x0
6063 08:06:21.396016 DBI_WR = 0x0
6064 08:06:21.396098 DBI_RD = 0x0
6065 08:06:21.399377 OTF = 0x1
6066 08:06:21.402969 ===================================
6067 08:06:21.406194 ===================================
6068 08:06:21.406276 ANA top config
6069 08:06:21.409191 ===================================
6070 08:06:21.412759 DLL_ASYNC_EN = 0
6071 08:06:21.415910 ALL_SLAVE_EN = 1
6072 08:06:21.419738 NEW_RANK_MODE = 1
6073 08:06:21.419821 DLL_IDLE_MODE = 1
6074 08:06:21.422465 LP45_APHY_COMB_EN = 1
6075 08:06:21.425833 TX_ODT_DIS = 1
6076 08:06:21.429248 NEW_8X_MODE = 1
6077 08:06:21.432457 ===================================
6078 08:06:21.435597 ===================================
6079 08:06:21.439152 data_rate = 800
6080 08:06:21.439234 CKR = 1
6081 08:06:21.442216 DQ_P2S_RATIO = 4
6082 08:06:21.445492 ===================================
6083 08:06:21.448976 CA_P2S_RATIO = 4
6084 08:06:21.452807 DQ_CA_OPEN = 0
6085 08:06:21.455341 DQ_SEMI_OPEN = 1
6086 08:06:21.458947 CA_SEMI_OPEN = 1
6087 08:06:21.459030 CA_FULL_RATE = 0
6088 08:06:21.461909 DQ_CKDIV4_EN = 0
6089 08:06:21.465692 CA_CKDIV4_EN = 1
6090 08:06:21.468705 CA_PREDIV_EN = 0
6091 08:06:21.472188 PH8_DLY = 0
6092 08:06:21.476003 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6093 08:06:21.476085 DQ_AAMCK_DIV = 0
6094 08:06:21.478637 CA_AAMCK_DIV = 0
6095 08:06:21.482270 CA_ADMCK_DIV = 4
6096 08:06:21.485705 DQ_TRACK_CA_EN = 0
6097 08:06:21.488821 CA_PICK = 800
6098 08:06:21.492580 CA_MCKIO = 400
6099 08:06:21.495438 MCKIO_SEMI = 400
6100 08:06:21.495519 PLL_FREQ = 3016
6101 08:06:21.498715 DQ_UI_PI_RATIO = 32
6102 08:06:21.501731 CA_UI_PI_RATIO = 32
6103 08:06:21.505109 ===================================
6104 08:06:21.508763 ===================================
6105 08:06:21.512286 memory_type:LPDDR4
6106 08:06:21.515689 GP_NUM : 10
6107 08:06:21.515770 SRAM_EN : 1
6108 08:06:21.519181 MD32_EN : 0
6109 08:06:21.521707 ===================================
6110 08:06:21.521788 [ANA_INIT] >>>>>>>>>>>>>>
6111 08:06:21.525405 <<<<<< [CONFIGURE PHASE]: ANA_TX
6112 08:06:21.528359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6113 08:06:21.531813 ===================================
6114 08:06:21.535005 data_rate = 800,PCW = 0X7400
6115 08:06:21.538241 ===================================
6116 08:06:21.541430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6117 08:06:21.548616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 08:06:21.558563 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 08:06:21.564814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6120 08:06:21.568148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6121 08:06:21.571449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6122 08:06:21.571533 [ANA_INIT] flow start
6123 08:06:21.574734 [ANA_INIT] PLL >>>>>>>>
6124 08:06:21.578500 [ANA_INIT] PLL <<<<<<<<
6125 08:06:21.578582 [ANA_INIT] MIDPI >>>>>>>>
6126 08:06:21.581681 [ANA_INIT] MIDPI <<<<<<<<
6127 08:06:21.584702 [ANA_INIT] DLL >>>>>>>>
6128 08:06:21.584785 [ANA_INIT] flow end
6129 08:06:21.591428 ============ LP4 DIFF to SE enter ============
6130 08:06:21.594561 ============ LP4 DIFF to SE exit ============
6131 08:06:21.598317 [ANA_INIT] <<<<<<<<<<<<<
6132 08:06:21.601405 [Flow] Enable top DCM control >>>>>
6133 08:06:21.604560 [Flow] Enable top DCM control <<<<<
6134 08:06:21.604645 Enable DLL master slave shuffle
6135 08:06:21.611292 ==============================================================
6136 08:06:21.614934 Gating Mode config
6137 08:06:21.618222 ==============================================================
6138 08:06:21.621230 Config description:
6139 08:06:21.631214 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6140 08:06:21.638182 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6141 08:06:21.640998 SELPH_MODE 0: By rank 1: By Phase
6142 08:06:21.647599 ==============================================================
6143 08:06:21.651281 GAT_TRACK_EN = 0
6144 08:06:21.654525 RX_GATING_MODE = 2
6145 08:06:21.657612 RX_GATING_TRACK_MODE = 2
6146 08:06:21.660997 SELPH_MODE = 1
6147 08:06:21.661070 PICG_EARLY_EN = 1
6148 08:06:21.664854 VALID_LAT_VALUE = 1
6149 08:06:21.671469 ==============================================================
6150 08:06:21.674409 Enter into Gating configuration >>>>
6151 08:06:21.677766 Exit from Gating configuration <<<<
6152 08:06:21.681506 Enter into DVFS_PRE_config >>>>>
6153 08:06:21.691107 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6154 08:06:21.694502 Exit from DVFS_PRE_config <<<<<
6155 08:06:21.697658 Enter into PICG configuration >>>>
6156 08:06:21.701042 Exit from PICG configuration <<<<
6157 08:06:21.704318 [RX_INPUT] configuration >>>>>
6158 08:06:21.708165 [RX_INPUT] configuration <<<<<
6159 08:06:21.711080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6160 08:06:21.717927 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6161 08:06:21.724495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6162 08:06:21.731477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6163 08:06:21.737767 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 08:06:21.741344 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 08:06:21.747456 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6166 08:06:21.751049 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6167 08:06:21.754047 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6168 08:06:21.757759 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6169 08:06:21.764029 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6170 08:06:21.767554 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 08:06:21.770616 ===================================
6172 08:06:21.773835 LPDDR4 DRAM CONFIGURATION
6173 08:06:21.777445 ===================================
6174 08:06:21.777527 EX_ROW_EN[0] = 0x0
6175 08:06:21.780452 EX_ROW_EN[1] = 0x0
6176 08:06:21.780534 LP4Y_EN = 0x0
6177 08:06:21.783682 WORK_FSP = 0x0
6178 08:06:21.783763 WL = 0x2
6179 08:06:21.787370 RL = 0x2
6180 08:06:21.790319 BL = 0x2
6181 08:06:21.790426 RPST = 0x0
6182 08:06:21.793831 RD_PRE = 0x0
6183 08:06:21.793939 WR_PRE = 0x1
6184 08:06:21.797001 WR_PST = 0x0
6185 08:06:21.797083 DBI_WR = 0x0
6186 08:06:21.800231 DBI_RD = 0x0
6187 08:06:21.800313 OTF = 0x1
6188 08:06:21.803661 ===================================
6189 08:06:21.807079 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6190 08:06:21.813598 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6191 08:06:21.816738 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6192 08:06:21.820408 ===================================
6193 08:06:21.823562 LPDDR4 DRAM CONFIGURATION
6194 08:06:21.826564 ===================================
6195 08:06:21.826644 EX_ROW_EN[0] = 0x10
6196 08:06:21.830026 EX_ROW_EN[1] = 0x0
6197 08:06:21.830107 LP4Y_EN = 0x0
6198 08:06:21.833346 WORK_FSP = 0x0
6199 08:06:21.833426 WL = 0x2
6200 08:06:21.837019 RL = 0x2
6201 08:06:21.837100 BL = 0x2
6202 08:06:21.839845 RPST = 0x0
6203 08:06:21.843177 RD_PRE = 0x0
6204 08:06:21.843258 WR_PRE = 0x1
6205 08:06:21.846440 WR_PST = 0x0
6206 08:06:21.846520 DBI_WR = 0x0
6207 08:06:21.849915 DBI_RD = 0x0
6208 08:06:21.849995 OTF = 0x1
6209 08:06:21.853307 ===================================
6210 08:06:21.860125 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6211 08:06:21.863883 nWR fixed to 30
6212 08:06:21.867525 [ModeRegInit_LP4] CH0 RK0
6213 08:06:21.867614 [ModeRegInit_LP4] CH0 RK1
6214 08:06:21.870256 [ModeRegInit_LP4] CH1 RK0
6215 08:06:21.873502 [ModeRegInit_LP4] CH1 RK1
6216 08:06:21.873594 match AC timing 19
6217 08:06:21.880207 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6218 08:06:21.883593 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6219 08:06:21.886896 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6220 08:06:21.893469 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6221 08:06:21.896877 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6222 08:06:21.896959 ==
6223 08:06:21.900037 Dram Type= 6, Freq= 0, CH_0, rank 0
6224 08:06:21.904166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 08:06:21.904247 ==
6226 08:06:21.910299 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 08:06:21.916722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6228 08:06:21.920397 [CA 0] Center 36 (8~64) winsize 57
6229 08:06:21.923382 [CA 1] Center 36 (8~64) winsize 57
6230 08:06:21.926792 [CA 2] Center 36 (8~64) winsize 57
6231 08:06:21.926873 [CA 3] Center 36 (8~64) winsize 57
6232 08:06:21.930237 [CA 4] Center 36 (8~64) winsize 57
6233 08:06:21.933413 [CA 5] Center 36 (8~64) winsize 57
6234 08:06:21.933493
6235 08:06:21.937018 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6236 08:06:21.940412
6237 08:06:21.943410 [CATrainingPosCal] consider 1 rank data
6238 08:06:21.943509 u2DelayCellTimex100 = 270/100 ps
6239 08:06:21.950393 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 08:06:21.953879 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 08:06:21.956627 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 08:06:21.960162 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 08:06:21.963820 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 08:06:21.966504 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 08:06:21.966586
6246 08:06:21.970181 CA PerBit enable=1, Macro0, CA PI delay=36
6247 08:06:21.970294
6248 08:06:21.973556 [CBTSetCACLKResult] CA Dly = 36
6249 08:06:21.976670 CS Dly: 1 (0~32)
6250 08:06:21.976750 ==
6251 08:06:21.979906 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 08:06:21.983284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 08:06:21.983365 ==
6254 08:06:21.990261 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 08:06:21.993738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6256 08:06:21.996311 [CA 0] Center 36 (8~64) winsize 57
6257 08:06:21.999962 [CA 1] Center 36 (8~64) winsize 57
6258 08:06:22.003051 [CA 2] Center 36 (8~64) winsize 57
6259 08:06:22.006476 [CA 3] Center 36 (8~64) winsize 57
6260 08:06:22.009779 [CA 4] Center 36 (8~64) winsize 57
6261 08:06:22.013018 [CA 5] Center 36 (8~64) winsize 57
6262 08:06:22.013100
6263 08:06:22.016806 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6264 08:06:22.016888
6265 08:06:22.019866 [CATrainingPosCal] consider 2 rank data
6266 08:06:22.023343 u2DelayCellTimex100 = 270/100 ps
6267 08:06:22.026560 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 08:06:22.029700 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 08:06:22.036432 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 08:06:22.040070 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 08:06:22.043292 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 08:06:22.046560 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 08:06:22.046641
6274 08:06:22.050227 CA PerBit enable=1, Macro0, CA PI delay=36
6275 08:06:22.050309
6276 08:06:22.053130 [CBTSetCACLKResult] CA Dly = 36
6277 08:06:22.053212 CS Dly: 1 (0~32)
6278 08:06:22.053277
6279 08:06:22.056500 ----->DramcWriteLeveling(PI) begin...
6280 08:06:22.059456 ==
6281 08:06:22.062675 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 08:06:22.066035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 08:06:22.066118 ==
6284 08:06:22.069444 Write leveling (Byte 0): 40 => 8
6285 08:06:22.072832 Write leveling (Byte 1): 40 => 8
6286 08:06:22.076276 DramcWriteLeveling(PI) end<-----
6287 08:06:22.076357
6288 08:06:22.076421 ==
6289 08:06:22.079435 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 08:06:22.082817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 08:06:22.082899 ==
6292 08:06:22.086341 [Gating] SW mode calibration
6293 08:06:22.092279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6294 08:06:22.099278 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6295 08:06:22.102816 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 08:06:22.106069 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 08:06:22.112519 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 08:06:22.115787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 08:06:22.118927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 08:06:22.122614 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 08:06:22.128837 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 08:06:22.132725 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 08:06:22.135721 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 08:06:22.138956 Total UI for P1: 0, mck2ui 16
6305 08:06:22.142669 best dqsien dly found for B0: ( 0, 14, 24)
6306 08:06:22.145696 Total UI for P1: 0, mck2ui 16
6307 08:06:22.149160 best dqsien dly found for B1: ( 0, 14, 24)
6308 08:06:22.152443 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6309 08:06:22.158957 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6310 08:06:22.159039
6311 08:06:22.161898 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 08:06:22.165430 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 08:06:22.169156 [Gating] SW calibration Done
6314 08:06:22.169263 ==
6315 08:06:22.172061 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 08:06:22.175325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 08:06:22.175443 ==
6318 08:06:22.178699 RX Vref Scan: 0
6319 08:06:22.178783
6320 08:06:22.178853 RX Vref 0 -> 0, step: 1
6321 08:06:22.178914
6322 08:06:22.182180 RX Delay -410 -> 252, step: 16
6323 08:06:22.185127 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6324 08:06:22.191795 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6325 08:06:22.195154 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6326 08:06:22.198875 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6327 08:06:22.202023 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6328 08:06:22.208300 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6329 08:06:22.211477 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6330 08:06:22.215011 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6331 08:06:22.218055 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6332 08:06:22.224830 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6333 08:06:22.228389 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6334 08:06:22.231494 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6335 08:06:22.238414 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6336 08:06:22.241516 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6337 08:06:22.244945 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6338 08:06:22.248445 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6339 08:06:22.248740 ==
6340 08:06:22.251909 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 08:06:22.258106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 08:06:22.258580 ==
6343 08:06:22.258913 DQS Delay:
6344 08:06:22.261650 DQS0 = 59, DQS1 = 59
6345 08:06:22.262109 DQM Delay:
6346 08:06:22.265187 DQM0 = 17, DQM1 = 9
6347 08:06:22.265633 DQ Delay:
6348 08:06:22.268786 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6349 08:06:22.271513 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6350 08:06:22.274747 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6351 08:06:22.278449 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6352 08:06:22.278865
6353 08:06:22.279197
6354 08:06:22.279554 ==
6355 08:06:22.282302 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 08:06:22.285135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 08:06:22.285601 ==
6358 08:06:22.285966
6359 08:06:22.286302
6360 08:06:22.288147 TX Vref Scan disable
6361 08:06:22.288617 == TX Byte 0 ==
6362 08:06:22.295043 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 08:06:22.298369 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 08:06:22.298633 == TX Byte 1 ==
6365 08:06:22.304626 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 08:06:22.308154 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 08:06:22.308236 ==
6368 08:06:22.311475 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 08:06:22.314351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 08:06:22.314442 ==
6371 08:06:22.314507
6372 08:06:22.314567
6373 08:06:22.317990 TX Vref Scan disable
6374 08:06:22.318079 == TX Byte 0 ==
6375 08:06:22.324874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 08:06:22.327723 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 08:06:22.327805 == TX Byte 1 ==
6378 08:06:22.334511 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 08:06:22.337982 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 08:06:22.338067
6381 08:06:22.338132 [DATLAT]
6382 08:06:22.340877 Freq=400, CH0 RK0
6383 08:06:22.340958
6384 08:06:22.341022 DATLAT Default: 0xf
6385 08:06:22.344266 0, 0xFFFF, sum = 0
6386 08:06:22.344349 1, 0xFFFF, sum = 0
6387 08:06:22.347945 2, 0xFFFF, sum = 0
6388 08:06:22.348028 3, 0xFFFF, sum = 0
6389 08:06:22.350744 4, 0xFFFF, sum = 0
6390 08:06:22.350827 5, 0xFFFF, sum = 0
6391 08:06:22.354151 6, 0xFFFF, sum = 0
6392 08:06:22.354234 7, 0xFFFF, sum = 0
6393 08:06:22.357907 8, 0xFFFF, sum = 0
6394 08:06:22.357990 9, 0xFFFF, sum = 0
6395 08:06:22.361210 10, 0xFFFF, sum = 0
6396 08:06:22.361293 11, 0xFFFF, sum = 0
6397 08:06:22.364236 12, 0xFFFF, sum = 0
6398 08:06:22.364319 13, 0x0, sum = 1
6399 08:06:22.367733 14, 0x0, sum = 2
6400 08:06:22.367815 15, 0x0, sum = 3
6401 08:06:22.371039 16, 0x0, sum = 4
6402 08:06:22.371122 best_step = 14
6403 08:06:22.371187
6404 08:06:22.371247 ==
6405 08:06:22.373949 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 08:06:22.380960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 08:06:22.381043 ==
6408 08:06:22.381107 RX Vref Scan: 1
6409 08:06:22.381168
6410 08:06:22.384457 RX Vref 0 -> 0, step: 1
6411 08:06:22.384539
6412 08:06:22.387504 RX Delay -359 -> 252, step: 8
6413 08:06:22.387586
6414 08:06:22.390998 Set Vref, RX VrefLevel [Byte0]: 62
6415 08:06:22.393741 [Byte1]: 48
6416 08:06:22.397599
6417 08:06:22.397680 Final RX Vref Byte 0 = 62 to rank0
6418 08:06:22.400608 Final RX Vref Byte 1 = 48 to rank0
6419 08:06:22.404431 Final RX Vref Byte 0 = 62 to rank1
6420 08:06:22.407220 Final RX Vref Byte 1 = 48 to rank1==
6421 08:06:22.410850 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 08:06:22.417711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 08:06:22.417793 ==
6424 08:06:22.417859 DQS Delay:
6425 08:06:22.420966 DQS0 = 60, DQS1 = 68
6426 08:06:22.421047 DQM Delay:
6427 08:06:22.421111 DQM0 = 14, DQM1 = 14
6428 08:06:22.424222 DQ Delay:
6429 08:06:22.427006 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6430 08:06:22.430319 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6431 08:06:22.430401 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6432 08:06:22.437664 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6433 08:06:22.437746
6434 08:06:22.437810
6435 08:06:22.443686 [DQSOSCAuto] RK0, (LSB)MR18= 0x817f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6436 08:06:22.446939 CH0 RK0: MR19=C0C, MR18=817F
6437 08:06:22.453686 CH0_RK0: MR19=0xC0C, MR18=0x817F, DQSOSC=393, MR23=63, INC=382, DEC=254
6438 08:06:22.453769 ==
6439 08:06:22.457100 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 08:06:22.460793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 08:06:22.460875 ==
6442 08:06:22.464067 [Gating] SW mode calibration
6443 08:06:22.470683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6444 08:06:22.477358 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6445 08:06:22.480403 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 08:06:22.483742 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 08:06:22.490349 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 08:06:22.493893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 08:06:22.497070 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 08:06:22.504184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 08:06:22.506835 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 08:06:22.510460 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 08:06:22.516903 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 08:06:22.516985 Total UI for P1: 0, mck2ui 16
6455 08:06:22.520771 best dqsien dly found for B0: ( 0, 14, 24)
6456 08:06:22.523745 Total UI for P1: 0, mck2ui 16
6457 08:06:22.526777 best dqsien dly found for B1: ( 0, 14, 24)
6458 08:06:22.533589 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6459 08:06:22.536920 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6460 08:06:22.537002
6461 08:06:22.540407 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 08:06:22.543211 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 08:06:22.546801 [Gating] SW calibration Done
6464 08:06:22.546883 ==
6465 08:06:22.549833 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 08:06:22.553316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 08:06:22.553398 ==
6468 08:06:22.556948 RX Vref Scan: 0
6469 08:06:22.557038
6470 08:06:22.557103 RX Vref 0 -> 0, step: 1
6471 08:06:22.557164
6472 08:06:22.560415 RX Delay -410 -> 252, step: 16
6473 08:06:22.566834 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6474 08:06:22.570094 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6475 08:06:22.573571 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6476 08:06:22.576321 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6477 08:06:22.583124 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6478 08:06:22.586720 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6479 08:06:22.590068 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6480 08:06:22.593140 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6481 08:06:22.600023 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6482 08:06:22.603209 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6483 08:06:22.606162 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6484 08:06:22.609505 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6485 08:06:22.615950 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6486 08:06:22.619446 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6487 08:06:22.622933 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6488 08:06:22.626244 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6489 08:06:22.629572 ==
6490 08:06:22.629654 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 08:06:22.636576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 08:06:22.636658 ==
6493 08:06:22.636723 DQS Delay:
6494 08:06:22.639416 DQS0 = 59, DQS1 = 59
6495 08:06:22.639498 DQM Delay:
6496 08:06:22.642926 DQM0 = 16, DQM1 = 10
6497 08:06:22.643007 DQ Delay:
6498 08:06:22.646010 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6499 08:06:22.649316 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6500 08:06:22.653111 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6501 08:06:22.655742 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6502 08:06:22.655825
6503 08:06:22.655890
6504 08:06:22.655949 ==
6505 08:06:22.659320 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 08:06:22.663044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 08:06:22.663152 ==
6508 08:06:22.663245
6509 08:06:22.663334
6510 08:06:22.666277 TX Vref Scan disable
6511 08:06:22.666372 == TX Byte 0 ==
6512 08:06:22.672717 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6513 08:06:22.676295 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6514 08:06:22.676378 == TX Byte 1 ==
6515 08:06:22.682542 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6516 08:06:22.685784 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6517 08:06:22.685867 ==
6518 08:06:22.688905 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 08:06:22.692901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 08:06:22.692984 ==
6521 08:06:22.693049
6522 08:06:22.693109
6523 08:06:22.695745 TX Vref Scan disable
6524 08:06:22.695826 == TX Byte 0 ==
6525 08:06:22.702272 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6526 08:06:22.705533 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6527 08:06:22.705615 == TX Byte 1 ==
6528 08:06:22.712291 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6529 08:06:22.715586 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6530 08:06:22.715667
6531 08:06:22.715731 [DATLAT]
6532 08:06:22.718683 Freq=400, CH0 RK1
6533 08:06:22.718765
6534 08:06:22.718829 DATLAT Default: 0xe
6535 08:06:22.722140 0, 0xFFFF, sum = 0
6536 08:06:22.722224 1, 0xFFFF, sum = 0
6537 08:06:22.725566 2, 0xFFFF, sum = 0
6538 08:06:22.725648 3, 0xFFFF, sum = 0
6539 08:06:22.728560 4, 0xFFFF, sum = 0
6540 08:06:22.728643 5, 0xFFFF, sum = 0
6541 08:06:22.732331 6, 0xFFFF, sum = 0
6542 08:06:22.732414 7, 0xFFFF, sum = 0
6543 08:06:22.735142 8, 0xFFFF, sum = 0
6544 08:06:22.738605 9, 0xFFFF, sum = 0
6545 08:06:22.738688 10, 0xFFFF, sum = 0
6546 08:06:22.742438 11, 0xFFFF, sum = 0
6547 08:06:22.742520 12, 0xFFFF, sum = 0
6548 08:06:22.745853 13, 0x0, sum = 1
6549 08:06:22.745936 14, 0x0, sum = 2
6550 08:06:22.748595 15, 0x0, sum = 3
6551 08:06:22.748678 16, 0x0, sum = 4
6552 08:06:22.748744 best_step = 14
6553 08:06:22.751672
6554 08:06:22.751753 ==
6555 08:06:22.755171 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 08:06:22.758551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 08:06:22.758633 ==
6558 08:06:22.758697 RX Vref Scan: 0
6559 08:06:22.758757
6560 08:06:22.761884 RX Vref 0 -> 0, step: 1
6561 08:06:22.761965
6562 08:06:22.765562 RX Delay -359 -> 252, step: 8
6563 08:06:22.772161 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6564 08:06:22.775458 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6565 08:06:22.778994 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6566 08:06:22.782614 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6567 08:06:22.788792 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6568 08:06:22.792260 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6569 08:06:22.795687 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6570 08:06:22.798795 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6571 08:06:22.805218 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6572 08:06:22.808707 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6573 08:06:22.811819 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6574 08:06:22.819074 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6575 08:06:22.822147 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6576 08:06:22.825582 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6577 08:06:22.828955 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6578 08:06:22.835098 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6579 08:06:22.835179 ==
6580 08:06:22.838596 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 08:06:22.842265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 08:06:22.842347 ==
6583 08:06:22.842412 DQS Delay:
6584 08:06:22.845216 DQS0 = 60, DQS1 = 72
6585 08:06:22.845297 DQM Delay:
6586 08:06:22.848721 DQM0 = 12, DQM1 = 17
6587 08:06:22.848802 DQ Delay:
6588 08:06:22.851735 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6589 08:06:22.855298 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6590 08:06:22.858820 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6591 08:06:22.861924 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6592 08:06:22.862006
6593 08:06:22.862070
6594 08:06:22.868553 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6595 08:06:22.872030 CH0 RK1: MR19=C0C, MR18=C57B
6596 08:06:22.878777 CH0_RK1: MR19=0xC0C, MR18=0xC57B, DQSOSC=385, MR23=63, INC=398, DEC=265
6597 08:06:22.881697 [RxdqsGatingPostProcess] freq 400
6598 08:06:22.888364 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6599 08:06:22.891869 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 08:06:22.891951 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 08:06:22.895015 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 08:06:22.898398 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 08:06:22.901988 best DQS0 dly(2T, 0.5T) = (0, 10)
6604 08:06:22.905218 best DQS1 dly(2T, 0.5T) = (0, 10)
6605 08:06:22.908137 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6606 08:06:22.911574 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6607 08:06:22.914757 Pre-setting of DQS Precalculation
6608 08:06:22.921433 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6609 08:06:22.921515 ==
6610 08:06:22.924545 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 08:06:22.928317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 08:06:22.928399 ==
6613 08:06:22.935046 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 08:06:22.938206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6615 08:06:22.941925 [CA 0] Center 36 (8~64) winsize 57
6616 08:06:22.944787 [CA 1] Center 36 (8~64) winsize 57
6617 08:06:22.948340 [CA 2] Center 36 (8~64) winsize 57
6618 08:06:22.951415 [CA 3] Center 36 (8~64) winsize 57
6619 08:06:22.954787 [CA 4] Center 36 (8~64) winsize 57
6620 08:06:22.958186 [CA 5] Center 36 (8~64) winsize 57
6621 08:06:22.958323
6622 08:06:22.961232 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6623 08:06:22.961386
6624 08:06:22.964609 [CATrainingPosCal] consider 1 rank data
6625 08:06:22.967853 u2DelayCellTimex100 = 270/100 ps
6626 08:06:22.971333 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 08:06:22.974628 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 08:06:22.977932 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 08:06:22.984846 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 08:06:22.987885 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 08:06:22.991734 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 08:06:22.992203
6633 08:06:22.994638 CA PerBit enable=1, Macro0, CA PI delay=36
6634 08:06:22.995104
6635 08:06:22.997952 [CBTSetCACLKResult] CA Dly = 36
6636 08:06:22.998379 CS Dly: 1 (0~32)
6637 08:06:22.998762 ==
6638 08:06:23.001592 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 08:06:23.008049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 08:06:23.008522 ==
6641 08:06:23.011443 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 08:06:23.018054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6643 08:06:23.021347 [CA 0] Center 36 (8~64) winsize 57
6644 08:06:23.024611 [CA 1] Center 36 (8~64) winsize 57
6645 08:06:23.027739 [CA 2] Center 36 (8~64) winsize 57
6646 08:06:23.030979 [CA 3] Center 36 (8~64) winsize 57
6647 08:06:23.034805 [CA 4] Center 36 (8~64) winsize 57
6648 08:06:23.037911 [CA 5] Center 36 (8~64) winsize 57
6649 08:06:23.038416
6650 08:06:23.041585 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6651 08:06:23.042053
6652 08:06:23.044451 [CATrainingPosCal] consider 2 rank data
6653 08:06:23.047885 u2DelayCellTimex100 = 270/100 ps
6654 08:06:23.050839 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 08:06:23.054300 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 08:06:23.057672 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 08:06:23.061081 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 08:06:23.064461 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 08:06:23.070644 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 08:06:23.071108
6661 08:06:23.074366 CA PerBit enable=1, Macro0, CA PI delay=36
6662 08:06:23.074829
6663 08:06:23.077438 [CBTSetCACLKResult] CA Dly = 36
6664 08:06:23.077898 CS Dly: 1 (0~32)
6665 08:06:23.078268
6666 08:06:23.081065 ----->DramcWriteLeveling(PI) begin...
6667 08:06:23.081531 ==
6668 08:06:23.084062 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 08:06:23.090740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 08:06:23.091210 ==
6671 08:06:23.094489 Write leveling (Byte 0): 40 => 8
6672 08:06:23.094909 Write leveling (Byte 1): 40 => 8
6673 08:06:23.097541 DramcWriteLeveling(PI) end<-----
6674 08:06:23.097961
6675 08:06:23.098291 ==
6676 08:06:23.100847 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 08:06:23.107431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 08:06:23.107872 ==
6679 08:06:23.110654 [Gating] SW mode calibration
6680 08:06:23.117203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6681 08:06:23.120474 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6682 08:06:23.127090 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 08:06:23.130299 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 08:06:23.133523 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 08:06:23.140151 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 08:06:23.143519 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 08:06:23.146819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 08:06:23.153613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 08:06:23.156954 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 08:06:23.160342 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 08:06:23.163450 Total UI for P1: 0, mck2ui 16
6692 08:06:23.166904 best dqsien dly found for B0: ( 0, 14, 24)
6693 08:06:23.169720 Total UI for P1: 0, mck2ui 16
6694 08:06:23.173234 best dqsien dly found for B1: ( 0, 14, 24)
6695 08:06:23.176555 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6696 08:06:23.179685 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6697 08:06:23.180110
6698 08:06:23.186422 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 08:06:23.189710 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 08:06:23.190234 [Gating] SW calibration Done
6701 08:06:23.193343 ==
6702 08:06:23.196740 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 08:06:23.199850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 08:06:23.200328 ==
6705 08:06:23.200803 RX Vref Scan: 0
6706 08:06:23.201252
6707 08:06:23.203255 RX Vref 0 -> 0, step: 1
6708 08:06:23.203781
6709 08:06:23.206634 RX Delay -410 -> 252, step: 16
6710 08:06:23.209716 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6711 08:06:23.213451 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6712 08:06:23.219995 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6713 08:06:23.223134 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6714 08:06:23.226582 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6715 08:06:23.230106 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6716 08:06:23.236493 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6717 08:06:23.240407 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6718 08:06:23.243249 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6719 08:06:23.246517 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6720 08:06:23.253315 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6721 08:06:23.256958 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6722 08:06:23.259604 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6723 08:06:23.262919 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6724 08:06:23.270261 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6725 08:06:23.272922 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6726 08:06:23.273403 ==
6727 08:06:23.276423 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 08:06:23.279768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 08:06:23.280205 ==
6730 08:06:23.283260 DQS Delay:
6731 08:06:23.283774 DQS0 = 51, DQS1 = 67
6732 08:06:23.286234 DQM Delay:
6733 08:06:23.286720 DQM0 = 12, DQM1 = 18
6734 08:06:23.287110 DQ Delay:
6735 08:06:23.289502 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6736 08:06:23.293055 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6737 08:06:23.296071 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6738 08:06:23.299491 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6739 08:06:23.299943
6740 08:06:23.300280
6741 08:06:23.300620 ==
6742 08:06:23.302959 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 08:06:23.309493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 08:06:23.309935 ==
6745 08:06:23.310272
6746 08:06:23.310596
6747 08:06:23.310909 TX Vref Scan disable
6748 08:06:23.313262 == TX Byte 0 ==
6749 08:06:23.316048 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 08:06:23.319117 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 08:06:23.322420 == TX Byte 1 ==
6752 08:06:23.326705 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 08:06:23.329198 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 08:06:23.332826 ==
6755 08:06:23.333244 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 08:06:23.339214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 08:06:23.339670 ==
6758 08:06:23.340003
6759 08:06:23.340314
6760 08:06:23.342335 TX Vref Scan disable
6761 08:06:23.342756 == TX Byte 0 ==
6762 08:06:23.346269 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 08:06:23.352536 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 08:06:23.352960 == TX Byte 1 ==
6765 08:06:23.355783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 08:06:23.359248 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 08:06:23.362060
6768 08:06:23.362284 [DATLAT]
6769 08:06:23.362461 Freq=400, CH1 RK0
6770 08:06:23.362633
6771 08:06:23.365412 DATLAT Default: 0xf
6772 08:06:23.365593 0, 0xFFFF, sum = 0
6773 08:06:23.369410 1, 0xFFFF, sum = 0
6774 08:06:23.369590 2, 0xFFFF, sum = 0
6775 08:06:23.371877 3, 0xFFFF, sum = 0
6776 08:06:23.372030 4, 0xFFFF, sum = 0
6777 08:06:23.375319 5, 0xFFFF, sum = 0
6778 08:06:23.378857 6, 0xFFFF, sum = 0
6779 08:06:23.378990 7, 0xFFFF, sum = 0
6780 08:06:23.382417 8, 0xFFFF, sum = 0
6781 08:06:23.382535 9, 0xFFFF, sum = 0
6782 08:06:23.385311 10, 0xFFFF, sum = 0
6783 08:06:23.385415 11, 0xFFFF, sum = 0
6784 08:06:23.388430 12, 0xFFFF, sum = 0
6785 08:06:23.388513 13, 0x0, sum = 1
6786 08:06:23.392187 14, 0x0, sum = 2
6787 08:06:23.392270 15, 0x0, sum = 3
6788 08:06:23.395037 16, 0x0, sum = 4
6789 08:06:23.395120 best_step = 14
6790 08:06:23.395185
6791 08:06:23.395246 ==
6792 08:06:23.398939 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 08:06:23.402096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 08:06:23.402179 ==
6795 08:06:23.405032 RX Vref Scan: 1
6796 08:06:23.405114
6797 08:06:23.409036 RX Vref 0 -> 0, step: 1
6798 08:06:23.409118
6799 08:06:23.409183 RX Delay -375 -> 252, step: 8
6800 08:06:23.411977
6801 08:06:23.412058 Set Vref, RX VrefLevel [Byte0]: 56
6802 08:06:23.415237 [Byte1]: 50
6803 08:06:23.420923
6804 08:06:23.421004 Final RX Vref Byte 0 = 56 to rank0
6805 08:06:23.424352 Final RX Vref Byte 1 = 50 to rank0
6806 08:06:23.427273 Final RX Vref Byte 0 = 56 to rank1
6807 08:06:23.430843 Final RX Vref Byte 1 = 50 to rank1==
6808 08:06:23.433912 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 08:06:23.440909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 08:06:23.441011 ==
6811 08:06:23.441093 DQS Delay:
6812 08:06:23.444278 DQS0 = 52, DQS1 = 64
6813 08:06:23.444380 DQM Delay:
6814 08:06:23.444461 DQM0 = 10, DQM1 = 11
6815 08:06:23.447727 DQ Delay:
6816 08:06:23.450852 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6817 08:06:23.450973 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6818 08:06:23.454577 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6819 08:06:23.457318 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6820 08:06:23.457453
6821 08:06:23.460799
6822 08:06:23.467216 [DQSOSCAuto] RK0, (LSB)MR18= 0x586c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6823 08:06:23.470870 CH1 RK0: MR19=C0C, MR18=586C
6824 08:06:23.477052 CH1_RK0: MR19=0xC0C, MR18=0x586C, DQSOSC=396, MR23=63, INC=376, DEC=251
6825 08:06:23.477295 ==
6826 08:06:23.480521 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 08:06:23.483991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 08:06:23.484294 ==
6829 08:06:23.487736 [Gating] SW mode calibration
6830 08:06:23.493863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6831 08:06:23.500945 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6832 08:06:23.504291 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 08:06:23.507188 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 08:06:23.513884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 08:06:23.517470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 08:06:23.520280 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 08:06:23.527021 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 08:06:23.530960 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 08:06:23.533670 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 08:06:23.540337 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 08:06:23.540805 Total UI for P1: 0, mck2ui 16
6842 08:06:23.544090 best dqsien dly found for B0: ( 0, 14, 24)
6843 08:06:23.547685 Total UI for P1: 0, mck2ui 16
6844 08:06:23.550040 best dqsien dly found for B1: ( 0, 14, 24)
6845 08:06:23.557086 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6846 08:06:23.560356 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6847 08:06:23.560778
6848 08:06:23.563811 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 08:06:23.567013 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 08:06:23.570557 [Gating] SW calibration Done
6851 08:06:23.570993 ==
6852 08:06:23.573383 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 08:06:23.577079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 08:06:23.577502 ==
6855 08:06:23.580165 RX Vref Scan: 0
6856 08:06:23.580585
6857 08:06:23.580919 RX Vref 0 -> 0, step: 1
6858 08:06:23.581234
6859 08:06:23.583647 RX Delay -410 -> 252, step: 16
6860 08:06:23.587275 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6861 08:06:23.593716 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6862 08:06:23.596832 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6863 08:06:23.599849 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6864 08:06:23.603103 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6865 08:06:23.609920 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6866 08:06:23.613465 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6867 08:06:23.616774 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6868 08:06:23.619728 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6869 08:06:23.626188 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6870 08:06:23.629658 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6871 08:06:23.633072 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6872 08:06:23.636183 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6873 08:06:23.643407 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6874 08:06:23.646169 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6875 08:06:23.649521 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6876 08:06:23.649603 ==
6877 08:06:23.652805 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 08:06:23.659500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 08:06:23.659582 ==
6880 08:06:23.659647 DQS Delay:
6881 08:06:23.663309 DQS0 = 59, DQS1 = 59
6882 08:06:23.663463 DQM Delay:
6883 08:06:23.663530 DQM0 = 19, DQM1 = 12
6884 08:06:23.666713 DQ Delay:
6885 08:06:23.669285 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6886 08:06:23.673054 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6887 08:06:23.675975 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6888 08:06:23.679733 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6889 08:06:23.679815
6890 08:06:23.679879
6891 08:06:23.679938 ==
6892 08:06:23.682548 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 08:06:23.686499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 08:06:23.686581 ==
6895 08:06:23.686646
6896 08:06:23.686706
6897 08:06:23.689506 TX Vref Scan disable
6898 08:06:23.689587 == TX Byte 0 ==
6899 08:06:23.696330 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6900 08:06:23.699624 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6901 08:06:23.699706 == TX Byte 1 ==
6902 08:06:23.702868 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6903 08:06:23.709464 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6904 08:06:23.709546 ==
6905 08:06:23.712544 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 08:06:23.716728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 08:06:23.717158 ==
6908 08:06:23.717499
6909 08:06:23.717811
6910 08:06:23.719696 TX Vref Scan disable
6911 08:06:23.720121 == TX Byte 0 ==
6912 08:06:23.726312 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6913 08:06:23.729590 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6914 08:06:23.730014 == TX Byte 1 ==
6915 08:06:23.736401 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6916 08:06:23.739298 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6917 08:06:23.739832
6918 08:06:23.740170 [DATLAT]
6919 08:06:23.742953 Freq=400, CH1 RK1
6920 08:06:23.743463
6921 08:06:23.743839 DATLAT Default: 0xe
6922 08:06:23.745968 0, 0xFFFF, sum = 0
6923 08:06:23.746398 1, 0xFFFF, sum = 0
6924 08:06:23.749660 2, 0xFFFF, sum = 0
6925 08:06:23.750088 3, 0xFFFF, sum = 0
6926 08:06:23.753181 4, 0xFFFF, sum = 0
6927 08:06:23.753616 5, 0xFFFF, sum = 0
6928 08:06:23.756030 6, 0xFFFF, sum = 0
6929 08:06:23.756464 7, 0xFFFF, sum = 0
6930 08:06:23.759585 8, 0xFFFF, sum = 0
6931 08:06:23.760023 9, 0xFFFF, sum = 0
6932 08:06:23.762764 10, 0xFFFF, sum = 0
6933 08:06:23.763206 11, 0xFFFF, sum = 0
6934 08:06:23.766439 12, 0xFFFF, sum = 0
6935 08:06:23.766870 13, 0x0, sum = 1
6936 08:06:23.769221 14, 0x0, sum = 2
6937 08:06:23.769654 15, 0x0, sum = 3
6938 08:06:23.772424 16, 0x0, sum = 4
6939 08:06:23.772850 best_step = 14
6940 08:06:23.773185
6941 08:06:23.773517 ==
6942 08:06:23.775909 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 08:06:23.782787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 08:06:23.783212 ==
6945 08:06:23.783587 RX Vref Scan: 0
6946 08:06:23.783907
6947 08:06:23.785981 RX Vref 0 -> 0, step: 1
6948 08:06:23.786404
6949 08:06:23.788974 RX Delay -359 -> 252, step: 8
6950 08:06:23.795767 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6951 08:06:23.799274 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6952 08:06:23.802702 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6953 08:06:23.805857 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6954 08:06:23.812644 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6955 08:06:23.815967 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6956 08:06:23.818951 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6957 08:06:23.822505 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6958 08:06:23.829050 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6959 08:06:23.831974 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6960 08:06:23.835768 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6961 08:06:23.842294 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6962 08:06:23.845511 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6963 08:06:23.848671 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6964 08:06:23.852263 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6965 08:06:23.858584 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6966 08:06:23.859012 ==
6967 08:06:23.861837 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 08:06:23.865239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 08:06:23.865668 ==
6970 08:06:23.866008 DQS Delay:
6971 08:06:23.868947 DQS0 = 60, DQS1 = 64
6972 08:06:23.869367 DQM Delay:
6973 08:06:23.872357 DQM0 = 12, DQM1 = 10
6974 08:06:23.872794 DQ Delay:
6975 08:06:23.875197 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6976 08:06:23.878615 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6977 08:06:23.882150 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6978 08:06:23.885121 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6979 08:06:23.885546
6980 08:06:23.885880
6981 08:06:23.891891 [DQSOSCAuto] RK1, (LSB)MR18= 0x83b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6982 08:06:23.895184 CH1 RK1: MR19=C0C, MR18=83B3
6983 08:06:23.901365 CH1_RK1: MR19=0xC0C, MR18=0x83B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6984 08:06:23.904775 [RxdqsGatingPostProcess] freq 400
6985 08:06:23.911849 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6986 08:06:23.914692 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 08:06:23.918216 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 08:06:23.921253 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 08:06:23.924921 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 08:06:23.925348 best DQS0 dly(2T, 0.5T) = (0, 10)
6991 08:06:23.928161 best DQS1 dly(2T, 0.5T) = (0, 10)
6992 08:06:23.931792 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6993 08:06:23.934621 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6994 08:06:23.938192 Pre-setting of DQS Precalculation
6995 08:06:23.944573 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6996 08:06:23.951551 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6997 08:06:23.957748 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6998 08:06:23.958182
6999 08:06:23.958518
7000 08:06:23.961361 [Calibration Summary] 800 Mbps
7001 08:06:23.961785 CH 0, Rank 0
7002 08:06:23.964750 SW Impedance : PASS
7003 08:06:23.968041 DUTY Scan : NO K
7004 08:06:23.968464 ZQ Calibration : PASS
7005 08:06:23.970883 Jitter Meter : NO K
7006 08:06:23.974491 CBT Training : PASS
7007 08:06:23.974916 Write leveling : PASS
7008 08:06:23.977749 RX DQS gating : PASS
7009 08:06:23.981054 RX DQ/DQS(RDDQC) : PASS
7010 08:06:23.981480 TX DQ/DQS : PASS
7011 08:06:23.984524 RX DATLAT : PASS
7012 08:06:23.987826 RX DQ/DQS(Engine): PASS
7013 08:06:23.988253 TX OE : NO K
7014 08:06:23.988594 All Pass.
7015 08:06:23.991018
7016 08:06:23.991469 CH 0, Rank 1
7017 08:06:23.994508 SW Impedance : PASS
7018 08:06:23.995044 DUTY Scan : NO K
7019 08:06:23.997458 ZQ Calibration : PASS
7020 08:06:24.000689 Jitter Meter : NO K
7021 08:06:24.001107 CBT Training : PASS
7022 08:06:24.003960 Write leveling : NO K
7023 08:06:24.004398 RX DQS gating : PASS
7024 08:06:24.007446 RX DQ/DQS(RDDQC) : PASS
7025 08:06:24.010716 TX DQ/DQS : PASS
7026 08:06:24.011133 RX DATLAT : PASS
7027 08:06:24.014013 RX DQ/DQS(Engine): PASS
7028 08:06:24.017299 TX OE : NO K
7029 08:06:24.017759 All Pass.
7030 08:06:24.018096
7031 08:06:24.018496 CH 1, Rank 0
7032 08:06:24.021037 SW Impedance : PASS
7033 08:06:24.024170 DUTY Scan : NO K
7034 08:06:24.024587 ZQ Calibration : PASS
7035 08:06:24.027467 Jitter Meter : NO K
7036 08:06:24.030830 CBT Training : PASS
7037 08:06:24.031256 Write leveling : PASS
7038 08:06:24.034296 RX DQS gating : PASS
7039 08:06:24.037734 RX DQ/DQS(RDDQC) : PASS
7040 08:06:24.038159 TX DQ/DQS : PASS
7041 08:06:24.040896 RX DATLAT : PASS
7042 08:06:24.044632 RX DQ/DQS(Engine): PASS
7043 08:06:24.045060 TX OE : NO K
7044 08:06:24.045421 All Pass.
7045 08:06:24.047327
7046 08:06:24.047791 CH 1, Rank 1
7047 08:06:24.050433 SW Impedance : PASS
7048 08:06:24.050856 DUTY Scan : NO K
7049 08:06:24.053968 ZQ Calibration : PASS
7050 08:06:24.054393 Jitter Meter : NO K
7051 08:06:24.057183 CBT Training : PASS
7052 08:06:24.060589 Write leveling : NO K
7053 08:06:24.061014 RX DQS gating : PASS
7054 08:06:24.063734 RX DQ/DQS(RDDQC) : PASS
7055 08:06:24.067483 TX DQ/DQS : PASS
7056 08:06:24.067911 RX DATLAT : PASS
7057 08:06:24.070778 RX DQ/DQS(Engine): PASS
7058 08:06:24.073745 TX OE : NO K
7059 08:06:24.074172 All Pass.
7060 08:06:24.074511
7061 08:06:24.077169 DramC Write-DBI off
7062 08:06:24.077596 PER_BANK_REFRESH: Hybrid Mode
7063 08:06:24.080763 TX_TRACKING: ON
7064 08:06:24.087345 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7065 08:06:24.093778 [FAST_K] Save calibration result to emmc
7066 08:06:24.097100 dramc_set_vcore_voltage set vcore to 725000
7067 08:06:24.097528 Read voltage for 1600, 0
7068 08:06:24.100579 Vio18 = 0
7069 08:06:24.101005 Vcore = 725000
7070 08:06:24.101339 Vdram = 0
7071 08:06:24.103990 Vddq = 0
7072 08:06:24.104413 Vmddr = 0
7073 08:06:24.106935 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7074 08:06:24.113802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7075 08:06:24.117186 MEM_TYPE=3, freq_sel=13
7076 08:06:24.120685 sv_algorithm_assistance_LP4_3733
7077 08:06:24.123460 ============ PULL DRAM RESETB DOWN ============
7078 08:06:24.126832 ========== PULL DRAM RESETB DOWN end =========
7079 08:06:24.133531 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7080 08:06:24.137165 ===================================
7081 08:06:24.137694 LPDDR4 DRAM CONFIGURATION
7082 08:06:24.140399 ===================================
7083 08:06:24.143721 EX_ROW_EN[0] = 0x0
7084 08:06:24.144146 EX_ROW_EN[1] = 0x0
7085 08:06:24.147176 LP4Y_EN = 0x0
7086 08:06:24.147647 WORK_FSP = 0x1
7087 08:06:24.150603 WL = 0x5
7088 08:06:24.151024 RL = 0x5
7089 08:06:24.153466 BL = 0x2
7090 08:06:24.156949 RPST = 0x0
7091 08:06:24.157373 RD_PRE = 0x0
7092 08:06:24.160173 WR_PRE = 0x1
7093 08:06:24.160611 WR_PST = 0x1
7094 08:06:24.163427 DBI_WR = 0x0
7095 08:06:24.163856 DBI_RD = 0x0
7096 08:06:24.166856 OTF = 0x1
7097 08:06:24.169836 ===================================
7098 08:06:24.173255 ===================================
7099 08:06:24.173679 ANA top config
7100 08:06:24.176800 ===================================
7101 08:06:24.180312 DLL_ASYNC_EN = 0
7102 08:06:24.183132 ALL_SLAVE_EN = 0
7103 08:06:24.183587 NEW_RANK_MODE = 1
7104 08:06:24.186816 DLL_IDLE_MODE = 1
7105 08:06:24.190045 LP45_APHY_COMB_EN = 1
7106 08:06:24.193349 TX_ODT_DIS = 0
7107 08:06:24.196485 NEW_8X_MODE = 1
7108 08:06:24.196975 ===================================
7109 08:06:24.199919 ===================================
7110 08:06:24.203376 data_rate = 3200
7111 08:06:24.206820 CKR = 1
7112 08:06:24.210149 DQ_P2S_RATIO = 8
7113 08:06:24.213151 ===================================
7114 08:06:24.216875 CA_P2S_RATIO = 8
7115 08:06:24.220049 DQ_CA_OPEN = 0
7116 08:06:24.223278 DQ_SEMI_OPEN = 0
7117 08:06:24.223791 CA_SEMI_OPEN = 0
7118 08:06:24.226510 CA_FULL_RATE = 0
7119 08:06:24.229572 DQ_CKDIV4_EN = 0
7120 08:06:24.232905 CA_CKDIV4_EN = 0
7121 08:06:24.236259 CA_PREDIV_EN = 0
7122 08:06:24.239691 PH8_DLY = 12
7123 08:06:24.240119 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7124 08:06:24.242788 DQ_AAMCK_DIV = 4
7125 08:06:24.246409 CA_AAMCK_DIV = 4
7126 08:06:24.249755 CA_ADMCK_DIV = 4
7127 08:06:24.252939 DQ_TRACK_CA_EN = 0
7128 08:06:24.256158 CA_PICK = 1600
7129 08:06:24.259507 CA_MCKIO = 1600
7130 08:06:24.259930 MCKIO_SEMI = 0
7131 08:06:24.262947 PLL_FREQ = 3068
7132 08:06:24.266288 DQ_UI_PI_RATIO = 32
7133 08:06:24.269700 CA_UI_PI_RATIO = 0
7134 08:06:24.272732 ===================================
7135 08:06:24.275982 ===================================
7136 08:06:24.279267 memory_type:LPDDR4
7137 08:06:24.279758 GP_NUM : 10
7138 08:06:24.282657 SRAM_EN : 1
7139 08:06:24.286595 MD32_EN : 0
7140 08:06:24.289293 ===================================
7141 08:06:24.289864 [ANA_INIT] >>>>>>>>>>>>>>
7142 08:06:24.292550 <<<<<< [CONFIGURE PHASE]: ANA_TX
7143 08:06:24.296018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7144 08:06:24.299317 ===================================
7145 08:06:24.302932 data_rate = 3200,PCW = 0X7600
7146 08:06:24.305596 ===================================
7147 08:06:24.308753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7148 08:06:24.315512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 08:06:24.318818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 08:06:24.325642 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7151 08:06:24.328971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7152 08:06:24.331916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7153 08:06:24.332348 [ANA_INIT] flow start
7154 08:06:24.335473 [ANA_INIT] PLL >>>>>>>>
7155 08:06:24.338282 [ANA_INIT] PLL <<<<<<<<
7156 08:06:24.341842 [ANA_INIT] MIDPI >>>>>>>>
7157 08:06:24.342275 [ANA_INIT] MIDPI <<<<<<<<
7158 08:06:24.345613 [ANA_INIT] DLL >>>>>>>>
7159 08:06:24.348363 [ANA_INIT] DLL <<<<<<<<
7160 08:06:24.348862 [ANA_INIT] flow end
7161 08:06:24.355063 ============ LP4 DIFF to SE enter ============
7162 08:06:24.358131 ============ LP4 DIFF to SE exit ============
7163 08:06:24.358575 [ANA_INIT] <<<<<<<<<<<<<
7164 08:06:24.361903 [Flow] Enable top DCM control >>>>>
7165 08:06:24.365017 [Flow] Enable top DCM control <<<<<
7166 08:06:24.368215 Enable DLL master slave shuffle
7167 08:06:24.375178 ==============================================================
7168 08:06:24.378260 Gating Mode config
7169 08:06:24.381745 ==============================================================
7170 08:06:24.385289 Config description:
7171 08:06:24.394665 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7172 08:06:24.401968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7173 08:06:24.404934 SELPH_MODE 0: By rank 1: By Phase
7174 08:06:24.411808 ==============================================================
7175 08:06:24.415156 GAT_TRACK_EN = 1
7176 08:06:24.418013 RX_GATING_MODE = 2
7177 08:06:24.421308 RX_GATING_TRACK_MODE = 2
7178 08:06:24.421749 SELPH_MODE = 1
7179 08:06:24.425285 PICG_EARLY_EN = 1
7180 08:06:24.428205 VALID_LAT_VALUE = 1
7181 08:06:24.434695 ==============================================================
7182 08:06:24.438172 Enter into Gating configuration >>>>
7183 08:06:24.441446 Exit from Gating configuration <<<<
7184 08:06:24.445375 Enter into DVFS_PRE_config >>>>>
7185 08:06:24.454823 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7186 08:06:24.458143 Exit from DVFS_PRE_config <<<<<
7187 08:06:24.461209 Enter into PICG configuration >>>>
7188 08:06:24.464681 Exit from PICG configuration <<<<
7189 08:06:24.467852 [RX_INPUT] configuration >>>>>
7190 08:06:24.471313 [RX_INPUT] configuration <<<<<
7191 08:06:24.474431 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7192 08:06:24.481271 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7193 08:06:24.488024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7194 08:06:24.494424 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7195 08:06:24.497835 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 08:06:24.504511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 08:06:24.511031 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7198 08:06:24.514589 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7199 08:06:24.517744 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7200 08:06:24.521274 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7201 08:06:24.524071 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7202 08:06:24.531082 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 08:06:24.534147 ===================================
7204 08:06:24.538157 LPDDR4 DRAM CONFIGURATION
7205 08:06:24.540983 ===================================
7206 08:06:24.541441 EX_ROW_EN[0] = 0x0
7207 08:06:24.544232 EX_ROW_EN[1] = 0x0
7208 08:06:24.544678 LP4Y_EN = 0x0
7209 08:06:24.547293 WORK_FSP = 0x1
7210 08:06:24.547758 WL = 0x5
7211 08:06:24.551249 RL = 0x5
7212 08:06:24.551835 BL = 0x2
7213 08:06:24.554764 RPST = 0x0
7214 08:06:24.555322 RD_PRE = 0x0
7215 08:06:24.557372 WR_PRE = 0x1
7216 08:06:24.557810 WR_PST = 0x1
7217 08:06:24.560649 DBI_WR = 0x0
7218 08:06:24.561070 DBI_RD = 0x0
7219 08:06:24.563953 OTF = 0x1
7220 08:06:24.567503 ===================================
7221 08:06:24.571049 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7222 08:06:24.574382 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7223 08:06:24.580869 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7224 08:06:24.584118 ===================================
7225 08:06:24.584544 LPDDR4 DRAM CONFIGURATION
7226 08:06:24.587261 ===================================
7227 08:06:24.590672 EX_ROW_EN[0] = 0x10
7228 08:06:24.593835 EX_ROW_EN[1] = 0x0
7229 08:06:24.594313 LP4Y_EN = 0x0
7230 08:06:24.597313 WORK_FSP = 0x1
7231 08:06:24.597825 WL = 0x5
7232 08:06:24.600347 RL = 0x5
7233 08:06:24.600837 BL = 0x2
7234 08:06:24.603831 RPST = 0x0
7235 08:06:24.604343 RD_PRE = 0x0
7236 08:06:24.607178 WR_PRE = 0x1
7237 08:06:24.607710 WR_PST = 0x1
7238 08:06:24.610375 DBI_WR = 0x0
7239 08:06:24.610942 DBI_RD = 0x0
7240 08:06:24.613585 OTF = 0x1
7241 08:06:24.616931 ===================================
7242 08:06:24.624289 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7243 08:06:24.624768 ==
7244 08:06:24.627037 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 08:06:24.630594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7246 08:06:24.631083 ==
7247 08:06:24.633596 [Duty_Offset_Calibration]
7248 08:06:24.634015 B0:2 B1:0 CA:4
7249 08:06:24.634351
7250 08:06:24.636870 [DutyScan_Calibration_Flow] k_type=0
7251 08:06:24.648244
7252 08:06:24.648666 ==CLK 0==
7253 08:06:24.651173 Final CLK duty delay cell = 0
7254 08:06:24.654493 [0] MAX Duty = 5062%(X100), DQS PI = 20
7255 08:06:24.658513 [0] MIN Duty = 4876%(X100), DQS PI = 54
7256 08:06:24.658938 [0] AVG Duty = 4969%(X100)
7257 08:06:24.661191
7258 08:06:24.664528 CH0 CLK Duty spec in!! Max-Min= 186%
7259 08:06:24.667973 [DutyScan_Calibration_Flow] ====Done====
7260 08:06:24.668397
7261 08:06:24.670994 [DutyScan_Calibration_Flow] k_type=1
7262 08:06:24.688586
7263 08:06:24.689008 ==DQS 0 ==
7264 08:06:24.691123 Final DQS duty delay cell = 0
7265 08:06:24.694504 [0] MAX Duty = 5125%(X100), DQS PI = 28
7266 08:06:24.697956 [0] MIN Duty = 4875%(X100), DQS PI = 48
7267 08:06:24.701565 [0] AVG Duty = 5000%(X100)
7268 08:06:24.702017
7269 08:06:24.702371 ==DQS 1 ==
7270 08:06:24.704568 Final DQS duty delay cell = 0
7271 08:06:24.707836 [0] MAX Duty = 5156%(X100), DQS PI = 32
7272 08:06:24.711165 [0] MIN Duty = 5062%(X100), DQS PI = 8
7273 08:06:24.714481 [0] AVG Duty = 5109%(X100)
7274 08:06:24.714563
7275 08:06:24.717732 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7276 08:06:24.717814
7277 08:06:24.720711 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7278 08:06:24.723924 [DutyScan_Calibration_Flow] ====Done====
7279 08:06:24.724006
7280 08:06:24.727787 [DutyScan_Calibration_Flow] k_type=3
7281 08:06:24.745183
7282 08:06:24.745273 ==DQM 0 ==
7283 08:06:24.747841 Final DQM duty delay cell = 0
7284 08:06:24.751277 [0] MAX Duty = 5187%(X100), DQS PI = 32
7285 08:06:24.754626 [0] MIN Duty = 4875%(X100), DQS PI = 0
7286 08:06:24.757935 [0] AVG Duty = 5031%(X100)
7287 08:06:24.758034
7288 08:06:24.758126 ==DQM 1 ==
7289 08:06:24.761261 Final DQM duty delay cell = 0
7290 08:06:24.764518 [0] MAX Duty = 4938%(X100), DQS PI = 0
7291 08:06:24.768231 [0] MIN Duty = 4813%(X100), DQS PI = 20
7292 08:06:24.768302 [0] AVG Duty = 4875%(X100)
7293 08:06:24.771420
7294 08:06:24.774409 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7295 08:06:24.774506
7296 08:06:24.777720 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7297 08:06:24.781196 [DutyScan_Calibration_Flow] ====Done====
7298 08:06:24.781294
7299 08:06:24.784233 [DutyScan_Calibration_Flow] k_type=2
7300 08:06:24.801283
7301 08:06:24.801370 ==DQ 0 ==
7302 08:06:24.804385 Final DQ duty delay cell = -4
7303 08:06:24.807546 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7304 08:06:24.810993 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7305 08:06:24.814074 [-4] AVG Duty = 4938%(X100)
7306 08:06:24.814153
7307 08:06:24.814218 ==DQ 1 ==
7308 08:06:24.817686 Final DQ duty delay cell = 0
7309 08:06:24.820781 [0] MAX Duty = 5156%(X100), DQS PI = 60
7310 08:06:24.824094 [0] MIN Duty = 5000%(X100), DQS PI = 16
7311 08:06:24.827491 [0] AVG Duty = 5078%(X100)
7312 08:06:24.827590
7313 08:06:24.830805 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7314 08:06:24.830903
7315 08:06:24.834313 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7316 08:06:24.837228 [DutyScan_Calibration_Flow] ====Done====
7317 08:06:24.837298 ==
7318 08:06:24.840644 Dram Type= 6, Freq= 0, CH_1, rank 0
7319 08:06:24.843800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7320 08:06:24.843899 ==
7321 08:06:24.847208 [Duty_Offset_Calibration]
7322 08:06:24.847303 B0:1 B1:-2 CA:0
7323 08:06:24.847424
7324 08:06:24.850307 [DutyScan_Calibration_Flow] k_type=0
7325 08:06:24.861369
7326 08:06:24.861442 ==CLK 0==
7327 08:06:24.865140 Final CLK duty delay cell = 0
7328 08:06:24.868734 [0] MAX Duty = 5062%(X100), DQS PI = 20
7329 08:06:24.871244 [0] MIN Duty = 4844%(X100), DQS PI = 60
7330 08:06:24.874734 [0] AVG Duty = 4953%(X100)
7331 08:06:24.874840
7332 08:06:24.878124 CH1 CLK Duty spec in!! Max-Min= 218%
7333 08:06:24.881692 [DutyScan_Calibration_Flow] ====Done====
7334 08:06:24.881804
7335 08:06:24.885036 [DutyScan_Calibration_Flow] k_type=1
7336 08:06:24.901390
7337 08:06:24.901553 ==DQS 0 ==
7338 08:06:24.904568 Final DQS duty delay cell = 0
7339 08:06:24.908314 [0] MAX Duty = 5187%(X100), DQS PI = 22
7340 08:06:24.911711 [0] MIN Duty = 5031%(X100), DQS PI = 54
7341 08:06:24.914682 [0] AVG Duty = 5109%(X100)
7342 08:06:24.915049
7343 08:06:24.915409 ==DQS 1 ==
7344 08:06:24.917977 Final DQS duty delay cell = 0
7345 08:06:24.921513 [0] MAX Duty = 5062%(X100), DQS PI = 0
7346 08:06:24.925087 [0] MIN Duty = 4844%(X100), DQS PI = 24
7347 08:06:24.928361 [0] AVG Duty = 4953%(X100)
7348 08:06:24.928855
7349 08:06:24.931426 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7350 08:06:24.931907
7351 08:06:24.934870 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7352 08:06:24.937942 [DutyScan_Calibration_Flow] ====Done====
7353 08:06:24.938525
7354 08:06:24.941908 [DutyScan_Calibration_Flow] k_type=3
7355 08:06:24.958488
7356 08:06:24.958972 ==DQM 0 ==
7357 08:06:24.962155 Final DQM duty delay cell = 0
7358 08:06:24.965126 [0] MAX Duty = 5031%(X100), DQS PI = 24
7359 08:06:24.968338 [0] MIN Duty = 4813%(X100), DQS PI = 54
7360 08:06:24.971552 [0] AVG Duty = 4922%(X100)
7361 08:06:24.972039
7362 08:06:24.972513 ==DQM 1 ==
7363 08:06:24.974941 Final DQM duty delay cell = 0
7364 08:06:24.978305 [0] MAX Duty = 5062%(X100), DQS PI = 34
7365 08:06:24.981855 [0] MIN Duty = 4875%(X100), DQS PI = 24
7366 08:06:24.984870 [0] AVG Duty = 4968%(X100)
7367 08:06:24.985361
7368 08:06:24.988320 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7369 08:06:24.988823
7370 08:06:24.991851 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7371 08:06:24.995423 [DutyScan_Calibration_Flow] ====Done====
7372 08:06:24.995912
7373 08:06:24.998122 [DutyScan_Calibration_Flow] k_type=2
7374 08:06:25.015466
7375 08:06:25.016045 ==DQ 0 ==
7376 08:06:25.019075 Final DQ duty delay cell = 0
7377 08:06:25.022306 [0] MAX Duty = 5093%(X100), DQS PI = 22
7378 08:06:25.025326 [0] MIN Duty = 4907%(X100), DQS PI = 46
7379 08:06:25.025876 [0] AVG Duty = 5000%(X100)
7380 08:06:25.028636
7381 08:06:25.029332 ==DQ 1 ==
7382 08:06:25.032199 Final DQ duty delay cell = 0
7383 08:06:25.035370 [0] MAX Duty = 5125%(X100), DQS PI = 34
7384 08:06:25.038860 [0] MIN Duty = 4969%(X100), DQS PI = 24
7385 08:06:25.039444 [0] AVG Duty = 5047%(X100)
7386 08:06:25.042061
7387 08:06:25.045134 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7388 08:06:25.045678
7389 08:06:25.048593 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7390 08:06:25.052230 [DutyScan_Calibration_Flow] ====Done====
7391 08:06:25.054980 nWR fixed to 30
7392 08:06:25.055469 [ModeRegInit_LP4] CH0 RK0
7393 08:06:25.058705 [ModeRegInit_LP4] CH0 RK1
7394 08:06:25.061713 [ModeRegInit_LP4] CH1 RK0
7395 08:06:25.065233 [ModeRegInit_LP4] CH1 RK1
7396 08:06:25.065676 match AC timing 5
7397 08:06:25.071620 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7398 08:06:25.074713 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7399 08:06:25.078237 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7400 08:06:25.085070 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7401 08:06:25.088380 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7402 08:06:25.088822 [MiockJmeterHQA]
7403 08:06:25.089188
7404 08:06:25.091795 [DramcMiockJmeter] u1RxGatingPI = 0
7405 08:06:25.094942 0 : 4253, 4026
7406 08:06:25.095452 4 : 4255, 4029
7407 08:06:25.098163 8 : 4252, 4027
7408 08:06:25.098727 12 : 4252, 4027
7409 08:06:25.099151 16 : 4252, 4027
7410 08:06:25.101691 20 : 4253, 4026
7411 08:06:25.102200 24 : 4252, 4027
7412 08:06:25.105109 28 : 4365, 4140
7413 08:06:25.105602 32 : 4252, 4027
7414 08:06:25.108730 36 : 4255, 4029
7415 08:06:25.109341 40 : 4253, 4027
7416 08:06:25.111146 44 : 4363, 4138
7417 08:06:25.111689 48 : 4252, 4027
7418 08:06:25.112148 52 : 4361, 4137
7419 08:06:25.114877 56 : 4250, 4027
7420 08:06:25.115443 60 : 4250, 4026
7421 08:06:25.118215 64 : 4250, 4027
7422 08:06:25.118755 68 : 4252, 4029
7423 08:06:25.122091 72 : 4250, 4027
7424 08:06:25.122587 76 : 4250, 4027
7425 08:06:25.124681 80 : 4363, 4140
7426 08:06:25.125120 84 : 4250, 4027
7427 08:06:25.125468 88 : 4252, 4029
7428 08:06:25.127872 92 : 4250, 4026
7429 08:06:25.128320 96 : 4360, 4138
7430 08:06:25.131315 100 : 4250, 4027
7431 08:06:25.131811 104 : 4250, 3808
7432 08:06:25.134588 108 : 4250, 5
7433 08:06:25.135048 112 : 4250, 0
7434 08:06:25.135531 116 : 4250, 0
7435 08:06:25.138107 120 : 4250, 0
7436 08:06:25.138539 124 : 4250, 0
7437 08:06:25.141475 128 : 4250, 0
7438 08:06:25.141907 132 : 4250, 0
7439 08:06:25.142277 136 : 4250, 0
7440 08:06:25.144865 140 : 4250, 0
7441 08:06:25.145443 144 : 4250, 0
7442 08:06:25.147743 148 : 4361, 0
7443 08:06:25.148171 152 : 4360, 0
7444 08:06:25.148532 156 : 4250, 0
7445 08:06:25.151037 160 : 4250, 0
7446 08:06:25.151516 164 : 4250, 0
7447 08:06:25.151892 168 : 4250, 0
7448 08:06:25.154492 172 : 4250, 0
7449 08:06:25.154923 176 : 4250, 0
7450 08:06:25.157635 180 : 4250, 0
7451 08:06:25.158080 184 : 4361, 0
7452 08:06:25.158450 188 : 4250, 0
7453 08:06:25.161110 192 : 4250, 0
7454 08:06:25.161559 196 : 4250, 0
7455 08:06:25.164547 200 : 4361, 0
7456 08:06:25.164991 204 : 4360, 0
7457 08:06:25.165367 208 : 4250, 0
7458 08:06:25.167901 212 : 4250, 0
7459 08:06:25.168357 216 : 4360, 0
7460 08:06:25.170921 220 : 4250, 0
7461 08:06:25.171537 224 : 4250, 0
7462 08:06:25.171990 228 : 4250, 0
7463 08:06:25.174303 232 : 4250, 0
7464 08:06:25.174834 236 : 4361, 1167
7465 08:06:25.177721 240 : 4250, 4027
7466 08:06:25.178187 244 : 4360, 4138
7467 08:06:25.180899 248 : 4250, 4027
7468 08:06:25.181344 252 : 4250, 4027
7469 08:06:25.184709 256 : 4250, 4027
7470 08:06:25.185152 260 : 4252, 4029
7471 08:06:25.185498 264 : 4250, 4027
7472 08:06:25.187489 268 : 4250, 4027
7473 08:06:25.187952 272 : 4249, 4027
7474 08:06:25.190829 276 : 4252, 4029
7475 08:06:25.191272 280 : 4250, 4026
7476 08:06:25.194215 284 : 4361, 4137
7477 08:06:25.194708 288 : 4363, 4140
7478 08:06:25.197482 292 : 4250, 4027
7479 08:06:25.198022 296 : 4363, 4140
7480 08:06:25.200922 300 : 4250, 4027
7481 08:06:25.201433 304 : 4250, 4027
7482 08:06:25.203948 308 : 4250, 4027
7483 08:06:25.204492 312 : 4252, 4029
7484 08:06:25.207504 316 : 4250, 4027
7485 08:06:25.208021 320 : 4252, 4027
7486 08:06:25.208474 324 : 4250, 4027
7487 08:06:25.210993 328 : 4252, 4029
7488 08:06:25.211662 332 : 4250, 4026
7489 08:06:25.214165 336 : 4361, 4137
7490 08:06:25.214673 340 : 4361, 4138
7491 08:06:25.217662 344 : 4250, 4027
7492 08:06:25.218223 348 : 4363, 4140
7493 08:06:25.221230 352 : 4250, 4020
7494 08:06:25.221742 356 : 4250, 3032
7495 08:06:25.224360 360 : 4250, 6
7496 08:06:25.224859
7497 08:06:25.225272 MIOCK jitter meter ch=0
7498 08:06:25.225692
7499 08:06:25.227504 1T = (360-108) = 252 dly cells
7500 08:06:25.234079 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7501 08:06:25.234453 ==
7502 08:06:25.237645 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 08:06:25.240939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 08:06:25.241354 ==
7505 08:06:25.247726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 08:06:25.250851 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 08:06:25.254572 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 08:06:25.260879 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 08:06:25.270266 [CA 0] Center 44 (14~75) winsize 62
7510 08:06:25.273545 [CA 1] Center 43 (13~74) winsize 62
7511 08:06:25.277106 [CA 2] Center 39 (10~69) winsize 60
7512 08:06:25.280364 [CA 3] Center 39 (10~68) winsize 59
7513 08:06:25.283357 [CA 4] Center 37 (8~67) winsize 60
7514 08:06:25.286896 [CA 5] Center 37 (7~67) winsize 61
7515 08:06:25.287200
7516 08:06:25.290450 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 08:06:25.290786
7518 08:06:25.293737 [CATrainingPosCal] consider 1 rank data
7519 08:06:25.297226 u2DelayCellTimex100 = 258/100 ps
7520 08:06:25.303598 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7521 08:06:25.306881 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7522 08:06:25.310322 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7523 08:06:25.313569 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7524 08:06:25.316696 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7525 08:06:25.319920 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7526 08:06:25.320234
7527 08:06:25.323436 CA PerBit enable=1, Macro0, CA PI delay=37
7528 08:06:25.323749
7529 08:06:25.327035 [CBTSetCACLKResult] CA Dly = 37
7530 08:06:25.330406 CS Dly: 11 (0~42)
7531 08:06:25.333460 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 08:06:25.336680 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 08:06:25.337049 ==
7534 08:06:25.340250 Dram Type= 6, Freq= 0, CH_0, rank 1
7535 08:06:25.347052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 08:06:25.347369 ==
7537 08:06:25.350296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 08:06:25.353379 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 08:06:25.359836 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 08:06:25.366338 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 08:06:25.374207 [CA 0] Center 44 (14~75) winsize 62
7542 08:06:25.377617 [CA 1] Center 43 (13~74) winsize 62
7543 08:06:25.380762 [CA 2] Center 39 (10~69) winsize 60
7544 08:06:25.384111 [CA 3] Center 39 (10~69) winsize 60
7545 08:06:25.387920 [CA 4] Center 37 (8~67) winsize 60
7546 08:06:25.391034 [CA 5] Center 37 (7~67) winsize 61
7547 08:06:25.391631
7548 08:06:25.394134 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7549 08:06:25.394575
7550 08:06:25.397290 [CATrainingPosCal] consider 2 rank data
7551 08:06:25.400713 u2DelayCellTimex100 = 258/100 ps
7552 08:06:25.407257 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7553 08:06:25.410431 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7554 08:06:25.413854 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7555 08:06:25.417320 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7556 08:06:25.420751 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7557 08:06:25.423768 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7558 08:06:25.424370
7559 08:06:25.426993 CA PerBit enable=1, Macro0, CA PI delay=37
7560 08:06:25.427616
7561 08:06:25.430190 [CBTSetCACLKResult] CA Dly = 37
7562 08:06:25.433972 CS Dly: 11 (0~43)
7563 08:06:25.437181 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 08:06:25.440620 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 08:06:25.441073
7566 08:06:25.443968 ----->DramcWriteLeveling(PI) begin...
7567 08:06:25.444411 ==
7568 08:06:25.446823 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 08:06:25.453551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 08:06:25.453994 ==
7571 08:06:25.456969 Write leveling (Byte 0): 36 => 36
7572 08:06:25.460143 Write leveling (Byte 1): 30 => 30
7573 08:06:25.460584 DramcWriteLeveling(PI) end<-----
7574 08:06:25.463662
7575 08:06:25.464099 ==
7576 08:06:25.466923 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 08:06:25.470066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 08:06:25.470517 ==
7579 08:06:25.473253 [Gating] SW mode calibration
7580 08:06:25.480235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7581 08:06:25.483222 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7582 08:06:25.490091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 08:06:25.493231 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 08:06:25.496361 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 08:06:25.503257 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 08:06:25.506662 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7587 08:06:25.510397 1 4 20 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7588 08:06:25.516361 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7589 08:06:25.519680 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 08:06:25.523474 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 08:06:25.529736 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 08:06:25.533489 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 08:06:25.536678 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7594 08:06:25.543074 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7595 08:06:25.546450 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7596 08:06:25.549821 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7597 08:06:25.556740 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 08:06:25.559934 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 08:06:25.563250 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 08:06:25.569392 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 08:06:25.573157 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 08:06:25.576612 1 6 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7603 08:06:25.582849 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7604 08:06:25.586302 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7605 08:06:25.589598 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 08:06:25.595960 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 08:06:25.599356 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 08:06:25.602810 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 08:06:25.609350 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 08:06:25.612679 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 08:06:25.616023 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7612 08:06:25.622390 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 08:06:25.626103 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 08:06:25.629241 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 08:06:25.636007 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 08:06:25.639477 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 08:06:25.642409 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 08:06:25.649119 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 08:06:25.652154 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 08:06:25.655501 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 08:06:25.662393 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 08:06:25.665778 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 08:06:25.669293 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 08:06:25.675835 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 08:06:25.678701 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 08:06:25.682070 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 08:06:25.685744 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 08:06:25.691795 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7629 08:06:25.695132 Total UI for P1: 0, mck2ui 16
7630 08:06:25.699041 best dqsien dly found for B0: ( 1, 9, 18)
7631 08:06:25.701936 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 08:06:25.705205 Total UI for P1: 0, mck2ui 16
7633 08:06:25.708866 best dqsien dly found for B1: ( 1, 9, 24)
7634 08:06:25.711735 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7635 08:06:25.715305 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7636 08:06:25.715798
7637 08:06:25.718672 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7638 08:06:25.725168 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7639 08:06:25.725625 [Gating] SW calibration Done
7640 08:06:25.725987 ==
7641 08:06:25.728291 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 08:06:25.734935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 08:06:25.735552 ==
7644 08:06:25.736000 RX Vref Scan: 0
7645 08:06:25.736410
7646 08:06:25.738063 RX Vref 0 -> 0, step: 1
7647 08:06:25.738664
7648 08:06:25.741816 RX Delay 0 -> 252, step: 8
7649 08:06:25.745006 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7650 08:06:25.748361 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7651 08:06:25.751270 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7652 08:06:25.758223 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7653 08:06:25.761812 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7654 08:06:25.765034 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7655 08:06:25.768237 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7656 08:06:25.771302 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7657 08:06:25.778254 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7658 08:06:25.781207 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7659 08:06:25.784490 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7660 08:06:25.788112 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7661 08:06:25.791021 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7662 08:06:25.798031 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7663 08:06:25.801084 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7664 08:06:25.804548 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7665 08:06:25.805047 ==
7666 08:06:25.808091 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 08:06:25.811036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 08:06:25.811648 ==
7669 08:06:25.814589 DQS Delay:
7670 08:06:25.815023 DQS0 = 0, DQS1 = 0
7671 08:06:25.817819 DQM Delay:
7672 08:06:25.818249 DQM0 = 128, DQM1 = 124
7673 08:06:25.821271 DQ Delay:
7674 08:06:25.824550 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7675 08:06:25.827610 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
7676 08:06:25.830985 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7677 08:06:25.834279 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7678 08:06:25.834848
7679 08:06:25.835219
7680 08:06:25.835594 ==
7681 08:06:25.837782 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 08:06:25.841278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 08:06:25.841834 ==
7684 08:06:25.842216
7685 08:06:25.842555
7686 08:06:25.844256 TX Vref Scan disable
7687 08:06:25.847891 == TX Byte 0 ==
7688 08:06:25.850717 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7689 08:06:25.854665 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7690 08:06:25.857245 == TX Byte 1 ==
7691 08:06:25.860646 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7692 08:06:25.864231 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7693 08:06:25.864864 ==
7694 08:06:25.867893 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 08:06:25.874087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 08:06:25.874621 ==
7697 08:06:25.887203
7698 08:06:25.890754 TX Vref early break, caculate TX vref
7699 08:06:25.894199 TX Vref=16, minBit 5, minWin=22, winSum=364
7700 08:06:25.897222 TX Vref=18, minBit 0, minWin=23, winSum=379
7701 08:06:25.900460 TX Vref=20, minBit 4, minWin=23, winSum=392
7702 08:06:25.903849 TX Vref=22, minBit 4, minWin=24, winSum=399
7703 08:06:25.907097 TX Vref=24, minBit 4, minWin=24, winSum=409
7704 08:06:25.913986 TX Vref=26, minBit 3, minWin=25, winSum=414
7705 08:06:25.917051 TX Vref=28, minBit 4, minWin=24, winSum=414
7706 08:06:25.920452 TX Vref=30, minBit 8, minWin=24, winSum=407
7707 08:06:25.924043 TX Vref=32, minBit 8, minWin=24, winSum=404
7708 08:06:25.926759 TX Vref=34, minBit 9, minWin=23, winSum=394
7709 08:06:25.930401 TX Vref=36, minBit 4, minWin=23, winSum=385
7710 08:06:25.936916 [TxChooseVref] Worse bit 3, Min win 25, Win sum 414, Final Vref 26
7711 08:06:25.937343
7712 08:06:25.940664 Final TX Range 0 Vref 26
7713 08:06:25.941116
7714 08:06:25.941479 ==
7715 08:06:25.943716 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 08:06:25.946637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 08:06:25.947064 ==
7718 08:06:25.947446
7719 08:06:25.950103
7720 08:06:25.950527 TX Vref Scan disable
7721 08:06:25.957156 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7722 08:06:25.957597 == TX Byte 0 ==
7723 08:06:25.960470 u2DelayCellOfst[0]=11 cells (3 PI)
7724 08:06:25.963810 u2DelayCellOfst[1]=15 cells (4 PI)
7725 08:06:25.967432 u2DelayCellOfst[2]=7 cells (2 PI)
7726 08:06:25.970297 u2DelayCellOfst[3]=7 cells (2 PI)
7727 08:06:25.973675 u2DelayCellOfst[4]=3 cells (1 PI)
7728 08:06:25.976906 u2DelayCellOfst[5]=0 cells (0 PI)
7729 08:06:25.980103 u2DelayCellOfst[6]=15 cells (4 PI)
7730 08:06:25.983611 u2DelayCellOfst[7]=15 cells (4 PI)
7731 08:06:25.986985 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7732 08:06:25.990233 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7733 08:06:25.993198 == TX Byte 1 ==
7734 08:06:25.997114 u2DelayCellOfst[8]=0 cells (0 PI)
7735 08:06:26.000044 u2DelayCellOfst[9]=3 cells (1 PI)
7736 08:06:26.000486 u2DelayCellOfst[10]=7 cells (2 PI)
7737 08:06:26.003308 u2DelayCellOfst[11]=3 cells (1 PI)
7738 08:06:26.006858 u2DelayCellOfst[12]=15 cells (4 PI)
7739 08:06:26.009949 u2DelayCellOfst[13]=11 cells (3 PI)
7740 08:06:26.013656 u2DelayCellOfst[14]=18 cells (5 PI)
7741 08:06:26.016961 u2DelayCellOfst[15]=11 cells (3 PI)
7742 08:06:26.019958 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7743 08:06:26.027005 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7744 08:06:26.027625 DramC Write-DBI on
7745 08:06:26.028177 ==
7746 08:06:26.030074 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 08:06:26.036196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 08:06:26.036632 ==
7749 08:06:26.036993
7750 08:06:26.037327
7751 08:06:26.037631 TX Vref Scan disable
7752 08:06:26.040404 == TX Byte 0 ==
7753 08:06:26.044030 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7754 08:06:26.047354 == TX Byte 1 ==
7755 08:06:26.050706 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7756 08:06:26.054136 DramC Write-DBI off
7757 08:06:26.054653
7758 08:06:26.055100 [DATLAT]
7759 08:06:26.055675 Freq=1600, CH0 RK0
7760 08:06:26.056106
7761 08:06:26.057144 DATLAT Default: 0xf
7762 08:06:26.057623 0, 0xFFFF, sum = 0
7763 08:06:26.060504 1, 0xFFFF, sum = 0
7764 08:06:26.063519 2, 0xFFFF, sum = 0
7765 08:06:26.064051 3, 0xFFFF, sum = 0
7766 08:06:26.066909 4, 0xFFFF, sum = 0
7767 08:06:26.067587 5, 0xFFFF, sum = 0
7768 08:06:26.070602 6, 0xFFFF, sum = 0
7769 08:06:26.071027 7, 0xFFFF, sum = 0
7770 08:06:26.073565 8, 0xFFFF, sum = 0
7771 08:06:26.074216 9, 0xFFFF, sum = 0
7772 08:06:26.077049 10, 0xFFFF, sum = 0
7773 08:06:26.077449 11, 0xFFFF, sum = 0
7774 08:06:26.080627 12, 0xFFFF, sum = 0
7775 08:06:26.081074 13, 0xEFFF, sum = 0
7776 08:06:26.084075 14, 0x0, sum = 1
7777 08:06:26.084524 15, 0x0, sum = 2
7778 08:06:26.086912 16, 0x0, sum = 3
7779 08:06:26.087354 17, 0x0, sum = 4
7780 08:06:26.090344 best_step = 15
7781 08:06:26.090774
7782 08:06:26.091132 ==
7783 08:06:26.093817 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 08:06:26.097296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 08:06:26.097732 ==
7786 08:06:26.100460 RX Vref Scan: 1
7787 08:06:26.100915
7788 08:06:26.101284 Set Vref Range= 24 -> 127
7789 08:06:26.101639
7790 08:06:26.104101 RX Vref 24 -> 127, step: 1
7791 08:06:26.104539
7792 08:06:26.107537 RX Delay 11 -> 252, step: 4
7793 08:06:26.107973
7794 08:06:26.110105 Set Vref, RX VrefLevel [Byte0]: 24
7795 08:06:26.113716 [Byte1]: 24
7796 08:06:26.114151
7797 08:06:26.116993 Set Vref, RX VrefLevel [Byte0]: 25
7798 08:06:26.120743 [Byte1]: 25
7799 08:06:26.123146
7800 08:06:26.123813 Set Vref, RX VrefLevel [Byte0]: 26
7801 08:06:26.126636 [Byte1]: 26
7802 08:06:26.130942
7803 08:06:26.131428 Set Vref, RX VrefLevel [Byte0]: 27
7804 08:06:26.134318 [Byte1]: 27
7805 08:06:26.138459
7806 08:06:26.138915 Set Vref, RX VrefLevel [Byte0]: 28
7807 08:06:26.141929 [Byte1]: 28
7808 08:06:26.146137
7809 08:06:26.146756 Set Vref, RX VrefLevel [Byte0]: 29
7810 08:06:26.149203 [Byte1]: 29
7811 08:06:26.154163
7812 08:06:26.154800 Set Vref, RX VrefLevel [Byte0]: 30
7813 08:06:26.156971 [Byte1]: 30
7814 08:06:26.161433
7815 08:06:26.161874 Set Vref, RX VrefLevel [Byte0]: 31
7816 08:06:26.164588 [Byte1]: 31
7817 08:06:26.169059
7818 08:06:26.169677 Set Vref, RX VrefLevel [Byte0]: 32
7819 08:06:26.172521 [Byte1]: 32
7820 08:06:26.176921
7821 08:06:26.177444 Set Vref, RX VrefLevel [Byte0]: 33
7822 08:06:26.179847 [Byte1]: 33
7823 08:06:26.184503
7824 08:06:26.185062 Set Vref, RX VrefLevel [Byte0]: 34
7825 08:06:26.187160 [Byte1]: 34
7826 08:06:26.191905
7827 08:06:26.192513 Set Vref, RX VrefLevel [Byte0]: 35
7828 08:06:26.195146 [Byte1]: 35
7829 08:06:26.199696
7830 08:06:26.200123 Set Vref, RX VrefLevel [Byte0]: 36
7831 08:06:26.202762 [Byte1]: 36
7832 08:06:26.207062
7833 08:06:26.207537 Set Vref, RX VrefLevel [Byte0]: 37
7834 08:06:26.210691 [Byte1]: 37
7835 08:06:26.214468
7836 08:06:26.214901 Set Vref, RX VrefLevel [Byte0]: 38
7837 08:06:26.218102 [Byte1]: 38
7838 08:06:26.222496
7839 08:06:26.223028 Set Vref, RX VrefLevel [Byte0]: 39
7840 08:06:26.225729 [Byte1]: 39
7841 08:06:26.230539
7842 08:06:26.231076 Set Vref, RX VrefLevel [Byte0]: 40
7843 08:06:26.233099 [Byte1]: 40
7844 08:06:26.237748
7845 08:06:26.238188 Set Vref, RX VrefLevel [Byte0]: 41
7846 08:06:26.240447 [Byte1]: 41
7847 08:06:26.245349
7848 08:06:26.245921 Set Vref, RX VrefLevel [Byte0]: 42
7849 08:06:26.248409 [Byte1]: 42
7850 08:06:26.252682
7851 08:06:26.253119 Set Vref, RX VrefLevel [Byte0]: 43
7852 08:06:26.255923 [Byte1]: 43
7853 08:06:26.260384
7854 08:06:26.260826 Set Vref, RX VrefLevel [Byte0]: 44
7855 08:06:26.263325 [Byte1]: 44
7856 08:06:26.267843
7857 08:06:26.268290 Set Vref, RX VrefLevel [Byte0]: 45
7858 08:06:26.271638 [Byte1]: 45
7859 08:06:26.275442
7860 08:06:26.276075 Set Vref, RX VrefLevel [Byte0]: 46
7861 08:06:26.278567 [Byte1]: 46
7862 08:06:26.283030
7863 08:06:26.283515 Set Vref, RX VrefLevel [Byte0]: 47
7864 08:06:26.286372 [Byte1]: 47
7865 08:06:26.290720
7866 08:06:26.291167 Set Vref, RX VrefLevel [Byte0]: 48
7867 08:06:26.294198 [Byte1]: 48
7868 08:06:26.298451
7869 08:06:26.298914 Set Vref, RX VrefLevel [Byte0]: 49
7870 08:06:26.301533 [Byte1]: 49
7871 08:06:26.305884
7872 08:06:26.306322 Set Vref, RX VrefLevel [Byte0]: 50
7873 08:06:26.309042 [Byte1]: 50
7874 08:06:26.313304
7875 08:06:26.313759 Set Vref, RX VrefLevel [Byte0]: 51
7876 08:06:26.317402 [Byte1]: 51
7877 08:06:26.321274
7878 08:06:26.321722 Set Vref, RX VrefLevel [Byte0]: 52
7879 08:06:26.324706 [Byte1]: 52
7880 08:06:26.328899
7881 08:06:26.329351 Set Vref, RX VrefLevel [Byte0]: 53
7882 08:06:26.332007 [Byte1]: 53
7883 08:06:26.336377
7884 08:06:26.336944 Set Vref, RX VrefLevel [Byte0]: 54
7885 08:06:26.339879 [Byte1]: 54
7886 08:06:26.344086
7887 08:06:26.344520 Set Vref, RX VrefLevel [Byte0]: 55
7888 08:06:26.347351 [Byte1]: 55
7889 08:06:26.352069
7890 08:06:26.352540 Set Vref, RX VrefLevel [Byte0]: 56
7891 08:06:26.355198 [Byte1]: 56
7892 08:06:26.359113
7893 08:06:26.359645 Set Vref, RX VrefLevel [Byte0]: 57
7894 08:06:26.362442 [Byte1]: 57
7895 08:06:26.366642
7896 08:06:26.367083 Set Vref, RX VrefLevel [Byte0]: 58
7897 08:06:26.370173 [Byte1]: 58
7898 08:06:26.374494
7899 08:06:26.375073 Set Vref, RX VrefLevel [Byte0]: 59
7900 08:06:26.377776 [Byte1]: 59
7901 08:06:26.381866
7902 08:06:26.382302 Set Vref, RX VrefLevel [Byte0]: 60
7903 08:06:26.385405 [Byte1]: 60
7904 08:06:26.389460
7905 08:06:26.389927 Set Vref, RX VrefLevel [Byte0]: 61
7906 08:06:26.393207 [Byte1]: 61
7907 08:06:26.397340
7908 08:06:26.397893 Set Vref, RX VrefLevel [Byte0]: 62
7909 08:06:26.400684 [Byte1]: 62
7910 08:06:26.404763
7911 08:06:26.405203 Set Vref, RX VrefLevel [Byte0]: 63
7912 08:06:26.408037 [Byte1]: 63
7913 08:06:26.412593
7914 08:06:26.413028 Set Vref, RX VrefLevel [Byte0]: 64
7915 08:06:26.415731 [Byte1]: 64
7916 08:06:26.420345
7917 08:06:26.420781 Set Vref, RX VrefLevel [Byte0]: 65
7918 08:06:26.423672 [Byte1]: 65
7919 08:06:26.427615
7920 08:06:26.428066 Set Vref, RX VrefLevel [Byte0]: 66
7921 08:06:26.430928 [Byte1]: 66
7922 08:06:26.435452
7923 08:06:26.435891 Set Vref, RX VrefLevel [Byte0]: 67
7924 08:06:26.438730 [Byte1]: 67
7925 08:06:26.442796
7926 08:06:26.443233 Set Vref, RX VrefLevel [Byte0]: 68
7927 08:06:26.446548 [Byte1]: 68
7928 08:06:26.450886
7929 08:06:26.451327 Set Vref, RX VrefLevel [Byte0]: 69
7930 08:06:26.454036 [Byte1]: 69
7931 08:06:26.458097
7932 08:06:26.458530 Set Vref, RX VrefLevel [Byte0]: 70
7933 08:06:26.461436 [Byte1]: 70
7934 08:06:26.465963
7935 08:06:26.466398 Set Vref, RX VrefLevel [Byte0]: 71
7936 08:06:26.469304 [Byte1]: 71
7937 08:06:26.473430
7938 08:06:26.473869 Set Vref, RX VrefLevel [Byte0]: 72
7939 08:06:26.476855 [Byte1]: 72
7940 08:06:26.481136
7941 08:06:26.481684 Set Vref, RX VrefLevel [Byte0]: 73
7942 08:06:26.484140 [Byte1]: 73
7943 08:06:26.489083
7944 08:06:26.489656 Set Vref, RX VrefLevel [Byte0]: 74
7945 08:06:26.492119 [Byte1]: 74
7946 08:06:26.496170
7947 08:06:26.496743 Set Vref, RX VrefLevel [Byte0]: 75
7948 08:06:26.499733 [Byte1]: 75
7949 08:06:26.504012
7950 08:06:26.504447 Set Vref, RX VrefLevel [Byte0]: 76
7951 08:06:26.507270 [Byte1]: 76
7952 08:06:26.511578
7953 08:06:26.512104 Set Vref, RX VrefLevel [Byte0]: 77
7954 08:06:26.514975 [Byte1]: 77
7955 08:06:26.519055
7956 08:06:26.519619 Final RX Vref Byte 0 = 63 to rank0
7957 08:06:26.522472 Final RX Vref Byte 1 = 60 to rank0
7958 08:06:26.525973 Final RX Vref Byte 0 = 63 to rank1
7959 08:06:26.528951 Final RX Vref Byte 1 = 60 to rank1==
7960 08:06:26.532742 Dram Type= 6, Freq= 0, CH_0, rank 0
7961 08:06:26.539410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 08:06:26.539981 ==
7963 08:06:26.540409 DQS Delay:
7964 08:06:26.540755 DQS0 = 0, DQS1 = 0
7965 08:06:26.542347 DQM Delay:
7966 08:06:26.542783 DQM0 = 126, DQM1 = 120
7967 08:06:26.546110 DQ Delay:
7968 08:06:26.549250 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7969 08:06:26.552101 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7970 08:06:26.555718 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7971 08:06:26.558687 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7972 08:06:26.559121
7973 08:06:26.559500
7974 08:06:26.559843
7975 08:06:26.562693 [DramC_TX_OE_Calibration] TA2
7976 08:06:26.565555 Original DQ_B0 (3 6) =30, OEN = 27
7977 08:06:26.568664 Original DQ_B1 (3 6) =30, OEN = 27
7978 08:06:26.572036 24, 0x0, End_B0=24 End_B1=24
7979 08:06:26.572483 25, 0x0, End_B0=25 End_B1=25
7980 08:06:26.575547 26, 0x0, End_B0=26 End_B1=26
7981 08:06:26.578776 27, 0x0, End_B0=27 End_B1=27
7982 08:06:26.582267 28, 0x0, End_B0=28 End_B1=28
7983 08:06:26.585730 29, 0x0, End_B0=29 End_B1=29
7984 08:06:26.586159 30, 0x0, End_B0=30 End_B1=30
7985 08:06:26.589093 31, 0x4141, End_B0=30 End_B1=30
7986 08:06:26.592076 Byte0 end_step=30 best_step=27
7987 08:06:26.595437 Byte1 end_step=30 best_step=27
7988 08:06:26.598480 Byte0 TX OE(2T, 0.5T) = (3, 3)
7989 08:06:26.602114 Byte1 TX OE(2T, 0.5T) = (3, 3)
7990 08:06:26.602556
7991 08:06:26.602918
7992 08:06:26.608552 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7993 08:06:26.611909 CH0 RK0: MR19=303, MR18=1413
7994 08:06:26.618947 CH0_RK0: MR19=0x303, MR18=0x1413, DQSOSC=399, MR23=63, INC=23, DEC=15
7995 08:06:26.619376
7996 08:06:26.621986 ----->DramcWriteLeveling(PI) begin...
7997 08:06:26.622506 ==
7998 08:06:26.625564 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 08:06:26.628915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 08:06:26.629404 ==
8001 08:06:26.632103 Write leveling (Byte 0): 37 => 37
8002 08:06:26.635526 Write leveling (Byte 1): 28 => 28
8003 08:06:26.638693 DramcWriteLeveling(PI) end<-----
8004 08:06:26.639200
8005 08:06:26.639668 ==
8006 08:06:26.641964 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 08:06:26.645473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 08:06:26.645916 ==
8009 08:06:26.649042 [Gating] SW mode calibration
8010 08:06:26.655697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8011 08:06:26.661774 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8012 08:06:26.665160 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 08:06:26.668703 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 08:06:26.675227 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 08:06:26.678475 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8016 08:06:26.682014 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
8017 08:06:26.688465 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8018 08:06:26.691759 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 08:06:26.695272 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 08:06:26.701764 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 08:06:26.705134 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 08:06:26.708449 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
8023 08:06:26.715217 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 1)
8024 08:06:26.718715 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8025 08:06:26.721714 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 08:06:26.728602 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 08:06:26.732059 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 08:06:26.735715 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 08:06:26.741755 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 08:06:26.745185 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8031 08:06:26.748233 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8032 08:06:26.755201 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8033 08:06:26.758205 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8034 08:06:26.761636 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 08:06:26.768240 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 08:06:26.771091 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 08:06:26.774446 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 08:06:26.777777 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 08:06:26.784533 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 08:06:26.788072 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8041 08:06:26.791581 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 08:06:26.797687 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 08:06:26.801116 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 08:06:26.804165 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 08:06:26.810902 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 08:06:26.814310 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 08:06:26.817871 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 08:06:26.824185 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 08:06:26.827813 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 08:06:26.830960 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 08:06:26.837753 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 08:06:26.840800 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 08:06:26.843790 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 08:06:26.850690 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 08:06:26.854120 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8056 08:06:26.857449 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8057 08:06:26.861092 Total UI for P1: 0, mck2ui 16
8058 08:06:26.863944 best dqsien dly found for B0: ( 1, 9, 10)
8059 08:06:26.870665 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8060 08:06:26.874147 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 08:06:26.877105 Total UI for P1: 0, mck2ui 16
8062 08:06:26.880401 best dqsien dly found for B1: ( 1, 9, 18)
8063 08:06:26.883669 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8064 08:06:26.886884 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8065 08:06:26.886961
8066 08:06:26.890477 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8067 08:06:26.894022 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8068 08:06:26.897102 [Gating] SW calibration Done
8069 08:06:26.897178 ==
8070 08:06:26.900025 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 08:06:26.906838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 08:06:26.906917 ==
8073 08:06:26.906998 RX Vref Scan: 0
8074 08:06:26.907082
8075 08:06:26.910812 RX Vref 0 -> 0, step: 1
8076 08:06:26.910889
8077 08:06:26.913319 RX Delay 0 -> 252, step: 8
8078 08:06:26.916496 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8079 08:06:26.919938 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8080 08:06:26.923305 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8081 08:06:26.926848 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8082 08:06:26.933104 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8083 08:06:26.936352 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8084 08:06:26.939750 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8085 08:06:26.943068 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8086 08:06:26.946287 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8087 08:06:26.953175 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8088 08:06:26.956441 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8089 08:06:26.959948 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8090 08:06:26.962962 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8091 08:06:26.969431 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8092 08:06:26.972797 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8093 08:06:26.976326 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8094 08:06:26.976429 ==
8095 08:06:26.979576 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 08:06:26.982661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 08:06:26.982738 ==
8098 08:06:26.985892 DQS Delay:
8099 08:06:26.985968 DQS0 = 0, DQS1 = 0
8100 08:06:26.989541 DQM Delay:
8101 08:06:26.989618 DQM0 = 128, DQM1 = 120
8102 08:06:26.989698 DQ Delay:
8103 08:06:26.996369 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8104 08:06:26.999526 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8105 08:06:27.002698 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8106 08:06:27.005949 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8107 08:06:27.006052
8108 08:06:27.006133
8109 08:06:27.006211 ==
8110 08:06:27.009207 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 08:06:27.012504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 08:06:27.012586 ==
8113 08:06:27.012667
8114 08:06:27.012747
8115 08:06:27.015936 TX Vref Scan disable
8116 08:06:27.019101 == TX Byte 0 ==
8117 08:06:27.022547 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8118 08:06:27.025954 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8119 08:06:27.029500 == TX Byte 1 ==
8120 08:06:27.032256 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8121 08:06:27.035929 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8122 08:06:27.036001 ==
8123 08:06:27.039171 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 08:06:27.045835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 08:06:27.045911 ==
8126 08:06:27.058047
8127 08:06:27.061795 TX Vref early break, caculate TX vref
8128 08:06:27.064760 TX Vref=16, minBit 8, minWin=22, winSum=374
8129 08:06:27.068347 TX Vref=18, minBit 8, minWin=22, winSum=386
8130 08:06:27.071340 TX Vref=20, minBit 8, minWin=22, winSum=391
8131 08:06:27.074763 TX Vref=22, minBit 8, minWin=23, winSum=394
8132 08:06:27.078445 TX Vref=24, minBit 8, minWin=24, winSum=404
8133 08:06:27.084919 TX Vref=26, minBit 8, minWin=24, winSum=414
8134 08:06:27.087990 TX Vref=28, minBit 8, minWin=25, winSum=418
8135 08:06:27.091306 TX Vref=30, minBit 8, minWin=24, winSum=413
8136 08:06:27.094504 TX Vref=32, minBit 8, minWin=23, winSum=408
8137 08:06:27.098141 TX Vref=34, minBit 8, minWin=23, winSum=395
8138 08:06:27.104761 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8139 08:06:27.104838
8140 08:06:27.108175 Final TX Range 0 Vref 28
8141 08:06:27.108248
8142 08:06:27.108313 ==
8143 08:06:27.111245 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 08:06:27.114812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 08:06:27.114907 ==
8146 08:06:27.114969
8147 08:06:27.115026
8148 08:06:27.117903 TX Vref Scan disable
8149 08:06:27.124939 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8150 08:06:27.125012 == TX Byte 0 ==
8151 08:06:27.127837 u2DelayCellOfst[0]=11 cells (3 PI)
8152 08:06:27.131059 u2DelayCellOfst[1]=18 cells (5 PI)
8153 08:06:27.134688 u2DelayCellOfst[2]=11 cells (3 PI)
8154 08:06:27.137575 u2DelayCellOfst[3]=11 cells (3 PI)
8155 08:06:27.140762 u2DelayCellOfst[4]=7 cells (2 PI)
8156 08:06:27.144055 u2DelayCellOfst[5]=0 cells (0 PI)
8157 08:06:27.147652 u2DelayCellOfst[6]=18 cells (5 PI)
8158 08:06:27.150865 u2DelayCellOfst[7]=18 cells (5 PI)
8159 08:06:27.154360 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8160 08:06:27.157394 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8161 08:06:27.160864 == TX Byte 1 ==
8162 08:06:27.164190 u2DelayCellOfst[8]=0 cells (0 PI)
8163 08:06:27.164257 u2DelayCellOfst[9]=3 cells (1 PI)
8164 08:06:27.167332 u2DelayCellOfst[10]=11 cells (3 PI)
8165 08:06:27.171026 u2DelayCellOfst[11]=7 cells (2 PI)
8166 08:06:27.174086 u2DelayCellOfst[12]=11 cells (3 PI)
8167 08:06:27.177067 u2DelayCellOfst[13]=11 cells (3 PI)
8168 08:06:27.180497 u2DelayCellOfst[14]=15 cells (4 PI)
8169 08:06:27.183824 u2DelayCellOfst[15]=15 cells (4 PI)
8170 08:06:27.187342 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8171 08:06:27.194014 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8172 08:06:27.194088 DramC Write-DBI on
8173 08:06:27.194151 ==
8174 08:06:27.197248 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 08:06:27.204233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 08:06:27.204309 ==
8177 08:06:27.204371
8178 08:06:27.204430
8179 08:06:27.204486 TX Vref Scan disable
8180 08:06:27.207693 == TX Byte 0 ==
8181 08:06:27.211368 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8182 08:06:27.214679 == TX Byte 1 ==
8183 08:06:27.217808 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8184 08:06:27.217879 DramC Write-DBI off
8185 08:06:27.221893
8186 08:06:27.221990 [DATLAT]
8187 08:06:27.222077 Freq=1600, CH0 RK1
8188 08:06:27.222166
8189 08:06:27.224438 DATLAT Default: 0xf
8190 08:06:27.224510 0, 0xFFFF, sum = 0
8191 08:06:27.227692 1, 0xFFFF, sum = 0
8192 08:06:27.227763 2, 0xFFFF, sum = 0
8193 08:06:27.231295 3, 0xFFFF, sum = 0
8194 08:06:27.234787 4, 0xFFFF, sum = 0
8195 08:06:27.234858 5, 0xFFFF, sum = 0
8196 08:06:27.238314 6, 0xFFFF, sum = 0
8197 08:06:27.238385 7, 0xFFFF, sum = 0
8198 08:06:27.241092 8, 0xFFFF, sum = 0
8199 08:06:27.241187 9, 0xFFFF, sum = 0
8200 08:06:27.244502 10, 0xFFFF, sum = 0
8201 08:06:27.244578 11, 0xFFFF, sum = 0
8202 08:06:27.247866 12, 0xFFFF, sum = 0
8203 08:06:27.247941 13, 0xCFFF, sum = 0
8204 08:06:27.250931 14, 0x0, sum = 1
8205 08:06:27.251000 15, 0x0, sum = 2
8206 08:06:27.254250 16, 0x0, sum = 3
8207 08:06:27.254325 17, 0x0, sum = 4
8208 08:06:27.257528 best_step = 15
8209 08:06:27.257597
8210 08:06:27.257655 ==
8211 08:06:27.261028 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 08:06:27.264549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 08:06:27.264618 ==
8214 08:06:27.267421 RX Vref Scan: 0
8215 08:06:27.267489
8216 08:06:27.267552 RX Vref 0 -> 0, step: 1
8217 08:06:27.267609
8218 08:06:27.271286 RX Delay 3 -> 252, step: 4
8219 08:06:27.274340 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8220 08:06:27.281204 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8221 08:06:27.284147 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8222 08:06:27.287360 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8223 08:06:27.290951 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8224 08:06:27.294084 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8225 08:06:27.301210 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8226 08:06:27.304451 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8227 08:06:27.307309 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8228 08:06:27.310802 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8229 08:06:27.314177 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8230 08:06:27.320711 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8231 08:06:27.324634 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8232 08:06:27.327909 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8233 08:06:27.331248 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8234 08:06:27.333831 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8235 08:06:27.337737 ==
8236 08:06:27.341074 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 08:06:27.343999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 08:06:27.344073 ==
8239 08:06:27.344135 DQS Delay:
8240 08:06:27.347381 DQS0 = 0, DQS1 = 0
8241 08:06:27.347485 DQM Delay:
8242 08:06:27.350878 DQM0 = 124, DQM1 = 117
8243 08:06:27.350947 DQ Delay:
8244 08:06:27.354048 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8245 08:06:27.357251 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8246 08:06:27.360603 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8247 08:06:27.364048 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8248 08:06:27.364119
8249 08:06:27.364186
8250 08:06:27.364244
8251 08:06:27.367506 [DramC_TX_OE_Calibration] TA2
8252 08:06:27.371100 Original DQ_B0 (3 6) =30, OEN = 27
8253 08:06:27.373798 Original DQ_B1 (3 6) =30, OEN = 27
8254 08:06:27.377040 24, 0x0, End_B0=24 End_B1=24
8255 08:06:27.380663 25, 0x0, End_B0=25 End_B1=25
8256 08:06:27.380735 26, 0x0, End_B0=26 End_B1=26
8257 08:06:27.384181 27, 0x0, End_B0=27 End_B1=27
8258 08:06:27.387753 28, 0x0, End_B0=28 End_B1=28
8259 08:06:27.390565 29, 0x0, End_B0=29 End_B1=29
8260 08:06:27.390639 30, 0x0, End_B0=30 End_B1=30
8261 08:06:27.393994 31, 0x4545, End_B0=30 End_B1=30
8262 08:06:27.397485 Byte0 end_step=30 best_step=27
8263 08:06:27.400687 Byte1 end_step=30 best_step=27
8264 08:06:27.404064 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 08:06:27.407234 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 08:06:27.407318
8267 08:06:27.407439
8268 08:06:27.414140 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8269 08:06:27.417608 CH0 RK1: MR19=303, MR18=2412
8270 08:06:27.423859 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8271 08:06:27.426894 [RxdqsGatingPostProcess] freq 1600
8272 08:06:27.433861 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 08:06:27.433941 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 08:06:27.437098 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 08:06:27.440194 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 08:06:27.443684 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 08:06:27.446601 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 08:06:27.450031 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 08:06:27.453446 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 08:06:27.456848 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 08:06:27.460530 Pre-setting of DQS Precalculation
8282 08:06:27.463504 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 08:06:27.463586 ==
8284 08:06:27.466833 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 08:06:27.473300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 08:06:27.473378 ==
8287 08:06:27.476665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 08:06:27.483237 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 08:06:27.486745 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 08:06:27.493376 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 08:06:27.501163 [CA 0] Center 42 (13~71) winsize 59
8292 08:06:27.503936 [CA 1] Center 42 (12~72) winsize 61
8293 08:06:27.507551 [CA 2] Center 38 (9~67) winsize 59
8294 08:06:27.511271 [CA 3] Center 37 (8~66) winsize 59
8295 08:06:27.514322 [CA 4] Center 37 (8~67) winsize 60
8296 08:06:27.517533 [CA 5] Center 36 (7~66) winsize 60
8297 08:06:27.517609
8298 08:06:27.521281 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 08:06:27.521388
8300 08:06:27.524488 [CATrainingPosCal] consider 1 rank data
8301 08:06:27.527522 u2DelayCellTimex100 = 258/100 ps
8302 08:06:27.530838 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8303 08:06:27.537268 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8304 08:06:27.540610 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8305 08:06:27.544013 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8306 08:06:27.547378 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8307 08:06:27.550599 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 08:06:27.550698
8309 08:06:27.554244 CA PerBit enable=1, Macro0, CA PI delay=36
8310 08:06:27.554319
8311 08:06:27.557160 [CBTSetCACLKResult] CA Dly = 36
8312 08:06:27.560489 CS Dly: 9 (0~40)
8313 08:06:27.564007 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 08:06:27.567714 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 08:06:27.567789 ==
8316 08:06:27.570927 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 08:06:27.574096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 08:06:27.574192 ==
8319 08:06:27.580990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 08:06:27.583839 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 08:06:27.590458 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 08:06:27.594234 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 08:06:27.604308 [CA 0] Center 42 (13~71) winsize 59
8324 08:06:27.607496 [CA 1] Center 42 (12~72) winsize 61
8325 08:06:27.610643 [CA 2] Center 37 (8~67) winsize 60
8326 08:06:27.613932 [CA 3] Center 37 (8~66) winsize 59
8327 08:06:27.617444 [CA 4] Center 37 (8~67) winsize 60
8328 08:06:27.620502 [CA 5] Center 36 (6~67) winsize 62
8329 08:06:27.620574
8330 08:06:27.623734 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 08:06:27.623804
8332 08:06:27.627131 [CATrainingPosCal] consider 2 rank data
8333 08:06:27.630416 u2DelayCellTimex100 = 258/100 ps
8334 08:06:27.637064 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8335 08:06:27.640492 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8336 08:06:27.643786 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8337 08:06:27.646799 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8338 08:06:27.650085 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8339 08:06:27.653480 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 08:06:27.653557
8341 08:06:27.656690 CA PerBit enable=1, Macro0, CA PI delay=36
8342 08:06:27.656760
8343 08:06:27.660192 [CBTSetCACLKResult] CA Dly = 36
8344 08:06:27.663245 CS Dly: 10 (0~43)
8345 08:06:27.666764 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 08:06:27.670538 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 08:06:27.670634
8348 08:06:27.673667 ----->DramcWriteLeveling(PI) begin...
8349 08:06:27.673764 ==
8350 08:06:27.676681 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 08:06:27.683517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 08:06:27.683597 ==
8353 08:06:27.686532 Write leveling (Byte 0): 26 => 26
8354 08:06:27.690121 Write leveling (Byte 1): 28 => 28
8355 08:06:27.690191 DramcWriteLeveling(PI) end<-----
8356 08:06:27.690251
8357 08:06:27.693351 ==
8358 08:06:27.693449 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 08:06:27.700528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 08:06:27.700621 ==
8361 08:06:27.703390 [Gating] SW mode calibration
8362 08:06:27.710176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 08:06:27.713462 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 08:06:27.720357 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 08:06:27.723576 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 08:06:27.726311 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 08:06:27.732931 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8368 08:06:27.736624 1 4 16 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 0)
8369 08:06:27.740140 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 08:06:27.746384 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 08:06:27.749994 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 08:06:27.753408 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 08:06:27.759905 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 08:06:27.762996 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 08:06:27.766341 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8376 08:06:27.773235 1 5 16 | B1->B0 | 2626 2727 | 1 0 | (1 0) (1 0)
8377 08:06:27.776562 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 08:06:27.779572 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 08:06:27.786682 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 08:06:27.789349 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 08:06:27.793146 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 08:06:27.796277 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 08:06:27.803071 1 6 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8384 08:06:27.806436 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8385 08:06:27.809527 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 08:06:27.815948 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 08:06:27.819525 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 08:06:27.822643 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 08:06:27.829587 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 08:06:27.832732 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 08:06:27.836307 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 08:06:27.843294 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 08:06:27.846348 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 08:06:27.849899 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 08:06:27.856239 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 08:06:27.859582 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 08:06:27.862667 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 08:06:27.869193 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 08:06:27.872606 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 08:06:27.876019 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 08:06:27.882718 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 08:06:27.886284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 08:06:27.889303 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 08:06:27.895788 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 08:06:27.899917 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 08:06:27.902796 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 08:06:27.909719 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8408 08:06:27.912916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8409 08:06:27.915786 Total UI for P1: 0, mck2ui 16
8410 08:06:27.919996 best dqsien dly found for B1: ( 1, 9, 14)
8411 08:06:27.922539 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 08:06:27.925818 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 08:06:27.929114 Total UI for P1: 0, mck2ui 16
8414 08:06:27.932814 best dqsien dly found for B0: ( 1, 9, 16)
8415 08:06:27.936137 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8416 08:06:27.942799 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8417 08:06:27.942970
8418 08:06:27.945835 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8419 08:06:27.949575 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8420 08:06:27.952917 [Gating] SW calibration Done
8421 08:06:27.953130 ==
8422 08:06:27.955953 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 08:06:27.959275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 08:06:27.959536 ==
8425 08:06:27.963051 RX Vref Scan: 0
8426 08:06:27.963286
8427 08:06:27.963552 RX Vref 0 -> 0, step: 1
8428 08:06:27.963793
8429 08:06:27.966219 RX Delay 0 -> 252, step: 8
8430 08:06:27.969336 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8431 08:06:27.972524 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8432 08:06:27.979369 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8433 08:06:27.982804 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8434 08:06:27.986151 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8435 08:06:27.989337 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8436 08:06:27.992924 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8437 08:06:27.999255 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8438 08:06:28.002620 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8439 08:06:28.006002 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8440 08:06:28.009258 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8441 08:06:28.012750 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8442 08:06:28.019038 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8443 08:06:28.023036 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8444 08:06:28.025745 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8445 08:06:28.029085 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8446 08:06:28.029598 ==
8447 08:06:28.032447 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 08:06:28.039286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 08:06:28.039831 ==
8450 08:06:28.040229 DQS Delay:
8451 08:06:28.042178 DQS0 = 0, DQS1 = 0
8452 08:06:28.042661 DQM Delay:
8453 08:06:28.045880 DQM0 = 132, DQM1 = 126
8454 08:06:28.046465 DQ Delay:
8455 08:06:28.049471 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8456 08:06:28.052488 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8457 08:06:28.055983 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8458 08:06:28.058951 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8459 08:06:28.059579
8460 08:06:28.059986
8461 08:06:28.060362 ==
8462 08:06:28.062342 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 08:06:28.069239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 08:06:28.069818 ==
8465 08:06:28.070224
8466 08:06:28.070611
8467 08:06:28.070981 TX Vref Scan disable
8468 08:06:28.071998 == TX Byte 0 ==
8469 08:06:28.075630 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8470 08:06:28.082206 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 08:06:28.082685 == TX Byte 1 ==
8472 08:06:28.085486 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8473 08:06:28.092279 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 08:06:28.092769 ==
8475 08:06:28.095279 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 08:06:28.099002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 08:06:28.099522 ==
8478 08:06:28.112279
8479 08:06:28.115245 TX Vref early break, caculate TX vref
8480 08:06:28.118588 TX Vref=16, minBit 9, minWin=21, winSum=361
8481 08:06:28.121814 TX Vref=18, minBit 9, minWin=22, winSum=374
8482 08:06:28.125701 TX Vref=20, minBit 5, minWin=23, winSum=386
8483 08:06:28.128882 TX Vref=22, minBit 1, minWin=23, winSum=393
8484 08:06:28.132432 TX Vref=24, minBit 1, minWin=24, winSum=406
8485 08:06:28.139199 TX Vref=26, minBit 1, minWin=25, winSum=415
8486 08:06:28.142448 TX Vref=28, minBit 1, minWin=25, winSum=418
8487 08:06:28.145886 TX Vref=30, minBit 1, minWin=25, winSum=416
8488 08:06:28.148563 TX Vref=32, minBit 0, minWin=24, winSum=409
8489 08:06:28.151963 TX Vref=34, minBit 0, minWin=23, winSum=398
8490 08:06:28.155327 TX Vref=36, minBit 9, minWin=22, winSum=385
8491 08:06:28.162013 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8492 08:06:28.162486
8493 08:06:28.165360 Final TX Range 0 Vref 28
8494 08:06:28.165850
8495 08:06:28.166239 ==
8496 08:06:28.168642 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 08:06:28.171651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 08:06:28.172125 ==
8499 08:06:28.172507
8500 08:06:28.175119
8501 08:06:28.175714 TX Vref Scan disable
8502 08:06:28.181947 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8503 08:06:28.182620 == TX Byte 0 ==
8504 08:06:28.185291 u2DelayCellOfst[0]=18 cells (5 PI)
8505 08:06:28.188769 u2DelayCellOfst[1]=11 cells (3 PI)
8506 08:06:28.191747 u2DelayCellOfst[2]=0 cells (0 PI)
8507 08:06:28.195003 u2DelayCellOfst[3]=7 cells (2 PI)
8508 08:06:28.198223 u2DelayCellOfst[4]=7 cells (2 PI)
8509 08:06:28.201561 u2DelayCellOfst[5]=18 cells (5 PI)
8510 08:06:28.205059 u2DelayCellOfst[6]=22 cells (6 PI)
8511 08:06:28.208149 u2DelayCellOfst[7]=7 cells (2 PI)
8512 08:06:28.211817 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8513 08:06:28.214589 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8514 08:06:28.217990 == TX Byte 1 ==
8515 08:06:28.221603 u2DelayCellOfst[8]=0 cells (0 PI)
8516 08:06:28.222167 u2DelayCellOfst[9]=7 cells (2 PI)
8517 08:06:28.225094 u2DelayCellOfst[10]=15 cells (4 PI)
8518 08:06:28.227817 u2DelayCellOfst[11]=11 cells (3 PI)
8519 08:06:28.231462 u2DelayCellOfst[12]=18 cells (5 PI)
8520 08:06:28.234733 u2DelayCellOfst[13]=22 cells (6 PI)
8521 08:06:28.237724 u2DelayCellOfst[14]=22 cells (6 PI)
8522 08:06:28.241111 u2DelayCellOfst[15]=22 cells (6 PI)
8523 08:06:28.247905 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8524 08:06:28.251004 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8525 08:06:28.251516 DramC Write-DBI on
8526 08:06:28.251920 ==
8527 08:06:28.254279 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 08:06:28.261006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 08:06:28.261459 ==
8530 08:06:28.261812
8531 08:06:28.262134
8532 08:06:28.264317 TX Vref Scan disable
8533 08:06:28.264758 == TX Byte 0 ==
8534 08:06:28.270777 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8535 08:06:28.271237 == TX Byte 1 ==
8536 08:06:28.274288 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8537 08:06:28.277319 DramC Write-DBI off
8538 08:06:28.277758
8539 08:06:28.278233 [DATLAT]
8540 08:06:28.280716 Freq=1600, CH1 RK0
8541 08:06:28.281157
8542 08:06:28.281535 DATLAT Default: 0xf
8543 08:06:28.284130 0, 0xFFFF, sum = 0
8544 08:06:28.284588 1, 0xFFFF, sum = 0
8545 08:06:28.287615 2, 0xFFFF, sum = 0
8546 08:06:28.288066 3, 0xFFFF, sum = 0
8547 08:06:28.291024 4, 0xFFFF, sum = 0
8548 08:06:28.291531 5, 0xFFFF, sum = 0
8549 08:06:28.294412 6, 0xFFFF, sum = 0
8550 08:06:28.294857 7, 0xFFFF, sum = 0
8551 08:06:28.297296 8, 0xFFFF, sum = 0
8552 08:06:28.297739 9, 0xFFFF, sum = 0
8553 08:06:28.301006 10, 0xFFFF, sum = 0
8554 08:06:28.303932 11, 0xFFFF, sum = 0
8555 08:06:28.304378 12, 0xFFFF, sum = 0
8556 08:06:28.307234 13, 0x8FFF, sum = 0
8557 08:06:28.307755 14, 0x0, sum = 1
8558 08:06:28.311158 15, 0x0, sum = 2
8559 08:06:28.311647 16, 0x0, sum = 3
8560 08:06:28.312016 17, 0x0, sum = 4
8561 08:06:28.314397 best_step = 15
8562 08:06:28.314857
8563 08:06:28.315280 ==
8564 08:06:28.317646 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 08:06:28.320631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 08:06:28.321073 ==
8567 08:06:28.324419 RX Vref Scan: 1
8568 08:06:28.324865
8569 08:06:28.327255 Set Vref Range= 24 -> 127
8570 08:06:28.327757
8571 08:06:28.328125 RX Vref 24 -> 127, step: 1
8572 08:06:28.328476
8573 08:06:28.330654 RX Delay 11 -> 252, step: 4
8574 08:06:28.331100
8575 08:06:28.333958 Set Vref, RX VrefLevel [Byte0]: 24
8576 08:06:28.337383 [Byte1]: 24
8577 08:06:28.340797
8578 08:06:28.341236 Set Vref, RX VrefLevel [Byte0]: 25
8579 08:06:28.343567 [Byte1]: 25
8580 08:06:28.347884
8581 08:06:28.348322 Set Vref, RX VrefLevel [Byte0]: 26
8582 08:06:28.351085 [Byte1]: 26
8583 08:06:28.355510
8584 08:06:28.355944 Set Vref, RX VrefLevel [Byte0]: 27
8585 08:06:28.358885 [Byte1]: 27
8586 08:06:28.363185
8587 08:06:28.363689 Set Vref, RX VrefLevel [Byte0]: 28
8588 08:06:28.366394 [Byte1]: 28
8589 08:06:28.371143
8590 08:06:28.371603 Set Vref, RX VrefLevel [Byte0]: 29
8591 08:06:28.374152 [Byte1]: 29
8592 08:06:28.378671
8593 08:06:28.379107 Set Vref, RX VrefLevel [Byte0]: 30
8594 08:06:28.382087 [Byte1]: 30
8595 08:06:28.386045
8596 08:06:28.386491 Set Vref, RX VrefLevel [Byte0]: 31
8597 08:06:28.389114 [Byte1]: 31
8598 08:06:28.393858
8599 08:06:28.394295 Set Vref, RX VrefLevel [Byte0]: 32
8600 08:06:28.396981 [Byte1]: 32
8601 08:06:28.401080
8602 08:06:28.401544 Set Vref, RX VrefLevel [Byte0]: 33
8603 08:06:28.404542 [Byte1]: 33
8604 08:06:28.408899
8605 08:06:28.409344 Set Vref, RX VrefLevel [Byte0]: 34
8606 08:06:28.412175 [Byte1]: 34
8607 08:06:28.416659
8608 08:06:28.417226 Set Vref, RX VrefLevel [Byte0]: 35
8609 08:06:28.419648 [Byte1]: 35
8610 08:06:28.424520
8611 08:06:28.424958 Set Vref, RX VrefLevel [Byte0]: 36
8612 08:06:28.427176 [Byte1]: 36
8613 08:06:28.431536
8614 08:06:28.432001 Set Vref, RX VrefLevel [Byte0]: 37
8615 08:06:28.435542 [Byte1]: 37
8616 08:06:28.439234
8617 08:06:28.439740 Set Vref, RX VrefLevel [Byte0]: 38
8618 08:06:28.442560 [Byte1]: 38
8619 08:06:28.447092
8620 08:06:28.447591 Set Vref, RX VrefLevel [Byte0]: 39
8621 08:06:28.450262 [Byte1]: 39
8622 08:06:28.454722
8623 08:06:28.455182 Set Vref, RX VrefLevel [Byte0]: 40
8624 08:06:28.458186 [Byte1]: 40
8625 08:06:28.462087
8626 08:06:28.462543 Set Vref, RX VrefLevel [Byte0]: 41
8627 08:06:28.465800 [Byte1]: 41
8628 08:06:28.469808
8629 08:06:28.470409 Set Vref, RX VrefLevel [Byte0]: 42
8630 08:06:28.472939 [Byte1]: 42
8631 08:06:28.477091
8632 08:06:28.477784 Set Vref, RX VrefLevel [Byte0]: 43
8633 08:06:28.480655 [Byte1]: 43
8634 08:06:28.485241
8635 08:06:28.485548 Set Vref, RX VrefLevel [Byte0]: 44
8636 08:06:28.488154 [Byte1]: 44
8637 08:06:28.492478
8638 08:06:28.492714 Set Vref, RX VrefLevel [Byte0]: 45
8639 08:06:28.495548 [Byte1]: 45
8640 08:06:28.500095
8641 08:06:28.500254 Set Vref, RX VrefLevel [Byte0]: 46
8642 08:06:28.503820 [Byte1]: 46
8643 08:06:28.507747
8644 08:06:28.507960 Set Vref, RX VrefLevel [Byte0]: 47
8645 08:06:28.511174 [Byte1]: 47
8646 08:06:28.515183
8647 08:06:28.515295 Set Vref, RX VrefLevel [Byte0]: 48
8648 08:06:28.518341 [Byte1]: 48
8649 08:06:28.522984
8650 08:06:28.523070 Set Vref, RX VrefLevel [Byte0]: 49
8651 08:06:28.526319 [Byte1]: 49
8652 08:06:28.530246
8653 08:06:28.530327 Set Vref, RX VrefLevel [Byte0]: 50
8654 08:06:28.533465 [Byte1]: 50
8655 08:06:28.537875
8656 08:06:28.537984 Set Vref, RX VrefLevel [Byte0]: 51
8657 08:06:28.541688 [Byte1]: 51
8658 08:06:28.545722
8659 08:06:28.545811 Set Vref, RX VrefLevel [Byte0]: 52
8660 08:06:28.549050 [Byte1]: 52
8661 08:06:28.553680
8662 08:06:28.553799 Set Vref, RX VrefLevel [Byte0]: 53
8663 08:06:28.556407 [Byte1]: 53
8664 08:06:28.560685
8665 08:06:28.560787 Set Vref, RX VrefLevel [Byte0]: 54
8666 08:06:28.564202 [Byte1]: 54
8667 08:06:28.568430
8668 08:06:28.568541 Set Vref, RX VrefLevel [Byte0]: 55
8669 08:06:28.571775 [Byte1]: 55
8670 08:06:28.576591
8671 08:06:28.576745 Set Vref, RX VrefLevel [Byte0]: 56
8672 08:06:28.579913 [Byte1]: 56
8673 08:06:28.583906
8674 08:06:28.584124 Set Vref, RX VrefLevel [Byte0]: 57
8675 08:06:28.587065 [Byte1]: 57
8676 08:06:28.591581
8677 08:06:28.591898 Set Vref, RX VrefLevel [Byte0]: 58
8678 08:06:28.594420 [Byte1]: 58
8679 08:06:28.599361
8680 08:06:28.599807 Set Vref, RX VrefLevel [Byte0]: 59
8681 08:06:28.602426 [Byte1]: 59
8682 08:06:28.607019
8683 08:06:28.607493 Set Vref, RX VrefLevel [Byte0]: 60
8684 08:06:28.610326 [Byte1]: 60
8685 08:06:28.614699
8686 08:06:28.615131 Set Vref, RX VrefLevel [Byte0]: 61
8687 08:06:28.617765 [Byte1]: 61
8688 08:06:28.621618
8689 08:06:28.621699 Set Vref, RX VrefLevel [Byte0]: 62
8690 08:06:28.624982 [Byte1]: 62
8691 08:06:28.629302
8692 08:06:28.629380 Set Vref, RX VrefLevel [Byte0]: 63
8693 08:06:28.632426 [Byte1]: 63
8694 08:06:28.637107
8695 08:06:28.637185 Set Vref, RX VrefLevel [Byte0]: 64
8696 08:06:28.640547 [Byte1]: 64
8697 08:06:28.644369
8698 08:06:28.644441 Set Vref, RX VrefLevel [Byte0]: 65
8699 08:06:28.648151 [Byte1]: 65
8700 08:06:28.652462
8701 08:06:28.652533 Set Vref, RX VrefLevel [Byte0]: 66
8702 08:06:28.655930 [Byte1]: 66
8703 08:06:28.659922
8704 08:06:28.659994 Set Vref, RX VrefLevel [Byte0]: 67
8705 08:06:28.662805 [Byte1]: 67
8706 08:06:28.667064
8707 08:06:28.667135 Set Vref, RX VrefLevel [Byte0]: 68
8708 08:06:28.670421 [Byte1]: 68
8709 08:06:28.675160
8710 08:06:28.675230 Set Vref, RX VrefLevel [Byte0]: 69
8711 08:06:28.678621 [Byte1]: 69
8712 08:06:28.682707
8713 08:06:28.682778 Set Vref, RX VrefLevel [Byte0]: 70
8714 08:06:28.686038 [Byte1]: 70
8715 08:06:28.689955
8716 08:06:28.690025 Set Vref, RX VrefLevel [Byte0]: 71
8717 08:06:28.693304 [Byte1]: 71
8718 08:06:28.697917
8719 08:06:28.697992 Final RX Vref Byte 0 = 57 to rank0
8720 08:06:28.701104 Final RX Vref Byte 1 = 53 to rank0
8721 08:06:28.704555 Final RX Vref Byte 0 = 57 to rank1
8722 08:06:28.707752 Final RX Vref Byte 1 = 53 to rank1==
8723 08:06:28.711081 Dram Type= 6, Freq= 0, CH_1, rank 0
8724 08:06:28.717961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 08:06:28.718038 ==
8726 08:06:28.718102 DQS Delay:
8727 08:06:28.718168 DQS0 = 0, DQS1 = 0
8728 08:06:28.720810 DQM Delay:
8729 08:06:28.720879 DQM0 = 131, DQM1 = 123
8730 08:06:28.724224 DQ Delay:
8731 08:06:28.727588 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8732 08:06:28.731123 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8733 08:06:28.734249 DQ8 =108, DQ9 =114, DQ10 =124, DQ11 =116
8734 08:06:28.737575 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8735 08:06:28.737646
8736 08:06:28.737706
8737 08:06:28.737764
8738 08:06:28.741043 [DramC_TX_OE_Calibration] TA2
8739 08:06:28.744324 Original DQ_B0 (3 6) =30, OEN = 27
8740 08:06:28.747477 Original DQ_B1 (3 6) =30, OEN = 27
8741 08:06:28.750774 24, 0x0, End_B0=24 End_B1=24
8742 08:06:28.750850 25, 0x0, End_B0=25 End_B1=25
8743 08:06:28.754244 26, 0x0, End_B0=26 End_B1=26
8744 08:06:28.757317 27, 0x0, End_B0=27 End_B1=27
8745 08:06:28.760990 28, 0x0, End_B0=28 End_B1=28
8746 08:06:28.763990 29, 0x0, End_B0=29 End_B1=29
8747 08:06:28.764089 30, 0x0, End_B0=30 End_B1=30
8748 08:06:28.767880 31, 0x4141, End_B0=30 End_B1=30
8749 08:06:28.771128 Byte0 end_step=30 best_step=27
8750 08:06:28.774233 Byte1 end_step=30 best_step=27
8751 08:06:28.777553 Byte0 TX OE(2T, 0.5T) = (3, 3)
8752 08:06:28.780918 Byte1 TX OE(2T, 0.5T) = (3, 3)
8753 08:06:28.780989
8754 08:06:28.781055
8755 08:06:28.787195 [DQSOSCAuto] RK0, (LSB)MR18= 0xc11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
8756 08:06:28.790647 CH1 RK0: MR19=303, MR18=C11
8757 08:06:28.797137 CH1_RK0: MR19=0x303, MR18=0xC11, DQSOSC=401, MR23=63, INC=22, DEC=15
8758 08:06:28.797212
8759 08:06:28.800918 ----->DramcWriteLeveling(PI) begin...
8760 08:06:28.800990 ==
8761 08:06:28.804045 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 08:06:28.807043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 08:06:28.807115 ==
8764 08:06:28.810603 Write leveling (Byte 0): 24 => 24
8765 08:06:28.813978 Write leveling (Byte 1): 27 => 27
8766 08:06:28.817201 DramcWriteLeveling(PI) end<-----
8767 08:06:28.817275
8768 08:06:28.817337 ==
8769 08:06:28.820316 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 08:06:28.823780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 08:06:28.823852 ==
8772 08:06:28.827575 [Gating] SW mode calibration
8773 08:06:28.833697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8774 08:06:28.840394 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8775 08:06:28.843844 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 08:06:28.847153 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 08:06:28.853745 1 4 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8778 08:06:28.856831 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 08:06:28.860393 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 08:06:28.867090 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 08:06:28.870623 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 08:06:28.873752 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 08:06:28.880179 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 08:06:28.883651 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 08:06:28.887265 1 5 8 | B1->B0 | 3333 2626 | 1 1 | (1 0) (1 0)
8786 08:06:28.893967 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8787 08:06:28.897316 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 08:06:28.900861 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 08:06:28.907344 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 08:06:28.910399 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 08:06:28.913600 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 08:06:28.920347 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8793 08:06:28.923858 1 6 8 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
8794 08:06:28.927061 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 08:06:28.930387 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 08:06:28.937698 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 08:06:28.940750 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 08:06:28.943635 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 08:06:28.950455 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 08:06:28.953891 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 08:06:28.957410 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8802 08:06:28.964043 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8803 08:06:28.967301 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 08:06:28.970426 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 08:06:28.976930 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 08:06:28.980382 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 08:06:28.983746 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 08:06:28.990405 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 08:06:28.993944 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 08:06:28.996579 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 08:06:29.003505 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 08:06:29.007074 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 08:06:29.010194 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 08:06:29.017013 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 08:06:29.020130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 08:06:29.023320 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8817 08:06:29.029897 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8818 08:06:29.033197 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8819 08:06:29.037024 Total UI for P1: 0, mck2ui 16
8820 08:06:29.040051 best dqsien dly found for B0: ( 1, 9, 6)
8821 08:06:29.043078 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 08:06:29.046831 Total UI for P1: 0, mck2ui 16
8823 08:06:29.049952 best dqsien dly found for B1: ( 1, 9, 10)
8824 08:06:29.053097 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8825 08:06:29.056272 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8826 08:06:29.056693
8827 08:06:29.063407 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8828 08:06:29.066088 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8829 08:06:29.069689 [Gating] SW calibration Done
8830 08:06:29.070106 ==
8831 08:06:29.072890 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 08:06:29.076220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 08:06:29.076691 ==
8834 08:06:29.077060 RX Vref Scan: 0
8835 08:06:29.077400
8836 08:06:29.079907 RX Vref 0 -> 0, step: 1
8837 08:06:29.080373
8838 08:06:29.082701 RX Delay 0 -> 252, step: 8
8839 08:06:29.086302 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8840 08:06:29.089699 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8841 08:06:29.092784 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8842 08:06:29.099588 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8843 08:06:29.103109 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8844 08:06:29.106458 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8845 08:06:29.109563 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8846 08:06:29.112979 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8847 08:06:29.119685 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8848 08:06:29.123353 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8849 08:06:29.126109 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8850 08:06:29.129661 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8851 08:06:29.136024 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8852 08:06:29.139453 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8853 08:06:29.142854 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8854 08:06:29.145950 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8855 08:06:29.146554 ==
8856 08:06:29.149361 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 08:06:29.152524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 08:06:29.155721 ==
8859 08:06:29.156163 DQS Delay:
8860 08:06:29.156546 DQS0 = 0, DQS1 = 0
8861 08:06:29.159315 DQM Delay:
8862 08:06:29.159832 DQM0 = 129, DQM1 = 127
8863 08:06:29.162894 DQ Delay:
8864 08:06:29.165760 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8865 08:06:29.169583 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8866 08:06:29.173197 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8867 08:06:29.176225 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8868 08:06:29.176708
8869 08:06:29.177076
8870 08:06:29.177430 ==
8871 08:06:29.179905 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 08:06:29.182465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 08:06:29.182963 ==
8874 08:06:29.186415
8875 08:06:29.186999
8876 08:06:29.187547 TX Vref Scan disable
8877 08:06:29.189421 == TX Byte 0 ==
8878 08:06:29.192613 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8879 08:06:29.196107 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8880 08:06:29.198972 == TX Byte 1 ==
8881 08:06:29.202520 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8882 08:06:29.206274 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8883 08:06:29.206850 ==
8884 08:06:29.209387 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 08:06:29.215456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 08:06:29.215962 ==
8887 08:06:29.228906
8888 08:06:29.232141 TX Vref early break, caculate TX vref
8889 08:06:29.234836 TX Vref=16, minBit 0, minWin=23, winSum=383
8890 08:06:29.238321 TX Vref=18, minBit 0, minWin=23, winSum=392
8891 08:06:29.242046 TX Vref=20, minBit 0, minWin=24, winSum=406
8892 08:06:29.245164 TX Vref=22, minBit 0, minWin=25, winSum=412
8893 08:06:29.248199 TX Vref=24, minBit 0, minWin=25, winSum=419
8894 08:06:29.255216 TX Vref=26, minBit 0, minWin=25, winSum=428
8895 08:06:29.258328 TX Vref=28, minBit 1, minWin=26, winSum=429
8896 08:06:29.261790 TX Vref=30, minBit 5, minWin=25, winSum=422
8897 08:06:29.264742 TX Vref=32, minBit 1, minWin=24, winSum=411
8898 08:06:29.268133 TX Vref=34, minBit 1, minWin=23, winSum=407
8899 08:06:29.271692 TX Vref=36, minBit 1, minWin=23, winSum=396
8900 08:06:29.278878 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
8901 08:06:29.279351
8902 08:06:29.281533 Final TX Range 0 Vref 28
8903 08:06:29.282002
8904 08:06:29.282371 ==
8905 08:06:29.285060 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 08:06:29.288273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 08:06:29.288746 ==
8908 08:06:29.289119
8909 08:06:29.289460
8910 08:06:29.291377 TX Vref Scan disable
8911 08:06:29.298325 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8912 08:06:29.298791 == TX Byte 0 ==
8913 08:06:29.301683 u2DelayCellOfst[0]=18 cells (5 PI)
8914 08:06:29.304786 u2DelayCellOfst[1]=11 cells (3 PI)
8915 08:06:29.308058 u2DelayCellOfst[2]=0 cells (0 PI)
8916 08:06:29.311456 u2DelayCellOfst[3]=3 cells (1 PI)
8917 08:06:29.314703 u2DelayCellOfst[4]=7 cells (2 PI)
8918 08:06:29.318089 u2DelayCellOfst[5]=18 cells (5 PI)
8919 08:06:29.321474 u2DelayCellOfst[6]=18 cells (5 PI)
8920 08:06:29.324531 u2DelayCellOfst[7]=3 cells (1 PI)
8921 08:06:29.328472 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8922 08:06:29.330994 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8923 08:06:29.334903 == TX Byte 1 ==
8924 08:06:29.338045 u2DelayCellOfst[8]=0 cells (0 PI)
8925 08:06:29.338547 u2DelayCellOfst[9]=7 cells (2 PI)
8926 08:06:29.341107 u2DelayCellOfst[10]=15 cells (4 PI)
8927 08:06:29.344391 u2DelayCellOfst[11]=7 cells (2 PI)
8928 08:06:29.348080 u2DelayCellOfst[12]=18 cells (5 PI)
8929 08:06:29.351029 u2DelayCellOfst[13]=18 cells (5 PI)
8930 08:06:29.354507 u2DelayCellOfst[14]=22 cells (6 PI)
8931 08:06:29.357787 u2DelayCellOfst[15]=18 cells (5 PI)
8932 08:06:29.364894 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8933 08:06:29.367684 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8934 08:06:29.368147 DramC Write-DBI on
8935 08:06:29.368524 ==
8936 08:06:29.370894 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 08:06:29.377374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 08:06:29.377796 ==
8939 08:06:29.378131
8940 08:06:29.378439
8941 08:06:29.378735 TX Vref Scan disable
8942 08:06:29.381940 == TX Byte 0 ==
8943 08:06:29.384712 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8944 08:06:29.388671 == TX Byte 1 ==
8945 08:06:29.391415 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8946 08:06:29.394869 DramC Write-DBI off
8947 08:06:29.395288
8948 08:06:29.395660 [DATLAT]
8949 08:06:29.395971 Freq=1600, CH1 RK1
8950 08:06:29.396271
8951 08:06:29.398098 DATLAT Default: 0xf
8952 08:06:29.401493 0, 0xFFFF, sum = 0
8953 08:06:29.401919 1, 0xFFFF, sum = 0
8954 08:06:29.404749 2, 0xFFFF, sum = 0
8955 08:06:29.405175 3, 0xFFFF, sum = 0
8956 08:06:29.408283 4, 0xFFFF, sum = 0
8957 08:06:29.408707 5, 0xFFFF, sum = 0
8958 08:06:29.411211 6, 0xFFFF, sum = 0
8959 08:06:29.411678 7, 0xFFFF, sum = 0
8960 08:06:29.414687 8, 0xFFFF, sum = 0
8961 08:06:29.415122 9, 0xFFFF, sum = 0
8962 08:06:29.417835 10, 0xFFFF, sum = 0
8963 08:06:29.418265 11, 0xFFFF, sum = 0
8964 08:06:29.421457 12, 0xFFFF, sum = 0
8965 08:06:29.421885 13, 0x8FFF, sum = 0
8966 08:06:29.424648 14, 0x0, sum = 1
8967 08:06:29.425081 15, 0x0, sum = 2
8968 08:06:29.428017 16, 0x0, sum = 3
8969 08:06:29.428443 17, 0x0, sum = 4
8970 08:06:29.431465 best_step = 15
8971 08:06:29.431884
8972 08:06:29.432219 ==
8973 08:06:29.434675 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 08:06:29.437785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 08:06:29.438204 ==
8976 08:06:29.441260 RX Vref Scan: 0
8977 08:06:29.441678
8978 08:06:29.442009 RX Vref 0 -> 0, step: 1
8979 08:06:29.442320
8980 08:06:29.445111 RX Delay 3 -> 252, step: 4
8981 08:06:29.448081 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8982 08:06:29.454800 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8983 08:06:29.457642 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8984 08:06:29.461032 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8985 08:06:29.464336 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8986 08:06:29.467855 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8987 08:06:29.474411 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8988 08:06:29.477933 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8989 08:06:29.481060 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8990 08:06:29.484339 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8991 08:06:29.487619 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8992 08:06:29.494209 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8993 08:06:29.497448 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8994 08:06:29.500942 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8995 08:06:29.504270 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8996 08:06:29.511216 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8997 08:06:29.511737 ==
8998 08:06:29.514534 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 08:06:29.517553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 08:06:29.518023 ==
9001 08:06:29.518391 DQS Delay:
9002 08:06:29.520926 DQS0 = 0, DQS1 = 0
9003 08:06:29.521392 DQM Delay:
9004 08:06:29.524762 DQM0 = 127, DQM1 = 125
9005 08:06:29.525181 DQ Delay:
9006 08:06:29.527678 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9007 08:06:29.530901 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9008 08:06:29.534123 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9009 08:06:29.537652 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9010 08:06:29.538071
9011 08:06:29.538405
9012 08:06:29.538771
9013 08:06:29.540735 [DramC_TX_OE_Calibration] TA2
9014 08:06:29.544098 Original DQ_B0 (3 6) =30, OEN = 27
9015 08:06:29.547205 Original DQ_B1 (3 6) =30, OEN = 27
9016 08:06:29.550663 24, 0x0, End_B0=24 End_B1=24
9017 08:06:29.554059 25, 0x0, End_B0=25 End_B1=25
9018 08:06:29.557726 26, 0x0, End_B0=26 End_B1=26
9019 08:06:29.558158 27, 0x0, End_B0=27 End_B1=27
9020 08:06:29.560577 28, 0x0, End_B0=28 End_B1=28
9021 08:06:29.563989 29, 0x0, End_B0=29 End_B1=29
9022 08:06:29.567653 30, 0x0, End_B0=30 End_B1=30
9023 08:06:29.568131 31, 0x4141, End_B0=30 End_B1=30
9024 08:06:29.570655 Byte0 end_step=30 best_step=27
9025 08:06:29.573721 Byte1 end_step=30 best_step=27
9026 08:06:29.577115 Byte0 TX OE(2T, 0.5T) = (3, 3)
9027 08:06:29.580468 Byte1 TX OE(2T, 0.5T) = (3, 3)
9028 08:06:29.580936
9029 08:06:29.581307
9030 08:06:29.587208 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9031 08:06:29.590647 CH1 RK1: MR19=303, MR18=E1B
9032 08:06:29.597136 CH1_RK1: MR19=0x303, MR18=0xE1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9033 08:06:29.600069 [RxdqsGatingPostProcess] freq 1600
9034 08:06:29.606726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9035 08:06:29.607193 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 08:06:29.610794 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 08:06:29.613626 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 08:06:29.616948 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 08:06:29.620455 best DQS0 dly(2T, 0.5T) = (1, 1)
9040 08:06:29.623735 best DQS1 dly(2T, 0.5T) = (1, 1)
9041 08:06:29.627249 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9042 08:06:29.630032 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9043 08:06:29.633695 Pre-setting of DQS Precalculation
9044 08:06:29.636869 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9045 08:06:29.647044 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9046 08:06:29.653230 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9047 08:06:29.653765
9048 08:06:29.654135
9049 08:06:29.656807 [Calibration Summary] 3200 Mbps
9050 08:06:29.657349 CH 0, Rank 0
9051 08:06:29.659905 SW Impedance : PASS
9052 08:06:29.660417 DUTY Scan : NO K
9053 08:06:29.663434 ZQ Calibration : PASS
9054 08:06:29.666641 Jitter Meter : NO K
9055 08:06:29.667133 CBT Training : PASS
9056 08:06:29.669668 Write leveling : PASS
9057 08:06:29.673460 RX DQS gating : PASS
9058 08:06:29.674060 RX DQ/DQS(RDDQC) : PASS
9059 08:06:29.676746 TX DQ/DQS : PASS
9060 08:06:29.679519 RX DATLAT : PASS
9061 08:06:29.680020 RX DQ/DQS(Engine): PASS
9062 08:06:29.682779 TX OE : PASS
9063 08:06:29.683286 All Pass.
9064 08:06:29.683814
9065 08:06:29.686311 CH 0, Rank 1
9066 08:06:29.686793 SW Impedance : PASS
9067 08:06:29.690058 DUTY Scan : NO K
9068 08:06:29.693052 ZQ Calibration : PASS
9069 08:06:29.693535 Jitter Meter : NO K
9070 08:06:29.696255 CBT Training : PASS
9071 08:06:29.699962 Write leveling : PASS
9072 08:06:29.700588 RX DQS gating : PASS
9073 08:06:29.703043 RX DQ/DQS(RDDQC) : PASS
9074 08:06:29.703572 TX DQ/DQS : PASS
9075 08:06:29.706393 RX DATLAT : PASS
9076 08:06:29.709647 RX DQ/DQS(Engine): PASS
9077 08:06:29.710132 TX OE : PASS
9078 08:06:29.713079 All Pass.
9079 08:06:29.713582
9080 08:06:29.714099 CH 1, Rank 0
9081 08:06:29.716230 SW Impedance : PASS
9082 08:06:29.716742 DUTY Scan : NO K
9083 08:06:29.719902 ZQ Calibration : PASS
9084 08:06:29.723320 Jitter Meter : NO K
9085 08:06:29.723928 CBT Training : PASS
9086 08:06:29.726326 Write leveling : PASS
9087 08:06:29.729848 RX DQS gating : PASS
9088 08:06:29.730552 RX DQ/DQS(RDDQC) : PASS
9089 08:06:29.733311 TX DQ/DQS : PASS
9090 08:06:29.736468 RX DATLAT : PASS
9091 08:06:29.736951 RX DQ/DQS(Engine): PASS
9092 08:06:29.739826 TX OE : PASS
9093 08:06:29.740360 All Pass.
9094 08:06:29.740842
9095 08:06:29.743498 CH 1, Rank 1
9096 08:06:29.744084 SW Impedance : PASS
9097 08:06:29.747072 DUTY Scan : NO K
9098 08:06:29.749955 ZQ Calibration : PASS
9099 08:06:29.750442 Jitter Meter : NO K
9100 08:06:29.753094 CBT Training : PASS
9101 08:06:29.753575 Write leveling : PASS
9102 08:06:29.756428 RX DQS gating : PASS
9103 08:06:29.759496 RX DQ/DQS(RDDQC) : PASS
9104 08:06:29.760020 TX DQ/DQS : PASS
9105 08:06:29.762961 RX DATLAT : PASS
9106 08:06:29.766585 RX DQ/DQS(Engine): PASS
9107 08:06:29.767030 TX OE : PASS
9108 08:06:29.769784 All Pass.
9109 08:06:29.770207
9110 08:06:29.770540 DramC Write-DBI on
9111 08:06:29.772753 PER_BANK_REFRESH: Hybrid Mode
9112 08:06:29.773238 TX_TRACKING: ON
9113 08:06:29.782978 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9114 08:06:29.792651 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9115 08:06:29.799236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9116 08:06:29.803216 [FAST_K] Save calibration result to emmc
9117 08:06:29.805931 sync common calibartion params.
9118 08:06:29.806418 sync cbt_mode0:1, 1:1
9119 08:06:29.809359 dram_init: ddr_geometry: 2
9120 08:06:29.812883 dram_init: ddr_geometry: 2
9121 08:06:29.813431 dram_init: ddr_geometry: 2
9122 08:06:29.815891 0:dram_rank_size:100000000
9123 08:06:29.818980 1:dram_rank_size:100000000
9124 08:06:29.825960 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9125 08:06:29.826474 DFS_SHUFFLE_HW_MODE: ON
9126 08:06:29.829060 dramc_set_vcore_voltage set vcore to 725000
9127 08:06:29.832763 Read voltage for 1600, 0
9128 08:06:29.833290 Vio18 = 0
9129 08:06:29.835722 Vcore = 725000
9130 08:06:29.836141 Vdram = 0
9131 08:06:29.836473 Vddq = 0
9132 08:06:29.838893 Vmddr = 0
9133 08:06:29.839481 switch to 3200 Mbps bootup
9134 08:06:29.842312 [DramcRunTimeConfig]
9135 08:06:29.842728 PHYPLL
9136 08:06:29.845575 DPM_CONTROL_AFTERK: ON
9137 08:06:29.845996 PER_BANK_REFRESH: ON
9138 08:06:29.849132 REFRESH_OVERHEAD_REDUCTION: ON
9139 08:06:29.852418 CMD_PICG_NEW_MODE: OFF
9140 08:06:29.852904 XRTWTW_NEW_MODE: ON
9141 08:06:29.855717 XRTRTR_NEW_MODE: ON
9142 08:06:29.856135 TX_TRACKING: ON
9143 08:06:29.859155 RDSEL_TRACKING: OFF
9144 08:06:29.862716 DQS Precalculation for DVFS: ON
9145 08:06:29.863136 RX_TRACKING: OFF
9146 08:06:29.865681 HW_GATING DBG: ON
9147 08:06:29.866097 ZQCS_ENABLE_LP4: ON
9148 08:06:29.869238 RX_PICG_NEW_MODE: ON
9149 08:06:29.869655 TX_PICG_NEW_MODE: ON
9150 08:06:29.872485 ENABLE_RX_DCM_DPHY: ON
9151 08:06:29.875999 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9152 08:06:29.879292 DUMMY_READ_FOR_TRACKING: OFF
9153 08:06:29.879746 !!! SPM_CONTROL_AFTERK: OFF
9154 08:06:29.882676 !!! SPM could not control APHY
9155 08:06:29.885736 IMPEDANCE_TRACKING: ON
9156 08:06:29.886204 TEMP_SENSOR: ON
9157 08:06:29.889039 HW_SAVE_FOR_SR: OFF
9158 08:06:29.892502 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9159 08:06:29.895775 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9160 08:06:29.899350 Read ODT Tracking: ON
9161 08:06:29.899835 Refresh Rate DeBounce: ON
9162 08:06:29.902085 DFS_NO_QUEUE_FLUSH: ON
9163 08:06:29.905955 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9164 08:06:29.908724 ENABLE_DFS_RUNTIME_MRW: OFF
9165 08:06:29.909299 DDR_RESERVE_NEW_MODE: ON
9166 08:06:29.911969 MR_CBT_SWITCH_FREQ: ON
9167 08:06:29.915366 =========================
9168 08:06:29.933203 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9169 08:06:29.936367 dram_init: ddr_geometry: 2
9170 08:06:29.954114 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9171 08:06:29.957836 dram_init: dram init end (result: 0)
9172 08:06:29.964716 DRAM-K: Full calibration passed in 24582 msecs
9173 08:06:29.967589 MRC: failed to locate region type 0.
9174 08:06:29.968095 DRAM rank0 size:0x100000000,
9175 08:06:29.971457 DRAM rank1 size=0x100000000
9176 08:06:29.981097 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9177 08:06:29.987465 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9178 08:06:29.994023 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9179 08:06:30.000308 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9180 08:06:30.004109 DRAM rank0 size:0x100000000,
9181 08:06:30.007550 DRAM rank1 size=0x100000000
9182 08:06:30.007988 CBMEM:
9183 08:06:30.010901 IMD: root @ 0xfffff000 254 entries.
9184 08:06:30.013649 IMD: root @ 0xffffec00 62 entries.
9185 08:06:30.016976 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9186 08:06:30.020418 WARNING: RO_VPD is uninitialized or empty.
9187 08:06:30.026510 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9188 08:06:30.033991 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9189 08:06:30.047002 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9190 08:06:30.058368 BS: romstage times (exec / console): total (unknown) / 24043 ms
9191 08:06:30.058446
9192 08:06:30.058517
9193 08:06:30.068240 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9194 08:06:30.071197 ARM64: Exception handlers installed.
9195 08:06:30.074575 ARM64: Testing exception
9196 08:06:30.078504 ARM64: Done test exception
9197 08:06:30.078586 Enumerating buses...
9198 08:06:30.081800 Show all devs... Before device enumeration.
9199 08:06:30.084680 Root Device: enabled 1
9200 08:06:30.087783 CPU_CLUSTER: 0: enabled 1
9201 08:06:30.087864 CPU: 00: enabled 1
9202 08:06:30.091567 Compare with tree...
9203 08:06:30.091648 Root Device: enabled 1
9204 08:06:30.094923 CPU_CLUSTER: 0: enabled 1
9205 08:06:30.098323 CPU: 00: enabled 1
9206 08:06:30.098404 Root Device scanning...
9207 08:06:30.101166 scan_static_bus for Root Device
9208 08:06:30.104766 CPU_CLUSTER: 0 enabled
9209 08:06:30.107694 scan_static_bus for Root Device done
9210 08:06:30.111465 scan_bus: bus Root Device finished in 8 msecs
9211 08:06:30.111547 done
9212 08:06:30.118007 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9213 08:06:30.121403 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9214 08:06:30.127568 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9215 08:06:30.131351 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9216 08:06:30.134541 Allocating resources...
9217 08:06:30.137825 Reading resources...
9218 08:06:30.141565 Root Device read_resources bus 0 link: 0
9219 08:06:30.141657 DRAM rank0 size:0x100000000,
9220 08:06:30.144299 DRAM rank1 size=0x100000000
9221 08:06:30.148213 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9222 08:06:30.151011 CPU: 00 missing read_resources
9223 08:06:30.157908 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9224 08:06:30.161059 Root Device read_resources bus 0 link: 0 done
9225 08:06:30.161201 Done reading resources.
9226 08:06:30.167904 Show resources in subtree (Root Device)...After reading.
9227 08:06:30.171448 Root Device child on link 0 CPU_CLUSTER: 0
9228 08:06:30.174291 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 08:06:30.184685 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 08:06:30.185115 CPU: 00
9231 08:06:30.187608 Root Device assign_resources, bus 0 link: 0
9232 08:06:30.191587 CPU_CLUSTER: 0 missing set_resources
9233 08:06:30.197831 Root Device assign_resources, bus 0 link: 0 done
9234 08:06:30.198504 Done setting resources.
9235 08:06:30.204713 Show resources in subtree (Root Device)...After assigning values.
9236 08:06:30.208021 Root Device child on link 0 CPU_CLUSTER: 0
9237 08:06:30.210763 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 08:06:30.221051 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 08:06:30.221547 CPU: 00
9240 08:06:30.224044 Done allocating resources.
9241 08:06:30.231006 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9242 08:06:30.231576 Enabling resources...
9243 08:06:30.232030 done.
9244 08:06:30.237551 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9245 08:06:30.238164 Initializing devices...
9246 08:06:30.240848 Root Device init
9247 08:06:30.241340 init hardware done!
9248 08:06:30.243918 0x00000018: ctrlr->caps
9249 08:06:30.247500 52.000 MHz: ctrlr->f_max
9250 08:06:30.247949 0.400 MHz: ctrlr->f_min
9251 08:06:30.251074 0x40ff8080: ctrlr->voltages
9252 08:06:30.251560 sclk: 390625
9253 08:06:30.254459 Bus Width = 1
9254 08:06:30.255000 sclk: 390625
9255 08:06:30.257718 Bus Width = 1
9256 08:06:30.258198 Early init status = 3
9257 08:06:30.264140 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9258 08:06:30.267344 in-header: 03 fc 00 00 01 00 00 00
9259 08:06:30.267900 in-data: 00
9260 08:06:30.274160 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9261 08:06:30.277679 in-header: 03 fd 00 00 00 00 00 00
9262 08:06:30.280842 in-data:
9263 08:06:30.284513 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9264 08:06:30.287227 in-header: 03 fc 00 00 01 00 00 00
9265 08:06:30.291108 in-data: 00
9266 08:06:30.293775 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9267 08:06:30.298523 in-header: 03 fd 00 00 00 00 00 00
9268 08:06:30.301969 in-data:
9269 08:06:30.305200 [SSUSB] Setting up USB HOST controller...
9270 08:06:30.308787 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9271 08:06:30.311618 [SSUSB] phy power-on done.
9272 08:06:30.315027 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9273 08:06:30.322001 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9274 08:06:30.324911 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9275 08:06:30.331442 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9276 08:06:30.338331 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9277 08:06:30.344597 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9278 08:06:30.351690 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9279 08:06:30.358214 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9280 08:06:30.361310 SPM: binary array size = 0x9dc
9281 08:06:30.364386 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9282 08:06:30.371307 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9283 08:06:30.377943 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9284 08:06:30.385142 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9285 08:06:30.387838 configure_display: Starting display init
9286 08:06:30.422151 anx7625_power_on_init: Init interface.
9287 08:06:30.425197 anx7625_disable_pd_protocol: Disabled PD feature.
9288 08:06:30.428796 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9289 08:06:30.456739 anx7625_start_dp_work: Secure OCM version=00
9290 08:06:30.459941 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9291 08:06:30.474615 sp_tx_get_edid_block: EDID Block = 1
9292 08:06:30.577307 Extracted contents:
9293 08:06:30.580265 header: 00 ff ff ff ff ff ff 00
9294 08:06:30.583842 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9295 08:06:30.586614 version: 01 04
9296 08:06:30.589910 basic params: 95 1f 11 78 0a
9297 08:06:30.593359 chroma info: 76 90 94 55 54 90 27 21 50 54
9298 08:06:30.596807 established: 00 00 00
9299 08:06:30.603354 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9300 08:06:30.606592 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9301 08:06:30.613089 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9302 08:06:30.619897 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9303 08:06:30.626608 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9304 08:06:30.629914 extensions: 00
9305 08:06:30.630239 checksum: fb
9306 08:06:30.630526
9307 08:06:30.633511 Manufacturer: IVO Model 57d Serial Number 0
9308 08:06:30.636040 Made week 0 of 2020
9309 08:06:30.636379 EDID version: 1.4
9310 08:06:30.639604 Digital display
9311 08:06:30.643007 6 bits per primary color channel
9312 08:06:30.643469 DisplayPort interface
9313 08:06:30.646441 Maximum image size: 31 cm x 17 cm
9314 08:06:30.649761 Gamma: 220%
9315 08:06:30.650087 Check DPMS levels
9316 08:06:30.652872 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9317 08:06:30.656184 First detailed timing is preferred timing
9318 08:06:30.659451 Established timings supported:
9319 08:06:30.663024 Standard timings supported:
9320 08:06:30.663602 Detailed timings
9321 08:06:30.669655 Hex of detail: 383680a07038204018303c0035ae10000019
9322 08:06:30.673033 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9323 08:06:30.679747 0780 0798 07c8 0820 hborder 0
9324 08:06:30.682762 0438 043b 0447 0458 vborder 0
9325 08:06:30.686601 -hsync -vsync
9326 08:06:30.686919 Did detailed timing
9327 08:06:30.689484 Hex of detail: 000000000000000000000000000000000000
9328 08:06:30.692804 Manufacturer-specified data, tag 0
9329 08:06:30.699488 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9330 08:06:30.699855 ASCII string: InfoVision
9331 08:06:30.705962 Hex of detail: 000000fe00523134304e574635205248200a
9332 08:06:30.709465 ASCII string: R140NWF5 RH
9333 08:06:30.709846 Checksum
9334 08:06:30.712872 Checksum: 0xfb (valid)
9335 08:06:30.716242 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9336 08:06:30.719190 DSI data_rate: 832800000 bps
9337 08:06:30.726044 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9338 08:06:30.729382 anx7625_parse_edid: pixelclock(138800).
9339 08:06:30.732459 hactive(1920), hsync(48), hfp(24), hbp(88)
9340 08:06:30.735963 vactive(1080), vsync(12), vfp(3), vbp(17)
9341 08:06:30.739056 anx7625_dsi_config: config dsi.
9342 08:06:30.745821 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9343 08:06:30.758915 anx7625_dsi_config: success to config DSI
9344 08:06:30.762231 anx7625_dp_start: MIPI phy setup OK.
9345 08:06:30.765829 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9346 08:06:30.768652 mtk_ddp_mode_set invalid vrefresh 60
9347 08:06:30.771888 main_disp_path_setup
9348 08:06:30.772282 ovl_layer_smi_id_en
9349 08:06:30.775173 ovl_layer_smi_id_en
9350 08:06:30.775530 ccorr_config
9351 08:06:30.775795 aal_config
9352 08:06:30.778859 gamma_config
9353 08:06:30.779182 postmask_config
9354 08:06:30.782204 dither_config
9355 08:06:30.785344 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9356 08:06:30.791660 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9357 08:06:30.794909 Root Device init finished in 551 msecs
9358 08:06:30.798351 CPU_CLUSTER: 0 init
9359 08:06:30.805812 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9360 08:06:30.808565 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9361 08:06:30.811718 APU_MBOX 0x190000b0 = 0x10001
9362 08:06:30.814978 APU_MBOX 0x190001b0 = 0x10001
9363 08:06:30.818580 APU_MBOX 0x190005b0 = 0x10001
9364 08:06:30.821473 APU_MBOX 0x190006b0 = 0x10001
9365 08:06:30.828480 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9366 08:06:30.838142 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9367 08:06:30.850114 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9368 08:06:30.857331 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9369 08:06:30.869199 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9370 08:06:30.878122 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9371 08:06:30.880717 CPU_CLUSTER: 0 init finished in 81 msecs
9372 08:06:30.883957 Devices initialized
9373 08:06:30.887349 Show all devs... After init.
9374 08:06:30.887989 Root Device: enabled 1
9375 08:06:30.891078 CPU_CLUSTER: 0: enabled 1
9376 08:06:30.894119 CPU: 00: enabled 1
9377 08:06:30.897324 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9378 08:06:30.900874 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9379 08:06:30.904068 ELOG: NV offset 0x57f000 size 0x1000
9380 08:06:30.910503 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9381 08:06:30.917264 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9382 08:06:30.920995 ELOG: Event(17) added with size 13 at 2023-09-21 08:06:31 UTC
9383 08:06:30.924392 out: cmd=0x121: 03 db 21 01 00 00 00 00
9384 08:06:30.928663 in-header: 03 56 00 00 2c 00 00 00
9385 08:06:30.942137 in-data: 08 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9386 08:06:30.948450 ELOG: Event(A1) added with size 10 at 2023-09-21 08:06:31 UTC
9387 08:06:30.955344 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9388 08:06:30.962345 ELOG: Event(A0) added with size 9 at 2023-09-21 08:06:31 UTC
9389 08:06:30.965526 elog_add_boot_reason: Logged dev mode boot
9390 08:06:30.968819 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9391 08:06:30.972131 Finalize devices...
9392 08:06:30.972612 Devices finalized
9393 08:06:30.978389 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9394 08:06:30.982081 Writing coreboot table at 0xffe64000
9395 08:06:30.985571 0. 000000000010a000-0000000000113fff: RAMSTAGE
9396 08:06:30.988432 1. 0000000040000000-00000000400fffff: RAM
9397 08:06:30.995086 2. 0000000040100000-000000004032afff: RAMSTAGE
9398 08:06:30.998199 3. 000000004032b000-00000000545fffff: RAM
9399 08:06:31.001953 4. 0000000054600000-000000005465ffff: BL31
9400 08:06:31.005267 5. 0000000054660000-00000000ffe63fff: RAM
9401 08:06:31.011682 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9402 08:06:31.014902 7. 0000000100000000-000000023fffffff: RAM
9403 08:06:31.015568 Passing 5 GPIOs to payload:
9404 08:06:31.021642 NAME | PORT | POLARITY | VALUE
9405 08:06:31.024779 EC in RW | 0x000000aa | low | undefined
9406 08:06:31.031631 EC interrupt | 0x00000005 | low | undefined
9407 08:06:31.035104 TPM interrupt | 0x000000ab | high | undefined
9408 08:06:31.038546 SD card detect | 0x00000011 | high | undefined
9409 08:06:31.044689 speaker enable | 0x00000093 | high | undefined
9410 08:06:31.048165 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9411 08:06:31.051509 in-header: 03 f9 00 00 02 00 00 00
9412 08:06:31.052003 in-data: 02 00
9413 08:06:31.054556 ADC[4]: Raw value=897040 ID=7
9414 08:06:31.058227 ADC[3]: Raw value=213440 ID=1
9415 08:06:31.058649 RAM Code: 0x71
9416 08:06:31.061549 ADC[6]: Raw value=74722 ID=0
9417 08:06:31.064975 ADC[5]: Raw value=212700 ID=1
9418 08:06:31.065549 SKU Code: 0x1
9419 08:06:31.071520 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9420 08:06:31.074477 coreboot table: 964 bytes.
9421 08:06:31.078126 IMD ROOT 0. 0xfffff000 0x00001000
9422 08:06:31.081152 IMD SMALL 1. 0xffffe000 0x00001000
9423 08:06:31.084465 RO MCACHE 2. 0xffffc000 0x00001104
9424 08:06:31.088365 CONSOLE 3. 0xfff7c000 0x00080000
9425 08:06:31.091100 FMAP 4. 0xfff7b000 0x00000452
9426 08:06:31.094512 TIME STAMP 5. 0xfff7a000 0x00000910
9427 08:06:31.097903 VBOOT WORK 6. 0xfff66000 0x00014000
9428 08:06:31.101598 RAMOOPS 7. 0xffe66000 0x00100000
9429 08:06:31.104552 COREBOOT 8. 0xffe64000 0x00002000
9430 08:06:31.104975 IMD small region:
9431 08:06:31.108058 IMD ROOT 0. 0xffffec00 0x00000400
9432 08:06:31.111344 VPD 1. 0xffffeb80 0x0000006c
9433 08:06:31.114756 MMC STATUS 2. 0xffffeb60 0x00000004
9434 08:06:31.120977 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9435 08:06:31.124418 Probing TPM: done!
9436 08:06:31.127859 Connected to device vid:did:rid of 1ae0:0028:00
9437 08:06:31.138314 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9438 08:06:31.141320 Initialized TPM device CR50 revision 0
9439 08:06:31.145141 Checking cr50 for pending updates
9440 08:06:31.148460 Reading cr50 TPM mode
9441 08:06:31.157136 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9442 08:06:31.163496 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9443 08:06:31.203325 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9444 08:06:31.206795 Checking segment from ROM address 0x40100000
9445 08:06:31.210269 Checking segment from ROM address 0x4010001c
9446 08:06:31.217041 Loading segment from ROM address 0x40100000
9447 08:06:31.217503 code (compression=0)
9448 08:06:31.226742 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9449 08:06:31.233502 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9450 08:06:31.234025 it's not compressed!
9451 08:06:31.240153 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9452 08:06:31.243537 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9453 08:06:31.264135 Loading segment from ROM address 0x4010001c
9454 08:06:31.264687 Entry Point 0x80000000
9455 08:06:31.267128 Loaded segments
9456 08:06:31.270462 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9457 08:06:31.277669 Jumping to boot code at 0x80000000(0xffe64000)
9458 08:06:31.284327 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9459 08:06:31.290450 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9460 08:06:31.298663 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9461 08:06:31.302163 Checking segment from ROM address 0x40100000
9462 08:06:31.304877 Checking segment from ROM address 0x4010001c
9463 08:06:31.311813 Loading segment from ROM address 0x40100000
9464 08:06:31.312272 code (compression=1)
9465 08:06:31.318276 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9466 08:06:31.328051 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9467 08:06:31.328516 using LZMA
9468 08:06:31.336631 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9469 08:06:31.343737 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9470 08:06:31.346777 Loading segment from ROM address 0x4010001c
9471 08:06:31.347495 Entry Point 0x54601000
9472 08:06:31.350081 Loaded segments
9473 08:06:31.353175 NOTICE: MT8192 bl31_setup
9474 08:06:31.360558 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9475 08:06:31.363524 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9476 08:06:31.367554 WARNING: region 0:
9477 08:06:31.370421 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 08:06:31.371058 WARNING: region 1:
9479 08:06:31.377059 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9480 08:06:31.380324 WARNING: region 2:
9481 08:06:31.383880 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9482 08:06:31.386879 WARNING: region 3:
9483 08:06:31.390401 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9484 08:06:31.394041 WARNING: region 4:
9485 08:06:31.400899 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9486 08:06:31.401388 WARNING: region 5:
9487 08:06:31.403856 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 08:06:31.407043 WARNING: region 6:
9489 08:06:31.410132 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9490 08:06:31.410737 WARNING: region 7:
9491 08:06:31.417444 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 08:06:31.423794 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9493 08:06:31.427293 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9494 08:06:31.430269 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9495 08:06:31.437233 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9496 08:06:31.440603 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9497 08:06:31.443581 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9498 08:06:31.450349 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9499 08:06:31.453901 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9500 08:06:31.460723 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9501 08:06:31.463802 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9502 08:06:31.466999 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9503 08:06:31.473594 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9504 08:06:31.476841 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9505 08:06:31.480285 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9506 08:06:31.487206 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9507 08:06:31.490616 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9508 08:06:31.496842 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9509 08:06:31.500282 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9510 08:06:31.503515 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9511 08:06:31.510211 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9512 08:06:31.513749 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9513 08:06:31.517216 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9514 08:06:31.523764 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9515 08:06:31.527170 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9516 08:06:31.533824 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9517 08:06:31.537287 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9518 08:06:31.541041 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9519 08:06:31.546839 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9520 08:06:31.550368 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9521 08:06:31.557356 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9522 08:06:31.560607 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9523 08:06:31.563846 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9524 08:06:31.570470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9525 08:06:31.573717 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9526 08:06:31.576962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9527 08:06:31.580402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9528 08:06:31.586918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9529 08:06:31.590271 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9530 08:06:31.593675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9531 08:06:31.597225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9532 08:06:31.600633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9533 08:06:31.607255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9534 08:06:31.610251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9535 08:06:31.613809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9536 08:06:31.617525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9537 08:06:31.623376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9538 08:06:31.626784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9539 08:06:31.630379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9540 08:06:31.636724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9541 08:06:31.640370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9542 08:06:31.646473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9543 08:06:31.650197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9544 08:06:31.653384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9545 08:06:31.660239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9546 08:06:31.663562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9547 08:06:31.670060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9548 08:06:31.673651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9549 08:06:31.676751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9550 08:06:31.683499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9551 08:06:31.686859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9552 08:06:31.693324 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9553 08:06:31.696501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9554 08:06:31.703340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9555 08:06:31.707030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9556 08:06:31.713562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9557 08:06:31.716606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9558 08:06:31.719970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9559 08:06:31.726912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9560 08:06:31.730223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9561 08:06:31.737176 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9562 08:06:31.740647 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9563 08:06:31.747287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9564 08:06:31.750881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9565 08:06:31.753431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9566 08:06:31.760825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9567 08:06:31.763771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9568 08:06:31.770418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9569 08:06:31.773926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9570 08:06:31.780570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9571 08:06:31.783768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9572 08:06:31.787371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9573 08:06:31.793732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9574 08:06:31.797343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9575 08:06:31.803864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9576 08:06:31.807007 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9577 08:06:31.813693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9578 08:06:31.817342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9579 08:06:31.820833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9580 08:06:31.827125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9581 08:06:31.830527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9582 08:06:31.837472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9583 08:06:31.840699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9584 08:06:31.847242 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9585 08:06:31.850487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9586 08:06:31.853951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9587 08:06:31.860796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9588 08:06:31.864134 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9589 08:06:31.867688 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9590 08:06:31.874095 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9591 08:06:31.877440 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9592 08:06:31.880761 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9593 08:06:31.887514 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9594 08:06:31.890872 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9595 08:06:31.894376 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9596 08:06:31.900823 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9597 08:06:31.904740 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9598 08:06:31.907479 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9599 08:06:31.914283 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9600 08:06:31.917705 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9601 08:06:31.924296 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9602 08:06:31.927926 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9603 08:06:31.931096 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9604 08:06:31.937499 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9605 08:06:31.940889 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9606 08:06:31.947542 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9607 08:06:31.951018 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9608 08:06:31.954741 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9609 08:06:31.957760 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9610 08:06:31.965010 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9611 08:06:31.968214 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9612 08:06:31.971023 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9613 08:06:31.974647 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9614 08:06:31.981252 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9615 08:06:31.984260 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9616 08:06:31.987817 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9617 08:06:31.994362 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9618 08:06:31.997898 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9619 08:06:32.004326 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9620 08:06:32.008090 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9621 08:06:32.011411 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9622 08:06:32.018063 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9623 08:06:32.021558 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9624 08:06:32.024302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9625 08:06:32.031364 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9626 08:06:32.034694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9627 08:06:32.040961 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9628 08:06:32.044338 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9629 08:06:32.047599 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9630 08:06:32.054473 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9631 08:06:32.057866 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9632 08:06:32.064500 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9633 08:06:32.067900 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9634 08:06:32.071287 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9635 08:06:32.077668 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9636 08:06:32.080891 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9637 08:06:32.088023 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9638 08:06:32.091347 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9639 08:06:32.094354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9640 08:06:32.101268 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9641 08:06:32.104390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9642 08:06:32.107670 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9643 08:06:32.114807 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9644 08:06:32.118271 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9645 08:06:32.124333 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9646 08:06:32.128133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9647 08:06:32.131562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9648 08:06:32.138168 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9649 08:06:32.141600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9650 08:06:32.144482 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9651 08:06:32.151771 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9652 08:06:32.154306 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9653 08:06:32.161142 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9654 08:06:32.164642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9655 08:06:32.167646 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9656 08:06:32.174796 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9657 08:06:32.177549 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9658 08:06:32.184640 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9659 08:06:32.187979 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9660 08:06:32.190835 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9661 08:06:32.197748 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9662 08:06:32.201031 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9663 08:06:32.207772 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9664 08:06:32.210892 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9665 08:06:32.214150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9666 08:06:32.221187 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9667 08:06:32.223976 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9668 08:06:32.230550 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9669 08:06:32.233936 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9670 08:06:32.237251 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9671 08:06:32.244478 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9672 08:06:32.247623 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9673 08:06:32.250493 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9674 08:06:32.257373 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9675 08:06:32.261283 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9676 08:06:32.267150 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9677 08:06:32.270853 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9678 08:06:32.273920 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9679 08:06:32.280452 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9680 08:06:32.283830 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9681 08:06:32.290778 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9682 08:06:32.294057 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9683 08:06:32.300601 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9684 08:06:32.303757 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9685 08:06:32.307186 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9686 08:06:32.313720 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9687 08:06:32.317014 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9688 08:06:32.323632 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9689 08:06:32.327004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9690 08:06:32.330574 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9691 08:06:32.336975 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9692 08:06:32.340425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9693 08:06:32.347106 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9694 08:06:32.350513 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9695 08:06:32.357124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9696 08:06:32.359917 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9697 08:06:32.363254 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9698 08:06:32.369883 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9699 08:06:32.373384 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9700 08:06:32.380125 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9701 08:06:32.383495 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9702 08:06:32.390127 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9703 08:06:32.393332 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9704 08:06:32.396528 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9705 08:06:32.402987 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9706 08:06:32.406449 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9707 08:06:32.413171 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9708 08:06:32.416698 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9709 08:06:32.419858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9710 08:06:32.426165 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9711 08:06:32.429549 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9712 08:06:32.436067 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9713 08:06:32.439874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9714 08:06:32.446269 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9715 08:06:32.449698 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9716 08:06:32.453240 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9717 08:06:32.459643 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9718 08:06:32.463009 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9719 08:06:32.469597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9720 08:06:32.472873 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9721 08:06:32.476326 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9722 08:06:32.479349 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9723 08:06:32.486290 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9724 08:06:32.489921 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9725 08:06:32.492779 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9726 08:06:32.495971 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9727 08:06:32.502657 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9728 08:06:32.506025 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9729 08:06:32.512616 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9730 08:06:32.516446 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9731 08:06:32.519380 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9732 08:06:32.526517 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9733 08:06:32.529664 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9734 08:06:32.532705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9735 08:06:32.539450 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9736 08:06:32.542630 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9737 08:06:32.549296 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9738 08:06:32.553031 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9739 08:06:32.555986 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9740 08:06:32.562413 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9741 08:06:32.565640 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9742 08:06:32.569029 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9743 08:06:32.576122 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9744 08:06:32.579459 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9745 08:06:32.582259 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9746 08:06:32.588970 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9747 08:06:32.592433 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9748 08:06:32.598789 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9749 08:06:32.602136 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9750 08:06:32.605181 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9751 08:06:32.612434 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9752 08:06:32.615679 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9753 08:06:32.618699 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9754 08:06:32.625122 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9755 08:06:32.628604 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9756 08:06:32.632100 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9757 08:06:32.638638 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9758 08:06:32.641966 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9759 08:06:32.648397 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9760 08:06:32.651605 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9761 08:06:32.655105 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9762 08:06:32.658385 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9763 08:06:32.665040 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9764 08:06:32.668382 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9765 08:06:32.671750 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9766 08:06:32.675223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9767 08:06:32.682198 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9768 08:06:32.685542 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9769 08:06:32.688467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9770 08:06:32.691832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9771 08:06:32.698669 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9772 08:06:32.702213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9773 08:06:32.704713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9774 08:06:32.711483 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9775 08:06:32.714980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9776 08:06:32.718168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9777 08:06:32.725139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9778 08:06:32.727996 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9779 08:06:32.734608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9780 08:06:32.738519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9781 08:06:32.741153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9782 08:06:32.748068 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9783 08:06:32.751016 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9784 08:06:32.757373 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9785 08:06:32.760755 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9786 08:06:32.767332 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9787 08:06:32.770504 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9788 08:06:32.774066 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9789 08:06:32.780561 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9790 08:06:32.784070 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9791 08:06:32.790713 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9792 08:06:32.793788 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9793 08:06:32.797506 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9794 08:06:32.803626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9795 08:06:32.807268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9796 08:06:32.814145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9797 08:06:32.817114 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9798 08:06:32.820429 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9799 08:06:32.827305 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9800 08:06:32.830558 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9801 08:06:32.837736 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9802 08:06:32.840688 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9803 08:06:32.847665 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9804 08:06:32.850904 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9805 08:06:32.853542 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9806 08:06:32.860368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9807 08:06:32.863924 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9808 08:06:32.870009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9809 08:06:32.873653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9810 08:06:32.876826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9811 08:06:32.883798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9812 08:06:32.886855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9813 08:06:32.893441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9814 08:06:32.897019 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9815 08:06:32.900497 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9816 08:06:32.907277 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9817 08:06:32.909995 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9818 08:06:32.916859 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9819 08:06:32.920191 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9820 08:06:32.926368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9821 08:06:32.929793 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9822 08:06:32.933428 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9823 08:06:32.939922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9824 08:06:32.943283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9825 08:06:32.949822 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9826 08:06:32.953340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9827 08:06:32.956255 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9828 08:06:32.963214 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9829 08:06:32.966128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9830 08:06:32.973066 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9831 08:06:32.976226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9832 08:06:32.979645 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9833 08:06:32.986289 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9834 08:06:32.989441 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9835 08:06:32.995990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9836 08:06:32.999657 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9837 08:06:33.002704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9838 08:06:33.009345 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9839 08:06:33.012548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9840 08:06:33.019716 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9841 08:06:33.022796 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9842 08:06:33.029304 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9843 08:06:33.032593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9844 08:06:33.036020 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9845 08:06:33.042349 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9846 08:06:33.045991 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9847 08:06:33.052949 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9848 08:06:33.055647 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9849 08:06:33.062205 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9850 08:06:33.065942 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9851 08:06:33.069052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9852 08:06:33.075321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9853 08:06:33.078846 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9854 08:06:33.085378 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9855 08:06:33.088628 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9856 08:06:33.095421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9857 08:06:33.098943 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9858 08:06:33.105307 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9859 08:06:33.109122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9860 08:06:33.112254 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9861 08:06:33.118545 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9862 08:06:33.121726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9863 08:06:33.128296 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9864 08:06:33.132305 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9865 08:06:33.138530 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9866 08:06:33.142024 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9867 08:06:33.145033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9868 08:06:33.151707 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9869 08:06:33.155342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9870 08:06:33.161751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9871 08:06:33.165424 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9872 08:06:33.172033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9873 08:06:33.175265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9874 08:06:33.181958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9875 08:06:33.184744 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9876 08:06:33.188091 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9877 08:06:33.194767 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9878 08:06:33.198119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9879 08:06:33.204507 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9880 08:06:33.208126 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9881 08:06:33.214691 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9882 08:06:33.217936 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9883 08:06:33.221238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9884 08:06:33.227853 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9885 08:06:33.231292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9886 08:06:33.238004 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9887 08:06:33.241306 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9888 08:06:33.248153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9889 08:06:33.250832 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9890 08:06:33.257509 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9891 08:06:33.260957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9892 08:06:33.264493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9893 08:06:33.270822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9894 08:06:33.273995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9895 08:06:33.280753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9896 08:06:33.284302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9897 08:06:33.287667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9898 08:06:33.294113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9899 08:06:33.297278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9900 08:06:33.303995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9901 08:06:33.307332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9902 08:06:33.314060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9903 08:06:33.317364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9904 08:06:33.323509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9905 08:06:33.327199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9906 08:06:33.333840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9907 08:06:33.337035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9908 08:06:33.343698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9909 08:06:33.347176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9910 08:06:33.353660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9911 08:06:33.356847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9912 08:06:33.363315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9913 08:06:33.366721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9914 08:06:33.373869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9915 08:06:33.376668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9916 08:06:33.383769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9917 08:06:33.386847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9918 08:06:33.393436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9919 08:06:33.396638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9920 08:06:33.403679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9921 08:06:33.406562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9922 08:06:33.413375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9923 08:06:33.416348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9924 08:06:33.422963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9925 08:06:33.426265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9926 08:06:33.433229 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9927 08:06:33.433312 INFO: [APUAPC] vio 0
9928 08:06:33.439826 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9929 08:06:33.442939 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9930 08:06:33.446742 INFO: [APUAPC] D0_APC_0: 0x400510
9931 08:06:33.449579 INFO: [APUAPC] D0_APC_1: 0x0
9932 08:06:33.452839 INFO: [APUAPC] D0_APC_2: 0x1540
9933 08:06:33.456648 INFO: [APUAPC] D0_APC_3: 0x0
9934 08:06:33.459525 INFO: [APUAPC] D1_APC_0: 0xffffffff
9935 08:06:33.462822 INFO: [APUAPC] D1_APC_1: 0xffffffff
9936 08:06:33.466536 INFO: [APUAPC] D1_APC_2: 0x3fffff
9937 08:06:33.469937 INFO: [APUAPC] D1_APC_3: 0x0
9938 08:06:33.472789 INFO: [APUAPC] D2_APC_0: 0xffffffff
9939 08:06:33.476277 INFO: [APUAPC] D2_APC_1: 0xffffffff
9940 08:06:33.479654 INFO: [APUAPC] D2_APC_2: 0x3fffff
9941 08:06:33.482834 INFO: [APUAPC] D2_APC_3: 0x0
9942 08:06:33.486276 INFO: [APUAPC] D3_APC_0: 0xffffffff
9943 08:06:33.489736 INFO: [APUAPC] D3_APC_1: 0xffffffff
9944 08:06:33.492653 INFO: [APUAPC] D3_APC_2: 0x3fffff
9945 08:06:33.496096 INFO: [APUAPC] D3_APC_3: 0x0
9946 08:06:33.500080 INFO: [APUAPC] D4_APC_0: 0xffffffff
9947 08:06:33.502727 INFO: [APUAPC] D4_APC_1: 0xffffffff
9948 08:06:33.506357 INFO: [APUAPC] D4_APC_2: 0x3fffff
9949 08:06:33.509983 INFO: [APUAPC] D4_APC_3: 0x0
9950 08:06:33.513132 INFO: [APUAPC] D5_APC_0: 0xffffffff
9951 08:06:33.516918 INFO: [APUAPC] D5_APC_1: 0xffffffff
9952 08:06:33.519521 INFO: [APUAPC] D5_APC_2: 0x3fffff
9953 08:06:33.519957 INFO: [APUAPC] D5_APC_3: 0x0
9954 08:06:33.523104 INFO: [APUAPC] D6_APC_0: 0xffffffff
9955 08:06:33.529724 INFO: [APUAPC] D6_APC_1: 0xffffffff
9956 08:06:33.532922 INFO: [APUAPC] D6_APC_2: 0x3fffff
9957 08:06:33.533555 INFO: [APUAPC] D6_APC_3: 0x0
9958 08:06:33.535970 INFO: [APUAPC] D7_APC_0: 0xffffffff
9959 08:06:33.539281 INFO: [APUAPC] D7_APC_1: 0xffffffff
9960 08:06:33.542640 INFO: [APUAPC] D7_APC_2: 0x3fffff
9961 08:06:33.545939 INFO: [APUAPC] D7_APC_3: 0x0
9962 08:06:33.549412 INFO: [APUAPC] D8_APC_0: 0xffffffff
9963 08:06:33.552780 INFO: [APUAPC] D8_APC_1: 0xffffffff
9964 08:06:33.556258 INFO: [APUAPC] D8_APC_2: 0x3fffff
9965 08:06:33.559146 INFO: [APUAPC] D8_APC_3: 0x0
9966 08:06:33.562545 INFO: [APUAPC] D9_APC_0: 0xffffffff
9967 08:06:33.566319 INFO: [APUAPC] D9_APC_1: 0xffffffff
9968 08:06:33.569470 INFO: [APUAPC] D9_APC_2: 0x3fffff
9969 08:06:33.573617 INFO: [APUAPC] D9_APC_3: 0x0
9970 08:06:33.576622 INFO: [APUAPC] D10_APC_0: 0xffffffff
9971 08:06:33.579232 INFO: [APUAPC] D10_APC_1: 0xffffffff
9972 08:06:33.582597 INFO: [APUAPC] D10_APC_2: 0x3fffff
9973 08:06:33.585883 INFO: [APUAPC] D10_APC_3: 0x0
9974 08:06:33.589387 INFO: [APUAPC] D11_APC_0: 0xffffffff
9975 08:06:33.592887 INFO: [APUAPC] D11_APC_1: 0xffffffff
9976 08:06:33.596132 INFO: [APUAPC] D11_APC_2: 0x3fffff
9977 08:06:33.599698 INFO: [APUAPC] D11_APC_3: 0x0
9978 08:06:33.602714 INFO: [APUAPC] D12_APC_0: 0xffffffff
9979 08:06:33.605900 INFO: [APUAPC] D12_APC_1: 0xffffffff
9980 08:06:33.609455 INFO: [APUAPC] D12_APC_2: 0x3fffff
9981 08:06:33.612687 INFO: [APUAPC] D12_APC_3: 0x0
9982 08:06:33.615840 INFO: [APUAPC] D13_APC_0: 0xffffffff
9983 08:06:33.619200 INFO: [APUAPC] D13_APC_1: 0xffffffff
9984 08:06:33.623019 INFO: [APUAPC] D13_APC_2: 0x3fffff
9985 08:06:33.625534 INFO: [APUAPC] D13_APC_3: 0x0
9986 08:06:33.628719 INFO: [APUAPC] D14_APC_0: 0xffffffff
9987 08:06:33.632598 INFO: [APUAPC] D14_APC_1: 0xffffffff
9988 08:06:33.636024 INFO: [APUAPC] D14_APC_2: 0x3fffff
9989 08:06:33.638964 INFO: [APUAPC] D14_APC_3: 0x0
9990 08:06:33.642372 INFO: [APUAPC] D15_APC_0: 0xffffffff
9991 08:06:33.646057 INFO: [APUAPC] D15_APC_1: 0xffffffff
9992 08:06:33.648850 INFO: [APUAPC] D15_APC_2: 0x3fffff
9993 08:06:33.651961 INFO: [APUAPC] D15_APC_3: 0x0
9994 08:06:33.655725 INFO: [APUAPC] APC_CON: 0x4
9995 08:06:33.658752 INFO: [NOCDAPC] D0_APC_0: 0x0
9996 08:06:33.662445 INFO: [NOCDAPC] D0_APC_1: 0x0
9997 08:06:33.665345 INFO: [NOCDAPC] D1_APC_0: 0x0
9998 08:06:33.668576 INFO: [NOCDAPC] D1_APC_1: 0xfff
9999 08:06:33.672166 INFO: [NOCDAPC] D2_APC_0: 0x0
10000 08:06:33.675226 INFO: [NOCDAPC] D2_APC_1: 0xfff
10001 08:06:33.675875 INFO: [NOCDAPC] D3_APC_0: 0x0
10002 08:06:33.679278 INFO: [NOCDAPC] D3_APC_1: 0xfff
10003 08:06:33.682193 INFO: [NOCDAPC] D4_APC_0: 0x0
10004 08:06:33.685352 INFO: [NOCDAPC] D4_APC_1: 0xfff
10005 08:06:33.688732 INFO: [NOCDAPC] D5_APC_0: 0x0
10006 08:06:33.692459 INFO: [NOCDAPC] D5_APC_1: 0xfff
10007 08:06:33.695924 INFO: [NOCDAPC] D6_APC_0: 0x0
10008 08:06:33.698865 INFO: [NOCDAPC] D6_APC_1: 0xfff
10009 08:06:33.702263 INFO: [NOCDAPC] D7_APC_0: 0x0
10010 08:06:33.705426 INFO: [NOCDAPC] D7_APC_1: 0xfff
10011 08:06:33.705899 INFO: [NOCDAPC] D8_APC_0: 0x0
10012 08:06:33.708482 INFO: [NOCDAPC] D8_APC_1: 0xfff
10013 08:06:33.712174 INFO: [NOCDAPC] D9_APC_0: 0x0
10014 08:06:33.715188 INFO: [NOCDAPC] D9_APC_1: 0xfff
10015 08:06:33.718618 INFO: [NOCDAPC] D10_APC_0: 0x0
10016 08:06:33.722012 INFO: [NOCDAPC] D10_APC_1: 0xfff
10017 08:06:33.725382 INFO: [NOCDAPC] D11_APC_0: 0x0
10018 08:06:33.728829 INFO: [NOCDAPC] D11_APC_1: 0xfff
10019 08:06:33.731842 INFO: [NOCDAPC] D12_APC_0: 0x0
10020 08:06:33.735430 INFO: [NOCDAPC] D12_APC_1: 0xfff
10021 08:06:33.738455 INFO: [NOCDAPC] D13_APC_0: 0x0
10022 08:06:33.741996 INFO: [NOCDAPC] D13_APC_1: 0xfff
10023 08:06:33.745209 INFO: [NOCDAPC] D14_APC_0: 0x0
10024 08:06:33.748708 INFO: [NOCDAPC] D14_APC_1: 0xfff
10025 08:06:33.749180 INFO: [NOCDAPC] D15_APC_0: 0x0
10026 08:06:33.751706 INFO: [NOCDAPC] D15_APC_1: 0xfff
10027 08:06:33.755352 INFO: [NOCDAPC] APC_CON: 0x4
10028 08:06:33.758337 INFO: [APUAPC] set_apusys_apc done
10029 08:06:33.761768 INFO: [DEVAPC] devapc_init done
10030 08:06:33.768371 INFO: GICv3 without legacy support detected.
10031 08:06:33.771846 INFO: ARM GICv3 driver initialized in EL3
10032 08:06:33.775190 INFO: Maximum SPI INTID supported: 639
10033 08:06:33.778901 INFO: BL31: Initializing runtime services
10034 08:06:33.784789 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10035 08:06:33.788625 INFO: SPM: enable CPC mode
10036 08:06:33.791722 INFO: mcdi ready for mcusys-off-idle and system suspend
10037 08:06:33.798002 INFO: BL31: Preparing for EL3 exit to normal world
10038 08:06:33.802188 INFO: Entry point address = 0x80000000
10039 08:06:33.802786 INFO: SPSR = 0x8
10040 08:06:33.808236
10041 08:06:33.808700
10042 08:06:33.809070
10043 08:06:33.812069 Starting depthcharge on Spherion...
10044 08:06:33.812537
10045 08:06:33.812906 Wipe memory regions:
10046 08:06:33.813255
10047 08:06:33.815947 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10048 08:06:33.816504 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10049 08:06:33.816968 Setting prompt string to ['asurada:']
10050 08:06:33.817408 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10051 08:06:33.818320 [0x00000040000000, 0x00000054600000)
10052 08:06:33.937339
10053 08:06:33.937876 [0x00000054660000, 0x00000080000000)
10054 08:06:34.197779
10055 08:06:34.198291 [0x000000821a7280, 0x000000ffe64000)
10056 08:06:34.941825
10057 08:06:34.941961 [0x00000100000000, 0x00000240000000)
10058 08:06:36.832936
10059 08:06:36.836497 Initializing XHCI USB controller at 0x11200000.
10060 08:06:37.874890
10061 08:06:37.877644 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10062 08:06:37.877731
10063 08:06:37.877797
10064 08:06:37.877861
10065 08:06:37.878152 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10067 08:06:37.978511 asurada: tftpboot 192.168.201.1 11585978/tftp-deploy-wcgepl6x/kernel/image.itb 11585978/tftp-deploy-wcgepl6x/kernel/cmdline
10068 08:06:37.978644 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 08:06:37.978732 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10070 08:06:37.983018 tftpboot 192.168.201.1 11585978/tftp-deploy-wcgepl6x/kernel/image.itp-deploy-wcgepl6x/kernel/cmdline
10071 08:06:37.983106
10072 08:06:37.983171 Waiting for link
10073 08:06:38.143334
10074 08:06:38.143486 R8152: Initializing
10075 08:06:38.143553
10076 08:06:38.146588 Version 6 (ocp_data = 5c30)
10077 08:06:38.146671
10078 08:06:38.150112 R8152: Done initializing
10079 08:06:38.150195
10080 08:06:38.150260 Adding net device
10081 08:06:40.179952
10082 08:06:40.180574 done.
10083 08:06:40.181123
10084 08:06:40.181646 MAC: 00:24:32:30:78:ff
10085 08:06:40.182118
10086 08:06:40.183495 Sending DHCP discover... done.
10087 08:06:40.184001
10088 08:06:40.186582 Waiting for reply... done.
10089 08:06:40.187008
10090 08:06:40.190142 Sending DHCP request... done.
10091 08:06:40.190740
10092 08:06:40.195609 Waiting for reply... done.
10093 08:06:40.196289
10094 08:06:40.196867 My ip is 192.168.201.21
10095 08:06:40.197223
10096 08:06:40.198722 The DHCP server ip is 192.168.201.1
10097 08:06:40.199256
10098 08:06:40.205854 TFTP server IP predefined by user: 192.168.201.1
10099 08:06:40.206297
10100 08:06:40.212447 Bootfile predefined by user: 11585978/tftp-deploy-wcgepl6x/kernel/image.itb
10101 08:06:40.212869
10102 08:06:40.213257 Sending tftp read request... done.
10103 08:06:40.215392
10104 08:06:40.219746 Waiting for the transfer...
10105 08:06:40.219829
10106 08:06:40.754244 00000000 ################################################################
10107 08:06:40.754380
10108 08:06:41.286595 00080000 ################################################################
10109 08:06:41.286732
10110 08:06:41.827231 00100000 ################################################################
10111 08:06:41.827416
10112 08:06:42.356808 00180000 ################################################################
10113 08:06:42.356961
10114 08:06:42.910876 00200000 ################################################################
10115 08:06:42.911014
10116 08:06:43.450697 00280000 ################################################################
10117 08:06:43.450832
10118 08:06:44.011558 00300000 ################################################################
10119 08:06:44.011690
10120 08:06:44.555998 00380000 ################################################################
10121 08:06:44.556148
10122 08:06:45.104495 00400000 ################################################################
10123 08:06:45.104632
10124 08:06:45.666946 00480000 ################################################################
10125 08:06:45.667093
10126 08:06:46.268385 00500000 ################################################################
10127 08:06:46.268524
10128 08:06:46.857400 00580000 ################################################################
10129 08:06:46.857540
10130 08:06:47.405863 00600000 ################################################################
10131 08:06:47.405998
10132 08:06:47.963362 00680000 ################################################################
10133 08:06:47.963547
10134 08:06:48.496321 00700000 ################################################################
10135 08:06:48.496453
10136 08:06:49.038159 00780000 ################################################################
10137 08:06:49.038328
10138 08:06:49.622709 00800000 ################################################################
10139 08:06:49.622848
10140 08:06:50.299008 00880000 ################################################################
10141 08:06:50.299534
10142 08:06:50.935346 00900000 ################################################################
10143 08:06:50.935562
10144 08:06:51.491066 00980000 ################################################################
10145 08:06:51.491198
10146 08:06:52.122278 00a00000 ################################################################
10147 08:06:52.122879
10148 08:06:52.816181 00a80000 ################################################################
10149 08:06:52.816731
10150 08:06:53.492346 00b00000 ################################################################
10151 08:06:53.493023
10152 08:06:54.180358 00b80000 ################################################################
10153 08:06:54.180870
10154 08:06:54.875823 00c00000 ################################################################
10155 08:06:54.876378
10156 08:06:55.539203 00c80000 ################################################################
10157 08:06:55.539889
10158 08:06:56.217599 00d00000 ################################################################
10159 08:06:56.218116
10160 08:06:56.882606 00d80000 ################################################################
10161 08:06:56.883163
10162 08:06:57.569064 00e00000 ################################################################
10163 08:06:57.569621
10164 08:06:58.227353 00e80000 ################################################################
10165 08:06:58.227506
10166 08:06:58.903696 00f00000 ################################################################
10167 08:06:58.904367
10168 08:06:59.590027 00f80000 ################################################################
10169 08:06:59.590541
10170 08:07:00.271850 01000000 ################################################################
10171 08:07:00.272430
10172 08:07:00.948354 01080000 ################################################################
10173 08:07:00.948860
10174 08:07:01.634933 01100000 ################################################################
10175 08:07:01.635495
10176 08:07:02.313933 01180000 ################################################################
10177 08:07:02.314069
10178 08:07:02.999153 01200000 ################################################################
10179 08:07:02.999769
10180 08:07:03.665356 01280000 ################################################################
10181 08:07:03.665883
10182 08:07:04.326239 01300000 ################################################################
10183 08:07:04.326785
10184 08:07:05.011068 01380000 ################################################################
10185 08:07:05.011649
10186 08:07:05.662738 01400000 ################################################################
10187 08:07:05.663254
10188 08:07:06.317809 01480000 ################################################################
10189 08:07:06.317943
10190 08:07:06.954858 01500000 ################################################################
10191 08:07:06.955005
10192 08:07:07.593697 01580000 ################################################################
10193 08:07:07.593841
10194 08:07:08.226019 01600000 ################################################################
10195 08:07:08.226162
10196 08:07:08.894469 01680000 ################################################################
10197 08:07:08.894996
10198 08:07:09.568291 01700000 ################################################################
10199 08:07:09.568852
10200 08:07:10.250266 01780000 ################################################################
10201 08:07:10.250835
10202 08:07:10.930994 01800000 ################################################################
10203 08:07:10.931606
10204 08:07:11.611932 01880000 ################################################################
10205 08:07:11.612481
10206 08:07:12.284482 01900000 ################################################################
10207 08:07:12.284993
10208 08:07:12.962673 01980000 ################################################################
10209 08:07:12.963224
10210 08:07:13.643219 01a00000 ################################################################
10211 08:07:13.643843
10212 08:07:14.319074 01a80000 ################################################################
10213 08:07:14.319634
10214 08:07:14.991607 01b00000 ################################################################
10215 08:07:14.992158
10216 08:07:15.650064 01b80000 ################################################################
10217 08:07:15.650430
10218 08:07:16.245981 01c00000 ################################################################
10219 08:07:16.246115
10220 08:07:16.881991 01c80000 ################################################################
10221 08:07:16.882126
10222 08:07:17.518680 01d00000 ################################################################
10223 08:07:17.519051
10224 08:07:18.176918 01d80000 ################################################################
10225 08:07:18.177051
10226 08:07:18.779567 01e00000 ################################################################
10227 08:07:18.780326
10228 08:07:19.376754 01e80000 ################################################################
10229 08:07:19.377296
10230 08:07:20.003866 01f00000 ################################################################
10231 08:07:20.004004
10232 08:07:20.597184 01f80000 ################################################################
10233 08:07:20.597322
10234 08:07:21.165536 02000000 ################################################################
10235 08:07:21.165675
10236 08:07:21.748647 02080000 ################################################################
10237 08:07:21.748787
10238 08:07:22.346580 02100000 ################################################################
10239 08:07:22.346788
10240 08:07:23.039694 02180000 ################################################################
10241 08:07:23.040247
10242 08:07:23.626924 02200000 ################################################################
10243 08:07:23.627197
10244 08:07:24.295204 02280000 ################################################################
10245 08:07:24.295782
10246 08:07:24.958028 02300000 ################################################################
10247 08:07:24.958182
10248 08:07:25.603305 02380000 ################################################################
10249 08:07:25.603469
10250 08:07:26.255001 02400000 ################################################################
10251 08:07:26.255594
10252 08:07:26.956112 02480000 ################################################################
10253 08:07:26.956626
10254 08:07:27.648947 02500000 ################################################################
10255 08:07:27.649498
10256 08:07:28.338866 02580000 ################################################################
10257 08:07:28.339423
10258 08:07:28.981094 02600000 ################################################################
10259 08:07:28.981233
10260 08:07:29.626373 02680000 ################################################################
10261 08:07:29.626521
10262 08:07:30.250876 02700000 ################################################################
10263 08:07:30.251025
10264 08:07:30.940748 02780000 ################################################################
10265 08:07:30.941307
10266 08:07:31.637722 02800000 ################################################################
10267 08:07:31.638274
10268 08:07:32.327594 02880000 ################################################################
10269 08:07:32.328120
10270 08:07:32.982914 02900000 ################################################################
10271 08:07:32.983465
10272 08:07:33.678778 02980000 ################################################################
10273 08:07:33.679335
10274 08:07:34.371740 02a00000 ################################################################
10275 08:07:34.372293
10276 08:07:35.033833 02a80000 ################################################################
10277 08:07:35.034397
10278 08:07:35.700563 02b00000 ################################################################
10279 08:07:35.701118
10280 08:07:36.394225 02b80000 ################################################################
10281 08:07:36.394737
10282 08:07:37.086823 02c00000 ################################################################
10283 08:07:37.087417
10284 08:07:37.769391 02c80000 ################################################################
10285 08:07:37.770207
10286 08:07:38.425194 02d00000 ################################################################
10287 08:07:38.425707
10288 08:07:39.054125 02d80000 ################################################################
10289 08:07:39.054272
10290 08:07:39.676394 02e00000 ################################################################
10291 08:07:39.676569
10292 08:07:40.322606 02e80000 ################################################################
10293 08:07:40.322753
10294 08:07:40.973623 02f00000 ################################################################
10295 08:07:40.974176
10296 08:07:41.660140 02f80000 ################################################################
10297 08:07:41.660765
10298 08:07:42.343433 03000000 ################################################################
10299 08:07:42.343962
10300 08:07:43.016619 03080000 ################################################################
10301 08:07:43.017213
10302 08:07:43.697786 03100000 ################################################################
10303 08:07:43.698329
10304 08:07:44.381506 03180000 ################################################################
10305 08:07:44.382072
10306 08:07:45.066484 03200000 ################################################################
10307 08:07:45.067049
10308 08:07:45.734052 03280000 ################################################################
10309 08:07:45.734609
10310 08:07:46.437982 03300000 ################################################################
10311 08:07:46.438530
10312 08:07:47.106675 03380000 ################################################################
10313 08:07:47.107243
10314 08:07:47.799319 03400000 ################################################################
10315 08:07:47.799565
10316 08:07:48.488865 03480000 ################################################################
10317 08:07:48.489450
10318 08:07:49.151277 03500000 ################################################################
10319 08:07:49.151850
10320 08:07:49.833394 03580000 ################################################################
10321 08:07:49.833942
10322 08:07:50.514516 03600000 ################################################################
10323 08:07:50.514670
10324 08:07:51.189217 03680000 ################################################################
10325 08:07:51.189757
10326 08:07:51.864887 03700000 ################################################################
10327 08:07:51.865029
10328 08:07:52.529460 03780000 ################################################################
10329 08:07:52.530015
10330 08:07:53.224685 03800000 ################################################################
10331 08:07:53.225247
10332 08:07:53.872717 03880000 ################################################################
10333 08:07:53.873272
10334 08:07:54.531255 03900000 ################################################################
10335 08:07:54.531861
10336 08:07:55.210805 03980000 ################################################################
10337 08:07:55.211329
10338 08:07:55.865403 03a00000 ################################################################
10339 08:07:55.865973
10340 08:07:56.543495 03a80000 ################################################################
10341 08:07:56.544109
10342 08:07:57.240337 03b00000 ################################################################
10343 08:07:57.240910
10344 08:07:57.890379 03b80000 ################################################################
10345 08:07:57.890931
10346 08:07:58.566047 03c00000 ################################################################
10347 08:07:58.566594
10348 08:07:59.233848 03c80000 ################################################################
10349 08:07:59.234362
10350 08:07:59.887974 03d00000 ################################################################
10351 08:07:59.888535
10352 08:08:00.537476 03d80000 ################################################################
10353 08:08:00.538036
10354 08:08:01.189796 03e00000 ################################################################
10355 08:08:01.190369
10356 08:08:01.868654 03e80000 ################################################################
10357 08:08:01.869218
10358 08:08:02.511218 03f00000 ################################################################
10359 08:08:02.511755
10360 08:08:03.164847 03f80000 ################################################################
10361 08:08:03.165407
10362 08:08:03.848207 04000000 ################################################################
10363 08:08:03.848769
10364 08:08:04.534975 04080000 ################################################################
10365 08:08:04.535575
10366 08:08:05.221222 04100000 ################################################################
10367 08:08:05.221795
10368 08:08:05.920645 04180000 ################################################################
10369 08:08:05.921197
10370 08:08:06.598806 04200000 ################################################################
10371 08:08:06.599363
10372 08:08:07.272650 04280000 ################################################################
10373 08:08:07.273192
10374 08:08:07.949322 04300000 ################################################################
10375 08:08:07.949829
10376 08:08:08.614267 04380000 ################################################################
10377 08:08:08.614828
10378 08:08:09.287564 04400000 ################################################################
10379 08:08:09.288073
10380 08:08:09.964214 04480000 ################################################################
10381 08:08:09.964725
10382 08:08:10.648406 04500000 ################################################################
10383 08:08:10.648556
10384 08:08:11.292887 04580000 ################################################################
10385 08:08:11.293034
10386 08:08:11.937802 04600000 ################################################################
10387 08:08:11.937946
10388 08:08:12.548926 04680000 ################################################################
10389 08:08:12.549072
10390 08:08:13.160900 04700000 ################################################################
10391 08:08:13.161049
10392 08:08:13.816272 04780000 ################################################################
10393 08:08:13.816780
10394 08:08:14.497114 04800000 ################################################################
10395 08:08:14.497673
10396 08:08:15.179978 04880000 ################################################################
10397 08:08:15.180557
10398 08:08:15.858216 04900000 ################################################################
10399 08:08:15.858776
10400 08:08:16.541996 04980000 ################################################################
10401 08:08:16.542571
10402 08:08:17.203177 04a00000 ################################################################
10403 08:08:17.203775
10404 08:08:17.861438 04a80000 ################################################################
10405 08:08:17.862001
10406 08:08:18.554756 04b00000 ################################################################
10407 08:08:18.555314
10408 08:08:19.134967 04b80000 ################################################################
10409 08:08:19.135160
10410 08:08:19.785440 04c00000 ################################################################
10411 08:08:19.785986
10412 08:08:20.387128 04c80000 ################################################################
10413 08:08:20.387273
10414 08:08:20.999006 04d00000 ################################################################
10415 08:08:20.999628
10416 08:08:21.686588 04d80000 ################################################################
10417 08:08:21.687175
10418 08:08:22.388377 04e00000 ################################################################
10419 08:08:22.388892
10420 08:08:23.053774 04e80000 ################################################################
10421 08:08:23.054287
10422 08:08:23.676779 04f00000 ################################################################
10423 08:08:23.676924
10424 08:08:24.292646 04f80000 ################################################################
10425 08:08:24.292797
10426 08:08:24.944442 05000000 ################################################################
10427 08:08:24.945014
10428 08:08:25.629784 05080000 ################################################################
10429 08:08:25.630299
10430 08:08:26.286303 05100000 ################################################################
10431 08:08:26.286865
10432 08:08:26.965907 05180000 ################################################################
10433 08:08:26.966458
10434 08:08:27.633187 05200000 ################################################################
10435 08:08:27.633740
10436 08:08:28.316119 05280000 ################################################################
10437 08:08:28.316686
10438 08:08:28.999209 05300000 ################################################################
10439 08:08:28.999800
10440 08:08:29.658459 05380000 ################################################################
10441 08:08:29.659027
10442 08:08:30.326876 05400000 ################################################################
10443 08:08:30.327476
10444 08:08:31.008959 05480000 ################################################################
10445 08:08:31.009468
10446 08:08:31.692262 05500000 ################################################################
10447 08:08:31.692829
10448 08:08:32.377491 05580000 ################################################################
10449 08:08:32.378050
10450 08:08:33.060610 05600000 ################################################################
10451 08:08:33.061158
10452 08:08:33.746696 05680000 ################################################################
10453 08:08:33.747254
10454 08:08:34.417603 05700000 ################################################################
10455 08:08:34.418173
10456 08:08:35.088804 05780000 ################################################################
10457 08:08:35.089441
10458 08:08:35.765207 05800000 ################################################################
10459 08:08:35.765757
10460 08:08:36.458206 05880000 ################################################################
10461 08:08:36.458840
10462 08:08:37.131908 05900000 ################################################################
10463 08:08:37.132524
10464 08:08:37.817660 05980000 ################################################################
10465 08:08:37.818210
10466 08:08:38.486529 05a00000 ################################################################
10467 08:08:38.487080
10468 08:08:39.170499 05a80000 ################################################################
10469 08:08:39.171176
10470 08:08:39.840741 05b00000 ################################################################
10471 08:08:39.841540
10472 08:08:40.520971 05b80000 ################################################################
10473 08:08:40.521528
10474 08:08:41.201658 05c00000 ################################################################
10475 08:08:41.202215
10476 08:08:41.870123 05c80000 ################################################################
10477 08:08:41.870730
10478 08:08:42.562571 05d00000 ################################################################
10479 08:08:42.563180
10480 08:08:43.264575 05d80000 ################################################################
10481 08:08:43.265145
10482 08:08:43.940093 05e00000 ################################################################
10483 08:08:43.940656
10484 08:08:44.611644 05e80000 ################################################################
10485 08:08:44.612215
10486 08:08:45.294856 05f00000 ################################################################
10487 08:08:45.295465
10488 08:08:45.972130 05f80000 ################################################################
10489 08:08:45.972698
10490 08:08:46.645604 06000000 ################################################################
10491 08:08:46.646180
10492 08:08:47.304079 06080000 ################################################################
10493 08:08:47.304642
10494 08:08:47.965746 06100000 ################################################################
10495 08:08:47.966307
10496 08:08:48.621518 06180000 ################################################################
10497 08:08:48.622106
10498 08:08:49.286887 06200000 ################################################################
10499 08:08:49.287528
10500 08:08:49.910644 06280000 ################################################################
10501 08:08:49.910780
10502 08:08:50.573681 06300000 ################################################################
10503 08:08:50.574234
10504 08:08:51.253593 06380000 ################################################################
10505 08:08:51.254224
10506 08:08:51.947500 06400000 ################################################################
10507 08:08:51.948112
10508 08:08:52.631463 06480000 ################################################################
10509 08:08:52.632083
10510 08:08:53.320471 06500000 ################################################################
10511 08:08:53.321042
10512 08:08:54.006228 06580000 ################################################################
10513 08:08:54.006872
10514 08:08:54.685304 06600000 ################################################################
10515 08:08:54.685869
10516 08:08:55.344710 06680000 ################################################################
10517 08:08:55.345273
10518 08:08:56.014716 06700000 ################################################################
10519 08:08:56.015355
10520 08:08:56.716503 06780000 ################################################################
10521 08:08:56.717111
10522 08:08:57.181477 06800000 ########################################### done.
10523 08:08:57.181992
10524 08:08:57.185214 The bootfile was 109402518 bytes long.
10525 08:08:57.185693
10526 08:08:57.188460 Sending tftp read request... done.
10527 08:08:57.188934
10528 08:08:57.192837 Waiting for the transfer...
10529 08:08:57.193307
10530 08:08:57.193679 00000000 # done.
10531 08:08:57.194037
10532 08:08:57.199426 Command line loaded dynamically from TFTP file: 11585978/tftp-deploy-wcgepl6x/kernel/cmdline
10533 08:08:57.199997
10534 08:08:57.216217 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10535 08:08:57.216791
10536 08:08:57.217245 Loading FIT.
10537 08:08:57.217615
10538 08:08:57.219106 Image ramdisk-1 has 98307938 bytes.
10539 08:08:57.219619
10540 08:08:57.222186 Image fdt-1 has 47278 bytes.
10541 08:08:57.222655
10542 08:08:57.225841 Image kernel-1 has 11045265 bytes.
10543 08:08:57.226309
10544 08:08:57.232456 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10545 08:08:57.233024
10546 08:08:57.252662 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10547 08:08:57.253252
10548 08:08:57.255963 Choosing best match conf-1 for compat google,spherion-rev2.
10549 08:08:57.260706
10550 08:08:57.265171 Connected to device vid:did:rid of 1ae0:0028:00
10551 08:08:57.273332
10552 08:08:57.277115 tpm_get_response: command 0x17b, return code 0x0
10553 08:08:57.277685
10554 08:08:57.279742 ec_init: CrosEC protocol v3 supported (256, 248)
10555 08:08:57.282947
10556 08:08:57.286498 tpm_cleanup: add release locality here.
10557 08:08:57.287064
10558 08:08:57.290167 Shutting down all USB controllers.
10559 08:08:57.290731
10560 08:08:57.293110 Removing current net device
10561 08:08:57.293671
10562 08:08:57.296589 Exiting depthcharge with code 4 at timestamp: 172808106
10563 08:08:57.297155
10564 08:08:57.299964 LZMA decompressing kernel-1 to 0x821a6718
10565 08:08:57.303728
10566 08:08:57.306273 LZMA decompressing kernel-1 to 0x40000000
10567 08:08:58.693914
10568 08:08:58.694490 jumping to kernel
10569 08:08:58.696337 end: 2.2.4 bootloader-commands (duration 00:02:25) [common]
10570 08:08:58.696873 start: 2.2.5 auto-login-action (timeout 00:02:00) [common]
10571 08:08:58.697292 Setting prompt string to ['Linux version [0-9]']
10572 08:08:58.697681 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10573 08:08:58.698067 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10574 08:08:58.776013
10575 08:08:58.779110 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10576 08:08:58.783202 start: 2.2.5.1 login-action (timeout 00:02:00) [common]
10577 08:08:58.783837 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10578 08:08:58.784240 Setting prompt string to []
10579 08:08:58.784785 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10580 08:08:58.785193 Using line separator: #'\n'#
10581 08:08:58.785534 No login prompt set.
10582 08:08:58.785876 Parsing kernel messages
10583 08:08:58.786185 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10584 08:08:58.786756 [login-action] Waiting for messages, (timeout 00:02:00)
10585 08:08:58.801803 [ 0.000000] Linux version 6.1.54-cip6 (KernelCI@build-j53272-arm64-gcc-10-defconfig-arm64-chromebook-xzlx8) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023
10586 08:08:58.805327 [ 0.000000] random: crng init done
10587 08:08:58.812241 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10588 08:08:58.815848 [ 0.000000] efi: UEFI not found.
10589 08:08:58.822463 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10590 08:08:58.828545 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10591 08:08:58.838317 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10592 08:08:58.848656 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10593 08:08:58.855189 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10594 08:08:58.861735 [ 0.000000] printk: bootconsole [mtk8250] enabled
10595 08:08:58.868267 [ 0.000000] NUMA: No NUMA configuration found
10596 08:08:58.874774 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10597 08:08:58.877898 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10598 08:08:58.881567 [ 0.000000] Zone ranges:
10599 08:08:58.887669 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10600 08:08:58.891499 [ 0.000000] DMA32 empty
10601 08:08:58.897897 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10602 08:08:58.901353 [ 0.000000] Movable zone start for each node
10603 08:08:58.904322 [ 0.000000] Early memory node ranges
10604 08:08:58.911234 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10605 08:08:58.917812 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10606 08:08:58.924145 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10607 08:08:58.930751 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10608 08:08:58.937864 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10609 08:08:58.944040 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10610 08:08:59.000340 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10611 08:08:59.006955 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10612 08:08:59.013264 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10613 08:08:59.016335 [ 0.000000] psci: probing for conduit method from DT.
10614 08:08:59.023013 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10615 08:08:59.026723 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10616 08:08:59.033037 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10617 08:08:59.036305 [ 0.000000] psci: SMC Calling Convention v1.2
10618 08:08:59.043359 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10619 08:08:59.046340 [ 0.000000] Detected VIPT I-cache on CPU0
10620 08:08:59.053213 [ 0.000000] CPU features: detected: GIC system register CPU interface
10621 08:08:59.059771 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10622 08:08:59.066570 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10623 08:08:59.072458 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10624 08:08:59.079279 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10625 08:08:59.089713 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10626 08:08:59.092899 [ 0.000000] alternatives: applying boot alternatives
10627 08:08:59.099302 [ 0.000000] Fallback order for Node 0: 0
10628 08:08:59.106241 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10629 08:08:59.109049 [ 0.000000] Policy zone: Normal
10630 08:08:59.122558 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10631 08:08:59.132046 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10632 08:08:59.143195 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10633 08:08:59.152848 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10634 08:08:59.160282 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10635 08:08:59.162731 <6>[ 0.000000] software IO TLB: area num 8.
10636 08:08:59.219595 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10637 08:08:59.368779 <6>[ 0.000000] Memory: 7873424K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 479344K reserved, 32768K cma-reserved)
10638 08:08:59.375482 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10639 08:08:59.382279 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10640 08:08:59.384915 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10641 08:08:59.391890 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10642 08:08:59.398357 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10643 08:08:59.401607 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10644 08:08:59.411847 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10645 08:08:59.418782 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10646 08:08:59.424863 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10647 08:08:59.431446 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10648 08:08:59.434872 <6>[ 0.000000] GICv3: 608 SPIs implemented
10649 08:08:59.438438 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10650 08:08:59.444743 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10651 08:08:59.448413 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10652 08:08:59.455199 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10653 08:08:59.468101 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10654 08:08:59.478250 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10655 08:08:59.487631 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10656 08:08:59.494793 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10657 08:08:59.508748 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10658 08:08:59.515027 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10659 08:08:59.521594 <6>[ 0.009232] Console: colour dummy device 80x25
10660 08:08:59.531655 <6>[ 0.013987] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10661 08:08:59.538048 <6>[ 0.024430] pid_max: default: 32768 minimum: 301
10662 08:08:59.541859 <6>[ 0.029296] LSM: Security Framework initializing
10663 08:08:59.548161 <6>[ 0.034233] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10664 08:08:59.558073 <6>[ 0.042047] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10665 08:08:59.564936 <6>[ 0.051456] cblist_init_generic: Setting adjustable number of callback queues.
10666 08:08:59.571091 <6>[ 0.058900] cblist_init_generic: Setting shift to 3 and lim to 1.
10667 08:08:59.581187 <6>[ 0.065278] cblist_init_generic: Setting adjustable number of callback queues.
10668 08:08:59.587891 <6>[ 0.072751] cblist_init_generic: Setting shift to 3 and lim to 1.
10669 08:08:59.591264 <6>[ 0.079151] rcu: Hierarchical SRCU implementation.
10670 08:08:59.597904 <6>[ 0.084197] rcu: Max phase no-delay instances is 1000.
10671 08:08:59.604591 <6>[ 0.091259] EFI services will not be available.
10672 08:08:59.607893 <6>[ 0.096204] smp: Bringing up secondary CPUs ...
10673 08:08:59.615774 <6>[ 0.101253] Detected VIPT I-cache on CPU1
10674 08:08:59.622537 <6>[ 0.101324] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10675 08:08:59.629017 <6>[ 0.101355] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10676 08:08:59.632309 <6>[ 0.101697] Detected VIPT I-cache on CPU2
10677 08:08:59.638832 <6>[ 0.101749] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10678 08:08:59.649422 <6>[ 0.101765] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10679 08:08:59.652339 <6>[ 0.102022] Detected VIPT I-cache on CPU3
10680 08:08:59.659013 <6>[ 0.102070] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10681 08:08:59.665632 <6>[ 0.102084] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10682 08:08:59.669109 <6>[ 0.102384] CPU features: detected: Spectre-v4
10683 08:08:59.675878 <6>[ 0.102391] CPU features: detected: Spectre-BHB
10684 08:08:59.679268 <6>[ 0.102396] Detected PIPT I-cache on CPU4
10685 08:08:59.685645 <6>[ 0.102456] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10686 08:08:59.691874 <6>[ 0.102472] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10687 08:08:59.698890 <6>[ 0.102764] Detected PIPT I-cache on CPU5
10688 08:08:59.704992 <6>[ 0.102828] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10689 08:08:59.712023 <6>[ 0.102845] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10690 08:08:59.715651 <6>[ 0.103128] Detected PIPT I-cache on CPU6
10691 08:08:59.722346 <6>[ 0.103195] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10692 08:08:59.728601 <6>[ 0.103211] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10693 08:08:59.735043 <6>[ 0.103506] Detected PIPT I-cache on CPU7
10694 08:08:59.742000 <6>[ 0.103573] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10695 08:08:59.748427 <6>[ 0.103589] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10696 08:08:59.751749 <6>[ 0.103636] smp: Brought up 1 node, 8 CPUs
10697 08:08:59.758332 <6>[ 0.244924] SMP: Total of 8 processors activated.
10698 08:08:59.761748 <6>[ 0.249845] CPU features: detected: 32-bit EL0 Support
10699 08:08:59.772026 <6>[ 0.255207] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10700 08:08:59.778112 <6>[ 0.264007] CPU features: detected: Common not Private translations
10701 08:08:59.784626 <6>[ 0.270482] CPU features: detected: CRC32 instructions
10702 08:08:59.788695 <6>[ 0.275866] CPU features: detected: RCpc load-acquire (LDAPR)
10703 08:08:59.794337 <6>[ 0.281863] CPU features: detected: LSE atomic instructions
10704 08:08:59.801176 <6>[ 0.287645] CPU features: detected: Privileged Access Never
10705 08:08:59.807973 <6>[ 0.293424] CPU features: detected: RAS Extension Support
10706 08:08:59.814324 <6>[ 0.299033] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10707 08:08:59.817447 <6>[ 0.306252] CPU: All CPU(s) started at EL2
10708 08:08:59.824242 <6>[ 0.310569] alternatives: applying system-wide alternatives
10709 08:08:59.833506 <6>[ 0.321278] devtmpfs: initialized
10710 08:08:59.848872 <6>[ 0.330252] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10711 08:08:59.855827 <6>[ 0.340214] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10712 08:08:59.859095 <6>[ 0.347873] pinctrl core: initialized pinctrl subsystem
10713 08:08:59.867335 <6>[ 0.354721] DMI not present or invalid.
10714 08:08:59.873730 <6>[ 0.359132] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10715 08:08:59.880261 <6>[ 0.365989] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10716 08:08:59.889915 <6>[ 0.373578] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10717 08:08:59.896923 <6>[ 0.381801] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10718 08:08:59.903456 <6>[ 0.390040] audit: initializing netlink subsys (disabled)
10719 08:08:59.910025 <5>[ 0.395729] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10720 08:08:59.917125 <6>[ 0.396486] thermal_sys: Registered thermal governor 'step_wise'
10721 08:08:59.923014 <6>[ 0.403695] thermal_sys: Registered thermal governor 'power_allocator'
10722 08:08:59.930189 <6>[ 0.409950] cpuidle: using governor menu
10723 08:08:59.933343 <6>[ 0.420911] NET: Registered PF_QIPCRTR protocol family
10724 08:08:59.939874 <6>[ 0.426386] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10725 08:08:59.946680 <6>[ 0.433490] ASID allocator initialised with 32768 entries
10726 08:08:59.952960 <6>[ 0.440132] Serial: AMBA PL011 UART driver
10727 08:08:59.961529 <4>[ 0.449277] Trying to register duplicate clock ID: 134
10728 08:09:00.018517 <6>[ 0.509567] KASLR enabled
10729 08:09:00.033418 <6>[ 0.517482] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10730 08:09:00.039999 <6>[ 0.524495] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10731 08:09:00.046161 <6>[ 0.530987] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10732 08:09:00.053043 <6>[ 0.537991] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10733 08:09:00.059605 <6>[ 0.544479] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10734 08:09:00.066313 <6>[ 0.551484] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10735 08:09:00.073415 <6>[ 0.557973] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10736 08:09:00.079514 <6>[ 0.564976] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10737 08:09:00.082794 <6>[ 0.572506] ACPI: Interpreter disabled.
10738 08:09:00.091760 <6>[ 0.579000] iommu: Default domain type: Translated
10739 08:09:00.097976 <6>[ 0.584112] iommu: DMA domain TLB invalidation policy: strict mode
10740 08:09:00.101186 <5>[ 0.590775] SCSI subsystem initialized
10741 08:09:00.107884 <6>[ 0.594942] usbcore: registered new interface driver usbfs
10742 08:09:00.114796 <6>[ 0.600673] usbcore: registered new interface driver hub
10743 08:09:00.118380 <6>[ 0.606227] usbcore: registered new device driver usb
10744 08:09:00.124971 <6>[ 0.612373] pps_core: LinuxPPS API ver. 1 registered
10745 08:09:00.134912 <6>[ 0.617567] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10746 08:09:00.137952 <6>[ 0.626912] PTP clock support registered
10747 08:09:00.141091 <6>[ 0.631157] EDAC MC: Ver: 3.0.0
10748 08:09:00.148773 <6>[ 0.636374] FPGA manager framework
10749 08:09:00.155159 <6>[ 0.640056] Advanced Linux Sound Architecture Driver Initialized.
10750 08:09:00.158693 <6>[ 0.646834] vgaarb: loaded
10751 08:09:00.165226 <6>[ 0.650002] clocksource: Switched to clocksource arch_sys_counter
10752 08:09:00.168499 <5>[ 0.656440] VFS: Disk quotas dquot_6.6.0
10753 08:09:00.175527 <6>[ 0.660625] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10754 08:09:00.178345 <6>[ 0.667816] pnp: PnP ACPI: disabled
10755 08:09:00.186718 <6>[ 0.674517] NET: Registered PF_INET protocol family
10756 08:09:00.196962 <6>[ 0.680113] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10757 08:09:00.208070 <6>[ 0.692442] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10758 08:09:00.218817 <6>[ 0.701258] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10759 08:09:00.225159 <6>[ 0.709227] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10760 08:09:00.231564 <6>[ 0.717927] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10761 08:09:00.243578 <6>[ 0.727687] TCP: Hash tables configured (established 65536 bind 65536)
10762 08:09:00.250481 <6>[ 0.734553] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10763 08:09:00.256765 <6>[ 0.741755] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10764 08:09:00.263920 <6>[ 0.749455] NET: Registered PF_UNIX/PF_LOCAL protocol family
10765 08:09:00.270345 <6>[ 0.755611] RPC: Registered named UNIX socket transport module.
10766 08:09:00.273335 <6>[ 0.761763] RPC: Registered udp transport module.
10767 08:09:00.279972 <6>[ 0.766696] RPC: Registered tcp transport module.
10768 08:09:00.286638 <6>[ 0.771625] RPC: Registered tcp NFSv4.1 backchannel transport module.
10769 08:09:00.290413 <6>[ 0.778292] PCI: CLS 0 bytes, default 64
10770 08:09:00.293184 <6>[ 0.782619] Unpacking initramfs...
10771 08:09:00.310226 <6>[ 0.794540] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10772 08:09:00.320377 <6>[ 0.803170] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10773 08:09:00.323257 <6>[ 0.812029] kvm [1]: IPA Size Limit: 40 bits
10774 08:09:00.330382 <6>[ 0.816557] kvm [1]: GICv3: no GICV resource entry
10775 08:09:00.333560 <6>[ 0.821580] kvm [1]: disabling GICv2 emulation
10776 08:09:00.340179 <6>[ 0.826267] kvm [1]: GIC system register CPU interface enabled
10777 08:09:00.346767 <6>[ 0.834017] kvm [1]: vgic interrupt IRQ18
10778 08:09:00.350365 <6>[ 0.838418] kvm [1]: VHE mode initialized successfully
10779 08:09:00.357301 <5>[ 0.844876] Initialise system trusted keyrings
10780 08:09:00.363757 <6>[ 0.849668] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10781 08:09:00.372368 <6>[ 0.859733] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10782 08:09:00.379029 <5>[ 0.866180] NFS: Registering the id_resolver key type
10783 08:09:00.382280 <5>[ 0.871479] Key type id_resolver registered
10784 08:09:00.388364 <5>[ 0.875893] Key type id_legacy registered
10785 08:09:00.395283 <6>[ 0.880176] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10786 08:09:00.401617 <6>[ 0.887097] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10787 08:09:00.408633 <6>[ 0.894824] 9p: Installing v9fs 9p2000 file system support
10788 08:09:00.444881 <5>[ 0.932148] Key type asymmetric registered
10789 08:09:00.447513 <5>[ 0.936479] Asymmetric key parser 'x509' registered
10790 08:09:00.457722 <6>[ 0.941640] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10791 08:09:00.460854 <6>[ 0.949258] io scheduler mq-deadline registered
10792 08:09:00.464823 <6>[ 0.954026] io scheduler kyber registered
10793 08:09:00.483727 <6>[ 0.971732] EINJ: ACPI disabled.
10794 08:09:00.517116 <4>[ 0.998134] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10795 08:09:00.527049 <4>[ 1.008763] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10796 08:09:00.542156 <6>[ 1.029797] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10797 08:09:00.549797 <6>[ 1.037759] printk: console [ttyS0] disabled
10798 08:09:00.578670 <6>[ 1.062408] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10799 08:09:00.584667 <6>[ 1.071896] printk: console [ttyS0] enabled
10800 08:09:00.588077 <6>[ 1.071896] printk: console [ttyS0] enabled
10801 08:09:00.594843 <6>[ 1.080791] printk: bootconsole [mtk8250] disabled
10802 08:09:00.597813 <6>[ 1.080791] printk: bootconsole [mtk8250] disabled
10803 08:09:00.604491 <6>[ 1.092246] SuperH (H)SCI(F) driver initialized
10804 08:09:00.608032 <6>[ 1.097561] msm_serial: driver initialized
10805 08:09:00.622232 <6>[ 1.106694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10806 08:09:00.632193 <6>[ 1.115238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10807 08:09:00.639111 <6>[ 1.123783] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10808 08:09:00.648716 <6>[ 1.132413] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10809 08:09:00.659120 <6>[ 1.141121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10810 08:09:00.665354 <6>[ 1.149834] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10811 08:09:00.675660 <6>[ 1.158374] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10812 08:09:00.682513 <6>[ 1.167178] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10813 08:09:00.692044 <6>[ 1.175723] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10814 08:09:00.703963 <6>[ 1.191782] loop: module loaded
10815 08:09:00.710734 <6>[ 1.197857] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10816 08:09:00.733968 <4>[ 1.221235] mtk-pmic-keys: Failed to locate of_node [id: -1]
10817 08:09:00.740354 <6>[ 1.228144] megasas: 07.719.03.00-rc1
10818 08:09:00.750263 <6>[ 1.237874] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10819 08:09:00.757958 <6>[ 1.245400] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10820 08:09:00.774682 <6>[ 1.261877] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10821 08:09:00.830604 <6>[ 1.311407] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10822 08:09:04.328776 <6>[ 4.817252] Freeing initrd memory: 96000K
10823 08:09:04.339294 <6>[ 4.827690] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10824 08:09:04.350385 <6>[ 4.838887] tun: Universal TUN/TAP device driver, 1.6
10825 08:09:04.353809 <6>[ 4.844980] thunder_xcv, ver 1.0
10826 08:09:04.357248 <6>[ 4.848486] thunder_bgx, ver 1.0
10827 08:09:04.360426 <6>[ 4.851983] nicpf, ver 1.0
10828 08:09:04.371001 <6>[ 4.856031] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10829 08:09:04.374433 <6>[ 4.863507] hns3: Copyright (c) 2017 Huawei Corporation.
10830 08:09:04.380886 <6>[ 4.869096] hclge is initializing
10831 08:09:04.384130 <6>[ 4.872671] e1000: Intel(R) PRO/1000 Network Driver
10832 08:09:04.390821 <6>[ 4.877801] e1000: Copyright (c) 1999-2006 Intel Corporation.
10833 08:09:04.394611 <6>[ 4.883820] e1000e: Intel(R) PRO/1000 Network Driver
10834 08:09:04.401129 <6>[ 4.889036] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10835 08:09:04.407772 <6>[ 4.895222] igb: Intel(R) Gigabit Ethernet Network Driver
10836 08:09:04.414463 <6>[ 4.900871] igb: Copyright (c) 2007-2014 Intel Corporation.
10837 08:09:04.420558 <6>[ 4.906707] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10838 08:09:04.427308 <6>[ 4.913225] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10839 08:09:04.431286 <6>[ 4.919693] sky2: driver version 1.30
10840 08:09:04.437409 <6>[ 4.924738] VFIO - User Level meta-driver version: 0.3
10841 08:09:04.444791 <6>[ 4.933057] usbcore: registered new interface driver usb-storage
10842 08:09:04.451484 <6>[ 4.939508] usbcore: registered new device driver onboard-usb-hub
10843 08:09:04.460941 <6>[ 4.948697] mt6397-rtc mt6359-rtc: registered as rtc0
10844 08:09:04.470827 <6>[ 4.954183] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T08:09:05 UTC (1695283745)
10845 08:09:04.473716 <6>[ 4.963792] i2c_dev: i2c /dev entries driver
10846 08:09:04.490788 <6>[ 4.975723] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10847 08:09:04.511601 <6>[ 4.999741] cpu cpu0: EM: created perf domain
10848 08:09:04.515364 <6>[ 5.004673] cpu cpu4: EM: created perf domain
10849 08:09:04.522102 <6>[ 5.010293] sdhci: Secure Digital Host Controller Interface driver
10850 08:09:04.528865 <6>[ 5.016722] sdhci: Copyright(c) Pierre Ossman
10851 08:09:04.535233 <6>[ 5.021679] Synopsys Designware Multimedia Card Interface Driver
10852 08:09:04.542242 <6>[ 5.028322] sdhci-pltfm: SDHCI platform and OF driver helper
10853 08:09:04.545389 <6>[ 5.028436] mmc0: CQHCI version 5.10
10854 08:09:04.552083 <6>[ 5.038757] ledtrig-cpu: registered to indicate activity on CPUs
10855 08:09:04.558851 <6>[ 5.045761] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10856 08:09:04.565708 <6>[ 5.052828] usbcore: registered new interface driver usbhid
10857 08:09:04.568951 <6>[ 5.058653] usbhid: USB HID core driver
10858 08:09:04.575435 <6>[ 5.062858] spi_master spi0: will run message pump with realtime priority
10859 08:09:04.620603 <6>[ 5.101810] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10860 08:09:04.639379 <6>[ 5.116784] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10861 08:09:04.645681 <6>[ 5.132385] cros-ec-spi spi0.0: Chrome EC device registered
10862 08:09:04.649009 <6>[ 5.138407] mmc0: Command Queue Engine enabled
10863 08:09:04.655463 <6>[ 5.143148] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10864 08:09:04.662804 <6>[ 5.150601] mmcblk0: mmc0:0001 DA4128 116 GiB
10865 08:09:04.673449 <6>[ 5.161689] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10866 08:09:04.683592 <6>[ 5.165316] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10867 08:09:04.690108 <6>[ 5.168991] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10868 08:09:04.693594 <6>[ 5.178228] NET: Registered PF_PACKET protocol family
10869 08:09:04.700366 <6>[ 5.182888] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10870 08:09:04.703642 <6>[ 5.187546] 9pnet: Installing 9P2000 support
10871 08:09:04.709889 <6>[ 5.193407] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10872 08:09:04.716453 <5>[ 5.197259] Key type dns_resolver registered
10873 08:09:04.720280 <6>[ 5.208678] registered taskstats version 1
10874 08:09:04.726393 <5>[ 5.213056] Loading compiled-in X.509 certificates
10875 08:09:04.754662 <4>[ 5.235778] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10876 08:09:04.764737 <4>[ 5.246547] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10877 08:09:04.771313 <3>[ 5.257080] debugfs: File 'uA_load' in directory '/' already present!
10878 08:09:04.777116 <3>[ 5.263782] debugfs: File 'min_uV' in directory '/' already present!
10879 08:09:04.783982 <3>[ 5.270446] debugfs: File 'max_uV' in directory '/' already present!
10880 08:09:04.790473 <3>[ 5.277065] debugfs: File 'constraint_flags' in directory '/' already present!
10881 08:09:04.802066 <3>[ 5.286827] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10882 08:09:04.813974 <6>[ 5.302019] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10883 08:09:04.821092 <6>[ 5.308759] xhci-mtk 11200000.usb: xHCI Host Controller
10884 08:09:04.827239 <6>[ 5.314252] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10885 08:09:04.837577 <6>[ 5.322100] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10886 08:09:04.843997 <6>[ 5.331523] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10887 08:09:04.850530 <6>[ 5.337594] xhci-mtk 11200000.usb: xHCI Host Controller
10888 08:09:04.856906 <6>[ 5.343075] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10889 08:09:04.863461 <6>[ 5.350730] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10890 08:09:04.870157 <6>[ 5.358402] hub 1-0:1.0: USB hub found
10891 08:09:04.873544 <6>[ 5.362417] hub 1-0:1.0: 1 port detected
10892 08:09:04.883372 <6>[ 5.366701] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10893 08:09:04.886802 <6>[ 5.375265] hub 2-0:1.0: USB hub found
10894 08:09:04.889952 <6>[ 5.379272] hub 2-0:1.0: 1 port detected
10895 08:09:04.899033 <6>[ 5.387335] mtk-msdc 11f70000.mmc: Got CD GPIO
10896 08:09:04.910126 <6>[ 5.395344] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10897 08:09:04.917031 <6>[ 5.403375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10898 08:09:04.926983 <4>[ 5.411303] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10899 08:09:04.936876 <6>[ 5.420840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10900 08:09:04.943932 <6>[ 5.428916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10901 08:09:04.949798 <6>[ 5.436938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10902 08:09:04.959916 <6>[ 5.444853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10903 08:09:04.966940 <6>[ 5.452669] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10904 08:09:04.976325 <6>[ 5.460489] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10905 08:09:04.986503 <6>[ 5.470917] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10906 08:09:04.993346 <6>[ 5.479278] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10907 08:09:05.003059 <6>[ 5.487621] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10908 08:09:05.009562 <6>[ 5.495959] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10909 08:09:05.019327 <6>[ 5.504296] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10910 08:09:05.029318 <6>[ 5.512635] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10911 08:09:05.035940 <6>[ 5.520973] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10912 08:09:05.046072 <6>[ 5.529311] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10913 08:09:05.052325 <6>[ 5.537648] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10914 08:09:05.062675 <6>[ 5.545986] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10915 08:09:05.069157 <6>[ 5.554329] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10916 08:09:05.078955 <6>[ 5.562668] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10917 08:09:05.085717 <6>[ 5.571006] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10918 08:09:05.096239 <6>[ 5.579344] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10919 08:09:05.102107 <6>[ 5.587682] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10920 08:09:05.108823 <6>[ 5.596411] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10921 08:09:05.115443 <6>[ 5.603587] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10922 08:09:05.122516 <6>[ 5.610331] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10923 08:09:05.132627 <6>[ 5.617104] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10924 08:09:05.138682 <6>[ 5.624037] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10925 08:09:05.145660 <6>[ 5.630882] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10926 08:09:05.155480 <6>[ 5.640021] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10927 08:09:05.165338 <6>[ 5.649140] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10928 08:09:05.175245 <6>[ 5.658435] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10929 08:09:05.185156 <6>[ 5.667902] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10930 08:09:05.191481 <6>[ 5.677370] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10931 08:09:05.202052 <6>[ 5.686490] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10932 08:09:05.211382 <6>[ 5.695958] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10933 08:09:05.221326 <6>[ 5.705078] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10934 08:09:05.231622 <6>[ 5.714375] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10935 08:09:05.240947 <6>[ 5.724536] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10936 08:09:05.251126 <6>[ 5.736069] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10937 08:09:05.301441 <6>[ 5.786277] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10938 08:09:05.454170 <6>[ 5.942299] hub 1-1:1.0: USB hub found
10939 08:09:05.457622 <6>[ 5.946663] hub 1-1:1.0: 4 ports detected
10940 08:09:05.581833 <6>[ 6.066576] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10941 08:09:05.607295 <6>[ 6.095546] hub 2-1:1.0: USB hub found
10942 08:09:05.610613 <6>[ 6.100008] hub 2-1:1.0: 3 ports detected
10943 08:09:05.777449 <6>[ 6.262280] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10944 08:09:05.909742 <6>[ 6.397411] hub 1-1.4:1.0: USB hub found
10945 08:09:05.912709 <6>[ 6.402053] hub 1-1.4:1.0: 2 ports detected
10946 08:09:05.989715 <6>[ 6.474532] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10947 08:09:06.208969 <6>[ 6.694320] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10948 08:09:06.401268 <6>[ 6.886302] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10949 08:09:17.538536 <6>[ 18.031298] ALSA device list:
10950 08:09:17.544911 <6>[ 18.034583] No soundcards found.
10951 08:09:17.552940 <6>[ 18.042635] Freeing unused kernel memory: 8448K
10952 08:09:17.556114 <6>[ 18.047614] Run /init as init process
10953 08:09:17.602669 <6>[ 18.092120] NET: Registered PF_INET6 protocol family
10954 08:09:17.609269 <6>[ 18.098372] Segment Routing with IPv6
10955 08:09:17.612583 <6>[ 18.102409] In-situ OAM (IOAM) with IPv6
10956 08:09:17.646874 <30>[ 18.116424] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10957 08:09:17.649846 <30>[ 18.140253] systemd[1]: Detected architecture arm64.
10958 08:09:17.653890
10959 08:09:17.656049 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10960 08:09:17.656514
10961 08:09:17.672541 <30>[ 18.162302] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10962 08:09:17.815466 <30>[ 18.301596] systemd[1]: Queued start job for default target Graphical Interface.
10963 08:09:17.869530 <30>[ 18.359185] systemd[1]: Created slice system-getty.slice.
10964 08:09:17.876307 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10965 08:09:17.894037 <30>[ 18.383008] systemd[1]: Created slice system-modprobe.slice.
10966 08:09:17.899720 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10967 08:09:17.921603 <30>[ 18.410823] systemd[1]: Created slice system-serial\x2dgetty.slice.
10968 08:09:17.931205 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10969 08:09:17.945716 <30>[ 18.435108] systemd[1]: Created slice User and Session Slice.
10970 08:09:17.951811 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10971 08:09:17.973007 <30>[ 18.459034] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10972 08:09:17.982739 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10973 08:09:18.000751 <30>[ 18.487079] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10974 08:09:18.007564 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10975 08:09:18.031493 <30>[ 18.514373] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10976 08:09:18.037885 <30>[ 18.526518] systemd[1]: Reached target Local Encrypted Volumes.
10977 08:09:18.044418 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10978 08:09:18.061500 <30>[ 18.550826] systemd[1]: Reached target Paths.
10979 08:09:18.067565 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10980 08:09:18.080898 <30>[ 18.570294] systemd[1]: Reached target Remote File Systems.
10981 08:09:18.087029 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10982 08:09:18.101002 <30>[ 18.590244] systemd[1]: Reached target Slices.
10983 08:09:18.104177 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10984 08:09:18.120699 <30>[ 18.610296] systemd[1]: Reached target Swap.
10985 08:09:18.124001 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10986 08:09:18.144263 <30>[ 18.630784] systemd[1]: Listening on initctl Compatibility Named Pipe.
10987 08:09:18.151168 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10988 08:09:18.157954 <30>[ 18.645844] systemd[1]: Listening on Journal Audit Socket.
10989 08:09:18.163972 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10990 08:09:18.177156 <30>[ 18.666752] systemd[1]: Listening on Journal Socket (/dev/log).
10991 08:09:18.183736 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10992 08:09:18.201589 <30>[ 18.691499] systemd[1]: Listening on Journal Socket.
10993 08:09:18.208727 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10994 08:09:18.221386 <30>[ 18.710838] systemd[1]: Listening on udev Control Socket.
10995 08:09:18.228023 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10996 08:09:18.245643 <30>[ 18.735295] systemd[1]: Listening on udev Kernel Socket.
10997 08:09:18.252050 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10998 08:09:18.300799 <30>[ 18.790521] systemd[1]: Mounting Huge Pages File System...
10999 08:09:18.307556 Mounting [0;1;39mHuge Pages File System[0m...
11000 08:09:18.324772 <30>[ 18.814225] systemd[1]: Mounting POSIX Message Queue File System...
11001 08:09:18.332048 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11002 08:09:18.368914 <30>[ 18.858358] systemd[1]: Mounting Kernel Debug File System...
11003 08:09:18.375347 Mounting [0;1;39mKernel Debug File System[0m...
11004 08:09:18.391847 <30>[ 18.878509] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11005 08:09:18.404969 <30>[ 18.891404] systemd[1]: Starting Create list of static device nodes for the current kernel...
11006 08:09:18.412274 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11007 08:09:18.432993 <30>[ 18.922736] systemd[1]: Starting Load Kernel Module configfs...
11008 08:09:18.439642 Starting [0;1;39mLoad Kernel Module configfs[0m...
11009 08:09:18.456227 <30>[ 18.945864] systemd[1]: Starting Load Kernel Module drm...
11010 08:09:18.462989 Starting [0;1;39mLoad Kernel Module drm[0m...
11011 08:09:18.479970 <30>[ 18.966688] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11012 08:09:18.529732 <30>[ 19.018929] systemd[1]: Starting Journal Service...
11013 08:09:18.532964 Starting [0;1;39mJournal Service[0m...
11014 08:09:18.551628 <30>[ 19.041317] systemd[1]: Starting Load Kernel Modules...
11015 08:09:18.558292 Starting [0;1;39mLoad Kernel Modules[0m...
11016 08:09:18.578786 <30>[ 19.064813] systemd[1]: Starting Remount Root and Kernel File Systems...
11017 08:09:18.584978 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11018 08:09:18.599946 <30>[ 19.089315] systemd[1]: Starting Coldplug All udev Devices...
11019 08:09:18.606132 Starting [0;1;39mColdplug All udev Devices[0m...
11020 08:09:18.626339 <30>[ 19.115152] systemd[1]: Started Journal Service.
11021 08:09:18.632139 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11022 08:09:18.648011 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11023 08:09:18.665579 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11024 08:09:18.683004 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11025 08:09:18.705668 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11026 08:09:18.722227 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11027 08:09:18.740215 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11028 08:09:18.758465 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11029 08:09:18.778536 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11030 08:09:18.793445 See 'systemctl status systemd-remount-fs.service' for details.
11031 08:09:18.831559 Mounting [0;1;39mKernel Configuration File System[0m...
11032 08:09:18.858232 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11033 08:09:18.870082 <46>[ 19.356311] systemd-journald[174]: Received client request to flush runtime journal.
11034 08:09:18.879460 Starting [0;1;39mLoad/Save Random Seed[0m...
11035 08:09:18.897971 Starting [0;1;39mApply Kernel Variables[0m...
11036 08:09:18.920778 Starting [0;1;39mCreate System Users[0m...
11037 08:09:18.941572 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11038 08:09:18.957907 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11039 08:09:18.978036 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11040 08:09:18.990580 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11041 08:09:19.006660 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11042 08:09:19.022711 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11043 08:09:19.073200 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11044 08:09:19.097731 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11045 08:09:19.113049 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11046 08:09:19.132809 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11047 08:09:19.181738 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11048 08:09:19.209707 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11049 08:09:19.230133 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11050 08:09:19.252820 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11051 08:09:19.334425 Starting [0;1;39mNetwork Time Synchronization[0m...
11052 08:09:19.354594 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11053 08:09:19.370341 <6>[ 19.857098] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11054 08:09:19.397330 <6>[ 19.886901] remoteproc remoteproc0: scp is available
11055 08:09:19.403686 <6>[ 19.892999] remoteproc remoteproc0: powering up scp
11056 08:09:19.413357 [[0;32m OK [<6>[ 19.900171] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11057 08:09:19.420215 0m] Finished [0<6>[ 19.908979] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11058 08:09:19.426822 ;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11059 08:09:19.449522 [[0;32m OK [<6>[ 19.935946] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11060 08:09:19.459352 0m] Found device<3>[ 19.936069] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11061 08:09:19.469181 <6>[ 19.946556] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11062 08:09:19.479329 [0;1;39m/dev/t<3>[ 19.954326] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11063 08:09:19.485534 <6>[ 19.962984] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11064 08:09:19.488655 tyS0[0m.
11065 08:09:19.495345 <3>[ 19.981173] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11066 08:09:19.505742 [[0;32m OK [<6>[ 19.992048] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11067 08:09:19.515808 0m] Started [0;1;39mNetwork Time Synchronizatio<4>[ 20.003062] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11068 08:09:19.518719 n[0m.
11069 08:09:19.529447 <4>[ 20.014971] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11070 08:09:19.535563 <3>[ 20.022904] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11071 08:09:19.545047 <4>[ 20.024378] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11072 08:09:19.548744 <4>[ 20.024378] Fallback method does not support PEC.
11073 08:09:19.558690 <3>[ 20.031038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 08:09:19.566146 <3>[ 20.031044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11075 08:09:19.575671 <3>[ 20.031053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11076 08:09:19.582255 <6>[ 20.041633] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11077 08:09:19.589031 <6>[ 20.041666] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11078 08:09:19.596181 <6>[ 20.041674] remoteproc remoteproc0: remote processor scp is now up
11079 08:09:19.606609 <3>[ 20.060418] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11080 08:09:19.612373 <3>[ 20.060971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11081 08:09:19.622799 <3>[ 20.090101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11082 08:09:19.625951 <6>[ 20.101271] mc: Linux media interface: v0.10
11083 08:09:19.635843 <3>[ 20.102556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11084 08:09:19.642569 <3>[ 20.105521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11085 08:09:19.649087 <3>[ 20.105548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11086 08:09:19.659113 <3>[ 20.105552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11087 08:09:19.665843 <3>[ 20.106052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11088 08:09:19.675758 <3>[ 20.106059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11089 08:09:19.681983 <3>[ 20.106062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11090 08:09:19.692008 <3>[ 20.106067] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11091 08:09:19.698777 <3>[ 20.106070] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11092 08:09:19.705912 <6>[ 20.108706] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11093 08:09:19.715532 <3>[ 20.108743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11094 08:09:19.719053 <6>[ 20.110161] usbcore: registered new interface driver r8152
11095 08:09:19.725622 <6>[ 20.137968] videodev: Linux video capture interface: v2.00
11096 08:09:19.735193 <6>[ 20.138158] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11097 08:09:19.741911 <6>[ 20.145576] pci_bus 0000:00: root bus resource [bus 00-ff]
11098 08:09:19.748420 <6>[ 20.206337] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11099 08:09:19.754915 <6>[ 20.209454] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11100 08:09:19.765689 <6>[ 20.216300] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11101 08:09:19.774927 <6>[ 20.220801] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11102 08:09:19.784714 <6>[ 20.231406] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11103 08:09:19.788303 <6>[ 20.236508] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11104 08:09:19.798505 <6>[ 20.244518] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11105 08:09:19.808496 <6>[ 20.245116] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11106 08:09:19.815487 <4>[ 20.248299] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11107 08:09:19.826305 <4>[ 20.248308] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11108 08:09:19.832694 <6>[ 20.250139] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11109 08:09:19.835938 <6>[ 20.294787] usbcore: registered new interface driver cdc_ether
11110 08:09:19.842537 <6>[ 20.302075] pci 0000:00:00.0: supports D1 D2
11111 08:09:19.853661 <3>[ 20.302674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11112 08:09:19.860302 <3>[ 20.304829] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
11113 08:09:19.863908 <6>[ 20.312041] Bluetooth: Core ver 2.22
11114 08:09:19.870070 <6>[ 20.319081] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11115 08:09:19.873701 <6>[ 20.319182] r8152 2-1.3:1.0 eth0: v1.12.13
11116 08:09:19.881017 <6>[ 20.319664] usbcore: registered new interface driver r8153_ecm
11117 08:09:19.890784 <3>[ 20.324080] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11118 08:09:19.897844 <3>[ 20.324840] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11119 08:09:19.904410 <6>[ 20.326672] NET: Registered PF_BLUETOOTH protocol family
11120 08:09:19.911127 <6>[ 20.334108] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11121 08:09:19.917511 <6>[ 20.335763] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11122 08:09:19.924065 <6>[ 20.335947] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11123 08:09:19.937751 <6>[ 20.336930] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11124 08:09:19.944638 <6>[ 20.337031] usbcore: registered new interface driver uvcvideo
11125 08:09:19.951461 <6>[ 20.337159] Bluetooth: HCI device and connection manager initialized
11126 08:09:19.954489 <6>[ 20.346181] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11127 08:09:19.964379 <3>[ 20.350200] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11128 08:09:19.972076 <6>[ 20.354199] Bluetooth: HCI socket layer initialized
11129 08:09:19.978575 <6>[ 20.358038] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11130 08:09:19.982353 <6>[ 20.364878] Bluetooth: L2CAP socket layer initialized
11131 08:09:19.988373 <6>[ 20.365313] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11132 08:09:19.995537 <6>[ 20.369234] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11133 08:09:20.005508 <3>[ 20.371733] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11134 08:09:20.012541 <6>[ 20.375318] Bluetooth: SCO socket layer initialized
11135 08:09:20.019576 <6>[ 20.384083] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11136 08:09:20.026053 <3>[ 20.394129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11137 08:09:20.032706 <6>[ 20.398253] pci 0000:01:00.0: supports D1 D2
11138 08:09:20.039982 <3>[ 20.426358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11139 08:09:20.046751 <6>[ 20.431943] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11140 08:09:20.053823 <6>[ 20.438589] usbcore: registered new interface driver btusb
11141 08:09:20.063475 <4>[ 20.439545] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11142 08:09:20.070471 <3>[ 20.439563] Bluetooth: hci0: Failed to load firmware file (-2)
11143 08:09:20.076630 <3>[ 20.439569] Bluetooth: hci0: Failed to set up firmware (-2)
11144 08:09:20.086183 <4>[ 20.439576] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11145 08:09:20.092771 <6>[ 20.442233] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11146 08:09:20.099666 <6>[ 20.442261] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11147 08:09:20.109574 <6>[ 20.442264] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11148 08:09:20.116582 <6>[ 20.442272] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11149 08:09:20.123171 <6>[ 20.442285] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11150 08:09:20.132834 <6>[ 20.442298] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11151 08:09:20.135782 <6>[ 20.442310] pci 0000:00:00.0: PCI bridge to [bus 01]
11152 08:09:20.146648 <6>[ 20.442315] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11153 08:09:20.152894 <6>[ 20.442450] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11154 08:09:20.159278 <6>[ 20.442889] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11155 08:09:20.162241 <6>[ 20.443309] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11156 08:09:20.179851 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbac<5>[ 20.664339] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11157 08:09:20.180420 klight.slice[0m.
11158 08:09:20.185838 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11159 08:09:20.200537 <5>[ 20.687016] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11160 08:09:20.210989 [[0;32m OK [<4>[ 20.694513] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11161 08:09:20.216960 0m] Reached targ<6>[ 20.704719] cfg80211: failed to load regulatory.db
11162 08:09:20.220517 et [0;1;39mSystem Time Synchronized[0m.
11163 08:09:20.269315 <6>[ 20.755826] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11164 08:09:20.276082 <6>[ 20.763358] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11165 08:09:20.289122 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11166 08:09:20.300148 <6>[ 20.790160] mt7921e 0000:01:00.0: ASIC revision: 79610010
11167 08:09:20.313910 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11168 08:09:20.402481 <4>[ 20.886198] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11169 08:09:20.475837 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11170 08:09:20.488193 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11171 08:09:20.508831 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11172 08:09:20.523977 <4>[ 21.007176] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11173 08:09:20.536926 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11174 08:09:20.553181 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11175 08:09:20.576894 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11176 08:09:20.592719 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11177 08:09:20.612242 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11178 08:09:20.636652 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11179 08:09:20.651841 <4>[ 21.134981] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11180 08:09:20.694083 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11181 08:09:20.722800 Starting [0;1;39mUser Login Management[0m...
11182 08:09:20.739637 Starting [0;1;39mPermit User Sessions[0m...
11183 08:09:20.756894 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11184 08:09:20.772303 <4>[ 21.255785] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11185 08:09:20.789218 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11186 08:09:20.814706 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11187 08:09:20.833023 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11188 08:09:20.869008 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11189 08:09:20.899689 [[0;32m OK [0m] Started [0;1;39mUser Login <4>[ 21.382850] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11190 08:09:20.903267 Management[0m.
11191 08:09:20.921875 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11192 08:09:20.939788 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11193 08:09:20.957641 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11194 08:09:21.007801 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11195 08:09:21.027016 <4>[ 21.510237] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11196 08:09:21.048961 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11197 08:09:21.096205
11198 08:09:21.096770
11199 08:09:21.100162 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11200 08:09:21.100894
11201 08:09:21.102834 debian-bullseye-arm64 login: root (automatic login)
11202 08:09:21.103300
11203 08:09:21.103697
11204 08:09:21.119157 Linux debian-bullseye-arm64 6.1.54-cip6 #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023 aarch64
11205 08:09:21.119792
11206 08:09:21.125599 The programs included with the Debian GNU/Linux system are free software;
11207 08:09:21.131961 the exact distribution terms for each program are described in the
11208 08:09:21.135282 individual files in /usr/share/doc/*/copyright.
11209 08:09:21.135896
11210 08:09:21.151856 Debian GNU/Linux comes with ABSOLUTELY NO WARRA<4>[ 21.633239] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11211 08:09:21.152443 NTY, to the extent
11212 08:09:21.154729 permitted by applicable law.
11213 08:09:21.155988 Matched prompt #10: / #
11215 08:09:21.157196 Setting prompt string to ['/ #']
11216 08:09:21.157671 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11218 08:09:21.158746 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11219 08:09:21.159231 start: 2.2.6 expect-shell-connection (timeout 00:01:38) [common]
11220 08:09:21.159653 Setting prompt string to ['/ #']
11221 08:09:21.159996 Forcing a shell prompt, looking for ['/ #']
11223 08:09:21.210853 / #
11224 08:09:21.211553 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11225 08:09:21.212119 Waiting using forced prompt support (timeout 00:02:30)
11226 08:09:21.217706
11227 08:09:21.218652 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11228 08:09:21.219190 start: 2.2.7 export-device-env (timeout 00:01:38) [common]
11229 08:09:21.219746 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11230 08:09:21.220252 end: 2.2 depthcharge-retry (duration 00:03:22) [common]
11231 08:09:21.220754 end: 2 depthcharge-action (duration 00:03:22) [common]
11232 08:09:21.221243 start: 3 lava-test-retry (timeout 00:05:00) [common]
11233 08:09:21.221724 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11234 08:09:21.222120 Using namespace: common
11236 08:09:21.323381 / # #
11237 08:09:21.324082 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11238 08:09:21.324784 <4>[ 21.758994] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11239 08:09:21.330294 #
11240 08:09:21.331189 Using /lava-11585978
11242 08:09:21.432437 / # export SHELL=/bin/sh
11243 08:09:21.433306 <4>[ 21.878956] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11244 08:09:21.439018 export SHELL=/bin/sh
11246 08:09:21.540782 / # . /lava-11585978/environment
11247 08:09:21.541560 . /lava-11585978/environment<4>[ 21.998796] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11248 08:09:21.547043
11250 08:09:21.648823 / # /lava-11585978/bin/lava-test-runner /lava-11585978/0
11251 08:09:21.649475 Test shell timeout: 10s (minimum of the action and connection timeout)
11252 08:09:21.651253 /lava-11585978/bin/lava-test-runner /lava-11585978/0<3>[ 22.116443] mt7921e 0000:01:00.0: hardware init failed
11253 08:09:21.655357
11254 08:09:21.695868 + export TESTRUN_ID=0_sleep
11255 08:09:21.696444 + cd /lava-11585978/0/tests/0_sleep
11256 08:09:21.696836 + cat uuid
11257 08:09:21.697185 + UUID=11585978_1.5.2.3.1
11258 08:09:21.697518 + set +x
11259 08:09:21.698151 <LAVA_SIGNAL_STARTRUN 0_sleep 11585978_1.5.2.3.1>
11260 08:09:21.698513 + ./config/lava/sleep/sleep.sh mem freeze
11261 08:09:21.698845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11262 08:09:21.699492 Received signal: <STARTRUN> 0_sleep 11585978_1.5.2.3.1
11263 08:09:21.699869 Starting test lava.0_sleep (11585978_1.5.2.3.1)
11264 08:09:21.700288 Skipping test definition patterns.
11265 08:09:21.700786 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11267 08:09:21.702814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11268 08:09:21.703499 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11270 08:09:21.704562 rtcwake: assuming RTC uses UTC ...
11271 08:09:21.714252 rtcwake: wakeup from "mem" using rtc0 at Thu<6>[ 22.203028] PM: suspend entry (deep)
11272 08:09:21.718012 Sep 21 08:09:28<6>[ 22.208116] Filesystems sync: 0.000 seconds
11273 08:09:21.721066 2023
11274 08:09:21.724610 <6>[ 22.216210] Freezing user space processes
11275 08:09:21.735170 <6>[ 22.222070] Freezing user space processes completed (elapsed 0.001 seconds)
11276 08:09:21.738494 <6>[ 22.229293] OOM killer disabled.
11277 08:09:21.741825 <6>[ 22.232774] Freezing remaining freezable tasks
11278 08:09:21.751995 <6>[ 22.238627] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11279 08:09:21.758571 <6>[ 22.246281] printk: Suspending console(s) (use no_console_suspend to debug)
11280 08:09:25.158107 <3>[ 25.422366] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11281 08:09:25.167101 <3>[ 25.422407] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11282 08:09:25.177811 <3>[ 25.422452] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11283 08:09:25.184725 <3>[ 25.422497] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11284 08:09:25.191144 <3>[ 25.422738] PM: Some devices failed to suspend, or early wake event detected
11285 08:09:25.201336 <4>[ 25.438780] typec port0-partner: PM: parent port0 should not be sleeping
11286 08:09:25.204117 <6>[ 25.695117] OOM killer enabled.
11287 08:09:25.207575 <6>[ 25.698531] Restarting tasks ... done.
11288 08:09:25.214046 <5>[ 25.704571] random: crng reseeded on system resumption
11289 08:09:25.219489 <6>[ 25.712950] PM: suspend exit
11290 08:09:25.222432 rtcwake: write error
11291 08:09:25.230382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11292 08:09:25.231226 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11294 08:09:25.234316 rtcwake: assuming RTC uses UTC ...
11295 08:09:25.240558 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:32 2023
11296 08:09:25.252801 <6>[ 25.743003] PM: suspend entry (deep)
11297 08:09:25.256304 <6>[ 25.746918] Filesystems sync: 0.000 seconds
11298 08:09:25.259569 <6>[ 25.751973] Freezing user space processes
11299 08:09:25.271038 <6>[ 25.757906] Freezing user space processes completed (elapsed 0.001 seconds)
11300 08:09:25.274068 <6>[ 25.765125] OOM killer disabled.
11301 08:09:25.277026 <6>[ 25.768606] Freezing remaining freezable tasks
11302 08:09:25.287268 <6>[ 25.774051] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11303 08:09:25.294228 <6>[ 25.781700] printk: Suspending console(s) (use no_console_suspend to debug)
11304 08:09:28.745813 <3>[ 29.006381] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11305 08:09:28.755290 <3>[ 29.006417] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11306 08:09:28.765251 <3>[ 29.006462] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11307 08:09:28.772162 <3>[ 29.006501] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11308 08:09:28.778501 <3>[ 29.006696] PM: Some devices failed to suspend, or early wake event detected
11309 08:09:28.785592 <6>[ 29.276271] OOM killer enabled.
11310 08:09:28.792625 <6>[ 29.279683] Restarting tasks ... done.
11311 08:09:28.796052 <5>[ 29.287414] random: crng reseeded on system resumption
11312 08:09:28.800325 <6>[ 29.294500] PM: suspend exit
11313 08:09:28.803531 rtcwake: write error
11314 08:09:28.812050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11315 08:09:28.812825 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11317 08:09:28.815221 rtcwake: assuming RTC uses UTC ...
11318 08:09:28.822532 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:35 2023
11319 08:09:28.834899 <6>[ 29.325975] PM: suspend entry (deep)
11320 08:09:28.838785 <6>[ 29.329858] Filesystems sync: 0.000 seconds
11321 08:09:28.841888 <6>[ 29.334885] Freezing user space processes
11322 08:09:28.854313 <6>[ 29.340884] Freezing user space processes completed (elapsed 0.001 seconds)
11323 08:09:28.856829 <6>[ 29.348168] OOM killer disabled.
11324 08:09:28.860131 <6>[ 29.351649] Freezing remaining freezable tasks
11325 08:09:28.870222 <6>[ 29.357740] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11326 08:09:28.876848 <6>[ 29.365413] printk: Suspending console(s) (use no_console_suspend to debug)
11327 08:09:32.324893 <3>[ 32.590336] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11328 08:09:32.334640 <3>[ 32.590377] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11329 08:09:32.345059 <3>[ 32.590431] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11330 08:09:32.351302 <3>[ 32.590477] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11331 08:09:32.358212 <3>[ 32.590871] PM: Some devices failed to suspend, or early wake event detected
11332 08:09:32.364995 <6>[ 32.856140] OOM killer enabled.
11333 08:09:32.373293 <6>[ 32.859552] Restarting tasks ... done.
11334 08:09:32.376516 <5>[ 32.868579] random: crng reseeded on system resumption
11335 08:09:32.381301 <6>[ 32.876124] PM: suspend exit
11336 08:09:32.385003 rtcwake: write error
11337 08:09:32.392497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11338 08:09:32.393359 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11340 08:09:32.395252 rtcwake: assuming RTC uses UTC ...
11341 08:09:32.402139 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:39 2023
11342 08:09:32.414698 <6>[ 32.906177] PM: suspend entry (deep)
11343 08:09:32.418593 <6>[ 32.910094] Filesystems sync: 0.000 seconds
11344 08:09:32.421447 <6>[ 32.915120] Freezing user space processes
11345 08:09:32.433358 <6>[ 32.921087] Freezing user space processes completed (elapsed 0.001 seconds)
11346 08:09:32.436413 <6>[ 32.928323] OOM killer disabled.
11347 08:09:32.439707 <6>[ 32.931803] Freezing remaining freezable tasks
11348 08:09:32.449903 <6>[ 32.937839] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11349 08:09:32.456499 <6>[ 32.945513] printk: Suspending console(s) (use no_console_suspend to debug)
11350 08:09:35.912828 <3>[ 36.174330] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11351 08:09:35.922750 <3>[ 36.174361] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11352 08:09:35.932678 <3>[ 36.174406] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11353 08:09:35.939563 <3>[ 36.174446] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11354 08:09:35.949104 <3>[ 36.174923] PM: Some devices failed to suspend, or early wake event detected
11355 08:09:35.952452 <6>[ 36.444295] OOM killer enabled.
11356 08:09:35.955807 <6>[ 36.447707] Restarting tasks ... done.
11357 08:09:35.963518 <5>[ 36.454936] random: crng reseeded on system resumption
11358 08:09:35.966576 <6>[ 36.461117] PM: suspend exit
11359 08:09:35.970115 rtcwake: write error
11360 08:09:35.976865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11361 08:09:35.977726 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11363 08:09:35.980791 rtcwake: assuming RTC uses UTC ...
11364 08:09:35.986920 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:42 2023
11365 08:09:35.999838 <6>[ 36.491103] PM: suspend entry (deep)
11366 08:09:36.002755 <6>[ 36.494990] Filesystems sync: 0.000 seconds
11367 08:09:36.006265 <6>[ 36.500037] Freezing user space processes
11368 08:09:36.017619 <6>[ 36.505920] Freezing user space processes completed (elapsed 0.001 seconds)
11369 08:09:36.020503 <6>[ 36.513141] OOM killer disabled.
11370 08:09:36.024045 <6>[ 36.516620] Freezing remaining freezable tasks
11371 08:09:36.034005 <6>[ 36.522600] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11372 08:09:36.041063 <6>[ 36.530250] printk: Suspending console(s) (use no_console_suspend to debug)
11373 08:09:39.496020 <3>[ 39.758295] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11374 08:09:39.505514 <3>[ 39.758320] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11375 08:09:39.515814 <3>[ 39.758347] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11376 08:09:39.522633 <3>[ 39.758373] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11377 08:09:39.532425 <3>[ 39.758574] PM: Some devices failed to suspend, or early wake event detected
11378 08:09:39.535950 <6>[ 40.027809] OOM killer enabled.
11379 08:09:39.539094 <6>[ 40.031221] Restarting tasks ... done.
11380 08:09:39.547005 <5>[ 40.038708] random: crng reseeded on system resumption
11381 08:09:39.550330 <6>[ 40.044947] PM: suspend exit
11382 08:09:39.553169 rtcwake: write error
11383 08:09:39.560971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11384 08:09:39.561836 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11386 08:09:39.564136 rtcwake: assuming RTC uses UTC ...
11387 08:09:39.571198 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:46 2023
11388 08:09:39.583669 <6>[ 40.075559] PM: suspend entry (deep)
11389 08:09:39.587085 <6>[ 40.079462] Filesystems sync: 0.000 seconds
11390 08:09:39.590321 <6>[ 40.084498] Freezing user space processes
11391 08:09:39.601360 <6>[ 40.090102] Freezing user space processes completed (elapsed 0.001 seconds)
11392 08:09:39.605059 <6>[ 40.097319] OOM killer disabled.
11393 08:09:39.607949 <6>[ 40.100798] Freezing remaining freezable tasks
11394 08:09:39.618111 <6>[ 40.106665] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11395 08:09:39.624323 <6>[ 40.114318] printk: Suspending console(s) (use no_console_suspend to debug)
11396 08:09:43.084222 <3>[ 43.342303] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11397 08:09:43.094391 <3>[ 43.342335] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11398 08:09:43.103576 <3>[ 43.342379] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11399 08:09:43.110800 <3>[ 43.342420] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11400 08:09:43.120378 <3>[ 43.342658] PM: Some devices failed to suspend, or early wake event detected
11401 08:09:43.123509 <6>[ 43.616396] OOM killer enabled.
11402 08:09:43.134493 <6>[ 43.619808] Restarting tasks ... done.
11403 08:09:43.137088 <5>[ 43.630508] random: crng reseeded on system resumption
11404 08:09:43.140764 <6>[ 43.636773] PM: suspend exit
11405 08:09:43.144605 rtcwake: write error
11406 08:09:43.151892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11407 08:09:43.152814 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11409 08:09:43.154879 rtcwake: assuming RTC uses UTC ...
11410 08:09:43.161387 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:49 2023
11411 08:09:43.174344 <6>[ 43.666801] PM: suspend entry (deep)
11412 08:09:43.177357 <6>[ 43.670710] Filesystems sync: 0.000 seconds
11413 08:09:43.181171 <6>[ 43.675756] Freezing user space processes
11414 08:09:43.193015 <6>[ 43.681732] Freezing user space processes completed (elapsed 0.001 seconds)
11415 08:09:43.196150 <6>[ 43.688967] OOM killer disabled.
11416 08:09:43.199729 <6>[ 43.692448] Freezing remaining freezable tasks
11417 08:09:43.208877 <6>[ 43.698030] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11418 08:09:43.215571 <6>[ 43.705679] printk: Suspending console(s) (use no_console_suspend to debug)
11419 08:09:46.658963 <3>[ 46.926300] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11420 08:09:46.672578 <3>[ 46.926329] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11421 08:09:46.679065 <3>[ 46.926365] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11422 08:09:46.685456 <3>[ 46.926401] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11423 08:09:46.695310 <3>[ 46.926638] PM: Some devices failed to suspend, or early wake event detected
11424 08:09:46.699181 <6>[ 47.192010] OOM killer enabled.
11425 08:09:46.707472 <6>[ 47.195427] Restarting tasks ... done.
11426 08:09:46.710836 <5>[ 47.204418] random: crng reseeded on system resumption
11427 08:09:46.714613 <6>[ 47.211042] PM: suspend exit
11428 08:09:46.718545 rtcwake: write error
11429 08:09:46.726364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11430 08:09:46.727217 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11432 08:09:46.729230 rtcwake: assuming RTC uses UTC ...
11433 08:09:46.736182 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:53 2023
11434 08:09:46.748949 <6>[ 47.241784] PM: suspend entry (deep)
11435 08:09:46.752073 <6>[ 47.245675] Filesystems sync: 0.000 seconds
11436 08:09:46.755488 <6>[ 47.250684] Freezing user space processes
11437 08:09:46.766922 <6>[ 47.256694] Freezing user space processes completed (elapsed 0.001 seconds)
11438 08:09:46.770878 <6>[ 47.263931] OOM killer disabled.
11439 08:09:46.773967 <6>[ 47.267416] Freezing remaining freezable tasks
11440 08:09:46.783764 <6>[ 47.273450] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11441 08:09:46.790436 <6>[ 47.281123] printk: Suspending console(s) (use no_console_suspend to debug)
11442 08:09:50.243834 <6>[ 48.206404] vpu: disabling
11443 08:09:50.247035 <6>[ 48.206550] vproc2: disabling
11444 08:09:50.250607 <6>[ 48.206606] vproc1: disabling
11445 08:09:50.253507 <6>[ 48.206660] vaud18: disabling
11446 08:09:50.257202 <6>[ 48.206908] vsram_others: disabling
11447 08:09:50.260351 <6>[ 48.207106] va09: disabling
11448 08:09:50.263616 <6>[ 48.207184] vsram_md: disabling
11449 08:09:50.266580 <6>[ 48.207312] Vgpu: disabling
11450 08:09:50.273857 <3>[ 50.510355] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11451 08:09:50.283805 <3>[ 50.510388] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11452 08:09:50.293215 <3>[ 50.510432] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11453 08:09:50.299951 <3>[ 50.510473] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11454 08:09:50.306563 <3>[ 50.510965] PM: Some devices failed to suspend, or early wake event detected
11455 08:09:50.309877 <6>[ 50.806246] OOM killer enabled.
11456 08:09:50.320429 <6>[ 50.809645] Restarting tasks ... done.
11457 08:09:50.326830 <5>[ 50.818440] random: crng reseeded on system resumption
11458 08:09:50.330505 <6>[ 50.825611] PM: suspend exit
11459 08:09:50.333297 rtcwake: write error
11460 08:09:50.340675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11461 08:09:50.341535 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11463 08:09:50.343734 rtcwake: assuming RTC uses UTC ...
11464 08:09:50.350609 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:09:57 2023
11465 08:09:50.362272 <6>[ 50.855550] PM: suspend entry (deep)
11466 08:09:50.365220 <6>[ 50.859442] Filesystems sync: 0.000 seconds
11467 08:09:50.369090 <6>[ 50.864489] Freezing user space processes
11468 08:09:50.380226 <6>[ 50.870101] Freezing user space processes completed (elapsed 0.001 seconds)
11469 08:09:50.383356 <6>[ 50.877321] OOM killer disabled.
11470 08:09:50.386922 <6>[ 50.880801] Freezing remaining freezable tasks
11471 08:09:50.396385 <6>[ 50.886671] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11472 08:09:50.403159 <6>[ 50.894320] printk: Suspending console(s) (use no_console_suspend to debug)
11473 08:09:53.834718 <3>[ 54.094328] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11474 08:09:53.844498 <3>[ 54.094358] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11475 08:09:53.854309 <3>[ 54.094399] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11476 08:09:53.860947 <3>[ 54.094437] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11477 08:09:53.867921 <3>[ 54.094663] PM: Some devices failed to suspend, or early wake event detected
11478 08:09:53.871274 <6>[ 54.368021] OOM killer enabled.
11479 08:09:53.879629 <6>[ 54.371433] Restarting tasks ... done.
11480 08:09:53.886218 <5>[ 54.378917] random: crng reseeded on system resumption
11481 08:09:53.889598 <6>[ 54.385905] PM: suspend exit
11482 08:09:53.893225 rtcwake: write error
11483 08:09:53.899739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11484 08:09:53.900597 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11486 08:09:53.903050 rtcwake: assuming RTC uses UTC ...
11487 08:09:53.909467 rtcwake: wakeup from "mem" using rtc0 at Thu Sep 21 08:10:00 2023
11488 08:09:53.922169 <6>[ 54.416039] PM: suspend entry (deep)
11489 08:09:53.925758 <6>[ 54.419937] Filesystems sync: 0.000 seconds
11490 08:09:53.928684 <6>[ 54.425017] Freezing user space processes
11491 08:09:53.940705 <6>[ 54.430853] Freezing user space processes completed (elapsed 0.001 seconds)
11492 08:09:53.943860 <6>[ 54.438072] OOM killer disabled.
11493 08:09:53.947184 <6>[ 54.441549] Freezing remaining freezable tasks
11494 08:09:53.957247 <6>[ 54.447642] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11495 08:09:53.964028 <6>[ 54.455309] printk: Suspending console(s) (use no_console_suspend to debug)
11496 08:09:57.414887 <3>[ 57.678322] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11497 08:09:57.424253 <3>[ 57.678354] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11498 08:09:57.434170 <3>[ 57.678397] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11499 08:09:57.440947 <3>[ 57.678439] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11500 08:09:57.450584 <3>[ 57.678744] PM: Some devices failed to suspend, or early wake event detected
11501 08:09:57.454450 <6>[ 57.948387] OOM killer enabled.
11502 08:09:57.457348 <6>[ 57.951799] Restarting tasks ... done.
11503 08:09:57.464674 <5>[ 57.958903] random: crng reseeded on system resumption
11504 08:09:57.468163 <6>[ 57.965090] PM: suspend exit
11505 08:09:57.471200 rtcwake: write error
11506 08:09:57.478697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11507 08:09:57.479551 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11509 08:09:57.481501 rtcwake: assuming RTC uses UTC ...
11510 08:09:57.488179 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:04 2023
11511 08:09:57.502711 <6>[ 57.996757] PM: suspend entry (s2idle)
11512 08:09:57.506546 <6>[ 58.000834] Filesystems sync: 0.000 seconds
11513 08:09:57.512356 <6>[ 58.005924] Freezing user space processes
11514 08:09:57.519479 <6>[ 58.011853] Freezing user space processes completed (elapsed 0.001 seconds)
11515 08:09:57.522520 <6>[ 58.019088] OOM killer disabled.
11516 08:09:57.529286 <6>[ 58.022571] Freezing remaining freezable tasks
11517 08:09:57.535535 <6>[ 58.028583] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11518 08:09:57.545670 <6>[ 58.036258] printk: Suspending console(s) (use no_console_suspend to debug)
11519 08:10:00.997809 <3>[ 61.262387] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11520 08:10:01.007639 <3>[ 61.262424] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11521 08:10:01.017526 <3>[ 61.262475] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11522 08:10:01.024741 <3>[ 61.262526] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11523 08:10:01.030520 <3>[ 61.262814] PM: Some devices failed to suspend, or early wake event detected
11524 08:10:01.034542 <6>[ 61.532309] OOM killer enabled.
11525 08:10:01.042578 <6>[ 61.535726] Restarting tasks ... done.
11526 08:10:01.049723 <5>[ 61.542801] random: crng reseeded on system resumption
11527 08:10:01.053078 <6>[ 61.548984] PM: suspend exit
11528 08:10:01.056346 rtcwake: write error
11529 08:10:01.062933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11530 08:10:01.063914 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11532 08:10:01.065865 rtcwake: assuming RTC uses UTC ...
11533 08:10:01.072530 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:07 2023
11534 08:10:01.084862 <6>[ 61.579033] PM: suspend entry (s2idle)
11535 08:10:01.088276 <6>[ 61.583112] Filesystems sync: 0.000 seconds
11536 08:10:01.094536 <6>[ 61.588153] Freezing user space processes
11537 08:10:01.101254 <6>[ 61.594180] Freezing user space processes completed (elapsed 0.001 seconds)
11538 08:10:01.104758 <6>[ 61.601405] OOM killer disabled.
11539 08:10:01.111437 <6>[ 61.604886] Freezing remaining freezable tasks
11540 08:10:01.118137 <6>[ 61.610802] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11541 08:10:01.127844 <6>[ 61.618451] printk: Suspending console(s) (use no_console_suspend to debug)
11542 08:10:04.581980 <3>[ 64.846332] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11543 08:10:04.591825 <3>[ 64.846372] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11544 08:10:04.601094 <3>[ 64.846424] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11545 08:10:04.608273 <3>[ 64.846478] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11546 08:10:04.617878 <3>[ 64.846901] PM: Some devices failed to suspend, or early wake event detected
11547 08:10:04.621546 <6>[ 65.116294] OOM killer enabled.
11548 08:10:04.624322 <6>[ 65.119707] Restarting tasks ... done.
11549 08:10:04.631549 <5>[ 65.126374] random: crng reseeded on system resumption
11550 08:10:04.635472 <6>[ 65.133638] PM: suspend exit
11551 08:10:04.638759 rtcwake: write error
11552 08:10:04.646187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11553 08:10:04.647048 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11555 08:10:04.649572 rtcwake: assuming RTC uses UTC ...
11556 08:10:04.656238 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:11 2023
11557 08:10:04.669227 <6>[ 65.163716] PM: suspend entry (s2idle)
11558 08:10:04.672064 <6>[ 65.167784] Filesystems sync: 0.000 seconds
11559 08:10:04.678787 <6>[ 65.172836] Freezing user space processes
11560 08:10:04.685440 <6>[ 65.178716] Freezing user space processes completed (elapsed 0.001 seconds)
11561 08:10:04.688348 <6>[ 65.185935] OOM killer disabled.
11562 08:10:04.695482 <6>[ 65.189415] Freezing remaining freezable tasks
11563 08:10:04.702071 <6>[ 65.195462] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11564 08:10:04.711649 <6>[ 65.203137] printk: Suspending console(s) (use no_console_suspend to debug)
11565 08:10:08.161354 <3>[ 68.430334] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11566 08:10:08.170910 <3>[ 68.430367] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11567 08:10:08.180997 <3>[ 68.430419] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11568 08:10:08.187912 <3>[ 68.430463] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11569 08:10:08.194310 <3>[ 68.430723] PM: Some devices failed to suspend, or early wake event detected
11570 08:10:08.198270 <6>[ 68.696328] OOM killer enabled.
11571 08:10:08.206365 <6>[ 68.699745] Restarting tasks ... done.
11572 08:10:08.212930 <5>[ 68.707129] random: crng reseeded on system resumption
11573 08:10:08.215925 <6>[ 68.713378] PM: suspend exit
11574 08:10:08.219596 rtcwake: write error
11575 08:10:08.226504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11576 08:10:08.227376 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11578 08:10:08.229292 rtcwake: assuming RTC uses UTC ...
11579 08:10:08.235671 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:15 2023
11580 08:10:08.248702 <6>[ 68.744008] PM: suspend entry (s2idle)
11581 08:10:08.252262 <6>[ 68.748077] Filesystems sync: 0.000 seconds
11582 08:10:08.259123 <6>[ 68.753136] Freezing user space processes
11583 08:10:08.265150 <6>[ 68.759050] Freezing user space processes completed (elapsed 0.001 seconds)
11584 08:10:08.268895 <6>[ 68.766277] OOM killer disabled.
11585 08:10:08.274950 <6>[ 68.769753] Freezing remaining freezable tasks
11586 08:10:08.281651 <6>[ 68.775778] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11587 08:10:08.291829 <6>[ 68.783451] printk: Suspending console(s) (use no_console_suspend to debug)
11588 08:10:11.748690 <3>[ 72.014309] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11589 08:10:11.758466 <3>[ 72.014340] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11590 08:10:11.768324 <3>[ 72.014385] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11591 08:10:11.775034 <3>[ 72.014425] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11592 08:10:11.781887 <3>[ 72.014727] PM: Some devices failed to suspend, or early wake event detected
11593 08:10:11.788283 <6>[ 72.284070] OOM killer enabled.
11594 08:10:11.791214 <6>[ 72.287482] Restarting tasks ... done.
11595 08:10:11.798999 <5>[ 72.294771] random: crng reseeded on system resumption
11596 08:10:11.802537 <6>[ 72.301606] PM: suspend exit
11597 08:10:11.805928 rtcwake: write error
11598 08:10:11.813601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11599 08:10:11.814488 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11601 08:10:11.817141 rtcwake: assuming RTC uses UTC ...
11602 08:10:11.822964 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:18 2023
11603 08:10:11.836614 <6>[ 72.331711] PM: suspend entry (s2idle)
11604 08:10:11.839493 <6>[ 72.335780] Filesystems sync: 0.000 seconds
11605 08:10:11.845721 <6>[ 72.340824] Freezing user space processes
11606 08:10:11.852183 <6>[ 72.346624] Freezing user space processes completed (elapsed 0.001 seconds)
11607 08:10:11.855857 <6>[ 72.353841] OOM killer disabled.
11608 08:10:11.862358 <6>[ 72.357321] Freezing remaining freezable tasks
11609 08:10:11.868993 <6>[ 72.363381] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11610 08:10:11.878860 <6>[ 72.371048] printk: Suspending console(s) (use no_console_suspend to debug)
11611 08:10:15.332316 <3>[ 75.598312] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11612 08:10:15.342593 <3>[ 75.598344] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11613 08:10:15.352314 <3>[ 75.598388] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11614 08:10:15.359117 <3>[ 75.598430] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11615 08:10:15.365257 <3>[ 75.598733] PM: Some devices failed to suspend, or early wake event detected
11616 08:10:15.372338 <6>[ 75.868319] OOM killer enabled.
11617 08:10:15.375267 <6>[ 75.871736] Restarting tasks ... done.
11618 08:10:15.382094 <5>[ 75.877736] random: crng reseeded on system resumption
11619 08:10:15.385630 <6>[ 75.884343] PM: suspend exit
11620 08:10:15.388429 rtcwake: write error
11621 08:10:15.396523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11622 08:10:15.397359 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11624 08:10:15.399788 rtcwake: assuming RTC uses UTC ...
11625 08:10:15.406644 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:22 2023
11626 08:10:15.418873 <6>[ 75.914970] PM: suspend entry (s2idle)
11627 08:10:15.422066 <6>[ 75.919047] Filesystems sync: 0.000 seconds
11628 08:10:15.428727 <6>[ 75.924089] Freezing user space processes
11629 08:10:15.435710 <6>[ 75.929982] Freezing user space processes completed (elapsed 0.001 seconds)
11630 08:10:15.438397 <6>[ 75.937224] OOM killer disabled.
11631 08:10:15.445123 <6>[ 75.940703] Freezing remaining freezable tasks
11632 08:10:15.452265 <6>[ 75.946610] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11633 08:10:15.461588 <6>[ 75.954267] printk: Suspending console(s) (use no_console_suspend to debug)
11634 08:10:18.916415 <3>[ 79.182305] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11635 08:10:18.926249 <3>[ 79.182336] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11636 08:10:18.936125 <3>[ 79.182380] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11637 08:10:18.942429 <3>[ 79.182422] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11638 08:10:18.949264 <3>[ 79.182726] PM: Some devices failed to suspend, or early wake event detected
11639 08:10:18.952468 <6>[ 79.452375] OOM killer enabled.
11640 08:10:18.961005 <6>[ 79.455789] Restarting tasks ... done.
11641 08:10:18.967789 <5>[ 79.463479] random: crng reseeded on system resumption
11642 08:10:18.971454 <6>[ 79.469621] PM: suspend exit
11643 08:10:18.974608 rtcwake: write error
11644 08:10:18.981242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11645 08:10:18.982107 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11647 08:10:18.984286 rtcwake: assuming RTC uses UTC ...
11648 08:10:18.990875 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:25 2023
11649 08:10:19.003003 <6>[ 79.499624] PM: suspend entry (s2idle)
11650 08:10:19.006590 <6>[ 79.503701] Filesystems sync: 0.000 seconds
11651 08:10:19.013136 <6>[ 79.508751] Freezing user space processes
11652 08:10:19.019507 <6>[ 79.514581] Freezing user space processes completed (elapsed 0.001 seconds)
11653 08:10:19.022683 <6>[ 79.521801] OOM killer disabled.
11654 08:10:19.029513 <6>[ 79.525280] Freezing remaining freezable tasks
11655 08:10:19.036332 <6>[ 79.531334] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11656 08:10:19.046353 <6>[ 79.539009] printk: Suspending console(s) (use no_console_suspend to debug)
11657 08:10:22.495292 <3>[ 82.766311] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11658 08:10:22.505221 <3>[ 82.766343] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11659 08:10:22.515131 <3>[ 82.766387] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11660 08:10:22.521886 <3>[ 82.766428] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11661 08:10:22.528277 <3>[ 82.766717] PM: Some devices failed to suspend, or early wake event detected
11662 08:10:22.535185 <6>[ 83.032197] OOM killer enabled.
11663 08:10:22.538482 <6>[ 83.035610] Restarting tasks ... done.
11664 08:10:22.545170 <5>[ 83.041508] random: crng reseeded on system resumption
11665 08:10:22.548481 <6>[ 83.048179] PM: suspend exit
11666 08:10:22.551727 rtcwake: write error
11667 08:10:22.559051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11668 08:10:22.560019 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11670 08:10:22.562851 rtcwake: assuming RTC uses UTC ...
11671 08:10:22.569204 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:29 2023
11672 08:10:22.582150 <6>[ 83.078667] PM: suspend entry (s2idle)
11673 08:10:22.585684 <6>[ 83.082747] Filesystems sync: 0.000 seconds
11674 08:10:22.591765 <6>[ 83.087822] Freezing user space processes
11675 08:10:22.598502 <6>[ 83.093818] Freezing user space processes completed (elapsed 0.001 seconds)
11676 08:10:22.601913 <6>[ 83.101060] OOM killer disabled.
11677 08:10:22.608004 <6>[ 83.104539] Freezing remaining freezable tasks
11678 08:10:22.614841 <6>[ 83.110067] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11679 08:10:22.621407 <6>[ 83.117720] printk: Suspending console(s) (use no_console_suspend to debug)
11680 08:10:26.083286 <3>[ 86.350305] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11681 08:10:26.092879 <3>[ 86.350336] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11682 08:10:26.103004 <3>[ 86.350380] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11683 08:10:26.109625 <3>[ 86.350421] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11684 08:10:26.116253 <3>[ 86.350710] PM: Some devices failed to suspend, or early wake event detected
11685 08:10:26.123354 <6>[ 86.620289] OOM killer enabled.
11686 08:10:26.126264 <6>[ 86.623701] Restarting tasks ... done.
11687 08:10:26.132687 <5>[ 86.629711] random: crng reseeded on system resumption
11688 08:10:26.136216 <6>[ 86.637051] PM: suspend exit
11689 08:10:26.139542 rtcwake: write error
11690 08:10:26.147563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11691 08:10:26.148432 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11693 08:10:26.151292 rtcwake: assuming RTC uses UTC ...
11694 08:10:26.157360 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:32 2023
11695 08:10:26.170276 <6>[ 86.667567] PM: suspend entry (s2idle)
11696 08:10:26.173568 <6>[ 86.671635] Filesystems sync: 0.000 seconds
11697 08:10:26.177308 <6>[ 86.676680] Freezing user space processes
11698 08:10:26.188363 <6>[ 86.682078] Freezing user space processes completed (elapsed 0.001 seconds)
11699 08:10:26.191519 <6>[ 86.689294] OOM killer disabled.
11700 08:10:26.194627 <6>[ 86.692772] Freezing remaining freezable tasks
11701 08:10:26.204438 <6>[ 86.698642] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11702 08:10:26.211152 <6>[ 86.706291] printk: Suspending console(s) (use no_console_suspend to debug)
11703 08:10:29.670685 <3>[ 89.934344] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11704 08:10:29.680457 <3>[ 89.934374] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11705 08:10:29.690847 <3>[ 89.934418] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11706 08:10:29.697036 <3>[ 89.934463] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11707 08:10:29.703713 <3>[ 89.934718] PM: Some devices failed to suspend, or early wake event detected
11708 08:10:29.711093 <6>[ 90.208302] OOM killer enabled.
11709 08:10:29.714215 <6>[ 90.211714] Restarting tasks ... done.
11710 08:10:29.721362 <5>[ 90.218976] random: crng reseeded on system resumption
11711 08:10:29.725015 <6>[ 90.225223] PM: suspend exit
11712 08:10:29.728345 rtcwake: write error
11713 08:10:29.735323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11714 08:10:29.736248 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11716 08:10:29.738603 rtcwake: assuming RTC uses UTC ...
11717 08:10:29.745140 rtcwake: wakeup from "freeze" using rtc0 at Thu Sep 21 08:10:36 2023
11718 08:10:29.757636 <6>[ 90.255669] PM: suspend entry (s2idle)
11719 08:10:29.761007 <6>[ 90.259739] Filesystems sync: 0.000 seconds
11720 08:10:29.767882 <6>[ 90.264768] Freezing user space processes
11721 08:10:29.774320 <6>[ 90.270085] Freezing user space processes completed (elapsed 0.001 seconds)
11722 08:10:29.777920 <6>[ 90.277301] OOM killer disabled.
11723 08:10:29.781289 <6>[ 90.280781] Freezing remaining freezable tasks
11724 08:10:29.792112 <6>[ 90.286667] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11725 08:10:29.798845 <6>[ 90.294318] printk: Suspending console(s) (use no_console_suspend to debug)
11726 08:10:33.250349 <3>[ 93.518341] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11727 08:10:33.260221 <3>[ 93.518373] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11728 08:10:33.270680 <3>[ 93.518417] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11729 08:10:33.276958 <3>[ 93.518461] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11730 08:10:33.283360 <3>[ 93.518646] PM: Some devices failed to suspend, or early wake event detected
11731 08:10:33.290082 <6>[ 93.788386] OOM killer enabled.
11732 08:10:33.293395 <6>[ 93.791805] Restarting tasks ... done.
11733 08:10:33.300776 <5>[ 93.798998] random: crng reseeded on system resumption
11734 08:10:33.304089 <6>[ 93.805672] PM: suspend exit
11735 08:10:33.307652 rtcwake: write error
11736 08:10:33.314694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11737 08:10:33.315563 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11739 08:10:33.317931 + set +x
11740 08:10:33.321273 <LAVA_SIGNAL_ENDRUN 0_sleep 11585978_1.5.2.3.1>
11741 08:10:33.321838 <LAVA_TEST_RUNNER EXIT>
11742 08:10:33.322494 Received signal: <ENDRUN> 0_sleep 11585978_1.5.2.3.1
11743 08:10:33.322951 Ending use of test pattern.
11744 08:10:33.323301 Ending test lava.0_sleep (11585978_1.5.2.3.1), duration 71.62
11746 08:10:33.324658 ok: lava_test_shell seems to have completed
11747 08:10:33.325713 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11748 08:10:33.326207 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11749 08:10:33.326680 end: 3 lava-test-retry (duration 00:01:12) [common]
11750 08:10:33.327149 start: 4 finalize (timeout 00:04:55) [common]
11751 08:10:33.327701 start: 4.1 power-off (timeout 00:00:30) [common]
11752 08:10:33.328525 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11753 08:10:33.415055 >> Command sent successfully.
11754 08:10:33.419644 Returned 0 in 0 seconds
11755 08:10:33.520608 end: 4.1 power-off (duration 00:00:00) [common]
11757 08:10:33.522172 start: 4.2 read-feedback (timeout 00:04:55) [common]
11758 08:10:33.523597 Listened to connection for namespace 'common' for up to 1s
11759 08:10:33.524476 Listened to connection for namespace 'common' for up to 1s
11760 08:10:34.523709 Finalising connection for namespace 'common'
11761 08:10:34.524432 Disconnecting from shell: Finalise
11762 08:10:34.524863 / #
11763 08:10:34.625955 end: 4.2 read-feedback (duration 00:00:01) [common]
11764 08:10:34.626666 end: 4 finalize (duration 00:00:01) [common]
11765 08:10:34.627277 Cleaning after the job
11766 08:10:34.627901 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/ramdisk
11767 08:10:34.674257 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/kernel
11768 08:10:34.703006 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/dtb
11769 08:10:34.703235 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585978/tftp-deploy-wcgepl6x/modules
11770 08:10:34.710470 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11585978
11771 08:10:34.880303 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11585978
11772 08:10:34.880483 Job finished correctly