Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 08:06:24.628928 lava-dispatcher, installed at version: 2023.06
2 08:06:24.629126 start: 0 validate
3 08:06:24.629267 Start time: 2023-09-21 08:06:24.629259+00:00 (UTC)
4 08:06:24.629398 Using caching service: 'http://localhost/cache/?uri=%s'
5 08:06:24.629541 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 08:06:24.896430 Using caching service: 'http://localhost/cache/?uri=%s'
7 08:06:24.896624 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 08:06:53.403745 Using caching service: 'http://localhost/cache/?uri=%s'
9 08:06:53.403918 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 08:06:53.669990 Using caching service: 'http://localhost/cache/?uri=%s'
11 08:06:53.670158 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:06:54.199665 Using caching service: 'http://localhost/cache/?uri=%s'
13 08:06:54.199830 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 08:06:56.202356 validate duration: 31.57
16 08:06:56.202667 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:06:56.202783 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:06:56.202888 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:06:56.203029 Not decompressing ramdisk as can be used compressed.
20 08:06:56.203125 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 08:06:56.203200 saving as /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/ramdisk/initrd.cpio.gz
22 08:06:56.203304 total size: 4665412 (4 MB)
23 08:06:56.469802 progress 0 % (0 MB)
24 08:06:56.471334 progress 5 % (0 MB)
25 08:06:56.472705 progress 10 % (0 MB)
26 08:06:56.474008 progress 15 % (0 MB)
27 08:06:56.475248 progress 20 % (0 MB)
28 08:06:56.476587 progress 25 % (1 MB)
29 08:06:56.477847 progress 30 % (1 MB)
30 08:06:56.479120 progress 35 % (1 MB)
31 08:06:56.480411 progress 40 % (1 MB)
32 08:06:56.481813 progress 45 % (2 MB)
33 08:06:56.483149 progress 50 % (2 MB)
34 08:06:56.484462 progress 55 % (2 MB)
35 08:06:56.485699 progress 60 % (2 MB)
36 08:06:56.486931 progress 65 % (2 MB)
37 08:06:56.488271 progress 70 % (3 MB)
38 08:06:56.489822 progress 75 % (3 MB)
39 08:06:56.491771 progress 80 % (3 MB)
40 08:06:56.493924 progress 85 % (3 MB)
41 08:06:56.495885 progress 90 % (4 MB)
42 08:06:56.497730 progress 95 % (4 MB)
43 08:06:56.499619 progress 100 % (4 MB)
44 08:06:56.499900 4 MB downloaded in 0.30 s (15.00 MB/s)
45 08:06:56.500137 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:06:56.500557 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:06:56.500698 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:06:56.500841 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:06:56.501044 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 08:06:56.501156 saving as /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/kernel/Image
52 08:06:56.501268 total size: 49304064 (47 MB)
53 08:06:56.501383 No compression specified
54 08:06:56.503038 progress 0 % (0 MB)
55 08:06:56.520331 progress 5 % (2 MB)
56 08:06:56.533451 progress 10 % (4 MB)
57 08:06:56.546214 progress 15 % (7 MB)
58 08:06:56.560229 progress 20 % (9 MB)
59 08:06:56.574026 progress 25 % (11 MB)
60 08:06:56.587150 progress 30 % (14 MB)
61 08:06:56.600672 progress 35 % (16 MB)
62 08:06:56.617786 progress 40 % (18 MB)
63 08:06:56.636868 progress 45 % (21 MB)
64 08:06:56.650302 progress 50 % (23 MB)
65 08:06:56.663344 progress 55 % (25 MB)
66 08:06:56.676442 progress 60 % (28 MB)
67 08:06:56.689685 progress 65 % (30 MB)
68 08:06:56.702840 progress 70 % (32 MB)
69 08:06:56.715825 progress 75 % (35 MB)
70 08:06:56.730093 progress 80 % (37 MB)
71 08:06:56.743441 progress 85 % (39 MB)
72 08:06:56.760476 progress 90 % (42 MB)
73 08:06:56.779244 progress 95 % (44 MB)
74 08:06:56.795398 progress 100 % (47 MB)
75 08:06:56.795689 47 MB downloaded in 0.29 s (159.71 MB/s)
76 08:06:56.795869 end: 1.2.1 http-download (duration 00:00:00) [common]
78 08:06:56.796153 end: 1.2 download-retry (duration 00:00:00) [common]
79 08:06:56.796281 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:06:56.796447 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:06:56.796643 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 08:06:56.796735 saving as /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/dtb/mt8192-asurada-spherion-r0.dtb
83 08:06:56.796813 total size: 47278 (0 MB)
84 08:06:56.796909 No compression specified
85 08:06:56.798041 progress 69 % (0 MB)
86 08:06:56.798341 progress 100 % (0 MB)
87 08:06:56.798529 0 MB downloaded in 0.00 s (26.32 MB/s)
88 08:06:56.798672 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:06:56.798960 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:06:56.799077 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:06:56.799191 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:06:56.799351 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 08:06:56.799420 saving as /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/nfsrootfs/full.rootfs.tar
95 08:06:56.799482 total size: 125290964 (119 MB)
96 08:06:56.799546 Using unxz to decompress xz
97 08:06:56.803784 progress 0 % (0 MB)
98 08:06:57.158408 progress 5 % (6 MB)
99 08:06:57.537891 progress 10 % (11 MB)
100 08:06:57.902281 progress 15 % (17 MB)
101 08:06:58.111245 progress 20 % (23 MB)
102 08:06:58.288038 progress 25 % (29 MB)
103 08:06:58.652977 progress 30 % (35 MB)
104 08:06:59.015132 progress 35 % (41 MB)
105 08:06:59.427870 progress 40 % (47 MB)
106 08:06:59.822835 progress 45 % (53 MB)
107 08:07:00.295036 progress 50 % (59 MB)
108 08:07:00.728243 progress 55 % (65 MB)
109 08:07:01.120972 progress 60 % (71 MB)
110 08:07:01.488066 progress 65 % (77 MB)
111 08:07:01.894565 progress 70 % (83 MB)
112 08:07:02.344022 progress 75 % (89 MB)
113 08:07:02.802809 progress 80 % (95 MB)
114 08:07:03.240974 progress 85 % (101 MB)
115 08:07:03.512575 progress 90 % (107 MB)
116 08:07:03.880053 progress 95 % (113 MB)
117 08:07:04.281229 progress 100 % (119 MB)
118 08:07:04.287120 119 MB downloaded in 7.49 s (15.96 MB/s)
119 08:07:04.287522 end: 1.4.1 http-download (duration 00:00:07) [common]
121 08:07:04.287961 end: 1.4 download-retry (duration 00:00:07) [common]
122 08:07:04.288097 start: 1.5 download-retry (timeout 00:09:52) [common]
123 08:07:04.288224 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 08:07:04.288437 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 08:07:04.288539 saving as /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/modules/modules.tar
126 08:07:04.288632 total size: 8625188 (8 MB)
127 08:07:04.288727 Using unxz to decompress xz
128 08:07:04.558083 progress 0 % (0 MB)
129 08:07:04.587457 progress 5 % (0 MB)
130 08:07:04.618045 progress 10 % (0 MB)
131 08:07:04.644811 progress 15 % (1 MB)
132 08:07:04.671491 progress 20 % (1 MB)
133 08:07:04.699425 progress 25 % (2 MB)
134 08:07:04.727105 progress 30 % (2 MB)
135 08:07:04.754907 progress 35 % (2 MB)
136 08:07:04.781008 progress 40 % (3 MB)
137 08:07:04.805866 progress 45 % (3 MB)
138 08:07:04.833426 progress 50 % (4 MB)
139 08:07:04.859441 progress 55 % (4 MB)
140 08:07:04.885024 progress 60 % (4 MB)
141 08:07:04.910632 progress 65 % (5 MB)
142 08:07:04.936480 progress 70 % (5 MB)
143 08:07:04.963495 progress 75 % (6 MB)
144 08:07:04.990776 progress 80 % (6 MB)
145 08:07:05.021547 progress 85 % (7 MB)
146 08:07:05.050002 progress 90 % (7 MB)
147 08:07:05.077426 progress 95 % (7 MB)
148 08:07:05.103209 progress 100 % (8 MB)
149 08:07:05.110076 8 MB downloaded in 0.82 s (10.01 MB/s)
150 08:07:05.110409 end: 1.5.1 http-download (duration 00:00:01) [common]
152 08:07:05.110683 end: 1.5 download-retry (duration 00:00:01) [common]
153 08:07:05.110780 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 08:07:05.110882 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 08:07:07.561734 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq
156 08:07:07.561953 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 08:07:07.562062 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 08:07:07.562260 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v
159 08:07:07.562402 makedir: /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin
160 08:07:07.562511 makedir: /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/tests
161 08:07:07.562617 makedir: /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/results
162 08:07:07.562724 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-add-keys
163 08:07:07.562884 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-add-sources
164 08:07:07.563021 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-background-process-start
165 08:07:07.563159 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-background-process-stop
166 08:07:07.563296 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-common-functions
167 08:07:07.563439 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-echo-ipv4
168 08:07:07.563618 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-install-packages
169 08:07:07.563773 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-installed-packages
170 08:07:07.563905 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-os-build
171 08:07:07.564041 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-probe-channel
172 08:07:07.564170 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-probe-ip
173 08:07:07.564303 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-target-ip
174 08:07:07.564432 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-target-mac
175 08:07:07.564568 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-target-storage
176 08:07:07.564700 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-case
177 08:07:07.564839 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-event
178 08:07:07.564972 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-feedback
179 08:07:07.565104 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-raise
180 08:07:07.565236 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-reference
181 08:07:07.565367 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-runner
182 08:07:07.565527 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-set
183 08:07:07.565661 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-test-shell
184 08:07:07.565797 Updating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-install-packages (oe)
185 08:07:07.565963 Updating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/bin/lava-installed-packages (oe)
186 08:07:07.566099 Creating /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/environment
187 08:07:07.566202 LAVA metadata
188 08:07:07.566282 - LAVA_JOB_ID=11585998
189 08:07:07.566349 - LAVA_DISPATCHER_IP=192.168.201.1
190 08:07:07.566469 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 08:07:07.566545 skipped lava-vland-overlay
192 08:07:07.566626 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 08:07:07.566710 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 08:07:07.566777 skipped lava-multinode-overlay
195 08:07:07.566852 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 08:07:07.566932 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 08:07:07.567016 Loading test definitions
198 08:07:07.567112 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 08:07:07.567188 Using /lava-11585998 at stage 0
200 08:07:07.567523 uuid=11585998_1.6.2.3.1 testdef=None
201 08:07:07.567619 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 08:07:07.567875 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 08:07:07.568431 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 08:07:07.568668 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 08:07:07.569345 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 08:07:07.569598 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 08:07:07.570302 runner path: /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/0/tests/0_dmesg test_uuid 11585998_1.6.2.3.1
210 08:07:07.570474 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 08:07:07.570719 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 08:07:07.570799 Using /lava-11585998 at stage 1
214 08:07:07.571129 uuid=11585998_1.6.2.3.5 testdef=None
215 08:07:07.571226 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 08:07:07.571314 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 08:07:07.571833 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 08:07:07.572098 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 08:07:07.572835 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 08:07:07.573078 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 08:07:07.573806 runner path: /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/1/tests/1_bootrr test_uuid 11585998_1.6.2.3.5
224 08:07:07.573979 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 08:07:07.574193 Creating lava-test-runner.conf files
227 08:07:07.574261 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/0 for stage 0
228 08:07:07.574357 - 0_dmesg
229 08:07:07.574441 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11585998/lava-overlay-zrzun77v/lava-11585998/1 for stage 1
230 08:07:07.574540 - 1_bootrr
231 08:07:07.574640 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 08:07:07.574731 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 08:07:07.582789 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 08:07:07.582952 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 08:07:07.583050 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 08:07:07.583141 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 08:07:07.583231 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 08:07:07.711999 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 08:07:07.712459 start: 1.6.4 extract-modules (timeout 00:09:48) [common]
240 08:07:07.712623 extracting modules file /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq
241 08:07:07.954448 extracting modules file /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11585998/extract-overlay-ramdisk-pkq67cuo/ramdisk
242 08:07:08.215946 end: 1.6.4 extract-modules (duration 00:00:01) [common]
243 08:07:08.216131 start: 1.6.5 apply-overlay-tftp (timeout 00:09:48) [common]
244 08:07:08.216238 [common] Applying overlay to NFS
245 08:07:08.216315 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585998/compress-overlay-_jwgeszq/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq
246 08:07:08.225288 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 08:07:08.225463 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
248 08:07:08.225566 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 08:07:08.225658 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
250 08:07:08.225740 Building ramdisk /var/lib/lava/dispatcher/tmp/11585998/extract-overlay-ramdisk-pkq67cuo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11585998/extract-overlay-ramdisk-pkq67cuo/ramdisk
251 08:07:08.579793 >> 119350 blocks
252 08:07:10.694091 rename /var/lib/lava/dispatcher/tmp/11585998/extract-overlay-ramdisk-pkq67cuo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/ramdisk/ramdisk.cpio.gz
253 08:07:10.694593 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 08:07:10.694728 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
255 08:07:10.694833 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
256 08:07:10.694945 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/kernel/Image'
257 08:07:24.477017 Returned 0 in 13 seconds
258 08:07:24.577690 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/kernel/image.itb
259 08:07:24.953012 output: FIT description: Kernel Image image with one or more FDT blobs
260 08:07:24.953419 output: Created: Thu Sep 21 09:07:24 2023
261 08:07:24.953509 output: Image 0 (kernel-1)
262 08:07:24.953579 output: Description:
263 08:07:24.953652 output: Created: Thu Sep 21 09:07:24 2023
264 08:07:24.953715 output: Type: Kernel Image
265 08:07:24.953777 output: Compression: lzma compressed
266 08:07:24.953843 output: Data Size: 11045265 Bytes = 10786.39 KiB = 10.53 MiB
267 08:07:24.953905 output: Architecture: AArch64
268 08:07:24.953963 output: OS: Linux
269 08:07:24.954028 output: Load Address: 0x00000000
270 08:07:24.954083 output: Entry Point: 0x00000000
271 08:07:24.954137 output: Hash algo: crc32
272 08:07:24.954193 output: Hash value: 886bc8a0
273 08:07:24.954250 output: Image 1 (fdt-1)
274 08:07:24.954303 output: Description: mt8192-asurada-spherion-r0
275 08:07:24.954357 output: Created: Thu Sep 21 09:07:24 2023
276 08:07:24.954418 output: Type: Flat Device Tree
277 08:07:24.954474 output: Compression: uncompressed
278 08:07:24.954527 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 08:07:24.954580 output: Architecture: AArch64
280 08:07:24.954639 output: Hash algo: crc32
281 08:07:24.954694 output: Hash value: cc4352de
282 08:07:24.954770 output: Image 2 (ramdisk-1)
283 08:07:24.954872 output: Description: unavailable
284 08:07:24.954974 output: Created: Thu Sep 21 09:07:24 2023
285 08:07:24.955078 output: Type: RAMDisk Image
286 08:07:24.955183 output: Compression: Unknown Compression
287 08:07:24.955296 output: Data Size: 17787594 Bytes = 17370.70 KiB = 16.96 MiB
288 08:07:24.955405 output: Architecture: AArch64
289 08:07:24.955508 output: OS: Linux
290 08:07:24.955614 output: Load Address: unavailable
291 08:07:24.955730 output: Entry Point: unavailable
292 08:07:24.955837 output: Hash algo: crc32
293 08:07:24.955940 output: Hash value: f6d6503f
294 08:07:24.956045 output: Default Configuration: 'conf-1'
295 08:07:24.956150 output: Configuration 0 (conf-1)
296 08:07:24.956256 output: Description: mt8192-asurada-spherion-r0
297 08:07:24.956359 output: Kernel: kernel-1
298 08:07:24.956465 output: Init Ramdisk: ramdisk-1
299 08:07:24.956568 output: FDT: fdt-1
300 08:07:24.956673 output: Loadables: kernel-1
301 08:07:24.956775 output:
302 08:07:24.957089 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 08:07:24.957255 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 08:07:24.957431 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
305 08:07:24.957596 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
306 08:07:24.957742 No LXC device requested
307 08:07:24.957886 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 08:07:24.958040 start: 1.8 deploy-device-env (timeout 00:09:31) [common]
309 08:07:24.958190 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 08:07:24.958317 Checking files for TFTP limit of 4294967296 bytes.
311 08:07:24.959150 end: 1 tftp-deploy (duration 00:00:29) [common]
312 08:07:24.959309 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 08:07:24.959467 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 08:07:24.959674 substitutions:
315 08:07:24.959791 - {DTB}: 11585998/tftp-deploy-rtj41f8m/dtb/mt8192-asurada-spherion-r0.dtb
316 08:07:24.959915 - {INITRD}: 11585998/tftp-deploy-rtj41f8m/ramdisk/ramdisk.cpio.gz
317 08:07:24.960025 - {KERNEL}: 11585998/tftp-deploy-rtj41f8m/kernel/Image
318 08:07:24.960138 - {LAVA_MAC}: None
319 08:07:24.960250 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq
320 08:07:24.960360 - {NFS_SERVER_IP}: 192.168.201.1
321 08:07:24.960467 - {PRESEED_CONFIG}: None
322 08:07:24.960576 - {PRESEED_LOCAL}: None
323 08:07:24.960680 - {RAMDISK}: 11585998/tftp-deploy-rtj41f8m/ramdisk/ramdisk.cpio.gz
324 08:07:24.960794 - {ROOT_PART}: None
325 08:07:24.960905 - {ROOT}: None
326 08:07:24.961017 - {SERVER_IP}: 192.168.201.1
327 08:07:24.961127 - {TEE}: None
328 08:07:24.961236 Parsed boot commands:
329 08:07:24.961341 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 08:07:24.961623 Parsed boot commands: tftpboot 192.168.201.1 11585998/tftp-deploy-rtj41f8m/kernel/image.itb 11585998/tftp-deploy-rtj41f8m/kernel/cmdline
331 08:07:24.961778 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 08:07:24.961929 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 08:07:24.962094 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 08:07:24.962246 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 08:07:24.962373 Not connected, no need to disconnect.
336 08:07:24.962510 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 08:07:24.962657 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 08:07:24.962779 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
339 08:07:24.967809 Setting prompt string to ['lava-test: # ']
340 08:07:24.968218 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 08:07:24.968369 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 08:07:24.968501 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 08:07:24.968629 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 08:07:24.968976 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
345 08:07:30.100514 >> Command sent successfully.
346 08:07:30.104402 Returned 0 in 5 seconds
347 08:07:30.204874 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 08:07:30.205427 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 08:07:30.205613 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 08:07:30.205756 Setting prompt string to 'Starting depthcharge on Spherion...'
352 08:07:30.205880 Changing prompt to 'Starting depthcharge on Spherion...'
353 08:07:30.206007 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 08:07:30.206434 [Enter `^Ec?' for help]
355 08:07:30.377056
356 08:07:30.377267
357 08:07:30.377395 F0: 102B 0000
358 08:07:30.377513
359 08:07:30.377626 F3: 1001 0000 [0200]
360 08:07:30.377741
361 08:07:30.380061 F3: 1001 0000
362 08:07:30.380190
363 08:07:30.380309 F7: 102D 0000
364 08:07:30.380423
365 08:07:30.383501 F1: 0000 0000
366 08:07:30.383630
367 08:07:30.383758 V0: 0000 0000 [0001]
368 08:07:30.383876
369 08:07:30.387124 00: 0007 8000
370 08:07:30.387257
371 08:07:30.387373 01: 0000 0000
372 08:07:30.387486
373 08:07:30.390269 BP: 0C00 0209 [0000]
374 08:07:30.390395
375 08:07:30.390508 G0: 1182 0000
376 08:07:30.390622
377 08:07:30.394339 EC: 0000 0021 [4000]
378 08:07:30.394458
379 08:07:30.394573 S7: 0000 0000 [0000]
380 08:07:30.394689
381 08:07:30.397404 CC: 0000 0000 [0001]
382 08:07:30.397528
383 08:07:30.397641 T0: 0000 0040 [010F]
384 08:07:30.397747
385 08:07:30.397856 Jump to BL
386 08:07:30.397978
387 08:07:30.424060
388 08:07:30.424246
389 08:07:30.424360
390 08:07:30.431290 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 08:07:30.434964 ARM64: Exception handlers installed.
392 08:07:30.438736 ARM64: Testing exception
393 08:07:30.442400 ARM64: Done test exception
394 08:07:30.449108 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 08:07:30.459353 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 08:07:30.465681 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 08:07:30.475881 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 08:07:30.482514 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 08:07:30.489051 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 08:07:30.500598 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 08:07:30.507217 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 08:07:30.526361 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 08:07:30.530118 WDT: Last reset was cold boot
404 08:07:30.533277 SPI1(PAD0) initialized at 2873684 Hz
405 08:07:30.536640 SPI5(PAD0) initialized at 992727 Hz
406 08:07:30.540225 VBOOT: Loading verstage.
407 08:07:30.546831 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 08:07:30.549953 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 08:07:30.553446 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 08:07:30.556424 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 08:07:30.563946 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 08:07:30.570673 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 08:07:30.582022 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 08:07:30.582151
415 08:07:30.582250
416 08:07:30.592394 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 08:07:30.596043 ARM64: Exception handlers installed.
418 08:07:30.598832 ARM64: Testing exception
419 08:07:30.598941 ARM64: Done test exception
420 08:07:30.605550 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 08:07:30.609129 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 08:07:30.622679 Probing TPM: . done!
423 08:07:30.622841 TPM ready after 0 ms
424 08:07:30.630011 Connected to device vid:did:rid of 1ae0:0028:00
425 08:07:30.636687 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 08:07:30.697572 Initialized TPM device CR50 revision 0
427 08:07:30.709089 tlcl_send_startup: Startup return code is 0
428 08:07:30.709183 TPM: setup succeeded
429 08:07:30.721096 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 08:07:30.729701 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 08:07:30.741984 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 08:07:30.752131 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 08:07:30.755611 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 08:07:30.759362 in-header: 03 07 00 00 08 00 00 00
435 08:07:30.763457 in-data: aa e4 47 04 13 02 00 00
436 08:07:30.767141 Chrome EC: UHEPI supported
437 08:07:30.773643 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 08:07:30.777756 in-header: 03 95 00 00 08 00 00 00
439 08:07:30.781040 in-data: 18 20 20 08 00 00 00 00
440 08:07:30.781164 Phase 1
441 08:07:30.785025 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 08:07:30.792672 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 08:07:30.796542 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 08:07:30.799848 Recovery requested (1009000e)
445 08:07:30.808119 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 08:07:30.813272 tlcl_extend: response is 0
447 08:07:30.822967 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 08:07:30.828141 tlcl_extend: response is 0
449 08:07:30.835294 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 08:07:30.855356 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 08:07:30.861831 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 08:07:30.861980
453 08:07:30.862089
454 08:07:30.871874 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 08:07:30.874967 ARM64: Exception handlers installed.
456 08:07:30.878598 ARM64: Testing exception
457 08:07:30.878718 ARM64: Done test exception
458 08:07:30.900635 pmic_efuse_setting: Set efuses in 11 msecs
459 08:07:30.904187 pmwrap_interface_init: Select PMIF_VLD_RDY
460 08:07:30.910624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 08:07:30.913933 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 08:07:30.921318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 08:07:30.925131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 08:07:30.928817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 08:07:30.936185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 08:07:30.939819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 08:07:30.943417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 08:07:30.946784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 08:07:30.954591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 08:07:30.958361 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 08:07:30.962089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 08:07:30.965387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 08:07:30.972892 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 08:07:30.980139 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 08:07:30.983822 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 08:07:30.991538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 08:07:30.995624 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 08:07:31.003018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 08:07:31.006749 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 08:07:31.013760 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 08:07:31.017988 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 08:07:31.025061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 08:07:31.028399 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 08:07:31.035797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 08:07:31.039866 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 08:07:31.046887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 08:07:31.050834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 08:07:31.054557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 08:07:31.057984 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 08:07:31.065058 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 08:07:31.069260 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 08:07:31.076309 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 08:07:31.080011 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 08:07:31.083774 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 08:07:31.090949 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 08:07:31.095252 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 08:07:31.098792 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 08:07:31.106396 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 08:07:31.110276 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 08:07:31.113506 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 08:07:31.117214 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 08:07:31.120902 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 08:07:31.125021 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 08:07:31.132301 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 08:07:31.136306 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 08:07:31.139661 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 08:07:31.143453 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 08:07:31.147356 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 08:07:31.151114 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 08:07:31.155132 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 08:07:31.162433 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 08:07:31.173501 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 08:07:31.176830 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 08:07:31.184777 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 08:07:31.191661 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 08:07:31.198871 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 08:07:31.203165 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 08:07:31.206119 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 08:07:31.214313 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x27
520 08:07:31.217784 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 08:07:31.226104 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 08:07:31.229116 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 08:07:31.239019 [RTC]rtc_get_frequency_meter,154: input=15, output=757
524 08:07:31.247961 [RTC]rtc_get_frequency_meter,154: input=23, output=942
525 08:07:31.257245 [RTC]rtc_get_frequency_meter,154: input=19, output=848
526 08:07:31.266628 [RTC]rtc_get_frequency_meter,154: input=17, output=804
527 08:07:31.276253 [RTC]rtc_get_frequency_meter,154: input=16, output=783
528 08:07:31.285960 [RTC]rtc_get_frequency_meter,154: input=16, output=781
529 08:07:31.295521 [RTC]rtc_get_frequency_meter,154: input=17, output=803
530 08:07:31.298580 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 08:07:31.306853 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
532 08:07:31.309936 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 08:07:31.313629 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 08:07:31.317758 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 08:07:31.321183 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 08:07:31.325237 ADC[4]: Raw value=906203 ID=7
537 08:07:31.325349 ADC[3]: Raw value=213810 ID=1
538 08:07:31.328914 RAM Code: 0x71
539 08:07:31.332584 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 08:07:31.339863 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 08:07:31.347277 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 08:07:31.354405 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 08:07:31.354522 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 08:07:31.360235 in-header: 03 07 00 00 08 00 00 00
545 08:07:31.364576 in-data: aa e4 47 04 13 02 00 00
546 08:07:31.367791 Chrome EC: UHEPI supported
547 08:07:31.371647 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 08:07:31.376348 in-header: 03 95 00 00 08 00 00 00
549 08:07:31.379551 in-data: 18 20 20 08 00 00 00 00
550 08:07:31.383717 MRC: failed to locate region type 0.
551 08:07:31.391007 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 08:07:31.394637 DRAM-K: Running full calibration
553 08:07:31.398419 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 08:07:31.402325 header.status = 0x0
555 08:07:31.406146 header.version = 0x6 (expected: 0x6)
556 08:07:31.406255 header.size = 0xd00 (expected: 0xd00)
557 08:07:31.409607 header.flags = 0x0
558 08:07:31.416919 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 08:07:31.434075 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 08:07:31.441171 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 08:07:31.444640 dram_init: ddr_geometry: 2
562 08:07:31.444728 [EMI] MDL number = 2
563 08:07:31.448921 [EMI] Get MDL freq = 0
564 08:07:31.449042 dram_init: ddr_type: 0
565 08:07:31.452535 is_discrete_lpddr4: 1
566 08:07:31.456055 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 08:07:31.456166
568 08:07:31.456267
569 08:07:31.456360 [Bian_co] ETT version 0.0.0.1
570 08:07:31.463383 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 08:07:31.463499
572 08:07:31.467629 dramc_set_vcore_voltage set vcore to 650000
573 08:07:31.467730 Read voltage for 800, 4
574 08:07:31.471203 Vio18 = 0
575 08:07:31.471323 Vcore = 650000
576 08:07:31.471437 Vdram = 0
577 08:07:31.471550 Vddq = 0
578 08:07:31.474659 Vmddr = 0
579 08:07:31.474784 dram_init: config_dvfs: 1
580 08:07:31.481950 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 08:07:31.486102 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 08:07:31.489712 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
583 08:07:31.493316 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
584 08:07:31.496973 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
585 08:07:31.500555 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
586 08:07:31.504161 MEM_TYPE=3, freq_sel=18
587 08:07:31.507898 sv_algorithm_assistance_LP4_1600
588 08:07:31.510949 ============ PULL DRAM RESETB DOWN ============
589 08:07:31.514507 ========== PULL DRAM RESETB DOWN end =========
590 08:07:31.517992 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 08:07:31.521959 ===================================
592 08:07:31.525543 LPDDR4 DRAM CONFIGURATION
593 08:07:31.530009 ===================================
594 08:07:31.530122 EX_ROW_EN[0] = 0x0
595 08:07:31.533283 EX_ROW_EN[1] = 0x0
596 08:07:31.533392 LP4Y_EN = 0x0
597 08:07:31.537042 WORK_FSP = 0x0
598 08:07:31.537156 WL = 0x2
599 08:07:31.540542 RL = 0x2
600 08:07:31.540647 BL = 0x2
601 08:07:31.543809 RPST = 0x0
602 08:07:31.543919 RD_PRE = 0x0
603 08:07:31.547310 WR_PRE = 0x1
604 08:07:31.547418 WR_PST = 0x0
605 08:07:31.551011 DBI_WR = 0x0
606 08:07:31.551094 DBI_RD = 0x0
607 08:07:31.553941 OTF = 0x1
608 08:07:31.557582 ===================================
609 08:07:31.560437 ===================================
610 08:07:31.560551 ANA top config
611 08:07:31.564080 ===================================
612 08:07:31.567158 DLL_ASYNC_EN = 0
613 08:07:31.570972 ALL_SLAVE_EN = 1
614 08:07:31.571052 NEW_RANK_MODE = 1
615 08:07:31.573972 DLL_IDLE_MODE = 1
616 08:07:31.577737 LP45_APHY_COMB_EN = 1
617 08:07:31.581287 TX_ODT_DIS = 1
618 08:07:31.581368 NEW_8X_MODE = 1
619 08:07:31.584637 ===================================
620 08:07:31.587948 ===================================
621 08:07:31.591126 data_rate = 1600
622 08:07:31.594300 CKR = 1
623 08:07:31.597718 DQ_P2S_RATIO = 8
624 08:07:31.601274 ===================================
625 08:07:31.604256 CA_P2S_RATIO = 8
626 08:07:31.604366 DQ_CA_OPEN = 0
627 08:07:31.608003 DQ_SEMI_OPEN = 0
628 08:07:31.611086 CA_SEMI_OPEN = 0
629 08:07:31.614601 CA_FULL_RATE = 0
630 08:07:31.617969 DQ_CKDIV4_EN = 1
631 08:07:31.621281 CA_CKDIV4_EN = 1
632 08:07:31.621364 CA_PREDIV_EN = 0
633 08:07:31.624704 PH8_DLY = 0
634 08:07:31.627883 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 08:07:31.631400 DQ_AAMCK_DIV = 4
636 08:07:31.634397 CA_AAMCK_DIV = 4
637 08:07:31.638027 CA_ADMCK_DIV = 4
638 08:07:31.638107 DQ_TRACK_CA_EN = 0
639 08:07:31.641470 CA_PICK = 800
640 08:07:31.645240 CA_MCKIO = 800
641 08:07:31.648811 MCKIO_SEMI = 0
642 08:07:31.652145 PLL_FREQ = 3068
643 08:07:31.652230 DQ_UI_PI_RATIO = 32
644 08:07:31.656666 CA_UI_PI_RATIO = 0
645 08:07:31.660129 ===================================
646 08:07:31.663478 ===================================
647 08:07:31.667752 memory_type:LPDDR4
648 08:07:31.667834 GP_NUM : 10
649 08:07:31.671328 SRAM_EN : 1
650 08:07:31.671414 MD32_EN : 0
651 08:07:31.674847 ===================================
652 08:07:31.678842 [ANA_INIT] >>>>>>>>>>>>>>
653 08:07:31.678960 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 08:07:31.681924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 08:07:31.685596 ===================================
656 08:07:31.688653 data_rate = 1600,PCW = 0X7600
657 08:07:31.692238 ===================================
658 08:07:31.695666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 08:07:31.702098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 08:07:31.708690 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 08:07:31.712439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 08:07:31.715382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 08:07:31.719007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 08:07:31.722094 [ANA_INIT] flow start
665 08:07:31.722172 [ANA_INIT] PLL >>>>>>>>
666 08:07:31.725471 [ANA_INIT] PLL <<<<<<<<
667 08:07:31.728995 [ANA_INIT] MIDPI >>>>>>>>
668 08:07:31.729102 [ANA_INIT] MIDPI <<<<<<<<
669 08:07:31.732024 [ANA_INIT] DLL >>>>>>>>
670 08:07:31.735846 [ANA_INIT] flow end
671 08:07:31.738841 ============ LP4 DIFF to SE enter ============
672 08:07:31.742337 ============ LP4 DIFF to SE exit ============
673 08:07:31.745759 [ANA_INIT] <<<<<<<<<<<<<
674 08:07:31.748768 [Flow] Enable top DCM control >>>>>
675 08:07:31.752366 [Flow] Enable top DCM control <<<<<
676 08:07:31.755378 Enable DLL master slave shuffle
677 08:07:31.758868 ==============================================================
678 08:07:31.762041 Gating Mode config
679 08:07:31.769112 ==============================================================
680 08:07:31.769199 Config description:
681 08:07:31.779216 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 08:07:31.785779 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 08:07:31.789057 SELPH_MODE 0: By rank 1: By Phase
684 08:07:31.795553 ==============================================================
685 08:07:31.798997 GAT_TRACK_EN = 1
686 08:07:31.802583 RX_GATING_MODE = 2
687 08:07:31.805579 RX_GATING_TRACK_MODE = 2
688 08:07:31.809214 SELPH_MODE = 1
689 08:07:31.812498 PICG_EARLY_EN = 1
690 08:07:31.812630 VALID_LAT_VALUE = 1
691 08:07:31.819481 ==============================================================
692 08:07:31.822543 Enter into Gating configuration >>>>
693 08:07:31.825649 Exit from Gating configuration <<<<
694 08:07:31.829246 Enter into DVFS_PRE_config >>>>>
695 08:07:31.839385 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 08:07:31.842396 Exit from DVFS_PRE_config <<<<<
697 08:07:31.845988 Enter into PICG configuration >>>>
698 08:07:31.849499 Exit from PICG configuration <<<<
699 08:07:31.852429 [RX_INPUT] configuration >>>>>
700 08:07:31.856060 [RX_INPUT] configuration <<<<<
701 08:07:31.859094 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 08:07:31.866196 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 08:07:31.872545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 08:07:31.879612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 08:07:31.882420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 08:07:31.889249 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 08:07:31.892784 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 08:07:31.899284 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 08:07:31.902713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 08:07:31.906007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 08:07:31.909675 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 08:07:31.915844 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 08:07:31.919521 ===================================
714 08:07:31.919650 LPDDR4 DRAM CONFIGURATION
715 08:07:31.922849 ===================================
716 08:07:31.926156 EX_ROW_EN[0] = 0x0
717 08:07:31.929325 EX_ROW_EN[1] = 0x0
718 08:07:31.929450 LP4Y_EN = 0x0
719 08:07:31.932687 WORK_FSP = 0x0
720 08:07:31.932773 WL = 0x2
721 08:07:31.936212 RL = 0x2
722 08:07:31.936305 BL = 0x2
723 08:07:31.939566 RPST = 0x0
724 08:07:31.939659 RD_PRE = 0x0
725 08:07:31.942588 WR_PRE = 0x1
726 08:07:31.942688 WR_PST = 0x0
727 08:07:31.946201 DBI_WR = 0x0
728 08:07:31.946286 DBI_RD = 0x0
729 08:07:31.949277 OTF = 0x1
730 08:07:31.952966 ===================================
731 08:07:31.956482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 08:07:31.959401 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 08:07:31.966093 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 08:07:31.969756 ===================================
735 08:07:31.969877 LPDDR4 DRAM CONFIGURATION
736 08:07:31.972871 ===================================
737 08:07:31.976166 EX_ROW_EN[0] = 0x10
738 08:07:31.976252 EX_ROW_EN[1] = 0x0
739 08:07:31.979738 LP4Y_EN = 0x0
740 08:07:31.979820 WORK_FSP = 0x0
741 08:07:31.982863 WL = 0x2
742 08:07:31.986642 RL = 0x2
743 08:07:31.986788 BL = 0x2
744 08:07:31.989489 RPST = 0x0
745 08:07:31.989624 RD_PRE = 0x0
746 08:07:31.993026 WR_PRE = 0x1
747 08:07:31.993166 WR_PST = 0x0
748 08:07:31.996093 DBI_WR = 0x0
749 08:07:31.996234 DBI_RD = 0x0
750 08:07:31.999976 OTF = 0x1
751 08:07:32.002911 ===================================
752 08:07:32.005911 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 08:07:32.012008 nWR fixed to 40
754 08:07:32.015406 [ModeRegInit_LP4] CH0 RK0
755 08:07:32.015493 [ModeRegInit_LP4] CH0 RK1
756 08:07:32.018704 [ModeRegInit_LP4] CH1 RK0
757 08:07:32.021934 [ModeRegInit_LP4] CH1 RK1
758 08:07:32.022017 match AC timing 13
759 08:07:32.028587 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 08:07:32.032133 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 08:07:32.035249 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 08:07:32.041923 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 08:07:32.045407 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 08:07:32.045496 [EMI DOE] emi_dcm 0
765 08:07:32.051925 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 08:07:32.052025 ==
767 08:07:32.055518 Dram Type= 6, Freq= 0, CH_0, rank 0
768 08:07:32.058433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 08:07:32.058518 ==
770 08:07:32.065443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 08:07:32.068474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 08:07:32.079257 [CA 0] Center 36 (6~67) winsize 62
773 08:07:32.082220 [CA 1] Center 36 (6~67) winsize 62
774 08:07:32.086055 [CA 2] Center 34 (4~65) winsize 62
775 08:07:32.089097 [CA 3] Center 34 (4~64) winsize 61
776 08:07:32.092288 [CA 4] Center 33 (2~64) winsize 63
777 08:07:32.095873 [CA 5] Center 32 (2~62) winsize 61
778 08:07:32.095959
779 08:07:32.099238 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 08:07:32.099351
781 08:07:32.102873 [CATrainingPosCal] consider 1 rank data
782 08:07:32.105703 u2DelayCellTimex100 = 270/100 ps
783 08:07:32.109416 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
784 08:07:32.112907 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
785 08:07:32.115882 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
786 08:07:32.122711 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
787 08:07:32.126224 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
788 08:07:32.129491 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
789 08:07:32.129576
790 08:07:32.132800 CA PerBit enable=1, Macro0, CA PI delay=32
791 08:07:32.132936
792 08:07:32.136482 [CBTSetCACLKResult] CA Dly = 32
793 08:07:32.136618 CS Dly: 4 (0~35)
794 08:07:32.136751 ==
795 08:07:32.139835 Dram Type= 6, Freq= 0, CH_0, rank 1
796 08:07:32.146284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 08:07:32.146401 ==
798 08:07:32.149456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 08:07:32.156124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 08:07:32.165553 [CA 0] Center 36 (6~67) winsize 62
801 08:07:32.169099 [CA 1] Center 36 (6~67) winsize 62
802 08:07:32.172055 [CA 2] Center 34 (4~65) winsize 62
803 08:07:32.175766 [CA 3] Center 34 (3~65) winsize 63
804 08:07:32.178818 [CA 4] Center 33 (3~63) winsize 61
805 08:07:32.182424 [CA 5] Center 32 (2~63) winsize 62
806 08:07:32.182543
807 08:07:32.185364 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 08:07:32.185463
809 08:07:32.189077 [CATrainingPosCal] consider 2 rank data
810 08:07:32.192136 u2DelayCellTimex100 = 270/100 ps
811 08:07:32.195491 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
812 08:07:32.198780 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
813 08:07:32.205406 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
814 08:07:32.208909 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
815 08:07:32.212558 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
816 08:07:32.215414 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
817 08:07:32.215531
818 08:07:32.219047 CA PerBit enable=1, Macro0, CA PI delay=32
819 08:07:32.219136
820 08:07:32.222131 [CBTSetCACLKResult] CA Dly = 32
821 08:07:32.222213 CS Dly: 4 (0~36)
822 08:07:32.222284
823 08:07:32.225913 ----->DramcWriteLeveling(PI) begin...
824 08:07:32.226016 ==
825 08:07:32.230130 Dram Type= 6, Freq= 0, CH_0, rank 0
826 08:07:32.233880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 08:07:32.233971 ==
828 08:07:32.237382 Write leveling (Byte 0): 34 => 34
829 08:07:32.240876 Write leveling (Byte 1): 33 => 33
830 08:07:32.244135 DramcWriteLeveling(PI) end<-----
831 08:07:32.244297
832 08:07:32.244410 ==
833 08:07:32.247619 Dram Type= 6, Freq= 0, CH_0, rank 0
834 08:07:32.251893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 08:07:32.252057 ==
836 08:07:32.255628 [Gating] SW mode calibration
837 08:07:32.262159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 08:07:32.265736 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 08:07:32.272245 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 08:07:32.275942 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 08:07:32.279211 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
842 08:07:32.285764 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 08:07:32.288863 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 08:07:32.292519 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 08:07:32.299259 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 08:07:32.302281 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 08:07:32.305751 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 08:07:32.312584 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 08:07:32.315527 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 08:07:32.319135 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 08:07:32.325835 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 08:07:32.328860 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 08:07:32.332514 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 08:07:32.335625 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 08:07:32.342411 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 08:07:32.345920 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 08:07:32.349027 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
858 08:07:32.355747 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
859 08:07:32.358920 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 08:07:32.362565 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 08:07:32.369440 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 08:07:32.372594 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 08:07:32.376145 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 08:07:32.382538 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 08:07:32.385703 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
866 08:07:32.389269 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
867 08:07:32.396266 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 08:07:32.399236 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 08:07:32.403091 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 08:07:32.405885 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 08:07:32.412883 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 08:07:32.415897 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
873 08:07:32.419682 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
874 08:07:32.426279 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 08:07:32.429286 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 08:07:32.432970 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 08:07:32.439487 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 08:07:32.443260 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 08:07:32.446294 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 08:07:32.452935 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 08:07:32.456003 0 11 8 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
882 08:07:32.459670 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
883 08:07:32.466376 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 08:07:32.469499 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 08:07:32.473132 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 08:07:32.476056 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 08:07:32.483301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 08:07:32.486283 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 08:07:32.489730 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
890 08:07:32.496411 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 08:07:32.499620 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 08:07:32.503166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 08:07:32.509516 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 08:07:32.512841 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 08:07:32.516409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 08:07:32.522812 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 08:07:32.526146 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 08:07:32.529808 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 08:07:32.536391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 08:07:32.540324 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 08:07:32.543083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 08:07:32.549570 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 08:07:32.553156 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 08:07:32.556796 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 08:07:32.559912 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
906 08:07:32.563034 Total UI for P1: 0, mck2ui 16
907 08:07:32.566702 best dqsien dly found for B0: ( 0, 14, 4)
908 08:07:32.573356 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
909 08:07:32.573435 Total UI for P1: 0, mck2ui 16
910 08:07:32.576938 best dqsien dly found for B1: ( 0, 14, 8)
911 08:07:32.580531 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
912 08:07:32.587216 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 08:07:32.587330
914 08:07:32.591084 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
915 08:07:32.594138 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 08:07:32.597428 [Gating] SW calibration Done
917 08:07:32.597530 ==
918 08:07:32.600550 Dram Type= 6, Freq= 0, CH_0, rank 0
919 08:07:32.603911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 08:07:32.604057 ==
921 08:07:32.604177 RX Vref Scan: 0
922 08:07:32.604298
923 08:07:32.607619 RX Vref 0 -> 0, step: 1
924 08:07:32.607750
925 08:07:32.610616 RX Delay -130 -> 252, step: 16
926 08:07:32.614050 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
927 08:07:32.617551 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
928 08:07:32.623965 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
929 08:07:32.627593 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
930 08:07:32.630804 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
931 08:07:32.634526 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
932 08:07:32.637478 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
933 08:07:32.640942 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
934 08:07:32.647314 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
935 08:07:32.651044 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
936 08:07:32.654680 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
937 08:07:32.657712 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
938 08:07:32.661352 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
939 08:07:32.667472 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
940 08:07:32.671129 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
941 08:07:32.674859 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
942 08:07:32.674966 ==
943 08:07:32.678092 Dram Type= 6, Freq= 0, CH_0, rank 0
944 08:07:32.680983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 08:07:32.681085 ==
946 08:07:32.684747 DQS Delay:
947 08:07:32.684859 DQS0 = 0, DQS1 = 0
948 08:07:32.687557 DQM Delay:
949 08:07:32.687671 DQM0 = 90, DQM1 = 85
950 08:07:32.687779 DQ Delay:
951 08:07:32.691227 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
952 08:07:32.694333 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
953 08:07:32.697928 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
954 08:07:32.701076 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
955 08:07:32.701180
956 08:07:32.701286
957 08:07:32.704644 ==
958 08:07:32.708031 Dram Type= 6, Freq= 0, CH_0, rank 0
959 08:07:32.711282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 08:07:32.711388 ==
961 08:07:32.711492
962 08:07:32.711587
963 08:07:32.714427 TX Vref Scan disable
964 08:07:32.714540 == TX Byte 0 ==
965 08:07:32.717888 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
966 08:07:32.724457 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
967 08:07:32.724572 == TX Byte 1 ==
968 08:07:32.727867 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
969 08:07:32.734442 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
970 08:07:32.734528 ==
971 08:07:32.737557 Dram Type= 6, Freq= 0, CH_0, rank 0
972 08:07:32.741071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 08:07:32.741178 ==
974 08:07:32.754542 TX Vref=22, minBit 9, minWin=27, winSum=447
975 08:07:32.757638 TX Vref=24, minBit 8, minWin=27, winSum=447
976 08:07:32.760643 TX Vref=26, minBit 10, minWin=27, winSum=451
977 08:07:32.764068 TX Vref=28, minBit 12, minWin=27, winSum=455
978 08:07:32.767305 TX Vref=30, minBit 15, minWin=27, winSum=455
979 08:07:32.774349 TX Vref=32, minBit 11, minWin=27, winSum=451
980 08:07:32.777283 [TxChooseVref] Worse bit 12, Min win 27, Win sum 455, Final Vref 28
981 08:07:32.777392
982 08:07:32.780872 Final TX Range 1 Vref 28
983 08:07:32.780978
984 08:07:32.781073 ==
985 08:07:32.784022 Dram Type= 6, Freq= 0, CH_0, rank 0
986 08:07:32.787785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 08:07:32.790791 ==
988 08:07:32.790895
989 08:07:32.790989
990 08:07:32.791081 TX Vref Scan disable
991 08:07:32.794347 == TX Byte 0 ==
992 08:07:32.798151 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
993 08:07:32.800922 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
994 08:07:32.804460 == TX Byte 1 ==
995 08:07:32.807625 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
996 08:07:32.811322 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
997 08:07:32.814295
998 08:07:32.814398 [DATLAT]
999 08:07:32.814498 Freq=800, CH0 RK0
1000 08:07:32.814591
1001 08:07:32.818032 DATLAT Default: 0xa
1002 08:07:32.818145 0, 0xFFFF, sum = 0
1003 08:07:32.821585 1, 0xFFFF, sum = 0
1004 08:07:32.821696 2, 0xFFFF, sum = 0
1005 08:07:32.824452 3, 0xFFFF, sum = 0
1006 08:07:32.824569 4, 0xFFFF, sum = 0
1007 08:07:32.827774 5, 0xFFFF, sum = 0
1008 08:07:32.827885 6, 0xFFFF, sum = 0
1009 08:07:32.831081 7, 0xFFFF, sum = 0
1010 08:07:32.831190 8, 0xFFFF, sum = 0
1011 08:07:32.834676 9, 0x0, sum = 1
1012 08:07:32.834764 10, 0x0, sum = 2
1013 08:07:32.837870 11, 0x0, sum = 3
1014 08:07:32.837983 12, 0x0, sum = 4
1015 08:07:32.841435 best_step = 10
1016 08:07:32.841540
1017 08:07:32.841624 ==
1018 08:07:32.844897 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 08:07:32.847774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 08:07:32.847862 ==
1021 08:07:32.851492 RX Vref Scan: 1
1022 08:07:32.851606
1023 08:07:32.851713 Set Vref Range= 32 -> 127
1024 08:07:32.851809
1025 08:07:32.854505 RX Vref 32 -> 127, step: 1
1026 08:07:32.854611
1027 08:07:32.858208 RX Delay -95 -> 252, step: 8
1028 08:07:32.858311
1029 08:07:32.861596 Set Vref, RX VrefLevel [Byte0]: 32
1030 08:07:32.864658 [Byte1]: 32
1031 08:07:32.864775
1032 08:07:32.868158 Set Vref, RX VrefLevel [Byte0]: 33
1033 08:07:32.871161 [Byte1]: 33
1034 08:07:32.874658
1035 08:07:32.874755 Set Vref, RX VrefLevel [Byte0]: 34
1036 08:07:32.878161 [Byte1]: 34
1037 08:07:32.882370
1038 08:07:32.885815 Set Vref, RX VrefLevel [Byte0]: 35
1039 08:07:32.885893 [Byte1]: 35
1040 08:07:32.890499
1041 08:07:32.890607 Set Vref, RX VrefLevel [Byte0]: 36
1042 08:07:32.893916 [Byte1]: 36
1043 08:07:32.898247
1044 08:07:32.898359 Set Vref, RX VrefLevel [Byte0]: 37
1045 08:07:32.901884 [Byte1]: 37
1046 08:07:32.905733
1047 08:07:32.905840 Set Vref, RX VrefLevel [Byte0]: 38
1048 08:07:32.908709 [Byte1]: 38
1049 08:07:32.913163
1050 08:07:32.913265 Set Vref, RX VrefLevel [Byte0]: 39
1051 08:07:32.916519 [Byte1]: 39
1052 08:07:32.920963
1053 08:07:32.921076 Set Vref, RX VrefLevel [Byte0]: 40
1054 08:07:32.923914 [Byte1]: 40
1055 08:07:32.928105
1056 08:07:32.928183 Set Vref, RX VrefLevel [Byte0]: 41
1057 08:07:32.931175 [Byte1]: 41
1058 08:07:32.935444
1059 08:07:32.935553 Set Vref, RX VrefLevel [Byte0]: 42
1060 08:07:32.938963 [Byte1]: 42
1061 08:07:32.943162
1062 08:07:32.943265 Set Vref, RX VrefLevel [Byte0]: 43
1063 08:07:32.946327 [Byte1]: 43
1064 08:07:32.950533
1065 08:07:32.950648 Set Vref, RX VrefLevel [Byte0]: 44
1066 08:07:32.953920 [Byte1]: 44
1067 08:07:32.958485
1068 08:07:32.958589 Set Vref, RX VrefLevel [Byte0]: 45
1069 08:07:32.961979 [Byte1]: 45
1070 08:07:32.966005
1071 08:07:32.966096 Set Vref, RX VrefLevel [Byte0]: 46
1072 08:07:32.969004 [Byte1]: 46
1073 08:07:32.973348
1074 08:07:32.973436 Set Vref, RX VrefLevel [Byte0]: 47
1075 08:07:32.977186 [Byte1]: 47
1076 08:07:32.981223
1077 08:07:32.981300 Set Vref, RX VrefLevel [Byte0]: 48
1078 08:07:32.984874 [Byte1]: 48
1079 08:07:32.988624
1080 08:07:32.988732 Set Vref, RX VrefLevel [Byte0]: 49
1081 08:07:32.992213 [Byte1]: 49
1082 08:07:32.996613
1083 08:07:32.996696 Set Vref, RX VrefLevel [Byte0]: 50
1084 08:07:32.999748 [Byte1]: 50
1085 08:07:33.004117
1086 08:07:33.004197 Set Vref, RX VrefLevel [Byte0]: 51
1087 08:07:33.007023 [Byte1]: 51
1088 08:07:33.011443
1089 08:07:33.011549 Set Vref, RX VrefLevel [Byte0]: 52
1090 08:07:33.017960 [Byte1]: 52
1091 08:07:33.018067
1092 08:07:33.021542 Set Vref, RX VrefLevel [Byte0]: 53
1093 08:07:33.024594 [Byte1]: 53
1094 08:07:33.024699
1095 08:07:33.028291 Set Vref, RX VrefLevel [Byte0]: 54
1096 08:07:33.031781 [Byte1]: 54
1097 08:07:33.031893
1098 08:07:33.034710 Set Vref, RX VrefLevel [Byte0]: 55
1099 08:07:33.038345 [Byte1]: 55
1100 08:07:33.041981
1101 08:07:33.042057 Set Vref, RX VrefLevel [Byte0]: 56
1102 08:07:33.045447 [Byte1]: 56
1103 08:07:33.049618
1104 08:07:33.049697 Set Vref, RX VrefLevel [Byte0]: 57
1105 08:07:33.053144 [Byte1]: 57
1106 08:07:33.057045
1107 08:07:33.057131 Set Vref, RX VrefLevel [Byte0]: 58
1108 08:07:33.060618 [Byte1]: 58
1109 08:07:33.064659
1110 08:07:33.064743 Set Vref, RX VrefLevel [Byte0]: 59
1111 08:07:33.067991 [Byte1]: 59
1112 08:07:33.072629
1113 08:07:33.072705 Set Vref, RX VrefLevel [Byte0]: 60
1114 08:07:33.075540 [Byte1]: 60
1115 08:07:33.079902
1116 08:07:33.079984 Set Vref, RX VrefLevel [Byte0]: 61
1117 08:07:33.083587 [Byte1]: 61
1118 08:07:33.087875
1119 08:07:33.087954 Set Vref, RX VrefLevel [Byte0]: 62
1120 08:07:33.090930 [Byte1]: 62
1121 08:07:33.095125
1122 08:07:33.095215 Set Vref, RX VrefLevel [Byte0]: 63
1123 08:07:33.098643 [Byte1]: 63
1124 08:07:33.102901
1125 08:07:33.102984 Set Vref, RX VrefLevel [Byte0]: 64
1126 08:07:33.105868 [Byte1]: 64
1127 08:07:33.110413
1128 08:07:33.110495 Set Vref, RX VrefLevel [Byte0]: 65
1129 08:07:33.117107 [Byte1]: 65
1130 08:07:33.117190
1131 08:07:33.119995 Set Vref, RX VrefLevel [Byte0]: 66
1132 08:07:33.123533 [Byte1]: 66
1133 08:07:33.123647
1134 08:07:33.126745 Set Vref, RX VrefLevel [Byte0]: 67
1135 08:07:33.130136 [Byte1]: 67
1136 08:07:33.130241
1137 08:07:33.133765 Set Vref, RX VrefLevel [Byte0]: 68
1138 08:07:33.137079 [Byte1]: 68
1139 08:07:33.140774
1140 08:07:33.140885 Set Vref, RX VrefLevel [Byte0]: 69
1141 08:07:33.144415 [Byte1]: 69
1142 08:07:33.148786
1143 08:07:33.148884 Set Vref, RX VrefLevel [Byte0]: 70
1144 08:07:33.151512 [Byte1]: 70
1145 08:07:33.156243
1146 08:07:33.156327 Set Vref, RX VrefLevel [Byte0]: 71
1147 08:07:33.159372 [Byte1]: 71
1148 08:07:33.163731
1149 08:07:33.163815 Set Vref, RX VrefLevel [Byte0]: 72
1150 08:07:33.166690 [Byte1]: 72
1151 08:07:33.171263
1152 08:07:33.171349 Set Vref, RX VrefLevel [Byte0]: 73
1153 08:07:33.174420 [Byte1]: 73
1154 08:07:33.178533
1155 08:07:33.178643 Set Vref, RX VrefLevel [Byte0]: 74
1156 08:07:33.182462 [Byte1]: 74
1157 08:07:33.186650
1158 08:07:33.186760 Set Vref, RX VrefLevel [Byte0]: 75
1159 08:07:33.189513 [Byte1]: 75
1160 08:07:33.194246
1161 08:07:33.194330 Set Vref, RX VrefLevel [Byte0]: 76
1162 08:07:33.197395 [Byte1]: 76
1163 08:07:33.201489
1164 08:07:33.201578 Set Vref, RX VrefLevel [Byte0]: 77
1165 08:07:33.205092 [Byte1]: 77
1166 08:07:33.209114
1167 08:07:33.209196 Set Vref, RX VrefLevel [Byte0]: 78
1168 08:07:33.212713 [Byte1]: 78
1169 08:07:33.216981
1170 08:07:33.217077 Final RX Vref Byte 0 = 55 to rank0
1171 08:07:33.220371 Final RX Vref Byte 1 = 56 to rank0
1172 08:07:33.223726 Final RX Vref Byte 0 = 55 to rank1
1173 08:07:33.226990 Final RX Vref Byte 1 = 56 to rank1==
1174 08:07:33.229982 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 08:07:33.236959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 08:07:33.237050 ==
1177 08:07:33.237164 DQS Delay:
1178 08:07:33.237254 DQS0 = 0, DQS1 = 0
1179 08:07:33.240268 DQM Delay:
1180 08:07:33.240347 DQM0 = 91, DQM1 = 84
1181 08:07:33.243181 DQ Delay:
1182 08:07:33.246806 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1183 08:07:33.249763 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1184 08:07:33.253545 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1185 08:07:33.256882 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1186 08:07:33.256970
1187 08:07:33.257054
1188 08:07:33.263541 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1189 08:07:33.266532 CH0 RK0: MR19=606, MR18=4C42
1190 08:07:33.273194 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1191 08:07:33.273281
1192 08:07:33.277027 ----->DramcWriteLeveling(PI) begin...
1193 08:07:33.277107 ==
1194 08:07:33.280355 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 08:07:33.283205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 08:07:33.283285 ==
1197 08:07:33.286605 Write leveling (Byte 0): 34 => 34
1198 08:07:33.290062 Write leveling (Byte 1): 33 => 33
1199 08:07:33.293295 DramcWriteLeveling(PI) end<-----
1200 08:07:33.293406
1201 08:07:33.293514 ==
1202 08:07:33.296629 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 08:07:33.340544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 08:07:33.340646 ==
1205 08:07:33.340740 [Gating] SW mode calibration
1206 08:07:33.341038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 08:07:33.341148 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 08:07:33.341250 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1209 08:07:33.341420 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1210 08:07:33.341562 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1211 08:07:33.341699 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 08:07:33.341799 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 08:07:33.341900 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 08:07:33.384661 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 08:07:33.385295 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 08:07:33.385562 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 08:07:33.385686 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 08:07:33.385797 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 08:07:33.385914 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 08:07:33.386021 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 08:07:33.386119 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 08:07:33.386546 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 08:07:33.386643 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 08:07:33.397109 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 08:07:33.397721 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1226 08:07:33.400067 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1227 08:07:33.403758 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 08:07:33.407111 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 08:07:33.413854 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 08:07:33.417310 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 08:07:33.420651 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 08:07:33.427175 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 08:07:33.430314 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 08:07:33.433846 0 9 8 | B1->B0 | 2c2c 2b2b | 1 0 | (1 1) (0 0)
1235 08:07:33.440256 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 08:07:33.443878 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 08:07:33.447432 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 08:07:33.450378 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 08:07:33.457140 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 08:07:33.460563 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 08:07:33.464024 0 10 4 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
1242 08:07:33.471134 0 10 8 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
1243 08:07:33.474848 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 08:07:33.479100 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 08:07:33.482640 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 08:07:33.485990 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 08:07:33.492546 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 08:07:33.496289 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 08:07:33.500210 0 11 4 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
1250 08:07:33.503376 0 11 8 | B1->B0 | 3c3c 3939 | 1 0 | (0 0) (0 0)
1251 08:07:33.509886 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 08:07:33.513407 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 08:07:33.517014 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 08:07:33.523417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 08:07:33.526641 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 08:07:33.529927 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 08:07:33.536518 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 08:07:33.540013 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1259 08:07:33.543755 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 08:07:33.550222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 08:07:33.553215 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 08:07:33.556567 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 08:07:33.563093 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 08:07:33.566803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 08:07:33.569748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 08:07:33.576594 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 08:07:33.579923 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 08:07:33.583543 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 08:07:33.586953 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 08:07:33.593341 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 08:07:33.596748 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 08:07:33.600423 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 08:07:33.607188 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 08:07:33.610604 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1275 08:07:33.613824 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1276 08:07:33.616666 Total UI for P1: 0, mck2ui 16
1277 08:07:33.620270 best dqsien dly found for B0: ( 0, 14, 8)
1278 08:07:33.626798 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 08:07:33.626903 Total UI for P1: 0, mck2ui 16
1280 08:07:33.633267 best dqsien dly found for B1: ( 0, 14, 10)
1281 08:07:33.636726 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1282 08:07:33.640095 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1283 08:07:33.640190
1284 08:07:33.643421 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1285 08:07:33.647508 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1286 08:07:33.650169 [Gating] SW calibration Done
1287 08:07:33.650275 ==
1288 08:07:33.653799 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 08:07:33.656831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 08:07:33.656909 ==
1291 08:07:33.660085 RX Vref Scan: 0
1292 08:07:33.660172
1293 08:07:33.660238 RX Vref 0 -> 0, step: 1
1294 08:07:33.660298
1295 08:07:33.663460 RX Delay -130 -> 252, step: 16
1296 08:07:33.667112 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1297 08:07:33.673696 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1298 08:07:33.677241 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1299 08:07:33.680130 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1300 08:07:33.683578 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1301 08:07:33.687055 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1302 08:07:33.690382 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1303 08:07:33.697342 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1304 08:07:33.700202 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1305 08:07:33.704114 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1306 08:07:33.707250 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1307 08:07:33.710593 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1308 08:07:33.717388 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1309 08:07:33.720646 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1310 08:07:33.723504 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1311 08:07:33.727180 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1312 08:07:33.727286 ==
1313 08:07:33.730335 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 08:07:33.737254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 08:07:33.737363 ==
1316 08:07:33.737481 DQS Delay:
1317 08:07:33.740383 DQS0 = 0, DQS1 = 0
1318 08:07:33.740496 DQM Delay:
1319 08:07:33.743794 DQM0 = 91, DQM1 = 82
1320 08:07:33.743870 DQ Delay:
1321 08:07:33.747074 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1322 08:07:33.750563 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1323 08:07:33.753912 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1324 08:07:33.756954 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1325 08:07:33.757050
1326 08:07:33.757128
1327 08:07:33.757251 ==
1328 08:07:33.760376 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 08:07:33.763993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 08:07:33.764087 ==
1331 08:07:33.764185
1332 08:07:33.764277
1333 08:07:33.767178 TX Vref Scan disable
1334 08:07:33.770667 == TX Byte 0 ==
1335 08:07:33.773389 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1336 08:07:33.776971 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1337 08:07:33.780623 == TX Byte 1 ==
1338 08:07:33.784111 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1339 08:07:33.786774 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1340 08:07:33.786873 ==
1341 08:07:33.790294 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 08:07:33.793674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 08:07:33.793772 ==
1344 08:07:33.807840 TX Vref=22, minBit 10, minWin=27, winSum=447
1345 08:07:33.811569 TX Vref=24, minBit 13, minWin=27, winSum=452
1346 08:07:33.814932 TX Vref=26, minBit 11, minWin=27, winSum=451
1347 08:07:33.818101 TX Vref=28, minBit 4, minWin=28, winSum=457
1348 08:07:33.821626 TX Vref=30, minBit 6, minWin=28, winSum=458
1349 08:07:33.828377 TX Vref=32, minBit 4, minWin=28, winSum=454
1350 08:07:33.831284 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 30
1351 08:07:33.831431
1352 08:07:33.835024 Final TX Range 1 Vref 30
1353 08:07:33.835123
1354 08:07:33.835186 ==
1355 08:07:33.838102 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 08:07:33.841461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 08:07:33.841541 ==
1358 08:07:33.841618
1359 08:07:33.845005
1360 08:07:33.845088 TX Vref Scan disable
1361 08:07:33.848145 == TX Byte 0 ==
1362 08:07:33.851624 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1363 08:07:33.854593 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1364 08:07:33.858045 == TX Byte 1 ==
1365 08:07:33.861590 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1366 08:07:33.864579 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1367 08:07:33.868225
1368 08:07:33.868311 [DATLAT]
1369 08:07:33.868382 Freq=800, CH0 RK1
1370 08:07:33.868443
1371 08:07:33.871394 DATLAT Default: 0xa
1372 08:07:33.871467 0, 0xFFFF, sum = 0
1373 08:07:33.874476 1, 0xFFFF, sum = 0
1374 08:07:33.874551 2, 0xFFFF, sum = 0
1375 08:07:33.877888 3, 0xFFFF, sum = 0
1376 08:07:33.877967 4, 0xFFFF, sum = 0
1377 08:07:33.881577 5, 0xFFFF, sum = 0
1378 08:07:33.884606 6, 0xFFFF, sum = 0
1379 08:07:33.884719 7, 0xFFFF, sum = 0
1380 08:07:33.888283 8, 0xFFFF, sum = 0
1381 08:07:33.888368 9, 0x0, sum = 1
1382 08:07:33.888435 10, 0x0, sum = 2
1383 08:07:33.891799 11, 0x0, sum = 3
1384 08:07:33.891876 12, 0x0, sum = 4
1385 08:07:33.895124 best_step = 10
1386 08:07:33.895246
1387 08:07:33.895338 ==
1388 08:07:33.898298 Dram Type= 6, Freq= 0, CH_0, rank 1
1389 08:07:33.901525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 08:07:33.901636 ==
1391 08:07:33.905080 RX Vref Scan: 0
1392 08:07:33.905194
1393 08:07:33.905287 RX Vref 0 -> 0, step: 1
1394 08:07:33.905381
1395 08:07:33.908174 RX Delay -79 -> 252, step: 8
1396 08:07:33.914996 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1397 08:07:33.918689 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1398 08:07:33.921418 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1399 08:07:33.925132 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1400 08:07:33.928403 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1401 08:07:33.934717 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1402 08:07:33.938219 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1403 08:07:33.941774 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1404 08:07:33.945163 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1405 08:07:33.948169 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1406 08:07:33.955212 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1407 08:07:33.958129 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1408 08:07:33.961556 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1409 08:07:33.964959 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1410 08:07:33.968429 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1411 08:07:33.974971 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1412 08:07:33.975093 ==
1413 08:07:33.978354 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 08:07:33.981574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 08:07:33.981695 ==
1416 08:07:33.981806 DQS Delay:
1417 08:07:33.985220 DQS0 = 0, DQS1 = 0
1418 08:07:33.985344 DQM Delay:
1419 08:07:33.988521 DQM0 = 94, DQM1 = 83
1420 08:07:33.988644 DQ Delay:
1421 08:07:33.991657 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1422 08:07:33.995019 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1423 08:07:33.998609 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1424 08:07:34.001637 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1425 08:07:34.001760
1426 08:07:34.001876
1427 08:07:34.008415 [DQSOSCAuto] RK1, (LSB)MR18= 0x4414, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1428 08:07:34.011683 CH0 RK1: MR19=606, MR18=4414
1429 08:07:34.018757 CH0_RK1: MR19=0x606, MR18=0x4414, DQSOSC=392, MR23=63, INC=96, DEC=64
1430 08:07:34.021835 [RxdqsGatingPostProcess] freq 800
1431 08:07:34.028521 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1432 08:07:34.028604 Pre-setting of DQS Precalculation
1433 08:07:34.035022 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1434 08:07:34.035112 ==
1435 08:07:34.038240 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 08:07:34.042021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 08:07:34.042146 ==
1438 08:07:34.048401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1439 08:07:34.055341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1440 08:07:34.063029 [CA 0] Center 36 (6~67) winsize 62
1441 08:07:34.066456 [CA 1] Center 36 (6~67) winsize 62
1442 08:07:34.069706 [CA 2] Center 34 (4~65) winsize 62
1443 08:07:34.072918 [CA 3] Center 34 (4~65) winsize 62
1444 08:07:34.076677 [CA 4] Center 35 (5~65) winsize 61
1445 08:07:34.079523 [CA 5] Center 34 (4~64) winsize 61
1446 08:07:34.079655
1447 08:07:34.083116 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1448 08:07:34.083237
1449 08:07:34.086034 [CATrainingPosCal] consider 1 rank data
1450 08:07:34.089725 u2DelayCellTimex100 = 270/100 ps
1451 08:07:34.092601 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 08:07:34.099373 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 08:07:34.102655 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 08:07:34.106243 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 08:07:34.109526 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1456 08:07:34.112660 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1457 08:07:34.112786
1458 08:07:34.116422 CA PerBit enable=1, Macro0, CA PI delay=34
1459 08:07:34.116548
1460 08:07:34.119380 [CBTSetCACLKResult] CA Dly = 34
1461 08:07:34.119501 CS Dly: 5 (0~36)
1462 08:07:34.123121 ==
1463 08:07:34.123242 Dram Type= 6, Freq= 0, CH_1, rank 1
1464 08:07:34.129590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 08:07:34.129723 ==
1466 08:07:34.133403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 08:07:34.140465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 08:07:34.150077 [CA 0] Center 36 (6~67) winsize 62
1469 08:07:34.153658 [CA 1] Center 36 (6~67) winsize 62
1470 08:07:34.157328 [CA 2] Center 35 (5~66) winsize 62
1471 08:07:34.160560 [CA 3] Center 34 (4~65) winsize 62
1472 08:07:34.164146 [CA 4] Center 35 (4~66) winsize 63
1473 08:07:34.167619 [CA 5] Center 34 (4~65) winsize 62
1474 08:07:34.167741
1475 08:07:34.170869 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1476 08:07:34.170951
1477 08:07:34.174261 [CATrainingPosCal] consider 2 rank data
1478 08:07:34.177709 u2DelayCellTimex100 = 270/100 ps
1479 08:07:34.181614 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 08:07:34.184425 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 08:07:34.188267 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1482 08:07:34.191354 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 08:07:34.194894 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1484 08:07:34.198043 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1485 08:07:34.198142
1486 08:07:34.201592 CA PerBit enable=1, Macro0, CA PI delay=34
1487 08:07:34.201721
1488 08:07:34.204848 [CBTSetCACLKResult] CA Dly = 34
1489 08:07:34.207726 CS Dly: 6 (0~38)
1490 08:07:34.207852
1491 08:07:34.211542 ----->DramcWriteLeveling(PI) begin...
1492 08:07:34.211675 ==
1493 08:07:34.214358 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 08:07:34.217931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 08:07:34.218058 ==
1496 08:07:34.221165 Write leveling (Byte 0): 27 => 27
1497 08:07:34.224617 Write leveling (Byte 1): 27 => 27
1498 08:07:34.227851 DramcWriteLeveling(PI) end<-----
1499 08:07:34.227976
1500 08:07:34.228089 ==
1501 08:07:34.231725 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 08:07:34.235141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 08:07:34.235266 ==
1504 08:07:34.238099 [Gating] SW mode calibration
1505 08:07:34.244715 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1506 08:07:34.251420 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1507 08:07:34.254609 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1508 08:07:34.258120 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1509 08:07:34.264948 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 08:07:34.268403 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 08:07:34.272001 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 08:07:34.278030 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 08:07:34.281734 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 08:07:34.285160 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 08:07:34.291773 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 08:07:34.295380 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 08:07:34.298397 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 08:07:34.305035 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 08:07:34.308450 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 08:07:34.311868 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 08:07:34.315249 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 08:07:34.321856 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 08:07:34.325039 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1524 08:07:34.328609 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1525 08:07:34.335009 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1526 08:07:34.338315 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 08:07:34.341878 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 08:07:34.348744 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 08:07:34.351631 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 08:07:34.355180 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 08:07:34.361996 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 08:07:34.365190 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1533 08:07:34.368487 0 9 8 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
1534 08:07:34.375385 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 08:07:34.378806 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 08:07:34.382208 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 08:07:34.385048 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 08:07:34.392111 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 08:07:34.395054 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1540 08:07:34.398620 0 10 4 | B1->B0 | 3232 2e2e | 1 1 | (1 0) (1 1)
1541 08:07:34.405358 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1542 08:07:34.408908 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 08:07:34.411862 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 08:07:34.418572 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 08:07:34.421861 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 08:07:34.425147 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 08:07:34.431964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 08:07:34.435017 0 11 4 | B1->B0 | 2a2a 3636 | 0 0 | (1 1) (0 0)
1549 08:07:34.438492 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1550 08:07:34.445346 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 08:07:34.448744 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 08:07:34.452109 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 08:07:34.458854 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 08:07:34.461675 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 08:07:34.465430 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 08:07:34.468641 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1557 08:07:34.475104 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 08:07:34.478452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 08:07:34.482126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 08:07:34.488379 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 08:07:34.491831 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 08:07:34.495397 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 08:07:34.501979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 08:07:34.505623 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 08:07:34.508426 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 08:07:34.515286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 08:07:34.518955 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 08:07:34.522311 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 08:07:34.528860 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 08:07:34.532183 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 08:07:34.535352 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1572 08:07:34.542094 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1573 08:07:34.545637 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 08:07:34.548973 Total UI for P1: 0, mck2ui 16
1575 08:07:34.552133 best dqsien dly found for B0: ( 0, 14, 4)
1576 08:07:34.555920 Total UI for P1: 0, mck2ui 16
1577 08:07:34.558616 best dqsien dly found for B1: ( 0, 14, 2)
1578 08:07:34.562217 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1579 08:07:34.565267 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1580 08:07:34.565346
1581 08:07:34.568655 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1582 08:07:34.572101 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1583 08:07:34.575783 [Gating] SW calibration Done
1584 08:07:34.575861 ==
1585 08:07:34.578876 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 08:07:34.582717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 08:07:34.582856 ==
1588 08:07:34.585453 RX Vref Scan: 0
1589 08:07:34.585587
1590 08:07:34.585701 RX Vref 0 -> 0, step: 1
1591 08:07:34.585827
1592 08:07:34.589245 RX Delay -130 -> 252, step: 16
1593 08:07:34.595339 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1594 08:07:34.598780 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1595 08:07:34.602544 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1596 08:07:34.605778 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1597 08:07:34.608775 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1598 08:07:34.612167 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1599 08:07:34.618819 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1600 08:07:34.622406 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1601 08:07:34.625513 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1602 08:07:34.628960 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1603 08:07:34.632479 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1604 08:07:34.639039 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1605 08:07:34.642174 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1606 08:07:34.645845 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1607 08:07:34.649072 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1608 08:07:34.652229 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1609 08:07:34.655665 ==
1610 08:07:34.659089 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 08:07:34.662527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 08:07:34.662656 ==
1613 08:07:34.662774 DQS Delay:
1614 08:07:34.666069 DQS0 = 0, DQS1 = 0
1615 08:07:34.666158 DQM Delay:
1616 08:07:34.669187 DQM0 = 94, DQM1 = 89
1617 08:07:34.669313 DQ Delay:
1618 08:07:34.672474 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1619 08:07:34.675890 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1620 08:07:34.679536 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1621 08:07:34.682426 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1622 08:07:34.682547
1623 08:07:34.682665
1624 08:07:34.682776 ==
1625 08:07:34.685825 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 08:07:34.689402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 08:07:34.689532 ==
1628 08:07:34.689646
1629 08:07:34.689761
1630 08:07:34.693361 TX Vref Scan disable
1631 08:07:34.695868 == TX Byte 0 ==
1632 08:07:34.699203 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1633 08:07:34.702809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1634 08:07:34.705840 == TX Byte 1 ==
1635 08:07:34.709355 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1636 08:07:34.713324 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1637 08:07:34.713449 ==
1638 08:07:34.716480 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 08:07:34.719618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 08:07:34.719754 ==
1641 08:07:34.733606 TX Vref=22, minBit 11, minWin=26, winSum=438
1642 08:07:34.736599 TX Vref=24, minBit 0, minWin=27, winSum=440
1643 08:07:34.740219 TX Vref=26, minBit 1, minWin=27, winSum=445
1644 08:07:34.744037 TX Vref=28, minBit 1, minWin=27, winSum=450
1645 08:07:34.746973 TX Vref=30, minBit 1, minWin=27, winSum=446
1646 08:07:34.750634 TX Vref=32, minBit 3, minWin=26, winSum=445
1647 08:07:34.756681 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1648 08:07:34.756764
1649 08:07:34.760333 Final TX Range 1 Vref 28
1650 08:07:34.760416
1651 08:07:34.760485 ==
1652 08:07:34.763654 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 08:07:34.766861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 08:07:34.766967 ==
1655 08:07:34.767075
1656 08:07:34.770465
1657 08:07:34.770586 TX Vref Scan disable
1658 08:07:34.773629 == TX Byte 0 ==
1659 08:07:34.777133 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1660 08:07:34.780084 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1661 08:07:34.783406 == TX Byte 1 ==
1662 08:07:34.786798 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1663 08:07:34.790219 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1664 08:07:34.790343
1665 08:07:34.793848 [DATLAT]
1666 08:07:34.793968 Freq=800, CH1 RK0
1667 08:07:34.794085
1668 08:07:34.796777 DATLAT Default: 0xa
1669 08:07:34.796896 0, 0xFFFF, sum = 0
1670 08:07:34.800517 1, 0xFFFF, sum = 0
1671 08:07:34.800643 2, 0xFFFF, sum = 0
1672 08:07:34.803817 3, 0xFFFF, sum = 0
1673 08:07:34.803936 4, 0xFFFF, sum = 0
1674 08:07:34.807038 5, 0xFFFF, sum = 0
1675 08:07:34.807146 6, 0xFFFF, sum = 0
1676 08:07:34.810497 7, 0xFFFF, sum = 0
1677 08:07:34.810574 8, 0xFFFF, sum = 0
1678 08:07:34.813537 9, 0x0, sum = 1
1679 08:07:34.813613 10, 0x0, sum = 2
1680 08:07:34.816961 11, 0x0, sum = 3
1681 08:07:34.817062 12, 0x0, sum = 4
1682 08:07:34.820618 best_step = 10
1683 08:07:34.820691
1684 08:07:34.820763 ==
1685 08:07:34.823516 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 08:07:34.827205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 08:07:34.827290 ==
1688 08:07:34.830683 RX Vref Scan: 1
1689 08:07:34.830804
1690 08:07:34.830920 Set Vref Range= 32 -> 127
1691 08:07:34.831034
1692 08:07:34.834087 RX Vref 32 -> 127, step: 1
1693 08:07:34.834209
1694 08:07:34.837119 RX Delay -63 -> 252, step: 8
1695 08:07:34.837225
1696 08:07:34.840490 Set Vref, RX VrefLevel [Byte0]: 32
1697 08:07:34.843552 [Byte1]: 32
1698 08:07:34.843669
1699 08:07:34.847093 Set Vref, RX VrefLevel [Byte0]: 33
1700 08:07:34.850225 [Byte1]: 33
1701 08:07:34.853868
1702 08:07:34.853951 Set Vref, RX VrefLevel [Byte0]: 34
1703 08:07:34.857021 [Byte1]: 34
1704 08:07:34.861513
1705 08:07:34.861591 Set Vref, RX VrefLevel [Byte0]: 35
1706 08:07:34.864250 [Byte1]: 35
1707 08:07:34.868626
1708 08:07:34.868701 Set Vref, RX VrefLevel [Byte0]: 36
1709 08:07:34.871655 [Byte1]: 36
1710 08:07:34.876296
1711 08:07:34.876407 Set Vref, RX VrefLevel [Byte0]: 37
1712 08:07:34.879073 [Byte1]: 37
1713 08:07:34.883748
1714 08:07:34.883825 Set Vref, RX VrefLevel [Byte0]: 38
1715 08:07:34.886939 [Byte1]: 38
1716 08:07:34.891036
1717 08:07:34.891112 Set Vref, RX VrefLevel [Byte0]: 39
1718 08:07:34.894329 [Byte1]: 39
1719 08:07:34.899014
1720 08:07:34.899092 Set Vref, RX VrefLevel [Byte0]: 40
1721 08:07:34.901774 [Byte1]: 40
1722 08:07:34.905924
1723 08:07:34.906025 Set Vref, RX VrefLevel [Byte0]: 41
1724 08:07:34.909509 [Byte1]: 41
1725 08:07:34.913450
1726 08:07:34.913559 Set Vref, RX VrefLevel [Byte0]: 42
1727 08:07:34.917150 [Byte1]: 42
1728 08:07:34.921220
1729 08:07:34.921324 Set Vref, RX VrefLevel [Byte0]: 43
1730 08:07:34.924271 [Byte1]: 43
1731 08:07:34.928392
1732 08:07:34.928471 Set Vref, RX VrefLevel [Byte0]: 44
1733 08:07:34.932070 [Byte1]: 44
1734 08:07:34.935867
1735 08:07:34.935946 Set Vref, RX VrefLevel [Byte0]: 45
1736 08:07:34.939098 [Byte1]: 45
1737 08:07:34.943800
1738 08:07:34.943884 Set Vref, RX VrefLevel [Byte0]: 46
1739 08:07:34.947189 [Byte1]: 46
1740 08:07:34.950842
1741 08:07:34.950959 Set Vref, RX VrefLevel [Byte0]: 47
1742 08:07:34.954284 [Byte1]: 47
1743 08:07:34.958376
1744 08:07:34.958481 Set Vref, RX VrefLevel [Byte0]: 48
1745 08:07:34.961613 [Byte1]: 48
1746 08:07:34.966423
1747 08:07:34.966527 Set Vref, RX VrefLevel [Byte0]: 49
1748 08:07:34.969074 [Byte1]: 49
1749 08:07:34.973737
1750 08:07:34.973844 Set Vref, RX VrefLevel [Byte0]: 50
1751 08:07:34.976711 [Byte1]: 50
1752 08:07:34.980953
1753 08:07:34.981037 Set Vref, RX VrefLevel [Byte0]: 51
1754 08:07:34.984099 [Byte1]: 51
1755 08:07:34.988696
1756 08:07:34.988807 Set Vref, RX VrefLevel [Byte0]: 52
1757 08:07:34.991906 [Byte1]: 52
1758 08:07:34.996378
1759 08:07:34.996472 Set Vref, RX VrefLevel [Byte0]: 53
1760 08:07:34.999299 [Byte1]: 53
1761 08:07:35.003478
1762 08:07:35.003581 Set Vref, RX VrefLevel [Byte0]: 54
1763 08:07:35.006692 [Byte1]: 54
1764 08:07:35.010839
1765 08:07:35.010930 Set Vref, RX VrefLevel [Byte0]: 55
1766 08:07:35.014375 [Byte1]: 55
1767 08:07:35.018702
1768 08:07:35.018811 Set Vref, RX VrefLevel [Byte0]: 56
1769 08:07:35.022075 [Byte1]: 56
1770 08:07:35.025968
1771 08:07:35.026085 Set Vref, RX VrefLevel [Byte0]: 57
1772 08:07:35.029380 [Byte1]: 57
1773 08:07:35.033563
1774 08:07:35.033671 Set Vref, RX VrefLevel [Byte0]: 58
1775 08:07:35.036773 [Byte1]: 58
1776 08:07:35.040804
1777 08:07:35.040892 Set Vref, RX VrefLevel [Byte0]: 59
1778 08:07:35.044454 [Byte1]: 59
1779 08:07:35.048683
1780 08:07:35.048794 Set Vref, RX VrefLevel [Byte0]: 60
1781 08:07:35.051804 [Byte1]: 60
1782 08:07:35.056147
1783 08:07:35.056229 Set Vref, RX VrefLevel [Byte0]: 61
1784 08:07:35.059539 [Byte1]: 61
1785 08:07:35.063743
1786 08:07:35.063845 Set Vref, RX VrefLevel [Byte0]: 62
1787 08:07:35.066622 [Byte1]: 62
1788 08:07:35.071124
1789 08:07:35.071205 Set Vref, RX VrefLevel [Byte0]: 63
1790 08:07:35.074510 [Byte1]: 63
1791 08:07:35.079013
1792 08:07:35.079095 Set Vref, RX VrefLevel [Byte0]: 64
1793 08:07:35.082041 [Byte1]: 64
1794 08:07:35.085950
1795 08:07:35.086031 Set Vref, RX VrefLevel [Byte0]: 65
1796 08:07:35.089215 [Byte1]: 65
1797 08:07:35.093614
1798 08:07:35.093695 Set Vref, RX VrefLevel [Byte0]: 66
1799 08:07:35.097314 [Byte1]: 66
1800 08:07:35.101328
1801 08:07:35.101430 Set Vref, RX VrefLevel [Byte0]: 67
1802 08:07:35.104250 [Byte1]: 67
1803 08:07:35.108698
1804 08:07:35.108830 Set Vref, RX VrefLevel [Byte0]: 68
1805 08:07:35.112016 [Byte1]: 68
1806 08:07:35.116210
1807 08:07:35.116338 Set Vref, RX VrefLevel [Byte0]: 69
1808 08:07:35.119472 [Byte1]: 69
1809 08:07:35.123508
1810 08:07:35.123630 Set Vref, RX VrefLevel [Byte0]: 70
1811 08:07:35.127060 [Byte1]: 70
1812 08:07:35.130774
1813 08:07:35.130902 Set Vref, RX VrefLevel [Byte0]: 71
1814 08:07:35.134530 [Byte1]: 71
1815 08:07:35.138457
1816 08:07:35.138588 Final RX Vref Byte 0 = 58 to rank0
1817 08:07:35.141887 Final RX Vref Byte 1 = 57 to rank0
1818 08:07:35.145181 Final RX Vref Byte 0 = 58 to rank1
1819 08:07:35.148310 Final RX Vref Byte 1 = 57 to rank1==
1820 08:07:35.152069 Dram Type= 6, Freq= 0, CH_1, rank 0
1821 08:07:35.158425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1822 08:07:35.158534 ==
1823 08:07:35.158633 DQS Delay:
1824 08:07:35.158724 DQS0 = 0, DQS1 = 0
1825 08:07:35.161968 DQM Delay:
1826 08:07:35.162083 DQM0 = 96, DQM1 = 90
1827 08:07:35.165218 DQ Delay:
1828 08:07:35.168727 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1829 08:07:35.171868 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1830 08:07:35.175367 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1831 08:07:35.178646 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1832 08:07:35.178729
1833 08:07:35.178793
1834 08:07:35.185124 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1835 08:07:35.188804 CH1 RK0: MR19=606, MR18=2A46
1836 08:07:35.195438 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1837 08:07:35.195522
1838 08:07:35.198655 ----->DramcWriteLeveling(PI) begin...
1839 08:07:35.198739 ==
1840 08:07:35.201892 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 08:07:35.205352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 08:07:35.205436 ==
1843 08:07:35.208736 Write leveling (Byte 0): 28 => 28
1844 08:07:35.211684 Write leveling (Byte 1): 28 => 28
1845 08:07:35.215221 DramcWriteLeveling(PI) end<-----
1846 08:07:35.215305
1847 08:07:35.215370 ==
1848 08:07:35.218818 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 08:07:35.221909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 08:07:35.221994 ==
1851 08:07:35.225351 [Gating] SW mode calibration
1852 08:07:35.232149 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1853 08:07:35.238824 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1854 08:07:35.242181 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1855 08:07:35.245428 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1856 08:07:35.251653 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1857 08:07:35.255127 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 08:07:35.258678 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 08:07:35.265262 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 08:07:35.268880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 08:07:35.271900 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 08:07:35.278462 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 08:07:35.281808 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 08:07:35.285298 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 08:07:35.291929 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 08:07:35.295580 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 08:07:35.298594 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 08:07:35.302144 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 08:07:35.308595 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 08:07:35.311936 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1871 08:07:35.315175 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1872 08:07:35.321927 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 08:07:35.325375 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 08:07:35.328603 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 08:07:35.335537 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 08:07:35.338578 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 08:07:35.342236 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 08:07:35.348435 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 08:07:35.352144 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
1880 08:07:35.355160 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1881 08:07:35.362036 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 08:07:35.365036 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 08:07:35.368710 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 08:07:35.375213 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 08:07:35.378935 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 08:07:35.382138 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1887 08:07:35.388568 0 10 4 | B1->B0 | 2d2d 2f2f | 0 0 | (1 0) (0 1)
1888 08:07:35.392201 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1889 08:07:35.395214 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 08:07:35.398392 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 08:07:35.405451 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 08:07:35.408528 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 08:07:35.412124 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 08:07:35.418860 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1895 08:07:35.422040 0 11 4 | B1->B0 | 3a3a 2c2c | 0 0 | (0 0) (0 0)
1896 08:07:35.425189 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
1897 08:07:35.432317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 08:07:35.435285 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 08:07:35.438666 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 08:07:35.445075 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 08:07:35.448930 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 08:07:35.452311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 08:07:35.458920 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 08:07:35.462466 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 08:07:35.465418 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 08:07:35.472121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 08:07:35.475430 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 08:07:35.478613 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 08:07:35.482085 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 08:07:35.488677 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 08:07:35.492356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 08:07:35.495968 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 08:07:35.502461 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 08:07:35.505420 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 08:07:35.508758 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 08:07:35.515431 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 08:07:35.518958 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 08:07:35.522559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 08:07:35.528912 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 08:07:35.528999 Total UI for P1: 0, mck2ui 16
1921 08:07:35.535596 best dqsien dly found for B0: ( 0, 14, 2)
1922 08:07:35.535702 Total UI for P1: 0, mck2ui 16
1923 08:07:35.542222 best dqsien dly found for B1: ( 0, 14, 2)
1924 08:07:35.545746 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1925 08:07:35.548810 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1926 08:07:35.548893
1927 08:07:35.552578 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1928 08:07:35.555356 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1929 08:07:35.558857 [Gating] SW calibration Done
1930 08:07:35.558932 ==
1931 08:07:35.562312 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 08:07:35.565703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 08:07:35.565802 ==
1934 08:07:35.568744 RX Vref Scan: 0
1935 08:07:35.568869
1936 08:07:35.568932 RX Vref 0 -> 0, step: 1
1937 08:07:35.568991
1938 08:07:35.572243 RX Delay -130 -> 252, step: 16
1939 08:07:35.575775 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1940 08:07:35.582198 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1941 08:07:35.585922 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1942 08:07:35.589049 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1943 08:07:35.592567 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1944 08:07:35.595948 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1945 08:07:35.599282 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1946 08:07:35.605495 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1947 08:07:35.609270 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1948 08:07:35.612097 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1949 08:07:35.615886 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1950 08:07:35.619094 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1951 08:07:35.625407 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1952 08:07:35.628739 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1953 08:07:35.632585 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1954 08:07:35.635514 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1955 08:07:35.635622 ==
1956 08:07:35.638879 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 08:07:35.645913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 08:07:35.646026 ==
1959 08:07:35.646119 DQS Delay:
1960 08:07:35.646211 DQS0 = 0, DQS1 = 0
1961 08:07:35.648929 DQM Delay:
1962 08:07:35.649004 DQM0 = 92, DQM1 = 88
1963 08:07:35.652241 DQ Delay:
1964 08:07:35.655955 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1965 08:07:35.658803 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1966 08:07:35.662415 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1967 08:07:35.665837 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1968 08:07:35.665938
1969 08:07:35.666034
1970 08:07:35.666128 ==
1971 08:07:35.669302 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 08:07:35.672582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 08:07:35.672692 ==
1974 08:07:35.672784
1975 08:07:35.672874
1976 08:07:35.675531 TX Vref Scan disable
1977 08:07:35.675629 == TX Byte 0 ==
1978 08:07:35.682205 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1979 08:07:35.685918 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1980 08:07:35.686001 == TX Byte 1 ==
1981 08:07:35.692254 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1982 08:07:35.696021 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1983 08:07:35.696103 ==
1984 08:07:35.699242 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 08:07:35.702160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 08:07:35.702243 ==
1987 08:07:35.716214 TX Vref=22, minBit 1, minWin=26, winSum=442
1988 08:07:35.719759 TX Vref=24, minBit 2, minWin=27, winSum=448
1989 08:07:35.723416 TX Vref=26, minBit 2, minWin=27, winSum=449
1990 08:07:35.726346 TX Vref=28, minBit 2, minWin=27, winSum=451
1991 08:07:35.729923 TX Vref=30, minBit 2, minWin=27, winSum=449
1992 08:07:35.733110 TX Vref=32, minBit 1, minWin=27, winSum=448
1993 08:07:35.739704 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
1994 08:07:35.739796
1995 08:07:35.743094 Final TX Range 1 Vref 28
1996 08:07:35.743201
1997 08:07:35.743294 ==
1998 08:07:35.746405 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 08:07:35.749992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 08:07:35.750076 ==
2001 08:07:35.750141
2002 08:07:35.752778
2003 08:07:35.752898 TX Vref Scan disable
2004 08:07:35.756619 == TX Byte 0 ==
2005 08:07:35.759708 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2006 08:07:35.763460 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2007 08:07:35.766832 == TX Byte 1 ==
2008 08:07:35.769942 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2009 08:07:35.773707 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2010 08:07:35.773790
2011 08:07:35.776616 [DATLAT]
2012 08:07:35.776698 Freq=800, CH1 RK1
2013 08:07:35.776764
2014 08:07:35.780117 DATLAT Default: 0xa
2015 08:07:35.780201 0, 0xFFFF, sum = 0
2016 08:07:35.782912 1, 0xFFFF, sum = 0
2017 08:07:35.782997 2, 0xFFFF, sum = 0
2018 08:07:35.786507 3, 0xFFFF, sum = 0
2019 08:07:35.786591 4, 0xFFFF, sum = 0
2020 08:07:35.789932 5, 0xFFFF, sum = 0
2021 08:07:35.790017 6, 0xFFFF, sum = 0
2022 08:07:35.793162 7, 0xFFFF, sum = 0
2023 08:07:35.796680 8, 0xFFFF, sum = 0
2024 08:07:35.796765 9, 0x0, sum = 1
2025 08:07:35.796831 10, 0x0, sum = 2
2026 08:07:35.799613 11, 0x0, sum = 3
2027 08:07:35.799707 12, 0x0, sum = 4
2028 08:07:35.803277 best_step = 10
2029 08:07:35.803359
2030 08:07:35.803423 ==
2031 08:07:35.806879 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 08:07:35.809970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 08:07:35.810054 ==
2034 08:07:35.812908 RX Vref Scan: 0
2035 08:07:35.812991
2036 08:07:35.813055 RX Vref 0 -> 0, step: 1
2037 08:07:35.813117
2038 08:07:35.816528 RX Delay -79 -> 252, step: 8
2039 08:07:35.823033 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2040 08:07:35.826544 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2041 08:07:35.830002 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2042 08:07:35.832976 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2043 08:07:35.836618 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2044 08:07:35.839866 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2045 08:07:35.846526 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2046 08:07:35.849979 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2047 08:07:35.853110 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2048 08:07:35.856814 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2049 08:07:35.859896 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2050 08:07:35.866960 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2051 08:07:35.869940 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2052 08:07:35.873132 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2053 08:07:35.876449 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2054 08:07:35.879982 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2055 08:07:35.880065 ==
2056 08:07:35.883336 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 08:07:35.890071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 08:07:35.890154 ==
2059 08:07:35.890220 DQS Delay:
2060 08:07:35.893279 DQS0 = 0, DQS1 = 0
2061 08:07:35.893361 DQM Delay:
2062 08:07:35.893428 DQM0 = 97, DQM1 = 90
2063 08:07:35.896971 DQ Delay:
2064 08:07:35.899669 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2065 08:07:35.903259 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2066 08:07:35.906594 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2067 08:07:35.909969 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2068 08:07:35.910052
2069 08:07:35.910117
2070 08:07:35.916944 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2071 08:07:35.919880 CH1 RK1: MR19=606, MR18=4711
2072 08:07:35.926502 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2073 08:07:35.930209 [RxdqsGatingPostProcess] freq 800
2074 08:07:35.933470 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2075 08:07:35.937162 Pre-setting of DQS Precalculation
2076 08:07:35.943715 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2077 08:07:35.950084 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2078 08:07:35.956476 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2079 08:07:35.956554
2080 08:07:35.956618
2081 08:07:35.960454 [Calibration Summary] 1600 Mbps
2082 08:07:35.960535 CH 0, Rank 0
2083 08:07:35.963284 SW Impedance : PASS
2084 08:07:35.966603 DUTY Scan : NO K
2085 08:07:35.966677 ZQ Calibration : PASS
2086 08:07:35.970025 Jitter Meter : NO K
2087 08:07:35.973454 CBT Training : PASS
2088 08:07:35.973532 Write leveling : PASS
2089 08:07:35.976854 RX DQS gating : PASS
2090 08:07:35.980034 RX DQ/DQS(RDDQC) : PASS
2091 08:07:35.980108 TX DQ/DQS : PASS
2092 08:07:35.983385 RX DATLAT : PASS
2093 08:07:35.986533 RX DQ/DQS(Engine): PASS
2094 08:07:35.986611 TX OE : NO K
2095 08:07:35.986676 All Pass.
2096 08:07:35.990067
2097 08:07:35.990175 CH 0, Rank 1
2098 08:07:35.990268 SW Impedance : PASS
2099 08:07:35.993607 DUTY Scan : NO K
2100 08:07:35.996801 ZQ Calibration : PASS
2101 08:07:35.996903 Jitter Meter : NO K
2102 08:07:36.000422 CBT Training : PASS
2103 08:07:36.003895 Write leveling : PASS
2104 08:07:36.003978 RX DQS gating : PASS
2105 08:07:36.006637 RX DQ/DQS(RDDQC) : PASS
2106 08:07:36.010129 TX DQ/DQS : PASS
2107 08:07:36.010258 RX DATLAT : PASS
2108 08:07:36.013165 RX DQ/DQS(Engine): PASS
2109 08:07:36.016807 TX OE : NO K
2110 08:07:36.016931 All Pass.
2111 08:07:36.017044
2112 08:07:36.017156 CH 1, Rank 0
2113 08:07:36.020204 SW Impedance : PASS
2114 08:07:36.023475 DUTY Scan : NO K
2115 08:07:36.023598 ZQ Calibration : PASS
2116 08:07:36.026790 Jitter Meter : NO K
2117 08:07:36.029883 CBT Training : PASS
2118 08:07:36.029994 Write leveling : PASS
2119 08:07:36.033381 RX DQS gating : PASS
2120 08:07:36.033470 RX DQ/DQS(RDDQC) : PASS
2121 08:07:36.036707 TX DQ/DQS : PASS
2122 08:07:36.039898 RX DATLAT : PASS
2123 08:07:36.039997 RX DQ/DQS(Engine): PASS
2124 08:07:36.043534 TX OE : NO K
2125 08:07:36.043642 All Pass.
2126 08:07:36.043713
2127 08:07:36.046962 CH 1, Rank 1
2128 08:07:36.047069 SW Impedance : PASS
2129 08:07:36.050099 DUTY Scan : NO K
2130 08:07:36.053477 ZQ Calibration : PASS
2131 08:07:36.053585 Jitter Meter : NO K
2132 08:07:36.057102 CBT Training : PASS
2133 08:07:36.060455 Write leveling : PASS
2134 08:07:36.060559 RX DQS gating : PASS
2135 08:07:36.063790 RX DQ/DQS(RDDQC) : PASS
2136 08:07:36.066548 TX DQ/DQS : PASS
2137 08:07:36.066659 RX DATLAT : PASS
2138 08:07:36.070203 RX DQ/DQS(Engine): PASS
2139 08:07:36.073684 TX OE : NO K
2140 08:07:36.073786 All Pass.
2141 08:07:36.073887
2142 08:07:36.073977 DramC Write-DBI off
2143 08:07:36.076811 PER_BANK_REFRESH: Hybrid Mode
2144 08:07:36.080107 TX_TRACKING: ON
2145 08:07:36.083743 [GetDramInforAfterCalByMRR] Vendor 6.
2146 08:07:36.086572 [GetDramInforAfterCalByMRR] Revision 606.
2147 08:07:36.090056 [GetDramInforAfterCalByMRR] Revision 2 0.
2148 08:07:36.090157 MR0 0x3b3b
2149 08:07:36.090249 MR8 0x5151
2150 08:07:36.096656 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 08:07:36.096766
2152 08:07:36.096860 MR0 0x3b3b
2153 08:07:36.096959 MR8 0x5151
2154 08:07:36.100009 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 08:07:36.100086
2156 08:07:36.110456 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2157 08:07:36.114071 [FAST_K] Save calibration result to emmc
2158 08:07:36.117450 [FAST_K] Save calibration result to emmc
2159 08:07:36.120150 dram_init: config_dvfs: 1
2160 08:07:36.123836 dramc_set_vcore_voltage set vcore to 662500
2161 08:07:36.127262 Read voltage for 1200, 2
2162 08:07:36.127389 Vio18 = 0
2163 08:07:36.127499 Vcore = 662500
2164 08:07:36.130381 Vdram = 0
2165 08:07:36.130501 Vddq = 0
2166 08:07:36.130616 Vmddr = 0
2167 08:07:36.137080 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2168 08:07:36.140095 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2169 08:07:36.143964 MEM_TYPE=3, freq_sel=15
2170 08:07:36.147322 sv_algorithm_assistance_LP4_1600
2171 08:07:36.150638 ============ PULL DRAM RESETB DOWN ============
2172 08:07:36.153956 ========== PULL DRAM RESETB DOWN end =========
2173 08:07:36.160771 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 08:07:36.163865 ===================================
2175 08:07:36.163969 LPDDR4 DRAM CONFIGURATION
2176 08:07:36.167295 ===================================
2177 08:07:36.170223 EX_ROW_EN[0] = 0x0
2178 08:07:36.173714 EX_ROW_EN[1] = 0x0
2179 08:07:36.173812 LP4Y_EN = 0x0
2180 08:07:36.177093 WORK_FSP = 0x0
2181 08:07:36.177187 WL = 0x4
2182 08:07:36.180653 RL = 0x4
2183 08:07:36.180727 BL = 0x2
2184 08:07:36.183830 RPST = 0x0
2185 08:07:36.183908 RD_PRE = 0x0
2186 08:07:36.187162 WR_PRE = 0x1
2187 08:07:36.187263 WR_PST = 0x0
2188 08:07:36.190592 DBI_WR = 0x0
2189 08:07:36.190692 DBI_RD = 0x0
2190 08:07:36.193660 OTF = 0x1
2191 08:07:36.197255 ===================================
2192 08:07:36.200295 ===================================
2193 08:07:36.200404 ANA top config
2194 08:07:36.203748 ===================================
2195 08:07:36.207415 DLL_ASYNC_EN = 0
2196 08:07:36.210460 ALL_SLAVE_EN = 0
2197 08:07:36.210566 NEW_RANK_MODE = 1
2198 08:07:36.214005 DLL_IDLE_MODE = 1
2199 08:07:36.217073 LP45_APHY_COMB_EN = 1
2200 08:07:36.220572 TX_ODT_DIS = 1
2201 08:07:36.224133 NEW_8X_MODE = 1
2202 08:07:36.227491 ===================================
2203 08:07:36.230774 ===================================
2204 08:07:36.230887 data_rate = 2400
2205 08:07:36.234218 CKR = 1
2206 08:07:36.237976 DQ_P2S_RATIO = 8
2207 08:07:36.240756 ===================================
2208 08:07:36.244526 CA_P2S_RATIO = 8
2209 08:07:36.248102 DQ_CA_OPEN = 0
2210 08:07:36.248214 DQ_SEMI_OPEN = 0
2211 08:07:36.250858 CA_SEMI_OPEN = 0
2212 08:07:36.254209 CA_FULL_RATE = 0
2213 08:07:36.257753 DQ_CKDIV4_EN = 0
2214 08:07:36.260635 CA_CKDIV4_EN = 0
2215 08:07:36.264674 CA_PREDIV_EN = 0
2216 08:07:36.264778 PH8_DLY = 17
2217 08:07:36.267578 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2218 08:07:36.271307 DQ_AAMCK_DIV = 4
2219 08:07:36.274024 CA_AAMCK_DIV = 4
2220 08:07:36.277399 CA_ADMCK_DIV = 4
2221 08:07:36.281081 DQ_TRACK_CA_EN = 0
2222 08:07:36.281160 CA_PICK = 1200
2223 08:07:36.284612 CA_MCKIO = 1200
2224 08:07:36.287621 MCKIO_SEMI = 0
2225 08:07:36.291088 PLL_FREQ = 2366
2226 08:07:36.294508 DQ_UI_PI_RATIO = 32
2227 08:07:36.297505 CA_UI_PI_RATIO = 0
2228 08:07:36.301401 ===================================
2229 08:07:36.304367 ===================================
2230 08:07:36.307774 memory_type:LPDDR4
2231 08:07:36.307851 GP_NUM : 10
2232 08:07:36.310936 SRAM_EN : 1
2233 08:07:36.311047 MD32_EN : 0
2234 08:07:36.314342 ===================================
2235 08:07:36.317759 [ANA_INIT] >>>>>>>>>>>>>>
2236 08:07:36.320820 <<<<<< [CONFIGURE PHASE]: ANA_TX
2237 08:07:36.324523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2238 08:07:36.327459 ===================================
2239 08:07:36.330975 data_rate = 2400,PCW = 0X5b00
2240 08:07:36.334348 ===================================
2241 08:07:36.337669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2242 08:07:36.341113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 08:07:36.347626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2244 08:07:36.351151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2245 08:07:36.354253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2246 08:07:36.357625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2247 08:07:36.361172 [ANA_INIT] flow start
2248 08:07:36.364589 [ANA_INIT] PLL >>>>>>>>
2249 08:07:36.364700 [ANA_INIT] PLL <<<<<<<<
2250 08:07:36.367541 [ANA_INIT] MIDPI >>>>>>>>
2251 08:07:36.370764 [ANA_INIT] MIDPI <<<<<<<<
2252 08:07:36.374350 [ANA_INIT] DLL >>>>>>>>
2253 08:07:36.374452 [ANA_INIT] DLL <<<<<<<<
2254 08:07:36.378050 [ANA_INIT] flow end
2255 08:07:36.380996 ============ LP4 DIFF to SE enter ============
2256 08:07:36.384262 ============ LP4 DIFF to SE exit ============
2257 08:07:36.387364 [ANA_INIT] <<<<<<<<<<<<<
2258 08:07:36.391057 [Flow] Enable top DCM control >>>>>
2259 08:07:36.394757 [Flow] Enable top DCM control <<<<<
2260 08:07:36.397615 Enable DLL master slave shuffle
2261 08:07:36.404186 ==============================================================
2262 08:07:36.404292 Gating Mode config
2263 08:07:36.411000 ==============================================================
2264 08:07:36.411132 Config description:
2265 08:07:36.420775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2266 08:07:36.427450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2267 08:07:36.434119 SELPH_MODE 0: By rank 1: By Phase
2268 08:07:36.437452 ==============================================================
2269 08:07:36.440826 GAT_TRACK_EN = 1
2270 08:07:36.444126 RX_GATING_MODE = 2
2271 08:07:36.447538 RX_GATING_TRACK_MODE = 2
2272 08:07:36.451041 SELPH_MODE = 1
2273 08:07:36.453907 PICG_EARLY_EN = 1
2274 08:07:36.457338 VALID_LAT_VALUE = 1
2275 08:07:36.460783 ==============================================================
2276 08:07:36.464124 Enter into Gating configuration >>>>
2277 08:07:36.467571 Exit from Gating configuration <<<<
2278 08:07:36.471028 Enter into DVFS_PRE_config >>>>>
2279 08:07:36.484067 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2280 08:07:36.487624 Exit from DVFS_PRE_config <<<<<
2281 08:07:36.487711 Enter into PICG configuration >>>>
2282 08:07:36.490773 Exit from PICG configuration <<<<
2283 08:07:36.494192 [RX_INPUT] configuration >>>>>
2284 08:07:36.497701 [RX_INPUT] configuration <<<<<
2285 08:07:36.504464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2286 08:07:36.507997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2287 08:07:36.514604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 08:07:36.521320 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 08:07:36.527983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 08:07:36.534202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 08:07:36.537803 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2292 08:07:36.541121 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2293 08:07:36.544658 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2294 08:07:36.550925 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2295 08:07:36.554171 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2296 08:07:36.557480 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2297 08:07:36.560911 ===================================
2298 08:07:36.564372 LPDDR4 DRAM CONFIGURATION
2299 08:07:36.567514 ===================================
2300 08:07:36.567668 EX_ROW_EN[0] = 0x0
2301 08:07:36.571025 EX_ROW_EN[1] = 0x0
2302 08:07:36.571188 LP4Y_EN = 0x0
2303 08:07:36.574350 WORK_FSP = 0x0
2304 08:07:36.577522 WL = 0x4
2305 08:07:36.577624 RL = 0x4
2306 08:07:36.580936 BL = 0x2
2307 08:07:36.581016 RPST = 0x0
2308 08:07:36.584339 RD_PRE = 0x0
2309 08:07:36.584457 WR_PRE = 0x1
2310 08:07:36.587790 WR_PST = 0x0
2311 08:07:36.587896 DBI_WR = 0x0
2312 08:07:36.591054 DBI_RD = 0x0
2313 08:07:36.591132 OTF = 0x1
2314 08:07:36.594422 ===================================
2315 08:07:36.597588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2316 08:07:36.604464 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2317 08:07:36.608058 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 08:07:36.610874 ===================================
2319 08:07:36.614407 LPDDR4 DRAM CONFIGURATION
2320 08:07:36.617507 ===================================
2321 08:07:36.617585 EX_ROW_EN[0] = 0x10
2322 08:07:36.620884 EX_ROW_EN[1] = 0x0
2323 08:07:36.620987 LP4Y_EN = 0x0
2324 08:07:36.624696 WORK_FSP = 0x0
2325 08:07:36.624776 WL = 0x4
2326 08:07:36.627550 RL = 0x4
2327 08:07:36.627668 BL = 0x2
2328 08:07:36.631222 RPST = 0x0
2329 08:07:36.631298 RD_PRE = 0x0
2330 08:07:36.634809 WR_PRE = 0x1
2331 08:07:36.634887 WR_PST = 0x0
2332 08:07:36.637627 DBI_WR = 0x0
2333 08:07:36.637712 DBI_RD = 0x0
2334 08:07:36.641329 OTF = 0x1
2335 08:07:36.644382 ===================================
2336 08:07:36.651069 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2337 08:07:36.651147 ==
2338 08:07:36.654741 Dram Type= 6, Freq= 0, CH_0, rank 0
2339 08:07:36.657977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2340 08:07:36.658087 ==
2341 08:07:36.661115 [Duty_Offset_Calibration]
2342 08:07:36.661193 B0:2 B1:1 CA:1
2343 08:07:36.661263
2344 08:07:36.664338 [DutyScan_Calibration_Flow] k_type=0
2345 08:07:36.675401
2346 08:07:36.675513 ==CLK 0==
2347 08:07:36.678552 Final CLK duty delay cell = 0
2348 08:07:36.682027 [0] MAX Duty = 5187%(X100), DQS PI = 24
2349 08:07:36.685348 [0] MIN Duty = 4875%(X100), DQS PI = 0
2350 08:07:36.685432 [0] AVG Duty = 5031%(X100)
2351 08:07:36.688799
2352 08:07:36.688907 CH0 CLK Duty spec in!! Max-Min= 312%
2353 08:07:36.694996 [DutyScan_Calibration_Flow] ====Done====
2354 08:07:36.695074
2355 08:07:36.698842 [DutyScan_Calibration_Flow] k_type=1
2356 08:07:36.712996
2357 08:07:36.713085 ==DQS 0 ==
2358 08:07:36.716420 Final DQS duty delay cell = -4
2359 08:07:36.719503 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2360 08:07:36.723143 [-4] MIN Duty = 4782%(X100), DQS PI = 62
2361 08:07:36.726299 [-4] AVG Duty = 4969%(X100)
2362 08:07:36.726411
2363 08:07:36.726526 ==DQS 1 ==
2364 08:07:36.729917 Final DQS duty delay cell = -4
2365 08:07:36.732866 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2366 08:07:36.736557 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2367 08:07:36.740025 [-4] AVG Duty = 4906%(X100)
2368 08:07:36.740102
2369 08:07:36.742831 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2370 08:07:36.742904
2371 08:07:36.746780 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2372 08:07:36.749531 [DutyScan_Calibration_Flow] ====Done====
2373 08:07:36.749637
2374 08:07:36.753079 [DutyScan_Calibration_Flow] k_type=3
2375 08:07:36.769985
2376 08:07:36.770091 ==DQM 0 ==
2377 08:07:36.773420 Final DQM duty delay cell = 0
2378 08:07:36.776669 [0] MAX Duty = 5156%(X100), DQS PI = 28
2379 08:07:36.779736 [0] MIN Duty = 4907%(X100), DQS PI = 58
2380 08:07:36.783356 [0] AVG Duty = 5031%(X100)
2381 08:07:36.783456
2382 08:07:36.783553 ==DQM 1 ==
2383 08:07:36.786888 Final DQM duty delay cell = 0
2384 08:07:36.790492 [0] MAX Duty = 5125%(X100), DQS PI = 24
2385 08:07:36.793332 [0] MIN Duty = 5031%(X100), DQS PI = 52
2386 08:07:36.796710 [0] AVG Duty = 5078%(X100)
2387 08:07:36.796797
2388 08:07:36.800547 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2389 08:07:36.800624
2390 08:07:36.803234 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2391 08:07:36.806656 [DutyScan_Calibration_Flow] ====Done====
2392 08:07:36.806735
2393 08:07:36.810313 [DutyScan_Calibration_Flow] k_type=2
2394 08:07:36.826772
2395 08:07:36.826884 ==DQ 0 ==
2396 08:07:36.830012 Final DQ duty delay cell = 0
2397 08:07:36.833114 [0] MAX Duty = 5062%(X100), DQS PI = 32
2398 08:07:36.836640 [0] MIN Duty = 4906%(X100), DQS PI = 0
2399 08:07:36.836718 [0] AVG Duty = 4984%(X100)
2400 08:07:36.840079
2401 08:07:36.840164 ==DQ 1 ==
2402 08:07:36.843027 Final DQ duty delay cell = 0
2403 08:07:36.846729 [0] MAX Duty = 5093%(X100), DQS PI = 26
2404 08:07:36.850016 [0] MIN Duty = 4969%(X100), DQS PI = 2
2405 08:07:36.850090 [0] AVG Duty = 5031%(X100)
2406 08:07:36.850156
2407 08:07:36.853059 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2408 08:07:36.853135
2409 08:07:36.856887 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2410 08:07:36.863520 [DutyScan_Calibration_Flow] ====Done====
2411 08:07:36.863629 ==
2412 08:07:36.866708 Dram Type= 6, Freq= 0, CH_1, rank 0
2413 08:07:36.870267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2414 08:07:36.870371 ==
2415 08:07:36.873285 [Duty_Offset_Calibration]
2416 08:07:36.873385 B0:1 B1:0 CA:0
2417 08:07:36.873475
2418 08:07:36.876897 [DutyScan_Calibration_Flow] k_type=0
2419 08:07:36.885538
2420 08:07:36.885614 ==CLK 0==
2421 08:07:36.888964 Final CLK duty delay cell = -4
2422 08:07:36.892164 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2423 08:07:36.895698 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2424 08:07:36.898622 [-4] AVG Duty = 4969%(X100)
2425 08:07:36.898728
2426 08:07:36.902150 CH1 CLK Duty spec in!! Max-Min= 124%
2427 08:07:36.905758 [DutyScan_Calibration_Flow] ====Done====
2428 08:07:36.905868
2429 08:07:36.908646 [DutyScan_Calibration_Flow] k_type=1
2430 08:07:36.925310
2431 08:07:36.925428 ==DQS 0 ==
2432 08:07:36.928610 Final DQS duty delay cell = 0
2433 08:07:36.932015 [0] MAX Duty = 5094%(X100), DQS PI = 26
2434 08:07:36.935174 [0] MIN Duty = 4875%(X100), DQS PI = 0
2435 08:07:36.938474 [0] AVG Duty = 4984%(X100)
2436 08:07:36.938584
2437 08:07:36.938681 ==DQS 1 ==
2438 08:07:36.941955 Final DQS duty delay cell = 0
2439 08:07:36.945449 [0] MAX Duty = 5218%(X100), DQS PI = 20
2440 08:07:36.948514 [0] MIN Duty = 4969%(X100), DQS PI = 10
2441 08:07:36.952245 [0] AVG Duty = 5093%(X100)
2442 08:07:36.952350
2443 08:07:36.955311 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2444 08:07:36.955384
2445 08:07:36.958590 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2446 08:07:36.962234 [DutyScan_Calibration_Flow] ====Done====
2447 08:07:36.962329
2448 08:07:36.965178 [DutyScan_Calibration_Flow] k_type=3
2449 08:07:36.982025
2450 08:07:36.982109 ==DQM 0 ==
2451 08:07:36.984947 Final DQM duty delay cell = 0
2452 08:07:36.988438 [0] MAX Duty = 5156%(X100), DQS PI = 4
2453 08:07:36.991759 [0] MIN Duty = 5031%(X100), DQS PI = 0
2454 08:07:36.991833 [0] AVG Duty = 5093%(X100)
2455 08:07:36.994973
2456 08:07:36.995100 ==DQM 1 ==
2457 08:07:36.998447 Final DQM duty delay cell = 0
2458 08:07:37.001462 [0] MAX Duty = 5031%(X100), DQS PI = 16
2459 08:07:37.005126 [0] MIN Duty = 4907%(X100), DQS PI = 36
2460 08:07:37.005198 [0] AVG Duty = 4969%(X100)
2461 08:07:37.008608
2462 08:07:37.011623 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2463 08:07:37.011714
2464 08:07:37.015029 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2465 08:07:37.018816 [DutyScan_Calibration_Flow] ====Done====
2466 08:07:37.018937
2467 08:07:37.021746 [DutyScan_Calibration_Flow] k_type=2
2468 08:07:37.037741
2469 08:07:37.037826 ==DQ 0 ==
2470 08:07:37.041250 Final DQ duty delay cell = -4
2471 08:07:37.044427 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2472 08:07:37.047828 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2473 08:07:37.050801 [-4] AVG Duty = 5000%(X100)
2474 08:07:37.050871
2475 08:07:37.050932 ==DQ 1 ==
2476 08:07:37.054668 Final DQ duty delay cell = 0
2477 08:07:37.057768 [0] MAX Duty = 5125%(X100), DQS PI = 18
2478 08:07:37.061062 [0] MIN Duty = 4969%(X100), DQS PI = 10
2479 08:07:37.061140 [0] AVG Duty = 5047%(X100)
2480 08:07:37.064336
2481 08:07:37.067774 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2482 08:07:37.067853
2483 08:07:37.071546 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2484 08:07:37.074390 [DutyScan_Calibration_Flow] ====Done====
2485 08:07:37.077673 nWR fixed to 30
2486 08:07:37.077750 [ModeRegInit_LP4] CH0 RK0
2487 08:07:37.080746 [ModeRegInit_LP4] CH0 RK1
2488 08:07:37.084415 [ModeRegInit_LP4] CH1 RK0
2489 08:07:37.084491 [ModeRegInit_LP4] CH1 RK1
2490 08:07:37.087845 match AC timing 7
2491 08:07:37.090921 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2492 08:07:37.094457 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2493 08:07:37.101693 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2494 08:07:37.104456 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2495 08:07:37.111199 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2496 08:07:37.111303 ==
2497 08:07:37.114323 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 08:07:37.117657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 08:07:37.117763 ==
2500 08:07:37.124805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 08:07:37.127749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2502 08:07:37.137776 [CA 0] Center 39 (8~70) winsize 63
2503 08:07:37.141309 [CA 1] Center 39 (8~70) winsize 63
2504 08:07:37.144406 [CA 2] Center 35 (5~66) winsize 62
2505 08:07:37.148005 [CA 3] Center 34 (4~65) winsize 62
2506 08:07:37.151218 [CA 4] Center 33 (3~64) winsize 62
2507 08:07:37.154697 [CA 5] Center 32 (3~62) winsize 60
2508 08:07:37.154802
2509 08:07:37.157595 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2510 08:07:37.157672
2511 08:07:37.161504 [CATrainingPosCal] consider 1 rank data
2512 08:07:37.164762 u2DelayCellTimex100 = 270/100 ps
2513 08:07:37.167594 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2514 08:07:37.170931 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2515 08:07:37.177526 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2516 08:07:37.181140 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2517 08:07:37.184741 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2518 08:07:37.187715 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2519 08:07:37.187830
2520 08:07:37.191131 CA PerBit enable=1, Macro0, CA PI delay=32
2521 08:07:37.191242
2522 08:07:37.194837 [CBTSetCACLKResult] CA Dly = 32
2523 08:07:37.194921 CS Dly: 6 (0~37)
2524 08:07:37.197674 ==
2525 08:07:37.197752 Dram Type= 6, Freq= 0, CH_0, rank 1
2526 08:07:37.204275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 08:07:37.204353 ==
2528 08:07:37.207716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 08:07:37.214322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 08:07:37.223520 [CA 0] Center 38 (8~69) winsize 62
2531 08:07:37.227063 [CA 1] Center 38 (8~69) winsize 62
2532 08:07:37.230471 [CA 2] Center 35 (5~66) winsize 62
2533 08:07:37.233363 [CA 3] Center 34 (4~65) winsize 62
2534 08:07:37.236988 [CA 4] Center 33 (3~64) winsize 62
2535 08:07:37.240659 [CA 5] Center 32 (3~62) winsize 60
2536 08:07:37.240756
2537 08:07:37.243521 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2538 08:07:37.243629
2539 08:07:37.247220 [CATrainingPosCal] consider 2 rank data
2540 08:07:37.250890 u2DelayCellTimex100 = 270/100 ps
2541 08:07:37.253561 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2542 08:07:37.257345 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2543 08:07:37.263763 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2544 08:07:37.267207 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2545 08:07:37.270879 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2546 08:07:37.273649 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2547 08:07:37.273734
2548 08:07:37.277210 CA PerBit enable=1, Macro0, CA PI delay=32
2549 08:07:37.277309
2550 08:07:37.280349 [CBTSetCACLKResult] CA Dly = 32
2551 08:07:37.280452 CS Dly: 6 (0~38)
2552 08:07:37.280535
2553 08:07:37.283860 ----->DramcWriteLeveling(PI) begin...
2554 08:07:37.283945 ==
2555 08:07:37.287102 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 08:07:37.293889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 08:07:37.293993 ==
2558 08:07:37.297340 Write leveling (Byte 0): 34 => 34
2559 08:07:37.300389 Write leveling (Byte 1): 29 => 29
2560 08:07:37.300494 DramcWriteLeveling(PI) end<-----
2561 08:07:37.303934
2562 08:07:37.304012 ==
2563 08:07:37.306978 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 08:07:37.310733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 08:07:37.310835 ==
2566 08:07:37.313938 [Gating] SW mode calibration
2567 08:07:37.320407 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2568 08:07:37.323685 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2569 08:07:37.330564 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2570 08:07:37.333996 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2571 08:07:37.336961 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 08:07:37.343688 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 08:07:37.347138 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 08:07:37.350557 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 08:07:37.357259 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2576 08:07:37.360681 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2577 08:07:37.364049 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2578 08:07:37.370503 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 08:07:37.373707 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 08:07:37.377110 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 08:07:37.384029 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 08:07:37.387211 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 08:07:37.390640 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2584 08:07:37.394332 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2585 08:07:37.400440 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2586 08:07:37.404150 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 08:07:37.407277 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 08:07:37.414461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 08:07:37.417300 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 08:07:37.420496 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 08:07:37.427465 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 08:07:37.430938 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2593 08:07:37.434138 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2594 08:07:37.440533 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 08:07:37.443815 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 08:07:37.447278 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 08:07:37.454351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 08:07:37.457238 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 08:07:37.460754 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 08:07:37.464299 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 08:07:37.470619 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 08:07:37.473862 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 08:07:37.477363 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 08:07:37.483993 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 08:07:37.487520 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 08:07:37.490931 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 08:07:37.497583 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 08:07:37.500701 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2609 08:07:37.504178 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 08:07:37.507593 Total UI for P1: 0, mck2ui 16
2611 08:07:37.511025 best dqsien dly found for B0: ( 1, 3, 28)
2612 08:07:37.514214 Total UI for P1: 0, mck2ui 16
2613 08:07:37.517789 best dqsien dly found for B1: ( 1, 3, 30)
2614 08:07:37.520911 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2615 08:07:37.524290 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2616 08:07:37.524369
2617 08:07:37.527861 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2618 08:07:37.534393 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2619 08:07:37.534469 [Gating] SW calibration Done
2620 08:07:37.537516 ==
2621 08:07:37.537594 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 08:07:37.544107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 08:07:37.544210 ==
2624 08:07:37.544294 RX Vref Scan: 0
2625 08:07:37.544356
2626 08:07:37.547644 RX Vref 0 -> 0, step: 1
2627 08:07:37.547729
2628 08:07:37.550643 RX Delay -40 -> 252, step: 8
2629 08:07:37.554117 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2630 08:07:37.557802 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2631 08:07:37.560891 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2632 08:07:37.567868 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2633 08:07:37.570953 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2634 08:07:37.574249 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2635 08:07:37.577578 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2636 08:07:37.580899 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2637 08:07:37.587490 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2638 08:07:37.590614 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2639 08:07:37.594160 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2640 08:07:37.598076 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2641 08:07:37.600737 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2642 08:07:37.607452 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2643 08:07:37.610779 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2644 08:07:37.614823 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2645 08:07:37.614937 ==
2646 08:07:37.617868 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 08:07:37.620953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 08:07:37.621036 ==
2649 08:07:37.624472 DQS Delay:
2650 08:07:37.624576 DQS0 = 0, DQS1 = 0
2651 08:07:37.624670 DQM Delay:
2652 08:07:37.627870 DQM0 = 121, DQM1 = 113
2653 08:07:37.627955 DQ Delay:
2654 08:07:37.631228 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2655 08:07:37.634548 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2656 08:07:37.638156 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2657 08:07:37.644590 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2658 08:07:37.644676
2659 08:07:37.644777
2660 08:07:37.644877 ==
2661 08:07:37.648123 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 08:07:37.651209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 08:07:37.651294 ==
2664 08:07:37.651397
2665 08:07:37.651496
2666 08:07:37.654461 TX Vref Scan disable
2667 08:07:37.654546 == TX Byte 0 ==
2668 08:07:37.661017 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2669 08:07:37.664728 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2670 08:07:37.664814 == TX Byte 1 ==
2671 08:07:37.671513 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2672 08:07:37.674387 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2673 08:07:37.674463 ==
2674 08:07:37.677960 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 08:07:37.681462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 08:07:37.681538 ==
2677 08:07:37.694240 TX Vref=22, minBit 0, minWin=25, winSum=406
2678 08:07:37.697495 TX Vref=24, minBit 1, minWin=25, winSum=413
2679 08:07:37.701044 TX Vref=26, minBit 0, minWin=25, winSum=420
2680 08:07:37.704022 TX Vref=28, minBit 0, minWin=26, winSum=423
2681 08:07:37.707603 TX Vref=30, minBit 0, minWin=26, winSum=423
2682 08:07:37.711177 TX Vref=32, minBit 0, minWin=26, winSum=423
2683 08:07:37.717759 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
2684 08:07:37.717866
2685 08:07:37.721008 Final TX Range 1 Vref 28
2686 08:07:37.721110
2687 08:07:37.721204 ==
2688 08:07:37.724359 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 08:07:37.727714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 08:07:37.727828 ==
2691 08:07:37.727914
2692 08:07:37.727995
2693 08:07:37.731299 TX Vref Scan disable
2694 08:07:37.734172 == TX Byte 0 ==
2695 08:07:37.737771 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2696 08:07:37.741276 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2697 08:07:37.744915 == TX Byte 1 ==
2698 08:07:37.747650 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2699 08:07:37.751022 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2700 08:07:37.751105
2701 08:07:37.754624 [DATLAT]
2702 08:07:37.754724 Freq=1200, CH0 RK0
2703 08:07:37.754808
2704 08:07:37.758201 DATLAT Default: 0xd
2705 08:07:37.758299 0, 0xFFFF, sum = 0
2706 08:07:37.761112 1, 0xFFFF, sum = 0
2707 08:07:37.761228 2, 0xFFFF, sum = 0
2708 08:07:37.764411 3, 0xFFFF, sum = 0
2709 08:07:37.764495 4, 0xFFFF, sum = 0
2710 08:07:37.767990 5, 0xFFFF, sum = 0
2711 08:07:37.768088 6, 0xFFFF, sum = 0
2712 08:07:37.771061 7, 0xFFFF, sum = 0
2713 08:07:37.771174 8, 0xFFFF, sum = 0
2714 08:07:37.774831 9, 0xFFFF, sum = 0
2715 08:07:37.774917 10, 0xFFFF, sum = 0
2716 08:07:37.777714 11, 0xFFFF, sum = 0
2717 08:07:37.777801 12, 0x0, sum = 1
2718 08:07:37.781604 13, 0x0, sum = 2
2719 08:07:37.781689 14, 0x0, sum = 3
2720 08:07:37.784668 15, 0x0, sum = 4
2721 08:07:37.784754 best_step = 13
2722 08:07:37.784841
2723 08:07:37.784924 ==
2724 08:07:37.788061 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 08:07:37.794372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2726 08:07:37.794457 ==
2727 08:07:37.794543 RX Vref Scan: 1
2728 08:07:37.794625
2729 08:07:37.797593 Set Vref Range= 32 -> 127
2730 08:07:37.797704
2731 08:07:37.801064 RX Vref 32 -> 127, step: 1
2732 08:07:37.801149
2733 08:07:37.804346 RX Delay -13 -> 252, step: 4
2734 08:07:37.804430
2735 08:07:37.808175 Set Vref, RX VrefLevel [Byte0]: 32
2736 08:07:37.808256 [Byte1]: 32
2737 08:07:37.812527
2738 08:07:37.812606 Set Vref, RX VrefLevel [Byte0]: 33
2739 08:07:37.815936 [Byte1]: 33
2740 08:07:37.820538
2741 08:07:37.820618 Set Vref, RX VrefLevel [Byte0]: 34
2742 08:07:37.823815 [Byte1]: 34
2743 08:07:37.828058
2744 08:07:37.828137 Set Vref, RX VrefLevel [Byte0]: 35
2745 08:07:37.831408 [Byte1]: 35
2746 08:07:37.835963
2747 08:07:37.836043 Set Vref, RX VrefLevel [Byte0]: 36
2748 08:07:37.839736 [Byte1]: 36
2749 08:07:37.844055
2750 08:07:37.844163 Set Vref, RX VrefLevel [Byte0]: 37
2751 08:07:37.847094 [Byte1]: 37
2752 08:07:37.852268
2753 08:07:37.852373 Set Vref, RX VrefLevel [Byte0]: 38
2754 08:07:37.855446 [Byte1]: 38
2755 08:07:37.859938
2756 08:07:37.860044 Set Vref, RX VrefLevel [Byte0]: 39
2757 08:07:37.863158 [Byte1]: 39
2758 08:07:37.867984
2759 08:07:37.868088 Set Vref, RX VrefLevel [Byte0]: 40
2760 08:07:37.870778 [Byte1]: 40
2761 08:07:37.875541
2762 08:07:37.875661 Set Vref, RX VrefLevel [Byte0]: 41
2763 08:07:37.879127 [Byte1]: 41
2764 08:07:37.883677
2765 08:07:37.883757 Set Vref, RX VrefLevel [Byte0]: 42
2766 08:07:37.886623 [Byte1]: 42
2767 08:07:37.891357
2768 08:07:37.891461 Set Vref, RX VrefLevel [Byte0]: 43
2769 08:07:37.894886 [Byte1]: 43
2770 08:07:37.899575
2771 08:07:37.899684 Set Vref, RX VrefLevel [Byte0]: 44
2772 08:07:37.902742 [Byte1]: 44
2773 08:07:37.907060
2774 08:07:37.907166 Set Vref, RX VrefLevel [Byte0]: 45
2775 08:07:37.910499 [Byte1]: 45
2776 08:07:37.915139
2777 08:07:37.915214 Set Vref, RX VrefLevel [Byte0]: 46
2778 08:07:37.918335 [Byte1]: 46
2779 08:07:37.923199
2780 08:07:37.923274 Set Vref, RX VrefLevel [Byte0]: 47
2781 08:07:37.925983 [Byte1]: 47
2782 08:07:37.931018
2783 08:07:37.931125 Set Vref, RX VrefLevel [Byte0]: 48
2784 08:07:37.934148 [Byte1]: 48
2785 08:07:37.939049
2786 08:07:37.939162 Set Vref, RX VrefLevel [Byte0]: 49
2787 08:07:37.942110 [Byte1]: 49
2788 08:07:37.946858
2789 08:07:37.946967 Set Vref, RX VrefLevel [Byte0]: 50
2790 08:07:37.949771 [Byte1]: 50
2791 08:07:37.954825
2792 08:07:37.954927 Set Vref, RX VrefLevel [Byte0]: 51
2793 08:07:37.958155 [Byte1]: 51
2794 08:07:37.962180
2795 08:07:37.962292 Set Vref, RX VrefLevel [Byte0]: 52
2796 08:07:37.966069 [Byte1]: 52
2797 08:07:37.970686
2798 08:07:37.970796 Set Vref, RX VrefLevel [Byte0]: 53
2799 08:07:37.973393 [Byte1]: 53
2800 08:07:37.978027
2801 08:07:37.978137 Set Vref, RX VrefLevel [Byte0]: 54
2802 08:07:37.981590 [Byte1]: 54
2803 08:07:37.985924
2804 08:07:37.986002 Set Vref, RX VrefLevel [Byte0]: 55
2805 08:07:37.989279 [Byte1]: 55
2806 08:07:37.993801
2807 08:07:37.993914 Set Vref, RX VrefLevel [Byte0]: 56
2808 08:07:37.997255 [Byte1]: 56
2809 08:07:38.001900
2810 08:07:38.002001 Set Vref, RX VrefLevel [Byte0]: 57
2811 08:07:38.004872 [Byte1]: 57
2812 08:07:38.009899
2813 08:07:38.010002 Set Vref, RX VrefLevel [Byte0]: 58
2814 08:07:38.012874 [Byte1]: 58
2815 08:07:38.017577
2816 08:07:38.017687 Set Vref, RX VrefLevel [Byte0]: 59
2817 08:07:38.020992 [Byte1]: 59
2818 08:07:38.025434
2819 08:07:38.025535 Set Vref, RX VrefLevel [Byte0]: 60
2820 08:07:38.029058 [Byte1]: 60
2821 08:07:38.033604
2822 08:07:38.033715 Set Vref, RX VrefLevel [Byte0]: 61
2823 08:07:38.036894 [Byte1]: 61
2824 08:07:38.041097
2825 08:07:38.041182 Set Vref, RX VrefLevel [Byte0]: 62
2826 08:07:38.044798 [Byte1]: 62
2827 08:07:38.049376
2828 08:07:38.049471 Set Vref, RX VrefLevel [Byte0]: 63
2829 08:07:38.052709 [Byte1]: 63
2830 08:07:38.057374
2831 08:07:38.057486 Set Vref, RX VrefLevel [Byte0]: 64
2832 08:07:38.060418 [Byte1]: 64
2833 08:07:38.065036
2834 08:07:38.065146 Set Vref, RX VrefLevel [Byte0]: 65
2835 08:07:38.068122 [Byte1]: 65
2836 08:07:38.072877
2837 08:07:38.072980 Set Vref, RX VrefLevel [Byte0]: 66
2838 08:07:38.075920 [Byte1]: 66
2839 08:07:38.080646
2840 08:07:38.080725 Set Vref, RX VrefLevel [Byte0]: 67
2841 08:07:38.084003 [Byte1]: 67
2842 08:07:38.088703
2843 08:07:38.088815 Set Vref, RX VrefLevel [Byte0]: 68
2844 08:07:38.092017 [Byte1]: 68
2845 08:07:38.096803
2846 08:07:38.096896 Final RX Vref Byte 0 = 55 to rank0
2847 08:07:38.099996 Final RX Vref Byte 1 = 47 to rank0
2848 08:07:38.103237 Final RX Vref Byte 0 = 55 to rank1
2849 08:07:38.106740 Final RX Vref Byte 1 = 47 to rank1==
2850 08:07:38.109642 Dram Type= 6, Freq= 0, CH_0, rank 0
2851 08:07:38.116544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 08:07:38.116642 ==
2853 08:07:38.116710 DQS Delay:
2854 08:07:38.116772 DQS0 = 0, DQS1 = 0
2855 08:07:38.120022 DQM Delay:
2856 08:07:38.120097 DQM0 = 120, DQM1 = 111
2857 08:07:38.123194 DQ Delay:
2858 08:07:38.126463 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2859 08:07:38.129993 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2860 08:07:38.133301 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
2861 08:07:38.136640 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2862 08:07:38.136729
2863 08:07:38.136800
2864 08:07:38.143075 [DQSOSCAuto] RK0, (LSB)MR18= 0x140e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2865 08:07:38.147113 CH0 RK0: MR19=404, MR18=140E
2866 08:07:38.153121 CH0_RK0: MR19=0x404, MR18=0x140E, DQSOSC=402, MR23=63, INC=40, DEC=27
2867 08:07:38.153201
2868 08:07:38.156539 ----->DramcWriteLeveling(PI) begin...
2869 08:07:38.156647 ==
2870 08:07:38.159717 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 08:07:38.163375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 08:07:38.166836 ==
2873 08:07:38.166942 Write leveling (Byte 0): 35 => 35
2874 08:07:38.169593 Write leveling (Byte 1): 30 => 30
2875 08:07:38.173117 DramcWriteLeveling(PI) end<-----
2876 08:07:38.173219
2877 08:07:38.173305 ==
2878 08:07:38.176912 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 08:07:38.183148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 08:07:38.183260 ==
2881 08:07:38.183353 [Gating] SW mode calibration
2882 08:07:38.193431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2883 08:07:38.196354 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2884 08:07:38.199854 0 15 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
2885 08:07:38.206808 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 08:07:38.209634 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 08:07:38.213126 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 08:07:38.220065 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 08:07:38.223552 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 08:07:38.226435 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 08:07:38.233652 0 15 28 | B1->B0 | 3030 3030 | 1 0 | (1 0) (0 0)
2892 08:07:38.236544 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2893 08:07:38.240085 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 08:07:38.246866 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 08:07:38.250033 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 08:07:38.253611 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 08:07:38.257125 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 08:07:38.263539 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2899 08:07:38.266833 1 0 28 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
2900 08:07:38.270004 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2901 08:07:38.277126 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 08:07:38.279961 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 08:07:38.283561 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 08:07:38.290382 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 08:07:38.293331 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 08:07:38.297051 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 08:07:38.303275 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2908 08:07:38.306753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 08:07:38.310334 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 08:07:38.316580 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 08:07:38.320179 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 08:07:38.323663 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 08:07:38.330139 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 08:07:38.333481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 08:07:38.337100 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 08:07:38.343750 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 08:07:38.346772 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 08:07:38.349960 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 08:07:38.356603 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 08:07:38.360089 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 08:07:38.363539 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 08:07:38.366754 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2923 08:07:38.373650 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2924 08:07:38.377219 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2925 08:07:38.380550 Total UI for P1: 0, mck2ui 16
2926 08:07:38.383905 best dqsien dly found for B1: ( 1, 3, 26)
2927 08:07:38.387029 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 08:07:38.390043 Total UI for P1: 0, mck2ui 16
2929 08:07:38.393394 best dqsien dly found for B0: ( 1, 3, 28)
2930 08:07:38.397074 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2931 08:07:38.400068 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2932 08:07:38.400173
2933 08:07:38.407133 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2934 08:07:38.410258 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2935 08:07:38.410364 [Gating] SW calibration Done
2936 08:07:38.413865 ==
2937 08:07:38.416820 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 08:07:38.420146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 08:07:38.420283 ==
2940 08:07:38.420383 RX Vref Scan: 0
2941 08:07:38.420455
2942 08:07:38.423760 RX Vref 0 -> 0, step: 1
2943 08:07:38.423836
2944 08:07:38.427040 RX Delay -40 -> 252, step: 8
2945 08:07:38.430565 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2946 08:07:38.434022 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2947 08:07:38.436819 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2948 08:07:38.444053 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2949 08:07:38.446893 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2950 08:07:38.450399 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2951 08:07:38.454135 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2952 08:07:38.457166 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2953 08:07:38.463511 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2954 08:07:38.467077 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2955 08:07:38.470550 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2956 08:07:38.473899 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2957 08:07:38.476757 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2958 08:07:38.483586 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2959 08:07:38.487058 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2960 08:07:38.490164 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2961 08:07:38.490291 ==
2962 08:07:38.493536 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 08:07:38.497383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 08:07:38.497507 ==
2965 08:07:38.500488 DQS Delay:
2966 08:07:38.500597 DQS0 = 0, DQS1 = 0
2967 08:07:38.503962 DQM Delay:
2968 08:07:38.504055 DQM0 = 123, DQM1 = 112
2969 08:07:38.504119 DQ Delay:
2970 08:07:38.507478 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2971 08:07:38.510396 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2972 08:07:38.517348 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2973 08:07:38.520830 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2974 08:07:38.520931
2975 08:07:38.521028
2976 08:07:38.521117 ==
2977 08:07:38.523649 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 08:07:38.527038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 08:07:38.527167 ==
2980 08:07:38.527279
2981 08:07:38.527392
2982 08:07:38.530667 TX Vref Scan disable
2983 08:07:38.530793 == TX Byte 0 ==
2984 08:07:38.537270 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2985 08:07:38.540462 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2986 08:07:38.540580 == TX Byte 1 ==
2987 08:07:38.547306 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2988 08:07:38.550750 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2989 08:07:38.550868 ==
2990 08:07:38.554249 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 08:07:38.557228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 08:07:38.557323 ==
2993 08:07:38.570626 TX Vref=22, minBit 1, minWin=24, winSum=411
2994 08:07:38.574268 TX Vref=24, minBit 1, minWin=25, winSum=416
2995 08:07:38.577197 TX Vref=26, minBit 2, minWin=26, winSum=426
2996 08:07:38.580677 TX Vref=28, minBit 13, minWin=25, winSum=423
2997 08:07:38.584216 TX Vref=30, minBit 1, minWin=26, winSum=426
2998 08:07:38.587561 TX Vref=32, minBit 5, minWin=25, winSum=419
2999 08:07:38.594525 [TxChooseVref] Worse bit 2, Min win 26, Win sum 426, Final Vref 26
3000 08:07:38.594649
3001 08:07:38.597687 Final TX Range 1 Vref 26
3002 08:07:38.597843
3003 08:07:38.597968 ==
3004 08:07:38.600822 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 08:07:38.604315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 08:07:38.604437 ==
3007 08:07:38.604552
3008 08:07:38.604671
3009 08:07:38.607736 TX Vref Scan disable
3010 08:07:38.610695 == TX Byte 0 ==
3011 08:07:38.613953 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3012 08:07:38.617424 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3013 08:07:38.620494 == TX Byte 1 ==
3014 08:07:38.624109 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3015 08:07:38.627740 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3016 08:07:38.627845
3017 08:07:38.631032 [DATLAT]
3018 08:07:38.631170 Freq=1200, CH0 RK1
3019 08:07:38.631244
3020 08:07:38.634624 DATLAT Default: 0xd
3021 08:07:38.634724 0, 0xFFFF, sum = 0
3022 08:07:38.637740 1, 0xFFFF, sum = 0
3023 08:07:38.637857 2, 0xFFFF, sum = 0
3024 08:07:38.641021 3, 0xFFFF, sum = 0
3025 08:07:38.641106 4, 0xFFFF, sum = 0
3026 08:07:38.644754 5, 0xFFFF, sum = 0
3027 08:07:38.644832 6, 0xFFFF, sum = 0
3028 08:07:38.647905 7, 0xFFFF, sum = 0
3029 08:07:38.647988 8, 0xFFFF, sum = 0
3030 08:07:38.651247 9, 0xFFFF, sum = 0
3031 08:07:38.651355 10, 0xFFFF, sum = 0
3032 08:07:38.654360 11, 0xFFFF, sum = 0
3033 08:07:38.654467 12, 0x0, sum = 1
3034 08:07:38.657914 13, 0x0, sum = 2
3035 08:07:38.658018 14, 0x0, sum = 3
3036 08:07:38.660879 15, 0x0, sum = 4
3037 08:07:38.660964 best_step = 13
3038 08:07:38.661029
3039 08:07:38.661089 ==
3040 08:07:38.664376 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 08:07:38.670943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 08:07:38.671026 ==
3043 08:07:38.671116 RX Vref Scan: 0
3044 08:07:38.671208
3045 08:07:38.674667 RX Vref 0 -> 0, step: 1
3046 08:07:38.674749
3047 08:07:38.677666 RX Delay -13 -> 252, step: 4
3048 08:07:38.681158 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3049 08:07:38.684567 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3050 08:07:38.690932 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3051 08:07:38.694434 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3052 08:07:38.697621 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3053 08:07:38.701349 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3054 08:07:38.704647 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3055 08:07:38.707571 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3056 08:07:38.714879 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3057 08:07:38.718137 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3058 08:07:38.721037 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3059 08:07:38.724806 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3060 08:07:38.728307 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3061 08:07:38.734746 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3062 08:07:38.738133 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3063 08:07:38.741794 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3064 08:07:38.741905 ==
3065 08:07:38.744488 Dram Type= 6, Freq= 0, CH_0, rank 1
3066 08:07:38.747961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 08:07:38.748036 ==
3068 08:07:38.751550 DQS Delay:
3069 08:07:38.751655 DQS0 = 0, DQS1 = 0
3070 08:07:38.754913 DQM Delay:
3071 08:07:38.755019 DQM0 = 120, DQM1 = 109
3072 08:07:38.757924 DQ Delay:
3073 08:07:38.761402 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3074 08:07:38.765227 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3075 08:07:38.767985 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3076 08:07:38.771076 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3077 08:07:38.771159
3078 08:07:38.771223
3079 08:07:38.778039 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3080 08:07:38.781131 CH0 RK1: MR19=403, MR18=10F1
3081 08:07:38.787885 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3082 08:07:38.791179 [RxdqsGatingPostProcess] freq 1200
3083 08:07:38.798191 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3084 08:07:38.798274 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 08:07:38.801244 best DQS1 dly(2T, 0.5T) = (0, 11)
3086 08:07:38.804554 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 08:07:38.807877 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3088 08:07:38.811427 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 08:07:38.815159 best DQS1 dly(2T, 0.5T) = (0, 11)
3090 08:07:38.817990 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 08:07:38.821636 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3092 08:07:38.824561 Pre-setting of DQS Precalculation
3093 08:07:38.828017 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3094 08:07:38.831217 ==
3095 08:07:38.835160 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 08:07:38.838400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 08:07:38.838532 ==
3098 08:07:38.841957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 08:07:38.848068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3100 08:07:38.857517 [CA 0] Center 37 (7~68) winsize 62
3101 08:07:38.861017 [CA 1] Center 37 (7~68) winsize 62
3102 08:07:38.864121 [CA 2] Center 35 (5~65) winsize 61
3103 08:07:38.867206 [CA 3] Center 34 (4~64) winsize 61
3104 08:07:38.870787 [CA 4] Center 34 (4~64) winsize 61
3105 08:07:38.873855 [CA 5] Center 33 (3~63) winsize 61
3106 08:07:38.873965
3107 08:07:38.877388 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3108 08:07:38.877495
3109 08:07:38.880730 [CATrainingPosCal] consider 1 rank data
3110 08:07:38.884332 u2DelayCellTimex100 = 270/100 ps
3111 08:07:38.887444 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3112 08:07:38.890891 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 08:07:38.893840 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3114 08:07:38.900753 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 08:07:38.903966 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 08:07:38.907782 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3117 08:07:38.907910
3118 08:07:38.910734 CA PerBit enable=1, Macro0, CA PI delay=33
3119 08:07:38.910854
3120 08:07:38.914027 [CBTSetCACLKResult] CA Dly = 33
3121 08:07:38.914131 CS Dly: 7 (0~38)
3122 08:07:38.914224 ==
3123 08:07:38.917872 Dram Type= 6, Freq= 0, CH_1, rank 1
3124 08:07:38.924533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 08:07:38.924617 ==
3126 08:07:38.927912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3127 08:07:38.934200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3128 08:07:38.943157 [CA 0] Center 37 (7~68) winsize 62
3129 08:07:38.946219 [CA 1] Center 38 (7~69) winsize 63
3130 08:07:38.949855 [CA 2] Center 35 (5~65) winsize 61
3131 08:07:38.952997 [CA 3] Center 34 (4~65) winsize 62
3132 08:07:38.955852 [CA 4] Center 34 (4~65) winsize 62
3133 08:07:38.959241 [CA 5] Center 33 (4~63) winsize 60
3134 08:07:38.959357
3135 08:07:38.963065 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3136 08:07:38.963151
3137 08:07:38.966284 [CATrainingPosCal] consider 2 rank data
3138 08:07:38.969421 u2DelayCellTimex100 = 270/100 ps
3139 08:07:38.973167 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3140 08:07:38.976340 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3141 08:07:38.982899 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3142 08:07:38.986430 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 08:07:38.989683 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3144 08:07:38.992896 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3145 08:07:38.992979
3146 08:07:38.995991 CA PerBit enable=1, Macro0, CA PI delay=33
3147 08:07:38.996075
3148 08:07:38.999923 [CBTSetCACLKResult] CA Dly = 33
3149 08:07:39.000008 CS Dly: 8 (0~41)
3150 08:07:39.000073
3151 08:07:39.002728 ----->DramcWriteLeveling(PI) begin...
3152 08:07:39.006169 ==
3153 08:07:39.006270 Dram Type= 6, Freq= 0, CH_1, rank 0
3154 08:07:39.013198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 08:07:39.013311 ==
3156 08:07:39.016081 Write leveling (Byte 0): 27 => 27
3157 08:07:39.019669 Write leveling (Byte 1): 27 => 27
3158 08:07:39.019811 DramcWriteLeveling(PI) end<-----
3159 08:07:39.022864
3160 08:07:39.023000 ==
3161 08:07:39.026434 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 08:07:39.029813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 08:07:39.029920 ==
3164 08:07:39.033185 [Gating] SW mode calibration
3165 08:07:39.039847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3166 08:07:39.043073 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3167 08:07:39.049468 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3168 08:07:39.053034 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 08:07:39.056425 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 08:07:39.062953 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 08:07:39.066711 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 08:07:39.069619 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 08:07:39.076487 0 15 24 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
3174 08:07:39.079981 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 08:07:39.083086 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 08:07:39.089539 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 08:07:39.093169 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 08:07:39.096685 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 08:07:39.099984 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 08:07:39.106413 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 08:07:39.110026 1 0 24 | B1->B0 | 2e2e 3c3c | 1 0 | (0 0) (0 0)
3182 08:07:39.113120 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 08:07:39.119545 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 08:07:39.123084 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 08:07:39.126529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 08:07:39.133506 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 08:07:39.137001 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 08:07:39.140327 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 08:07:39.146813 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3190 08:07:39.150238 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3191 08:07:39.153541 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 08:07:39.159874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 08:07:39.163723 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 08:07:39.166986 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 08:07:39.173703 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 08:07:39.176670 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 08:07:39.180040 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 08:07:39.183443 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 08:07:39.190442 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 08:07:39.193319 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 08:07:39.196856 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 08:07:39.203264 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 08:07:39.206914 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 08:07:39.209990 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 08:07:39.216568 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3206 08:07:39.220103 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3207 08:07:39.223780 Total UI for P1: 0, mck2ui 16
3208 08:07:39.227027 best dqsien dly found for B1: ( 1, 3, 24)
3209 08:07:39.230417 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 08:07:39.233514 Total UI for P1: 0, mck2ui 16
3211 08:07:39.236694 best dqsien dly found for B0: ( 1, 3, 26)
3212 08:07:39.240068 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3213 08:07:39.243547 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3214 08:07:39.243628
3215 08:07:39.246994 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3216 08:07:39.253499 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3217 08:07:39.253608 [Gating] SW calibration Done
3218 08:07:39.253680 ==
3219 08:07:39.257039 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 08:07:39.263952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 08:07:39.264042 ==
3222 08:07:39.264114 RX Vref Scan: 0
3223 08:07:39.264188
3224 08:07:39.266852 RX Vref 0 -> 0, step: 1
3225 08:07:39.266925
3226 08:07:39.270245 RX Delay -40 -> 252, step: 8
3227 08:07:39.273985 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3228 08:07:39.277239 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3229 08:07:39.280950 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3230 08:07:39.283920 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3231 08:07:39.290593 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3232 08:07:39.293819 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3233 08:07:39.297262 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3234 08:07:39.300200 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3235 08:07:39.303912 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3236 08:07:39.310552 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3237 08:07:39.314091 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3238 08:07:39.317076 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3239 08:07:39.320415 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3240 08:07:39.323390 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3241 08:07:39.330783 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3242 08:07:39.333506 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3243 08:07:39.333590 ==
3244 08:07:39.336671 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 08:07:39.340720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 08:07:39.340804 ==
3247 08:07:39.343941 DQS Delay:
3248 08:07:39.344031 DQS0 = 0, DQS1 = 0
3249 08:07:39.344096 DQM Delay:
3250 08:07:39.346908 DQM0 = 119, DQM1 = 116
3251 08:07:39.347011 DQ Delay:
3252 08:07:39.350509 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3253 08:07:39.354311 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3254 08:07:39.356998 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3255 08:07:39.363570 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3256 08:07:39.363684
3257 08:07:39.363792
3258 08:07:39.363856 ==
3259 08:07:39.367270 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 08:07:39.370398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 08:07:39.370517 ==
3262 08:07:39.370612
3263 08:07:39.370710
3264 08:07:39.374314 TX Vref Scan disable
3265 08:07:39.374440 == TX Byte 0 ==
3266 08:07:39.380430 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 08:07:39.383747 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 08:07:39.383834 == TX Byte 1 ==
3269 08:07:39.390583 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3270 08:07:39.393823 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3271 08:07:39.393910 ==
3272 08:07:39.397299 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 08:07:39.400974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 08:07:39.401057 ==
3275 08:07:39.413215 TX Vref=22, minBit 9, minWin=25, winSum=416
3276 08:07:39.416353 TX Vref=24, minBit 9, minWin=24, winSum=417
3277 08:07:39.419925 TX Vref=26, minBit 9, minWin=25, winSum=421
3278 08:07:39.423040 TX Vref=28, minBit 1, minWin=26, winSum=426
3279 08:07:39.426527 TX Vref=30, minBit 1, minWin=26, winSum=428
3280 08:07:39.430020 TX Vref=32, minBit 1, minWin=26, winSum=431
3281 08:07:39.436581 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 32
3282 08:07:39.436667
3283 08:07:39.439574 Final TX Range 1 Vref 32
3284 08:07:39.439658
3285 08:07:39.439723 ==
3286 08:07:39.443270 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 08:07:39.446628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 08:07:39.446711 ==
3289 08:07:39.446777
3290 08:07:39.446838
3291 08:07:39.449511 TX Vref Scan disable
3292 08:07:39.453327 == TX Byte 0 ==
3293 08:07:39.456402 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3294 08:07:39.459937 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3295 08:07:39.463235 == TX Byte 1 ==
3296 08:07:39.466928 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3297 08:07:39.470033 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3298 08:07:39.470144
3299 08:07:39.473362 [DATLAT]
3300 08:07:39.473463 Freq=1200, CH1 RK0
3301 08:07:39.473564
3302 08:07:39.476837 DATLAT Default: 0xd
3303 08:07:39.476951 0, 0xFFFF, sum = 0
3304 08:07:39.480445 1, 0xFFFF, sum = 0
3305 08:07:39.480550 2, 0xFFFF, sum = 0
3306 08:07:39.483249 3, 0xFFFF, sum = 0
3307 08:07:39.483357 4, 0xFFFF, sum = 0
3308 08:07:39.486543 5, 0xFFFF, sum = 0
3309 08:07:39.486652 6, 0xFFFF, sum = 0
3310 08:07:39.489985 7, 0xFFFF, sum = 0
3311 08:07:39.490094 8, 0xFFFF, sum = 0
3312 08:07:39.493812 9, 0xFFFF, sum = 0
3313 08:07:39.493921 10, 0xFFFF, sum = 0
3314 08:07:39.496808 11, 0xFFFF, sum = 0
3315 08:07:39.496916 12, 0x0, sum = 1
3316 08:07:39.499938 13, 0x0, sum = 2
3317 08:07:39.500029 14, 0x0, sum = 3
3318 08:07:39.503379 15, 0x0, sum = 4
3319 08:07:39.503454 best_step = 13
3320 08:07:39.503517
3321 08:07:39.503576 ==
3322 08:07:39.507116 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 08:07:39.513029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 08:07:39.513121 ==
3325 08:07:39.513215 RX Vref Scan: 1
3326 08:07:39.513305
3327 08:07:39.516311 Set Vref Range= 32 -> 127
3328 08:07:39.516414
3329 08:07:39.520068 RX Vref 32 -> 127, step: 1
3330 08:07:39.520156
3331 08:07:39.520223 RX Delay -5 -> 252, step: 4
3332 08:07:39.523333
3333 08:07:39.523408 Set Vref, RX VrefLevel [Byte0]: 32
3334 08:07:39.526780 [Byte1]: 32
3335 08:07:39.530990
3336 08:07:39.531066 Set Vref, RX VrefLevel [Byte0]: 33
3337 08:07:39.534289 [Byte1]: 33
3338 08:07:39.538988
3339 08:07:39.539071 Set Vref, RX VrefLevel [Byte0]: 34
3340 08:07:39.542342 [Byte1]: 34
3341 08:07:39.546525
3342 08:07:39.546650 Set Vref, RX VrefLevel [Byte0]: 35
3343 08:07:39.550279 [Byte1]: 35
3344 08:07:39.554495
3345 08:07:39.554613 Set Vref, RX VrefLevel [Byte0]: 36
3346 08:07:39.557785 [Byte1]: 36
3347 08:07:39.562295
3348 08:07:39.562425 Set Vref, RX VrefLevel [Byte0]: 37
3349 08:07:39.565853 [Byte1]: 37
3350 08:07:39.570058
3351 08:07:39.570175 Set Vref, RX VrefLevel [Byte0]: 38
3352 08:07:39.573531 [Byte1]: 38
3353 08:07:39.578258
3354 08:07:39.578384 Set Vref, RX VrefLevel [Byte0]: 39
3355 08:07:39.581660 [Byte1]: 39
3356 08:07:39.586255
3357 08:07:39.586386 Set Vref, RX VrefLevel [Byte0]: 40
3358 08:07:39.589210 [Byte1]: 40
3359 08:07:39.593845
3360 08:07:39.593969 Set Vref, RX VrefLevel [Byte0]: 41
3361 08:07:39.597062 [Byte1]: 41
3362 08:07:39.602055
3363 08:07:39.602178 Set Vref, RX VrefLevel [Byte0]: 42
3364 08:07:39.605282 [Byte1]: 42
3365 08:07:39.609347
3366 08:07:39.609473 Set Vref, RX VrefLevel [Byte0]: 43
3367 08:07:39.612889 [Byte1]: 43
3368 08:07:39.617541
3369 08:07:39.617673 Set Vref, RX VrefLevel [Byte0]: 44
3370 08:07:39.620794 [Byte1]: 44
3371 08:07:39.625260
3372 08:07:39.625379 Set Vref, RX VrefLevel [Byte0]: 45
3373 08:07:39.628286 [Byte1]: 45
3374 08:07:39.632834
3375 08:07:39.632959 Set Vref, RX VrefLevel [Byte0]: 46
3376 08:07:39.636642 [Byte1]: 46
3377 08:07:39.641221
3378 08:07:39.641347 Set Vref, RX VrefLevel [Byte0]: 47
3379 08:07:39.644098 [Byte1]: 47
3380 08:07:39.649010
3381 08:07:39.649134 Set Vref, RX VrefLevel [Byte0]: 48
3382 08:07:39.652144 [Byte1]: 48
3383 08:07:39.656903
3384 08:07:39.657029 Set Vref, RX VrefLevel [Byte0]: 49
3385 08:07:39.659954 [Byte1]: 49
3386 08:07:39.664525
3387 08:07:39.664653 Set Vref, RX VrefLevel [Byte0]: 50
3388 08:07:39.667999 [Byte1]: 50
3389 08:07:39.672479
3390 08:07:39.672607 Set Vref, RX VrefLevel [Byte0]: 51
3391 08:07:39.675781 [Byte1]: 51
3392 08:07:39.679856
3393 08:07:39.679979 Set Vref, RX VrefLevel [Byte0]: 52
3394 08:07:39.683387 [Byte1]: 52
3395 08:07:39.687828
3396 08:07:39.687957 Set Vref, RX VrefLevel [Byte0]: 53
3397 08:07:39.691398 [Byte1]: 53
3398 08:07:39.695678
3399 08:07:39.695799 Set Vref, RX VrefLevel [Byte0]: 54
3400 08:07:39.699387 [Byte1]: 54
3401 08:07:39.703505
3402 08:07:39.703627 Set Vref, RX VrefLevel [Byte0]: 55
3403 08:07:39.706758 [Byte1]: 55
3404 08:07:39.711781
3405 08:07:39.711906 Set Vref, RX VrefLevel [Byte0]: 56
3406 08:07:39.714631 [Byte1]: 56
3407 08:07:39.719132
3408 08:07:39.719256 Set Vref, RX VrefLevel [Byte0]: 57
3409 08:07:39.722632 [Byte1]: 57
3410 08:07:39.727398
3411 08:07:39.727516 Set Vref, RX VrefLevel [Byte0]: 58
3412 08:07:39.730493 [Byte1]: 58
3413 08:07:39.734911
3414 08:07:39.735038 Set Vref, RX VrefLevel [Byte0]: 59
3415 08:07:39.738236 [Byte1]: 59
3416 08:07:39.743290
3417 08:07:39.743412 Set Vref, RX VrefLevel [Byte0]: 60
3418 08:07:39.746354 [Byte1]: 60
3419 08:07:39.750588
3420 08:07:39.750710 Set Vref, RX VrefLevel [Byte0]: 61
3421 08:07:39.754422 [Byte1]: 61
3422 08:07:39.758680
3423 08:07:39.758800 Set Vref, RX VrefLevel [Byte0]: 62
3424 08:07:39.762262 [Byte1]: 62
3425 08:07:39.766351
3426 08:07:39.766472 Set Vref, RX VrefLevel [Byte0]: 63
3427 08:07:39.769713 [Byte1]: 63
3428 08:07:39.774430
3429 08:07:39.774548 Set Vref, RX VrefLevel [Byte0]: 64
3430 08:07:39.777778 [Byte1]: 64
3431 08:07:39.782492
3432 08:07:39.782615 Set Vref, RX VrefLevel [Byte0]: 65
3433 08:07:39.785326 [Byte1]: 65
3434 08:07:39.790297
3435 08:07:39.790423 Set Vref, RX VrefLevel [Byte0]: 66
3436 08:07:39.793461 [Byte1]: 66
3437 08:07:39.797899
3438 08:07:39.798005 Set Vref, RX VrefLevel [Byte0]: 67
3439 08:07:39.801368 [Byte1]: 67
3440 08:07:39.806144
3441 08:07:39.806220 Set Vref, RX VrefLevel [Byte0]: 68
3442 08:07:39.809103 [Byte1]: 68
3443 08:07:39.814014
3444 08:07:39.814087 Set Vref, RX VrefLevel [Byte0]: 69
3445 08:07:39.817025 [Byte1]: 69
3446 08:07:39.821167
3447 08:07:39.821240 Set Vref, RX VrefLevel [Byte0]: 70
3448 08:07:39.824899 [Byte1]: 70
3449 08:07:39.829451
3450 08:07:39.829526 Final RX Vref Byte 0 = 54 to rank0
3451 08:07:39.832474 Final RX Vref Byte 1 = 54 to rank0
3452 08:07:39.835807 Final RX Vref Byte 0 = 54 to rank1
3453 08:07:39.839198 Final RX Vref Byte 1 = 54 to rank1==
3454 08:07:39.842525 Dram Type= 6, Freq= 0, CH_1, rank 0
3455 08:07:39.849221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 08:07:39.849298 ==
3457 08:07:39.849362 DQS Delay:
3458 08:07:39.849422 DQS0 = 0, DQS1 = 0
3459 08:07:39.852623 DQM Delay:
3460 08:07:39.852689 DQM0 = 120, DQM1 = 117
3461 08:07:39.855786 DQ Delay:
3462 08:07:39.859360 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3463 08:07:39.862999 DQ4 =122, DQ5 =130, DQ6 =128, DQ7 =120
3464 08:07:39.866043 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3465 08:07:39.869076 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3466 08:07:39.869150
3467 08:07:39.869212
3468 08:07:39.875776 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3469 08:07:39.879245 CH1 RK0: MR19=404, MR18=114
3470 08:07:39.886435 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3471 08:07:39.886513
3472 08:07:39.889331 ----->DramcWriteLeveling(PI) begin...
3473 08:07:39.889417 ==
3474 08:07:39.892403 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 08:07:39.895935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3476 08:07:39.896037 ==
3477 08:07:39.899083 Write leveling (Byte 0): 25 => 25
3478 08:07:39.902379 Write leveling (Byte 1): 28 => 28
3479 08:07:39.905747 DramcWriteLeveling(PI) end<-----
3480 08:07:39.905832
3481 08:07:39.905897 ==
3482 08:07:39.909221 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 08:07:39.915813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 08:07:39.915892 ==
3485 08:07:39.915962 [Gating] SW mode calibration
3486 08:07:39.926265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3487 08:07:39.929820 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3488 08:07:39.932951 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 08:07:39.939577 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 08:07:39.942834 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 08:07:39.946743 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 08:07:39.953215 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 08:07:39.956186 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 08:07:39.959933 0 15 24 | B1->B0 | 2c2c 3434 | 1 1 | (1 0) (1 1)
3495 08:07:39.966774 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3496 08:07:39.969774 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 08:07:39.972851 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 08:07:39.976328 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 08:07:39.983041 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 08:07:39.986367 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 08:07:39.989889 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 08:07:39.996742 1 0 24 | B1->B0 | 4242 2a2a | 0 1 | (0 0) (0 0)
3503 08:07:39.999589 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3504 08:07:40.003135 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 08:07:40.009567 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 08:07:40.012978 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 08:07:40.015969 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 08:07:40.022572 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 08:07:40.026356 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 08:07:40.029514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3511 08:07:40.036168 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3512 08:07:40.039457 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 08:07:40.043156 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 08:07:40.049364 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 08:07:40.052597 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 08:07:40.056097 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 08:07:40.062541 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 08:07:40.066034 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 08:07:40.069361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 08:07:40.075894 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 08:07:40.079174 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 08:07:40.082844 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 08:07:40.089299 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 08:07:40.092761 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 08:07:40.096212 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3526 08:07:40.099188 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3527 08:07:40.105812 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3528 08:07:40.109463 Total UI for P1: 0, mck2ui 16
3529 08:07:40.112960 best dqsien dly found for B1: ( 1, 3, 22)
3530 08:07:40.116180 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 08:07:40.119421 Total UI for P1: 0, mck2ui 16
3532 08:07:40.122519 best dqsien dly found for B0: ( 1, 3, 26)
3533 08:07:40.126073 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3534 08:07:40.129265 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3535 08:07:40.129369
3536 08:07:40.132329 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3537 08:07:40.136166 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3538 08:07:40.139022 [Gating] SW calibration Done
3539 08:07:40.139101 ==
3540 08:07:40.142701 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 08:07:40.149007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 08:07:40.149118 ==
3543 08:07:40.149196 RX Vref Scan: 0
3544 08:07:40.149259
3545 08:07:40.152773 RX Vref 0 -> 0, step: 1
3546 08:07:40.152851
3547 08:07:40.155572 RX Delay -40 -> 252, step: 8
3548 08:07:40.159169 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3549 08:07:40.162478 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3550 08:07:40.165450 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3551 08:07:40.172174 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3552 08:07:40.175761 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3553 08:07:40.178764 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3554 08:07:40.182551 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3555 08:07:40.185380 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3556 08:07:40.188850 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3557 08:07:40.195517 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3558 08:07:40.198849 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3559 08:07:40.202246 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3560 08:07:40.205489 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3561 08:07:40.212042 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3562 08:07:40.215698 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3563 08:07:40.219336 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3564 08:07:40.219420 ==
3565 08:07:40.221851 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 08:07:40.225591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 08:07:40.225675 ==
3568 08:07:40.229076 DQS Delay:
3569 08:07:40.229204 DQS0 = 0, DQS1 = 0
3570 08:07:40.232078 DQM Delay:
3571 08:07:40.232162 DQM0 = 120, DQM1 = 117
3572 08:07:40.232227 DQ Delay:
3573 08:07:40.235742 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3574 08:07:40.238629 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3575 08:07:40.245469 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3576 08:07:40.248505 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3577 08:07:40.248636
3578 08:07:40.248753
3579 08:07:40.248862 ==
3580 08:07:40.252060 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 08:07:40.255787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 08:07:40.255913 ==
3583 08:07:40.256024
3584 08:07:40.256136
3585 08:07:40.258847 TX Vref Scan disable
3586 08:07:40.262242 == TX Byte 0 ==
3587 08:07:40.265259 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3588 08:07:40.268606 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3589 08:07:40.272224 == TX Byte 1 ==
3590 08:07:40.275507 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3591 08:07:40.278457 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3592 08:07:40.278581 ==
3593 08:07:40.282074 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 08:07:40.285354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 08:07:40.288603 ==
3596 08:07:40.298950 TX Vref=22, minBit 9, minWin=25, winSum=417
3597 08:07:40.301771 TX Vref=24, minBit 2, minWin=26, winSum=425
3598 08:07:40.305199 TX Vref=26, minBit 2, minWin=26, winSum=427
3599 08:07:40.308623 TX Vref=28, minBit 9, minWin=26, winSum=435
3600 08:07:40.312017 TX Vref=30, minBit 2, minWin=26, winSum=434
3601 08:07:40.318424 TX Vref=32, minBit 9, minWin=26, winSum=436
3602 08:07:40.321835 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3603 08:07:40.321920
3604 08:07:40.324835 Final TX Range 1 Vref 32
3605 08:07:40.324919
3606 08:07:40.324984 ==
3607 08:07:40.328243 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 08:07:40.331680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 08:07:40.331791 ==
3610 08:07:40.335239
3611 08:07:40.335349
3612 08:07:40.335454 TX Vref Scan disable
3613 08:07:40.338822 == TX Byte 0 ==
3614 08:07:40.341697 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3615 08:07:40.345392 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3616 08:07:40.348197 == TX Byte 1 ==
3617 08:07:40.351669 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3618 08:07:40.354658 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3619 08:07:40.358229
3620 08:07:40.358314 [DATLAT]
3621 08:07:40.358421 Freq=1200, CH1 RK1
3622 08:07:40.358527
3623 08:07:40.361577 DATLAT Default: 0xd
3624 08:07:40.361654 0, 0xFFFF, sum = 0
3625 08:07:40.365134 1, 0xFFFF, sum = 0
3626 08:07:40.365212 2, 0xFFFF, sum = 0
3627 08:07:40.368228 3, 0xFFFF, sum = 0
3628 08:07:40.371759 4, 0xFFFF, sum = 0
3629 08:07:40.371866 5, 0xFFFF, sum = 0
3630 08:07:40.374685 6, 0xFFFF, sum = 0
3631 08:07:40.374792 7, 0xFFFF, sum = 0
3632 08:07:40.378088 8, 0xFFFF, sum = 0
3633 08:07:40.378193 9, 0xFFFF, sum = 0
3634 08:07:40.381547 10, 0xFFFF, sum = 0
3635 08:07:40.381631 11, 0xFFFF, sum = 0
3636 08:07:40.384845 12, 0x0, sum = 1
3637 08:07:40.384952 13, 0x0, sum = 2
3638 08:07:40.388325 14, 0x0, sum = 3
3639 08:07:40.388440 15, 0x0, sum = 4
3640 08:07:40.388509 best_step = 13
3641 08:07:40.391345
3642 08:07:40.391454 ==
3643 08:07:40.394978 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 08:07:40.398136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 08:07:40.398210 ==
3646 08:07:40.398284 RX Vref Scan: 0
3647 08:07:40.398346
3648 08:07:40.401516 RX Vref 0 -> 0, step: 1
3649 08:07:40.401621
3650 08:07:40.404770 RX Delay -5 -> 252, step: 4
3651 08:07:40.407852 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3652 08:07:40.414903 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3653 08:07:40.417872 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3654 08:07:40.421368 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3655 08:07:40.424385 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3656 08:07:40.428104 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3657 08:07:40.434320 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3658 08:07:40.437951 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3659 08:07:40.441235 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3660 08:07:40.444791 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3661 08:07:40.447940 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3662 08:07:40.454410 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3663 08:07:40.457868 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3664 08:07:40.461163 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3665 08:07:40.464388 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3666 08:07:40.468277 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3667 08:07:40.470986 ==
3668 08:07:40.471099 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 08:07:40.477627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 08:07:40.477741 ==
3671 08:07:40.477839 DQS Delay:
3672 08:07:40.481156 DQS0 = 0, DQS1 = 0
3673 08:07:40.481233 DQM Delay:
3674 08:07:40.484406 DQM0 = 120, DQM1 = 118
3675 08:07:40.484478 DQ Delay:
3676 08:07:40.487929 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3677 08:07:40.490984 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3678 08:07:40.494111 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3679 08:07:40.497575 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3680 08:07:40.497682
3681 08:07:40.497776
3682 08:07:40.507929 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3683 08:07:40.511532 CH1 RK1: MR19=403, MR18=13F0
3684 08:07:40.514568 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3685 08:07:40.517915 [RxdqsGatingPostProcess] freq 1200
3686 08:07:40.524676 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3687 08:07:40.527400 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 08:07:40.531060 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 08:07:40.534436 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 08:07:40.537612 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 08:07:40.541032 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 08:07:40.543959 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 08:07:40.547730 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 08:07:40.551121 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 08:07:40.551219 Pre-setting of DQS Precalculation
3696 08:07:40.557596 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3697 08:07:40.564206 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3698 08:07:40.570890 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3699 08:07:40.570996
3700 08:07:40.571092
3701 08:07:40.574306 [Calibration Summary] 2400 Mbps
3702 08:07:40.577430 CH 0, Rank 0
3703 08:07:40.577533 SW Impedance : PASS
3704 08:07:40.580752 DUTY Scan : NO K
3705 08:07:40.583624 ZQ Calibration : PASS
3706 08:07:40.583734 Jitter Meter : NO K
3707 08:07:40.587124 CBT Training : PASS
3708 08:07:40.590743 Write leveling : PASS
3709 08:07:40.590852 RX DQS gating : PASS
3710 08:07:40.594168 RX DQ/DQS(RDDQC) : PASS
3711 08:07:40.597291 TX DQ/DQS : PASS
3712 08:07:40.597368 RX DATLAT : PASS
3713 08:07:40.600822 RX DQ/DQS(Engine): PASS
3714 08:07:40.600920 TX OE : NO K
3715 08:07:40.603576 All Pass.
3716 08:07:40.603688
3717 08:07:40.603779 CH 0, Rank 1
3718 08:07:40.607261 SW Impedance : PASS
3719 08:07:40.607357 DUTY Scan : NO K
3720 08:07:40.610806 ZQ Calibration : PASS
3721 08:07:40.613987 Jitter Meter : NO K
3722 08:07:40.614087 CBT Training : PASS
3723 08:07:40.617416 Write leveling : PASS
3724 08:07:40.620940 RX DQS gating : PASS
3725 08:07:40.621041 RX DQ/DQS(RDDQC) : PASS
3726 08:07:40.623669 TX DQ/DQS : PASS
3727 08:07:40.627160 RX DATLAT : PASS
3728 08:07:40.627258 RX DQ/DQS(Engine): PASS
3729 08:07:40.630120 TX OE : NO K
3730 08:07:40.630224 All Pass.
3731 08:07:40.630325
3732 08:07:40.633615 CH 1, Rank 0
3733 08:07:40.633722 SW Impedance : PASS
3734 08:07:40.637265 DUTY Scan : NO K
3735 08:07:40.640478 ZQ Calibration : PASS
3736 08:07:40.640580 Jitter Meter : NO K
3737 08:07:40.643803 CBT Training : PASS
3738 08:07:40.646939 Write leveling : PASS
3739 08:07:40.647011 RX DQS gating : PASS
3740 08:07:40.650295 RX DQ/DQS(RDDQC) : PASS
3741 08:07:40.653687 TX DQ/DQS : PASS
3742 08:07:40.653760 RX DATLAT : PASS
3743 08:07:40.656906 RX DQ/DQS(Engine): PASS
3744 08:07:40.656976 TX OE : NO K
3745 08:07:40.660373 All Pass.
3746 08:07:40.660442
3747 08:07:40.660502 CH 1, Rank 1
3748 08:07:40.663240 SW Impedance : PASS
3749 08:07:40.663334 DUTY Scan : NO K
3750 08:07:40.666664 ZQ Calibration : PASS
3751 08:07:40.670042 Jitter Meter : NO K
3752 08:07:40.670146 CBT Training : PASS
3753 08:07:40.673266 Write leveling : PASS
3754 08:07:40.676575 RX DQS gating : PASS
3755 08:07:40.676678 RX DQ/DQS(RDDQC) : PASS
3756 08:07:40.680114 TX DQ/DQS : PASS
3757 08:07:40.683262 RX DATLAT : PASS
3758 08:07:40.683361 RX DQ/DQS(Engine): PASS
3759 08:07:40.686556 TX OE : NO K
3760 08:07:40.686653 All Pass.
3761 08:07:40.686746
3762 08:07:40.689864 DramC Write-DBI off
3763 08:07:40.693238 PER_BANK_REFRESH: Hybrid Mode
3764 08:07:40.693311 TX_TRACKING: ON
3765 08:07:40.702909 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3766 08:07:40.706610 [FAST_K] Save calibration result to emmc
3767 08:07:40.709675 dramc_set_vcore_voltage set vcore to 650000
3768 08:07:40.713330 Read voltage for 600, 5
3769 08:07:40.713433 Vio18 = 0
3770 08:07:40.713536 Vcore = 650000
3771 08:07:40.716489 Vdram = 0
3772 08:07:40.716590 Vddq = 0
3773 08:07:40.716667 Vmddr = 0
3774 08:07:40.723010 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3775 08:07:40.726528 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3776 08:07:40.729580 MEM_TYPE=3, freq_sel=19
3777 08:07:40.733212 sv_algorithm_assistance_LP4_1600
3778 08:07:40.736432 ============ PULL DRAM RESETB DOWN ============
3779 08:07:40.742786 ========== PULL DRAM RESETB DOWN end =========
3780 08:07:40.746304 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3781 08:07:40.749833 ===================================
3782 08:07:40.752742 LPDDR4 DRAM CONFIGURATION
3783 08:07:40.756118 ===================================
3784 08:07:40.756196 EX_ROW_EN[0] = 0x0
3785 08:07:40.759801 EX_ROW_EN[1] = 0x0
3786 08:07:40.759904 LP4Y_EN = 0x0
3787 08:07:40.763044 WORK_FSP = 0x0
3788 08:07:40.763157 WL = 0x2
3789 08:07:40.766024 RL = 0x2
3790 08:07:40.766138 BL = 0x2
3791 08:07:40.769682 RPST = 0x0
3792 08:07:40.769789 RD_PRE = 0x0
3793 08:07:40.773102 WR_PRE = 0x1
3794 08:07:40.773202 WR_PST = 0x0
3795 08:07:40.777699 DBI_WR = 0x0
3796 08:07:40.777786 DBI_RD = 0x0
3797 08:07:40.779381 OTF = 0x1
3798 08:07:40.783084 ===================================
3799 08:07:40.785961 ===================================
3800 08:07:40.786040 ANA top config
3801 08:07:40.789441 ===================================
3802 08:07:40.792576 DLL_ASYNC_EN = 0
3803 08:07:40.796031 ALL_SLAVE_EN = 1
3804 08:07:40.799278 NEW_RANK_MODE = 1
3805 08:07:40.802567 DLL_IDLE_MODE = 1
3806 08:07:40.802671 LP45_APHY_COMB_EN = 1
3807 08:07:40.806001 TX_ODT_DIS = 1
3808 08:07:40.808996 NEW_8X_MODE = 1
3809 08:07:40.812412 ===================================
3810 08:07:40.815519 ===================================
3811 08:07:40.818982 data_rate = 1200
3812 08:07:40.822533 CKR = 1
3813 08:07:40.822639 DQ_P2S_RATIO = 8
3814 08:07:40.825536 ===================================
3815 08:07:40.829175 CA_P2S_RATIO = 8
3816 08:07:40.832221 DQ_CA_OPEN = 0
3817 08:07:40.835675 DQ_SEMI_OPEN = 0
3818 08:07:40.838693 CA_SEMI_OPEN = 0
3819 08:07:40.842470 CA_FULL_RATE = 0
3820 08:07:40.842550 DQ_CKDIV4_EN = 1
3821 08:07:40.845485 CA_CKDIV4_EN = 1
3822 08:07:40.848914 CA_PREDIV_EN = 0
3823 08:07:40.852321 PH8_DLY = 0
3824 08:07:40.855589 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3825 08:07:40.858912 DQ_AAMCK_DIV = 4
3826 08:07:40.859029 CA_AAMCK_DIV = 4
3827 08:07:40.862214 CA_ADMCK_DIV = 4
3828 08:07:40.865705 DQ_TRACK_CA_EN = 0
3829 08:07:40.868872 CA_PICK = 600
3830 08:07:40.872208 CA_MCKIO = 600
3831 08:07:40.875295 MCKIO_SEMI = 0
3832 08:07:40.878954 PLL_FREQ = 2288
3833 08:07:40.879064 DQ_UI_PI_RATIO = 32
3834 08:07:40.882387 CA_UI_PI_RATIO = 0
3835 08:07:40.885384 ===================================
3836 08:07:40.889045 ===================================
3837 08:07:40.891925 memory_type:LPDDR4
3838 08:07:40.895490 GP_NUM : 10
3839 08:07:40.895595 SRAM_EN : 1
3840 08:07:40.898950 MD32_EN : 0
3841 08:07:40.902117 ===================================
3842 08:07:40.902222 [ANA_INIT] >>>>>>>>>>>>>>
3843 08:07:40.905274 <<<<<< [CONFIGURE PHASE]: ANA_TX
3844 08:07:40.909235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3845 08:07:40.911911 ===================================
3846 08:07:40.915561 data_rate = 1200,PCW = 0X5800
3847 08:07:40.918700 ===================================
3848 08:07:40.921887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3849 08:07:40.928584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3850 08:07:40.935426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3851 08:07:40.938397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3852 08:07:40.942136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3853 08:07:40.945203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3854 08:07:40.948587 [ANA_INIT] flow start
3855 08:07:40.948715 [ANA_INIT] PLL >>>>>>>>
3856 08:07:40.951752 [ANA_INIT] PLL <<<<<<<<
3857 08:07:40.955363 [ANA_INIT] MIDPI >>>>>>>>
3858 08:07:40.955487 [ANA_INIT] MIDPI <<<<<<<<
3859 08:07:40.958906 [ANA_INIT] DLL >>>>>>>>
3860 08:07:40.961604 [ANA_INIT] flow end
3861 08:07:40.965032 ============ LP4 DIFF to SE enter ============
3862 08:07:40.968745 ============ LP4 DIFF to SE exit ============
3863 08:07:40.971793 [ANA_INIT] <<<<<<<<<<<<<
3864 08:07:40.975241 [Flow] Enable top DCM control >>>>>
3865 08:07:40.978647 [Flow] Enable top DCM control <<<<<
3866 08:07:40.981817 Enable DLL master slave shuffle
3867 08:07:40.985275 ==============================================================
3868 08:07:40.988234 Gating Mode config
3869 08:07:40.995156 ==============================================================
3870 08:07:40.995265 Config description:
3871 08:07:41.005382 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3872 08:07:41.011645 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3873 08:07:41.015290 SELPH_MODE 0: By rank 1: By Phase
3874 08:07:41.021745 ==============================================================
3875 08:07:41.025365 GAT_TRACK_EN = 1
3876 08:07:41.028492 RX_GATING_MODE = 2
3877 08:07:41.031673 RX_GATING_TRACK_MODE = 2
3878 08:07:41.035101 SELPH_MODE = 1
3879 08:07:41.038073 PICG_EARLY_EN = 1
3880 08:07:41.041831 VALID_LAT_VALUE = 1
3881 08:07:41.044771 ==============================================================
3882 08:07:41.048118 Enter into Gating configuration >>>>
3883 08:07:41.051704 Exit from Gating configuration <<<<
3884 08:07:41.054755 Enter into DVFS_PRE_config >>>>>
3885 08:07:41.068175 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3886 08:07:41.068304 Exit from DVFS_PRE_config <<<<<
3887 08:07:41.071207 Enter into PICG configuration >>>>
3888 08:07:41.074856 Exit from PICG configuration <<<<
3889 08:07:41.078494 [RX_INPUT] configuration >>>>>
3890 08:07:41.081553 [RX_INPUT] configuration <<<<<
3891 08:07:41.088295 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3892 08:07:41.091353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3893 08:07:41.098072 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3894 08:07:41.105053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3895 08:07:41.111573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3896 08:07:41.118761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3897 08:07:41.121579 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3898 08:07:41.124854 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3899 08:07:41.128352 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3900 08:07:41.135178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3901 08:07:41.138396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3902 08:07:41.141151 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 08:07:41.144477 ===================================
3904 08:07:41.148148 LPDDR4 DRAM CONFIGURATION
3905 08:07:41.151281 ===================================
3906 08:07:41.151392 EX_ROW_EN[0] = 0x0
3907 08:07:41.154885 EX_ROW_EN[1] = 0x0
3908 08:07:41.154995 LP4Y_EN = 0x0
3909 08:07:41.158126 WORK_FSP = 0x0
3910 08:07:41.161461 WL = 0x2
3911 08:07:41.161585 RL = 0x2
3912 08:07:41.164742 BL = 0x2
3913 08:07:41.164840 RPST = 0x0
3914 08:07:41.167753 RD_PRE = 0x0
3915 08:07:41.167848 WR_PRE = 0x1
3916 08:07:41.171308 WR_PST = 0x0
3917 08:07:41.171413 DBI_WR = 0x0
3918 08:07:41.174862 DBI_RD = 0x0
3919 08:07:41.174971 OTF = 0x1
3920 08:07:41.177967 ===================================
3921 08:07:41.181679 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3922 08:07:41.187957 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3923 08:07:41.191241 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3924 08:07:41.194740 ===================================
3925 08:07:41.197945 LPDDR4 DRAM CONFIGURATION
3926 08:07:41.201422 ===================================
3927 08:07:41.201541 EX_ROW_EN[0] = 0x10
3928 08:07:41.204886 EX_ROW_EN[1] = 0x0
3929 08:07:41.204999 LP4Y_EN = 0x0
3930 08:07:41.207954 WORK_FSP = 0x0
3931 08:07:41.208056 WL = 0x2
3932 08:07:41.211202 RL = 0x2
3933 08:07:41.211312 BL = 0x2
3934 08:07:41.214688 RPST = 0x0
3935 08:07:41.217543 RD_PRE = 0x0
3936 08:07:41.217664 WR_PRE = 0x1
3937 08:07:41.221001 WR_PST = 0x0
3938 08:07:41.221140 DBI_WR = 0x0
3939 08:07:41.224732 DBI_RD = 0x0
3940 08:07:41.224862 OTF = 0x1
3941 08:07:41.227752 ===================================
3942 08:07:41.234448 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3943 08:07:41.238462 nWR fixed to 30
3944 08:07:41.241456 [ModeRegInit_LP4] CH0 RK0
3945 08:07:41.241579 [ModeRegInit_LP4] CH0 RK1
3946 08:07:41.244843 [ModeRegInit_LP4] CH1 RK0
3947 08:07:41.247813 [ModeRegInit_LP4] CH1 RK1
3948 08:07:41.247939 match AC timing 17
3949 08:07:41.254988 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3950 08:07:41.257706 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3951 08:07:41.261134 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3952 08:07:41.267962 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3953 08:07:41.270959 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3954 08:07:41.271062 ==
3955 08:07:41.274487 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 08:07:41.277753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 08:07:41.277835 ==
3958 08:07:41.284581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 08:07:41.291180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3960 08:07:41.294244 [CA 0] Center 36 (5~67) winsize 63
3961 08:07:41.297736 [CA 1] Center 36 (5~67) winsize 63
3962 08:07:41.300905 [CA 2] Center 34 (3~65) winsize 63
3963 08:07:41.304561 [CA 3] Center 33 (3~64) winsize 62
3964 08:07:41.307589 [CA 4] Center 33 (2~64) winsize 63
3965 08:07:41.311288 [CA 5] Center 32 (2~63) winsize 62
3966 08:07:41.311388
3967 08:07:41.314440 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3968 08:07:41.314542
3969 08:07:41.317860 [CATrainingPosCal] consider 1 rank data
3970 08:07:41.321277 u2DelayCellTimex100 = 270/100 ps
3971 08:07:41.323977 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3972 08:07:41.327514 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3973 08:07:41.331311 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3974 08:07:41.333935 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3975 08:07:41.340851 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3976 08:07:41.344382 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3977 08:07:41.344466
3978 08:07:41.347150 CA PerBit enable=1, Macro0, CA PI delay=32
3979 08:07:41.347232
3980 08:07:41.350697 [CBTSetCACLKResult] CA Dly = 32
3981 08:07:41.350779 CS Dly: 4 (0~35)
3982 08:07:41.350845 ==
3983 08:07:41.354230 Dram Type= 6, Freq= 0, CH_0, rank 1
3984 08:07:41.360506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 08:07:41.360646 ==
3986 08:07:41.364094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 08:07:41.370427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3988 08:07:41.373784 [CA 0] Center 35 (5~66) winsize 62
3989 08:07:41.377322 [CA 1] Center 35 (5~66) winsize 62
3990 08:07:41.380595 [CA 2] Center 34 (3~65) winsize 63
3991 08:07:41.384186 [CA 3] Center 33 (3~64) winsize 62
3992 08:07:41.387437 [CA 4] Center 33 (2~64) winsize 63
3993 08:07:41.390989 [CA 5] Center 32 (2~63) winsize 62
3994 08:07:41.391085
3995 08:07:41.393890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3996 08:07:41.393972
3997 08:07:41.397434 [CATrainingPosCal] consider 2 rank data
3998 08:07:41.400402 u2DelayCellTimex100 = 270/100 ps
3999 08:07:41.403786 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4000 08:07:41.407182 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4001 08:07:41.410770 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4002 08:07:41.417401 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4003 08:07:41.420586 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4004 08:07:41.423904 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4005 08:07:41.423999
4006 08:07:41.427493 CA PerBit enable=1, Macro0, CA PI delay=32
4007 08:07:41.427600
4008 08:07:41.430725 [CBTSetCACLKResult] CA Dly = 32
4009 08:07:41.430865 CS Dly: 4 (0~36)
4010 08:07:41.431003
4011 08:07:41.433961 ----->DramcWriteLeveling(PI) begin...
4012 08:07:41.434079 ==
4013 08:07:41.437632 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 08:07:41.443924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 08:07:41.444008 ==
4016 08:07:41.447428 Write leveling (Byte 0): 32 => 32
4017 08:07:41.450799 Write leveling (Byte 1): 32 => 32
4018 08:07:41.450881 DramcWriteLeveling(PI) end<-----
4019 08:07:41.453697
4020 08:07:41.453779 ==
4021 08:07:41.457302 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 08:07:41.460402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 08:07:41.460485 ==
4024 08:07:41.463957 [Gating] SW mode calibration
4025 08:07:41.470648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4026 08:07:41.473876 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4027 08:07:41.480762 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 08:07:41.483762 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 08:07:41.487226 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 08:07:41.493728 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4031 08:07:41.497229 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4032 08:07:41.500520 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 08:07:41.507079 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 08:07:41.510105 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 08:07:41.513569 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 08:07:41.520207 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 08:07:41.523782 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 08:07:41.526588 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4039 08:07:41.533808 0 10 16 | B1->B0 | 3333 4646 | 1 0 | (1 1) (0 0)
4040 08:07:41.536849 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 08:07:41.540261 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 08:07:41.546634 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 08:07:41.550248 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 08:07:41.553125 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 08:07:41.559840 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 08:07:41.563148 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4047 08:07:41.566648 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4048 08:07:41.573497 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 08:07:41.576289 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 08:07:41.579995 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 08:07:41.586551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 08:07:41.589854 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 08:07:41.593001 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 08:07:41.596418 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 08:07:41.603173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 08:07:41.606996 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 08:07:41.609536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 08:07:41.616414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 08:07:41.619464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 08:07:41.623103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 08:07:41.629796 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 08:07:41.632765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 08:07:41.636402 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 08:07:41.639931 Total UI for P1: 0, mck2ui 16
4065 08:07:41.642784 best dqsien dly found for B0: ( 0, 13, 14)
4066 08:07:41.646349 Total UI for P1: 0, mck2ui 16
4067 08:07:41.650095 best dqsien dly found for B1: ( 0, 13, 14)
4068 08:07:41.652926 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4069 08:07:41.655927 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4070 08:07:41.659593
4071 08:07:41.662940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4072 08:07:41.666051 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4073 08:07:41.669500 [Gating] SW calibration Done
4074 08:07:41.669587 ==
4075 08:07:41.672824 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 08:07:41.675957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 08:07:41.676040 ==
4078 08:07:41.676113 RX Vref Scan: 0
4079 08:07:41.676174
4080 08:07:41.680028 RX Vref 0 -> 0, step: 1
4081 08:07:41.680104
4082 08:07:41.683067 RX Delay -230 -> 252, step: 16
4083 08:07:41.686259 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4084 08:07:41.689433 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4085 08:07:41.696301 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4086 08:07:41.699622 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4087 08:07:41.703059 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4088 08:07:41.706167 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4089 08:07:41.712614 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4090 08:07:41.716235 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4091 08:07:41.719361 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4092 08:07:41.722621 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4093 08:07:41.726111 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4094 08:07:41.732669 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4095 08:07:41.735921 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4096 08:07:41.739501 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4097 08:07:41.743014 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4098 08:07:41.749810 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4099 08:07:41.749919 ==
4100 08:07:41.752587 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 08:07:41.756332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 08:07:41.756418 ==
4103 08:07:41.756484 DQS Delay:
4104 08:07:41.759459 DQS0 = 0, DQS1 = 0
4105 08:07:41.759543 DQM Delay:
4106 08:07:41.763034 DQM0 = 52, DQM1 = 46
4107 08:07:41.763121 DQ Delay:
4108 08:07:41.766354 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4109 08:07:41.769425 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4110 08:07:41.772995 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4111 08:07:41.776135 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4112 08:07:41.776265
4113 08:07:41.776379
4114 08:07:41.776491 ==
4115 08:07:41.779275 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 08:07:41.782873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 08:07:41.782999 ==
4118 08:07:41.786318
4119 08:07:41.786442
4120 08:07:41.786556 TX Vref Scan disable
4121 08:07:41.789515 == TX Byte 0 ==
4122 08:07:41.792701 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4123 08:07:41.795949 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4124 08:07:41.799477 == TX Byte 1 ==
4125 08:07:41.802587 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4126 08:07:41.805867 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4127 08:07:41.805967 ==
4128 08:07:41.809355 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 08:07:41.815716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 08:07:41.815834 ==
4131 08:07:41.815906
4132 08:07:41.815968
4133 08:07:41.816033 TX Vref Scan disable
4134 08:07:41.820507 == TX Byte 0 ==
4135 08:07:41.823590 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4136 08:07:41.827421 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4137 08:07:41.830194 == TX Byte 1 ==
4138 08:07:41.833650 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4139 08:07:41.836977 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4140 08:07:41.840680
4141 08:07:41.840763 [DATLAT]
4142 08:07:41.840828 Freq=600, CH0 RK0
4143 08:07:41.840897
4144 08:07:41.843854 DATLAT Default: 0x9
4145 08:07:41.843932 0, 0xFFFF, sum = 0
4146 08:07:41.846916 1, 0xFFFF, sum = 0
4147 08:07:41.846996 2, 0xFFFF, sum = 0
4148 08:07:41.850384 3, 0xFFFF, sum = 0
4149 08:07:41.850470 4, 0xFFFF, sum = 0
4150 08:07:41.854418 5, 0xFFFF, sum = 0
4151 08:07:41.857217 6, 0xFFFF, sum = 0
4152 08:07:41.857297 7, 0xFFFF, sum = 0
4153 08:07:41.857362 8, 0x0, sum = 1
4154 08:07:41.860202 9, 0x0, sum = 2
4155 08:07:41.860286 10, 0x0, sum = 3
4156 08:07:41.863949 11, 0x0, sum = 4
4157 08:07:41.864030 best_step = 9
4158 08:07:41.864095
4159 08:07:41.864162 ==
4160 08:07:41.867337 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 08:07:41.873922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 08:07:41.874009 ==
4163 08:07:41.874075 RX Vref Scan: 1
4164 08:07:41.874136
4165 08:07:41.876924 RX Vref 0 -> 0, step: 1
4166 08:07:41.877000
4167 08:07:41.880519 RX Delay -163 -> 252, step: 8
4168 08:07:41.880627
4169 08:07:41.883939 Set Vref, RX VrefLevel [Byte0]: 55
4170 08:07:41.886723 [Byte1]: 47
4171 08:07:41.886826
4172 08:07:41.890342 Final RX Vref Byte 0 = 55 to rank0
4173 08:07:41.893319 Final RX Vref Byte 1 = 47 to rank0
4174 08:07:41.896726 Final RX Vref Byte 0 = 55 to rank1
4175 08:07:41.900066 Final RX Vref Byte 1 = 47 to rank1==
4176 08:07:41.903318 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 08:07:41.906730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 08:07:41.906811 ==
4179 08:07:41.910346 DQS Delay:
4180 08:07:41.910421 DQS0 = 0, DQS1 = 0
4181 08:07:41.910485 DQM Delay:
4182 08:07:41.913873 DQM0 = 53, DQM1 = 45
4183 08:07:41.913982 DQ Delay:
4184 08:07:41.916544 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =48
4185 08:07:41.920394 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4186 08:07:41.923886 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4187 08:07:41.926697 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4188 08:07:41.926814
4189 08:07:41.926907
4190 08:07:41.936864 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4191 08:07:41.940296 CH0 RK0: MR19=808, MR18=6C60
4192 08:07:41.943431 CH0_RK0: MR19=0x808, MR18=0x6C60, DQSOSC=389, MR23=63, INC=173, DEC=115
4193 08:07:41.943537
4194 08:07:41.946814 ----->DramcWriteLeveling(PI) begin...
4195 08:07:41.950110 ==
4196 08:07:41.953572 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 08:07:41.956894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 08:07:41.956999 ==
4199 08:07:41.959758 Write leveling (Byte 0): 35 => 35
4200 08:07:41.963152 Write leveling (Byte 1): 31 => 31
4201 08:07:41.966781 DramcWriteLeveling(PI) end<-----
4202 08:07:41.966864
4203 08:07:41.966930 ==
4204 08:07:41.970395 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 08:07:41.973870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 08:07:41.973995 ==
4207 08:07:41.976752 [Gating] SW mode calibration
4208 08:07:41.983509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4209 08:07:41.986620 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4210 08:07:41.993360 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 08:07:41.996674 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 08:07:41.999924 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 08:07:42.006489 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
4214 08:07:42.010097 0 9 16 | B1->B0 | 2c2c 2727 | 0 0 | (1 1) (0 0)
4215 08:07:42.013155 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 08:07:42.019648 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 08:07:42.023439 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 08:07:42.026197 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 08:07:42.033028 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 08:07:42.036546 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 08:07:42.040107 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4222 08:07:42.046587 0 10 16 | B1->B0 | 3d3d 4343 | 1 0 | (0 0) (0 0)
4223 08:07:42.049671 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 08:07:42.053155 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 08:07:42.059753 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 08:07:42.063383 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 08:07:42.066887 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 08:07:42.073290 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 08:07:42.076397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4230 08:07:42.079801 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4231 08:07:42.086513 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 08:07:42.090130 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 08:07:42.092821 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 08:07:42.100002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 08:07:42.103365 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 08:07:42.106239 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 08:07:42.109967 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 08:07:42.116659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 08:07:42.119891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 08:07:42.123146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 08:07:42.129842 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 08:07:42.132761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 08:07:42.136442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 08:07:42.142812 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 08:07:42.146100 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 08:07:42.149649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 08:07:42.152832 Total UI for P1: 0, mck2ui 16
4248 08:07:42.156248 best dqsien dly found for B0: ( 0, 13, 14)
4249 08:07:42.159512 Total UI for P1: 0, mck2ui 16
4250 08:07:42.163205 best dqsien dly found for B1: ( 0, 13, 14)
4251 08:07:42.166161 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4252 08:07:42.169989 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4253 08:07:42.173009
4254 08:07:42.175961 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4255 08:07:42.179427 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4256 08:07:42.183031 [Gating] SW calibration Done
4257 08:07:42.183109 ==
4258 08:07:42.185948 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 08:07:42.189313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 08:07:42.189389 ==
4261 08:07:42.189458 RX Vref Scan: 0
4262 08:07:42.189518
4263 08:07:42.192876 RX Vref 0 -> 0, step: 1
4264 08:07:42.192952
4265 08:07:42.195811 RX Delay -230 -> 252, step: 16
4266 08:07:42.199595 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4267 08:07:42.202619 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4268 08:07:42.209443 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4269 08:07:42.212998 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4270 08:07:42.216662 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4271 08:07:42.219327 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4272 08:07:42.226015 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4273 08:07:42.229530 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4274 08:07:42.233001 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4275 08:07:42.236053 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4276 08:07:42.239695 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4277 08:07:42.246112 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4278 08:07:42.249050 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4279 08:07:42.252563 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4280 08:07:42.255924 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4281 08:07:42.262743 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4282 08:07:42.262822 ==
4283 08:07:42.266062 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 08:07:42.269689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 08:07:42.269788 ==
4286 08:07:42.269888 DQS Delay:
4287 08:07:42.273022 DQS0 = 0, DQS1 = 0
4288 08:07:42.273119 DQM Delay:
4289 08:07:42.275971 DQM0 = 52, DQM1 = 43
4290 08:07:42.276054 DQ Delay:
4291 08:07:42.279085 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4292 08:07:42.282673 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4293 08:07:42.285842 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4294 08:07:42.289357 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4295 08:07:42.289438
4296 08:07:42.289503
4297 08:07:42.289563 ==
4298 08:07:42.292351 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 08:07:42.296162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 08:07:42.298952 ==
4301 08:07:42.299034
4302 08:07:42.299098
4303 08:07:42.299158 TX Vref Scan disable
4304 08:07:42.302446 == TX Byte 0 ==
4305 08:07:42.305734 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4306 08:07:42.309187 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4307 08:07:42.312440 == TX Byte 1 ==
4308 08:07:42.315652 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4309 08:07:42.319238 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4310 08:07:42.322788 ==
4311 08:07:42.325472 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 08:07:42.328986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 08:07:42.329070 ==
4314 08:07:42.329156
4315 08:07:42.329236
4316 08:07:42.332127 TX Vref Scan disable
4317 08:07:42.332211 == TX Byte 0 ==
4318 08:07:42.338957 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4319 08:07:42.342268 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4320 08:07:42.342356 == TX Byte 1 ==
4321 08:07:42.348938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4322 08:07:42.352547 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4323 08:07:42.352634
4324 08:07:42.352719 [DATLAT]
4325 08:07:42.355755 Freq=600, CH0 RK1
4326 08:07:42.355841
4327 08:07:42.355942 DATLAT Default: 0x9
4328 08:07:42.358946 0, 0xFFFF, sum = 0
4329 08:07:42.359033 1, 0xFFFF, sum = 0
4330 08:07:42.362423 2, 0xFFFF, sum = 0
4331 08:07:42.362534 3, 0xFFFF, sum = 0
4332 08:07:42.366079 4, 0xFFFF, sum = 0
4333 08:07:42.366184 5, 0xFFFF, sum = 0
4334 08:07:42.369268 6, 0xFFFF, sum = 0
4335 08:07:42.372243 7, 0xFFFF, sum = 0
4336 08:07:42.372320 8, 0x0, sum = 1
4337 08:07:42.372384 9, 0x0, sum = 2
4338 08:07:42.375715 10, 0x0, sum = 3
4339 08:07:42.375803 11, 0x0, sum = 4
4340 08:07:42.379100 best_step = 9
4341 08:07:42.379175
4342 08:07:42.379257 ==
4343 08:07:42.382252 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 08:07:42.385674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 08:07:42.385786 ==
4346 08:07:42.388872 RX Vref Scan: 0
4347 08:07:42.388954
4348 08:07:42.389026 RX Vref 0 -> 0, step: 1
4349 08:07:42.389131
4350 08:07:42.392565 RX Delay -163 -> 252, step: 8
4351 08:07:42.399216 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4352 08:07:42.402469 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4353 08:07:42.406009 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4354 08:07:42.409388 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4355 08:07:42.412699 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4356 08:07:42.418974 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4357 08:07:42.422522 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4358 08:07:42.425715 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4359 08:07:42.429611 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4360 08:07:42.432298 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4361 08:07:42.439176 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4362 08:07:42.442594 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4363 08:07:42.445638 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4364 08:07:42.449025 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4365 08:07:42.455618 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4366 08:07:42.459357 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4367 08:07:42.459458 ==
4368 08:07:42.462451 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 08:07:42.465889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 08:07:42.465961 ==
4371 08:07:42.466021 DQS Delay:
4372 08:07:42.469354 DQS0 = 0, DQS1 = 0
4373 08:07:42.469424 DQM Delay:
4374 08:07:42.472695 DQM0 = 54, DQM1 = 45
4375 08:07:42.472776 DQ Delay:
4376 08:07:42.475777 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4377 08:07:42.479243 DQ4 =52, DQ5 =48, DQ6 =60, DQ7 =60
4378 08:07:42.482904 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4379 08:07:42.486092 DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =52
4380 08:07:42.486203
4381 08:07:42.486294
4382 08:07:42.496297 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4383 08:07:42.496405 CH0 RK1: MR19=808, MR18=6323
4384 08:07:42.502933 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4385 08:07:42.506187 [RxdqsGatingPostProcess] freq 600
4386 08:07:42.512784 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4387 08:07:42.516052 Pre-setting of DQS Precalculation
4388 08:07:42.519376 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4389 08:07:42.519484 ==
4390 08:07:42.522953 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 08:07:42.525878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 08:07:42.525962 ==
4393 08:07:42.532954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 08:07:42.539098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4395 08:07:42.542827 [CA 0] Center 35 (5~66) winsize 62
4396 08:07:42.546290 [CA 1] Center 36 (5~67) winsize 63
4397 08:07:42.549023 [CA 2] Center 34 (4~65) winsize 62
4398 08:07:42.552424 [CA 3] Center 34 (3~65) winsize 63
4399 08:07:42.555677 [CA 4] Center 34 (4~65) winsize 62
4400 08:07:42.559355 [CA 5] Center 33 (3~64) winsize 62
4401 08:07:42.559437
4402 08:07:42.562521 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4403 08:07:42.562603
4404 08:07:42.565598 [CATrainingPosCal] consider 1 rank data
4405 08:07:42.569110 u2DelayCellTimex100 = 270/100 ps
4406 08:07:42.572594 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 08:07:42.575979 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4408 08:07:42.578929 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 08:07:42.582128 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4410 08:07:42.585747 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 08:07:42.592453 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 08:07:42.592536
4413 08:07:42.596053 CA PerBit enable=1, Macro0, CA PI delay=33
4414 08:07:42.596135
4415 08:07:42.599090 [CBTSetCACLKResult] CA Dly = 33
4416 08:07:42.599188 CS Dly: 6 (0~37)
4417 08:07:42.599278 ==
4418 08:07:42.602142 Dram Type= 6, Freq= 0, CH_1, rank 1
4419 08:07:42.605672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 08:07:42.609515 ==
4421 08:07:42.612216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 08:07:42.618819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4423 08:07:42.622428 [CA 0] Center 36 (6~67) winsize 62
4424 08:07:42.625509 [CA 1] Center 36 (6~67) winsize 62
4425 08:07:42.628910 [CA 2] Center 35 (4~66) winsize 63
4426 08:07:42.632524 [CA 3] Center 35 (4~66) winsize 63
4427 08:07:42.635493 [CA 4] Center 35 (4~66) winsize 63
4428 08:07:42.639036 [CA 5] Center 34 (4~65) winsize 62
4429 08:07:42.639143
4430 08:07:42.641989 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4431 08:07:42.642060
4432 08:07:42.645851 [CATrainingPosCal] consider 2 rank data
4433 08:07:42.649003 u2DelayCellTimex100 = 270/100 ps
4434 08:07:42.652353 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4435 08:07:42.655738 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4436 08:07:42.658738 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4437 08:07:42.665795 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4438 08:07:42.668347 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4439 08:07:42.671986 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4440 08:07:42.672070
4441 08:07:42.675611 CA PerBit enable=1, Macro0, CA PI delay=34
4442 08:07:42.675723
4443 08:07:42.678629 [CBTSetCACLKResult] CA Dly = 34
4444 08:07:42.678706 CS Dly: 6 (0~38)
4445 08:07:42.678807
4446 08:07:42.682288 ----->DramcWriteLeveling(PI) begin...
4447 08:07:42.682419 ==
4448 08:07:42.685195 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 08:07:42.692028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 08:07:42.692156 ==
4451 08:07:42.695099 Write leveling (Byte 0): 27 => 27
4452 08:07:42.698800 Write leveling (Byte 1): 30 => 30
4453 08:07:42.698923 DramcWriteLeveling(PI) end<-----
4454 08:07:42.702440
4455 08:07:42.702560 ==
4456 08:07:42.705250 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 08:07:42.708738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 08:07:42.708860 ==
4459 08:07:42.711829 [Gating] SW mode calibration
4460 08:07:42.719110 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 08:07:42.721665 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4462 08:07:42.728799 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 08:07:42.731759 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 08:07:42.735231 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4465 08:07:42.741889 0 9 12 | B1->B0 | 3030 2727 | 0 0 | (1 0) (1 1)
4466 08:07:42.745336 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 08:07:42.748298 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 08:07:42.755379 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 08:07:42.758863 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 08:07:42.762040 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 08:07:42.768300 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 08:07:42.771510 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 08:07:42.775027 0 10 12 | B1->B0 | 3737 3939 | 0 0 | (0 0) (0 0)
4474 08:07:42.781817 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 08:07:42.785138 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 08:07:42.788494 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 08:07:42.795177 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 08:07:42.798151 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 08:07:42.801623 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 08:07:42.808462 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 08:07:42.811810 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4482 08:07:42.815058 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 08:07:42.818506 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 08:07:42.824632 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 08:07:42.828274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 08:07:42.832011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 08:07:42.838209 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 08:07:42.841331 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 08:07:42.844735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 08:07:42.851559 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 08:07:42.854901 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 08:07:42.858066 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 08:07:42.865040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 08:07:42.867992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 08:07:42.871411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 08:07:42.878222 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 08:07:42.881483 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4498 08:07:42.884686 Total UI for P1: 0, mck2ui 16
4499 08:07:42.888197 best dqsien dly found for B0: ( 0, 13, 10)
4500 08:07:42.891520 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 08:07:42.894898 Total UI for P1: 0, mck2ui 16
4502 08:07:42.897891 best dqsien dly found for B1: ( 0, 13, 12)
4503 08:07:42.901366 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4504 08:07:42.904938 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4505 08:07:42.905036
4506 08:07:42.911258 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4507 08:07:42.914902 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4508 08:07:42.915001 [Gating] SW calibration Done
4509 08:07:42.918235 ==
4510 08:07:42.921274 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 08:07:42.924638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 08:07:42.924737 ==
4513 08:07:42.924835 RX Vref Scan: 0
4514 08:07:42.924910
4515 08:07:42.927841 RX Vref 0 -> 0, step: 1
4516 08:07:42.927937
4517 08:07:42.931511 RX Delay -230 -> 252, step: 16
4518 08:07:42.934833 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4519 08:07:42.938239 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4520 08:07:42.944740 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4521 08:07:42.948547 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4522 08:07:42.951437 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4523 08:07:42.954817 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4524 08:07:42.957680 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4525 08:07:42.965003 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4526 08:07:42.967804 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4527 08:07:42.971387 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4528 08:07:42.974669 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4529 08:07:42.981386 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4530 08:07:42.984972 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4531 08:07:42.987619 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4532 08:07:42.991338 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4533 08:07:42.997927 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4534 08:07:42.998012 ==
4535 08:07:43.000865 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 08:07:43.004358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 08:07:43.004441 ==
4538 08:07:43.004507 DQS Delay:
4539 08:07:43.007689 DQS0 = 0, DQS1 = 0
4540 08:07:43.007772 DQM Delay:
4541 08:07:43.010996 DQM0 = 50, DQM1 = 46
4542 08:07:43.011078 DQ Delay:
4543 08:07:43.014169 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4544 08:07:43.017568 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4545 08:07:43.020948 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4546 08:07:43.024518 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4547 08:07:43.024627
4548 08:07:43.024729
4549 08:07:43.024819 ==
4550 08:07:43.027902 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 08:07:43.031076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 08:07:43.031180 ==
4553 08:07:43.031244
4554 08:07:43.034126
4555 08:07:43.034209 TX Vref Scan disable
4556 08:07:43.037744 == TX Byte 0 ==
4557 08:07:43.040810 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4558 08:07:43.044126 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4559 08:07:43.047680 == TX Byte 1 ==
4560 08:07:43.051241 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 08:07:43.054252 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 08:07:43.054361 ==
4563 08:07:43.057873 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 08:07:43.064579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 08:07:43.064672 ==
4566 08:07:43.064739
4567 08:07:43.064800
4568 08:07:43.064858 TX Vref Scan disable
4569 08:07:43.068687 == TX Byte 0 ==
4570 08:07:43.072246 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4571 08:07:43.078754 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4572 08:07:43.078832 == TX Byte 1 ==
4573 08:07:43.081934 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 08:07:43.088786 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 08:07:43.088871
4576 08:07:43.088936 [DATLAT]
4577 08:07:43.089008 Freq=600, CH1 RK0
4578 08:07:43.089074
4579 08:07:43.091789 DATLAT Default: 0x9
4580 08:07:43.091873 0, 0xFFFF, sum = 0
4581 08:07:43.095382 1, 0xFFFF, sum = 0
4582 08:07:43.095466 2, 0xFFFF, sum = 0
4583 08:07:43.098826 3, 0xFFFF, sum = 0
4584 08:07:43.101945 4, 0xFFFF, sum = 0
4585 08:07:43.102060 5, 0xFFFF, sum = 0
4586 08:07:43.105719 6, 0xFFFF, sum = 0
4587 08:07:43.105812 7, 0xFFFF, sum = 0
4588 08:07:43.108589 8, 0x0, sum = 1
4589 08:07:43.108665 9, 0x0, sum = 2
4590 08:07:43.108728 10, 0x0, sum = 3
4591 08:07:43.111977 11, 0x0, sum = 4
4592 08:07:43.112064 best_step = 9
4593 08:07:43.112129
4594 08:07:43.112198 ==
4595 08:07:43.115033 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 08:07:43.122039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 08:07:43.122126 ==
4598 08:07:43.122191 RX Vref Scan: 1
4599 08:07:43.122252
4600 08:07:43.125481 RX Vref 0 -> 0, step: 1
4601 08:07:43.125554
4602 08:07:43.128403 RX Delay -163 -> 252, step: 8
4603 08:07:43.128475
4604 08:07:43.131906 Set Vref, RX VrefLevel [Byte0]: 54
4605 08:07:43.135346 [Byte1]: 54
4606 08:07:43.135418
4607 08:07:43.138480 Final RX Vref Byte 0 = 54 to rank0
4608 08:07:43.141752 Final RX Vref Byte 1 = 54 to rank0
4609 08:07:43.144993 Final RX Vref Byte 0 = 54 to rank1
4610 08:07:43.148317 Final RX Vref Byte 1 = 54 to rank1==
4611 08:07:43.151723 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 08:07:43.155126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 08:07:43.155203 ==
4614 08:07:43.158658 DQS Delay:
4615 08:07:43.158734 DQS0 = 0, DQS1 = 0
4616 08:07:43.158803 DQM Delay:
4617 08:07:43.161531 DQM0 = 48, DQM1 = 44
4618 08:07:43.161603 DQ Delay:
4619 08:07:43.165445 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4620 08:07:43.168236 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4621 08:07:43.171833 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4622 08:07:43.175150 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4623 08:07:43.175224
4624 08:07:43.175286
4625 08:07:43.185523 [DQSOSCAuto] RK0, (LSB)MR18= 0x496e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4626 08:07:43.188279 CH1 RK0: MR19=808, MR18=496E
4627 08:07:43.191533 CH1_RK0: MR19=0x808, MR18=0x496E, DQSOSC=389, MR23=63, INC=173, DEC=115
4628 08:07:43.191608
4629 08:07:43.195192 ----->DramcWriteLeveling(PI) begin...
4630 08:07:43.198577 ==
4631 08:07:43.201593 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 08:07:43.205045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 08:07:43.205119 ==
4634 08:07:43.208435 Write leveling (Byte 0): 29 => 29
4635 08:07:43.212215 Write leveling (Byte 1): 30 => 30
4636 08:07:43.214929 DramcWriteLeveling(PI) end<-----
4637 08:07:43.215008
4638 08:07:43.215070 ==
4639 08:07:43.218369 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 08:07:43.221984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 08:07:43.222059 ==
4642 08:07:43.225158 [Gating] SW mode calibration
4643 08:07:43.231356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4644 08:07:43.238447 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4645 08:07:43.241707 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 08:07:43.245135 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 08:07:43.248449 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 08:07:43.254550 0 9 12 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 0)
4649 08:07:43.258077 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 08:07:43.261326 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 08:07:43.268122 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 08:07:43.271420 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 08:07:43.274479 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 08:07:43.281556 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 08:07:43.284571 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 08:07:43.288094 0 10 12 | B1->B0 | 3737 3636 | 0 1 | (0 0) (0 0)
4657 08:07:43.295166 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 08:07:43.298073 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 08:07:43.301774 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 08:07:43.308225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 08:07:43.311797 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 08:07:43.314865 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 08:07:43.321763 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4664 08:07:43.324795 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4665 08:07:43.328136 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 08:07:43.335004 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 08:07:43.337996 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 08:07:43.341683 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 08:07:43.347758 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 08:07:43.351284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 08:07:43.354970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 08:07:43.361438 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 08:07:43.364553 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 08:07:43.368194 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 08:07:43.374472 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 08:07:43.377801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 08:07:43.380954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 08:07:43.387450 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 08:07:43.391087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4680 08:07:43.394380 Total UI for P1: 0, mck2ui 16
4681 08:07:43.397499 best dqsien dly found for B1: ( 0, 13, 6)
4682 08:07:43.401112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4683 08:07:43.404426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 08:07:43.407391 Total UI for P1: 0, mck2ui 16
4685 08:07:43.411152 best dqsien dly found for B0: ( 0, 13, 10)
4686 08:07:43.414263 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4687 08:07:43.420708 best DQS1 dly(MCK, UI, PI) = (0, 13, 6)
4688 08:07:43.420791
4689 08:07:43.424600 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4690 08:07:43.427870 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 6)
4691 08:07:43.431238 [Gating] SW calibration Done
4692 08:07:43.431339 ==
4693 08:07:43.434032 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 08:07:43.437310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 08:07:43.437382 ==
4696 08:07:43.437446 RX Vref Scan: 0
4697 08:07:43.440600
4698 08:07:43.440676 RX Vref 0 -> 0, step: 1
4699 08:07:43.440745
4700 08:07:43.444016 RX Delay -230 -> 252, step: 16
4701 08:07:43.447297 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4702 08:07:43.454002 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4703 08:07:43.457601 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4704 08:07:43.460627 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4705 08:07:43.464135 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4706 08:07:43.467865 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4707 08:07:43.473972 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4708 08:07:43.477493 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4709 08:07:43.480548 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4710 08:07:43.484168 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4711 08:07:43.490652 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4712 08:07:43.494044 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4713 08:07:43.496903 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4714 08:07:43.500430 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4715 08:07:43.507342 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4716 08:07:43.510503 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4717 08:07:43.510585 ==
4718 08:07:43.513569 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 08:07:43.517057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 08:07:43.517161 ==
4721 08:07:43.520098 DQS Delay:
4722 08:07:43.520216 DQS0 = 0, DQS1 = 0
4723 08:07:43.520308 DQM Delay:
4724 08:07:43.523726 DQM0 = 50, DQM1 = 48
4725 08:07:43.523826 DQ Delay:
4726 08:07:43.526676 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4727 08:07:43.530343 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4728 08:07:43.533764 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4729 08:07:43.537074 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4730 08:07:43.537172
4731 08:07:43.537236
4732 08:07:43.537295 ==
4733 08:07:43.540137 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 08:07:43.546762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 08:07:43.546848 ==
4736 08:07:43.546914
4737 08:07:43.546973
4738 08:07:43.547031 TX Vref Scan disable
4739 08:07:43.550133 == TX Byte 0 ==
4740 08:07:43.553707 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4741 08:07:43.556634 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4742 08:07:43.559987 == TX Byte 1 ==
4743 08:07:43.563695 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4744 08:07:43.570267 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4745 08:07:43.570346 ==
4746 08:07:43.573472 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 08:07:43.577029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 08:07:43.577108 ==
4749 08:07:43.577172
4750 08:07:43.577232
4751 08:07:43.579976 TX Vref Scan disable
4752 08:07:43.583061 == TX Byte 0 ==
4753 08:07:43.586840 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4754 08:07:43.589788 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4755 08:07:43.593640 == TX Byte 1 ==
4756 08:07:43.596362 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4757 08:07:43.599738 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4758 08:07:43.599821
4759 08:07:43.599909 [DATLAT]
4760 08:07:43.602856 Freq=600, CH1 RK1
4761 08:07:43.602952
4762 08:07:43.606473 DATLAT Default: 0x9
4763 08:07:43.606544 0, 0xFFFF, sum = 0
4764 08:07:43.610098 1, 0xFFFF, sum = 0
4765 08:07:43.610212 2, 0xFFFF, sum = 0
4766 08:07:43.613202 3, 0xFFFF, sum = 0
4767 08:07:43.613302 4, 0xFFFF, sum = 0
4768 08:07:43.616074 5, 0xFFFF, sum = 0
4769 08:07:43.616189 6, 0xFFFF, sum = 0
4770 08:07:43.619713 7, 0xFFFF, sum = 0
4771 08:07:43.619813 8, 0x0, sum = 1
4772 08:07:43.622951 9, 0x0, sum = 2
4773 08:07:43.623025 10, 0x0, sum = 3
4774 08:07:43.626280 11, 0x0, sum = 4
4775 08:07:43.626385 best_step = 9
4776 08:07:43.626476
4777 08:07:43.626581 ==
4778 08:07:43.629640 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 08:07:43.632608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 08:07:43.632709 ==
4781 08:07:43.635959 RX Vref Scan: 0
4782 08:07:43.636036
4783 08:07:43.639309 RX Vref 0 -> 0, step: 1
4784 08:07:43.639396
4785 08:07:43.639499 RX Delay -163 -> 252, step: 8
4786 08:07:43.646898 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4787 08:07:43.650343 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4788 08:07:43.653769 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4789 08:07:43.657044 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4790 08:07:43.660387 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4791 08:07:43.666865 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4792 08:07:43.670378 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4793 08:07:43.673883 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4794 08:07:43.677072 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4795 08:07:43.683786 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4796 08:07:43.687537 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4797 08:07:43.690270 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4798 08:07:43.693431 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4799 08:07:43.696991 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4800 08:07:43.703556 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4801 08:07:43.706696 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4802 08:07:43.706815 ==
4803 08:07:43.710468 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 08:07:43.713496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 08:07:43.713619 ==
4806 08:07:43.716825 DQS Delay:
4807 08:07:43.716947 DQS0 = 0, DQS1 = 0
4808 08:07:43.717060 DQM Delay:
4809 08:07:43.720130 DQM0 = 49, DQM1 = 46
4810 08:07:43.720254 DQ Delay:
4811 08:07:43.723190 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4812 08:07:43.726797 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4813 08:07:43.729830 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4814 08:07:43.733211 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4815 08:07:43.733331
4816 08:07:43.733443
4817 08:07:43.743891 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4818 08:07:43.744021 CH1 RK1: MR19=808, MR18=6C23
4819 08:07:43.750203 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4820 08:07:43.753187 [RxdqsGatingPostProcess] freq 600
4821 08:07:43.759969 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4822 08:07:43.763089 Pre-setting of DQS Precalculation
4823 08:07:43.766615 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4824 08:07:43.773090 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4825 08:07:43.783426 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4826 08:07:43.783539
4827 08:07:43.783632
4828 08:07:43.787074 [Calibration Summary] 1200 Mbps
4829 08:07:43.787184 CH 0, Rank 0
4830 08:07:43.789750 SW Impedance : PASS
4831 08:07:43.789868 DUTY Scan : NO K
4832 08:07:43.793323 ZQ Calibration : PASS
4833 08:07:43.796299 Jitter Meter : NO K
4834 08:07:43.796376 CBT Training : PASS
4835 08:07:43.799883 Write leveling : PASS
4836 08:07:43.802953 RX DQS gating : PASS
4837 08:07:43.803061 RX DQ/DQS(RDDQC) : PASS
4838 08:07:43.806661 TX DQ/DQS : PASS
4839 08:07:43.806770 RX DATLAT : PASS
4840 08:07:43.809580 RX DQ/DQS(Engine): PASS
4841 08:07:43.813004 TX OE : NO K
4842 08:07:43.813135 All Pass.
4843 08:07:43.813254
4844 08:07:43.813372 CH 0, Rank 1
4845 08:07:43.816026 SW Impedance : PASS
4846 08:07:43.819656 DUTY Scan : NO K
4847 08:07:43.819785 ZQ Calibration : PASS
4848 08:07:43.822774 Jitter Meter : NO K
4849 08:07:43.826347 CBT Training : PASS
4850 08:07:43.826473 Write leveling : PASS
4851 08:07:43.829297 RX DQS gating : PASS
4852 08:07:43.832912 RX DQ/DQS(RDDQC) : PASS
4853 08:07:43.832990 TX DQ/DQS : PASS
4854 08:07:43.835980 RX DATLAT : PASS
4855 08:07:43.839741 RX DQ/DQS(Engine): PASS
4856 08:07:43.839844 TX OE : NO K
4857 08:07:43.843133 All Pass.
4858 08:07:43.843237
4859 08:07:43.843329 CH 1, Rank 0
4860 08:07:43.846368 SW Impedance : PASS
4861 08:07:43.846474 DUTY Scan : NO K
4862 08:07:43.849143 ZQ Calibration : PASS
4863 08:07:43.852960 Jitter Meter : NO K
4864 08:07:43.853038 CBT Training : PASS
4865 08:07:43.856024 Write leveling : PASS
4866 08:07:43.859420 RX DQS gating : PASS
4867 08:07:43.859495 RX DQ/DQS(RDDQC) : PASS
4868 08:07:43.862812 TX DQ/DQS : PASS
4869 08:07:43.862885 RX DATLAT : PASS
4870 08:07:43.865672 RX DQ/DQS(Engine): PASS
4871 08:07:43.869226 TX OE : NO K
4872 08:07:43.869301 All Pass.
4873 08:07:43.869363
4874 08:07:43.869421 CH 1, Rank 1
4875 08:07:43.872567 SW Impedance : PASS
4876 08:07:43.875810 DUTY Scan : NO K
4877 08:07:43.875888 ZQ Calibration : PASS
4878 08:07:43.879317 Jitter Meter : NO K
4879 08:07:43.882805 CBT Training : PASS
4880 08:07:43.882883 Write leveling : PASS
4881 08:07:43.886145 RX DQS gating : PASS
4882 08:07:43.889345 RX DQ/DQS(RDDQC) : PASS
4883 08:07:43.889475 TX DQ/DQS : PASS
4884 08:07:43.892406 RX DATLAT : PASS
4885 08:07:43.896153 RX DQ/DQS(Engine): PASS
4886 08:07:43.896299 TX OE : NO K
4887 08:07:43.899299 All Pass.
4888 08:07:43.899433
4889 08:07:43.899541 DramC Write-DBI off
4890 08:07:43.902600 PER_BANK_REFRESH: Hybrid Mode
4891 08:07:43.902710 TX_TRACKING: ON
4892 08:07:43.912549 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4893 08:07:43.915499 [FAST_K] Save calibration result to emmc
4894 08:07:43.919200 dramc_set_vcore_voltage set vcore to 662500
4895 08:07:43.922339 Read voltage for 933, 3
4896 08:07:43.922414 Vio18 = 0
4897 08:07:43.925392 Vcore = 662500
4898 08:07:43.925492 Vdram = 0
4899 08:07:43.925582 Vddq = 0
4900 08:07:43.929317 Vmddr = 0
4901 08:07:43.932015 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4902 08:07:43.939172 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4903 08:07:43.939279 MEM_TYPE=3, freq_sel=17
4904 08:07:43.942026 sv_algorithm_assistance_LP4_1600
4905 08:07:43.945673 ============ PULL DRAM RESETB DOWN ============
4906 08:07:43.952268 ========== PULL DRAM RESETB DOWN end =========
4907 08:07:43.955630 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4908 08:07:43.958807 ===================================
4909 08:07:43.961847 LPDDR4 DRAM CONFIGURATION
4910 08:07:43.965272 ===================================
4911 08:07:43.965375 EX_ROW_EN[0] = 0x0
4912 08:07:43.968328 EX_ROW_EN[1] = 0x0
4913 08:07:43.972179 LP4Y_EN = 0x0
4914 08:07:43.972282 WORK_FSP = 0x0
4915 08:07:43.975248 WL = 0x3
4916 08:07:43.975323 RL = 0x3
4917 08:07:43.978615 BL = 0x2
4918 08:07:43.978684 RPST = 0x0
4919 08:07:43.981908 RD_PRE = 0x0
4920 08:07:43.981987 WR_PRE = 0x1
4921 08:07:43.985230 WR_PST = 0x0
4922 08:07:43.985334 DBI_WR = 0x0
4923 08:07:43.988454 DBI_RD = 0x0
4924 08:07:43.988532 OTF = 0x1
4925 08:07:43.992035 ===================================
4926 08:07:43.995486 ===================================
4927 08:07:43.998430 ANA top config
4928 08:07:44.001899 ===================================
4929 08:07:44.002009 DLL_ASYNC_EN = 0
4930 08:07:44.005571 ALL_SLAVE_EN = 1
4931 08:07:44.008820 NEW_RANK_MODE = 1
4932 08:07:44.011770 DLL_IDLE_MODE = 1
4933 08:07:44.015006 LP45_APHY_COMB_EN = 1
4934 08:07:44.015107 TX_ODT_DIS = 1
4935 08:07:44.018467 NEW_8X_MODE = 1
4936 08:07:44.021537 ===================================
4937 08:07:44.025324 ===================================
4938 08:07:44.028238 data_rate = 1866
4939 08:07:44.032041 CKR = 1
4940 08:07:44.034942 DQ_P2S_RATIO = 8
4941 08:07:44.038380 ===================================
4942 08:07:44.038488 CA_P2S_RATIO = 8
4943 08:07:44.041916 DQ_CA_OPEN = 0
4944 08:07:44.044795 DQ_SEMI_OPEN = 0
4945 08:07:44.048513 CA_SEMI_OPEN = 0
4946 08:07:44.052009 CA_FULL_RATE = 0
4947 08:07:44.054911 DQ_CKDIV4_EN = 1
4948 08:07:44.055032 CA_CKDIV4_EN = 1
4949 08:07:44.058662 CA_PREDIV_EN = 0
4950 08:07:44.061627 PH8_DLY = 0
4951 08:07:44.064786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4952 08:07:44.068441 DQ_AAMCK_DIV = 4
4953 08:07:44.071509 CA_AAMCK_DIV = 4
4954 08:07:44.071617 CA_ADMCK_DIV = 4
4955 08:07:44.075316 DQ_TRACK_CA_EN = 0
4956 08:07:44.078136 CA_PICK = 933
4957 08:07:44.081255 CA_MCKIO = 933
4958 08:07:44.084931 MCKIO_SEMI = 0
4959 08:07:44.087948 PLL_FREQ = 3732
4960 08:07:44.091960 DQ_UI_PI_RATIO = 32
4961 08:07:44.092049 CA_UI_PI_RATIO = 0
4962 08:07:44.094913 ===================================
4963 08:07:44.097994 ===================================
4964 08:07:44.101516 memory_type:LPDDR4
4965 08:07:44.105054 GP_NUM : 10
4966 08:07:44.105159 SRAM_EN : 1
4967 08:07:44.108188 MD32_EN : 0
4968 08:07:44.111842 ===================================
4969 08:07:44.114945 [ANA_INIT] >>>>>>>>>>>>>>
4970 08:07:44.118454 <<<<<< [CONFIGURE PHASE]: ANA_TX
4971 08:07:44.121538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4972 08:07:44.124946 ===================================
4973 08:07:44.125023 data_rate = 1866,PCW = 0X8f00
4974 08:07:44.128115 ===================================
4975 08:07:44.131414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4976 08:07:44.138070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 08:07:44.144529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4978 08:07:44.148182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4979 08:07:44.151317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4980 08:07:44.154966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4981 08:07:44.157917 [ANA_INIT] flow start
4982 08:07:44.157996 [ANA_INIT] PLL >>>>>>>>
4983 08:07:44.161387 [ANA_INIT] PLL <<<<<<<<
4984 08:07:44.165131 [ANA_INIT] MIDPI >>>>>>>>
4985 08:07:44.168158 [ANA_INIT] MIDPI <<<<<<<<
4986 08:07:44.168242 [ANA_INIT] DLL >>>>>>>>
4987 08:07:44.171417 [ANA_INIT] flow end
4988 08:07:44.174857 ============ LP4 DIFF to SE enter ============
4989 08:07:44.177917 ============ LP4 DIFF to SE exit ============
4990 08:07:44.181398 [ANA_INIT] <<<<<<<<<<<<<
4991 08:07:44.184418 [Flow] Enable top DCM control >>>>>
4992 08:07:44.187967 [Flow] Enable top DCM control <<<<<
4993 08:07:44.191707 Enable DLL master slave shuffle
4994 08:07:44.197819 ==============================================================
4995 08:07:44.197904 Gating Mode config
4996 08:07:44.204869 ==============================================================
4997 08:07:44.204956 Config description:
4998 08:07:44.214654 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4999 08:07:44.221362 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5000 08:07:44.228051 SELPH_MODE 0: By rank 1: By Phase
5001 08:07:44.231035 ==============================================================
5002 08:07:44.234554 GAT_TRACK_EN = 1
5003 08:07:44.238092 RX_GATING_MODE = 2
5004 08:07:44.240953 RX_GATING_TRACK_MODE = 2
5005 08:07:44.244640 SELPH_MODE = 1
5006 08:07:44.247877 PICG_EARLY_EN = 1
5007 08:07:44.251062 VALID_LAT_VALUE = 1
5008 08:07:44.254603 ==============================================================
5009 08:07:44.257944 Enter into Gating configuration >>>>
5010 08:07:44.260972 Exit from Gating configuration <<<<
5011 08:07:44.264417 Enter into DVFS_PRE_config >>>>>
5012 08:07:44.277465 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5013 08:07:44.281353 Exit from DVFS_PRE_config <<<<<
5014 08:07:44.284130 Enter into PICG configuration >>>>
5015 08:07:44.284244 Exit from PICG configuration <<<<
5016 08:07:44.287817 [RX_INPUT] configuration >>>>>
5017 08:07:44.291087 [RX_INPUT] configuration <<<<<
5018 08:07:44.297447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5019 08:07:44.300955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5020 08:07:44.307307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5021 08:07:44.314157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5022 08:07:44.321115 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 08:07:44.327353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 08:07:44.330526 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5025 08:07:44.334128 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5026 08:07:44.337659 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5027 08:07:44.344075 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5028 08:07:44.347470 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5029 08:07:44.351083 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5030 08:07:44.354108 ===================================
5031 08:07:44.357640 LPDDR4 DRAM CONFIGURATION
5032 08:07:44.361023 ===================================
5033 08:07:44.364245 EX_ROW_EN[0] = 0x0
5034 08:07:44.364348 EX_ROW_EN[1] = 0x0
5035 08:07:44.367591 LP4Y_EN = 0x0
5036 08:07:44.367690 WORK_FSP = 0x0
5037 08:07:44.370777 WL = 0x3
5038 08:07:44.370852 RL = 0x3
5039 08:07:44.374142 BL = 0x2
5040 08:07:44.374220 RPST = 0x0
5041 08:07:44.377334 RD_PRE = 0x0
5042 08:07:44.377469 WR_PRE = 0x1
5043 08:07:44.381279 WR_PST = 0x0
5044 08:07:44.381411 DBI_WR = 0x0
5045 08:07:44.384271 DBI_RD = 0x0
5046 08:07:44.384383 OTF = 0x1
5047 08:07:44.387451 ===================================
5048 08:07:44.390832 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5049 08:07:44.397606 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5050 08:07:44.400639 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 08:07:44.404238 ===================================
5052 08:07:44.407514 LPDDR4 DRAM CONFIGURATION
5053 08:07:44.410814 ===================================
5054 08:07:44.410889 EX_ROW_EN[0] = 0x10
5055 08:07:44.414278 EX_ROW_EN[1] = 0x0
5056 08:07:44.414351 LP4Y_EN = 0x0
5057 08:07:44.417588 WORK_FSP = 0x0
5058 08:07:44.421039 WL = 0x3
5059 08:07:44.421134 RL = 0x3
5060 08:07:44.424176 BL = 0x2
5061 08:07:44.424277 RPST = 0x0
5062 08:07:44.427622 RD_PRE = 0x0
5063 08:07:44.427705 WR_PRE = 0x1
5064 08:07:44.430826 WR_PST = 0x0
5065 08:07:44.430902 DBI_WR = 0x0
5066 08:07:44.434328 DBI_RD = 0x0
5067 08:07:44.434429 OTF = 0x1
5068 08:07:44.437447 ===================================
5069 08:07:44.444266 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5070 08:07:44.448315 nWR fixed to 30
5071 08:07:44.451199 [ModeRegInit_LP4] CH0 RK0
5072 08:07:44.451304 [ModeRegInit_LP4] CH0 RK1
5073 08:07:44.454836 [ModeRegInit_LP4] CH1 RK0
5074 08:07:44.458011 [ModeRegInit_LP4] CH1 RK1
5075 08:07:44.458094 match AC timing 9
5076 08:07:44.464434 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5077 08:07:44.468066 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5078 08:07:44.471746 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5079 08:07:44.477808 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5080 08:07:44.481401 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5081 08:07:44.481504 ==
5082 08:07:44.484501 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 08:07:44.488261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 08:07:44.488347 ==
5085 08:07:44.494954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 08:07:44.501092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5087 08:07:44.504833 [CA 0] Center 37 (7~68) winsize 62
5088 08:07:44.508161 [CA 1] Center 37 (7~68) winsize 62
5089 08:07:44.511677 [CA 2] Center 34 (4~65) winsize 62
5090 08:07:44.514518 [CA 3] Center 33 (3~64) winsize 62
5091 08:07:44.517633 [CA 4] Center 33 (3~64) winsize 62
5092 08:07:44.521367 [CA 5] Center 32 (2~62) winsize 61
5093 08:07:44.521474
5094 08:07:44.524327 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5095 08:07:44.524419
5096 08:07:44.527816 [CATrainingPosCal] consider 1 rank data
5097 08:07:44.531194 u2DelayCellTimex100 = 270/100 ps
5098 08:07:44.534779 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5099 08:07:44.537952 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5100 08:07:44.541254 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5101 08:07:44.544268 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5102 08:07:44.547737 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5103 08:07:44.551165 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5104 08:07:44.551247
5105 08:07:44.557983 CA PerBit enable=1, Macro0, CA PI delay=32
5106 08:07:44.558088
5107 08:07:44.561061 [CBTSetCACLKResult] CA Dly = 32
5108 08:07:44.561160 CS Dly: 5 (0~36)
5109 08:07:44.561248 ==
5110 08:07:44.564824 Dram Type= 6, Freq= 0, CH_0, rank 1
5111 08:07:44.567604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 08:07:44.567695 ==
5113 08:07:44.574609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 08:07:44.581039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5115 08:07:44.584505 [CA 0] Center 37 (6~68) winsize 63
5116 08:07:44.587471 [CA 1] Center 37 (7~68) winsize 62
5117 08:07:44.590975 [CA 2] Center 34 (4~65) winsize 62
5118 08:07:44.594574 [CA 3] Center 34 (4~65) winsize 62
5119 08:07:44.597439 [CA 4] Center 33 (3~63) winsize 61
5120 08:07:44.601118 [CA 5] Center 32 (2~62) winsize 61
5121 08:07:44.601221
5122 08:07:44.604127 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5123 08:07:44.604207
5124 08:07:44.607993 [CATrainingPosCal] consider 2 rank data
5125 08:07:44.610959 u2DelayCellTimex100 = 270/100 ps
5126 08:07:44.614518 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5127 08:07:44.617708 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5128 08:07:44.621147 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5129 08:07:44.624324 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5130 08:07:44.627999 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5131 08:07:44.634090 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5132 08:07:44.634176
5133 08:07:44.637291 CA PerBit enable=1, Macro0, CA PI delay=32
5134 08:07:44.637377
5135 08:07:44.641021 [CBTSetCACLKResult] CA Dly = 32
5136 08:07:44.641136 CS Dly: 6 (0~38)
5137 08:07:44.641232
5138 08:07:44.644469 ----->DramcWriteLeveling(PI) begin...
5139 08:07:44.644548 ==
5140 08:07:44.647808 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 08:07:44.650936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 08:07:44.654074 ==
5143 08:07:44.654180 Write leveling (Byte 0): 32 => 32
5144 08:07:44.657659 Write leveling (Byte 1): 29 => 29
5145 08:07:44.660973 DramcWriteLeveling(PI) end<-----
5146 08:07:44.661060
5147 08:07:44.661146 ==
5148 08:07:44.664418 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 08:07:44.670854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 08:07:44.670966 ==
5151 08:07:44.671069 [Gating] SW mode calibration
5152 08:07:44.681143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5153 08:07:44.684493 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5154 08:07:44.691169 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5155 08:07:44.694129 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 08:07:44.697951 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 08:07:44.700672 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 08:07:44.707786 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 08:07:44.710937 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 08:07:44.714474 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5161 08:07:44.720980 0 14 28 | B1->B0 | 3333 2929 | 0 0 | (0 1) (1 1)
5162 08:07:44.723901 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5163 08:07:44.727553 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 08:07:44.733897 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 08:07:44.737247 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 08:07:44.741160 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 08:07:44.747356 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 08:07:44.751138 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5169 08:07:44.753784 0 15 28 | B1->B0 | 2727 3a3a | 1 0 | (0 0) (0 0)
5170 08:07:44.760416 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5171 08:07:44.763756 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 08:07:44.767159 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 08:07:44.773849 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 08:07:44.777438 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 08:07:44.780661 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 08:07:44.787190 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 08:07:44.790622 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5178 08:07:44.793813 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 08:07:44.800304 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 08:07:44.803961 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 08:07:44.807020 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 08:07:44.813540 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 08:07:44.817270 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 08:07:44.820745 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 08:07:44.827331 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 08:07:44.830225 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 08:07:44.833957 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 08:07:44.836872 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 08:07:44.843307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 08:07:44.847012 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 08:07:44.850123 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 08:07:44.856989 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5193 08:07:44.860204 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5194 08:07:44.863412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5195 08:07:44.866765 Total UI for P1: 0, mck2ui 16
5196 08:07:44.870030 best dqsien dly found for B0: ( 1, 2, 26)
5197 08:07:44.876874 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 08:07:44.876991 Total UI for P1: 0, mck2ui 16
5199 08:07:44.883831 best dqsien dly found for B1: ( 1, 3, 0)
5200 08:07:44.887258 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5201 08:07:44.890805 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5202 08:07:44.890882
5203 08:07:44.893514 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5204 08:07:44.897032 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5205 08:07:44.900187 [Gating] SW calibration Done
5206 08:07:44.900270 ==
5207 08:07:44.903535 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 08:07:44.907055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 08:07:44.907163 ==
5210 08:07:44.909990 RX Vref Scan: 0
5211 08:07:44.910097
5212 08:07:44.910195 RX Vref 0 -> 0, step: 1
5213 08:07:44.910285
5214 08:07:44.913525 RX Delay -80 -> 252, step: 8
5215 08:07:44.916865 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5216 08:07:44.923657 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5217 08:07:44.926603 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5218 08:07:44.930182 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5219 08:07:44.933029 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5220 08:07:44.936827 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5221 08:07:44.939813 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5222 08:07:44.946542 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5223 08:07:44.950160 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5224 08:07:44.953006 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5225 08:07:44.956588 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5226 08:07:44.960143 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5227 08:07:44.963736 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5228 08:07:44.970198 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5229 08:07:44.973015 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5230 08:07:44.976812 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5231 08:07:44.976897 ==
5232 08:07:44.979910 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 08:07:44.983086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 08:07:44.986327 ==
5235 08:07:44.986402 DQS Delay:
5236 08:07:44.986466 DQS0 = 0, DQS1 = 0
5237 08:07:44.989507 DQM Delay:
5238 08:07:44.989585 DQM0 = 103, DQM1 = 95
5239 08:07:44.993271 DQ Delay:
5240 08:07:44.996530 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5241 08:07:44.999481 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5242 08:07:45.002897 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5243 08:07:45.006254 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5244 08:07:45.006377
5245 08:07:45.006493
5246 08:07:45.006607 ==
5247 08:07:45.009515 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 08:07:45.012852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 08:07:45.012939 ==
5250 08:07:45.013026
5251 08:07:45.013107
5252 08:07:45.016698 TX Vref Scan disable
5253 08:07:45.016780 == TX Byte 0 ==
5254 08:07:45.022903 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5255 08:07:45.026149 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5256 08:07:45.026230 == TX Byte 1 ==
5257 08:07:45.032855 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5258 08:07:45.036487 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5259 08:07:45.036568 ==
5260 08:07:45.039528 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 08:07:45.043047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 08:07:45.043132 ==
5263 08:07:45.043200
5264 08:07:45.043262
5265 08:07:45.046487 TX Vref Scan disable
5266 08:07:45.050057 == TX Byte 0 ==
5267 08:07:45.053276 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5268 08:07:45.056220 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5269 08:07:45.059606 == TX Byte 1 ==
5270 08:07:45.063313 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5271 08:07:45.066191 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5272 08:07:45.066301
5273 08:07:45.069722 [DATLAT]
5274 08:07:45.069831 Freq=933, CH0 RK0
5275 08:07:45.069929
5276 08:07:45.073308 DATLAT Default: 0xd
5277 08:07:45.073392 0, 0xFFFF, sum = 0
5278 08:07:45.076122 1, 0xFFFF, sum = 0
5279 08:07:45.076202 2, 0xFFFF, sum = 0
5280 08:07:45.079545 3, 0xFFFF, sum = 0
5281 08:07:45.079656 4, 0xFFFF, sum = 0
5282 08:07:45.082529 5, 0xFFFF, sum = 0
5283 08:07:45.082606 6, 0xFFFF, sum = 0
5284 08:07:45.086207 7, 0xFFFF, sum = 0
5285 08:07:45.089478 8, 0xFFFF, sum = 0
5286 08:07:45.089557 9, 0xFFFF, sum = 0
5287 08:07:45.092596 10, 0x0, sum = 1
5288 08:07:45.092670 11, 0x0, sum = 2
5289 08:07:45.092736 12, 0x0, sum = 3
5290 08:07:45.096342 13, 0x0, sum = 4
5291 08:07:45.096419 best_step = 11
5292 08:07:45.096480
5293 08:07:45.096538 ==
5294 08:07:45.099691 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 08:07:45.106385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 08:07:45.106472 ==
5297 08:07:45.106549 RX Vref Scan: 1
5298 08:07:45.106613
5299 08:07:45.109734 RX Vref 0 -> 0, step: 1
5300 08:07:45.109811
5301 08:07:45.112743 RX Delay -53 -> 252, step: 4
5302 08:07:45.112821
5303 08:07:45.116185 Set Vref, RX VrefLevel [Byte0]: 55
5304 08:07:45.119460 [Byte1]: 47
5305 08:07:45.119542
5306 08:07:45.122824 Final RX Vref Byte 0 = 55 to rank0
5307 08:07:45.126252 Final RX Vref Byte 1 = 47 to rank0
5308 08:07:45.129663 Final RX Vref Byte 0 = 55 to rank1
5309 08:07:45.132688 Final RX Vref Byte 1 = 47 to rank1==
5310 08:07:45.136321 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 08:07:45.139308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 08:07:45.139417 ==
5313 08:07:45.142916 DQS Delay:
5314 08:07:45.143020 DQS0 = 0, DQS1 = 0
5315 08:07:45.145625 DQM Delay:
5316 08:07:45.145728 DQM0 = 104, DQM1 = 95
5317 08:07:45.145812 DQ Delay:
5318 08:07:45.149624 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5319 08:07:45.152441 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5320 08:07:45.155973 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5321 08:07:45.162654 DQ12 =102, DQ13 =100, DQ14 =106, DQ15 =104
5322 08:07:45.162731
5323 08:07:45.162794
5324 08:07:45.169391 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5325 08:07:45.172264 CH0 RK0: MR19=505, MR18=3028
5326 08:07:45.178758 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5327 08:07:45.178838
5328 08:07:45.182186 ----->DramcWriteLeveling(PI) begin...
5329 08:07:45.182301 ==
5330 08:07:45.185896 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 08:07:45.189534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 08:07:45.189617 ==
5333 08:07:45.192516 Write leveling (Byte 0): 34 => 34
5334 08:07:45.195359 Write leveling (Byte 1): 30 => 30
5335 08:07:45.198980 DramcWriteLeveling(PI) end<-----
5336 08:07:45.199089
5337 08:07:45.199190 ==
5338 08:07:45.201973 Dram Type= 6, Freq= 0, CH_0, rank 1
5339 08:07:45.205150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 08:07:45.205228 ==
5341 08:07:45.208689 [Gating] SW mode calibration
5342 08:07:45.215512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5343 08:07:45.221921 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5344 08:07:45.225253 0 14 0 | B1->B0 | 302f 3333 | 1 1 | (0 0) (1 1)
5345 08:07:45.231888 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 08:07:45.235422 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 08:07:45.238681 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 08:07:45.245212 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 08:07:45.249004 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 08:07:45.251836 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5351 08:07:45.258924 0 14 28 | B1->B0 | 2e2e 2e2e | 0 0 | (0 1) (0 1)
5352 08:07:45.261737 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 08:07:45.265456 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 08:07:45.271885 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 08:07:45.274967 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 08:07:45.278446 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 08:07:45.281680 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 08:07:45.288269 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 08:07:45.292039 0 15 28 | B1->B0 | 3b3b 3434 | 0 0 | (0 0) (0 0)
5360 08:07:45.295128 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5361 08:07:45.301578 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 08:07:45.305349 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 08:07:45.308604 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 08:07:45.315051 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 08:07:45.318456 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 08:07:45.321952 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 08:07:45.328525 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5368 08:07:45.331734 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5369 08:07:45.335107 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 08:07:45.341445 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 08:07:45.344947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 08:07:45.348071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 08:07:45.354593 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 08:07:45.358087 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 08:07:45.361739 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 08:07:45.368289 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 08:07:45.371529 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 08:07:45.374713 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 08:07:45.381339 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 08:07:45.384838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 08:07:45.388067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 08:07:45.394421 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 08:07:45.397830 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5384 08:07:45.401620 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5385 08:07:45.404562 Total UI for P1: 0, mck2ui 16
5386 08:07:45.408081 best dqsien dly found for B1: ( 1, 2, 28)
5387 08:07:45.414601 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 08:07:45.414682 Total UI for P1: 0, mck2ui 16
5389 08:07:45.417855 best dqsien dly found for B0: ( 1, 2, 30)
5390 08:07:45.424526 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5391 08:07:45.427947 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5392 08:07:45.428029
5393 08:07:45.431466 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5394 08:07:45.434981 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5395 08:07:45.437659 [Gating] SW calibration Done
5396 08:07:45.437740 ==
5397 08:07:45.441199 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 08:07:45.444601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 08:07:45.444710 ==
5400 08:07:45.448007 RX Vref Scan: 0
5401 08:07:45.448102
5402 08:07:45.448194 RX Vref 0 -> 0, step: 1
5403 08:07:45.448283
5404 08:07:45.451173 RX Delay -80 -> 252, step: 8
5405 08:07:45.454939 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5406 08:07:45.458300 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5407 08:07:45.464599 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5408 08:07:45.467791 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5409 08:07:45.471371 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5410 08:07:45.474597 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5411 08:07:45.477578 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5412 08:07:45.484037 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5413 08:07:45.487865 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5414 08:07:45.491245 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5415 08:07:45.494524 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5416 08:07:45.497968 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5417 08:07:45.500791 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5418 08:07:45.507510 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5419 08:07:45.510893 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5420 08:07:45.514454 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5421 08:07:45.514536 ==
5422 08:07:45.517956 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 08:07:45.521020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 08:07:45.521103 ==
5425 08:07:45.524539 DQS Delay:
5426 08:07:45.524620 DQS0 = 0, DQS1 = 0
5427 08:07:45.524685 DQM Delay:
5428 08:07:45.528116 DQM0 = 105, DQM1 = 93
5429 08:07:45.528197 DQ Delay:
5430 08:07:45.531303 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5431 08:07:45.534470 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5432 08:07:45.537568 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5433 08:07:45.540918 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5434 08:07:45.541003
5435 08:07:45.541068
5436 08:07:45.544222 ==
5437 08:07:45.547746 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 08:07:45.550790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 08:07:45.550866 ==
5440 08:07:45.550930
5441 08:07:45.550991
5442 08:07:45.554373 TX Vref Scan disable
5443 08:07:45.554488 == TX Byte 0 ==
5444 08:07:45.560911 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5445 08:07:45.564167 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5446 08:07:45.564276 == TX Byte 1 ==
5447 08:07:45.570815 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5448 08:07:45.573943 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5449 08:07:45.574050 ==
5450 08:07:45.577170 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 08:07:45.580840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 08:07:45.580925 ==
5453 08:07:45.581007
5454 08:07:45.581117
5455 08:07:45.583972 TX Vref Scan disable
5456 08:07:45.587517 == TX Byte 0 ==
5457 08:07:45.590701 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5458 08:07:45.594172 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5459 08:07:45.597342 == TX Byte 1 ==
5460 08:07:45.600919 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5461 08:07:45.604105 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5462 08:07:45.604180
5463 08:07:45.607535 [DATLAT]
5464 08:07:45.607645 Freq=933, CH0 RK1
5465 08:07:45.607712
5466 08:07:45.611159 DATLAT Default: 0xb
5467 08:07:45.611274 0, 0xFFFF, sum = 0
5468 08:07:45.614051 1, 0xFFFF, sum = 0
5469 08:07:45.614129 2, 0xFFFF, sum = 0
5470 08:07:45.617668 3, 0xFFFF, sum = 0
5471 08:07:45.617752 4, 0xFFFF, sum = 0
5472 08:07:45.620557 5, 0xFFFF, sum = 0
5473 08:07:45.620631 6, 0xFFFF, sum = 0
5474 08:07:45.624299 7, 0xFFFF, sum = 0
5475 08:07:45.624373 8, 0xFFFF, sum = 0
5476 08:07:45.627204 9, 0xFFFF, sum = 0
5477 08:07:45.627304 10, 0x0, sum = 1
5478 08:07:45.630416 11, 0x0, sum = 2
5479 08:07:45.630489 12, 0x0, sum = 3
5480 08:07:45.634173 13, 0x0, sum = 4
5481 08:07:45.634283 best_step = 11
5482 08:07:45.634379
5483 08:07:45.634476 ==
5484 08:07:45.637435 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 08:07:45.640910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 08:07:45.643821 ==
5487 08:07:45.643906 RX Vref Scan: 0
5488 08:07:45.643973
5489 08:07:45.647015 RX Vref 0 -> 0, step: 1
5490 08:07:45.647091
5491 08:07:45.650592 RX Delay -53 -> 252, step: 4
5492 08:07:45.653943 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5493 08:07:45.657434 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5494 08:07:45.663962 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5495 08:07:45.667243 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5496 08:07:45.670324 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5497 08:07:45.673764 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5498 08:07:45.677079 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5499 08:07:45.684030 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5500 08:07:45.687140 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5501 08:07:45.690510 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5502 08:07:45.693989 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5503 08:07:45.696806 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5504 08:07:45.700473 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5505 08:07:45.706950 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5506 08:07:45.710598 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5507 08:07:45.714088 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5508 08:07:45.714200 ==
5509 08:07:45.717426 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 08:07:45.720091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 08:07:45.720197 ==
5512 08:07:45.723675 DQS Delay:
5513 08:07:45.723806 DQS0 = 0, DQS1 = 0
5514 08:07:45.726872 DQM Delay:
5515 08:07:45.726990 DQM0 = 104, DQM1 = 93
5516 08:07:45.727099 DQ Delay:
5517 08:07:45.733445 DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =102
5518 08:07:45.737030 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5519 08:07:45.740488 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =86
5520 08:07:45.743540 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =100
5521 08:07:45.743665
5522 08:07:45.743775
5523 08:07:45.750036 [DQSOSCAuto] RK1, (LSB)MR18= 0x2800, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5524 08:07:45.753719 CH0 RK1: MR19=505, MR18=2800
5525 08:07:45.760196 CH0_RK1: MR19=0x505, MR18=0x2800, DQSOSC=409, MR23=63, INC=64, DEC=43
5526 08:07:45.763264 [RxdqsGatingPostProcess] freq 933
5527 08:07:45.766603 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5528 08:07:45.770447 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 08:07:45.773666 best DQS1 dly(2T, 0.5T) = (0, 11)
5530 08:07:45.776614 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 08:07:45.779816 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5532 08:07:45.783324 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 08:07:45.786392 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 08:07:45.790034 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 08:07:45.793096 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 08:07:45.796532 Pre-setting of DQS Precalculation
5537 08:07:45.799926 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5538 08:07:45.803114 ==
5539 08:07:45.803217 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 08:07:45.809994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 08:07:45.810111 ==
5542 08:07:45.813352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 08:07:45.819490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5544 08:07:45.823132 [CA 0] Center 36 (6~67) winsize 62
5545 08:07:45.826636 [CA 1] Center 36 (6~67) winsize 62
5546 08:07:45.829934 [CA 2] Center 34 (4~65) winsize 62
5547 08:07:45.833230 [CA 3] Center 34 (4~65) winsize 62
5548 08:07:45.837017 [CA 4] Center 34 (4~65) winsize 62
5549 08:07:45.840158 [CA 5] Center 33 (3~64) winsize 62
5550 08:07:45.840283
5551 08:07:45.843791 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5552 08:07:45.843919
5553 08:07:45.846586 [CATrainingPosCal] consider 1 rank data
5554 08:07:45.849719 u2DelayCellTimex100 = 270/100 ps
5555 08:07:45.853222 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5556 08:07:45.859976 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 08:07:45.863179 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5558 08:07:45.866530 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5559 08:07:45.870023 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5560 08:07:45.873026 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5561 08:07:45.873154
5562 08:07:45.876325 CA PerBit enable=1, Macro0, CA PI delay=33
5563 08:07:45.876449
5564 08:07:45.879921 [CBTSetCACLKResult] CA Dly = 33
5565 08:07:45.880045 CS Dly: 7 (0~38)
5566 08:07:45.883781 ==
5567 08:07:45.883887 Dram Type= 6, Freq= 0, CH_1, rank 1
5568 08:07:45.889984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 08:07:45.890114 ==
5570 08:07:45.893359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 08:07:45.899633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5572 08:07:45.903490 [CA 0] Center 36 (6~67) winsize 62
5573 08:07:45.906319 [CA 1] Center 37 (6~68) winsize 63
5574 08:07:45.909964 [CA 2] Center 35 (5~65) winsize 61
5575 08:07:45.913283 [CA 3] Center 34 (4~65) winsize 62
5576 08:07:45.916762 [CA 4] Center 34 (4~65) winsize 62
5577 08:07:45.920402 [CA 5] Center 33 (3~64) winsize 62
5578 08:07:45.920499
5579 08:07:45.923220 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5580 08:07:45.923322
5581 08:07:45.926682 [CATrainingPosCal] consider 2 rank data
5582 08:07:45.930218 u2DelayCellTimex100 = 270/100 ps
5583 08:07:45.933665 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5584 08:07:45.936426 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5585 08:07:45.943284 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5586 08:07:45.946444 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5587 08:07:45.950159 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5588 08:07:45.953089 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5589 08:07:45.953224
5590 08:07:45.956479 CA PerBit enable=1, Macro0, CA PI delay=33
5591 08:07:45.956605
5592 08:07:45.960446 [CBTSetCACLKResult] CA Dly = 33
5593 08:07:45.960569 CS Dly: 8 (0~40)
5594 08:07:45.960681
5595 08:07:45.963382 ----->DramcWriteLeveling(PI) begin...
5596 08:07:45.967017 ==
5597 08:07:45.967142 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 08:07:45.973281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 08:07:45.973410 ==
5600 08:07:45.977038 Write leveling (Byte 0): 29 => 29
5601 08:07:45.980255 Write leveling (Byte 1): 27 => 27
5602 08:07:45.983976 DramcWriteLeveling(PI) end<-----
5603 08:07:45.984103
5604 08:07:45.984218 ==
5605 08:07:45.986595 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 08:07:45.990058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 08:07:45.990163 ==
5608 08:07:45.993781 [Gating] SW mode calibration
5609 08:07:46.000029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 08:07:46.003620 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5611 08:07:46.009869 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 08:07:46.013098 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 08:07:46.016871 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 08:07:46.023305 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 08:07:46.026529 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 08:07:46.029823 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5617 08:07:46.036535 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5618 08:07:46.039542 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5619 08:07:46.043114 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 08:07:46.049945 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 08:07:46.053230 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 08:07:46.056416 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 08:07:46.063101 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 08:07:46.066741 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 08:07:46.069461 0 15 24 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
5626 08:07:46.076142 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5627 08:07:46.079814 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 08:07:46.082861 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 08:07:46.089301 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 08:07:46.092764 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 08:07:46.096135 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 08:07:46.102597 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 08:07:46.105863 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5634 08:07:46.109584 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5635 08:07:46.115860 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 08:07:46.119101 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 08:07:46.122639 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 08:07:46.128987 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 08:07:46.132687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 08:07:46.135665 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 08:07:46.142859 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 08:07:46.145628 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 08:07:46.149243 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 08:07:46.156077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 08:07:46.158996 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 08:07:46.162367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 08:07:46.165886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 08:07:46.172795 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 08:07:46.175709 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5650 08:07:46.179347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 08:07:46.182579 Total UI for P1: 0, mck2ui 16
5652 08:07:46.185906 best dqsien dly found for B0: ( 1, 2, 24)
5653 08:07:46.189111 Total UI for P1: 0, mck2ui 16
5654 08:07:46.192575 best dqsien dly found for B1: ( 1, 2, 24)
5655 08:07:46.195763 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5656 08:07:46.202475 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5657 08:07:46.202556
5658 08:07:46.206146 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5659 08:07:46.208874 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5660 08:07:46.212367 [Gating] SW calibration Done
5661 08:07:46.212469 ==
5662 08:07:46.215696 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 08:07:46.219233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 08:07:46.219347 ==
5665 08:07:46.219430 RX Vref Scan: 0
5666 08:07:46.222030
5667 08:07:46.222129 RX Vref 0 -> 0, step: 1
5668 08:07:46.222229
5669 08:07:46.225631 RX Delay -80 -> 252, step: 8
5670 08:07:46.228638 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5671 08:07:46.232237 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5672 08:07:46.238856 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5673 08:07:46.242632 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5674 08:07:46.245632 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5675 08:07:46.248742 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5676 08:07:46.252375 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5677 08:07:46.255627 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5678 08:07:46.259077 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5679 08:07:46.265588 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5680 08:07:46.268437 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5681 08:07:46.272157 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5682 08:07:46.275340 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5683 08:07:46.278914 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5684 08:07:46.285566 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5685 08:07:46.288375 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5686 08:07:46.288489 ==
5687 08:07:46.292022 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 08:07:46.295277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 08:07:46.295382 ==
5690 08:07:46.298372 DQS Delay:
5691 08:07:46.298478 DQS0 = 0, DQS1 = 0
5692 08:07:46.298580 DQM Delay:
5693 08:07:46.301759 DQM0 = 103, DQM1 = 99
5694 08:07:46.301888 DQ Delay:
5695 08:07:46.305592 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5696 08:07:46.308508 DQ4 =99, DQ5 =119, DQ6 =115, DQ7 =103
5697 08:07:46.311630 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5698 08:07:46.315457 DQ12 =107, DQ13 =111, DQ14 =103, DQ15 =107
5699 08:07:46.315572
5700 08:07:46.318745
5701 08:07:46.318856 ==
5702 08:07:46.322162 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 08:07:46.325580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 08:07:46.325665 ==
5705 08:07:46.325739
5706 08:07:46.325800
5707 08:07:46.328521 TX Vref Scan disable
5708 08:07:46.328606 == TX Byte 0 ==
5709 08:07:46.332219 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5710 08:07:46.338670 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5711 08:07:46.338752 == TX Byte 1 ==
5712 08:07:46.341820 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5713 08:07:46.349021 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5714 08:07:46.349132 ==
5715 08:07:46.352005 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 08:07:46.355181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 08:07:46.355299 ==
5718 08:07:46.355395
5719 08:07:46.355489
5720 08:07:46.358563 TX Vref Scan disable
5721 08:07:46.362102 == TX Byte 0 ==
5722 08:07:46.365589 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5723 08:07:46.368895 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5724 08:07:46.372153 == TX Byte 1 ==
5725 08:07:46.374983 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 08:07:46.378809 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 08:07:46.378915
5728 08:07:46.379009 [DATLAT]
5729 08:07:46.382286 Freq=933, CH1 RK0
5730 08:07:46.382366
5731 08:07:46.385030 DATLAT Default: 0xd
5732 08:07:46.385105 0, 0xFFFF, sum = 0
5733 08:07:46.388274 1, 0xFFFF, sum = 0
5734 08:07:46.388349 2, 0xFFFF, sum = 0
5735 08:07:46.391578 3, 0xFFFF, sum = 0
5736 08:07:46.391689 4, 0xFFFF, sum = 0
5737 08:07:46.395485 5, 0xFFFF, sum = 0
5738 08:07:46.395584 6, 0xFFFF, sum = 0
5739 08:07:46.398487 7, 0xFFFF, sum = 0
5740 08:07:46.398571 8, 0xFFFF, sum = 0
5741 08:07:46.401887 9, 0xFFFF, sum = 0
5742 08:07:46.401990 10, 0x0, sum = 1
5743 08:07:46.405239 11, 0x0, sum = 2
5744 08:07:46.405315 12, 0x0, sum = 3
5745 08:07:46.408635 13, 0x0, sum = 4
5746 08:07:46.408741 best_step = 11
5747 08:07:46.408834
5748 08:07:46.408923 ==
5749 08:07:46.411599 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 08:07:46.414904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 08:07:46.418264 ==
5752 08:07:46.418348 RX Vref Scan: 1
5753 08:07:46.418413
5754 08:07:46.422025 RX Vref 0 -> 0, step: 1
5755 08:07:46.422107
5756 08:07:46.424794 RX Delay -45 -> 252, step: 4
5757 08:07:46.424876
5758 08:07:46.424981 Set Vref, RX VrefLevel [Byte0]: 54
5759 08:07:46.428177 [Byte1]: 54
5760 08:07:46.433250
5761 08:07:46.433359 Final RX Vref Byte 0 = 54 to rank0
5762 08:07:46.436426 Final RX Vref Byte 1 = 54 to rank0
5763 08:07:46.439871 Final RX Vref Byte 0 = 54 to rank1
5764 08:07:46.443449 Final RX Vref Byte 1 = 54 to rank1==
5765 08:07:46.446532 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 08:07:46.453040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 08:07:46.453150 ==
5768 08:07:46.453246 DQS Delay:
5769 08:07:46.453343 DQS0 = 0, DQS1 = 0
5770 08:07:46.456577 DQM Delay:
5771 08:07:46.456678 DQM0 = 103, DQM1 = 101
5772 08:07:46.460246 DQ Delay:
5773 08:07:46.463065 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5774 08:07:46.466459 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5775 08:07:46.469971 DQ8 =90, DQ9 =92, DQ10 =102, DQ11 =94
5776 08:07:46.473196 DQ12 =106, DQ13 =108, DQ14 =108, DQ15 =108
5777 08:07:46.473323
5778 08:07:46.473439
5779 08:07:46.480019 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5780 08:07:46.483272 CH1 RK0: MR19=505, MR18=1930
5781 08:07:46.490150 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5782 08:07:46.490261
5783 08:07:46.493332 ----->DramcWriteLeveling(PI) begin...
5784 08:07:46.493436 ==
5785 08:07:46.496325 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 08:07:46.500063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 08:07:46.500173 ==
5788 08:07:46.503416 Write leveling (Byte 0): 26 => 26
5789 08:07:46.506530 Write leveling (Byte 1): 28 => 28
5790 08:07:46.509894 DramcWriteLeveling(PI) end<-----
5791 08:07:46.509999
5792 08:07:46.510090 ==
5793 08:07:46.513186 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 08:07:46.516660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 08:07:46.520281 ==
5796 08:07:46.520381 [Gating] SW mode calibration
5797 08:07:46.529886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5798 08:07:46.533175 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5799 08:07:46.536764 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 08:07:46.543606 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 08:07:46.546872 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 08:07:46.549892 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 08:07:46.556497 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 08:07:46.560078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 08:07:46.563367 0 14 24 | B1->B0 | 2e2e 3232 | 1 0 | (1 1) (0 0)
5806 08:07:46.570199 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
5807 08:07:46.573057 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 08:07:46.576563 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 08:07:46.583366 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 08:07:46.586625 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 08:07:46.589725 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 08:07:46.596712 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5813 08:07:46.599914 0 15 24 | B1->B0 | 3737 2d2d | 0 0 | (0 0) (0 0)
5814 08:07:46.603218 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
5815 08:07:46.606447 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 08:07:46.612976 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 08:07:46.616463 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 08:07:46.619911 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 08:07:46.626944 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 08:07:46.629857 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 08:07:46.633156 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5822 08:07:46.639610 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5823 08:07:46.643226 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 08:07:46.646840 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 08:07:46.653373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 08:07:46.656536 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 08:07:46.659977 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 08:07:46.666658 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 08:07:46.670326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 08:07:46.673200 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 08:07:46.680307 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 08:07:46.682947 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 08:07:46.686740 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 08:07:46.693207 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 08:07:46.696306 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 08:07:46.699595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 08:07:46.702942 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5838 08:07:46.709989 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 08:07:46.713304 Total UI for P1: 0, mck2ui 16
5840 08:07:46.716747 best dqsien dly found for B0: ( 1, 2, 24)
5841 08:07:46.719625 Total UI for P1: 0, mck2ui 16
5842 08:07:46.723073 best dqsien dly found for B1: ( 1, 2, 24)
5843 08:07:46.726694 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5844 08:07:46.729636 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5845 08:07:46.729737
5846 08:07:46.733283 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5847 08:07:46.736726 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5848 08:07:46.739431 [Gating] SW calibration Done
5849 08:07:46.739536 ==
5850 08:07:46.743125 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 08:07:46.746166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 08:07:46.746244 ==
5853 08:07:46.749361 RX Vref Scan: 0
5854 08:07:46.749463
5855 08:07:46.752672 RX Vref 0 -> 0, step: 1
5856 08:07:46.752768
5857 08:07:46.752861 RX Delay -80 -> 252, step: 8
5858 08:07:46.759739 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5859 08:07:46.762687 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5860 08:07:46.765921 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5861 08:07:46.769555 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5862 08:07:46.772597 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5863 08:07:46.779430 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5864 08:07:46.782554 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5865 08:07:46.785882 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5866 08:07:46.789388 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5867 08:07:46.792589 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5868 08:07:46.795894 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5869 08:07:46.802732 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5870 08:07:46.806128 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5871 08:07:46.809012 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5872 08:07:46.812631 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5873 08:07:46.815870 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5874 08:07:46.819330 ==
5875 08:07:46.822641 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 08:07:46.825614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 08:07:46.825721 ==
5878 08:07:46.825803 DQS Delay:
5879 08:07:46.829421 DQS0 = 0, DQS1 = 0
5880 08:07:46.829503 DQM Delay:
5881 08:07:46.832691 DQM0 = 104, DQM1 = 99
5882 08:07:46.832778 DQ Delay:
5883 08:07:46.835793 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5884 08:07:46.839292 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5885 08:07:46.843105 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5886 08:07:46.846445 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5887 08:07:46.846549
5888 08:07:46.846645
5889 08:07:46.846724 ==
5890 08:07:46.849368 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 08:07:46.852926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 08:07:46.853031 ==
5893 08:07:46.855949
5894 08:07:46.856055
5895 08:07:46.856130 TX Vref Scan disable
5896 08:07:46.859578 == TX Byte 0 ==
5897 08:07:46.862674 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5898 08:07:46.866449 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5899 08:07:46.869350 == TX Byte 1 ==
5900 08:07:46.872978 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5901 08:07:46.876314 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5902 08:07:46.876424 ==
5903 08:07:46.879271 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 08:07:46.885889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 08:07:46.885971 ==
5906 08:07:46.886067
5907 08:07:46.886157
5908 08:07:46.886247 TX Vref Scan disable
5909 08:07:46.889867 == TX Byte 0 ==
5910 08:07:46.893201 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5911 08:07:46.900209 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5912 08:07:46.900288 == TX Byte 1 ==
5913 08:07:46.903683 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5914 08:07:46.909746 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5915 08:07:46.909853
5916 08:07:46.909946 [DATLAT]
5917 08:07:46.910049 Freq=933, CH1 RK1
5918 08:07:46.910150
5919 08:07:46.913645 DATLAT Default: 0xb
5920 08:07:46.913747 0, 0xFFFF, sum = 0
5921 08:07:46.916611 1, 0xFFFF, sum = 0
5922 08:07:46.916715 2, 0xFFFF, sum = 0
5923 08:07:46.919679 3, 0xFFFF, sum = 0
5924 08:07:46.923610 4, 0xFFFF, sum = 0
5925 08:07:46.923703 5, 0xFFFF, sum = 0
5926 08:07:46.926424 6, 0xFFFF, sum = 0
5927 08:07:46.926498 7, 0xFFFF, sum = 0
5928 08:07:46.930016 8, 0xFFFF, sum = 0
5929 08:07:46.930101 9, 0xFFFF, sum = 0
5930 08:07:46.932992 10, 0x0, sum = 1
5931 08:07:46.933093 11, 0x0, sum = 2
5932 08:07:46.936867 12, 0x0, sum = 3
5933 08:07:46.936977 13, 0x0, sum = 4
5934 08:07:46.937076 best_step = 11
5935 08:07:46.937171
5936 08:07:46.939905 ==
5937 08:07:46.943137 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 08:07:46.946303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 08:07:46.946411 ==
5940 08:07:46.946506 RX Vref Scan: 0
5941 08:07:46.946600
5942 08:07:46.949819 RX Vref 0 -> 0, step: 1
5943 08:07:46.949938
5944 08:07:46.952787 RX Delay -45 -> 252, step: 4
5945 08:07:46.956153 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5946 08:07:46.962777 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5947 08:07:46.966570 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5948 08:07:46.969553 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5949 08:07:46.973189 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5950 08:07:46.976337 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5951 08:07:46.983323 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5952 08:07:46.986424 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5953 08:07:46.989595 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5954 08:07:46.992920 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5955 08:07:46.996369 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5956 08:07:46.999610 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5957 08:07:47.006146 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5958 08:07:47.009453 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5959 08:07:47.012798 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5960 08:07:47.016174 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5961 08:07:47.016283 ==
5962 08:07:47.019414 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 08:07:47.026093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 08:07:47.026206 ==
5965 08:07:47.026305 DQS Delay:
5966 08:07:47.029811 DQS0 = 0, DQS1 = 0
5967 08:07:47.029935 DQM Delay:
5968 08:07:47.032926 DQM0 = 104, DQM1 = 101
5969 08:07:47.033070 DQ Delay:
5970 08:07:47.035867 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5971 08:07:47.039515 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5972 08:07:47.043005 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5973 08:07:47.045957 DQ12 =110, DQ13 =108, DQ14 =106, DQ15 =110
5974 08:07:47.046061
5975 08:07:47.046160
5976 08:07:47.055912 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5977 08:07:47.056028 CH1 RK1: MR19=505, MR18=2F02
5978 08:07:47.063129 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5979 08:07:47.066095 [RxdqsGatingPostProcess] freq 933
5980 08:07:47.072548 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5981 08:07:47.076492 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 08:07:47.079467 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 08:07:47.082676 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 08:07:47.086191 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 08:07:47.086274 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 08:07:47.089644 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 08:07:47.092567 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 08:07:47.095937 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 08:07:47.099080 Pre-setting of DQS Precalculation
5990 08:07:47.106030 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5991 08:07:47.112388 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5992 08:07:47.119248 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5993 08:07:47.119406
5994 08:07:47.119518
5995 08:07:47.123129 [Calibration Summary] 1866 Mbps
5996 08:07:47.123265 CH 0, Rank 0
5997 08:07:47.125605 SW Impedance : PASS
5998 08:07:47.128885 DUTY Scan : NO K
5999 08:07:47.128991 ZQ Calibration : PASS
6000 08:07:47.132563 Jitter Meter : NO K
6001 08:07:47.135586 CBT Training : PASS
6002 08:07:47.135727 Write leveling : PASS
6003 08:07:47.139388 RX DQS gating : PASS
6004 08:07:47.142358 RX DQ/DQS(RDDQC) : PASS
6005 08:07:47.142477 TX DQ/DQS : PASS
6006 08:07:47.145807 RX DATLAT : PASS
6007 08:07:47.149417 RX DQ/DQS(Engine): PASS
6008 08:07:47.149537 TX OE : NO K
6009 08:07:47.149651 All Pass.
6010 08:07:47.149753
6011 08:07:47.152816 CH 0, Rank 1
6012 08:07:47.152937 SW Impedance : PASS
6013 08:07:47.155703 DUTY Scan : NO K
6014 08:07:47.159419 ZQ Calibration : PASS
6015 08:07:47.159541 Jitter Meter : NO K
6016 08:07:47.162195 CBT Training : PASS
6017 08:07:47.165879 Write leveling : PASS
6018 08:07:47.165962 RX DQS gating : PASS
6019 08:07:47.169592 RX DQ/DQS(RDDQC) : PASS
6020 08:07:47.172686 TX DQ/DQS : PASS
6021 08:07:47.172811 RX DATLAT : PASS
6022 08:07:47.176281 RX DQ/DQS(Engine): PASS
6023 08:07:47.179241 TX OE : NO K
6024 08:07:47.179362 All Pass.
6025 08:07:47.179478
6026 08:07:47.179585 CH 1, Rank 0
6027 08:07:47.182530 SW Impedance : PASS
6028 08:07:47.185607 DUTY Scan : NO K
6029 08:07:47.185733 ZQ Calibration : PASS
6030 08:07:47.189026 Jitter Meter : NO K
6031 08:07:47.189154 CBT Training : PASS
6032 08:07:47.192597 Write leveling : PASS
6033 08:07:47.195758 RX DQS gating : PASS
6034 08:07:47.195883 RX DQ/DQS(RDDQC) : PASS
6035 08:07:47.199064 TX DQ/DQS : PASS
6036 08:07:47.202599 RX DATLAT : PASS
6037 08:07:47.202682 RX DQ/DQS(Engine): PASS
6038 08:07:47.205556 TX OE : NO K
6039 08:07:47.205639 All Pass.
6040 08:07:47.205704
6041 08:07:47.209155 CH 1, Rank 1
6042 08:07:47.209239 SW Impedance : PASS
6043 08:07:47.212415 DUTY Scan : NO K
6044 08:07:47.215502 ZQ Calibration : PASS
6045 08:07:47.215585 Jitter Meter : NO K
6046 08:07:47.219161 CBT Training : PASS
6047 08:07:47.222561 Write leveling : PASS
6048 08:07:47.222644 RX DQS gating : PASS
6049 08:07:47.225897 RX DQ/DQS(RDDQC) : PASS
6050 08:07:47.229231 TX DQ/DQS : PASS
6051 08:07:47.229314 RX DATLAT : PASS
6052 08:07:47.232385 RX DQ/DQS(Engine): PASS
6053 08:07:47.235630 TX OE : NO K
6054 08:07:47.235721 All Pass.
6055 08:07:47.235787
6056 08:07:47.235847 DramC Write-DBI off
6057 08:07:47.239036 PER_BANK_REFRESH: Hybrid Mode
6058 08:07:47.242127 TX_TRACKING: ON
6059 08:07:47.248931 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6060 08:07:47.252591 [FAST_K] Save calibration result to emmc
6061 08:07:47.258970 dramc_set_vcore_voltage set vcore to 650000
6062 08:07:47.259086 Read voltage for 400, 6
6063 08:07:47.262321 Vio18 = 0
6064 08:07:47.262441 Vcore = 650000
6065 08:07:47.262547 Vdram = 0
6066 08:07:47.265356 Vddq = 0
6067 08:07:47.265476 Vmddr = 0
6068 08:07:47.269043 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6069 08:07:47.275553 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6070 08:07:47.278800 MEM_TYPE=3, freq_sel=20
6071 08:07:47.282137 sv_algorithm_assistance_LP4_800
6072 08:07:47.285375 ============ PULL DRAM RESETB DOWN ============
6073 08:07:47.288729 ========== PULL DRAM RESETB DOWN end =========
6074 08:07:47.291902 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6075 08:07:47.295280 ===================================
6076 08:07:47.299014 LPDDR4 DRAM CONFIGURATION
6077 08:07:47.302060 ===================================
6078 08:07:47.305212 EX_ROW_EN[0] = 0x0
6079 08:07:47.305337 EX_ROW_EN[1] = 0x0
6080 08:07:47.308556 LP4Y_EN = 0x0
6081 08:07:47.308677 WORK_FSP = 0x0
6082 08:07:47.311858 WL = 0x2
6083 08:07:47.311978 RL = 0x2
6084 08:07:47.315503 BL = 0x2
6085 08:07:47.315627 RPST = 0x0
6086 08:07:47.318559 RD_PRE = 0x0
6087 08:07:47.318663 WR_PRE = 0x1
6088 08:07:47.321782 WR_PST = 0x0
6089 08:07:47.321911 DBI_WR = 0x0
6090 08:07:47.325242 DBI_RD = 0x0
6091 08:07:47.325364 OTF = 0x1
6092 08:07:47.328396 ===================================
6093 08:07:47.331914 ===================================
6094 08:07:47.335213 ANA top config
6095 08:07:47.338414 ===================================
6096 08:07:47.341643 DLL_ASYNC_EN = 0
6097 08:07:47.341726 ALL_SLAVE_EN = 1
6098 08:07:47.345408 NEW_RANK_MODE = 1
6099 08:07:47.348697 DLL_IDLE_MODE = 1
6100 08:07:47.351893 LP45_APHY_COMB_EN = 1
6101 08:07:47.355503 TX_ODT_DIS = 1
6102 08:07:47.355610 NEW_8X_MODE = 1
6103 08:07:47.358395 ===================================
6104 08:07:47.362232 ===================================
6105 08:07:47.365253 data_rate = 800
6106 08:07:47.368891 CKR = 1
6107 08:07:47.372064 DQ_P2S_RATIO = 4
6108 08:07:47.375010 ===================================
6109 08:07:47.378485 CA_P2S_RATIO = 4
6110 08:07:47.378567 DQ_CA_OPEN = 0
6111 08:07:47.381685 DQ_SEMI_OPEN = 1
6112 08:07:47.384828 CA_SEMI_OPEN = 1
6113 08:07:47.388461 CA_FULL_RATE = 0
6114 08:07:47.391993 DQ_CKDIV4_EN = 0
6115 08:07:47.395151 CA_CKDIV4_EN = 1
6116 08:07:47.395227 CA_PREDIV_EN = 0
6117 08:07:47.398586 PH8_DLY = 0
6118 08:07:47.401582 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6119 08:07:47.405251 DQ_AAMCK_DIV = 0
6120 08:07:47.408455 CA_AAMCK_DIV = 0
6121 08:07:47.411563 CA_ADMCK_DIV = 4
6122 08:07:47.411668 DQ_TRACK_CA_EN = 0
6123 08:07:47.414944 CA_PICK = 800
6124 08:07:47.418277 CA_MCKIO = 400
6125 08:07:47.421488 MCKIO_SEMI = 400
6126 08:07:47.425011 PLL_FREQ = 3016
6127 08:07:47.428187 DQ_UI_PI_RATIO = 32
6128 08:07:47.431519 CA_UI_PI_RATIO = 32
6129 08:07:47.434832 ===================================
6130 08:07:47.438226 ===================================
6131 08:07:47.438308 memory_type:LPDDR4
6132 08:07:47.441902 GP_NUM : 10
6133 08:07:47.445085 SRAM_EN : 1
6134 08:07:47.445210 MD32_EN : 0
6135 08:07:47.448045 ===================================
6136 08:07:47.451555 [ANA_INIT] >>>>>>>>>>>>>>
6137 08:07:47.454823 <<<<<< [CONFIGURE PHASE]: ANA_TX
6138 08:07:47.457983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6139 08:07:47.461378 ===================================
6140 08:07:47.464496 data_rate = 800,PCW = 0X7400
6141 08:07:47.468075 ===================================
6142 08:07:47.471371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6143 08:07:47.474788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 08:07:47.487963 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 08:07:47.491625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6146 08:07:47.495044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6147 08:07:47.497987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6148 08:07:47.501842 [ANA_INIT] flow start
6149 08:07:47.501924 [ANA_INIT] PLL >>>>>>>>
6150 08:07:47.505011 [ANA_INIT] PLL <<<<<<<<
6151 08:07:47.507984 [ANA_INIT] MIDPI >>>>>>>>
6152 08:07:47.511560 [ANA_INIT] MIDPI <<<<<<<<
6153 08:07:47.511649 [ANA_INIT] DLL >>>>>>>>
6154 08:07:47.514577 [ANA_INIT] flow end
6155 08:07:47.518016 ============ LP4 DIFF to SE enter ============
6156 08:07:47.521383 ============ LP4 DIFF to SE exit ============
6157 08:07:47.524897 [ANA_INIT] <<<<<<<<<<<<<
6158 08:07:47.528235 [Flow] Enable top DCM control >>>>>
6159 08:07:47.530993 [Flow] Enable top DCM control <<<<<
6160 08:07:47.534822 Enable DLL master slave shuffle
6161 08:07:47.541154 ==============================================================
6162 08:07:47.541238 Gating Mode config
6163 08:07:47.547820 ==============================================================
6164 08:07:47.547903 Config description:
6165 08:07:47.557730 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6166 08:07:47.564715 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6167 08:07:47.571208 SELPH_MODE 0: By rank 1: By Phase
6168 08:07:47.574567 ==============================================================
6169 08:07:47.577849 GAT_TRACK_EN = 0
6170 08:07:47.581084 RX_GATING_MODE = 2
6171 08:07:47.584286 RX_GATING_TRACK_MODE = 2
6172 08:07:47.587560 SELPH_MODE = 1
6173 08:07:47.590827 PICG_EARLY_EN = 1
6174 08:07:47.594384 VALID_LAT_VALUE = 1
6175 08:07:47.597562 ==============================================================
6176 08:07:47.601097 Enter into Gating configuration >>>>
6177 08:07:47.604862 Exit from Gating configuration <<<<
6178 08:07:47.607663 Enter into DVFS_PRE_config >>>>>
6179 08:07:47.621347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6180 08:07:47.624351 Exit from DVFS_PRE_config <<<<<
6181 08:07:47.627745 Enter into PICG configuration >>>>
6182 08:07:47.627859 Exit from PICG configuration <<<<
6183 08:07:47.631136 [RX_INPUT] configuration >>>>>
6184 08:07:47.634617 [RX_INPUT] configuration <<<<<
6185 08:07:47.641341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6186 08:07:47.644260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6187 08:07:47.650905 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 08:07:47.658293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 08:07:47.664398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 08:07:47.671141 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 08:07:47.674519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6192 08:07:47.677510 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6193 08:07:47.680960 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6194 08:07:47.687656 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6195 08:07:47.691267 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6196 08:07:47.694152 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 08:07:47.697369 ===================================
6198 08:07:47.701071 LPDDR4 DRAM CONFIGURATION
6199 08:07:47.704455 ===================================
6200 08:07:47.707613 EX_ROW_EN[0] = 0x0
6201 08:07:47.707727 EX_ROW_EN[1] = 0x0
6202 08:07:47.710888 LP4Y_EN = 0x0
6203 08:07:47.710986 WORK_FSP = 0x0
6204 08:07:47.714369 WL = 0x2
6205 08:07:47.714451 RL = 0x2
6206 08:07:47.717404 BL = 0x2
6207 08:07:47.717533 RPST = 0x0
6208 08:07:47.720584 RD_PRE = 0x0
6209 08:07:47.720713 WR_PRE = 0x1
6210 08:07:47.724203 WR_PST = 0x0
6211 08:07:47.724310 DBI_WR = 0x0
6212 08:07:47.727848 DBI_RD = 0x0
6213 08:07:47.727948 OTF = 0x1
6214 08:07:47.730937 ===================================
6215 08:07:47.737591 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6216 08:07:47.740641 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6217 08:07:47.744211 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6218 08:07:47.747566 ===================================
6219 08:07:47.750785 LPDDR4 DRAM CONFIGURATION
6220 08:07:47.754359 ===================================
6221 08:07:47.754480 EX_ROW_EN[0] = 0x10
6222 08:07:47.757253 EX_ROW_EN[1] = 0x0
6223 08:07:47.761053 LP4Y_EN = 0x0
6224 08:07:47.761137 WORK_FSP = 0x0
6225 08:07:47.763915 WL = 0x2
6226 08:07:47.763996 RL = 0x2
6227 08:07:47.767742 BL = 0x2
6228 08:07:47.767824 RPST = 0x0
6229 08:07:47.770709 RD_PRE = 0x0
6230 08:07:47.770790 WR_PRE = 0x1
6231 08:07:47.774176 WR_PST = 0x0
6232 08:07:47.774257 DBI_WR = 0x0
6233 08:07:47.777638 DBI_RD = 0x0
6234 08:07:47.777720 OTF = 0x1
6235 08:07:47.780646 ===================================
6236 08:07:47.787312 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6237 08:07:47.792016 nWR fixed to 30
6238 08:07:47.794949 [ModeRegInit_LP4] CH0 RK0
6239 08:07:47.795030 [ModeRegInit_LP4] CH0 RK1
6240 08:07:47.798906 [ModeRegInit_LP4] CH1 RK0
6241 08:07:47.801602 [ModeRegInit_LP4] CH1 RK1
6242 08:07:47.801684 match AC timing 19
6243 08:07:47.808479 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6244 08:07:47.811618 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6245 08:07:47.814991 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6246 08:07:47.821632 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6247 08:07:47.825006 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6248 08:07:47.825088 ==
6249 08:07:47.828445 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 08:07:47.831624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 08:07:47.831716 ==
6252 08:07:47.838268 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 08:07:47.844761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6254 08:07:47.848346 [CA 0] Center 36 (8~64) winsize 57
6255 08:07:47.851574 [CA 1] Center 36 (8~64) winsize 57
6256 08:07:47.854748 [CA 2] Center 36 (8~64) winsize 57
6257 08:07:47.854845 [CA 3] Center 36 (8~64) winsize 57
6258 08:07:47.858288 [CA 4] Center 36 (8~64) winsize 57
6259 08:07:47.861968 [CA 5] Center 36 (8~64) winsize 57
6260 08:07:47.862051
6261 08:07:47.864971 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6262 08:07:47.868144
6263 08:07:47.871724 [CATrainingPosCal] consider 1 rank data
6264 08:07:47.871855 u2DelayCellTimex100 = 270/100 ps
6265 08:07:47.878047 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 08:07:47.881568 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 08:07:47.885060 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 08:07:47.888175 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 08:07:47.891730 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 08:07:47.894811 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 08:07:47.894935
6272 08:07:47.898451 CA PerBit enable=1, Macro0, CA PI delay=36
6273 08:07:47.898571
6274 08:07:47.901365 [CBTSetCACLKResult] CA Dly = 36
6275 08:07:47.905292 CS Dly: 1 (0~32)
6276 08:07:47.905413 ==
6277 08:07:47.908714 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 08:07:47.911385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 08:07:47.911507 ==
6280 08:07:47.917968 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 08:07:47.921667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6282 08:07:47.924815 [CA 0] Center 36 (8~64) winsize 57
6283 08:07:47.928156 [CA 1] Center 36 (8~64) winsize 57
6284 08:07:47.931678 [CA 2] Center 36 (8~64) winsize 57
6285 08:07:47.934564 [CA 3] Center 36 (8~64) winsize 57
6286 08:07:47.938142 [CA 4] Center 36 (8~64) winsize 57
6287 08:07:47.941532 [CA 5] Center 36 (8~64) winsize 57
6288 08:07:47.941659
6289 08:07:47.944485 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6290 08:07:47.944610
6291 08:07:47.947981 [CATrainingPosCal] consider 2 rank data
6292 08:07:47.951246 u2DelayCellTimex100 = 270/100 ps
6293 08:07:47.954653 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 08:07:47.958225 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 08:07:47.961246 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 08:07:47.967758 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 08:07:47.971162 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 08:07:47.974759 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 08:07:47.974884
6300 08:07:47.977809 CA PerBit enable=1, Macro0, CA PI delay=36
6301 08:07:47.977932
6302 08:07:47.981256 [CBTSetCACLKResult] CA Dly = 36
6303 08:07:47.981383 CS Dly: 1 (0~32)
6304 08:07:47.981500
6305 08:07:47.984795 ----->DramcWriteLeveling(PI) begin...
6306 08:07:47.984921 ==
6307 08:07:47.988025 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 08:07:47.994573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 08:07:47.994698 ==
6310 08:07:47.997825 Write leveling (Byte 0): 40 => 8
6311 08:07:47.997947 Write leveling (Byte 1): 40 => 8
6312 08:07:48.001575 DramcWriteLeveling(PI) end<-----
6313 08:07:48.001702
6314 08:07:48.001813 ==
6315 08:07:48.004730 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 08:07:48.011167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 08:07:48.011291 ==
6318 08:07:48.014674 [Gating] SW mode calibration
6319 08:07:48.021253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6320 08:07:48.024234 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6321 08:07:48.030939 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 08:07:48.034424 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 08:07:48.038341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 08:07:48.044562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 08:07:48.047970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 08:07:48.051135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 08:07:48.057776 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 08:07:48.061071 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 08:07:48.064783 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 08:07:48.067841 Total UI for P1: 0, mck2ui 16
6331 08:07:48.071358 best dqsien dly found for B0: ( 0, 14, 24)
6332 08:07:48.074448 Total UI for P1: 0, mck2ui 16
6333 08:07:48.077517 best dqsien dly found for B1: ( 0, 14, 24)
6334 08:07:48.081213 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6335 08:07:48.084434 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6336 08:07:48.084547
6337 08:07:48.087653 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 08:07:48.094365 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 08:07:48.094457 [Gating] SW calibration Done
6340 08:07:48.094522 ==
6341 08:07:48.097889 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 08:07:48.104132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 08:07:48.104239 ==
6344 08:07:48.104336 RX Vref Scan: 0
6345 08:07:48.104428
6346 08:07:48.107629 RX Vref 0 -> 0, step: 1
6347 08:07:48.107712
6348 08:07:48.110856 RX Delay -410 -> 252, step: 16
6349 08:07:48.114435 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6350 08:07:48.117965 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6351 08:07:48.124409 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6352 08:07:48.127820 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6353 08:07:48.130908 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6354 08:07:48.134282 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6355 08:07:48.138022 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6356 08:07:48.144267 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6357 08:07:48.147641 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6358 08:07:48.151598 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6359 08:07:48.157585 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6360 08:07:48.160722 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6361 08:07:48.164506 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6362 08:07:48.167369 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6363 08:07:48.174237 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6364 08:07:48.177491 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6365 08:07:48.177565 ==
6366 08:07:48.181116 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 08:07:48.184071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 08:07:48.184161 ==
6369 08:07:48.187828 DQS Delay:
6370 08:07:48.187945 DQS0 = 27, DQS1 = 35
6371 08:07:48.191241 DQM Delay:
6372 08:07:48.191336 DQM0 = 10, DQM1 = 11
6373 08:07:48.191461 DQ Delay:
6374 08:07:48.194020 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6375 08:07:48.197604 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6376 08:07:48.200729 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6377 08:07:48.204446 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6378 08:07:48.204525
6379 08:07:48.204588
6380 08:07:48.204647 ==
6381 08:07:48.207453 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 08:07:48.210836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 08:07:48.214229 ==
6384 08:07:48.214310
6385 08:07:48.214374
6386 08:07:48.214435 TX Vref Scan disable
6387 08:07:48.217273 == TX Byte 0 ==
6388 08:07:48.220753 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 08:07:48.224417 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 08:07:48.227678 == TX Byte 1 ==
6391 08:07:48.230579 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 08:07:48.233986 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 08:07:48.234093 ==
6394 08:07:48.237359 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 08:07:48.243765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 08:07:48.243841 ==
6397 08:07:48.243904
6398 08:07:48.243966
6399 08:07:48.244022 TX Vref Scan disable
6400 08:07:48.247319 == TX Byte 0 ==
6401 08:07:48.250333 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 08:07:48.253711 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 08:07:48.257039 == TX Byte 1 ==
6404 08:07:48.260480 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 08:07:48.263550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 08:07:48.263656
6407 08:07:48.266841 [DATLAT]
6408 08:07:48.266919 Freq=400, CH0 RK0
6409 08:07:48.267033
6410 08:07:48.270247 DATLAT Default: 0xf
6411 08:07:48.270348 0, 0xFFFF, sum = 0
6412 08:07:48.273599 1, 0xFFFF, sum = 0
6413 08:07:48.273705 2, 0xFFFF, sum = 0
6414 08:07:48.277063 3, 0xFFFF, sum = 0
6415 08:07:48.277171 4, 0xFFFF, sum = 0
6416 08:07:48.280217 5, 0xFFFF, sum = 0
6417 08:07:48.280327 6, 0xFFFF, sum = 0
6418 08:07:48.283814 7, 0xFFFF, sum = 0
6419 08:07:48.283923 8, 0xFFFF, sum = 0
6420 08:07:48.286819 9, 0xFFFF, sum = 0
6421 08:07:48.286898 10, 0xFFFF, sum = 0
6422 08:07:48.290660 11, 0xFFFF, sum = 0
6423 08:07:48.293669 12, 0xFFFF, sum = 0
6424 08:07:48.293772 13, 0x0, sum = 1
6425 08:07:48.293866 14, 0x0, sum = 2
6426 08:07:48.297325 15, 0x0, sum = 3
6427 08:07:48.297426 16, 0x0, sum = 4
6428 08:07:48.300191 best_step = 14
6429 08:07:48.300266
6430 08:07:48.300330 ==
6431 08:07:48.303715 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 08:07:48.306708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 08:07:48.306804 ==
6434 08:07:48.310374 RX Vref Scan: 1
6435 08:07:48.310466
6436 08:07:48.310556 RX Vref 0 -> 0, step: 1
6437 08:07:48.310642
6438 08:07:48.313876 RX Delay -311 -> 252, step: 8
6439 08:07:48.313972
6440 08:07:48.316918 Set Vref, RX VrefLevel [Byte0]: 55
6441 08:07:48.319890 [Byte1]: 47
6442 08:07:48.325434
6443 08:07:48.325554 Final RX Vref Byte 0 = 55 to rank0
6444 08:07:48.328843 Final RX Vref Byte 1 = 47 to rank0
6445 08:07:48.331802 Final RX Vref Byte 0 = 55 to rank1
6446 08:07:48.335185 Final RX Vref Byte 1 = 47 to rank1==
6447 08:07:48.338514 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 08:07:48.345050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 08:07:48.345159 ==
6450 08:07:48.345252 DQS Delay:
6451 08:07:48.348587 DQS0 = 28, DQS1 = 36
6452 08:07:48.348698 DQM Delay:
6453 08:07:48.348792 DQM0 = 11, DQM1 = 12
6454 08:07:48.351593 DQ Delay:
6455 08:07:48.355199 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6456 08:07:48.355281 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6457 08:07:48.358222 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6458 08:07:48.362153 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6459 08:07:48.362228
6460 08:07:48.362295
6461 08:07:48.371962 [DQSOSCAuto] RK0, (LSB)MR18= 0xcebd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6462 08:07:48.375337 CH0 RK0: MR19=C0C, MR18=CEBD
6463 08:07:48.381739 CH0_RK0: MR19=0xC0C, MR18=0xCEBD, DQSOSC=384, MR23=63, INC=400, DEC=267
6464 08:07:48.381825 ==
6465 08:07:48.385051 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 08:07:48.388239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 08:07:48.388315 ==
6468 08:07:48.391789 [Gating] SW mode calibration
6469 08:07:48.398469 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6470 08:07:48.401822 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6471 08:07:48.408329 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 08:07:48.411788 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 08:07:48.415446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 08:07:48.422061 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 08:07:48.425619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 08:07:48.428367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 08:07:48.434867 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 08:07:48.438570 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 08:07:48.441464 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 08:07:48.445084 Total UI for P1: 0, mck2ui 16
6481 08:07:48.448284 best dqsien dly found for B0: ( 0, 14, 24)
6482 08:07:48.451532 Total UI for P1: 0, mck2ui 16
6483 08:07:48.455103 best dqsien dly found for B1: ( 0, 14, 24)
6484 08:07:48.457990 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6485 08:07:48.461768 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6486 08:07:48.461877
6487 08:07:48.467996 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 08:07:48.471431 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 08:07:48.474868 [Gating] SW calibration Done
6490 08:07:48.474979 ==
6491 08:07:48.477897 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 08:07:48.481535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 08:07:48.481639 ==
6494 08:07:48.481732 RX Vref Scan: 0
6495 08:07:48.481823
6496 08:07:48.484945 RX Vref 0 -> 0, step: 1
6497 08:07:48.485042
6498 08:07:48.487884 RX Delay -410 -> 252, step: 16
6499 08:07:48.491400 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6500 08:07:48.498182 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6501 08:07:48.501231 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6502 08:07:48.504559 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6503 08:07:48.508191 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6504 08:07:48.514693 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6505 08:07:48.517823 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6506 08:07:48.521435 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6507 08:07:48.524489 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6508 08:07:48.528152 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6509 08:07:48.534757 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6510 08:07:48.538195 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6511 08:07:48.541356 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6512 08:07:48.545216 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6513 08:07:48.551476 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6514 08:07:48.555121 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6515 08:07:48.555221 ==
6516 08:07:48.558187 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 08:07:48.561452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 08:07:48.561557 ==
6519 08:07:48.564826 DQS Delay:
6520 08:07:48.564925 DQS0 = 27, DQS1 = 35
6521 08:07:48.567731 DQM Delay:
6522 08:07:48.567807 DQM0 = 12, DQM1 = 12
6523 08:07:48.571537 DQ Delay:
6524 08:07:48.571634 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6525 08:07:48.574693 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6526 08:07:48.578102 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6527 08:07:48.580976 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6528 08:07:48.581052
6529 08:07:48.581115
6530 08:07:48.581190 ==
6531 08:07:48.584297 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 08:07:48.591395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 08:07:48.591512 ==
6534 08:07:48.591616
6535 08:07:48.591721
6536 08:07:48.591812 TX Vref Scan disable
6537 08:07:48.594290 == TX Byte 0 ==
6538 08:07:48.598227 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6539 08:07:48.600944 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6540 08:07:48.604558 == TX Byte 1 ==
6541 08:07:48.608018 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6542 08:07:48.611462 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6543 08:07:48.611562 ==
6544 08:07:48.614438 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 08:07:48.620907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 08:07:48.620989 ==
6547 08:07:48.621055
6548 08:07:48.621116
6549 08:07:48.621181 TX Vref Scan disable
6550 08:07:48.624297 == TX Byte 0 ==
6551 08:07:48.627620 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6552 08:07:48.631032 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6553 08:07:48.634496 == TX Byte 1 ==
6554 08:07:48.637506 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6555 08:07:48.641453 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6556 08:07:48.641558
6557 08:07:48.644348 [DATLAT]
6558 08:07:48.644454 Freq=400, CH0 RK1
6559 08:07:48.644548
6560 08:07:48.647739 DATLAT Default: 0xe
6561 08:07:48.647814 0, 0xFFFF, sum = 0
6562 08:07:48.650941 1, 0xFFFF, sum = 0
6563 08:07:48.651040 2, 0xFFFF, sum = 0
6564 08:07:48.654218 3, 0xFFFF, sum = 0
6565 08:07:48.654321 4, 0xFFFF, sum = 0
6566 08:07:48.657945 5, 0xFFFF, sum = 0
6567 08:07:48.658019 6, 0xFFFF, sum = 0
6568 08:07:48.660721 7, 0xFFFF, sum = 0
6569 08:07:48.660792 8, 0xFFFF, sum = 0
6570 08:07:48.664191 9, 0xFFFF, sum = 0
6571 08:07:48.664263 10, 0xFFFF, sum = 0
6572 08:07:48.667439 11, 0xFFFF, sum = 0
6573 08:07:48.670865 12, 0xFFFF, sum = 0
6574 08:07:48.670941 13, 0x0, sum = 1
6575 08:07:48.671004 14, 0x0, sum = 2
6576 08:07:48.674284 15, 0x0, sum = 3
6577 08:07:48.674360 16, 0x0, sum = 4
6578 08:07:48.677597 best_step = 14
6579 08:07:48.677671
6580 08:07:48.677733 ==
6581 08:07:48.680908 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 08:07:48.684310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 08:07:48.684385 ==
6584 08:07:48.688092 RX Vref Scan: 0
6585 08:07:48.688199
6586 08:07:48.688265 RX Vref 0 -> 0, step: 1
6587 08:07:48.688325
6588 08:07:48.690820 RX Delay -311 -> 252, step: 8
6589 08:07:48.699159 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6590 08:07:48.702684 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6591 08:07:48.705536 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6592 08:07:48.709169 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6593 08:07:48.715663 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6594 08:07:48.719441 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6595 08:07:48.722041 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6596 08:07:48.725823 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6597 08:07:48.732248 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6598 08:07:48.735818 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6599 08:07:48.738947 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6600 08:07:48.745589 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6601 08:07:48.748772 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6602 08:07:48.751991 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6603 08:07:48.755354 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6604 08:07:48.762724 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6605 08:07:48.762807 ==
6606 08:07:48.765650 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 08:07:48.768626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 08:07:48.768702 ==
6609 08:07:48.768771 DQS Delay:
6610 08:07:48.772211 DQS0 = 24, DQS1 = 36
6611 08:07:48.772284 DQM Delay:
6612 08:07:48.775569 DQM0 = 8, DQM1 = 13
6613 08:07:48.775673 DQ Delay:
6614 08:07:48.778967 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6615 08:07:48.782511 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6616 08:07:48.785273 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6617 08:07:48.789006 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6618 08:07:48.789110
6619 08:07:48.789213
6620 08:07:48.795307 [DQSOSCAuto] RK1, (LSB)MR18= 0xb857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6621 08:07:48.798811 CH0 RK1: MR19=C0C, MR18=B857
6622 08:07:48.805339 CH0_RK1: MR19=0xC0C, MR18=0xB857, DQSOSC=386, MR23=63, INC=396, DEC=264
6623 08:07:48.808987 [RxdqsGatingPostProcess] freq 400
6624 08:07:48.811742 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6625 08:07:48.815370 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 08:07:48.818790 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 08:07:48.821986 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 08:07:48.825659 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 08:07:48.828432 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 08:07:48.831678 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 08:07:48.835352 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 08:07:48.838845 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 08:07:48.841739 Pre-setting of DQS Precalculation
6634 08:07:48.845513 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6635 08:07:48.848461 ==
6636 08:07:48.848571 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 08:07:48.855293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 08:07:48.855421 ==
6639 08:07:48.858210 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 08:07:48.865219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6641 08:07:48.868389 [CA 0] Center 36 (8~64) winsize 57
6642 08:07:48.871935 [CA 1] Center 36 (8~64) winsize 57
6643 08:07:48.875277 [CA 2] Center 36 (8~64) winsize 57
6644 08:07:48.878519 [CA 3] Center 36 (8~64) winsize 57
6645 08:07:48.881953 [CA 4] Center 36 (8~64) winsize 57
6646 08:07:48.885151 [CA 5] Center 36 (8~64) winsize 57
6647 08:07:48.885233
6648 08:07:48.888228 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6649 08:07:48.888315
6650 08:07:48.891506 [CATrainingPosCal] consider 1 rank data
6651 08:07:48.894781 u2DelayCellTimex100 = 270/100 ps
6652 08:07:48.898112 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 08:07:48.901432 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 08:07:48.904688 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 08:07:48.908272 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 08:07:48.914929 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 08:07:48.918093 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 08:07:48.918221
6659 08:07:48.921513 CA PerBit enable=1, Macro0, CA PI delay=36
6660 08:07:48.921606
6661 08:07:48.924427 [CBTSetCACLKResult] CA Dly = 36
6662 08:07:48.924496 CS Dly: 1 (0~32)
6663 08:07:48.924555 ==
6664 08:07:48.927902 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 08:07:48.934533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 08:07:48.934646 ==
6667 08:07:48.938062 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 08:07:48.944438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6669 08:07:48.948083 [CA 0] Center 36 (8~64) winsize 57
6670 08:07:48.950936 [CA 1] Center 36 (8~64) winsize 57
6671 08:07:48.954532 [CA 2] Center 36 (8~64) winsize 57
6672 08:07:48.958027 [CA 3] Center 36 (8~64) winsize 57
6673 08:07:48.961013 [CA 4] Center 36 (8~64) winsize 57
6674 08:07:48.964714 [CA 5] Center 36 (8~64) winsize 57
6675 08:07:48.964789
6676 08:07:48.968078 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6677 08:07:48.968173
6678 08:07:48.971156 [CATrainingPosCal] consider 2 rank data
6679 08:07:48.974545 u2DelayCellTimex100 = 270/100 ps
6680 08:07:48.977795 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 08:07:48.981270 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 08:07:48.984473 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 08:07:48.987527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 08:07:48.991060 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 08:07:48.994807 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 08:07:48.994905
6687 08:07:48.997976 CA PerBit enable=1, Macro0, CA PI delay=36
6688 08:07:49.001301
6689 08:07:49.001371 [CBTSetCACLKResult] CA Dly = 36
6690 08:07:49.004981 CS Dly: 1 (0~32)
6691 08:07:49.005054
6692 08:07:49.007979 ----->DramcWriteLeveling(PI) begin...
6693 08:07:49.008048 ==
6694 08:07:49.011383 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 08:07:49.014752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 08:07:49.014827 ==
6697 08:07:49.017524 Write leveling (Byte 0): 40 => 8
6698 08:07:49.021209 Write leveling (Byte 1): 40 => 8
6699 08:07:49.024929 DramcWriteLeveling(PI) end<-----
6700 08:07:49.024996
6701 08:07:49.025056 ==
6702 08:07:49.027887 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 08:07:49.031415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 08:07:49.031486 ==
6705 08:07:49.034231 [Gating] SW mode calibration
6706 08:07:49.040803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6707 08:07:49.047566 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6708 08:07:49.051079 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 08:07:49.057657 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 08:07:49.060999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 08:07:49.064322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 08:07:49.071326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 08:07:49.074538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 08:07:49.077860 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 08:07:49.084379 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 08:07:49.087348 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 08:07:49.090634 Total UI for P1: 0, mck2ui 16
6718 08:07:49.094077 best dqsien dly found for B0: ( 0, 14, 24)
6719 08:07:49.097241 Total UI for P1: 0, mck2ui 16
6720 08:07:49.100810 best dqsien dly found for B1: ( 0, 14, 24)
6721 08:07:49.103819 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6722 08:07:49.107575 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6723 08:07:49.107676
6724 08:07:49.110512 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 08:07:49.114060 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 08:07:49.117406 [Gating] SW calibration Done
6727 08:07:49.117477 ==
6728 08:07:49.120618 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 08:07:49.123857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 08:07:49.123931 ==
6731 08:07:49.127717 RX Vref Scan: 0
6732 08:07:49.127797
6733 08:07:49.130673 RX Vref 0 -> 0, step: 1
6734 08:07:49.130746
6735 08:07:49.130840 RX Delay -410 -> 252, step: 16
6736 08:07:49.137590 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6737 08:07:49.140932 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6738 08:07:49.144220 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6739 08:07:49.147452 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6740 08:07:49.154162 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6741 08:07:49.157725 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6742 08:07:49.160743 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6743 08:07:49.164341 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6744 08:07:49.170901 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6745 08:07:49.174589 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6746 08:07:49.177488 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6747 08:07:49.180766 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6748 08:07:49.187766 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6749 08:07:49.190931 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6750 08:07:49.193807 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6751 08:07:49.200719 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6752 08:07:49.200822 ==
6753 08:07:49.204425 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 08:07:49.207633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 08:07:49.207728 ==
6756 08:07:49.207792 DQS Delay:
6757 08:07:49.210693 DQS0 = 35, DQS1 = 35
6758 08:07:49.210766 DQM Delay:
6759 08:07:49.214110 DQM0 = 18, DQM1 = 13
6760 08:07:49.214183 DQ Delay:
6761 08:07:49.217333 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6762 08:07:49.220671 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6763 08:07:49.224200 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6764 08:07:49.227258 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6765 08:07:49.227359
6766 08:07:49.227460
6767 08:07:49.227554 ==
6768 08:07:49.230549 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 08:07:49.234034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 08:07:49.234111 ==
6771 08:07:49.234174
6772 08:07:49.234233
6773 08:07:49.237134 TX Vref Scan disable
6774 08:07:49.237214 == TX Byte 0 ==
6775 08:07:49.244206 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 08:07:49.247605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 08:07:49.247726 == TX Byte 1 ==
6778 08:07:49.254030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 08:07:49.257398 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 08:07:49.257496 ==
6781 08:07:49.260471 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 08:07:49.263960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 08:07:49.264034 ==
6784 08:07:49.264097
6785 08:07:49.264176
6786 08:07:49.267196 TX Vref Scan disable
6787 08:07:49.270560 == TX Byte 0 ==
6788 08:07:49.273493 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 08:07:49.276996 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 08:07:49.277084 == TX Byte 1 ==
6791 08:07:49.283499 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 08:07:49.287019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 08:07:49.287095
6794 08:07:49.287158 [DATLAT]
6795 08:07:49.290606 Freq=400, CH1 RK0
6796 08:07:49.290678
6797 08:07:49.290740 DATLAT Default: 0xf
6798 08:07:49.293659 0, 0xFFFF, sum = 0
6799 08:07:49.293732 1, 0xFFFF, sum = 0
6800 08:07:49.297147 2, 0xFFFF, sum = 0
6801 08:07:49.297228 3, 0xFFFF, sum = 0
6802 08:07:49.300563 4, 0xFFFF, sum = 0
6803 08:07:49.303735 5, 0xFFFF, sum = 0
6804 08:07:49.303824 6, 0xFFFF, sum = 0
6805 08:07:49.307242 7, 0xFFFF, sum = 0
6806 08:07:49.307347 8, 0xFFFF, sum = 0
6807 08:07:49.310383 9, 0xFFFF, sum = 0
6808 08:07:49.310480 10, 0xFFFF, sum = 0
6809 08:07:49.313496 11, 0xFFFF, sum = 0
6810 08:07:49.313585 12, 0xFFFF, sum = 0
6811 08:07:49.317255 13, 0x0, sum = 1
6812 08:07:49.317331 14, 0x0, sum = 2
6813 08:07:49.320500 15, 0x0, sum = 3
6814 08:07:49.320606 16, 0x0, sum = 4
6815 08:07:49.320698 best_step = 14
6816 08:07:49.323434
6817 08:07:49.323507 ==
6818 08:07:49.326935 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 08:07:49.330625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 08:07:49.330722 ==
6821 08:07:49.330823 RX Vref Scan: 1
6822 08:07:49.330912
6823 08:07:49.333513 RX Vref 0 -> 0, step: 1
6824 08:07:49.333608
6825 08:07:49.336992 RX Delay -311 -> 252, step: 8
6826 08:07:49.337103
6827 08:07:49.340017 Set Vref, RX VrefLevel [Byte0]: 54
6828 08:07:49.343230 [Byte1]: 54
6829 08:07:49.347048
6830 08:07:49.347169 Final RX Vref Byte 0 = 54 to rank0
6831 08:07:49.350312 Final RX Vref Byte 1 = 54 to rank0
6832 08:07:49.353966 Final RX Vref Byte 0 = 54 to rank1
6833 08:07:49.357142 Final RX Vref Byte 1 = 54 to rank1==
6834 08:07:49.360770 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 08:07:49.367302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 08:07:49.367420 ==
6837 08:07:49.367529 DQS Delay:
6838 08:07:49.370308 DQS0 = 32, DQS1 = 32
6839 08:07:49.370408 DQM Delay:
6840 08:07:49.370530 DQM0 = 13, DQM1 = 10
6841 08:07:49.373971 DQ Delay:
6842 08:07:49.376991 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6843 08:07:49.380543 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6844 08:07:49.380644 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6845 08:07:49.383854 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6846 08:07:49.383954
6847 08:07:49.387595
6848 08:07:49.394002 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6849 08:07:49.396985 CH1 RK0: MR19=C0C, MR18=90C9
6850 08:07:49.404110 CH1_RK0: MR19=0xC0C, MR18=0x90C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6851 08:07:49.404199 ==
6852 08:07:49.407303 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 08:07:49.410629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 08:07:49.410753 ==
6855 08:07:49.413785 [Gating] SW mode calibration
6856 08:07:49.420998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6857 08:07:49.423784 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6858 08:07:49.430674 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 08:07:49.434157 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 08:07:49.437073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 08:07:49.444195 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 08:07:49.447191 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 08:07:49.450256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 08:07:49.457348 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 08:07:49.460472 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 08:07:49.463618 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 08:07:49.466866 Total UI for P1: 0, mck2ui 16
6868 08:07:49.470537 best dqsien dly found for B0: ( 0, 14, 24)
6869 08:07:49.473680 Total UI for P1: 0, mck2ui 16
6870 08:07:49.476820 best dqsien dly found for B1: ( 0, 14, 24)
6871 08:07:49.480334 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6872 08:07:49.483473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6873 08:07:49.486868
6874 08:07:49.489957 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 08:07:49.493473 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 08:07:49.496946 [Gating] SW calibration Done
6877 08:07:49.497033 ==
6878 08:07:49.500363 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 08:07:49.503314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 08:07:49.503418 ==
6881 08:07:49.503511 RX Vref Scan: 0
6882 08:07:49.503600
6883 08:07:49.506934 RX Vref 0 -> 0, step: 1
6884 08:07:49.507008
6885 08:07:49.510489 RX Delay -410 -> 252, step: 16
6886 08:07:49.513682 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6887 08:07:49.520310 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6888 08:07:49.523770 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6889 08:07:49.526760 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6890 08:07:49.530204 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6891 08:07:49.536916 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6892 08:07:49.540262 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6893 08:07:49.543456 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6894 08:07:49.547023 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6895 08:07:49.550083 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6896 08:07:49.557087 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6897 08:07:49.560369 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6898 08:07:49.563456 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6899 08:07:49.570167 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6900 08:07:49.573007 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6901 08:07:49.576560 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6902 08:07:49.576638 ==
6903 08:07:49.580065 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 08:07:49.582973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 08:07:49.586564 ==
6906 08:07:49.586668 DQS Delay:
6907 08:07:49.586753 DQS0 = 35, DQS1 = 35
6908 08:07:49.590359 DQM Delay:
6909 08:07:49.590451 DQM0 = 18, DQM1 = 15
6910 08:07:49.593750 DQ Delay:
6911 08:07:49.593845 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6912 08:07:49.596516 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6913 08:07:49.599829 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6914 08:07:49.603109 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6915 08:07:49.603185
6916 08:07:49.603251
6917 08:07:49.606472 ==
6918 08:07:49.606572 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 08:07:49.613368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 08:07:49.613447 ==
6921 08:07:49.613512
6922 08:07:49.613572
6923 08:07:49.616425 TX Vref Scan disable
6924 08:07:49.616529 == TX Byte 0 ==
6925 08:07:49.619934 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6926 08:07:49.623273 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6927 08:07:49.626700 == TX Byte 1 ==
6928 08:07:49.629793 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6929 08:07:49.633393 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6930 08:07:49.636874 ==
6931 08:07:49.636946 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 08:07:49.643481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 08:07:49.643587 ==
6934 08:07:49.643679
6935 08:07:49.643740
6936 08:07:49.646321 TX Vref Scan disable
6937 08:07:49.646390 == TX Byte 0 ==
6938 08:07:49.650134 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6939 08:07:49.653218 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6940 08:07:49.656649 == TX Byte 1 ==
6941 08:07:49.660117 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6942 08:07:49.663083 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6943 08:07:49.666461
6944 08:07:49.666566 [DATLAT]
6945 08:07:49.666658 Freq=400, CH1 RK1
6946 08:07:49.666747
6947 08:07:49.670051 DATLAT Default: 0xe
6948 08:07:49.670150 0, 0xFFFF, sum = 0
6949 08:07:49.673585 1, 0xFFFF, sum = 0
6950 08:07:49.673692 2, 0xFFFF, sum = 0
6951 08:07:49.676625 3, 0xFFFF, sum = 0
6952 08:07:49.676695 4, 0xFFFF, sum = 0
6953 08:07:49.679727 5, 0xFFFF, sum = 0
6954 08:07:49.679808 6, 0xFFFF, sum = 0
6955 08:07:49.682987 7, 0xFFFF, sum = 0
6956 08:07:49.686334 8, 0xFFFF, sum = 0
6957 08:07:49.686438 9, 0xFFFF, sum = 0
6958 08:07:49.689824 10, 0xFFFF, sum = 0
6959 08:07:49.689926 11, 0xFFFF, sum = 0
6960 08:07:49.693601 12, 0xFFFF, sum = 0
6961 08:07:49.693675 13, 0x0, sum = 1
6962 08:07:49.696354 14, 0x0, sum = 2
6963 08:07:49.696425 15, 0x0, sum = 3
6964 08:07:49.699742 16, 0x0, sum = 4
6965 08:07:49.699815 best_step = 14
6966 08:07:49.699878
6967 08:07:49.699936 ==
6968 08:07:49.703319 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 08:07:49.706619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 08:07:49.706695 ==
6971 08:07:49.709898 RX Vref Scan: 0
6972 08:07:49.709973
6973 08:07:49.713092 RX Vref 0 -> 0, step: 1
6974 08:07:49.713163
6975 08:07:49.713225 RX Delay -311 -> 252, step: 8
6976 08:07:49.721883 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6977 08:07:49.724868 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6978 08:07:49.728457 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6979 08:07:49.731574 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6980 08:07:49.738229 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6981 08:07:49.742192 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6982 08:07:49.744768 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6983 08:07:49.748458 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6984 08:07:49.755024 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6985 08:07:49.758149 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6986 08:07:49.761407 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6987 08:07:49.765053 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6988 08:07:49.771555 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6989 08:07:49.774889 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6990 08:07:49.777836 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6991 08:07:49.784711 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6992 08:07:49.784793 ==
6993 08:07:49.787921 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 08:07:49.791431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 08:07:49.791508 ==
6996 08:07:49.791572 DQS Delay:
6997 08:07:49.794505 DQS0 = 28, DQS1 = 36
6998 08:07:49.794579 DQM Delay:
6999 08:07:49.797959 DQM0 = 10, DQM1 = 14
7000 08:07:49.798058 DQ Delay:
7001 08:07:49.801086 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =4
7002 08:07:49.804757 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7003 08:07:49.807726 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7004 08:07:49.811328 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7005 08:07:49.811406
7006 08:07:49.811470
7007 08:07:49.818025 [DQSOSCAuto] RK1, (LSB)MR18= 0xc355, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7008 08:07:49.821132 CH1 RK1: MR19=C0C, MR18=C355
7009 08:07:49.828170 CH1_RK1: MR19=0xC0C, MR18=0xC355, DQSOSC=385, MR23=63, INC=398, DEC=265
7010 08:07:49.830949 [RxdqsGatingPostProcess] freq 400
7011 08:07:49.837600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7012 08:07:49.837681 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 08:07:49.841057 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 08:07:49.844866 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 08:07:49.847776 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 08:07:49.851024 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 08:07:49.854256 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 08:07:49.858048 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 08:07:49.861028 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 08:07:49.864580 Pre-setting of DQS Precalculation
7021 08:07:49.867508 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7022 08:07:49.877787 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7023 08:07:49.884136 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7024 08:07:49.884215
7025 08:07:49.884282
7026 08:07:49.887727 [Calibration Summary] 800 Mbps
7027 08:07:49.887800 CH 0, Rank 0
7028 08:07:49.890777 SW Impedance : PASS
7029 08:07:49.890847 DUTY Scan : NO K
7030 08:07:49.894256 ZQ Calibration : PASS
7031 08:07:49.897803 Jitter Meter : NO K
7032 08:07:49.897876 CBT Training : PASS
7033 08:07:49.900744 Write leveling : PASS
7034 08:07:49.904048 RX DQS gating : PASS
7035 08:07:49.904130 RX DQ/DQS(RDDQC) : PASS
7036 08:07:49.908002 TX DQ/DQS : PASS
7037 08:07:49.910872 RX DATLAT : PASS
7038 08:07:49.910954 RX DQ/DQS(Engine): PASS
7039 08:07:49.914425 TX OE : NO K
7040 08:07:49.914508 All Pass.
7041 08:07:49.914596
7042 08:07:49.917388 CH 0, Rank 1
7043 08:07:49.917472 SW Impedance : PASS
7044 08:07:49.921051 DUTY Scan : NO K
7045 08:07:49.924003 ZQ Calibration : PASS
7046 08:07:49.924088 Jitter Meter : NO K
7047 08:07:49.927253 CBT Training : PASS
7048 08:07:49.930498 Write leveling : NO K
7049 08:07:49.930583 RX DQS gating : PASS
7050 08:07:49.933804 RX DQ/DQS(RDDQC) : PASS
7051 08:07:49.933888 TX DQ/DQS : PASS
7052 08:07:49.937352 RX DATLAT : PASS
7053 08:07:49.940882 RX DQ/DQS(Engine): PASS
7054 08:07:49.940967 TX OE : NO K
7055 08:07:49.944317 All Pass.
7056 08:07:49.944401
7057 08:07:49.944488 CH 1, Rank 0
7058 08:07:49.947614 SW Impedance : PASS
7059 08:07:49.947708 DUTY Scan : NO K
7060 08:07:49.951158 ZQ Calibration : PASS
7061 08:07:49.954344 Jitter Meter : NO K
7062 08:07:49.954430 CBT Training : PASS
7063 08:07:49.957420 Write leveling : PASS
7064 08:07:49.960673 RX DQS gating : PASS
7065 08:07:49.960757 RX DQ/DQS(RDDQC) : PASS
7066 08:07:49.963923 TX DQ/DQS : PASS
7067 08:07:49.967808 RX DATLAT : PASS
7068 08:07:49.967892 RX DQ/DQS(Engine): PASS
7069 08:07:49.970459 TX OE : NO K
7070 08:07:49.970545 All Pass.
7071 08:07:49.970613
7072 08:07:49.973949 CH 1, Rank 1
7073 08:07:49.974024 SW Impedance : PASS
7074 08:07:49.977544 DUTY Scan : NO K
7075 08:07:49.980541 ZQ Calibration : PASS
7076 08:07:49.980627 Jitter Meter : NO K
7077 08:07:49.984235 CBT Training : PASS
7078 08:07:49.984320 Write leveling : NO K
7079 08:07:49.987800 RX DQS gating : PASS
7080 08:07:49.990598 RX DQ/DQS(RDDQC) : PASS
7081 08:07:49.990682 TX DQ/DQS : PASS
7082 08:07:49.994262 RX DATLAT : PASS
7083 08:07:49.997247 RX DQ/DQS(Engine): PASS
7084 08:07:49.997332 TX OE : NO K
7085 08:07:50.000571 All Pass.
7086 08:07:50.000658
7087 08:07:50.000744 DramC Write-DBI off
7088 08:07:50.004065 PER_BANK_REFRESH: Hybrid Mode
7089 08:07:50.007277 TX_TRACKING: ON
7090 08:07:50.014109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7091 08:07:50.017924 [FAST_K] Save calibration result to emmc
7092 08:07:50.020534 dramc_set_vcore_voltage set vcore to 725000
7093 08:07:50.024300 Read voltage for 1600, 0
7094 08:07:50.024382 Vio18 = 0
7095 08:07:50.027453 Vcore = 725000
7096 08:07:50.027535 Vdram = 0
7097 08:07:50.027600 Vddq = 0
7098 08:07:50.030857 Vmddr = 0
7099 08:07:50.033698 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7100 08:07:50.040802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7101 08:07:50.040898 MEM_TYPE=3, freq_sel=13
7102 08:07:50.043885 sv_algorithm_assistance_LP4_3733
7103 08:07:50.050997 ============ PULL DRAM RESETB DOWN ============
7104 08:07:50.054186 ========== PULL DRAM RESETB DOWN end =========
7105 08:07:50.057278 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7106 08:07:50.061023 ===================================
7107 08:07:50.063841 LPDDR4 DRAM CONFIGURATION
7108 08:07:50.067499 ===================================
7109 08:07:50.067621 EX_ROW_EN[0] = 0x0
7110 08:07:50.070374 EX_ROW_EN[1] = 0x0
7111 08:07:50.073897 LP4Y_EN = 0x0
7112 08:07:50.073993 WORK_FSP = 0x1
7113 08:07:50.077345 WL = 0x5
7114 08:07:50.077425 RL = 0x5
7115 08:07:50.080454 BL = 0x2
7116 08:07:50.080579 RPST = 0x0
7117 08:07:50.083855 RD_PRE = 0x0
7118 08:07:50.083936 WR_PRE = 0x1
7119 08:07:50.087382 WR_PST = 0x1
7120 08:07:50.087522 DBI_WR = 0x0
7121 08:07:50.090453 DBI_RD = 0x0
7122 08:07:50.090579 OTF = 0x1
7123 08:07:50.093977 ===================================
7124 08:07:50.096973 ===================================
7125 08:07:50.100619 ANA top config
7126 08:07:50.103422 ===================================
7127 08:07:50.103506 DLL_ASYNC_EN = 0
7128 08:07:50.107030 ALL_SLAVE_EN = 0
7129 08:07:50.110041 NEW_RANK_MODE = 1
7130 08:07:50.113593 DLL_IDLE_MODE = 1
7131 08:07:50.117294 LP45_APHY_COMB_EN = 1
7132 08:07:50.117383 TX_ODT_DIS = 0
7133 08:07:50.120166 NEW_8X_MODE = 1
7134 08:07:50.123817 ===================================
7135 08:07:50.126996 ===================================
7136 08:07:50.130341 data_rate = 3200
7137 08:07:50.133529 CKR = 1
7138 08:07:50.136670 DQ_P2S_RATIO = 8
7139 08:07:50.139960 ===================================
7140 08:07:50.140042 CA_P2S_RATIO = 8
7141 08:07:50.143456 DQ_CA_OPEN = 0
7142 08:07:50.146961 DQ_SEMI_OPEN = 0
7143 08:07:50.150309 CA_SEMI_OPEN = 0
7144 08:07:50.153360 CA_FULL_RATE = 0
7145 08:07:50.156879 DQ_CKDIV4_EN = 0
7146 08:07:50.156954 CA_CKDIV4_EN = 0
7147 08:07:50.160582 CA_PREDIV_EN = 0
7148 08:07:50.163234 PH8_DLY = 12
7149 08:07:50.166552 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7150 08:07:50.169725 DQ_AAMCK_DIV = 4
7151 08:07:50.173152 CA_AAMCK_DIV = 4
7152 08:07:50.173228 CA_ADMCK_DIV = 4
7153 08:07:50.176847 DQ_TRACK_CA_EN = 0
7154 08:07:50.179914 CA_PICK = 1600
7155 08:07:50.183737 CA_MCKIO = 1600
7156 08:07:50.186621 MCKIO_SEMI = 0
7157 08:07:50.189842 PLL_FREQ = 3068
7158 08:07:50.193141 DQ_UI_PI_RATIO = 32
7159 08:07:50.196768 CA_UI_PI_RATIO = 0
7160 08:07:50.200451 ===================================
7161 08:07:50.200547 ===================================
7162 08:07:50.203475 memory_type:LPDDR4
7163 08:07:50.206811 GP_NUM : 10
7164 08:07:50.206914 SRAM_EN : 1
7165 08:07:50.209801 MD32_EN : 0
7166 08:07:50.213115 ===================================
7167 08:07:50.216681 [ANA_INIT] >>>>>>>>>>>>>>
7168 08:07:50.220086 <<<<<< [CONFIGURE PHASE]: ANA_TX
7169 08:07:50.223150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7170 08:07:50.226527 ===================================
7171 08:07:50.226627 data_rate = 3200,PCW = 0X7600
7172 08:07:50.230384 ===================================
7173 08:07:50.232980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7174 08:07:50.240019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 08:07:50.246433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 08:07:50.249740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7177 08:07:50.253008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7178 08:07:50.256529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7179 08:07:50.260030 [ANA_INIT] flow start
7180 08:07:50.263143 [ANA_INIT] PLL >>>>>>>>
7181 08:07:50.263218 [ANA_INIT] PLL <<<<<<<<
7182 08:07:50.266466 [ANA_INIT] MIDPI >>>>>>>>
7183 08:07:50.269875 [ANA_INIT] MIDPI <<<<<<<<
7184 08:07:50.269951 [ANA_INIT] DLL >>>>>>>>
7185 08:07:50.273244 [ANA_INIT] DLL <<<<<<<<
7186 08:07:50.276313 [ANA_INIT] flow end
7187 08:07:50.279864 ============ LP4 DIFF to SE enter ============
7188 08:07:50.283044 ============ LP4 DIFF to SE exit ============
7189 08:07:50.286764 [ANA_INIT] <<<<<<<<<<<<<
7190 08:07:50.289577 [Flow] Enable top DCM control >>>>>
7191 08:07:50.293084 [Flow] Enable top DCM control <<<<<
7192 08:07:50.296669 Enable DLL master slave shuffle
7193 08:07:50.299692 ==============================================================
7194 08:07:50.303098 Gating Mode config
7195 08:07:50.309640 ==============================================================
7196 08:07:50.309716 Config description:
7197 08:07:50.319713 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7198 08:07:50.326349 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7199 08:07:50.329807 SELPH_MODE 0: By rank 1: By Phase
7200 08:07:50.336465 ==============================================================
7201 08:07:50.339988 GAT_TRACK_EN = 1
7202 08:07:50.342875 RX_GATING_MODE = 2
7203 08:07:50.346142 RX_GATING_TRACK_MODE = 2
7204 08:07:50.349543 SELPH_MODE = 1
7205 08:07:50.353026 PICG_EARLY_EN = 1
7206 08:07:50.353113 VALID_LAT_VALUE = 1
7207 08:07:50.359605 ==============================================================
7208 08:07:50.362954 Enter into Gating configuration >>>>
7209 08:07:50.366349 Exit from Gating configuration <<<<
7210 08:07:50.369997 Enter into DVFS_PRE_config >>>>>
7211 08:07:50.379575 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7212 08:07:50.383360 Exit from DVFS_PRE_config <<<<<
7213 08:07:50.386385 Enter into PICG configuration >>>>
7214 08:07:50.389813 Exit from PICG configuration <<<<
7215 08:07:50.392767 [RX_INPUT] configuration >>>>>
7216 08:07:50.396501 [RX_INPUT] configuration <<<<<
7217 08:07:50.402690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7218 08:07:50.406336 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7219 08:07:50.413018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 08:07:50.419225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 08:07:50.426502 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 08:07:50.432592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 08:07:50.436023 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7224 08:07:50.439287 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7225 08:07:50.442599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7226 08:07:50.448910 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7227 08:07:50.452553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7228 08:07:50.455959 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 08:07:50.458813 ===================================
7230 08:07:50.462398 LPDDR4 DRAM CONFIGURATION
7231 08:07:50.465796 ===================================
7232 08:07:50.465908 EX_ROW_EN[0] = 0x0
7233 08:07:50.468820 EX_ROW_EN[1] = 0x0
7234 08:07:50.471885 LP4Y_EN = 0x0
7235 08:07:50.471989 WORK_FSP = 0x1
7236 08:07:50.475644 WL = 0x5
7237 08:07:50.475757 RL = 0x5
7238 08:07:50.478839 BL = 0x2
7239 08:07:50.478945 RPST = 0x0
7240 08:07:50.482016 RD_PRE = 0x0
7241 08:07:50.482093 WR_PRE = 0x1
7242 08:07:50.485613 WR_PST = 0x1
7243 08:07:50.485686 DBI_WR = 0x0
7244 08:07:50.488701 DBI_RD = 0x0
7245 08:07:50.488805 OTF = 0x1
7246 08:07:50.492031 ===================================
7247 08:07:50.495766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7248 08:07:50.502357 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7249 08:07:50.505111 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7250 08:07:50.508614 ===================================
7251 08:07:50.511870 LPDDR4 DRAM CONFIGURATION
7252 08:07:50.515478 ===================================
7253 08:07:50.515586 EX_ROW_EN[0] = 0x10
7254 08:07:50.519017 EX_ROW_EN[1] = 0x0
7255 08:07:50.522265 LP4Y_EN = 0x0
7256 08:07:50.522365 WORK_FSP = 0x1
7257 08:07:50.525093 WL = 0x5
7258 08:07:50.525179 RL = 0x5
7259 08:07:50.528694 BL = 0x2
7260 08:07:50.528793 RPST = 0x0
7261 08:07:50.532358 RD_PRE = 0x0
7262 08:07:50.532429 WR_PRE = 0x1
7263 08:07:50.535150 WR_PST = 0x1
7264 08:07:50.535251 DBI_WR = 0x0
7265 08:07:50.538831 DBI_RD = 0x0
7266 08:07:50.538927 OTF = 0x1
7267 08:07:50.541657 ===================================
7268 08:07:50.548363 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7269 08:07:50.548442 ==
7270 08:07:50.552090 Dram Type= 6, Freq= 0, CH_0, rank 0
7271 08:07:50.555299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7272 08:07:50.555373 ==
7273 08:07:50.558428 [Duty_Offset_Calibration]
7274 08:07:50.562199 B0:2 B1:1 CA:1
7275 08:07:50.562280
7276 08:07:50.564968 [DutyScan_Calibration_Flow] k_type=0
7277 08:07:50.573647
7278 08:07:50.573729 ==CLK 0==
7279 08:07:50.577013 Final CLK duty delay cell = 0
7280 08:07:50.580445 [0] MAX Duty = 5156%(X100), DQS PI = 22
7281 08:07:50.583677 [0] MIN Duty = 4907%(X100), DQS PI = 0
7282 08:07:50.583760 [0] AVG Duty = 5031%(X100)
7283 08:07:50.583826
7284 08:07:50.587156 CH0 CLK Duty spec in!! Max-Min= 249%
7285 08:07:50.593551 [DutyScan_Calibration_Flow] ====Done====
7286 08:07:50.593633
7287 08:07:50.596578 [DutyScan_Calibration_Flow] k_type=1
7288 08:07:50.612980
7289 08:07:50.613109 ==DQS 0 ==
7290 08:07:50.615981 Final DQS duty delay cell = -4
7291 08:07:50.619815 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7292 08:07:50.622556 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7293 08:07:50.626183 [-4] AVG Duty = 4906%(X100)
7294 08:07:50.626267
7295 08:07:50.626332 ==DQS 1 ==
7296 08:07:50.629257 Final DQS duty delay cell = 0
7297 08:07:50.632837 [0] MAX Duty = 5187%(X100), DQS PI = 20
7298 08:07:50.635811 [0] MIN Duty = 5062%(X100), DQS PI = 36
7299 08:07:50.639139 [0] AVG Duty = 5124%(X100)
7300 08:07:50.639221
7301 08:07:50.642603 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7302 08:07:50.642695
7303 08:07:50.645973 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7304 08:07:50.649087 [DutyScan_Calibration_Flow] ====Done====
7305 08:07:50.649186
7306 08:07:50.652215 [DutyScan_Calibration_Flow] k_type=3
7307 08:07:50.669501
7308 08:07:50.669604 ==DQM 0 ==
7309 08:07:50.672731 Final DQM duty delay cell = 0
7310 08:07:50.676149 [0] MAX Duty = 5187%(X100), DQS PI = 26
7311 08:07:50.679072 [0] MIN Duty = 4907%(X100), DQS PI = 56
7312 08:07:50.682505 [0] AVG Duty = 5047%(X100)
7313 08:07:50.682587
7314 08:07:50.682652 ==DQM 1 ==
7315 08:07:50.686321 Final DQM duty delay cell = -4
7316 08:07:50.689187 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7317 08:07:50.692622 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7318 08:07:50.695965 [-4] AVG Duty = 4906%(X100)
7319 08:07:50.696048
7320 08:07:50.699192 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7321 08:07:50.699310
7322 08:07:50.702670 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7323 08:07:50.705950 [DutyScan_Calibration_Flow] ====Done====
7324 08:07:50.706065
7325 08:07:50.709291 [DutyScan_Calibration_Flow] k_type=2
7326 08:07:50.726760
7327 08:07:50.726841 ==DQ 0 ==
7328 08:07:50.730568 Final DQ duty delay cell = 0
7329 08:07:50.733445 [0] MAX Duty = 5062%(X100), DQS PI = 24
7330 08:07:50.737141 [0] MIN Duty = 4907%(X100), DQS PI = 0
7331 08:07:50.737251 [0] AVG Duty = 4984%(X100)
7332 08:07:50.740425
7333 08:07:50.740500 ==DQ 1 ==
7334 08:07:50.743753 Final DQ duty delay cell = 0
7335 08:07:50.747092 [0] MAX Duty = 5156%(X100), DQS PI = 22
7336 08:07:50.750343 [0] MIN Duty = 4938%(X100), DQS PI = 34
7337 08:07:50.750450 [0] AVG Duty = 5047%(X100)
7338 08:07:50.750541
7339 08:07:50.756452 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7340 08:07:50.756543
7341 08:07:50.759989 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7342 08:07:50.763521 [DutyScan_Calibration_Flow] ====Done====
7343 08:07:50.763618 ==
7344 08:07:50.766599 Dram Type= 6, Freq= 0, CH_1, rank 0
7345 08:07:50.770393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7346 08:07:50.770494 ==
7347 08:07:50.773596 [Duty_Offset_Calibration]
7348 08:07:50.773694 B0:1 B1:0 CA:1
7349 08:07:50.773783
7350 08:07:50.776571 [DutyScan_Calibration_Flow] k_type=0
7351 08:07:50.786654
7352 08:07:50.786754 ==CLK 0==
7353 08:07:50.789712 Final CLK duty delay cell = -4
7354 08:07:50.793400 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7355 08:07:50.796104 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7356 08:07:50.799498 [-4] AVG Duty = 4922%(X100)
7357 08:07:50.799579
7358 08:07:50.803045 CH1 CLK Duty spec in!! Max-Min= 156%
7359 08:07:50.806595 [DutyScan_Calibration_Flow] ====Done====
7360 08:07:50.806680
7361 08:07:50.809453 [DutyScan_Calibration_Flow] k_type=1
7362 08:07:50.826481
7363 08:07:50.826596 ==DQS 0 ==
7364 08:07:50.829841 Final DQS duty delay cell = 0
7365 08:07:50.833123 [0] MAX Duty = 5094%(X100), DQS PI = 14
7366 08:07:50.836005 [0] MIN Duty = 4844%(X100), DQS PI = 50
7367 08:07:50.839525 [0] AVG Duty = 4969%(X100)
7368 08:07:50.839623
7369 08:07:50.839723 ==DQS 1 ==
7370 08:07:50.843406 Final DQS duty delay cell = 0
7371 08:07:50.846173 [0] MAX Duty = 5249%(X100), DQS PI = 16
7372 08:07:50.849789 [0] MIN Duty = 4969%(X100), DQS PI = 6
7373 08:07:50.853384 [0] AVG Duty = 5109%(X100)
7374 08:07:50.853482
7375 08:07:50.856010 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7376 08:07:50.856092
7377 08:07:50.859471 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7378 08:07:50.862968 [DutyScan_Calibration_Flow] ====Done====
7379 08:07:50.863076
7380 08:07:50.866031 [DutyScan_Calibration_Flow] k_type=3
7381 08:07:50.883420
7382 08:07:50.883543 ==DQM 0 ==
7383 08:07:50.886505 Final DQM duty delay cell = 0
7384 08:07:50.889549 [0] MAX Duty = 5218%(X100), DQS PI = 8
7385 08:07:50.893034 [0] MIN Duty = 4969%(X100), DQS PI = 48
7386 08:07:50.896660 [0] AVG Duty = 5093%(X100)
7387 08:07:50.896782
7388 08:07:50.896891 ==DQM 1 ==
7389 08:07:50.899821 Final DQM duty delay cell = 0
7390 08:07:50.903434 [0] MAX Duty = 5093%(X100), DQS PI = 16
7391 08:07:50.906369 [0] MIN Duty = 4907%(X100), DQS PI = 50
7392 08:07:50.909683 [0] AVG Duty = 5000%(X100)
7393 08:07:50.909802
7394 08:07:50.912935 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7395 08:07:50.913056
7396 08:07:50.916591 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7397 08:07:50.919788 [DutyScan_Calibration_Flow] ====Done====
7398 08:07:50.919906
7399 08:07:50.923258 [DutyScan_Calibration_Flow] k_type=2
7400 08:07:50.939084
7401 08:07:50.939206 ==DQ 0 ==
7402 08:07:50.942687 Final DQ duty delay cell = -4
7403 08:07:50.946182 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7404 08:07:50.949162 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7405 08:07:50.952658 [-4] AVG Duty = 4968%(X100)
7406 08:07:50.952762
7407 08:07:50.952855 ==DQ 1 ==
7408 08:07:50.956035 Final DQ duty delay cell = 0
7409 08:07:50.959145 [0] MAX Duty = 5124%(X100), DQS PI = 16
7410 08:07:50.962465 [0] MIN Duty = 4969%(X100), DQS PI = 8
7411 08:07:50.965953 [0] AVG Duty = 5046%(X100)
7412 08:07:50.966035
7413 08:07:50.969127 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7414 08:07:50.969209
7415 08:07:50.972136 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7416 08:07:50.975616 [DutyScan_Calibration_Flow] ====Done====
7417 08:07:50.979299 nWR fixed to 30
7418 08:07:50.982119 [ModeRegInit_LP4] CH0 RK0
7419 08:07:50.982201 [ModeRegInit_LP4] CH0 RK1
7420 08:07:50.985629 [ModeRegInit_LP4] CH1 RK0
7421 08:07:50.988552 [ModeRegInit_LP4] CH1 RK1
7422 08:07:50.988634 match AC timing 5
7423 08:07:50.995603 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7424 08:07:50.998648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7425 08:07:51.001814 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7426 08:07:51.008846 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7427 08:07:51.011810 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7428 08:07:51.011892 [MiockJmeterHQA]
7429 08:07:51.011957
7430 08:07:51.015214 [DramcMiockJmeter] u1RxGatingPI = 0
7431 08:07:51.018600 0 : 4252, 4027
7432 08:07:51.018683 4 : 4363, 4137
7433 08:07:51.021994 8 : 4253, 4026
7434 08:07:51.022077 12 : 4253, 4027
7435 08:07:51.025265 16 : 4252, 4027
7436 08:07:51.025347 20 : 4252, 4027
7437 08:07:51.025413 24 : 4363, 4137
7438 08:07:51.028531 28 : 4363, 4138
7439 08:07:51.028613 32 : 4253, 4026
7440 08:07:51.031766 36 : 4252, 4027
7441 08:07:51.031848 40 : 4252, 4027
7442 08:07:51.035269 44 : 4253, 4026
7443 08:07:51.035351 48 : 4255, 4030
7444 08:07:51.035416 52 : 4363, 4138
7445 08:07:51.038406 56 : 4250, 4027
7446 08:07:51.038488 60 : 4250, 4026
7447 08:07:51.042134 64 : 4250, 4026
7448 08:07:51.042217 68 : 4252, 4030
7449 08:07:51.045413 72 : 4250, 4026
7450 08:07:51.045495 76 : 4361, 4137
7451 08:07:51.048787 80 : 4361, 4138
7452 08:07:51.048872 84 : 4250, 4026
7453 08:07:51.048937 88 : 4250, 50
7454 08:07:51.052028 92 : 4250, 0
7455 08:07:51.052111 96 : 4363, 0
7456 08:07:51.054968 100 : 4252, 0
7457 08:07:51.055060 104 : 4360, 0
7458 08:07:51.055126 108 : 4250, 0
7459 08:07:51.058880 112 : 4250, 0
7460 08:07:51.058996 116 : 4252, 0
7461 08:07:51.061450 120 : 4250, 0
7462 08:07:51.061558 124 : 4361, 0
7463 08:07:51.061650 128 : 4361, 0
7464 08:07:51.064753 132 : 4250, 0
7465 08:07:51.064827 136 : 4361, 0
7466 08:07:51.064890 140 : 4250, 0
7467 08:07:51.068234 144 : 4250, 0
7468 08:07:51.068312 148 : 4250, 0
7469 08:07:51.071765 152 : 4360, 0
7470 08:07:51.071836 156 : 4361, 0
7471 08:07:51.071897 160 : 4250, 0
7472 08:07:51.074788 164 : 4250, 0
7473 08:07:51.074886 168 : 4253, 0
7474 08:07:51.078363 172 : 4250, 0
7475 08:07:51.078463 176 : 4250, 0
7476 08:07:51.078562 180 : 4363, 0
7477 08:07:51.081320 184 : 4250, 0
7478 08:07:51.081393 188 : 4361, 0
7479 08:07:51.084909 192 : 4250, 0
7480 08:07:51.084987 196 : 4250, 0
7481 08:07:51.085057 200 : 4250, 0
7482 08:07:51.088117 204 : 4360, 1384
7483 08:07:51.088188 208 : 4252, 4000
7484 08:07:51.091546 212 : 4361, 4137
7485 08:07:51.091652 216 : 4253, 4029
7486 08:07:51.094834 220 : 4360, 4138
7487 08:07:51.094931 224 : 4360, 4137
7488 08:07:51.098707 228 : 4250, 4026
7489 08:07:51.098819 232 : 4250, 4027
7490 08:07:51.101757 236 : 4363, 4140
7491 08:07:51.101835 240 : 4250, 4027
7492 08:07:51.101899 244 : 4250, 4026
7493 08:07:51.104563 248 : 4250, 4027
7494 08:07:51.104647 252 : 4252, 4030
7495 08:07:51.108007 256 : 4249, 4027
7496 08:07:51.108090 260 : 4250, 4026
7497 08:07:51.111573 264 : 4361, 4137
7498 08:07:51.111685 268 : 4250, 4027
7499 08:07:51.114571 272 : 4250, 4027
7500 08:07:51.114654 276 : 4360, 4137
7501 08:07:51.118258 280 : 4250, 4026
7502 08:07:51.118341 284 : 4250, 4027
7503 08:07:51.121542 288 : 4363, 4140
7504 08:07:51.121624 292 : 4250, 4027
7505 08:07:51.125113 296 : 4250, 4026
7506 08:07:51.125196 300 : 4250, 4027
7507 08:07:51.125262 304 : 4252, 4030
7508 08:07:51.128084 308 : 4250, 3966
7509 08:07:51.128167 312 : 4250, 1912
7510 08:07:51.128234
7511 08:07:51.131499 MIOCK jitter meter ch=0
7512 08:07:51.131581
7513 08:07:51.134957 1T = (312-88) = 224 dly cells
7514 08:07:51.141907 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7515 08:07:51.141990 ==
7516 08:07:51.144571 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 08:07:51.148208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 08:07:51.148292 ==
7519 08:07:51.154549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 08:07:51.157991 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 08:07:51.161321 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 08:07:51.167750 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 08:07:51.176929 [CA 0] Center 42 (12~73) winsize 62
7524 08:07:51.180174 [CA 1] Center 42 (12~73) winsize 62
7525 08:07:51.183808 [CA 2] Center 37 (8~67) winsize 60
7526 08:07:51.186812 [CA 3] Center 37 (7~67) winsize 61
7527 08:07:51.190131 [CA 4] Center 36 (6~66) winsize 61
7528 08:07:51.193357 [CA 5] Center 35 (6~64) winsize 59
7529 08:07:51.193432
7530 08:07:51.196774 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 08:07:51.196847
7532 08:07:51.200333 [CATrainingPosCal] consider 1 rank data
7533 08:07:51.203194 u2DelayCellTimex100 = 290/100 ps
7534 08:07:51.206791 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7535 08:07:51.213124 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7536 08:07:51.216786 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7537 08:07:51.220325 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7538 08:07:51.223223 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7539 08:07:51.226806 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7540 08:07:51.226882
7541 08:07:51.230024 CA PerBit enable=1, Macro0, CA PI delay=35
7542 08:07:51.230124
7543 08:07:51.233112 [CBTSetCACLKResult] CA Dly = 35
7544 08:07:51.236544 CS Dly: 9 (0~40)
7545 08:07:51.240143 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 08:07:51.243433 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 08:07:51.243509 ==
7548 08:07:51.246845 Dram Type= 6, Freq= 0, CH_0, rank 1
7549 08:07:51.250254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 08:07:51.250348 ==
7551 08:07:51.256746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 08:07:51.260029 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 08:07:51.266383 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 08:07:51.269687 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 08:07:51.279855 [CA 0] Center 42 (12~73) winsize 62
7556 08:07:51.283192 [CA 1] Center 42 (12~73) winsize 62
7557 08:07:51.286371 [CA 2] Center 37 (8~67) winsize 60
7558 08:07:51.290120 [CA 3] Center 38 (8~68) winsize 61
7559 08:07:51.293311 [CA 4] Center 35 (6~65) winsize 60
7560 08:07:51.296568 [CA 5] Center 35 (5~65) winsize 61
7561 08:07:51.296650
7562 08:07:51.299934 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7563 08:07:51.300010
7564 08:07:51.303251 [CATrainingPosCal] consider 2 rank data
7565 08:07:51.306836 u2DelayCellTimex100 = 290/100 ps
7566 08:07:51.310343 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7567 08:07:51.316668 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7568 08:07:51.319630 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7569 08:07:51.322851 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7570 08:07:51.326565 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7571 08:07:51.329892 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7572 08:07:51.329966
7573 08:07:51.332881 CA PerBit enable=1, Macro0, CA PI delay=35
7574 08:07:51.332955
7575 08:07:51.336542 [CBTSetCACLKResult] CA Dly = 35
7576 08:07:51.339505 CS Dly: 10 (0~42)
7577 08:07:51.342730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 08:07:51.346158 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 08:07:51.346235
7580 08:07:51.349472 ----->DramcWriteLeveling(PI) begin...
7581 08:07:51.349587 ==
7582 08:07:51.353004 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 08:07:51.359658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 08:07:51.359782 ==
7585 08:07:51.363120 Write leveling (Byte 0): 37 => 37
7586 08:07:51.363244 Write leveling (Byte 1): 27 => 27
7587 08:07:51.366251 DramcWriteLeveling(PI) end<-----
7588 08:07:51.366369
7589 08:07:51.366482 ==
7590 08:07:51.369782 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 08:07:51.375994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 08:07:51.376128 ==
7593 08:07:51.379390 [Gating] SW mode calibration
7594 08:07:51.385868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7595 08:07:51.389347 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7596 08:07:51.395968 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 08:07:51.399603 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 08:07:51.402525 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7599 08:07:51.409457 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7600 08:07:51.412556 1 4 16 | B1->B0 | 2424 3535 | 0 1 | (0 0) (1 1)
7601 08:07:51.416145 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 08:07:51.422533 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 08:07:51.425955 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 08:07:51.428982 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 08:07:51.436011 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7606 08:07:51.439026 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7607 08:07:51.442657 1 5 12 | B1->B0 | 3434 2726 | 1 1 | (1 1) (0 1)
7608 08:07:51.449254 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7609 08:07:51.452647 1 5 20 | B1->B0 | 2727 2727 | 0 0 | (1 0) (0 0)
7610 08:07:51.455657 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7611 08:07:51.462721 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 08:07:51.465398 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7613 08:07:51.469276 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 08:07:51.472264 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7615 08:07:51.479211 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7616 08:07:51.482544 1 6 16 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7617 08:07:51.485755 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7618 08:07:51.492181 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 08:07:51.495805 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 08:07:51.499200 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 08:07:51.505575 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 08:07:51.509094 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 08:07:51.512193 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 08:07:51.519148 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7625 08:07:51.522436 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7626 08:07:51.525320 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 08:07:51.532194 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 08:07:51.535203 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 08:07:51.538701 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 08:07:51.545902 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 08:07:51.548875 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 08:07:51.552253 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 08:07:51.558679 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 08:07:51.562028 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 08:07:51.565749 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 08:07:51.572183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 08:07:51.575448 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 08:07:51.579437 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 08:07:51.582134 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7640 08:07:51.589155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7641 08:07:51.592579 Total UI for P1: 0, mck2ui 16
7642 08:07:51.595496 best dqsien dly found for B0: ( 1, 9, 10)
7643 08:07:51.598842 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7644 08:07:51.602043 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 08:07:51.605370 Total UI for P1: 0, mck2ui 16
7646 08:07:51.608663 best dqsien dly found for B1: ( 1, 9, 18)
7647 08:07:51.611604 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7648 08:07:51.615330 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7649 08:07:51.618712
7650 08:07:51.621574 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7651 08:07:51.625334 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7652 08:07:51.628588 [Gating] SW calibration Done
7653 08:07:51.628671 ==
7654 08:07:51.631496 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 08:07:51.635075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 08:07:51.635160 ==
7657 08:07:51.638715 RX Vref Scan: 0
7658 08:07:51.638798
7659 08:07:51.638863 RX Vref 0 -> 0, step: 1
7660 08:07:51.638925
7661 08:07:51.641415 RX Delay 0 -> 252, step: 8
7662 08:07:51.645060 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7663 08:07:51.648045 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7664 08:07:51.655221 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7665 08:07:51.658042 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7666 08:07:51.661522 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7667 08:07:51.664596 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7668 08:07:51.671340 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7669 08:07:51.674575 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7670 08:07:51.677658 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7671 08:07:51.681247 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7672 08:07:51.684446 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7673 08:07:51.687885 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7674 08:07:51.694578 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7675 08:07:51.697924 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7676 08:07:51.701578 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7677 08:07:51.704742 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7678 08:07:51.704858 ==
7679 08:07:51.708220 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 08:07:51.714303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 08:07:51.714425 ==
7682 08:07:51.714543 DQS Delay:
7683 08:07:51.717417 DQS0 = 0, DQS1 = 0
7684 08:07:51.717539 DQM Delay:
7685 08:07:51.720690 DQM0 = 137, DQM1 = 129
7686 08:07:51.720802 DQ Delay:
7687 08:07:51.724250 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7688 08:07:51.727847 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7689 08:07:51.730731 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7690 08:07:51.734400 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7691 08:07:51.734474
7692 08:07:51.734541
7693 08:07:51.734600 ==
7694 08:07:51.737420 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 08:07:51.744323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 08:07:51.744445 ==
7697 08:07:51.744565
7698 08:07:51.744675
7699 08:07:51.744771 TX Vref Scan disable
7700 08:07:51.747493 == TX Byte 0 ==
7701 08:07:51.750858 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7702 08:07:51.754592 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7703 08:07:51.757536 == TX Byte 1 ==
7704 08:07:51.760961 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7705 08:07:51.764611 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7706 08:07:51.767823 ==
7707 08:07:51.771392 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 08:07:51.774139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 08:07:51.774239 ==
7710 08:07:51.787392
7711 08:07:51.790970 TX Vref early break, caculate TX vref
7712 08:07:51.794387 TX Vref=16, minBit 0, minWin=22, winSum=373
7713 08:07:51.797229 TX Vref=18, minBit 0, minWin=23, winSum=386
7714 08:07:51.800516 TX Vref=20, minBit 1, minWin=23, winSum=397
7715 08:07:51.803947 TX Vref=22, minBit 4, minWin=24, winSum=407
7716 08:07:51.807348 TX Vref=24, minBit 2, minWin=24, winSum=410
7717 08:07:51.813769 TX Vref=26, minBit 3, minWin=24, winSum=423
7718 08:07:51.817226 TX Vref=28, minBit 1, minWin=25, winSum=422
7719 08:07:51.820827 TX Vref=30, minBit 6, minWin=24, winSum=410
7720 08:07:51.824414 TX Vref=32, minBit 0, minWin=24, winSum=402
7721 08:07:51.826998 TX Vref=34, minBit 1, minWin=23, winSum=394
7722 08:07:51.833979 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
7723 08:07:51.834065
7724 08:07:51.837677 Final TX Range 0 Vref 28
7725 08:07:51.837785
7726 08:07:51.837860 ==
7727 08:07:51.840331 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 08:07:51.844181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 08:07:51.844313 ==
7730 08:07:51.844428
7731 08:07:51.844542
7732 08:07:51.847004 TX Vref Scan disable
7733 08:07:51.853619 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7734 08:07:51.853750 == TX Byte 0 ==
7735 08:07:51.857604 u2DelayCellOfst[0]=10 cells (3 PI)
7736 08:07:51.860693 u2DelayCellOfst[1]=13 cells (4 PI)
7737 08:07:51.863950 u2DelayCellOfst[2]=10 cells (3 PI)
7738 08:07:51.866964 u2DelayCellOfst[3]=10 cells (3 PI)
7739 08:07:51.870325 u2DelayCellOfst[4]=6 cells (2 PI)
7740 08:07:51.873995 u2DelayCellOfst[5]=0 cells (0 PI)
7741 08:07:51.877068 u2DelayCellOfst[6]=16 cells (5 PI)
7742 08:07:51.880311 u2DelayCellOfst[7]=13 cells (4 PI)
7743 08:07:51.883925 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7744 08:07:51.887101 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7745 08:07:51.890562 == TX Byte 1 ==
7746 08:07:51.890686 u2DelayCellOfst[8]=0 cells (0 PI)
7747 08:07:51.893665 u2DelayCellOfst[9]=3 cells (1 PI)
7748 08:07:51.897112 u2DelayCellOfst[10]=10 cells (3 PI)
7749 08:07:51.900636 u2DelayCellOfst[11]=6 cells (2 PI)
7750 08:07:51.903972 u2DelayCellOfst[12]=10 cells (3 PI)
7751 08:07:51.906754 u2DelayCellOfst[13]=10 cells (3 PI)
7752 08:07:51.909996 u2DelayCellOfst[14]=13 cells (4 PI)
7753 08:07:51.913445 u2DelayCellOfst[15]=10 cells (3 PI)
7754 08:07:51.916897 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7755 08:07:51.923371 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7756 08:07:51.923492 DramC Write-DBI on
7757 08:07:51.923609 ==
7758 08:07:51.926887 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 08:07:51.930052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 08:07:51.933581 ==
7761 08:07:51.933705
7762 08:07:51.933822
7763 08:07:51.933932 TX Vref Scan disable
7764 08:07:51.937197 == TX Byte 0 ==
7765 08:07:51.940972 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7766 08:07:51.943922 == TX Byte 1 ==
7767 08:07:51.947525 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7768 08:07:51.947612 DramC Write-DBI off
7769 08:07:51.950350
7770 08:07:51.950428 [DATLAT]
7771 08:07:51.950514 Freq=1600, CH0 RK0
7772 08:07:51.950592
7773 08:07:51.953860 DATLAT Default: 0xf
7774 08:07:51.953961 0, 0xFFFF, sum = 0
7775 08:07:51.956925 1, 0xFFFF, sum = 0
7776 08:07:51.957026 2, 0xFFFF, sum = 0
7777 08:07:51.960552 3, 0xFFFF, sum = 0
7778 08:07:51.963626 4, 0xFFFF, sum = 0
7779 08:07:51.963719 5, 0xFFFF, sum = 0
7780 08:07:51.967078 6, 0xFFFF, sum = 0
7781 08:07:51.967159 7, 0xFFFF, sum = 0
7782 08:07:51.970187 8, 0xFFFF, sum = 0
7783 08:07:51.970265 9, 0xFFFF, sum = 0
7784 08:07:51.973668 10, 0xFFFF, sum = 0
7785 08:07:51.973795 11, 0xFFFF, sum = 0
7786 08:07:51.977328 12, 0xFFFF, sum = 0
7787 08:07:51.977458 13, 0xFFFF, sum = 0
7788 08:07:51.980539 14, 0x0, sum = 1
7789 08:07:51.980664 15, 0x0, sum = 2
7790 08:07:51.983890 16, 0x0, sum = 3
7791 08:07:51.984015 17, 0x0, sum = 4
7792 08:07:51.987526 best_step = 15
7793 08:07:51.987656
7794 08:07:51.987768 ==
7795 08:07:51.990649 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 08:07:51.994289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 08:07:51.994415 ==
7798 08:07:51.994526 RX Vref Scan: 1
7799 08:07:51.994641
7800 08:07:51.996996 Set Vref Range= 24 -> 127
7801 08:07:51.997118
7802 08:07:52.000439 RX Vref 24 -> 127, step: 1
7803 08:07:52.000554
7804 08:07:52.003699 RX Delay 19 -> 252, step: 4
7805 08:07:52.003819
7806 08:07:52.007086 Set Vref, RX VrefLevel [Byte0]: 24
7807 08:07:52.010186 [Byte1]: 24
7808 08:07:52.010309
7809 08:07:52.013596 Set Vref, RX VrefLevel [Byte0]: 25
7810 08:07:52.016909 [Byte1]: 25
7811 08:07:52.017035
7812 08:07:52.020494 Set Vref, RX VrefLevel [Byte0]: 26
7813 08:07:52.023913 [Byte1]: 26
7814 08:07:52.027343
7815 08:07:52.027462 Set Vref, RX VrefLevel [Byte0]: 27
7816 08:07:52.030549 [Byte1]: 27
7817 08:07:52.035281
7818 08:07:52.035403 Set Vref, RX VrefLevel [Byte0]: 28
7819 08:07:52.038215 [Byte1]: 28
7820 08:07:52.042632
7821 08:07:52.042753 Set Vref, RX VrefLevel [Byte0]: 29
7822 08:07:52.045918 [Byte1]: 29
7823 08:07:52.050148
7824 08:07:52.050273 Set Vref, RX VrefLevel [Byte0]: 30
7825 08:07:52.056846 [Byte1]: 30
7826 08:07:52.056974
7827 08:07:52.059801 Set Vref, RX VrefLevel [Byte0]: 31
7828 08:07:52.063751 [Byte1]: 31
7829 08:07:52.063826
7830 08:07:52.066492 Set Vref, RX VrefLevel [Byte0]: 32
7831 08:07:52.069718 [Byte1]: 32
7832 08:07:52.069792
7833 08:07:52.072905 Set Vref, RX VrefLevel [Byte0]: 33
7834 08:07:52.076501 [Byte1]: 33
7835 08:07:52.080229
7836 08:07:52.080302 Set Vref, RX VrefLevel [Byte0]: 34
7837 08:07:52.083740 [Byte1]: 34
7838 08:07:52.088091
7839 08:07:52.088196 Set Vref, RX VrefLevel [Byte0]: 35
7840 08:07:52.090947 [Byte1]: 35
7841 08:07:52.095502
7842 08:07:52.095601 Set Vref, RX VrefLevel [Byte0]: 36
7843 08:07:52.098940 [Byte1]: 36
7844 08:07:52.103003
7845 08:07:52.103122 Set Vref, RX VrefLevel [Byte0]: 37
7846 08:07:52.106760 [Byte1]: 37
7847 08:07:52.110851
7848 08:07:52.110926 Set Vref, RX VrefLevel [Byte0]: 38
7849 08:07:52.114017 [Byte1]: 38
7850 08:07:52.118368
7851 08:07:52.118495 Set Vref, RX VrefLevel [Byte0]: 39
7852 08:07:52.121394 [Byte1]: 39
7853 08:07:52.126029
7854 08:07:52.126152 Set Vref, RX VrefLevel [Byte0]: 40
7855 08:07:52.129132 [Byte1]: 40
7856 08:07:52.133603
7857 08:07:52.133729 Set Vref, RX VrefLevel [Byte0]: 41
7858 08:07:52.136572 [Byte1]: 41
7859 08:07:52.141303
7860 08:07:52.141426 Set Vref, RX VrefLevel [Byte0]: 42
7861 08:07:52.144163 [Byte1]: 42
7862 08:07:52.148442
7863 08:07:52.148570 Set Vref, RX VrefLevel [Byte0]: 43
7864 08:07:52.151693 [Byte1]: 43
7865 08:07:52.156073
7866 08:07:52.156197 Set Vref, RX VrefLevel [Byte0]: 44
7867 08:07:52.159234 [Byte1]: 44
7868 08:07:52.164037
7869 08:07:52.164156 Set Vref, RX VrefLevel [Byte0]: 45
7870 08:07:52.166905 [Byte1]: 45
7871 08:07:52.171433
7872 08:07:52.171555 Set Vref, RX VrefLevel [Byte0]: 46
7873 08:07:52.175164 [Byte1]: 46
7874 08:07:52.178688
7875 08:07:52.178816 Set Vref, RX VrefLevel [Byte0]: 47
7876 08:07:52.182252 [Byte1]: 47
7877 08:07:52.186725
7878 08:07:52.186842 Set Vref, RX VrefLevel [Byte0]: 48
7879 08:07:52.189716 [Byte1]: 48
7880 08:07:52.194131
7881 08:07:52.194253 Set Vref, RX VrefLevel [Byte0]: 49
7882 08:07:52.197136 [Byte1]: 49
7883 08:07:52.201591
7884 08:07:52.201710 Set Vref, RX VrefLevel [Byte0]: 50
7885 08:07:52.205353 [Byte1]: 50
7886 08:07:52.209225
7887 08:07:52.209355 Set Vref, RX VrefLevel [Byte0]: 51
7888 08:07:52.212623 [Byte1]: 51
7889 08:07:52.217024
7890 08:07:52.217150 Set Vref, RX VrefLevel [Byte0]: 52
7891 08:07:52.220534 [Byte1]: 52
7892 08:07:52.224506
7893 08:07:52.224629 Set Vref, RX VrefLevel [Byte0]: 53
7894 08:07:52.227660 [Byte1]: 53
7895 08:07:52.232139
7896 08:07:52.232267 Set Vref, RX VrefLevel [Byte0]: 54
7897 08:07:52.235010 [Byte1]: 54
7898 08:07:52.239661
7899 08:07:52.239738 Set Vref, RX VrefLevel [Byte0]: 55
7900 08:07:52.242816 [Byte1]: 55
7901 08:07:52.247016
7902 08:07:52.247093 Set Vref, RX VrefLevel [Byte0]: 56
7903 08:07:52.250353 [Byte1]: 56
7904 08:07:52.254727
7905 08:07:52.254827 Set Vref, RX VrefLevel [Byte0]: 57
7906 08:07:52.257963 [Byte1]: 57
7907 08:07:52.262233
7908 08:07:52.262309 Set Vref, RX VrefLevel [Byte0]: 58
7909 08:07:52.265578 [Byte1]: 58
7910 08:07:52.269484
7911 08:07:52.269559 Set Vref, RX VrefLevel [Byte0]: 59
7912 08:07:52.273117 [Byte1]: 59
7913 08:07:52.277049
7914 08:07:52.277119 Set Vref, RX VrefLevel [Byte0]: 60
7915 08:07:52.280501 [Byte1]: 60
7916 08:07:52.284654
7917 08:07:52.284728 Set Vref, RX VrefLevel [Byte0]: 61
7918 08:07:52.288345 [Byte1]: 61
7919 08:07:52.292402
7920 08:07:52.292471 Set Vref, RX VrefLevel [Byte0]: 62
7921 08:07:52.295727 [Byte1]: 62
7922 08:07:52.300201
7923 08:07:52.300279 Set Vref, RX VrefLevel [Byte0]: 63
7924 08:07:52.303112 [Byte1]: 63
7925 08:07:52.307371
7926 08:07:52.307468 Set Vref, RX VrefLevel [Byte0]: 64
7927 08:07:52.310682 [Byte1]: 64
7928 08:07:52.315197
7929 08:07:52.315268 Set Vref, RX VrefLevel [Byte0]: 65
7930 08:07:52.318200 [Byte1]: 65
7931 08:07:52.323010
7932 08:07:52.323082 Set Vref, RX VrefLevel [Byte0]: 66
7933 08:07:52.325915 [Byte1]: 66
7934 08:07:52.330522
7935 08:07:52.330593 Set Vref, RX VrefLevel [Byte0]: 67
7936 08:07:52.333494 [Byte1]: 67
7937 08:07:52.337907
7938 08:07:52.337983 Set Vref, RX VrefLevel [Byte0]: 68
7939 08:07:52.341413 [Byte1]: 68
7940 08:07:52.345622
7941 08:07:52.345703 Set Vref, RX VrefLevel [Byte0]: 69
7942 08:07:52.348920 [Byte1]: 69
7943 08:07:52.353339
7944 08:07:52.353424 Set Vref, RX VrefLevel [Byte0]: 70
7945 08:07:52.356180 [Byte1]: 70
7946 08:07:52.360461
7947 08:07:52.360536 Set Vref, RX VrefLevel [Byte0]: 71
7948 08:07:52.363828 [Byte1]: 71
7949 08:07:52.368213
7950 08:07:52.368292 Set Vref, RX VrefLevel [Byte0]: 72
7951 08:07:52.371526 [Byte1]: 72
7952 08:07:52.375656
7953 08:07:52.375763 Set Vref, RX VrefLevel [Byte0]: 73
7954 08:07:52.379014 [Byte1]: 73
7955 08:07:52.383198
7956 08:07:52.383345 Set Vref, RX VrefLevel [Byte0]: 74
7957 08:07:52.386470 [Byte1]: 74
7958 08:07:52.390864
7959 08:07:52.390980 Set Vref, RX VrefLevel [Byte0]: 75
7960 08:07:52.394058 [Byte1]: 75
7961 08:07:52.398493
7962 08:07:52.398569 Final RX Vref Byte 0 = 59 to rank0
7963 08:07:52.401884 Final RX Vref Byte 1 = 59 to rank0
7964 08:07:52.405241 Final RX Vref Byte 0 = 59 to rank1
7965 08:07:52.408526 Final RX Vref Byte 1 = 59 to rank1==
7966 08:07:52.412011 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 08:07:52.418409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 08:07:52.418496 ==
7969 08:07:52.418560 DQS Delay:
7970 08:07:52.418623 DQS0 = 0, DQS1 = 0
7971 08:07:52.421906 DQM Delay:
7972 08:07:52.421987 DQM0 = 134, DQM1 = 127
7973 08:07:52.425429 DQ Delay:
7974 08:07:52.428661 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7975 08:07:52.431584 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7976 08:07:52.435276 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7977 08:07:52.438712 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7978 08:07:52.438789
7979 08:07:52.438884
7980 08:07:52.438942
7981 08:07:52.441598 [DramC_TX_OE_Calibration] TA2
7982 08:07:52.445080 Original DQ_B0 (3 6) =30, OEN = 27
7983 08:07:52.448515 Original DQ_B1 (3 6) =30, OEN = 27
7984 08:07:52.452036 24, 0x0, End_B0=24 End_B1=24
7985 08:07:52.452119 25, 0x0, End_B0=25 End_B1=25
7986 08:07:52.455401 26, 0x0, End_B0=26 End_B1=26
7987 08:07:52.458245 27, 0x0, End_B0=27 End_B1=27
7988 08:07:52.461580 28, 0x0, End_B0=28 End_B1=28
7989 08:07:52.461663 29, 0x0, End_B0=29 End_B1=29
7990 08:07:52.465173 30, 0x0, End_B0=30 End_B1=30
7991 08:07:52.468612 31, 0x4141, End_B0=30 End_B1=30
7992 08:07:52.471848 Byte0 end_step=30 best_step=27
7993 08:07:52.475392 Byte1 end_step=30 best_step=27
7994 08:07:52.478912 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 08:07:52.478990 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 08:07:52.479053
7997 08:07:52.479112
7998 08:07:52.488677 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7999 08:07:52.491971 CH0 RK0: MR19=303, MR18=2521
8000 08:07:52.498755 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
8001 08:07:52.498832
8002 08:07:52.502204 ----->DramcWriteLeveling(PI) begin...
8003 08:07:52.502283 ==
8004 08:07:52.505382 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 08:07:52.508404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 08:07:52.508476 ==
8007 08:07:52.512167 Write leveling (Byte 0): 38 => 38
8008 08:07:52.515154 Write leveling (Byte 1): 26 => 26
8009 08:07:52.518436 DramcWriteLeveling(PI) end<-----
8010 08:07:52.518512
8011 08:07:52.518575 ==
8012 08:07:52.521889 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 08:07:52.525056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 08:07:52.525130 ==
8015 08:07:52.528384 [Gating] SW mode calibration
8016 08:07:52.535242 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 08:07:52.541666 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 08:07:52.544841 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 08:07:52.548186 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 08:07:52.554820 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 08:07:52.558199 1 4 12 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8022 08:07:52.561762 1 4 16 | B1->B0 | 3232 3535 | 0 0 | (0 0) (0 0)
8023 08:07:52.568381 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8024 08:07:52.571833 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
8025 08:07:52.574780 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
8026 08:07:52.581591 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8027 08:07:52.584960 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 08:07:52.588063 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 08:07:52.594735 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8030 08:07:52.598128 1 5 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
8031 08:07:52.601509 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 08:07:52.608049 1 5 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8033 08:07:52.611331 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8034 08:07:52.614497 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 08:07:52.618173 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8036 08:07:52.625087 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8037 08:07:52.628305 1 6 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8038 08:07:52.631898 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
8039 08:07:52.638146 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 08:07:52.641399 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 08:07:52.645016 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 08:07:52.651418 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 08:07:52.654696 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 08:07:52.658457 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 08:07:52.664540 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8046 08:07:52.668319 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8047 08:07:52.671477 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 08:07:52.678173 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 08:07:52.681522 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 08:07:52.684641 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 08:07:52.691317 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 08:07:52.694859 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 08:07:52.698070 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 08:07:52.704915 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 08:07:52.707787 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 08:07:52.711212 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 08:07:52.718347 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 08:07:52.721061 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 08:07:52.724648 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 08:07:52.728056 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 08:07:52.734471 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 08:07:52.737997 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8063 08:07:52.741348 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 08:07:52.744515 Total UI for P1: 0, mck2ui 16
8065 08:07:52.748150 best dqsien dly found for B0: ( 1, 9, 12)
8066 08:07:52.751389 Total UI for P1: 0, mck2ui 16
8067 08:07:52.754500 best dqsien dly found for B1: ( 1, 9, 16)
8068 08:07:52.758286 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8069 08:07:52.761639 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8070 08:07:52.761722
8071 08:07:52.768153 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8072 08:07:52.771441 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8073 08:07:52.774256 [Gating] SW calibration Done
8074 08:07:52.774333 ==
8075 08:07:52.777839 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 08:07:52.781603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 08:07:52.781677 ==
8078 08:07:52.781743 RX Vref Scan: 0
8079 08:07:52.781804
8080 08:07:52.784582 RX Vref 0 -> 0, step: 1
8081 08:07:52.784656
8082 08:07:52.788041 RX Delay 0 -> 252, step: 8
8083 08:07:52.791523 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8084 08:07:52.794429 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8085 08:07:52.798228 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8086 08:07:52.804444 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8087 08:07:52.807728 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8088 08:07:52.811423 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8089 08:07:52.814498 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8090 08:07:52.817899 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8091 08:07:52.824491 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8092 08:07:52.827968 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8093 08:07:52.830996 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8094 08:07:52.834550 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8095 08:07:52.838017 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8096 08:07:52.844479 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8097 08:07:52.848170 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8098 08:07:52.851188 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8099 08:07:52.851264 ==
8100 08:07:52.854298 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 08:07:52.857644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 08:07:52.861005 ==
8103 08:07:52.861084 DQS Delay:
8104 08:07:52.861147 DQS0 = 0, DQS1 = 0
8105 08:07:52.864648 DQM Delay:
8106 08:07:52.864716 DQM0 = 137, DQM1 = 128
8107 08:07:52.867685 DQ Delay:
8108 08:07:52.870921 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
8109 08:07:52.874200 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8110 08:07:52.877597 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8111 08:07:52.881076 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8112 08:07:52.881153
8113 08:07:52.881216
8114 08:07:52.881279 ==
8115 08:07:52.884277 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 08:07:52.887382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 08:07:52.887455 ==
8118 08:07:52.890849
8119 08:07:52.890921
8120 08:07:52.890985 TX Vref Scan disable
8121 08:07:52.894434 == TX Byte 0 ==
8122 08:07:52.897376 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8123 08:07:52.900584 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8124 08:07:52.904277 == TX Byte 1 ==
8125 08:07:52.907138 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8126 08:07:52.911057 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8127 08:07:52.913748 ==
8128 08:07:52.913833 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 08:07:52.920546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 08:07:52.920630 ==
8131 08:07:52.933761
8132 08:07:52.937066 TX Vref early break, caculate TX vref
8133 08:07:52.940589 TX Vref=16, minBit 1, minWin=23, winSum=388
8134 08:07:52.943939 TX Vref=18, minBit 4, minWin=23, winSum=396
8135 08:07:52.947450 TX Vref=20, minBit 3, minWin=24, winSum=407
8136 08:07:52.950497 TX Vref=22, minBit 0, minWin=25, winSum=411
8137 08:07:52.953988 TX Vref=24, minBit 3, minWin=24, winSum=421
8138 08:07:52.960581 TX Vref=26, minBit 1, minWin=25, winSum=426
8139 08:07:52.964128 TX Vref=28, minBit 4, minWin=25, winSum=428
8140 08:07:52.967055 TX Vref=30, minBit 3, minWin=25, winSum=417
8141 08:07:52.970820 TX Vref=32, minBit 4, minWin=24, winSum=408
8142 08:07:52.974210 TX Vref=34, minBit 1, minWin=24, winSum=404
8143 08:07:52.980520 [TxChooseVref] Worse bit 4, Min win 25, Win sum 428, Final Vref 28
8144 08:07:52.980627
8145 08:07:52.984206 Final TX Range 0 Vref 28
8146 08:07:52.984285
8147 08:07:52.984355 ==
8148 08:07:52.987634 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 08:07:52.990351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 08:07:52.990428 ==
8151 08:07:52.990491
8152 08:07:52.990555
8153 08:07:52.993940 TX Vref Scan disable
8154 08:07:53.000295 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8155 08:07:53.000376 == TX Byte 0 ==
8156 08:07:53.003827 u2DelayCellOfst[0]=13 cells (4 PI)
8157 08:07:53.007220 u2DelayCellOfst[1]=16 cells (5 PI)
8158 08:07:53.010824 u2DelayCellOfst[2]=10 cells (3 PI)
8159 08:07:53.013867 u2DelayCellOfst[3]=10 cells (3 PI)
8160 08:07:53.016921 u2DelayCellOfst[4]=10 cells (3 PI)
8161 08:07:53.020542 u2DelayCellOfst[5]=0 cells (0 PI)
8162 08:07:53.024242 u2DelayCellOfst[6]=16 cells (5 PI)
8163 08:07:53.024321 u2DelayCellOfst[7]=16 cells (5 PI)
8164 08:07:53.030328 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8165 08:07:53.033928 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8166 08:07:53.034004 == TX Byte 1 ==
8167 08:07:53.037236 u2DelayCellOfst[8]=3 cells (1 PI)
8168 08:07:53.040645 u2DelayCellOfst[9]=0 cells (0 PI)
8169 08:07:53.044137 u2DelayCellOfst[10]=6 cells (2 PI)
8170 08:07:53.047465 u2DelayCellOfst[11]=3 cells (1 PI)
8171 08:07:53.050432 u2DelayCellOfst[12]=13 cells (4 PI)
8172 08:07:53.053543 u2DelayCellOfst[13]=10 cells (3 PI)
8173 08:07:53.057280 u2DelayCellOfst[14]=13 cells (4 PI)
8174 08:07:53.060620 u2DelayCellOfst[15]=13 cells (4 PI)
8175 08:07:53.063653 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8176 08:07:53.070272 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8177 08:07:53.070411 DramC Write-DBI on
8178 08:07:53.070529 ==
8179 08:07:53.073973 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 08:07:53.077592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 08:07:53.077724 ==
8182 08:07:53.080277
8183 08:07:53.080406
8184 08:07:53.080520 TX Vref Scan disable
8185 08:07:53.083778 == TX Byte 0 ==
8186 08:07:53.087480 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
8187 08:07:53.090708 == TX Byte 1 ==
8188 08:07:53.093771 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8189 08:07:53.097201 DramC Write-DBI off
8190 08:07:53.097330
8191 08:07:53.097447 [DATLAT]
8192 08:07:53.097562 Freq=1600, CH0 RK1
8193 08:07:53.097675
8194 08:07:53.100349 DATLAT Default: 0xf
8195 08:07:53.100477 0, 0xFFFF, sum = 0
8196 08:07:53.103414 1, 0xFFFF, sum = 0
8197 08:07:53.106940 2, 0xFFFF, sum = 0
8198 08:07:53.107069 3, 0xFFFF, sum = 0
8199 08:07:53.110476 4, 0xFFFF, sum = 0
8200 08:07:53.110599 5, 0xFFFF, sum = 0
8201 08:07:53.113436 6, 0xFFFF, sum = 0
8202 08:07:53.113571 7, 0xFFFF, sum = 0
8203 08:07:53.116910 8, 0xFFFF, sum = 0
8204 08:07:53.117037 9, 0xFFFF, sum = 0
8205 08:07:53.119951 10, 0xFFFF, sum = 0
8206 08:07:53.120080 11, 0xFFFF, sum = 0
8207 08:07:53.123680 12, 0xFFFF, sum = 0
8208 08:07:53.123763 13, 0xFFFF, sum = 0
8209 08:07:53.127270 14, 0x0, sum = 1
8210 08:07:53.127372 15, 0x0, sum = 2
8211 08:07:53.130531 16, 0x0, sum = 3
8212 08:07:53.130641 17, 0x0, sum = 4
8213 08:07:53.133737 best_step = 15
8214 08:07:53.133811
8215 08:07:53.133873 ==
8216 08:07:53.136643 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 08:07:53.139963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 08:07:53.140036 ==
8219 08:07:53.143525 RX Vref Scan: 0
8220 08:07:53.143621
8221 08:07:53.143709 RX Vref 0 -> 0, step: 1
8222 08:07:53.143773
8223 08:07:53.147160 RX Delay 19 -> 252, step: 4
8224 08:07:53.150219 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8225 08:07:53.156950 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8226 08:07:53.160180 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8227 08:07:53.163345 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8228 08:07:53.166511 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8229 08:07:53.170213 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8230 08:07:53.177115 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8231 08:07:53.180047 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8232 08:07:53.183362 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8233 08:07:53.186847 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8234 08:07:53.190311 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8235 08:07:53.197008 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8236 08:07:53.199984 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8237 08:07:53.203467 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8238 08:07:53.206383 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8239 08:07:53.210161 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8240 08:07:53.213081 ==
8241 08:07:53.216342 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 08:07:53.219861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 08:07:53.219944 ==
8244 08:07:53.220010 DQS Delay:
8245 08:07:53.222829 DQS0 = 0, DQS1 = 0
8246 08:07:53.222902 DQM Delay:
8247 08:07:53.226448 DQM0 = 134, DQM1 = 127
8248 08:07:53.226518 DQ Delay:
8249 08:07:53.229440 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8250 08:07:53.233191 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8251 08:07:53.236689 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8252 08:07:53.239609 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8253 08:07:53.239711
8254 08:07:53.239776
8255 08:07:53.239843
8256 08:07:53.242647 [DramC_TX_OE_Calibration] TA2
8257 08:07:53.246134 Original DQ_B0 (3 6) =30, OEN = 27
8258 08:07:53.249629 Original DQ_B1 (3 6) =30, OEN = 27
8259 08:07:53.252600 24, 0x0, End_B0=24 End_B1=24
8260 08:07:53.255777 25, 0x0, End_B0=25 End_B1=25
8261 08:07:53.255860 26, 0x0, End_B0=26 End_B1=26
8262 08:07:53.259440 27, 0x0, End_B0=27 End_B1=27
8263 08:07:53.263078 28, 0x0, End_B0=28 End_B1=28
8264 08:07:53.266550 29, 0x0, End_B0=29 End_B1=29
8265 08:07:53.269537 30, 0x0, End_B0=30 End_B1=30
8266 08:07:53.269615 31, 0x4141, End_B0=30 End_B1=30
8267 08:07:53.272811 Byte0 end_step=30 best_step=27
8268 08:07:53.275951 Byte1 end_step=30 best_step=27
8269 08:07:53.279606 Byte0 TX OE(2T, 0.5T) = (3, 3)
8270 08:07:53.282556 Byte1 TX OE(2T, 0.5T) = (3, 3)
8271 08:07:53.282637
8272 08:07:53.282702
8273 08:07:53.289463 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8274 08:07:53.293148 CH0 RK1: MR19=303, MR18=2008
8275 08:07:53.299721 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8276 08:07:53.302721 [RxdqsGatingPostProcess] freq 1600
8277 08:07:53.309280 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8278 08:07:53.309390 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 08:07:53.312698 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 08:07:53.315906 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 08:07:53.319516 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 08:07:53.322648 best DQS0 dly(2T, 0.5T) = (1, 1)
8283 08:07:53.325893 best DQS1 dly(2T, 0.5T) = (1, 1)
8284 08:07:53.329550 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8285 08:07:53.332581 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8286 08:07:53.336291 Pre-setting of DQS Precalculation
8287 08:07:53.339086 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8288 08:07:53.339170 ==
8289 08:07:53.342739 Dram Type= 6, Freq= 0, CH_1, rank 0
8290 08:07:53.349357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 08:07:53.349440 ==
8292 08:07:53.352925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8293 08:07:53.359428 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8294 08:07:53.362328 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8295 08:07:53.369305 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8296 08:07:53.376807 [CA 0] Center 42 (13~71) winsize 59
8297 08:07:53.380130 [CA 1] Center 41 (12~71) winsize 60
8298 08:07:53.383414 [CA 2] Center 38 (9~68) winsize 60
8299 08:07:53.386899 [CA 3] Center 37 (9~66) winsize 58
8300 08:07:53.390414 [CA 4] Center 39 (10~68) winsize 59
8301 08:07:53.393514 [CA 5] Center 37 (8~66) winsize 59
8302 08:07:53.393624
8303 08:07:53.396783 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8304 08:07:53.396869
8305 08:07:53.400001 [CATrainingPosCal] consider 1 rank data
8306 08:07:53.403145 u2DelayCellTimex100 = 290/100 ps
8307 08:07:53.406644 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8308 08:07:53.413095 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8309 08:07:53.416762 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8310 08:07:53.419775 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8311 08:07:53.423277 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8312 08:07:53.426852 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8313 08:07:53.426938
8314 08:07:53.430025 CA PerBit enable=1, Macro0, CA PI delay=37
8315 08:07:53.430135
8316 08:07:53.433626 [CBTSetCACLKResult] CA Dly = 37
8317 08:07:53.436602 CS Dly: 11 (0~42)
8318 08:07:53.440183 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8319 08:07:53.443074 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8320 08:07:53.443176 ==
8321 08:07:53.446587 Dram Type= 6, Freq= 0, CH_1, rank 1
8322 08:07:53.450224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 08:07:53.453189 ==
8324 08:07:53.456615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 08:07:53.459725 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 08:07:53.466788 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 08:07:53.469710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 08:07:53.480101 [CA 0] Center 42 (12~72) winsize 61
8329 08:07:53.483338 [CA 1] Center 42 (13~72) winsize 60
8330 08:07:53.486734 [CA 2] Center 38 (9~68) winsize 60
8331 08:07:53.489875 [CA 3] Center 38 (9~68) winsize 60
8332 08:07:53.493632 [CA 4] Center 38 (8~69) winsize 62
8333 08:07:53.496877 [CA 5] Center 37 (8~67) winsize 60
8334 08:07:53.496987
8335 08:07:53.499849 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8336 08:07:53.499956
8337 08:07:53.503167 [CATrainingPosCal] consider 2 rank data
8338 08:07:53.506678 u2DelayCellTimex100 = 290/100 ps
8339 08:07:53.513377 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8340 08:07:53.516442 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8341 08:07:53.519765 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8342 08:07:53.522834 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8343 08:07:53.526178 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8344 08:07:53.529444 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8345 08:07:53.529518
8346 08:07:53.533253 CA PerBit enable=1, Macro0, CA PI delay=37
8347 08:07:53.533330
8348 08:07:53.536283 [CBTSetCACLKResult] CA Dly = 37
8349 08:07:53.539846 CS Dly: 12 (0~45)
8350 08:07:53.543391 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 08:07:53.546031 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 08:07:53.546117
8353 08:07:53.549650 ----->DramcWriteLeveling(PI) begin...
8354 08:07:53.549723 ==
8355 08:07:53.552640 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 08:07:53.559123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 08:07:53.559209 ==
8358 08:07:53.562738 Write leveling (Byte 0): 25 => 25
8359 08:07:53.566317 Write leveling (Byte 1): 28 => 28
8360 08:07:53.566398 DramcWriteLeveling(PI) end<-----
8361 08:07:53.566463
8362 08:07:53.569277 ==
8363 08:07:53.572630 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 08:07:53.576128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 08:07:53.576210 ==
8366 08:07:53.579187 [Gating] SW mode calibration
8367 08:07:53.585760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8368 08:07:53.589153 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8369 08:07:53.596049 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 08:07:53.599083 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 08:07:53.602846 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8372 08:07:53.608902 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 08:07:53.612528 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 08:07:53.615918 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 08:07:53.622739 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 08:07:53.625760 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 08:07:53.628886 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 08:07:53.635924 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8379 08:07:53.639130 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
8380 08:07:53.642461 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8381 08:07:53.648919 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 08:07:53.652429 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 08:07:53.655650 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 08:07:53.662603 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 08:07:53.665408 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 08:07:53.668920 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 08:07:53.675634 1 6 8 | B1->B0 | 2525 3b3b | 0 1 | (0 0) (0 0)
8388 08:07:53.679201 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8389 08:07:53.682030 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 08:07:53.685724 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 08:07:53.692137 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 08:07:53.695591 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 08:07:53.699110 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 08:07:53.705667 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 08:07:53.708864 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 08:07:53.712050 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 08:07:53.718738 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8398 08:07:53.722174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 08:07:53.725643 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 08:07:53.731890 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 08:07:53.735138 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 08:07:53.738666 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 08:07:53.745066 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 08:07:53.748511 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 08:07:53.751833 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 08:07:53.758356 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 08:07:53.761765 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 08:07:53.764972 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 08:07:53.771589 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 08:07:53.775268 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 08:07:53.778139 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 08:07:53.784836 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8413 08:07:53.788583 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 08:07:53.791781 Total UI for P1: 0, mck2ui 16
8415 08:07:53.795505 best dqsien dly found for B0: ( 1, 9, 10)
8416 08:07:53.798205 Total UI for P1: 0, mck2ui 16
8417 08:07:53.801598 best dqsien dly found for B1: ( 1, 9, 10)
8418 08:07:53.805082 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8419 08:07:53.808664 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8420 08:07:53.808749
8421 08:07:53.811505 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8422 08:07:53.815072 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8423 08:07:53.818486 [Gating] SW calibration Done
8424 08:07:53.818561 ==
8425 08:07:53.821861 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 08:07:53.825310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 08:07:53.828536 ==
8428 08:07:53.828618 RX Vref Scan: 0
8429 08:07:53.828682
8430 08:07:53.831895 RX Vref 0 -> 0, step: 1
8431 08:07:53.831965
8432 08:07:53.832025 RX Delay 0 -> 252, step: 8
8433 08:07:53.838566 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8434 08:07:53.841783 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8435 08:07:53.845176 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8436 08:07:53.848766 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8437 08:07:53.851993 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8438 08:07:53.858396 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8439 08:07:53.861586 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8440 08:07:53.864874 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8441 08:07:53.868569 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8442 08:07:53.871689 iDelay=200, Bit 9, Center 127 (80 ~ 175) 96
8443 08:07:53.874940 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8444 08:07:53.881738 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8445 08:07:53.885413 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8446 08:07:53.888509 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8447 08:07:53.891873 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8448 08:07:53.898280 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8449 08:07:53.898368 ==
8450 08:07:53.901868 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 08:07:53.904962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 08:07:53.905039 ==
8453 08:07:53.905110 DQS Delay:
8454 08:07:53.908200 DQS0 = 0, DQS1 = 0
8455 08:07:53.908276 DQM Delay:
8456 08:07:53.911577 DQM0 = 137, DQM1 = 133
8457 08:07:53.911688 DQ Delay:
8458 08:07:53.915307 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8459 08:07:53.918098 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8460 08:07:53.921437 DQ8 =119, DQ9 =127, DQ10 =131, DQ11 =127
8461 08:07:53.924977 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8462 08:07:53.925061
8463 08:07:53.925126
8464 08:07:53.925186 ==
8465 08:07:53.928513 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 08:07:53.935091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 08:07:53.935168 ==
8468 08:07:53.935232
8469 08:07:53.935291
8470 08:07:53.935368 TX Vref Scan disable
8471 08:07:53.938661 == TX Byte 0 ==
8472 08:07:53.941951 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8473 08:07:53.948886 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8474 08:07:53.948963 == TX Byte 1 ==
8475 08:07:53.952004 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8476 08:07:53.955090 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8477 08:07:53.958736 ==
8478 08:07:53.961765 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 08:07:53.965076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 08:07:53.965147 ==
8481 08:07:53.978375
8482 08:07:53.981818 TX Vref early break, caculate TX vref
8483 08:07:53.985548 TX Vref=16, minBit 0, minWin=23, winSum=380
8484 08:07:53.988783 TX Vref=18, minBit 1, minWin=23, winSum=388
8485 08:07:53.991838 TX Vref=20, minBit 9, minWin=23, winSum=395
8486 08:07:53.995809 TX Vref=22, minBit 6, minWin=24, winSum=408
8487 08:07:53.998369 TX Vref=24, minBit 0, minWin=25, winSum=416
8488 08:07:54.005479 TX Vref=26, minBit 0, minWin=25, winSum=420
8489 08:07:54.008353 TX Vref=28, minBit 2, minWin=25, winSum=424
8490 08:07:54.011866 TX Vref=30, minBit 2, minWin=25, winSum=418
8491 08:07:54.015404 TX Vref=32, minBit 10, minWin=24, winSum=413
8492 08:07:54.018065 TX Vref=34, minBit 0, minWin=24, winSum=404
8493 08:07:54.021948 TX Vref=36, minBit 0, minWin=23, winSum=389
8494 08:07:54.028588 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 28
8495 08:07:54.028665
8496 08:07:54.031382 Final TX Range 0 Vref 28
8497 08:07:54.031468
8498 08:07:54.031529 ==
8499 08:07:54.035233 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 08:07:54.038029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 08:07:54.038110 ==
8502 08:07:54.038174
8503 08:07:54.041526
8504 08:07:54.041605 TX Vref Scan disable
8505 08:07:54.048361 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8506 08:07:54.048456 == TX Byte 0 ==
8507 08:07:54.051360 u2DelayCellOfst[0]=16 cells (5 PI)
8508 08:07:54.054789 u2DelayCellOfst[1]=10 cells (3 PI)
8509 08:07:54.058270 u2DelayCellOfst[2]=0 cells (0 PI)
8510 08:07:54.061599 u2DelayCellOfst[3]=6 cells (2 PI)
8511 08:07:54.064959 u2DelayCellOfst[4]=6 cells (2 PI)
8512 08:07:54.068211 u2DelayCellOfst[5]=16 cells (5 PI)
8513 08:07:54.071315 u2DelayCellOfst[6]=16 cells (5 PI)
8514 08:07:54.074565 u2DelayCellOfst[7]=6 cells (2 PI)
8515 08:07:54.077930 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8516 08:07:54.081645 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8517 08:07:54.084833 == TX Byte 1 ==
8518 08:07:54.087871 u2DelayCellOfst[8]=0 cells (0 PI)
8519 08:07:54.091214 u2DelayCellOfst[9]=6 cells (2 PI)
8520 08:07:54.091293 u2DelayCellOfst[10]=13 cells (4 PI)
8521 08:07:54.094882 u2DelayCellOfst[11]=3 cells (1 PI)
8522 08:07:54.097897 u2DelayCellOfst[12]=16 cells (5 PI)
8523 08:07:54.101464 u2DelayCellOfst[13]=16 cells (5 PI)
8524 08:07:54.104778 u2DelayCellOfst[14]=20 cells (6 PI)
8525 08:07:54.107590 u2DelayCellOfst[15]=16 cells (5 PI)
8526 08:07:54.114280 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8527 08:07:54.117914 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8528 08:07:54.117994 DramC Write-DBI on
8529 08:07:54.118057 ==
8530 08:07:54.120805 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 08:07:54.127734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 08:07:54.127815 ==
8533 08:07:54.127878
8534 08:07:54.127936
8535 08:07:54.130888 TX Vref Scan disable
8536 08:07:54.130995 == TX Byte 0 ==
8537 08:07:54.137669 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8538 08:07:54.137749 == TX Byte 1 ==
8539 08:07:54.141029 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8540 08:07:54.144308 DramC Write-DBI off
8541 08:07:54.144386
8542 08:07:54.144449 [DATLAT]
8543 08:07:54.147434 Freq=1600, CH1 RK0
8544 08:07:54.147538
8545 08:07:54.147602 DATLAT Default: 0xf
8546 08:07:54.150894 0, 0xFFFF, sum = 0
8547 08:07:54.150974 1, 0xFFFF, sum = 0
8548 08:07:54.154171 2, 0xFFFF, sum = 0
8549 08:07:54.154251 3, 0xFFFF, sum = 0
8550 08:07:54.157488 4, 0xFFFF, sum = 0
8551 08:07:54.157571 5, 0xFFFF, sum = 0
8552 08:07:54.161054 6, 0xFFFF, sum = 0
8553 08:07:54.161134 7, 0xFFFF, sum = 0
8554 08:07:54.163938 8, 0xFFFF, sum = 0
8555 08:07:54.164018 9, 0xFFFF, sum = 0
8556 08:07:54.167661 10, 0xFFFF, sum = 0
8557 08:07:54.170814 11, 0xFFFF, sum = 0
8558 08:07:54.170888 12, 0xFFFF, sum = 0
8559 08:07:54.173854 13, 0xFFFF, sum = 0
8560 08:07:54.173933 14, 0x0, sum = 1
8561 08:07:54.177392 15, 0x0, sum = 2
8562 08:07:54.177481 16, 0x0, sum = 3
8563 08:07:54.177550 17, 0x0, sum = 4
8564 08:07:54.180385 best_step = 15
8565 08:07:54.180486
8566 08:07:54.180549 ==
8567 08:07:54.184106 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 08:07:54.187096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 08:07:54.187176 ==
8570 08:07:54.190405 RX Vref Scan: 1
8571 08:07:54.190515
8572 08:07:54.194020 Set Vref Range= 24 -> 127
8573 08:07:54.194119
8574 08:07:54.194224 RX Vref 24 -> 127, step: 1
8575 08:07:54.194311
8576 08:07:54.197182 RX Delay 27 -> 252, step: 4
8577 08:07:54.197282
8578 08:07:54.200927 Set Vref, RX VrefLevel [Byte0]: 24
8579 08:07:54.203745 [Byte1]: 24
8580 08:07:54.203854
8581 08:07:54.207288 Set Vref, RX VrefLevel [Byte0]: 25
8582 08:07:54.210642 [Byte1]: 25
8583 08:07:54.214362
8584 08:07:54.214451 Set Vref, RX VrefLevel [Byte0]: 26
8585 08:07:54.218044 [Byte1]: 26
8586 08:07:54.222155
8587 08:07:54.222232 Set Vref, RX VrefLevel [Byte0]: 27
8588 08:07:54.225573 [Byte1]: 27
8589 08:07:54.229592
8590 08:07:54.229672 Set Vref, RX VrefLevel [Byte0]: 28
8591 08:07:54.232905 [Byte1]: 28
8592 08:07:54.237335
8593 08:07:54.237407 Set Vref, RX VrefLevel [Byte0]: 29
8594 08:07:54.240552 [Byte1]: 29
8595 08:07:54.244635
8596 08:07:54.244740 Set Vref, RX VrefLevel [Byte0]: 30
8597 08:07:54.247757 [Byte1]: 30
8598 08:07:54.252342
8599 08:07:54.252423 Set Vref, RX VrefLevel [Byte0]: 31
8600 08:07:54.255277 [Byte1]: 31
8601 08:07:54.259575
8602 08:07:54.259698 Set Vref, RX VrefLevel [Byte0]: 32
8603 08:07:54.263039 [Byte1]: 32
8604 08:07:54.267078
8605 08:07:54.267153 Set Vref, RX VrefLevel [Byte0]: 33
8606 08:07:54.270595 [Byte1]: 33
8607 08:07:54.274709
8608 08:07:54.274784 Set Vref, RX VrefLevel [Byte0]: 34
8609 08:07:54.277958 [Byte1]: 34
8610 08:07:54.282667
8611 08:07:54.282750 Set Vref, RX VrefLevel [Byte0]: 35
8612 08:07:54.285610 [Byte1]: 35
8613 08:07:54.289823
8614 08:07:54.289970 Set Vref, RX VrefLevel [Byte0]: 36
8615 08:07:54.293184 [Byte1]: 36
8616 08:07:54.297433
8617 08:07:54.297545 Set Vref, RX VrefLevel [Byte0]: 37
8618 08:07:54.300493 [Byte1]: 37
8619 08:07:54.305075
8620 08:07:54.305163 Set Vref, RX VrefLevel [Byte0]: 38
8621 08:07:54.308028 [Byte1]: 38
8622 08:07:54.312163
8623 08:07:54.312237 Set Vref, RX VrefLevel [Byte0]: 39
8624 08:07:54.315533 [Byte1]: 39
8625 08:07:54.319603
8626 08:07:54.319709 Set Vref, RX VrefLevel [Byte0]: 40
8627 08:07:54.323261 [Byte1]: 40
8628 08:07:54.327481
8629 08:07:54.330535 Set Vref, RX VrefLevel [Byte0]: 41
8630 08:07:54.330616 [Byte1]: 41
8631 08:07:54.335024
8632 08:07:54.335104 Set Vref, RX VrefLevel [Byte0]: 42
8633 08:07:54.338142 [Byte1]: 42
8634 08:07:54.342375
8635 08:07:54.342450 Set Vref, RX VrefLevel [Byte0]: 43
8636 08:07:54.345635 [Byte1]: 43
8637 08:07:54.349851
8638 08:07:54.349952 Set Vref, RX VrefLevel [Byte0]: 44
8639 08:07:54.353446 [Byte1]: 44
8640 08:07:54.357654
8641 08:07:54.357774 Set Vref, RX VrefLevel [Byte0]: 45
8642 08:07:54.360689 [Byte1]: 45
8643 08:07:54.365500
8644 08:07:54.365579 Set Vref, RX VrefLevel [Byte0]: 46
8645 08:07:54.368360 [Byte1]: 46
8646 08:07:54.372463
8647 08:07:54.372542 Set Vref, RX VrefLevel [Byte0]: 47
8648 08:07:54.376110 [Byte1]: 47
8649 08:07:54.380301
8650 08:07:54.380380 Set Vref, RX VrefLevel [Byte0]: 48
8651 08:07:54.383556 [Byte1]: 48
8652 08:07:54.387806
8653 08:07:54.387901 Set Vref, RX VrefLevel [Byte0]: 49
8654 08:07:54.390680 [Byte1]: 49
8655 08:07:54.395116
8656 08:07:54.395195 Set Vref, RX VrefLevel [Byte0]: 50
8657 08:07:54.398269 [Byte1]: 50
8658 08:07:54.402783
8659 08:07:54.402862 Set Vref, RX VrefLevel [Byte0]: 51
8660 08:07:54.406126 [Byte1]: 51
8661 08:07:54.410243
8662 08:07:54.410341 Set Vref, RX VrefLevel [Byte0]: 52
8663 08:07:54.413792 [Byte1]: 52
8664 08:07:54.418142
8665 08:07:54.418222 Set Vref, RX VrefLevel [Byte0]: 53
8666 08:07:54.420963 [Byte1]: 53
8667 08:07:54.425757
8668 08:07:54.425837 Set Vref, RX VrefLevel [Byte0]: 54
8669 08:07:54.428452 [Byte1]: 54
8670 08:07:54.432769
8671 08:07:54.432848 Set Vref, RX VrefLevel [Byte0]: 55
8672 08:07:54.436142 [Byte1]: 55
8673 08:07:54.440360
8674 08:07:54.440439 Set Vref, RX VrefLevel [Byte0]: 56
8675 08:07:54.443801 [Byte1]: 56
8676 08:07:54.447952
8677 08:07:54.448031 Set Vref, RX VrefLevel [Byte0]: 57
8678 08:07:54.451376 [Byte1]: 57
8679 08:07:54.455824
8680 08:07:54.455954 Set Vref, RX VrefLevel [Byte0]: 58
8681 08:07:54.458692 [Byte1]: 58
8682 08:07:54.462884
8683 08:07:54.462963 Set Vref, RX VrefLevel [Byte0]: 59
8684 08:07:54.466380 [Byte1]: 59
8685 08:07:54.470805
8686 08:07:54.470884 Set Vref, RX VrefLevel [Byte0]: 60
8687 08:07:54.474257 [Byte1]: 60
8688 08:07:54.478185
8689 08:07:54.478264 Set Vref, RX VrefLevel [Byte0]: 61
8690 08:07:54.481732 [Byte1]: 61
8691 08:07:54.485770
8692 08:07:54.485850 Set Vref, RX VrefLevel [Byte0]: 62
8693 08:07:54.488818 [Byte1]: 62
8694 08:07:54.493139
8695 08:07:54.493218 Set Vref, RX VrefLevel [Byte0]: 63
8696 08:07:54.496656 [Byte1]: 63
8697 08:07:54.500598
8698 08:07:54.500677 Set Vref, RX VrefLevel [Byte0]: 64
8699 08:07:54.504066 [Byte1]: 64
8700 08:07:54.508459
8701 08:07:54.508538 Set Vref, RX VrefLevel [Byte0]: 65
8702 08:07:54.511448 [Byte1]: 65
8703 08:07:54.515631
8704 08:07:54.515756 Set Vref, RX VrefLevel [Byte0]: 66
8705 08:07:54.519236 [Byte1]: 66
8706 08:07:54.523570
8707 08:07:54.523715 Set Vref, RX VrefLevel [Byte0]: 67
8708 08:07:54.526610 [Byte1]: 67
8709 08:07:54.530602
8710 08:07:54.530707 Set Vref, RX VrefLevel [Byte0]: 68
8711 08:07:54.534181 [Byte1]: 68
8712 08:07:54.538423
8713 08:07:54.538504 Set Vref, RX VrefLevel [Byte0]: 69
8714 08:07:54.541645 [Byte1]: 69
8715 08:07:54.546018
8716 08:07:54.546100 Set Vref, RX VrefLevel [Byte0]: 70
8717 08:07:54.549734 [Byte1]: 70
8718 08:07:54.553636
8719 08:07:54.553716 Set Vref, RX VrefLevel [Byte0]: 71
8720 08:07:54.556953 [Byte1]: 71
8721 08:07:54.561232
8722 08:07:54.561306 Set Vref, RX VrefLevel [Byte0]: 72
8723 08:07:54.564268 [Byte1]: 72
8724 08:07:54.568460
8725 08:07:54.568534 Set Vref, RX VrefLevel [Byte0]: 73
8726 08:07:54.571557 [Byte1]: 73
8727 08:07:54.576104
8728 08:07:54.576242 Set Vref, RX VrefLevel [Byte0]: 74
8729 08:07:54.579154 [Byte1]: 74
8730 08:07:54.583428
8731 08:07:54.583531 Set Vref, RX VrefLevel [Byte0]: 75
8732 08:07:54.586661 [Byte1]: 75
8733 08:07:54.591135
8734 08:07:54.591217 Set Vref, RX VrefLevel [Byte0]: 76
8735 08:07:54.594491 [Byte1]: 76
8736 08:07:54.598653
8737 08:07:54.598734 Final RX Vref Byte 0 = 58 to rank0
8738 08:07:54.602115 Final RX Vref Byte 1 = 57 to rank0
8739 08:07:54.605214 Final RX Vref Byte 0 = 58 to rank1
8740 08:07:54.608693 Final RX Vref Byte 1 = 57 to rank1==
8741 08:07:54.612438 Dram Type= 6, Freq= 0, CH_1, rank 0
8742 08:07:54.615430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 08:07:54.618734 ==
8744 08:07:54.618833 DQS Delay:
8745 08:07:54.618929 DQS0 = 0, DQS1 = 0
8746 08:07:54.621833 DQM Delay:
8747 08:07:54.621910 DQM0 = 134, DQM1 = 131
8748 08:07:54.625379 DQ Delay:
8749 08:07:54.628982 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8750 08:07:54.631824 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8751 08:07:54.635734 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8752 08:07:54.639184 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8753 08:07:54.639253
8754 08:07:54.639312
8755 08:07:54.639369
8756 08:07:54.642269 [DramC_TX_OE_Calibration] TA2
8757 08:07:54.645429 Original DQ_B0 (3 6) =30, OEN = 27
8758 08:07:54.648571 Original DQ_B1 (3 6) =30, OEN = 27
8759 08:07:54.651933 24, 0x0, End_B0=24 End_B1=24
8760 08:07:54.652005 25, 0x0, End_B0=25 End_B1=25
8761 08:07:54.655560 26, 0x0, End_B0=26 End_B1=26
8762 08:07:54.658577 27, 0x0, End_B0=27 End_B1=27
8763 08:07:54.662079 28, 0x0, End_B0=28 End_B1=28
8764 08:07:54.662211 29, 0x0, End_B0=29 End_B1=29
8765 08:07:54.665366 30, 0x0, End_B0=30 End_B1=30
8766 08:07:54.669037 31, 0x4141, End_B0=30 End_B1=30
8767 08:07:54.671907 Byte0 end_step=30 best_step=27
8768 08:07:54.675200 Byte1 end_step=30 best_step=27
8769 08:07:54.678442 Byte0 TX OE(2T, 0.5T) = (3, 3)
8770 08:07:54.678522 Byte1 TX OE(2T, 0.5T) = (3, 3)
8771 08:07:54.678584
8772 08:07:54.681993
8773 08:07:54.688229 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8774 08:07:54.692065 CH1 RK0: MR19=303, MR18=1826
8775 08:07:54.698528 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8776 08:07:54.698609
8777 08:07:54.701810 ----->DramcWriteLeveling(PI) begin...
8778 08:07:54.701907 ==
8779 08:07:54.705347 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 08:07:54.708321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 08:07:54.708401 ==
8782 08:07:54.711880 Write leveling (Byte 0): 25 => 25
8783 08:07:54.714972 Write leveling (Byte 1): 29 => 29
8784 08:07:54.718365 DramcWriteLeveling(PI) end<-----
8785 08:07:54.718444
8786 08:07:54.718507 ==
8787 08:07:54.721785 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 08:07:54.725322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 08:07:54.725454 ==
8790 08:07:54.728464 [Gating] SW mode calibration
8791 08:07:54.735006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8792 08:07:54.741600 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8793 08:07:54.745395 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 08:07:54.748528 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 08:07:54.754883 1 4 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
8796 08:07:54.758263 1 4 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (0 0)
8797 08:07:54.761655 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 08:07:54.768287 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 08:07:54.771312 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 08:07:54.774670 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 08:07:54.781381 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 08:07:54.784960 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8803 08:07:54.788165 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8804 08:07:54.795038 1 5 12 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
8805 08:07:54.798106 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 08:07:54.801549 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 08:07:54.808519 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 08:07:54.811503 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 08:07:54.815050 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 08:07:54.821451 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 08:07:54.824842 1 6 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
8812 08:07:54.827709 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 08:07:54.834901 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 08:07:54.838090 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 08:07:54.841162 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 08:07:54.844628 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 08:07:54.851404 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 08:07:54.854497 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8819 08:07:54.857920 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8820 08:07:54.864344 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8821 08:07:54.867850 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8822 08:07:54.870975 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 08:07:54.878064 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 08:07:54.881213 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 08:07:54.884505 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 08:07:54.891121 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 08:07:54.894486 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 08:07:54.898119 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 08:07:54.904155 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 08:07:54.907567 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 08:07:54.910840 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 08:07:54.917419 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 08:07:54.921041 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 08:07:54.924621 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8835 08:07:54.930960 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8836 08:07:54.934578 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8837 08:07:54.937559 Total UI for P1: 0, mck2ui 16
8838 08:07:54.941424 best dqsien dly found for B1: ( 1, 9, 6)
8839 08:07:54.944019 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 08:07:54.947790 Total UI for P1: 0, mck2ui 16
8841 08:07:54.951308 best dqsien dly found for B0: ( 1, 9, 12)
8842 08:07:54.954346 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8843 08:07:54.957706 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8844 08:07:54.957778
8845 08:07:54.960865 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8846 08:07:54.967771 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8847 08:07:54.967849 [Gating] SW calibration Done
8848 08:07:54.967910 ==
8849 08:07:54.970671 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 08:07:54.977263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 08:07:54.977342 ==
8852 08:07:54.977403 RX Vref Scan: 0
8853 08:07:54.977461
8854 08:07:54.980820 RX Vref 0 -> 0, step: 1
8855 08:07:54.980887
8856 08:07:54.984484 RX Delay 0 -> 252, step: 8
8857 08:07:54.987229 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8858 08:07:54.990660 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8859 08:07:54.994173 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8860 08:07:55.000529 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8861 08:07:55.003809 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8862 08:07:55.007669 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8863 08:07:55.010539 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8864 08:07:55.013874 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8865 08:07:55.020625 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8866 08:07:55.023887 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8867 08:07:55.027198 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8868 08:07:55.030491 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8869 08:07:55.033721 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8870 08:07:55.040673 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8871 08:07:55.043570 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8872 08:07:55.047181 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8873 08:07:55.047253 ==
8874 08:07:55.050934 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 08:07:55.053667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 08:07:55.053741 ==
8877 08:07:55.056781 DQS Delay:
8878 08:07:55.056856 DQS0 = 0, DQS1 = 0
8879 08:07:55.060639 DQM Delay:
8880 08:07:55.060707 DQM0 = 136, DQM1 = 133
8881 08:07:55.060769 DQ Delay:
8882 08:07:55.066816 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8883 08:07:55.070378 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8884 08:07:55.073827 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8885 08:07:55.077516 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8886 08:07:55.077584
8887 08:07:55.077644
8888 08:07:55.077709 ==
8889 08:07:55.080259 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 08:07:55.083799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 08:07:55.083872 ==
8892 08:07:55.083941
8893 08:07:55.084000
8894 08:07:55.087395 TX Vref Scan disable
8895 08:07:55.090127 == TX Byte 0 ==
8896 08:07:55.093586 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8897 08:07:55.097228 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8898 08:07:55.100720 == TX Byte 1 ==
8899 08:07:55.103273 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8900 08:07:55.106925 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8901 08:07:55.106997 ==
8902 08:07:55.110124 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 08:07:55.116557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 08:07:55.116631 ==
8905 08:07:55.127743
8906 08:07:55.131448 TX Vref early break, caculate TX vref
8907 08:07:55.134802 TX Vref=16, minBit 0, minWin=23, winSum=385
8908 08:07:55.137965 TX Vref=18, minBit 0, minWin=23, winSum=393
8909 08:07:55.141237 TX Vref=20, minBit 0, minWin=24, winSum=399
8910 08:07:55.144527 TX Vref=22, minBit 0, minWin=25, winSum=411
8911 08:07:55.148062 TX Vref=24, minBit 0, minWin=25, winSum=416
8912 08:07:55.154285 TX Vref=26, minBit 0, minWin=25, winSum=425
8913 08:07:55.157687 TX Vref=28, minBit 0, minWin=25, winSum=422
8914 08:07:55.160967 TX Vref=30, minBit 0, minWin=24, winSum=421
8915 08:07:55.164082 TX Vref=32, minBit 0, minWin=24, winSum=414
8916 08:07:55.167501 TX Vref=34, minBit 0, minWin=24, winSum=401
8917 08:07:55.174155 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8918 08:07:55.174286
8919 08:07:55.177465 Final TX Range 0 Vref 26
8920 08:07:55.177593
8921 08:07:55.177704 ==
8922 08:07:55.180869 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 08:07:55.184311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 08:07:55.184414 ==
8925 08:07:55.184505
8926 08:07:55.184599
8927 08:07:55.187339 TX Vref Scan disable
8928 08:07:55.194265 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8929 08:07:55.194343 == TX Byte 0 ==
8930 08:07:55.197760 u2DelayCellOfst[0]=16 cells (5 PI)
8931 08:07:55.200687 u2DelayCellOfst[1]=10 cells (3 PI)
8932 08:07:55.204209 u2DelayCellOfst[2]=0 cells (0 PI)
8933 08:07:55.207439 u2DelayCellOfst[3]=6 cells (2 PI)
8934 08:07:55.210948 u2DelayCellOfst[4]=6 cells (2 PI)
8935 08:07:55.214148 u2DelayCellOfst[5]=16 cells (5 PI)
8936 08:07:55.217716 u2DelayCellOfst[6]=16 cells (5 PI)
8937 08:07:55.220811 u2DelayCellOfst[7]=6 cells (2 PI)
8938 08:07:55.224065 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8939 08:07:55.227554 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 08:07:55.231035 == TX Byte 1 ==
8941 08:07:55.231105 u2DelayCellOfst[8]=0 cells (0 PI)
8942 08:07:55.234395 u2DelayCellOfst[9]=3 cells (1 PI)
8943 08:07:55.237719 u2DelayCellOfst[10]=10 cells (3 PI)
8944 08:07:55.241151 u2DelayCellOfst[11]=3 cells (1 PI)
8945 08:07:55.244150 u2DelayCellOfst[12]=13 cells (4 PI)
8946 08:07:55.247586 u2DelayCellOfst[13]=16 cells (5 PI)
8947 08:07:55.250621 u2DelayCellOfst[14]=16 cells (5 PI)
8948 08:07:55.254006 u2DelayCellOfst[15]=16 cells (5 PI)
8949 08:07:55.257391 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8950 08:07:55.264246 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8951 08:07:55.264326 DramC Write-DBI on
8952 08:07:55.264389 ==
8953 08:07:55.267896 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 08:07:55.271204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 08:07:55.271333 ==
8956 08:07:55.274100
8957 08:07:55.274173
8958 08:07:55.274234 TX Vref Scan disable
8959 08:07:55.277825 == TX Byte 0 ==
8960 08:07:55.281063 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8961 08:07:55.284580 == TX Byte 1 ==
8962 08:07:55.287782 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8963 08:07:55.287881 DramC Write-DBI off
8964 08:07:55.290777
8965 08:07:55.290848 [DATLAT]
8966 08:07:55.290909 Freq=1600, CH1 RK1
8967 08:07:55.290966
8968 08:07:55.293872 DATLAT Default: 0xf
8969 08:07:55.293942 0, 0xFFFF, sum = 0
8970 08:07:55.297537 1, 0xFFFF, sum = 0
8971 08:07:55.297616 2, 0xFFFF, sum = 0
8972 08:07:55.300663 3, 0xFFFF, sum = 0
8973 08:07:55.304191 4, 0xFFFF, sum = 0
8974 08:07:55.304265 5, 0xFFFF, sum = 0
8975 08:07:55.307123 6, 0xFFFF, sum = 0
8976 08:07:55.307193 7, 0xFFFF, sum = 0
8977 08:07:55.310679 8, 0xFFFF, sum = 0
8978 08:07:55.310753 9, 0xFFFF, sum = 0
8979 08:07:55.314007 10, 0xFFFF, sum = 0
8980 08:07:55.314084 11, 0xFFFF, sum = 0
8981 08:07:55.316968 12, 0xFFFF, sum = 0
8982 08:07:55.317046 13, 0xFFFF, sum = 0
8983 08:07:55.320524 14, 0x0, sum = 1
8984 08:07:55.320628 15, 0x0, sum = 2
8985 08:07:55.323800 16, 0x0, sum = 3
8986 08:07:55.323874 17, 0x0, sum = 4
8987 08:07:55.327026 best_step = 15
8988 08:07:55.327098
8989 08:07:55.327164 ==
8990 08:07:55.330825 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 08:07:55.333569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 08:07:55.333640 ==
8993 08:07:55.337152 RX Vref Scan: 0
8994 08:07:55.337222
8995 08:07:55.337288 RX Vref 0 -> 0, step: 1
8996 08:07:55.337345
8997 08:07:55.340661 RX Delay 19 -> 252, step: 4
8998 08:07:55.343567 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8999 08:07:55.350700 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9000 08:07:55.353734 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9001 08:07:55.357018 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9002 08:07:55.360588 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9003 08:07:55.363599 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9004 08:07:55.367369 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9005 08:07:55.374073 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9006 08:07:55.376878 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9007 08:07:55.380625 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9008 08:07:55.383430 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9009 08:07:55.387023 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9010 08:07:55.393663 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9011 08:07:55.397220 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9012 08:07:55.400271 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9013 08:07:55.403984 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9014 08:07:55.404063 ==
9015 08:07:55.407090 Dram Type= 6, Freq= 0, CH_1, rank 1
9016 08:07:55.413708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9017 08:07:55.413789 ==
9018 08:07:55.413851 DQS Delay:
9019 08:07:55.416876 DQS0 = 0, DQS1 = 0
9020 08:07:55.416971 DQM Delay:
9021 08:07:55.417070 DQM0 = 134, DQM1 = 130
9022 08:07:55.420416 DQ Delay:
9023 08:07:55.423898 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9024 08:07:55.427052 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9025 08:07:55.430112 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9026 08:07:55.433472 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9027 08:07:55.433593
9028 08:07:55.433707
9029 08:07:55.433816
9030 08:07:55.437122 [DramC_TX_OE_Calibration] TA2
9031 08:07:55.440403 Original DQ_B0 (3 6) =30, OEN = 27
9032 08:07:55.443914 Original DQ_B1 (3 6) =30, OEN = 27
9033 08:07:55.446948 24, 0x0, End_B0=24 End_B1=24
9034 08:07:55.447070 25, 0x0, End_B0=25 End_B1=25
9035 08:07:55.450444 26, 0x0, End_B0=26 End_B1=26
9036 08:07:55.453606 27, 0x0, End_B0=27 End_B1=27
9037 08:07:55.456931 28, 0x0, End_B0=28 End_B1=28
9038 08:07:55.460649 29, 0x0, End_B0=29 End_B1=29
9039 08:07:55.460774 30, 0x0, End_B0=30 End_B1=30
9040 08:07:55.463905 31, 0x4141, End_B0=30 End_B1=30
9041 08:07:55.466964 Byte0 end_step=30 best_step=27
9042 08:07:55.470473 Byte1 end_step=30 best_step=27
9043 08:07:55.473520 Byte0 TX OE(2T, 0.5T) = (3, 3)
9044 08:07:55.477354 Byte1 TX OE(2T, 0.5T) = (3, 3)
9045 08:07:55.477473
9046 08:07:55.477604
9047 08:07:55.483697 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9048 08:07:55.487072 CH1 RK1: MR19=303, MR18=250A
9049 08:07:55.493654 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
9050 08:07:55.497122 [RxdqsGatingPostProcess] freq 1600
9051 08:07:55.500429 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9052 08:07:55.503365 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 08:07:55.506785 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 08:07:55.510152 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 08:07:55.513529 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 08:07:55.516952 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 08:07:55.519995 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 08:07:55.523556 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 08:07:55.526822 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 08:07:55.530093 Pre-setting of DQS Precalculation
9061 08:07:55.534068 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9062 08:07:55.540433 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9063 08:07:55.546820 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 08:07:55.546897
9065 08:07:55.546960
9066 08:07:55.550078 [Calibration Summary] 3200 Mbps
9067 08:07:55.553680 CH 0, Rank 0
9068 08:07:55.553757 SW Impedance : PASS
9069 08:07:55.556652 DUTY Scan : NO K
9070 08:07:55.560152 ZQ Calibration : PASS
9071 08:07:55.560223 Jitter Meter : NO K
9072 08:07:55.563527 CBT Training : PASS
9073 08:07:55.566423 Write leveling : PASS
9074 08:07:55.566534 RX DQS gating : PASS
9075 08:07:55.570134 RX DQ/DQS(RDDQC) : PASS
9076 08:07:55.573492 TX DQ/DQS : PASS
9077 08:07:55.573574 RX DATLAT : PASS
9078 08:07:55.576571 RX DQ/DQS(Engine): PASS
9079 08:07:55.579804 TX OE : PASS
9080 08:07:55.579880 All Pass.
9081 08:07:55.579949
9082 08:07:55.580008 CH 0, Rank 1
9083 08:07:55.582953 SW Impedance : PASS
9084 08:07:55.586863 DUTY Scan : NO K
9085 08:07:55.586945 ZQ Calibration : PASS
9086 08:07:55.590270 Jitter Meter : NO K
9087 08:07:55.590402 CBT Training : PASS
9088 08:07:55.593290 Write leveling : PASS
9089 08:07:55.596415 RX DQS gating : PASS
9090 08:07:55.596535 RX DQ/DQS(RDDQC) : PASS
9091 08:07:55.599776 TX DQ/DQS : PASS
9092 08:07:55.603375 RX DATLAT : PASS
9093 08:07:55.603496 RX DQ/DQS(Engine): PASS
9094 08:07:55.606825 TX OE : PASS
9095 08:07:55.606953 All Pass.
9096 08:07:55.607064
9097 08:07:55.609787 CH 1, Rank 0
9098 08:07:55.609924 SW Impedance : PASS
9099 08:07:55.613571 DUTY Scan : NO K
9100 08:07:55.616328 ZQ Calibration : PASS
9101 08:07:55.616452 Jitter Meter : NO K
9102 08:07:55.619968 CBT Training : PASS
9103 08:07:55.623074 Write leveling : PASS
9104 08:07:55.623201 RX DQS gating : PASS
9105 08:07:55.626338 RX DQ/DQS(RDDQC) : PASS
9106 08:07:55.629862 TX DQ/DQS : PASS
9107 08:07:55.629992 RX DATLAT : PASS
9108 08:07:55.632805 RX DQ/DQS(Engine): PASS
9109 08:07:55.636429 TX OE : PASS
9110 08:07:55.636548 All Pass.
9111 08:07:55.636664
9112 08:07:55.636775 CH 1, Rank 1
9113 08:07:55.639498 SW Impedance : PASS
9114 08:07:55.642796 DUTY Scan : NO K
9115 08:07:55.642923 ZQ Calibration : PASS
9116 08:07:55.646000 Jitter Meter : NO K
9117 08:07:55.646106 CBT Training : PASS
9118 08:07:55.649776 Write leveling : PASS
9119 08:07:55.653219 RX DQS gating : PASS
9120 08:07:55.653291 RX DQ/DQS(RDDQC) : PASS
9121 08:07:55.656472 TX DQ/DQS : PASS
9122 08:07:55.659689 RX DATLAT : PASS
9123 08:07:55.659762 RX DQ/DQS(Engine): PASS
9124 08:07:55.663102 TX OE : PASS
9125 08:07:55.663185 All Pass.
9126 08:07:55.663248
9127 08:07:55.666259 DramC Write-DBI on
9128 08:07:55.669691 PER_BANK_REFRESH: Hybrid Mode
9129 08:07:55.669778 TX_TRACKING: ON
9130 08:07:55.679359 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9131 08:07:55.686014 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9132 08:07:55.693175 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 08:07:55.696066 [FAST_K] Save calibration result to emmc
9134 08:07:55.699336 sync common calibartion params.
9135 08:07:55.702930 sync cbt_mode0:1, 1:1
9136 08:07:55.706293 dram_init: ddr_geometry: 2
9137 08:07:55.706380 dram_init: ddr_geometry: 2
9138 08:07:55.709116 dram_init: ddr_geometry: 2
9139 08:07:55.712984 0:dram_rank_size:100000000
9140 08:07:55.716193 1:dram_rank_size:100000000
9141 08:07:55.719173 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9142 08:07:55.722829 DFS_SHUFFLE_HW_MODE: ON
9143 08:07:55.725615 dramc_set_vcore_voltage set vcore to 725000
9144 08:07:55.729372 Read voltage for 1600, 0
9145 08:07:55.729478 Vio18 = 0
9146 08:07:55.729539 Vcore = 725000
9147 08:07:55.732695 Vdram = 0
9148 08:07:55.732765 Vddq = 0
9149 08:07:55.732825 Vmddr = 0
9150 08:07:55.736108 switch to 3200 Mbps bootup
9151 08:07:55.739256 [DramcRunTimeConfig]
9152 08:07:55.739327 PHYPLL
9153 08:07:55.739393 DPM_CONTROL_AFTERK: ON
9154 08:07:55.742654 PER_BANK_REFRESH: ON
9155 08:07:55.745791 REFRESH_OVERHEAD_REDUCTION: ON
9156 08:07:55.745862 CMD_PICG_NEW_MODE: OFF
9157 08:07:55.749298 XRTWTW_NEW_MODE: ON
9158 08:07:55.752692 XRTRTR_NEW_MODE: ON
9159 08:07:55.752764 TX_TRACKING: ON
9160 08:07:55.755551 RDSEL_TRACKING: OFF
9161 08:07:55.755621 DQS Precalculation for DVFS: ON
9162 08:07:55.759093 RX_TRACKING: OFF
9163 08:07:55.759184 HW_GATING DBG: ON
9164 08:07:55.762354 ZQCS_ENABLE_LP4: ON
9165 08:07:55.762453 RX_PICG_NEW_MODE: ON
9166 08:07:55.765703 TX_PICG_NEW_MODE: ON
9167 08:07:55.769149 ENABLE_RX_DCM_DPHY: ON
9168 08:07:55.772163 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9169 08:07:55.772238 DUMMY_READ_FOR_TRACKING: OFF
9170 08:07:55.775712 !!! SPM_CONTROL_AFTERK: OFF
9171 08:07:55.778831 !!! SPM could not control APHY
9172 08:07:55.782465 IMPEDANCE_TRACKING: ON
9173 08:07:55.782547 TEMP_SENSOR: ON
9174 08:07:55.785927 HW_SAVE_FOR_SR: OFF
9175 08:07:55.786004 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9176 08:07:55.792588 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9177 08:07:55.792671 Read ODT Tracking: ON
9178 08:07:55.795770 Refresh Rate DeBounce: ON
9179 08:07:55.795839 DFS_NO_QUEUE_FLUSH: ON
9180 08:07:55.799251 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9181 08:07:55.802321 ENABLE_DFS_RUNTIME_MRW: OFF
9182 08:07:55.805796 DDR_RESERVE_NEW_MODE: ON
9183 08:07:55.805863 MR_CBT_SWITCH_FREQ: ON
9184 08:07:55.808887 =========================
9185 08:07:55.828679 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9186 08:07:55.831878 dram_init: ddr_geometry: 2
9187 08:07:55.850095 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9188 08:07:55.853058 dram_init: dram init end (result: 0)
9189 08:07:55.860136 DRAM-K: Full calibration passed in 24454 msecs
9190 08:07:55.863129 MRC: failed to locate region type 0.
9191 08:07:55.863207 DRAM rank0 size:0x100000000,
9192 08:07:55.866881 DRAM rank1 size=0x100000000
9193 08:07:55.876403 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9194 08:07:55.883404 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9195 08:07:55.889990 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9196 08:07:55.896903 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9197 08:07:55.900112 DRAM rank0 size:0x100000000,
9198 08:07:55.903398 DRAM rank1 size=0x100000000
9199 08:07:55.903466 CBMEM:
9200 08:07:55.906959 IMD: root @ 0xfffff000 254 entries.
9201 08:07:55.909940 IMD: root @ 0xffffec00 62 entries.
9202 08:07:55.913308 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9203 08:07:55.916519 WARNING: RO_VPD is uninitialized or empty.
9204 08:07:55.923406 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9205 08:07:55.929967 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9206 08:07:55.942483 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9207 08:07:55.954130 BS: romstage times (exec / console): total (unknown) / 23986 ms
9208 08:07:55.954213
9209 08:07:55.954295
9210 08:07:55.964135 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9211 08:07:55.967659 ARM64: Exception handlers installed.
9212 08:07:55.970748 ARM64: Testing exception
9213 08:07:55.974597 ARM64: Done test exception
9214 08:07:55.974686 Enumerating buses...
9215 08:07:55.977380 Show all devs... Before device enumeration.
9216 08:07:55.980949 Root Device: enabled 1
9217 08:07:55.984563 CPU_CLUSTER: 0: enabled 1
9218 08:07:55.984643 CPU: 00: enabled 1
9219 08:07:55.987563 Compare with tree...
9220 08:07:55.987657 Root Device: enabled 1
9221 08:07:55.991293 CPU_CLUSTER: 0: enabled 1
9222 08:07:55.994344 CPU: 00: enabled 1
9223 08:07:55.994424 Root Device scanning...
9224 08:07:55.997403 scan_static_bus for Root Device
9225 08:07:56.000655 CPU_CLUSTER: 0 enabled
9226 08:07:56.004231 scan_static_bus for Root Device done
9227 08:07:56.007794 scan_bus: bus Root Device finished in 8 msecs
9228 08:07:56.007892 done
9229 08:07:56.014545 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9230 08:07:56.017275 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9231 08:07:56.024212 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9232 08:07:56.027163 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9233 08:07:56.030680 Allocating resources...
9234 08:07:56.030760 Reading resources...
9235 08:07:56.037351 Root Device read_resources bus 0 link: 0
9236 08:07:56.037432 DRAM rank0 size:0x100000000,
9237 08:07:56.041065 DRAM rank1 size=0x100000000
9238 08:07:56.043863 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9239 08:07:56.047170 CPU: 00 missing read_resources
9240 08:07:56.050570 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9241 08:07:56.057318 Root Device read_resources bus 0 link: 0 done
9242 08:07:56.057439 Done reading resources.
9243 08:07:56.063901 Show resources in subtree (Root Device)...After reading.
9244 08:07:56.067385 Root Device child on link 0 CPU_CLUSTER: 0
9245 08:07:56.070640 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 08:07:56.081031 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 08:07:56.081190 CPU: 00
9248 08:07:56.083881 Root Device assign_resources, bus 0 link: 0
9249 08:07:56.087387 CPU_CLUSTER: 0 missing set_resources
9250 08:07:56.090952 Root Device assign_resources, bus 0 link: 0 done
9251 08:07:56.093684 Done setting resources.
9252 08:07:56.100799 Show resources in subtree (Root Device)...After assigning values.
9253 08:07:56.103580 Root Device child on link 0 CPU_CLUSTER: 0
9254 08:07:56.107138 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 08:07:56.117074 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 08:07:56.117197 CPU: 00
9257 08:07:56.120406 Done allocating resources.
9258 08:07:56.123972 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9259 08:07:56.127210 Enabling resources...
9260 08:07:56.127324 done.
9261 08:07:56.130602 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9262 08:07:56.134083 Initializing devices...
9263 08:07:56.137583 Root Device init
9264 08:07:56.137684 init hardware done!
9265 08:07:56.140559 0x00000018: ctrlr->caps
9266 08:07:56.140640 52.000 MHz: ctrlr->f_max
9267 08:07:56.144293 0.400 MHz: ctrlr->f_min
9268 08:07:56.147399 0x40ff8080: ctrlr->voltages
9269 08:07:56.147525 sclk: 390625
9270 08:07:56.150647 Bus Width = 1
9271 08:07:56.150773 sclk: 390625
9272 08:07:56.150879 Bus Width = 1
9273 08:07:56.154150 Early init status = 3
9274 08:07:56.157297 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9275 08:07:56.161837 in-header: 03 fb 00 00 01 00 00 00
9276 08:07:56.164924 in-data: 01
9277 08:07:56.168484 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 08:07:56.172061 in-header: 03 fb 00 00 01 00 00 00
9279 08:07:56.175461 in-data: 01
9280 08:07:56.178663 [SSUSB] Setting up USB HOST controller...
9281 08:07:56.182055 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9282 08:07:56.185402 [SSUSB] phy power-on done.
9283 08:07:56.188513 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9284 08:07:56.195589 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9285 08:07:56.198754 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9286 08:07:56.205263 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9287 08:07:56.212085 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9288 08:07:56.218461 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9289 08:07:56.225363 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9290 08:07:56.231858 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9291 08:07:56.235562 SPM: binary array size = 0x9dc
9292 08:07:56.238412 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9293 08:07:56.244957 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9294 08:07:56.251488 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9295 08:07:56.258291 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9296 08:07:56.261586 configure_display: Starting display init
9297 08:07:56.295276 anx7625_power_on_init: Init interface.
9298 08:07:56.298993 anx7625_disable_pd_protocol: Disabled PD feature.
9299 08:07:56.302169 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9300 08:07:56.329779 anx7625_start_dp_work: Secure OCM version=00
9301 08:07:56.333264 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9302 08:07:56.347978 sp_tx_get_edid_block: EDID Block = 1
9303 08:07:56.450524 Extracted contents:
9304 08:07:56.453869 header: 00 ff ff ff ff ff ff 00
9305 08:07:56.457430 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9306 08:07:56.460650 version: 01 04
9307 08:07:56.464061 basic params: 95 1f 11 78 0a
9308 08:07:56.466795 chroma info: 76 90 94 55 54 90 27 21 50 54
9309 08:07:56.470327 established: 00 00 00
9310 08:07:56.477032 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9311 08:07:56.483786 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9312 08:07:56.486697 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9313 08:07:56.493300 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9314 08:07:56.500072 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9315 08:07:56.503055 extensions: 00
9316 08:07:56.503155 checksum: fb
9317 08:07:56.503249
9318 08:07:56.510142 Manufacturer: IVO Model 57d Serial Number 0
9319 08:07:56.510222 Made week 0 of 2020
9320 08:07:56.513086 EDID version: 1.4
9321 08:07:56.513165 Digital display
9322 08:07:56.516470 6 bits per primary color channel
9323 08:07:56.516551 DisplayPort interface
9324 08:07:56.520027 Maximum image size: 31 cm x 17 cm
9325 08:07:56.523174 Gamma: 220%
9326 08:07:56.523253 Check DPMS levels
9327 08:07:56.526446 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9328 08:07:56.533116 First detailed timing is preferred timing
9329 08:07:56.533197 Established timings supported:
9330 08:07:56.536535 Standard timings supported:
9331 08:07:56.539656 Detailed timings
9332 08:07:56.542931 Hex of detail: 383680a07038204018303c0035ae10000019
9333 08:07:56.549878 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9334 08:07:56.552839 0780 0798 07c8 0820 hborder 0
9335 08:07:56.556485 0438 043b 0447 0458 vborder 0
9336 08:07:56.559566 -hsync -vsync
9337 08:07:56.559657 Did detailed timing
9338 08:07:56.566400 Hex of detail: 000000000000000000000000000000000000
9339 08:07:56.569869 Manufacturer-specified data, tag 0
9340 08:07:56.573003 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9341 08:07:56.576684 ASCII string: InfoVision
9342 08:07:56.579771 Hex of detail: 000000fe00523134304e574635205248200a
9343 08:07:56.583182 ASCII string: R140NWF5 RH
9344 08:07:56.583297 Checksum
9345 08:07:56.586162 Checksum: 0xfb (valid)
9346 08:07:56.589890 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9347 08:07:56.592700 DSI data_rate: 832800000 bps
9348 08:07:56.599358 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9349 08:07:56.603251 anx7625_parse_edid: pixelclock(138800).
9350 08:07:56.606462 hactive(1920), hsync(48), hfp(24), hbp(88)
9351 08:07:56.609458 vactive(1080), vsync(12), vfp(3), vbp(17)
9352 08:07:56.613095 anx7625_dsi_config: config dsi.
9353 08:07:56.619537 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9354 08:07:56.632859 anx7625_dsi_config: success to config DSI
9355 08:07:56.635956 anx7625_dp_start: MIPI phy setup OK.
9356 08:07:56.639564 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9357 08:07:56.642402 mtk_ddp_mode_set invalid vrefresh 60
9358 08:07:56.645969 main_disp_path_setup
9359 08:07:56.646077 ovl_layer_smi_id_en
9360 08:07:56.649369 ovl_layer_smi_id_en
9361 08:07:56.649472 ccorr_config
9362 08:07:56.649564 aal_config
9363 08:07:56.652432 gamma_config
9364 08:07:56.652530 postmask_config
9365 08:07:56.656010 dither_config
9366 08:07:56.659355 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9367 08:07:56.665741 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9368 08:07:56.669229 Root Device init finished in 529 msecs
9369 08:07:56.669332 CPU_CLUSTER: 0 init
9370 08:07:56.679297 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9371 08:07:56.683172 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9372 08:07:56.685989 APU_MBOX 0x190000b0 = 0x10001
9373 08:07:56.689419 APU_MBOX 0x190001b0 = 0x10001
9374 08:07:56.692752 APU_MBOX 0x190005b0 = 0x10001
9375 08:07:56.695984 APU_MBOX 0x190006b0 = 0x10001
9376 08:07:56.699474 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9377 08:07:56.711828 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9378 08:07:56.724229 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9379 08:07:56.730669 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9380 08:07:56.742307 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9381 08:07:56.751289 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9382 08:07:56.754968 CPU_CLUSTER: 0 init finished in 81 msecs
9383 08:07:56.758171 Devices initialized
9384 08:07:56.761639 Show all devs... After init.
9385 08:07:56.761724 Root Device: enabled 1
9386 08:07:56.765118 CPU_CLUSTER: 0: enabled 1
9387 08:07:56.767823 CPU: 00: enabled 1
9388 08:07:56.771289 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9389 08:07:56.774746 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9390 08:07:56.778415 ELOG: NV offset 0x57f000 size 0x1000
9391 08:07:56.784664 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9392 08:07:56.791501 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9393 08:07:56.794665 ELOG: Event(17) added with size 13 at 2023-09-21 08:06:29 UTC
9394 08:07:56.797856 out: cmd=0x121: 03 db 21 01 00 00 00 00
9395 08:07:56.801730 in-header: 03 f5 00 00 2c 00 00 00
9396 08:07:56.815266 in-data: 6a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 08:07:56.821682 ELOG: Event(A1) added with size 10 at 2023-09-21 08:06:29 UTC
9398 08:07:56.828303 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9399 08:07:56.834807 ELOG: Event(A0) added with size 9 at 2023-09-21 08:06:29 UTC
9400 08:07:56.838366 elog_add_boot_reason: Logged dev mode boot
9401 08:07:56.841584 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9402 08:07:56.844799 Finalize devices...
9403 08:07:56.844892 Devices finalized
9404 08:07:56.851671 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9405 08:07:56.854772 Writing coreboot table at 0xffe64000
9406 08:07:56.857935 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 08:07:56.861626 1. 0000000040000000-00000000400fffff: RAM
9408 08:07:56.864570 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 08:07:56.871263 3. 000000004032b000-00000000545fffff: RAM
9410 08:07:56.874634 4. 0000000054600000-000000005465ffff: BL31
9411 08:07:56.878165 5. 0000000054660000-00000000ffe63fff: RAM
9412 08:07:56.884545 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 08:07:56.888042 7. 0000000100000000-000000023fffffff: RAM
9414 08:07:56.888125 Passing 5 GPIOs to payload:
9415 08:07:56.894580 NAME | PORT | POLARITY | VALUE
9416 08:07:56.898116 EC in RW | 0x000000aa | low | undefined
9417 08:07:56.904416 EC interrupt | 0x00000005 | low | undefined
9418 08:07:56.907775 TPM interrupt | 0x000000ab | high | undefined
9419 08:07:56.911128 SD card detect | 0x00000011 | high | undefined
9420 08:07:56.917525 speaker enable | 0x00000093 | high | undefined
9421 08:07:56.921117 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 08:07:56.924554 in-header: 03 f9 00 00 02 00 00 00
9423 08:07:56.924644 in-data: 02 00
9424 08:07:56.927937 ADC[4]: Raw value=904726 ID=7
9425 08:07:56.931115 ADC[3]: Raw value=213441 ID=1
9426 08:07:56.931195 RAM Code: 0x71
9427 08:07:56.934725 ADC[6]: Raw value=75332 ID=0
9428 08:07:56.937549 ADC[5]: Raw value=213072 ID=1
9429 08:07:56.937629 SKU Code: 0x1
9430 08:07:56.944235 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9431 08:07:56.947963 coreboot table: 964 bytes.
9432 08:07:56.950935 IMD ROOT 0. 0xfffff000 0x00001000
9433 08:07:56.954264 IMD SMALL 1. 0xffffe000 0x00001000
9434 08:07:56.957898 RO MCACHE 2. 0xffffc000 0x00001104
9435 08:07:56.961139 CONSOLE 3. 0xfff7c000 0x00080000
9436 08:07:56.964303 FMAP 4. 0xfff7b000 0x00000452
9437 08:07:56.967482 TIME STAMP 5. 0xfff7a000 0x00000910
9438 08:07:56.971152 VBOOT WORK 6. 0xfff66000 0x00014000
9439 08:07:56.974070 RAMOOPS 7. 0xffe66000 0x00100000
9440 08:07:56.977475 COREBOOT 8. 0xffe64000 0x00002000
9441 08:07:56.977598 IMD small region:
9442 08:07:56.980984 IMD ROOT 0. 0xffffec00 0x00000400
9443 08:07:56.983865 VPD 1. 0xffffeb80 0x0000006c
9444 08:07:56.987460 MMC STATUS 2. 0xffffeb60 0x00000004
9445 08:07:56.993881 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 08:07:56.997305 Probing TPM: done!
9447 08:07:57.000926 Connected to device vid:did:rid of 1ae0:0028:00
9448 08:07:57.010674 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9449 08:07:57.014178 Initialized TPM device CR50 revision 0
9450 08:07:57.017809 Checking cr50 for pending updates
9451 08:07:57.021243 Reading cr50 TPM mode
9452 08:07:57.029754 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9453 08:07:57.036557 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9454 08:07:57.076494 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9455 08:07:57.079756 Checking segment from ROM address 0x40100000
9456 08:07:57.083146 Checking segment from ROM address 0x4010001c
9457 08:07:57.090210 Loading segment from ROM address 0x40100000
9458 08:07:57.090330 code (compression=0)
9459 08:07:57.096729 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9460 08:07:57.106585 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9461 08:07:57.106705 it's not compressed!
9462 08:07:57.113671 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9463 08:07:57.116706 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9464 08:07:57.137069 Loading segment from ROM address 0x4010001c
9465 08:07:57.137199 Entry Point 0x80000000
9466 08:07:57.139977 Loaded segments
9467 08:07:57.143377 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9468 08:07:57.150076 Jumping to boot code at 0x80000000(0xffe64000)
9469 08:07:57.156797 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9470 08:07:57.163449 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9471 08:07:57.171408 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9472 08:07:57.174748 Checking segment from ROM address 0x40100000
9473 08:07:57.177902 Checking segment from ROM address 0x4010001c
9474 08:07:57.184451 Loading segment from ROM address 0x40100000
9475 08:07:57.184573 code (compression=1)
9476 08:07:57.191173 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9477 08:07:57.200940 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9478 08:07:57.201065 using LZMA
9479 08:07:57.209681 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9480 08:07:57.216639 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9481 08:07:57.220027 Loading segment from ROM address 0x4010001c
9482 08:07:57.220148 Entry Point 0x54601000
9483 08:07:57.222853 Loaded segments
9484 08:07:57.226168 NOTICE: MT8192 bl31_setup
9485 08:07:57.233029 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9486 08:07:57.236588 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9487 08:07:57.240308 WARNING: region 0:
9488 08:07:57.243033 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 08:07:57.243146 WARNING: region 1:
9490 08:07:57.250250 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9491 08:07:57.253066 WARNING: region 2:
9492 08:07:57.256602 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9493 08:07:57.260013 WARNING: region 3:
9494 08:07:57.263473 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 08:07:57.266604 WARNING: region 4:
9496 08:07:57.273680 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 08:07:57.273795 WARNING: region 5:
9498 08:07:57.276517 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 08:07:57.280235 WARNING: region 6:
9500 08:07:57.283458 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 08:07:57.283539 WARNING: region 7:
9502 08:07:57.289808 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 08:07:57.296557 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9504 08:07:57.299927 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9505 08:07:57.303130 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9506 08:07:57.310172 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9507 08:07:57.313024 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9508 08:07:57.316997 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9509 08:07:57.323518 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9510 08:07:57.327085 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9511 08:07:57.333280 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9512 08:07:57.336799 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9513 08:07:57.340277 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9514 08:07:57.346893 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9515 08:07:57.350207 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9516 08:07:57.353592 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9517 08:07:57.360001 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9518 08:07:57.363817 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9519 08:07:57.366461 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9520 08:07:57.373694 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9521 08:07:57.376805 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9522 08:07:57.380037 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9523 08:07:57.386631 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9524 08:07:57.390051 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9525 08:07:57.396932 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9526 08:07:57.400369 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9527 08:07:57.406993 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9528 08:07:57.409866 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9529 08:07:57.413701 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9530 08:07:57.420026 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9531 08:07:57.423471 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9532 08:07:57.427261 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9533 08:07:57.433363 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9534 08:07:57.437252 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9535 08:07:57.440286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9536 08:07:57.447100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9537 08:07:57.450087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9538 08:07:57.453714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9539 08:07:57.456882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9540 08:07:57.463862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9541 08:07:57.466955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9542 08:07:57.470480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9543 08:07:57.473778 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9544 08:07:57.480469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9545 08:07:57.483651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9546 08:07:57.487119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9547 08:07:57.490218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9548 08:07:57.497020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9549 08:07:57.500309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9550 08:07:57.503397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9551 08:07:57.510155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9552 08:07:57.513610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9553 08:07:57.516830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9554 08:07:57.523340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9555 08:07:57.526667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9556 08:07:57.533559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9557 08:07:57.536598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9558 08:07:57.543458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9559 08:07:57.547093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9560 08:07:57.549992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9561 08:07:57.557023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9562 08:07:57.560268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9563 08:07:57.567387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9564 08:07:57.570255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9565 08:07:57.577339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9566 08:07:57.580349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9567 08:07:57.586740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9568 08:07:57.590559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9569 08:07:57.593404 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9570 08:07:57.600506 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9571 08:07:57.603510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9572 08:07:57.610257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9573 08:07:57.613789 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9574 08:07:57.617609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9575 08:07:57.623611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9576 08:07:57.627420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9577 08:07:57.634010 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9578 08:07:57.637165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9579 08:07:57.643984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9580 08:07:57.647264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9581 08:07:57.650429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9582 08:07:57.657091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9583 08:07:57.660469 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9584 08:07:57.667141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9585 08:07:57.670953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9586 08:07:57.676739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9587 08:07:57.680375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9588 08:07:57.683799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9589 08:07:57.690363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9590 08:07:57.693965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9591 08:07:57.700536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9592 08:07:57.703514 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9593 08:07:57.710516 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9594 08:07:57.713858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9595 08:07:57.720446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9596 08:07:57.723766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9597 08:07:57.726943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9598 08:07:57.733674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9599 08:07:57.736902 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9600 08:07:57.740433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9601 08:07:57.746935 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9602 08:07:57.750665 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9603 08:07:57.754050 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9604 08:07:57.757408 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9605 08:07:57.764049 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9606 08:07:57.767132 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9607 08:07:57.773888 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9608 08:07:57.777150 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9609 08:07:57.780268 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9610 08:07:57.787044 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9611 08:07:57.790228 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9612 08:07:57.796876 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9613 08:07:57.800402 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9614 08:07:57.803405 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9615 08:07:57.810483 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9616 08:07:57.813491 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9617 08:07:57.820545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9618 08:07:57.823934 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9619 08:07:57.826833 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9620 08:07:57.833358 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9621 08:07:57.836894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9622 08:07:57.840330 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9623 08:07:57.843879 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9624 08:07:57.850522 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9625 08:07:57.853671 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9626 08:07:57.856951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9627 08:07:57.860357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9628 08:07:57.867080 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9629 08:07:57.870671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9630 08:07:57.877114 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9631 08:07:57.880909 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9632 08:07:57.883518 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9633 08:07:57.890192 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9634 08:07:57.893744 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9635 08:07:57.900443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9636 08:07:57.903726 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9637 08:07:57.906921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9638 08:07:57.913556 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9639 08:07:57.916939 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9640 08:07:57.920605 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9641 08:07:57.926815 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9642 08:07:57.930379 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9643 08:07:57.937063 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9644 08:07:57.940361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9645 08:07:57.944025 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9646 08:07:57.950639 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9647 08:07:57.953981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9648 08:07:57.960615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9649 08:07:57.964121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9650 08:07:57.966964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9651 08:07:57.973789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9652 08:07:57.977518 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9653 08:07:57.984187 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9654 08:07:57.987332 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9655 08:07:57.990432 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9656 08:07:57.997244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9657 08:07:58.000636 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9658 08:07:58.004000 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9659 08:07:58.010658 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9660 08:07:58.013934 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9661 08:07:58.020631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9662 08:07:58.023776 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9663 08:07:58.027112 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9664 08:07:58.033830 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9665 08:07:58.037161 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9666 08:07:58.043743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9667 08:07:58.046811 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9668 08:07:58.050243 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9669 08:07:58.057708 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9670 08:07:58.060525 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9671 08:07:58.064062 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9672 08:07:58.070415 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9673 08:07:58.073877 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9674 08:07:58.080768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9675 08:07:58.084077 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9676 08:07:58.087511 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9677 08:07:58.094010 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9678 08:07:58.097428 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9679 08:07:58.100376 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9680 08:07:58.107173 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9681 08:07:58.110479 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9682 08:07:58.117416 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9683 08:07:58.120480 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9684 08:07:58.124105 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9685 08:07:58.130165 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9686 08:07:58.133861 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9687 08:07:58.140549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9688 08:07:58.143575 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9689 08:07:58.146993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9690 08:07:58.153485 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9691 08:07:58.156791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9692 08:07:58.163945 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9693 08:07:58.167413 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9694 08:07:58.170409 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9695 08:07:58.176829 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9696 08:07:58.180435 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9697 08:07:58.187295 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9698 08:07:58.190070 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9699 08:07:58.196728 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9700 08:07:58.200192 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9701 08:07:58.203945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9702 08:07:58.210202 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9703 08:07:58.213787 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9704 08:07:58.220353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9705 08:07:58.223273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9706 08:07:58.226914 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9707 08:07:58.233505 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9708 08:07:58.236736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9709 08:07:58.243490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9710 08:07:58.246685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9711 08:07:58.250352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9712 08:07:58.256537 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9713 08:07:58.260020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9714 08:07:58.266603 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9715 08:07:58.269969 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9716 08:07:58.276386 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9717 08:07:58.279861 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9718 08:07:58.283308 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9719 08:07:58.289643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9720 08:07:58.293122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9721 08:07:58.300025 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9722 08:07:58.303397 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9723 08:07:58.309574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9724 08:07:58.313180 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9725 08:07:58.316684 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9726 08:07:58.323262 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9727 08:07:58.326204 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9728 08:07:58.333049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9729 08:07:58.336150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9730 08:07:58.339294 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9731 08:07:58.346086 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9732 08:07:58.349617 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9733 08:07:58.352942 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9734 08:07:58.356042 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9735 08:07:58.363367 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9736 08:07:58.366127 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9737 08:07:58.369252 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9738 08:07:58.376618 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9739 08:07:58.379453 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9740 08:07:58.383019 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9741 08:07:58.389298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9742 08:07:58.392727 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9743 08:07:58.396083 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9744 08:07:58.402727 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9745 08:07:58.406567 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9746 08:07:58.413286 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9747 08:07:58.416018 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9748 08:07:58.419596 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9749 08:07:58.426084 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9750 08:07:58.429811 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9751 08:07:58.432607 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9752 08:07:58.439222 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9753 08:07:58.442899 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9754 08:07:58.449886 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9755 08:07:58.452694 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9756 08:07:58.455860 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9757 08:07:58.462777 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9758 08:07:58.466023 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9759 08:07:58.469504 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9760 08:07:58.475833 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9761 08:07:58.479529 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9762 08:07:58.482383 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9763 08:07:58.489278 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9764 08:07:58.492563 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9765 08:07:58.498932 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9766 08:07:58.502808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9767 08:07:58.505708 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9768 08:07:58.512390 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9769 08:07:58.515460 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9770 08:07:58.518901 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9771 08:07:58.525782 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9772 08:07:58.528685 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9773 08:07:58.532331 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9774 08:07:58.535768 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9775 08:07:58.542469 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9776 08:07:58.545652 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9777 08:07:58.549399 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9778 08:07:58.552216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9779 08:07:58.555604 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9780 08:07:58.562411 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9781 08:07:58.566038 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9782 08:07:58.569141 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9783 08:07:58.575239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9784 08:07:58.578823 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9785 08:07:58.582055 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9786 08:07:58.588890 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9787 08:07:58.591811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9788 08:07:58.598983 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9789 08:07:58.602062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9790 08:07:58.605300 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9791 08:07:58.611691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9792 08:07:58.615290 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9793 08:07:58.621824 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9794 08:07:58.625246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9795 08:07:58.628844 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9796 08:07:58.635090 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9797 08:07:58.638430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9798 08:07:58.645047 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9799 08:07:58.648634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9800 08:07:58.652436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9801 08:07:58.658710 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9802 08:07:58.662195 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9803 08:07:58.668747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9804 08:07:58.671720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9805 08:07:58.674951 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9806 08:07:58.681843 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9807 08:07:58.685285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9808 08:07:58.691834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9809 08:07:58.695584 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9810 08:07:58.698395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9811 08:07:58.705130 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9812 08:07:58.708661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9813 08:07:58.715152 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9814 08:07:58.718943 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9815 08:07:58.725286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9816 08:07:58.728677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9817 08:07:58.731649 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9818 08:07:58.738389 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9819 08:07:58.741615 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9820 08:07:58.748849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9821 08:07:58.751501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9822 08:07:58.754849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9823 08:07:58.761429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9824 08:07:58.765157 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9825 08:07:58.771750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9826 08:07:58.775046 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9827 08:07:58.778560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9828 08:07:58.785152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9829 08:07:58.788087 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9830 08:07:58.795057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9831 08:07:58.798488 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9832 08:07:58.801470 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9833 08:07:58.808208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9834 08:07:58.811986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9835 08:07:58.818477 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9836 08:07:58.821407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9837 08:07:58.824974 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9838 08:07:58.831575 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9839 08:07:58.834976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9840 08:07:58.841555 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9841 08:07:58.844737 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9842 08:07:58.848150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9843 08:07:58.854819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9844 08:07:58.857896 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9845 08:07:58.864489 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9846 08:07:58.867779 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9847 08:07:58.874585 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9848 08:07:58.877695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9849 08:07:58.881321 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9850 08:07:58.887901 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9851 08:07:58.890840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9852 08:07:58.898102 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9853 08:07:58.901119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9854 08:07:58.904464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9855 08:07:58.910992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9856 08:07:58.913953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9857 08:07:58.920675 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9858 08:07:58.924394 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9859 08:07:58.930981 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9860 08:07:58.934061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9861 08:07:58.937289 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9862 08:07:58.944047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9863 08:07:58.947529 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9864 08:07:58.953998 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9865 08:07:58.957722 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9866 08:07:58.964091 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9867 08:07:58.967746 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9868 08:07:58.970601 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9869 08:07:58.977764 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9870 08:07:58.980783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9871 08:07:58.987317 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9872 08:07:58.990910 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9873 08:07:58.997351 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9874 08:07:59.000871 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9875 08:07:59.004023 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9876 08:07:59.011078 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9877 08:07:59.014459 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9878 08:07:59.020595 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9879 08:07:59.024153 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9880 08:07:59.027762 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9881 08:07:59.034240 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9882 08:07:59.037647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9883 08:07:59.044114 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9884 08:07:59.047689 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9885 08:07:59.054131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9886 08:07:59.057652 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9887 08:07:59.064175 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9888 08:07:59.067205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9889 08:07:59.070802 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9890 08:07:59.077240 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9891 08:07:59.081075 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9892 08:07:59.087439 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9893 08:07:59.090781 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9894 08:07:59.097428 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9895 08:07:59.100997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9896 08:07:59.104017 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9897 08:07:59.111246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9898 08:07:59.113882 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9899 08:07:59.120640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9900 08:07:59.124213 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9901 08:07:59.130829 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9902 08:07:59.133970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9903 08:07:59.137149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9904 08:07:59.144170 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9905 08:07:59.147236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9906 08:07:59.154516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9907 08:07:59.157745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9908 08:07:59.160711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9909 08:07:59.167251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9910 08:07:59.170679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9911 08:07:59.177423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9912 08:07:59.180889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9913 08:07:59.188216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9914 08:07:59.191044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9915 08:07:59.197597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9916 08:07:59.201069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9917 08:07:59.207584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9918 08:07:59.210967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9919 08:07:59.217897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9920 08:07:59.220950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9921 08:07:59.227411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9922 08:07:59.231025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9923 08:07:59.237814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9924 08:07:59.241027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9925 08:07:59.247323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9926 08:07:59.250908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9927 08:07:59.257638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9928 08:07:59.260946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9929 08:07:59.268087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9930 08:07:59.270758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9931 08:07:59.277040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9932 08:07:59.280943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9933 08:07:59.287494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9934 08:07:59.291173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9935 08:07:59.297772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9936 08:07:59.300663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9937 08:07:59.304128 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9938 08:07:59.307626 INFO: [APUAPC] vio 0
9939 08:07:59.310944 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9940 08:07:59.317429 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9941 08:07:59.321043 INFO: [APUAPC] D0_APC_0: 0x400510
9942 08:07:59.324032 INFO: [APUAPC] D0_APC_1: 0x0
9943 08:07:59.327737 INFO: [APUAPC] D0_APC_2: 0x1540
9944 08:07:59.327863 INFO: [APUAPC] D0_APC_3: 0x0
9945 08:07:59.330925 INFO: [APUAPC] D1_APC_0: 0xffffffff
9946 08:07:59.334663 INFO: [APUAPC] D1_APC_1: 0xffffffff
9947 08:07:59.337352 INFO: [APUAPC] D1_APC_2: 0x3fffff
9948 08:07:59.341275 INFO: [APUAPC] D1_APC_3: 0x0
9949 08:07:59.344019 INFO: [APUAPC] D2_APC_0: 0xffffffff
9950 08:07:59.347573 INFO: [APUAPC] D2_APC_1: 0xffffffff
9951 08:07:59.350809 INFO: [APUAPC] D2_APC_2: 0x3fffff
9952 08:07:59.354117 INFO: [APUAPC] D2_APC_3: 0x0
9953 08:07:59.357333 INFO: [APUAPC] D3_APC_0: 0xffffffff
9954 08:07:59.361063 INFO: [APUAPC] D3_APC_1: 0xffffffff
9955 08:07:59.364327 INFO: [APUAPC] D3_APC_2: 0x3fffff
9956 08:07:59.367778 INFO: [APUAPC] D3_APC_3: 0x0
9957 08:07:59.371157 INFO: [APUAPC] D4_APC_0: 0xffffffff
9958 08:07:59.374155 INFO: [APUAPC] D4_APC_1: 0xffffffff
9959 08:07:59.377562 INFO: [APUAPC] D4_APC_2: 0x3fffff
9960 08:07:59.381074 INFO: [APUAPC] D4_APC_3: 0x0
9961 08:07:59.384331 INFO: [APUAPC] D5_APC_0: 0xffffffff
9962 08:07:59.387612 INFO: [APUAPC] D5_APC_1: 0xffffffff
9963 08:07:59.390964 INFO: [APUAPC] D5_APC_2: 0x3fffff
9964 08:07:59.394196 INFO: [APUAPC] D5_APC_3: 0x0
9965 08:07:59.397601 INFO: [APUAPC] D6_APC_0: 0xffffffff
9966 08:07:59.400496 INFO: [APUAPC] D6_APC_1: 0xffffffff
9967 08:07:59.403998 INFO: [APUAPC] D6_APC_2: 0x3fffff
9968 08:07:59.407473 INFO: [APUAPC] D6_APC_3: 0x0
9969 08:07:59.411033 INFO: [APUAPC] D7_APC_0: 0xffffffff
9970 08:07:59.413843 INFO: [APUAPC] D7_APC_1: 0xffffffff
9971 08:07:59.417228 INFO: [APUAPC] D7_APC_2: 0x3fffff
9972 08:07:59.420911 INFO: [APUAPC] D7_APC_3: 0x0
9973 08:07:59.424199 INFO: [APUAPC] D8_APC_0: 0xffffffff
9974 08:07:59.427157 INFO: [APUAPC] D8_APC_1: 0xffffffff
9975 08:07:59.430726 INFO: [APUAPC] D8_APC_2: 0x3fffff
9976 08:07:59.433998 INFO: [APUAPC] D8_APC_3: 0x0
9977 08:07:59.437330 INFO: [APUAPC] D9_APC_0: 0xffffffff
9978 08:07:59.441068 INFO: [APUAPC] D9_APC_1: 0xffffffff
9979 08:07:59.444039 INFO: [APUAPC] D9_APC_2: 0x3fffff
9980 08:07:59.447310 INFO: [APUAPC] D9_APC_3: 0x0
9981 08:07:59.450481 INFO: [APUAPC] D10_APC_0: 0xffffffff
9982 08:07:59.454429 INFO: [APUAPC] D10_APC_1: 0xffffffff
9983 08:07:59.457156 INFO: [APUAPC] D10_APC_2: 0x3fffff
9984 08:07:59.460416 INFO: [APUAPC] D10_APC_3: 0x0
9985 08:07:59.464281 INFO: [APUAPC] D11_APC_0: 0xffffffff
9986 08:07:59.466994 INFO: [APUAPC] D11_APC_1: 0xffffffff
9987 08:07:59.470686 INFO: [APUAPC] D11_APC_2: 0x3fffff
9988 08:07:59.473748 INFO: [APUAPC] D11_APC_3: 0x0
9989 08:07:59.477073 INFO: [APUAPC] D12_APC_0: 0xffffffff
9990 08:07:59.480586 INFO: [APUAPC] D12_APC_1: 0xffffffff
9991 08:07:59.483883 INFO: [APUAPC] D12_APC_2: 0x3fffff
9992 08:07:59.487270 INFO: [APUAPC] D12_APC_3: 0x0
9993 08:07:59.490608 INFO: [APUAPC] D13_APC_0: 0xffffffff
9994 08:07:59.493644 INFO: [APUAPC] D13_APC_1: 0xffffffff
9995 08:07:59.496862 INFO: [APUAPC] D13_APC_2: 0x3fffff
9996 08:07:59.500281 INFO: [APUAPC] D13_APC_3: 0x0
9997 08:07:59.503604 INFO: [APUAPC] D14_APC_0: 0xffffffff
9998 08:07:59.507269 INFO: [APUAPC] D14_APC_1: 0xffffffff
9999 08:07:59.510180 INFO: [APUAPC] D14_APC_2: 0x3fffff
10000 08:07:59.513653 INFO: [APUAPC] D14_APC_3: 0x0
10001 08:07:59.516958 INFO: [APUAPC] D15_APC_0: 0xffffffff
10002 08:07:59.520375 INFO: [APUAPC] D15_APC_1: 0xffffffff
10003 08:07:59.523754 INFO: [APUAPC] D15_APC_2: 0x3fffff
10004 08:07:59.527086 INFO: [APUAPC] D15_APC_3: 0x0
10005 08:07:59.530620 INFO: [APUAPC] APC_CON: 0x4
10006 08:07:59.530738 INFO: [NOCDAPC] D0_APC_0: 0x0
10007 08:07:59.533610 INFO: [NOCDAPC] D0_APC_1: 0x0
10008 08:07:59.537244 INFO: [NOCDAPC] D1_APC_0: 0x0
10009 08:07:59.540470 INFO: [NOCDAPC] D1_APC_1: 0xfff
10010 08:07:59.543846 INFO: [NOCDAPC] D2_APC_0: 0x0
10011 08:07:59.546821 INFO: [NOCDAPC] D2_APC_1: 0xfff
10012 08:07:59.550264 INFO: [NOCDAPC] D3_APC_0: 0x0
10013 08:07:59.553889 INFO: [NOCDAPC] D3_APC_1: 0xfff
10014 08:07:59.556796 INFO: [NOCDAPC] D4_APC_0: 0x0
10015 08:07:59.560316 INFO: [NOCDAPC] D4_APC_1: 0xfff
10016 08:07:59.560397 INFO: [NOCDAPC] D5_APC_0: 0x0
10017 08:07:59.563329 INFO: [NOCDAPC] D5_APC_1: 0xfff
10018 08:07:59.566615 INFO: [NOCDAPC] D6_APC_0: 0x0
10019 08:07:59.570301 INFO: [NOCDAPC] D6_APC_1: 0xfff
10020 08:07:59.573752 INFO: [NOCDAPC] D7_APC_0: 0x0
10021 08:07:59.576777 INFO: [NOCDAPC] D7_APC_1: 0xfff
10022 08:07:59.580325 INFO: [NOCDAPC] D8_APC_0: 0x0
10023 08:07:59.583899 INFO: [NOCDAPC] D8_APC_1: 0xfff
10024 08:07:59.587308 INFO: [NOCDAPC] D9_APC_0: 0x0
10025 08:07:59.589945 INFO: [NOCDAPC] D9_APC_1: 0xfff
10026 08:07:59.593705 INFO: [NOCDAPC] D10_APC_0: 0x0
10027 08:07:59.596750 INFO: [NOCDAPC] D10_APC_1: 0xfff
10028 08:07:59.596875 INFO: [NOCDAPC] D11_APC_0: 0x0
10029 08:07:59.600094 INFO: [NOCDAPC] D11_APC_1: 0xfff
10030 08:07:59.603138 INFO: [NOCDAPC] D12_APC_0: 0x0
10031 08:07:59.606309 INFO: [NOCDAPC] D12_APC_1: 0xfff
10032 08:07:59.610136 INFO: [NOCDAPC] D13_APC_0: 0x0
10033 08:07:59.613411 INFO: [NOCDAPC] D13_APC_1: 0xfff
10034 08:07:59.616720 INFO: [NOCDAPC] D14_APC_0: 0x0
10035 08:07:59.619609 INFO: [NOCDAPC] D14_APC_1: 0xfff
10036 08:07:59.622930 INFO: [NOCDAPC] D15_APC_0: 0x0
10037 08:07:59.626612 INFO: [NOCDAPC] D15_APC_1: 0xfff
10038 08:07:59.629609 INFO: [NOCDAPC] APC_CON: 0x4
10039 08:07:59.632900 INFO: [APUAPC] set_apusys_apc done
10040 08:07:59.636446 INFO: [DEVAPC] devapc_init done
10041 08:07:59.639924 INFO: GICv3 without legacy support detected.
10042 08:07:59.642781 INFO: ARM GICv3 driver initialized in EL3
10043 08:07:59.646248 INFO: Maximum SPI INTID supported: 639
10044 08:07:59.653289 INFO: BL31: Initializing runtime services
10045 08:07:59.656600 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10046 08:07:59.659609 INFO: SPM: enable CPC mode
10047 08:07:59.666077 INFO: mcdi ready for mcusys-off-idle and system suspend
10048 08:07:59.669534 INFO: BL31: Preparing for EL3 exit to normal world
10049 08:07:59.673051 INFO: Entry point address = 0x80000000
10050 08:07:59.676281 INFO: SPSR = 0x8
10051 08:07:59.681017
10052 08:07:59.681147
10053 08:07:59.681268
10054 08:07:59.684497 Starting depthcharge on Spherion...
10055 08:07:59.684622
10056 08:07:59.684760 Wipe memory regions:
10057 08:07:59.684868
10058 08:07:59.685838 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10059 08:07:59.685994 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10060 08:07:59.686493 Setting prompt string to ['asurada:']
10061 08:07:59.686642 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10062 08:07:59.687928 [0x00000040000000, 0x00000054600000)
10063 08:07:59.810159
10064 08:07:59.810334 [0x00000054660000, 0x00000080000000)
10065 08:08:00.070967
10066 08:08:00.071102 [0x000000821a7280, 0x000000ffe64000)
10067 08:08:00.816015
10068 08:08:00.816226 [0x00000100000000, 0x00000240000000)
10069 08:08:02.706367
10070 08:08:02.709587 Initializing XHCI USB controller at 0x11200000.
10071 08:08:03.747621
10072 08:08:03.750576 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10073 08:08:03.750659
10074 08:08:03.750723
10075 08:08:03.750784
10076 08:08:03.751062 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 08:08:03.851386 asurada: tftpboot 192.168.201.1 11585998/tftp-deploy-rtj41f8m/kernel/image.itb 11585998/tftp-deploy-rtj41f8m/kernel/cmdline
10079 08:08:03.851578 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 08:08:03.851719 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10081 08:08:03.856195 tftpboot 192.168.201.1 11585998/tftp-deploy-rtj41f8m/kernel/image.ittp-deploy-rtj41f8m/kernel/cmdline
10082 08:08:03.856323
10083 08:08:03.856436 Waiting for link
10084 08:08:04.016681
10085 08:08:04.016858 R8152: Initializing
10086 08:08:04.016977
10087 08:08:04.019620 Version 9 (ocp_data = 6010)
10088 08:08:04.019745
10089 08:08:04.023235 R8152: Done initializing
10090 08:08:04.023354
10091 08:08:04.023464 Adding net device
10092 08:08:05.895603
10093 08:08:05.895758 done.
10094 08:08:05.895874
10095 08:08:05.895965 MAC: 00:e0:4c:78:7a:aa
10096 08:08:05.896024
10097 08:08:05.898709 Sending DHCP discover... done.
10098 08:08:05.898815
10099 08:08:08.906380 Waiting for reply... done.
10100 08:08:08.906532
10101 08:08:08.906599 Sending DHCP request... done.
10102 08:08:08.909242
10103 08:08:08.909324 Waiting for reply... done.
10104 08:08:08.909389
10105 08:08:08.912842 My ip is 192.168.201.12
10106 08:08:08.912923
10107 08:08:08.916009 The DHCP server ip is 192.168.201.1
10108 08:08:08.916091
10109 08:08:08.919260 TFTP server IP predefined by user: 192.168.201.1
10110 08:08:08.919342
10111 08:08:08.926102 Bootfile predefined by user: 11585998/tftp-deploy-rtj41f8m/kernel/image.itb
10112 08:08:08.926184
10113 08:08:08.928996 Sending tftp read request... done.
10114 08:08:08.929077
10115 08:08:08.932475 Waiting for the transfer...
10116 08:08:08.932556
10117 08:08:09.206526 00000000 ################################################################
10118 08:08:09.206669
10119 08:08:09.492987 00080000 ################################################################
10120 08:08:09.493133
10121 08:08:09.786475 00100000 ################################################################
10122 08:08:09.786686
10123 08:08:10.056914 00180000 ################################################################
10124 08:08:10.057054
10125 08:08:10.350980 00200000 ################################################################
10126 08:08:10.351122
10127 08:08:10.634633 00280000 ################################################################
10128 08:08:10.634772
10129 08:08:10.900180 00300000 ################################################################
10130 08:08:10.900346
10131 08:08:11.171399 00380000 ################################################################
10132 08:08:11.171595
10133 08:08:11.444967 00400000 ################################################################
10134 08:08:11.445109
10135 08:08:11.712801 00480000 ################################################################
10136 08:08:11.712997
10137 08:08:11.995061 00500000 ################################################################
10138 08:08:11.995202
10139 08:08:12.285999 00580000 ################################################################
10140 08:08:12.286141
10141 08:08:12.568123 00600000 ################################################################
10142 08:08:12.568267
10143 08:08:12.852398 00680000 ################################################################
10144 08:08:12.852532
10145 08:08:13.124368 00700000 ################################################################
10146 08:08:13.124503
10147 08:08:13.413107 00780000 ################################################################
10148 08:08:13.413240
10149 08:08:13.713045 00800000 ################################################################
10150 08:08:13.713210
10151 08:08:14.008271 00880000 ################################################################
10152 08:08:14.008399
10153 08:08:14.305024 00900000 ################################################################
10154 08:08:14.305158
10155 08:08:14.603451 00980000 ################################################################
10156 08:08:14.603586
10157 08:08:14.870627 00a00000 ################################################################
10158 08:08:14.870760
10159 08:08:15.136603 00a80000 ################################################################
10160 08:08:15.136792
10161 08:08:15.409257 00b00000 ################################################################
10162 08:08:15.409391
10163 08:08:15.691082 00b80000 ################################################################
10164 08:08:15.691254
10165 08:08:15.942533 00c00000 ################################################################
10166 08:08:15.942665
10167 08:08:16.209273 00c80000 ################################################################
10168 08:08:16.209405
10169 08:08:16.489592 00d00000 ################################################################
10170 08:08:16.489731
10171 08:08:16.768538 00d80000 ################################################################
10172 08:08:16.768671
10173 08:08:17.052245 00e00000 ################################################################
10174 08:08:17.052384
10175 08:08:17.326669 00e80000 ################################################################
10176 08:08:17.326802
10177 08:08:17.595264 00f00000 ################################################################
10178 08:08:17.595396
10179 08:08:17.858322 00f80000 ################################################################
10180 08:08:17.858455
10181 08:08:18.116510 01000000 ################################################################
10182 08:08:18.116645
10183 08:08:18.381294 01080000 ################################################################
10184 08:08:18.381430
10185 08:08:18.655386 01100000 ################################################################
10186 08:08:18.655555
10187 08:08:18.944429 01180000 ################################################################
10188 08:08:18.944571
10189 08:08:19.226027 01200000 ################################################################
10190 08:08:19.226178
10191 08:08:19.521507 01280000 ################################################################
10192 08:08:19.521654
10193 08:08:19.819402 01300000 ################################################################
10194 08:08:19.819548
10195 08:08:20.111410 01380000 ################################################################
10196 08:08:20.111559
10197 08:08:20.397482 01400000 ################################################################
10198 08:08:20.397654
10199 08:08:20.679982 01480000 ################################################################
10200 08:08:20.680183
10201 08:08:20.945698 01500000 ################################################################
10202 08:08:20.945846
10203 08:08:21.218300 01580000 ################################################################
10204 08:08:21.218504
10205 08:08:21.490563 01600000 ################################################################
10206 08:08:21.490700
10207 08:08:21.759180 01680000 ################################################################
10208 08:08:21.759381
10209 08:08:22.028988 01700000 ################################################################
10210 08:08:22.029187
10211 08:08:22.309577 01780000 ################################################################
10212 08:08:22.309724
10213 08:08:22.572465 01800000 ################################################################
10214 08:08:22.572632
10215 08:08:22.837101 01880000 ################################################################
10216 08:08:22.837244
10217 08:08:23.097613 01900000 ################################################################
10218 08:08:23.097753
10219 08:08:23.356534 01980000 ################################################################
10220 08:08:23.356740
10221 08:08:23.616095 01a00000 ################################################################
10222 08:08:23.616264
10223 08:08:23.871050 01a80000 ################################################################
10224 08:08:23.871194
10225 08:08:24.133336 01b00000 ################################################################
10226 08:08:24.133526
10227 08:08:24.156375 01b80000 ###### done.
10228 08:08:24.156513
10229 08:08:24.159597 The bootfile was 28882174 bytes long.
10230 08:08:24.159758
10231 08:08:24.162696 Sending tftp read request... done.
10232 08:08:24.162815
10233 08:08:24.166027 Waiting for the transfer...
10234 08:08:24.166148
10235 08:08:24.169244 00000000 # done.
10236 08:08:24.169370
10237 08:08:24.176145 Command line loaded dynamically from TFTP file: 11585998/tftp-deploy-rtj41f8m/kernel/cmdline
10238 08:08:24.176271
10239 08:08:24.199434 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10240 08:08:24.199563
10241 08:08:24.199705 Loading FIT.
10242 08:08:24.199829
10243 08:08:24.202140 Image ramdisk-1 has 17787594 bytes.
10244 08:08:24.202260
10245 08:08:24.205704 Image fdt-1 has 47278 bytes.
10246 08:08:24.205825
10247 08:08:24.209321 Image kernel-1 has 11045265 bytes.
10248 08:08:24.209442
10249 08:08:24.215585 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10250 08:08:24.218776
10251 08:08:24.235475 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10252 08:08:24.235607
10253 08:08:24.238722 Choosing best match conf-1 for compat google,spherion-rev2.
10254 08:08:24.244448
10255 08:08:24.249285 Connected to device vid:did:rid of 1ae0:0028:00
10256 08:08:24.256982
10257 08:08:24.260357 tpm_get_response: command 0x17b, return code 0x0
10258 08:08:24.260478
10259 08:08:24.263836 ec_init: CrosEC protocol v3 supported (256, 248)
10260 08:08:24.267823
10261 08:08:24.271348 tpm_cleanup: add release locality here.
10262 08:08:24.271468
10263 08:08:24.271581 Shutting down all USB controllers.
10264 08:08:24.274629
10265 08:08:24.274748 Removing current net device
10266 08:08:24.274861
10267 08:08:24.281038 Exiting depthcharge with code 4 at timestamp: 53853278
10268 08:08:24.281162
10269 08:08:24.284310 LZMA decompressing kernel-1 to 0x821a6718
10270 08:08:24.284431
10271 08:08:24.287235 LZMA decompressing kernel-1 to 0x40000000
10272 08:08:25.675499
10273 08:08:25.675733 jumping to kernel
10274 08:08:25.676331 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10275 08:08:25.676491 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10276 08:08:25.676622 Setting prompt string to ['Linux version [0-9]']
10277 08:08:25.676743 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 08:08:25.676867 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 08:08:25.757282
10280 08:08:25.760768 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10281 08:08:25.764496 start: 2.2.5.1 login-action (timeout 00:03:59) [common]
10282 08:08:25.764633 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 08:08:25.764755 Setting prompt string to []
10284 08:08:25.764886 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10285 08:08:25.765013 Using line separator: #'\n'#
10286 08:08:25.765120 No login prompt set.
10287 08:08:25.765236 Parsing kernel messages
10288 08:08:25.765342 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10289 08:08:25.765531 [login-action] Waiting for messages, (timeout 00:03:59)
10290 08:08:25.784248 [ 0.000000] Linux version 6.1.54-cip6 (KernelCI@build-j53272-arm64-gcc-10-defconfig-arm64-chromebook-xzlx8) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023
10291 08:08:25.787134 [ 0.000000] random: crng init done
10292 08:08:25.793602 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10293 08:08:25.796894 [ 0.000000] efi: UEFI not found.
10294 08:08:25.804102 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10295 08:08:25.810340 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10296 08:08:25.820614 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10297 08:08:25.830337 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10298 08:08:25.836927 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10299 08:08:25.843492 [ 0.000000] printk: bootconsole [mtk8250] enabled
10300 08:08:25.846970 [ 0.000000] NUMA: No NUMA configuration found
10301 08:08:25.856502 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10302 08:08:25.860066 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10303 08:08:25.863649 [ 0.000000] Zone ranges:
10304 08:08:25.870057 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10305 08:08:25.872953 [ 0.000000] DMA32 empty
10306 08:08:25.879835 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10307 08:08:25.883068 [ 0.000000] Movable zone start for each node
10308 08:08:25.886607 [ 0.000000] Early memory node ranges
10309 08:08:25.893274 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10310 08:08:25.899674 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10311 08:08:25.906347 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10312 08:08:25.912959 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10313 08:08:25.916333 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10314 08:08:25.926030 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10315 08:08:25.981462 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10316 08:08:25.988111 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10317 08:08:25.994916 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10318 08:08:25.998515 [ 0.000000] psci: probing for conduit method from DT.
10319 08:08:26.004807 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10320 08:08:26.008251 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10321 08:08:26.015022 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10322 08:08:26.018241 [ 0.000000] psci: SMC Calling Convention v1.2
10323 08:08:26.024985 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10324 08:08:26.028003 [ 0.000000] Detected VIPT I-cache on CPU0
10325 08:08:26.035037 [ 0.000000] CPU features: detected: GIC system register CPU interface
10326 08:08:26.041407 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10327 08:08:26.047622 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10328 08:08:26.054303 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10329 08:08:26.061098 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10330 08:08:26.070836 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10331 08:08:26.074285 [ 0.000000] alternatives: applying boot alternatives
10332 08:08:26.081287 [ 0.000000] Fallback order for Node 0: 0
10333 08:08:26.087770 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10334 08:08:26.091058 [ 0.000000] Policy zone: Normal
10335 08:08:26.114228 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10336 08:08:26.123494 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10337 08:08:26.134389 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10338 08:08:26.144602 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10339 08:08:26.150813 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10340 08:08:26.153722 <6>[ 0.000000] software IO TLB: area num 8.
10341 08:08:26.211238 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10342 08:08:26.360061 <6>[ 0.000000] Memory: 7952060K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 400708K reserved, 32768K cma-reserved)
10343 08:08:26.366602 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10344 08:08:26.373378 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10345 08:08:26.376598 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10346 08:08:26.383247 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10347 08:08:26.390249 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10348 08:08:26.393351 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10349 08:08:26.403523 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10350 08:08:26.409797 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10351 08:08:26.416636 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10352 08:08:26.423457 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10353 08:08:26.426380 <6>[ 0.000000] GICv3: 608 SPIs implemented
10354 08:08:26.429817 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10355 08:08:26.436307 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10356 08:08:26.439532 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10357 08:08:26.446451 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10358 08:08:26.459278 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10359 08:08:26.469447 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10360 08:08:26.479604 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10361 08:08:26.486876 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10362 08:08:26.500369 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10363 08:08:26.506763 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10364 08:08:26.513436 <6>[ 0.009181] Console: colour dummy device 80x25
10365 08:08:26.523432 <6>[ 0.013934] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10366 08:08:26.530170 <6>[ 0.024441] pid_max: default: 32768 minimum: 301
10367 08:08:26.533333 <6>[ 0.029343] LSM: Security Framework initializing
10368 08:08:26.540141 <6>[ 0.034280] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10369 08:08:26.549927 <6>[ 0.042094] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 08:08:26.556585 <6>[ 0.051504] cblist_init_generic: Setting adjustable number of callback queues.
10371 08:08:26.563340 <6>[ 0.058947] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 08:08:26.573186 <6>[ 0.065285] cblist_init_generic: Setting adjustable number of callback queues.
10373 08:08:26.579714 <6>[ 0.072712] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 08:08:26.583377 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10375 08:08:26.589356 <6>[ 0.084157] rcu: Max phase no-delay instances is 1000.
10376 08:08:26.596000 <6>[ 0.091187] EFI services will not be available.
10377 08:08:26.599271 <6>[ 0.096146] smp: Bringing up secondary CPUs ...
10378 08:08:26.607449 <6>[ 0.101196] Detected VIPT I-cache on CPU1
10379 08:08:26.614602 <6>[ 0.101267] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10380 08:08:26.620775 <6>[ 0.101297] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10381 08:08:26.624418 <6>[ 0.101636] Detected VIPT I-cache on CPU2
10382 08:08:26.630953 <6>[ 0.101688] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10383 08:08:26.637821 <6>[ 0.101706] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10384 08:08:26.644081 <6>[ 0.101963] Detected VIPT I-cache on CPU3
10385 08:08:26.650616 <6>[ 0.102011] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10386 08:08:26.657254 <6>[ 0.102025] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10387 08:08:26.660784 <6>[ 0.102329] CPU features: detected: Spectre-v4
10388 08:08:26.667319 <6>[ 0.102335] CPU features: detected: Spectre-BHB
10389 08:08:26.670851 <6>[ 0.102340] Detected PIPT I-cache on CPU4
10390 08:08:26.677192 <6>[ 0.102396] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10391 08:08:26.684334 <6>[ 0.102413] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10392 08:08:26.690520 <6>[ 0.102708] Detected PIPT I-cache on CPU5
10393 08:08:26.697145 <6>[ 0.102772] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10394 08:08:26.703764 <6>[ 0.102789] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10395 08:08:26.707165 <6>[ 0.103069] Detected PIPT I-cache on CPU6
10396 08:08:26.713563 <6>[ 0.103133] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10397 08:08:26.720662 <6>[ 0.103149] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10398 08:08:26.727184 <6>[ 0.103446] Detected PIPT I-cache on CPU7
10399 08:08:26.734057 <6>[ 0.103510] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10400 08:08:26.740382 <6>[ 0.103526] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10401 08:08:26.743599 <6>[ 0.103575] smp: Brought up 1 node, 8 CPUs
10402 08:08:26.750004 <6>[ 0.244843] SMP: Total of 8 processors activated.
10403 08:08:26.753595 <6>[ 0.249763] CPU features: detected: 32-bit EL0 Support
10404 08:08:26.763797 <6>[ 0.255125] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10405 08:08:26.770014 <6>[ 0.263926] CPU features: detected: Common not Private translations
10406 08:08:26.773229 <6>[ 0.270401] CPU features: detected: CRC32 instructions
10407 08:08:26.780169 <6>[ 0.275786] CPU features: detected: RCpc load-acquire (LDAPR)
10408 08:08:26.786418 <6>[ 0.281745] CPU features: detected: LSE atomic instructions
10409 08:08:26.793098 <6>[ 0.287527] CPU features: detected: Privileged Access Never
10410 08:08:26.796711 <6>[ 0.293343] CPU features: detected: RAS Extension Support
10411 08:08:26.806392 <6>[ 0.298951] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10412 08:08:26.809937 <6>[ 0.306174] CPU: All CPU(s) started at EL2
10413 08:08:26.816787 <6>[ 0.310491] alternatives: applying system-wide alternatives
10414 08:08:26.825569 <6>[ 0.321198] devtmpfs: initialized
10415 08:08:26.841186 <6>[ 0.330161] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10416 08:08:26.847216 <6>[ 0.340123] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10417 08:08:26.854045 <6>[ 0.348389] pinctrl core: initialized pinctrl subsystem
10418 08:08:26.857003 <6>[ 0.355033] DMI not present or invalid.
10419 08:08:26.864357 <6>[ 0.359448] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10420 08:08:26.873738 <6>[ 0.366340] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10421 08:08:26.880686 <6>[ 0.373908] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10422 08:08:26.890446 <6>[ 0.382137] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10423 08:08:26.894042 <6>[ 0.390381] audit: initializing netlink subsys (disabled)
10424 08:08:26.903550 <5>[ 0.396073] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10425 08:08:26.910378 <6>[ 0.396767] thermal_sys: Registered thermal governor 'step_wise'
10426 08:08:26.917089 <6>[ 0.404043] thermal_sys: Registered thermal governor 'power_allocator'
10427 08:08:26.920339 <6>[ 0.410295] cpuidle: using governor menu
10428 08:08:26.926787 <6>[ 0.421255] NET: Registered PF_QIPCRTR protocol family
10429 08:08:26.933369 <6>[ 0.426747] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10430 08:08:26.940167 <6>[ 0.433852] ASID allocator initialised with 32768 entries
10431 08:08:26.943447 <6>[ 0.440415] Serial: AMBA PL011 UART driver
10432 08:08:26.953183 <4>[ 0.449189] Trying to register duplicate clock ID: 134
10433 08:08:27.007393 <6>[ 0.506831] KASLR enabled
10434 08:08:27.021577 <6>[ 0.514547] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10435 08:08:27.028348 <6>[ 0.521561] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10436 08:08:27.035177 <6>[ 0.528052] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10437 08:08:27.041474 <6>[ 0.535056] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10438 08:08:27.048206 <6>[ 0.541543] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10439 08:08:27.054940 <6>[ 0.548546] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10440 08:08:27.061389 <6>[ 0.555035] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10441 08:08:27.068063 <6>[ 0.562039] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10442 08:08:27.071031 <6>[ 0.569560] ACPI: Interpreter disabled.
10443 08:08:27.080059 <6>[ 0.575955] iommu: Default domain type: Translated
10444 08:08:27.086632 <6>[ 0.581066] iommu: DMA domain TLB invalidation policy: strict mode
10445 08:08:27.090156 <5>[ 0.587726] SCSI subsystem initialized
10446 08:08:27.096336 <6>[ 0.591870] usbcore: registered new interface driver usbfs
10447 08:08:27.103294 <6>[ 0.597603] usbcore: registered new interface driver hub
10448 08:08:27.106902 <6>[ 0.603154] usbcore: registered new device driver usb
10449 08:08:27.113052 <6>[ 0.609244] pps_core: LinuxPPS API ver. 1 registered
10450 08:08:27.122943 <6>[ 0.614439] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10451 08:08:27.126622 <6>[ 0.623784] PTP clock support registered
10452 08:08:27.129851 <6>[ 0.628027] EDAC MC: Ver: 3.0.0
10453 08:08:27.137272 <6>[ 0.633203] FPGA manager framework
10454 08:08:27.140827 <6>[ 0.636884] Advanced Linux Sound Architecture Driver Initialized.
10455 08:08:27.144169 <6>[ 0.643663] vgaarb: loaded
10456 08:08:27.151238 <6>[ 0.646849] clocksource: Switched to clocksource arch_sys_counter
10457 08:08:27.157915 <5>[ 0.653291] VFS: Disk quotas dquot_6.6.0
10458 08:08:27.164605 <6>[ 0.657480] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10459 08:08:27.167949 <6>[ 0.664670] pnp: PnP ACPI: disabled
10460 08:08:27.175868 <6>[ 0.671403] NET: Registered PF_INET protocol family
10461 08:08:27.185115 <6>[ 0.677012] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10462 08:08:27.196481 <6>[ 0.689310] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10463 08:08:27.206407 <6>[ 0.698124] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10464 08:08:27.213102 <6>[ 0.706092] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10465 08:08:27.220100 <6>[ 0.714788] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10466 08:08:27.232124 <6>[ 0.724531] TCP: Hash tables configured (established 65536 bind 65536)
10467 08:08:27.238693 <6>[ 0.731393] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 08:08:27.245455 <6>[ 0.738592] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10469 08:08:27.251852 <6>[ 0.746294] NET: Registered PF_UNIX/PF_LOCAL protocol family
10470 08:08:27.258698 <6>[ 0.752470] RPC: Registered named UNIX socket transport module.
10471 08:08:27.261997 <6>[ 0.758625] RPC: Registered udp transport module.
10472 08:08:27.268790 <6>[ 0.763559] RPC: Registered tcp transport module.
10473 08:08:27.274865 <6>[ 0.768491] RPC: Registered tcp NFSv4.1 backchannel transport module.
10474 08:08:27.278432 <6>[ 0.775159] PCI: CLS 0 bytes, default 64
10475 08:08:27.281488 <6>[ 0.779565] Unpacking initramfs...
10476 08:08:27.305966 <6>[ 0.798971] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10477 08:08:27.316466 <6>[ 0.807634] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10478 08:08:27.319239 <6>[ 0.816485] kvm [1]: IPA Size Limit: 40 bits
10479 08:08:27.326220 <6>[ 0.821015] kvm [1]: GICv3: no GICV resource entry
10480 08:08:27.329562 <6>[ 0.826037] kvm [1]: disabling GICv2 emulation
10481 08:08:27.335753 <6>[ 0.830726] kvm [1]: GIC system register CPU interface enabled
10482 08:08:27.339286 <6>[ 0.836888] kvm [1]: vgic interrupt IRQ18
10483 08:08:27.346165 <6>[ 0.841243] kvm [1]: VHE mode initialized successfully
10484 08:08:27.352356 <5>[ 0.847658] Initialise system trusted keyrings
10485 08:08:27.359099 <6>[ 0.852470] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10486 08:08:27.366280 <6>[ 0.862387] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10487 08:08:27.372851 <5>[ 0.868825] NFS: Registering the id_resolver key type
10488 08:08:27.376591 <5>[ 0.874129] Key type id_resolver registered
10489 08:08:27.382797 <5>[ 0.878545] Key type id_legacy registered
10490 08:08:27.389650 <6>[ 0.882823] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10491 08:08:27.396303 <6>[ 0.889744] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10492 08:08:27.402771 <6>[ 0.897472] 9p: Installing v9fs 9p2000 file system support
10493 08:08:27.439317 <5>[ 0.935276] Key type asymmetric registered
10494 08:08:27.442704 <5>[ 0.939607] Asymmetric key parser 'x509' registered
10495 08:08:27.452829 <6>[ 0.944774] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10496 08:08:27.455552 <6>[ 0.952394] io scheduler mq-deadline registered
10497 08:08:27.459051 <6>[ 0.957163] io scheduler kyber registered
10498 08:08:27.478061 <6>[ 0.974286] EINJ: ACPI disabled.
10499 08:08:27.510634 <4>[ 0.999954] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 08:08:27.520555 <4>[ 1.010591] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 08:08:27.535879 <6>[ 1.031505] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10502 08:08:27.543764 <6>[ 1.039576] printk: console [ttyS0] disabled
10503 08:08:27.571258 <6>[ 1.064211] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10504 08:08:27.578242 <6>[ 1.073688] printk: console [ttyS0] enabled
10505 08:08:27.581380 <6>[ 1.073688] printk: console [ttyS0] enabled
10506 08:08:27.587878 <6>[ 1.082582] printk: bootconsole [mtk8250] disabled
10507 08:08:27.591291 <6>[ 1.082582] printk: bootconsole [mtk8250] disabled
10508 08:08:27.598197 <6>[ 1.093875] SuperH (H)SCI(F) driver initialized
10509 08:08:27.601215 <6>[ 1.099201] msm_serial: driver initialized
10510 08:08:27.615558 <6>[ 1.108217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10511 08:08:27.625287 <6>[ 1.116764] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10512 08:08:27.632055 <6>[ 1.125312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10513 08:08:27.641987 <6>[ 1.133942] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10514 08:08:27.652083 <6>[ 1.142654] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10515 08:08:27.658703 <6>[ 1.151367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10516 08:08:27.668463 <6>[ 1.159908] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10517 08:08:27.675238 <6>[ 1.168731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10518 08:08:27.685211 <6>[ 1.177276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10519 08:08:27.697033 <6>[ 1.193000] loop: module loaded
10520 08:08:27.703277 <6>[ 1.199033] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10521 08:08:27.726532 <4>[ 1.222523] mtk-pmic-keys: Failed to locate of_node [id: -1]
10522 08:08:27.733598 <6>[ 1.229278] megasas: 07.719.03.00-rc1
10523 08:08:27.742802 <6>[ 1.238889] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10524 08:08:27.750458 <6>[ 1.246231] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10525 08:08:27.766759 <6>[ 1.262776] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10526 08:08:27.823012 <6>[ 1.312710] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10527 08:08:28.019244 <6>[ 1.515431] Freeing initrd memory: 17364K
10528 08:08:28.029612 <6>[ 1.525855] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10529 08:08:28.040932 <6>[ 1.536765] tun: Universal TUN/TAP device driver, 1.6
10530 08:08:28.043945 <6>[ 1.542818] thunder_xcv, ver 1.0
10531 08:08:28.047363 <6>[ 1.546320] thunder_bgx, ver 1.0
10532 08:08:28.050639 <6>[ 1.549818] nicpf, ver 1.0
10533 08:08:28.061209 <6>[ 1.553832] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10534 08:08:28.064510 <6>[ 1.561307] hns3: Copyright (c) 2017 Huawei Corporation.
10535 08:08:28.067984 <6>[ 1.566897] hclge is initializing
10536 08:08:28.074805 <6>[ 1.570475] e1000: Intel(R) PRO/1000 Network Driver
10537 08:08:28.081294 <6>[ 1.575606] e1000: Copyright (c) 1999-2006 Intel Corporation.
10538 08:08:28.084556 <6>[ 1.581617] e1000e: Intel(R) PRO/1000 Network Driver
10539 08:08:28.091429 <6>[ 1.586832] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10540 08:08:28.097811 <6>[ 1.593016] igb: Intel(R) Gigabit Ethernet Network Driver
10541 08:08:28.104445 <6>[ 1.598666] igb: Copyright (c) 2007-2014 Intel Corporation.
10542 08:08:28.110997 <6>[ 1.604501] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10543 08:08:28.114895 <6>[ 1.611019] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10544 08:08:28.121592 <6>[ 1.617490] sky2: driver version 1.30
10545 08:08:28.128008 <6>[ 1.622488] VFIO - User Level meta-driver version: 0.3
10546 08:08:28.134558 <6>[ 1.630741] usbcore: registered new interface driver usb-storage
10547 08:08:28.141514 <6>[ 1.637186] usbcore: registered new device driver onboard-usb-hub
10548 08:08:28.150461 <6>[ 1.646320] mt6397-rtc mt6359-rtc: registered as rtc0
10549 08:08:28.160136 <6>[ 1.651786] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T08:07:00 UTC (1695283620)
10550 08:08:28.163537 <6>[ 1.661345] i2c_dev: i2c /dev entries driver
10551 08:08:28.180212 <6>[ 1.673014] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10552 08:08:28.199928 <6>[ 1.696006] cpu cpu0: EM: created perf domain
10553 08:08:28.203110 <6>[ 1.700924] cpu cpu4: EM: created perf domain
10554 08:08:28.210558 <6>[ 1.706493] sdhci: Secure Digital Host Controller Interface driver
10555 08:08:28.217337 <6>[ 1.712925] sdhci: Copyright(c) Pierre Ossman
10556 08:08:28.223792 <6>[ 1.717880] Synopsys Designware Multimedia Card Interface Driver
10557 08:08:28.230587 <6>[ 1.724517] sdhci-pltfm: SDHCI platform and OF driver helper
10558 08:08:28.233571 <6>[ 1.724647] mmc0: CQHCI version 5.10
10559 08:08:28.240593 <6>[ 1.734804] ledtrig-cpu: registered to indicate activity on CPUs
10560 08:08:28.247380 <6>[ 1.741758] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10561 08:08:28.253920 <6>[ 1.748828] usbcore: registered new interface driver usbhid
10562 08:08:28.257552 <6>[ 1.754653] usbhid: USB HID core driver
10563 08:08:28.263767 <6>[ 1.758877] spi_master spi0: will run message pump with realtime priority
10564 08:08:28.308212 <6>[ 1.797522] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10565 08:08:28.327525 <6>[ 1.813750] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10566 08:08:28.330993 <6>[ 1.827380] mmc0: Command Queue Engine enabled
10567 08:08:28.337906 <6>[ 1.832148] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10568 08:08:28.344395 <6>[ 1.839497] mmcblk0: mmc0:0001 DA4128 116 GiB
10569 08:08:28.347806 <6>[ 1.844337] cros-ec-spi spi0.0: Chrome EC device registered
10570 08:08:28.354361 <6>[ 1.848291] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10571 08:08:28.361849 <6>[ 1.858129] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10572 08:08:28.368856 <6>[ 1.864084] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10573 08:08:28.375173 <6>[ 1.870242] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10574 08:08:28.394378 <6>[ 1.887027] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10575 08:08:28.401964 <6>[ 1.897739] NET: Registered PF_PACKET protocol family
10576 08:08:28.404922 <6>[ 1.903125] 9pnet: Installing 9P2000 support
10577 08:08:28.411745 <5>[ 1.907688] Key type dns_resolver registered
10578 08:08:28.414829 <6>[ 1.912689] registered taskstats version 1
10579 08:08:28.421549 <5>[ 1.917070] Loading compiled-in X.509 certificates
10580 08:08:28.453135 <4>[ 1.942319] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 08:08:28.462840 <4>[ 1.953241] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 08:08:28.469661 <3>[ 1.963781] debugfs: File 'uA_load' in directory '/' already present!
10583 08:08:28.476205 <3>[ 1.970482] debugfs: File 'min_uV' in directory '/' already present!
10584 08:08:28.482893 <3>[ 1.977088] debugfs: File 'max_uV' in directory '/' already present!
10585 08:08:28.489182 <3>[ 1.983695] debugfs: File 'constraint_flags' in directory '/' already present!
10586 08:08:28.500902 <3>[ 1.993528] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10587 08:08:28.513903 <6>[ 2.009986] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10588 08:08:28.520663 <6>[ 2.016742] xhci-mtk 11200000.usb: xHCI Host Controller
10589 08:08:28.527047 <6>[ 2.022263] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10590 08:08:28.537603 <6>[ 2.030223] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10591 08:08:28.544203 <6>[ 2.039677] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10592 08:08:28.550748 <6>[ 2.045754] xhci-mtk 11200000.usb: xHCI Host Controller
10593 08:08:28.557960 <6>[ 2.051233] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10594 08:08:28.564384 <6>[ 2.058882] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10595 08:08:28.570719 <6>[ 2.066601] hub 1-0:1.0: USB hub found
10596 08:08:28.573852 <6>[ 2.070623] hub 1-0:1.0: 1 port detected
10597 08:08:28.580790 <6>[ 2.074913] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10598 08:08:28.587336 <6>[ 2.083554] hub 2-0:1.0: USB hub found
10599 08:08:28.590718 <6>[ 2.087573] hub 2-0:1.0: 1 port detected
10600 08:08:28.598148 <6>[ 2.094231] mtk-msdc 11f70000.mmc: Got CD GPIO
10601 08:08:28.610381 <6>[ 2.102977] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 08:08:28.617135 <6>[ 2.111007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 08:08:28.626879 <4>[ 2.118935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 08:08:28.636815 <6>[ 2.128480] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 08:08:28.643451 <6>[ 2.136558] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 08:08:28.650130 <6>[ 2.144594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 08:08:28.660385 <6>[ 2.152510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 08:08:28.666776 <6>[ 2.160327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 08:08:28.677309 <6>[ 2.168144] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 08:08:28.687100 <6>[ 2.178584] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 08:08:28.693508 <6>[ 2.186941] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 08:08:28.703493 <6>[ 2.195285] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 08:08:28.709903 <6>[ 2.203623] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 08:08:28.719947 <6>[ 2.211961] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 08:08:28.726926 <6>[ 2.220300] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 08:08:28.736778 <6>[ 2.228637] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 08:08:28.743471 <6>[ 2.236975] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 08:08:28.753318 <6>[ 2.245313] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 08:08:28.760069 <6>[ 2.253652] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 08:08:28.770242 <6>[ 2.261990] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 08:08:28.776810 <6>[ 2.270328] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 08:08:28.786876 <6>[ 2.278667] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 08:08:28.793725 <6>[ 2.287004] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 08:08:28.803877 <6>[ 2.295342] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 08:08:28.810249 <6>[ 2.304064] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 08:08:28.816948 <6>[ 2.311214] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 08:08:28.823612 <6>[ 2.317949] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 08:08:28.830305 <6>[ 2.324703] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 08:08:28.836636 <6>[ 2.331683] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 08:08:28.846858 <6>[ 2.338566] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 08:08:28.856825 <6>[ 2.347698] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 08:08:28.863317 <6>[ 2.356817] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 08:08:28.873201 <6>[ 2.366113] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 08:08:28.883269 <6>[ 2.375581] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 08:08:28.892979 <6>[ 2.385048] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 08:08:28.903424 <6>[ 2.394167] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 08:08:28.912723 <6>[ 2.403638] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 08:08:28.919423 <6>[ 2.412757] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 08:08:28.929712 <6>[ 2.422054] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 08:08:28.942544 <6>[ 2.432214] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 08:08:28.952589 <6>[ 2.443761] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 08:08:28.959102 <6>[ 2.453396] Trying to probe devices needed for running init ...
10643 08:08:29.002400 <6>[ 2.495111] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10644 08:08:29.156002 <6>[ 2.652187] hub 1-1:1.0: USB hub found
10645 08:08:29.159443 <6>[ 2.656648] hub 1-1:1.0: 4 ports detected
10646 08:08:29.282631 <6>[ 2.775469] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10647 08:08:29.310720 <6>[ 2.806519] hub 2-1:1.0: USB hub found
10648 08:08:29.313591 <6>[ 2.811108] hub 2-1:1.0: 3 ports detected
10649 08:08:29.482112 <6>[ 2.975121] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10650 08:08:29.614580 <6>[ 3.110529] hub 1-1.4:1.0: USB hub found
10651 08:08:29.617567 <6>[ 3.115118] hub 1-1.4:1.0: 2 ports detected
10652 08:08:29.694325 <6>[ 3.187388] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10653 08:08:29.914285 <6>[ 3.407141] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10654 08:08:30.106457 <6>[ 3.599204] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10655 08:08:41.235438 <6>[ 14.736132] ALSA device list:
10656 08:08:41.241487 <6>[ 14.739420] No soundcards found.
10657 08:08:41.250384 <6>[ 14.747458] Freeing unused kernel memory: 8448K
10658 08:08:41.253653 <6>[ 14.752438] Run /init as init process
10659 08:08:41.264119 Loading, please wait...
10660 08:08:41.285406 Starting version 247.3-7+deb11u2
10661 08:08:41.519873 <6>[ 15.014108] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10662 08:08:41.526717 <6>[ 15.022759] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10663 08:08:41.540543 <6>[ 15.034680] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10664 08:08:41.547105 <6>[ 15.037131] remoteproc remoteproc0: scp is available
10665 08:08:41.557151 <6>[ 15.049606] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10666 08:08:41.560521 <6>[ 15.049719] remoteproc remoteproc0: powering up scp
10667 08:08:41.567251 <6>[ 15.052178] usbcore: registered new interface driver r8152
10668 08:08:41.573507 <6>[ 15.069223] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10669 08:08:41.580647 <6>[ 15.077926] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10670 08:08:41.587248 <4>[ 15.081116] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10671 08:08:41.593556 <6>[ 15.085239] mc: Linux media interface: v0.10
10672 08:08:41.607892 <4>[ 15.102151] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10673 08:08:41.618478 <3>[ 15.112702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 08:08:41.625132 <3>[ 15.120895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 08:08:41.634956 <3>[ 15.129001] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 08:08:41.641593 <6>[ 15.133424] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10677 08:08:41.648138 <6>[ 15.136024] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10678 08:08:41.658233 <3>[ 15.137369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 08:08:41.665391 <3>[ 15.160153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 08:08:41.675105 <6>[ 15.163662] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10681 08:08:41.684491 <3>[ 15.168312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 08:08:41.691428 <3>[ 15.168329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 08:08:41.701175 <3>[ 15.168337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 08:08:41.707939 <6>[ 15.176170] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10685 08:08:41.711225 <6>[ 15.176175] pci_bus 0000:00: root bus resource [bus 00-ff]
10686 08:08:41.721380 <6>[ 15.176180] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10687 08:08:41.728387 <6>[ 15.176183] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10688 08:08:41.735065 <6>[ 15.176214] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10689 08:08:41.744649 <6>[ 15.176227] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10690 08:08:41.748523 <6>[ 15.176302] pci 0000:00:00.0: supports D1 D2
10691 08:08:41.754729 <6>[ 15.176304] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10692 08:08:41.765116 <6>[ 15.177265] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10693 08:08:41.768227 <6>[ 15.177336] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10694 08:08:41.778539 <6>[ 15.177360] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10695 08:08:41.785370 <6>[ 15.177377] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10696 08:08:41.791981 <6>[ 15.177392] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10697 08:08:41.794824 <6>[ 15.177494] pci 0000:01:00.0: supports D1 D2
10698 08:08:41.801794 <6>[ 15.177495] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10699 08:08:41.811741 <6>[ 15.178860] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10700 08:08:41.821730 <4>[ 15.181286] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10701 08:08:41.828372 <4>[ 15.181296] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10702 08:08:41.838565 <3>[ 15.186551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 08:08:41.844896 <4>[ 15.194591] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10704 08:08:41.851568 <4>[ 15.194591] Fallback method does not support PEC.
10705 08:08:41.858345 <6>[ 15.194712] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10706 08:08:41.865317 <6>[ 15.194734] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10707 08:08:41.874942 <6>[ 15.194737] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10708 08:08:41.881525 <6>[ 15.194746] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10709 08:08:41.891323 <6>[ 15.194758] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10710 08:08:41.897762 <6>[ 15.194771] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10711 08:08:41.904914 <6>[ 15.194783] pci 0000:00:00.0: PCI bridge to [bus 01]
10712 08:08:41.911314 <6>[ 15.194788] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10713 08:08:41.917849 <6>[ 15.195421] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10714 08:08:41.924620 <6>[ 15.195988] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10715 08:08:41.931191 <6>[ 15.196341] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10716 08:08:41.937937 <3>[ 15.202859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 08:08:41.944602 <6>[ 15.209287] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10718 08:08:41.954316 <6>[ 15.222891] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10719 08:08:41.964021 <3>[ 15.225095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 08:08:41.970697 <6>[ 15.232372] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10721 08:08:41.980912 <3>[ 15.232961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 08:08:41.987139 <3>[ 15.232966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 08:08:41.997340 <3>[ 15.233005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 08:08:42.004054 <3>[ 15.233008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 08:08:42.010339 <3>[ 15.233011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 08:08:42.020489 <3>[ 15.233016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 08:08:42.027140 <3>[ 15.233018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 08:08:42.037153 <3>[ 15.233033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 08:08:42.040661 <6>[ 15.239149] r8152 2-1.3:1.0 eth0: v1.12.13
10730 08:08:42.046798 <6>[ 15.246093] remoteproc remoteproc0: remote processor scp is now up
10731 08:08:42.053866 <6>[ 15.251951] videodev: Linux video capture interface: v2.00
10732 08:08:42.056988 <6>[ 15.252269] usbcore: registered new interface driver cdc_ether
10733 08:08:42.067169 <6>[ 15.255030] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10734 08:08:42.073696 <6>[ 15.266336] usbcore: registered new interface driver r8153_ecm
10735 08:08:42.080285 <6>[ 15.267656] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10736 08:08:42.090353 <5>[ 15.274295] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10737 08:08:42.096535 <3>[ 15.277208] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 08:08:42.103091 <6>[ 15.281141] Bluetooth: Core ver 2.22
10739 08:08:42.106469 <6>[ 15.288371] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10740 08:08:42.113254 <6>[ 15.294786] NET: Registered PF_BLUETOOTH protocol family
10741 08:08:42.119784 <5>[ 15.298467] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10742 08:08:42.126562 <6>[ 15.316910] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10743 08:08:42.133056 <6>[ 15.324237] Bluetooth: HCI device and connection manager initialized
10744 08:08:42.139807 <6>[ 15.332962] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10745 08:08:42.152820 <6>[ 15.333652] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10746 08:08:42.159305 <6>[ 15.333777] usbcore: registered new interface driver uvcvideo
10747 08:08:42.162942 <6>[ 15.340437] Bluetooth: HCI socket layer initialized
10748 08:08:42.169840 <6>[ 15.666528] Bluetooth: L2CAP socket layer initialized
10749 08:08:42.172912 <6>[ 15.671842] Bluetooth: SCO socket layer initialized
10750 08:08:42.183412 <4>[ 15.677496] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10751 08:08:42.190115 <6>[ 15.686422] cfg80211: failed to load regulatory.db
10752 08:08:42.198634 <6>[ 15.696053] usbcore: registered new interface driver btusb
10753 08:08:42.208495 <4>[ 15.697408] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10754 08:08:42.215226 <3>[ 15.712427] Bluetooth: hci0: Failed to load firmware file (-2)
10755 08:08:42.221606 <3>[ 15.718521] Bluetooth: hci0: Failed to set up firmware (-2)
10756 08:08:42.228478 <6>[ 15.721875] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10757 08:08:42.238238 <4>[ 15.724353] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10758 08:08:42.245230 <6>[ 15.731834] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10759 08:08:42.271219 <6>[ 15.768800] mt7921e 0000:01:00.0: ASIC revision: 79610010
10760 08:08:42.375561 <4>[ 15.866406] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 08:08:42.391265 Begin: Loading essential drivers ... done.
10762 08:08:42.394524 Begin: Running /scripts/init-premount ... done.
10763 08:08:42.401131 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10764 08:08:42.411158 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10765 08:08:42.414488 Device /sys/class/net/enx00e04c787aaa found
10766 08:08:42.414611 done.
10767 08:08:42.496006 IP-Config: enx00e04c787aaa hardw<4>[ 15.985795] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10768 08:08:42.499789 are address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10769 08:08:42.613474 <4>[ 16.104342] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 08:08:42.728783 <4>[ 16.220048] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 08:08:42.844927 <4>[ 16.335986] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 08:08:42.960754 <4>[ 16.451881] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 08:08:43.076762 <4>[ 16.567825] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 08:08:43.192460 <4>[ 16.683767] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 08:08:43.308683 <4>[ 16.799752] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 08:08:43.390307 <6>[ 16.887793] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10777 08:08:43.424745 <4>[ 16.915693] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 08:08:43.532008 <3>[ 17.029670] mt7921e 0000:01:00.0: hardware init failed
10779 08:08:43.654148 IP-Config: no response after 2 secs - giving up
10780 08:08:43.700900 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10781 08:08:43.704221 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10782 08:08:43.710430 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10783 08:08:43.720309 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10784 08:08:43.727602 host : mt8192-asurada-spherion-r0-cbg-0
10785 08:08:43.733870 domain : lava-rack
10786 08:08:43.737105 rootserver: 192.168.201.1 rootpath:
10787 08:08:43.737209 filename :
10788 08:08:43.801717 done.
10789 08:08:43.808210 Begin: Running /scripts/nfs-bottom ... done.
10790 08:08:43.825480 Begin: Running /scripts/init-bottom ... done.
10791 08:08:45.000556 <6>[ 18.498514] NET: Registered PF_INET6 protocol family
10792 08:08:45.008056 <6>[ 18.505906] Segment Routing with IPv6
10793 08:08:45.011325 <6>[ 18.509948] In-situ OAM (IOAM) with IPv6
10794 08:08:45.128876 <30>[ 18.607353] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10795 08:08:45.135553 <30>[ 18.631830] systemd[1]: Detected architecture arm64.
10796 08:08:45.153251
10797 08:08:45.156540 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10798 08:08:45.156665
10799 08:08:45.175080 <30>[ 18.673258] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10800 08:08:45.766254 <30>[ 19.261206] systemd[1]: Queued start job for default target Graphical Interface.
10801 08:08:45.790505 <30>[ 19.288667] systemd[1]: Created slice system-getty.slice.
10802 08:08:45.797256 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10803 08:08:45.814302 <30>[ 19.312520] systemd[1]: Created slice system-modprobe.slice.
10804 08:08:45.820856 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10805 08:08:45.839046 <30>[ 19.337210] systemd[1]: Created slice system-serial\x2dgetty.slice.
10806 08:08:45.849596 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10807 08:08:45.862606 <30>[ 19.360218] systemd[1]: Created slice User and Session Slice.
10808 08:08:45.869048 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10809 08:08:45.889253 <30>[ 19.383853] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10810 08:08:45.899080 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10811 08:08:45.916845 <30>[ 19.411344] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10812 08:08:45.923148 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10813 08:08:45.943992 <30>[ 19.435258] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10814 08:08:45.950452 <30>[ 19.447409] systemd[1]: Reached target Local Encrypted Volumes.
10815 08:08:45.956895 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10816 08:08:45.973639 <30>[ 19.471738] systemd[1]: Reached target Paths.
10817 08:08:45.977011 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10818 08:08:45.993106 <30>[ 19.491136] systemd[1]: Reached target Remote File Systems.
10819 08:08:45.999790 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10820 08:08:46.017208 <30>[ 19.515500] systemd[1]: Reached target Slices.
10821 08:08:46.023932 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10822 08:08:46.037451 <30>[ 19.535162] systemd[1]: Reached target Swap.
10823 08:08:46.040491 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10824 08:08:46.060913 <30>[ 19.555653] systemd[1]: Listening on initctl Compatibility Named Pipe.
10825 08:08:46.067443 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10826 08:08:46.074232 <30>[ 19.571701] systemd[1]: Listening on Journal Audit Socket.
10827 08:08:46.080892 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10828 08:08:46.098413 <30>[ 19.596262] systemd[1]: Listening on Journal Socket (/dev/log).
10829 08:08:46.105036 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10830 08:08:46.121689 <30>[ 19.619753] systemd[1]: Listening on Journal Socket.
10831 08:08:46.128502 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10832 08:08:46.145767 <30>[ 19.640479] systemd[1]: Listening on Network Service Netlink Socket.
10833 08:08:46.152192 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10834 08:08:46.167320 <30>[ 19.665585] systemd[1]: Listening on udev Control Socket.
10835 08:08:46.173886 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10836 08:08:46.189435 <30>[ 19.687638] systemd[1]: Listening on udev Kernel Socket.
10837 08:08:46.196147 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10838 08:08:46.245592 <30>[ 19.743629] systemd[1]: Mounting Huge Pages File System...
10839 08:08:46.252320 Mounting [0;1;39mHuge Pages File System[0m...
10840 08:08:46.267079 <30>[ 19.765431] systemd[1]: Mounting POSIX Message Queue File System...
10841 08:08:46.273926 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10842 08:08:46.292371 <30>[ 19.790403] systemd[1]: Mounting Kernel Debug File System...
10843 08:08:46.298622 Mounting [0;1;39mKernel Debug File System[0m...
10844 08:08:46.316891 <30>[ 19.811626] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10845 08:08:46.338448 <30>[ 19.833363] systemd[1]: Starting Create list of static device nodes for the current kernel...
10846 08:08:46.345162 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10847 08:08:46.401765 <30>[ 19.899892] systemd[1]: Starting Load Kernel Module configfs...
10848 08:08:46.408494 Starting [0;1;39mLoad Kernel Module configfs[0m...
10849 08:08:46.426230 <30>[ 19.924211] systemd[1]: Starting Load Kernel Module drm...
10850 08:08:46.432828 Starting [0;1;39mLoad Kernel Module drm[0m...
10851 08:08:46.449619 <30>[ 19.947937] systemd[1]: Starting Load Kernel Module fuse...
10852 08:08:46.456444 Starting [0;1;39mLoad Kernel Module fuse[0m...
10853 08:08:46.485480 <6>[ 19.983852] fuse: init (API version 7.37)
10854 08:08:46.495600 <30>[ 19.984506] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10855 08:08:46.508663 <30>[ 20.006598] systemd[1]: Starting Journal Service...
10856 08:08:46.515170 Starting [0;1;39mJournal Service[0m...
10857 08:08:46.538320 <30>[ 20.036318] systemd[1]: Starting Load Kernel Modules...
10858 08:08:46.544471 Starting [0;1;39mLoad Kernel Modules[0m...
10859 08:08:46.609233 <30>[ 20.104252] systemd[1]: Starting Remount Root and Kernel File Systems...
10860 08:08:46.616054 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10861 08:08:46.633081 <30>[ 20.131184] systemd[1]: Starting Coldplug All udev Devices...
10862 08:08:46.639473 Starting [0;1;39mColdplug All udev Devices[0m...
10863 08:08:46.657536 <30>[ 20.155429] systemd[1]: Mounted Huge Pages File System.
10864 08:08:46.665124 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10865 08:08:46.674371 <3>[ 20.167452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 08:08:46.681241 <30>[ 20.176908] systemd[1]: Mounted POSIX Message Queue File System.
10867 08:08:46.687904 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10868 08:08:46.704719 <3>[ 20.199386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 08:08:46.711502 <30>[ 20.199393] systemd[1]: Mounted Kernel Debug File System.
10870 08:08:46.718016 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10871 08:08:46.741203 <30>[ 20.235932] systemd[1]: Finished Create list of static device nodes for the current kernel.
10872 08:08:46.748482 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10873 08:08:46.760828 <3>[ 20.255785] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 08:08:46.770964 <30>[ 20.269442] systemd[1]: modprobe@configfs.service: Succeeded.
10875 08:08:46.785034 <30>[ 20.282964] systemd[1]: Finished Load Kernel Module configfs.
10876 08:08:46.791717 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10877 08:08:46.803392 <3>[ 20.298120] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 08:08:46.811183 <30>[ 20.309388] systemd[1]: modprobe@drm.service: Succeeded.
10879 08:08:46.818575 <30>[ 20.316553] systemd[1]: Finished Load Kernel Module drm.
10880 08:08:46.825564 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10881 08:08:46.837886 <3>[ 20.332663] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 08:08:46.845041 <30>[ 20.343185] systemd[1]: modprobe@fuse.service: Succeeded.
10883 08:08:46.851845 <30>[ 20.349847] systemd[1]: Finished Load Kernel Module fuse.
10884 08:08:46.858472 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10885 08:08:46.868749 <3>[ 20.363697] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 08:08:46.876848 <30>[ 20.374998] systemd[1]: Finished Load Kernel Modules.
10887 08:08:46.883392 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10888 08:08:46.901470 <3>[ 20.396423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 08:08:46.908109 <30>[ 20.397033] systemd[1]: Finished Remount Root and Kernel File Systems.
10890 08:08:46.915156 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10891 08:08:46.932848 <3>[ 20.427812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 08:08:46.963264 <3>[ 20.458012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 08:08:46.988068 <30>[ 20.485873] systemd[1]: Mounting FUSE Control File System...
10894 08:08:46.998223 <3>[ 20.489915] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 08:08:47.005044 Mounting [0;1;39mFUSE Control File System[0m...
10896 08:08:47.019836 <30>[ 20.517451] systemd[1]: Mounting Kernel Configuration File System...
10897 08:08:47.030073 <3>[ 20.522743] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 08:08:47.036789 Mounting [0;1;39mKernel Configuration File System[0m...
10899 08:08:47.060350 <30>[ 20.554862] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10900 08:08:47.070078 <3>[ 20.564015] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 08:08:47.080177 <30>[ 20.564087] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10902 08:08:47.121781 <30>[ 20.619745] systemd[1]: Starting Load/Save Random Seed...
10903 08:08:47.128291 Starting [0;1;39mLoad/Save Random Seed[0m...
10904 08:08:47.154534 <30>[ 20.652584] systemd[1]: Starting Apply Kernel Variables...
10905 08:08:47.161023 Starting [0;1;39mApply Kernel Variables[0m...
10906 08:08:47.189638 <4>[ 20.678032] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10907 08:08:47.200379 <3>[ 20.693868] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10908 08:08:47.203539 <30>[ 20.699172] systemd[1]: Starting Create System Users...
10909 08:08:47.209768 Starting [0;1;39mCreate System Users[0m...
10910 08:08:47.231743 <30>[ 20.729912] systemd[1]: Started Journal Service.
10911 08:08:47.238359 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10912 08:08:47.262434 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10913 08:08:47.272851 See 'systemctl status systemd-udev-trigger.service' for details.
10914 08:08:47.294126 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10915 08:08:47.313249 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10916 08:08:47.330985 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10917 08:08:47.346809 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10918 08:08:47.361949 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10919 08:08:47.398021 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10920 08:08:47.417671 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10921 08:08:47.449853 <46>[ 20.945162] systemd-journald[299]: Received client request to flush runtime journal.
10922 08:08:47.474714 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10923 08:08:47.493449 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10924 08:08:47.509195 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10925 08:08:47.569726 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10926 08:08:48.844354 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10927 08:08:48.885860 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10928 08:08:48.919149 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10929 08:08:48.982050 Starting [0;1;39mNetwork Service[0m...
10930 08:08:49.287715 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10931 08:08:49.306873 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10932 08:08:49.357078 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10933 08:08:49.633858 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10934 08:08:49.653124 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10935 08:08:49.695251 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10936 08:08:49.719129 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10937 08:08:49.738664 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10938 08:08:49.754165 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10939 08:08:49.773140 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10940 08:08:49.841431 Starting [0;1;39mNetwork Name Resolution[0m...
10941 08:08:49.868807 Starting [0;1;39mNetwork Time Synchronization[0m...
10942 08:08:49.887490 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10943 08:08:49.946208 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10944 08:08:50.109026 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10945 08:08:50.125745 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10946 08:08:50.148093 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10947 08:08:50.164667 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10948 08:08:50.184883 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10949 08:08:50.283592 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10950 08:08:50.328750 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10951 08:08:50.361286 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10952 08:08:50.374910 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10953 08:08:50.388980 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10954 08:08:50.580248 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10955 08:08:50.592769 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10956 08:08:50.608992 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10957 08:08:50.661341 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10958 08:08:51.157676 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10959 08:08:51.544382 Starting [0;1;39mUser Login Management[0m...
10960 08:08:51.569331 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10961 08:08:51.587850 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10962 08:08:51.608681 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10963 08:08:51.667087 Starting [0;1;39mPermit User Sessions[0m...
10964 08:08:51.759931 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10965 08:08:51.787288 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10966 08:08:51.847096 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10967 08:08:51.910364 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10968 08:08:51.925471 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10969 08:08:51.943934 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10970 08:08:51.952974 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10971 08:08:51.969906 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10972 08:08:52.027018 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10973 08:08:52.062781 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10974 08:08:52.136187
10975 08:08:52.136307
10976 08:08:52.138956 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10977 08:08:52.139031
10978 08:08:52.142518 debian-bullseye-arm64 login: root (automatic login)
10979 08:08:52.142616
10980 08:08:52.142704
10981 08:08:52.413624 Linux debian-bullseye-arm64 6.1.54-cip6 #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023 aarch64
10982 08:08:52.413821
10983 08:08:52.420573 The programs included with the Debian GNU/Linux system are free software;
10984 08:08:52.426886 the exact distribution terms for each program are described in the
10985 08:08:52.430138 individual files in /usr/share/doc/*/copyright.
10986 08:08:52.430244
10987 08:08:52.437328 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10988 08:08:52.440222 permitted by applicable law.
10989 08:08:52.488112 Matched prompt #10: / #
10991 08:08:52.488344 Setting prompt string to ['/ #']
10992 08:08:52.488439 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10994 08:08:52.488632 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10995 08:08:52.488725 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10996 08:08:52.488794 Setting prompt string to ['/ #']
10997 08:08:52.488854 Forcing a shell prompt, looking for ['/ #']
10999 08:08:52.539064 / #
11000 08:08:52.539168 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11001 08:08:52.539271 Waiting using forced prompt support (timeout 00:02:30)
11002 08:08:52.544059
11003 08:08:52.544329 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11004 08:08:52.544421 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11006 08:08:52.644759 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq'
11007 08:08:52.650344 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11585998/extract-nfsrootfs-y1pgsxqq'
11009 08:08:52.750876 / # export NFS_SERVER_IP='192.168.201.1'
11010 08:08:52.756136 export NFS_SERVER_IP='192.168.201.1'
11011 08:08:52.756421 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11012 08:08:52.756521 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
11013 08:08:52.756611 end: 2 depthcharge-action (duration 00:01:28) [common]
11014 08:08:52.756705 start: 3 lava-test-retry (timeout 00:01:00) [common]
11015 08:08:52.756792 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11016 08:08:52.756865 Using namespace: common
11018 08:08:52.857196 / # #
11019 08:08:52.857314 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11020 08:08:52.862238 #
11021 08:08:52.862504 Using /lava-11585998
11023 08:08:52.962863 / # export SHELL=/bin/sh
11024 08:08:52.968386 export SHELL=/bin/sh
11026 08:08:53.068908 / # . /lava-11585998/environment
11027 08:08:53.074225 . /lava-11585998/environment
11029 08:08:53.180456 / # /lava-11585998/bin/lava-test-runner /lava-11585998/0
11030 08:08:53.180571 Test shell timeout: 10s (minimum of the action and connection timeout)
11031 08:08:53.185260 /lava-11585998/bin/lava-test-runner /lava-11585998/0
11032 08:08:53.372418 + export TESTRUN_ID=0_dmesg
11033 08:08:53.375878 + cd /lava-11585998/0/tests/0_dmesg
11034 08:08:53.379419 + cat uuid
11035 08:08:53.385974 + UUID=11585998_1.<8>[ 26.883508] <LAVA_SIGNAL_STARTRUN 0_dmesg 11585998_1.6.2.3.1>
11036 08:08:53.386237 Received signal: <STARTRUN> 0_dmesg 11585998_1.6.2.3.1
11037 08:08:53.386314 Starting test lava.0_dmesg (11585998_1.6.2.3.1)
11038 08:08:53.386399 Skipping test definition patterns.
11039 08:08:53.389032 6.2.3.1
11040 08:08:53.389116 + set +x
11041 08:08:53.392478 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11042 08:08:53.468816 <8>[ 26.964277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11043 08:08:53.469118 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11045 08:08:53.521681 <8>[ 27.017251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11046 08:08:53.521953 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11048 08:08:53.581741 <8>[ 27.077320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11049 08:08:53.582010 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11051 08:08:53.585195 + set +x
11052 08:08:53.588436 <8>[ 27.087046] <LAVA_SIGNAL_ENDRUN 0_dmesg 11585998_1.6.2.3.1>
11053 08:08:53.588695 Received signal: <ENDRUN> 0_dmesg 11585998_1.6.2.3.1
11054 08:08:53.588776 Ending use of test pattern.
11055 08:08:53.588838 Ending test lava.0_dmesg (11585998_1.6.2.3.1), duration 0.20
11057 08:08:53.593122 <LAVA_TEST_RUNNER EXIT>
11058 08:08:53.593373 ok: lava_test_shell seems to have completed
11059 08:08:53.593475 alert: pass
crit: pass
emerg: pass
11060 08:08:53.593562 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11061 08:08:53.593644 end: 3 lava-test-retry (duration 00:00:01) [common]
11062 08:08:53.593725 start: 4 lava-test-retry (timeout 00:01:00) [common]
11063 08:08:53.593804 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11064 08:08:53.593866 Using namespace: common
11066 08:08:53.694129 / # #
11067 08:08:53.694294 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11068 08:08:53.694442 Using /lava-11585998
11070 08:08:53.794838 export SHELL=/bin/sh
11071 08:08:53.794997 #
11073 08:08:53.895504 / # export SHELL=/bin/sh. /lava-11585998/environment
11074 08:08:53.895686
11076 08:08:53.996221 / # . /lava-11585998/environment/lava-11585998/bin/lava-test-runner /lava-11585998/1
11077 08:08:53.996332 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 08:08:53.996440
11079 08:08:54.001782 / # /lava-11585998/bin/lava-test-runner /lava-11585998/1
11080 08:08:54.090369 + export TESTRUN_ID=1_bootrr
11081 08:08:54.093755 + cd /lava-11585998/1/tests/1_bootrr
11082 08:08:54.097233 + cat uuid
11083 08:08:54.103853 + UUID=11585998_1.<8>[ 27.600365] <LAVA_SIGNAL_STARTRUN 1_bootrr 11585998_1.6.2.3.5>
11084 08:08:54.103965 6.2.3.5
11085 08:08:54.104061 + set +x
11086 08:08:54.104359 Received signal: <STARTRUN> 1_bootrr 11585998_1.6.2.3.5
11087 08:08:54.104429 Starting test lava.1_bootrr (11585998_1.6.2.3.5)
11088 08:08:54.104516 Skipping test definition patterns.
11089 08:08:54.117047 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11585998/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11090 08:08:54.120227 + cd /opt/bootrr/libexec/bootrr
11091 08:08:54.124019 + sh helpers/bootrr-auto
11092 08:08:54.164694 /lava-11585998/1/../bin/lava-test-case
11093 08:08:54.185811 <8>[ 27.682018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11094 08:08:54.186126 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11096 08:08:54.223031 /lava-11585998/1/../bin/lava-test-case
11097 08:08:54.246145 <8>[ 27.742288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11098 08:08:54.246460 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11100 08:08:54.266600 /lava-11585998/1/../bin/lava-test-case
11101 08:08:54.286531 <8>[ 27.782379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11102 08:08:54.286790 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11104 08:08:54.334080 /lava-11585998/1/../bin/lava-test-case
11105 08:08:54.355052 <8>[ 27.850912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11106 08:08:54.355364 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11108 08:08:54.387944 /lava-11585998/1/../bin/lava-test-case
11109 08:08:54.409057 <8>[ 27.905091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11110 08:08:54.409373 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11112 08:08:54.437754 /lava-11585998/1/../bin/lava-test-case
11113 08:08:54.464128 <8>[ 27.959926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11114 08:08:54.464445 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11116 08:08:54.492908 /lava-11585998/1/../bin/lava-test-case
11117 08:08:54.515561 <8>[ 28.011233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11118 08:08:54.515907 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11120 08:08:54.542463 /lava-11585998/1/../bin/lava-test-case
11121 08:08:54.564614 <8>[ 28.060329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11122 08:08:54.564918 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11124 08:08:54.583057 /lava-11585998/1/../bin/lava-test-case
11125 08:08:54.604294 <8>[ 28.099567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11126 08:08:54.604607 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11128 08:08:54.631930 /lava-11585998/1/../bin/lava-test-case
11129 08:08:54.652950 <8>[ 28.148666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11130 08:08:54.653257 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11132 08:08:54.671422 /lava-11585998/1/../bin/lava-test-case
11133 08:08:54.691719 <8>[ 28.187768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11134 08:08:54.692028 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11136 08:08:54.725263 /lava-11585998/1/../bin/lava-test-case
11137 08:08:54.746771 <8>[ 28.242566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11138 08:08:54.747038 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11140 08:08:54.772693 /lava-11585998/1/../bin/lava-test-case
11141 08:08:54.796494 <8>[ 28.292161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11142 08:08:54.796750 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11144 08:08:54.827400 /lava-11585998/1/../bin/lava-test-case
11145 08:08:54.847275 <8>[ 28.343089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11146 08:08:54.847594 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11148 08:08:54.876256 /lava-11585998/1/../bin/lava-test-case
11149 08:08:54.897193 <8>[ 28.392921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11150 08:08:54.897502 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11152 08:08:54.919016 /lava-11585998/1/../bin/lava-test-case
11153 08:08:54.940764 <8>[ 28.436236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11154 08:08:54.941072 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11156 08:08:54.970514 /lava-11585998/1/../bin/lava-test-case
11157 08:08:54.991144 <8>[ 28.487129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11158 08:08:54.991403 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11160 08:08:55.010474 /lava-11585998/1/../bin/lava-test-case
11161 08:08:55.031325 <8>[ 28.526826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11162 08:08:55.031641 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11164 08:08:55.064913 /lava-11585998/1/../bin/lava-test-case
11165 08:08:55.086100 <8>[ 28.581823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11166 08:08:55.086358 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11168 08:08:55.103355 /lava-11585998/1/../bin/lava-test-case
11169 08:08:55.125700 <8>[ 28.621578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11170 08:08:55.125999 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11172 08:08:55.154052 /lava-11585998/1/../bin/lava-test-case
11173 08:08:55.177090 <8>[ 28.673210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11174 08:08:55.177399 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11176 08:08:55.196536 /lava-11585998/1/../bin/lava-test-case
11177 08:08:55.217327 <8>[ 28.713423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11178 08:08:55.217640 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11180 08:08:55.245295 /lava-11585998/1/../bin/lava-test-case
11181 08:08:55.267449 <8>[ 28.763331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11182 08:08:55.267714 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11184 08:08:55.284266 /lava-11585998/1/../bin/lava-test-case
11185 08:08:55.306100 <8>[ 28.802200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11186 08:08:55.306409 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11188 08:08:55.340707 /lava-11585998/1/../bin/lava-test-case
11189 08:08:55.362834 <8>[ 28.858881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11190 08:08:55.363142 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11192 08:08:55.390062 /lava-11585998/1/../bin/lava-test-case
11193 08:08:55.412576 <8>[ 28.908324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11194 08:08:55.412888 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11196 08:08:55.430727 /lava-11585998/1/../bin/lava-test-case
11197 08:08:55.455235 <8>[ 28.951071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11198 08:08:55.455543 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11200 08:08:55.484918 /lava-11585998/1/../bin/lava-test-case
11201 08:08:55.508709 <8>[ 29.004609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11202 08:08:55.509020 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11204 08:08:55.528367 /lava-11585998/1/../bin/lava-test-case
11205 08:08:55.550162 <8>[ 29.045691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11206 08:08:55.550418 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11208 08:08:55.579421 /lava-11585998/1/../bin/lava-test-case
11209 08:08:55.603994 <8>[ 29.099835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11210 08:08:55.604267 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11212 08:08:55.630888 /lava-11585998/1/../bin/lava-test-case
11213 08:08:55.653681 <8>[ 29.149502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11214 08:08:55.653987 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11216 08:08:55.689878 /lava-11585998/1/../bin/lava-test-case
11217 08:08:55.711758 <8>[ 29.207638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11218 08:08:55.712069 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11220 08:08:55.739038 /lava-11585998/1/../bin/lava-test-case
11221 08:08:55.760766 <8>[ 29.256782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11222 08:08:55.761037 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11224 08:08:55.779675 /lava-11585998/1/../bin/lava-test-case
11225 08:08:55.802126 <8>[ 29.297603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11226 08:08:55.802381 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11228 08:08:55.830030 /lava-11585998/1/../bin/lava-test-case
11229 08:08:55.853978 <8>[ 29.349923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11230 08:08:55.854231 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11232 08:08:55.880801 /lava-11585998/1/../bin/lava-test-case
11233 08:08:55.902061 <8>[ 29.398076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11234 08:08:55.902360 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11236 08:08:55.919829 /lava-11585998/1/../bin/lava-test-case
11237 08:08:55.941988 <8>[ 29.437987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11238 08:08:55.942242 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11240 08:08:55.970850 /lava-11585998/1/../bin/lava-test-case
11241 08:08:55.993208 <8>[ 29.489060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11242 08:08:55.993471 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11244 08:08:56.019496 /lava-11585998/1/../bin/lava-test-case
11245 08:08:56.041510 <8>[ 29.537314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11246 08:08:56.041779 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11248 08:08:56.071210 /lava-11585998/1/../bin/lava-test-case
11249 08:08:56.094868 <8>[ 29.590936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11250 08:08:56.095171 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11252 08:08:56.112791 /lava-11585998/1/../bin/lava-test-case
11253 08:08:56.137334 <8>[ 29.633405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11254 08:08:56.137594 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11256 08:08:56.169594 /lava-11585998/1/../bin/lava-test-case
11257 08:08:56.190555 <8>[ 29.686172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11258 08:08:56.190841 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11260 08:08:56.209995 /lava-11585998/1/../bin/lava-test-case
11261 08:08:56.233152 <8>[ 29.729330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11262 08:08:56.233437 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11264 08:08:56.264441 /lava-11585998/1/../bin/lava-test-case
11265 08:08:56.286556 <8>[ 29.782290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11266 08:08:56.286846 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11268 08:08:56.307262 /lava-11585998/1/../bin/lava-test-case
11269 08:08:56.327992 <8>[ 29.823800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11270 08:08:56.328275 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11272 08:08:56.361104 /lava-11585998/1/../bin/lava-test-case
11273 08:08:56.383258 <8>[ 29.879367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11274 08:08:56.383541 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11276 08:08:56.401842 /lava-11585998/1/../bin/lava-test-case
11277 08:08:56.423854 <8>[ 29.919819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11278 08:08:56.424188 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11280 08:08:56.450738 /lava-11585998/1/../bin/lava-test-case
11281 08:08:56.470075 <8>[ 29.966014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11282 08:08:56.470331 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11284 08:08:56.487248 /lava-11585998/1/../bin/lava-test-case
11285 08:08:56.510407 <8>[ 30.006206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11286 08:08:56.510663 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11288 08:08:56.539621 /lava-11585998/1/../bin/lava-test-case
11289 08:08:56.561752 <8>[ 30.057716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11290 08:08:56.562060 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11292 08:08:56.590045 /lava-11585998/1/../bin/lava-test-case
11293 08:08:56.614511 <8>[ 30.110232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11294 08:08:56.614770 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11296 08:08:56.632271 /lava-11585998/1/../bin/lava-test-case
11297 08:08:56.653207 <8>[ 30.149368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11298 08:08:56.653465 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11300 08:08:56.689980 /lava-11585998/1/../bin/lava-test-case
11301 08:08:56.714159 <8>[ 30.209988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11302 08:08:56.714419 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11304 08:08:56.733031 /lava-11585998/1/../bin/lava-test-case
11305 08:08:56.754869 <8>[ 30.250793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11306 08:08:56.755135 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11308 08:08:56.784511 /lava-11585998/1/../bin/lava-test-case
11309 08:08:56.810923 <8>[ 30.306538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11310 08:08:56.811186 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11312 08:08:56.840149 /lava-11585998/1/../bin/lava-test-case
11313 08:08:56.863250 <8>[ 30.359087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11314 08:08:56.863507 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11316 08:08:56.892261 /lava-11585998/1/../bin/lava-test-case
11317 08:08:56.915068 <8>[ 30.410643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11318 08:08:56.915325 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11320 08:08:56.939946 /lava-11585998/1/../bin/lava-test-case
11321 08:08:56.967101 <8>[ 30.462872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11322 08:08:56.967364 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11324 08:08:57.001870 /lava-11585998/1/../bin/lava-test-case
11325 08:08:57.026655 <8>[ 30.522688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11326 08:08:57.026911 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11328 08:08:57.046360 /lava-11585998/1/../bin/lava-test-case
11329 08:08:57.067516 <8>[ 30.563625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11330 08:08:57.067829 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11332 08:08:57.096744 /lava-11585998/1/../bin/lava-test-case
11333 08:08:57.117759 <8>[ 30.613873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11334 08:08:57.118019 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11336 08:08:57.143581 /lava-11585998/1/../bin/lava-test-case
11337 08:08:57.165128 <8>[ 30.661286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11338 08:08:57.165382 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11340 08:08:57.182793 /lava-11585998/1/../bin/lava-test-case
11341 08:08:57.203487 <8>[ 30.699887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11342 08:08:57.203746 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11344 08:08:57.231341 /lava-11585998/1/../bin/lava-test-case
11345 08:08:57.254934 <8>[ 30.751006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11346 08:08:57.255192 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11348 08:08:57.271619 /lava-11585998/1/../bin/lava-test-case
11349 08:08:57.299126 <8>[ 30.795363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11350 08:08:57.299383 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11352 08:08:57.330512 /lava-11585998/1/../bin/lava-test-case
11353 08:08:57.355071 <8>[ 30.851359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11354 08:08:57.355327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11356 08:08:57.375075 /lava-11585998/1/../bin/lava-test-case
11357 08:08:57.398956 <8>[ 30.895017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11358 08:08:57.399218 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11360 08:08:57.427866 /lava-11585998/1/../bin/lava-test-case
11361 08:08:57.448713 <8>[ 30.944929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11362 08:08:57.448972 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11364 08:08:57.474709 /lava-11585998/1/../bin/lava-test-case
11365 08:08:57.494875 <8>[ 30.991155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11366 08:08:57.495156 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11368 08:08:57.521389 /lava-11585998/1/../bin/lava-test-case
11369 08:08:57.543377 <8>[ 31.039281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11370 08:08:57.543657 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11372 08:08:57.570452 /lava-11585998/1/../bin/lava-test-case
11373 08:08:57.595072 <8>[ 31.091054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11374 08:08:57.595332 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11376 08:08:57.630827 /lava-11585998/1/../bin/lava-test-case
11377 08:08:57.654270 <8>[ 31.150230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11378 08:08:57.654531 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11380 08:08:57.682979 /lava-11585998/1/../bin/lava-test-case
11381 08:08:57.702721 <8>[ 31.198691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11382 08:08:57.702980 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11384 08:08:57.728980 /lava-11585998/1/../bin/lava-test-case
11385 08:08:57.752653 <8>[ 31.248613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11386 08:08:57.752915 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11388 08:08:57.779179 /lava-11585998/1/../bin/lava-test-case
11389 08:08:57.799122 <8>[ 31.295209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11390 08:08:57.799415 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11392 08:08:57.828359 /lava-11585998/1/../bin/lava-test-case
11393 08:08:57.851908 <8>[ 31.347885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11394 08:08:57.852164 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11396 08:08:57.877671 /lava-11585998/1/../bin/lava-test-case
11397 08:08:57.899302 <8>[ 31.395677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11398 08:08:57.899604 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11400 08:08:57.926331 /lava-11585998/1/../bin/lava-test-case
11401 08:08:57.949268 <8>[ 31.445495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11402 08:08:57.949529 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11404 08:08:57.984653 /lava-11585998/1/../bin/lava-test-case
11405 08:08:58.005973 <8>[ 31.502073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11406 08:08:58.006231 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11408 08:08:58.037088 /lava-11585998/1/../bin/lava-test-case
11409 08:08:58.061951 <8>[ 31.558117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11410 08:08:58.062214 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11412 08:08:58.091116 /lava-11585998/1/../bin/lava-test-case
11413 08:08:58.113240 <8>[ 31.609382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11414 08:08:58.113496 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11416 08:08:58.139819 /lava-11585998/1/../bin/lava-test-case
11417 08:08:58.161373 <8>[ 31.657115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11418 08:08:58.161629 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11420 08:08:58.180138 /lava-11585998/1/../bin/lava-test-case
11421 08:08:58.202645 <8>[ 31.698961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11422 08:08:58.202897 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11424 08:08:58.233778 /lava-11585998/1/../bin/lava-test-case
11425 08:08:58.255818 <8>[ 31.751864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11426 08:08:58.256075 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11428 08:08:58.280109 /lava-11585998/1/../bin/lava-test-case
11429 08:08:58.303753 <8>[ 31.799773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11430 08:08:58.304057 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11432 08:08:58.332172 /lava-11585998/1/../bin/lava-test-case
11433 08:08:58.354959 <8>[ 31.851109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11434 08:08:58.355233 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11436 08:08:58.372842 /lava-11585998/1/../bin/lava-test-case
11437 08:08:58.394179 <8>[ 31.890470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11438 08:08:58.394437 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11440 08:08:58.423006 /lava-11585998/1/../bin/lava-test-case
11441 08:08:58.445229 <8>[ 31.941355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11442 08:08:58.445486 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11444 08:08:58.463828 /lava-11585998/1/../bin/lava-test-case
11445 08:08:58.487408 <8>[ 31.983653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11446 08:08:58.487678 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11448 08:08:58.514817 /lava-11585998/1/../bin/lava-test-case
11449 08:08:58.535535 <8>[ 32.031976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11450 08:08:58.535793 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11452 08:08:58.553547 /lava-11585998/1/../bin/lava-test-case
11453 08:08:58.574951 <8>[ 32.071382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11454 08:08:58.575208 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11456 08:08:58.611458 /lava-11585998/1/../bin/lava-test-case
11457 08:08:58.632838 <8>[ 32.128720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11458 08:08:58.633094 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11460 08:08:58.650673 /lava-11585998/1/../bin/lava-test-case
11461 08:08:58.670071 <8>[ 32.166455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11462 08:08:58.670332 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11464 08:08:58.700824 /lava-11585998/1/../bin/lava-test-case
11465 08:08:58.724011 <8>[ 32.219963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11466 08:08:58.724265 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11468 08:08:58.754342 /lava-11585998/1/../bin/lava-test-case
11469 08:08:58.777109 <8>[ 32.273477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11470 08:08:58.777365 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11472 08:08:58.810801 /lava-11585998/1/../bin/lava-test-case
11473 08:08:58.831053 <8>[ 32.327125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11474 08:08:58.831316 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11476 08:08:58.860641 /lava-11585998/1/../bin/lava-test-case
11477 08:08:58.882607 <8>[ 32.378607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11478 08:08:58.882871 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11480 08:08:58.901825 /lava-11585998/1/../bin/lava-test-case
11481 08:08:58.924978 <8>[ 32.421045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11482 08:08:58.925238 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11484 08:08:58.960362 /lava-11585998/1/../bin/lava-test-case
11485 08:08:58.984410 <8>[ 32.480854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11486 08:08:58.984670 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11488 08:08:59.003557 /lava-11585998/1/../bin/lava-test-case
11489 08:08:59.023014 <8>[ 32.519330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11490 08:08:59.023270 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11492 08:09:00.066857 /lava-11585998/1/../bin/lava-test-case
11493 08:09:00.093112 <8>[ 33.589318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11494 08:09:00.093380 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11496 08:09:00.112105 /lava-11585998/1/../bin/lava-test-case
11497 08:09:00.137662 <8>[ 33.634068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11498 08:09:00.137918 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11500 08:09:01.174459 /lava-11585998/1/../bin/lava-test-case
11501 08:09:01.197951 <8>[ 34.694679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11502 08:09:01.198223 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11504 08:09:01.216139 /lava-11585998/1/../bin/lava-test-case
11505 08:09:01.235503 <8>[ 34.731634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11506 08:09:01.235791 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11508 08:09:02.271567 /lava-11585998/1/../bin/lava-test-case
11509 08:09:02.297720 <8>[ 35.794462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11510 08:09:02.298001 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11512 08:09:02.317567 /lava-11585998/1/../bin/lava-test-case
11513 08:09:02.341434 <8>[ 35.838026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11514 08:09:02.341689 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11516 08:09:03.380242 /lava-11585998/1/../bin/lava-test-case
11517 08:09:03.402230 <8>[ 36.898928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11518 08:09:03.402507 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11520 08:09:03.421567 /lava-11585998/1/../bin/lava-test-case
11521 08:09:03.445935 <8>[ 36.942406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11522 08:09:03.446192 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11524 08:09:04.483605 /lava-11585998/1/../bin/lava-test-case
11525 08:09:04.506175 <8>[ 38.003316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11526 08:09:04.506493 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11528 08:09:04.520789 /lava-11585998/1/../bin/lava-test-case
11529 08:09:04.539167 <8>[ 38.035528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11530 08:09:04.539480 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11532 08:09:05.574808 /lava-11585998/1/../bin/lava-test-case
11533 08:09:05.598544 <8>[ 39.095510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11534 08:09:05.598817 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11536 08:09:05.615321 /lava-11585998/1/../bin/lava-test-case
11537 08:09:05.637709 <8>[ 39.134687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11538 08:09:05.638035 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11540 08:09:06.677256 /lava-11585998/1/../bin/lava-test-case
11541 08:09:06.702284 <8>[ 40.199548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11542 08:09:06.702581 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11544 08:09:06.719077 /lava-11585998/1/../bin/lava-test-case
11545 08:09:06.741344 <8>[ 40.238670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11546 08:09:06.741636 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11548 08:09:06.761472 /lava-11585998/1/../bin/lava-test-case
11549 08:09:06.784183 <8>[ 40.281259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11550 08:09:06.784479 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11552 08:09:07.822636 /lava-11585998/1/../bin/lava-test-case
11553 08:09:07.845130 <8>[ 41.342468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11554 08:09:07.845432 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11556 08:09:07.864003 /lava-11585998/1/../bin/lava-test-case
11557 08:09:07.885188 <8>[ 41.382385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11558 08:09:07.885545 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11560 08:09:07.912247 /lava-11585998/1/../bin/lava-test-case
11561 08:09:07.931479 <8>[ 41.428508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11562 08:09:07.931862 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11564 08:09:07.948533 /lava-11585998/1/../bin/lava-test-case
11565 08:09:07.970352 <8>[ 41.467177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11566 08:09:07.970691 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11568 08:09:07.997324 /lava-11585998/1/../bin/lava-test-case
11569 08:09:08.018152 <8>[ 41.515572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11570 08:09:08.018519 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11572 08:09:08.045716 /lava-11585998/1/../bin/lava-test-case
11573 08:09:08.069843 <8>[ 41.567133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11574 08:09:08.070149 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11576 08:09:08.097883 /lava-11585998/1/../bin/lava-test-case
11577 08:09:08.116515 <8>[ 41.613860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11578 08:09:08.116808 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11580 08:09:08.143643 /lava-11585998/1/../bin/lava-test-case
11581 08:09:08.165479 <8>[ 41.662666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11582 08:09:08.165795 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11584 08:09:08.197198 /lava-11585998/1/../bin/lava-test-case
11585 08:09:08.225031 <8>[ 41.722445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11586 08:09:08.225321 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11588 08:09:08.255194 /lava-11585998/1/../bin/lava-test-case
11589 08:09:08.277341 <8>[ 41.774661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11590 08:09:08.277670 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11592 08:09:08.296960 /lava-11585998/1/../bin/lava-test-case
11593 08:09:08.323405 <8>[ 41.820871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11594 08:09:08.323665 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11596 08:09:08.354212 /lava-11585998/1/../bin/lava-test-case
11597 08:09:08.377125 <8>[ 41.874133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11598 08:09:08.377517 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11600 08:09:08.396193 /lava-11585998/1/../bin/lava-test-case
11601 08:09:08.419594 <8>[ 41.917079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11602 08:09:08.420017 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11604 08:09:08.455952 /lava-11585998/1/../bin/lava-test-case
11605 08:09:08.479301 <8>[ 41.976580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11606 08:09:08.479615 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11608 08:09:08.498566 /lava-11585998/1/../bin/lava-test-case
11609 08:09:08.520313 <8>[ 42.017697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11610 08:09:08.520689 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11612 08:09:08.549826 /lava-11585998/1/../bin/lava-test-case
11613 08:09:08.572659 <8>[ 42.070108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11614 08:09:08.573025 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11616 08:09:08.594771 /lava-11585998/1/../bin/lava-test-case
11617 08:09:08.620686 <8>[ 42.118217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11618 08:09:08.621054 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11620 08:09:08.650651 /lava-11585998/1/../bin/lava-test-case
11621 08:09:08.673741 <8>[ 42.171280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11622 08:09:08.674090 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11624 08:09:08.693699 /lava-11585998/1/../bin/lava-test-case
11625 08:09:08.718663 <8>[ 42.215982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11626 08:09:08.719035 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11628 08:09:08.749557 /lava-11585998/1/../bin/lava-test-case
11629 08:09:08.770240 <8>[ 42.267754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11630 08:09:08.770575 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11632 08:09:08.795730 /lava-11585998/1/../bin/lava-test-case
11633 08:09:08.816772 <8>[ 42.313690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11634 08:09:08.817119 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11636 08:09:09.856924 /lava-11585998/1/../bin/lava-test-case
11637 08:09:09.886451 <8>[ 43.384068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11638 08:09:09.886768 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11640 08:09:10.923499 /lava-11585998/1/../bin/lava-test-case
11641 08:09:10.946086 <8>[ 44.443761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11642 08:09:10.946398 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11644 08:09:10.964397 /lava-11585998/1/../bin/lava-test-case
11645 08:09:10.985254 <8>[ 44.482664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11646 08:09:10.985547 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11648 08:09:11.009830 /lava-11585998/1/../bin/lava-test-case
11649 08:09:11.032191 <8>[ 44.529977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11650 08:09:11.032490 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11652 08:09:11.051643 /lava-11585998/1/../bin/lava-test-case
11653 08:09:11.073112 <8>[ 44.570988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11654 08:09:11.073400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11656 08:09:11.100764 /lava-11585998/1/../bin/lava-test-case
11657 08:09:11.123781 <8>[ 44.621405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11658 08:09:11.124078 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11660 08:09:11.141522 /lava-11585998/1/../bin/lava-test-case
11661 08:09:11.164017 <8>[ 44.661638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11662 08:09:11.164299 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11664 08:09:11.193099 /lava-11585998/1/../bin/lava-test-case
11665 08:09:11.214840 <8>[ 44.712234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11666 08:09:11.215137 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11668 08:09:11.241346 /lava-11585998/1/../bin/lava-test-case
11669 08:09:11.261391 <8>[ 44.759113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11670 08:09:11.261681 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11672 08:09:11.293510 /lava-11585998/1/../bin/lava-test-case
11673 08:09:11.316142 <8>[ 44.813656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11674 08:09:11.316434 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11676 08:09:11.334863 /lava-11585998/1/../bin/lava-test-case
11677 08:09:11.357783 <8>[ 44.855243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11678 08:09:11.358073 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11680 08:09:11.386736 /lava-11585998/1/../bin/lava-test-case
11681 08:09:11.409487 <8>[ 44.907422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11682 08:09:11.409780 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11684 08:09:11.428280 /lava-11585998/1/../bin/lava-test-case
11685 08:09:11.449546 <8>[ 44.947515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11686 08:09:11.449836 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11688 08:09:11.476919 /lava-11585998/1/../bin/lava-test-case
11689 08:09:11.498553 <8>[ 44.996474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11690 08:09:11.498840 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11692 08:09:11.518321 /lava-11585998/1/../bin/lava-test-case
11693 08:09:11.548583 <8>[ 45.045812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11694 08:09:11.548882 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11696 08:09:11.577287 /lava-11585998/1/../bin/lava-test-case
11697 08:09:11.602603 <8>[ 45.100237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11698 08:09:11.602889 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11700 08:09:11.624879 /lava-11585998/1/../bin/lava-test-case
11701 08:09:11.645808 <8>[ 45.143167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11702 08:09:11.646099 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11704 08:09:11.675340 /lava-11585998/1/../bin/lava-test-case
11705 08:09:11.697242 <8>[ 45.195124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11706 08:09:11.697534 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11708 08:09:11.716561 /lava-11585998/1/../bin/lava-test-case
11709 08:09:11.739774 <8>[ 45.237180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11710 08:09:11.740064 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11712 08:09:11.773667 /lava-11585998/1/../bin/lava-test-case
11713 08:09:11.796056 <8>[ 45.293897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11714 08:09:11.796351 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11716 08:09:11.816394 /lava-11585998/1/../bin/lava-test-case
11717 08:09:11.838313 <8>[ 45.335710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11718 08:09:11.838600 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11720 08:09:11.873484 /lava-11585998/1/../bin/lava-test-case
11721 08:09:11.896046 <8>[ 45.393916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11722 08:09:11.896342 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11724 08:09:12.654777 <6>[ 46.159331] vpu: disabling
11725 08:09:12.658251 <6>[ 46.162462] vproc2: disabling
11726 08:09:12.661691 <6>[ 46.165791] vproc1: disabling
11727 08:09:12.664951 <6>[ 46.169128] vaud18: disabling
11728 08:09:12.671348 <6>[ 46.172648] vsram_others: disabling
11729 08:09:12.674715 <6>[ 46.176650] va09: disabling
11730 08:09:12.677866 <6>[ 46.179818] vsram_md: disabling
11731 08:09:12.681544 <6>[ 46.183411] Vgpu: disabling
11732 08:09:12.922130 /lava-11585998/1/../bin/lava-test-case
11733 08:09:12.946115 <8>[ 46.444160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11734 08:09:12.946436 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11736 08:09:13.984839 /lava-11585998/1/../bin/lava-test-case
11737 08:09:14.009075 <8>[ 47.507089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11738 08:09:14.009350 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11739 08:09:14.009436 Bad test result: blocked
11740 08:09:14.029319 /lava-11585998/1/../bin/lava-test-case
11741 08:09:14.051689 <8>[ 47.549267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11742 08:09:14.051962 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11744 08:09:15.092054 /lava-11585998/1/../bin/lava-test-case
11745 08:09:15.112998 <8>[ 48.610927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11746 08:09:15.113292 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11748 08:09:15.131425 /lava-11585998/1/../bin/lava-test-case
11749 08:09:15.152464 <8>[ 48.650723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11750 08:09:15.152723 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11752 08:09:15.180428 /lava-11585998/1/../bin/lava-test-case
11753 08:09:15.200011 <8>[ 48.698388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11754 08:09:15.200274 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11756 08:09:15.226588 /lava-11585998/1/../bin/lava-test-case
11757 08:09:15.247611 <8>[ 48.745426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11758 08:09:15.247889 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11760 08:09:15.263122 /lava-11585998/1/../bin/lava-test-case
11761 08:09:15.282511 <8>[ 48.780605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11762 08:09:15.282765 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11764 08:09:15.309081 /lava-11585998/1/../bin/lava-test-case
11765 08:09:15.329469 <8>[ 48.827735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11766 08:09:15.329782 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11768 08:09:15.346134 /lava-11585998/1/../bin/lava-test-case
11769 08:09:15.370699 <8>[ 48.868787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11770 08:09:15.371005 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11772 08:09:16.417471 /lava-11585998/1/../bin/lava-test-case
11773 08:09:16.441305 <8>[ 49.939645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11774 08:09:16.441696 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11776 08:09:16.460587 /lava-11585998/1/../bin/lava-test-case
11777 08:09:16.483974 <8>[ 49.982262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11778 08:09:16.484300 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11780 08:09:17.519294 /lava-11585998/1/../bin/lava-test-case
11781 08:09:17.542458 <8>[ 51.040998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11782 08:09:17.542851 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11784 08:09:17.559361 /lava-11585998/1/../bin/lava-test-case
11785 08:09:17.580727 <8>[ 51.079184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11786 08:09:17.581056 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11788 08:09:18.620062 /lava-11585998/1/../bin/lava-test-case
11789 08:09:18.644145 <8>[ 52.142383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11790 08:09:18.644471 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11792 08:09:18.660187 /lava-11585998/1/../bin/lava-test-case
11793 08:09:18.683057 <8>[ 52.181599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11794 08:09:18.683379 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11796 08:09:19.721188 /lava-11585998/1/../bin/lava-test-case
11797 08:09:19.748368 <8>[ 53.247058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11798 08:09:19.748715 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11800 08:09:19.767057 /lava-11585998/1/../bin/lava-test-case
11801 08:09:19.790075 <8>[ 53.288861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11802 08:09:19.790425 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11804 08:09:19.818208 /lava-11585998/1/../bin/lava-test-case
11805 08:09:19.841513 <8>[ 53.339997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11806 08:09:19.841835 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11808 08:09:19.869078 /lava-11585998/1/../bin/lava-test-case
11809 08:09:19.896448 <8>[ 53.394861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11810 08:09:19.896816 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11812 08:09:19.916624 /lava-11585998/1/../bin/lava-test-case
11813 08:09:19.938442 <8>[ 53.436834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11814 08:09:19.938778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11816 08:09:19.966621 /lava-11585998/1/../bin/lava-test-case
11817 08:09:19.988549 <8>[ 53.487353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11818 08:09:19.988878 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11820 08:09:20.008514 /lava-11585998/1/../bin/lava-test-case
11821 08:09:20.029230 <8>[ 53.527740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11822 08:09:20.029591 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11824 08:09:20.063769 /lava-11585998/1/../bin/lava-test-case
11825 08:09:20.083785 <8>[ 53.582275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11826 08:09:20.084104 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11828 08:09:20.105534 /lava-11585998/1/../bin/lava-test-case
11829 08:09:20.128156 <8>[ 53.626672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11830 08:09:20.128484 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11832 08:09:20.153747 /lava-11585998/1/../bin/lava-test-case
11833 08:09:20.177763 <8>[ 53.675930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11834 08:09:20.178105 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11836 08:09:20.183056 + set +x
11837 08:09:20.186334 Received signal: <ENDRUN> 1_bootrr 11585998_1.6.2.3.5
11838 08:09:20.186430 Ending use of test pattern.
11839 08:09:20.186496 Ending test lava.1_bootrr (11585998_1.6.2.3.5), duration 26.08
11841 08:09:20.189264 <8>[ 53.688118] <LAVA_SIGNAL_ENDRUN 1_bootrr 11585998_1.6.2.3.5>
11842 08:09:20.193121 <LAVA_TEST_RUNNER EXIT>
11843 08:09:20.193384 ok: lava_test_shell seems to have completed
11844 08:09:20.194349 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11845 08:09:20.194492 end: 4.1 lava-test-shell (duration 00:00:27) [common]
11846 08:09:20.194577 end: 4 lava-test-retry (duration 00:00:27) [common]
11847 08:09:20.194663 start: 5 finalize (timeout 00:07:36) [common]
11848 08:09:20.194751 start: 5.1 power-off (timeout 00:00:30) [common]
11849 08:09:20.194900 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11850 08:09:20.272023 >> Command sent successfully.
11851 08:09:20.274626 Returned 0 in 0 seconds
11852 08:09:20.375036 end: 5.1 power-off (duration 00:00:00) [common]
11854 08:09:20.375391 start: 5.2 read-feedback (timeout 00:07:36) [common]
11855 08:09:20.375691 Listened to connection for namespace 'common' for up to 1s
11856 08:09:21.375746 Finalising connection for namespace 'common'
11857 08:09:21.375931 Disconnecting from shell: Finalise
11858 08:09:21.376022 / #
11859 08:09:21.476378 end: 5.2 read-feedback (duration 00:00:01) [common]
11860 08:09:21.476561 end: 5 finalize (duration 00:00:01) [common]
11861 08:09:21.476673 Cleaning after the job
11862 08:09:21.476777 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/ramdisk
11863 08:09:21.479490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/kernel
11864 08:09:21.492186 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/dtb
11865 08:09:21.492426 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/nfsrootfs
11866 08:09:21.567050 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585998/tftp-deploy-rtj41f8m/modules
11867 08:09:21.574601 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11585998
11868 08:09:21.967324 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11585998
11869 08:09:21.967511 Job finished correctly