Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
1 08:04:49.081719 lava-dispatcher, installed at version: 2023.06
2 08:04:49.081926 start: 0 validate
3 08:04:49.082065 Start time: 2023-09-21 08:04:49.082057+00:00 (UTC)
4 08:04:49.082194 Using caching service: 'http://localhost/cache/?uri=%s'
5 08:04:49.082340 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 08:04:49.359021 Using caching service: 'http://localhost/cache/?uri=%s'
7 08:04:49.359762 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 08:05:22.146240 Using caching service: 'http://localhost/cache/?uri=%s'
9 08:05:22.147049 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 08:05:22.417521 Using caching service: 'http://localhost/cache/?uri=%s'
11 08:05:22.418214 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 08:05:27.683183 validate duration: 38.60
14 08:05:27.683448 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:05:27.683546 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:05:27.683640 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:05:27.683799 Not decompressing ramdisk as can be used compressed.
18 08:05:27.683902 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 08:05:27.683970 saving as /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/ramdisk/rootfs.cpio.gz
20 08:05:27.684036 total size: 34390042 (32 MB)
21 08:05:27.948934 progress 0 % (0 MB)
22 08:05:27.958084 progress 5 % (1 MB)
23 08:05:27.966938 progress 10 % (3 MB)
24 08:05:27.975854 progress 15 % (4 MB)
25 08:05:27.984732 progress 20 % (6 MB)
26 08:05:27.993810 progress 25 % (8 MB)
27 08:05:28.002816 progress 30 % (9 MB)
28 08:05:28.011875 progress 35 % (11 MB)
29 08:05:28.020739 progress 40 % (13 MB)
30 08:05:28.029759 progress 45 % (14 MB)
31 08:05:28.038960 progress 50 % (16 MB)
32 08:05:28.048139 progress 55 % (18 MB)
33 08:05:28.057030 progress 60 % (19 MB)
34 08:05:28.066200 progress 65 % (21 MB)
35 08:05:28.075080 progress 70 % (22 MB)
36 08:05:28.084113 progress 75 % (24 MB)
37 08:05:28.092904 progress 80 % (26 MB)
38 08:05:28.101945 progress 85 % (27 MB)
39 08:05:28.110996 progress 90 % (29 MB)
40 08:05:28.119992 progress 95 % (31 MB)
41 08:05:28.128672 progress 100 % (32 MB)
42 08:05:28.128882 32 MB downloaded in 0.44 s (73.73 MB/s)
43 08:05:28.129049 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:05:28.129288 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:05:28.129375 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:05:28.129459 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:05:28.129597 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 08:05:28.129667 saving as /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/kernel/Image
50 08:05:28.129727 total size: 49304064 (47 MB)
51 08:05:28.129788 No compression specified
52 08:05:28.130921 progress 0 % (0 MB)
53 08:05:28.143739 progress 5 % (2 MB)
54 08:05:28.156472 progress 10 % (4 MB)
55 08:05:28.169109 progress 15 % (7 MB)
56 08:05:28.181815 progress 20 % (9 MB)
57 08:05:28.194569 progress 25 % (11 MB)
58 08:05:28.207114 progress 30 % (14 MB)
59 08:05:28.219995 progress 35 % (16 MB)
60 08:05:28.232899 progress 40 % (18 MB)
61 08:05:28.245697 progress 45 % (21 MB)
62 08:05:28.258459 progress 50 % (23 MB)
63 08:05:28.271413 progress 55 % (25 MB)
64 08:05:28.284184 progress 60 % (28 MB)
65 08:05:28.296981 progress 65 % (30 MB)
66 08:05:28.309744 progress 70 % (32 MB)
67 08:05:28.322497 progress 75 % (35 MB)
68 08:05:28.335307 progress 80 % (37 MB)
69 08:05:28.348149 progress 85 % (39 MB)
70 08:05:28.361096 progress 90 % (42 MB)
71 08:05:28.373614 progress 95 % (44 MB)
72 08:05:28.386277 progress 100 % (47 MB)
73 08:05:28.386508 47 MB downloaded in 0.26 s (183.12 MB/s)
74 08:05:28.386727 end: 1.2.1 http-download (duration 00:00:00) [common]
76 08:05:28.387023 end: 1.2 download-retry (duration 00:00:00) [common]
77 08:05:28.387111 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:05:28.387201 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:05:28.387375 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 08:05:28.387444 saving as /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/dtb/mt8192-asurada-spherion-r0.dtb
81 08:05:28.387505 total size: 47278 (0 MB)
82 08:05:28.387565 No compression specified
83 08:05:28.388814 progress 69 % (0 MB)
84 08:05:28.389123 progress 100 % (0 MB)
85 08:05:28.389291 0 MB downloaded in 0.00 s (25.28 MB/s)
86 08:05:28.389413 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:05:28.389662 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:05:28.389746 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:05:28.389827 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:05:28.389941 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 08:05:28.390038 saving as /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/modules/modules.tar
93 08:05:28.390099 total size: 8625188 (8 MB)
94 08:05:28.390159 Using unxz to decompress xz
95 08:05:28.394335 progress 0 % (0 MB)
96 08:05:28.415927 progress 5 % (0 MB)
97 08:05:28.438308 progress 10 % (0 MB)
98 08:05:28.464361 progress 15 % (1 MB)
99 08:05:28.490445 progress 20 % (1 MB)
100 08:05:28.517605 progress 25 % (2 MB)
101 08:05:28.545202 progress 30 % (2 MB)
102 08:05:28.573604 progress 35 % (2 MB)
103 08:05:28.598711 progress 40 % (3 MB)
104 08:05:28.623922 progress 45 % (3 MB)
105 08:05:28.651075 progress 50 % (4 MB)
106 08:05:28.676550 progress 55 % (4 MB)
107 08:05:28.701500 progress 60 % (4 MB)
108 08:05:28.726676 progress 65 % (5 MB)
109 08:05:28.752442 progress 70 % (5 MB)
110 08:05:28.776472 progress 75 % (6 MB)
111 08:05:28.802760 progress 80 % (6 MB)
112 08:05:28.833203 progress 85 % (7 MB)
113 08:05:28.860618 progress 90 % (7 MB)
114 08:05:28.886562 progress 95 % (7 MB)
115 08:05:28.909923 progress 100 % (8 MB)
116 08:05:28.914919 8 MB downloaded in 0.52 s (15.67 MB/s)
117 08:05:28.915288 end: 1.4.1 http-download (duration 00:00:01) [common]
119 08:05:28.915689 end: 1.4 download-retry (duration 00:00:01) [common]
120 08:05:28.915829 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 08:05:28.915972 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 08:05:28.916097 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:05:28.916230 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 08:05:28.916539 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt
125 08:05:28.916737 makedir: /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin
126 08:05:28.916899 makedir: /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/tests
127 08:05:28.917051 makedir: /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/results
128 08:05:28.917222 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-add-keys
129 08:05:28.917440 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-add-sources
130 08:05:28.917633 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-background-process-start
131 08:05:28.917826 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-background-process-stop
132 08:05:28.918016 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-common-functions
133 08:05:28.918200 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-echo-ipv4
134 08:05:28.918393 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-install-packages
135 08:05:28.918581 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-installed-packages
136 08:05:28.918808 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-os-build
137 08:05:28.919043 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-probe-channel
138 08:05:28.919236 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-probe-ip
139 08:05:28.919428 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-target-ip
140 08:05:28.919617 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-target-mac
141 08:05:28.919804 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-target-storage
142 08:05:28.920000 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-case
143 08:05:28.920188 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-event
144 08:05:28.920375 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-feedback
145 08:05:28.920554 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-raise
146 08:05:28.920747 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-reference
147 08:05:28.920973 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-runner
148 08:05:28.921159 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-set
149 08:05:28.921350 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-test-shell
150 08:05:28.921550 Updating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-install-packages (oe)
151 08:05:28.921759 Updating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/bin/lava-installed-packages (oe)
152 08:05:28.921927 Creating /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/environment
153 08:05:28.922063 LAVA metadata
154 08:05:28.922166 - LAVA_JOB_ID=11585982
155 08:05:28.922280 - LAVA_DISPATCHER_IP=192.168.201.1
156 08:05:28.922443 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 08:05:28.922562 skipped lava-vland-overlay
158 08:05:28.922683 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 08:05:28.922845 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 08:05:28.922975 skipped lava-multinode-overlay
161 08:05:28.923093 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 08:05:28.923228 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 08:05:28.923350 Loading test definitions
164 08:05:28.923492 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 08:05:28.923612 Using /lava-11585982 at stage 0
166 08:05:28.924068 uuid=11585982_1.5.2.3.1 testdef=None
167 08:05:28.924196 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 08:05:28.924325 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 08:05:28.925079 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 08:05:28.925459 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 08:05:28.926373 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 08:05:28.926766 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 08:05:28.927724 runner path: /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/0/tests/0_cros-ec test_uuid 11585982_1.5.2.3.1
176 08:05:28.927934 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 08:05:28.928272 Creating lava-test-runner.conf files
179 08:05:28.928373 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11585982/lava-overlay-do7bq2nt/lava-11585982/0 for stage 0
180 08:05:28.928511 - 0_cros-ec
181 08:05:28.928653 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 08:05:28.928783 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 08:05:28.938655 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 08:05:28.938877 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 08:05:28.939009 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 08:05:28.939141 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 08:05:28.939275 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 08:05:29.957039 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 08:05:29.957439 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 08:05:29.957559 extracting modules file /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11585982/extract-overlay-ramdisk-zp67v9e7/ramdisk
191 08:05:30.200637 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 08:05:30.200804 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 08:05:30.200901 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585982/compress-overlay-ol1zb92k/overlay-1.5.2.4.tar.gz to ramdisk
194 08:05:30.200973 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585982/compress-overlay-ol1zb92k/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11585982/extract-overlay-ramdisk-zp67v9e7/ramdisk
195 08:05:30.208289 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 08:05:30.208412 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 08:05:30.208516 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 08:05:30.208612 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 08:05:30.208690 Building ramdisk /var/lib/lava/dispatcher/tmp/11585982/extract-overlay-ramdisk-zp67v9e7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11585982/extract-overlay-ramdisk-zp67v9e7/ramdisk
200 08:05:30.993737 >> 271019 blocks
201 08:05:35.719513 rename /var/lib/lava/dispatcher/tmp/11585982/extract-overlay-ramdisk-zp67v9e7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/ramdisk/ramdisk.cpio.gz
202 08:05:35.719973 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 08:05:35.720104 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 08:05:35.720211 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 08:05:35.720318 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/kernel/Image'
206 08:05:48.639615 Returned 0 in 12 seconds
207 08:05:48.740276 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/kernel/image.itb
208 08:05:49.466544 output: FIT description: Kernel Image image with one or more FDT blobs
209 08:05:49.466984 output: Created: Thu Sep 21 09:05:49 2023
210 08:05:49.467061 output: Image 0 (kernel-1)
211 08:05:49.467127 output: Description:
212 08:05:49.467189 output: Created: Thu Sep 21 09:05:49 2023
213 08:05:49.467252 output: Type: Kernel Image
214 08:05:49.467313 output: Compression: lzma compressed
215 08:05:49.467370 output: Data Size: 11045265 Bytes = 10786.39 KiB = 10.53 MiB
216 08:05:49.467430 output: Architecture: AArch64
217 08:05:49.467491 output: OS: Linux
218 08:05:49.467546 output: Load Address: 0x00000000
219 08:05:49.467600 output: Entry Point: 0x00000000
220 08:05:49.467652 output: Hash algo: crc32
221 08:05:49.467705 output: Hash value: 886bc8a0
222 08:05:49.467758 output: Image 1 (fdt-1)
223 08:05:49.467811 output: Description: mt8192-asurada-spherion-r0
224 08:05:49.467863 output: Created: Thu Sep 21 09:05:49 2023
225 08:05:49.467916 output: Type: Flat Device Tree
226 08:05:49.467968 output: Compression: uncompressed
227 08:05:49.468021 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 08:05:49.468073 output: Architecture: AArch64
229 08:05:49.468125 output: Hash algo: crc32
230 08:05:49.468177 output: Hash value: cc4352de
231 08:05:49.468229 output: Image 2 (ramdisk-1)
232 08:05:49.468281 output: Description: unavailable
233 08:05:49.468333 output: Created: Thu Sep 21 09:05:49 2023
234 08:05:49.468385 output: Type: RAMDisk Image
235 08:05:49.468438 output: Compression: Unknown Compression
236 08:05:49.468490 output: Data Size: 47526005 Bytes = 46412.11 KiB = 45.32 MiB
237 08:05:49.468543 output: Architecture: AArch64
238 08:05:49.468595 output: OS: Linux
239 08:05:49.468647 output: Load Address: unavailable
240 08:05:49.468699 output: Entry Point: unavailable
241 08:05:49.468751 output: Hash algo: crc32
242 08:05:49.468802 output: Hash value: 27471fde
243 08:05:49.468855 output: Default Configuration: 'conf-1'
244 08:05:49.468906 output: Configuration 0 (conf-1)
245 08:05:49.468958 output: Description: mt8192-asurada-spherion-r0
246 08:05:49.469010 output: Kernel: kernel-1
247 08:05:49.469062 output: Init Ramdisk: ramdisk-1
248 08:05:49.469114 output: FDT: fdt-1
249 08:05:49.469166 output: Loadables: kernel-1
250 08:05:49.469218 output:
251 08:05:49.469424 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 08:05:49.469524 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 08:05:49.469628 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 08:05:49.469725 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 08:05:49.469806 No LXC device requested
256 08:05:49.469885 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 08:05:49.469971 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 08:05:49.470048 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 08:05:49.470120 Checking files for TFTP limit of 4294967296 bytes.
260 08:05:49.470625 end: 1 tftp-deploy (duration 00:00:22) [common]
261 08:05:49.470758 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 08:05:49.470865 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 08:05:49.470985 substitutions:
264 08:05:49.471053 - {DTB}: 11585982/tftp-deploy-ced_i668/dtb/mt8192-asurada-spherion-r0.dtb
265 08:05:49.471117 - {INITRD}: 11585982/tftp-deploy-ced_i668/ramdisk/ramdisk.cpio.gz
266 08:05:49.471176 - {KERNEL}: 11585982/tftp-deploy-ced_i668/kernel/Image
267 08:05:49.471233 - {LAVA_MAC}: None
268 08:05:49.471289 - {PRESEED_CONFIG}: None
269 08:05:49.471344 - {PRESEED_LOCAL}: None
270 08:05:49.471398 - {RAMDISK}: 11585982/tftp-deploy-ced_i668/ramdisk/ramdisk.cpio.gz
271 08:05:49.471453 - {ROOT_PART}: None
272 08:05:49.471506 - {ROOT}: None
273 08:05:49.471560 - {SERVER_IP}: 192.168.201.1
274 08:05:49.471613 - {TEE}: None
275 08:05:49.471734 Parsed boot commands:
276 08:05:49.471818 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 08:05:49.472033 Parsed boot commands: tftpboot 192.168.201.1 11585982/tftp-deploy-ced_i668/kernel/image.itb 11585982/tftp-deploy-ced_i668/kernel/cmdline
278 08:05:49.472121 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 08:05:49.472206 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 08:05:49.472298 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 08:05:49.472386 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 08:05:49.472455 Not connected, no need to disconnect.
283 08:05:49.472527 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 08:05:49.472605 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 08:05:49.472672 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 08:05:49.476959 Setting prompt string to ['lava-test: # ']
287 08:05:49.477375 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 08:05:49.477491 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 08:05:49.477614 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 08:05:49.477738 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 08:05:49.477958 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 08:05:54.628316 >> Command sent successfully.
293 08:05:54.634345 Returned 0 in 5 seconds
294 08:05:54.735125 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 08:05:54.736533 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 08:05:54.737027 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 08:05:54.737475 Setting prompt string to 'Starting depthcharge on Spherion...'
299 08:05:54.737834 Changing prompt to 'Starting depthcharge on Spherion...'
300 08:05:54.738199 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 08:05:54.739466 [Enter `^Ec?' for help]
302 08:05:54.904486 5.371902] init: cras state chang
303 08:05:54.905016 F0: 102B 0000
304 08:05:54.905355
305 08:05:54.907245 F3: 1001 0000 [0200]
306 08:05:54.907676
307 08:05:54.908015 F3: 1001 0000
308 08:05:54.908331
309 08:05:54.908636 F7: 102D 0000
310 08:05:54.908931
311 08:05:54.910611 F1: 0000 0000
312 08:05:54.911092
313 08:05:54.911431 V0: 0000 0000 [0001]
314 08:05:54.911763
315 08:05:54.914793 00: 0007 8000
316 08:05:54.915343
317 08:05:54.915686 01: 0000 0000
318 08:05:54.916009
319 08:05:54.917937 BP: 0C00 0209 [0000]
320 08:05:54.918458
321 08:05:54.918855 G0: 1182 0000
322 08:05:54.919187
323 08:05:54.921719 EC: 0000 0021 [4000]
324 08:05:54.922246
325 08:05:54.922586 S7: 0000 0000 [0000]
326 08:05:54.922968
327 08:05:54.924568 CC: 0000 0000 [0001]
328 08:05:54.925084
329 08:05:54.925424 T0: 0000 0040 [010F]
330 08:05:54.925740
331 08:05:54.926041 Jump to BL
332 08:05:54.926336
333 08:05:54.951359
334 08:05:54.951878
335 08:05:54.952213
336 08:05:54.958864 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 08:05:54.962798 ARM64: Exception handlers installed.
338 08:05:54.965682 ARM64: Testing exception
339 08:05:54.969064 ARM64: Done test exception
340 08:05:54.975791 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 08:05:54.986325 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 08:05:54.992958 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 08:05:55.003373 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 08:05:55.010252 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 08:05:55.016869 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 08:05:55.028020 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 08:05:55.034446 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 08:05:55.054118 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 08:05:55.057861 WDT: Last reset was cold boot
350 08:05:55.060442 SPI1(PAD0) initialized at 2873684 Hz
351 08:05:55.063803 SPI5(PAD0) initialized at 992727 Hz
352 08:05:55.067148 VBOOT: Loading verstage.
353 08:05:55.074653 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 08:05:55.078328 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 08:05:55.080841 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 08:05:55.083991 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 08:05:55.091427 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 08:05:55.098118 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 08:05:55.109038 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 08:05:55.109579
361 08:05:55.109922
362 08:05:55.119413 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 08:05:55.122946 ARM64: Exception handlers installed.
364 08:05:55.126567 ARM64: Testing exception
365 08:05:55.127152 ARM64: Done test exception
366 08:05:55.132667 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 08:05:55.136152 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 08:05:55.151045 Probing TPM: . done!
369 08:05:55.151572 TPM ready after 0 ms
370 08:05:55.157939 Connected to device vid:did:rid of 1ae0:0028:00
371 08:05:55.164644 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 08:05:55.223673 Initialized TPM device CR50 revision 0
373 08:05:55.233445 tlcl_send_startup: Startup return code is 0
374 08:05:55.233876 TPM: setup succeeded
375 08:05:55.245478 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 08:05:55.253865 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 08:05:55.265976 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 08:05:55.275989 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 08:05:55.279502 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 08:05:55.284393 in-header: 03 07 00 00 08 00 00 00
381 08:05:55.288204 in-data: aa e4 47 04 13 02 00 00
382 08:05:55.291623 Chrome EC: UHEPI supported
383 08:05:55.298903 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 08:05:55.303096 in-header: 03 ad 00 00 08 00 00 00
385 08:05:55.306430 in-data: 00 20 20 08 00 00 00 00
386 08:05:55.306925 Phase 1
387 08:05:55.310147 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 08:05:55.318156 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 08:05:55.321853 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 08:05:55.325220 Recovery requested (1009000e)
391 08:05:55.333565 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 08:05:55.338898 tlcl_extend: response is 0
393 08:05:55.348302 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 08:05:55.354846 tlcl_extend: response is 0
395 08:05:55.360681 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 08:05:55.381432 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 08:05:55.387944 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 08:05:55.388466
399 08:05:55.388805
400 08:05:55.398020 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 08:05:55.401785 ARM64: Exception handlers installed.
402 08:05:55.402335 ARM64: Testing exception
403 08:05:55.404778 ARM64: Done test exception
404 08:05:55.426217 pmic_efuse_setting: Set efuses in 11 msecs
405 08:05:55.430340 pmwrap_interface_init: Select PMIF_VLD_RDY
406 08:05:55.436777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 08:05:55.440185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 08:05:55.443852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 08:05:55.451239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 08:05:55.454485 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 08:05:55.462310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 08:05:55.465218 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 08:05:55.468925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 08:05:55.472527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 08:05:55.480263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 08:05:55.483817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 08:05:55.487144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 08:05:55.490490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 08:05:55.497913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 08:05:55.505579 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 08:05:55.508885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 08:05:55.516183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 08:05:55.520464 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 08:05:55.527874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 08:05:55.531484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 08:05:55.538841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 08:05:55.545135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 08:05:55.549137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 08:05:55.556547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 08:05:55.560233 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 08:05:55.567407 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 08:05:55.570892 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 08:05:55.575104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 08:05:55.581920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 08:05:55.585328 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 08:05:55.589205 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 08:05:55.596645 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 08:05:55.599884 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 08:05:55.603822 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 08:05:55.611108 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 08:05:55.615248 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 08:05:55.622542 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 08:05:55.626247 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 08:05:55.629994 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 08:05:55.633242 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 08:05:55.637246 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 08:05:55.644682 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 08:05:55.647816 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 08:05:55.651762 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 08:05:55.655135 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 08:05:55.659020 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 08:05:55.663056 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 08:05:55.669880 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 08:05:55.673495 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 08:05:55.676995 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 08:05:55.680484 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 08:05:55.688371 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 08:05:55.698949 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 08:05:55.702914 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 08:05:55.710356 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 08:05:55.717660 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 08:05:55.725340 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 08:05:55.729005 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 08:05:55.732462 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 08:05:55.739864 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x3
466 08:05:55.743716 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 08:05:55.751365 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 08:05:55.754888 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 08:05:55.763678 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 08:05:55.773195 [RTC]rtc_get_frequency_meter,154: input=23, output=979
471 08:05:55.782559 [RTC]rtc_get_frequency_meter,154: input=19, output=885
472 08:05:55.792516 [RTC]rtc_get_frequency_meter,154: input=17, output=838
473 08:05:55.802099 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 08:05:55.811020 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 08:05:55.820939 [RTC]rtc_get_frequency_meter,154: input=16, output=813
476 08:05:55.825090 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 08:05:55.828814 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 08:05:55.832466 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 08:05:55.840427 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 08:05:55.843933 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 08:05:55.847821 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 08:05:55.848251 ADC[4]: Raw value=902805 ID=7
483 08:05:55.851271 ADC[3]: Raw value=213336 ID=1
484 08:05:55.855905 RAM Code: 0x71
485 08:05:55.859051 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 08:05:55.862217 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 08:05:55.873952 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 08:05:55.877536 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 08:05:55.880937 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 08:05:55.885884 in-header: 03 07 00 00 08 00 00 00
491 08:05:55.889443 in-data: aa e4 47 04 13 02 00 00
492 08:05:55.892304 Chrome EC: UHEPI supported
493 08:05:55.899993 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 08:05:55.903837 in-header: 03 ed 00 00 08 00 00 00
495 08:05:55.907600 in-data: 80 20 60 08 00 00 00 00
496 08:05:55.908166 MRC: failed to locate region type 0.
497 08:05:55.915245 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 08:05:55.919071 DRAM-K: Running full calibration
499 08:05:55.926085 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 08:05:55.926513 header.status = 0x0
501 08:05:55.929831 header.version = 0x6 (expected: 0x6)
502 08:05:55.933579 header.size = 0xd00 (expected: 0xd00)
503 08:05:55.934111 header.flags = 0x0
504 08:05:55.940739 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 08:05:55.959137 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 08:05:55.966606 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 08:05:55.970143 dram_init: ddr_geometry: 2
508 08:05:55.970565 [EMI] MDL number = 2
509 08:05:55.974380 [EMI] Get MDL freq = 0
510 08:05:55.974838 dram_init: ddr_type: 0
511 08:05:55.977793 is_discrete_lpddr4: 1
512 08:05:55.982135 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 08:05:55.982668
514 08:05:55.983074
515 08:05:55.983429 [Bian_co] ETT version 0.0.0.1
516 08:05:55.989104 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 08:05:55.989660
518 08:05:55.992168 dramc_set_vcore_voltage set vcore to 650000
519 08:05:55.992598 Read voltage for 800, 4
520 08:05:55.995652 Vio18 = 0
521 08:05:55.996096 Vcore = 650000
522 08:05:55.996445 Vdram = 0
523 08:05:56.000003 Vddq = 0
524 08:05:56.000560 Vmddr = 0
525 08:05:56.000905 dram_init: config_dvfs: 1
526 08:05:56.007508 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 08:05:56.010974 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 08:05:56.014774 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 08:05:56.018639 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 08:05:56.021521 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 08:05:56.025246 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 08:05:56.028794 MEM_TYPE=3, freq_sel=18
533 08:05:56.031695 sv_algorithm_assistance_LP4_1600
534 08:05:56.034976 ============ PULL DRAM RESETB DOWN ============
535 08:05:56.041777 ========== PULL DRAM RESETB DOWN end =========
536 08:05:56.045498 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 08:05:56.048499 ===================================
538 08:05:56.051939 LPDDR4 DRAM CONFIGURATION
539 08:05:56.055670 ===================================
540 08:05:56.056191 EX_ROW_EN[0] = 0x0
541 08:05:56.058431 EX_ROW_EN[1] = 0x0
542 08:05:56.058891 LP4Y_EN = 0x0
543 08:05:56.062018 WORK_FSP = 0x0
544 08:05:56.062537 WL = 0x2
545 08:05:56.065397 RL = 0x2
546 08:05:56.065823 BL = 0x2
547 08:05:56.068551 RPST = 0x0
548 08:05:56.068975 RD_PRE = 0x0
549 08:05:56.072532 WR_PRE = 0x1
550 08:05:56.072985 WR_PST = 0x0
551 08:05:56.075240 DBI_WR = 0x0
552 08:05:56.075663 DBI_RD = 0x0
553 08:05:56.079146 OTF = 0x1
554 08:05:56.082923 ===================================
555 08:05:56.085847 ===================================
556 08:05:56.086377 ANA top config
557 08:05:56.089048 ===================================
558 08:05:56.092703 DLL_ASYNC_EN = 0
559 08:05:56.095374 ALL_SLAVE_EN = 1
560 08:05:56.099683 NEW_RANK_MODE = 1
561 08:05:56.100221 DLL_IDLE_MODE = 1
562 08:05:56.102880 LP45_APHY_COMB_EN = 1
563 08:05:56.105911 TX_ODT_DIS = 1
564 08:05:56.109085 NEW_8X_MODE = 1
565 08:05:56.112404 ===================================
566 08:05:56.115568 ===================================
567 08:05:56.115997 data_rate = 1600
568 08:05:56.119585 CKR = 1
569 08:05:56.122773 DQ_P2S_RATIO = 8
570 08:05:56.125819 ===================================
571 08:05:56.129129 CA_P2S_RATIO = 8
572 08:05:56.132553 DQ_CA_OPEN = 0
573 08:05:56.132981 DQ_SEMI_OPEN = 0
574 08:05:56.136124 CA_SEMI_OPEN = 0
575 08:05:56.139413 CA_FULL_RATE = 0
576 08:05:56.142894 DQ_CKDIV4_EN = 1
577 08:05:56.146824 CA_CKDIV4_EN = 1
578 08:05:56.149779 CA_PREDIV_EN = 0
579 08:05:56.150294 PH8_DLY = 0
580 08:05:56.153167 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 08:05:56.156671 DQ_AAMCK_DIV = 4
582 08:05:56.159474 CA_AAMCK_DIV = 4
583 08:05:56.163242 CA_ADMCK_DIV = 4
584 08:05:56.163785 DQ_TRACK_CA_EN = 0
585 08:05:56.166618 CA_PICK = 800
586 08:05:56.170013 CA_MCKIO = 800
587 08:05:56.173009 MCKIO_SEMI = 0
588 08:05:56.177042 PLL_FREQ = 3068
589 08:05:56.180536 DQ_UI_PI_RATIO = 32
590 08:05:56.181054 CA_UI_PI_RATIO = 0
591 08:05:56.184594 ===================================
592 08:05:56.188164 ===================================
593 08:05:56.191879 memory_type:LPDDR4
594 08:05:56.192421 GP_NUM : 10
595 08:05:56.195852 SRAM_EN : 1
596 08:05:56.196277 MD32_EN : 0
597 08:05:56.199631 ===================================
598 08:05:56.203480 [ANA_INIT] >>>>>>>>>>>>>>
599 08:05:56.206892 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 08:05:56.211071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 08:05:56.211684 ===================================
602 08:05:56.214297 data_rate = 1600,PCW = 0X7600
603 08:05:56.218236 ===================================
604 08:05:56.220872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 08:05:56.227941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 08:05:56.231420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 08:05:56.237990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 08:05:56.241336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 08:05:56.244827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 08:05:56.245342 [ANA_INIT] flow start
611 08:05:56.248363 [ANA_INIT] PLL >>>>>>>>
612 08:05:56.251592 [ANA_INIT] PLL <<<<<<<<
613 08:05:56.254888 [ANA_INIT] MIDPI >>>>>>>>
614 08:05:56.255411 [ANA_INIT] MIDPI <<<<<<<<
615 08:05:56.258796 [ANA_INIT] DLL >>>>>>>>
616 08:05:56.262477 [ANA_INIT] flow end
617 08:05:56.264866 ============ LP4 DIFF to SE enter ============
618 08:05:56.268449 ============ LP4 DIFF to SE exit ============
619 08:05:56.271144 [ANA_INIT] <<<<<<<<<<<<<
620 08:05:56.274948 [Flow] Enable top DCM control >>>>>
621 08:05:56.278380 [Flow] Enable top DCM control <<<<<
622 08:05:56.278945 Enable DLL master slave shuffle
623 08:05:56.284583 ==============================================================
624 08:05:56.288811 Gating Mode config
625 08:05:56.292430 ==============================================================
626 08:05:56.295521 Config description:
627 08:05:56.305256 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 08:05:56.311780 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 08:05:56.315183 SELPH_MODE 0: By rank 1: By Phase
630 08:05:56.322471 ==============================================================
631 08:05:56.325333 GAT_TRACK_EN = 1
632 08:05:56.328844 RX_GATING_MODE = 2
633 08:05:56.329362 RX_GATING_TRACK_MODE = 2
634 08:05:56.331901 SELPH_MODE = 1
635 08:05:56.335665 PICG_EARLY_EN = 1
636 08:05:56.338886 VALID_LAT_VALUE = 1
637 08:05:56.345708 ==============================================================
638 08:05:56.348459 Enter into Gating configuration >>>>
639 08:05:56.352348 Exit from Gating configuration <<<<
640 08:05:56.355379 Enter into DVFS_PRE_config >>>>>
641 08:05:56.365547 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 08:05:56.369354 Exit from DVFS_PRE_config <<<<<
643 08:05:56.372156 Enter into PICG configuration >>>>
644 08:05:56.375416 Exit from PICG configuration <<<<
645 08:05:56.379092 [RX_INPUT] configuration >>>>>
646 08:05:56.379615 [RX_INPUT] configuration <<<<<
647 08:05:56.385915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 08:05:56.392698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 08:05:56.396151 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 08:05:56.403276 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 08:05:56.409995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 08:05:56.416999 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 08:05:56.420606 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 08:05:56.423695 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 08:05:56.426946 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 08:05:56.433956 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 08:05:56.437229 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 08:05:56.440455 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 08:05:56.443676 ===================================
660 08:05:56.446902 LPDDR4 DRAM CONFIGURATION
661 08:05:56.450017 ===================================
662 08:05:56.450441 EX_ROW_EN[0] = 0x0
663 08:05:56.453375 EX_ROW_EN[1] = 0x0
664 08:05:56.456822 LP4Y_EN = 0x0
665 08:05:56.457246 WORK_FSP = 0x0
666 08:05:56.460321 WL = 0x2
667 08:05:56.460838 RL = 0x2
668 08:05:56.463531 BL = 0x2
669 08:05:56.463954 RPST = 0x0
670 08:05:56.467100 RD_PRE = 0x0
671 08:05:56.467621 WR_PRE = 0x1
672 08:05:56.470253 WR_PST = 0x0
673 08:05:56.470704 DBI_WR = 0x0
674 08:05:56.473682 DBI_RD = 0x0
675 08:05:56.474107 OTF = 0x1
676 08:05:56.476998 ===================================
677 08:05:56.480184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 08:05:56.487191 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 08:05:56.490229 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 08:05:56.493546 ===================================
681 08:05:56.496769 LPDDR4 DRAM CONFIGURATION
682 08:05:56.500627 ===================================
683 08:05:56.501149 EX_ROW_EN[0] = 0x10
684 08:05:56.503501 EX_ROW_EN[1] = 0x0
685 08:05:56.503925 LP4Y_EN = 0x0
686 08:05:56.507162 WORK_FSP = 0x0
687 08:05:56.507699 WL = 0x2
688 08:05:56.510496 RL = 0x2
689 08:05:56.511069 BL = 0x2
690 08:05:56.514253 RPST = 0x0
691 08:05:56.514677 RD_PRE = 0x0
692 08:05:56.516979 WR_PRE = 0x1
693 08:05:56.520715 WR_PST = 0x0
694 08:05:56.521239 DBI_WR = 0x0
695 08:05:56.524136 DBI_RD = 0x0
696 08:05:56.524657 OTF = 0x1
697 08:05:56.527401 ===================================
698 08:05:56.534023 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 08:05:56.537375 nWR fixed to 40
700 08:05:56.541194 [ModeRegInit_LP4] CH0 RK0
701 08:05:56.541712 [ModeRegInit_LP4] CH0 RK1
702 08:05:56.544472 [ModeRegInit_LP4] CH1 RK0
703 08:05:56.547700 [ModeRegInit_LP4] CH1 RK1
704 08:05:56.548219 match AC timing 13
705 08:05:56.554142 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 08:05:56.557728 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 08:05:56.561235 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 08:05:56.568156 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 08:05:56.570552 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 08:05:56.571022 [EMI DOE] emi_dcm 0
711 08:05:56.578097 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 08:05:56.578624 ==
713 08:05:56.581211 Dram Type= 6, Freq= 0, CH_0, rank 0
714 08:05:56.584488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 08:05:56.585014 ==
716 08:05:56.591661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 08:05:56.594689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 08:05:56.604812 [CA 0] Center 37 (7~68) winsize 62
719 08:05:56.608411 [CA 1] Center 37 (6~68) winsize 63
720 08:05:56.611434 [CA 2] Center 35 (4~66) winsize 63
721 08:05:56.614540 [CA 3] Center 34 (4~65) winsize 62
722 08:05:56.618638 [CA 4] Center 33 (3~64) winsize 62
723 08:05:56.621483 [CA 5] Center 33 (3~64) winsize 62
724 08:05:56.622143
725 08:05:56.624760 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 08:05:56.625284
727 08:05:56.628411 [CATrainingPosCal] consider 1 rank data
728 08:05:56.631590 u2DelayCellTimex100 = 270/100 ps
729 08:05:56.634793 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 08:05:56.638406 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 08:05:56.642414 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
732 08:05:56.649051 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 08:05:56.651961 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 08:05:56.655357 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 08:05:56.655880
736 08:05:56.658542 CA PerBit enable=1, Macro0, CA PI delay=33
737 08:05:56.659085
738 08:05:56.662410 [CBTSetCACLKResult] CA Dly = 33
739 08:05:56.662970 CS Dly: 5 (0~36)
740 08:05:56.663310 ==
741 08:05:56.665676 Dram Type= 6, Freq= 0, CH_0, rank 1
742 08:05:56.672149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 08:05:56.672678 ==
744 08:05:56.675210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 08:05:56.682473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 08:05:56.690915 [CA 0] Center 37 (6~68) winsize 63
747 08:05:56.694511 [CA 1] Center 37 (7~68) winsize 62
748 08:05:56.697660 [CA 2] Center 35 (4~66) winsize 63
749 08:05:56.701287 [CA 3] Center 35 (4~66) winsize 63
750 08:05:56.704157 [CA 4] Center 34 (3~65) winsize 63
751 08:05:56.707639 [CA 5] Center 33 (3~64) winsize 62
752 08:05:56.708214
753 08:05:56.711444 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 08:05:56.711887
755 08:05:56.714319 [CATrainingPosCal] consider 2 rank data
756 08:05:56.717895 u2DelayCellTimex100 = 270/100 ps
757 08:05:56.721301 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 08:05:56.724685 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 08:05:56.727958 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
760 08:05:56.734696 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 08:05:56.738534 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 08:05:56.741844 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 08:05:56.742381
764 08:05:56.744530 CA PerBit enable=1, Macro0, CA PI delay=33
765 08:05:56.745120
766 08:05:56.747994 [CBTSetCACLKResult] CA Dly = 33
767 08:05:56.748559 CS Dly: 5 (0~37)
768 08:05:56.748903
769 08:05:56.751324 ----->DramcWriteLeveling(PI) begin...
770 08:05:56.751754 ==
771 08:05:56.755340 Dram Type= 6, Freq= 0, CH_0, rank 0
772 08:05:56.758586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 08:05:56.762253 ==
774 08:05:56.762803 Write leveling (Byte 0): 29 => 29
775 08:05:56.765897 Write leveling (Byte 1): 30 => 30
776 08:05:56.769462 DramcWriteLeveling(PI) end<-----
777 08:05:56.769978
778 08:05:56.770312 ==
779 08:05:56.773178 Dram Type= 6, Freq= 0, CH_0, rank 0
780 08:05:56.776573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 08:05:56.777114 ==
782 08:05:56.780407 [Gating] SW mode calibration
783 08:05:56.787262 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 08:05:56.791252 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 08:05:56.797562 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 08:05:56.800874 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 08:05:56.804663 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 08:05:56.811472 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 08:05:56.814397 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 08:05:56.818146 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 08:05:56.824737 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 08:05:56.827947 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 08:05:56.831262 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 08:05:56.837595 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 08:05:56.841180 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 08:05:56.844425 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 08:05:56.848063 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 08:05:56.854372 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 08:05:56.858071 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 08:05:56.861384 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 08:05:56.868618 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 08:05:56.871267 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 08:05:56.874856 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 08:05:56.881955 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 08:05:56.885206 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 08:05:56.888874 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 08:05:56.894776 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 08:05:56.898841 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 08:05:56.901913 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 08:05:56.905666 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 08:05:56.911952 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 08:05:56.915984 0 9 12 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
813 08:05:56.918880 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 08:05:56.925967 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 08:05:56.929014 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 08:05:56.932063 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 08:05:56.938700 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 08:05:56.943070 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 08:05:56.946066 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 1)
820 08:05:56.952242 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
821 08:05:56.955584 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 08:05:56.959347 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 08:05:56.962211 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 08:05:56.968955 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 08:05:56.972490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 08:05:56.975415 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 08:05:56.982288 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
828 08:05:56.986178 0 11 12 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
829 08:05:56.989254 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 08:05:56.995964 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 08:05:56.998889 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 08:05:57.002550 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 08:05:57.009592 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 08:05:57.012572 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 08:05:57.016061 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 08:05:57.019656 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 08:05:57.026151 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 08:05:57.029360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 08:05:57.032595 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 08:05:57.039354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 08:05:57.042710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 08:05:57.045934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 08:05:57.053345 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 08:05:57.056848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 08:05:57.059306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 08:05:57.065949 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 08:05:57.069460 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 08:05:57.073012 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 08:05:57.079714 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 08:05:57.083157 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 08:05:57.086044 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 08:05:57.089525 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 08:05:57.093429 Total UI for P1: 0, mck2ui 16
854 08:05:57.096266 best dqsien dly found for B0: ( 0, 14, 6)
855 08:05:57.100014 Total UI for P1: 0, mck2ui 16
856 08:05:57.103087 best dqsien dly found for B1: ( 0, 14, 8)
857 08:05:57.106473 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 08:05:57.110905 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 08:05:57.111421
860 08:05:57.116989 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 08:05:57.120131 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 08:05:57.120653 [Gating] SW calibration Done
863 08:05:57.123540 ==
864 08:05:57.124058 Dram Type= 6, Freq= 0, CH_0, rank 0
865 08:05:57.130790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 08:05:57.131322 ==
867 08:05:57.131659 RX Vref Scan: 0
868 08:05:57.131969
869 08:05:57.133287 RX Vref 0 -> 0, step: 1
870 08:05:57.133707
871 08:05:57.136388 RX Delay -130 -> 252, step: 16
872 08:05:57.139839 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 08:05:57.143664 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 08:05:57.147072 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 08:05:57.153561 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 08:05:57.156550 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 08:05:57.160371 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 08:05:57.163709 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 08:05:57.166855 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 08:05:57.171007 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 08:05:57.177066 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 08:05:57.180636 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 08:05:57.183361 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
884 08:05:57.187165 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 08:05:57.190623 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 08:05:57.197371 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 08:05:57.201143 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 08:05:57.201669 ==
889 08:05:57.203763 Dram Type= 6, Freq= 0, CH_0, rank 0
890 08:05:57.207352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 08:05:57.207880 ==
892 08:05:57.211122 DQS Delay:
893 08:05:57.211645 DQS0 = 0, DQS1 = 0
894 08:05:57.211980 DQM Delay:
895 08:05:57.214275 DQM0 = 87, DQM1 = 79
896 08:05:57.214842 DQ Delay:
897 08:05:57.217281 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 08:05:57.220657 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
899 08:05:57.223643 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
900 08:05:57.227160 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 08:05:57.227588
902 08:05:57.227922
903 08:05:57.228231 ==
904 08:05:57.230636 Dram Type= 6, Freq= 0, CH_0, rank 0
905 08:05:57.237209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 08:05:57.237687 ==
907 08:05:57.238034
908 08:05:57.238342
909 08:05:57.238634 TX Vref Scan disable
910 08:05:57.241097 == TX Byte 0 ==
911 08:05:57.244223 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 08:05:57.247859 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 08:05:57.250613 == TX Byte 1 ==
914 08:05:57.254886 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
915 08:05:57.257499 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
916 08:05:57.261049 ==
917 08:05:57.261476 Dram Type= 6, Freq= 0, CH_0, rank 0
918 08:05:57.267947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 08:05:57.268477 ==
920 08:05:57.280019 TX Vref=22, minBit 0, minWin=27, winSum=439
921 08:05:57.282979 TX Vref=24, minBit 0, minWin=27, winSum=438
922 08:05:57.286607 TX Vref=26, minBit 0, minWin=27, winSum=446
923 08:05:57.290304 TX Vref=28, minBit 3, minWin=27, winSum=448
924 08:05:57.293259 TX Vref=30, minBit 2, minWin=28, winSum=455
925 08:05:57.296522 TX Vref=32, minBit 0, minWin=28, winSum=451
926 08:05:57.303279 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
927 08:05:57.303708
928 08:05:57.306946 Final TX Range 1 Vref 30
929 08:05:57.307372
930 08:05:57.307706 ==
931 08:05:57.310086 Dram Type= 6, Freq= 0, CH_0, rank 0
932 08:05:57.313644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 08:05:57.314144 ==
934 08:05:57.314484
935 08:05:57.314884
936 08:05:57.317016 TX Vref Scan disable
937 08:05:57.320003 == TX Byte 0 ==
938 08:05:57.323443 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
939 08:05:57.327125 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
940 08:05:57.330004 == TX Byte 1 ==
941 08:05:57.333477 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 08:05:57.337016 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 08:05:57.337635
944 08:05:57.340152 [DATLAT]
945 08:05:57.340575 Freq=800, CH0 RK0
946 08:05:57.340909
947 08:05:57.343525 DATLAT Default: 0xa
948 08:05:57.343946 0, 0xFFFF, sum = 0
949 08:05:57.346847 1, 0xFFFF, sum = 0
950 08:05:57.347287 2, 0xFFFF, sum = 0
951 08:05:57.350530 3, 0xFFFF, sum = 0
952 08:05:57.351115 4, 0xFFFF, sum = 0
953 08:05:57.353952 5, 0xFFFF, sum = 0
954 08:05:57.354477 6, 0xFFFF, sum = 0
955 08:05:57.357301 7, 0xFFFF, sum = 0
956 08:05:57.357828 8, 0xFFFF, sum = 0
957 08:05:57.360528 9, 0x0, sum = 1
958 08:05:57.360977 10, 0x0, sum = 2
959 08:05:57.364308 11, 0x0, sum = 3
960 08:05:57.364836 12, 0x0, sum = 4
961 08:05:57.367096 best_step = 10
962 08:05:57.367517
963 08:05:57.367854 ==
964 08:05:57.370919 Dram Type= 6, Freq= 0, CH_0, rank 0
965 08:05:57.374215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 08:05:57.374771 ==
967 08:05:57.375121 RX Vref Scan: 1
968 08:05:57.376881
969 08:05:57.377304 Set Vref Range= 32 -> 127
970 08:05:57.377641
971 08:05:57.380705 RX Vref 32 -> 127, step: 1
972 08:05:57.381231
973 08:05:57.383848 RX Delay -95 -> 252, step: 8
974 08:05:57.384366
975 08:05:57.387194 Set Vref, RX VrefLevel [Byte0]: 32
976 08:05:57.390878 [Byte1]: 32
977 08:05:57.391393
978 08:05:57.394123 Set Vref, RX VrefLevel [Byte0]: 33
979 08:05:57.397797 [Byte1]: 33
980 08:05:57.398325
981 08:05:57.401745 Set Vref, RX VrefLevel [Byte0]: 34
982 08:05:57.404407 [Byte1]: 34
983 08:05:57.404986
984 08:05:57.408169 Set Vref, RX VrefLevel [Byte0]: 35
985 08:05:57.411320 [Byte1]: 35
986 08:05:57.415452
987 08:05:57.416025 Set Vref, RX VrefLevel [Byte0]: 36
988 08:05:57.418825 [Byte1]: 36
989 08:05:57.422872
990 08:05:57.423401 Set Vref, RX VrefLevel [Byte0]: 37
991 08:05:57.426248 [Byte1]: 37
992 08:05:57.430953
993 08:05:57.431474 Set Vref, RX VrefLevel [Byte0]: 38
994 08:05:57.434320 [Byte1]: 38
995 08:05:57.438364
996 08:05:57.439038 Set Vref, RX VrefLevel [Byte0]: 39
997 08:05:57.442024 [Byte1]: 39
998 08:05:57.446156
999 08:05:57.446717 Set Vref, RX VrefLevel [Byte0]: 40
1000 08:05:57.449128 [Byte1]: 40
1001 08:05:57.453374
1002 08:05:57.453792 Set Vref, RX VrefLevel [Byte0]: 41
1003 08:05:57.456705 [Byte1]: 41
1004 08:05:57.461046
1005 08:05:57.461465 Set Vref, RX VrefLevel [Byte0]: 42
1006 08:05:57.464649 [Byte1]: 42
1007 08:05:57.468620
1008 08:05:57.469040 Set Vref, RX VrefLevel [Byte0]: 43
1009 08:05:57.471825 [Byte1]: 43
1010 08:05:57.476209
1011 08:05:57.476629 Set Vref, RX VrefLevel [Byte0]: 44
1012 08:05:57.479504 [Byte1]: 44
1013 08:05:57.483546
1014 08:05:57.483963 Set Vref, RX VrefLevel [Byte0]: 45
1015 08:05:57.487566 [Byte1]: 45
1016 08:05:57.490951
1017 08:05:57.491372 Set Vref, RX VrefLevel [Byte0]: 46
1018 08:05:57.494690 [Byte1]: 46
1019 08:05:57.498903
1020 08:05:57.499421 Set Vref, RX VrefLevel [Byte0]: 47
1021 08:05:57.502713 [Byte1]: 47
1022 08:05:57.506511
1023 08:05:57.507153 Set Vref, RX VrefLevel [Byte0]: 48
1024 08:05:57.510449 [Byte1]: 48
1025 08:05:57.513839
1026 08:05:57.514253 Set Vref, RX VrefLevel [Byte0]: 49
1027 08:05:57.516962 [Byte1]: 49
1028 08:05:57.521632
1029 08:05:57.522143 Set Vref, RX VrefLevel [Byte0]: 50
1030 08:05:57.524971 [Byte1]: 50
1031 08:05:57.528872
1032 08:05:57.529362 Set Vref, RX VrefLevel [Byte0]: 51
1033 08:05:57.532400 [Byte1]: 51
1034 08:05:57.536609
1035 08:05:57.537024 Set Vref, RX VrefLevel [Byte0]: 52
1036 08:05:57.539926 [Byte1]: 52
1037 08:05:57.544370
1038 08:05:57.544882 Set Vref, RX VrefLevel [Byte0]: 53
1039 08:05:57.547259 [Byte1]: 53
1040 08:05:57.551871
1041 08:05:57.552376 Set Vref, RX VrefLevel [Byte0]: 54
1042 08:05:57.555664 [Byte1]: 54
1043 08:05:57.559648
1044 08:05:57.560157 Set Vref, RX VrefLevel [Byte0]: 55
1045 08:05:57.562837 [Byte1]: 55
1046 08:05:57.567419
1047 08:05:57.567929 Set Vref, RX VrefLevel [Byte0]: 56
1048 08:05:57.571437 [Byte1]: 56
1049 08:05:57.574531
1050 08:05:57.574992 Set Vref, RX VrefLevel [Byte0]: 57
1051 08:05:57.577918 [Byte1]: 57
1052 08:05:57.582495
1053 08:05:57.583035 Set Vref, RX VrefLevel [Byte0]: 58
1054 08:05:57.585370 [Byte1]: 58
1055 08:05:57.590323
1056 08:05:57.590878 Set Vref, RX VrefLevel [Byte0]: 59
1057 08:05:57.593517 [Byte1]: 59
1058 08:05:57.597957
1059 08:05:57.598465 Set Vref, RX VrefLevel [Byte0]: 60
1060 08:05:57.600863 [Byte1]: 60
1061 08:05:57.605438
1062 08:05:57.605861 Set Vref, RX VrefLevel [Byte0]: 61
1063 08:05:57.608757 [Byte1]: 61
1064 08:05:57.612749
1065 08:05:57.613260 Set Vref, RX VrefLevel [Byte0]: 62
1066 08:05:57.615878 [Byte1]: 62
1067 08:05:57.620248
1068 08:05:57.620747 Set Vref, RX VrefLevel [Byte0]: 63
1069 08:05:57.624035 [Byte1]: 63
1070 08:05:57.628161
1071 08:05:57.628672 Set Vref, RX VrefLevel [Byte0]: 64
1072 08:05:57.631468 [Byte1]: 64
1073 08:05:57.635689
1074 08:05:57.636205 Set Vref, RX VrefLevel [Byte0]: 65
1075 08:05:57.639018 [Byte1]: 65
1076 08:05:57.643372
1077 08:05:57.643880 Set Vref, RX VrefLevel [Byte0]: 66
1078 08:05:57.646491 [Byte1]: 66
1079 08:05:57.651356
1080 08:05:57.651862 Set Vref, RX VrefLevel [Byte0]: 67
1081 08:05:57.654323 [Byte1]: 67
1082 08:05:57.658238
1083 08:05:57.658786 Set Vref, RX VrefLevel [Byte0]: 68
1084 08:05:57.661817 [Byte1]: 68
1085 08:05:57.666033
1086 08:05:57.666543 Set Vref, RX VrefLevel [Byte0]: 69
1087 08:05:57.669145 [Byte1]: 69
1088 08:05:57.673214
1089 08:05:57.673665 Set Vref, RX VrefLevel [Byte0]: 70
1090 08:05:57.677029 [Byte1]: 70
1091 08:05:57.680668
1092 08:05:57.681087 Set Vref, RX VrefLevel [Byte0]: 71
1093 08:05:57.684346 [Byte1]: 71
1094 08:05:57.689217
1095 08:05:57.689725 Set Vref, RX VrefLevel [Byte0]: 72
1096 08:05:57.692426 [Byte1]: 72
1097 08:05:57.696575
1098 08:05:57.697087 Set Vref, RX VrefLevel [Byte0]: 73
1099 08:05:57.699472 [Byte1]: 73
1100 08:05:57.703868
1101 08:05:57.704381 Set Vref, RX VrefLevel [Byte0]: 74
1102 08:05:57.707431 [Byte1]: 74
1103 08:05:57.711407
1104 08:05:57.711918 Set Vref, RX VrefLevel [Byte0]: 75
1105 08:05:57.714930 [Byte1]: 75
1106 08:05:57.719166
1107 08:05:57.719680 Set Vref, RX VrefLevel [Byte0]: 76
1108 08:05:57.722093 [Byte1]: 76
1109 08:05:57.726683
1110 08:05:57.727255 Set Vref, RX VrefLevel [Byte0]: 77
1111 08:05:57.730024 [Byte1]: 77
1112 08:05:57.734671
1113 08:05:57.735231 Final RX Vref Byte 0 = 62 to rank0
1114 08:05:57.737296 Final RX Vref Byte 1 = 58 to rank0
1115 08:05:57.741056 Final RX Vref Byte 0 = 62 to rank1
1116 08:05:57.743928 Final RX Vref Byte 1 = 58 to rank1==
1117 08:05:57.747658 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 08:05:57.753695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 08:05:57.754113 ==
1120 08:05:57.754458 DQS Delay:
1121 08:05:57.757476 DQS0 = 0, DQS1 = 0
1122 08:05:57.757890 DQM Delay:
1123 08:05:57.758221 DQM0 = 86, DQM1 = 79
1124 08:05:57.760427 DQ Delay:
1125 08:05:57.763832 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1126 08:05:57.767726 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1127 08:05:57.770759 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1128 08:05:57.774146 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1129 08:05:57.774748
1130 08:05:57.775107
1131 08:05:57.780644 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1132 08:05:57.784130 CH0 RK0: MR19=606, MR18=2B12
1133 08:05:57.790899 CH0_RK0: MR19=0x606, MR18=0x2B12, DQSOSC=398, MR23=63, INC=93, DEC=62
1134 08:05:57.791316
1135 08:05:57.794130 ----->DramcWriteLeveling(PI) begin...
1136 08:05:57.794664 ==
1137 08:05:57.797614 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 08:05:57.801019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 08:05:57.801549 ==
1140 08:05:57.804546 Write leveling (Byte 0): 30 => 30
1141 08:05:57.807875 Write leveling (Byte 1): 29 => 29
1142 08:05:57.810918 DramcWriteLeveling(PI) end<-----
1143 08:05:57.811340
1144 08:05:57.811671 ==
1145 08:05:57.814815 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 08:05:57.817733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 08:05:57.818157 ==
1148 08:05:57.821533 [Gating] SW mode calibration
1149 08:05:57.828147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 08:05:57.834791 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 08:05:57.838085 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 08:05:57.881776 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 08:05:57.882263 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 08:05:57.883010 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 08:05:57.883430 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 08:05:57.883768 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 08:05:57.884079 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 08:05:57.884439 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 08:05:57.884749 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 08:05:57.885041 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 08:05:57.885325 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 08:05:57.906461 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 08:05:57.907000 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 08:05:57.907339 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 08:05:57.907964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 08:05:57.908291 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 08:05:57.910405 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 08:05:57.913584 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1169 08:05:57.916723 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1170 08:05:57.920204 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 08:05:57.926886 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 08:05:57.930932 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 08:05:57.933748 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 08:05:57.937340 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 08:05:57.944310 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 08:05:57.947306 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 08:05:57.950907 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1178 08:05:57.957280 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1179 08:05:57.960950 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 08:05:57.964325 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 08:05:57.970491 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 08:05:57.974256 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 08:05:57.977581 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 08:05:57.984238 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
1185 08:05:57.987454 0 10 8 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
1186 08:05:57.991074 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1187 08:05:57.994238 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 08:05:58.000551 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 08:05:58.004001 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 08:05:58.007768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 08:05:58.015211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 08:05:58.018636 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1193 08:05:58.022053 0 11 8 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (1 1)
1194 08:05:58.025272 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1195 08:05:58.031694 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 08:05:58.035627 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 08:05:58.039057 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 08:05:58.042139 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 08:05:58.049805 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 08:05:58.052819 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 08:05:58.056533 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 08:05:58.062461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 08:05:58.066536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 08:05:58.069049 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 08:05:58.075911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 08:05:58.079429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 08:05:58.083089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 08:05:58.089548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 08:05:58.092653 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 08:05:58.096655 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 08:05:58.100052 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 08:05:58.106477 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 08:05:58.109831 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 08:05:58.113179 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 08:05:58.119909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 08:05:58.122988 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 08:05:58.126712 Total UI for P1: 0, mck2ui 16
1218 08:05:58.129620 best dqsien dly found for B0: ( 0, 14, 2)
1219 08:05:58.133232 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 08:05:58.140128 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 08:05:58.140613 Total UI for P1: 0, mck2ui 16
1222 08:05:58.143100 best dqsien dly found for B1: ( 0, 14, 6)
1223 08:05:58.150178 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1224 08:05:58.153392 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1225 08:05:58.153806
1226 08:05:58.156434 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1227 08:05:58.159932 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 08:05:58.163343 [Gating] SW calibration Done
1229 08:05:58.163850 ==
1230 08:05:58.166590 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 08:05:58.170224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 08:05:58.170876 ==
1233 08:05:58.171227 RX Vref Scan: 0
1234 08:05:58.171539
1235 08:05:58.173604 RX Vref 0 -> 0, step: 1
1236 08:05:58.174091
1237 08:05:58.176717 RX Delay -130 -> 252, step: 16
1238 08:05:58.179900 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1239 08:05:58.183186 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1240 08:05:58.190821 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1241 08:05:58.193912 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1242 08:05:58.197274 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1243 08:05:58.200300 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1244 08:05:58.203598 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1245 08:05:58.207115 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1246 08:05:58.214222 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1247 08:05:58.217191 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1248 08:05:58.220678 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1249 08:05:58.224262 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1250 08:05:58.227078 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1251 08:05:58.234169 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1252 08:05:58.237430 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1253 08:05:58.240864 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1254 08:05:58.241281 ==
1255 08:05:58.243871 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 08:05:58.247221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 08:05:58.247643 ==
1258 08:05:58.251162 DQS Delay:
1259 08:05:58.251650 DQS0 = 0, DQS1 = 0
1260 08:05:58.254255 DQM Delay:
1261 08:05:58.254668 DQM0 = 84, DQM1 = 75
1262 08:05:58.255035 DQ Delay:
1263 08:05:58.256992 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1264 08:05:58.260913 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1265 08:05:58.264471 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1266 08:05:58.267422 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1267 08:05:58.267838
1268 08:05:58.268167
1269 08:05:58.270697 ==
1270 08:05:58.271159 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 08:05:58.277475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 08:05:58.277898 ==
1273 08:05:58.278225
1274 08:05:58.278555
1275 08:05:58.280369 TX Vref Scan disable
1276 08:05:58.280800 == TX Byte 0 ==
1277 08:05:58.284314 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1278 08:05:58.290550 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1279 08:05:58.291237 == TX Byte 1 ==
1280 08:05:58.294009 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1281 08:05:58.300676 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1282 08:05:58.301100 ==
1283 08:05:58.304148 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 08:05:58.307523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 08:05:58.307944 ==
1286 08:05:58.320588 TX Vref=22, minBit 3, minWin=27, winSum=444
1287 08:05:58.323823 TX Vref=24, minBit 3, minWin=27, winSum=446
1288 08:05:58.327022 TX Vref=26, minBit 3, minWin=27, winSum=450
1289 08:05:58.330829 TX Vref=28, minBit 3, minWin=27, winSum=452
1290 08:05:58.333931 TX Vref=30, minBit 3, minWin=27, winSum=453
1291 08:05:58.337411 TX Vref=32, minBit 0, minWin=28, winSum=453
1292 08:05:58.344129 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1293 08:05:58.344545
1294 08:05:58.347234 Final TX Range 1 Vref 32
1295 08:05:58.347649
1296 08:05:58.347975 ==
1297 08:05:58.350414 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 08:05:58.354112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 08:05:58.354526 ==
1300 08:05:58.354898
1301 08:05:58.355262
1302 08:05:58.357348 TX Vref Scan disable
1303 08:05:58.360572 == TX Byte 0 ==
1304 08:05:58.364281 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1305 08:05:58.367363 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1306 08:05:58.370830 == TX Byte 1 ==
1307 08:05:58.374228 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1308 08:05:58.377578 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1309 08:05:58.377992
1310 08:05:58.380937 [DATLAT]
1311 08:05:58.381346 Freq=800, CH0 RK1
1312 08:05:58.381674
1313 08:05:58.384327 DATLAT Default: 0xa
1314 08:05:58.384743 0, 0xFFFF, sum = 0
1315 08:05:58.388307 1, 0xFFFF, sum = 0
1316 08:05:58.388830 2, 0xFFFF, sum = 0
1317 08:05:58.391250 3, 0xFFFF, sum = 0
1318 08:05:58.391680 4, 0xFFFF, sum = 0
1319 08:05:58.394172 5, 0xFFFF, sum = 0
1320 08:05:58.394593 6, 0xFFFF, sum = 0
1321 08:05:58.397778 7, 0xFFFF, sum = 0
1322 08:05:58.398197 8, 0xFFFF, sum = 0
1323 08:05:58.401210 9, 0x0, sum = 1
1324 08:05:58.401662 10, 0x0, sum = 2
1325 08:05:58.404243 11, 0x0, sum = 3
1326 08:05:58.404661 12, 0x0, sum = 4
1327 08:05:58.408005 best_step = 10
1328 08:05:58.408378
1329 08:05:58.408677 ==
1330 08:05:58.411214 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 08:05:58.414344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 08:05:58.414760 ==
1333 08:05:58.415067 RX Vref Scan: 0
1334 08:05:58.415347
1335 08:05:58.418055 RX Vref 0 -> 0, step: 1
1336 08:05:58.418431
1337 08:05:58.421775 RX Delay -95 -> 252, step: 8
1338 08:05:58.424621 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1339 08:05:58.431529 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1340 08:05:58.435429 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1341 08:05:58.438369 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1342 08:05:58.442004 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1343 08:05:58.445168 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1344 08:05:58.448317 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1345 08:05:58.455104 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1346 08:05:58.458466 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1347 08:05:58.461847 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1348 08:05:58.465415 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1349 08:05:58.468916 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1350 08:05:58.475366 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1351 08:05:58.478657 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1352 08:05:58.482130 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1353 08:05:58.485102 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1354 08:05:58.485517 ==
1355 08:05:58.489141 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 08:05:58.492520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 08:05:58.495824 ==
1358 08:05:58.496340 DQS Delay:
1359 08:05:58.496669 DQS0 = 0, DQS1 = 0
1360 08:05:58.499462 DQM Delay:
1361 08:05:58.499981 DQM0 = 87, DQM1 = 78
1362 08:05:58.502359 DQ Delay:
1363 08:05:58.502918 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1364 08:05:58.505734 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1365 08:05:58.509423 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1366 08:05:58.512342 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1367 08:05:58.512859
1368 08:05:58.513188
1369 08:05:58.522635 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1370 08:05:58.525588 CH0 RK1: MR19=606, MR18=2F18
1371 08:05:58.529002 CH0_RK1: MR19=0x606, MR18=0x2F18, DQSOSC=397, MR23=63, INC=93, DEC=62
1372 08:05:58.532542 [RxdqsGatingPostProcess] freq 800
1373 08:05:58.539228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 08:05:58.542819 Pre-setting of DQS Precalculation
1375 08:05:58.545810 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 08:05:58.546334 ==
1377 08:05:58.548997 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 08:05:58.556063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 08:05:58.556744 ==
1380 08:05:58.559842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 08:05:58.566149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 08:05:58.575335 [CA 0] Center 36 (6~67) winsize 62
1383 08:05:58.579081 [CA 1] Center 36 (5~67) winsize 63
1384 08:05:58.582143 [CA 2] Center 34 (4~64) winsize 61
1385 08:05:58.585130 [CA 3] Center 33 (3~64) winsize 62
1386 08:05:58.588599 [CA 4] Center 34 (3~65) winsize 63
1387 08:05:58.591783 [CA 5] Center 33 (3~64) winsize 62
1388 08:05:58.592201
1389 08:05:58.595384 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1390 08:05:58.595800
1391 08:05:58.598850 [CATrainingPosCal] consider 1 rank data
1392 08:05:58.602103 u2DelayCellTimex100 = 270/100 ps
1393 08:05:58.605390 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1394 08:05:58.608940 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1395 08:05:58.612068 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1396 08:05:58.619359 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 08:05:58.622056 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1398 08:05:58.625130 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 08:05:58.625356
1400 08:05:58.628836 CA PerBit enable=1, Macro0, CA PI delay=33
1401 08:05:58.629059
1402 08:05:58.632254 [CBTSetCACLKResult] CA Dly = 33
1403 08:05:58.632433 CS Dly: 4 (0~35)
1404 08:05:58.632575 ==
1405 08:05:58.635781 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 08:05:58.638908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 08:05:58.642035 ==
1408 08:05:58.645373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 08:05:58.652368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 08:05:58.661258 [CA 0] Center 36 (5~67) winsize 63
1411 08:05:58.664454 [CA 1] Center 36 (6~67) winsize 62
1412 08:05:58.667518 [CA 2] Center 33 (3~64) winsize 62
1413 08:05:58.671318 [CA 3] Center 33 (3~64) winsize 62
1414 08:05:58.674352 [CA 4] Center 34 (3~65) winsize 63
1415 08:05:58.678235 [CA 5] Center 33 (3~64) winsize 62
1416 08:05:58.678497
1417 08:05:58.681909 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1418 08:05:58.682061
1419 08:05:58.686280 [CATrainingPosCal] consider 2 rank data
1420 08:05:58.689683 u2DelayCellTimex100 = 270/100 ps
1421 08:05:58.693541 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1422 08:05:58.697112 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 08:05:58.700462 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1424 08:05:58.704172 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 08:05:58.707947 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1426 08:05:58.711453 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 08:05:58.711569
1428 08:05:58.715112 CA PerBit enable=1, Macro0, CA PI delay=33
1429 08:05:58.715531
1430 08:05:58.718382 [CBTSetCACLKResult] CA Dly = 33
1431 08:05:58.719075 CS Dly: 5 (0~37)
1432 08:05:58.719689
1433 08:05:58.721745 ----->DramcWriteLeveling(PI) begin...
1434 08:05:58.722122 ==
1435 08:05:58.725257 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 08:05:58.728915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 08:05:58.731607 ==
1438 08:05:58.735260 Write leveling (Byte 0): 27 => 27
1439 08:05:58.735484 Write leveling (Byte 1): 31 => 31
1440 08:05:58.738255 DramcWriteLeveling(PI) end<-----
1441 08:05:58.738485
1442 08:05:58.738663 ==
1443 08:05:58.741712 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 08:05:58.748622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 08:05:58.748776 ==
1446 08:05:58.748895 [Gating] SW mode calibration
1447 08:05:58.758405 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 08:05:58.761641 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 08:05:58.765393 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 08:05:58.771829 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 08:05:58.775730 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 08:05:58.778639 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 08:05:58.785193 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 08:05:58.788478 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 08:05:58.791762 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 08:05:58.799040 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 08:05:58.801760 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 08:05:58.805460 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 08:05:58.812264 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 08:05:58.815560 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1461 08:05:58.818649 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 08:05:58.822085 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 08:05:58.829115 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 08:05:58.832157 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 08:05:58.835495 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1466 08:05:58.842509 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 08:05:58.845387 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1468 08:05:58.849059 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 08:05:58.855543 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 08:05:58.858703 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 08:05:58.862253 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 08:05:58.869096 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 08:05:58.872673 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 08:05:58.876054 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1475 08:05:58.882285 0 9 8 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
1476 08:05:58.885831 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 08:05:58.889414 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 08:05:58.892573 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 08:05:58.898864 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 08:05:58.902275 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 08:05:58.905956 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 08:05:58.912157 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1483 08:05:58.916036 0 10 8 | B1->B0 | 2d2d 2f2f | 1 1 | (1 1) (1 1)
1484 08:05:58.918951 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1485 08:05:58.926020 0 10 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1486 08:05:58.929240 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1487 08:05:58.932791 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1488 08:05:58.939430 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 08:05:58.942512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 08:05:58.946093 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 08:05:58.953001 0 11 8 | B1->B0 | 3434 2e2e | 1 0 | (0 0) (1 1)
1492 08:05:58.956249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 08:05:58.959913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 08:05:58.963132 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 08:05:58.969637 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 08:05:58.972812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 08:05:58.976682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 08:05:58.983245 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 08:05:58.986666 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1500 08:05:58.989888 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 08:05:58.996822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 08:05:58.999992 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 08:05:59.003753 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 08:05:59.006933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 08:05:59.013350 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 08:05:59.016885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 08:05:59.020330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 08:05:59.027164 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 08:05:59.030313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 08:05:59.033800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 08:05:59.040701 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 08:05:59.043906 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 08:05:59.047573 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 08:05:59.053856 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 08:05:59.057821 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 08:05:59.060434 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 08:05:59.064001 Total UI for P1: 0, mck2ui 16
1518 08:05:59.067270 best dqsien dly found for B0: ( 0, 14, 6)
1519 08:05:59.070610 Total UI for P1: 0, mck2ui 16
1520 08:05:59.073873 best dqsien dly found for B1: ( 0, 14, 6)
1521 08:05:59.077291 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 08:05:59.081125 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1523 08:05:59.081573
1524 08:05:59.084057 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 08:05:59.087497 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 08:05:59.091024 [Gating] SW calibration Done
1527 08:05:59.091509 ==
1528 08:05:59.094110 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 08:05:59.097623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 08:05:59.101374 ==
1531 08:05:59.101858 RX Vref Scan: 0
1532 08:05:59.102189
1533 08:05:59.104342 RX Vref 0 -> 0, step: 1
1534 08:05:59.104753
1535 08:05:59.108207 RX Delay -130 -> 252, step: 16
1536 08:05:59.111394 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1537 08:05:59.114603 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1538 08:05:59.117984 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1539 08:05:59.121150 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1540 08:05:59.124755 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1541 08:05:59.131746 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1542 08:05:59.134673 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1543 08:05:59.138137 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1544 08:05:59.141402 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1545 08:05:59.144883 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1546 08:05:59.151449 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1547 08:05:59.155180 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1548 08:05:59.158232 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1549 08:05:59.161742 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1550 08:05:59.165409 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1551 08:05:59.171620 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1552 08:05:59.172034 ==
1553 08:05:59.175052 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 08:05:59.178652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 08:05:59.179178 ==
1556 08:05:59.179520 DQS Delay:
1557 08:05:59.182129 DQS0 = 0, DQS1 = 0
1558 08:05:59.182644 DQM Delay:
1559 08:05:59.185018 DQM0 = 83, DQM1 = 77
1560 08:05:59.185533 DQ Delay:
1561 08:05:59.188779 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1562 08:05:59.191935 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1563 08:05:59.195900 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1564 08:05:59.198904 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1565 08:05:59.199381
1566 08:05:59.199707
1567 08:05:59.200015 ==
1568 08:05:59.202123 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 08:05:59.205305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 08:05:59.205794 ==
1571 08:05:59.206123
1572 08:05:59.206426
1573 08:05:59.209341 TX Vref Scan disable
1574 08:05:59.212189 == TX Byte 0 ==
1575 08:05:59.215208 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 08:05:59.219102 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 08:05:59.222125 == TX Byte 1 ==
1578 08:05:59.225481 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1579 08:05:59.229160 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1580 08:05:59.229573 ==
1581 08:05:59.232315 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 08:05:59.235767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 08:05:59.236279 ==
1584 08:05:59.250396 TX Vref=22, minBit 8, minWin=26, winSum=433
1585 08:05:59.253699 TX Vref=24, minBit 8, minWin=26, winSum=434
1586 08:05:59.257333 TX Vref=26, minBit 9, minWin=27, winSum=443
1587 08:05:59.261652 TX Vref=28, minBit 10, minWin=27, winSum=453
1588 08:05:59.264929 TX Vref=30, minBit 13, minWin=27, winSum=453
1589 08:05:59.268369 TX Vref=32, minBit 0, minWin=28, winSum=454
1590 08:05:59.275113 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1591 08:05:59.275663
1592 08:05:59.278241 Final TX Range 1 Vref 32
1593 08:05:59.278652
1594 08:05:59.279028 ==
1595 08:05:59.281504 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 08:05:59.285080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 08:05:59.285606 ==
1598 08:05:59.286170
1599 08:05:59.286529
1600 08:05:59.288264 TX Vref Scan disable
1601 08:05:59.291841 == TX Byte 0 ==
1602 08:05:59.295477 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 08:05:59.298873 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 08:05:59.301729 == TX Byte 1 ==
1605 08:05:59.305449 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1606 08:05:59.308237 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1607 08:05:59.308660
1608 08:05:59.308984 [DATLAT]
1609 08:05:59.311476 Freq=800, CH1 RK0
1610 08:05:59.311890
1611 08:05:59.312217 DATLAT Default: 0xa
1612 08:05:59.315025 0, 0xFFFF, sum = 0
1613 08:05:59.318929 1, 0xFFFF, sum = 0
1614 08:05:59.319454 2, 0xFFFF, sum = 0
1615 08:05:59.321859 3, 0xFFFF, sum = 0
1616 08:05:59.322279 4, 0xFFFF, sum = 0
1617 08:05:59.325013 5, 0xFFFF, sum = 0
1618 08:05:59.325433 6, 0xFFFF, sum = 0
1619 08:05:59.328409 7, 0xFFFF, sum = 0
1620 08:05:59.328869 8, 0xFFFF, sum = 0
1621 08:05:59.332469 9, 0x0, sum = 1
1622 08:05:59.332991 10, 0x0, sum = 2
1623 08:05:59.333331 11, 0x0, sum = 3
1624 08:05:59.335282 12, 0x0, sum = 4
1625 08:05:59.335701 best_step = 10
1626 08:05:59.336026
1627 08:05:59.338632 ==
1628 08:05:59.339086 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 08:05:59.345362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 08:05:59.345876 ==
1631 08:05:59.346209 RX Vref Scan: 1
1632 08:05:59.346515
1633 08:05:59.348910 Set Vref Range= 32 -> 127
1634 08:05:59.349413
1635 08:05:59.352372 RX Vref 32 -> 127, step: 1
1636 08:05:59.352883
1637 08:05:59.355100 RX Delay -95 -> 252, step: 8
1638 08:05:59.355514
1639 08:05:59.358581 Set Vref, RX VrefLevel [Byte0]: 32
1640 08:05:59.361925 [Byte1]: 32
1641 08:05:59.362413
1642 08:05:59.365085 Set Vref, RX VrefLevel [Byte0]: 33
1643 08:05:59.368592 [Byte1]: 33
1644 08:05:59.369081
1645 08:05:59.371535 Set Vref, RX VrefLevel [Byte0]: 34
1646 08:05:59.375372 [Byte1]: 34
1647 08:05:59.375942
1648 08:05:59.378618 Set Vref, RX VrefLevel [Byte0]: 35
1649 08:05:59.382124 [Byte1]: 35
1650 08:05:59.385846
1651 08:05:59.386407 Set Vref, RX VrefLevel [Byte0]: 36
1652 08:05:59.388966 [Byte1]: 36
1653 08:05:59.393914
1654 08:05:59.394400 Set Vref, RX VrefLevel [Byte0]: 37
1655 08:05:59.397268 [Byte1]: 37
1656 08:05:59.401369
1657 08:05:59.401893 Set Vref, RX VrefLevel [Byte0]: 38
1658 08:05:59.404645 [Byte1]: 38
1659 08:05:59.408676
1660 08:05:59.409186 Set Vref, RX VrefLevel [Byte0]: 39
1661 08:05:59.411965 [Byte1]: 39
1662 08:05:59.416360
1663 08:05:59.416942 Set Vref, RX VrefLevel [Byte0]: 40
1664 08:05:59.419478 [Byte1]: 40
1665 08:05:59.424155
1666 08:05:59.424671 Set Vref, RX VrefLevel [Byte0]: 41
1667 08:05:59.427069 [Byte1]: 41
1668 08:05:59.431076
1669 08:05:59.431486 Set Vref, RX VrefLevel [Byte0]: 42
1670 08:05:59.435029 [Byte1]: 42
1671 08:05:59.439444
1672 08:05:59.439951 Set Vref, RX VrefLevel [Byte0]: 43
1673 08:05:59.442506 [Byte1]: 43
1674 08:05:59.447015
1675 08:05:59.447425 Set Vref, RX VrefLevel [Byte0]: 44
1676 08:05:59.450149 [Byte1]: 44
1677 08:05:59.454855
1678 08:05:59.455354 Set Vref, RX VrefLevel [Byte0]: 45
1679 08:05:59.458019 [Byte1]: 45
1680 08:05:59.461870
1681 08:05:59.462371 Set Vref, RX VrefLevel [Byte0]: 46
1682 08:05:59.465247 [Byte1]: 46
1683 08:05:59.469555
1684 08:05:59.470063 Set Vref, RX VrefLevel [Byte0]: 47
1685 08:05:59.472970 [Byte1]: 47
1686 08:05:59.477198
1687 08:05:59.477610 Set Vref, RX VrefLevel [Byte0]: 48
1688 08:05:59.480078 [Byte1]: 48
1689 08:05:59.485302
1690 08:05:59.485808 Set Vref, RX VrefLevel [Byte0]: 49
1691 08:05:59.487880 [Byte1]: 49
1692 08:05:59.492498
1693 08:05:59.492930 Set Vref, RX VrefLevel [Byte0]: 50
1694 08:05:59.495624 [Byte1]: 50
1695 08:05:59.499639
1696 08:05:59.500047 Set Vref, RX VrefLevel [Byte0]: 51
1697 08:05:59.503185 [Byte1]: 51
1698 08:05:59.507148
1699 08:05:59.507557 Set Vref, RX VrefLevel [Byte0]: 52
1700 08:05:59.511295 [Byte1]: 52
1701 08:05:59.514942
1702 08:05:59.515433 Set Vref, RX VrefLevel [Byte0]: 53
1703 08:05:59.518401 [Byte1]: 53
1704 08:05:59.522845
1705 08:05:59.523258 Set Vref, RX VrefLevel [Byte0]: 54
1706 08:05:59.526324 [Byte1]: 54
1707 08:05:59.530629
1708 08:05:59.531183 Set Vref, RX VrefLevel [Byte0]: 55
1709 08:05:59.533559 [Byte1]: 55
1710 08:05:59.537507
1711 08:05:59.537923 Set Vref, RX VrefLevel [Byte0]: 56
1712 08:05:59.541491 [Byte1]: 56
1713 08:05:59.545381
1714 08:05:59.545910 Set Vref, RX VrefLevel [Byte0]: 57
1715 08:05:59.549148 [Byte1]: 57
1716 08:05:59.552843
1717 08:05:59.553259 Set Vref, RX VrefLevel [Byte0]: 58
1718 08:05:59.556574 [Byte1]: 58
1719 08:05:59.561198
1720 08:05:59.561711 Set Vref, RX VrefLevel [Byte0]: 59
1721 08:05:59.563934 [Byte1]: 59
1722 08:05:59.568263
1723 08:05:59.568739 Set Vref, RX VrefLevel [Byte0]: 60
1724 08:05:59.571605 [Byte1]: 60
1725 08:05:59.575742
1726 08:05:59.576168 Set Vref, RX VrefLevel [Byte0]: 61
1727 08:05:59.578896 [Byte1]: 61
1728 08:05:59.583693
1729 08:05:59.584217 Set Vref, RX VrefLevel [Byte0]: 62
1730 08:05:59.586883 [Byte1]: 62
1731 08:05:59.590803
1732 08:05:59.591314 Set Vref, RX VrefLevel [Byte0]: 63
1733 08:05:59.594213 [Byte1]: 63
1734 08:05:59.598359
1735 08:05:59.598889 Set Vref, RX VrefLevel [Byte0]: 64
1736 08:05:59.601864 [Byte1]: 64
1737 08:05:59.606215
1738 08:05:59.606824 Set Vref, RX VrefLevel [Byte0]: 65
1739 08:05:59.609599 [Byte1]: 65
1740 08:05:59.613940
1741 08:05:59.614448 Set Vref, RX VrefLevel [Byte0]: 66
1742 08:05:59.616934 [Byte1]: 66
1743 08:05:59.621388
1744 08:05:59.621798 Set Vref, RX VrefLevel [Byte0]: 67
1745 08:05:59.624722 [Byte1]: 67
1746 08:05:59.629017
1747 08:05:59.629432 Set Vref, RX VrefLevel [Byte0]: 68
1748 08:05:59.632606 [Byte1]: 68
1749 08:05:59.637023
1750 08:05:59.637533 Set Vref, RX VrefLevel [Byte0]: 69
1751 08:05:59.639801 [Byte1]: 69
1752 08:05:59.644015
1753 08:05:59.644426 Set Vref, RX VrefLevel [Byte0]: 70
1754 08:05:59.647280 [Byte1]: 70
1755 08:05:59.651966
1756 08:05:59.652442 Set Vref, RX VrefLevel [Byte0]: 71
1757 08:05:59.655266 [Byte1]: 71
1758 08:05:59.659554
1759 08:05:59.660051 Set Vref, RX VrefLevel [Byte0]: 72
1760 08:05:59.662548 [Byte1]: 72
1761 08:05:59.667083
1762 08:05:59.667610 Set Vref, RX VrefLevel [Byte0]: 73
1763 08:05:59.670687 [Byte1]: 73
1764 08:05:59.674704
1765 08:05:59.675154 Set Vref, RX VrefLevel [Byte0]: 74
1766 08:05:59.677906 [Byte1]: 74
1767 08:05:59.682496
1768 08:05:59.683051 Set Vref, RX VrefLevel [Byte0]: 75
1769 08:05:59.685406 [Byte1]: 75
1770 08:05:59.689756
1771 08:05:59.690213 Set Vref, RX VrefLevel [Byte0]: 76
1772 08:05:59.693570 [Byte1]: 76
1773 08:05:59.697435
1774 08:05:59.697933 Final RX Vref Byte 0 = 60 to rank0
1775 08:05:59.701400 Final RX Vref Byte 1 = 60 to rank0
1776 08:05:59.704116 Final RX Vref Byte 0 = 60 to rank1
1777 08:05:59.707297 Final RX Vref Byte 1 = 60 to rank1==
1778 08:05:59.711150 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 08:05:59.713877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 08:05:59.717809 ==
1781 08:05:59.718221 DQS Delay:
1782 08:05:59.718546 DQS0 = 0, DQS1 = 0
1783 08:05:59.720728 DQM Delay:
1784 08:05:59.721149 DQM0 = 83, DQM1 = 75
1785 08:05:59.724050 DQ Delay:
1786 08:05:59.724464 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =84
1787 08:05:59.727607 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1788 08:05:59.730684 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1789 08:05:59.733948 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1790 08:05:59.737612
1791 08:05:59.738021
1792 08:05:59.744328 [DQSOSCAuto] RK0, (LSB)MR18= 0x29fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1793 08:05:59.747674 CH1 RK0: MR19=605, MR18=29FD
1794 08:05:59.753899 CH1_RK0: MR19=0x605, MR18=0x29FD, DQSOSC=399, MR23=63, INC=92, DEC=61
1795 08:05:59.754317
1796 08:05:59.757797 ----->DramcWriteLeveling(PI) begin...
1797 08:05:59.758312 ==
1798 08:05:59.760287 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 08:05:59.764043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 08:05:59.764547 ==
1801 08:05:59.767697 Write leveling (Byte 0): 28 => 28
1802 08:05:59.770671 Write leveling (Byte 1): 29 => 29
1803 08:05:59.774402 DramcWriteLeveling(PI) end<-----
1804 08:05:59.774950
1805 08:05:59.775282 ==
1806 08:05:59.777542 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 08:05:59.781067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 08:05:59.781574 ==
1809 08:05:59.784748 [Gating] SW mode calibration
1810 08:05:59.790899 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 08:05:59.797815 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 08:05:59.801117 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 0)
1813 08:05:59.804386 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 08:05:59.807617 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 08:05:59.814623 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 08:05:59.817710 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 08:05:59.821091 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 08:05:59.827890 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 08:05:59.831274 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 08:05:59.835174 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 08:05:59.841342 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1822 08:05:59.844979 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 08:05:59.848294 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1824 08:05:59.855023 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1825 08:05:59.858661 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 08:05:59.862164 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 08:05:59.868581 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 08:05:59.871658 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1829 08:05:59.874851 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1830 08:05:59.878279 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1831 08:05:59.885410 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 08:05:59.888380 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 08:05:59.892146 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 08:05:59.898844 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 08:05:59.902654 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 08:05:59.905854 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 08:05:59.912185 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1838 08:05:59.915417 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1839 08:05:59.918792 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1840 08:05:59.922119 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1841 08:05:59.928727 0 9 20 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
1842 08:05:59.931992 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 08:05:59.935458 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1844 08:05:59.942510 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1845 08:05:59.945317 0 10 4 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 1)
1846 08:05:59.949212 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1847 08:05:59.955448 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 08:05:59.959086 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 08:05:59.962565 0 10 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1850 08:05:59.969160 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 08:05:59.972761 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 08:05:59.975838 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 08:05:59.979418 0 11 4 | B1->B0 | 2828 3131 | 0 1 | (0 0) (0 0)
1854 08:05:59.986483 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
1855 08:05:59.989552 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 08:05:59.992622 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 08:05:59.999214 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 08:06:00.002653 0 11 24 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
1859 08:06:00.006043 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 08:06:00.012604 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 08:06:00.016207 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1862 08:06:00.019530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 08:06:00.026813 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 08:06:00.030123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 08:06:00.033172 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 08:06:00.036210 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 08:06:00.043298 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 08:06:00.046578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 08:06:00.050142 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 08:06:00.056644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 08:06:00.060132 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 08:06:00.063375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 08:06:00.069865 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 08:06:00.073296 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 08:06:00.076844 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 08:06:00.083449 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 08:06:00.086655 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 08:06:00.090064 Total UI for P1: 0, mck2ui 16
1879 08:06:00.093528 best dqsien dly found for B0: ( 0, 14, 2)
1880 08:06:00.097354 Total UI for P1: 0, mck2ui 16
1881 08:06:00.100580 best dqsien dly found for B1: ( 0, 14, 2)
1882 08:06:00.103527 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1883 08:06:00.107449 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1884 08:06:00.107858
1885 08:06:00.111019 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1886 08:06:00.113653 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 08:06:00.117284 [Gating] SW calibration Done
1888 08:06:00.117792 ==
1889 08:06:00.120461 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 08:06:00.123613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 08:06:00.124025 ==
1892 08:06:00.127355 RX Vref Scan: 0
1893 08:06:00.127865
1894 08:06:00.128192 RX Vref 0 -> 0, step: 1
1895 08:06:00.128496
1896 08:06:00.130577 RX Delay -130 -> 252, step: 16
1897 08:06:00.134072 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1898 08:06:00.140676 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1899 08:06:00.143812 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1900 08:06:00.147254 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1901 08:06:00.150626 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1902 08:06:00.154145 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1903 08:06:00.160806 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1904 08:06:00.164522 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1905 08:06:00.167645 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1906 08:06:00.170800 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1907 08:06:00.174208 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1908 08:06:00.177338 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1909 08:06:00.184463 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1910 08:06:00.187712 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1911 08:06:00.190820 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 08:06:00.194799 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1913 08:06:00.195306 ==
1914 08:06:00.197896 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 08:06:00.204870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 08:06:00.205473 ==
1917 08:06:00.205815 DQS Delay:
1918 08:06:00.206122 DQS0 = 0, DQS1 = 0
1919 08:06:00.208191 DQM Delay:
1920 08:06:00.208707 DQM0 = 78, DQM1 = 76
1921 08:06:00.211453 DQ Delay:
1922 08:06:00.214545 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1923 08:06:00.215016 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1924 08:06:00.218357 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1925 08:06:00.221425 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1926 08:06:00.224611
1927 08:06:00.225136
1928 08:06:00.225469 ==
1929 08:06:00.228557 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 08:06:00.230897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 08:06:00.231319 ==
1932 08:06:00.231653
1933 08:06:00.231959
1934 08:06:00.234914 TX Vref Scan disable
1935 08:06:00.235551 == TX Byte 0 ==
1936 08:06:00.241848 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1937 08:06:00.245249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1938 08:06:00.245776 == TX Byte 1 ==
1939 08:06:00.251611 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1940 08:06:00.254591 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1941 08:06:00.255099 ==
1942 08:06:00.257610 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 08:06:00.261320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 08:06:00.261845 ==
1945 08:06:00.274597 TX Vref=22, minBit 10, minWin=26, winSum=439
1946 08:06:00.278057 TX Vref=24, minBit 0, minWin=27, winSum=448
1947 08:06:00.281486 TX Vref=26, minBit 0, minWin=27, winSum=447
1948 08:06:00.284879 TX Vref=28, minBit 2, minWin=28, winSum=453
1949 08:06:00.287969 TX Vref=30, minBit 0, minWin=28, winSum=452
1950 08:06:00.291357 TX Vref=32, minBit 2, minWin=28, winSum=453
1951 08:06:00.298170 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 28
1952 08:06:00.298624
1953 08:06:00.301912 Final TX Range 1 Vref 28
1954 08:06:00.302376
1955 08:06:00.302698 ==
1956 08:06:00.304930 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 08:06:00.308246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 08:06:00.308740 ==
1959 08:06:00.309104
1960 08:06:00.309408
1961 08:06:00.311621 TX Vref Scan disable
1962 08:06:00.315119 == TX Byte 0 ==
1963 08:06:00.318632 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 08:06:00.321498 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 08:06:00.325170 == TX Byte 1 ==
1966 08:06:00.328819 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1967 08:06:00.331746 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1968 08:06:00.332161
1969 08:06:00.335061 [DATLAT]
1970 08:06:00.335535 Freq=800, CH1 RK1
1971 08:06:00.335926
1972 08:06:00.338518 DATLAT Default: 0xa
1973 08:06:00.339015 0, 0xFFFF, sum = 0
1974 08:06:00.341669 1, 0xFFFF, sum = 0
1975 08:06:00.342156 2, 0xFFFF, sum = 0
1976 08:06:00.345226 3, 0xFFFF, sum = 0
1977 08:06:00.345619 4, 0xFFFF, sum = 0
1978 08:06:00.348654 5, 0xFFFF, sum = 0
1979 08:06:00.349123 6, 0xFFFF, sum = 0
1980 08:06:00.352349 7, 0xFFFF, sum = 0
1981 08:06:00.352815 8, 0xFFFF, sum = 0
1982 08:06:00.355527 9, 0x0, sum = 1
1983 08:06:00.356054 10, 0x0, sum = 2
1984 08:06:00.358679 11, 0x0, sum = 3
1985 08:06:00.359223 12, 0x0, sum = 4
1986 08:06:00.361997 best_step = 10
1987 08:06:00.362604
1988 08:06:00.363074 ==
1989 08:06:00.365352 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 08:06:00.368810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 08:06:00.369226 ==
1992 08:06:00.369557 RX Vref Scan: 0
1993 08:06:00.369865
1994 08:06:00.372134 RX Vref 0 -> 0, step: 1
1995 08:06:00.372548
1996 08:06:00.375119 RX Delay -111 -> 252, step: 8
1997 08:06:00.378647 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1998 08:06:00.385520 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1999 08:06:00.388919 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2000 08:06:00.391978 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2001 08:06:00.395571 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2002 08:06:00.398774 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2003 08:06:00.405475 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2004 08:06:00.408995 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2005 08:06:00.413032 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
2006 08:06:00.415878 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2007 08:06:00.419020 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2008 08:06:00.422493 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2009 08:06:00.429578 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2010 08:06:00.433148 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2011 08:06:00.436055 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2012 08:06:00.439167 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2013 08:06:00.439599 ==
2014 08:06:00.442470 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 08:06:00.449390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 08:06:00.449808 ==
2017 08:06:00.450138 DQS Delay:
2018 08:06:00.450442 DQS0 = 0, DQS1 = 0
2019 08:06:00.452398 DQM Delay:
2020 08:06:00.452810 DQM0 = 80, DQM1 = 76
2021 08:06:00.455837 DQ Delay:
2022 08:06:00.459303 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2023 08:06:00.459906 DQ4 =80, DQ5 =88, DQ6 =92, DQ7 =76
2024 08:06:00.462543 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
2025 08:06:00.465865 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2026 08:06:00.469303
2027 08:06:00.469860
2028 08:06:00.476231 [DQSOSCAuto] RK1, (LSB)MR18= 0x2430, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2029 08:06:00.479506 CH1 RK1: MR19=606, MR18=2430
2030 08:06:00.486648 CH1_RK1: MR19=0x606, MR18=0x2430, DQSOSC=397, MR23=63, INC=93, DEC=62
2031 08:06:00.489343 [RxdqsGatingPostProcess] freq 800
2032 08:06:00.493073 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 08:06:00.496355 Pre-setting of DQS Precalculation
2034 08:06:00.502669 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 08:06:00.509640 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 08:06:00.516136 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 08:06:00.516729
2038 08:06:00.517180
2039 08:06:00.519760 [Calibration Summary] 1600 Mbps
2040 08:06:00.520174 CH 0, Rank 0
2041 08:06:00.523200 SW Impedance : PASS
2042 08:06:00.526077 DUTY Scan : NO K
2043 08:06:00.526489 ZQ Calibration : PASS
2044 08:06:00.530355 Jitter Meter : NO K
2045 08:06:00.530919 CBT Training : PASS
2046 08:06:00.532829 Write leveling : PASS
2047 08:06:00.536344 RX DQS gating : PASS
2048 08:06:00.536910 RX DQ/DQS(RDDQC) : PASS
2049 08:06:00.539829 TX DQ/DQS : PASS
2050 08:06:00.542889 RX DATLAT : PASS
2051 08:06:00.543347 RX DQ/DQS(Engine): PASS
2052 08:06:00.546900 TX OE : NO K
2053 08:06:00.547406 All Pass.
2054 08:06:00.547734
2055 08:06:00.549723 CH 0, Rank 1
2056 08:06:00.550135 SW Impedance : PASS
2057 08:06:00.553569 DUTY Scan : NO K
2058 08:06:00.556679 ZQ Calibration : PASS
2059 08:06:00.557093 Jitter Meter : NO K
2060 08:06:00.559914 CBT Training : PASS
2061 08:06:00.560330 Write leveling : PASS
2062 08:06:00.563128 RX DQS gating : PASS
2063 08:06:00.566599 RX DQ/DQS(RDDQC) : PASS
2064 08:06:00.567057 TX DQ/DQS : PASS
2065 08:06:00.569885 RX DATLAT : PASS
2066 08:06:00.573595 RX DQ/DQS(Engine): PASS
2067 08:06:00.574081 TX OE : NO K
2068 08:06:00.576943 All Pass.
2069 08:06:00.577451
2070 08:06:00.577777 CH 1, Rank 0
2071 08:06:00.580219 SW Impedance : PASS
2072 08:06:00.580634 DUTY Scan : NO K
2073 08:06:00.583395 ZQ Calibration : PASS
2074 08:06:00.586827 Jitter Meter : NO K
2075 08:06:00.587246 CBT Training : PASS
2076 08:06:00.589866 Write leveling : PASS
2077 08:06:00.590281 RX DQS gating : PASS
2078 08:06:00.593666 RX DQ/DQS(RDDQC) : PASS
2079 08:06:00.597366 TX DQ/DQS : PASS
2080 08:06:00.597878 RX DATLAT : PASS
2081 08:06:00.600138 RX DQ/DQS(Engine): PASS
2082 08:06:00.603780 TX OE : NO K
2083 08:06:00.604295 All Pass.
2084 08:06:00.604623
2085 08:06:00.604927 CH 1, Rank 1
2086 08:06:00.607057 SW Impedance : PASS
2087 08:06:00.610263 DUTY Scan : NO K
2088 08:06:00.610817 ZQ Calibration : PASS
2089 08:06:00.613749 Jitter Meter : NO K
2090 08:06:00.617339 CBT Training : PASS
2091 08:06:00.617843 Write leveling : PASS
2092 08:06:00.620916 RX DQS gating : PASS
2093 08:06:00.624083 RX DQ/DQS(RDDQC) : PASS
2094 08:06:00.624642 TX DQ/DQS : PASS
2095 08:06:00.626998 RX DATLAT : PASS
2096 08:06:00.627407 RX DQ/DQS(Engine): PASS
2097 08:06:00.630306 TX OE : NO K
2098 08:06:00.630941 All Pass.
2099 08:06:00.631485
2100 08:06:00.633594 DramC Write-DBI off
2101 08:06:00.636969 PER_BANK_REFRESH: Hybrid Mode
2102 08:06:00.637417 TX_TRACKING: ON
2103 08:06:00.640450 [GetDramInforAfterCalByMRR] Vendor 6.
2104 08:06:00.644041 [GetDramInforAfterCalByMRR] Revision 606.
2105 08:06:00.647306 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 08:06:00.650482 MR0 0x3b3b
2107 08:06:00.651035 MR8 0x5151
2108 08:06:00.654159 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 08:06:00.654768
2110 08:06:00.657204 MR0 0x3b3b
2111 08:06:00.657775 MR8 0x5151
2112 08:06:00.660761 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 08:06:00.661346
2114 08:06:00.670567 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 08:06:00.673987 [FAST_K] Save calibration result to emmc
2116 08:06:00.677465 [FAST_K] Save calibration result to emmc
2117 08:06:00.677874 dram_init: config_dvfs: 1
2118 08:06:00.684354 dramc_set_vcore_voltage set vcore to 662500
2119 08:06:00.684774 Read voltage for 1200, 2
2120 08:06:00.687488 Vio18 = 0
2121 08:06:00.687900 Vcore = 662500
2122 08:06:00.688227 Vdram = 0
2123 08:06:00.688585 Vddq = 0
2124 08:06:00.691082 Vmddr = 0
2125 08:06:00.694427 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 08:06:00.700913 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 08:06:00.701335 MEM_TYPE=3, freq_sel=15
2128 08:06:00.704524 sv_algorithm_assistance_LP4_1600
2129 08:06:00.711325 ============ PULL DRAM RESETB DOWN ============
2130 08:06:00.714636 ========== PULL DRAM RESETB DOWN end =========
2131 08:06:00.717371 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 08:06:00.720838 ===================================
2133 08:06:00.724181 LPDDR4 DRAM CONFIGURATION
2134 08:06:00.727984 ===================================
2135 08:06:00.728146 EX_ROW_EN[0] = 0x0
2136 08:06:00.731234 EX_ROW_EN[1] = 0x0
2137 08:06:00.734602 LP4Y_EN = 0x0
2138 08:06:00.734788 WORK_FSP = 0x0
2139 08:06:00.738379 WL = 0x4
2140 08:06:00.738557 RL = 0x4
2141 08:06:00.741501 BL = 0x2
2142 08:06:00.741680 RPST = 0x0
2143 08:06:00.745114 RD_PRE = 0x0
2144 08:06:00.745300 WR_PRE = 0x1
2145 08:06:00.748580 WR_PST = 0x0
2146 08:06:00.748776 DBI_WR = 0x0
2147 08:06:00.752026 DBI_RD = 0x0
2148 08:06:00.752224 OTF = 0x1
2149 08:06:00.755363 ===================================
2150 08:06:00.758302 ===================================
2151 08:06:00.758516 ANA top config
2152 08:06:00.761889 ===================================
2153 08:06:00.765192 DLL_ASYNC_EN = 0
2154 08:06:00.768562 ALL_SLAVE_EN = 0
2155 08:06:00.772221 NEW_RANK_MODE = 1
2156 08:06:00.775433 DLL_IDLE_MODE = 1
2157 08:06:00.775720 LP45_APHY_COMB_EN = 1
2158 08:06:00.778407 TX_ODT_DIS = 1
2159 08:06:00.782143 NEW_8X_MODE = 1
2160 08:06:00.785405 ===================================
2161 08:06:00.788933 ===================================
2162 08:06:00.792130 data_rate = 2400
2163 08:06:00.795174 CKR = 1
2164 08:06:00.795586 DQ_P2S_RATIO = 8
2165 08:06:00.798377 ===================================
2166 08:06:00.802250 CA_P2S_RATIO = 8
2167 08:06:00.805765 DQ_CA_OPEN = 0
2168 08:06:00.809284 DQ_SEMI_OPEN = 0
2169 08:06:00.812870 CA_SEMI_OPEN = 0
2170 08:06:00.813381 CA_FULL_RATE = 0
2171 08:06:00.815873 DQ_CKDIV4_EN = 0
2172 08:06:00.819222 CA_CKDIV4_EN = 0
2173 08:06:00.822223 CA_PREDIV_EN = 0
2174 08:06:00.825818 PH8_DLY = 17
2175 08:06:00.829850 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 08:06:00.830499 DQ_AAMCK_DIV = 4
2177 08:06:00.832107 CA_AAMCK_DIV = 4
2178 08:06:00.835651 CA_ADMCK_DIV = 4
2179 08:06:00.839327 DQ_TRACK_CA_EN = 0
2180 08:06:00.842873 CA_PICK = 1200
2181 08:06:00.846159 CA_MCKIO = 1200
2182 08:06:00.846570 MCKIO_SEMI = 0
2183 08:06:00.848951 PLL_FREQ = 2366
2184 08:06:00.852246 DQ_UI_PI_RATIO = 32
2185 08:06:00.855798 CA_UI_PI_RATIO = 0
2186 08:06:00.859073 ===================================
2187 08:06:00.862284 ===================================
2188 08:06:00.865916 memory_type:LPDDR4
2189 08:06:00.866439 GP_NUM : 10
2190 08:06:00.869132 SRAM_EN : 1
2191 08:06:00.872459 MD32_EN : 0
2192 08:06:00.876214 ===================================
2193 08:06:00.876631 [ANA_INIT] >>>>>>>>>>>>>>
2194 08:06:00.879110 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 08:06:00.883288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 08:06:00.886151 ===================================
2197 08:06:00.889232 data_rate = 2400,PCW = 0X5b00
2198 08:06:00.892441 ===================================
2199 08:06:00.896010 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 08:06:00.902858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 08:06:00.906125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 08:06:00.912805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 08:06:00.916081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 08:06:00.919759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 08:06:00.920179 [ANA_INIT] flow start
2206 08:06:00.922710 [ANA_INIT] PLL >>>>>>>>
2207 08:06:00.926284 [ANA_INIT] PLL <<<<<<<<
2208 08:06:00.926700 [ANA_INIT] MIDPI >>>>>>>>
2209 08:06:00.929566 [ANA_INIT] MIDPI <<<<<<<<
2210 08:06:00.932936 [ANA_INIT] DLL >>>>>>>>
2211 08:06:00.933404 [ANA_INIT] DLL <<<<<<<<
2212 08:06:00.936092 [ANA_INIT] flow end
2213 08:06:00.939619 ============ LP4 DIFF to SE enter ============
2214 08:06:00.942654 ============ LP4 DIFF to SE exit ============
2215 08:06:00.946443 [ANA_INIT] <<<<<<<<<<<<<
2216 08:06:00.949594 [Flow] Enable top DCM control >>>>>
2217 08:06:00.953052 [Flow] Enable top DCM control <<<<<
2218 08:06:00.956344 Enable DLL master slave shuffle
2219 08:06:00.963196 ==============================================================
2220 08:06:00.963633 Gating Mode config
2221 08:06:00.969679 ==============================================================
2222 08:06:00.970225 Config description:
2223 08:06:00.979901 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 08:06:00.986980 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 08:06:00.993467 SELPH_MODE 0: By rank 1: By Phase
2226 08:06:00.996524 ==============================================================
2227 08:06:00.999980 GAT_TRACK_EN = 1
2228 08:06:01.002998 RX_GATING_MODE = 2
2229 08:06:01.006504 RX_GATING_TRACK_MODE = 2
2230 08:06:01.010367 SELPH_MODE = 1
2231 08:06:01.013476 PICG_EARLY_EN = 1
2232 08:06:01.016816 VALID_LAT_VALUE = 1
2233 08:06:01.019888 ==============================================================
2234 08:06:01.023226 Enter into Gating configuration >>>>
2235 08:06:01.027088 Exit from Gating configuration <<<<
2236 08:06:01.030427 Enter into DVFS_PRE_config >>>>>
2237 08:06:01.040336 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 08:06:01.043867 Exit from DVFS_PRE_config <<<<<
2239 08:06:01.046784 Enter into PICG configuration >>>>
2240 08:06:01.050600 Exit from PICG configuration <<<<
2241 08:06:01.053645 [RX_INPUT] configuration >>>>>
2242 08:06:01.056831 [RX_INPUT] configuration <<<<<
2243 08:06:01.060493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 08:06:01.067102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 08:06:01.073806 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 08:06:01.080753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 08:06:01.087457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 08:06:01.090780 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 08:06:01.093897 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 08:06:01.100908 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 08:06:01.104134 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 08:06:01.107894 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 08:06:01.111217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 08:06:01.117907 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 08:06:01.121255 ===================================
2256 08:06:01.121668 LPDDR4 DRAM CONFIGURATION
2257 08:06:01.124966 ===================================
2258 08:06:01.127770 EX_ROW_EN[0] = 0x0
2259 08:06:01.131526 EX_ROW_EN[1] = 0x0
2260 08:06:01.131955 LP4Y_EN = 0x0
2261 08:06:01.134509 WORK_FSP = 0x0
2262 08:06:01.134987 WL = 0x4
2263 08:06:01.137882 RL = 0x4
2264 08:06:01.138459 BL = 0x2
2265 08:06:01.141113 RPST = 0x0
2266 08:06:01.141651 RD_PRE = 0x0
2267 08:06:01.144424 WR_PRE = 0x1
2268 08:06:01.144994 WR_PST = 0x0
2269 08:06:01.148178 DBI_WR = 0x0
2270 08:06:01.148703 DBI_RD = 0x0
2271 08:06:01.151391 OTF = 0x1
2272 08:06:01.154540 ===================================
2273 08:06:01.158193 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 08:06:01.161356 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 08:06:01.164584 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 08:06:01.168149 ===================================
2277 08:06:01.171402 LPDDR4 DRAM CONFIGURATION
2278 08:06:01.175046 ===================================
2279 08:06:01.178318 EX_ROW_EN[0] = 0x10
2280 08:06:01.178964 EX_ROW_EN[1] = 0x0
2281 08:06:01.181688 LP4Y_EN = 0x0
2282 08:06:01.182099 WORK_FSP = 0x0
2283 08:06:01.184862 WL = 0x4
2284 08:06:01.185275 RL = 0x4
2285 08:06:01.188468 BL = 0x2
2286 08:06:01.188884 RPST = 0x0
2287 08:06:01.191552 RD_PRE = 0x0
2288 08:06:01.191976 WR_PRE = 0x1
2289 08:06:01.194904 WR_PST = 0x0
2290 08:06:01.195542 DBI_WR = 0x0
2291 08:06:01.198359 DBI_RD = 0x0
2292 08:06:01.198825 OTF = 0x1
2293 08:06:01.201640 ===================================
2294 08:06:01.208568 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 08:06:01.208982 ==
2296 08:06:01.211758 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 08:06:01.218458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 08:06:01.218901 ==
2299 08:06:01.219144 [Duty_Offset_Calibration]
2300 08:06:01.221932 B0:3 B1:-1 CA:1
2301 08:06:01.222224
2302 08:06:01.225054 [DutyScan_Calibration_Flow] k_type=0
2303 08:06:01.233750
2304 08:06:01.233967 ==CLK 0==
2305 08:06:01.236341 Final CLK duty delay cell = -4
2306 08:06:01.240176 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2307 08:06:01.243119 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2308 08:06:01.246336 [-4] AVG Duty = 4953%(X100)
2309 08:06:01.246559
2310 08:06:01.250057 CH0 CLK Duty spec in!! Max-Min= 156%
2311 08:06:01.253134 [DutyScan_Calibration_Flow] ====Done====
2312 08:06:01.253357
2313 08:06:01.256337 [DutyScan_Calibration_Flow] k_type=1
2314 08:06:01.271965
2315 08:06:01.272185 ==DQS 0 ==
2316 08:06:01.275284 Final DQS duty delay cell = 0
2317 08:06:01.278683 [0] MAX Duty = 5125%(X100), DQS PI = 42
2318 08:06:01.281715 [0] MIN Duty = 4969%(X100), DQS PI = 14
2319 08:06:01.281938 [0] AVG Duty = 5047%(X100)
2320 08:06:01.285237
2321 08:06:01.285508 ==DQS 1 ==
2322 08:06:01.288625 Final DQS duty delay cell = -4
2323 08:06:01.292108 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2324 08:06:01.295645 [-4] MIN Duty = 5000%(X100), DQS PI = 46
2325 08:06:01.298884 [-4] AVG Duty = 5062%(X100)
2326 08:06:01.299298
2327 08:06:01.302393 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2328 08:06:01.302862
2329 08:06:01.305718 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2330 08:06:01.308967 [DutyScan_Calibration_Flow] ====Done====
2331 08:06:01.309380
2332 08:06:01.312149 [DutyScan_Calibration_Flow] k_type=3
2333 08:06:01.329130
2334 08:06:01.329541 ==DQM 0 ==
2335 08:06:01.332517 Final DQM duty delay cell = 0
2336 08:06:01.335611 [0] MAX Duty = 5000%(X100), DQS PI = 36
2337 08:06:01.339258 [0] MIN Duty = 4906%(X100), DQS PI = 2
2338 08:06:01.339673 [0] AVG Duty = 4953%(X100)
2339 08:06:01.340000
2340 08:06:01.342432 ==DQM 1 ==
2341 08:06:01.345583 Final DQM duty delay cell = 0
2342 08:06:01.349188 [0] MAX Duty = 5124%(X100), DQS PI = 32
2343 08:06:01.352912 [0] MIN Duty = 4969%(X100), DQS PI = 10
2344 08:06:01.353325 [0] AVG Duty = 5046%(X100)
2345 08:06:01.353650
2346 08:06:01.355941 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2347 08:06:01.359033
2348 08:06:01.362326 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2349 08:06:01.365680 [DutyScan_Calibration_Flow] ====Done====
2350 08:06:01.366084
2351 08:06:01.369089 [DutyScan_Calibration_Flow] k_type=2
2352 08:06:01.384483
2353 08:06:01.384894 ==DQ 0 ==
2354 08:06:01.387923 Final DQ duty delay cell = -4
2355 08:06:01.391178 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2356 08:06:01.394289 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2357 08:06:01.398165 [-4] AVG Duty = 4968%(X100)
2358 08:06:01.398245
2359 08:06:01.398308 ==DQ 1 ==
2360 08:06:01.401340 Final DQ duty delay cell = 0
2361 08:06:01.404196 [0] MAX Duty = 5031%(X100), DQS PI = 26
2362 08:06:01.407709 [0] MIN Duty = 4907%(X100), DQS PI = 46
2363 08:06:01.407789 [0] AVG Duty = 4969%(X100)
2364 08:06:01.407852
2365 08:06:01.411623 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2366 08:06:01.414145
2367 08:06:01.417842 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2368 08:06:01.421147 [DutyScan_Calibration_Flow] ====Done====
2369 08:06:01.421227 ==
2370 08:06:01.424432 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 08:06:01.427890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 08:06:01.427972 ==
2373 08:06:01.431099 [Duty_Offset_Calibration]
2374 08:06:01.431187 B0:1 B1:1 CA:2
2375 08:06:01.431251
2376 08:06:01.434633 [DutyScan_Calibration_Flow] k_type=0
2377 08:06:01.444339
2378 08:06:01.444419 ==CLK 0==
2379 08:06:01.447682 Final CLK duty delay cell = 0
2380 08:06:01.451340 [0] MAX Duty = 5156%(X100), DQS PI = 24
2381 08:06:01.454393 [0] MIN Duty = 4969%(X100), DQS PI = 38
2382 08:06:01.454474 [0] AVG Duty = 5062%(X100)
2383 08:06:01.454538
2384 08:06:01.457768 CH1 CLK Duty spec in!! Max-Min= 187%
2385 08:06:01.464931 [DutyScan_Calibration_Flow] ====Done====
2386 08:06:01.465012
2387 08:06:01.467744 [DutyScan_Calibration_Flow] k_type=1
2388 08:06:01.483753
2389 08:06:01.483835 ==DQS 0 ==
2390 08:06:01.487277 Final DQS duty delay cell = 0
2391 08:06:01.490653 [0] MAX Duty = 5031%(X100), DQS PI = 20
2392 08:06:01.493875 [0] MIN Duty = 4844%(X100), DQS PI = 50
2393 08:06:01.493956 [0] AVG Duty = 4937%(X100)
2394 08:06:01.497193
2395 08:06:01.497289 ==DQS 1 ==
2396 08:06:01.500934 Final DQS duty delay cell = 0
2397 08:06:01.504089 [0] MAX Duty = 5062%(X100), DQS PI = 36
2398 08:06:01.507130 [0] MIN Duty = 4907%(X100), DQS PI = 16
2399 08:06:01.507211 [0] AVG Duty = 4984%(X100)
2400 08:06:01.510608
2401 08:06:01.513852 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2402 08:06:01.513933
2403 08:06:01.517244 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2404 08:06:01.520612 [DutyScan_Calibration_Flow] ====Done====
2405 08:06:01.520693
2406 08:06:01.523813 [DutyScan_Calibration_Flow] k_type=3
2407 08:06:01.540327
2408 08:06:01.540408 ==DQM 0 ==
2409 08:06:01.543718 Final DQM duty delay cell = 0
2410 08:06:01.547252 [0] MAX Duty = 5093%(X100), DQS PI = 16
2411 08:06:01.550307 [0] MIN Duty = 4875%(X100), DQS PI = 50
2412 08:06:01.550388 [0] AVG Duty = 4984%(X100)
2413 08:06:01.554241
2414 08:06:01.554322 ==DQM 1 ==
2415 08:06:01.557102 Final DQM duty delay cell = 0
2416 08:06:01.561099 [0] MAX Duty = 5156%(X100), DQS PI = 62
2417 08:06:01.564131 [0] MIN Duty = 4969%(X100), DQS PI = 4
2418 08:06:01.564212 [0] AVG Duty = 5062%(X100)
2419 08:06:01.564276
2420 08:06:01.570705 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2421 08:06:01.570822
2422 08:06:01.573844 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2423 08:06:01.577048 [DutyScan_Calibration_Flow] ====Done====
2424 08:06:01.577128
2425 08:06:01.580579 [DutyScan_Calibration_Flow] k_type=2
2426 08:06:01.596915
2427 08:06:01.596996 ==DQ 0 ==
2428 08:06:01.600137 Final DQ duty delay cell = 0
2429 08:06:01.603554 [0] MAX Duty = 5156%(X100), DQS PI = 18
2430 08:06:01.606978 [0] MIN Duty = 4938%(X100), DQS PI = 50
2431 08:06:01.607060 [0] AVG Duty = 5047%(X100)
2432 08:06:01.607150
2433 08:06:01.610414 ==DQ 1 ==
2434 08:06:01.613485 Final DQ duty delay cell = 0
2435 08:06:01.616862 [0] MAX Duty = 5093%(X100), DQS PI = 8
2436 08:06:01.620305 [0] MIN Duty = 5031%(X100), DQS PI = 2
2437 08:06:01.620412 [0] AVG Duty = 5062%(X100)
2438 08:06:01.620507
2439 08:06:01.623697 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2440 08:06:01.623805
2441 08:06:01.627307 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2442 08:06:01.630540 [DutyScan_Calibration_Flow] ====Done====
2443 08:06:01.635901 nWR fixed to 30
2444 08:06:01.639354 [ModeRegInit_LP4] CH0 RK0
2445 08:06:01.639449 [ModeRegInit_LP4] CH0 RK1
2446 08:06:01.642661 [ModeRegInit_LP4] CH1 RK0
2447 08:06:01.645683 [ModeRegInit_LP4] CH1 RK1
2448 08:06:01.645778 match AC timing 7
2449 08:06:01.652688 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 08:06:01.656167 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 08:06:01.659116 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 08:06:01.665864 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 08:06:01.669379 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 08:06:01.669454 ==
2455 08:06:01.672467 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 08:06:01.676016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 08:06:01.676090 ==
2458 08:06:01.682544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 08:06:01.689149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2460 08:06:01.696898 [CA 0] Center 40 (10~71) winsize 62
2461 08:06:01.699774 [CA 1] Center 39 (9~70) winsize 62
2462 08:06:01.703489 [CA 2] Center 36 (6~67) winsize 62
2463 08:06:01.706541 [CA 3] Center 36 (6~66) winsize 61
2464 08:06:01.710094 [CA 4] Center 34 (4~65) winsize 62
2465 08:06:01.713596 [CA 5] Center 34 (4~64) winsize 61
2466 08:06:01.713677
2467 08:06:01.716780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2468 08:06:01.716861
2469 08:06:01.720601 [CATrainingPosCal] consider 1 rank data
2470 08:06:01.723453 u2DelayCellTimex100 = 270/100 ps
2471 08:06:01.726810 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2472 08:06:01.730193 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2473 08:06:01.733617 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2474 08:06:01.740337 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2475 08:06:01.743819 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2476 08:06:01.747396 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2477 08:06:01.747477
2478 08:06:01.750182 CA PerBit enable=1, Macro0, CA PI delay=34
2479 08:06:01.750263
2480 08:06:01.754080 [CBTSetCACLKResult] CA Dly = 34
2481 08:06:01.754163 CS Dly: 7 (0~38)
2482 08:06:01.754264 ==
2483 08:06:01.756883 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 08:06:01.763534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 08:06:01.763621 ==
2486 08:06:01.766962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 08:06:01.773966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 08:06:01.782743 [CA 0] Center 39 (9~70) winsize 62
2489 08:06:01.785825 [CA 1] Center 39 (9~70) winsize 62
2490 08:06:01.789636 [CA 2] Center 36 (6~67) winsize 62
2491 08:06:01.792930 [CA 3] Center 35 (5~66) winsize 62
2492 08:06:01.796232 [CA 4] Center 34 (4~65) winsize 62
2493 08:06:01.799466 [CA 5] Center 34 (4~64) winsize 61
2494 08:06:01.799548
2495 08:06:01.803148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2496 08:06:01.803229
2497 08:06:01.806019 [CATrainingPosCal] consider 2 rank data
2498 08:06:01.809579 u2DelayCellTimex100 = 270/100 ps
2499 08:06:01.813243 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2500 08:06:01.816399 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2501 08:06:01.819323 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2502 08:06:01.826052 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2503 08:06:01.829964 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2504 08:06:01.833152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2505 08:06:01.833251
2506 08:06:01.836259 CA PerBit enable=1, Macro0, CA PI delay=34
2507 08:06:01.836338
2508 08:06:01.839811 [CBTSetCACLKResult] CA Dly = 34
2509 08:06:01.839885 CS Dly: 8 (0~41)
2510 08:06:01.839945
2511 08:06:01.842716 ----->DramcWriteLeveling(PI) begin...
2512 08:06:01.842832 ==
2513 08:06:01.846287 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 08:06:01.853344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 08:06:01.853447 ==
2516 08:06:01.856196 Write leveling (Byte 0): 30 => 30
2517 08:06:01.856294 Write leveling (Byte 1): 29 => 29
2518 08:06:01.859700 DramcWriteLeveling(PI) end<-----
2519 08:06:01.859774
2520 08:06:01.863096 ==
2521 08:06:01.863179 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 08:06:01.870094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 08:06:01.870176 ==
2524 08:06:01.873184 [Gating] SW mode calibration
2525 08:06:01.880114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 08:06:01.883343 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 08:06:01.890136 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 08:06:01.893414 0 15 4 | B1->B0 | 2323 3131 | 1 1 | (0 0) (1 1)
2529 08:06:01.896903 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2530 08:06:01.903390 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 08:06:01.906908 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 08:06:01.910274 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 08:06:01.913468 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 08:06:01.920304 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 08:06:01.923509 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
2536 08:06:01.926856 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 08:06:01.933503 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 08:06:01.936833 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 08:06:01.940355 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 08:06:01.947370 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 08:06:01.950509 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 08:06:01.953999 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 08:06:01.957332 1 1 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2544 08:06:01.963822 1 1 4 | B1->B0 | 3f3e 4646 | 1 0 | (0 0) (0 0)
2545 08:06:01.967108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 08:06:01.970480 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 08:06:01.977233 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 08:06:01.980503 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 08:06:01.983823 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 08:06:01.990930 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 08:06:01.994186 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2552 08:06:01.997540 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 08:06:02.003994 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 08:06:02.007858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 08:06:02.011189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 08:06:02.014621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 08:06:02.020928 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 08:06:02.024653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 08:06:02.027623 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 08:06:02.034464 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 08:06:02.037795 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 08:06:02.041221 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 08:06:02.047605 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 08:06:02.051272 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 08:06:02.054376 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 08:06:02.061253 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 08:06:02.064617 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 08:06:02.068126 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 08:06:02.071423 Total UI for P1: 0, mck2ui 16
2570 08:06:02.074876 best dqsien dly found for B0: ( 1, 4, 0)
2571 08:06:02.078151 Total UI for P1: 0, mck2ui 16
2572 08:06:02.081535 best dqsien dly found for B1: ( 1, 4, 2)
2573 08:06:02.084717 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2574 08:06:02.087970 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2575 08:06:02.088049
2576 08:06:02.091447 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2577 08:06:02.094674 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2578 08:06:02.098614 [Gating] SW calibration Done
2579 08:06:02.098688 ==
2580 08:06:02.101501 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 08:06:02.104830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 08:06:02.108272 ==
2583 08:06:02.108353 RX Vref Scan: 0
2584 08:06:02.108415
2585 08:06:02.111415 RX Vref 0 -> 0, step: 1
2586 08:06:02.111487
2587 08:06:02.111548 RX Delay -40 -> 252, step: 8
2588 08:06:02.118654 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2589 08:06:02.122055 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2590 08:06:02.125106 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2591 08:06:02.128722 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2592 08:06:02.132346 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2593 08:06:02.138889 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2594 08:06:02.142089 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2595 08:06:02.145558 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2596 08:06:02.148572 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2597 08:06:02.152226 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2598 08:06:02.155687 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2599 08:06:02.162005 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2600 08:06:02.165480 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2601 08:06:02.169011 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2602 08:06:02.172232 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2603 08:06:02.175676 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2604 08:06:02.178892 ==
2605 08:06:02.178963 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 08:06:02.185904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 08:06:02.185978 ==
2608 08:06:02.186046 DQS Delay:
2609 08:06:02.189259 DQS0 = 0, DQS1 = 0
2610 08:06:02.189331 DQM Delay:
2611 08:06:02.192593 DQM0 = 115, DQM1 = 107
2612 08:06:02.192669 DQ Delay:
2613 08:06:02.195779 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2614 08:06:02.199325 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2615 08:06:02.202467 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2616 08:06:02.206024 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2617 08:06:02.206094
2618 08:06:02.206153
2619 08:06:02.206215 ==
2620 08:06:02.209359 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 08:06:02.213572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 08:06:02.213678 ==
2623 08:06:02.216257
2624 08:06:02.216364
2625 08:06:02.216452 TX Vref Scan disable
2626 08:06:02.219234 == TX Byte 0 ==
2627 08:06:02.222849 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2628 08:06:02.226154 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2629 08:06:02.229352 == TX Byte 1 ==
2630 08:06:02.233282 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2631 08:06:02.236386 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2632 08:06:02.236457 ==
2633 08:06:02.239750 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 08:06:02.246010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 08:06:02.246089 ==
2636 08:06:02.256709 TX Vref=22, minBit 1, minWin=25, winSum=419
2637 08:06:02.260199 TX Vref=24, minBit 1, minWin=25, winSum=424
2638 08:06:02.263248 TX Vref=26, minBit 5, minWin=25, winSum=428
2639 08:06:02.266645 TX Vref=28, minBit 0, minWin=26, winSum=433
2640 08:06:02.270032 TX Vref=30, minBit 4, minWin=26, winSum=439
2641 08:06:02.273649 TX Vref=32, minBit 1, minWin=26, winSum=433
2642 08:06:02.280178 [TxChooseVref] Worse bit 4, Min win 26, Win sum 439, Final Vref 30
2643 08:06:02.280278
2644 08:06:02.283887 Final TX Range 1 Vref 30
2645 08:06:02.283962
2646 08:06:02.284023 ==
2647 08:06:02.286799 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 08:06:02.290539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 08:06:02.290632 ==
2650 08:06:02.290730
2651 08:06:02.290790
2652 08:06:02.293863 TX Vref Scan disable
2653 08:06:02.297378 == TX Byte 0 ==
2654 08:06:02.300111 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2655 08:06:02.303701 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2656 08:06:02.307359 == TX Byte 1 ==
2657 08:06:02.310791 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2658 08:06:02.313808 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2659 08:06:02.313876
2660 08:06:02.316967 [DATLAT]
2661 08:06:02.317033 Freq=1200, CH0 RK0
2662 08:06:02.317091
2663 08:06:02.320534 DATLAT Default: 0xd
2664 08:06:02.320605 0, 0xFFFF, sum = 0
2665 08:06:02.323626 1, 0xFFFF, sum = 0
2666 08:06:02.323693 2, 0xFFFF, sum = 0
2667 08:06:02.327551 3, 0xFFFF, sum = 0
2668 08:06:02.327620 4, 0xFFFF, sum = 0
2669 08:06:02.330334 5, 0xFFFF, sum = 0
2670 08:06:02.330438 6, 0xFFFF, sum = 0
2671 08:06:02.334148 7, 0xFFFF, sum = 0
2672 08:06:02.334250 8, 0xFFFF, sum = 0
2673 08:06:02.337274 9, 0xFFFF, sum = 0
2674 08:06:02.337344 10, 0xFFFF, sum = 0
2675 08:06:02.340879 11, 0xFFFF, sum = 0
2676 08:06:02.340951 12, 0x0, sum = 1
2677 08:06:02.343840 13, 0x0, sum = 2
2678 08:06:02.343940 14, 0x0, sum = 3
2679 08:06:02.347016 15, 0x0, sum = 4
2680 08:06:02.347096 best_step = 13
2681 08:06:02.347156
2682 08:06:02.347211 ==
2683 08:06:02.350625 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 08:06:02.354468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 08:06:02.357717 ==
2686 08:06:02.357783 RX Vref Scan: 1
2687 08:06:02.357841
2688 08:06:02.360767 Set Vref Range= 32 -> 127
2689 08:06:02.360833
2690 08:06:02.364057 RX Vref 32 -> 127, step: 1
2691 08:06:02.364123
2692 08:06:02.364180 RX Delay -21 -> 252, step: 4
2693 08:06:02.364242
2694 08:06:02.367344 Set Vref, RX VrefLevel [Byte0]: 32
2695 08:06:02.371315 [Byte1]: 32
2696 08:06:02.374823
2697 08:06:02.374895 Set Vref, RX VrefLevel [Byte0]: 33
2698 08:06:02.378203 [Byte1]: 33
2699 08:06:02.383089
2700 08:06:02.383179 Set Vref, RX VrefLevel [Byte0]: 34
2701 08:06:02.386227 [Byte1]: 34
2702 08:06:02.390666
2703 08:06:02.390797 Set Vref, RX VrefLevel [Byte0]: 35
2704 08:06:02.393886 [Byte1]: 35
2705 08:06:02.398820
2706 08:06:02.398890 Set Vref, RX VrefLevel [Byte0]: 36
2707 08:06:02.401966 [Byte1]: 36
2708 08:06:02.406520
2709 08:06:02.406592 Set Vref, RX VrefLevel [Byte0]: 37
2710 08:06:02.409832 [Byte1]: 37
2711 08:06:02.414622
2712 08:06:02.414730 Set Vref, RX VrefLevel [Byte0]: 38
2713 08:06:02.417789 [Byte1]: 38
2714 08:06:02.422332
2715 08:06:02.422427 Set Vref, RX VrefLevel [Byte0]: 39
2716 08:06:02.425873 [Byte1]: 39
2717 08:06:02.430213
2718 08:06:02.430282 Set Vref, RX VrefLevel [Byte0]: 40
2719 08:06:02.433624 [Byte1]: 40
2720 08:06:02.438134
2721 08:06:02.438232 Set Vref, RX VrefLevel [Byte0]: 41
2722 08:06:02.441524 [Byte1]: 41
2723 08:06:02.446080
2724 08:06:02.446149 Set Vref, RX VrefLevel [Byte0]: 42
2725 08:06:02.449307 [Byte1]: 42
2726 08:06:02.454289
2727 08:06:02.454355 Set Vref, RX VrefLevel [Byte0]: 43
2728 08:06:02.457617 [Byte1]: 43
2729 08:06:02.461944
2730 08:06:02.462014 Set Vref, RX VrefLevel [Byte0]: 44
2731 08:06:02.465249 [Byte1]: 44
2732 08:06:02.470381
2733 08:06:02.470449 Set Vref, RX VrefLevel [Byte0]: 45
2734 08:06:02.473292 [Byte1]: 45
2735 08:06:02.478125
2736 08:06:02.478195 Set Vref, RX VrefLevel [Byte0]: 46
2737 08:06:02.481514 [Byte1]: 46
2738 08:06:02.486584
2739 08:06:02.486677 Set Vref, RX VrefLevel [Byte0]: 47
2740 08:06:02.488970 [Byte1]: 47
2741 08:06:02.493933
2742 08:06:02.494010 Set Vref, RX VrefLevel [Byte0]: 48
2743 08:06:02.497319 [Byte1]: 48
2744 08:06:02.501562
2745 08:06:02.501633 Set Vref, RX VrefLevel [Byte0]: 49
2746 08:06:02.505389 [Byte1]: 49
2747 08:06:02.510018
2748 08:06:02.510088 Set Vref, RX VrefLevel [Byte0]: 50
2749 08:06:02.512644 [Byte1]: 50
2750 08:06:02.517694
2751 08:06:02.517767 Set Vref, RX VrefLevel [Byte0]: 51
2752 08:06:02.521017 [Byte1]: 51
2753 08:06:02.525712
2754 08:06:02.525794 Set Vref, RX VrefLevel [Byte0]: 52
2755 08:06:02.528832 [Byte1]: 52
2756 08:06:02.533232
2757 08:06:02.533299 Set Vref, RX VrefLevel [Byte0]: 53
2758 08:06:02.537021 [Byte1]: 53
2759 08:06:02.541066
2760 08:06:02.541138 Set Vref, RX VrefLevel [Byte0]: 54
2761 08:06:02.544338 [Byte1]: 54
2762 08:06:02.549227
2763 08:06:02.549298 Set Vref, RX VrefLevel [Byte0]: 55
2764 08:06:02.552878 [Byte1]: 55
2765 08:06:02.557053
2766 08:06:02.557118 Set Vref, RX VrefLevel [Byte0]: 56
2767 08:06:02.560610 [Byte1]: 56
2768 08:06:02.564863
2769 08:06:02.564929 Set Vref, RX VrefLevel [Byte0]: 57
2770 08:06:02.568566 [Byte1]: 57
2771 08:06:02.572764
2772 08:06:02.572839 Set Vref, RX VrefLevel [Byte0]: 58
2773 08:06:02.576669 [Byte1]: 58
2774 08:06:02.580710
2775 08:06:02.580814 Set Vref, RX VrefLevel [Byte0]: 59
2776 08:06:02.584590 [Byte1]: 59
2777 08:06:02.589057
2778 08:06:02.589123 Set Vref, RX VrefLevel [Byte0]: 60
2779 08:06:02.592418 [Byte1]: 60
2780 08:06:02.596924
2781 08:06:02.596994 Set Vref, RX VrefLevel [Byte0]: 61
2782 08:06:02.600398 [Byte1]: 61
2783 08:06:02.604894
2784 08:06:02.604971 Set Vref, RX VrefLevel [Byte0]: 62
2785 08:06:02.607833 [Byte1]: 62
2786 08:06:02.613012
2787 08:06:02.613083 Set Vref, RX VrefLevel [Byte0]: 63
2788 08:06:02.616051 [Byte1]: 63
2789 08:06:02.620731
2790 08:06:02.620805 Set Vref, RX VrefLevel [Byte0]: 64
2791 08:06:02.623971 [Byte1]: 64
2792 08:06:02.628725
2793 08:06:02.628797 Set Vref, RX VrefLevel [Byte0]: 65
2794 08:06:02.631790 [Byte1]: 65
2795 08:06:02.636461
2796 08:06:02.636531 Set Vref, RX VrefLevel [Byte0]: 66
2797 08:06:02.640030 [Byte1]: 66
2798 08:06:02.644298
2799 08:06:02.644381 Set Vref, RX VrefLevel [Byte0]: 67
2800 08:06:02.647683 [Byte1]: 67
2801 08:06:02.652133
2802 08:06:02.652201 Set Vref, RX VrefLevel [Byte0]: 68
2803 08:06:02.655687 [Byte1]: 68
2804 08:06:02.660468
2805 08:06:02.660540 Final RX Vref Byte 0 = 56 to rank0
2806 08:06:02.663382 Final RX Vref Byte 1 = 50 to rank0
2807 08:06:02.667105 Final RX Vref Byte 0 = 56 to rank1
2808 08:06:02.670490 Final RX Vref Byte 1 = 50 to rank1==
2809 08:06:02.673871 Dram Type= 6, Freq= 0, CH_0, rank 0
2810 08:06:02.676910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2811 08:06:02.680463 ==
2812 08:06:02.680541 DQS Delay:
2813 08:06:02.680603 DQS0 = 0, DQS1 = 0
2814 08:06:02.683672 DQM Delay:
2815 08:06:02.683743 DQM0 = 114, DQM1 = 104
2816 08:06:02.687274 DQ Delay:
2817 08:06:02.690514 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2818 08:06:02.694112 DQ4 =114, DQ5 =110, DQ6 =120, DQ7 =122
2819 08:06:02.697373 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2820 08:06:02.700682 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2821 08:06:02.700755
2822 08:06:02.700814
2823 08:06:02.707053 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2824 08:06:02.710654 CH0 RK0: MR19=303, MR18=FEEE
2825 08:06:02.717399 CH0_RK0: MR19=0x303, MR18=0xFEEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2826 08:06:02.717476
2827 08:06:02.720833 ----->DramcWriteLeveling(PI) begin...
2828 08:06:02.720904 ==
2829 08:06:02.724018 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 08:06:02.727275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 08:06:02.727353 ==
2832 08:06:02.730755 Write leveling (Byte 0): 34 => 34
2833 08:06:02.733949 Write leveling (Byte 1): 28 => 28
2834 08:06:02.737447 DramcWriteLeveling(PI) end<-----
2835 08:06:02.737514
2836 08:06:02.737609 ==
2837 08:06:02.740607 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 08:06:02.744145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 08:06:02.744219 ==
2840 08:06:02.747725 [Gating] SW mode calibration
2841 08:06:02.754336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2842 08:06:02.761209 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2843 08:06:02.764391 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
2844 08:06:02.767457 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2845 08:06:02.774228 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 08:06:02.777836 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 08:06:02.780961 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 08:06:02.788090 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 08:06:02.791221 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 08:06:02.794388 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
2851 08:06:02.801228 1 0 0 | B1->B0 | 2d2d 2727 | 1 0 | (1 0) (0 0)
2852 08:06:02.804779 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 08:06:02.807816 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 08:06:02.814830 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 08:06:02.818010 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 08:06:02.821548 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 08:06:02.827889 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2858 08:06:02.831621 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2859 08:06:02.834616 1 1 0 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
2860 08:06:02.838093 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2861 08:06:02.845009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 08:06:02.848348 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 08:06:02.851520 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 08:06:02.858547 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 08:06:02.861991 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2866 08:06:02.865194 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2867 08:06:02.872033 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2868 08:06:02.875366 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2869 08:06:02.878403 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 08:06:02.882174 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 08:06:02.888368 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 08:06:02.891775 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 08:06:02.895455 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 08:06:02.902400 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 08:06:02.905428 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 08:06:02.908797 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 08:06:02.915707 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 08:06:02.918563 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 08:06:02.921903 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 08:06:02.929077 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 08:06:02.932137 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2882 08:06:02.935912 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2883 08:06:02.942026 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2884 08:06:02.942104 Total UI for P1: 0, mck2ui 16
2885 08:06:02.945977 best dqsien dly found for B0: ( 1, 3, 26)
2886 08:06:02.952250 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 08:06:02.955482 Total UI for P1: 0, mck2ui 16
2888 08:06:02.958881 best dqsien dly found for B1: ( 1, 3, 30)
2889 08:06:02.962404 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2890 08:06:02.965636 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2891 08:06:02.965704
2892 08:06:02.969191 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2893 08:06:02.972202 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2894 08:06:02.975530 [Gating] SW calibration Done
2895 08:06:02.975599 ==
2896 08:06:02.979177 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 08:06:02.982419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 08:06:02.982489 ==
2899 08:06:02.985790 RX Vref Scan: 0
2900 08:06:02.985855
2901 08:06:02.985911 RX Vref 0 -> 0, step: 1
2902 08:06:02.985967
2903 08:06:02.988890 RX Delay -40 -> 252, step: 8
2904 08:06:02.992600 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2905 08:06:02.999161 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2906 08:06:03.002474 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2907 08:06:03.006136 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2908 08:06:03.009303 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2909 08:06:03.012513 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2910 08:06:03.019100 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2911 08:06:03.022890 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2912 08:06:03.026138 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2913 08:06:03.029225 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2914 08:06:03.032538 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2915 08:06:03.036296 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2916 08:06:03.042780 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2917 08:06:03.046000 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2918 08:06:03.049618 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2919 08:06:03.052782 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2920 08:06:03.052847 ==
2921 08:06:03.056234 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 08:06:03.063286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 08:06:03.063360 ==
2924 08:06:03.063424 DQS Delay:
2925 08:06:03.063483 DQS0 = 0, DQS1 = 0
2926 08:06:03.066238 DQM Delay:
2927 08:06:03.066314 DQM0 = 116, DQM1 = 105
2928 08:06:03.069419 DQ Delay:
2929 08:06:03.073144 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2930 08:06:03.076182 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2931 08:06:03.079584 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2932 08:06:03.083213 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2933 08:06:03.083311
2934 08:06:03.083402
2935 08:06:03.083486 ==
2936 08:06:03.086654 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 08:06:03.089990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 08:06:03.090095 ==
2939 08:06:03.090155
2940 08:06:03.090211
2941 08:06:03.093690 TX Vref Scan disable
2942 08:06:03.096489 == TX Byte 0 ==
2943 08:06:03.099734 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2944 08:06:03.103143 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2945 08:06:03.106585 == TX Byte 1 ==
2946 08:06:03.109921 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2947 08:06:03.113844 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2948 08:06:03.113911 ==
2949 08:06:03.117020 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 08:06:03.120161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 08:06:03.123274 ==
2952 08:06:03.133810 TX Vref=22, minBit 0, minWin=25, winSum=418
2953 08:06:03.137692 TX Vref=24, minBit 1, minWin=25, winSum=424
2954 08:06:03.140586 TX Vref=26, minBit 0, minWin=26, winSum=427
2955 08:06:03.144160 TX Vref=28, minBit 2, minWin=26, winSum=435
2956 08:06:03.147332 TX Vref=30, minBit 3, minWin=26, winSum=434
2957 08:06:03.150573 TX Vref=32, minBit 3, minWin=26, winSum=435
2958 08:06:03.157620 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 28
2959 08:06:03.157700
2960 08:06:03.161273 Final TX Range 1 Vref 28
2961 08:06:03.161353
2962 08:06:03.161416 ==
2963 08:06:03.164332 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 08:06:03.167539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 08:06:03.167620 ==
2966 08:06:03.167684
2967 08:06:03.167743
2968 08:06:03.170892 TX Vref Scan disable
2969 08:06:03.174004 == TX Byte 0 ==
2970 08:06:03.177281 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2971 08:06:03.180796 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2972 08:06:03.184030 == TX Byte 1 ==
2973 08:06:03.187411 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2974 08:06:03.191058 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2975 08:06:03.191138
2976 08:06:03.194822 [DATLAT]
2977 08:06:03.194902 Freq=1200, CH0 RK1
2978 08:06:03.194965
2979 08:06:03.197453 DATLAT Default: 0xd
2980 08:06:03.197533 0, 0xFFFF, sum = 0
2981 08:06:03.201046 1, 0xFFFF, sum = 0
2982 08:06:03.201127 2, 0xFFFF, sum = 0
2983 08:06:03.204217 3, 0xFFFF, sum = 0
2984 08:06:03.204299 4, 0xFFFF, sum = 0
2985 08:06:03.207537 5, 0xFFFF, sum = 0
2986 08:06:03.207618 6, 0xFFFF, sum = 0
2987 08:06:03.210880 7, 0xFFFF, sum = 0
2988 08:06:03.210961 8, 0xFFFF, sum = 0
2989 08:06:03.214468 9, 0xFFFF, sum = 0
2990 08:06:03.214549 10, 0xFFFF, sum = 0
2991 08:06:03.217569 11, 0xFFFF, sum = 0
2992 08:06:03.217651 12, 0x0, sum = 1
2993 08:06:03.221106 13, 0x0, sum = 2
2994 08:06:03.221186 14, 0x0, sum = 3
2995 08:06:03.224397 15, 0x0, sum = 4
2996 08:06:03.224478 best_step = 13
2997 08:06:03.224541
2998 08:06:03.224599 ==
2999 08:06:03.227698 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 08:06:03.234836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 08:06:03.234908 ==
3002 08:06:03.234970 RX Vref Scan: 0
3003 08:06:03.235028
3004 08:06:03.238588 RX Vref 0 -> 0, step: 1
3005 08:06:03.238681
3006 08:06:03.241839 RX Delay -21 -> 252, step: 4
3007 08:06:03.244743 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3008 08:06:03.247916 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3009 08:06:03.251383 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
3010 08:06:03.258078 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3011 08:06:03.261313 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3012 08:06:03.264905 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3013 08:06:03.268142 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3014 08:06:03.272206 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3015 08:06:03.274839 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3016 08:06:03.281416 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3017 08:06:03.284788 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3018 08:06:03.288045 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3019 08:06:03.291626 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3020 08:06:03.295044 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3021 08:06:03.301752 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3022 08:06:03.304961 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3023 08:06:03.305033 ==
3024 08:06:03.308648 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 08:06:03.311801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 08:06:03.311877 ==
3027 08:06:03.315273 DQS Delay:
3028 08:06:03.315346 DQS0 = 0, DQS1 = 0
3029 08:06:03.315406 DQM Delay:
3030 08:06:03.318541 DQM0 = 114, DQM1 = 104
3031 08:06:03.318635 DQ Delay:
3032 08:06:03.322013 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
3033 08:06:03.325324 DQ4 =112, DQ5 =106, DQ6 =120, DQ7 =122
3034 08:06:03.328999 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3035 08:06:03.332008 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =114
3036 08:06:03.332087
3037 08:06:03.335486
3038 08:06:03.342087 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 407 ps
3039 08:06:03.345505 CH0 RK1: MR19=403, MR18=6F8
3040 08:06:03.348983 CH0_RK1: MR19=0x403, MR18=0x6F8, DQSOSC=407, MR23=63, INC=39, DEC=26
3041 08:06:03.352108 [RxdqsGatingPostProcess] freq 1200
3042 08:06:03.358995 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3043 08:06:03.362300 best DQS0 dly(2T, 0.5T) = (0, 12)
3044 08:06:03.365565 best DQS1 dly(2T, 0.5T) = (0, 12)
3045 08:06:03.369191 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3046 08:06:03.372487 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3047 08:06:03.375622 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 08:06:03.379116 best DQS1 dly(2T, 0.5T) = (0, 11)
3049 08:06:03.382519 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 08:06:03.385734 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3051 08:06:03.385814 Pre-setting of DQS Precalculation
3052 08:06:03.392280 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3053 08:06:03.392360 ==
3054 08:06:03.395624 Dram Type= 6, Freq= 0, CH_1, rank 0
3055 08:06:03.399376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 08:06:03.399456 ==
3057 08:06:03.405991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3058 08:06:03.412341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3059 08:06:03.419283 [CA 0] Center 38 (8~68) winsize 61
3060 08:06:03.422868 [CA 1] Center 38 (8~68) winsize 61
3061 08:06:03.426690 [CA 2] Center 35 (5~65) winsize 61
3062 08:06:03.429722 [CA 3] Center 34 (4~65) winsize 62
3063 08:06:03.433245 [CA 4] Center 34 (4~65) winsize 62
3064 08:06:03.436150 [CA 5] Center 34 (4~64) winsize 61
3065 08:06:03.436230
3066 08:06:03.440059 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3067 08:06:03.440139
3068 08:06:03.443326 [CATrainingPosCal] consider 1 rank data
3069 08:06:03.446398 u2DelayCellTimex100 = 270/100 ps
3070 08:06:03.450108 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3071 08:06:03.453160 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3072 08:06:03.456313 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3073 08:06:03.463456 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3074 08:06:03.466965 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3075 08:06:03.469721 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3076 08:06:03.469800
3077 08:06:03.473425 CA PerBit enable=1, Macro0, CA PI delay=34
3078 08:06:03.473505
3079 08:06:03.476657 [CBTSetCACLKResult] CA Dly = 34
3080 08:06:03.476737 CS Dly: 6 (0~37)
3081 08:06:03.476801 ==
3082 08:06:03.480027 Dram Type= 6, Freq= 0, CH_1, rank 1
3083 08:06:03.483541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 08:06:03.486960 ==
3085 08:06:03.490528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3086 08:06:03.497005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3087 08:06:03.505254 [CA 0] Center 38 (8~68) winsize 61
3088 08:06:03.508494 [CA 1] Center 38 (8~68) winsize 61
3089 08:06:03.511785 [CA 2] Center 34 (4~65) winsize 62
3090 08:06:03.515334 [CA 3] Center 34 (4~65) winsize 62
3091 08:06:03.519485 [CA 4] Center 34 (4~65) winsize 62
3092 08:06:03.522231 [CA 5] Center 33 (3~63) winsize 61
3093 08:06:03.522311
3094 08:06:03.525172 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3095 08:06:03.525252
3096 08:06:03.528528 [CATrainingPosCal] consider 2 rank data
3097 08:06:03.532059 u2DelayCellTimex100 = 270/100 ps
3098 08:06:03.535366 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3099 08:06:03.538630 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3100 08:06:03.541893 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3101 08:06:03.548752 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3102 08:06:03.552034 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3103 08:06:03.555313 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3104 08:06:03.555393
3105 08:06:03.558715 CA PerBit enable=1, Macro0, CA PI delay=33
3106 08:06:03.558817
3107 08:06:03.562457 [CBTSetCACLKResult] CA Dly = 33
3108 08:06:03.562537 CS Dly: 7 (0~40)
3109 08:06:03.562600
3110 08:06:03.565817 ----->DramcWriteLeveling(PI) begin...
3111 08:06:03.565899 ==
3112 08:06:03.568971 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 08:06:03.575873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 08:06:03.575953 ==
3115 08:06:03.579138 Write leveling (Byte 0): 27 => 27
3116 08:06:03.579218 Write leveling (Byte 1): 27 => 27
3117 08:06:03.582025 DramcWriteLeveling(PI) end<-----
3118 08:06:03.582113
3119 08:06:03.585397 ==
3120 08:06:03.585477 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 08:06:03.592235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 08:06:03.592316 ==
3123 08:06:03.595600 [Gating] SW mode calibration
3124 08:06:03.602631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3125 08:06:03.605983 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3126 08:06:03.612427 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3127 08:06:03.615929 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 08:06:03.619473 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 08:06:03.622669 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 08:06:03.629323 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 08:06:03.632242 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 08:06:03.635989 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 08:06:03.642668 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3134 08:06:03.646001 1 0 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3135 08:06:03.649350 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 08:06:03.656241 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 08:06:03.659333 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 08:06:03.662937 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 08:06:03.669940 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 08:06:03.672843 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 08:06:03.676702 1 0 28 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
3142 08:06:03.679784 1 1 0 | B1->B0 | 4242 3a3a | 0 0 | (0 0) (0 0)
3143 08:06:03.686418 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 08:06:03.689734 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 08:06:03.693334 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 08:06:03.700536 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 08:06:03.703182 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 08:06:03.706665 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 08:06:03.713134 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3150 08:06:03.716715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3151 08:06:03.720300 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 08:06:03.726648 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 08:06:03.730365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 08:06:03.733392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 08:06:03.736807 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 08:06:03.743566 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 08:06:03.746833 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 08:06:03.750573 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 08:06:03.756943 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 08:06:03.760456 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 08:06:03.763752 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 08:06:03.770419 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 08:06:03.773738 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 08:06:03.777096 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 08:06:03.783741 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3166 08:06:03.787301 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 08:06:03.790636 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 08:06:03.794209 Total UI for P1: 0, mck2ui 16
3169 08:06:03.797152 best dqsien dly found for B0: ( 1, 3, 30)
3170 08:06:03.800398 Total UI for P1: 0, mck2ui 16
3171 08:06:03.804263 best dqsien dly found for B1: ( 1, 4, 0)
3172 08:06:03.807328 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3173 08:06:03.810584 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3174 08:06:03.810652
3175 08:06:03.814055 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3176 08:06:03.817509 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3177 08:06:03.821059 [Gating] SW calibration Done
3178 08:06:03.821139 ==
3179 08:06:03.824263 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 08:06:03.827239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 08:06:03.830877 ==
3182 08:06:03.830957 RX Vref Scan: 0
3183 08:06:03.831020
3184 08:06:03.834176 RX Vref 0 -> 0, step: 1
3185 08:06:03.834255
3186 08:06:03.837424 RX Delay -40 -> 252, step: 8
3187 08:06:03.841062 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3188 08:06:03.844127 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3189 08:06:03.847642 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3190 08:06:03.850674 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3191 08:06:03.854422 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3192 08:06:03.861088 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3193 08:06:03.864145 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3194 08:06:03.867707 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3195 08:06:03.871219 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3196 08:06:03.874506 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3197 08:06:03.881049 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3198 08:06:03.884238 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3199 08:06:03.887822 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3200 08:06:03.891168 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3201 08:06:03.894669 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3202 08:06:03.901378 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3203 08:06:03.901475 ==
3204 08:06:03.904727 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 08:06:03.908719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 08:06:03.908797 ==
3207 08:06:03.908859 DQS Delay:
3208 08:06:03.911274 DQS0 = 0, DQS1 = 0
3209 08:06:03.911371 DQM Delay:
3210 08:06:03.914489 DQM0 = 116, DQM1 = 108
3211 08:06:03.914570 DQ Delay:
3212 08:06:03.917866 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3213 08:06:03.921358 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3214 08:06:03.924670 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3215 08:06:03.927826 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3216 08:06:03.927901
3217 08:06:03.927963
3218 08:06:03.928020 ==
3219 08:06:03.931357 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 08:06:03.938440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 08:06:03.938542 ==
3222 08:06:03.938636
3223 08:06:03.938746
3224 08:06:03.938820 TX Vref Scan disable
3225 08:06:03.942062 == TX Byte 0 ==
3226 08:06:03.944878 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3227 08:06:03.948157 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3228 08:06:03.951879 == TX Byte 1 ==
3229 08:06:03.955136 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3230 08:06:03.958324 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3231 08:06:03.961742 ==
3232 08:06:03.961839 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 08:06:03.968245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 08:06:03.968339 ==
3235 08:06:03.979116 TX Vref=22, minBit 9, minWin=24, winSum=410
3236 08:06:03.982500 TX Vref=24, minBit 1, minWin=25, winSum=419
3237 08:06:03.986036 TX Vref=26, minBit 0, minWin=26, winSum=421
3238 08:06:03.989332 TX Vref=28, minBit 2, minWin=26, winSum=431
3239 08:06:03.992984 TX Vref=30, minBit 9, minWin=25, winSum=430
3240 08:06:03.995987 TX Vref=32, minBit 1, minWin=26, winSum=433
3241 08:06:04.002566 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 32
3242 08:06:04.002645
3243 08:06:04.006528 Final TX Range 1 Vref 32
3244 08:06:04.006602
3245 08:06:04.006663 ==
3246 08:06:04.009426 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 08:06:04.013333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 08:06:04.013416 ==
3249 08:06:04.013480
3250 08:06:04.013539
3251 08:06:04.015937 TX Vref Scan disable
3252 08:06:04.019373 == TX Byte 0 ==
3253 08:06:04.023037 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3254 08:06:04.026180 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3255 08:06:04.029722 == TX Byte 1 ==
3256 08:06:04.033156 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3257 08:06:04.036803 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3258 08:06:04.036893
3259 08:06:04.039630 [DATLAT]
3260 08:06:04.039699 Freq=1200, CH1 RK0
3261 08:06:04.039759
3262 08:06:04.043048 DATLAT Default: 0xd
3263 08:06:04.043154 0, 0xFFFF, sum = 0
3264 08:06:04.046605 1, 0xFFFF, sum = 0
3265 08:06:04.046713 2, 0xFFFF, sum = 0
3266 08:06:04.049583 3, 0xFFFF, sum = 0
3267 08:06:04.049664 4, 0xFFFF, sum = 0
3268 08:06:04.053356 5, 0xFFFF, sum = 0
3269 08:06:04.053437 6, 0xFFFF, sum = 0
3270 08:06:04.056446 7, 0xFFFF, sum = 0
3271 08:06:04.056527 8, 0xFFFF, sum = 0
3272 08:06:04.059881 9, 0xFFFF, sum = 0
3273 08:06:04.059961 10, 0xFFFF, sum = 0
3274 08:06:04.063450 11, 0xFFFF, sum = 0
3275 08:06:04.063531 12, 0x0, sum = 1
3276 08:06:04.066981 13, 0x0, sum = 2
3277 08:06:04.067085 14, 0x0, sum = 3
3278 08:06:04.069678 15, 0x0, sum = 4
3279 08:06:04.069758 best_step = 13
3280 08:06:04.069820
3281 08:06:04.069878 ==
3282 08:06:04.073177 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 08:06:04.079757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 08:06:04.079857 ==
3285 08:06:04.079937 RX Vref Scan: 1
3286 08:06:04.079997
3287 08:06:04.083259 Set Vref Range= 32 -> 127
3288 08:06:04.083339
3289 08:06:04.086645 RX Vref 32 -> 127, step: 1
3290 08:06:04.086730
3291 08:06:04.086834 RX Delay -21 -> 252, step: 4
3292 08:06:04.086892
3293 08:06:04.089890 Set Vref, RX VrefLevel [Byte0]: 32
3294 08:06:04.092952 [Byte1]: 32
3295 08:06:04.097635
3296 08:06:04.097715 Set Vref, RX VrefLevel [Byte0]: 33
3297 08:06:04.100818 [Byte1]: 33
3298 08:06:04.105481
3299 08:06:04.105560 Set Vref, RX VrefLevel [Byte0]: 34
3300 08:06:04.109329 [Byte1]: 34
3301 08:06:04.113470
3302 08:06:04.113550 Set Vref, RX VrefLevel [Byte0]: 35
3303 08:06:04.116755 [Byte1]: 35
3304 08:06:04.121112
3305 08:06:04.121217 Set Vref, RX VrefLevel [Byte0]: 36
3306 08:06:04.124872 [Byte1]: 36
3307 08:06:04.129107
3308 08:06:04.129214 Set Vref, RX VrefLevel [Byte0]: 37
3309 08:06:04.132354 [Byte1]: 37
3310 08:06:04.137312
3311 08:06:04.137391 Set Vref, RX VrefLevel [Byte0]: 38
3312 08:06:04.140391 [Byte1]: 38
3313 08:06:04.144987
3314 08:06:04.145066 Set Vref, RX VrefLevel [Byte0]: 39
3315 08:06:04.148206 [Byte1]: 39
3316 08:06:04.153171
3317 08:06:04.153251 Set Vref, RX VrefLevel [Byte0]: 40
3318 08:06:04.156377 [Byte1]: 40
3319 08:06:04.161039
3320 08:06:04.161118 Set Vref, RX VrefLevel [Byte0]: 41
3321 08:06:04.164248 [Byte1]: 41
3322 08:06:04.168872
3323 08:06:04.168951 Set Vref, RX VrefLevel [Byte0]: 42
3324 08:06:04.172381 [Byte1]: 42
3325 08:06:04.176494
3326 08:06:04.176573 Set Vref, RX VrefLevel [Byte0]: 43
3327 08:06:04.180338 [Byte1]: 43
3328 08:06:04.184714
3329 08:06:04.184822 Set Vref, RX VrefLevel [Byte0]: 44
3330 08:06:04.187889 [Byte1]: 44
3331 08:06:04.193068
3332 08:06:04.193151 Set Vref, RX VrefLevel [Byte0]: 45
3333 08:06:04.195756 [Byte1]: 45
3334 08:06:04.201375
3335 08:06:04.201453 Set Vref, RX VrefLevel [Byte0]: 46
3336 08:06:04.203791 [Byte1]: 46
3337 08:06:04.208637
3338 08:06:04.208713 Set Vref, RX VrefLevel [Byte0]: 47
3339 08:06:04.212090 [Byte1]: 47
3340 08:06:04.217003
3341 08:06:04.217082 Set Vref, RX VrefLevel [Byte0]: 48
3342 08:06:04.219738 [Byte1]: 48
3343 08:06:04.224083
3344 08:06:04.224162 Set Vref, RX VrefLevel [Byte0]: 49
3345 08:06:04.227839 [Byte1]: 49
3346 08:06:04.232449
3347 08:06:04.232547 Set Vref, RX VrefLevel [Byte0]: 50
3348 08:06:04.235463 [Byte1]: 50
3349 08:06:04.239891
3350 08:06:04.240001 Set Vref, RX VrefLevel [Byte0]: 51
3351 08:06:04.243345 [Byte1]: 51
3352 08:06:04.247868
3353 08:06:04.247964 Set Vref, RX VrefLevel [Byte0]: 52
3354 08:06:04.251182 [Byte1]: 52
3355 08:06:04.255685
3356 08:06:04.255800 Set Vref, RX VrefLevel [Byte0]: 53
3357 08:06:04.259013 [Byte1]: 53
3358 08:06:04.264115
3359 08:06:04.264213 Set Vref, RX VrefLevel [Byte0]: 54
3360 08:06:04.267190 [Byte1]: 54
3361 08:06:04.272065
3362 08:06:04.272179 Set Vref, RX VrefLevel [Byte0]: 55
3363 08:06:04.275090 [Byte1]: 55
3364 08:06:04.279458
3365 08:06:04.279550 Set Vref, RX VrefLevel [Byte0]: 56
3366 08:06:04.283044 [Byte1]: 56
3367 08:06:04.287659
3368 08:06:04.287765 Set Vref, RX VrefLevel [Byte0]: 57
3369 08:06:04.290685 [Byte1]: 57
3370 08:06:04.295482
3371 08:06:04.295575 Set Vref, RX VrefLevel [Byte0]: 58
3372 08:06:04.299009 [Byte1]: 58
3373 08:06:04.303390
3374 08:06:04.303488 Set Vref, RX VrefLevel [Byte0]: 59
3375 08:06:04.306974 [Byte1]: 59
3376 08:06:04.311098
3377 08:06:04.311186 Set Vref, RX VrefLevel [Byte0]: 60
3378 08:06:04.315020 [Byte1]: 60
3379 08:06:04.319461
3380 08:06:04.319551 Set Vref, RX VrefLevel [Byte0]: 61
3381 08:06:04.322853 [Byte1]: 61
3382 08:06:04.326979
3383 08:06:04.327060 Set Vref, RX VrefLevel [Byte0]: 62
3384 08:06:04.330491 [Byte1]: 62
3385 08:06:04.334811
3386 08:06:04.334890 Set Vref, RX VrefLevel [Byte0]: 63
3387 08:06:04.338489 [Byte1]: 63
3388 08:06:04.342884
3389 08:06:04.342959 Set Vref, RX VrefLevel [Byte0]: 64
3390 08:06:04.346489 [Byte1]: 64
3391 08:06:04.350731
3392 08:06:04.350818 Set Vref, RX VrefLevel [Byte0]: 65
3393 08:06:04.354610 [Byte1]: 65
3394 08:06:04.358854
3395 08:06:04.358940 Set Vref, RX VrefLevel [Byte0]: 66
3396 08:06:04.362179 [Byte1]: 66
3397 08:06:04.366709
3398 08:06:04.366889 Set Vref, RX VrefLevel [Byte0]: 67
3399 08:06:04.369933 [Byte1]: 67
3400 08:06:04.375204
3401 08:06:04.375351 Set Vref, RX VrefLevel [Byte0]: 68
3402 08:06:04.378320 [Byte1]: 68
3403 08:06:04.382487
3404 08:06:04.382569 Set Vref, RX VrefLevel [Byte0]: 69
3405 08:06:04.386026 [Byte1]: 69
3406 08:06:04.390614
3407 08:06:04.390718 Final RX Vref Byte 0 = 61 to rank0
3408 08:06:04.394009 Final RX Vref Byte 1 = 53 to rank0
3409 08:06:04.397160 Final RX Vref Byte 0 = 61 to rank1
3410 08:06:04.400871 Final RX Vref Byte 1 = 53 to rank1==
3411 08:06:04.403832 Dram Type= 6, Freq= 0, CH_1, rank 0
3412 08:06:04.407228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 08:06:04.410744 ==
3414 08:06:04.410838 DQS Delay:
3415 08:06:04.410905 DQS0 = 0, DQS1 = 0
3416 08:06:04.413827 DQM Delay:
3417 08:06:04.413911 DQM0 = 116, DQM1 = 110
3418 08:06:04.417544 DQ Delay:
3419 08:06:04.420860 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =114
3420 08:06:04.424281 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3421 08:06:04.427506 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =104
3422 08:06:04.430899 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =114
3423 08:06:04.430983
3424 08:06:04.431047
3425 08:06:04.437680 [DQSOSCAuto] RK0, (LSB)MR18= 0xe4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3426 08:06:04.440763 CH1 RK0: MR19=403, MR18=E4
3427 08:06:04.447562 CH1_RK0: MR19=0x403, MR18=0xE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3428 08:06:04.447651
3429 08:06:04.451172 ----->DramcWriteLeveling(PI) begin...
3430 08:06:04.451257 ==
3431 08:06:04.454642 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 08:06:04.457717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 08:06:04.457801 ==
3434 08:06:04.461063 Write leveling (Byte 0): 27 => 27
3435 08:06:04.464864 Write leveling (Byte 1): 29 => 29
3436 08:06:04.468049 DramcWriteLeveling(PI) end<-----
3437 08:06:04.468131
3438 08:06:04.468196 ==
3439 08:06:04.471263 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 08:06:04.474512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 08:06:04.474594 ==
3442 08:06:04.477876 [Gating] SW mode calibration
3443 08:06:04.484555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3444 08:06:04.491513 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3445 08:06:04.494820 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 08:06:04.497973 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 08:06:04.504609 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 08:06:04.508272 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 08:06:04.511497 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 08:06:04.518368 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 08:06:04.521855 0 15 24 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
3452 08:06:04.525002 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 1) (1 0)
3453 08:06:04.531559 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 08:06:04.534676 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3455 08:06:04.538485 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 08:06:04.541377 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3457 08:06:04.548250 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 08:06:04.551828 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3459 08:06:04.555406 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3460 08:06:04.562162 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 08:06:04.565017 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 08:06:04.568823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 08:06:04.575192 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 08:06:04.578748 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 08:06:04.582097 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 08:06:04.588358 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 08:06:04.592048 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3468 08:06:04.595034 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3469 08:06:04.601925 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 08:06:04.605165 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 08:06:04.608547 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 08:06:04.612293 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 08:06:04.618956 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 08:06:04.622250 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 08:06:04.625642 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 08:06:04.632475 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 08:06:04.635398 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 08:06:04.638615 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 08:06:04.645960 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 08:06:04.648925 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 08:06:04.652478 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 08:06:04.658804 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3483 08:06:04.662011 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3484 08:06:04.665508 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3485 08:06:04.668730 Total UI for P1: 0, mck2ui 16
3486 08:06:04.672175 best dqsien dly found for B0: ( 1, 3, 22)
3487 08:06:04.675931 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 08:06:04.678840 Total UI for P1: 0, mck2ui 16
3489 08:06:04.682292 best dqsien dly found for B1: ( 1, 3, 28)
3490 08:06:04.686089 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3491 08:06:04.688833 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3492 08:06:04.692213
3493 08:06:04.695762 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3494 08:06:04.698990 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3495 08:06:04.702415 [Gating] SW calibration Done
3496 08:06:04.702487 ==
3497 08:06:04.705360 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 08:06:04.709347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 08:06:04.709461 ==
3500 08:06:04.709524 RX Vref Scan: 0
3501 08:06:04.712184
3502 08:06:04.712264 RX Vref 0 -> 0, step: 1
3503 08:06:04.712327
3504 08:06:04.715408 RX Delay -40 -> 252, step: 8
3505 08:06:04.718646 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3506 08:06:04.722204 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3507 08:06:04.729896 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3508 08:06:04.732029 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3509 08:06:04.735688 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3510 08:06:04.739298 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3511 08:06:04.742327 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3512 08:06:04.749490 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3513 08:06:04.752275 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3514 08:06:04.755588 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3515 08:06:04.759493 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3516 08:06:04.762363 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3517 08:06:04.765762 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3518 08:06:04.772428 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3519 08:06:04.775530 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3520 08:06:04.779459 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3521 08:06:04.779539 ==
3522 08:06:04.782375 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 08:06:04.785843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 08:06:04.788998 ==
3525 08:06:04.789078 DQS Delay:
3526 08:06:04.789141 DQS0 = 0, DQS1 = 0
3527 08:06:04.792314 DQM Delay:
3528 08:06:04.792394 DQM0 = 112, DQM1 = 110
3529 08:06:04.795674 DQ Delay:
3530 08:06:04.799201 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3531 08:06:04.802735 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3532 08:06:04.805874 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3533 08:06:04.809049 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3534 08:06:04.809128
3535 08:06:04.809192
3536 08:06:04.809250 ==
3537 08:06:04.812380 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 08:06:04.816205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 08:06:04.816288 ==
3540 08:06:04.816352
3541 08:06:04.816411
3542 08:06:04.819349 TX Vref Scan disable
3543 08:06:04.822496 == TX Byte 0 ==
3544 08:06:04.826475 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3545 08:06:04.829375 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3546 08:06:04.832464 == TX Byte 1 ==
3547 08:06:04.835826 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3548 08:06:04.839107 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3549 08:06:04.839179 ==
3550 08:06:04.842652 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 08:06:04.846359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 08:06:04.849218 ==
3553 08:06:04.859014 TX Vref=22, minBit 3, minWin=25, winSum=419
3554 08:06:04.862961 TX Vref=24, minBit 3, minWin=25, winSum=423
3555 08:06:04.866382 TX Vref=26, minBit 2, minWin=26, winSum=432
3556 08:06:04.869293 TX Vref=28, minBit 2, minWin=26, winSum=434
3557 08:06:04.872334 TX Vref=30, minBit 2, minWin=26, winSum=432
3558 08:06:04.876029 TX Vref=32, minBit 1, minWin=26, winSum=432
3559 08:06:04.882536 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 28
3560 08:06:04.882626
3561 08:06:04.886001 Final TX Range 1 Vref 28
3562 08:06:04.886074
3563 08:06:04.886133 ==
3564 08:06:04.889199 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 08:06:04.893045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 08:06:04.893118 ==
3567 08:06:04.893179
3568 08:06:04.893235
3569 08:06:04.896095 TX Vref Scan disable
3570 08:06:04.899487 == TX Byte 0 ==
3571 08:06:04.902515 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 08:06:04.905863 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 08:06:04.909002 == TX Byte 1 ==
3574 08:06:04.912399 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3575 08:06:04.916175 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3576 08:06:04.916246
3577 08:06:04.919712 [DATLAT]
3578 08:06:04.919780 Freq=1200, CH1 RK1
3579 08:06:04.919839
3580 08:06:04.922384 DATLAT Default: 0xd
3581 08:06:04.922460 0, 0xFFFF, sum = 0
3582 08:06:04.925761 1, 0xFFFF, sum = 0
3583 08:06:04.925839 2, 0xFFFF, sum = 0
3584 08:06:04.929304 3, 0xFFFF, sum = 0
3585 08:06:04.929384 4, 0xFFFF, sum = 0
3586 08:06:04.932422 5, 0xFFFF, sum = 0
3587 08:06:04.932498 6, 0xFFFF, sum = 0
3588 08:06:04.935777 7, 0xFFFF, sum = 0
3589 08:06:04.935852 8, 0xFFFF, sum = 0
3590 08:06:04.939304 9, 0xFFFF, sum = 0
3591 08:06:04.939382 10, 0xFFFF, sum = 0
3592 08:06:04.942947 11, 0xFFFF, sum = 0
3593 08:06:04.943045 12, 0x0, sum = 1
3594 08:06:04.946098 13, 0x0, sum = 2
3595 08:06:04.946180 14, 0x0, sum = 3
3596 08:06:04.949762 15, 0x0, sum = 4
3597 08:06:04.949843 best_step = 13
3598 08:06:04.949907
3599 08:06:04.949965 ==
3600 08:06:04.952869 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 08:06:04.959387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 08:06:04.959468 ==
3603 08:06:04.959532 RX Vref Scan: 0
3604 08:06:04.959591
3605 08:06:04.962627 RX Vref 0 -> 0, step: 1
3606 08:06:04.962706
3607 08:06:04.965840 RX Delay -21 -> 252, step: 4
3608 08:06:04.969609 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3609 08:06:04.972524 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3610 08:06:04.979357 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3611 08:06:04.982699 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3612 08:06:04.986177 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3613 08:06:04.989383 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3614 08:06:04.993003 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3615 08:06:04.996317 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3616 08:06:05.002680 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3617 08:06:05.006704 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3618 08:06:05.009597 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3619 08:06:05.012869 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3620 08:06:05.016341 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3621 08:06:05.023457 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3622 08:06:05.026315 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3623 08:06:05.029837 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3624 08:06:05.029949 ==
3625 08:06:05.032872 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 08:06:05.036403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 08:06:05.039406 ==
3628 08:06:05.039486 DQS Delay:
3629 08:06:05.039550 DQS0 = 0, DQS1 = 0
3630 08:06:05.043054 DQM Delay:
3631 08:06:05.043133 DQM0 = 113, DQM1 = 109
3632 08:06:05.046513 DQ Delay:
3633 08:06:05.049488 DQ0 =114, DQ1 =108, DQ2 =106, DQ3 =112
3634 08:06:05.053323 DQ4 =112, DQ5 =124, DQ6 =120, DQ7 =110
3635 08:06:05.056380 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3636 08:06:05.059612 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3637 08:06:05.059692
3638 08:06:05.059754
3639 08:06:05.066422 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3640 08:06:05.069469 CH1 RK1: MR19=303, MR18=F7FE
3641 08:06:05.076315 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3642 08:06:05.079612 [RxdqsGatingPostProcess] freq 1200
3643 08:06:05.086456 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3644 08:06:05.086532 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 08:06:05.089761 best DQS1 dly(2T, 0.5T) = (0, 12)
3646 08:06:05.092964 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 08:06:05.096192 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3648 08:06:05.099593 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 08:06:05.103620 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 08:06:05.106573 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 08:06:05.109752 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 08:06:05.113224 Pre-setting of DQS Precalculation
3653 08:06:05.116306 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3654 08:06:05.126704 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3655 08:06:05.133074 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3656 08:06:05.133151
3657 08:06:05.133213
3658 08:06:05.136856 [Calibration Summary] 2400 Mbps
3659 08:06:05.136931 CH 0, Rank 0
3660 08:06:05.139719 SW Impedance : PASS
3661 08:06:05.139793 DUTY Scan : NO K
3662 08:06:05.143204 ZQ Calibration : PASS
3663 08:06:05.146737 Jitter Meter : NO K
3664 08:06:05.146842 CBT Training : PASS
3665 08:06:05.149803 Write leveling : PASS
3666 08:06:05.153766 RX DQS gating : PASS
3667 08:06:05.153838 RX DQ/DQS(RDDQC) : PASS
3668 08:06:05.156329 TX DQ/DQS : PASS
3669 08:06:05.159879 RX DATLAT : PASS
3670 08:06:05.159948 RX DQ/DQS(Engine): PASS
3671 08:06:05.163058 TX OE : NO K
3672 08:06:05.163130 All Pass.
3673 08:06:05.163190
3674 08:06:05.166821 CH 0, Rank 1
3675 08:06:05.166889 SW Impedance : PASS
3676 08:06:05.170094 DUTY Scan : NO K
3677 08:06:05.170160 ZQ Calibration : PASS
3678 08:06:05.173195 Jitter Meter : NO K
3679 08:06:05.176745 CBT Training : PASS
3680 08:06:05.176813 Write leveling : PASS
3681 08:06:05.180210 RX DQS gating : PASS
3682 08:06:05.183201 RX DQ/DQS(RDDQC) : PASS
3683 08:06:05.183300 TX DQ/DQS : PASS
3684 08:06:05.186709 RX DATLAT : PASS
3685 08:06:05.190205 RX DQ/DQS(Engine): PASS
3686 08:06:05.190276 TX OE : NO K
3687 08:06:05.193106 All Pass.
3688 08:06:05.193176
3689 08:06:05.193235 CH 1, Rank 0
3690 08:06:05.196721 SW Impedance : PASS
3691 08:06:05.196795 DUTY Scan : NO K
3692 08:06:05.199851 ZQ Calibration : PASS
3693 08:06:05.203529 Jitter Meter : NO K
3694 08:06:05.203602 CBT Training : PASS
3695 08:06:05.206984 Write leveling : PASS
3696 08:06:05.207063 RX DQS gating : PASS
3697 08:06:05.209960 RX DQ/DQS(RDDQC) : PASS
3698 08:06:05.213181 TX DQ/DQS : PASS
3699 08:06:05.213248 RX DATLAT : PASS
3700 08:06:05.216693 RX DQ/DQS(Engine): PASS
3701 08:06:05.220040 TX OE : NO K
3702 08:06:05.220111 All Pass.
3703 08:06:05.220169
3704 08:06:05.220224 CH 1, Rank 1
3705 08:06:05.223203 SW Impedance : PASS
3706 08:06:05.226509 DUTY Scan : NO K
3707 08:06:05.226584 ZQ Calibration : PASS
3708 08:06:05.230376 Jitter Meter : NO K
3709 08:06:05.233442 CBT Training : PASS
3710 08:06:05.233509 Write leveling : PASS
3711 08:06:05.236801 RX DQS gating : PASS
3712 08:06:05.239927 RX DQ/DQS(RDDQC) : PASS
3713 08:06:05.239993 TX DQ/DQS : PASS
3714 08:06:05.243415 RX DATLAT : PASS
3715 08:06:05.243519 RX DQ/DQS(Engine): PASS
3716 08:06:05.246814 TX OE : NO K
3717 08:06:05.246904 All Pass.
3718 08:06:05.246967
3719 08:06:05.249854 DramC Write-DBI off
3720 08:06:05.253631 PER_BANK_REFRESH: Hybrid Mode
3721 08:06:05.253712 TX_TRACKING: ON
3722 08:06:05.263423 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3723 08:06:05.266851 [FAST_K] Save calibration result to emmc
3724 08:06:05.270227 dramc_set_vcore_voltage set vcore to 650000
3725 08:06:05.273431 Read voltage for 600, 5
3726 08:06:05.273511 Vio18 = 0
3727 08:06:05.273575 Vcore = 650000
3728 08:06:05.277094 Vdram = 0
3729 08:06:05.277188 Vddq = 0
3730 08:06:05.277251 Vmddr = 0
3731 08:06:05.283301 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3732 08:06:05.287201 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3733 08:06:05.290149 MEM_TYPE=3, freq_sel=19
3734 08:06:05.293320 sv_algorithm_assistance_LP4_1600
3735 08:06:05.296827 ============ PULL DRAM RESETB DOWN ============
3736 08:06:05.303450 ========== PULL DRAM RESETB DOWN end =========
3737 08:06:05.306817 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 08:06:05.309934 ===================================
3739 08:06:05.313883 LPDDR4 DRAM CONFIGURATION
3740 08:06:05.316848 ===================================
3741 08:06:05.316926 EX_ROW_EN[0] = 0x0
3742 08:06:05.320023 EX_ROW_EN[1] = 0x0
3743 08:06:05.320093 LP4Y_EN = 0x0
3744 08:06:05.323258 WORK_FSP = 0x0
3745 08:06:05.323325 WL = 0x2
3746 08:06:05.327066 RL = 0x2
3747 08:06:05.327141 BL = 0x2
3748 08:06:05.330377 RPST = 0x0
3749 08:06:05.330445 RD_PRE = 0x0
3750 08:06:05.333520 WR_PRE = 0x1
3751 08:06:05.333589 WR_PST = 0x0
3752 08:06:05.336656 DBI_WR = 0x0
3753 08:06:05.336739 DBI_RD = 0x0
3754 08:06:05.340312 OTF = 0x1
3755 08:06:05.343947 ===================================
3756 08:06:05.346633 ===================================
3757 08:06:05.346709 ANA top config
3758 08:06:05.350022 ===================================
3759 08:06:05.353548 DLL_ASYNC_EN = 0
3760 08:06:05.357080 ALL_SLAVE_EN = 1
3761 08:06:05.360163 NEW_RANK_MODE = 1
3762 08:06:05.360244 DLL_IDLE_MODE = 1
3763 08:06:05.363164 LP45_APHY_COMB_EN = 1
3764 08:06:05.366702 TX_ODT_DIS = 1
3765 08:06:05.370098 NEW_8X_MODE = 1
3766 08:06:05.373637 ===================================
3767 08:06:05.376572 ===================================
3768 08:06:05.380115 data_rate = 1200
3769 08:06:05.380185 CKR = 1
3770 08:06:05.383819 DQ_P2S_RATIO = 8
3771 08:06:05.386717 ===================================
3772 08:06:05.390075 CA_P2S_RATIO = 8
3773 08:06:05.393263 DQ_CA_OPEN = 0
3774 08:06:05.396684 DQ_SEMI_OPEN = 0
3775 08:06:05.400290 CA_SEMI_OPEN = 0
3776 08:06:05.400355 CA_FULL_RATE = 0
3777 08:06:05.403614 DQ_CKDIV4_EN = 1
3778 08:06:05.407027 CA_CKDIV4_EN = 1
3779 08:06:05.410311 CA_PREDIV_EN = 0
3780 08:06:05.413275 PH8_DLY = 0
3781 08:06:05.413348 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3782 08:06:05.416627 DQ_AAMCK_DIV = 4
3783 08:06:05.420117 CA_AAMCK_DIV = 4
3784 08:06:05.423569 CA_ADMCK_DIV = 4
3785 08:06:05.427047 DQ_TRACK_CA_EN = 0
3786 08:06:05.429940 CA_PICK = 600
3787 08:06:05.433960 CA_MCKIO = 600
3788 08:06:05.434031 MCKIO_SEMI = 0
3789 08:06:05.437026 PLL_FREQ = 2288
3790 08:06:05.440206 DQ_UI_PI_RATIO = 32
3791 08:06:05.443500 CA_UI_PI_RATIO = 0
3792 08:06:05.447542 ===================================
3793 08:06:05.450365 ===================================
3794 08:06:05.453789 memory_type:LPDDR4
3795 08:06:05.453857 GP_NUM : 10
3796 08:06:05.456949 SRAM_EN : 1
3797 08:06:05.457013 MD32_EN : 0
3798 08:06:05.460320 ===================================
3799 08:06:05.463903 [ANA_INIT] >>>>>>>>>>>>>>
3800 08:06:05.467061 <<<<<< [CONFIGURE PHASE]: ANA_TX
3801 08:06:05.470310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3802 08:06:05.473818 ===================================
3803 08:06:05.476776 data_rate = 1200,PCW = 0X5800
3804 08:06:05.480299 ===================================
3805 08:06:05.483974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3806 08:06:05.490408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 08:06:05.493343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 08:06:05.500790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3809 08:06:05.503514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3810 08:06:05.507087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3811 08:06:05.507154 [ANA_INIT] flow start
3812 08:06:05.510244 [ANA_INIT] PLL >>>>>>>>
3813 08:06:05.513792 [ANA_INIT] PLL <<<<<<<<
3814 08:06:05.513861 [ANA_INIT] MIDPI >>>>>>>>
3815 08:06:05.517038 [ANA_INIT] MIDPI <<<<<<<<
3816 08:06:05.520590 [ANA_INIT] DLL >>>>>>>>
3817 08:06:05.520658 [ANA_INIT] flow end
3818 08:06:05.523358 ============ LP4 DIFF to SE enter ============
3819 08:06:05.530568 ============ LP4 DIFF to SE exit ============
3820 08:06:05.530670 [ANA_INIT] <<<<<<<<<<<<<
3821 08:06:05.533818 [Flow] Enable top DCM control >>>>>
3822 08:06:05.536964 [Flow] Enable top DCM control <<<<<
3823 08:06:05.540378 Enable DLL master slave shuffle
3824 08:06:05.547204 ==============================================================
3825 08:06:05.547279 Gating Mode config
3826 08:06:05.553731 ==============================================================
3827 08:06:05.557197 Config description:
3828 08:06:05.567074 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3829 08:06:05.573577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3830 08:06:05.577075 SELPH_MODE 0: By rank 1: By Phase
3831 08:06:05.583968 ==============================================================
3832 08:06:05.587204 GAT_TRACK_EN = 1
3833 08:06:05.587275 RX_GATING_MODE = 2
3834 08:06:05.590610 RX_GATING_TRACK_MODE = 2
3835 08:06:05.593630 SELPH_MODE = 1
3836 08:06:05.596996 PICG_EARLY_EN = 1
3837 08:06:05.600423 VALID_LAT_VALUE = 1
3838 08:06:05.607182 ==============================================================
3839 08:06:05.610815 Enter into Gating configuration >>>>
3840 08:06:05.613958 Exit from Gating configuration <<<<
3841 08:06:05.617577 Enter into DVFS_PRE_config >>>>>
3842 08:06:05.627468 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3843 08:06:05.630676 Exit from DVFS_PRE_config <<<<<
3844 08:06:05.634115 Enter into PICG configuration >>>>
3845 08:06:05.637521 Exit from PICG configuration <<<<
3846 08:06:05.640648 [RX_INPUT] configuration >>>>>
3847 08:06:05.640716 [RX_INPUT] configuration <<<<<
3848 08:06:05.647632 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3849 08:06:05.653864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3850 08:06:05.657129 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 08:06:05.664281 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 08:06:05.671107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 08:06:05.677468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 08:06:05.680904 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3855 08:06:05.684354 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3856 08:06:05.690719 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3857 08:06:05.694055 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3858 08:06:05.697497 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3859 08:06:05.700902 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 08:06:05.704308 ===================================
3861 08:06:05.707449 LPDDR4 DRAM CONFIGURATION
3862 08:06:05.710938 ===================================
3863 08:06:05.714104 EX_ROW_EN[0] = 0x0
3864 08:06:05.714170 EX_ROW_EN[1] = 0x0
3865 08:06:05.717875 LP4Y_EN = 0x0
3866 08:06:05.717945 WORK_FSP = 0x0
3867 08:06:05.720741 WL = 0x2
3868 08:06:05.720815 RL = 0x2
3869 08:06:05.724057 BL = 0x2
3870 08:06:05.724130 RPST = 0x0
3871 08:06:05.727492 RD_PRE = 0x0
3872 08:06:05.727580 WR_PRE = 0x1
3873 08:06:05.731140 WR_PST = 0x0
3874 08:06:05.731210 DBI_WR = 0x0
3875 08:06:05.734026 DBI_RD = 0x0
3876 08:06:05.734095 OTF = 0x1
3877 08:06:05.737535 ===================================
3878 08:06:05.744499 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3879 08:06:05.747803 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3880 08:06:05.751051 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 08:06:05.754095 ===================================
3882 08:06:05.758021 LPDDR4 DRAM CONFIGURATION
3883 08:06:05.760887 ===================================
3884 08:06:05.760996 EX_ROW_EN[0] = 0x10
3885 08:06:05.764210 EX_ROW_EN[1] = 0x0
3886 08:06:05.767529 LP4Y_EN = 0x0
3887 08:06:05.767639 WORK_FSP = 0x0
3888 08:06:05.771106 WL = 0x2
3889 08:06:05.771186 RL = 0x2
3890 08:06:05.774305 BL = 0x2
3891 08:06:05.774384 RPST = 0x0
3892 08:06:05.777919 RD_PRE = 0x0
3893 08:06:05.777993 WR_PRE = 0x1
3894 08:06:05.781435 WR_PST = 0x0
3895 08:06:05.781505 DBI_WR = 0x0
3896 08:06:05.784283 DBI_RD = 0x0
3897 08:06:05.784355 OTF = 0x1
3898 08:06:05.787685 ===================================
3899 08:06:05.794383 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3900 08:06:05.798623 nWR fixed to 30
3901 08:06:05.802010 [ModeRegInit_LP4] CH0 RK0
3902 08:06:05.802093 [ModeRegInit_LP4] CH0 RK1
3903 08:06:05.805142 [ModeRegInit_LP4] CH1 RK0
3904 08:06:05.808494 [ModeRegInit_LP4] CH1 RK1
3905 08:06:05.808562 match AC timing 17
3906 08:06:05.815142 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3907 08:06:05.818781 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3908 08:06:05.821740 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3909 08:06:05.828565 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3910 08:06:05.831800 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3911 08:06:05.831869 ==
3912 08:06:05.835395 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 08:06:05.838407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3914 08:06:05.838482 ==
3915 08:06:05.845352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3916 08:06:05.851904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3917 08:06:05.855479 [CA 0] Center 36 (6~67) winsize 62
3918 08:06:05.858645 [CA 1] Center 36 (6~66) winsize 61
3919 08:06:05.861826 [CA 2] Center 34 (4~65) winsize 62
3920 08:06:05.865436 [CA 3] Center 34 (4~64) winsize 61
3921 08:06:05.868987 [CA 4] Center 33 (3~64) winsize 62
3922 08:06:05.872098 [CA 5] Center 33 (3~64) winsize 62
3923 08:06:05.872168
3924 08:06:05.875631 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3925 08:06:05.875705
3926 08:06:05.878806 [CATrainingPosCal] consider 1 rank data
3927 08:06:05.882231 u2DelayCellTimex100 = 270/100 ps
3928 08:06:05.885600 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3929 08:06:05.889260 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3930 08:06:05.892829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 08:06:05.896014 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3932 08:06:05.899217 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 08:06:05.902344 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 08:06:05.902411
3935 08:06:05.905843 CA PerBit enable=1, Macro0, CA PI delay=33
3936 08:06:05.905907
3937 08:06:05.909486 [CBTSetCACLKResult] CA Dly = 33
3938 08:06:05.912324 CS Dly: 5 (0~36)
3939 08:06:05.912392 ==
3940 08:06:05.915576 Dram Type= 6, Freq= 0, CH_0, rank 1
3941 08:06:05.919814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 08:06:05.919880 ==
3943 08:06:05.925701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 08:06:05.932530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 08:06:05.935484 [CA 0] Center 36 (6~66) winsize 61
3946 08:06:05.938982 [CA 1] Center 36 (6~66) winsize 61
3947 08:06:05.942316 [CA 2] Center 34 (4~65) winsize 62
3948 08:06:05.945641 [CA 3] Center 34 (4~65) winsize 62
3949 08:06:05.949412 [CA 4] Center 33 (3~64) winsize 62
3950 08:06:05.952959 [CA 5] Center 33 (3~64) winsize 62
3951 08:06:05.953030
3952 08:06:05.955640 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 08:06:05.955715
3954 08:06:05.959348 [CATrainingPosCal] consider 2 rank data
3955 08:06:05.962350 u2DelayCellTimex100 = 270/100 ps
3956 08:06:05.965635 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 08:06:05.969439 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3958 08:06:05.972240 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 08:06:05.975604 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3960 08:06:05.979105 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 08:06:05.982673 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 08:06:05.982764
3963 08:06:05.985763 CA PerBit enable=1, Macro0, CA PI delay=33
3964 08:06:05.985845
3965 08:06:05.989109 [CBTSetCACLKResult] CA Dly = 33
3966 08:06:05.992480 CS Dly: 5 (0~36)
3967 08:06:05.992562
3968 08:06:05.995761 ----->DramcWriteLeveling(PI) begin...
3969 08:06:05.995867 ==
3970 08:06:05.999378 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 08:06:06.002361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 08:06:06.002444 ==
3973 08:06:06.006095 Write leveling (Byte 0): 31 => 31
3974 08:06:06.009441 Write leveling (Byte 1): 28 => 28
3975 08:06:06.012392 DramcWriteLeveling(PI) end<-----
3976 08:06:06.012461
3977 08:06:06.012526 ==
3978 08:06:06.016016 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 08:06:06.019421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 08:06:06.019490 ==
3981 08:06:06.022526 [Gating] SW mode calibration
3982 08:06:06.029428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3983 08:06:06.035821 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3984 08:06:06.039015 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 08:06:06.042526 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 08:06:06.049225 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 08:06:06.052813 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3988 08:06:06.055928 0 9 16 | B1->B0 | 3131 2d2d | 0 1 | (0 0) (1 0)
3989 08:06:06.062743 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3990 08:06:06.066018 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 08:06:06.069374 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 08:06:06.075737 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 08:06:06.079087 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 08:06:06.082552 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 08:06:06.089335 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3996 08:06:06.092500 0 10 16 | B1->B0 | 3030 4040 | 0 0 | (0 0) (0 0)
3997 08:06:06.096171 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 08:06:06.102509 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 08:06:06.105745 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 08:06:06.109138 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 08:06:06.115838 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 08:06:06.119141 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 08:06:06.122658 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 08:06:06.126152 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4005 08:06:06.132742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4006 08:06:06.135914 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 08:06:06.139446 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 08:06:06.146057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 08:06:06.149730 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 08:06:06.152847 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 08:06:06.159320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 08:06:06.162551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 08:06:06.166417 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 08:06:06.172910 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 08:06:06.176192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 08:06:06.180159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 08:06:06.186307 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 08:06:06.189254 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 08:06:06.192966 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 08:06:06.200098 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4021 08:06:06.203123 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 08:06:06.206082 Total UI for P1: 0, mck2ui 16
4023 08:06:06.209657 best dqsien dly found for B0: ( 0, 13, 16)
4024 08:06:06.212807 Total UI for P1: 0, mck2ui 16
4025 08:06:06.216203 best dqsien dly found for B1: ( 0, 13, 16)
4026 08:06:06.219532 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4027 08:06:06.222963 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4028 08:06:06.223034
4029 08:06:06.226192 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4030 08:06:06.229919 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4031 08:06:06.232767 [Gating] SW calibration Done
4032 08:06:06.232840 ==
4033 08:06:06.236448 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 08:06:06.239797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 08:06:06.239871 ==
4036 08:06:06.242814 RX Vref Scan: 0
4037 08:06:06.242889
4038 08:06:06.246182 RX Vref 0 -> 0, step: 1
4039 08:06:06.246254
4040 08:06:06.246318 RX Delay -230 -> 252, step: 16
4041 08:06:06.252779 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4042 08:06:06.256445 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4043 08:06:06.259844 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4044 08:06:06.262910 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4045 08:06:06.270040 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4046 08:06:06.272560 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4047 08:06:06.276312 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4048 08:06:06.279222 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4049 08:06:06.282985 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4050 08:06:06.289202 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4051 08:06:06.292667 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4052 08:06:06.295899 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4053 08:06:06.299439 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4054 08:06:06.306383 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4055 08:06:06.309445 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4056 08:06:06.313177 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4057 08:06:06.313246 ==
4058 08:06:06.316528 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 08:06:06.320155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 08:06:06.320230 ==
4061 08:06:06.323254 DQS Delay:
4062 08:06:06.323326 DQS0 = 0, DQS1 = 0
4063 08:06:06.326131 DQM Delay:
4064 08:06:06.326197 DQM0 = 41, DQM1 = 33
4065 08:06:06.326255 DQ Delay:
4066 08:06:06.329942 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4067 08:06:06.333028 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4068 08:06:06.336130 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4069 08:06:06.339407 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4070 08:06:06.339480
4071 08:06:06.339541
4072 08:06:06.339598 ==
4073 08:06:06.342954 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 08:06:06.350047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 08:06:06.350155 ==
4076 08:06:06.350219
4077 08:06:06.350278
4078 08:06:06.350333 TX Vref Scan disable
4079 08:06:06.354234 == TX Byte 0 ==
4080 08:06:06.356842 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4081 08:06:06.360856 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4082 08:06:06.363394 == TX Byte 1 ==
4083 08:06:06.366974 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4084 08:06:06.373813 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4085 08:06:06.373886 ==
4086 08:06:06.376928 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 08:06:06.380224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 08:06:06.380297 ==
4089 08:06:06.380357
4090 08:06:06.380413
4091 08:06:06.383453 TX Vref Scan disable
4092 08:06:06.386904 == TX Byte 0 ==
4093 08:06:06.389932 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4094 08:06:06.393771 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4095 08:06:06.396543 == TX Byte 1 ==
4096 08:06:06.400360 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4097 08:06:06.403360 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4098 08:06:06.403429
4099 08:06:06.403489 [DATLAT]
4100 08:06:06.406879 Freq=600, CH0 RK0
4101 08:06:06.406949
4102 08:06:06.407011 DATLAT Default: 0x9
4103 08:06:06.410155 0, 0xFFFF, sum = 0
4104 08:06:06.410223 1, 0xFFFF, sum = 0
4105 08:06:06.413985 2, 0xFFFF, sum = 0
4106 08:06:06.416945 3, 0xFFFF, sum = 0
4107 08:06:06.417017 4, 0xFFFF, sum = 0
4108 08:06:06.420354 5, 0xFFFF, sum = 0
4109 08:06:06.420424 6, 0xFFFF, sum = 0
4110 08:06:06.423545 7, 0xFFFF, sum = 0
4111 08:06:06.423617 8, 0x0, sum = 1
4112 08:06:06.423713 9, 0x0, sum = 2
4113 08:06:06.426923 10, 0x0, sum = 3
4114 08:06:06.427000 11, 0x0, sum = 4
4115 08:06:06.430676 best_step = 9
4116 08:06:06.430786
4117 08:06:06.430847 ==
4118 08:06:06.433646 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 08:06:06.436721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 08:06:06.436791 ==
4121 08:06:06.440056 RX Vref Scan: 1
4122 08:06:06.440121
4123 08:06:06.440179 RX Vref 0 -> 0, step: 1
4124 08:06:06.440237
4125 08:06:06.444299 RX Delay -195 -> 252, step: 8
4126 08:06:06.444363
4127 08:06:06.446939 Set Vref, RX VrefLevel [Byte0]: 56
4128 08:06:06.449937 [Byte1]: 50
4129 08:06:06.454251
4130 08:06:06.454322 Final RX Vref Byte 0 = 56 to rank0
4131 08:06:06.457546 Final RX Vref Byte 1 = 50 to rank0
4132 08:06:06.460829 Final RX Vref Byte 0 = 56 to rank1
4133 08:06:06.464401 Final RX Vref Byte 1 = 50 to rank1==
4134 08:06:06.467531 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 08:06:06.474141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 08:06:06.474216 ==
4137 08:06:06.474282 DQS Delay:
4138 08:06:06.474340 DQS0 = 0, DQS1 = 0
4139 08:06:06.477430 DQM Delay:
4140 08:06:06.477504 DQM0 = 42, DQM1 = 33
4141 08:06:06.481013 DQ Delay:
4142 08:06:06.484329 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4143 08:06:06.484405 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4144 08:06:06.487885 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4145 08:06:06.491353 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4146 08:06:06.494411
4147 08:06:06.494481
4148 08:06:06.500793 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4149 08:06:06.504345 CH0 RK0: MR19=808, MR18=3E1D
4150 08:06:06.510980 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4151 08:06:06.511054
4152 08:06:06.514301 ----->DramcWriteLeveling(PI) begin...
4153 08:06:06.514373 ==
4154 08:06:06.517675 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 08:06:06.520708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 08:06:06.520778 ==
4157 08:06:06.524030 Write leveling (Byte 0): 32 => 32
4158 08:06:06.528163 Write leveling (Byte 1): 32 => 32
4159 08:06:06.531041 DramcWriteLeveling(PI) end<-----
4160 08:06:06.531108
4161 08:06:06.531166 ==
4162 08:06:06.535130 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 08:06:06.537309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 08:06:06.537379 ==
4165 08:06:06.541011 [Gating] SW mode calibration
4166 08:06:06.547539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4167 08:06:06.553959 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4168 08:06:06.557363 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 08:06:06.560757 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 08:06:06.567607 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 08:06:06.570610 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4172 08:06:06.574035 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4173 08:06:06.580857 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 08:06:06.584113 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 08:06:06.587576 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 08:06:06.594090 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 08:06:06.597337 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 08:06:06.600976 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 08:06:06.607486 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4180 08:06:06.610812 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4181 08:06:06.613942 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 08:06:06.617397 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 08:06:06.624255 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 08:06:06.627532 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 08:06:06.630807 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 08:06:06.637582 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 08:06:06.641599 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4188 08:06:06.644523 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4189 08:06:06.651137 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 08:06:06.654504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 08:06:06.657493 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 08:06:06.664494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 08:06:06.667812 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 08:06:06.671264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 08:06:06.677916 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 08:06:06.681223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 08:06:06.684675 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 08:06:06.690957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 08:06:06.694152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 08:06:06.697846 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 08:06:06.701175 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 08:06:06.708324 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 08:06:06.711005 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4204 08:06:06.714250 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4205 08:06:06.717585 Total UI for P1: 0, mck2ui 16
4206 08:06:06.721151 best dqsien dly found for B0: ( 0, 13, 12)
4207 08:06:06.727757 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 08:06:06.727826 Total UI for P1: 0, mck2ui 16
4209 08:06:06.734534 best dqsien dly found for B1: ( 0, 13, 16)
4210 08:06:06.738019 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 08:06:06.741257 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4212 08:06:06.741324
4213 08:06:06.744198 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 08:06:06.747904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4215 08:06:06.751314 [Gating] SW calibration Done
4216 08:06:06.751387 ==
4217 08:06:06.754487 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 08:06:06.757669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 08:06:06.757737 ==
4220 08:06:06.761004 RX Vref Scan: 0
4221 08:06:06.761068
4222 08:06:06.761127 RX Vref 0 -> 0, step: 1
4223 08:06:06.761183
4224 08:06:06.764508 RX Delay -230 -> 252, step: 16
4225 08:06:06.771288 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4226 08:06:06.774418 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4227 08:06:06.778108 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4228 08:06:06.781019 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4229 08:06:06.784456 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4230 08:06:06.791614 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4231 08:06:06.794271 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4232 08:06:06.797728 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4233 08:06:06.800965 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4234 08:06:06.808201 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4235 08:06:06.811035 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4236 08:06:06.814607 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4237 08:06:06.817869 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4238 08:06:06.820990 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4239 08:06:06.827444 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4240 08:06:06.831447 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4241 08:06:06.831522 ==
4242 08:06:06.834391 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 08:06:06.837611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 08:06:06.837684 ==
4245 08:06:06.841442 DQS Delay:
4246 08:06:06.841508 DQS0 = 0, DQS1 = 0
4247 08:06:06.841566 DQM Delay:
4248 08:06:06.844496 DQM0 = 39, DQM1 = 31
4249 08:06:06.844576 DQ Delay:
4250 08:06:06.848043 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4251 08:06:06.851145 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4252 08:06:06.854460 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4253 08:06:06.857708 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4254 08:06:06.857788
4255 08:06:06.857851
4256 08:06:06.857910 ==
4257 08:06:06.861020 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 08:06:06.868013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 08:06:06.868093 ==
4260 08:06:06.868156
4261 08:06:06.868214
4262 08:06:06.868287 TX Vref Scan disable
4263 08:06:06.871784 == TX Byte 0 ==
4264 08:06:06.874848 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4265 08:06:06.881675 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4266 08:06:06.881756 == TX Byte 1 ==
4267 08:06:06.885134 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4268 08:06:06.888261 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4269 08:06:06.891590 ==
4270 08:06:06.895486 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 08:06:06.898140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 08:06:06.898220 ==
4273 08:06:06.898283
4274 08:06:06.898341
4275 08:06:06.901603 TX Vref Scan disable
4276 08:06:06.901682 == TX Byte 0 ==
4277 08:06:06.908167 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4278 08:06:06.911557 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4279 08:06:06.911637 == TX Byte 1 ==
4280 08:06:06.918239 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4281 08:06:06.921678 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4282 08:06:06.921832
4283 08:06:06.921895 [DATLAT]
4284 08:06:06.925272 Freq=600, CH0 RK1
4285 08:06:06.925368
4286 08:06:06.925430 DATLAT Default: 0x9
4287 08:06:06.928327 0, 0xFFFF, sum = 0
4288 08:06:06.928460 1, 0xFFFF, sum = 0
4289 08:06:06.931954 2, 0xFFFF, sum = 0
4290 08:06:06.932035 3, 0xFFFF, sum = 0
4291 08:06:06.934974 4, 0xFFFF, sum = 0
4292 08:06:06.935056 5, 0xFFFF, sum = 0
4293 08:06:06.938609 6, 0xFFFF, sum = 0
4294 08:06:06.938689 7, 0xFFFF, sum = 0
4295 08:06:06.941936 8, 0x0, sum = 1
4296 08:06:06.942017 9, 0x0, sum = 2
4297 08:06:06.945258 10, 0x0, sum = 3
4298 08:06:06.945338 11, 0x0, sum = 4
4299 08:06:06.948761 best_step = 9
4300 08:06:06.948897
4301 08:06:06.948987 ==
4302 08:06:06.951761 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 08:06:06.955629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 08:06:06.955708 ==
4305 08:06:06.955771 RX Vref Scan: 0
4306 08:06:06.958786
4307 08:06:06.958892 RX Vref 0 -> 0, step: 1
4308 08:06:06.958986
4309 08:06:06.961989 RX Delay -195 -> 252, step: 8
4310 08:06:06.968923 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4311 08:06:06.971953 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4312 08:06:06.975454 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4313 08:06:06.978629 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4314 08:06:06.985467 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4315 08:06:06.988748 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4316 08:06:06.991893 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4317 08:06:06.995252 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4318 08:06:06.998993 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4319 08:06:07.005436 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4320 08:06:07.009227 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4321 08:06:07.012261 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4322 08:06:07.015476 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4323 08:06:07.022056 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4324 08:06:07.025573 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4325 08:06:07.029108 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4326 08:06:07.029188 ==
4327 08:06:07.031928 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 08:06:07.035109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 08:06:07.035194 ==
4330 08:06:07.038760 DQS Delay:
4331 08:06:07.038854 DQS0 = 0, DQS1 = 0
4332 08:06:07.042334 DQM Delay:
4333 08:06:07.042413 DQM0 = 39, DQM1 = 34
4334 08:06:07.042477 DQ Delay:
4335 08:06:07.045044 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4336 08:06:07.048603 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4337 08:06:07.052271 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4338 08:06:07.055481 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4339 08:06:07.055560
4340 08:06:07.055622
4341 08:06:07.065281 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4342 08:06:07.069531 CH0 RK1: MR19=808, MR18=4729
4343 08:06:07.072058 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4344 08:06:07.075382 [RxdqsGatingPostProcess] freq 600
4345 08:06:07.082146 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 08:06:07.085689 Pre-setting of DQS Precalculation
4347 08:06:07.089011 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 08:06:07.089120 ==
4349 08:06:07.092264 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 08:06:07.098658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 08:06:07.098781 ==
4352 08:06:07.102592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 08:06:07.108900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4354 08:06:07.112076 [CA 0] Center 35 (5~66) winsize 62
4355 08:06:07.115447 [CA 1] Center 35 (5~65) winsize 61
4356 08:06:07.118882 [CA 2] Center 34 (4~65) winsize 62
4357 08:06:07.122772 [CA 3] Center 33 (3~64) winsize 62
4358 08:06:07.125525 [CA 4] Center 34 (3~65) winsize 63
4359 08:06:07.128787 [CA 5] Center 33 (3~64) winsize 62
4360 08:06:07.128888
4361 08:06:07.132183 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4362 08:06:07.132264
4363 08:06:07.135926 [CATrainingPosCal] consider 1 rank data
4364 08:06:07.138935 u2DelayCellTimex100 = 270/100 ps
4365 08:06:07.142300 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 08:06:07.145552 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4367 08:06:07.152359 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4368 08:06:07.156071 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4369 08:06:07.159120 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4370 08:06:07.162596 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 08:06:07.162676
4372 08:06:07.165465 CA PerBit enable=1, Macro0, CA PI delay=33
4373 08:06:07.165545
4374 08:06:07.168989 [CBTSetCACLKResult] CA Dly = 33
4375 08:06:07.169068 CS Dly: 3 (0~34)
4376 08:06:07.169132 ==
4377 08:06:07.172700 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 08:06:07.179105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 08:06:07.179185 ==
4380 08:06:07.182550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 08:06:07.189292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 08:06:07.192311 [CA 0] Center 35 (5~66) winsize 62
4383 08:06:07.195903 [CA 1] Center 35 (5~66) winsize 62
4384 08:06:07.199421 [CA 2] Center 34 (4~65) winsize 62
4385 08:06:07.202582 [CA 3] Center 34 (3~65) winsize 63
4386 08:06:07.205994 [CA 4] Center 34 (4~65) winsize 62
4387 08:06:07.209421 [CA 5] Center 33 (3~64) winsize 62
4388 08:06:07.209501
4389 08:06:07.212659 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 08:06:07.212739
4391 08:06:07.216415 [CATrainingPosCal] consider 2 rank data
4392 08:06:07.219212 u2DelayCellTimex100 = 270/100 ps
4393 08:06:07.222363 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 08:06:07.225733 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4395 08:06:07.228987 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4396 08:06:07.236137 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4397 08:06:07.239235 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 08:06:07.242921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 08:06:07.243001
4400 08:06:07.245746 CA PerBit enable=1, Macro0, CA PI delay=33
4401 08:06:07.245826
4402 08:06:07.248993 [CBTSetCACLKResult] CA Dly = 33
4403 08:06:07.249073 CS Dly: 4 (0~36)
4404 08:06:07.249136
4405 08:06:07.252438 ----->DramcWriteLeveling(PI) begin...
4406 08:06:07.252519 ==
4407 08:06:07.255744 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 08:06:07.262604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 08:06:07.262710 ==
4410 08:06:07.266101 Write leveling (Byte 0): 30 => 30
4411 08:06:07.269063 Write leveling (Byte 1): 31 => 31
4412 08:06:07.269143 DramcWriteLeveling(PI) end<-----
4413 08:06:07.269206
4414 08:06:07.272364 ==
4415 08:06:07.276219 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 08:06:07.279069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 08:06:07.279199 ==
4418 08:06:07.282727 [Gating] SW mode calibration
4419 08:06:07.289554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 08:06:07.292623 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 08:06:07.299506 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 08:06:07.302640 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 08:06:07.306380 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 08:06:07.313038 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 1)
4425 08:06:07.316551 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
4426 08:06:07.319346 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 08:06:07.322703 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 08:06:07.330482 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 08:06:07.332839 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4430 08:06:07.336007 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 08:06:07.343057 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 08:06:07.346292 0 10 12 | B1->B0 | 2929 2b2b | 1 1 | (0 0) (0 0)
4433 08:06:07.349627 0 10 16 | B1->B0 | 3939 4444 | 1 1 | (0 0) (0 0)
4434 08:06:07.356116 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 08:06:07.359784 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 08:06:07.362783 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 08:06:07.369633 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 08:06:07.373119 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 08:06:07.376233 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 08:06:07.382696 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 08:06:07.385737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 08:06:07.389350 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 08:06:07.396146 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 08:06:07.399303 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 08:06:07.402818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 08:06:07.409377 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 08:06:07.412711 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 08:06:07.415929 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 08:06:07.422560 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 08:06:07.426161 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 08:06:07.429384 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 08:06:07.435945 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 08:06:07.439181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 08:06:07.442382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 08:06:07.445831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 08:06:07.452848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 08:06:07.456153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 08:06:07.459260 Total UI for P1: 0, mck2ui 16
4459 08:06:07.462785 best dqsien dly found for B0: ( 0, 13, 14)
4460 08:06:07.465870 Total UI for P1: 0, mck2ui 16
4461 08:06:07.469059 best dqsien dly found for B1: ( 0, 13, 14)
4462 08:06:07.472510 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4463 08:06:07.475809 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4464 08:06:07.475880
4465 08:06:07.479455 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4466 08:06:07.482889 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4467 08:06:07.485984 [Gating] SW calibration Done
4468 08:06:07.486055 ==
4469 08:06:07.489276 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 08:06:07.496257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 08:06:07.496336 ==
4472 08:06:07.496398 RX Vref Scan: 0
4473 08:06:07.496470
4474 08:06:07.499356 RX Vref 0 -> 0, step: 1
4475 08:06:07.499427
4476 08:06:07.503068 RX Delay -230 -> 252, step: 16
4477 08:06:07.505865 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4478 08:06:07.509654 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4479 08:06:07.512945 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4480 08:06:07.519826 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4481 08:06:07.522819 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4482 08:06:07.525825 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4483 08:06:07.529404 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4484 08:06:07.532700 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4485 08:06:07.539344 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4486 08:06:07.543074 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4487 08:06:07.546343 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4488 08:06:07.549202 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4489 08:06:07.556004 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4490 08:06:07.559554 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4491 08:06:07.563127 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4492 08:06:07.566050 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4493 08:06:07.566122 ==
4494 08:06:07.569355 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 08:06:07.576112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 08:06:07.576189 ==
4497 08:06:07.576251 DQS Delay:
4498 08:06:07.576309 DQS0 = 0, DQS1 = 0
4499 08:06:07.579340 DQM Delay:
4500 08:06:07.579413 DQM0 = 43, DQM1 = 36
4501 08:06:07.582871 DQ Delay:
4502 08:06:07.586143 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4503 08:06:07.586217 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4504 08:06:07.589308 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4505 08:06:07.596380 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4506 08:06:07.596455
4507 08:06:07.596521
4508 08:06:07.596578 ==
4509 08:06:07.600064 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 08:06:07.602668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 08:06:07.602758 ==
4512 08:06:07.602835
4513 08:06:07.602890
4514 08:06:07.606504 TX Vref Scan disable
4515 08:06:07.606573 == TX Byte 0 ==
4516 08:06:07.613310 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4517 08:06:07.616341 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4518 08:06:07.616407 == TX Byte 1 ==
4519 08:06:07.623134 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4520 08:06:07.626223 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4521 08:06:07.626292 ==
4522 08:06:07.629725 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 08:06:07.632647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 08:06:07.632712 ==
4525 08:06:07.632769
4526 08:06:07.632824
4527 08:06:07.636815 TX Vref Scan disable
4528 08:06:07.639888 == TX Byte 0 ==
4529 08:06:07.643109 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4530 08:06:07.646485 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4531 08:06:07.649588 == TX Byte 1 ==
4532 08:06:07.653167 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4533 08:06:07.656530 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4534 08:06:07.656611
4535 08:06:07.659892 [DATLAT]
4536 08:06:07.659971 Freq=600, CH1 RK0
4537 08:06:07.660035
4538 08:06:07.663151 DATLAT Default: 0x9
4539 08:06:07.663231 0, 0xFFFF, sum = 0
4540 08:06:07.666635 1, 0xFFFF, sum = 0
4541 08:06:07.666779 2, 0xFFFF, sum = 0
4542 08:06:07.669829 3, 0xFFFF, sum = 0
4543 08:06:07.669919 4, 0xFFFF, sum = 0
4544 08:06:07.673594 5, 0xFFFF, sum = 0
4545 08:06:07.673675 6, 0xFFFF, sum = 0
4546 08:06:07.676594 7, 0xFFFF, sum = 0
4547 08:06:07.676676 8, 0x0, sum = 1
4548 08:06:07.679650 9, 0x0, sum = 2
4549 08:06:07.679731 10, 0x0, sum = 3
4550 08:06:07.683600 11, 0x0, sum = 4
4551 08:06:07.683681 best_step = 9
4552 08:06:07.683745
4553 08:06:07.683803 ==
4554 08:06:07.686507 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 08:06:07.689785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 08:06:07.692901 ==
4557 08:06:07.692981 RX Vref Scan: 1
4558 08:06:07.693044
4559 08:06:07.696164 RX Vref 0 -> 0, step: 1
4560 08:06:07.696244
4561 08:06:07.699912 RX Delay -195 -> 252, step: 8
4562 08:06:07.699991
4563 08:06:07.703169 Set Vref, RX VrefLevel [Byte0]: 61
4564 08:06:07.703249 [Byte1]: 53
4565 08:06:07.707825
4566 08:06:07.707921 Final RX Vref Byte 0 = 61 to rank0
4567 08:06:07.711285 Final RX Vref Byte 1 = 53 to rank0
4568 08:06:07.714813 Final RX Vref Byte 0 = 61 to rank1
4569 08:06:07.718070 Final RX Vref Byte 1 = 53 to rank1==
4570 08:06:07.721506 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 08:06:07.727801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 08:06:07.727882 ==
4573 08:06:07.727945 DQS Delay:
4574 08:06:07.728003 DQS0 = 0, DQS1 = 0
4575 08:06:07.731438 DQM Delay:
4576 08:06:07.731517 DQM0 = 40, DQM1 = 34
4577 08:06:07.735091 DQ Delay:
4578 08:06:07.737848 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4579 08:06:07.737928 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4580 08:06:07.741435 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4581 08:06:07.747805 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4582 08:06:07.747885
4583 08:06:07.747947
4584 08:06:07.754440 [DQSOSCAuto] RK0, (LSB)MR18= 0x460a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
4585 08:06:07.757683 CH1 RK0: MR19=808, MR18=460A
4586 08:06:07.764470 CH1_RK0: MR19=0x808, MR18=0x460A, DQSOSC=396, MR23=63, INC=167, DEC=111
4587 08:06:07.764551
4588 08:06:07.768319 ----->DramcWriteLeveling(PI) begin...
4589 08:06:07.768400 ==
4590 08:06:07.771955 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 08:06:07.774689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 08:06:07.774808 ==
4593 08:06:07.777850 Write leveling (Byte 0): 28 => 28
4594 08:06:07.781594 Write leveling (Byte 1): 31 => 31
4595 08:06:07.784536 DramcWriteLeveling(PI) end<-----
4596 08:06:07.784615
4597 08:06:07.784678 ==
4598 08:06:07.788308 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 08:06:07.791647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 08:06:07.791727 ==
4601 08:06:07.794621 [Gating] SW mode calibration
4602 08:06:07.801208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4603 08:06:07.807936 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4604 08:06:07.811498 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 08:06:07.814647 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 08:06:07.821404 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 08:06:07.824562 0 9 12 | B1->B0 | 3232 2727 | 0 0 | (0 1) (0 0)
4608 08:06:07.828116 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4609 08:06:07.835005 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 08:06:07.838304 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 08:06:07.841564 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 08:06:07.848456 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 08:06:07.851903 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 08:06:07.855017 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4615 08:06:07.858588 0 10 12 | B1->B0 | 2f2f 3e3e | 0 0 | (1 1) (0 0)
4616 08:06:07.865254 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 08:06:07.868294 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 08:06:07.871949 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 08:06:07.878409 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 08:06:07.881570 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 08:06:07.884972 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 08:06:07.891840 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 08:06:07.895080 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4624 08:06:07.898516 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4625 08:06:07.905327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 08:06:07.908323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 08:06:07.911620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 08:06:07.918428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 08:06:07.921611 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 08:06:07.925097 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 08:06:07.931715 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 08:06:07.935115 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 08:06:07.938425 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 08:06:07.942115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 08:06:07.948203 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 08:06:07.951620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 08:06:07.955044 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 08:06:07.961760 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 08:06:07.965118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4640 08:06:07.968445 Total UI for P1: 0, mck2ui 16
4641 08:06:07.971751 best dqsien dly found for B0: ( 0, 13, 10)
4642 08:06:07.974882 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4643 08:06:07.981580 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 08:06:07.981652 Total UI for P1: 0, mck2ui 16
4645 08:06:07.988092 best dqsien dly found for B1: ( 0, 13, 14)
4646 08:06:07.991895 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4647 08:06:07.995308 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4648 08:06:07.995389
4649 08:06:07.998548 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4650 08:06:08.002229 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4651 08:06:08.005033 [Gating] SW calibration Done
4652 08:06:08.005103 ==
4653 08:06:08.008466 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 08:06:08.012090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 08:06:08.012159 ==
4656 08:06:08.015172 RX Vref Scan: 0
4657 08:06:08.015269
4658 08:06:08.015356 RX Vref 0 -> 0, step: 1
4659 08:06:08.015440
4660 08:06:08.018961 RX Delay -230 -> 252, step: 16
4661 08:06:08.021777 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4662 08:06:08.028924 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4663 08:06:08.032236 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4664 08:06:08.035544 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4665 08:06:08.038651 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4666 08:06:08.045179 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4667 08:06:08.048700 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4668 08:06:08.052040 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4669 08:06:08.055792 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4670 08:06:08.059079 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4671 08:06:08.065592 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4672 08:06:08.068876 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4673 08:06:08.072001 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4674 08:06:08.075496 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4675 08:06:08.082261 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4676 08:06:08.085602 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4677 08:06:08.085675 ==
4678 08:06:08.088812 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 08:06:08.091858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 08:06:08.091956 ==
4681 08:06:08.095962 DQS Delay:
4682 08:06:08.096028 DQS0 = 0, DQS1 = 0
4683 08:06:08.096088 DQM Delay:
4684 08:06:08.098656 DQM0 = 41, DQM1 = 37
4685 08:06:08.098742 DQ Delay:
4686 08:06:08.102121 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4687 08:06:08.106025 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4688 08:06:08.108710 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4689 08:06:08.112060 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4690 08:06:08.112134
4691 08:06:08.112226
4692 08:06:08.112282 ==
4693 08:06:08.115537 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 08:06:08.118587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 08:06:08.122126 ==
4696 08:06:08.122190
4697 08:06:08.122246
4698 08:06:08.122304 TX Vref Scan disable
4699 08:06:08.125546 == TX Byte 0 ==
4700 08:06:08.128719 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 08:06:08.135826 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 08:06:08.135903 == TX Byte 1 ==
4703 08:06:08.138705 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 08:06:08.145422 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 08:06:08.145496 ==
4706 08:06:08.148549 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 08:06:08.152153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 08:06:08.152230 ==
4709 08:06:08.152292
4710 08:06:08.152352
4711 08:06:08.155408 TX Vref Scan disable
4712 08:06:08.155490 == TX Byte 0 ==
4713 08:06:08.161868 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4714 08:06:08.165410 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4715 08:06:08.165516 == TX Byte 1 ==
4716 08:06:08.171922 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4717 08:06:08.175516 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4718 08:06:08.175596
4719 08:06:08.175660 [DATLAT]
4720 08:06:08.178893 Freq=600, CH1 RK1
4721 08:06:08.178998
4722 08:06:08.179064 DATLAT Default: 0x9
4723 08:06:08.182200 0, 0xFFFF, sum = 0
4724 08:06:08.182308 1, 0xFFFF, sum = 0
4725 08:06:08.185680 2, 0xFFFF, sum = 0
4726 08:06:08.185783 3, 0xFFFF, sum = 0
4727 08:06:08.189548 4, 0xFFFF, sum = 0
4728 08:06:08.189630 5, 0xFFFF, sum = 0
4729 08:06:08.192269 6, 0xFFFF, sum = 0
4730 08:06:08.195449 7, 0xFFFF, sum = 0
4731 08:06:08.195530 8, 0x0, sum = 1
4732 08:06:08.195594 9, 0x0, sum = 2
4733 08:06:08.198841 10, 0x0, sum = 3
4734 08:06:08.198922 11, 0x0, sum = 4
4735 08:06:08.202405 best_step = 9
4736 08:06:08.202484
4737 08:06:08.202547 ==
4738 08:06:08.205565 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 08:06:08.208949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 08:06:08.209086 ==
4741 08:06:08.212388 RX Vref Scan: 0
4742 08:06:08.212468
4743 08:06:08.212531 RX Vref 0 -> 0, step: 1
4744 08:06:08.212590
4745 08:06:08.215703 RX Delay -195 -> 252, step: 8
4746 08:06:08.222910 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4747 08:06:08.225851 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4748 08:06:08.229871 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4749 08:06:08.232753 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4750 08:06:08.239014 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4751 08:06:08.242365 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4752 08:06:08.245970 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4753 08:06:08.248968 iDelay=205, Bit 7, Center 32 (-115 ~ 180) 296
4754 08:06:08.252474 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4755 08:06:08.258973 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4756 08:06:08.262873 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4757 08:06:08.265748 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4758 08:06:08.269066 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4759 08:06:08.276276 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4760 08:06:08.279207 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4761 08:06:08.283265 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4762 08:06:08.283346 ==
4763 08:06:08.286117 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 08:06:08.289243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 08:06:08.289324 ==
4766 08:06:08.292605 DQS Delay:
4767 08:06:08.292685 DQS0 = 0, DQS1 = 0
4768 08:06:08.295807 DQM Delay:
4769 08:06:08.295903 DQM0 = 39, DQM1 = 32
4770 08:06:08.295998 DQ Delay:
4771 08:06:08.299618 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4772 08:06:08.302597 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4773 08:06:08.305871 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4774 08:06:08.309246 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4775 08:06:08.309331
4776 08:06:08.309395
4777 08:06:08.319564 [DQSOSCAuto] RK1, (LSB)MR18= 0x3846, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4778 08:06:08.322943 CH1 RK1: MR19=808, MR18=3846
4779 08:06:08.326161 CH1_RK1: MR19=0x808, MR18=0x3846, DQSOSC=396, MR23=63, INC=167, DEC=111
4780 08:06:08.329363 [RxdqsGatingPostProcess] freq 600
4781 08:06:08.336183 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4782 08:06:08.339414 Pre-setting of DQS Precalculation
4783 08:06:08.343058 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4784 08:06:08.352554 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4785 08:06:08.359321 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4786 08:06:08.359402
4787 08:06:08.359465
4788 08:06:08.362671 [Calibration Summary] 1200 Mbps
4789 08:06:08.362820 CH 0, Rank 0
4790 08:06:08.366260 SW Impedance : PASS
4791 08:06:08.366371 DUTY Scan : NO K
4792 08:06:08.369158 ZQ Calibration : PASS
4793 08:06:08.372988 Jitter Meter : NO K
4794 08:06:08.373067 CBT Training : PASS
4795 08:06:08.376276 Write leveling : PASS
4796 08:06:08.379381 RX DQS gating : PASS
4797 08:06:08.379461 RX DQ/DQS(RDDQC) : PASS
4798 08:06:08.382919 TX DQ/DQS : PASS
4799 08:06:08.382999 RX DATLAT : PASS
4800 08:06:08.386073 RX DQ/DQS(Engine): PASS
4801 08:06:08.389224 TX OE : NO K
4802 08:06:08.389321 All Pass.
4803 08:06:08.389399
4804 08:06:08.389456 CH 0, Rank 1
4805 08:06:08.393011 SW Impedance : PASS
4806 08:06:08.396507 DUTY Scan : NO K
4807 08:06:08.396587 ZQ Calibration : PASS
4808 08:06:08.399377 Jitter Meter : NO K
4809 08:06:08.402795 CBT Training : PASS
4810 08:06:08.402892 Write leveling : PASS
4811 08:06:08.406422 RX DQS gating : PASS
4812 08:06:08.409715 RX DQ/DQS(RDDQC) : PASS
4813 08:06:08.409795 TX DQ/DQS : PASS
4814 08:06:08.412629 RX DATLAT : PASS
4815 08:06:08.416407 RX DQ/DQS(Engine): PASS
4816 08:06:08.416486 TX OE : NO K
4817 08:06:08.416550 All Pass.
4818 08:06:08.419666
4819 08:06:08.419745 CH 1, Rank 0
4820 08:06:08.422633 SW Impedance : PASS
4821 08:06:08.422737 DUTY Scan : NO K
4822 08:06:08.426247 ZQ Calibration : PASS
4823 08:06:08.426327 Jitter Meter : NO K
4824 08:06:08.429368 CBT Training : PASS
4825 08:06:08.432793 Write leveling : PASS
4826 08:06:08.432874 RX DQS gating : PASS
4827 08:06:08.436495 RX DQ/DQS(RDDQC) : PASS
4828 08:06:08.439332 TX DQ/DQS : PASS
4829 08:06:08.439415 RX DATLAT : PASS
4830 08:06:08.442644 RX DQ/DQS(Engine): PASS
4831 08:06:08.445978 TX OE : NO K
4832 08:06:08.446049 All Pass.
4833 08:06:08.446109
4834 08:06:08.446165 CH 1, Rank 1
4835 08:06:08.449375 SW Impedance : PASS
4836 08:06:08.452568 DUTY Scan : NO K
4837 08:06:08.452636 ZQ Calibration : PASS
4838 08:06:08.456027 Jitter Meter : NO K
4839 08:06:08.459653 CBT Training : PASS
4840 08:06:08.459718 Write leveling : PASS
4841 08:06:08.462504 RX DQS gating : PASS
4842 08:06:08.466303 RX DQ/DQS(RDDQC) : PASS
4843 08:06:08.466371 TX DQ/DQS : PASS
4844 08:06:08.469215 RX DATLAT : PASS
4845 08:06:08.469280 RX DQ/DQS(Engine): PASS
4846 08:06:08.472457 TX OE : NO K
4847 08:06:08.472523 All Pass.
4848 08:06:08.475977
4849 08:06:08.476045 DramC Write-DBI off
4850 08:06:08.479076 PER_BANK_REFRESH: Hybrid Mode
4851 08:06:08.479147 TX_TRACKING: ON
4852 08:06:08.488974 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4853 08:06:08.492314 [FAST_K] Save calibration result to emmc
4854 08:06:08.496347 dramc_set_vcore_voltage set vcore to 662500
4855 08:06:08.499272 Read voltage for 933, 3
4856 08:06:08.499345 Vio18 = 0
4857 08:06:08.502771 Vcore = 662500
4858 08:06:08.502856 Vdram = 0
4859 08:06:08.502915 Vddq = 0
4860 08:06:08.502972 Vmddr = 0
4861 08:06:08.509201 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4862 08:06:08.512334 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4863 08:06:08.515620 MEM_TYPE=3, freq_sel=17
4864 08:06:08.519181 sv_algorithm_assistance_LP4_1600
4865 08:06:08.522571 ============ PULL DRAM RESETB DOWN ============
4866 08:06:08.528934 ========== PULL DRAM RESETB DOWN end =========
4867 08:06:08.532867 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4868 08:06:08.535963 ===================================
4869 08:06:08.539385 LPDDR4 DRAM CONFIGURATION
4870 08:06:08.542487 ===================================
4871 08:06:08.542561 EX_ROW_EN[0] = 0x0
4872 08:06:08.546454 EX_ROW_EN[1] = 0x0
4873 08:06:08.546552 LP4Y_EN = 0x0
4874 08:06:08.549249 WORK_FSP = 0x0
4875 08:06:08.549323 WL = 0x3
4876 08:06:08.552505 RL = 0x3
4877 08:06:08.552580 BL = 0x2
4878 08:06:08.555764 RPST = 0x0
4879 08:06:08.555837 RD_PRE = 0x0
4880 08:06:08.559321 WR_PRE = 0x1
4881 08:06:08.559397 WR_PST = 0x0
4882 08:06:08.562807 DBI_WR = 0x0
4883 08:06:08.562904 DBI_RD = 0x0
4884 08:06:08.565928 OTF = 0x1
4885 08:06:08.569180 ===================================
4886 08:06:08.572955 ===================================
4887 08:06:08.573026 ANA top config
4888 08:06:08.575904 ===================================
4889 08:06:08.579134 DLL_ASYNC_EN = 0
4890 08:06:08.583031 ALL_SLAVE_EN = 1
4891 08:06:08.586640 NEW_RANK_MODE = 1
4892 08:06:08.586756 DLL_IDLE_MODE = 1
4893 08:06:08.589423 LP45_APHY_COMB_EN = 1
4894 08:06:08.592563 TX_ODT_DIS = 1
4895 08:06:08.595828 NEW_8X_MODE = 1
4896 08:06:08.599549 ===================================
4897 08:06:08.602832 ===================================
4898 08:06:08.606090 data_rate = 1866
4899 08:06:08.606157 CKR = 1
4900 08:06:08.609625 DQ_P2S_RATIO = 8
4901 08:06:08.613025 ===================================
4902 08:06:08.616346 CA_P2S_RATIO = 8
4903 08:06:08.619711 DQ_CA_OPEN = 0
4904 08:06:08.623042 DQ_SEMI_OPEN = 0
4905 08:06:08.623109 CA_SEMI_OPEN = 0
4906 08:06:08.626190 CA_FULL_RATE = 0
4907 08:06:08.629570 DQ_CKDIV4_EN = 1
4908 08:06:08.633156 CA_CKDIV4_EN = 1
4909 08:06:08.636129 CA_PREDIV_EN = 0
4910 08:06:08.639378 PH8_DLY = 0
4911 08:06:08.639445 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4912 08:06:08.642688 DQ_AAMCK_DIV = 4
4913 08:06:08.646170 CA_AAMCK_DIV = 4
4914 08:06:08.649675 CA_ADMCK_DIV = 4
4915 08:06:08.652932 DQ_TRACK_CA_EN = 0
4916 08:06:08.656551 CA_PICK = 933
4917 08:06:08.656652 CA_MCKIO = 933
4918 08:06:08.659909 MCKIO_SEMI = 0
4919 08:06:08.663349 PLL_FREQ = 3732
4920 08:06:08.666550 DQ_UI_PI_RATIO = 32
4921 08:06:08.669597 CA_UI_PI_RATIO = 0
4922 08:06:08.673109 ===================================
4923 08:06:08.676239 ===================================
4924 08:06:08.679714 memory_type:LPDDR4
4925 08:06:08.679795 GP_NUM : 10
4926 08:06:08.683201 SRAM_EN : 1
4927 08:06:08.683281 MD32_EN : 0
4928 08:06:08.686520 ===================================
4929 08:06:08.689493 [ANA_INIT] >>>>>>>>>>>>>>
4930 08:06:08.692987 <<<<<< [CONFIGURE PHASE]: ANA_TX
4931 08:06:08.696253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4932 08:06:08.699554 ===================================
4933 08:06:08.702857 data_rate = 1866,PCW = 0X8f00
4934 08:06:08.706656 ===================================
4935 08:06:08.710069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4936 08:06:08.712978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 08:06:08.719998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 08:06:08.723012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4939 08:06:08.729869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4940 08:06:08.733109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4941 08:06:08.733189 [ANA_INIT] flow start
4942 08:06:08.736180 [ANA_INIT] PLL >>>>>>>>
4943 08:06:08.739538 [ANA_INIT] PLL <<<<<<<<
4944 08:06:08.739618 [ANA_INIT] MIDPI >>>>>>>>
4945 08:06:08.743067 [ANA_INIT] MIDPI <<<<<<<<
4946 08:06:08.746620 [ANA_INIT] DLL >>>>>>>>
4947 08:06:08.746700 [ANA_INIT] flow end
4948 08:06:08.749873 ============ LP4 DIFF to SE enter ============
4949 08:06:08.756619 ============ LP4 DIFF to SE exit ============
4950 08:06:08.756726 [ANA_INIT] <<<<<<<<<<<<<
4951 08:06:08.759783 [Flow] Enable top DCM control >>>>>
4952 08:06:08.763429 [Flow] Enable top DCM control <<<<<
4953 08:06:08.766738 Enable DLL master slave shuffle
4954 08:06:08.773241 ==============================================================
4955 08:06:08.773322 Gating Mode config
4956 08:06:08.779678 ==============================================================
4957 08:06:08.783105 Config description:
4958 08:06:08.793147 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4959 08:06:08.799605 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4960 08:06:08.803398 SELPH_MODE 0: By rank 1: By Phase
4961 08:06:08.810107 ==============================================================
4962 08:06:08.810203 GAT_TRACK_EN = 1
4963 08:06:08.813260 RX_GATING_MODE = 2
4964 08:06:08.816585 RX_GATING_TRACK_MODE = 2
4965 08:06:08.819967 SELPH_MODE = 1
4966 08:06:08.823080 PICG_EARLY_EN = 1
4967 08:06:08.826665 VALID_LAT_VALUE = 1
4968 08:06:08.833428 ==============================================================
4969 08:06:08.836979 Enter into Gating configuration >>>>
4970 08:06:08.839846 Exit from Gating configuration <<<<
4971 08:06:08.843201 Enter into DVFS_PRE_config >>>>>
4972 08:06:08.852987 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4973 08:06:08.856344 Exit from DVFS_PRE_config <<<<<
4974 08:06:08.859606 Enter into PICG configuration >>>>
4975 08:06:08.863073 Exit from PICG configuration <<<<
4976 08:06:08.866347 [RX_INPUT] configuration >>>>>
4977 08:06:08.866421 [RX_INPUT] configuration <<<<<
4978 08:06:08.872931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4979 08:06:08.879594 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4980 08:06:08.883007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 08:06:08.889839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 08:06:08.896495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 08:06:08.903004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 08:06:08.906271 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4985 08:06:08.909897 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4986 08:06:08.916342 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4987 08:06:08.919737 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4988 08:06:08.923264 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4989 08:06:08.926828 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 08:06:08.929650 ===================================
4991 08:06:08.933117 LPDDR4 DRAM CONFIGURATION
4992 08:06:08.936649 ===================================
4993 08:06:08.939698 EX_ROW_EN[0] = 0x0
4994 08:06:08.939780 EX_ROW_EN[1] = 0x0
4995 08:06:08.943187 LP4Y_EN = 0x0
4996 08:06:08.943267 WORK_FSP = 0x0
4997 08:06:08.946435 WL = 0x3
4998 08:06:08.946535 RL = 0x3
4999 08:06:08.949757 BL = 0x2
5000 08:06:08.949837 RPST = 0x0
5001 08:06:08.953434 RD_PRE = 0x0
5002 08:06:08.953515 WR_PRE = 0x1
5003 08:06:08.956578 WR_PST = 0x0
5004 08:06:08.956658 DBI_WR = 0x0
5005 08:06:08.959779 DBI_RD = 0x0
5006 08:06:08.963056 OTF = 0x1
5007 08:06:08.963138 ===================================
5008 08:06:08.969763 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5009 08:06:08.973266 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5010 08:06:08.976389 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 08:06:08.980138 ===================================
5012 08:06:08.983227 LPDDR4 DRAM CONFIGURATION
5013 08:06:08.987089 ===================================
5014 08:06:08.990298 EX_ROW_EN[0] = 0x10
5015 08:06:08.990379 EX_ROW_EN[1] = 0x0
5016 08:06:08.993168 LP4Y_EN = 0x0
5017 08:06:08.993249 WORK_FSP = 0x0
5018 08:06:08.997243 WL = 0x3
5019 08:06:08.997325 RL = 0x3
5020 08:06:08.999866 BL = 0x2
5021 08:06:08.999984 RPST = 0x0
5022 08:06:09.003219 RD_PRE = 0x0
5023 08:06:09.003316 WR_PRE = 0x1
5024 08:06:09.007350 WR_PST = 0x0
5025 08:06:09.007430 DBI_WR = 0x0
5026 08:06:09.010012 DBI_RD = 0x0
5027 08:06:09.010093 OTF = 0x1
5028 08:06:09.013271 ===================================
5029 08:06:09.020278 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5030 08:06:09.024830 nWR fixed to 30
5031 08:06:09.027785 [ModeRegInit_LP4] CH0 RK0
5032 08:06:09.027866 [ModeRegInit_LP4] CH0 RK1
5033 08:06:09.031133 [ModeRegInit_LP4] CH1 RK0
5034 08:06:09.034982 [ModeRegInit_LP4] CH1 RK1
5035 08:06:09.035063 match AC timing 9
5036 08:06:09.041564 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5037 08:06:09.044624 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5038 08:06:09.048073 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5039 08:06:09.054683 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5040 08:06:09.057971 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5041 08:06:09.058060 ==
5042 08:06:09.061386 Dram Type= 6, Freq= 0, CH_0, rank 0
5043 08:06:09.064343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5044 08:06:09.064424 ==
5045 08:06:09.071160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5046 08:06:09.077746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5047 08:06:09.081520 [CA 0] Center 38 (7~69) winsize 63
5048 08:06:09.084855 [CA 1] Center 38 (7~69) winsize 63
5049 08:06:09.087659 [CA 2] Center 35 (5~66) winsize 62
5050 08:06:09.091166 [CA 3] Center 35 (5~66) winsize 62
5051 08:06:09.094449 [CA 4] Center 34 (4~65) winsize 62
5052 08:06:09.097861 [CA 5] Center 34 (4~64) winsize 61
5053 08:06:09.097942
5054 08:06:09.101628 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5055 08:06:09.101709
5056 08:06:09.104676 [CATrainingPosCal] consider 1 rank data
5057 08:06:09.108133 u2DelayCellTimex100 = 270/100 ps
5058 08:06:09.111241 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5059 08:06:09.114948 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5060 08:06:09.118221 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5061 08:06:09.121730 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5062 08:06:09.124898 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5063 08:06:09.128056 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5064 08:06:09.128137
5065 08:06:09.131591 CA PerBit enable=1, Macro0, CA PI delay=34
5066 08:06:09.131688
5067 08:06:09.134544 [CBTSetCACLKResult] CA Dly = 34
5068 08:06:09.138112 CS Dly: 7 (0~38)
5069 08:06:09.138192 ==
5070 08:06:09.141240 Dram Type= 6, Freq= 0, CH_0, rank 1
5071 08:06:09.144855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 08:06:09.144938 ==
5073 08:06:09.151629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 08:06:09.157910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5075 08:06:09.161449 [CA 0] Center 38 (8~69) winsize 62
5076 08:06:09.164581 [CA 1] Center 38 (8~69) winsize 62
5077 08:06:09.168332 [CA 2] Center 35 (5~66) winsize 62
5078 08:06:09.171336 [CA 3] Center 35 (5~66) winsize 62
5079 08:06:09.174696 [CA 4] Center 34 (4~65) winsize 62
5080 08:06:09.174820 [CA 5] Center 33 (3~64) winsize 62
5081 08:06:09.178510
5082 08:06:09.181799 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5083 08:06:09.181881
5084 08:06:09.184766 [CATrainingPosCal] consider 2 rank data
5085 08:06:09.188533 u2DelayCellTimex100 = 270/100 ps
5086 08:06:09.191630 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5087 08:06:09.195499 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5088 08:06:09.198105 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5089 08:06:09.201631 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5090 08:06:09.204836 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5091 08:06:09.207973 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5092 08:06:09.208070
5093 08:06:09.211620 CA PerBit enable=1, Macro0, CA PI delay=34
5094 08:06:09.211715
5095 08:06:09.214888 [CBTSetCACLKResult] CA Dly = 34
5096 08:06:09.217980 CS Dly: 7 (0~39)
5097 08:06:09.218078
5098 08:06:09.221729 ----->DramcWriteLeveling(PI) begin...
5099 08:06:09.221810 ==
5100 08:06:09.224840 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 08:06:09.228148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 08:06:09.228230 ==
5103 08:06:09.231378 Write leveling (Byte 0): 32 => 32
5104 08:06:09.234603 Write leveling (Byte 1): 25 => 25
5105 08:06:09.238228 DramcWriteLeveling(PI) end<-----
5106 08:06:09.238325
5107 08:06:09.238420 ==
5108 08:06:09.241442 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 08:06:09.245095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 08:06:09.245192 ==
5111 08:06:09.248141 [Gating] SW mode calibration
5112 08:06:09.255672 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5113 08:06:09.261836 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5114 08:06:09.265173 0 14 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5115 08:06:09.268091 0 14 4 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
5116 08:06:09.275089 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 08:06:09.278351 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 08:06:09.281483 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 08:06:09.288320 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 08:06:09.291587 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 08:06:09.294908 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5122 08:06:09.301969 0 15 0 | B1->B0 | 3131 2525 | 0 0 | (0 0) (1 0)
5123 08:06:09.304874 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5124 08:06:09.308446 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 08:06:09.314916 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 08:06:09.318374 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 08:06:09.321451 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 08:06:09.328443 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 08:06:09.331387 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 08:06:09.334922 1 0 0 | B1->B0 | 3232 4242 | 1 0 | (0 0) (0 0)
5131 08:06:09.341899 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 08:06:09.344974 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 08:06:09.348587 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 08:06:09.351942 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 08:06:09.358395 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 08:06:09.361610 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 08:06:09.365033 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 08:06:09.372210 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5139 08:06:09.375251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 08:06:09.378267 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 08:06:09.385114 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 08:06:09.388360 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 08:06:09.391990 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 08:06:09.398467 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 08:06:09.401619 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 08:06:09.404859 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 08:06:09.411773 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 08:06:09.414943 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 08:06:09.418329 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 08:06:09.425348 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 08:06:09.428668 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 08:06:09.432007 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 08:06:09.435036 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5154 08:06:09.442106 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5155 08:06:09.445202 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5156 08:06:09.448967 Total UI for P1: 0, mck2ui 16
5157 08:06:09.452216 best dqsien dly found for B0: ( 1, 2, 30)
5158 08:06:09.455028 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 08:06:09.458362 Total UI for P1: 0, mck2ui 16
5160 08:06:09.462141 best dqsien dly found for B1: ( 1, 3, 4)
5161 08:06:09.465679 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5162 08:06:09.468709 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5163 08:06:09.468791
5164 08:06:09.475464 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5165 08:06:09.478988 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5166 08:06:09.479109 [Gating] SW calibration Done
5167 08:06:09.482416 ==
5168 08:06:09.482497 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 08:06:09.488676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 08:06:09.488757 ==
5171 08:06:09.488856 RX Vref Scan: 0
5172 08:06:09.488916
5173 08:06:09.492287 RX Vref 0 -> 0, step: 1
5174 08:06:09.492369
5175 08:06:09.495238 RX Delay -80 -> 252, step: 8
5176 08:06:09.498662 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5177 08:06:09.502293 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5178 08:06:09.505496 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5179 08:06:09.508813 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5180 08:06:09.515753 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5181 08:06:09.519173 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5182 08:06:09.522521 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5183 08:06:09.525852 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5184 08:06:09.529336 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5185 08:06:09.532817 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5186 08:06:09.538981 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5187 08:06:09.541975 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5188 08:06:09.545564 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5189 08:06:09.549163 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5190 08:06:09.552265 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5191 08:06:09.555782 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5192 08:06:09.558969 ==
5193 08:06:09.562291 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 08:06:09.565702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 08:06:09.565784 ==
5196 08:06:09.565847 DQS Delay:
5197 08:06:09.568796 DQS0 = 0, DQS1 = 0
5198 08:06:09.568877 DQM Delay:
5199 08:06:09.572295 DQM0 = 99, DQM1 = 87
5200 08:06:09.572376 DQ Delay:
5201 08:06:09.575765 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5202 08:06:09.579185 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5203 08:06:09.582680 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5204 08:06:09.585674 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5205 08:06:09.585758
5206 08:06:09.585871
5207 08:06:09.585995 ==
5208 08:06:09.588566 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 08:06:09.592098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 08:06:09.592179 ==
5211 08:06:09.592243
5212 08:06:09.595219
5213 08:06:09.595300 TX Vref Scan disable
5214 08:06:09.598608 == TX Byte 0 ==
5215 08:06:09.601740 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5216 08:06:09.605415 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5217 08:06:09.608737 == TX Byte 1 ==
5218 08:06:09.611732 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5219 08:06:09.614994 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5220 08:06:09.615073 ==
5221 08:06:09.618334 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 08:06:09.625240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 08:06:09.625408 ==
5224 08:06:09.625526
5225 08:06:09.625642
5226 08:06:09.625766 TX Vref Scan disable
5227 08:06:09.630043 == TX Byte 0 ==
5228 08:06:09.632887 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5229 08:06:09.636400 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5230 08:06:09.640038 == TX Byte 1 ==
5231 08:06:09.642956 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5232 08:06:09.646352 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5233 08:06:09.649619
5234 08:06:09.649771 [DATLAT]
5235 08:06:09.649878 Freq=933, CH0 RK0
5236 08:06:09.649964
5237 08:06:09.652833 DATLAT Default: 0xd
5238 08:06:09.652947 0, 0xFFFF, sum = 0
5239 08:06:09.656248 1, 0xFFFF, sum = 0
5240 08:06:09.656324 2, 0xFFFF, sum = 0
5241 08:06:09.659441 3, 0xFFFF, sum = 0
5242 08:06:09.659545 4, 0xFFFF, sum = 0
5243 08:06:09.663073 5, 0xFFFF, sum = 0
5244 08:06:09.666067 6, 0xFFFF, sum = 0
5245 08:06:09.666150 7, 0xFFFF, sum = 0
5246 08:06:09.669351 8, 0xFFFF, sum = 0
5247 08:06:09.669443 9, 0xFFFF, sum = 0
5248 08:06:09.673150 10, 0x0, sum = 1
5249 08:06:09.673239 11, 0x0, sum = 2
5250 08:06:09.673352 12, 0x0, sum = 3
5251 08:06:09.676198 13, 0x0, sum = 4
5252 08:06:09.676305 best_step = 11
5253 08:06:09.676398
5254 08:06:09.676461 ==
5255 08:06:09.679393 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 08:06:09.686282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 08:06:09.686406 ==
5258 08:06:09.686498 RX Vref Scan: 1
5259 08:06:09.686576
5260 08:06:09.689775 RX Vref 0 -> 0, step: 1
5261 08:06:09.689909
5262 08:06:09.692829 RX Delay -61 -> 252, step: 4
5263 08:06:09.692936
5264 08:06:09.696463 Set Vref, RX VrefLevel [Byte0]: 56
5265 08:06:09.699494 [Byte1]: 50
5266 08:06:09.699569
5267 08:06:09.703128 Final RX Vref Byte 0 = 56 to rank0
5268 08:06:09.706609 Final RX Vref Byte 1 = 50 to rank0
5269 08:06:09.709739 Final RX Vref Byte 0 = 56 to rank1
5270 08:06:09.713240 Final RX Vref Byte 1 = 50 to rank1==
5271 08:06:09.716481 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 08:06:09.720298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 08:06:09.720404 ==
5274 08:06:09.723479 DQS Delay:
5275 08:06:09.723620 DQS0 = 0, DQS1 = 0
5276 08:06:09.723716 DQM Delay:
5277 08:06:09.726692 DQM0 = 96, DQM1 = 87
5278 08:06:09.726824 DQ Delay:
5279 08:06:09.729749 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5280 08:06:09.733258 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5281 08:06:09.736554 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5282 08:06:09.739578 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5283 08:06:09.739666
5284 08:06:09.739728
5285 08:06:09.749804 [DQSOSCAuto] RK0, (LSB)MR18= 0x1702, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5286 08:06:09.753362 CH0 RK0: MR19=505, MR18=1702
5287 08:06:09.756393 CH0_RK0: MR19=0x505, MR18=0x1702, DQSOSC=414, MR23=63, INC=63, DEC=42
5288 08:06:09.756475
5289 08:06:09.760341 ----->DramcWriteLeveling(PI) begin...
5290 08:06:09.760438 ==
5291 08:06:09.763218 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 08:06:09.770015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 08:06:09.770102 ==
5294 08:06:09.773073 Write leveling (Byte 0): 31 => 31
5295 08:06:09.776928 Write leveling (Byte 1): 28 => 28
5296 08:06:09.777010 DramcWriteLeveling(PI) end<-----
5297 08:06:09.777074
5298 08:06:09.780547 ==
5299 08:06:09.783147 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 08:06:09.786808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 08:06:09.786890 ==
5302 08:06:09.789847 [Gating] SW mode calibration
5303 08:06:09.796668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5304 08:06:09.800174 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5305 08:06:09.807016 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
5306 08:06:09.810615 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 08:06:09.813502 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 08:06:09.820185 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 08:06:09.823613 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 08:06:09.826830 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 08:06:09.833528 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 08:06:09.837055 0 14 28 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 1)
5313 08:06:09.839952 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5314 08:06:09.846933 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 08:06:09.849986 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 08:06:09.854131 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 08:06:09.856664 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 08:06:09.863872 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 08:06:09.866762 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 08:06:09.870313 0 15 28 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
5321 08:06:09.876991 1 0 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
5322 08:06:09.880064 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 08:06:09.883352 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 08:06:09.890316 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 08:06:09.893683 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 08:06:09.896627 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 08:06:09.903233 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 08:06:09.906588 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5329 08:06:09.909999 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5330 08:06:09.916974 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5331 08:06:09.920192 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 08:06:09.923231 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 08:06:09.929873 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 08:06:09.933761 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 08:06:09.936797 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 08:06:09.943328 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 08:06:09.946575 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 08:06:09.950067 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 08:06:09.956736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 08:06:09.959887 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 08:06:09.963473 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 08:06:09.966559 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 08:06:09.973310 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5344 08:06:09.976731 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5345 08:06:09.980396 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5346 08:06:09.983709 Total UI for P1: 0, mck2ui 16
5347 08:06:09.986977 best dqsien dly found for B0: ( 1, 2, 26)
5348 08:06:09.993546 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 08:06:09.993672 Total UI for P1: 0, mck2ui 16
5350 08:06:10.000090 best dqsien dly found for B1: ( 1, 3, 0)
5351 08:06:10.003377 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5352 08:06:10.007024 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5353 08:06:10.007126
5354 08:06:10.010523 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5355 08:06:10.013240 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5356 08:06:10.016597 [Gating] SW calibration Done
5357 08:06:10.016725 ==
5358 08:06:10.020023 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 08:06:10.023482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 08:06:10.023568 ==
5361 08:06:10.026670 RX Vref Scan: 0
5362 08:06:10.026813
5363 08:06:10.026919 RX Vref 0 -> 0, step: 1
5364 08:06:10.027069
5365 08:06:10.030073 RX Delay -80 -> 252, step: 8
5366 08:06:10.033541 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5367 08:06:10.036741 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5368 08:06:10.043073 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5369 08:06:10.046677 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5370 08:06:10.049773 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5371 08:06:10.053325 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5372 08:06:10.056934 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5373 08:06:10.060128 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5374 08:06:10.066684 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5375 08:06:10.069870 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5376 08:06:10.073060 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5377 08:06:10.077031 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5378 08:06:10.080165 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5379 08:06:10.086510 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5380 08:06:10.090038 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5381 08:06:10.093568 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5382 08:06:10.093648 ==
5383 08:06:10.096995 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 08:06:10.099785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 08:06:10.099865 ==
5386 08:06:10.103049 DQS Delay:
5387 08:06:10.103146 DQS0 = 0, DQS1 = 0
5388 08:06:10.103223 DQM Delay:
5389 08:06:10.106919 DQM0 = 98, DQM1 = 88
5390 08:06:10.107022 DQ Delay:
5391 08:06:10.110227 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =95
5392 08:06:10.113372 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =111
5393 08:06:10.116453 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5394 08:06:10.119715 DQ12 =87, DQ13 =95, DQ14 =99, DQ15 =95
5395 08:06:10.119788
5396 08:06:10.119849
5397 08:06:10.119909 ==
5398 08:06:10.123156 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 08:06:10.130107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 08:06:10.130205 ==
5401 08:06:10.130285
5402 08:06:10.130375
5403 08:06:10.130449 TX Vref Scan disable
5404 08:06:10.133943 == TX Byte 0 ==
5405 08:06:10.137043 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5406 08:06:10.140105 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5407 08:06:10.144047 == TX Byte 1 ==
5408 08:06:10.146915 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5409 08:06:10.150121 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5410 08:06:10.153644 ==
5411 08:06:10.157045 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 08:06:10.160088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 08:06:10.160170 ==
5414 08:06:10.160270
5415 08:06:10.160330
5416 08:06:10.163618 TX Vref Scan disable
5417 08:06:10.163703 == TX Byte 0 ==
5418 08:06:10.170563 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5419 08:06:10.173895 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5420 08:06:10.173968 == TX Byte 1 ==
5421 08:06:10.180328 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5422 08:06:10.183602 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5423 08:06:10.183676
5424 08:06:10.183736 [DATLAT]
5425 08:06:10.187234 Freq=933, CH0 RK1
5426 08:06:10.187303
5427 08:06:10.187368 DATLAT Default: 0xb
5428 08:06:10.190287 0, 0xFFFF, sum = 0
5429 08:06:10.190361 1, 0xFFFF, sum = 0
5430 08:06:10.193485 2, 0xFFFF, sum = 0
5431 08:06:10.193556 3, 0xFFFF, sum = 0
5432 08:06:10.197884 4, 0xFFFF, sum = 0
5433 08:06:10.197961 5, 0xFFFF, sum = 0
5434 08:06:10.200518 6, 0xFFFF, sum = 0
5435 08:06:10.200586 7, 0xFFFF, sum = 0
5436 08:06:10.203663 8, 0xFFFF, sum = 0
5437 08:06:10.203740 9, 0xFFFF, sum = 0
5438 08:06:10.207062 10, 0x0, sum = 1
5439 08:06:10.207143 11, 0x0, sum = 2
5440 08:06:10.210466 12, 0x0, sum = 3
5441 08:06:10.210542 13, 0x0, sum = 4
5442 08:06:10.213496 best_step = 11
5443 08:06:10.213572
5444 08:06:10.213641 ==
5445 08:06:10.216981 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 08:06:10.220118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 08:06:10.220194 ==
5448 08:06:10.223678 RX Vref Scan: 0
5449 08:06:10.223755
5450 08:06:10.223862 RX Vref 0 -> 0, step: 1
5451 08:06:10.223921
5452 08:06:10.226842 RX Delay -61 -> 252, step: 4
5453 08:06:10.233879 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5454 08:06:10.237116 iDelay=199, Bit 1, Center 96 (-1 ~ 194) 196
5455 08:06:10.240520 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5456 08:06:10.243889 iDelay=199, Bit 3, Center 96 (-1 ~ 194) 196
5457 08:06:10.247180 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5458 08:06:10.250614 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5459 08:06:10.257255 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5460 08:06:10.260540 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5461 08:06:10.264030 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5462 08:06:10.267193 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5463 08:06:10.270593 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5464 08:06:10.274206 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5465 08:06:10.281010 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5466 08:06:10.283784 iDelay=199, Bit 13, Center 92 (7 ~ 178) 172
5467 08:06:10.287310 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5468 08:06:10.290522 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5469 08:06:10.290589 ==
5470 08:06:10.293810 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 08:06:10.297364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 08:06:10.300667 ==
5473 08:06:10.300735 DQS Delay:
5474 08:06:10.300794 DQS0 = 0, DQS1 = 0
5475 08:06:10.304654 DQM Delay:
5476 08:06:10.304723 DQM0 = 96, DQM1 = 87
5477 08:06:10.307960 DQ Delay:
5478 08:06:10.310994 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =96
5479 08:06:10.311063 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5480 08:06:10.314039 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5481 08:06:10.317722 DQ12 =90, DQ13 =92, DQ14 =98, DQ15 =94
5482 08:06:10.320954
5483 08:06:10.321034
5484 08:06:10.327724 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
5485 08:06:10.330822 CH0 RK1: MR19=505, MR18=1C09
5486 08:06:10.337604 CH0_RK1: MR19=0x505, MR18=0x1C09, DQSOSC=412, MR23=63, INC=63, DEC=42
5487 08:06:10.340769 [RxdqsGatingPostProcess] freq 933
5488 08:06:10.344183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5489 08:06:10.347812 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 08:06:10.351105 best DQS1 dly(2T, 0.5T) = (0, 11)
5491 08:06:10.353821 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 08:06:10.357637 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5493 08:06:10.360864 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 08:06:10.363877 best DQS1 dly(2T, 0.5T) = (0, 11)
5495 08:06:10.367358 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 08:06:10.370794 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5497 08:06:10.373811 Pre-setting of DQS Precalculation
5498 08:06:10.377694 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5499 08:06:10.377766 ==
5500 08:06:10.380741 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 08:06:10.383864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 08:06:10.387213 ==
5503 08:06:10.390579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 08:06:10.397198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5505 08:06:10.400917 [CA 0] Center 36 (6~67) winsize 62
5506 08:06:10.404197 [CA 1] Center 36 (6~67) winsize 62
5507 08:06:10.407075 [CA 2] Center 34 (4~64) winsize 61
5508 08:06:10.410878 [CA 3] Center 33 (3~64) winsize 62
5509 08:06:10.414253 [CA 4] Center 34 (4~64) winsize 61
5510 08:06:10.417433 [CA 5] Center 33 (3~63) winsize 61
5511 08:06:10.417549
5512 08:06:10.420754 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5513 08:06:10.420821
5514 08:06:10.423736 [CATrainingPosCal] consider 1 rank data
5515 08:06:10.427058 u2DelayCellTimex100 = 270/100 ps
5516 08:06:10.430441 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 08:06:10.434208 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5518 08:06:10.436947 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 08:06:10.440738 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5520 08:06:10.447264 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5521 08:06:10.450369 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5522 08:06:10.450438
5523 08:06:10.453720 CA PerBit enable=1, Macro0, CA PI delay=33
5524 08:06:10.453794
5525 08:06:10.457291 [CBTSetCACLKResult] CA Dly = 33
5526 08:06:10.457369 CS Dly: 4 (0~35)
5527 08:06:10.457431 ==
5528 08:06:10.460497 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 08:06:10.463641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 08:06:10.467299 ==
5531 08:06:10.470323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 08:06:10.477094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5533 08:06:10.480648 [CA 0] Center 36 (6~67) winsize 62
5534 08:06:10.484073 [CA 1] Center 36 (6~67) winsize 62
5535 08:06:10.487663 [CA 2] Center 33 (3~64) winsize 62
5536 08:06:10.490758 [CA 3] Center 33 (3~64) winsize 62
5537 08:06:10.494253 [CA 4] Center 33 (3~64) winsize 62
5538 08:06:10.498218 [CA 5] Center 32 (2~63) winsize 62
5539 08:06:10.498292
5540 08:06:10.501124 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5541 08:06:10.501200
5542 08:06:10.503883 [CATrainingPosCal] consider 2 rank data
5543 08:06:10.507504 u2DelayCellTimex100 = 270/100 ps
5544 08:06:10.511012 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5545 08:06:10.514250 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5546 08:06:10.517498 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 08:06:10.521176 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5548 08:06:10.524498 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5549 08:06:10.530928 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5550 08:06:10.531000
5551 08:06:10.534273 CA PerBit enable=1, Macro0, CA PI delay=33
5552 08:06:10.534347
5553 08:06:10.537561 [CBTSetCACLKResult] CA Dly = 33
5554 08:06:10.537652 CS Dly: 5 (0~38)
5555 08:06:10.537714
5556 08:06:10.540668 ----->DramcWriteLeveling(PI) begin...
5557 08:06:10.540747 ==
5558 08:06:10.544177 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 08:06:10.547183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 08:06:10.550895 ==
5561 08:06:10.550971 Write leveling (Byte 0): 26 => 26
5562 08:06:10.554031 Write leveling (Byte 1): 28 => 28
5563 08:06:10.557541 DramcWriteLeveling(PI) end<-----
5564 08:06:10.557611
5565 08:06:10.557671 ==
5566 08:06:10.560850 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 08:06:10.567159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 08:06:10.567234 ==
5569 08:06:10.567301 [Gating] SW mode calibration
5570 08:06:10.577287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 08:06:10.580954 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5572 08:06:10.584013 0 14 0 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
5573 08:06:10.590807 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 08:06:10.594008 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5575 08:06:10.597247 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 08:06:10.604094 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 08:06:10.607279 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 08:06:10.611077 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5579 08:06:10.617701 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5580 08:06:10.620695 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
5581 08:06:10.624091 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 08:06:10.631032 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 08:06:10.634004 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5584 08:06:10.637358 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5585 08:06:10.644285 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 08:06:10.647751 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 08:06:10.650673 0 15 28 | B1->B0 | 2c2c 2d2d | 0 0 | (0 0) (0 0)
5588 08:06:10.657478 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 08:06:10.661136 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 08:06:10.664193 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 08:06:10.667882 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 08:06:10.674137 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 08:06:10.677905 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 08:06:10.681436 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 08:06:10.687629 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 08:06:10.690683 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 08:06:10.694136 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 08:06:10.700588 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 08:06:10.704225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 08:06:10.707492 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 08:06:10.714550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 08:06:10.717402 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 08:06:10.720871 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 08:06:10.727150 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 08:06:10.731158 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 08:06:10.734509 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 08:06:10.740636 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 08:06:10.744049 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 08:06:10.747881 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 08:06:10.754227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 08:06:10.757803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5612 08:06:10.760671 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 08:06:10.764160 Total UI for P1: 0, mck2ui 16
5614 08:06:10.767160 best dqsien dly found for B0: ( 1, 2, 28)
5615 08:06:10.770617 Total UI for P1: 0, mck2ui 16
5616 08:06:10.773994 best dqsien dly found for B1: ( 1, 2, 28)
5617 08:06:10.777372 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5618 08:06:10.781006 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5619 08:06:10.781078
5620 08:06:10.784339 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5621 08:06:10.790528 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5622 08:06:10.790603 [Gating] SW calibration Done
5623 08:06:10.790667 ==
5624 08:06:10.794337 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 08:06:10.800980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 08:06:10.801064 ==
5627 08:06:10.801126 RX Vref Scan: 0
5628 08:06:10.801202
5629 08:06:10.804087 RX Vref 0 -> 0, step: 1
5630 08:06:10.804161
5631 08:06:10.807555 RX Delay -80 -> 252, step: 8
5632 08:06:10.811080 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5633 08:06:10.814289 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5634 08:06:10.817742 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5635 08:06:10.820785 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5636 08:06:10.824287 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5637 08:06:10.831274 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5638 08:06:10.834454 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5639 08:06:10.837775 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5640 08:06:10.840971 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5641 08:06:10.844488 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5642 08:06:10.847919 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5643 08:06:10.854377 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5644 08:06:10.857497 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5645 08:06:10.861358 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5646 08:06:10.864369 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5647 08:06:10.867799 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5648 08:06:10.867865 ==
5649 08:06:10.871400 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 08:06:10.877613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 08:06:10.877687 ==
5652 08:06:10.877748 DQS Delay:
5653 08:06:10.881076 DQS0 = 0, DQS1 = 0
5654 08:06:10.881141 DQM Delay:
5655 08:06:10.881199 DQM0 = 96, DQM1 = 88
5656 08:06:10.884444 DQ Delay:
5657 08:06:10.887659 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5658 08:06:10.891449 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5659 08:06:10.894099 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5660 08:06:10.898356 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5661 08:06:10.898431
5662 08:06:10.898492
5663 08:06:10.898548 ==
5664 08:06:10.901005 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 08:06:10.904522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 08:06:10.904590 ==
5667 08:06:10.904650
5668 08:06:10.904716
5669 08:06:10.908058 TX Vref Scan disable
5670 08:06:10.908128 == TX Byte 0 ==
5671 08:06:10.914681 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 08:06:10.917876 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 08:06:10.917956 == TX Byte 1 ==
5674 08:06:10.924440 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5675 08:06:10.927745 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5676 08:06:10.927814 ==
5677 08:06:10.931009 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 08:06:10.934355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 08:06:10.934430 ==
5680 08:06:10.934491
5681 08:06:10.934558
5682 08:06:10.937803 TX Vref Scan disable
5683 08:06:10.941204 == TX Byte 0 ==
5684 08:06:10.944814 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5685 08:06:10.947920 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5686 08:06:10.950923 == TX Byte 1 ==
5687 08:06:10.954306 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5688 08:06:10.957822 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5689 08:06:10.957889
5690 08:06:10.961681 [DATLAT]
5691 08:06:10.961748 Freq=933, CH1 RK0
5692 08:06:10.961807
5693 08:06:10.964527 DATLAT Default: 0xd
5694 08:06:10.964591 0, 0xFFFF, sum = 0
5695 08:06:10.968497 1, 0xFFFF, sum = 0
5696 08:06:10.968571 2, 0xFFFF, sum = 0
5697 08:06:10.971320 3, 0xFFFF, sum = 0
5698 08:06:10.971391 4, 0xFFFF, sum = 0
5699 08:06:10.974424 5, 0xFFFF, sum = 0
5700 08:06:10.974491 6, 0xFFFF, sum = 0
5701 08:06:10.978062 7, 0xFFFF, sum = 0
5702 08:06:10.978128 8, 0xFFFF, sum = 0
5703 08:06:10.981488 9, 0xFFFF, sum = 0
5704 08:06:10.981553 10, 0x0, sum = 1
5705 08:06:10.985339 11, 0x0, sum = 2
5706 08:06:10.985405 12, 0x0, sum = 3
5707 08:06:10.987960 13, 0x0, sum = 4
5708 08:06:10.988025 best_step = 11
5709 08:06:10.988102
5710 08:06:10.988192 ==
5711 08:06:10.991391 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 08:06:10.994674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 08:06:10.998422 ==
5714 08:06:10.998494 RX Vref Scan: 1
5715 08:06:10.998564
5716 08:06:11.001379 RX Vref 0 -> 0, step: 1
5717 08:06:11.001450
5718 08:06:11.004627 RX Delay -61 -> 252, step: 4
5719 08:06:11.004694
5720 08:06:11.008238 Set Vref, RX VrefLevel [Byte0]: 61
5721 08:06:11.008303 [Byte1]: 53
5722 08:06:11.013430
5723 08:06:11.013507 Final RX Vref Byte 0 = 61 to rank0
5724 08:06:11.016874 Final RX Vref Byte 1 = 53 to rank0
5725 08:06:11.019853 Final RX Vref Byte 0 = 61 to rank1
5726 08:06:11.023244 Final RX Vref Byte 1 = 53 to rank1==
5727 08:06:11.027017 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 08:06:11.030013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 08:06:11.033443 ==
5730 08:06:11.033511 DQS Delay:
5731 08:06:11.033579 DQS0 = 0, DQS1 = 0
5732 08:06:11.036918 DQM Delay:
5733 08:06:11.036992 DQM0 = 98, DQM1 = 90
5734 08:06:11.040223 DQ Delay:
5735 08:06:11.043553 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5736 08:06:11.043692 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5737 08:06:11.046675 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =86
5738 08:06:11.053365 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =94
5739 08:06:11.053449
5740 08:06:11.053512
5741 08:06:11.060087 [DQSOSCAuto] RK0, (LSB)MR18= 0x18f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5742 08:06:11.063330 CH1 RK0: MR19=504, MR18=18F4
5743 08:06:11.070026 CH1_RK0: MR19=0x504, MR18=0x18F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5744 08:06:11.070101
5745 08:06:11.073971 ----->DramcWriteLeveling(PI) begin...
5746 08:06:11.074055 ==
5747 08:06:11.077205 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 08:06:11.080232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 08:06:11.080313 ==
5750 08:06:11.083552 Write leveling (Byte 0): 27 => 27
5751 08:06:11.087129 Write leveling (Byte 1): 30 => 30
5752 08:06:11.090373 DramcWriteLeveling(PI) end<-----
5753 08:06:11.090457
5754 08:06:11.090524 ==
5755 08:06:11.093766 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 08:06:11.096770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 08:06:11.096842 ==
5758 08:06:11.100265 [Gating] SW mode calibration
5759 08:06:11.106984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5760 08:06:11.113434 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5761 08:06:11.117300 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5762 08:06:11.120096 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 08:06:11.126939 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 08:06:11.130480 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5765 08:06:11.133604 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 08:06:11.140318 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 08:06:11.143638 0 14 24 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
5768 08:06:11.147016 0 14 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
5769 08:06:11.154074 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 08:06:11.156901 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 08:06:11.160119 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 08:06:11.163530 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 08:06:11.170602 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 08:06:11.173966 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5775 08:06:11.177345 0 15 24 | B1->B0 | 2626 3636 | 0 1 | (1 1) (0 0)
5776 08:06:11.183535 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5777 08:06:11.187309 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 08:06:11.190964 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 08:06:11.197098 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 08:06:11.200904 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 08:06:11.204010 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 08:06:11.210670 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 08:06:11.213587 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5784 08:06:11.217162 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 08:06:11.224385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 08:06:11.227452 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 08:06:11.230610 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 08:06:11.234093 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 08:06:11.240547 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 08:06:11.244286 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 08:06:11.247138 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 08:06:11.254523 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 08:06:11.257588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 08:06:11.260633 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 08:06:11.267950 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 08:06:11.270632 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 08:06:11.274151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 08:06:11.280941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 08:06:11.284242 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5800 08:06:11.287494 Total UI for P1: 0, mck2ui 16
5801 08:06:11.290942 best dqsien dly found for B0: ( 1, 2, 22)
5802 08:06:11.294322 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 08:06:11.297230 Total UI for P1: 0, mck2ui 16
5804 08:06:11.300656 best dqsien dly found for B1: ( 1, 2, 24)
5805 08:06:11.304096 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5806 08:06:11.307779 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5807 08:06:11.307858
5808 08:06:11.311219 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5809 08:06:11.317783 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5810 08:06:11.317883 [Gating] SW calibration Done
5811 08:06:11.318021 ==
5812 08:06:11.320964 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 08:06:11.327703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 08:06:11.327784 ==
5815 08:06:11.327847 RX Vref Scan: 0
5816 08:06:11.327908
5817 08:06:11.331202 RX Vref 0 -> 0, step: 1
5818 08:06:11.331275
5819 08:06:11.334224 RX Delay -80 -> 252, step: 8
5820 08:06:11.337662 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5821 08:06:11.341339 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5822 08:06:11.344322 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5823 08:06:11.347357 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5824 08:06:11.350767 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5825 08:06:11.357441 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5826 08:06:11.360635 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5827 08:06:11.363924 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5828 08:06:11.367423 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5829 08:06:11.370707 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5830 08:06:11.377277 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5831 08:06:11.381010 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5832 08:06:11.384235 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5833 08:06:11.387474 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5834 08:06:11.390597 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5835 08:06:11.393952 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5836 08:06:11.394027 ==
5837 08:06:11.397562 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 08:06:11.403949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 08:06:11.404033 ==
5840 08:06:11.404099 DQS Delay:
5841 08:06:11.407248 DQS0 = 0, DQS1 = 0
5842 08:06:11.407325 DQM Delay:
5843 08:06:11.407387 DQM0 = 95, DQM1 = 89
5844 08:06:11.410677 DQ Delay:
5845 08:06:11.414537 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5846 08:06:11.417535 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5847 08:06:11.420619 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5848 08:06:11.424064 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5849 08:06:11.424138
5850 08:06:11.424207
5851 08:06:11.424267 ==
5852 08:06:11.427438 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 08:06:11.431244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 08:06:11.431336 ==
5855 08:06:11.431397
5856 08:06:11.431460
5857 08:06:11.434016 TX Vref Scan disable
5858 08:06:11.434136 == TX Byte 0 ==
5859 08:06:11.440521 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 08:06:11.444469 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 08:06:11.444546 == TX Byte 1 ==
5862 08:06:11.450609 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5863 08:06:11.454405 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5864 08:06:11.454501 ==
5865 08:06:11.457455 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 08:06:11.461114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 08:06:11.461183 ==
5868 08:06:11.461280
5869 08:06:11.464254
5870 08:06:11.464320 TX Vref Scan disable
5871 08:06:11.467857 == TX Byte 0 ==
5872 08:06:11.470684 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5873 08:06:11.474031 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5874 08:06:11.477526 == TX Byte 1 ==
5875 08:06:11.481231 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5876 08:06:11.484315 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5877 08:06:11.484384
5878 08:06:11.487265 [DATLAT]
5879 08:06:11.487333 Freq=933, CH1 RK1
5880 08:06:11.487461
5881 08:06:11.490552 DATLAT Default: 0xb
5882 08:06:11.490647 0, 0xFFFF, sum = 0
5883 08:06:11.493915 1, 0xFFFF, sum = 0
5884 08:06:11.493985 2, 0xFFFF, sum = 0
5885 08:06:11.497406 3, 0xFFFF, sum = 0
5886 08:06:11.497475 4, 0xFFFF, sum = 0
5887 08:06:11.500901 5, 0xFFFF, sum = 0
5888 08:06:11.500981 6, 0xFFFF, sum = 0
5889 08:06:11.504105 7, 0xFFFF, sum = 0
5890 08:06:11.504176 8, 0xFFFF, sum = 0
5891 08:06:11.507288 9, 0xFFFF, sum = 0
5892 08:06:11.507359 10, 0x0, sum = 1
5893 08:06:11.510864 11, 0x0, sum = 2
5894 08:06:11.510932 12, 0x0, sum = 3
5895 08:06:11.513974 13, 0x0, sum = 4
5896 08:06:11.514041 best_step = 11
5897 08:06:11.514098
5898 08:06:11.514163 ==
5899 08:06:11.517803 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 08:06:11.524555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 08:06:11.524632 ==
5902 08:06:11.524692 RX Vref Scan: 0
5903 08:06:11.524749
5904 08:06:11.527403 RX Vref 0 -> 0, step: 1
5905 08:06:11.527468
5906 08:06:11.531119 RX Delay -61 -> 252, step: 4
5907 08:06:11.534512 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5908 08:06:11.537666 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5909 08:06:11.544733 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5910 08:06:11.547542 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5911 08:06:11.551151 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5912 08:06:11.554293 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5913 08:06:11.557770 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5914 08:06:11.561231 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5915 08:06:11.564213 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5916 08:06:11.571324 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5917 08:06:11.574323 iDelay=195, Bit 10, Center 92 (-1 ~ 186) 188
5918 08:06:11.578184 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5919 08:06:11.580954 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5920 08:06:11.584603 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5921 08:06:11.587895 iDelay=195, Bit 14, Center 96 (3 ~ 190) 188
5922 08:06:11.594531 iDelay=195, Bit 15, Center 96 (3 ~ 190) 188
5923 08:06:11.594636 ==
5924 08:06:11.597906 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 08:06:11.600991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 08:06:11.601069 ==
5927 08:06:11.601129 DQS Delay:
5928 08:06:11.604414 DQS0 = 0, DQS1 = 0
5929 08:06:11.604482 DQM Delay:
5930 08:06:11.607823 DQM0 = 95, DQM1 = 90
5931 08:06:11.607889 DQ Delay:
5932 08:06:11.611021 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5933 08:06:11.614835 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5934 08:06:11.617994 DQ8 =82, DQ9 =80, DQ10 =92, DQ11 =82
5935 08:06:11.621155 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5936 08:06:11.621223
5937 08:06:11.621283
5938 08:06:11.628080 [DQSOSCAuto] RK1, (LSB)MR18= 0xc15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5939 08:06:11.631131 CH1 RK1: MR19=505, MR18=C15
5940 08:06:11.638174 CH1_RK1: MR19=0x505, MR18=0xC15, DQSOSC=415, MR23=63, INC=62, DEC=41
5941 08:06:11.641480 [RxdqsGatingPostProcess] freq 933
5942 08:06:11.647901 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 08:06:11.647982 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 08:06:11.651435 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 08:06:11.654534 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 08:06:11.657841 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 08:06:11.661321 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 08:06:11.664297 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 08:06:11.668100 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 08:06:11.671206 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 08:06:11.674558 Pre-setting of DQS Precalculation
5952 08:06:11.681047 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 08:06:11.687843 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 08:06:11.694612 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 08:06:11.694738
5956 08:06:11.694821
5957 08:06:11.698035 [Calibration Summary] 1866 Mbps
5958 08:06:11.698107 CH 0, Rank 0
5959 08:06:11.701471 SW Impedance : PASS
5960 08:06:11.701543 DUTY Scan : NO K
5961 08:06:11.704805 ZQ Calibration : PASS
5962 08:06:11.707865 Jitter Meter : NO K
5963 08:06:11.707933 CBT Training : PASS
5964 08:06:11.711349 Write leveling : PASS
5965 08:06:11.715021 RX DQS gating : PASS
5966 08:06:11.715095 RX DQ/DQS(RDDQC) : PASS
5967 08:06:11.717780 TX DQ/DQS : PASS
5968 08:06:11.721285 RX DATLAT : PASS
5969 08:06:11.721352 RX DQ/DQS(Engine): PASS
5970 08:06:11.724676 TX OE : NO K
5971 08:06:11.724774 All Pass.
5972 08:06:11.724869
5973 08:06:11.727789 CH 0, Rank 1
5974 08:06:11.727856 SW Impedance : PASS
5975 08:06:11.731176 DUTY Scan : NO K
5976 08:06:11.734526 ZQ Calibration : PASS
5977 08:06:11.734621 Jitter Meter : NO K
5978 08:06:11.738010 CBT Training : PASS
5979 08:06:11.741349 Write leveling : PASS
5980 08:06:11.741424 RX DQS gating : PASS
5981 08:06:11.744631 RX DQ/DQS(RDDQC) : PASS
5982 08:06:11.744700 TX DQ/DQS : PASS
5983 08:06:11.748680 RX DATLAT : PASS
5984 08:06:11.751096 RX DQ/DQS(Engine): PASS
5985 08:06:11.751172 TX OE : NO K
5986 08:06:11.754172 All Pass.
5987 08:06:11.754265
5988 08:06:11.754365 CH 1, Rank 0
5989 08:06:11.757974 SW Impedance : PASS
5990 08:06:11.758047 DUTY Scan : NO K
5991 08:06:11.761080 ZQ Calibration : PASS
5992 08:06:11.764737 Jitter Meter : NO K
5993 08:06:11.764814 CBT Training : PASS
5994 08:06:11.768009 Write leveling : PASS
5995 08:06:11.771521 RX DQS gating : PASS
5996 08:06:11.771602 RX DQ/DQS(RDDQC) : PASS
5997 08:06:11.774679 TX DQ/DQS : PASS
5998 08:06:11.777610 RX DATLAT : PASS
5999 08:06:11.777685 RX DQ/DQS(Engine): PASS
6000 08:06:11.780939 TX OE : NO K
6001 08:06:11.781008 All Pass.
6002 08:06:11.781073
6003 08:06:11.784614 CH 1, Rank 1
6004 08:06:11.784681 SW Impedance : PASS
6005 08:06:11.788160 DUTY Scan : NO K
6006 08:06:11.788231 ZQ Calibration : PASS
6007 08:06:11.791302 Jitter Meter : NO K
6008 08:06:11.794659 CBT Training : PASS
6009 08:06:11.794791 Write leveling : PASS
6010 08:06:11.798188 RX DQS gating : PASS
6011 08:06:11.801777 RX DQ/DQS(RDDQC) : PASS
6012 08:06:11.801849 TX DQ/DQS : PASS
6013 08:06:11.804527 RX DATLAT : PASS
6014 08:06:11.807737 RX DQ/DQS(Engine): PASS
6015 08:06:11.807811 TX OE : NO K
6016 08:06:11.811211 All Pass.
6017 08:06:11.811281
6018 08:06:11.811340 DramC Write-DBI off
6019 08:06:11.814628 PER_BANK_REFRESH: Hybrid Mode
6020 08:06:11.814746 TX_TRACKING: ON
6021 08:06:11.824753 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 08:06:11.827723 [FAST_K] Save calibration result to emmc
6023 08:06:11.831206 dramc_set_vcore_voltage set vcore to 650000
6024 08:06:11.834309 Read voltage for 400, 6
6025 08:06:11.834381 Vio18 = 0
6026 08:06:11.837867 Vcore = 650000
6027 08:06:11.837941 Vdram = 0
6028 08:06:11.838003 Vddq = 0
6029 08:06:11.838067 Vmddr = 0
6030 08:06:11.844692 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 08:06:11.851206 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 08:06:11.851280 MEM_TYPE=3, freq_sel=20
6033 08:06:11.854836 sv_algorithm_assistance_LP4_800
6034 08:06:11.857745 ============ PULL DRAM RESETB DOWN ============
6035 08:06:11.864450 ========== PULL DRAM RESETB DOWN end =========
6036 08:06:11.867834 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 08:06:11.871385 ===================================
6038 08:06:11.874637 LPDDR4 DRAM CONFIGURATION
6039 08:06:11.878329 ===================================
6040 08:06:11.878400 EX_ROW_EN[0] = 0x0
6041 08:06:11.881322 EX_ROW_EN[1] = 0x0
6042 08:06:11.881390 LP4Y_EN = 0x0
6043 08:06:11.885004 WORK_FSP = 0x0
6044 08:06:11.885084 WL = 0x2
6045 08:06:11.888190 RL = 0x2
6046 08:06:11.888259 BL = 0x2
6047 08:06:11.891335 RPST = 0x0
6048 08:06:11.891433 RD_PRE = 0x0
6049 08:06:11.894969 WR_PRE = 0x1
6050 08:06:11.895059 WR_PST = 0x0
6051 08:06:11.898050 DBI_WR = 0x0
6052 08:06:11.901378 DBI_RD = 0x0
6053 08:06:11.901447 OTF = 0x1
6054 08:06:11.904887 ===================================
6055 08:06:11.907959 ===================================
6056 08:06:11.908036 ANA top config
6057 08:06:11.911567 ===================================
6058 08:06:11.914988 DLL_ASYNC_EN = 0
6059 08:06:11.918050 ALL_SLAVE_EN = 1
6060 08:06:11.921936 NEW_RANK_MODE = 1
6061 08:06:11.922007 DLL_IDLE_MODE = 1
6062 08:06:11.924664 LP45_APHY_COMB_EN = 1
6063 08:06:11.928685 TX_ODT_DIS = 1
6064 08:06:11.931499 NEW_8X_MODE = 1
6065 08:06:11.934902 ===================================
6066 08:06:11.938125 ===================================
6067 08:06:11.941852 data_rate = 800
6068 08:06:11.941922 CKR = 1
6069 08:06:11.945032 DQ_P2S_RATIO = 4
6070 08:06:11.947962 ===================================
6071 08:06:11.951220 CA_P2S_RATIO = 4
6072 08:06:11.954600 DQ_CA_OPEN = 0
6073 08:06:11.958111 DQ_SEMI_OPEN = 1
6074 08:06:11.961524 CA_SEMI_OPEN = 1
6075 08:06:11.961600 CA_FULL_RATE = 0
6076 08:06:11.964963 DQ_CKDIV4_EN = 0
6077 08:06:11.968404 CA_CKDIV4_EN = 1
6078 08:06:11.971448 CA_PREDIV_EN = 0
6079 08:06:11.975092 PH8_DLY = 0
6080 08:06:11.978145 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 08:06:11.978243 DQ_AAMCK_DIV = 0
6082 08:06:11.981361 CA_AAMCK_DIV = 0
6083 08:06:11.985156 CA_ADMCK_DIV = 4
6084 08:06:11.988214 DQ_TRACK_CA_EN = 0
6085 08:06:11.991765 CA_PICK = 800
6086 08:06:11.994967 CA_MCKIO = 400
6087 08:06:11.995071 MCKIO_SEMI = 400
6088 08:06:11.998562 PLL_FREQ = 3016
6089 08:06:12.001626 DQ_UI_PI_RATIO = 32
6090 08:06:12.005014 CA_UI_PI_RATIO = 32
6091 08:06:12.008391 ===================================
6092 08:06:12.011999 ===================================
6093 08:06:12.015330 memory_type:LPDDR4
6094 08:06:12.015400 GP_NUM : 10
6095 08:06:12.018365 SRAM_EN : 1
6096 08:06:12.022261 MD32_EN : 0
6097 08:06:12.025473 ===================================
6098 08:06:12.025544 [ANA_INIT] >>>>>>>>>>>>>>
6099 08:06:12.028451 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 08:06:12.031976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 08:06:12.035501 ===================================
6102 08:06:12.038509 data_rate = 800,PCW = 0X7400
6103 08:06:12.041849 ===================================
6104 08:06:12.045175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 08:06:12.051807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 08:06:12.062166 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 08:06:12.065643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 08:06:12.068911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 08:06:12.071829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 08:06:12.075364 [ANA_INIT] flow start
6111 08:06:12.078530 [ANA_INIT] PLL >>>>>>>>
6112 08:06:12.078600 [ANA_INIT] PLL <<<<<<<<
6113 08:06:12.082431 [ANA_INIT] MIDPI >>>>>>>>
6114 08:06:12.085306 [ANA_INIT] MIDPI <<<<<<<<
6115 08:06:12.085377 [ANA_INIT] DLL >>>>>>>>
6116 08:06:12.088631 [ANA_INIT] flow end
6117 08:06:12.092184 ============ LP4 DIFF to SE enter ============
6118 08:06:12.098672 ============ LP4 DIFF to SE exit ============
6119 08:06:12.098806 [ANA_INIT] <<<<<<<<<<<<<
6120 08:06:12.102240 [Flow] Enable top DCM control >>>>>
6121 08:06:12.105793 [Flow] Enable top DCM control <<<<<
6122 08:06:12.108863 Enable DLL master slave shuffle
6123 08:06:12.115411 ==============================================================
6124 08:06:12.115567 Gating Mode config
6125 08:06:12.121924 ==============================================================
6126 08:06:12.125260 Config description:
6127 08:06:12.131903 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 08:06:12.139203 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 08:06:12.145663 SELPH_MODE 0: By rank 1: By Phase
6130 08:06:12.148635 ==============================================================
6131 08:06:12.151897 GAT_TRACK_EN = 0
6132 08:06:12.155279 RX_GATING_MODE = 2
6133 08:06:12.158832 RX_GATING_TRACK_MODE = 2
6134 08:06:12.162318 SELPH_MODE = 1
6135 08:06:12.165545 PICG_EARLY_EN = 1
6136 08:06:12.168854 VALID_LAT_VALUE = 1
6137 08:06:12.175256 ==============================================================
6138 08:06:12.179074 Enter into Gating configuration >>>>
6139 08:06:12.182039 Exit from Gating configuration <<<<
6140 08:06:12.182118 Enter into DVFS_PRE_config >>>>>
6141 08:06:12.195716 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 08:06:12.199084 Exit from DVFS_PRE_config <<<<<
6143 08:06:12.202315 Enter into PICG configuration >>>>
6144 08:06:12.205670 Exit from PICG configuration <<<<
6145 08:06:12.205750 [RX_INPUT] configuration >>>>>
6146 08:06:12.209414 [RX_INPUT] configuration <<<<<
6147 08:06:12.215772 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 08:06:12.219448 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 08:06:12.225825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 08:06:12.232832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 08:06:12.239065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 08:06:12.246027 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 08:06:12.249359 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 08:06:12.252846 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 08:06:12.256119 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 08:06:12.262485 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 08:06:12.266164 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 08:06:12.269144 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 08:06:12.272567 ===================================
6160 08:06:12.275960 LPDDR4 DRAM CONFIGURATION
6161 08:06:12.279604 ===================================
6162 08:06:12.279686 EX_ROW_EN[0] = 0x0
6163 08:06:12.282523 EX_ROW_EN[1] = 0x0
6164 08:06:12.285714 LP4Y_EN = 0x0
6165 08:06:12.285799 WORK_FSP = 0x0
6166 08:06:12.289367 WL = 0x2
6167 08:06:12.289448 RL = 0x2
6168 08:06:12.292825 BL = 0x2
6169 08:06:12.292906 RPST = 0x0
6170 08:06:12.295990 RD_PRE = 0x0
6171 08:06:12.296071 WR_PRE = 0x1
6172 08:06:12.299276 WR_PST = 0x0
6173 08:06:12.299356 DBI_WR = 0x0
6174 08:06:12.302456 DBI_RD = 0x0
6175 08:06:12.302535 OTF = 0x1
6176 08:06:12.305966 ===================================
6177 08:06:12.309715 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 08:06:12.316205 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 08:06:12.319123 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 08:06:12.322478 ===================================
6181 08:06:12.326027 LPDDR4 DRAM CONFIGURATION
6182 08:06:12.329230 ===================================
6183 08:06:12.329310 EX_ROW_EN[0] = 0x10
6184 08:06:12.332962 EX_ROW_EN[1] = 0x0
6185 08:06:12.333041 LP4Y_EN = 0x0
6186 08:06:12.335749 WORK_FSP = 0x0
6187 08:06:12.339440 WL = 0x2
6188 08:06:12.339519 RL = 0x2
6189 08:06:12.342442 BL = 0x2
6190 08:06:12.342540 RPST = 0x0
6191 08:06:12.346004 RD_PRE = 0x0
6192 08:06:12.346084 WR_PRE = 0x1
6193 08:06:12.349517 WR_PST = 0x0
6194 08:06:12.349597 DBI_WR = 0x0
6195 08:06:12.352642 DBI_RD = 0x0
6196 08:06:12.352722 OTF = 0x1
6197 08:06:12.355885 ===================================
6198 08:06:12.362364 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 08:06:12.367033 nWR fixed to 30
6200 08:06:12.369742 [ModeRegInit_LP4] CH0 RK0
6201 08:06:12.369843 [ModeRegInit_LP4] CH0 RK1
6202 08:06:12.373484 [ModeRegInit_LP4] CH1 RK0
6203 08:06:12.376494 [ModeRegInit_LP4] CH1 RK1
6204 08:06:12.376575 match AC timing 19
6205 08:06:12.382875 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 08:06:12.386670 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 08:06:12.389898 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 08:06:12.396658 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 08:06:12.399829 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 08:06:12.399910 ==
6211 08:06:12.403561 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 08:06:12.407057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 08:06:12.407138 ==
6214 08:06:12.413952 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 08:06:12.420097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6216 08:06:12.423452 [CA 0] Center 36 (8~64) winsize 57
6217 08:06:12.423533 [CA 1] Center 36 (8~64) winsize 57
6218 08:06:12.426948 [CA 2] Center 36 (8~64) winsize 57
6219 08:06:12.430198 [CA 3] Center 36 (8~64) winsize 57
6220 08:06:12.433341 [CA 4] Center 36 (8~64) winsize 57
6221 08:06:12.436679 [CA 5] Center 36 (8~64) winsize 57
6222 08:06:12.436760
6223 08:06:12.440314 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6224 08:06:12.440395
6225 08:06:12.443910 [CATrainingPosCal] consider 1 rank data
6226 08:06:12.446661 u2DelayCellTimex100 = 270/100 ps
6227 08:06:12.450263 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 08:06:12.454064 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 08:06:12.460047 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 08:06:12.463445 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 08:06:12.466880 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 08:06:12.470072 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 08:06:12.470153
6234 08:06:12.473354 CA PerBit enable=1, Macro0, CA PI delay=36
6235 08:06:12.473438
6236 08:06:12.476756 [CBTSetCACLKResult] CA Dly = 36
6237 08:06:12.476837 CS Dly: 1 (0~32)
6238 08:06:12.480029 ==
6239 08:06:12.480141 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 08:06:12.486587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 08:06:12.486667 ==
6242 08:06:12.490195 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 08:06:12.496593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 08:06:12.500099 [CA 0] Center 36 (8~64) winsize 57
6245 08:06:12.503361 [CA 1] Center 36 (8~64) winsize 57
6246 08:06:12.507125 [CA 2] Center 36 (8~64) winsize 57
6247 08:06:12.510128 [CA 3] Center 36 (8~64) winsize 57
6248 08:06:12.513405 [CA 4] Center 36 (8~64) winsize 57
6249 08:06:12.516913 [CA 5] Center 36 (8~64) winsize 57
6250 08:06:12.516993
6251 08:06:12.519938 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 08:06:12.520018
6253 08:06:12.523503 [CATrainingPosCal] consider 2 rank data
6254 08:06:12.526850 u2DelayCellTimex100 = 270/100 ps
6255 08:06:12.530053 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 08:06:12.533462 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 08:06:12.536851 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 08:06:12.539990 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 08:06:12.543600 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 08:06:12.546782 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 08:06:12.550222
6262 08:06:12.553212 CA PerBit enable=1, Macro0, CA PI delay=36
6263 08:06:12.553292
6264 08:06:12.557135 [CBTSetCACLKResult] CA Dly = 36
6265 08:06:12.557215 CS Dly: 1 (0~32)
6266 08:06:12.557279
6267 08:06:12.560145 ----->DramcWriteLeveling(PI) begin...
6268 08:06:12.560226 ==
6269 08:06:12.563770 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 08:06:12.566674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 08:06:12.566798 ==
6272 08:06:12.570530 Write leveling (Byte 0): 40 => 8
6273 08:06:12.573630 Write leveling (Byte 1): 32 => 0
6274 08:06:12.576632 DramcWriteLeveling(PI) end<-----
6275 08:06:12.576712
6276 08:06:12.576774 ==
6277 08:06:12.580491 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 08:06:12.583463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 08:06:12.586975 ==
6280 08:06:12.587055 [Gating] SW mode calibration
6281 08:06:12.596650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 08:06:12.599884 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 08:06:12.603280 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 08:06:12.609972 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 08:06:12.614028 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 08:06:12.616755 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 08:06:12.623803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 08:06:12.627086 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 08:06:12.630151 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 08:06:12.636791 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 08:06:12.640280 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 08:06:12.643582 Total UI for P1: 0, mck2ui 16
6293 08:06:12.646907 best dqsien dly found for B0: ( 0, 14, 24)
6294 08:06:12.650238 Total UI for P1: 0, mck2ui 16
6295 08:06:12.653375 best dqsien dly found for B1: ( 0, 14, 24)
6296 08:06:12.656612 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 08:06:12.660060 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 08:06:12.660140
6299 08:06:12.663293 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 08:06:12.667121 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 08:06:12.670496 [Gating] SW calibration Done
6302 08:06:12.670576 ==
6303 08:06:12.673613 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 08:06:12.676738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 08:06:12.676818 ==
6306 08:06:12.679868 RX Vref Scan: 0
6307 08:06:12.679947
6308 08:06:12.683554 RX Vref 0 -> 0, step: 1
6309 08:06:12.683634
6310 08:06:12.683696 RX Delay -410 -> 252, step: 16
6311 08:06:12.690232 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6312 08:06:12.694141 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6313 08:06:12.697336 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6314 08:06:12.700642 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6315 08:06:12.706876 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6316 08:06:12.710391 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6317 08:06:12.713727 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6318 08:06:12.717133 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6319 08:06:12.723422 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6320 08:06:12.727266 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6321 08:06:12.730221 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6322 08:06:12.733765 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6323 08:06:12.741115 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6324 08:06:12.743788 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6325 08:06:12.747075 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6326 08:06:12.750120 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6327 08:06:12.753517 ==
6328 08:06:12.756767 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 08:06:12.760582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 08:06:12.760687 ==
6331 08:06:12.760780 DQS Delay:
6332 08:06:12.763589 DQS0 = 35, DQS1 = 51
6333 08:06:12.763669 DQM Delay:
6334 08:06:12.766690 DQM0 = 7, DQM1 = 10
6335 08:06:12.766816 DQ Delay:
6336 08:06:12.770228 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6337 08:06:12.773964 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6338 08:06:12.777290 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6339 08:06:12.780993 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6340 08:06:12.781072
6341 08:06:12.781134
6342 08:06:12.781192 ==
6343 08:06:12.783812 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 08:06:12.787445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 08:06:12.787525 ==
6346 08:06:12.787588
6347 08:06:12.787647
6348 08:06:12.790397 TX Vref Scan disable
6349 08:06:12.790476 == TX Byte 0 ==
6350 08:06:12.797185 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 08:06:12.800642 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 08:06:12.800721 == TX Byte 1 ==
6353 08:06:12.803769 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6354 08:06:12.810519 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6355 08:06:12.810599 ==
6356 08:06:12.813788 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 08:06:12.817592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 08:06:12.817671 ==
6359 08:06:12.817734
6360 08:06:12.817790
6361 08:06:12.820614 TX Vref Scan disable
6362 08:06:12.820693 == TX Byte 0 ==
6363 08:06:12.827383 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 08:06:12.830616 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 08:06:12.830744 == TX Byte 1 ==
6366 08:06:12.834357 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6367 08:06:12.840465 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6368 08:06:12.840544
6369 08:06:12.840607 [DATLAT]
6370 08:06:12.844312 Freq=400, CH0 RK0
6371 08:06:12.844396
6372 08:06:12.844458 DATLAT Default: 0xf
6373 08:06:12.847310 0, 0xFFFF, sum = 0
6374 08:06:12.847397 1, 0xFFFF, sum = 0
6375 08:06:12.850924 2, 0xFFFF, sum = 0
6376 08:06:12.851004 3, 0xFFFF, sum = 0
6377 08:06:12.853968 4, 0xFFFF, sum = 0
6378 08:06:12.854075 5, 0xFFFF, sum = 0
6379 08:06:12.857551 6, 0xFFFF, sum = 0
6380 08:06:12.857632 7, 0xFFFF, sum = 0
6381 08:06:12.860678 8, 0xFFFF, sum = 0
6382 08:06:12.860758 9, 0xFFFF, sum = 0
6383 08:06:12.864055 10, 0xFFFF, sum = 0
6384 08:06:12.864155 11, 0xFFFF, sum = 0
6385 08:06:12.867367 12, 0xFFFF, sum = 0
6386 08:06:12.867448 13, 0x0, sum = 1
6387 08:06:12.870879 14, 0x0, sum = 2
6388 08:06:12.870960 15, 0x0, sum = 3
6389 08:06:12.873950 16, 0x0, sum = 4
6390 08:06:12.874031 best_step = 14
6391 08:06:12.874092
6392 08:06:12.874150 ==
6393 08:06:12.877481 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 08:06:12.883865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 08:06:12.883945 ==
6396 08:06:12.884008 RX Vref Scan: 1
6397 08:06:12.884067
6398 08:06:12.887366 RX Vref 0 -> 0, step: 1
6399 08:06:12.887445
6400 08:06:12.890804 RX Delay -343 -> 252, step: 8
6401 08:06:12.890886
6402 08:06:12.893992 Set Vref, RX VrefLevel [Byte0]: 56
6403 08:06:12.897317 [Byte1]: 50
6404 08:06:12.897396
6405 08:06:12.900551 Final RX Vref Byte 0 = 56 to rank0
6406 08:06:12.904109 Final RX Vref Byte 1 = 50 to rank0
6407 08:06:12.907477 Final RX Vref Byte 0 = 56 to rank1
6408 08:06:12.911115 Final RX Vref Byte 1 = 50 to rank1==
6409 08:06:12.913863 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 08:06:12.917107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 08:06:12.920379 ==
6412 08:06:12.920459 DQS Delay:
6413 08:06:12.920523 DQS0 = 44, DQS1 = 60
6414 08:06:12.923812 DQM Delay:
6415 08:06:12.923892 DQM0 = 11, DQM1 = 14
6416 08:06:12.926930 DQ Delay:
6417 08:06:12.927011 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6418 08:06:12.931112 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6419 08:06:12.933830 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6420 08:06:12.937530 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6421 08:06:12.937610
6422 08:06:12.937674
6423 08:06:12.947137 [DQSOSCAuto] RK0, (LSB)MR18= 0x8857, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6424 08:06:12.950531 CH0 RK0: MR19=C0C, MR18=8857
6425 08:06:12.956810 CH0_RK0: MR19=0xC0C, MR18=0x8857, DQSOSC=392, MR23=63, INC=384, DEC=256
6426 08:06:12.956890 ==
6427 08:06:12.960736 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 08:06:12.963717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 08:06:12.963798 ==
6430 08:06:12.967405 [Gating] SW mode calibration
6431 08:06:12.974043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 08:06:12.977033 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 08:06:12.983956 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 08:06:12.987217 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 08:06:12.990506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 08:06:12.997391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 08:06:13.000602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 08:06:13.003871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 08:06:13.010483 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 08:06:13.013875 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 08:06:13.017307 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 08:06:13.020508 Total UI for P1: 0, mck2ui 16
6443 08:06:13.023910 best dqsien dly found for B0: ( 0, 14, 24)
6444 08:06:13.027772 Total UI for P1: 0, mck2ui 16
6445 08:06:13.030278 best dqsien dly found for B1: ( 0, 14, 24)
6446 08:06:13.034416 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 08:06:13.037348 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 08:06:13.037428
6449 08:06:13.040702 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 08:06:13.047123 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 08:06:13.047205 [Gating] SW calibration Done
6452 08:06:13.047270 ==
6453 08:06:13.050569 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 08:06:13.057262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 08:06:13.057342 ==
6456 08:06:13.057407 RX Vref Scan: 0
6457 08:06:13.057466
6458 08:06:13.060314 RX Vref 0 -> 0, step: 1
6459 08:06:13.060394
6460 08:06:13.063798 RX Delay -410 -> 252, step: 16
6461 08:06:13.067330 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6462 08:06:13.070641 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6463 08:06:13.077689 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6464 08:06:13.080903 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6465 08:06:13.083691 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6466 08:06:13.087378 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6467 08:06:13.094008 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6468 08:06:13.097506 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6469 08:06:13.100468 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6470 08:06:13.103851 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6471 08:06:13.110451 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6472 08:06:13.113980 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6473 08:06:13.117064 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6474 08:06:13.120891 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6475 08:06:13.127522 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6476 08:06:13.130920 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6477 08:06:13.131001 ==
6478 08:06:13.134074 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 08:06:13.137069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 08:06:13.137150 ==
6481 08:06:13.140550 DQS Delay:
6482 08:06:13.140630 DQS0 = 35, DQS1 = 51
6483 08:06:13.140693 DQM Delay:
6484 08:06:13.144252 DQM0 = 4, DQM1 = 10
6485 08:06:13.144332 DQ Delay:
6486 08:06:13.147459 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6487 08:06:13.150889 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6488 08:06:13.153835 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6489 08:06:13.157241 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6490 08:06:13.157322
6491 08:06:13.157384
6492 08:06:13.157443 ==
6493 08:06:13.161041 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 08:06:13.164092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 08:06:13.164174 ==
6496 08:06:13.167628
6497 08:06:13.167708
6498 08:06:13.167788 TX Vref Scan disable
6499 08:06:13.170494 == TX Byte 0 ==
6500 08:06:13.174612 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6501 08:06:13.177329 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6502 08:06:13.180838 == TX Byte 1 ==
6503 08:06:13.183930 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6504 08:06:13.187443 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6505 08:06:13.187526 ==
6506 08:06:13.190552 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 08:06:13.194092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 08:06:13.194198 ==
6509 08:06:13.194292
6510 08:06:13.197143
6511 08:06:13.197223 TX Vref Scan disable
6512 08:06:13.200794 == TX Byte 0 ==
6513 08:06:13.204253 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6514 08:06:13.207296 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6515 08:06:13.210942 == TX Byte 1 ==
6516 08:06:13.214360 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6517 08:06:13.217242 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6518 08:06:13.217322
6519 08:06:13.217403 [DATLAT]
6520 08:06:13.220577 Freq=400, CH0 RK1
6521 08:06:13.220674
6522 08:06:13.220753 DATLAT Default: 0xe
6523 08:06:13.224264 0, 0xFFFF, sum = 0
6524 08:06:13.224345 1, 0xFFFF, sum = 0
6525 08:06:13.227343 2, 0xFFFF, sum = 0
6526 08:06:13.227424 3, 0xFFFF, sum = 0
6527 08:06:13.230648 4, 0xFFFF, sum = 0
6528 08:06:13.230786 5, 0xFFFF, sum = 0
6529 08:06:13.234538 6, 0xFFFF, sum = 0
6530 08:06:13.234635 7, 0xFFFF, sum = 0
6531 08:06:13.237367 8, 0xFFFF, sum = 0
6532 08:06:13.241514 9, 0xFFFF, sum = 0
6533 08:06:13.241595 10, 0xFFFF, sum = 0
6534 08:06:13.244237 11, 0xFFFF, sum = 0
6535 08:06:13.244319 12, 0xFFFF, sum = 0
6536 08:06:13.247563 13, 0x0, sum = 1
6537 08:06:13.247644 14, 0x0, sum = 2
6538 08:06:13.250926 15, 0x0, sum = 3
6539 08:06:13.251007 16, 0x0, sum = 4
6540 08:06:13.251072 best_step = 14
6541 08:06:13.251154
6542 08:06:13.254410 ==
6543 08:06:13.257547 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 08:06:13.260735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 08:06:13.260815 ==
6546 08:06:13.260878 RX Vref Scan: 0
6547 08:06:13.260937
6548 08:06:13.264239 RX Vref 0 -> 0, step: 1
6549 08:06:13.264319
6550 08:06:13.267908 RX Delay -343 -> 252, step: 8
6551 08:06:13.274486 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6552 08:06:13.277513 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6553 08:06:13.281172 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6554 08:06:13.284851 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6555 08:06:13.290958 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6556 08:06:13.294880 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6557 08:06:13.297815 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6558 08:06:13.301516 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6559 08:06:13.307797 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6560 08:06:13.311521 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6561 08:06:13.314641 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6562 08:06:13.317811 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6563 08:06:13.325054 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6564 08:06:13.328036 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6565 08:06:13.331256 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6566 08:06:13.334561 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6567 08:06:13.338169 ==
6568 08:06:13.338249 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 08:06:13.344455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 08:06:13.344554 ==
6571 08:06:13.344633 DQS Delay:
6572 08:06:13.347907 DQS0 = 48, DQS1 = 60
6573 08:06:13.347988 DQM Delay:
6574 08:06:13.351181 DQM0 = 14, DQM1 = 13
6575 08:06:13.351264 DQ Delay:
6576 08:06:13.354596 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6577 08:06:13.358144 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6578 08:06:13.361567 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6579 08:06:13.364854 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6580 08:06:13.364934
6581 08:06:13.364997
6582 08:06:13.371842 [DQSOSCAuto] RK1, (LSB)MR18= 0x9e72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6583 08:06:13.375068 CH0 RK1: MR19=C0C, MR18=9E72
6584 08:06:13.381835 CH0_RK1: MR19=0xC0C, MR18=0x9E72, DQSOSC=390, MR23=63, INC=388, DEC=258
6585 08:06:13.384887 [RxdqsGatingPostProcess] freq 400
6586 08:06:13.388718 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 08:06:13.391747 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 08:06:13.394908 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 08:06:13.398424 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 08:06:13.402096 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 08:06:13.405026 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 08:06:13.408521 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 08:06:13.411726 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 08:06:13.414859 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 08:06:13.418452 Pre-setting of DQS Precalculation
6596 08:06:13.421569 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 08:06:13.421650 ==
6598 08:06:13.425020 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 08:06:13.431845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 08:06:13.431926 ==
6601 08:06:13.435120 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 08:06:13.441532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6603 08:06:13.444974 [CA 0] Center 36 (8~64) winsize 57
6604 08:06:13.448442 [CA 1] Center 36 (8~64) winsize 57
6605 08:06:13.451983 [CA 2] Center 36 (8~64) winsize 57
6606 08:06:13.455403 [CA 3] Center 36 (8~64) winsize 57
6607 08:06:13.458381 [CA 4] Center 36 (8~64) winsize 57
6608 08:06:13.461951 [CA 5] Center 36 (8~64) winsize 57
6609 08:06:13.462031
6610 08:06:13.465428 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6611 08:06:13.465508
6612 08:06:13.468678 [CATrainingPosCal] consider 1 rank data
6613 08:06:13.471933 u2DelayCellTimex100 = 270/100 ps
6614 08:06:13.475290 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 08:06:13.478611 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 08:06:13.481783 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 08:06:13.485194 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 08:06:13.488402 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 08:06:13.491888 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 08:06:13.491969
6621 08:06:13.494878 CA PerBit enable=1, Macro0, CA PI delay=36
6622 08:06:13.498473
6623 08:06:13.498594 [CBTSetCACLKResult] CA Dly = 36
6624 08:06:13.502224 CS Dly: 1 (0~32)
6625 08:06:13.502305 ==
6626 08:06:13.504813 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 08:06:13.508729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 08:06:13.508809 ==
6629 08:06:13.515056 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 08:06:13.521669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 08:06:13.524990 [CA 0] Center 36 (8~64) winsize 57
6632 08:06:13.525070 [CA 1] Center 36 (8~64) winsize 57
6633 08:06:13.528616 [CA 2] Center 36 (8~64) winsize 57
6634 08:06:13.531735 [CA 3] Center 36 (8~64) winsize 57
6635 08:06:13.535524 [CA 4] Center 36 (8~64) winsize 57
6636 08:06:13.538471 [CA 5] Center 36 (8~64) winsize 57
6637 08:06:13.538551
6638 08:06:13.542179 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 08:06:13.542259
6640 08:06:13.545287 [CATrainingPosCal] consider 2 rank data
6641 08:06:13.548420 u2DelayCellTimex100 = 270/100 ps
6642 08:06:13.551933 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 08:06:13.558502 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 08:06:13.561813 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 08:06:13.565109 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 08:06:13.568534 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 08:06:13.572519 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 08:06:13.572600
6649 08:06:13.575282 CA PerBit enable=1, Macro0, CA PI delay=36
6650 08:06:13.575363
6651 08:06:13.578433 [CBTSetCACLKResult] CA Dly = 36
6652 08:06:13.578514 CS Dly: 1 (0~32)
6653 08:06:13.578583
6654 08:06:13.581894 ----->DramcWriteLeveling(PI) begin...
6655 08:06:13.585010 ==
6656 08:06:13.588636 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 08:06:13.591902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 08:06:13.591983 ==
6659 08:06:13.595540 Write leveling (Byte 0): 40 => 8
6660 08:06:13.598484 Write leveling (Byte 1): 40 => 8
6661 08:06:13.602073 DramcWriteLeveling(PI) end<-----
6662 08:06:13.602153
6663 08:06:13.602216 ==
6664 08:06:13.605138 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 08:06:13.608452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 08:06:13.608532 ==
6667 08:06:13.611837 [Gating] SW mode calibration
6668 08:06:13.618642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 08:06:13.621833 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 08:06:13.628298 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 08:06:13.631925 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 08:06:13.635227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 08:06:13.641883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 08:06:13.645428 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 08:06:13.648625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 08:06:13.655940 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 08:06:13.658556 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 08:06:13.662035 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 08:06:13.665349 Total UI for P1: 0, mck2ui 16
6680 08:06:13.668590 best dqsien dly found for B0: ( 0, 14, 24)
6681 08:06:13.672121 Total UI for P1: 0, mck2ui 16
6682 08:06:13.675704 best dqsien dly found for B1: ( 0, 14, 24)
6683 08:06:13.679042 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 08:06:13.682296 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 08:06:13.682376
6686 08:06:13.685488 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 08:06:13.692076 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 08:06:13.692156 [Gating] SW calibration Done
6689 08:06:13.692219 ==
6690 08:06:13.695739 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 08:06:13.702476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 08:06:13.702557 ==
6693 08:06:13.702621 RX Vref Scan: 0
6694 08:06:13.702680
6695 08:06:13.705540 RX Vref 0 -> 0, step: 1
6696 08:06:13.705620
6697 08:06:13.708689 RX Delay -410 -> 252, step: 16
6698 08:06:13.712462 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6699 08:06:13.716142 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6700 08:06:13.722389 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6701 08:06:13.726157 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6702 08:06:13.729252 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6703 08:06:13.732115 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6704 08:06:13.735654 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6705 08:06:13.742269 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6706 08:06:13.745364 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6707 08:06:13.749087 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6708 08:06:13.755491 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6709 08:06:13.758860 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6710 08:06:13.762102 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6711 08:06:13.765349 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6712 08:06:13.772117 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6713 08:06:13.775238 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6714 08:06:13.775318 ==
6715 08:06:13.778521 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 08:06:13.782080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 08:06:13.782161 ==
6718 08:06:13.785791 DQS Delay:
6719 08:06:13.785897 DQS0 = 51, DQS1 = 59
6720 08:06:13.785988 DQM Delay:
6721 08:06:13.789077 DQM0 = 19, DQM1 = 16
6722 08:06:13.789158 DQ Delay:
6723 08:06:13.792159 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6724 08:06:13.795359 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6725 08:06:13.799187 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6726 08:06:13.802747 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6727 08:06:13.802844
6728 08:06:13.802907
6729 08:06:13.802966 ==
6730 08:06:13.805349 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 08:06:13.812150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 08:06:13.812245 ==
6733 08:06:13.812308
6734 08:06:13.812366
6735 08:06:13.812422 TX Vref Scan disable
6736 08:06:13.815324 == TX Byte 0 ==
6737 08:06:13.818635 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 08:06:13.822297 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 08:06:13.825547 == TX Byte 1 ==
6740 08:06:13.828952 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 08:06:13.832513 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 08:06:13.832593 ==
6743 08:06:13.835420 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 08:06:13.842511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 08:06:13.842617 ==
6746 08:06:13.842708
6747 08:06:13.842818
6748 08:06:13.842907 TX Vref Scan disable
6749 08:06:13.845866 == TX Byte 0 ==
6750 08:06:13.849149 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 08:06:13.852559 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 08:06:13.855957 == TX Byte 1 ==
6753 08:06:13.859353 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 08:06:13.862607 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 08:06:13.862715
6756 08:06:13.865417 [DATLAT]
6757 08:06:13.865497 Freq=400, CH1 RK0
6758 08:06:13.865561
6759 08:06:13.868736 DATLAT Default: 0xf
6760 08:06:13.868820 0, 0xFFFF, sum = 0
6761 08:06:13.872103 1, 0xFFFF, sum = 0
6762 08:06:13.872185 2, 0xFFFF, sum = 0
6763 08:06:13.875766 3, 0xFFFF, sum = 0
6764 08:06:13.875848 4, 0xFFFF, sum = 0
6765 08:06:13.879112 5, 0xFFFF, sum = 0
6766 08:06:13.879193 6, 0xFFFF, sum = 0
6767 08:06:13.882175 7, 0xFFFF, sum = 0
6768 08:06:13.882256 8, 0xFFFF, sum = 0
6769 08:06:13.885719 9, 0xFFFF, sum = 0
6770 08:06:13.885800 10, 0xFFFF, sum = 0
6771 08:06:13.888723 11, 0xFFFF, sum = 0
6772 08:06:13.888805 12, 0xFFFF, sum = 0
6773 08:06:13.892219 13, 0x0, sum = 1
6774 08:06:13.892300 14, 0x0, sum = 2
6775 08:06:13.896153 15, 0x0, sum = 3
6776 08:06:13.896235 16, 0x0, sum = 4
6777 08:06:13.898764 best_step = 14
6778 08:06:13.898845
6779 08:06:13.898908 ==
6780 08:06:13.902209 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 08:06:13.905733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 08:06:13.905814 ==
6783 08:06:13.909194 RX Vref Scan: 1
6784 08:06:13.909314
6785 08:06:13.909377 RX Vref 0 -> 0, step: 1
6786 08:06:13.909437
6787 08:06:13.915649 RX Delay -359 -> 252, step: 8
6788 08:06:13.915733
6789 08:06:13.915799 Set Vref, RX VrefLevel [Byte0]: 61
6790 08:06:13.919412 [Byte1]: 53
6791 08:06:13.923641
6792 08:06:13.923722 Final RX Vref Byte 0 = 61 to rank0
6793 08:06:13.926703 Final RX Vref Byte 1 = 53 to rank0
6794 08:06:13.929998 Final RX Vref Byte 0 = 61 to rank1
6795 08:06:13.933987 Final RX Vref Byte 1 = 53 to rank1==
6796 08:06:13.936641 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 08:06:13.943296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 08:06:13.943378 ==
6799 08:06:13.943441 DQS Delay:
6800 08:06:13.946563 DQS0 = 52, DQS1 = 56
6801 08:06:13.946672 DQM Delay:
6802 08:06:13.946794 DQM0 = 16, DQM1 = 10
6803 08:06:13.950245 DQ Delay:
6804 08:06:13.953719 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =16
6805 08:06:13.956927 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =16
6806 08:06:13.957009 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6807 08:06:13.960070 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6808 08:06:13.960151
6809 08:06:13.963501
6810 08:06:13.970321 [DQSOSCAuto] RK0, (LSB)MR18= 0x882e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
6811 08:06:13.973347 CH1 RK0: MR19=C0C, MR18=882E
6812 08:06:13.979918 CH1_RK0: MR19=0xC0C, MR18=0x882E, DQSOSC=392, MR23=63, INC=384, DEC=256
6813 08:06:13.979999 ==
6814 08:06:13.983831 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 08:06:13.986641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 08:06:13.986782 ==
6817 08:06:13.989944 [Gating] SW mode calibration
6818 08:06:13.996930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 08:06:14.000070 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 08:06:14.006910 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 08:06:14.010298 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6822 08:06:14.014282 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 08:06:14.020222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 08:06:14.023729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 08:06:14.027133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 08:06:14.033865 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 08:06:14.037145 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 08:06:14.040611 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 08:06:14.044137 Total UI for P1: 0, mck2ui 16
6830 08:06:14.047548 best dqsien dly found for B0: ( 0, 14, 24)
6831 08:06:14.050867 Total UI for P1: 0, mck2ui 16
6832 08:06:14.053578 best dqsien dly found for B1: ( 0, 14, 24)
6833 08:06:14.057471 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 08:06:14.060824 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 08:06:14.060904
6836 08:06:14.063953 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 08:06:14.070299 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 08:06:14.070380 [Gating] SW calibration Done
6839 08:06:14.074026 ==
6840 08:06:14.074107 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 08:06:14.080371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 08:06:14.080453 ==
6843 08:06:14.080516 RX Vref Scan: 0
6844 08:06:14.080575
6845 08:06:14.083960 RX Vref 0 -> 0, step: 1
6846 08:06:14.084041
6847 08:06:14.087048 RX Delay -410 -> 252, step: 16
6848 08:06:14.090303 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6849 08:06:14.093801 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6850 08:06:14.100394 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6851 08:06:14.103893 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6852 08:06:14.107075 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6853 08:06:14.110676 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6854 08:06:14.116900 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6855 08:06:14.120609 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6856 08:06:14.124153 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6857 08:06:14.127539 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6858 08:06:14.134182 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6859 08:06:14.137534 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6860 08:06:14.140770 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6861 08:06:14.143885 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6862 08:06:14.150756 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6863 08:06:14.153844 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6864 08:06:14.153924 ==
6865 08:06:14.157162 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 08:06:14.160333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 08:06:14.160414 ==
6868 08:06:14.163589 DQS Delay:
6869 08:06:14.163687 DQS0 = 51, DQS1 = 59
6870 08:06:14.163765 DQM Delay:
6871 08:06:14.167369 DQM0 = 16, DQM1 = 20
6872 08:06:14.167471 DQ Delay:
6873 08:06:14.170695 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6874 08:06:14.174251 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6875 08:06:14.177689 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6876 08:06:14.180891 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6877 08:06:14.180972
6878 08:06:14.181035
6879 08:06:14.181094 ==
6880 08:06:14.184039 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 08:06:14.187607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 08:06:14.190689 ==
6883 08:06:14.190817
6884 08:06:14.190881
6885 08:06:14.190940 TX Vref Scan disable
6886 08:06:14.194371 == TX Byte 0 ==
6887 08:06:14.197357 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6888 08:06:14.200823 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6889 08:06:14.204141 == TX Byte 1 ==
6890 08:06:14.207639 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 08:06:14.210803 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 08:06:14.210901 ==
6893 08:06:14.214061 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 08:06:14.217821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 08:06:14.217901 ==
6896 08:06:14.220770
6897 08:06:14.220851
6898 08:06:14.220914 TX Vref Scan disable
6899 08:06:14.224266 == TX Byte 0 ==
6900 08:06:14.227656 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6901 08:06:14.230904 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6902 08:06:14.234168 == TX Byte 1 ==
6903 08:06:14.237894 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6904 08:06:14.241121 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6905 08:06:14.241201
6906 08:06:14.241264 [DATLAT]
6907 08:06:14.244347 Freq=400, CH1 RK1
6908 08:06:14.244428
6909 08:06:14.244491 DATLAT Default: 0xe
6910 08:06:14.247556 0, 0xFFFF, sum = 0
6911 08:06:14.247637 1, 0xFFFF, sum = 0
6912 08:06:14.250847 2, 0xFFFF, sum = 0
6913 08:06:14.254735 3, 0xFFFF, sum = 0
6914 08:06:14.254831 4, 0xFFFF, sum = 0
6915 08:06:14.257520 5, 0xFFFF, sum = 0
6916 08:06:14.257602 6, 0xFFFF, sum = 0
6917 08:06:14.261097 7, 0xFFFF, sum = 0
6918 08:06:14.261211 8, 0xFFFF, sum = 0
6919 08:06:14.264921 9, 0xFFFF, sum = 0
6920 08:06:14.265032 10, 0xFFFF, sum = 0
6921 08:06:14.267673 11, 0xFFFF, sum = 0
6922 08:06:14.267755 12, 0xFFFF, sum = 0
6923 08:06:14.271128 13, 0x0, sum = 1
6924 08:06:14.271210 14, 0x0, sum = 2
6925 08:06:14.274957 15, 0x0, sum = 3
6926 08:06:14.275038 16, 0x0, sum = 4
6927 08:06:14.277609 best_step = 14
6928 08:06:14.277688
6929 08:06:14.277751 ==
6930 08:06:14.281435 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 08:06:14.284842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 08:06:14.284940 ==
6933 08:06:14.285038 RX Vref Scan: 0
6934 08:06:14.285113
6935 08:06:14.287941 RX Vref 0 -> 0, step: 1
6936 08:06:14.288021
6937 08:06:14.290956 RX Delay -359 -> 252, step: 8
6938 08:06:14.298653 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6939 08:06:14.301992 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6940 08:06:14.305382 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6941 08:06:14.308280 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6942 08:06:14.315127 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6943 08:06:14.318338 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6944 08:06:14.321629 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6945 08:06:14.324971 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6946 08:06:14.331570 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6947 08:06:14.334969 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6948 08:06:14.338622 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6949 08:06:14.341844 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6950 08:06:14.348543 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6951 08:06:14.352296 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6952 08:06:14.355353 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6953 08:06:14.358390 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6954 08:06:14.362123 ==
6955 08:06:14.365138 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 08:06:14.368190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 08:06:14.368271 ==
6958 08:06:14.368336 DQS Delay:
6959 08:06:14.371591 DQS0 = 52, DQS1 = 56
6960 08:06:14.371672 DQM Delay:
6961 08:06:14.374831 DQM0 = 13, DQM1 = 9
6962 08:06:14.374912 DQ Delay:
6963 08:06:14.378634 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6964 08:06:14.381711 DQ4 =12, DQ5 =28, DQ6 =24, DQ7 =8
6965 08:06:14.385186 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6966 08:06:14.388344 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6967 08:06:14.388426
6968 08:06:14.388490
6969 08:06:14.395441 [DQSOSCAuto] RK1, (LSB)MR18= 0x748a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6970 08:06:14.398640 CH1 RK1: MR19=C0C, MR18=748A
6971 08:06:14.405091 CH1_RK1: MR19=0xC0C, MR18=0x748A, DQSOSC=392, MR23=63, INC=384, DEC=256
6972 08:06:14.408319 [RxdqsGatingPostProcess] freq 400
6973 08:06:14.411994 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 08:06:14.415173 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 08:06:14.418884 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 08:06:14.421991 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 08:06:14.424970 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 08:06:14.428596 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 08:06:14.431734 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 08:06:14.435420 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 08:06:14.438551 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 08:06:14.442017 Pre-setting of DQS Precalculation
6983 08:06:14.445071 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 08:06:14.451988 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 08:06:14.461771 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 08:06:14.461853
6987 08:06:14.461918
6988 08:06:14.464887 [Calibration Summary] 800 Mbps
6989 08:06:14.464968 CH 0, Rank 0
6990 08:06:14.468430 SW Impedance : PASS
6991 08:06:14.468511 DUTY Scan : NO K
6992 08:06:14.471596 ZQ Calibration : PASS
6993 08:06:14.471677 Jitter Meter : NO K
6994 08:06:14.474954 CBT Training : PASS
6995 08:06:14.478307 Write leveling : PASS
6996 08:06:14.478388 RX DQS gating : PASS
6997 08:06:14.481852 RX DQ/DQS(RDDQC) : PASS
6998 08:06:14.485296 TX DQ/DQS : PASS
6999 08:06:14.485378 RX DATLAT : PASS
7000 08:06:14.488338 RX DQ/DQS(Engine): PASS
7001 08:06:14.491627 TX OE : NO K
7002 08:06:14.491709 All Pass.
7003 08:06:14.491774
7004 08:06:14.491833 CH 0, Rank 1
7005 08:06:14.495194 SW Impedance : PASS
7006 08:06:14.498568 DUTY Scan : NO K
7007 08:06:14.498650 ZQ Calibration : PASS
7008 08:06:14.502104 Jitter Meter : NO K
7009 08:06:14.505803 CBT Training : PASS
7010 08:06:14.505884 Write leveling : NO K
7011 08:06:14.508491 RX DQS gating : PASS
7012 08:06:14.508572 RX DQ/DQS(RDDQC) : PASS
7013 08:06:14.512097 TX DQ/DQS : PASS
7014 08:06:14.515490 RX DATLAT : PASS
7015 08:06:14.515571 RX DQ/DQS(Engine): PASS
7016 08:06:14.518561 TX OE : NO K
7017 08:06:14.518643 All Pass.
7018 08:06:14.518708
7019 08:06:14.522068 CH 1, Rank 0
7020 08:06:14.522148 SW Impedance : PASS
7021 08:06:14.525234 DUTY Scan : NO K
7022 08:06:14.528434 ZQ Calibration : PASS
7023 08:06:14.528516 Jitter Meter : NO K
7024 08:06:14.532102 CBT Training : PASS
7025 08:06:14.535270 Write leveling : PASS
7026 08:06:14.535351 RX DQS gating : PASS
7027 08:06:14.538946 RX DQ/DQS(RDDQC) : PASS
7028 08:06:14.542474 TX DQ/DQS : PASS
7029 08:06:14.542555 RX DATLAT : PASS
7030 08:06:14.545457 RX DQ/DQS(Engine): PASS
7031 08:06:14.548613 TX OE : NO K
7032 08:06:14.548695 All Pass.
7033 08:06:14.548759
7034 08:06:14.548819 CH 1, Rank 1
7035 08:06:14.552037 SW Impedance : PASS
7036 08:06:14.555255 DUTY Scan : NO K
7037 08:06:14.555337 ZQ Calibration : PASS
7038 08:06:14.558659 Jitter Meter : NO K
7039 08:06:14.558781 CBT Training : PASS
7040 08:06:14.562198 Write leveling : NO K
7041 08:06:14.565625 RX DQS gating : PASS
7042 08:06:14.565707 RX DQ/DQS(RDDQC) : PASS
7043 08:06:14.568583 TX DQ/DQS : PASS
7044 08:06:14.572243 RX DATLAT : PASS
7045 08:06:14.572324 RX DQ/DQS(Engine): PASS
7046 08:06:14.575471 TX OE : NO K
7047 08:06:14.575553 All Pass.
7048 08:06:14.575618
7049 08:06:14.579038 DramC Write-DBI off
7050 08:06:14.582066 PER_BANK_REFRESH: Hybrid Mode
7051 08:06:14.582162 TX_TRACKING: ON
7052 08:06:14.592095 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 08:06:14.595672 [FAST_K] Save calibration result to emmc
7054 08:06:14.598616 dramc_set_vcore_voltage set vcore to 725000
7055 08:06:14.602252 Read voltage for 1600, 0
7056 08:06:14.602333 Vio18 = 0
7057 08:06:14.602398 Vcore = 725000
7058 08:06:14.605622 Vdram = 0
7059 08:06:14.605712 Vddq = 0
7060 08:06:14.605777 Vmddr = 0
7061 08:06:14.612108 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 08:06:14.615387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 08:06:14.618878 MEM_TYPE=3, freq_sel=13
7064 08:06:14.622474 sv_algorithm_assistance_LP4_3733
7065 08:06:14.625908 ============ PULL DRAM RESETB DOWN ============
7066 08:06:14.628961 ========== PULL DRAM RESETB DOWN end =========
7067 08:06:14.635325 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 08:06:14.638665 ===================================
7069 08:06:14.638788 LPDDR4 DRAM CONFIGURATION
7070 08:06:14.642566 ===================================
7071 08:06:14.645559 EX_ROW_EN[0] = 0x0
7072 08:06:14.649018 EX_ROW_EN[1] = 0x0
7073 08:06:14.649098 LP4Y_EN = 0x0
7074 08:06:14.652507 WORK_FSP = 0x1
7075 08:06:14.652587 WL = 0x5
7076 08:06:14.655880 RL = 0x5
7077 08:06:14.655960 BL = 0x2
7078 08:06:14.658834 RPST = 0x0
7079 08:06:14.658914 RD_PRE = 0x0
7080 08:06:14.662447 WR_PRE = 0x1
7081 08:06:14.662527 WR_PST = 0x1
7082 08:06:14.665272 DBI_WR = 0x0
7083 08:06:14.665352 DBI_RD = 0x0
7084 08:06:14.669225 OTF = 0x1
7085 08:06:14.672041 ===================================
7086 08:06:14.675437 ===================================
7087 08:06:14.675517 ANA top config
7088 08:06:14.679184 ===================================
7089 08:06:14.682197 DLL_ASYNC_EN = 0
7090 08:06:14.685948 ALL_SLAVE_EN = 0
7091 08:06:14.686029 NEW_RANK_MODE = 1
7092 08:06:14.689088 DLL_IDLE_MODE = 1
7093 08:06:14.692504 LP45_APHY_COMB_EN = 1
7094 08:06:14.695796 TX_ODT_DIS = 0
7095 08:06:14.699136 NEW_8X_MODE = 1
7096 08:06:14.702214 ===================================
7097 08:06:14.702294 ===================================
7098 08:06:14.705287 data_rate = 3200
7099 08:06:14.709051 CKR = 1
7100 08:06:14.712741 DQ_P2S_RATIO = 8
7101 08:06:14.715360 ===================================
7102 08:06:14.718746 CA_P2S_RATIO = 8
7103 08:06:14.722331 DQ_CA_OPEN = 0
7104 08:06:14.725622 DQ_SEMI_OPEN = 0
7105 08:06:14.725702 CA_SEMI_OPEN = 0
7106 08:06:14.728809 CA_FULL_RATE = 0
7107 08:06:14.732177 DQ_CKDIV4_EN = 0
7108 08:06:14.735806 CA_CKDIV4_EN = 0
7109 08:06:14.738743 CA_PREDIV_EN = 0
7110 08:06:14.738837 PH8_DLY = 12
7111 08:06:14.742220 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 08:06:14.745826 DQ_AAMCK_DIV = 4
7113 08:06:14.749164 CA_AAMCK_DIV = 4
7114 08:06:14.752303 CA_ADMCK_DIV = 4
7115 08:06:14.756027 DQ_TRACK_CA_EN = 0
7116 08:06:14.759180 CA_PICK = 1600
7117 08:06:14.759261 CA_MCKIO = 1600
7118 08:06:14.762752 MCKIO_SEMI = 0
7119 08:06:14.766150 PLL_FREQ = 3068
7120 08:06:14.769319 DQ_UI_PI_RATIO = 32
7121 08:06:14.772132 CA_UI_PI_RATIO = 0
7122 08:06:14.775484 ===================================
7123 08:06:14.778998 ===================================
7124 08:06:14.782358 memory_type:LPDDR4
7125 08:06:14.782438 GP_NUM : 10
7126 08:06:14.785762 SRAM_EN : 1
7127 08:06:14.785842 MD32_EN : 0
7128 08:06:14.788931 ===================================
7129 08:06:14.792507 [ANA_INIT] >>>>>>>>>>>>>>
7130 08:06:14.795577 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 08:06:14.798697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 08:06:14.802518 ===================================
7133 08:06:14.805697 data_rate = 3200,PCW = 0X7600
7134 08:06:14.809522 ===================================
7135 08:06:14.812304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 08:06:14.815652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 08:06:14.822590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 08:06:14.826010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 08:06:14.829121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 08:06:14.835755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 08:06:14.835835 [ANA_INIT] flow start
7142 08:06:14.838912 [ANA_INIT] PLL >>>>>>>>
7143 08:06:14.838992 [ANA_INIT] PLL <<<<<<<<
7144 08:06:14.842777 [ANA_INIT] MIDPI >>>>>>>>
7145 08:06:14.845524 [ANA_INIT] MIDPI <<<<<<<<
7146 08:06:14.849294 [ANA_INIT] DLL >>>>>>>>
7147 08:06:14.849375 [ANA_INIT] DLL <<<<<<<<
7148 08:06:14.852216 [ANA_INIT] flow end
7149 08:06:14.855883 ============ LP4 DIFF to SE enter ============
7150 08:06:14.859312 ============ LP4 DIFF to SE exit ============
7151 08:06:14.862334 [ANA_INIT] <<<<<<<<<<<<<
7152 08:06:14.865686 [Flow] Enable top DCM control >>>>>
7153 08:06:14.869271 [Flow] Enable top DCM control <<<<<
7154 08:06:14.872307 Enable DLL master slave shuffle
7155 08:06:14.878890 ==============================================================
7156 08:06:14.878972 Gating Mode config
7157 08:06:14.885597 ==============================================================
7158 08:06:14.885700 Config description:
7159 08:06:14.895876 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 08:06:14.902141 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 08:06:14.909432 SELPH_MODE 0: By rank 1: By Phase
7162 08:06:14.912226 ==============================================================
7163 08:06:14.915581 GAT_TRACK_EN = 1
7164 08:06:14.919113 RX_GATING_MODE = 2
7165 08:06:14.922273 RX_GATING_TRACK_MODE = 2
7166 08:06:14.925604 SELPH_MODE = 1
7167 08:06:14.929161 PICG_EARLY_EN = 1
7168 08:06:14.932358 VALID_LAT_VALUE = 1
7169 08:06:14.935708 ==============================================================
7170 08:06:14.939047 Enter into Gating configuration >>>>
7171 08:06:14.942896 Exit from Gating configuration <<<<
7172 08:06:14.945876 Enter into DVFS_PRE_config >>>>>
7173 08:06:14.959257 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 08:06:14.959340 Exit from DVFS_PRE_config <<<<<
7175 08:06:14.962645 Enter into PICG configuration >>>>
7176 08:06:14.966025 Exit from PICG configuration <<<<
7177 08:06:14.969640 [RX_INPUT] configuration >>>>>
7178 08:06:14.972657 [RX_INPUT] configuration <<<<<
7179 08:06:14.979633 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 08:06:14.982957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 08:06:14.989261 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 08:06:14.996198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 08:06:15.002514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 08:06:15.009392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 08:06:15.012876 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 08:06:15.015800 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 08:06:15.019171 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 08:06:15.026015 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 08:06:15.029243 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 08:06:15.032505 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 08:06:15.036128 ===================================
7192 08:06:15.039178 LPDDR4 DRAM CONFIGURATION
7193 08:06:15.042961 ===================================
7194 08:06:15.043058 EX_ROW_EN[0] = 0x0
7195 08:06:15.046171 EX_ROW_EN[1] = 0x0
7196 08:06:15.046252 LP4Y_EN = 0x0
7197 08:06:15.049143 WORK_FSP = 0x1
7198 08:06:15.049224 WL = 0x5
7199 08:06:15.052658 RL = 0x5
7200 08:06:15.055889 BL = 0x2
7201 08:06:15.055970 RPST = 0x0
7202 08:06:15.059879 RD_PRE = 0x0
7203 08:06:15.059976 WR_PRE = 0x1
7204 08:06:15.063128 WR_PST = 0x1
7205 08:06:15.063209 DBI_WR = 0x0
7206 08:06:15.066145 DBI_RD = 0x0
7207 08:06:15.066226 OTF = 0x1
7208 08:06:15.069878 ===================================
7209 08:06:15.073276 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 08:06:15.076125 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 08:06:15.082728 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 08:06:15.086595 ===================================
7213 08:06:15.089548 LPDDR4 DRAM CONFIGURATION
7214 08:06:15.092701 ===================================
7215 08:06:15.092782 EX_ROW_EN[0] = 0x10
7216 08:06:15.096764 EX_ROW_EN[1] = 0x0
7217 08:06:15.096846 LP4Y_EN = 0x0
7218 08:06:15.099710 WORK_FSP = 0x1
7219 08:06:15.099791 WL = 0x5
7220 08:06:15.102980 RL = 0x5
7221 08:06:15.103062 BL = 0x2
7222 08:06:15.106326 RPST = 0x0
7223 08:06:15.106407 RD_PRE = 0x0
7224 08:06:15.109784 WR_PRE = 0x1
7225 08:06:15.109865 WR_PST = 0x1
7226 08:06:15.112978 DBI_WR = 0x0
7227 08:06:15.113060 DBI_RD = 0x0
7228 08:06:15.116328 OTF = 0x1
7229 08:06:15.119585 ===================================
7230 08:06:15.126316 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 08:06:15.126398 ==
7232 08:06:15.129740 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 08:06:15.133099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 08:06:15.133180 ==
7235 08:06:15.136501 [Duty_Offset_Calibration]
7236 08:06:15.136602 B0:2 B1:-1 CA:1
7237 08:06:15.136727
7238 08:06:15.140118 [DutyScan_Calibration_Flow] k_type=0
7239 08:06:15.149798
7240 08:06:15.149879 ==CLK 0==
7241 08:06:15.152969 Final CLK duty delay cell = -4
7242 08:06:15.156206 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7243 08:06:15.159519 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7244 08:06:15.162906 [-4] AVG Duty = 4937%(X100)
7245 08:06:15.162996
7246 08:06:15.166502 CH0 CLK Duty spec in!! Max-Min= 187%
7247 08:06:15.169864 [DutyScan_Calibration_Flow] ====Done====
7248 08:06:15.169962
7249 08:06:15.172811 [DutyScan_Calibration_Flow] k_type=1
7250 08:06:15.189374
7251 08:06:15.189455 ==DQS 0 ==
7252 08:06:15.192205 Final DQS duty delay cell = 0
7253 08:06:15.196538 [0] MAX Duty = 5125%(X100), DQS PI = 56
7254 08:06:15.199100 [0] MIN Duty = 5000%(X100), DQS PI = 14
7255 08:06:15.202338 [0] AVG Duty = 5062%(X100)
7256 08:06:15.202419
7257 08:06:15.202484 ==DQS 1 ==
7258 08:06:15.205980 Final DQS duty delay cell = -4
7259 08:06:15.209446 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7260 08:06:15.212649 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7261 08:06:15.216255 [-4] AVG Duty = 5046%(X100)
7262 08:06:15.216336
7263 08:06:15.219126 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7264 08:06:15.219207
7265 08:06:15.222595 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7266 08:06:15.225747 [DutyScan_Calibration_Flow] ====Done====
7267 08:06:15.225829
7268 08:06:15.229242 [DutyScan_Calibration_Flow] k_type=3
7269 08:06:15.246355
7270 08:06:15.246437 ==DQM 0 ==
7271 08:06:15.249750 Final DQM duty delay cell = 0
7272 08:06:15.253064 [0] MAX Duty = 5000%(X100), DQS PI = 20
7273 08:06:15.256625 [0] MIN Duty = 4875%(X100), DQS PI = 4
7274 08:06:15.256783 [0] AVG Duty = 4937%(X100)
7275 08:06:15.256877
7276 08:06:15.260354 ==DQM 1 ==
7277 08:06:15.263343 Final DQM duty delay cell = 0
7278 08:06:15.266928 [0] MAX Duty = 5218%(X100), DQS PI = 58
7279 08:06:15.269932 [0] MIN Duty = 4969%(X100), DQS PI = 18
7280 08:06:15.270014 [0] AVG Duty = 5093%(X100)
7281 08:06:15.270079
7282 08:06:15.276995 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7283 08:06:15.277076
7284 08:06:15.280241 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7285 08:06:15.283327 [DutyScan_Calibration_Flow] ====Done====
7286 08:06:15.283408
7287 08:06:15.286481 [DutyScan_Calibration_Flow] k_type=2
7288 08:06:15.302976
7289 08:06:15.303057 ==DQ 0 ==
7290 08:06:15.306187 Final DQ duty delay cell = -4
7291 08:06:15.309464 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7292 08:06:15.312876 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7293 08:06:15.316202 [-4] AVG Duty = 4922%(X100)
7294 08:06:15.316282
7295 08:06:15.316345 ==DQ 1 ==
7296 08:06:15.319379 Final DQ duty delay cell = 0
7297 08:06:15.322878 [0] MAX Duty = 5031%(X100), DQS PI = 30
7298 08:06:15.326157 [0] MIN Duty = 4907%(X100), DQS PI = 18
7299 08:06:15.326241 [0] AVG Duty = 4969%(X100)
7300 08:06:15.329453
7301 08:06:15.333055 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7302 08:06:15.333136
7303 08:06:15.336197 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7304 08:06:15.339846 [DutyScan_Calibration_Flow] ====Done====
7305 08:06:15.339927 ==
7306 08:06:15.342700 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 08:06:15.346483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 08:06:15.346564 ==
7309 08:06:15.349874 [Duty_Offset_Calibration]
7310 08:06:15.349954 B0:1 B1:1 CA:2
7311 08:06:15.350017
7312 08:06:15.353277 [DutyScan_Calibration_Flow] k_type=0
7313 08:06:15.363226
7314 08:06:15.363306 ==CLK 0==
7315 08:06:15.366718 Final CLK duty delay cell = 0
7316 08:06:15.370336 [0] MAX Duty = 5187%(X100), DQS PI = 24
7317 08:06:15.373503 [0] MIN Duty = 4938%(X100), DQS PI = 56
7318 08:06:15.373584 [0] AVG Duty = 5062%(X100)
7319 08:06:15.376761
7320 08:06:15.379818 CH1 CLK Duty spec in!! Max-Min= 249%
7321 08:06:15.383831 [DutyScan_Calibration_Flow] ====Done====
7322 08:06:15.383912
7323 08:06:15.386524 [DutyScan_Calibration_Flow] k_type=1
7324 08:06:15.403199
7325 08:06:15.403306 ==DQS 0 ==
7326 08:06:15.406443 Final DQS duty delay cell = 0
7327 08:06:15.409679 [0] MAX Duty = 5062%(X100), DQS PI = 20
7328 08:06:15.412916 [0] MIN Duty = 4813%(X100), DQS PI = 52
7329 08:06:15.416651 [0] AVG Duty = 4937%(X100)
7330 08:06:15.416745
7331 08:06:15.416823 ==DQS 1 ==
7332 08:06:15.419840 Final DQS duty delay cell = 0
7333 08:06:15.423127 [0] MAX Duty = 5062%(X100), DQS PI = 58
7334 08:06:15.426360 [0] MIN Duty = 4938%(X100), DQS PI = 12
7335 08:06:15.429857 [0] AVG Duty = 5000%(X100)
7336 08:06:15.429939
7337 08:06:15.432881 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7338 08:06:15.432991
7339 08:06:15.436194 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7340 08:06:15.439729 [DutyScan_Calibration_Flow] ====Done====
7341 08:06:15.439825
7342 08:06:15.443188 [DutyScan_Calibration_Flow] k_type=3
7343 08:06:15.460214
7344 08:06:15.460294 ==DQM 0 ==
7345 08:06:15.463372 Final DQM duty delay cell = 0
7346 08:06:15.466645 [0] MAX Duty = 5156%(X100), DQS PI = 20
7347 08:06:15.470322 [0] MIN Duty = 4844%(X100), DQS PI = 50
7348 08:06:15.470403 [0] AVG Duty = 5000%(X100)
7349 08:06:15.473248
7350 08:06:15.473329 ==DQM 1 ==
7351 08:06:15.476942 Final DQM duty delay cell = 0
7352 08:06:15.480302 [0] MAX Duty = 5125%(X100), DQS PI = 10
7353 08:06:15.483478 [0] MIN Duty = 4907%(X100), DQS PI = 20
7354 08:06:15.483559 [0] AVG Duty = 5016%(X100)
7355 08:06:15.486747
7356 08:06:15.490398 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7357 08:06:15.490505
7358 08:06:15.493517 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7359 08:06:15.496749 [DutyScan_Calibration_Flow] ====Done====
7360 08:06:15.496830
7361 08:06:15.499799 [DutyScan_Calibration_Flow] k_type=2
7362 08:06:15.516886
7363 08:06:15.516981 ==DQ 0 ==
7364 08:06:15.520218 Final DQ duty delay cell = 0
7365 08:06:15.523977 [0] MAX Duty = 5156%(X100), DQS PI = 20
7366 08:06:15.527003 [0] MIN Duty = 4907%(X100), DQS PI = 52
7367 08:06:15.527099 [0] AVG Duty = 5031%(X100)
7368 08:06:15.527164
7369 08:06:15.530681 ==DQ 1 ==
7370 08:06:15.533735 Final DQ duty delay cell = 0
7371 08:06:15.537795 [0] MAX Duty = 5124%(X100), DQS PI = 42
7372 08:06:15.540839 [0] MIN Duty = 5031%(X100), DQS PI = 0
7373 08:06:15.540948 [0] AVG Duty = 5077%(X100)
7374 08:06:15.541016
7375 08:06:15.543819 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7376 08:06:15.543900
7377 08:06:15.547136 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7378 08:06:15.550575 [DutyScan_Calibration_Flow] ====Done====
7379 08:06:15.555893 nWR fixed to 30
7380 08:06:15.559204 [ModeRegInit_LP4] CH0 RK0
7381 08:06:15.559285 [ModeRegInit_LP4] CH0 RK1
7382 08:06:15.562621 [ModeRegInit_LP4] CH1 RK0
7383 08:06:15.565986 [ModeRegInit_LP4] CH1 RK1
7384 08:06:15.566086 match AC timing 5
7385 08:06:15.572812 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 08:06:15.576006 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 08:06:15.579499 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 08:06:15.586392 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 08:06:15.589102 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 08:06:15.589183 [MiockJmeterHQA]
7391 08:06:15.589248
7392 08:06:15.592476 [DramcMiockJmeter] u1RxGatingPI = 0
7393 08:06:15.595986 0 : 4253, 4027
7394 08:06:15.596068 4 : 4252, 4027
7395 08:06:15.599160 8 : 4252, 4027
7396 08:06:15.599242 12 : 4253, 4026
7397 08:06:15.602873 16 : 4253, 4027
7398 08:06:15.602956 20 : 4253, 4026
7399 08:06:15.603020 24 : 4255, 4030
7400 08:06:15.605951 28 : 4363, 4137
7401 08:06:15.606033 32 : 4252, 4027
7402 08:06:15.609208 36 : 4252, 4027
7403 08:06:15.609290 40 : 4253, 4026
7404 08:06:15.612554 44 : 4255, 4030
7405 08:06:15.612636 48 : 4253, 4026
7406 08:06:15.612701 52 : 4363, 4138
7407 08:06:15.616080 56 : 4363, 4137
7408 08:06:15.616191 60 : 4250, 4026
7409 08:06:15.619210 64 : 4250, 4027
7410 08:06:15.619321 68 : 4250, 4026
7411 08:06:15.622948 72 : 4253, 4026
7412 08:06:15.623030 76 : 4252, 4030
7413 08:06:15.626151 80 : 4361, 4137
7414 08:06:15.626261 84 : 4250, 4027
7415 08:06:15.626328 88 : 4250, 4026
7416 08:06:15.629357 92 : 4250, 4026
7417 08:06:15.629440 96 : 4252, 3713
7418 08:06:15.632572 100 : 4250, 0
7419 08:06:15.632654 104 : 4252, 0
7420 08:06:15.632720 108 : 4250, 0
7421 08:06:15.636049 112 : 4250, 0
7422 08:06:15.636147 116 : 4252, 0
7423 08:06:15.639576 120 : 4250, 0
7424 08:06:15.639659 124 : 4360, 0
7425 08:06:15.639724 128 : 4360, 0
7426 08:06:15.642765 132 : 4250, 0
7427 08:06:15.642851 136 : 4250, 0
7428 08:06:15.645793 140 : 4249, 0
7429 08:06:15.645871 144 : 4250, 0
7430 08:06:15.645935 148 : 4250, 0
7431 08:06:15.649192 152 : 4250, 0
7432 08:06:15.649293 156 : 4252, 0
7433 08:06:15.652846 160 : 4361, 0
7434 08:06:15.652942 164 : 4360, 0
7435 08:06:15.653031 168 : 4363, 0
7436 08:06:15.655772 172 : 4250, 0
7437 08:06:15.655844 176 : 4250, 0
7438 08:06:15.655904 180 : 4250, 0
7439 08:06:15.659207 184 : 4250, 0
7440 08:06:15.659309 188 : 4250, 0
7441 08:06:15.662515 192 : 4250, 0
7442 08:06:15.662617 196 : 4252, 0
7443 08:06:15.662711 200 : 4250, 0
7444 08:06:15.666344 204 : 4250, 0
7445 08:06:15.666450 208 : 4252, 0
7446 08:06:15.669631 212 : 4361, 124
7447 08:06:15.669735 216 : 4361, 3972
7448 08:06:15.672711 220 : 4249, 4027
7449 08:06:15.672815 224 : 4250, 4026
7450 08:06:15.672909 228 : 4250, 4027
7451 08:06:15.676137 232 : 4252, 4030
7452 08:06:15.676213 236 : 4250, 4026
7453 08:06:15.679091 240 : 4250, 4026
7454 08:06:15.679171 244 : 4361, 4137
7455 08:06:15.682497 248 : 4250, 4027
7456 08:06:15.682569 252 : 4250, 4026
7457 08:06:15.685707 256 : 4361, 4137
7458 08:06:15.685811 260 : 4250, 4026
7459 08:06:15.689506 264 : 4250, 4027
7460 08:06:15.689610 268 : 4363, 4140
7461 08:06:15.692899 272 : 4250, 4026
7462 08:06:15.693000 276 : 4250, 4026
7463 08:06:15.693097 280 : 4250, 4027
7464 08:06:15.696037 284 : 4252, 4030
7465 08:06:15.696116 288 : 4250, 4027
7466 08:06:15.699573 292 : 4250, 4026
7467 08:06:15.699650 296 : 4361, 4137
7468 08:06:15.703274 300 : 4250, 4027
7469 08:06:15.703349 304 : 4250, 4027
7470 08:06:15.706623 308 : 4361, 4137
7471 08:06:15.706735 312 : 4250, 4026
7472 08:06:15.709563 316 : 4250, 4027
7473 08:06:15.709666 320 : 4363, 4140
7474 08:06:15.713118 324 : 4250, 4026
7475 08:06:15.713222 328 : 4250, 4026
7476 08:06:15.713360 332 : 4250, 3169
7477 08:06:15.716579 336 : 4250, 113
7478 08:06:15.716676
7479 08:06:15.719865 MIOCK jitter meter ch=0
7480 08:06:15.719981
7481 08:06:15.720077 1T = (336-100) = 236 dly cells
7482 08:06:15.726202 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7483 08:06:15.726307 ==
7484 08:06:15.729972 Dram Type= 6, Freq= 0, CH_0, rank 0
7485 08:06:15.733426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 08:06:15.736093 ==
7487 08:06:15.739568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 08:06:15.743162 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 08:06:15.750145 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 08:06:15.753195 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 08:06:15.763550 [CA 0] Center 44 (14~75) winsize 62
7492 08:06:15.766980 [CA 1] Center 43 (13~74) winsize 62
7493 08:06:15.770316 [CA 2] Center 39 (10~68) winsize 59
7494 08:06:15.773359 [CA 3] Center 39 (10~68) winsize 59
7495 08:06:15.776949 [CA 4] Center 37 (7~67) winsize 61
7496 08:06:15.780027 [CA 5] Center 37 (7~67) winsize 61
7497 08:06:15.780124
7498 08:06:15.783474 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 08:06:15.783546
7500 08:06:15.786785 [CATrainingPosCal] consider 1 rank data
7501 08:06:15.790436 u2DelayCellTimex100 = 275/100 ps
7502 08:06:15.793580 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7503 08:06:15.800486 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7504 08:06:15.803667 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7505 08:06:15.806984 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7506 08:06:15.810917 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7507 08:06:15.813879 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7508 08:06:15.813977
7509 08:06:15.816960 CA PerBit enable=1, Macro0, CA PI delay=37
7510 08:06:15.817064
7511 08:06:15.820182 [CBTSetCACLKResult] CA Dly = 37
7512 08:06:15.823926 CS Dly: 11 (0~42)
7513 08:06:15.827328 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 08:06:15.830456 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 08:06:15.830556 ==
7516 08:06:15.833787 Dram Type= 6, Freq= 0, CH_0, rank 1
7517 08:06:15.837076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 08:06:15.837205 ==
7519 08:06:15.843760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 08:06:15.847079 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 08:06:15.854054 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 08:06:15.857259 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 08:06:15.868012 [CA 0] Center 44 (14~75) winsize 62
7524 08:06:15.871148 [CA 1] Center 44 (14~75) winsize 62
7525 08:06:15.874331 [CA 2] Center 40 (11~69) winsize 59
7526 08:06:15.877488 [CA 3] Center 39 (10~69) winsize 60
7527 08:06:15.880774 [CA 4] Center 38 (8~68) winsize 61
7528 08:06:15.884094 [CA 5] Center 37 (7~67) winsize 61
7529 08:06:15.884171
7530 08:06:15.887295 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 08:06:15.887368
7532 08:06:15.890580 [CATrainingPosCal] consider 2 rank data
7533 08:06:15.893788 u2DelayCellTimex100 = 275/100 ps
7534 08:06:15.900583 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7535 08:06:15.904066 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7536 08:06:15.907625 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7537 08:06:15.910677 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7538 08:06:15.913966 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7539 08:06:15.917350 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7540 08:06:15.917454
7541 08:06:15.921354 CA PerBit enable=1, Macro0, CA PI delay=37
7542 08:06:15.921461
7543 08:06:15.924384 [CBTSetCACLKResult] CA Dly = 37
7544 08:06:15.927802 CS Dly: 12 (0~44)
7545 08:06:15.930647 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 08:06:15.934189 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 08:06:15.934288
7548 08:06:15.937431 ----->DramcWriteLeveling(PI) begin...
7549 08:06:15.937529 ==
7550 08:06:15.941237 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 08:06:15.944487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 08:06:15.947711 ==
7553 08:06:15.947814 Write leveling (Byte 0): 32 => 32
7554 08:06:15.950949 Write leveling (Byte 1): 28 => 28
7555 08:06:15.954518 DramcWriteLeveling(PI) end<-----
7556 08:06:15.954616
7557 08:06:15.954704 ==
7558 08:06:15.957806 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 08:06:15.964597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 08:06:15.964670 ==
7561 08:06:15.964752 [Gating] SW mode calibration
7562 08:06:15.974399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7563 08:06:15.977612 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7564 08:06:15.980787 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 08:06:15.987401 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 08:06:15.991199 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 08:06:15.994080 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 08:06:16.000941 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7569 08:06:16.004352 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7570 08:06:16.008103 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7571 08:06:16.014254 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 08:06:16.017949 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 08:06:16.021027 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 08:06:16.027824 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7575 08:06:16.030844 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7576 08:06:16.034400 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
7577 08:06:16.041280 1 5 20 | B1->B0 | 3434 2525 | 0 0 | (0 1) (0 0)
7578 08:06:16.044532 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7579 08:06:16.048013 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 08:06:16.054244 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 08:06:16.057768 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 08:06:16.060994 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 08:06:16.064724 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 08:06:16.071526 1 6 16 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7585 08:06:16.074656 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7586 08:06:16.077573 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7587 08:06:16.084248 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 08:06:16.087949 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 08:06:16.091340 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 08:06:16.097868 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 08:06:16.101022 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 08:06:16.104702 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 08:06:16.111153 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7594 08:06:16.114711 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 08:06:16.118260 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 08:06:16.124250 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 08:06:16.127802 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 08:06:16.131016 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 08:06:16.137828 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 08:06:16.141408 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 08:06:16.144293 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 08:06:16.147616 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 08:06:16.154532 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 08:06:16.157707 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 08:06:16.161320 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 08:06:16.167658 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 08:06:16.170927 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 08:06:16.174272 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7609 08:06:16.181151 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7610 08:06:16.184222 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7611 08:06:16.188194 Total UI for P1: 0, mck2ui 16
7612 08:06:16.191080 best dqsien dly found for B0: ( 1, 9, 16)
7613 08:06:16.194779 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 08:06:16.197596 Total UI for P1: 0, mck2ui 16
7615 08:06:16.200898 best dqsien dly found for B1: ( 1, 9, 20)
7616 08:06:16.204210 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7617 08:06:16.208194 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7618 08:06:16.208262
7619 08:06:16.214169 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7620 08:06:16.217621 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7621 08:06:16.221033 [Gating] SW calibration Done
7622 08:06:16.221136 ==
7623 08:06:16.224777 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 08:06:16.227593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 08:06:16.227693 ==
7626 08:06:16.227782 RX Vref Scan: 0
7627 08:06:16.227871
7628 08:06:16.231209 RX Vref 0 -> 0, step: 1
7629 08:06:16.231309
7630 08:06:16.234456 RX Delay 0 -> 252, step: 8
7631 08:06:16.237871 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7632 08:06:16.241170 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7633 08:06:16.244655 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7634 08:06:16.251380 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7635 08:06:16.254588 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7636 08:06:16.257831 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7637 08:06:16.261187 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7638 08:06:16.264422 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7639 08:06:16.271202 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7640 08:06:16.274555 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7641 08:06:16.277782 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7642 08:06:16.281206 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7643 08:06:16.284415 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7644 08:06:16.291540 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7645 08:06:16.294963 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7646 08:06:16.298124 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7647 08:06:16.298204 ==
7648 08:06:16.301290 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 08:06:16.304876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 08:06:16.304950 ==
7651 08:06:16.308194 DQS Delay:
7652 08:06:16.308267 DQS0 = 0, DQS1 = 0
7653 08:06:16.308329 DQM Delay:
7654 08:06:16.311473 DQM0 = 132, DQM1 = 125
7655 08:06:16.311547 DQ Delay:
7656 08:06:16.314533 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7657 08:06:16.318061 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7658 08:06:16.324751 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7659 08:06:16.328272 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7660 08:06:16.328387
7661 08:06:16.328487
7662 08:06:16.328574 ==
7663 08:06:16.331690 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 08:06:16.335104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 08:06:16.335201 ==
7666 08:06:16.335298
7667 08:06:16.335389
7668 08:06:16.338145 TX Vref Scan disable
7669 08:06:16.338249 == TX Byte 0 ==
7670 08:06:16.345163 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7671 08:06:16.348246 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7672 08:06:16.348354 == TX Byte 1 ==
7673 08:06:16.355201 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7674 08:06:16.358485 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7675 08:06:16.358581 ==
7676 08:06:16.362131 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 08:06:16.365123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 08:06:16.365205 ==
7679 08:06:16.380820
7680 08:06:16.383557 TX Vref early break, caculate TX vref
7681 08:06:16.386623 TX Vref=16, minBit 1, minWin=21, winSum=355
7682 08:06:16.390559 TX Vref=18, minBit 0, minWin=22, winSum=370
7683 08:06:16.393761 TX Vref=20, minBit 4, minWin=22, winSum=377
7684 08:06:16.397181 TX Vref=22, minBit 1, minWin=22, winSum=390
7685 08:06:16.400629 TX Vref=24, minBit 0, minWin=23, winSum=399
7686 08:06:16.407285 TX Vref=26, minBit 4, minWin=24, winSum=413
7687 08:06:16.410330 TX Vref=28, minBit 1, minWin=23, winSum=410
7688 08:06:16.413538 TX Vref=30, minBit 0, minWin=25, winSum=415
7689 08:06:16.417375 TX Vref=32, minBit 4, minWin=23, winSum=410
7690 08:06:16.420352 TX Vref=34, minBit 4, minWin=23, winSum=398
7691 08:06:16.423478 TX Vref=36, minBit 0, minWin=23, winSum=388
7692 08:06:16.430877 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 30
7693 08:06:16.430959
7694 08:06:16.433540 Final TX Range 0 Vref 30
7695 08:06:16.433621
7696 08:06:16.433697 ==
7697 08:06:16.437056 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 08:06:16.440323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 08:06:16.440407 ==
7700 08:06:16.440471
7701 08:06:16.440530
7702 08:06:16.443663 TX Vref Scan disable
7703 08:06:16.450169 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7704 08:06:16.450295 == TX Byte 0 ==
7705 08:06:16.453621 u2DelayCellOfst[0]=14 cells (4 PI)
7706 08:06:16.457155 u2DelayCellOfst[1]=21 cells (6 PI)
7707 08:06:16.460411 u2DelayCellOfst[2]=10 cells (3 PI)
7708 08:06:16.463525 u2DelayCellOfst[3]=14 cells (4 PI)
7709 08:06:16.467230 u2DelayCellOfst[4]=7 cells (2 PI)
7710 08:06:16.470690 u2DelayCellOfst[5]=0 cells (0 PI)
7711 08:06:16.473906 u2DelayCellOfst[6]=17 cells (5 PI)
7712 08:06:16.474002 u2DelayCellOfst[7]=21 cells (6 PI)
7713 08:06:16.480768 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7714 08:06:16.484172 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7715 08:06:16.484274 == TX Byte 1 ==
7716 08:06:16.487342 u2DelayCellOfst[8]=0 cells (0 PI)
7717 08:06:16.490614 u2DelayCellOfst[9]=3 cells (1 PI)
7718 08:06:16.493865 u2DelayCellOfst[10]=10 cells (3 PI)
7719 08:06:16.497717 u2DelayCellOfst[11]=3 cells (1 PI)
7720 08:06:16.500786 u2DelayCellOfst[12]=14 cells (4 PI)
7721 08:06:16.504175 u2DelayCellOfst[13]=10 cells (3 PI)
7722 08:06:16.507098 u2DelayCellOfst[14]=17 cells (5 PI)
7723 08:06:16.510477 u2DelayCellOfst[15]=14 cells (4 PI)
7724 08:06:16.514249 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7725 08:06:16.517287 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7726 08:06:16.520592 DramC Write-DBI on
7727 08:06:16.520704 ==
7728 08:06:16.523904 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 08:06:16.527127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 08:06:16.527230 ==
7731 08:06:16.527319
7732 08:06:16.530744
7733 08:06:16.530852 TX Vref Scan disable
7734 08:06:16.533966 == TX Byte 0 ==
7735 08:06:16.537064 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7736 08:06:16.540593 == TX Byte 1 ==
7737 08:06:16.544015 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7738 08:06:16.544113 DramC Write-DBI off
7739 08:06:16.544206
7740 08:06:16.547345 [DATLAT]
7741 08:06:16.547441 Freq=1600, CH0 RK0
7742 08:06:16.547533
7743 08:06:16.550461 DATLAT Default: 0xf
7744 08:06:16.550559 0, 0xFFFF, sum = 0
7745 08:06:16.554187 1, 0xFFFF, sum = 0
7746 08:06:16.554288 2, 0xFFFF, sum = 0
7747 08:06:16.557282 3, 0xFFFF, sum = 0
7748 08:06:16.557381 4, 0xFFFF, sum = 0
7749 08:06:16.560651 5, 0xFFFF, sum = 0
7750 08:06:16.560749 6, 0xFFFF, sum = 0
7751 08:06:16.564176 7, 0xFFFF, sum = 0
7752 08:06:16.564277 8, 0xFFFF, sum = 0
7753 08:06:16.567549 9, 0xFFFF, sum = 0
7754 08:06:16.570696 10, 0xFFFF, sum = 0
7755 08:06:16.570816 11, 0xFFFF, sum = 0
7756 08:06:16.573649 12, 0xFFFF, sum = 0
7757 08:06:16.573747 13, 0xFFFF, sum = 0
7758 08:06:16.577514 14, 0x0, sum = 1
7759 08:06:16.577617 15, 0x0, sum = 2
7760 08:06:16.580609 16, 0x0, sum = 3
7761 08:06:16.580708 17, 0x0, sum = 4
7762 08:06:16.580797 best_step = 15
7763 08:06:16.580887
7764 08:06:16.583729 ==
7765 08:06:16.587222 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 08:06:16.590994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 08:06:16.591075 ==
7768 08:06:16.591166 RX Vref Scan: 1
7769 08:06:16.591233
7770 08:06:16.593779 Set Vref Range= 24 -> 127
7771 08:06:16.593877
7772 08:06:16.597345 RX Vref 24 -> 127, step: 1
7773 08:06:16.597446
7774 08:06:16.600807 RX Delay 11 -> 252, step: 4
7775 08:06:16.600907
7776 08:06:16.603977 Set Vref, RX VrefLevel [Byte0]: 24
7777 08:06:16.607203 [Byte1]: 24
7778 08:06:16.607293
7779 08:06:16.610575 Set Vref, RX VrefLevel [Byte0]: 25
7780 08:06:16.613772 [Byte1]: 25
7781 08:06:16.613868
7782 08:06:16.617229 Set Vref, RX VrefLevel [Byte0]: 26
7783 08:06:16.620278 [Byte1]: 26
7784 08:06:16.624030
7785 08:06:16.624136 Set Vref, RX VrefLevel [Byte0]: 27
7786 08:06:16.627366 [Byte1]: 27
7787 08:06:16.631484
7788 08:06:16.631588 Set Vref, RX VrefLevel [Byte0]: 28
7789 08:06:16.635172 [Byte1]: 28
7790 08:06:16.639106
7791 08:06:16.639204 Set Vref, RX VrefLevel [Byte0]: 29
7792 08:06:16.642474 [Byte1]: 29
7793 08:06:16.646682
7794 08:06:16.646787 Set Vref, RX VrefLevel [Byte0]: 30
7795 08:06:16.650392 [Byte1]: 30
7796 08:06:16.654252
7797 08:06:16.654348 Set Vref, RX VrefLevel [Byte0]: 31
7798 08:06:16.657533 [Byte1]: 31
7799 08:06:16.662120
7800 08:06:16.662218 Set Vref, RX VrefLevel [Byte0]: 32
7801 08:06:16.665547 [Byte1]: 32
7802 08:06:16.669696
7803 08:06:16.669797 Set Vref, RX VrefLevel [Byte0]: 33
7804 08:06:16.672875 [Byte1]: 33
7805 08:06:16.677128
7806 08:06:16.677241 Set Vref, RX VrefLevel [Byte0]: 34
7807 08:06:16.680337 [Byte1]: 34
7808 08:06:16.685258
7809 08:06:16.685353 Set Vref, RX VrefLevel [Byte0]: 35
7810 08:06:16.688621 [Byte1]: 35
7811 08:06:16.692380
7812 08:06:16.692483 Set Vref, RX VrefLevel [Byte0]: 36
7813 08:06:16.695926 [Byte1]: 36
7814 08:06:16.700027
7815 08:06:16.700133 Set Vref, RX VrefLevel [Byte0]: 37
7816 08:06:16.703896 [Byte1]: 37
7817 08:06:16.707475
7818 08:06:16.707561 Set Vref, RX VrefLevel [Byte0]: 38
7819 08:06:16.711396 [Byte1]: 38
7820 08:06:16.715675
7821 08:06:16.715774 Set Vref, RX VrefLevel [Byte0]: 39
7822 08:06:16.718865 [Byte1]: 39
7823 08:06:16.723000
7824 08:06:16.723104 Set Vref, RX VrefLevel [Byte0]: 40
7825 08:06:16.726198 [Byte1]: 40
7826 08:06:16.730964
7827 08:06:16.731066 Set Vref, RX VrefLevel [Byte0]: 41
7828 08:06:16.733765 [Byte1]: 41
7829 08:06:16.738208
7830 08:06:16.738326 Set Vref, RX VrefLevel [Byte0]: 42
7831 08:06:16.741541 [Byte1]: 42
7832 08:06:16.745784
7833 08:06:16.745860 Set Vref, RX VrefLevel [Byte0]: 43
7834 08:06:16.748877 [Byte1]: 43
7835 08:06:16.753795
7836 08:06:16.753894 Set Vref, RX VrefLevel [Byte0]: 44
7837 08:06:16.756964 [Byte1]: 44
7838 08:06:16.760884
7839 08:06:16.760982 Set Vref, RX VrefLevel [Byte0]: 45
7840 08:06:16.764487 [Byte1]: 45
7841 08:06:16.768486
7842 08:06:16.768587 Set Vref, RX VrefLevel [Byte0]: 46
7843 08:06:16.771846 [Byte1]: 46
7844 08:06:16.776473
7845 08:06:16.776572 Set Vref, RX VrefLevel [Byte0]: 47
7846 08:06:16.779583 [Byte1]: 47
7847 08:06:16.784187
7848 08:06:16.784284 Set Vref, RX VrefLevel [Byte0]: 48
7849 08:06:16.787134 [Byte1]: 48
7850 08:06:16.791414
7851 08:06:16.791517 Set Vref, RX VrefLevel [Byte0]: 49
7852 08:06:16.794637 [Byte1]: 49
7853 08:06:16.799088
7854 08:06:16.799190 Set Vref, RX VrefLevel [Byte0]: 50
7855 08:06:16.802893 [Byte1]: 50
7856 08:06:16.806489
7857 08:06:16.806587 Set Vref, RX VrefLevel [Byte0]: 51
7858 08:06:16.809815 [Byte1]: 51
7859 08:06:16.814277
7860 08:06:16.814376 Set Vref, RX VrefLevel [Byte0]: 52
7861 08:06:16.817714 [Byte1]: 52
7862 08:06:16.822021
7863 08:06:16.822123 Set Vref, RX VrefLevel [Byte0]: 53
7864 08:06:16.825396 [Byte1]: 53
7865 08:06:16.829479
7866 08:06:16.829579 Set Vref, RX VrefLevel [Byte0]: 54
7867 08:06:16.832841 [Byte1]: 54
7868 08:06:16.837139
7869 08:06:16.837240 Set Vref, RX VrefLevel [Byte0]: 55
7870 08:06:16.840740 [Byte1]: 55
7871 08:06:16.844973
7872 08:06:16.845048 Set Vref, RX VrefLevel [Byte0]: 56
7873 08:06:16.847851 [Byte1]: 56
7874 08:06:16.852345
7875 08:06:16.852442 Set Vref, RX VrefLevel [Byte0]: 57
7876 08:06:16.855677 [Byte1]: 57
7877 08:06:16.859783
7878 08:06:16.859885 Set Vref, RX VrefLevel [Byte0]: 58
7879 08:06:16.863269 [Byte1]: 58
7880 08:06:16.867892
7881 08:06:16.867963 Set Vref, RX VrefLevel [Byte0]: 59
7882 08:06:16.871148 [Byte1]: 59
7883 08:06:16.875436
7884 08:06:16.875538 Set Vref, RX VrefLevel [Byte0]: 60
7885 08:06:16.878589 [Byte1]: 60
7886 08:06:16.882665
7887 08:06:16.882794 Set Vref, RX VrefLevel [Byte0]: 61
7888 08:06:16.886636 [Byte1]: 61
7889 08:06:16.890474
7890 08:06:16.890573 Set Vref, RX VrefLevel [Byte0]: 62
7891 08:06:16.894283 [Byte1]: 62
7892 08:06:16.897856
7893 08:06:16.897959 Set Vref, RX VrefLevel [Byte0]: 63
7894 08:06:16.901211 [Byte1]: 63
7895 08:06:16.905769
7896 08:06:16.905845 Set Vref, RX VrefLevel [Byte0]: 64
7897 08:06:16.908772 [Byte1]: 64
7898 08:06:16.913167
7899 08:06:16.913269 Set Vref, RX VrefLevel [Byte0]: 65
7900 08:06:16.916834 [Byte1]: 65
7901 08:06:16.920983
7902 08:06:16.921081 Set Vref, RX VrefLevel [Byte0]: 66
7903 08:06:16.924047 [Byte1]: 66
7904 08:06:16.928675
7905 08:06:16.928772 Set Vref, RX VrefLevel [Byte0]: 67
7906 08:06:16.931856 [Byte1]: 67
7907 08:06:16.936430
7908 08:06:16.936528 Set Vref, RX VrefLevel [Byte0]: 68
7909 08:06:16.939506 [Byte1]: 68
7910 08:06:16.943951
7911 08:06:16.944049 Set Vref, RX VrefLevel [Byte0]: 69
7912 08:06:16.947247 [Byte1]: 69
7913 08:06:16.951275
7914 08:06:16.954846 Set Vref, RX VrefLevel [Byte0]: 70
7915 08:06:16.954949 [Byte1]: 70
7916 08:06:16.959126
7917 08:06:16.959196 Set Vref, RX VrefLevel [Byte0]: 71
7918 08:06:16.962256 [Byte1]: 71
7919 08:06:16.966516
7920 08:06:16.966617 Set Vref, RX VrefLevel [Byte0]: 72
7921 08:06:16.969649 [Byte1]: 72
7922 08:06:16.974547
7923 08:06:16.974650 Set Vref, RX VrefLevel [Byte0]: 73
7924 08:06:16.977328 [Byte1]: 73
7925 08:06:16.981704
7926 08:06:16.981793 Set Vref, RX VrefLevel [Byte0]: 74
7927 08:06:16.985068 [Byte1]: 74
7928 08:06:16.989272
7929 08:06:16.989374 Set Vref, RX VrefLevel [Byte0]: 75
7930 08:06:16.993289 [Byte1]: 75
7931 08:06:16.997248
7932 08:06:16.997347 Set Vref, RX VrefLevel [Byte0]: 76
7933 08:06:17.000581 [Byte1]: 76
7934 08:06:17.004619
7935 08:06:17.004717 Final RX Vref Byte 0 = 62 to rank0
7936 08:06:17.007994 Final RX Vref Byte 1 = 61 to rank0
7937 08:06:17.011443 Final RX Vref Byte 0 = 62 to rank1
7938 08:06:17.014760 Final RX Vref Byte 1 = 61 to rank1==
7939 08:06:17.017853 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 08:06:17.024603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 08:06:17.024720 ==
7942 08:06:17.024816 DQS Delay:
7943 08:06:17.027889 DQS0 = 0, DQS1 = 0
7944 08:06:17.027958 DQM Delay:
7945 08:06:17.028019 DQM0 = 129, DQM1 = 122
7946 08:06:17.031065 DQ Delay:
7947 08:06:17.034266 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7948 08:06:17.037706 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
7949 08:06:17.041082 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7950 08:06:17.044474 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
7951 08:06:17.044573
7952 08:06:17.044660
7953 08:06:17.044745
7954 08:06:17.047586 [DramC_TX_OE_Calibration] TA2
7955 08:06:17.050951 Original DQ_B0 (3 6) =30, OEN = 27
7956 08:06:17.054130 Original DQ_B1 (3 6) =30, OEN = 27
7957 08:06:17.057479 24, 0x0, End_B0=24 End_B1=24
7958 08:06:17.057566 25, 0x0, End_B0=25 End_B1=25
7959 08:06:17.061037 26, 0x0, End_B0=26 End_B1=26
7960 08:06:17.064071 27, 0x0, End_B0=27 End_B1=27
7961 08:06:17.067455 28, 0x0, End_B0=28 End_B1=28
7962 08:06:17.070948 29, 0x0, End_B0=29 End_B1=29
7963 08:06:17.071021 30, 0x0, End_B0=30 End_B1=30
7964 08:06:17.074244 31, 0x4141, End_B0=30 End_B1=30
7965 08:06:17.077681 Byte0 end_step=30 best_step=27
7966 08:06:17.080773 Byte1 end_step=30 best_step=27
7967 08:06:17.084086 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 08:06:17.087484 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 08:06:17.087570
7970 08:06:17.087631
7971 08:06:17.094107 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7972 08:06:17.097732 CH0 RK0: MR19=303, MR18=1206
7973 08:06:17.104331 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7974 08:06:17.104432
7975 08:06:17.107490 ----->DramcWriteLeveling(PI) begin...
7976 08:06:17.107564 ==
7977 08:06:17.110799 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 08:06:17.114067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 08:06:17.114163 ==
7980 08:06:17.117923 Write leveling (Byte 0): 32 => 32
7981 08:06:17.120806 Write leveling (Byte 1): 27 => 27
7982 08:06:17.124612 DramcWriteLeveling(PI) end<-----
7983 08:06:17.124686
7984 08:06:17.124747 ==
7985 08:06:17.127390 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 08:06:17.130561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 08:06:17.130668 ==
7988 08:06:17.134019 [Gating] SW mode calibration
7989 08:06:17.140756 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 08:06:17.147257 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 08:06:17.150761 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 08:06:17.154222 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 08:06:17.160664 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7994 08:06:17.164123 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7995 08:06:17.167629 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7996 08:06:17.174671 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7997 08:06:17.177254 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 08:06:17.180918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 08:06:17.187641 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 08:06:17.191065 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 08:06:17.194204 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8002 08:06:17.200966 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8003 08:06:17.204420 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8004 08:06:17.207512 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8005 08:06:17.210958 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8006 08:06:17.217486 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 08:06:17.220912 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 08:06:17.224140 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 08:06:17.230983 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8010 08:06:17.234313 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8011 08:06:17.237544 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8012 08:06:17.244341 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
8013 08:06:17.247667 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 08:06:17.250834 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 08:06:17.257660 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 08:06:17.261331 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 08:06:17.264402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 08:06:17.271252 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8019 08:06:17.274471 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8020 08:06:17.277926 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8021 08:06:17.284444 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8022 08:06:17.287783 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 08:06:17.291221 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 08:06:17.294462 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 08:06:17.301183 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 08:06:17.304606 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 08:06:17.308066 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 08:06:17.314798 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 08:06:17.318114 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 08:06:17.321161 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 08:06:17.327754 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 08:06:17.331133 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 08:06:17.334669 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 08:06:17.341165 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8035 08:06:17.341268 Total UI for P1: 0, mck2ui 16
8036 08:06:17.348581 best dqsien dly found for B0: ( 1, 9, 8)
8037 08:06:17.351582 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 08:06:17.354716 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8039 08:06:17.358274 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8040 08:06:17.365012 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 08:06:17.368690 Total UI for P1: 0, mck2ui 16
8042 08:06:17.371547 best dqsien dly found for B1: ( 1, 9, 20)
8043 08:06:17.374839 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8044 08:06:17.377837 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8045 08:06:17.377908
8046 08:06:17.381883 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8047 08:06:17.384713 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8048 08:06:17.388009 [Gating] SW calibration Done
8049 08:06:17.388105 ==
8050 08:06:17.391586 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 08:06:17.395171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 08:06:17.395270 ==
8053 08:06:17.397929 RX Vref Scan: 0
8054 08:06:17.398026
8055 08:06:17.398117 RX Vref 0 -> 0, step: 1
8056 08:06:17.401543
8057 08:06:17.401640 RX Delay 0 -> 252, step: 8
8058 08:06:17.405042 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8059 08:06:17.411894 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8060 08:06:17.415240 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8061 08:06:17.418120 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8062 08:06:17.421959 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8063 08:06:17.425306 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8064 08:06:17.432012 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8065 08:06:17.434970 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8066 08:06:17.438308 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8067 08:06:17.441605 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8068 08:06:17.445362 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8069 08:06:17.451392 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8070 08:06:17.454877 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8071 08:06:17.458028 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8072 08:06:17.461670 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8073 08:06:17.464782 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8074 08:06:17.468485 ==
8075 08:06:17.468566 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 08:06:17.475001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 08:06:17.475083 ==
8078 08:06:17.475147 DQS Delay:
8079 08:06:17.478659 DQS0 = 0, DQS1 = 0
8080 08:06:17.478747 DQM Delay:
8081 08:06:17.481536 DQM0 = 130, DQM1 = 125
8082 08:06:17.481616 DQ Delay:
8083 08:06:17.484925 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8084 08:06:17.488265 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8085 08:06:17.491467 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8086 08:06:17.495126 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8087 08:06:17.495201
8088 08:06:17.495262
8089 08:06:17.495339 ==
8090 08:06:17.498043 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 08:06:17.504975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 08:06:17.505085 ==
8093 08:06:17.505177
8094 08:06:17.505263
8095 08:06:17.505347 TX Vref Scan disable
8096 08:06:17.508347 == TX Byte 0 ==
8097 08:06:17.511745 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8098 08:06:17.518199 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8099 08:06:17.518274 == TX Byte 1 ==
8100 08:06:17.522026 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8101 08:06:17.528740 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8102 08:06:17.528822 ==
8103 08:06:17.531420 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 08:06:17.534652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 08:06:17.534769 ==
8106 08:06:17.548862
8107 08:06:17.552132 TX Vref early break, caculate TX vref
8108 08:06:17.555521 TX Vref=16, minBit 5, minWin=21, winSum=366
8109 08:06:17.558931 TX Vref=18, minBit 1, minWin=22, winSum=375
8110 08:06:17.562849 TX Vref=20, minBit 5, minWin=23, winSum=387
8111 08:06:17.565565 TX Vref=22, minBit 0, minWin=24, winSum=395
8112 08:06:17.569171 TX Vref=24, minBit 1, minWin=24, winSum=401
8113 08:06:17.576054 TX Vref=26, minBit 4, minWin=24, winSum=413
8114 08:06:17.579464 TX Vref=28, minBit 0, minWin=25, winSum=418
8115 08:06:17.582801 TX Vref=30, minBit 0, minWin=25, winSum=414
8116 08:06:17.585868 TX Vref=32, minBit 0, minWin=24, winSum=408
8117 08:06:17.589069 TX Vref=34, minBit 1, minWin=23, winSum=399
8118 08:06:17.592209 TX Vref=36, minBit 1, minWin=23, winSum=388
8119 08:06:17.599367 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8120 08:06:17.599450
8121 08:06:17.602262 Final TX Range 0 Vref 28
8122 08:06:17.602344
8123 08:06:17.602407 ==
8124 08:06:17.605711 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 08:06:17.608953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 08:06:17.609053 ==
8127 08:06:17.609119
8128 08:06:17.609179
8129 08:06:17.612200 TX Vref Scan disable
8130 08:06:17.619003 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8131 08:06:17.619085 == TX Byte 0 ==
8132 08:06:17.622394 u2DelayCellOfst[0]=14 cells (4 PI)
8133 08:06:17.626117 u2DelayCellOfst[1]=17 cells (5 PI)
8134 08:06:17.629168 u2DelayCellOfst[2]=10 cells (3 PI)
8135 08:06:17.632636 u2DelayCellOfst[3]=10 cells (3 PI)
8136 08:06:17.636045 u2DelayCellOfst[4]=10 cells (3 PI)
8137 08:06:17.638939 u2DelayCellOfst[5]=0 cells (0 PI)
8138 08:06:17.642333 u2DelayCellOfst[6]=17 cells (5 PI)
8139 08:06:17.645786 u2DelayCellOfst[7]=21 cells (6 PI)
8140 08:06:17.649211 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8141 08:06:17.652627 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8142 08:06:17.655710 == TX Byte 1 ==
8143 08:06:17.655790 u2DelayCellOfst[8]=0 cells (0 PI)
8144 08:06:17.659192 u2DelayCellOfst[9]=0 cells (0 PI)
8145 08:06:17.662569 u2DelayCellOfst[10]=3 cells (1 PI)
8146 08:06:17.665871 u2DelayCellOfst[11]=0 cells (0 PI)
8147 08:06:17.668934 u2DelayCellOfst[12]=14 cells (4 PI)
8148 08:06:17.673091 u2DelayCellOfst[13]=7 cells (2 PI)
8149 08:06:17.675781 u2DelayCellOfst[14]=17 cells (5 PI)
8150 08:06:17.679236 u2DelayCellOfst[15]=10 cells (3 PI)
8151 08:06:17.682676 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8152 08:06:17.686089 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8153 08:06:17.689766 DramC Write-DBI on
8154 08:06:17.689847 ==
8155 08:06:17.692577 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 08:06:17.696143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 08:06:17.696264 ==
8158 08:06:17.696373
8159 08:06:17.696464
8160 08:06:17.699188 TX Vref Scan disable
8161 08:06:17.702542 == TX Byte 0 ==
8162 08:06:17.706062 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8163 08:06:17.709448 == TX Byte 1 ==
8164 08:06:17.712884 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8165 08:06:17.712959 DramC Write-DBI off
8166 08:06:17.713028
8167 08:06:17.716238 [DATLAT]
8168 08:06:17.716313 Freq=1600, CH0 RK1
8169 08:06:17.716374
8170 08:06:17.719319 DATLAT Default: 0xf
8171 08:06:17.719393 0, 0xFFFF, sum = 0
8172 08:06:17.723015 1, 0xFFFF, sum = 0
8173 08:06:17.723090 2, 0xFFFF, sum = 0
8174 08:06:17.726286 3, 0xFFFF, sum = 0
8175 08:06:17.726400 4, 0xFFFF, sum = 0
8176 08:06:17.729374 5, 0xFFFF, sum = 0
8177 08:06:17.729453 6, 0xFFFF, sum = 0
8178 08:06:17.732575 7, 0xFFFF, sum = 0
8179 08:06:17.732647 8, 0xFFFF, sum = 0
8180 08:06:17.735893 9, 0xFFFF, sum = 0
8181 08:06:17.735995 10, 0xFFFF, sum = 0
8182 08:06:17.739542 11, 0xFFFF, sum = 0
8183 08:06:17.742831 12, 0xFFFF, sum = 0
8184 08:06:17.742941 13, 0xFFFF, sum = 0
8185 08:06:17.745874 14, 0x0, sum = 1
8186 08:06:17.745946 15, 0x0, sum = 2
8187 08:06:17.749768 16, 0x0, sum = 3
8188 08:06:17.749869 17, 0x0, sum = 4
8189 08:06:17.749965 best_step = 15
8190 08:06:17.750062
8191 08:06:17.752944 ==
8192 08:06:17.753044 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 08:06:17.759249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 08:06:17.759325 ==
8195 08:06:17.759386 RX Vref Scan: 0
8196 08:06:17.759444
8197 08:06:17.762941 RX Vref 0 -> 0, step: 1
8198 08:06:17.763040
8199 08:06:17.766119 RX Delay 11 -> 252, step: 4
8200 08:06:17.769352 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8201 08:06:17.772555 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8202 08:06:17.779211 iDelay=195, Bit 2, Center 122 (67 ~ 178) 112
8203 08:06:17.783017 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8204 08:06:17.786889 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8205 08:06:17.789660 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8206 08:06:17.792577 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8207 08:06:17.796218 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8208 08:06:17.802656 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8209 08:06:17.805967 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8210 08:06:17.809591 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8211 08:06:17.812957 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8212 08:06:17.819481 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8213 08:06:17.822839 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8214 08:06:17.826057 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8215 08:06:17.829391 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8216 08:06:17.829495 ==
8217 08:06:17.832914 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 08:06:17.836069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 08:06:17.839502 ==
8220 08:06:17.839576 DQS Delay:
8221 08:06:17.839637 DQS0 = 0, DQS1 = 0
8222 08:06:17.843208 DQM Delay:
8223 08:06:17.843316 DQM0 = 127, DQM1 = 122
8224 08:06:17.846087 DQ Delay:
8225 08:06:17.849658 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8226 08:06:17.853096 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =136
8227 08:06:17.856171 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8228 08:06:17.860051 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8229 08:06:17.860124
8230 08:06:17.860200
8231 08:06:17.860261
8232 08:06:17.863081 [DramC_TX_OE_Calibration] TA2
8233 08:06:17.866150 Original DQ_B0 (3 6) =30, OEN = 27
8234 08:06:17.869520 Original DQ_B1 (3 6) =30, OEN = 27
8235 08:06:17.869605 24, 0x0, End_B0=24 End_B1=24
8236 08:06:17.873118 25, 0x0, End_B0=25 End_B1=25
8237 08:06:17.876044 26, 0x0, End_B0=26 End_B1=26
8238 08:06:17.879375 27, 0x0, End_B0=27 End_B1=27
8239 08:06:17.882680 28, 0x0, End_B0=28 End_B1=28
8240 08:06:17.882796 29, 0x0, End_B0=29 End_B1=29
8241 08:06:17.886268 30, 0x0, End_B0=30 End_B1=30
8242 08:06:17.889527 31, 0x4141, End_B0=30 End_B1=30
8243 08:06:17.892529 Byte0 end_step=30 best_step=27
8244 08:06:17.895941 Byte1 end_step=30 best_step=27
8245 08:06:17.899214 Byte0 TX OE(2T, 0.5T) = (3, 3)
8246 08:06:17.899295 Byte1 TX OE(2T, 0.5T) = (3, 3)
8247 08:06:17.899360
8248 08:06:17.899419
8249 08:06:17.909385 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8250 08:06:17.913057 CH0 RK1: MR19=303, MR18=1A0F
8251 08:06:17.919625 CH0_RK1: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8252 08:06:17.919706 [RxdqsGatingPostProcess] freq 1600
8253 08:06:17.926206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8254 08:06:17.929310 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 08:06:17.932804 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 08:06:17.936326 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 08:06:17.939185 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 08:06:17.942541 best DQS0 dly(2T, 0.5T) = (1, 1)
8259 08:06:17.945873 best DQS1 dly(2T, 0.5T) = (1, 1)
8260 08:06:17.949302 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8261 08:06:17.949383 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8262 08:06:17.952837 Pre-setting of DQS Precalculation
8263 08:06:17.959426 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8264 08:06:17.959508 ==
8265 08:06:17.962773 Dram Type= 6, Freq= 0, CH_1, rank 0
8266 08:06:17.966029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 08:06:17.966111 ==
8268 08:06:17.972622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8269 08:06:17.975986 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8270 08:06:17.979703 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8271 08:06:17.986364 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8272 08:06:17.995234 [CA 0] Center 42 (14~71) winsize 58
8273 08:06:17.998975 [CA 1] Center 42 (13~71) winsize 59
8274 08:06:18.002281 [CA 2] Center 37 (8~66) winsize 59
8275 08:06:18.005599 [CA 3] Center 36 (7~65) winsize 59
8276 08:06:18.008766 [CA 4] Center 37 (8~67) winsize 60
8277 08:06:18.012026 [CA 5] Center 36 (7~66) winsize 60
8278 08:06:18.012107
8279 08:06:18.015072 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8280 08:06:18.015153
8281 08:06:18.018900 [CATrainingPosCal] consider 1 rank data
8282 08:06:18.021730 u2DelayCellTimex100 = 275/100 ps
8283 08:06:18.025274 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8284 08:06:18.031579 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8285 08:06:18.035720 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8286 08:06:18.038786 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8287 08:06:18.041799 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8288 08:06:18.045376 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8289 08:06:18.045457
8290 08:06:18.048772 CA PerBit enable=1, Macro0, CA PI delay=36
8291 08:06:18.048852
8292 08:06:18.051929 [CBTSetCACLKResult] CA Dly = 36
8293 08:06:18.055089 CS Dly: 9 (0~40)
8294 08:06:18.058436 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8295 08:06:18.061672 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8296 08:06:18.061753 ==
8297 08:06:18.065021 Dram Type= 6, Freq= 0, CH_1, rank 1
8298 08:06:18.068419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 08:06:18.068500 ==
8300 08:06:18.075354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8301 08:06:18.078342 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8302 08:06:18.085417 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8303 08:06:18.088786 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8304 08:06:18.098362 [CA 0] Center 43 (14~72) winsize 59
8305 08:06:18.101586 [CA 1] Center 43 (14~72) winsize 59
8306 08:06:18.105449 [CA 2] Center 37 (9~66) winsize 58
8307 08:06:18.108310 [CA 3] Center 37 (8~66) winsize 59
8308 08:06:18.111880 [CA 4] Center 37 (8~67) winsize 60
8309 08:06:18.115241 [CA 5] Center 37 (8~66) winsize 59
8310 08:06:18.115358
8311 08:06:18.118426 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8312 08:06:18.118507
8313 08:06:18.122320 [CATrainingPosCal] consider 2 rank data
8314 08:06:18.125241 u2DelayCellTimex100 = 275/100 ps
8315 08:06:18.128889 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8316 08:06:18.135209 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8317 08:06:18.138429 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8318 08:06:18.141883 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8319 08:06:18.145350 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8320 08:06:18.148908 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8321 08:06:18.148988
8322 08:06:18.151998 CA PerBit enable=1, Macro0, CA PI delay=36
8323 08:06:18.152078
8324 08:06:18.155164 [CBTSetCACLKResult] CA Dly = 36
8325 08:06:18.155245 CS Dly: 11 (0~44)
8326 08:06:18.161995 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8327 08:06:18.165089 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8328 08:06:18.165170
8329 08:06:18.168571 ----->DramcWriteLeveling(PI) begin...
8330 08:06:18.168652 ==
8331 08:06:18.171932 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 08:06:18.175274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 08:06:18.175354 ==
8334 08:06:18.178611 Write leveling (Byte 0): 24 => 24
8335 08:06:18.182350 Write leveling (Byte 1): 29 => 29
8336 08:06:18.185791 DramcWriteLeveling(PI) end<-----
8337 08:06:18.185871
8338 08:06:18.185934 ==
8339 08:06:18.188715 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 08:06:18.192009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 08:06:18.195677 ==
8342 08:06:18.195757 [Gating] SW mode calibration
8343 08:06:18.202143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8344 08:06:18.209094 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8345 08:06:18.212141 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 08:06:18.219077 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 08:06:18.222440 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 08:06:18.225954 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 08:06:18.232393 1 4 16 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
8350 08:06:18.235695 1 4 20 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8351 08:06:18.239271 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 08:06:18.242294 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 08:06:18.249157 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 08:06:18.252480 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 08:06:18.255994 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 08:06:18.262534 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8357 08:06:18.265877 1 5 16 | B1->B0 | 2525 2e2e | 0 0 | (1 0) (0 1)
8358 08:06:18.268817 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 08:06:18.275475 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 08:06:18.279232 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 08:06:18.282170 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 08:06:18.289118 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 08:06:18.292199 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 08:06:18.295538 1 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8365 08:06:18.302655 1 6 16 | B1->B0 | 3a3a 3232 | 0 0 | (0 0) (0 0)
8366 08:06:18.305916 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 08:06:18.308760 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 08:06:18.315720 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 08:06:18.318814 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 08:06:18.322412 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 08:06:18.328902 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 08:06:18.332269 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 08:06:18.335777 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8374 08:06:18.338950 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8375 08:06:18.345900 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 08:06:18.349250 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 08:06:18.352389 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 08:06:18.359571 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 08:06:18.362980 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 08:06:18.366148 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 08:06:18.372907 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 08:06:18.375846 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 08:06:18.379116 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 08:06:18.385660 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 08:06:18.389438 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 08:06:18.392722 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 08:06:18.399423 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 08:06:18.403013 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 08:06:18.405816 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8390 08:06:18.409169 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 08:06:18.412791 Total UI for P1: 0, mck2ui 16
8392 08:06:18.415745 best dqsien dly found for B0: ( 1, 9, 16)
8393 08:06:18.419195 Total UI for P1: 0, mck2ui 16
8394 08:06:18.422769 best dqsien dly found for B1: ( 1, 9, 16)
8395 08:06:18.425746 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8396 08:06:18.429637 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8397 08:06:18.432833
8398 08:06:18.435918 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8399 08:06:18.439276 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8400 08:06:18.442540 [Gating] SW calibration Done
8401 08:06:18.442621 ==
8402 08:06:18.446400 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 08:06:18.449331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 08:06:18.449413 ==
8405 08:06:18.449477 RX Vref Scan: 0
8406 08:06:18.452877
8407 08:06:18.452958 RX Vref 0 -> 0, step: 1
8408 08:06:18.453021
8409 08:06:18.456189 RX Delay 0 -> 252, step: 8
8410 08:06:18.459335 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8411 08:06:18.463045 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8412 08:06:18.469199 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8413 08:06:18.472579 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8414 08:06:18.475949 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8415 08:06:18.479436 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8416 08:06:18.482460 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8417 08:06:18.486040 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8418 08:06:18.492572 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8419 08:06:18.495923 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8420 08:06:18.499588 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8421 08:06:18.502840 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8422 08:06:18.509027 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8423 08:06:18.512762 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8424 08:06:18.515928 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8425 08:06:18.519358 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8426 08:06:18.519438 ==
8427 08:06:18.522388 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 08:06:18.526238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 08:06:18.529200 ==
8430 08:06:18.529281 DQS Delay:
8431 08:06:18.529345 DQS0 = 0, DQS1 = 0
8432 08:06:18.532674 DQM Delay:
8433 08:06:18.532754 DQM0 = 135, DQM1 = 127
8434 08:06:18.535912 DQ Delay:
8435 08:06:18.539282 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8436 08:06:18.542990 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8437 08:06:18.546560 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8438 08:06:18.549615 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8439 08:06:18.549695
8440 08:06:18.549759
8441 08:06:18.549819 ==
8442 08:06:18.553232 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 08:06:18.555853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 08:06:18.555936 ==
8445 08:06:18.556000
8446 08:06:18.556060
8447 08:06:18.559182 TX Vref Scan disable
8448 08:06:18.562556 == TX Byte 0 ==
8449 08:06:18.566058 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8450 08:06:18.569788 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8451 08:06:18.573014 == TX Byte 1 ==
8452 08:06:18.575996 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8453 08:06:18.579547 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8454 08:06:18.579628 ==
8455 08:06:18.582966 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 08:06:18.586580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 08:06:18.589544 ==
8458 08:06:18.602377
8459 08:06:18.605302 TX Vref early break, caculate TX vref
8460 08:06:18.608827 TX Vref=16, minBit 5, minWin=21, winSum=363
8461 08:06:18.612309 TX Vref=18, minBit 8, minWin=21, winSum=372
8462 08:06:18.615460 TX Vref=20, minBit 8, minWin=22, winSum=385
8463 08:06:18.618489 TX Vref=22, minBit 8, minWin=22, winSum=393
8464 08:06:18.621729 TX Vref=24, minBit 8, minWin=23, winSum=403
8465 08:06:18.628549 TX Vref=26, minBit 8, minWin=24, winSum=411
8466 08:06:18.632080 TX Vref=28, minBit 8, minWin=25, winSum=420
8467 08:06:18.635321 TX Vref=30, minBit 8, minWin=24, winSum=416
8468 08:06:18.638578 TX Vref=32, minBit 0, minWin=25, winSum=411
8469 08:06:18.642268 TX Vref=34, minBit 1, minWin=23, winSum=399
8470 08:06:18.645661 TX Vref=36, minBit 8, minWin=23, winSum=387
8471 08:06:18.651970 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8472 08:06:18.652052
8473 08:06:18.655579 Final TX Range 0 Vref 28
8474 08:06:18.655661
8475 08:06:18.655725 ==
8476 08:06:18.659105 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 08:06:18.662010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 08:06:18.662091 ==
8479 08:06:18.662155
8480 08:06:18.662214
8481 08:06:18.665905 TX Vref Scan disable
8482 08:06:18.672598 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8483 08:06:18.672680 == TX Byte 0 ==
8484 08:06:18.675470 u2DelayCellOfst[0]=17 cells (5 PI)
8485 08:06:18.678857 u2DelayCellOfst[1]=10 cells (3 PI)
8486 08:06:18.682292 u2DelayCellOfst[2]=0 cells (0 PI)
8487 08:06:18.685398 u2DelayCellOfst[3]=7 cells (2 PI)
8488 08:06:18.688628 u2DelayCellOfst[4]=7 cells (2 PI)
8489 08:06:18.692074 u2DelayCellOfst[5]=17 cells (5 PI)
8490 08:06:18.695659 u2DelayCellOfst[6]=17 cells (5 PI)
8491 08:06:18.695740 u2DelayCellOfst[7]=7 cells (2 PI)
8492 08:06:18.702032 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8493 08:06:18.705447 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8494 08:06:18.705528 == TX Byte 1 ==
8495 08:06:18.708826 u2DelayCellOfst[8]=0 cells (0 PI)
8496 08:06:18.712092 u2DelayCellOfst[9]=7 cells (2 PI)
8497 08:06:18.715813 u2DelayCellOfst[10]=10 cells (3 PI)
8498 08:06:18.718946 u2DelayCellOfst[11]=7 cells (2 PI)
8499 08:06:18.722279 u2DelayCellOfst[12]=14 cells (4 PI)
8500 08:06:18.725649 u2DelayCellOfst[13]=17 cells (5 PI)
8501 08:06:18.729115 u2DelayCellOfst[14]=17 cells (5 PI)
8502 08:06:18.732217 u2DelayCellOfst[15]=17 cells (5 PI)
8503 08:06:18.735466 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8504 08:06:18.739149 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8505 08:06:18.742378 DramC Write-DBI on
8506 08:06:18.742485 ==
8507 08:06:18.745518 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 08:06:18.748950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 08:06:18.749041 ==
8510 08:06:18.749104
8511 08:06:18.752063
8512 08:06:18.752140 TX Vref Scan disable
8513 08:06:18.755793 == TX Byte 0 ==
8514 08:06:18.758998 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8515 08:06:18.762175 == TX Byte 1 ==
8516 08:06:18.765877 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8517 08:06:18.765952 DramC Write-DBI off
8518 08:06:18.766013
8519 08:06:18.769187 [DATLAT]
8520 08:06:18.769256 Freq=1600, CH1 RK0
8521 08:06:18.769316
8522 08:06:18.772721 DATLAT Default: 0xf
8523 08:06:18.772791 0, 0xFFFF, sum = 0
8524 08:06:18.775561 1, 0xFFFF, sum = 0
8525 08:06:18.775632 2, 0xFFFF, sum = 0
8526 08:06:18.778905 3, 0xFFFF, sum = 0
8527 08:06:18.779004 4, 0xFFFF, sum = 0
8528 08:06:18.782528 5, 0xFFFF, sum = 0
8529 08:06:18.782624 6, 0xFFFF, sum = 0
8530 08:06:18.785443 7, 0xFFFF, sum = 0
8531 08:06:18.785550 8, 0xFFFF, sum = 0
8532 08:06:18.789343 9, 0xFFFF, sum = 0
8533 08:06:18.789424 10, 0xFFFF, sum = 0
8534 08:06:18.792681 11, 0xFFFF, sum = 0
8535 08:06:18.795743 12, 0xFFFF, sum = 0
8536 08:06:18.795824 13, 0xFFFF, sum = 0
8537 08:06:18.798910 14, 0x0, sum = 1
8538 08:06:18.799004 15, 0x0, sum = 2
8539 08:06:18.802408 16, 0x0, sum = 3
8540 08:06:18.802518 17, 0x0, sum = 4
8541 08:06:18.802582 best_step = 15
8542 08:06:18.802641
8543 08:06:18.805505 ==
8544 08:06:18.808851 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 08:06:18.812686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 08:06:18.812780 ==
8547 08:06:18.812843 RX Vref Scan: 1
8548 08:06:18.812901
8549 08:06:18.815770 Set Vref Range= 24 -> 127
8550 08:06:18.815850
8551 08:06:18.818978 RX Vref 24 -> 127, step: 1
8552 08:06:18.819071
8553 08:06:18.822415 RX Delay 11 -> 252, step: 4
8554 08:06:18.822494
8555 08:06:18.825988 Set Vref, RX VrefLevel [Byte0]: 24
8556 08:06:18.829093 [Byte1]: 24
8557 08:06:18.829174
8558 08:06:18.832252 Set Vref, RX VrefLevel [Byte0]: 25
8559 08:06:18.835550 [Byte1]: 25
8560 08:06:18.835632
8561 08:06:18.838838 Set Vref, RX VrefLevel [Byte0]: 26
8562 08:06:18.842026 [Byte1]: 26
8563 08:06:18.845324
8564 08:06:18.845406 Set Vref, RX VrefLevel [Byte0]: 27
8565 08:06:18.848687 [Byte1]: 27
8566 08:06:18.853288
8567 08:06:18.853369 Set Vref, RX VrefLevel [Byte0]: 28
8568 08:06:18.856337 [Byte1]: 28
8569 08:06:18.861107
8570 08:06:18.861188 Set Vref, RX VrefLevel [Byte0]: 29
8571 08:06:18.864203 [Byte1]: 29
8572 08:06:18.868320
8573 08:06:18.868407 Set Vref, RX VrefLevel [Byte0]: 30
8574 08:06:18.872059 [Byte1]: 30
8575 08:06:18.876288
8576 08:06:18.876368 Set Vref, RX VrefLevel [Byte0]: 31
8577 08:06:18.879321 [Byte1]: 31
8578 08:06:18.883642
8579 08:06:18.883723 Set Vref, RX VrefLevel [Byte0]: 32
8580 08:06:18.886855 [Byte1]: 32
8581 08:06:18.891239
8582 08:06:18.891327 Set Vref, RX VrefLevel [Byte0]: 33
8583 08:06:18.894628 [Byte1]: 33
8584 08:06:18.899132
8585 08:06:18.899213 Set Vref, RX VrefLevel [Byte0]: 34
8586 08:06:18.902244 [Byte1]: 34
8587 08:06:18.906866
8588 08:06:18.906946 Set Vref, RX VrefLevel [Byte0]: 35
8589 08:06:18.909827 [Byte1]: 35
8590 08:06:18.914191
8591 08:06:18.914280 Set Vref, RX VrefLevel [Byte0]: 36
8592 08:06:18.917302 [Byte1]: 36
8593 08:06:18.921689
8594 08:06:18.921762 Set Vref, RX VrefLevel [Byte0]: 37
8595 08:06:18.924941 [Byte1]: 37
8596 08:06:18.929401
8597 08:06:18.929481 Set Vref, RX VrefLevel [Byte0]: 38
8598 08:06:18.932656 [Byte1]: 38
8599 08:06:18.936759
8600 08:06:18.936839 Set Vref, RX VrefLevel [Byte0]: 39
8601 08:06:18.940446 [Byte1]: 39
8602 08:06:18.944465
8603 08:06:18.944545 Set Vref, RX VrefLevel [Byte0]: 40
8604 08:06:18.947570 [Byte1]: 40
8605 08:06:18.951992
8606 08:06:18.952076 Set Vref, RX VrefLevel [Byte0]: 41
8607 08:06:18.955483 [Byte1]: 41
8608 08:06:18.959969
8609 08:06:18.960049 Set Vref, RX VrefLevel [Byte0]: 42
8610 08:06:18.963524 [Byte1]: 42
8611 08:06:18.967160
8612 08:06:18.967241 Set Vref, RX VrefLevel [Byte0]: 43
8613 08:06:18.970677 [Byte1]: 43
8614 08:06:18.974813
8615 08:06:18.974893 Set Vref, RX VrefLevel [Byte0]: 44
8616 08:06:18.978556 [Byte1]: 44
8617 08:06:18.982351
8618 08:06:18.982431 Set Vref, RX VrefLevel [Byte0]: 45
8619 08:06:18.985726 [Byte1]: 45
8620 08:06:18.990015
8621 08:06:18.990095 Set Vref, RX VrefLevel [Byte0]: 46
8622 08:06:18.993491 [Byte1]: 46
8623 08:06:18.997757
8624 08:06:18.997863 Set Vref, RX VrefLevel [Byte0]: 47
8625 08:06:19.001946 [Byte1]: 47
8626 08:06:19.005402
8627 08:06:19.005482 Set Vref, RX VrefLevel [Byte0]: 48
8628 08:06:19.009011 [Byte1]: 48
8629 08:06:19.012939
8630 08:06:19.013019 Set Vref, RX VrefLevel [Byte0]: 49
8631 08:06:19.016352 [Byte1]: 49
8632 08:06:19.020491
8633 08:06:19.020571 Set Vref, RX VrefLevel [Byte0]: 50
8634 08:06:19.023976 [Byte1]: 50
8635 08:06:19.028559
8636 08:06:19.028639 Set Vref, RX VrefLevel [Byte0]: 51
8637 08:06:19.031388 [Byte1]: 51
8638 08:06:19.035802
8639 08:06:19.035882 Set Vref, RX VrefLevel [Byte0]: 52
8640 08:06:19.039276 [Byte1]: 52
8641 08:06:19.043818
8642 08:06:19.043899 Set Vref, RX VrefLevel [Byte0]: 53
8643 08:06:19.046675 [Byte1]: 53
8644 08:06:19.051544
8645 08:06:19.051623 Set Vref, RX VrefLevel [Byte0]: 54
8646 08:06:19.054286 [Byte1]: 54
8647 08:06:19.058808
8648 08:06:19.058889 Set Vref, RX VrefLevel [Byte0]: 55
8649 08:06:19.062162 [Byte1]: 55
8650 08:06:19.066739
8651 08:06:19.066819 Set Vref, RX VrefLevel [Byte0]: 56
8652 08:06:19.070081 [Byte1]: 56
8653 08:06:19.074024
8654 08:06:19.074104 Set Vref, RX VrefLevel [Byte0]: 57
8655 08:06:19.077039 [Byte1]: 57
8656 08:06:19.081792
8657 08:06:19.081872 Set Vref, RX VrefLevel [Byte0]: 58
8658 08:06:19.085209 [Byte1]: 58
8659 08:06:19.089104
8660 08:06:19.089184 Set Vref, RX VrefLevel [Byte0]: 59
8661 08:06:19.092294 [Byte1]: 59
8662 08:06:19.096576
8663 08:06:19.096655 Set Vref, RX VrefLevel [Byte0]: 60
8664 08:06:19.100309 [Byte1]: 60
8665 08:06:19.104500
8666 08:06:19.104580 Set Vref, RX VrefLevel [Byte0]: 61
8667 08:06:19.107676 [Byte1]: 61
8668 08:06:19.112119
8669 08:06:19.112202 Set Vref, RX VrefLevel [Byte0]: 62
8670 08:06:19.115315 [Byte1]: 62
8671 08:06:19.119675
8672 08:06:19.119755 Set Vref, RX VrefLevel [Byte0]: 63
8673 08:06:19.123183 [Byte1]: 63
8674 08:06:19.127256
8675 08:06:19.127337 Set Vref, RX VrefLevel [Byte0]: 64
8676 08:06:19.130402 [Byte1]: 64
8677 08:06:19.134885
8678 08:06:19.134965 Set Vref, RX VrefLevel [Byte0]: 65
8679 08:06:19.141291 [Byte1]: 65
8680 08:06:19.141371
8681 08:06:19.144591 Set Vref, RX VrefLevel [Byte0]: 66
8682 08:06:19.147936 [Byte1]: 66
8683 08:06:19.148017
8684 08:06:19.151753 Set Vref, RX VrefLevel [Byte0]: 67
8685 08:06:19.154963 [Byte1]: 67
8686 08:06:19.155044
8687 08:06:19.158166 Set Vref, RX VrefLevel [Byte0]: 68
8688 08:06:19.162019 [Byte1]: 68
8689 08:06:19.165641
8690 08:06:19.165721 Set Vref, RX VrefLevel [Byte0]: 69
8691 08:06:19.169078 [Byte1]: 69
8692 08:06:19.173335
8693 08:06:19.173415 Set Vref, RX VrefLevel [Byte0]: 70
8694 08:06:19.176309 [Byte1]: 70
8695 08:06:19.180264
8696 08:06:19.180344 Set Vref, RX VrefLevel [Byte0]: 71
8697 08:06:19.183734 [Byte1]: 71
8698 08:06:19.188060
8699 08:06:19.188140 Set Vref, RX VrefLevel [Byte0]: 72
8700 08:06:19.191361 [Byte1]: 72
8701 08:06:19.195978
8702 08:06:19.196059 Set Vref, RX VrefLevel [Byte0]: 73
8703 08:06:19.199003 [Byte1]: 73
8704 08:06:19.203168
8705 08:06:19.203248 Final RX Vref Byte 0 = 63 to rank0
8706 08:06:19.206927 Final RX Vref Byte 1 = 53 to rank0
8707 08:06:19.209810 Final RX Vref Byte 0 = 63 to rank1
8708 08:06:19.213819 Final RX Vref Byte 1 = 53 to rank1==
8709 08:06:19.216925 Dram Type= 6, Freq= 0, CH_1, rank 0
8710 08:06:19.220141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8711 08:06:19.223349 ==
8712 08:06:19.223430 DQS Delay:
8713 08:06:19.223494 DQS0 = 0, DQS1 = 0
8714 08:06:19.226567 DQM Delay:
8715 08:06:19.226672 DQM0 = 131, DQM1 = 124
8716 08:06:19.230280 DQ Delay:
8717 08:06:19.233297 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =132
8718 08:06:19.236614 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8719 08:06:19.240355 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8720 08:06:19.244030 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8721 08:06:19.244109
8722 08:06:19.244172
8723 08:06:19.244231
8724 08:06:19.246730 [DramC_TX_OE_Calibration] TA2
8725 08:06:19.250314 Original DQ_B0 (3 6) =30, OEN = 27
8726 08:06:19.253891 Original DQ_B1 (3 6) =30, OEN = 27
8727 08:06:19.253972 24, 0x0, End_B0=24 End_B1=24
8728 08:06:19.256757 25, 0x0, End_B0=25 End_B1=25
8729 08:06:19.260211 26, 0x0, End_B0=26 End_B1=26
8730 08:06:19.263297 27, 0x0, End_B0=27 End_B1=27
8731 08:06:19.266950 28, 0x0, End_B0=28 End_B1=28
8732 08:06:19.267033 29, 0x0, End_B0=29 End_B1=29
8733 08:06:19.270139 30, 0x0, End_B0=30 End_B1=30
8734 08:06:19.273447 31, 0x4141, End_B0=30 End_B1=30
8735 08:06:19.276807 Byte0 end_step=30 best_step=27
8736 08:06:19.280867 Byte1 end_step=30 best_step=27
8737 08:06:19.283666 Byte0 TX OE(2T, 0.5T) = (3, 3)
8738 08:06:19.283747 Byte1 TX OE(2T, 0.5T) = (3, 3)
8739 08:06:19.283810
8740 08:06:19.283868
8741 08:06:19.293748 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8742 08:06:19.296938 CH1 RK0: MR19=302, MR18=14FE
8743 08:06:19.300293 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8744 08:06:19.303726
8745 08:06:19.306773 ----->DramcWriteLeveling(PI) begin...
8746 08:06:19.306855 ==
8747 08:06:19.310450 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 08:06:19.313480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 08:06:19.313561 ==
8750 08:06:19.317259 Write leveling (Byte 0): 24 => 24
8751 08:06:19.320031 Write leveling (Byte 1): 27 => 27
8752 08:06:19.323487 DramcWriteLeveling(PI) end<-----
8753 08:06:19.323567
8754 08:06:19.323630 ==
8755 08:06:19.327455 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 08:06:19.330101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 08:06:19.330182 ==
8758 08:06:19.333389 [Gating] SW mode calibration
8759 08:06:19.340471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8760 08:06:19.347066 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8761 08:06:19.350570 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 08:06:19.353440 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 08:06:19.360680 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8764 08:06:19.363756 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8765 08:06:19.366931 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 08:06:19.370431 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 08:06:19.377424 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 08:06:19.380212 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 08:06:19.383632 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 08:06:19.390374 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8771 08:06:19.393841 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8772 08:06:19.396893 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8773 08:06:19.403681 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 08:06:19.406882 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 08:06:19.410207 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 08:06:19.417190 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 08:06:19.420627 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 08:06:19.423838 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 08:06:19.430224 1 6 8 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
8780 08:06:19.433900 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8781 08:06:19.437303 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 08:06:19.443678 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 08:06:19.447244 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 08:06:19.450356 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 08:06:19.453719 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 08:06:19.460320 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 08:06:19.463688 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8788 08:06:19.467350 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8789 08:06:19.473867 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 08:06:19.476999 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 08:06:19.480452 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 08:06:19.487151 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 08:06:19.491023 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 08:06:19.494202 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 08:06:19.500153 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 08:06:19.503663 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 08:06:19.507512 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 08:06:19.513742 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 08:06:19.517331 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 08:06:19.520510 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 08:06:19.527693 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 08:06:19.530624 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8803 08:06:19.533785 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8804 08:06:19.537246 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8805 08:06:19.543734 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 08:06:19.547270 Total UI for P1: 0, mck2ui 16
8807 08:06:19.550887 best dqsien dly found for B0: ( 1, 9, 8)
8808 08:06:19.554176 Total UI for P1: 0, mck2ui 16
8809 08:06:19.557308 best dqsien dly found for B1: ( 1, 9, 12)
8810 08:06:19.561089 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8811 08:06:19.564231 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8812 08:06:19.564312
8813 08:06:19.567416 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8814 08:06:19.570823 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8815 08:06:19.574062 [Gating] SW calibration Done
8816 08:06:19.574142 ==
8817 08:06:19.577777 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 08:06:19.580581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 08:06:19.580662 ==
8820 08:06:19.584259 RX Vref Scan: 0
8821 08:06:19.584339
8822 08:06:19.584402 RX Vref 0 -> 0, step: 1
8823 08:06:19.584461
8824 08:06:19.587305 RX Delay 0 -> 252, step: 8
8825 08:06:19.590870 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8826 08:06:19.597671 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8827 08:06:19.600926 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8828 08:06:19.604747 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8829 08:06:19.607559 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8830 08:06:19.611070 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8831 08:06:19.614000 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8832 08:06:19.621550 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8833 08:06:19.624161 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8834 08:06:19.627865 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8835 08:06:19.631319 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8836 08:06:19.634800 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8837 08:06:19.641014 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8838 08:06:19.644610 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8839 08:06:19.647778 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8840 08:06:19.651228 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8841 08:06:19.651307 ==
8842 08:06:19.654315 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 08:06:19.661450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 08:06:19.661525 ==
8845 08:06:19.661587 DQS Delay:
8846 08:06:19.661644 DQS0 = 0, DQS1 = 0
8847 08:06:19.664866 DQM Delay:
8848 08:06:19.664932 DQM0 = 133, DQM1 = 128
8849 08:06:19.667676 DQ Delay:
8850 08:06:19.671312 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8851 08:06:19.674881 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8852 08:06:19.678114 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8853 08:06:19.681583 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8854 08:06:19.681657
8855 08:06:19.681725
8856 08:06:19.681783 ==
8857 08:06:19.684480 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 08:06:19.687926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 08:06:19.688006 ==
8860 08:06:19.691157
8861 08:06:19.691224
8862 08:06:19.691288 TX Vref Scan disable
8863 08:06:19.695024 == TX Byte 0 ==
8864 08:06:19.698107 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8865 08:06:19.701192 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8866 08:06:19.704384 == TX Byte 1 ==
8867 08:06:19.707991 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8868 08:06:19.711047 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8869 08:06:19.711113 ==
8870 08:06:19.714425 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 08:06:19.721786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 08:06:19.721855 ==
8873 08:06:19.733948
8874 08:06:19.734022 TX Vref early break, caculate TX vref
8875 08:06:19.740592 TX Vref=16, minBit 8, minWin=22, winSum=380
8876 08:06:19.743937 TX Vref=18, minBit 9, minWin=23, winSum=391
8877 08:06:19.747717 TX Vref=20, minBit 13, minWin=23, winSum=399
8878 08:06:19.750757 TX Vref=22, minBit 8, minWin=24, winSum=405
8879 08:06:19.754531 TX Vref=24, minBit 0, minWin=25, winSum=413
8880 08:06:19.757557 TX Vref=26, minBit 0, minWin=25, winSum=425
8881 08:06:19.764215 TX Vref=28, minBit 9, minWin=25, winSum=426
8882 08:06:19.767495 TX Vref=30, minBit 5, minWin=25, winSum=423
8883 08:06:19.770917 TX Vref=32, minBit 0, minWin=25, winSum=418
8884 08:06:19.774465 TX Vref=34, minBit 9, minWin=24, winSum=409
8885 08:06:19.777639 TX Vref=36, minBit 0, minWin=24, winSum=401
8886 08:06:19.784016 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 28
8887 08:06:19.784099
8888 08:06:19.787508 Final TX Range 0 Vref 28
8889 08:06:19.787588
8890 08:06:19.787651 ==
8891 08:06:19.790884 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 08:06:19.794698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 08:06:19.794823 ==
8894 08:06:19.794887
8895 08:06:19.794947
8896 08:06:19.797650 TX Vref Scan disable
8897 08:06:19.804244 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8898 08:06:19.804325 == TX Byte 0 ==
8899 08:06:19.807873 u2DelayCellOfst[0]=17 cells (5 PI)
8900 08:06:19.810719 u2DelayCellOfst[1]=14 cells (4 PI)
8901 08:06:19.813917 u2DelayCellOfst[2]=0 cells (0 PI)
8902 08:06:19.817720 u2DelayCellOfst[3]=7 cells (2 PI)
8903 08:06:19.820870 u2DelayCellOfst[4]=7 cells (2 PI)
8904 08:06:19.823932 u2DelayCellOfst[5]=17 cells (5 PI)
8905 08:06:19.827480 u2DelayCellOfst[6]=17 cells (5 PI)
8906 08:06:19.827560 u2DelayCellOfst[7]=7 cells (2 PI)
8907 08:06:19.834162 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8908 08:06:19.837684 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8909 08:06:19.837764 == TX Byte 1 ==
8910 08:06:19.840722 u2DelayCellOfst[8]=0 cells (0 PI)
8911 08:06:19.844154 u2DelayCellOfst[9]=3 cells (1 PI)
8912 08:06:19.847348 u2DelayCellOfst[10]=10 cells (3 PI)
8913 08:06:19.851166 u2DelayCellOfst[11]=7 cells (2 PI)
8914 08:06:19.854198 u2DelayCellOfst[12]=14 cells (4 PI)
8915 08:06:19.857532 u2DelayCellOfst[13]=14 cells (4 PI)
8916 08:06:19.861179 u2DelayCellOfst[14]=17 cells (5 PI)
8917 08:06:19.864241 u2DelayCellOfst[15]=17 cells (5 PI)
8918 08:06:19.867425 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8919 08:06:19.870758 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 08:06:19.874266 DramC Write-DBI on
8921 08:06:19.874346 ==
8922 08:06:19.877491 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 08:06:19.880964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 08:06:19.881045 ==
8925 08:06:19.881108
8926 08:06:19.884227
8927 08:06:19.884307 TX Vref Scan disable
8928 08:06:19.887523 == TX Byte 0 ==
8929 08:06:19.890788 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8930 08:06:19.894525 == TX Byte 1 ==
8931 08:06:19.897762 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8932 08:06:19.897867 DramC Write-DBI off
8933 08:06:19.897956
8934 08:06:19.900702 [DATLAT]
8935 08:06:19.900799 Freq=1600, CH1 RK1
8936 08:06:19.900863
8937 08:06:19.904563 DATLAT Default: 0xf
8938 08:06:19.904657 0, 0xFFFF, sum = 0
8939 08:06:19.907435 1, 0xFFFF, sum = 0
8940 08:06:19.907503 2, 0xFFFF, sum = 0
8941 08:06:19.910714 3, 0xFFFF, sum = 0
8942 08:06:19.910810 4, 0xFFFF, sum = 0
8943 08:06:19.914151 5, 0xFFFF, sum = 0
8944 08:06:19.914256 6, 0xFFFF, sum = 0
8945 08:06:19.917533 7, 0xFFFF, sum = 0
8946 08:06:19.917633 8, 0xFFFF, sum = 0
8947 08:06:19.921253 9, 0xFFFF, sum = 0
8948 08:06:19.921327 10, 0xFFFF, sum = 0
8949 08:06:19.924342 11, 0xFFFF, sum = 0
8950 08:06:19.927802 12, 0xFFFF, sum = 0
8951 08:06:19.927885 13, 0xFFFF, sum = 0
8952 08:06:19.930646 14, 0x0, sum = 1
8953 08:06:19.930785 15, 0x0, sum = 2
8954 08:06:19.934077 16, 0x0, sum = 3
8955 08:06:19.934171 17, 0x0, sum = 4
8956 08:06:19.934239 best_step = 15
8957 08:06:19.934300
8958 08:06:19.937555 ==
8959 08:06:19.937637 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 08:06:19.944320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 08:06:19.944401 ==
8962 08:06:19.944465 RX Vref Scan: 0
8963 08:06:19.944525
8964 08:06:19.947871 RX Vref 0 -> 0, step: 1
8965 08:06:19.947952
8966 08:06:19.951420 RX Delay 11 -> 252, step: 4
8967 08:06:19.954257 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8968 08:06:19.957811 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8969 08:06:19.964610 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8970 08:06:19.967821 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
8971 08:06:19.970910 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8972 08:06:19.974395 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8973 08:06:19.977508 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8974 08:06:19.980929 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8975 08:06:19.987928 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8976 08:06:19.991032 iDelay=191, Bit 9, Center 114 (59 ~ 170) 112
8977 08:06:19.994277 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8978 08:06:19.997376 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8979 08:06:20.004318 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8980 08:06:20.007831 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
8981 08:06:20.010930 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8982 08:06:20.014268 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8983 08:06:20.014344 ==
8984 08:06:20.017705 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 08:06:20.020867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 08:06:20.024260 ==
8987 08:06:20.024342 DQS Delay:
8988 08:06:20.024406 DQS0 = 0, DQS1 = 0
8989 08:06:20.027643 DQM Delay:
8990 08:06:20.027724 DQM0 = 130, DQM1 = 126
8991 08:06:20.031078 DQ Delay:
8992 08:06:20.034182 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =128
8993 08:06:20.037671 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
8994 08:06:20.041163 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
8995 08:06:20.044497 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
8996 08:06:20.044578
8997 08:06:20.044643
8998 08:06:20.044702
8999 08:06:20.047718 [DramC_TX_OE_Calibration] TA2
9000 08:06:20.050695 Original DQ_B0 (3 6) =30, OEN = 27
9001 08:06:20.054068 Original DQ_B1 (3 6) =30, OEN = 27
9002 08:06:20.057573 24, 0x0, End_B0=24 End_B1=24
9003 08:06:20.057656 25, 0x0, End_B0=25 End_B1=25
9004 08:06:20.060683 26, 0x0, End_B0=26 End_B1=26
9005 08:06:20.064257 27, 0x0, End_B0=27 End_B1=27
9006 08:06:20.067389 28, 0x0, End_B0=28 End_B1=28
9007 08:06:20.067472 29, 0x0, End_B0=29 End_B1=29
9008 08:06:20.071241 30, 0x0, End_B0=30 End_B1=30
9009 08:06:20.074377 31, 0x4141, End_B0=30 End_B1=30
9010 08:06:20.078008 Byte0 end_step=30 best_step=27
9011 08:06:20.081169 Byte1 end_step=30 best_step=27
9012 08:06:20.084259 Byte0 TX OE(2T, 0.5T) = (3, 3)
9013 08:06:20.084340 Byte1 TX OE(2T, 0.5T) = (3, 3)
9014 08:06:20.084404
9015 08:06:20.084464
9016 08:06:20.094241 [DQSOSCAuto] RK1, (LSB)MR18= 0xf14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9017 08:06:20.097537 CH1 RK1: MR19=303, MR18=F14
9018 08:06:20.100831 CH1_RK1: MR19=0x303, MR18=0xF14, DQSOSC=399, MR23=63, INC=23, DEC=15
9019 08:06:20.104134 [RxdqsGatingPostProcess] freq 1600
9020 08:06:20.110911 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9021 08:06:20.114121 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 08:06:20.117355 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 08:06:20.120852 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 08:06:20.124519 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 08:06:20.127657 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 08:06:20.127737 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 08:06:20.130889 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 08:06:20.134279 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 08:06:20.137595 Pre-setting of DQS Precalculation
9030 08:06:20.144073 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9031 08:06:20.150971 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9032 08:06:20.157660 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9033 08:06:20.157768
9034 08:06:20.157863
9035 08:06:20.161291 [Calibration Summary] 3200 Mbps
9036 08:06:20.161398 CH 0, Rank 0
9037 08:06:20.164324 SW Impedance : PASS
9038 08:06:20.167752 DUTY Scan : NO K
9039 08:06:20.167859 ZQ Calibration : PASS
9040 08:06:20.171355 Jitter Meter : NO K
9041 08:06:20.174426 CBT Training : PASS
9042 08:06:20.174523 Write leveling : PASS
9043 08:06:20.177510 RX DQS gating : PASS
9044 08:06:20.181236 RX DQ/DQS(RDDQC) : PASS
9045 08:06:20.181317 TX DQ/DQS : PASS
9046 08:06:20.184373 RX DATLAT : PASS
9047 08:06:20.188332 RX DQ/DQS(Engine): PASS
9048 08:06:20.188424 TX OE : PASS
9049 08:06:20.188490 All Pass.
9050 08:06:20.188549
9051 08:06:20.191059 CH 0, Rank 1
9052 08:06:20.191140 SW Impedance : PASS
9053 08:06:20.194584 DUTY Scan : NO K
9054 08:06:20.198331 ZQ Calibration : PASS
9055 08:06:20.198412 Jitter Meter : NO K
9056 08:06:20.201184 CBT Training : PASS
9057 08:06:20.204388 Write leveling : PASS
9058 08:06:20.204473 RX DQS gating : PASS
9059 08:06:20.207700 RX DQ/DQS(RDDQC) : PASS
9060 08:06:20.211600 TX DQ/DQS : PASS
9061 08:06:20.211681 RX DATLAT : PASS
9062 08:06:20.214540 RX DQ/DQS(Engine): PASS
9063 08:06:20.218034 TX OE : PASS
9064 08:06:20.218114 All Pass.
9065 08:06:20.218177
9066 08:06:20.218236 CH 1, Rank 0
9067 08:06:20.221147 SW Impedance : PASS
9068 08:06:20.224383 DUTY Scan : NO K
9069 08:06:20.224463 ZQ Calibration : PASS
9070 08:06:20.227701 Jitter Meter : NO K
9071 08:06:20.227781 CBT Training : PASS
9072 08:06:20.231226 Write leveling : PASS
9073 08:06:20.234315 RX DQS gating : PASS
9074 08:06:20.234396 RX DQ/DQS(RDDQC) : PASS
9075 08:06:20.237914 TX DQ/DQS : PASS
9076 08:06:20.241243 RX DATLAT : PASS
9077 08:06:20.241324 RX DQ/DQS(Engine): PASS
9078 08:06:20.244184 TX OE : PASS
9079 08:06:20.244264 All Pass.
9080 08:06:20.244327
9081 08:06:20.247983 CH 1, Rank 1
9082 08:06:20.248075 SW Impedance : PASS
9083 08:06:20.251205 DUTY Scan : NO K
9084 08:06:20.254372 ZQ Calibration : PASS
9085 08:06:20.254495 Jitter Meter : NO K
9086 08:06:20.257654 CBT Training : PASS
9087 08:06:20.261022 Write leveling : PASS
9088 08:06:20.261105 RX DQS gating : PASS
9089 08:06:20.264350 RX DQ/DQS(RDDQC) : PASS
9090 08:06:20.268426 TX DQ/DQS : PASS
9091 08:06:20.268527 RX DATLAT : PASS
9092 08:06:20.271244 RX DQ/DQS(Engine): PASS
9093 08:06:20.271340 TX OE : PASS
9094 08:06:20.274861 All Pass.
9095 08:06:20.274932
9096 08:06:20.275008 DramC Write-DBI on
9097 08:06:20.278071 PER_BANK_REFRESH: Hybrid Mode
9098 08:06:20.281556 TX_TRACKING: ON
9099 08:06:20.287687 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9100 08:06:20.298018 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9101 08:06:20.304761 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 08:06:20.307690 [FAST_K] Save calibration result to emmc
9103 08:06:20.311275 sync common calibartion params.
9104 08:06:20.311347 sync cbt_mode0:1, 1:1
9105 08:06:20.314523 dram_init: ddr_geometry: 2
9106 08:06:20.317955 dram_init: ddr_geometry: 2
9107 08:06:20.321630 dram_init: ddr_geometry: 2
9108 08:06:20.321700 0:dram_rank_size:100000000
9109 08:06:20.324747 1:dram_rank_size:100000000
9110 08:06:20.331188 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9111 08:06:20.331264 DFS_SHUFFLE_HW_MODE: ON
9112 08:06:20.334869 dramc_set_vcore_voltage set vcore to 725000
9113 08:06:20.337992 Read voltage for 1600, 0
9114 08:06:20.338089 Vio18 = 0
9115 08:06:20.341205 Vcore = 725000
9116 08:06:20.341274 Vdram = 0
9117 08:06:20.341333 Vddq = 0
9118 08:06:20.345059 Vmddr = 0
9119 08:06:20.345139 switch to 3200 Mbps bootup
9120 08:06:20.348214 [DramcRunTimeConfig]
9121 08:06:20.348294 PHYPLL
9122 08:06:20.351415 DPM_CONTROL_AFTERK: ON
9123 08:06:20.351496 PER_BANK_REFRESH: ON
9124 08:06:20.354520 REFRESH_OVERHEAD_REDUCTION: ON
9125 08:06:20.358075 CMD_PICG_NEW_MODE: OFF
9126 08:06:20.358184 XRTWTW_NEW_MODE: ON
9127 08:06:20.362099 XRTRTR_NEW_MODE: ON
9128 08:06:20.362190 TX_TRACKING: ON
9129 08:06:20.365194 RDSEL_TRACKING: OFF
9130 08:06:20.368317 DQS Precalculation for DVFS: ON
9131 08:06:20.368401 RX_TRACKING: OFF
9132 08:06:20.371165 HW_GATING DBG: ON
9133 08:06:20.371273 ZQCS_ENABLE_LP4: ON
9134 08:06:20.374633 RX_PICG_NEW_MODE: ON
9135 08:06:20.374758 TX_PICG_NEW_MODE: ON
9136 08:06:20.378047 ENABLE_RX_DCM_DPHY: ON
9137 08:06:20.381516 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9138 08:06:20.384782 DUMMY_READ_FOR_TRACKING: OFF
9139 08:06:20.384889 !!! SPM_CONTROL_AFTERK: OFF
9140 08:06:20.388251 !!! SPM could not control APHY
9141 08:06:20.391651 IMPEDANCE_TRACKING: ON
9142 08:06:20.391731 TEMP_SENSOR: ON
9143 08:06:20.394674 HW_SAVE_FOR_SR: OFF
9144 08:06:20.398088 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9145 08:06:20.401775 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9146 08:06:20.401856 Read ODT Tracking: ON
9147 08:06:20.405137 Refresh Rate DeBounce: ON
9148 08:06:20.408402 DFS_NO_QUEUE_FLUSH: ON
9149 08:06:20.411658 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9150 08:06:20.411738 ENABLE_DFS_RUNTIME_MRW: OFF
9151 08:06:20.414851 DDR_RESERVE_NEW_MODE: ON
9152 08:06:20.418046 MR_CBT_SWITCH_FREQ: ON
9153 08:06:20.418126 =========================
9154 08:06:20.438432 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9155 08:06:20.441843 dram_init: ddr_geometry: 2
9156 08:06:20.459548 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9157 08:06:20.463394 dram_init: dram init end (result: 0)
9158 08:06:20.469540 DRAM-K: Full calibration passed in 24540 msecs
9159 08:06:20.472980 MRC: failed to locate region type 0.
9160 08:06:20.473078 DRAM rank0 size:0x100000000,
9161 08:06:20.476410 DRAM rank1 size=0x100000000
9162 08:06:20.486429 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9163 08:06:20.492976 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9164 08:06:20.499506 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9165 08:06:20.506474 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9166 08:06:20.509660 DRAM rank0 size:0x100000000,
9167 08:06:20.513195 DRAM rank1 size=0x100000000
9168 08:06:20.513276 CBMEM:
9169 08:06:20.516644 IMD: root @ 0xfffff000 254 entries.
9170 08:06:20.519926 IMD: root @ 0xffffec00 62 entries.
9171 08:06:20.522775 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9172 08:06:20.526210 WARNING: RO_VPD is uninitialized or empty.
9173 08:06:20.533189 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9174 08:06:20.540096 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9175 08:06:20.552350 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9176 08:06:20.564401 BS: romstage times (exec / console): total (unknown) / 24050 ms
9177 08:06:20.564495
9178 08:06:20.564573
9179 08:06:20.574159 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9180 08:06:20.577184 ARM64: Exception handlers installed.
9181 08:06:20.580676 ARM64: Testing exception
9182 08:06:20.580761 ARM64: Done test exception
9183 08:06:20.584437 Enumerating buses...
9184 08:06:20.587434 Show all devs... Before device enumeration.
9185 08:06:20.590664 Root Device: enabled 1
9186 08:06:20.593975 CPU_CLUSTER: 0: enabled 1
9187 08:06:20.594057 CPU: 00: enabled 1
9188 08:06:20.597575 Compare with tree...
9189 08:06:20.597666 Root Device: enabled 1
9190 08:06:20.600774 CPU_CLUSTER: 0: enabled 1
9191 08:06:20.600881 CPU: 00: enabled 1
9192 08:06:20.604228 Root Device scanning...
9193 08:06:20.607425 scan_static_bus for Root Device
9194 08:06:20.611300 CPU_CLUSTER: 0 enabled
9195 08:06:20.614344 scan_static_bus for Root Device done
9196 08:06:20.617642 scan_bus: bus Root Device finished in 8 msecs
9197 08:06:20.617719 done
9198 08:06:20.624601 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9199 08:06:20.627850 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9200 08:06:20.631180 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9201 08:06:20.637870 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9202 08:06:20.641153 Allocating resources...
9203 08:06:20.641226 Reading resources...
9204 08:06:20.644793 Root Device read_resources bus 0 link: 0
9205 08:06:20.647816 DRAM rank0 size:0x100000000,
9206 08:06:20.651736 DRAM rank1 size=0x100000000
9207 08:06:20.654759 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9208 08:06:20.658012 CPU: 00 missing read_resources
9209 08:06:20.661181 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9210 08:06:20.664401 Root Device read_resources bus 0 link: 0 done
9211 08:06:20.668150 Done reading resources.
9212 08:06:20.671582 Show resources in subtree (Root Device)...After reading.
9213 08:06:20.678312 Root Device child on link 0 CPU_CLUSTER: 0
9214 08:06:20.681745 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 08:06:20.688731 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 08:06:20.691641 CPU: 00
9217 08:06:20.695089 Root Device assign_resources, bus 0 link: 0
9218 08:06:20.699146 CPU_CLUSTER: 0 missing set_resources
9219 08:06:20.701621 Root Device assign_resources, bus 0 link: 0 done
9220 08:06:20.705084 Done setting resources.
9221 08:06:20.708205 Show resources in subtree (Root Device)...After assigning values.
9222 08:06:20.714738 Root Device child on link 0 CPU_CLUSTER: 0
9223 08:06:20.718595 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 08:06:20.724697 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 08:06:20.728385 CPU: 00
9226 08:06:20.728507 Done allocating resources.
9227 08:06:20.734747 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9228 08:06:20.737996 Enabling resources...
9229 08:06:20.738102 done.
9230 08:06:20.741554 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9231 08:06:20.744983 Initializing devices...
9232 08:06:20.745103 Root Device init
9233 08:06:20.748633 init hardware done!
9234 08:06:20.751442 0x00000018: ctrlr->caps
9235 08:06:20.751521 52.000 MHz: ctrlr->f_max
9236 08:06:20.755207 0.400 MHz: ctrlr->f_min
9237 08:06:20.757840 0x40ff8080: ctrlr->voltages
9238 08:06:20.757949 sclk: 390625
9239 08:06:20.758017 Bus Width = 1
9240 08:06:20.761318 sclk: 390625
9241 08:06:20.761390 Bus Width = 1
9242 08:06:20.764698 Early init status = 3
9243 08:06:20.767957 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9244 08:06:20.771286 in-header: 03 fc 00 00 01 00 00 00
9245 08:06:20.774900 in-data: 00
9246 08:06:20.778206 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9247 08:06:20.782567 in-header: 03 fd 00 00 00 00 00 00
9248 08:06:20.785905 in-data:
9249 08:06:20.789783 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9250 08:06:20.793365 in-header: 03 fc 00 00 01 00 00 00
9251 08:06:20.796113 in-data: 00
9252 08:06:20.799575 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9253 08:06:20.803789 in-header: 03 fd 00 00 00 00 00 00
9254 08:06:20.807388 in-data:
9255 08:06:20.810511 [SSUSB] Setting up USB HOST controller...
9256 08:06:20.814599 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9257 08:06:20.817363 [SSUSB] phy power-on done.
9258 08:06:20.820654 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9259 08:06:20.827316 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9260 08:06:20.831029 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9261 08:06:20.837461 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9262 08:06:20.844129 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9263 08:06:20.850623 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9264 08:06:20.857161 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9265 08:06:20.863962 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9266 08:06:20.864044 SPM: binary array size = 0x9dc
9267 08:06:20.870895 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9268 08:06:20.877288 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9269 08:06:20.883904 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9270 08:06:20.887485 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9271 08:06:20.890831 configure_display: Starting display init
9272 08:06:20.927198 anx7625_power_on_init: Init interface.
9273 08:06:20.930660 anx7625_disable_pd_protocol: Disabled PD feature.
9274 08:06:20.933694 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9275 08:06:20.961493 anx7625_start_dp_work: Secure OCM version=00
9276 08:06:20.965242 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9277 08:06:20.979743 sp_tx_get_edid_block: EDID Block = 1
9278 08:06:21.082916 Extracted contents:
9279 08:06:21.085515 header: 00 ff ff ff ff ff ff 00
9280 08:06:21.089005 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9281 08:06:21.092186 version: 01 04
9282 08:06:21.095691 basic params: 95 1f 11 78 0a
9283 08:06:21.099006 chroma info: 76 90 94 55 54 90 27 21 50 54
9284 08:06:21.102698 established: 00 00 00
9285 08:06:21.109125 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9286 08:06:21.112282 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9287 08:06:21.118732 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9288 08:06:21.125886 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9289 08:06:21.132638 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9290 08:06:21.135482 extensions: 00
9291 08:06:21.135563 checksum: fb
9292 08:06:21.135627
9293 08:06:21.138986 Manufacturer: IVO Model 57d Serial Number 0
9294 08:06:21.142185 Made week 0 of 2020
9295 08:06:21.142266 EDID version: 1.4
9296 08:06:21.145397 Digital display
9297 08:06:21.149311 6 bits per primary color channel
9298 08:06:21.149441 DisplayPort interface
9299 08:06:21.152262 Maximum image size: 31 cm x 17 cm
9300 08:06:21.152343 Gamma: 220%
9301 08:06:21.155646 Check DPMS levels
9302 08:06:21.159303 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9303 08:06:21.162519 First detailed timing is preferred timing
9304 08:06:21.165786 Established timings supported:
9305 08:06:21.168818 Standard timings supported:
9306 08:06:21.168898 Detailed timings
9307 08:06:21.175789 Hex of detail: 383680a07038204018303c0035ae10000019
9308 08:06:21.179120 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9309 08:06:21.182626 0780 0798 07c8 0820 hborder 0
9310 08:06:21.189053 0438 043b 0447 0458 vborder 0
9311 08:06:21.189133 -hsync -vsync
9312 08:06:21.192485 Did detailed timing
9313 08:06:21.195978 Hex of detail: 000000000000000000000000000000000000
9314 08:06:21.199137 Manufacturer-specified data, tag 0
9315 08:06:21.205803 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9316 08:06:21.205883 ASCII string: InfoVision
9317 08:06:21.212470 Hex of detail: 000000fe00523134304e574635205248200a
9318 08:06:21.212550 ASCII string: R140NWF5 RH
9319 08:06:21.215769 Checksum
9320 08:06:21.215849 Checksum: 0xfb (valid)
9321 08:06:21.222326 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9322 08:06:21.222407 DSI data_rate: 832800000 bps
9323 08:06:21.230069 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9324 08:06:21.233672 anx7625_parse_edid: pixelclock(138800).
9325 08:06:21.236623 hactive(1920), hsync(48), hfp(24), hbp(88)
9326 08:06:21.240379 vactive(1080), vsync(12), vfp(3), vbp(17)
9327 08:06:21.243167 anx7625_dsi_config: config dsi.
9328 08:06:21.250605 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9329 08:06:21.264206 anx7625_dsi_config: success to config DSI
9330 08:06:21.267629 anx7625_dp_start: MIPI phy setup OK.
9331 08:06:21.271662 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9332 08:06:21.274529 mtk_ddp_mode_set invalid vrefresh 60
9333 08:06:21.278008 main_disp_path_setup
9334 08:06:21.278088 ovl_layer_smi_id_en
9335 08:06:21.281077 ovl_layer_smi_id_en
9336 08:06:21.281157 ccorr_config
9337 08:06:21.281221 aal_config
9338 08:06:21.284824 gamma_config
9339 08:06:21.284903 postmask_config
9340 08:06:21.288050 dither_config
9341 08:06:21.291083 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9342 08:06:21.297693 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9343 08:06:21.301098 Root Device init finished in 551 msecs
9344 08:06:21.301178 CPU_CLUSTER: 0 init
9345 08:06:21.311361 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9346 08:06:21.314744 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9347 08:06:21.317691 APU_MBOX 0x190000b0 = 0x10001
9348 08:06:21.321196 APU_MBOX 0x190001b0 = 0x10001
9349 08:06:21.324768 APU_MBOX 0x190005b0 = 0x10001
9350 08:06:21.327716 APU_MBOX 0x190006b0 = 0x10001
9351 08:06:21.331180 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9352 08:06:21.343372 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9353 08:06:21.356076 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9354 08:06:21.362501 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9355 08:06:21.374211 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9356 08:06:21.383097 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9357 08:06:21.386494 CPU_CLUSTER: 0 init finished in 81 msecs
9358 08:06:21.389884 Devices initialized
9359 08:06:21.392980 Show all devs... After init.
9360 08:06:21.393061 Root Device: enabled 1
9361 08:06:21.396581 CPU_CLUSTER: 0: enabled 1
9362 08:06:21.399715 CPU: 00: enabled 1
9363 08:06:21.402776 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9364 08:06:21.406217 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9365 08:06:21.409552 ELOG: NV offset 0x57f000 size 0x1000
9366 08:06:21.416167 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9367 08:06:21.423059 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9368 08:06:21.425964 ELOG: Event(17) added with size 13 at 2023-09-21 08:06:22 UTC
9369 08:06:21.432921 out: cmd=0x121: 03 db 21 01 00 00 00 00
9370 08:06:21.436199 in-header: 03 ff 00 00 2c 00 00 00
9371 08:06:21.446156 in-data: 60 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 08:06:21.452826 ELOG: Event(A1) added with size 10 at 2023-09-21 08:06:22 UTC
9373 08:06:21.459687 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9374 08:06:21.466227 ELOG: Event(A0) added with size 9 at 2023-09-21 08:06:22 UTC
9375 08:06:21.469192 elog_add_boot_reason: Logged dev mode boot
9376 08:06:21.475780 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9377 08:06:21.475858 Finalize devices...
9378 08:06:21.479392 Devices finalized
9379 08:06:21.482587 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9380 08:06:21.485739 Writing coreboot table at 0xffe64000
9381 08:06:21.489166 0. 000000000010a000-0000000000113fff: RAMSTAGE
9382 08:06:21.492600 1. 0000000040000000-00000000400fffff: RAM
9383 08:06:21.499160 2. 0000000040100000-000000004032afff: RAMSTAGE
9384 08:06:21.502219 3. 000000004032b000-00000000545fffff: RAM
9385 08:06:21.505910 4. 0000000054600000-000000005465ffff: BL31
9386 08:06:21.509017 5. 0000000054660000-00000000ffe63fff: RAM
9387 08:06:21.515783 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9388 08:06:21.519130 7. 0000000100000000-000000023fffffff: RAM
9389 08:06:21.522391 Passing 5 GPIOs to payload:
9390 08:06:21.525692 NAME | PORT | POLARITY | VALUE
9391 08:06:21.529505 EC in RW | 0x000000aa | low | undefined
9392 08:06:21.536232 EC interrupt | 0x00000005 | low | undefined
9393 08:06:21.539889 TPM interrupt | 0x000000ab | high | undefined
9394 08:06:21.546012 SD card detect | 0x00000011 | high | undefined
9395 08:06:21.549454 speaker enable | 0x00000093 | high | undefined
9396 08:06:21.552756 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9397 08:06:21.555976 in-header: 03 f9 00 00 02 00 00 00
9398 08:06:21.559178 in-data: 02 00
9399 08:06:21.559257 ADC[4]: Raw value=900221 ID=7
9400 08:06:21.562844 ADC[3]: Raw value=213336 ID=1
9401 08:06:21.565828 RAM Code: 0x71
9402 08:06:21.565921 ADC[6]: Raw value=74926 ID=0
9403 08:06:21.569213 ADC[5]: Raw value=211860 ID=1
9404 08:06:21.573083 SKU Code: 0x1
9405 08:06:21.576297 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ae81
9406 08:06:21.579739 coreboot table: 964 bytes.
9407 08:06:21.583150 IMD ROOT 0. 0xfffff000 0x00001000
9408 08:06:21.586432 IMD SMALL 1. 0xffffe000 0x00001000
9409 08:06:21.589735 RO MCACHE 2. 0xffffc000 0x00001104
9410 08:06:21.592695 CONSOLE 3. 0xfff7c000 0x00080000
9411 08:06:21.596121 FMAP 4. 0xfff7b000 0x00000452
9412 08:06:21.599253 TIME STAMP 5. 0xfff7a000 0x00000910
9413 08:06:21.602566 VBOOT WORK 6. 0xfff66000 0x00014000
9414 08:06:21.606018 RAMOOPS 7. 0xffe66000 0x00100000
9415 08:06:21.609614 COREBOOT 8. 0xffe64000 0x00002000
9416 08:06:21.609695 IMD small region:
9417 08:06:21.612840 IMD ROOT 0. 0xffffec00 0x00000400
9418 08:06:21.615833 VPD 1. 0xffffeb80 0x0000006c
9419 08:06:21.619585 MMC STATUS 2. 0xffffeb60 0x00000004
9420 08:06:21.626574 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9421 08:06:21.629460 Probing TPM: done!
9422 08:06:21.632551 Connected to device vid:did:rid of 1ae0:0028:00
9423 08:06:21.643200 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9424 08:06:21.646077 Initialized TPM device CR50 revision 0
9425 08:06:21.650293 Checking cr50 for pending updates
9426 08:06:21.652998 Reading cr50 TPM mode
9427 08:06:21.661764 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9428 08:06:21.668275 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9429 08:06:21.708705 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9430 08:06:21.711703 Checking segment from ROM address 0x40100000
9431 08:06:21.715343 Checking segment from ROM address 0x4010001c
9432 08:06:21.721830 Loading segment from ROM address 0x40100000
9433 08:06:21.721911 code (compression=0)
9434 08:06:21.728412 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9435 08:06:21.738542 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9436 08:06:21.738647 it's not compressed!
9437 08:06:21.745579 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9438 08:06:21.748444 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9439 08:06:21.768665 Loading segment from ROM address 0x4010001c
9440 08:06:21.768747 Entry Point 0x80000000
9441 08:06:21.771996 Loaded segments
9442 08:06:21.775639 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9443 08:06:21.782014 Jumping to boot code at 0x80000000(0xffe64000)
9444 08:06:21.788830 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9445 08:06:21.795814 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9446 08:06:21.803415 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9447 08:06:21.806623 Checking segment from ROM address 0x40100000
9448 08:06:21.809772 Checking segment from ROM address 0x4010001c
9449 08:06:21.816329 Loading segment from ROM address 0x40100000
9450 08:06:21.816410 code (compression=1)
9451 08:06:21.823115 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9452 08:06:21.833284 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9453 08:06:21.833366 using LZMA
9454 08:06:21.841637 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9455 08:06:21.848369 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9456 08:06:21.851519 Loading segment from ROM address 0x4010001c
9457 08:06:21.851601 Entry Point 0x54601000
9458 08:06:21.854928 Loaded segments
9459 08:06:21.858666 NOTICE: MT8192 bl31_setup
9460 08:06:21.864951 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9461 08:06:21.869112 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9462 08:06:21.872522 WARNING: region 0:
9463 08:06:21.875617 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 08:06:21.875697 WARNING: region 1:
9465 08:06:21.882145 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9466 08:06:21.885915 WARNING: region 2:
9467 08:06:21.888458 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9468 08:06:21.891761 WARNING: region 3:
9469 08:06:21.895189 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 08:06:21.899020 WARNING: region 4:
9471 08:06:21.901928 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 08:06:21.905365 WARNING: region 5:
9473 08:06:21.908565 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 08:06:21.911968 WARNING: region 6:
9475 08:06:21.915808 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 08:06:21.915889 WARNING: region 7:
9477 08:06:21.921953 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 08:06:21.929005 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9479 08:06:21.932045 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9480 08:06:21.935371 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9481 08:06:21.942068 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9482 08:06:21.945629 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9483 08:06:21.949100 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9484 08:06:21.955573 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9485 08:06:21.959467 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9486 08:06:21.962573 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9487 08:06:21.969006 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9488 08:06:21.972429 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9489 08:06:21.975930 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9490 08:06:21.982364 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9491 08:06:21.986319 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9492 08:06:21.992606 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9493 08:06:21.996192 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9494 08:06:21.999226 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9495 08:06:22.006056 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9496 08:06:22.009649 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9497 08:06:22.012885 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9498 08:06:22.019750 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9499 08:06:22.023351 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9500 08:06:22.026229 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9501 08:06:22.032986 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9502 08:06:22.036491 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9503 08:06:22.043385 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9504 08:06:22.046092 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9505 08:06:22.049794 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9506 08:06:22.056509 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9507 08:06:22.059672 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9508 08:06:22.066490 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9509 08:06:22.070164 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9510 08:06:22.073156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9511 08:06:22.076575 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9512 08:06:22.083474 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9513 08:06:22.086440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9514 08:06:22.089985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9515 08:06:22.093260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9516 08:06:22.100110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9517 08:06:22.103668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9518 08:06:22.106757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9519 08:06:22.109964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9520 08:06:22.113363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9521 08:06:22.120704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9522 08:06:22.123527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9523 08:06:22.127490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9524 08:06:22.130681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9525 08:06:22.137009 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9526 08:06:22.140263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9527 08:06:22.147091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9528 08:06:22.150699 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9529 08:06:22.153892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9530 08:06:22.160995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9531 08:06:22.164496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9532 08:06:22.170780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9533 08:06:22.174034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9534 08:06:22.177622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9535 08:06:22.184082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9536 08:06:22.187763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9537 08:06:22.194180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9538 08:06:22.197604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9539 08:06:22.204710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9540 08:06:22.207772 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9541 08:06:22.211472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9542 08:06:22.217995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9543 08:06:22.221615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9544 08:06:22.228344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9545 08:06:22.231624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9546 08:06:22.235040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9547 08:06:22.241811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9548 08:06:22.245333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9549 08:06:22.252092 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9550 08:06:22.255596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9551 08:06:22.258481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9552 08:06:22.265231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9553 08:06:22.268678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9554 08:06:22.275375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9555 08:06:22.278745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9556 08:06:22.285586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9557 08:06:22.288812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9558 08:06:22.292367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9559 08:06:22.299193 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9560 08:06:22.302630 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9561 08:06:22.309298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9562 08:06:22.312779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9563 08:06:22.315853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9564 08:06:22.322616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9565 08:06:22.325754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9566 08:06:22.333111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9567 08:06:22.336064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9568 08:06:22.339602 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9569 08:06:22.346247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9570 08:06:22.349185 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9571 08:06:22.356131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9572 08:06:22.359586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9573 08:06:22.366606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9574 08:06:22.369480 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9575 08:06:22.372983 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9576 08:06:22.376078 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9577 08:06:22.382852 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9578 08:06:22.386377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9579 08:06:22.389624 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9580 08:06:22.396834 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9581 08:06:22.400039 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9582 08:06:22.406608 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9583 08:06:22.410122 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9584 08:06:22.413248 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9585 08:06:22.419861 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9586 08:06:22.423234 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9587 08:06:22.427135 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9588 08:06:22.433059 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9589 08:06:22.436556 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9590 08:06:22.443581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9591 08:06:22.446549 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9592 08:06:22.450299 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9593 08:06:22.456722 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9594 08:06:22.460700 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9595 08:06:22.463295 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9596 08:06:22.470184 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9597 08:06:22.473419 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9598 08:06:22.476935 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9599 08:06:22.480301 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9600 08:06:22.483319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9601 08:06:22.489907 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9602 08:06:22.493510 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9603 08:06:22.500101 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9604 08:06:22.503477 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9605 08:06:22.506905 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9606 08:06:22.514045 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9607 08:06:22.516936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9608 08:06:22.520372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9609 08:06:22.526969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9610 08:06:22.530503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9611 08:06:22.537104 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9612 08:06:22.540451 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9613 08:06:22.544083 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9614 08:06:22.550565 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9615 08:06:22.553797 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9616 08:06:22.557236 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9617 08:06:22.563852 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9618 08:06:22.567271 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9619 08:06:22.574306 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9620 08:06:22.577308 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9621 08:06:22.581138 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9622 08:06:22.587293 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9623 08:06:22.591015 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9624 08:06:22.594336 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9625 08:06:22.601386 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9626 08:06:22.604143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9627 08:06:22.611280 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9628 08:06:22.614489 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9629 08:06:22.617751 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9630 08:06:22.624231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9631 08:06:22.627877 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9632 08:06:22.631393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9633 08:06:22.637836 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9634 08:06:22.641634 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9635 08:06:22.647870 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9636 08:06:22.651177 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9637 08:06:22.654872 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9638 08:06:22.661190 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9639 08:06:22.664972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9640 08:06:22.668040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9641 08:06:22.674950 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9642 08:06:22.678156 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9643 08:06:22.684923 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9644 08:06:22.688082 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9645 08:06:22.691619 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9646 08:06:22.698366 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9647 08:06:22.701490 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9648 08:06:22.708118 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9649 08:06:22.711717 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9650 08:06:22.714884 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9651 08:06:22.721582 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9652 08:06:22.724668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9653 08:06:22.727937 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9654 08:06:22.734694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9655 08:06:22.738261 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9656 08:06:22.744890 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9657 08:06:22.748359 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9658 08:06:22.751507 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9659 08:06:22.758177 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9660 08:06:22.761157 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9661 08:06:22.764543 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9662 08:06:22.771609 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9663 08:06:22.774831 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9664 08:06:22.781488 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9665 08:06:22.784727 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9666 08:06:22.788025 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9667 08:06:22.794927 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9668 08:06:22.798654 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9669 08:06:22.804822 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9670 08:06:22.808488 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9671 08:06:22.811867 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9672 08:06:22.818165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9673 08:06:22.821896 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9674 08:06:22.828813 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9675 08:06:22.831894 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9676 08:06:22.838387 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9677 08:06:22.841436 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9678 08:06:22.845091 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9679 08:06:22.851547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9680 08:06:22.854637 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9681 08:06:22.861629 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9682 08:06:22.864691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9683 08:06:22.868061 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9684 08:06:22.874519 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9685 08:06:22.878414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9686 08:06:22.884956 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9687 08:06:22.888219 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9688 08:06:22.891795 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9689 08:06:22.898033 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9690 08:06:22.901557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9691 08:06:22.908016 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9692 08:06:22.911205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9693 08:06:22.918115 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9694 08:06:22.921234 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9695 08:06:22.924847 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9696 08:06:22.931291 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9697 08:06:22.934555 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9698 08:06:22.941963 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9699 08:06:22.944980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9700 08:06:22.947925 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9701 08:06:22.954796 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9702 08:06:22.957877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9703 08:06:22.964556 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9704 08:06:22.967945 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9705 08:06:22.974387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9706 08:06:22.978024 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9707 08:06:22.981124 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9708 08:06:22.984676 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9709 08:06:22.991751 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9710 08:06:22.994482 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9711 08:06:22.998185 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9712 08:06:23.001357 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9713 08:06:23.007895 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9714 08:06:23.011229 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9715 08:06:23.017954 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9716 08:06:23.021625 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9717 08:06:23.024671 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9718 08:06:23.028050 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9719 08:06:23.035039 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9720 08:06:23.038615 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9721 08:06:23.041503 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9722 08:06:23.048046 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9723 08:06:23.051736 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9724 08:06:23.058412 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9725 08:06:23.061755 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9726 08:06:23.064724 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9727 08:06:23.071768 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9728 08:06:23.075780 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9729 08:06:23.078052 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9730 08:06:23.084998 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9731 08:06:23.088540 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9732 08:06:23.091628 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9733 08:06:23.098528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9734 08:06:23.101954 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9735 08:06:23.108463 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9736 08:06:23.111798 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9737 08:06:23.115135 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9738 08:06:23.121560 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9739 08:06:23.125065 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9740 08:06:23.128267 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9741 08:06:23.135546 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9742 08:06:23.138732 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9743 08:06:23.141641 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9744 08:06:23.148574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9745 08:06:23.152021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9746 08:06:23.155178 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9747 08:06:23.161764 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9748 08:06:23.165413 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9749 08:06:23.168994 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9750 08:06:23.171684 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9751 08:06:23.175616 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9752 08:06:23.182039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9753 08:06:23.185525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9754 08:06:23.188832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9755 08:06:23.192362 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9756 08:06:23.198756 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9757 08:06:23.201781 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9758 08:06:23.205200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9759 08:06:23.212017 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9760 08:06:23.215896 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9761 08:06:23.219103 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9762 08:06:23.225770 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9763 08:06:23.228808 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9764 08:06:23.235714 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9765 08:06:23.238758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9766 08:06:23.242404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9767 08:06:23.249144 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9768 08:06:23.252302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9769 08:06:23.255884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9770 08:06:23.262820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9771 08:06:23.266027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9772 08:06:23.272489 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9773 08:06:23.275548 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9774 08:06:23.278973 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9775 08:06:23.286205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9776 08:06:23.289143 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9777 08:06:23.296052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9778 08:06:23.299100 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9779 08:06:23.302957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9780 08:06:23.309334 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9781 08:06:23.312747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9782 08:06:23.319269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9783 08:06:23.322826 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9784 08:06:23.326024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9785 08:06:23.332833 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9786 08:06:23.335802 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9787 08:06:23.342421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9788 08:06:23.346259 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9789 08:06:23.349323 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9790 08:06:23.356005 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9791 08:06:23.359288 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9792 08:06:23.365659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9793 08:06:23.368932 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9794 08:06:23.372446 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9795 08:06:23.379042 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9796 08:06:23.382586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9797 08:06:23.389272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9798 08:06:23.392297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9799 08:06:23.395940 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9800 08:06:23.402758 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9801 08:06:23.406169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9802 08:06:23.412602 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9803 08:06:23.415852 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9804 08:06:23.419362 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9805 08:06:23.426329 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9806 08:06:23.429505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9807 08:06:23.436028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9808 08:06:23.439204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9809 08:06:23.442931 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9810 08:06:23.449332 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9811 08:06:23.452899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9812 08:06:23.459783 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9813 08:06:23.462615 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9814 08:06:23.469290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9815 08:06:23.472788 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9816 08:06:23.476191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9817 08:06:23.482946 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9818 08:06:23.486083 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9819 08:06:23.492689 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9820 08:06:23.495914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9821 08:06:23.499010 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9822 08:06:23.505863 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9823 08:06:23.509457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9824 08:06:23.512759 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9825 08:06:23.519122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9826 08:06:23.522918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9827 08:06:23.529184 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9828 08:06:23.532642 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9829 08:06:23.539393 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9830 08:06:23.542666 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9831 08:06:23.546065 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9832 08:06:23.553056 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9833 08:06:23.556087 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9834 08:06:23.562570 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9835 08:06:23.565987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9836 08:06:23.569356 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9837 08:06:23.575957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9838 08:06:23.579224 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9839 08:06:23.585982 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9840 08:06:23.589267 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9841 08:06:23.595946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9842 08:06:23.599597 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9843 08:06:23.603020 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9844 08:06:23.609711 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9845 08:06:23.613223 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9846 08:06:23.619707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9847 08:06:23.623110 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9848 08:06:23.626264 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9849 08:06:23.633242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9850 08:06:23.636168 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9851 08:06:23.643002 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9852 08:06:23.646184 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9853 08:06:23.653445 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9854 08:06:23.656256 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9855 08:06:23.659664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9856 08:06:23.666582 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9857 08:06:23.669881 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9858 08:06:23.676601 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9859 08:06:23.679714 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9860 08:06:23.686033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9861 08:06:23.689437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9862 08:06:23.696342 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9863 08:06:23.699319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9864 08:06:23.702801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9865 08:06:23.709465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9866 08:06:23.713131 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9867 08:06:23.719788 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9868 08:06:23.723109 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9869 08:06:23.729627 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9870 08:06:23.733433 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9871 08:06:23.736416 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9872 08:06:23.742629 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9873 08:06:23.746473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9874 08:06:23.752655 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9875 08:06:23.756202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9876 08:06:23.762777 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9877 08:06:23.766016 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9878 08:06:23.769434 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9879 08:06:23.776365 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9880 08:06:23.779776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9881 08:06:23.782919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9882 08:06:23.789704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9883 08:06:23.792619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9884 08:06:23.799568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9885 08:06:23.802791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9886 08:06:23.809296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9887 08:06:23.812694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9888 08:06:23.819343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9889 08:06:23.822628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9890 08:06:23.829254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9891 08:06:23.833063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9892 08:06:23.839324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9893 08:06:23.842641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9894 08:06:23.849430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9895 08:06:23.852584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9896 08:06:23.859945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9897 08:06:23.863081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9898 08:06:23.869261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9899 08:06:23.872987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9900 08:06:23.879408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9901 08:06:23.882570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9902 08:06:23.889300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9903 08:06:23.893076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9904 08:06:23.899471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9905 08:06:23.903131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9906 08:06:23.909392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9907 08:06:23.913053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9908 08:06:23.919407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9909 08:06:23.922829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9910 08:06:23.929573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9911 08:06:23.933095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9912 08:06:23.936147 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9913 08:06:23.939555 INFO: [APUAPC] vio 0
9914 08:06:23.943085 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9915 08:06:23.949578 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9916 08:06:23.952677 INFO: [APUAPC] D0_APC_0: 0x400510
9917 08:06:23.956355 INFO: [APUAPC] D0_APC_1: 0x0
9918 08:06:23.959440 INFO: [APUAPC] D0_APC_2: 0x1540
9919 08:06:23.959520 INFO: [APUAPC] D0_APC_3: 0x0
9920 08:06:23.963117 INFO: [APUAPC] D1_APC_0: 0xffffffff
9921 08:06:23.966433 INFO: [APUAPC] D1_APC_1: 0xffffffff
9922 08:06:23.969447 INFO: [APUAPC] D1_APC_2: 0x3fffff
9923 08:06:23.973050 INFO: [APUAPC] D1_APC_3: 0x0
9924 08:06:23.976175 INFO: [APUAPC] D2_APC_0: 0xffffffff
9925 08:06:23.980063 INFO: [APUAPC] D2_APC_1: 0xffffffff
9926 08:06:23.983233 INFO: [APUAPC] D2_APC_2: 0x3fffff
9927 08:06:23.986830 INFO: [APUAPC] D2_APC_3: 0x0
9928 08:06:23.989757 INFO: [APUAPC] D3_APC_0: 0xffffffff
9929 08:06:23.992996 INFO: [APUAPC] D3_APC_1: 0xffffffff
9930 08:06:23.996594 INFO: [APUAPC] D3_APC_2: 0x3fffff
9931 08:06:23.999691 INFO: [APUAPC] D3_APC_3: 0x0
9932 08:06:24.003221 INFO: [APUAPC] D4_APC_0: 0xffffffff
9933 08:06:24.006542 INFO: [APUAPC] D4_APC_1: 0xffffffff
9934 08:06:24.009820 INFO: [APUAPC] D4_APC_2: 0x3fffff
9935 08:06:24.012997 INFO: [APUAPC] D4_APC_3: 0x0
9936 08:06:24.016288 INFO: [APUAPC] D5_APC_0: 0xffffffff
9937 08:06:24.019688 INFO: [APUAPC] D5_APC_1: 0xffffffff
9938 08:06:24.023258 INFO: [APUAPC] D5_APC_2: 0x3fffff
9939 08:06:24.027414 INFO: [APUAPC] D5_APC_3: 0x0
9940 08:06:24.029670 INFO: [APUAPC] D6_APC_0: 0xffffffff
9941 08:06:24.033296 INFO: [APUAPC] D6_APC_1: 0xffffffff
9942 08:06:24.036362 INFO: [APUAPC] D6_APC_2: 0x3fffff
9943 08:06:24.039793 INFO: [APUAPC] D6_APC_3: 0x0
9944 08:06:24.043162 INFO: [APUAPC] D7_APC_0: 0xffffffff
9945 08:06:24.046719 INFO: [APUAPC] D7_APC_1: 0xffffffff
9946 08:06:24.049808 INFO: [APUAPC] D7_APC_2: 0x3fffff
9947 08:06:24.053034 INFO: [APUAPC] D7_APC_3: 0x0
9948 08:06:24.056478 INFO: [APUAPC] D8_APC_0: 0xffffffff
9949 08:06:24.060548 INFO: [APUAPC] D8_APC_1: 0xffffffff
9950 08:06:24.063412 INFO: [APUAPC] D8_APC_2: 0x3fffff
9951 08:06:24.063492 INFO: [APUAPC] D8_APC_3: 0x0
9952 08:06:24.069936 INFO: [APUAPC] D9_APC_0: 0xffffffff
9953 08:06:24.073248 INFO: [APUAPC] D9_APC_1: 0xffffffff
9954 08:06:24.073328 INFO: [APUAPC] D9_APC_2: 0x3fffff
9955 08:06:24.076920 INFO: [APUAPC] D9_APC_3: 0x0
9956 08:06:24.080109 INFO: [APUAPC] D10_APC_0: 0xffffffff
9957 08:06:24.083220 INFO: [APUAPC] D10_APC_1: 0xffffffff
9958 08:06:24.087124 INFO: [APUAPC] D10_APC_2: 0x3fffff
9959 08:06:24.090281 INFO: [APUAPC] D10_APC_3: 0x0
9960 08:06:24.094030 INFO: [APUAPC] D11_APC_0: 0xffffffff
9961 08:06:24.096686 INFO: [APUAPC] D11_APC_1: 0xffffffff
9962 08:06:24.100144 INFO: [APUAPC] D11_APC_2: 0x3fffff
9963 08:06:24.103552 INFO: [APUAPC] D11_APC_3: 0x0
9964 08:06:24.106694 INFO: [APUAPC] D12_APC_0: 0xffffffff
9965 08:06:24.109779 INFO: [APUAPC] D12_APC_1: 0xffffffff
9966 08:06:24.116758 INFO: [APUAPC] D12_APC_2: 0x3fffff
9967 08:06:24.116839 INFO: [APUAPC] D12_APC_3: 0x0
9968 08:06:24.119936 INFO: [APUAPC] D13_APC_0: 0xffffffff
9969 08:06:24.126394 INFO: [APUAPC] D13_APC_1: 0xffffffff
9970 08:06:24.129730 INFO: [APUAPC] D13_APC_2: 0x3fffff
9971 08:06:24.129810 INFO: [APUAPC] D13_APC_3: 0x0
9972 08:06:24.133627 INFO: [APUAPC] D14_APC_0: 0xffffffff
9973 08:06:24.139935 INFO: [APUAPC] D14_APC_1: 0xffffffff
9974 08:06:24.143336 INFO: [APUAPC] D14_APC_2: 0x3fffff
9975 08:06:24.143420 INFO: [APUAPC] D14_APC_3: 0x0
9976 08:06:24.146372 INFO: [APUAPC] D15_APC_0: 0xffffffff
9977 08:06:24.153761 INFO: [APUAPC] D15_APC_1: 0xffffffff
9978 08:06:24.156973 INFO: [APUAPC] D15_APC_2: 0x3fffff
9979 08:06:24.157053 INFO: [APUAPC] D15_APC_3: 0x0
9980 08:06:24.160137 INFO: [APUAPC] APC_CON: 0x4
9981 08:06:24.163585 INFO: [NOCDAPC] D0_APC_0: 0x0
9982 08:06:24.166891 INFO: [NOCDAPC] D0_APC_1: 0x0
9983 08:06:24.169954 INFO: [NOCDAPC] D1_APC_0: 0x0
9984 08:06:24.173061 INFO: [NOCDAPC] D1_APC_1: 0xfff
9985 08:06:24.176565 INFO: [NOCDAPC] D2_APC_0: 0x0
9986 08:06:24.179761 INFO: [NOCDAPC] D2_APC_1: 0xfff
9987 08:06:24.179842 INFO: [NOCDAPC] D3_APC_0: 0x0
9988 08:06:24.183199 INFO: [NOCDAPC] D3_APC_1: 0xfff
9989 08:06:24.186590 INFO: [NOCDAPC] D4_APC_0: 0x0
9990 08:06:24.190248 INFO: [NOCDAPC] D4_APC_1: 0xfff
9991 08:06:24.193114 INFO: [NOCDAPC] D5_APC_0: 0x0
9992 08:06:24.196646 INFO: [NOCDAPC] D5_APC_1: 0xfff
9993 08:06:24.199984 INFO: [NOCDAPC] D6_APC_0: 0x0
9994 08:06:24.203222 INFO: [NOCDAPC] D6_APC_1: 0xfff
9995 08:06:24.206973 INFO: [NOCDAPC] D7_APC_0: 0x0
9996 08:06:24.210059 INFO: [NOCDAPC] D7_APC_1: 0xfff
9997 08:06:24.213196 INFO: [NOCDAPC] D8_APC_0: 0x0
9998 08:06:24.213276 INFO: [NOCDAPC] D8_APC_1: 0xfff
9999 08:06:24.216745 INFO: [NOCDAPC] D9_APC_0: 0x0
10000 08:06:24.220179 INFO: [NOCDAPC] D9_APC_1: 0xfff
10001 08:06:24.223917 INFO: [NOCDAPC] D10_APC_0: 0x0
10002 08:06:24.226672 INFO: [NOCDAPC] D10_APC_1: 0xfff
10003 08:06:24.230492 INFO: [NOCDAPC] D11_APC_0: 0x0
10004 08:06:24.233400 INFO: [NOCDAPC] D11_APC_1: 0xfff
10005 08:06:24.236870 INFO: [NOCDAPC] D12_APC_0: 0x0
10006 08:06:24.240695 INFO: [NOCDAPC] D12_APC_1: 0xfff
10007 08:06:24.243175 INFO: [NOCDAPC] D13_APC_0: 0x0
10008 08:06:24.246913 INFO: [NOCDAPC] D13_APC_1: 0xfff
10009 08:06:24.249910 INFO: [NOCDAPC] D14_APC_0: 0x0
10010 08:06:24.253328 INFO: [NOCDAPC] D14_APC_1: 0xfff
10011 08:06:24.253408 INFO: [NOCDAPC] D15_APC_0: 0x0
10012 08:06:24.257042 INFO: [NOCDAPC] D15_APC_1: 0xfff
10013 08:06:24.259984 INFO: [NOCDAPC] APC_CON: 0x4
10014 08:06:24.263365 INFO: [APUAPC] set_apusys_apc done
10015 08:06:24.267051 INFO: [DEVAPC] devapc_init done
10016 08:06:24.270034 INFO: GICv3 without legacy support detected.
10017 08:06:24.276919 INFO: ARM GICv3 driver initialized in EL3
10018 08:06:24.280043 INFO: Maximum SPI INTID supported: 639
10019 08:06:24.283546 INFO: BL31: Initializing runtime services
10020 08:06:24.290345 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10021 08:06:24.290426 INFO: SPM: enable CPC mode
10022 08:06:24.296986 INFO: mcdi ready for mcusys-off-idle and system suspend
10023 08:06:24.300298 INFO: BL31: Preparing for EL3 exit to normal world
10024 08:06:24.306770 INFO: Entry point address = 0x80000000
10025 08:06:24.306850 INFO: SPSR = 0x8
10026 08:06:24.313432
10027 08:06:24.313511
10028 08:06:24.313575
10029 08:06:24.316361 Starting depthcharge on Spherion...
10030 08:06:24.316441
10031 08:06:24.316504 Wipe memory regions:
10032 08:06:24.316563
10033 08:06:24.317230 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10034 08:06:24.317326 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10035 08:06:24.317411 Setting prompt string to ['asurada:']
10036 08:06:24.317488 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10037 08:06:24.319848 [0x00000040000000, 0x00000054600000)
10038 08:06:24.442118
10039 08:06:24.442234 [0x00000054660000, 0x00000080000000)
10040 08:06:24.702310
10041 08:06:24.702442 [0x000000821a7280, 0x000000ffe64000)
10042 08:06:25.447726
10043 08:06:25.447871 [0x00000100000000, 0x00000240000000)
10044 08:06:27.337759
10045 08:06:27.340573 Initializing XHCI USB controller at 0x11200000.
10046 08:06:28.378836
10047 08:06:28.382245 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10048 08:06:28.382335
10049 08:06:28.382412
10050 08:06:28.382502
10051 08:06:28.382824 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 08:06:28.483179 asurada: tftpboot 192.168.201.1 11585982/tftp-deploy-ced_i668/kernel/image.itb 11585982/tftp-deploy-ced_i668/kernel/cmdline
10054 08:06:28.483306 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 08:06:28.483390 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10056 08:06:28.487807 tftpboot 192.168.201.1 11585982/tftp-deploy-ced_i668/kernel/image.itp-deploy-ced_i668/kernel/cmdline
10057 08:06:28.487891
10058 08:06:28.487954 Waiting for link
10059 08:06:28.645643
10060 08:06:28.645758 R8152: Initializing
10061 08:06:28.645824
10062 08:06:28.649009 Version 6 (ocp_data = 5c30)
10063 08:06:28.649091
10064 08:06:28.652353 R8152: Done initializing
10065 08:06:28.652434
10066 08:06:28.652498 Adding net device
10067 08:06:30.620415
10068 08:06:30.620563 done.
10069 08:06:30.620630
10070 08:06:30.620690 MAC: 00:24:32:30:78:52
10071 08:06:30.620749
10072 08:06:30.624123 Sending DHCP discover... done.
10073 08:06:30.624204
10074 08:06:38.016624 Waiting for reply... done.
10075 08:06:38.017109
10076 08:06:38.017437 Sending DHCP request... done.
10077 08:06:38.019812
10078 08:06:38.024387 Waiting for reply... done.
10079 08:06:38.024802
10080 08:06:38.025132 My ip is 192.168.201.14
10081 08:06:38.025442
10082 08:06:38.028616 The DHCP server ip is 192.168.201.1
10083 08:06:38.029201
10084 08:06:38.035181 TFTP server IP predefined by user: 192.168.201.1
10085 08:06:38.035734
10086 08:06:38.041726 Bootfile predefined by user: 11585982/tftp-deploy-ced_i668/kernel/image.itb
10087 08:06:38.042147
10088 08:06:38.042476 Sending tftp read request... done.
10089 08:06:38.042835
10090 08:06:38.051253 Waiting for the transfer...
10091 08:06:38.051757
10092 08:06:38.779890 00000000 ################################################################
10093 08:06:38.780413
10094 08:06:39.484917 00080000 ################################################################
10095 08:06:39.485046
10096 08:06:40.114756 00100000 ################################################################
10097 08:06:40.114928
10098 08:06:40.702386 00180000 ################################################################
10099 08:06:40.702521
10100 08:06:41.341641 00200000 ################################################################
10101 08:06:41.342157
10102 08:06:42.031252 00280000 ################################################################
10103 08:06:42.031738
10104 08:06:42.680423 00300000 ################################################################
10105 08:06:42.680912
10106 08:06:43.324780 00380000 ################################################################
10107 08:06:43.325289
10108 08:06:43.939521 00400000 ################################################################
10109 08:06:43.939672
10110 08:06:44.495420 00480000 ################################################################
10111 08:06:44.495590
10112 08:06:45.069286 00500000 ################################################################
10113 08:06:45.069444
10114 08:06:45.710385 00580000 ################################################################
10115 08:06:45.710954
10116 08:06:46.393836 00600000 ################################################################
10117 08:06:46.393971
10118 08:06:47.046645 00680000 ################################################################
10119 08:06:47.047223
10120 08:06:47.711430 00700000 ################################################################
10121 08:06:47.711578
10122 08:06:48.360398 00780000 ################################################################
10123 08:06:48.360906
10124 08:06:49.005018 00800000 ################################################################
10125 08:06:49.005152
10126 08:06:49.651141 00880000 ################################################################
10127 08:06:49.651637
10128 08:06:50.268316 00900000 ################################################################
10129 08:06:50.268451
10130 08:06:50.863610 00980000 ################################################################
10131 08:06:50.863803
10132 08:06:51.495890 00a00000 ################################################################
10133 08:06:51.496457
10134 08:06:52.241331 00a80000 ################################################################
10135 08:06:52.241872
10136 08:06:52.881129 00b00000 ################################################################
10137 08:06:52.881282
10138 08:06:53.556670 00b80000 ################################################################
10139 08:06:53.557232
10140 08:06:54.244807 00c00000 ################################################################
10141 08:06:54.245296
10142 08:06:54.952974 00c80000 ################################################################
10143 08:06:54.953461
10144 08:06:55.666787 00d00000 ################################################################
10145 08:06:55.667523
10146 08:06:56.363422 00d80000 ################################################################
10147 08:06:56.363944
10148 08:06:57.050780 00e00000 ################################################################
10149 08:06:57.051298
10150 08:06:57.778424 00e80000 ################################################################
10151 08:06:57.778954
10152 08:06:58.504305 00f00000 ################################################################
10153 08:06:58.504807
10154 08:06:59.206095 00f80000 ################################################################
10155 08:06:59.206588
10156 08:06:59.891775 01000000 ################################################################
10157 08:06:59.892295
10158 08:07:00.599455 01080000 ################################################################
10159 08:07:00.599988
10160 08:07:01.323027 01100000 ################################################################
10161 08:07:01.323576
10162 08:07:02.037801 01180000 ################################################################
10163 08:07:02.038312
10164 08:07:02.768440 01200000 ################################################################
10165 08:07:02.769204
10166 08:07:03.501726 01280000 ################################################################
10167 08:07:03.502233
10168 08:07:04.218024 01300000 ################################################################
10169 08:07:04.218541
10170 08:07:04.913695 01380000 ################################################################
10171 08:07:04.914301
10172 08:07:05.617346 01400000 ################################################################
10173 08:07:05.617877
10174 08:07:06.338382 01480000 ################################################################
10175 08:07:06.338940
10176 08:07:07.030037 01500000 ################################################################
10177 08:07:07.030541
10178 08:07:07.712976 01580000 ################################################################
10179 08:07:07.713598
10180 08:07:08.437649 01600000 ################################################################
10181 08:07:08.437822
10182 08:07:09.155744 01680000 ################################################################
10183 08:07:09.156354
10184 08:07:09.892941 01700000 ################################################################
10185 08:07:09.893527
10186 08:07:10.607548 01780000 ################################################################
10187 08:07:10.608063
10188 08:07:11.324615 01800000 ################################################################
10189 08:07:11.325139
10190 08:07:12.040382 01880000 ################################################################
10191 08:07:12.040891
10192 08:07:12.733739 01900000 ################################################################
10193 08:07:12.734324
10194 08:07:13.444126 01980000 ################################################################
10195 08:07:13.444647
10196 08:07:14.157104 01a00000 ################################################################
10197 08:07:14.157681
10198 08:07:14.895191 01a80000 ################################################################
10199 08:07:14.895783
10200 08:07:15.584800 01b00000 ################################################################
10201 08:07:15.585339
10202 08:07:16.271633 01b80000 ################################################################
10203 08:07:16.272154
10204 08:07:16.976610 01c00000 ################################################################
10205 08:07:16.977177
10206 08:07:17.705980 01c80000 ################################################################
10207 08:07:17.706491
10208 08:07:18.431769 01d00000 ################################################################
10209 08:07:18.432282
10210 08:07:19.148096 01d80000 ################################################################
10211 08:07:19.148601
10212 08:07:19.863808 01e00000 ################################################################
10213 08:07:19.864366
10214 08:07:20.550048 01e80000 ################################################################
10215 08:07:20.550561
10216 08:07:21.262153 01f00000 ################################################################
10217 08:07:21.262666
10218 08:07:21.980012 01f80000 ################################################################
10219 08:07:21.980525
10220 08:07:22.716414 02000000 ################################################################
10221 08:07:22.717067
10222 08:07:23.412769 02080000 ################################################################
10223 08:07:23.413350
10224 08:07:24.105788 02100000 ################################################################
10225 08:07:24.106303
10226 08:07:24.821760 02180000 ################################################################
10227 08:07:24.822347
10228 08:07:25.542230 02200000 ################################################################
10229 08:07:25.542779
10230 08:07:26.231900 02280000 ################################################################
10231 08:07:26.232403
10232 08:07:26.938490 02300000 ################################################################
10233 08:07:26.939202
10234 08:07:27.661182 02380000 ################################################################
10235 08:07:27.661850
10236 08:07:28.371325 02400000 ################################################################
10237 08:07:28.371837
10238 08:07:29.093660 02480000 ################################################################
10239 08:07:29.094195
10240 08:07:29.802892 02500000 ################################################################
10241 08:07:29.803414
10242 08:07:30.503741 02580000 ################################################################
10243 08:07:30.504288
10244 08:07:31.226207 02600000 ################################################################
10245 08:07:31.226880
10246 08:07:31.935253 02680000 ################################################################
10247 08:07:31.935813
10248 08:07:32.629990 02700000 ################################################################
10249 08:07:32.630500
10250 08:07:33.311571 02780000 ################################################################
10251 08:07:33.312074
10252 08:07:34.029408 02800000 ################################################################
10253 08:07:34.029991
10254 08:07:34.738566 02880000 ################################################################
10255 08:07:34.739093
10256 08:07:35.421872 02900000 ################################################################
10257 08:07:35.422432
10258 08:07:36.143572 02980000 ################################################################
10259 08:07:36.144171
10260 08:07:36.848366 02a00000 ################################################################
10261 08:07:36.848929
10262 08:07:37.562970 02a80000 ################################################################
10263 08:07:37.563457
10264 08:07:38.245685 02b00000 ################################################################
10265 08:07:38.246180
10266 08:07:38.924819 02b80000 ################################################################
10267 08:07:38.925333
10268 08:07:39.637654 02c00000 ################################################################
10269 08:07:39.638138
10270 08:07:40.365671 02c80000 ################################################################
10271 08:07:40.366193
10272 08:07:41.078432 02d00000 ################################################################
10273 08:07:41.079041
10274 08:07:41.803837 02d80000 ################################################################
10275 08:07:41.804397
10276 08:07:42.520629 02e00000 ################################################################
10277 08:07:42.521261
10278 08:07:43.249438 02e80000 ################################################################
10279 08:07:43.249949
10280 08:07:43.972392 02f00000 ################################################################
10281 08:07:43.972958
10282 08:07:44.699468 02f80000 ################################################################
10283 08:07:44.699990
10284 08:07:45.425977 03000000 ################################################################
10285 08:07:45.426695
10286 08:07:46.134217 03080000 ################################################################
10287 08:07:46.134709
10288 08:07:46.858591 03100000 ################################################################
10289 08:07:46.859141
10290 08:07:47.585499 03180000 ################################################################
10291 08:07:47.586082
10292 08:07:48.301933 03200000 ################################################################
10293 08:07:48.302461
10294 08:07:49.004518 03280000 ################################################################
10295 08:07:49.005134
10296 08:07:49.711545 03300000 ################################################################
10297 08:07:49.712063
10298 08:07:50.414804 03380000 ################################################################
10299 08:07:50.415454
10300 08:07:51.131270 03400000 ################################################################
10301 08:07:51.131793
10302 08:07:51.805554 03480000 ################################################################
10303 08:07:51.806049
10304 08:07:52.517830 03500000 ################################################################
10305 08:07:52.518372
10306 08:07:53.246087 03580000 ################################################################
10307 08:07:53.246797
10308 08:07:53.937395 03600000 ################################################################
10309 08:07:53.938008
10310 08:07:54.649449 03680000 ################################################################
10311 08:07:54.650230
10312 08:07:55.377399 03700000 ################################################################
10313 08:07:55.378000
10314 08:07:55.943100 03780000 #################################################### done.
10315 08:07:55.943654
10316 08:07:55.946099 The bootfile was 58620586 bytes long.
10317 08:07:55.946515
10318 08:07:55.949589 Sending tftp read request... done.
10319 08:07:55.950000
10320 08:07:55.953823 Waiting for the transfer...
10321 08:07:55.954253
10322 08:07:55.954795 00000000 # done.
10323 08:07:55.955225
10324 08:07:55.960762 Command line loaded dynamically from TFTP file: 11585982/tftp-deploy-ced_i668/kernel/cmdline
10325 08:07:55.961188
10326 08:07:55.973705 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10327 08:07:55.977359
10328 08:07:55.977884 Loading FIT.
10329 08:07:55.978326
10330 08:07:55.980283 Image ramdisk-1 has 47526005 bytes.
10331 08:07:55.980708
10332 08:07:55.983505 Image fdt-1 has 47278 bytes.
10333 08:07:55.983929
10334 08:07:55.984360 Image kernel-1 has 11045265 bytes.
10335 08:07:55.987124
10336 08:07:55.994313 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10337 08:07:55.994918
10338 08:07:56.010645 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10339 08:07:56.011247
10340 08:07:56.017251 Choosing best match conf-1 for compat google,spherion-rev2.
10341 08:07:56.021448
10342 08:07:56.026359 Connected to device vid:did:rid of 1ae0:0028:00
10343 08:07:56.034317
10344 08:07:56.037606 tpm_get_response: command 0x17b, return code 0x0
10345 08:07:56.038138
10346 08:07:56.044403 ec_init: CrosEC protocol v3 supported (256, 248)
10347 08:07:56.045036
10348 08:07:56.047761 tpm_cleanup: add release locality here.
10349 08:07:56.048186
10350 08:07:56.051159 Shutting down all USB controllers.
10351 08:07:56.051694
10352 08:07:56.054418 Removing current net device
10353 08:07:56.054878
10354 08:07:56.057572 Exiting depthcharge with code 4 at timestamp: 121105839
10355 08:07:56.057998
10356 08:07:56.064335 LZMA decompressing kernel-1 to 0x821a6718
10357 08:07:56.064846
10358 08:07:56.067696 LZMA decompressing kernel-1 to 0x40000000
10359 08:07:57.455114
10360 08:07:57.455683 jumping to kernel
10361 08:07:57.458163 end: 2.2.4 bootloader-commands (duration 00:01:33) [common]
10362 08:07:57.458915 start: 2.2.5 auto-login-action (timeout 00:02:52) [common]
10363 08:07:57.459494 Setting prompt string to ['Linux version [0-9]']
10364 08:07:57.460096 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10365 08:07:57.460496 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10366 08:07:57.536755
10367 08:07:57.540316 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10368 08:07:57.543973 start: 2.2.5.1 login-action (timeout 00:02:52) [common]
10369 08:07:57.544502 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10370 08:07:57.544968 Setting prompt string to []
10371 08:07:57.545532 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10372 08:07:57.545970 Using line separator: #'\n'#
10373 08:07:57.546343 No login prompt set.
10374 08:07:57.546776 Parsing kernel messages
10375 08:07:57.547163 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10376 08:07:57.548073 [login-action] Waiting for messages, (timeout 00:02:52)
10377 08:07:57.563557 [ 0.000000] Linux version 6.1.54-cip6 (KernelCI@build-j53272-arm64-gcc-10-defconfig-arm64-chromebook-xzlx8) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023
10378 08:07:57.566643 [ 0.000000] random: crng init done
10379 08:07:57.570147 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10380 08:07:57.573445 [ 0.000000] efi: UEFI not found.
10381 08:07:57.583852 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10382 08:07:57.590254 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10383 08:07:57.600255 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10384 08:07:57.610438 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10385 08:07:57.616690 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10386 08:07:57.619864 [ 0.000000] printk: bootconsole [mtk8250] enabled
10387 08:07:57.628555 [ 0.000000] NUMA: No NUMA configuration found
10388 08:07:57.635275 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10389 08:07:57.642294 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10390 08:07:57.642889 [ 0.000000] Zone ranges:
10391 08:07:57.648360 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10392 08:07:57.651667 [ 0.000000] DMA32 empty
10393 08:07:57.658710 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10394 08:07:57.662143 [ 0.000000] Movable zone start for each node
10395 08:07:57.665545 [ 0.000000] Early memory node ranges
10396 08:07:57.671796 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10397 08:07:57.678462 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10398 08:07:57.685172 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10399 08:07:57.691920 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10400 08:07:57.698876 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10401 08:07:57.705227 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10402 08:07:57.761065 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10403 08:07:57.767497 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10404 08:07:57.774608 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10405 08:07:57.777600 [ 0.000000] psci: probing for conduit method from DT.
10406 08:07:57.784399 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10407 08:07:57.787617 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10408 08:07:57.794647 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10409 08:07:57.797867 [ 0.000000] psci: SMC Calling Convention v1.2
10410 08:07:57.804377 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10411 08:07:57.807567 [ 0.000000] Detected VIPT I-cache on CPU0
10412 08:07:57.814716 [ 0.000000] CPU features: detected: GIC system register CPU interface
10413 08:07:57.821096 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10414 08:07:57.827738 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10415 08:07:57.834563 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10416 08:07:57.840914 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10417 08:07:57.847851 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10418 08:07:57.854811 [ 0.000000] alternatives: applying boot alternatives
10419 08:07:57.858258 [ 0.000000] Fallback order for Node 0: 0
10420 08:07:57.864973 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10421 08:07:57.867974 [ 0.000000] Policy zone: Normal
10422 08:07:57.884690 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10423 08:07:57.894634 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10424 08:07:57.904678 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10425 08:07:57.914801 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10426 08:07:57.921372 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10427 08:07:57.924883 <6>[ 0.000000] software IO TLB: area num 8.
10428 08:07:57.980343 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10429 08:07:58.129758 <6>[ 0.000000] Memory: 7923016K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 429752K reserved, 32768K cma-reserved)
10430 08:07:58.136661 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10431 08:07:58.143282 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10432 08:07:58.146846 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10433 08:07:58.153424 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10434 08:07:58.160169 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10435 08:07:58.163923 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10436 08:07:58.173587 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10437 08:07:58.180308 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10438 08:07:58.183269 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10439 08:07:58.191094 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10440 08:07:58.194214 <6>[ 0.000000] GICv3: 608 SPIs implemented
10441 08:07:58.200975 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10442 08:07:58.204110 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10443 08:07:58.207591 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10444 08:07:58.217178 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10445 08:07:58.227673 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10446 08:07:58.240663 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10447 08:07:58.247344 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10448 08:07:58.256167 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10449 08:07:58.269504 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10450 08:07:58.276482 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10451 08:07:58.283313 <6>[ 0.009182] Console: colour dummy device 80x25
10452 08:07:58.293023 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10453 08:07:58.299624 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10454 08:07:58.302599 <6>[ 0.029220] LSM: Security Framework initializing
10455 08:07:58.309742 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10456 08:07:58.319395 <6>[ 0.042000] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10457 08:07:58.325946 <6>[ 0.051457] cblist_init_generic: Setting adjustable number of callback queues.
10458 08:07:58.332818 <6>[ 0.058902] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 08:07:58.342962 <6>[ 0.065240] cblist_init_generic: Setting adjustable number of callback queues.
10460 08:07:58.345786 <6>[ 0.072713] cblist_init_generic: Setting shift to 3 and lim to 1.
10461 08:07:58.352581 <6>[ 0.079141] rcu: Hierarchical SRCU implementation.
10462 08:07:58.359377 <6>[ 0.084156] rcu: Max phase no-delay instances is 1000.
10463 08:07:58.365703 <6>[ 0.091188] EFI services will not be available.
10464 08:07:58.369316 <6>[ 0.096173] smp: Bringing up secondary CPUs ...
10465 08:07:58.377003 <6>[ 0.101220] Detected VIPT I-cache on CPU1
10466 08:07:58.384253 <6>[ 0.101293] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10467 08:07:58.390529 <6>[ 0.101322] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10468 08:07:58.393810 <6>[ 0.101659] Detected VIPT I-cache on CPU2
10469 08:07:58.400905 <6>[ 0.101708] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10470 08:07:58.407727 <6>[ 0.101724] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10471 08:07:58.413916 <6>[ 0.101980] Detected VIPT I-cache on CPU3
10472 08:07:58.420627 <6>[ 0.102027] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10473 08:07:58.427274 <6>[ 0.102041] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10474 08:07:58.430320 <6>[ 0.102343] CPU features: detected: Spectre-v4
10475 08:07:58.437285 <6>[ 0.102349] CPU features: detected: Spectre-BHB
10476 08:07:58.440862 <6>[ 0.102354] Detected PIPT I-cache on CPU4
10477 08:07:58.447673 <6>[ 0.102411] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10478 08:07:58.454139 <6>[ 0.102428] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10479 08:07:58.457573 <6>[ 0.102721] Detected PIPT I-cache on CPU5
10480 08:07:58.467322 <6>[ 0.102783] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10481 08:07:58.474148 <6>[ 0.102799] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10482 08:07:58.477363 <6>[ 0.103082] Detected PIPT I-cache on CPU6
10483 08:07:58.484558 <6>[ 0.103148] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10484 08:07:58.490686 <6>[ 0.103164] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10485 08:07:58.494352 <6>[ 0.103461] Detected PIPT I-cache on CPU7
10486 08:07:58.501091 <6>[ 0.103525] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10487 08:07:58.507573 <6>[ 0.103541] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10488 08:07:58.514645 <6>[ 0.103589] smp: Brought up 1 node, 8 CPUs
10489 08:07:58.517945 <6>[ 0.244807] SMP: Total of 8 processors activated.
10490 08:07:58.524356 <6>[ 0.249758] CPU features: detected: 32-bit EL0 Support
10491 08:07:58.534025 <6>[ 0.255120] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10492 08:07:58.540726 <6>[ 0.263975] CPU features: detected: Common not Private translations
10493 08:07:58.544041 <6>[ 0.270491] CPU features: detected: CRC32 instructions
10494 08:07:58.550801 <6>[ 0.275875] CPU features: detected: RCpc load-acquire (LDAPR)
10495 08:07:58.557064 <6>[ 0.281835] CPU features: detected: LSE atomic instructions
10496 08:07:58.560711 <6>[ 0.287616] CPU features: detected: Privileged Access Never
10497 08:07:58.567445 <6>[ 0.293396] CPU features: detected: RAS Extension Support
10498 08:07:58.573686 <6>[ 0.299004] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10499 08:07:58.580485 <6>[ 0.306269] CPU: All CPU(s) started at EL2
10500 08:07:58.583810 <6>[ 0.310586] alternatives: applying system-wide alternatives
10501 08:07:58.595126 <6>[ 0.321296] devtmpfs: initialized
10502 08:07:58.607350 <6>[ 0.330285] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10503 08:07:58.617437 <6>[ 0.340249] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10504 08:07:58.624248 <6>[ 0.348504] pinctrl core: initialized pinctrl subsystem
10505 08:07:58.627404 <6>[ 0.355147] DMI not present or invalid.
10506 08:07:58.634169 <6>[ 0.359559] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10507 08:07:58.643780 <6>[ 0.366448] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10508 08:07:58.650590 <6>[ 0.374033] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10509 08:07:58.660801 <6>[ 0.382260] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10510 08:07:58.664308 <6>[ 0.390505] audit: initializing netlink subsys (disabled)
10511 08:07:58.674305 <5>[ 0.396199] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10512 08:07:58.680471 <6>[ 0.396901] thermal_sys: Registered thermal governor 'step_wise'
10513 08:07:58.687236 <6>[ 0.404167] thermal_sys: Registered thermal governor 'power_allocator'
10514 08:07:58.690261 <6>[ 0.410423] cpuidle: using governor menu
10515 08:07:58.694128 <6>[ 0.421384] NET: Registered PF_QIPCRTR protocol family
10516 08:07:58.703465 <6>[ 0.426869] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10517 08:07:58.707068 <6>[ 0.433974] ASID allocator initialised with 32768 entries
10518 08:07:58.714136 <6>[ 0.440536] Serial: AMBA PL011 UART driver
10519 08:07:58.723637 <4>[ 0.449320] Trying to register duplicate clock ID: 134
10520 08:07:58.779233 <6>[ 0.508908] KASLR enabled
10521 08:07:58.793853 <6>[ 0.516659] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10522 08:07:58.800050 <6>[ 0.523674] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10523 08:07:58.806881 <6>[ 0.530162] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10524 08:07:58.813449 <6>[ 0.537167] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10525 08:07:58.820077 <6>[ 0.543655] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10526 08:07:58.826622 <6>[ 0.550659] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10527 08:07:58.834106 <6>[ 0.557148] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10528 08:07:58.840361 <6>[ 0.564154] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10529 08:07:58.843415 <6>[ 0.571677] ACPI: Interpreter disabled.
10530 08:07:58.851715 <6>[ 0.578113] iommu: Default domain type: Translated
10531 08:07:58.859648 <6>[ 0.583226] iommu: DMA domain TLB invalidation policy: strict mode
10532 08:07:58.861607 <5>[ 0.589887] SCSI subsystem initialized
10533 08:07:58.868641 <6>[ 0.594051] usbcore: registered new interface driver usbfs
10534 08:07:58.874951 <6>[ 0.599786] usbcore: registered new interface driver hub
10535 08:07:58.878843 <6>[ 0.605338] usbcore: registered new device driver usb
10536 08:07:58.885381 <6>[ 0.611443] pps_core: LinuxPPS API ver. 1 registered
10537 08:07:58.895180 <6>[ 0.616637] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10538 08:07:58.898293 <6>[ 0.625984] PTP clock support registered
10539 08:07:58.902112 <6>[ 0.630228] EDAC MC: Ver: 3.0.0
10540 08:07:58.909346 <6>[ 0.635408] FPGA manager framework
10541 08:07:58.912810 <6>[ 0.639089] Advanced Linux Sound Architecture Driver Initialized.
10542 08:07:58.916027 <6>[ 0.645869] vgaarb: loaded
10543 08:07:58.922902 <6>[ 0.648968] clocksource: Switched to clocksource arch_sys_counter
10544 08:07:58.929465 <5>[ 0.655410] VFS: Disk quotas dquot_6.6.0
10545 08:07:58.936171 <6>[ 0.659597] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10546 08:07:58.939439 <6>[ 0.666790] pnp: PnP ACPI: disabled
10547 08:07:58.947144 <6>[ 0.673503] NET: Registered PF_INET protocol family
10548 08:07:58.956797 <6>[ 0.679100] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10549 08:07:58.968624 <6>[ 0.691420] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10550 08:07:58.978577 <6>[ 0.700233] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10551 08:07:58.985145 <6>[ 0.708205] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10552 08:07:58.991690 <6>[ 0.716905] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10553 08:07:59.003347 <6>[ 0.726666] TCP: Hash tables configured (established 65536 bind 65536)
10554 08:07:59.010572 <6>[ 0.733535] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10555 08:07:59.016960 <6>[ 0.740737] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 08:07:59.023458 <6>[ 0.748436] NET: Registered PF_UNIX/PF_LOCAL protocol family
10557 08:07:59.030618 <6>[ 0.754596] RPC: Registered named UNIX socket transport module.
10558 08:07:59.033450 <6>[ 0.760750] RPC: Registered udp transport module.
10559 08:07:59.040695 <6>[ 0.765682] RPC: Registered tcp transport module.
10560 08:07:59.047181 <6>[ 0.770614] RPC: Registered tcp NFSv4.1 backchannel transport module.
10561 08:07:59.050108 <6>[ 0.777278] PCI: CLS 0 bytes, default 64
10562 08:07:59.053228 <6>[ 0.781609] Unpacking initramfs...
10563 08:07:59.078315 <6>[ 0.801250] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10564 08:07:59.088512 <6>[ 0.809898] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10565 08:07:59.091742 <6>[ 0.818727] kvm [1]: IPA Size Limit: 40 bits
10566 08:07:59.098274 <6>[ 0.823256] kvm [1]: GICv3: no GICV resource entry
10567 08:07:59.102013 <6>[ 0.828278] kvm [1]: disabling GICv2 emulation
10568 08:07:59.108428 <6>[ 0.832965] kvm [1]: GIC system register CPU interface enabled
10569 08:07:59.112049 <6>[ 0.839133] kvm [1]: vgic interrupt IRQ18
10570 08:07:59.118069 <6>[ 0.843487] kvm [1]: VHE mode initialized successfully
10571 08:07:59.124912 <5>[ 0.849926] Initialise system trusted keyrings
10572 08:07:59.131554 <6>[ 0.854734] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10573 08:07:59.138437 <6>[ 0.864730] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10574 08:07:59.145055 <5>[ 0.871106] NFS: Registering the id_resolver key type
10575 08:07:59.148868 <5>[ 0.876407] Key type id_resolver registered
10576 08:07:59.155210 <5>[ 0.880821] Key type id_legacy registered
10577 08:07:59.161435 <6>[ 0.885115] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10578 08:07:59.168739 <6>[ 0.892037] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10579 08:07:59.174801 <6>[ 0.899750] 9p: Installing v9fs 9p2000 file system support
10580 08:07:59.211674 <5>[ 0.937393] Key type asymmetric registered
10581 08:07:59.214254 <5>[ 0.941726] Asymmetric key parser 'x509' registered
10582 08:07:59.224353 <6>[ 0.946866] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10583 08:07:59.228085 <6>[ 0.954480] io scheduler mq-deadline registered
10584 08:07:59.230807 <6>[ 0.959273] io scheduler kyber registered
10585 08:07:59.249919 <6>[ 0.976351] EINJ: ACPI disabled.
10586 08:07:59.282229 <4>[ 1.001706] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 08:07:59.292259 <4>[ 1.012356] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 08:07:59.306669 <6>[ 1.033158] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10589 08:07:59.314972 <6>[ 1.041124] printk: console [ttyS0] disabled
10590 08:07:59.342798 <6>[ 1.065767] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10591 08:07:59.349281 <6>[ 1.075246] printk: console [ttyS0] enabled
10592 08:07:59.352263 <6>[ 1.075246] printk: console [ttyS0] enabled
10593 08:07:59.359237 <6>[ 1.084140] printk: bootconsole [mtk8250] disabled
10594 08:07:59.362694 <6>[ 1.084140] printk: bootconsole [mtk8250] disabled
10595 08:07:59.369350 <6>[ 1.095463] SuperH (H)SCI(F) driver initialized
10596 08:07:59.372033 <6>[ 1.100747] msm_serial: driver initialized
10597 08:07:59.386815 <6>[ 1.109746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10598 08:07:59.396721 <6>[ 1.118293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10599 08:07:59.403264 <6>[ 1.126835] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10600 08:07:59.413232 <6>[ 1.135464] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10601 08:07:59.423156 <6>[ 1.144170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10602 08:07:59.429557 <6>[ 1.152883] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10603 08:07:59.439896 <6>[ 1.161431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10604 08:07:59.446678 <6>[ 1.170236] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10605 08:07:59.456564 <6>[ 1.178795] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10606 08:07:59.468130 <6>[ 1.194626] loop: module loaded
10607 08:07:59.474697 <6>[ 1.200646] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10608 08:07:59.497998 <4>[ 1.224106] mtk-pmic-keys: Failed to locate of_node [id: -1]
10609 08:07:59.504478 <6>[ 1.231170] megasas: 07.719.03.00-rc1
10610 08:07:59.514802 <6>[ 1.240922] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10611 08:07:59.522388 <6>[ 1.248388] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10612 08:07:59.539330 <6>[ 1.265166] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10613 08:07:59.595597 <6>[ 1.315237] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10614 08:08:01.083014 <6>[ 2.809794] Freeing initrd memory: 46408K
10615 08:08:01.093602 <6>[ 2.820383] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10616 08:08:01.104503 <6>[ 2.831280] tun: Universal TUN/TAP device driver, 1.6
10617 08:08:01.107722 <6>[ 2.837356] thunder_xcv, ver 1.0
10618 08:08:01.111453 <6>[ 2.840852] thunder_bgx, ver 1.0
10619 08:08:01.114670 <6>[ 2.844349] nicpf, ver 1.0
10620 08:08:01.125196 <6>[ 2.848387] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10621 08:08:01.128211 <6>[ 2.855863] hns3: Copyright (c) 2017 Huawei Corporation.
10622 08:08:01.135163 <6>[ 2.861486] hclge is initializing
10623 08:08:01.138686 <6>[ 2.865061] e1000: Intel(R) PRO/1000 Network Driver
10624 08:08:01.145038 <6>[ 2.870190] e1000: Copyright (c) 1999-2006 Intel Corporation.
10625 08:08:01.148417 <6>[ 2.876204] e1000e: Intel(R) PRO/1000 Network Driver
10626 08:08:01.155259 <6>[ 2.881420] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10627 08:08:01.161884 <6>[ 2.887605] igb: Intel(R) Gigabit Ethernet Network Driver
10628 08:08:01.168293 <6>[ 2.893255] igb: Copyright (c) 2007-2014 Intel Corporation.
10629 08:08:01.174616 <6>[ 2.899092] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10630 08:08:01.181634 <6>[ 2.905610] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10631 08:08:01.184760 <6>[ 2.912077] sky2: driver version 1.30
10632 08:08:01.191699 <6>[ 2.917089] VFIO - User Level meta-driver version: 0.3
10633 08:08:01.198522 <6>[ 2.925337] usbcore: registered new interface driver usb-storage
10634 08:08:01.205096 <6>[ 2.931791] usbcore: registered new device driver onboard-usb-hub
10635 08:08:01.214389 <6>[ 2.940902] mt6397-rtc mt6359-rtc: registered as rtc0
10636 08:08:01.224363 <6>[ 2.946368] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T08:08:02 UTC (1695283682)
10637 08:08:01.227423 <6>[ 2.955935] i2c_dev: i2c /dev entries driver
10638 08:08:01.244437 <6>[ 2.967785] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10639 08:08:01.265467 <6>[ 2.991802] cpu cpu0: EM: created perf domain
10640 08:08:01.268614 <6>[ 2.996736] cpu cpu4: EM: created perf domain
10641 08:08:01.275706 <6>[ 3.002357] sdhci: Secure Digital Host Controller Interface driver
10642 08:08:01.282333 <6>[ 3.008790] sdhci: Copyright(c) Pierre Ossman
10643 08:08:01.289559 <6>[ 3.013757] Synopsys Designware Multimedia Card Interface Driver
10644 08:08:01.292184 <6>[ 3.020381] mmc0: CQHCI version 5.10
10645 08:08:01.298878 <6>[ 3.020388] sdhci-pltfm: SDHCI platform and OF driver helper
10646 08:08:01.305645 <6>[ 3.031205] ledtrig-cpu: registered to indicate activity on CPUs
10647 08:08:01.312750 <6>[ 3.038208] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10648 08:08:01.319337 <6>[ 3.045235] usbcore: registered new interface driver usbhid
10649 08:08:01.321958 <6>[ 3.051059] usbhid: USB HID core driver
10650 08:08:01.332153 <6>[ 3.055254] spi_master spi0: will run message pump with realtime priority
10651 08:08:01.374267 <6>[ 3.094227] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10652 08:08:01.392476 <6>[ 3.109356] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10653 08:08:01.396339 <6>[ 3.122967] mmc0: Command Queue Engine enabled
10654 08:08:01.402802 <6>[ 3.127745] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10655 08:08:01.409766 <6>[ 3.134696] cros-ec-spi spi0.0: Chrome EC device registered
10656 08:08:01.413108 <6>[ 3.135011] mmcblk0: mmc0:0001 DA4128 116 GiB
10657 08:08:01.423419 <6>[ 3.149627] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10658 08:08:01.430864 <6>[ 3.157281] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10659 08:08:01.437758 <6>[ 3.163162] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10660 08:08:01.444163 <6>[ 3.169155] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10661 08:08:01.458860 <6>[ 3.182231] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10662 08:08:01.465750 <6>[ 3.192625] NET: Registered PF_PACKET protocol family
10663 08:08:01.469653 <6>[ 3.198035] 9pnet: Installing 9P2000 support
10664 08:08:01.476039 <5>[ 3.202598] Key type dns_resolver registered
10665 08:08:01.479588 <6>[ 3.207584] registered taskstats version 1
10666 08:08:01.485864 <5>[ 3.211977] Loading compiled-in X.509 certificates
10667 08:08:01.516533 <4>[ 3.236439] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10668 08:08:01.526589 <4>[ 3.247242] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 08:08:01.533137 <3>[ 3.257852] debugfs: File 'uA_load' in directory '/' already present!
10670 08:08:01.539811 <3>[ 3.264561] debugfs: File 'min_uV' in directory '/' already present!
10671 08:08:01.546694 <3>[ 3.271171] debugfs: File 'max_uV' in directory '/' already present!
10672 08:08:01.553120 <3>[ 3.277779] debugfs: File 'constraint_flags' in directory '/' already present!
10673 08:08:01.564374 <3>[ 3.287600] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10674 08:08:01.577999 <6>[ 3.304905] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10675 08:08:01.584880 <6>[ 3.311796] xhci-mtk 11200000.usb: xHCI Host Controller
10676 08:08:01.592226 <6>[ 3.317337] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10677 08:08:01.602104 <6>[ 3.325218] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10678 08:08:01.608341 <6>[ 3.334652] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10679 08:08:01.615042 <6>[ 3.340754] xhci-mtk 11200000.usb: xHCI Host Controller
10680 08:08:01.622196 <6>[ 3.346241] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10681 08:08:01.628306 <6>[ 3.353897] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10682 08:08:01.635218 <6>[ 3.361788] hub 1-0:1.0: USB hub found
10683 08:08:01.638696 <6>[ 3.365813] hub 1-0:1.0: 1 port detected
10684 08:08:01.645370 <6>[ 3.370126] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10685 08:08:01.652383 <6>[ 3.378942] hub 2-0:1.0: USB hub found
10686 08:08:01.655360 <6>[ 3.382963] hub 2-0:1.0: 1 port detected
10687 08:08:01.663937 <6>[ 3.390613] mtk-msdc 11f70000.mmc: Got CD GPIO
10688 08:08:01.675526 <6>[ 3.398872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10689 08:08:01.681847 <6>[ 3.406908] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10690 08:08:01.692155 <4>[ 3.414855] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10691 08:08:01.701641 <6>[ 3.424427] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10692 08:08:01.708433 <6>[ 3.432510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10693 08:08:01.715082 <6>[ 3.440527] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10694 08:08:01.725563 <6>[ 3.448444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10695 08:08:01.732068 <6>[ 3.456261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10696 08:08:01.742211 <6>[ 3.464077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10697 08:08:01.752136 <6>[ 3.474477] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10698 08:08:01.758272 <6>[ 3.482846] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10699 08:08:01.769128 <6>[ 3.491193] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10700 08:08:01.775233 <6>[ 3.499532] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10701 08:08:01.784944 <6>[ 3.507870] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10702 08:08:01.792151 <6>[ 3.516208] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10703 08:08:01.802127 <6>[ 3.524547] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10704 08:08:01.808815 <6>[ 3.532885] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10705 08:08:01.818353 <6>[ 3.541227] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10706 08:08:01.825214 <6>[ 3.549565] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10707 08:08:01.835115 <6>[ 3.557902] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10708 08:08:01.842271 <6>[ 3.566240] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10709 08:08:01.851633 <6>[ 3.574577] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10710 08:08:01.858297 <6>[ 3.582916] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10711 08:08:01.868662 <6>[ 3.591253] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10712 08:08:01.875036 <6>[ 3.599990] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10713 08:08:01.881387 <6>[ 3.607161] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10714 08:08:01.887987 <6>[ 3.613927] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10715 08:08:01.895256 <6>[ 3.620693] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10716 08:08:01.901534 <6>[ 3.627626] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10717 08:08:01.911237 <6>[ 3.634489] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10718 08:08:01.921240 <6>[ 3.643620] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10719 08:08:01.931138 <6>[ 3.652743] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10720 08:08:01.941451 <6>[ 3.662037] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10721 08:08:01.947731 <6>[ 3.671507] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10722 08:08:01.957652 <6>[ 3.680974] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10723 08:08:01.967625 <6>[ 3.690095] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10724 08:08:01.977702 <6>[ 3.699562] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10725 08:08:01.987630 <6>[ 3.708683] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10726 08:08:01.997501 <6>[ 3.717977] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10727 08:08:02.007531 <6>[ 3.728138] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10728 08:08:02.017455 <6>[ 3.739494] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10729 08:08:02.070110 <6>[ 3.793245] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10730 08:08:02.224565 <6>[ 3.951185] hub 1-1:1.0: USB hub found
10731 08:08:02.227492 <6>[ 3.955666] hub 1-1:1.0: 4 ports detected
10732 08:08:02.349836 <6>[ 4.073276] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10733 08:08:02.375735 <6>[ 4.102607] hub 2-1:1.0: USB hub found
10734 08:08:02.379452 <6>[ 4.107074] hub 2-1:1.0: 3 ports detected
10735 08:08:02.549859 <6>[ 4.273250] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10736 08:08:02.682561 <6>[ 4.409166] hub 1-1.4:1.0: USB hub found
10737 08:08:02.685673 <6>[ 4.413839] hub 1-1.4:1.0: 2 ports detected
10738 08:08:02.762056 <6>[ 4.485431] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10739 08:08:02.981735 <6>[ 4.705296] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10740 08:08:03.174302 <6>[ 4.897293] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10741 08:08:14.315310 <6>[ 16.046300] ALSA device list:
10742 08:08:14.321998 <6>[ 16.049585] No soundcards found.
10743 08:08:14.329506 <6>[ 16.057625] Freeing unused kernel memory: 8448K
10744 08:08:14.332723 <6>[ 16.062619] Run /init as init process
10745 08:08:14.382526 <6>[ 16.110299] NET: Registered PF_INET6 protocol family
10746 08:08:14.389129 <6>[ 16.116640] Segment Routing with IPv6
10747 08:08:14.392204 <6>[ 16.120593] In-situ OAM (IOAM) with IPv6
10748 08:08:14.424824 <30>[ 16.135973] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10749 08:08:14.431724 <30>[ 16.160001] systemd[1]: Detected architecture arm64.
10750 08:08:14.432295
10751 08:08:14.439112 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10752 08:08:14.439678
10753 08:08:14.453047 <30>[ 16.181388] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10754 08:08:14.596191 <30>[ 16.321484] systemd[1]: Queued start job for default target Graphical Interface.
10755 08:08:14.622107 <30>[ 16.350130] systemd[1]: Created slice system-getty.slice.
10756 08:08:14.628596 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10757 08:08:14.645761 <30>[ 16.373659] systemd[1]: Created slice system-modprobe.slice.
10758 08:08:14.652125 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10759 08:08:14.669327 <30>[ 16.397733] systemd[1]: Created slice system-serial\x2dgetty.slice.
10760 08:08:14.679743 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10761 08:08:14.693247 <30>[ 16.421659] systemd[1]: Created slice User and Session Slice.
10762 08:08:14.700203 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10763 08:08:14.721429 <30>[ 16.445820] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10764 08:08:14.731154 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10765 08:08:14.749321 <30>[ 16.473811] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10766 08:08:14.755624 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10767 08:08:14.779976 <30>[ 16.501346] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10768 08:08:14.786539 <30>[ 16.513519] systemd[1]: Reached target Local Encrypted Volumes.
10769 08:08:14.793737 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10770 08:08:14.809680 <30>[ 16.537762] systemd[1]: Reached target Paths.
10771 08:08:14.813552 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10772 08:08:14.829253 <30>[ 16.557276] systemd[1]: Reached target Remote File Systems.
10773 08:08:14.835945 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10774 08:08:14.853373 <30>[ 16.581638] systemd[1]: Reached target Slices.
10775 08:08:14.859832 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10776 08:08:14.873062 <30>[ 16.601317] systemd[1]: Reached target Swap.
10777 08:08:14.876454 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10778 08:08:14.896583 <30>[ 16.621783] systemd[1]: Listening on initctl Compatibility Named Pipe.
10779 08:08:14.903285 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10780 08:08:14.910180 <30>[ 16.637077] systemd[1]: Listening on Journal Audit Socket.
10781 08:08:14.916827 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10782 08:08:14.929973 <30>[ 16.657774] systemd[1]: Listening on Journal Socket (/dev/log).
10783 08:08:14.936202 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10784 08:08:14.954461 <30>[ 16.682536] systemd[1]: Listening on Journal Socket.
10785 08:08:14.960972 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10786 08:08:14.973837 <30>[ 16.701971] systemd[1]: Listening on Network Service Netlink Socket.
10787 08:08:14.984171 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10788 08:08:14.998650 <30>[ 16.726479] systemd[1]: Listening on udev Control Socket.
10789 08:08:15.004791 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10790 08:08:15.022148 <30>[ 16.750365] systemd[1]: Listening on udev Kernel Socket.
10791 08:08:15.029485 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10792 08:08:15.077129 <30>[ 16.805297] systemd[1]: Mounting Huge Pages File System...
10793 08:08:15.083507 Mounting [0;1;39mHuge Pages File System[0m...
10794 08:08:15.101942 <30>[ 16.827085] systemd[1]: Mounting POSIX Message Queue File System...
10795 08:08:15.105195 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10796 08:08:15.129818 <30>[ 16.857295] systemd[1]: Mounting Kernel Debug File System...
10797 08:08:15.135514 Mounting [0;1;39mKernel Debug File System[0m...
10798 08:08:15.157065 <30>[ 16.881896] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10799 08:08:15.170527 <30>[ 16.895168] systemd[1]: Starting Create list of static device nodes for the current kernel...
10800 08:08:15.177520 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10801 08:08:15.197831 <30>[ 16.926185] systemd[1]: Starting Load Kernel Module configfs...
10802 08:08:15.204533 Starting [0;1;39mLoad Kernel Module configfs[0m...
10803 08:08:15.225625 <30>[ 16.953953] systemd[1]: Starting Load Kernel Module drm...
10804 08:08:15.232951 Starting [0;1;39mLoad Kernel Module drm[0m...
10805 08:08:15.252938 <30>[ 16.977728] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10806 08:08:15.268060 <30>[ 16.995913] systemd[1]: Starting Journal Service...
10807 08:08:15.270964 Starting [0;1;39mJournal Service[0m...
10808 08:08:15.294717 <30>[ 17.022898] systemd[1]: Starting Load Kernel Modules...
10809 08:08:15.301293 Starting [0;1;39mLoad Kernel Modules[0m...
10810 08:08:15.325175 <30>[ 17.050097] systemd[1]: Starting Remount Root and Kernel File Systems...
10811 08:08:15.331577 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10812 08:08:15.353535 <30>[ 17.081467] systemd[1]: Starting Coldplug All udev Devices...
10813 08:08:15.359312 Starting [0;1;39mColdplug All udev Devices[0m...
10814 08:08:15.379734 <30>[ 17.108091] systemd[1]: Started Journal Service.
10815 08:08:15.386142 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10816 08:08:15.407893 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10817 08:08:15.431037 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10818 08:08:15.445737 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10819 08:08:15.466710 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10820 08:08:15.483726 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10821 08:08:15.503665 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10822 08:08:15.522798 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10823 08:08:15.543330 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10824 08:08:15.557307 See 'systemctl status systemd-remount-fs.service' for details.
10825 08:08:15.633436 Mounting [0;1;39mKernel Configuration File System[0m...
10826 08:08:15.654266 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10827 08:08:15.674036 <46>[ 17.399035] systemd-journald[178]: Received client request to flush runtime journal.
10828 08:08:15.680777 Starting [0;1;39mLoad/Save Random Seed[0m...
10829 08:08:15.697834 Starting [0;1;39mApply Kernel Variables[0m...
10830 08:08:15.718397 Starting [0;1;39mCreate System Users[0m...
10831 08:08:15.738476 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10832 08:08:15.754170 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10833 08:08:15.773957 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10834 08:08:15.787375 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10835 08:08:15.802904 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10836 08:08:15.811018 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10837 08:08:15.861928 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10838 08:08:15.884904 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10839 08:08:15.897723 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10840 08:08:15.913387 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10841 08:08:15.966097 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10842 08:08:15.992506 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10843 08:08:16.011887 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10844 08:08:16.034651 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10845 08:08:16.088759 Starting [0;1;39mNetwork Service[0m...
10846 08:08:16.112153 Starting [0;1;39mNetwork Time Synchronization[0m...
10847 08:08:16.140135 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10848 08:08:16.162456 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10849 08:08:16.194206 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10850 08:08:16.234224 <6>[ 17.959180] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10851 08:08:16.241095 <6>[ 17.966795] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10852 08:08:16.250550 <6>[ 17.975678] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10853 08:08:16.257478 <6>[ 17.978112] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10854 08:08:16.264226 <4>[ 17.980353] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10855 08:08:16.273977 <4>[ 17.995107] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10856 08:08:16.281273 Starting [0;1;39mLoad/<6>[ 18.008541] remoteproc remoteproc0: scp is available
10857 08:08:16.287498 Save Screen …o<6>[ 18.015128] remoteproc remoteproc0: powering up scp
10858 08:08:16.294142 f leds:white:kbd<6>[ 18.018860] usbcore: registered new interface driver r8152
10859 08:08:16.304447 <6>[ 18.021463] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10860 08:08:16.310532 _backlight[0m..<6>[ 18.037028] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10861 08:08:16.311051 .
10862 08:08:16.346706 <6>[ 18.075240] mc: Linux media interface: v0.10
10863 08:08:16.368321 <3>[ 18.093254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 08:08:16.374697 <6>[ 18.095856] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10865 08:08:16.384974 <3>[ 18.103158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 08:08:16.391334 <3>[ 18.117525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 08:08:16.401706 <6>[ 18.120484] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10868 08:08:16.411355 Startin<3>[ 18.135817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 08:08:16.421870 g [0;1;39mNetwo<6>[ 18.137251] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10870 08:08:16.428263 <3>[ 18.144762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 08:08:16.434856 rk Name Resoluti<6>[ 18.153538] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10872 08:08:16.444515 <3>[ 18.161499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 08:08:16.445069 on[0m...
10874 08:08:16.454807 <4>[ 18.161602] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10875 08:08:16.457966 <4>[ 18.161602] Fallback method does not support PEC.
10876 08:08:16.467767 <6>[ 18.166134] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10877 08:08:16.478218 <6>[ 18.166381] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10878 08:08:16.485435 <6>[ 18.169789] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10879 08:08:16.495051 <6>[ 18.169894] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10880 08:08:16.498760 <6>[ 18.169907] remoteproc remoteproc0: remote processor scp is now up
10881 08:08:16.508794 <3>[ 18.177727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10882 08:08:16.515581 <3>[ 18.177736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10883 08:08:16.525243 <3>[ 18.177890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 08:08:16.535553 <4>[ 18.209784] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10885 08:08:16.541801 <3>[ 18.211705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 08:08:16.551989 <3>[ 18.218717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 08:08:16.555045 <6>[ 18.219843] pci_bus 0000:00: root bus resource [bus 00-ff]
10888 08:08:16.564786 <6>[ 18.219855] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10889 08:08:16.574936 <6>[ 18.219859] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10890 08:08:16.578376 <6>[ 18.219911] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10891 08:08:16.588218 <6>[ 18.219928] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10892 08:08:16.591343 <6>[ 18.220012] pci 0000:00:00.0: supports D1 D2
10893 08:08:16.597729 <6>[ 18.220015] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10894 08:08:16.607846 <3>[ 18.227260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 08:08:16.614813 <4>[ 18.233940] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10896 08:08:16.624218 <6>[ 18.241563] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10897 08:08:16.627453 <6>[ 18.241679] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10898 08:08:16.637950 <6>[ 18.241705] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10899 08:08:16.644862 <6>[ 18.241723] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10900 08:08:16.652158 <6>[ 18.241738] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10901 08:08:16.662474 <3>[ 18.241838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 08:08:16.665630 <6>[ 18.241851] pci 0000:01:00.0: supports D1 D2
10903 08:08:16.675598 <3>[ 18.241907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 08:08:16.682305 <3>[ 18.241911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 08:08:16.692218 <3>[ 18.241914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 08:08:16.698710 <3>[ 18.241917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 08:08:16.705260 <3>[ 18.241920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10908 08:08:16.715275 <3>[ 18.241942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 08:08:16.722105 <6>[ 18.243278] videodev: Linux video capture interface: v2.00
10910 08:08:16.728378 <6>[ 18.246008] usbcore: registered new interface driver cdc_ether
10911 08:08:16.732299 <6>[ 18.280779] Bluetooth: Core ver 2.22
10912 08:08:16.738679 <6>[ 18.284295] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10913 08:08:16.742106 <6>[ 18.289893] NET: Registered PF_BLUETOOTH protocol family
10914 08:08:16.748988 <6>[ 18.309334] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10915 08:08:16.755198 <6>[ 18.313824] Bluetooth: HCI device and connection manager initialized
10916 08:08:16.766431 <6>[ 18.320952] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10917 08:08:16.769593 <6>[ 18.321126] usbcore: registered new interface driver r8153_ecm
10918 08:08:16.776315 <6>[ 18.325215] Bluetooth: HCI socket layer initialized
10919 08:08:16.783978 <6>[ 18.332782] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10920 08:08:16.790174 <6>[ 18.340101] Bluetooth: L2CAP socket layer initialized
10921 08:08:16.797256 <6>[ 18.348590] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10922 08:08:16.803491 <6>[ 18.356946] Bluetooth: SCO socket layer initialized
10923 08:08:16.810505 <6>[ 18.362888] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10924 08:08:16.817346 <6>[ 18.375179] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10925 08:08:16.826784 <6>[ 18.378120] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10926 08:08:16.830054 <6>[ 18.378143] pci 0000:00:00.0: PCI bridge to [bus 01]
10927 08:08:16.839999 <6>[ 18.378150] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10928 08:08:16.843902 <6>[ 18.383382] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10929 08:08:16.853631 <3>[ 18.385840] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 08:08:16.860398 <3>[ 18.386696] power_supply sbs-5-000b: driver failed to report `health' property: -6
10931 08:08:16.867532 <6>[ 18.442881] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10932 08:08:16.873151 <6>[ 18.446846] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10933 08:08:16.880847 <6>[ 18.447059] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10934 08:08:16.886635 <6>[ 18.449537] usbcore: registered new interface driver btusb
10935 08:08:16.890273 <6>[ 18.449624] r8152 2-1.3:1.0 eth0: v1.12.13
10936 08:08:16.900385 <4>[ 18.450385] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10937 08:08:16.907369 <3>[ 18.450398] Bluetooth: hci0: Failed to load firmware file (-2)
10938 08:08:16.913633 <3>[ 18.450401] Bluetooth: hci0: Failed to set up firmware (-2)
10939 08:08:16.923716 <4>[ 18.450406] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10940 08:08:16.936813 <6>[ 18.458395] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10941 08:08:16.943676 <6>[ 18.459418] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10942 08:08:16.953414 <6>[ 18.468186] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10943 08:08:16.960211 <5>[ 18.469772] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10944 08:08:16.966924 <6>[ 18.473250] usbcore: registered new interface driver uvcvideo
10945 08:08:16.973094 <6>[ 18.482023] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10946 08:08:16.979958 <5>[ 18.483162] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10947 08:08:16.986313 <3>[ 18.503482] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 08:08:16.996510 <3>[ 18.504290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10949 08:08:17.006656 <3>[ 18.519744] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 08:08:17.020051 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronizatio<4>[ 18.743353] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10951 08:08:17.020683 n[0m.
10952 08:08:17.027204 <6>[ 18.753640] cfg80211: failed to load regulatory.db
10953 08:08:17.034028 <3>[ 18.759542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 08:08:17.043088 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10955 08:08:17.068718 <3>[ 18.793462] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 08:08:17.074707 <6>[ 18.798123] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10957 08:08:17.081594 <6>[ 18.809765] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10958 08:08:17.087972 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10959 08:08:17.105928 <3>[ 18.831061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 08:08:17.112877 <6>[ 18.836414] mt7921e 0000:01:00.0: ASIC revision: 79610010
10961 08:08:17.119337 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10962 08:08:17.137876 <3>[ 18.863267] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 08:08:17.161612 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10964 08:08:17.219192 <4>[ 18.940876] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10965 08:08:17.279721 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10966 08:08:17.292905 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10967 08:08:17.312620 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10968 08:08:17.340217 [[0;32m OK [0m] Reached target [0;1;39mSystem Initializatio<4>[ 19.060123] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 08:08:17.340806 n[0m.
10970 08:08:17.357674 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10971 08:08:17.373019 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10972 08:08:17.393372 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10973 08:08:17.416512 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10974 08:08:17.429039 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10975 08:08:17.460524 [[0;32m OK [0m] Listening on<4>[ 19.180461] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10976 08:08:17.463749 [0;1;39mD-Bus System Message Bus Socket[0m.
10977 08:08:17.478559 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10978 08:08:17.493549 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10979 08:08:17.512846 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10980 08:08:17.547455 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10981 08:08:17.578257 <4>[ 19.300174] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10982 08:08:17.593188 Starting [0;1;39mUser Login Management[0m...
10983 08:08:17.614390 Starting [0;1;39mPermit User Sessions[0m...
10984 08:08:17.636562 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10985 08:08:17.653682 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10986 08:08:17.670820 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10987 08:08:17.697355 <4>[ 19.419224] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10988 08:08:17.704033 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10989 08:08:17.738651 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10990 08:08:17.758641 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10991 08:08:17.773892 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10992 08:08:17.790413 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10993 08:08:17.813664 <4>[ 19.535699] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 08:08:17.820355 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10995 08:08:17.863205 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10996 08:08:17.902068 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10997 08:08:17.935164 <4>[ 19.657280] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10998 08:08:17.967168
10999 08:08:17.967727
11000 08:08:17.970327 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11001 08:08:17.970947
11002 08:08:17.973497 debian-bullseye-arm64 login: root (automatic login)
11003 08:08:17.974029
11004 08:08:17.974405
11005 08:08:17.999703 Linux debian-bullseye-arm64 6.1.54-cip6 #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023 aarch64
11006 08:08:18.000409
11007 08:08:18.006447 The programs included with the Debian GNU/Linux system are free software;
11008 08:08:18.013117 the exact distribution terms for each program are described in the
11009 08:08:18.015880 individual files in /usr/share/doc/*/copyright.
11010 08:08:18.016342
11011 08:08:18.022135 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11012 08:08:18.025736 permitted by applicable law.
11013 08:08:18.027240 Matched prompt #10: / #
11015 08:08:18.028345 Setting prompt string to ['/ #']
11016 08:08:18.028935 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11018 08:08:18.030056 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11019 08:08:18.030528 start: 2.2.6 expect-shell-connection (timeout 00:02:31) [common]
11020 08:08:18.030968 Setting prompt string to ['/ #']
11021 08:08:18.031320 Forcing a shell prompt, looking for ['/ #']
11023 08:08:18.082275 / #
11024 08:08:18.082987 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11025 08:08:18.083459 Waiting using forced prompt support (timeout 00:02:30)
11026 08:08:18.083989 <4>[ 19.776208] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11027 08:08:18.088800
11028 08:08:18.089784 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11029 08:08:18.090323 start: 2.2.7 export-device-env (timeout 00:02:31) [common]
11030 08:08:18.090876 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11031 08:08:18.091363 end: 2.2 depthcharge-retry (duration 00:02:29) [common]
11032 08:08:18.091837 end: 2 depthcharge-action (duration 00:02:29) [common]
11033 08:08:18.092308 start: 3 lava-test-retry (timeout 00:05:00) [common]
11034 08:08:18.092765 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11035 08:08:18.093170 Using namespace: common
11037 08:08:18.194328 / # #
11038 08:08:18.195092 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11039 08:08:18.195711 #<4>[ 19.895816] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11040 08:08:18.200766
11041 08:08:18.201773 Using /lava-11585982
11043 08:08:18.303252 / # export SHELL=/bin/sh
11044 08:08:18.304065 export SHELL=/bin/sh<4>[ 20.015761] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11045 08:08:18.304521 <6>[ 20.020822] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11046 08:08:18.306855 <6>[ 20.034990] r8152 2-1.3:1.0 enx002432307852: carrier on
11047 08:08:18.307316
11049 08:08:18.448666 / # . /lava-11585982/environment
11050 08:08:18.449491 <3>[ 20.133631] mt7921e 0000:01:00.0: hardware init failed
11051 08:08:18.455341 . /lava-11585982/environment
11053 08:08:18.557067 / # /lava-11585982/bin/lava-test-runner /lava-11585982/0
11054 08:08:18.557693 Test shell timeout: 10s (minimum of the action and connection timeout)
11055 08:08:18.563761 /lava-11585982/bin/lava-test-runner /lava-11585982/0
11056 08:08:18.584723 + export TESTRUN_ID=0_cros-ec
11057 08:08:18.591094 +<8>[ 20.319238] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11585982_1.5.2.3.1>
11058 08:08:18.591943 Received signal: <STARTRUN> 0_cros-ec 11585982_1.5.2.3.1
11059 08:08:18.592371 Starting test lava.0_cros-ec (11585982_1.5.2.3.1)
11060 08:08:18.592818 Skipping test definition patterns.
11061 08:08:18.594971 cd /lava-11585982/0/tests/0_cros-ec
11062 08:08:18.598322 + cat uuid
11063 08:08:18.598950 + UUID=11585982_1.5.2.3.1
11064 08:08:18.599334 + set +x
11065 08:08:18.604399 + python3 -m cros.runners.lava_runner -v
11066 08:08:18.963682 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11067 08:08:18.970612 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11068 08:08:18.974402
11069 08:08:18.980497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11070 08:08:18.981356 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11072 08:08:18.986961 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11073 08:08:18.994298 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11074 08:08:18.997201
11075 08:08:19.001070 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_ac<8
11076 08:08:19.001708 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_ac<8', 'result': 'unknown'}
11077 08:08:19.007028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_ac<8>[ 20.732818] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11585982_1.5.2.3.1>
11078 08:08:19.007775 Received signal: <ENDRUN> 0_cros-ec 11585982_1.5.2.3.1
11079 08:08:19.008210 Ending use of test pattern.
11080 08:08:19.008558 Ending test lava.0_cros-ec (11585982_1.5.2.3.1), duration 0.42
11082 08:08:19.010312 cel_iio_data_is_valid RESULT=skip>
11083 08:08:19.013054 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11084 08:08:19.019971 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11085 08:08:19.020120
11086 08:08:19.026868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11087 08:08:19.027164 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11089 08:08:19.033265 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11090 08:08:19.039664 Checks the standard ABI for the main Embedded Controller. ... ok
11091 08:08:19.039774
11092 08:08:19.043117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11093 08:08:19.043405 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11095 08:08:19.050201 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11096 08:08:19.056842 Checks the main Embedded controller character device. ... ok
11097 08:08:19.057074
11098 08:08:19.060000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11099 08:08:19.060472 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11101 08:08:19.066862 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11102 08:08:19.073722 Checks basic comunication with the main Embedded controller. ... ok
11103 08:08:19.074110
11104 08:08:19.079914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11105 08:08:19.080545 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11107 08:08:19.082914 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11108 08:08:19.090159 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11109 08:08:19.093432
11110 08:08:19.096491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11111 08:08:19.097273 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11113 08:08:19.103419 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11114 08:08:19.109833 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11115 08:08:19.110398
11116 08:08:19.116868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11117 08:08:19.117710 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11119 08:08:19.123247 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11120 08:08:19.130362 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11121 08:08:19.131009
11122 08:08:19.133732 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11124 08:08:19.136914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11125 08:08:19.139739 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11126 08:08:19.146874 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11127 08:08:19.147489
11128 08:08:19.153292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11129 08:08:19.154135 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11131 08:08:19.160767 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11132 08:08:19.167081 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11133 08:08:19.167702
11134 08:08:19.173383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11135 08:08:19.174216 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11137 08:08:19.179693 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11138 08:08:19.186647 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11139 08:08:19.187265
11140 08:08:19.193572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11141 08:08:19.194407 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11143 08:08:19.196847 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11144 08:08:19.206650 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11145 08:08:19.207249
11146 08:08:19.209693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11147 08:08:19.210430 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11149 08:08:19.216811 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11150 08:08:19.226597 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11151 08:08:19.227370
11152 08:08:19.233214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11153 08:08:19.234032 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11155 08:08:19.239537 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11156 08:08:19.242904 Check the cros battery ABI. ... skipped 'No BAT found'
11157 08:08:19.243370
11158 08:08:19.249463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11159 08:08:19.250199 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11161 08:08:19.256284 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11162 08:08:19.263294 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11163 08:08:19.263873
11164 08:08:19.269601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11165 08:08:19.270454 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11167 08:08:19.275983 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11168 08:08:19.283307 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11169 08:08:19.283772
11170 08:08:19.289671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11171 08:08:19.290522 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11173 08:08:19.296212 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11174 08:08:19.303009 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11175 08:08:19.303577
11176 08:08:19.309493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11177 08:08:19.310053
11178 08:08:19.310698 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11180 08:08:19.316676 ----------------------------------------------------------------------
11181 08:08:19.317240 Ran 18 tests in 0.006s
11182 08:08:19.317606
11183 08:08:19.319418 OK (skipped=15)
11184 08:08:19.319877 + set +x
11185 08:08:19.322466 <LAVA_TEST_RUNNER EXIT>
11186 08:08:19.323242 ok: lava_test_shell seems to have completed
11187 08:08:19.324190 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11188 08:08:19.324706 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11189 08:08:19.325167 end: 3 lava-test-retry (duration 00:00:01) [common]
11190 08:08:19.325648 start: 4 finalize (timeout 00:07:08) [common]
11191 08:08:19.326132 start: 4.1 power-off (timeout 00:00:30) [common]
11192 08:08:19.327003 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11193 08:08:19.449087 >> Command sent successfully.
11194 08:08:19.452903 Returned 0 in 0 seconds
11195 08:08:19.553790 end: 4.1 power-off (duration 00:00:00) [common]
11197 08:08:19.555440 start: 4.2 read-feedback (timeout 00:07:08) [common]
11198 08:08:19.556792 Listened to connection for namespace 'common' for up to 1s
11199 08:08:20.557361 Finalising connection for namespace 'common'
11200 08:08:20.558003 Disconnecting from shell: Finalise
11201 08:08:20.558390 / #
11202 08:08:20.659367 end: 4.2 read-feedback (duration 00:00:01) [common]
11203 08:08:20.660066 end: 4 finalize (duration 00:00:01) [common]
11204 08:08:20.660643 Cleaning after the job
11205 08:08:20.661198 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/ramdisk
11206 08:08:20.691059 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/kernel
11207 08:08:20.708673 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/dtb
11208 08:08:20.708939 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585982/tftp-deploy-ced_i668/modules
11209 08:08:20.719000 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11585982
11210 08:08:20.837707 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11585982
11211 08:08:20.837882 Job finished correctly