Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 65
1 08:05:20.542968 lava-dispatcher, installed at version: 2023.06
2 08:05:20.543171 start: 0 validate
3 08:05:20.543310 Start time: 2023-09-21 08:05:20.543302+00:00 (UTC)
4 08:05:20.543439 Using caching service: 'http://localhost/cache/?uri=%s'
5 08:05:20.543580 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 08:05:20.812600 Using caching service: 'http://localhost/cache/?uri=%s'
7 08:05:20.813411 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 08:05:21.083289 Using caching service: 'http://localhost/cache/?uri=%s'
9 08:05:21.084047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 08:05:43.015165 Using caching service: 'http://localhost/cache/?uri=%s'
11 08:05:43.015849 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.54-cip6%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 08:05:43.549658 validate duration: 23.01
14 08:05:43.549997 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:05:43.550171 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:05:43.550260 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:05:43.550396 Not decompressing ramdisk as can be used compressed.
18 08:05:43.550481 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 08:05:43.550546 saving as /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/ramdisk/rootfs.cpio.gz
20 08:05:43.550608 total size: 26246609 (25 MB)
21 08:05:47.253428 progress 0 % (0 MB)
22 08:05:47.264574 progress 5 % (1 MB)
23 08:05:47.271311 progress 10 % (2 MB)
24 08:05:47.277922 progress 15 % (3 MB)
25 08:05:47.284520 progress 20 % (5 MB)
26 08:05:47.291198 progress 25 % (6 MB)
27 08:05:47.297746 progress 30 % (7 MB)
28 08:05:47.304351 progress 35 % (8 MB)
29 08:05:47.310892 progress 40 % (10 MB)
30 08:05:47.317408 progress 45 % (11 MB)
31 08:05:47.323855 progress 50 % (12 MB)
32 08:05:47.330301 progress 55 % (13 MB)
33 08:05:47.336697 progress 60 % (15 MB)
34 08:05:47.343101 progress 65 % (16 MB)
35 08:05:47.349521 progress 70 % (17 MB)
36 08:05:47.356053 progress 75 % (18 MB)
37 08:05:47.362817 progress 80 % (20 MB)
38 08:05:47.369443 progress 85 % (21 MB)
39 08:05:47.378556 progress 90 % (22 MB)
40 08:05:47.388468 progress 95 % (23 MB)
41 08:05:47.398747 progress 100 % (25 MB)
42 08:05:47.399188 25 MB downloaded in 3.85 s (6.50 MB/s)
43 08:05:47.399468 end: 1.1.1 http-download (duration 00:00:04) [common]
45 08:05:47.399942 end: 1.1 download-retry (duration 00:00:04) [common]
46 08:05:47.400090 start: 1.2 download-retry (timeout 00:09:56) [common]
47 08:05:47.400236 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 08:05:47.400440 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 08:05:47.400560 saving as /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/kernel/Image
50 08:05:47.400644 total size: 49304064 (47 MB)
51 08:05:47.400707 No compression specified
52 08:05:47.401862 progress 0 % (0 MB)
53 08:05:47.414067 progress 5 % (2 MB)
54 08:05:47.426035 progress 10 % (4 MB)
55 08:05:47.438041 progress 15 % (7 MB)
56 08:05:47.449956 progress 20 % (9 MB)
57 08:05:47.462244 progress 25 % (11 MB)
58 08:05:47.474513 progress 30 % (14 MB)
59 08:05:47.486751 progress 35 % (16 MB)
60 08:05:47.499126 progress 40 % (18 MB)
61 08:05:47.511630 progress 45 % (21 MB)
62 08:05:47.523609 progress 50 % (23 MB)
63 08:05:47.535529 progress 55 % (25 MB)
64 08:05:47.547437 progress 60 % (28 MB)
65 08:05:47.559716 progress 65 % (30 MB)
66 08:05:47.571679 progress 70 % (32 MB)
67 08:05:47.583851 progress 75 % (35 MB)
68 08:05:47.596198 progress 80 % (37 MB)
69 08:05:47.608579 progress 85 % (39 MB)
70 08:05:47.621152 progress 90 % (42 MB)
71 08:05:47.633091 progress 95 % (44 MB)
72 08:05:47.644895 progress 100 % (47 MB)
73 08:05:47.645121 47 MB downloaded in 0.24 s (192.33 MB/s)
74 08:05:47.645269 end: 1.2.1 http-download (duration 00:00:00) [common]
76 08:05:47.645492 end: 1.2 download-retry (duration 00:00:00) [common]
77 08:05:47.645579 start: 1.3 download-retry (timeout 00:09:56) [common]
78 08:05:47.645665 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 08:05:47.645799 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 08:05:47.645866 saving as /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/dtb/mt8192-asurada-spherion-r0.dtb
81 08:05:47.645924 total size: 47278 (0 MB)
82 08:05:47.645983 No compression specified
83 08:05:47.647045 progress 69 % (0 MB)
84 08:05:47.647307 progress 100 % (0 MB)
85 08:05:47.647455 0 MB downloaded in 0.00 s (29.49 MB/s)
86 08:05:47.647577 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:05:47.647789 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:05:47.647872 start: 1.4 download-retry (timeout 00:09:56) [common]
90 08:05:47.647951 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 08:05:47.648054 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.54-cip6/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 08:05:47.648120 saving as /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/modules/modules.tar
93 08:05:47.648180 total size: 8625188 (8 MB)
94 08:05:47.648239 Using unxz to decompress xz
95 08:05:47.651668 progress 0 % (0 MB)
96 08:05:47.672583 progress 5 % (0 MB)
97 08:05:47.694316 progress 10 % (0 MB)
98 08:05:47.719926 progress 15 % (1 MB)
99 08:05:47.744745 progress 20 % (1 MB)
100 08:05:47.769520 progress 25 % (2 MB)
101 08:05:47.794723 progress 30 % (2 MB)
102 08:05:47.821256 progress 35 % (2 MB)
103 08:05:47.845180 progress 40 % (3 MB)
104 08:05:47.868315 progress 45 % (3 MB)
105 08:05:47.893597 progress 50 % (4 MB)
106 08:05:47.918291 progress 55 % (4 MB)
107 08:05:47.942098 progress 60 % (4 MB)
108 08:05:47.965790 progress 65 % (5 MB)
109 08:05:47.989397 progress 70 % (5 MB)
110 08:05:48.012878 progress 75 % (6 MB)
111 08:05:48.038328 progress 80 % (6 MB)
112 08:05:48.066891 progress 85 % (7 MB)
113 08:05:48.092845 progress 90 % (7 MB)
114 08:05:48.118279 progress 95 % (7 MB)
115 08:05:48.140738 progress 100 % (8 MB)
116 08:05:48.145634 8 MB downloaded in 0.50 s (16.54 MB/s)
117 08:05:48.145867 end: 1.4.1 http-download (duration 00:00:00) [common]
119 08:05:48.146112 end: 1.4 download-retry (duration 00:00:00) [common]
120 08:05:48.146202 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 08:05:48.146294 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 08:05:48.146373 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:05:48.146462 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 08:05:48.146687 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v
125 08:05:48.146810 makedir: /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin
126 08:05:48.146911 makedir: /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/tests
127 08:05:48.147004 makedir: /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/results
128 08:05:48.147116 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-add-keys
129 08:05:48.147291 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-add-sources
130 08:05:48.147413 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-background-process-start
131 08:05:48.147536 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-background-process-stop
132 08:05:48.147655 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-common-functions
133 08:05:48.147772 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-echo-ipv4
134 08:05:48.147888 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-install-packages
135 08:05:48.148005 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-installed-packages
136 08:05:48.148120 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-os-build
137 08:05:48.148236 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-probe-channel
138 08:05:48.148352 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-probe-ip
139 08:05:48.148467 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-target-ip
140 08:05:48.148582 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-target-mac
141 08:05:48.148698 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-target-storage
142 08:05:48.148819 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-case
143 08:05:48.148942 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-event
144 08:05:48.149096 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-feedback
145 08:05:48.149212 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-raise
146 08:05:48.149329 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-reference
147 08:05:48.149447 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-runner
148 08:05:48.149563 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-set
149 08:05:48.149680 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-test-shell
150 08:05:48.149801 Updating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-install-packages (oe)
151 08:05:48.149951 Updating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/bin/lava-installed-packages (oe)
152 08:05:48.150066 Creating /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/environment
153 08:05:48.150162 LAVA metadata
154 08:05:48.150233 - LAVA_JOB_ID=11585993
155 08:05:48.150296 - LAVA_DISPATCHER_IP=192.168.201.1
156 08:05:48.150395 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 08:05:48.150464 skipped lava-vland-overlay
158 08:05:48.150540 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 08:05:48.150617 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 08:05:48.150682 skipped lava-multinode-overlay
161 08:05:48.150752 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 08:05:48.150832 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 08:05:48.150905 Loading test definitions
164 08:05:48.150993 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 08:05:48.151066 Using /lava-11585993 at stage 0
166 08:05:48.151351 uuid=11585993_1.5.2.3.1 testdef=None
167 08:05:48.151438 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 08:05:48.151520 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 08:05:48.152018 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 08:05:48.152231 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 08:05:48.152811 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 08:05:48.153089 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 08:05:48.154044 runner path: /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11585993_1.5.2.3.1
176 08:05:48.154195 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 08:05:48.154395 Creating lava-test-runner.conf files
179 08:05:48.154456 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11585993/lava-overlay-gyd4of6v/lava-11585993/0 for stage 0
180 08:05:48.154540 - 0_v4l2-compliance-mtk-vcodec-enc
181 08:05:48.154634 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 08:05:48.154719 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 08:05:48.161335 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 08:05:48.161436 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 08:05:48.161519 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 08:05:48.161602 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 08:05:48.161684 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 08:05:48.820471 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 08:05:48.820831 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 08:05:48.820972 extracting modules file /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11585993/extract-overlay-ramdisk-8oimgptt/ramdisk
191 08:05:49.028303 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 08:05:49.028473 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 08:05:49.028572 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585993/compress-overlay-zi_qhec2/overlay-1.5.2.4.tar.gz to ramdisk
194 08:05:49.028644 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11585993/compress-overlay-zi_qhec2/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11585993/extract-overlay-ramdisk-8oimgptt/ramdisk
195 08:05:49.034846 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 08:05:49.034960 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 08:05:49.035051 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 08:05:49.035140 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 08:05:49.035218 Building ramdisk /var/lib/lava/dispatcher/tmp/11585993/extract-overlay-ramdisk-8oimgptt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11585993/extract-overlay-ramdisk-8oimgptt/ramdisk
200 08:05:49.627435 >> 228379 blocks
201 08:05:53.454897 rename /var/lib/lava/dispatcher/tmp/11585993/extract-overlay-ramdisk-8oimgptt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/ramdisk/ramdisk.cpio.gz
202 08:05:53.455315 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 08:05:53.455443 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 08:05:53.455543 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 08:05:53.455655 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/kernel/Image'
206 08:06:05.179427 Returned 0 in 11 seconds
207 08:06:05.280517 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/kernel/image.itb
208 08:06:05.918366 output: FIT description: Kernel Image image with one or more FDT blobs
209 08:06:05.918804 output: Created: Thu Sep 21 09:06:05 2023
210 08:06:05.918915 output: Image 0 (kernel-1)
211 08:06:05.919005 output: Description:
212 08:06:05.919070 output: Created: Thu Sep 21 09:06:05 2023
213 08:06:05.919190 output: Type: Kernel Image
214 08:06:05.919262 output: Compression: lzma compressed
215 08:06:05.919326 output: Data Size: 11045265 Bytes = 10786.39 KiB = 10.53 MiB
216 08:06:05.919407 output: Architecture: AArch64
217 08:06:05.919485 output: OS: Linux
218 08:06:05.919543 output: Load Address: 0x00000000
219 08:06:05.919615 output: Entry Point: 0x00000000
220 08:06:05.919671 output: Hash algo: crc32
221 08:06:05.919736 output: Hash value: 886bc8a0
222 08:06:05.919836 output: Image 1 (fdt-1)
223 08:06:05.919890 output: Description: mt8192-asurada-spherion-r0
224 08:06:05.919945 output: Created: Thu Sep 21 09:06:05 2023
225 08:06:05.919998 output: Type: Flat Device Tree
226 08:06:05.920051 output: Compression: uncompressed
227 08:06:05.920105 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 08:06:05.920174 output: Architecture: AArch64
229 08:06:05.920228 output: Hash algo: crc32
230 08:06:05.920288 output: Hash value: cc4352de
231 08:06:05.920375 output: Image 2 (ramdisk-1)
232 08:06:05.920473 output: Description: unavailable
233 08:06:05.920582 output: Created: Thu Sep 21 09:06:05 2023
234 08:06:05.920699 output: Type: RAMDisk Image
235 08:06:05.920755 output: Compression: Unknown Compression
236 08:06:05.920818 output: Data Size: 39358556 Bytes = 38436.09 KiB = 37.54 MiB
237 08:06:05.920886 output: Architecture: AArch64
238 08:06:05.920949 output: OS: Linux
239 08:06:05.921035 output: Load Address: unavailable
240 08:06:05.921091 output: Entry Point: unavailable
241 08:06:05.921144 output: Hash algo: crc32
242 08:06:05.921203 output: Hash value: 27b2455b
243 08:06:05.921268 output: Default Configuration: 'conf-1'
244 08:06:05.921323 output: Configuration 0 (conf-1)
245 08:06:05.921377 output: Description: mt8192-asurada-spherion-r0
246 08:06:05.921449 output: Kernel: kernel-1
247 08:06:05.921514 output: Init Ramdisk: ramdisk-1
248 08:06:05.921618 output: FDT: fdt-1
249 08:06:05.921672 output: Loadables: kernel-1
250 08:06:05.921725 output:
251 08:06:05.921944 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 08:06:05.922066 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 08:06:05.922181 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 08:06:05.922279 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 08:06:05.922358 No LXC device requested
256 08:06:05.922437 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 08:06:05.922524 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 08:06:05.922601 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 08:06:05.922671 Checking files for TFTP limit of 4294967296 bytes.
260 08:06:05.923330 end: 1 tftp-deploy (duration 00:00:22) [common]
261 08:06:05.923448 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 08:06:05.923563 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 08:06:05.923690 substitutions:
264 08:06:05.923778 - {DTB}: 11585993/tftp-deploy-gliuz5fj/dtb/mt8192-asurada-spherion-r0.dtb
265 08:06:05.923848 - {INITRD}: 11585993/tftp-deploy-gliuz5fj/ramdisk/ramdisk.cpio.gz
266 08:06:05.923962 - {KERNEL}: 11585993/tftp-deploy-gliuz5fj/kernel/Image
267 08:06:05.924092 - {LAVA_MAC}: None
268 08:06:05.924185 - {PRESEED_CONFIG}: None
269 08:06:05.924243 - {PRESEED_LOCAL}: None
270 08:06:05.924299 - {RAMDISK}: 11585993/tftp-deploy-gliuz5fj/ramdisk/ramdisk.cpio.gz
271 08:06:05.924356 - {ROOT_PART}: None
272 08:06:05.924412 - {ROOT}: None
273 08:06:05.924506 - {SERVER_IP}: 192.168.201.1
274 08:06:05.924582 - {TEE}: None
275 08:06:05.924638 Parsed boot commands:
276 08:06:05.924706 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 08:06:05.924884 Parsed boot commands: tftpboot 192.168.201.1 11585993/tftp-deploy-gliuz5fj/kernel/image.itb 11585993/tftp-deploy-gliuz5fj/kernel/cmdline
278 08:06:05.925026 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 08:06:05.925112 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 08:06:05.925203 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 08:06:05.925291 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 08:06:05.925359 Not connected, no need to disconnect.
283 08:06:05.925449 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 08:06:05.925572 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 08:06:05.925711 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 08:06:05.929408 Setting prompt string to ['lava-test: # ']
287 08:06:05.929783 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 08:06:05.930028 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 08:06:05.930245 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 08:06:05.930391 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 08:06:05.930748 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 08:06:11.083543 >> Command sent successfully.
293 08:06:11.094766 Returned 0 in 5 seconds
294 08:06:11.195928 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 08:06:11.197481 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 08:06:11.198023 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 08:06:11.198504 Setting prompt string to 'Starting depthcharge on Spherion...'
299 08:06:11.198887 Changing prompt to 'Starting depthcharge on Spherion...'
300 08:06:11.199260 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 08:06:11.200539 [Enter `^Ec?' for help]
302 08:06:11.361632
303 08:06:11.362441
304 08:06:11.362851 F0: 102B 0000
305 08:06:11.363211
306 08:06:11.363552 F3: 1001 0000 [0200]
307 08:06:11.364652
308 08:06:11.365157 F3: 1001 0000
309 08:06:11.365540
310 08:06:11.365886 F7: 102D 0000
311 08:06:11.366215
312 08:06:11.368068 F1: 0000 0000
313 08:06:11.368537
314 08:06:11.368911 V0: 0000 0000 [0001]
315 08:06:11.369312
316 08:06:11.371479 00: 0007 8000
317 08:06:11.371955
318 08:06:11.372325 01: 0000 0000
319 08:06:11.372676
320 08:06:11.374967 BP: 0C00 0209 [0000]
321 08:06:11.375533
322 08:06:11.375933 G0: 1182 0000
323 08:06:11.376288
324 08:06:11.378533 EC: 0000 0021 [4000]
325 08:06:11.379100
326 08:06:11.379475 S7: 0000 0000 [0000]
327 08:06:11.379826
328 08:06:11.381368 CC: 0000 0000 [0001]
329 08:06:11.381839
330 08:06:11.382210 T0: 0000 0040 [010F]
331 08:06:11.382560
332 08:06:11.385007 Jump to BL
333 08:06:11.385478
334 08:06:11.408779
335 08:06:11.409385
336 08:06:11.409764
337 08:06:11.416287 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 08:06:11.419790 ARM64: Exception handlers installed.
339 08:06:11.423394 ARM64: Testing exception
340 08:06:11.426628 ARM64: Done test exception
341 08:06:11.433309 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 08:06:11.444110 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 08:06:11.451202 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 08:06:11.460854 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 08:06:11.467438 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 08:06:11.474221 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 08:06:11.485206 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 08:06:11.492336 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 08:06:11.511312 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 08:06:11.514879 WDT: Last reset was cold boot
351 08:06:11.518237 SPI1(PAD0) initialized at 2873684 Hz
352 08:06:11.521417 SPI5(PAD0) initialized at 992727 Hz
353 08:06:11.524841 VBOOT: Loading verstage.
354 08:06:11.531940 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 08:06:11.534809 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 08:06:11.538134 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 08:06:11.541366 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 08:06:11.548661 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 08:06:11.555658 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 08:06:11.566332 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 08:06:11.566903
362 08:06:11.567277
363 08:06:11.576727 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 08:06:11.579838 ARM64: Exception handlers installed.
365 08:06:11.583300 ARM64: Testing exception
366 08:06:11.583870 ARM64: Done test exception
367 08:06:11.589875 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 08:06:11.593216 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 08:06:11.607967 Probing TPM: . done!
370 08:06:11.608534 TPM ready after 0 ms
371 08:06:11.614239 Connected to device vid:did:rid of 1ae0:0028:00
372 08:06:11.621236 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 08:06:11.624635 Initialized TPM device CR50 revision 0
374 08:06:11.691374 tlcl_send_startup: Startup return code is 0
375 08:06:11.691926 TPM: setup succeeded
376 08:06:11.702755 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 08:06:11.711944 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 08:06:11.721835 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 08:06:11.731052 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 08:06:11.734244 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 08:06:11.740236 in-header: 03 07 00 00 08 00 00 00
382 08:06:11.743728 in-data: aa e4 47 04 13 02 00 00
383 08:06:11.747064 Chrome EC: UHEPI supported
384 08:06:11.754701 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 08:06:11.758403 in-header: 03 ad 00 00 08 00 00 00
386 08:06:11.761725 in-data: 00 20 20 08 00 00 00 00
387 08:06:11.762337 Phase 1
388 08:06:11.765324 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 08:06:11.773002 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 08:06:11.780233 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 08:06:11.780813 Recovery requested (1009000e)
392 08:06:11.790285 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 08:06:11.795928 tlcl_extend: response is 0
394 08:06:11.805488 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 08:06:11.810441 tlcl_extend: response is 0
396 08:06:11.817517 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 08:06:11.837756 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 08:06:11.845006 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 08:06:11.845492
400 08:06:11.845861
401 08:06:11.855420 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 08:06:11.858721 ARM64: Exception handlers installed.
403 08:06:11.859190 ARM64: Testing exception
404 08:06:11.862361 ARM64: Done test exception
405 08:06:11.883920 pmic_efuse_setting: Set efuses in 11 msecs
406 08:06:11.886995 pmwrap_interface_init: Select PMIF_VLD_RDY
407 08:06:11.893825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 08:06:11.897607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 08:06:11.901149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 08:06:11.907909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 08:06:11.911510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 08:06:11.915041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 08:06:11.922429 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 08:06:11.926310 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 08:06:11.929587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 08:06:11.937359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 08:06:11.941344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 08:06:11.944351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 08:06:11.947379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 08:06:11.954756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 08:06:11.961436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 08:06:11.968167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 08:06:11.972219 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 08:06:11.980002 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 08:06:11.983535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 08:06:11.990162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 08:06:11.993374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 08:06:12.000889 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 08:06:12.007378 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 08:06:12.011112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 08:06:12.017901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 08:06:12.024190 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 08:06:12.027401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 08:06:12.030919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 08:06:12.037838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 08:06:12.040841 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 08:06:12.047970 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 08:06:12.051068 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 08:06:12.057821 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 08:06:12.060811 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 08:06:12.067888 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 08:06:12.071091 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 08:06:12.077668 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 08:06:12.081043 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 08:06:12.088219 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 08:06:12.092055 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 08:06:12.095600 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 08:06:12.099003 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 08:06:12.105491 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 08:06:12.109263 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 08:06:12.112661 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 08:06:12.115946 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 08:06:12.122484 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 08:06:12.125849 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 08:06:12.129368 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 08:06:12.132473 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 08:06:12.139280 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 08:06:12.145738 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 08:06:12.155988 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 08:06:12.159435 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 08:06:12.166612 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 08:06:12.177454 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 08:06:12.181146 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 08:06:12.185077 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 08:06:12.188125 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 08:06:12.196993 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1c
467 08:06:12.199913 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 08:06:12.208711 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 08:06:12.211346 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 08:06:12.221090 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 08:06:12.230410 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 08:06:12.239183 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 08:06:12.249243 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 08:06:12.258451 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 08:06:12.261839 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 08:06:12.268482 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 08:06:12.271744 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 08:06:12.275079 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 08:06:12.279046 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 08:06:12.283131 ADC[4]: Raw value=902876 ID=7
481 08:06:12.286466 ADC[3]: Raw value=213179 ID=1
482 08:06:12.286940 RAM Code: 0x71
483 08:06:12.289929 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 08:06:12.297657 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 08:06:12.305113 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 08:06:12.311751 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 08:06:12.314982 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 08:06:12.318499 in-header: 03 07 00 00 08 00 00 00
489 08:06:12.321824 in-data: aa e4 47 04 13 02 00 00
490 08:06:12.324965 Chrome EC: UHEPI supported
491 08:06:12.331661 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 08:06:12.334968 in-header: 03 ed 00 00 08 00 00 00
493 08:06:12.338126 in-data: 80 20 60 08 00 00 00 00
494 08:06:12.341751 MRC: failed to locate region type 0.
495 08:06:12.348436 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 08:06:12.349052 DRAM-K: Running full calibration
497 08:06:12.355258 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 08:06:12.358592 header.status = 0x0
499 08:06:12.361830 header.version = 0x6 (expected: 0x6)
500 08:06:12.365190 header.size = 0xd00 (expected: 0xd00)
501 08:06:12.365761 header.flags = 0x0
502 08:06:12.371771 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 08:06:12.390353 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 08:06:12.396731 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 08:06:12.399989 dram_init: ddr_geometry: 2
506 08:06:12.403584 [EMI] MDL number = 2
507 08:06:12.404287 [EMI] Get MDL freq = 0
508 08:06:12.407170 dram_init: ddr_type: 0
509 08:06:12.407655 is_discrete_lpddr4: 1
510 08:06:12.410146 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 08:06:12.410609
512 08:06:12.411008
513 08:06:12.414110 [Bian_co] ETT version 0.0.0.1
514 08:06:12.420134 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 08:06:12.420709
516 08:06:12.424182 dramc_set_vcore_voltage set vcore to 650000
517 08:06:12.424753 Read voltage for 800, 4
518 08:06:12.427252 Vio18 = 0
519 08:06:12.427822 Vcore = 650000
520 08:06:12.428198 Vdram = 0
521 08:06:12.430321 Vddq = 0
522 08:06:12.430892 Vmddr = 0
523 08:06:12.433786 dram_init: config_dvfs: 1
524 08:06:12.437192 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 08:06:12.444113 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 08:06:12.447090 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 08:06:12.450793 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 08:06:12.454274 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 08:06:12.457419 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 08:06:12.460871 MEM_TYPE=3, freq_sel=18
531 08:06:12.464256 sv_algorithm_assistance_LP4_1600
532 08:06:12.467338 ============ PULL DRAM RESETB DOWN ============
533 08:06:12.470792 ========== PULL DRAM RESETB DOWN end =========
534 08:06:12.477642 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 08:06:12.480661 ===================================
536 08:06:12.481277 LPDDR4 DRAM CONFIGURATION
537 08:06:12.484282 ===================================
538 08:06:12.487404 EX_ROW_EN[0] = 0x0
539 08:06:12.490591 EX_ROW_EN[1] = 0x0
540 08:06:12.491061 LP4Y_EN = 0x0
541 08:06:12.494272 WORK_FSP = 0x0
542 08:06:12.494959 WL = 0x2
543 08:06:12.497270 RL = 0x2
544 08:06:12.497734 BL = 0x2
545 08:06:12.500743 RPST = 0x0
546 08:06:12.501239 RD_PRE = 0x0
547 08:06:12.504080 WR_PRE = 0x1
548 08:06:12.504694 WR_PST = 0x0
549 08:06:12.507376 DBI_WR = 0x0
550 08:06:12.507843 DBI_RD = 0x0
551 08:06:12.510553 OTF = 0x1
552 08:06:12.513947 ===================================
553 08:06:12.517376 ===================================
554 08:06:12.517845 ANA top config
555 08:06:12.521100 ===================================
556 08:06:12.524110 DLL_ASYNC_EN = 0
557 08:06:12.527547 ALL_SLAVE_EN = 1
558 08:06:12.528117 NEW_RANK_MODE = 1
559 08:06:12.531002 DLL_IDLE_MODE = 1
560 08:06:12.534260 LP45_APHY_COMB_EN = 1
561 08:06:12.537806 TX_ODT_DIS = 1
562 08:06:12.540857 NEW_8X_MODE = 1
563 08:06:12.544113 ===================================
564 08:06:12.547647 ===================================
565 08:06:12.548215 data_rate = 1600
566 08:06:12.550985 CKR = 1
567 08:06:12.554582 DQ_P2S_RATIO = 8
568 08:06:12.557731 ===================================
569 08:06:12.561591 CA_P2S_RATIO = 8
570 08:06:12.564599 DQ_CA_OPEN = 0
571 08:06:12.565198 DQ_SEMI_OPEN = 0
572 08:06:12.567679 CA_SEMI_OPEN = 0
573 08:06:12.570932 CA_FULL_RATE = 0
574 08:06:12.574856 DQ_CKDIV4_EN = 1
575 08:06:12.577579 CA_CKDIV4_EN = 1
576 08:06:12.580999 CA_PREDIV_EN = 0
577 08:06:12.581583 PH8_DLY = 0
578 08:06:12.584176 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 08:06:12.588125 DQ_AAMCK_DIV = 4
580 08:06:12.591314 CA_AAMCK_DIV = 4
581 08:06:12.594517 CA_ADMCK_DIV = 4
582 08:06:12.597716 DQ_TRACK_CA_EN = 0
583 08:06:12.598285 CA_PICK = 800
584 08:06:12.601371 CA_MCKIO = 800
585 08:06:12.604564 MCKIO_SEMI = 0
586 08:06:12.607622 PLL_FREQ = 3068
587 08:06:12.611068 DQ_UI_PI_RATIO = 32
588 08:06:12.614796 CA_UI_PI_RATIO = 0
589 08:06:12.617791 ===================================
590 08:06:12.621665 ===================================
591 08:06:12.622261 memory_type:LPDDR4
592 08:06:12.625464 GP_NUM : 10
593 08:06:12.626045 SRAM_EN : 1
594 08:06:12.629351 MD32_EN : 0
595 08:06:12.632847 ===================================
596 08:06:12.633374 [ANA_INIT] >>>>>>>>>>>>>>
597 08:06:12.636779 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 08:06:12.639937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 08:06:12.644013 ===================================
600 08:06:12.647693 data_rate = 1600,PCW = 0X7600
601 08:06:12.651400 ===================================
602 08:06:12.655063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 08:06:12.658786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 08:06:12.666272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 08:06:12.669567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 08:06:12.673546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 08:06:12.677016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 08:06:12.677691 [ANA_INIT] flow start
609 08:06:12.680882 [ANA_INIT] PLL >>>>>>>>
610 08:06:12.684096 [ANA_INIT] PLL <<<<<<<<
611 08:06:12.684865 [ANA_INIT] MIDPI >>>>>>>>
612 08:06:12.687801 [ANA_INIT] MIDPI <<<<<<<<
613 08:06:12.691570 [ANA_INIT] DLL >>>>>>>>
614 08:06:12.692352 [ANA_INIT] flow end
615 08:06:12.695526 ============ LP4 DIFF to SE enter ============
616 08:06:12.699502 ============ LP4 DIFF to SE exit ============
617 08:06:12.702864 [ANA_INIT] <<<<<<<<<<<<<
618 08:06:12.706531 [Flow] Enable top DCM control >>>>>
619 08:06:12.710390 [Flow] Enable top DCM control <<<<<
620 08:06:12.710854 Enable DLL master slave shuffle
621 08:06:12.717726 ==============================================================
622 08:06:12.718328 Gating Mode config
623 08:06:12.725426 ==============================================================
624 08:06:12.725991 Config description:
625 08:06:12.736921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 08:06:12.744265 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 08:06:12.747577 SELPH_MODE 0: By rank 1: By Phase
628 08:06:12.751191 ==============================================================
629 08:06:12.755459 GAT_TRACK_EN = 1
630 08:06:12.759061 RX_GATING_MODE = 2
631 08:06:12.762991 RX_GATING_TRACK_MODE = 2
632 08:06:12.766367 SELPH_MODE = 1
633 08:06:12.766947 PICG_EARLY_EN = 1
634 08:06:12.770069 VALID_LAT_VALUE = 1
635 08:06:12.778044 ==============================================================
636 08:06:12.781620 Enter into Gating configuration >>>>
637 08:06:12.782085 Exit from Gating configuration <<<<
638 08:06:12.785218 Enter into DVFS_PRE_config >>>>>
639 08:06:12.797146 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 08:06:12.800683 Exit from DVFS_PRE_config <<<<<
641 08:06:12.804390 Enter into PICG configuration >>>>
642 08:06:12.808274 Exit from PICG configuration <<<<
643 08:06:12.808738 [RX_INPUT] configuration >>>>>
644 08:06:12.811982 [RX_INPUT] configuration <<<<<
645 08:06:12.819309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 08:06:12.823048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 08:06:12.829854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 08:06:12.833631 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 08:06:12.840890 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 08:06:12.848393 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 08:06:12.852311 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 08:06:12.856305 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 08:06:12.860452 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 08:06:12.863796 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 08:06:12.867482 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 08:06:12.874160 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 08:06:12.874636 ===================================
658 08:06:12.877948 LPDDR4 DRAM CONFIGURATION
659 08:06:12.881631 ===================================
660 08:06:12.882102 EX_ROW_EN[0] = 0x0
661 08:06:12.885385 EX_ROW_EN[1] = 0x0
662 08:06:12.885859 LP4Y_EN = 0x0
663 08:06:12.889102 WORK_FSP = 0x0
664 08:06:12.889575 WL = 0x2
665 08:06:12.893701 RL = 0x2
666 08:06:12.894261 BL = 0x2
667 08:06:12.896923 RPST = 0x0
668 08:06:12.897508 RD_PRE = 0x0
669 08:06:12.900879 WR_PRE = 0x1
670 08:06:12.901485 WR_PST = 0x0
671 08:06:12.904444 DBI_WR = 0x0
672 08:06:12.905057 DBI_RD = 0x0
673 08:06:12.905443 OTF = 0x1
674 08:06:12.907758 ===================================
675 08:06:12.914471 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 08:06:12.918380 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 08:06:12.921079 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 08:06:12.924659 ===================================
679 08:06:12.927994 LPDDR4 DRAM CONFIGURATION
680 08:06:12.931092 ===================================
681 08:06:12.934499 EX_ROW_EN[0] = 0x10
682 08:06:12.935080 EX_ROW_EN[1] = 0x0
683 08:06:12.937783 LP4Y_EN = 0x0
684 08:06:12.938343 WORK_FSP = 0x0
685 08:06:12.941082 WL = 0x2
686 08:06:12.941660 RL = 0x2
687 08:06:12.944883 BL = 0x2
688 08:06:12.945489 RPST = 0x0
689 08:06:12.947674 RD_PRE = 0x0
690 08:06:12.948134 WR_PRE = 0x1
691 08:06:12.951358 WR_PST = 0x0
692 08:06:12.951921 DBI_WR = 0x0
693 08:06:12.954469 DBI_RD = 0x0
694 08:06:12.954931 OTF = 0x1
695 08:06:12.957914 ===================================
696 08:06:12.964896 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 08:06:12.969118 nWR fixed to 40
698 08:06:12.971992 [ModeRegInit_LP4] CH0 RK0
699 08:06:12.972456 [ModeRegInit_LP4] CH0 RK1
700 08:06:12.975556 [ModeRegInit_LP4] CH1 RK0
701 08:06:12.978846 [ModeRegInit_LP4] CH1 RK1
702 08:06:12.979410 match AC timing 13
703 08:06:12.985518 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 08:06:12.989047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 08:06:12.992441 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 08:06:12.998647 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 08:06:13.002182 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 08:06:13.002754 [EMI DOE] emi_dcm 0
709 08:06:13.009004 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 08:06:13.009560 ==
711 08:06:13.012308 Dram Type= 6, Freq= 0, CH_0, rank 0
712 08:06:13.015654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 08:06:13.016122 ==
714 08:06:13.022345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 08:06:13.025752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 08:06:13.036866 [CA 0] Center 38 (7~69) winsize 63
717 08:06:13.039448 [CA 1] Center 38 (7~69) winsize 63
718 08:06:13.043173 [CA 2] Center 35 (5~66) winsize 62
719 08:06:13.046308 [CA 3] Center 35 (5~66) winsize 62
720 08:06:13.049585 [CA 4] Center 34 (4~65) winsize 62
721 08:06:13.052884 [CA 5] Center 34 (3~65) winsize 63
722 08:06:13.053405
723 08:06:13.056262 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 08:06:13.056728
725 08:06:13.059750 [CATrainingPosCal] consider 1 rank data
726 08:06:13.063371 u2DelayCellTimex100 = 270/100 ps
727 08:06:13.066381 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 08:06:13.069818 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 08:06:13.076460 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 08:06:13.079749 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 08:06:13.083495 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
732 08:06:13.086617 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
733 08:06:13.087191
734 08:06:13.089670 CA PerBit enable=1, Macro0, CA PI delay=34
735 08:06:13.090138
736 08:06:13.093393 [CBTSetCACLKResult] CA Dly = 34
737 08:06:13.093965 CS Dly: 6 (0~37)
738 08:06:13.094337 ==
739 08:06:13.096611 Dram Type= 6, Freq= 0, CH_0, rank 1
740 08:06:13.103324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 08:06:13.103897 ==
742 08:06:13.106928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 08:06:13.113728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 08:06:13.122766 [CA 0] Center 38 (7~69) winsize 63
745 08:06:13.126063 [CA 1] Center 38 (8~69) winsize 62
746 08:06:13.129525 [CA 2] Center 36 (5~67) winsize 63
747 08:06:13.132919 [CA 3] Center 36 (5~67) winsize 63
748 08:06:13.136383 [CA 4] Center 35 (4~66) winsize 63
749 08:06:13.139398 [CA 5] Center 34 (4~65) winsize 62
750 08:06:13.139966
751 08:06:13.142744 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 08:06:13.143318
753 08:06:13.146126 [CATrainingPosCal] consider 2 rank data
754 08:06:13.149350 u2DelayCellTimex100 = 270/100 ps
755 08:06:13.152900 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 08:06:13.156564 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 08:06:13.159581 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 08:06:13.166104 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 08:06:13.169701 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 08:06:13.172647 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
761 08:06:13.173417
762 08:06:13.176246 CA PerBit enable=1, Macro0, CA PI delay=34
763 08:06:13.176713
764 08:06:13.179699 [CBTSetCACLKResult] CA Dly = 34
765 08:06:13.180321 CS Dly: 6 (0~38)
766 08:06:13.180708
767 08:06:13.182903 ----->DramcWriteLeveling(PI) begin...
768 08:06:13.183480 ==
769 08:06:13.186287 Dram Type= 6, Freq= 0, CH_0, rank 0
770 08:06:13.192914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 08:06:13.193523 ==
772 08:06:13.196660 Write leveling (Byte 0): 30 => 30
773 08:06:13.199631 Write leveling (Byte 1): 30 => 30
774 08:06:13.200107 DramcWriteLeveling(PI) end<-----
775 08:06:13.203437
776 08:06:13.204008 ==
777 08:06:13.206207 Dram Type= 6, Freq= 0, CH_0, rank 0
778 08:06:13.209447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 08:06:13.209920 ==
780 08:06:13.212774 [Gating] SW mode calibration
781 08:06:13.219741 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 08:06:13.223289 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 08:06:13.229808 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 08:06:13.233078 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 08:06:13.236499 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 08:06:13.243099 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 08:06:13.246542 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 08:06:13.250065 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 08:06:13.256323 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 08:06:13.260087 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 08:06:13.263901 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 08:06:13.268016 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 08:06:13.271003 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 08:06:13.277771 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 08:06:13.281086 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 08:06:13.284485 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 08:06:13.292151 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 08:06:13.295086 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 08:06:13.298378 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 08:06:13.301836 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 08:06:13.308704 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
802 08:06:13.311851 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 08:06:13.315435 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 08:06:13.321865 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 08:06:13.325589 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 08:06:13.329065 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 08:06:13.335559 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 08:06:13.338644 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
809 08:06:13.342085 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
810 08:06:13.348720 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
811 08:06:13.351999 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 08:06:13.355499 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 08:06:13.359062 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 08:06:13.365586 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 08:06:13.368862 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 08:06:13.371873 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
817 08:06:13.378689 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
818 08:06:13.381877 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
819 08:06:13.385237 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 08:06:13.392200 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 08:06:13.395457 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 08:06:13.399080 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 08:06:13.405691 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 08:06:13.409231 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
825 08:06:13.412556 0 11 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
826 08:06:13.419284 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
827 08:06:13.422579 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 08:06:13.425742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 08:06:13.428918 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 08:06:13.435989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 08:06:13.438724 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 08:06:13.442821 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 08:06:13.448801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 08:06:13.452449 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 08:06:13.455643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 08:06:13.462340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 08:06:13.465813 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 08:06:13.469103 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 08:06:13.475459 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 08:06:13.479022 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 08:06:13.482394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 08:06:13.489136 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 08:06:13.492555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 08:06:13.495665 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 08:06:13.502431 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 08:06:13.505736 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 08:06:13.509027 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 08:06:13.512451 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 08:06:13.519591 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 08:06:13.522786 Total UI for P1: 0, mck2ui 16
851 08:06:13.525852 best dqsien dly found for B0: ( 0, 14, 6)
852 08:06:13.529310 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 08:06:13.533094 Total UI for P1: 0, mck2ui 16
854 08:06:13.536105 best dqsien dly found for B1: ( 0, 14, 8)
855 08:06:13.539464 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
856 08:06:13.542692 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 08:06:13.543261
858 08:06:13.546180 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 08:06:13.549103 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 08:06:13.552875 [Gating] SW calibration Done
861 08:06:13.553474 ==
862 08:06:13.556677 Dram Type= 6, Freq= 0, CH_0, rank 0
863 08:06:13.559378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 08:06:13.559944 ==
865 08:06:13.562854 RX Vref Scan: 0
866 08:06:13.563422
867 08:06:13.566657 RX Vref 0 -> 0, step: 1
868 08:06:13.567223
869 08:06:13.567595 RX Delay -130 -> 252, step: 16
870 08:06:13.573085 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
871 08:06:13.576503 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 08:06:13.579652 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
873 08:06:13.582657 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 08:06:13.586279 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 08:06:13.592845 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 08:06:13.596144 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 08:06:13.599345 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 08:06:13.603069 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 08:06:13.606519 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 08:06:13.612795 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 08:06:13.616293 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 08:06:13.619773 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 08:06:13.623106 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 08:06:13.626558 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 08:06:13.632841 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 08:06:13.633410 ==
887 08:06:13.636494 Dram Type= 6, Freq= 0, CH_0, rank 0
888 08:06:13.639858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 08:06:13.640423 ==
890 08:06:13.640790 DQS Delay:
891 08:06:13.643339 DQS0 = 0, DQS1 = 0
892 08:06:13.643904 DQM Delay:
893 08:06:13.646468 DQM0 = 92, DQM1 = 80
894 08:06:13.646930 DQ Delay:
895 08:06:13.650177 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
896 08:06:13.653428 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
897 08:06:13.656786 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
898 08:06:13.659985 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
899 08:06:13.660545
900 08:06:13.660912
901 08:06:13.661288 ==
902 08:06:13.662963 Dram Type= 6, Freq= 0, CH_0, rank 0
903 08:06:13.666543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 08:06:13.667137 ==
905 08:06:13.669569
906 08:06:13.670029
907 08:06:13.670391 TX Vref Scan disable
908 08:06:13.673043 == TX Byte 0 ==
909 08:06:13.676164 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
910 08:06:13.680028 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
911 08:06:13.683435 == TX Byte 1 ==
912 08:06:13.686317 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 08:06:13.689525 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 08:06:13.689993 ==
915 08:06:13.693203 Dram Type= 6, Freq= 0, CH_0, rank 0
916 08:06:13.699528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 08:06:13.700021 ==
918 08:06:13.711963 TX Vref=22, minBit 11, minWin=26, winSum=438
919 08:06:13.714767 TX Vref=24, minBit 6, minWin=27, winSum=441
920 08:06:13.717914 TX Vref=26, minBit 6, minWin=27, winSum=446
921 08:06:13.721566 TX Vref=28, minBit 14, minWin=27, winSum=452
922 08:06:13.724887 TX Vref=30, minBit 6, minWin=28, winSum=454
923 08:06:13.731430 TX Vref=32, minBit 10, minWin=27, winSum=456
924 08:06:13.735141 [TxChooseVref] Worse bit 6, Min win 28, Win sum 454, Final Vref 30
925 08:06:13.735624
926 08:06:13.738507 Final TX Range 1 Vref 30
927 08:06:13.739090
928 08:06:13.739578 ==
929 08:06:13.741433 Dram Type= 6, Freq= 0, CH_0, rank 0
930 08:06:13.744828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 08:06:13.745457 ==
932 08:06:13.748020
933 08:06:13.748652
934 08:06:13.749169 TX Vref Scan disable
935 08:06:13.751607 == TX Byte 0 ==
936 08:06:13.754911 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 08:06:13.758153 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 08:06:13.761894 == TX Byte 1 ==
939 08:06:13.765115 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 08:06:13.768544 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 08:06:13.771837
942 08:06:13.772413 [DATLAT]
943 08:06:13.772962 Freq=800, CH0 RK0
944 08:06:13.773470
945 08:06:13.774980 DATLAT Default: 0xa
946 08:06:13.775484 0, 0xFFFF, sum = 0
947 08:06:13.777941 1, 0xFFFF, sum = 0
948 08:06:13.778427 2, 0xFFFF, sum = 0
949 08:06:13.781607 3, 0xFFFF, sum = 0
950 08:06:13.782205 4, 0xFFFF, sum = 0
951 08:06:13.785041 5, 0xFFFF, sum = 0
952 08:06:13.785629 6, 0xFFFF, sum = 0
953 08:06:13.788248 7, 0xFFFF, sum = 0
954 08:06:13.791705 8, 0xFFFF, sum = 0
955 08:06:13.792289 9, 0x0, sum = 1
956 08:06:13.792787 10, 0x0, sum = 2
957 08:06:13.795341 11, 0x0, sum = 3
958 08:06:13.795921 12, 0x0, sum = 4
959 08:06:13.798103 best_step = 10
960 08:06:13.798584
961 08:06:13.799064 ==
962 08:06:13.801558 Dram Type= 6, Freq= 0, CH_0, rank 0
963 08:06:13.805297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 08:06:13.805888 ==
965 08:06:13.808405 RX Vref Scan: 1
966 08:06:13.808886
967 08:06:13.809407 Set Vref Range= 32 -> 127
968 08:06:13.809861
969 08:06:13.811790 RX Vref 32 -> 127, step: 1
970 08:06:13.812258
971 08:06:13.815600 RX Delay -95 -> 252, step: 8
972 08:06:13.816161
973 08:06:13.818502 Set Vref, RX VrefLevel [Byte0]: 32
974 08:06:13.821718 [Byte1]: 32
975 08:06:13.822278
976 08:06:13.824891 Set Vref, RX VrefLevel [Byte0]: 33
977 08:06:13.828420 [Byte1]: 33
978 08:06:13.831741
979 08:06:13.832210 Set Vref, RX VrefLevel [Byte0]: 34
980 08:06:13.835416 [Byte1]: 34
981 08:06:13.839529
982 08:06:13.840090 Set Vref, RX VrefLevel [Byte0]: 35
983 08:06:13.843026 [Byte1]: 35
984 08:06:13.847423
985 08:06:13.847983 Set Vref, RX VrefLevel [Byte0]: 36
986 08:06:13.850358 [Byte1]: 36
987 08:06:13.854609
988 08:06:13.855169 Set Vref, RX VrefLevel [Byte0]: 37
989 08:06:13.857925 [Byte1]: 37
990 08:06:13.862759
991 08:06:13.863318 Set Vref, RX VrefLevel [Byte0]: 38
992 08:06:13.865863 [Byte1]: 38
993 08:06:13.869871
994 08:06:13.870424 Set Vref, RX VrefLevel [Byte0]: 39
995 08:06:13.873278 [Byte1]: 39
996 08:06:13.877404
997 08:06:13.877867 Set Vref, RX VrefLevel [Byte0]: 40
998 08:06:13.880887 [Byte1]: 40
999 08:06:13.885100
1000 08:06:13.885654 Set Vref, RX VrefLevel [Byte0]: 41
1001 08:06:13.888750 [Byte1]: 41
1002 08:06:13.892565
1003 08:06:13.893167 Set Vref, RX VrefLevel [Byte0]: 42
1004 08:06:13.895925 [Byte1]: 42
1005 08:06:13.900426
1006 08:06:13.901037 Set Vref, RX VrefLevel [Byte0]: 43
1007 08:06:13.903439 [Byte1]: 43
1008 08:06:13.907814
1009 08:06:13.908376 Set Vref, RX VrefLevel [Byte0]: 44
1010 08:06:13.911001 [Byte1]: 44
1011 08:06:13.915060
1012 08:06:13.915529 Set Vref, RX VrefLevel [Byte0]: 45
1013 08:06:13.919017 [Byte1]: 45
1014 08:06:13.923115
1015 08:06:13.923696 Set Vref, RX VrefLevel [Byte0]: 46
1016 08:06:13.926413 [Byte1]: 46
1017 08:06:13.931050
1018 08:06:13.931642 Set Vref, RX VrefLevel [Byte0]: 47
1019 08:06:13.934207 [Byte1]: 47
1020 08:06:13.938392
1021 08:06:13.938871 Set Vref, RX VrefLevel [Byte0]: 48
1022 08:06:13.942064 [Byte1]: 48
1023 08:06:13.946235
1024 08:06:13.946830 Set Vref, RX VrefLevel [Byte0]: 49
1025 08:06:13.949701 [Byte1]: 49
1026 08:06:13.954218
1027 08:06:13.954802 Set Vref, RX VrefLevel [Byte0]: 50
1028 08:06:13.957389 [Byte1]: 50
1029 08:06:13.961474
1030 08:06:13.962055 Set Vref, RX VrefLevel [Byte0]: 51
1031 08:06:13.965080 [Byte1]: 51
1032 08:06:13.968683
1033 08:06:13.969290 Set Vref, RX VrefLevel [Byte0]: 52
1034 08:06:13.971724 [Byte1]: 52
1035 08:06:13.976478
1036 08:06:13.977118 Set Vref, RX VrefLevel [Byte0]: 53
1037 08:06:13.980017 [Byte1]: 53
1038 08:06:13.984051
1039 08:06:13.984624 Set Vref, RX VrefLevel [Byte0]: 54
1040 08:06:13.987125 [Byte1]: 54
1041 08:06:13.991452
1042 08:06:13.992031 Set Vref, RX VrefLevel [Byte0]: 55
1043 08:06:13.994968 [Byte1]: 55
1044 08:06:13.999053
1045 08:06:13.999635 Set Vref, RX VrefLevel [Byte0]: 56
1046 08:06:14.002155 [Byte1]: 56
1047 08:06:14.006790
1048 08:06:14.007353 Set Vref, RX VrefLevel [Byte0]: 57
1049 08:06:14.010069 [Byte1]: 57
1050 08:06:14.014055
1051 08:06:14.014517 Set Vref, RX VrefLevel [Byte0]: 58
1052 08:06:14.017463 [Byte1]: 58
1053 08:06:14.021692
1054 08:06:14.022248 Set Vref, RX VrefLevel [Byte0]: 59
1055 08:06:14.024992 [Byte1]: 59
1056 08:06:14.029243
1057 08:06:14.029794 Set Vref, RX VrefLevel [Byte0]: 60
1058 08:06:14.032579 [Byte1]: 60
1059 08:06:14.036924
1060 08:06:14.037507 Set Vref, RX VrefLevel [Byte0]: 61
1061 08:06:14.039997 [Byte1]: 61
1062 08:06:14.045036
1063 08:06:14.045586 Set Vref, RX VrefLevel [Byte0]: 62
1064 08:06:14.048323 [Byte1]: 62
1065 08:06:14.051985
1066 08:06:14.052460 Set Vref, RX VrefLevel [Byte0]: 63
1067 08:06:14.055819 [Byte1]: 63
1068 08:06:14.059859
1069 08:06:14.060414 Set Vref, RX VrefLevel [Byte0]: 64
1070 08:06:14.063223 [Byte1]: 64
1071 08:06:14.067662
1072 08:06:14.068222 Set Vref, RX VrefLevel [Byte0]: 65
1073 08:06:14.071009 [Byte1]: 65
1074 08:06:14.074974
1075 08:06:14.075535 Set Vref, RX VrefLevel [Byte0]: 66
1076 08:06:14.078216 [Byte1]: 66
1077 08:06:14.083001
1078 08:06:14.083562 Set Vref, RX VrefLevel [Byte0]: 67
1079 08:06:14.085792 [Byte1]: 67
1080 08:06:14.090344
1081 08:06:14.090902 Set Vref, RX VrefLevel [Byte0]: 68
1082 08:06:14.093257 [Byte1]: 68
1083 08:06:14.097835
1084 08:06:14.098394 Set Vref, RX VrefLevel [Byte0]: 69
1085 08:06:14.101040 [Byte1]: 69
1086 08:06:14.105507
1087 08:06:14.106069 Set Vref, RX VrefLevel [Byte0]: 70
1088 08:06:14.109078 [Byte1]: 70
1089 08:06:14.113302
1090 08:06:14.113860 Set Vref, RX VrefLevel [Byte0]: 71
1091 08:06:14.116555 [Byte1]: 71
1092 08:06:14.120667
1093 08:06:14.121270 Set Vref, RX VrefLevel [Byte0]: 72
1094 08:06:14.123768 [Byte1]: 72
1095 08:06:14.128285
1096 08:06:14.128844 Set Vref, RX VrefLevel [Byte0]: 73
1097 08:06:14.131582 [Byte1]: 73
1098 08:06:14.135840
1099 08:06:14.136423 Set Vref, RX VrefLevel [Byte0]: 74
1100 08:06:14.138852 [Byte1]: 74
1101 08:06:14.143451
1102 08:06:14.144014 Set Vref, RX VrefLevel [Byte0]: 75
1103 08:06:14.146561 [Byte1]: 75
1104 08:06:14.151275
1105 08:06:14.152007 Set Vref, RX VrefLevel [Byte0]: 76
1106 08:06:14.154032 [Byte1]: 76
1107 08:06:14.158611
1108 08:06:14.159166 Set Vref, RX VrefLevel [Byte0]: 77
1109 08:06:14.161594 [Byte1]: 77
1110 08:06:14.166213
1111 08:06:14.166773 Final RX Vref Byte 0 = 61 to rank0
1112 08:06:14.169573 Final RX Vref Byte 1 = 63 to rank0
1113 08:06:14.173011 Final RX Vref Byte 0 = 61 to rank1
1114 08:06:14.176230 Final RX Vref Byte 1 = 63 to rank1==
1115 08:06:14.179411 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 08:06:14.182840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 08:06:14.186313 ==
1118 08:06:14.186872 DQS Delay:
1119 08:06:14.187235 DQS0 = 0, DQS1 = 0
1120 08:06:14.189471 DQM Delay:
1121 08:06:14.189925 DQM0 = 93, DQM1 = 82
1122 08:06:14.192821 DQ Delay:
1123 08:06:14.196341 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1124 08:06:14.196903 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1125 08:06:14.199626 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1126 08:06:14.202994 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1127 08:06:14.206524
1128 08:06:14.206985
1129 08:06:14.213229 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1130 08:06:14.216410 CH0 RK0: MR19=606, MR18=3C37
1131 08:06:14.222958 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1132 08:06:14.223528
1133 08:06:14.226567 ----->DramcWriteLeveling(PI) begin...
1134 08:06:14.227139 ==
1135 08:06:14.229801 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 08:06:14.233048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 08:06:14.233608 ==
1138 08:06:14.236482 Write leveling (Byte 0): 32 => 32
1139 08:06:14.239811 Write leveling (Byte 1): 31 => 31
1140 08:06:14.243463 DramcWriteLeveling(PI) end<-----
1141 08:06:14.244027
1142 08:06:14.244394 ==
1143 08:06:14.246442 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 08:06:14.249618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 08:06:14.250095 ==
1146 08:06:14.252906 [Gating] SW mode calibration
1147 08:06:14.260051 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 08:06:14.266572 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 08:06:14.269834 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 08:06:14.273592 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 08:06:14.279968 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 08:06:14.283165 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 08:06:14.286951 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 08:06:14.290351 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 08:06:14.334182 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 08:06:14.335269 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 08:06:14.335850 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 08:06:14.336412 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 08:06:14.336924 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 08:06:14.337481 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 08:06:14.338048 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 08:06:14.338546 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 08:06:14.339031 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 08:06:14.339514 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 08:06:14.363329 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 08:06:14.364045 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 08:06:14.364760 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1168 08:06:14.365181 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 08:06:14.365689 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 08:06:14.366164 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 08:06:14.367166 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 08:06:14.370885 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 08:06:14.374891 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 08:06:14.380599 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1175 08:06:14.384461 0 9 8 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
1176 08:06:14.387591 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 08:06:14.394373 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 08:06:14.397795 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 08:06:14.401608 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 08:06:14.404292 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 08:06:14.411037 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 08:06:14.414433 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1183 08:06:14.417856 0 10 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
1184 08:06:14.424295 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 08:06:14.427932 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 08:06:14.430908 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 08:06:14.437939 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 08:06:14.440768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 08:06:14.444712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 08:06:14.450634 0 11 4 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
1191 08:06:14.454285 0 11 8 | B1->B0 | 3a3a 4444 | 0 0 | (1 1) (0 0)
1192 08:06:14.457591 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 08:06:14.464304 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 08:06:14.467386 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 08:06:14.471117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 08:06:14.477582 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 08:06:14.480823 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 08:06:14.484605 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 08:06:14.491179 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 08:06:14.494426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 08:06:14.497499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 08:06:14.501094 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 08:06:14.507855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 08:06:14.511509 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 08:06:14.515209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 08:06:14.519284 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 08:06:14.523038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 08:06:14.530272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 08:06:14.533611 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 08:06:14.536850 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 08:06:14.540998 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 08:06:14.547454 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 08:06:14.550610 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 08:06:14.554053 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 08:06:14.560449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 08:06:14.564031 Total UI for P1: 0, mck2ui 16
1217 08:06:14.567049 best dqsien dly found for B0: ( 0, 14, 4)
1218 08:06:14.570776 Total UI for P1: 0, mck2ui 16
1219 08:06:14.573856 best dqsien dly found for B1: ( 0, 14, 4)
1220 08:06:14.577209 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 08:06:14.580457 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1222 08:06:14.581049
1223 08:06:14.583970 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 08:06:14.587224 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 08:06:14.590531 [Gating] SW calibration Done
1226 08:06:14.591091 ==
1227 08:06:14.593824 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 08:06:14.597193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 08:06:14.597753 ==
1230 08:06:14.600652 RX Vref Scan: 0
1231 08:06:14.601247
1232 08:06:14.601728 RX Vref 0 -> 0, step: 1
1233 08:06:14.602075
1234 08:06:14.603538 RX Delay -130 -> 252, step: 16
1235 08:06:14.607164 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 08:06:14.613540 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 08:06:14.617021 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1238 08:06:14.620261 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1239 08:06:14.623831 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 08:06:14.626876 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1241 08:06:14.633693 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 08:06:14.636825 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1243 08:06:14.640562 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1244 08:06:14.644247 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1245 08:06:14.646975 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1246 08:06:14.653762 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1247 08:06:14.657108 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1248 08:06:14.660576 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1249 08:06:14.664154 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 08:06:14.667127 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1251 08:06:14.670628 ==
1252 08:06:14.671189 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 08:06:14.677115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 08:06:14.677674 ==
1255 08:06:14.678044 DQS Delay:
1256 08:06:14.680507 DQS0 = 0, DQS1 = 0
1257 08:06:14.681008 DQM Delay:
1258 08:06:14.683848 DQM0 = 89, DQM1 = 78
1259 08:06:14.684307 DQ Delay:
1260 08:06:14.687208 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1261 08:06:14.690703 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1262 08:06:14.694328 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1263 08:06:14.696986 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1264 08:06:14.697457
1265 08:06:14.697815
1266 08:06:14.698149 ==
1267 08:06:14.700655 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 08:06:14.704228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 08:06:14.704789 ==
1270 08:06:14.705211
1271 08:06:14.705552
1272 08:06:14.707369 TX Vref Scan disable
1273 08:06:14.710843 == TX Byte 0 ==
1274 08:06:14.714353 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1275 08:06:14.717581 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1276 08:06:14.720746 == TX Byte 1 ==
1277 08:06:14.724137 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1278 08:06:14.727383 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1279 08:06:14.727945 ==
1280 08:06:14.730779 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 08:06:14.733670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 08:06:14.734136 ==
1283 08:06:14.748290 TX Vref=22, minBit 1, minWin=27, winSum=443
1284 08:06:14.751533 TX Vref=24, minBit 8, minWin=27, winSum=448
1285 08:06:14.755276 TX Vref=26, minBit 8, minWin=27, winSum=453
1286 08:06:14.758563 TX Vref=28, minBit 8, minWin=27, winSum=454
1287 08:06:14.762455 TX Vref=30, minBit 8, minWin=28, winSum=456
1288 08:06:14.765332 TX Vref=32, minBit 8, minWin=27, winSum=455
1289 08:06:14.771747 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 30
1290 08:06:14.772308
1291 08:06:14.775503 Final TX Range 1 Vref 30
1292 08:06:14.776062
1293 08:06:14.776420 ==
1294 08:06:14.778368 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 08:06:14.781678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 08:06:14.782136 ==
1297 08:06:14.782511
1298 08:06:14.782841
1299 08:06:14.784998 TX Vref Scan disable
1300 08:06:14.788323 == TX Byte 0 ==
1301 08:06:14.791784 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1302 08:06:14.794939 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1303 08:06:14.798182 == TX Byte 1 ==
1304 08:06:14.801802 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1305 08:06:14.805201 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1306 08:06:14.805663
1307 08:06:14.808893 [DATLAT]
1308 08:06:14.809473 Freq=800, CH0 RK1
1309 08:06:14.809832
1310 08:06:14.811533 DATLAT Default: 0xa
1311 08:06:14.811980 0, 0xFFFF, sum = 0
1312 08:06:14.815175 1, 0xFFFF, sum = 0
1313 08:06:14.815731 2, 0xFFFF, sum = 0
1314 08:06:14.818851 3, 0xFFFF, sum = 0
1315 08:06:14.819403 4, 0xFFFF, sum = 0
1316 08:06:14.821723 5, 0xFFFF, sum = 0
1317 08:06:14.822277 6, 0xFFFF, sum = 0
1318 08:06:14.825400 7, 0xFFFF, sum = 0
1319 08:06:14.828419 8, 0xFFFF, sum = 0
1320 08:06:14.829131 9, 0x0, sum = 1
1321 08:06:14.829502 10, 0x0, sum = 2
1322 08:06:14.831860 11, 0x0, sum = 3
1323 08:06:14.832412 12, 0x0, sum = 4
1324 08:06:14.835301 best_step = 10
1325 08:06:14.835848
1326 08:06:14.836206 ==
1327 08:06:14.838614 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 08:06:14.841517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 08:06:14.841966 ==
1330 08:06:14.845020 RX Vref Scan: 0
1331 08:06:14.845572
1332 08:06:14.845932 RX Vref 0 -> 0, step: 1
1333 08:06:14.846261
1334 08:06:14.848495 RX Delay -95 -> 252, step: 8
1335 08:06:14.855283 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 08:06:14.858235 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1337 08:06:14.861731 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1338 08:06:14.865413 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1339 08:06:14.868558 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1340 08:06:14.875416 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1341 08:06:14.878468 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1342 08:06:14.881638 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1343 08:06:14.884829 iDelay=209, Bit 8, Center 76 (-23 ~ 176) 200
1344 08:06:14.888672 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1345 08:06:14.895107 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1346 08:06:14.898877 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1347 08:06:14.901895 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1348 08:06:14.905236 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1349 08:06:14.908657 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1350 08:06:14.915223 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1351 08:06:14.915771 ==
1352 08:06:14.919027 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 08:06:14.921987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 08:06:14.922537 ==
1355 08:06:14.922895 DQS Delay:
1356 08:06:14.925706 DQS0 = 0, DQS1 = 0
1357 08:06:14.926249 DQM Delay:
1358 08:06:14.929110 DQM0 = 91, DQM1 = 82
1359 08:06:14.929650 DQ Delay:
1360 08:06:14.932211 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1361 08:06:14.935768 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1362 08:06:14.938924 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1363 08:06:14.942092 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1364 08:06:14.942634
1365 08:06:14.942987
1366 08:06:14.948754 [DQSOSCAuto] RK1, (LSB)MR18= 0x4521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1367 08:06:14.951899 CH0 RK1: MR19=606, MR18=4521
1368 08:06:14.958768 CH0_RK1: MR19=0x606, MR18=0x4521, DQSOSC=392, MR23=63, INC=96, DEC=64
1369 08:06:14.962055 [RxdqsGatingPostProcess] freq 800
1370 08:06:14.968884 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 08:06:14.969450 Pre-setting of DQS Precalculation
1372 08:06:14.975484 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 08:06:14.976033 ==
1374 08:06:14.979077 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 08:06:14.982337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 08:06:14.982896 ==
1377 08:06:14.988865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 08:06:14.995220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 08:06:15.003283 [CA 0] Center 36 (6~67) winsize 62
1380 08:06:15.006738 [CA 1] Center 36 (6~67) winsize 62
1381 08:06:15.010014 [CA 2] Center 34 (4~65) winsize 62
1382 08:06:15.013519 [CA 3] Center 34 (3~65) winsize 63
1383 08:06:15.016731 [CA 4] Center 34 (4~65) winsize 62
1384 08:06:15.020364 [CA 5] Center 33 (3~64) winsize 62
1385 08:06:15.020906
1386 08:06:15.023408 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1387 08:06:15.023955
1388 08:06:15.026857 [CATrainingPosCal] consider 1 rank data
1389 08:06:15.029870 u2DelayCellTimex100 = 270/100 ps
1390 08:06:15.033359 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1391 08:06:15.036756 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 08:06:15.043530 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 08:06:15.046837 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1394 08:06:15.050054 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 08:06:15.053302 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 08:06:15.053853
1397 08:06:15.056919 CA PerBit enable=1, Macro0, CA PI delay=33
1398 08:06:15.057503
1399 08:06:15.060127 [CBTSetCACLKResult] CA Dly = 33
1400 08:06:15.060678 CS Dly: 5 (0~36)
1401 08:06:15.063264 ==
1402 08:06:15.063711 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 08:06:15.069724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 08:06:15.070189 ==
1405 08:06:15.073696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 08:06:15.079756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 08:06:15.089675 [CA 0] Center 37 (6~68) winsize 63
1408 08:06:15.092528 [CA 1] Center 37 (6~68) winsize 63
1409 08:06:15.096218 [CA 2] Center 35 (5~66) winsize 62
1410 08:06:15.099603 [CA 3] Center 34 (4~65) winsize 62
1411 08:06:15.102781 [CA 4] Center 34 (4~65) winsize 62
1412 08:06:15.106366 [CA 5] Center 34 (4~64) winsize 61
1413 08:06:15.106938
1414 08:06:15.109658 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 08:06:15.110119
1416 08:06:15.113224 [CATrainingPosCal] consider 2 rank data
1417 08:06:15.116462 u2DelayCellTimex100 = 270/100 ps
1418 08:06:15.119599 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 08:06:15.123213 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 08:06:15.129828 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 08:06:15.133186 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 08:06:15.136512 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 08:06:15.139642 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 08:06:15.140203
1425 08:06:15.143314 CA PerBit enable=1, Macro0, CA PI delay=34
1426 08:06:15.143878
1427 08:06:15.146636 [CBTSetCACLKResult] CA Dly = 34
1428 08:06:15.147196 CS Dly: 6 (0~38)
1429 08:06:15.147564
1430 08:06:15.149486 ----->DramcWriteLeveling(PI) begin...
1431 08:06:15.152896 ==
1432 08:06:15.153380 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 08:06:15.159776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 08:06:15.160353 ==
1435 08:06:15.163167 Write leveling (Byte 0): 24 => 24
1436 08:06:15.166304 Write leveling (Byte 1): 30 => 30
1437 08:06:15.169773 DramcWriteLeveling(PI) end<-----
1438 08:06:15.170332
1439 08:06:15.170692 ==
1440 08:06:15.173051 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 08:06:15.176762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 08:06:15.177462 ==
1443 08:06:15.180006 [Gating] SW mode calibration
1444 08:06:15.188223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 08:06:15.192014 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 08:06:15.195674 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 08:06:15.199068 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1448 08:06:15.202898 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 08:06:15.210410 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 08:06:15.214169 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 08:06:15.217261 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 08:06:15.221015 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 08:06:15.227530 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 08:06:15.230347 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 08:06:15.234155 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 08:06:15.240919 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 08:06:15.244189 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 08:06:15.247635 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 08:06:15.254211 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 08:06:15.257736 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 08:06:15.261133 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 08:06:15.264806 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1463 08:06:15.271312 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1464 08:06:15.274275 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 08:06:15.277827 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 08:06:15.284200 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 08:06:15.287852 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 08:06:15.291189 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 08:06:15.297733 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 08:06:15.301174 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 08:06:15.304593 0 9 4 | B1->B0 | 2323 2727 | 1 1 | (1 1) (0 0)
1472 08:06:15.311123 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 08:06:15.314566 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 08:06:15.317560 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 08:06:15.324602 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 08:06:15.327607 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 08:06:15.331084 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1478 08:06:15.334374 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1479 08:06:15.341248 0 10 4 | B1->B0 | 2e2e 2f2f | 0 1 | (1 0) (1 0)
1480 08:06:15.344542 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 08:06:15.348239 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 08:06:15.354512 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 08:06:15.357840 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 08:06:15.361511 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 08:06:15.368041 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 08:06:15.371394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 08:06:15.374697 0 11 4 | B1->B0 | 3030 3939 | 1 1 | (0 0) (0 0)
1488 08:06:15.381440 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 08:06:15.384692 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 08:06:15.387890 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 08:06:15.394846 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 08:06:15.397605 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 08:06:15.401238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 08:06:15.404456 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 08:06:15.411556 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1496 08:06:15.414666 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 08:06:15.418312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 08:06:15.424725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 08:06:15.428391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 08:06:15.431322 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 08:06:15.438236 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 08:06:15.441402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 08:06:15.444473 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 08:06:15.451632 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 08:06:15.455094 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 08:06:15.458522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 08:06:15.464968 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 08:06:15.468527 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 08:06:15.471401 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 08:06:15.478409 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1511 08:06:15.481622 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1512 08:06:15.484884 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 08:06:15.488115 Total UI for P1: 0, mck2ui 16
1514 08:06:15.491625 best dqsien dly found for B0: ( 0, 14, 2)
1515 08:06:15.494997 Total UI for P1: 0, mck2ui 16
1516 08:06:15.498336 best dqsien dly found for B1: ( 0, 14, 6)
1517 08:06:15.501842 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1518 08:06:15.504926 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1519 08:06:15.505413
1520 08:06:15.508428 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1521 08:06:15.511979 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 08:06:15.515088 [Gating] SW calibration Done
1523 08:06:15.515719 ==
1524 08:06:15.518842 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 08:06:15.522152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 08:06:15.522717 ==
1527 08:06:15.525408 RX Vref Scan: 0
1528 08:06:15.525974
1529 08:06:15.528514 RX Vref 0 -> 0, step: 1
1530 08:06:15.529172
1531 08:06:15.529654 RX Delay -130 -> 252, step: 16
1532 08:06:15.535458 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1533 08:06:15.538735 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1534 08:06:15.542144 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1535 08:06:15.545540 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1536 08:06:15.548634 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1537 08:06:15.555781 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1538 08:06:15.558848 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1539 08:06:15.562743 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1540 08:06:15.565600 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1541 08:06:15.569044 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1542 08:06:15.575594 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1543 08:06:15.578850 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1544 08:06:15.582322 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1545 08:06:15.585348 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1546 08:06:15.588619 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1547 08:06:15.595652 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1548 08:06:15.596212 ==
1549 08:06:15.599013 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 08:06:15.602735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 08:06:15.603294 ==
1552 08:06:15.603756 DQS Delay:
1553 08:06:15.605502 DQS0 = 0, DQS1 = 0
1554 08:06:15.605959 DQM Delay:
1555 08:06:15.609287 DQM0 = 93, DQM1 = 80
1556 08:06:15.609841 DQ Delay:
1557 08:06:15.612517 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1558 08:06:15.615616 DQ4 =93, DQ5 =101, DQ6 =109, DQ7 =85
1559 08:06:15.619238 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1560 08:06:15.622420 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 08:06:15.622978
1562 08:06:15.623336
1563 08:06:15.623666 ==
1564 08:06:15.625611 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 08:06:15.630029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 08:06:15.630582 ==
1567 08:06:15.630941
1568 08:06:15.632283
1569 08:06:15.632737 TX Vref Scan disable
1570 08:06:15.635697 == TX Byte 0 ==
1571 08:06:15.638907 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1572 08:06:15.642066 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1573 08:06:15.645858 == TX Byte 1 ==
1574 08:06:15.648925 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1575 08:06:15.652317 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1576 08:06:15.653013 ==
1577 08:06:15.655738 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 08:06:15.662324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 08:06:15.662895 ==
1580 08:06:15.674601 TX Vref=22, minBit 8, minWin=27, winSum=448
1581 08:06:15.677897 TX Vref=24, minBit 8, minWin=27, winSum=451
1582 08:06:15.681353 TX Vref=26, minBit 15, minWin=27, winSum=455
1583 08:06:15.684793 TX Vref=28, minBit 13, minWin=27, winSum=457
1584 08:06:15.687980 TX Vref=30, minBit 15, minWin=27, winSum=457
1585 08:06:15.694840 TX Vref=32, minBit 12, minWin=27, winSum=454
1586 08:06:15.697803 [TxChooseVref] Worse bit 13, Min win 27, Win sum 457, Final Vref 28
1587 08:06:15.698262
1588 08:06:15.701743 Final TX Range 1 Vref 28
1589 08:06:15.702300
1590 08:06:15.702659 ==
1591 08:06:15.704552 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 08:06:15.708091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 08:06:15.711957 ==
1594 08:06:15.712517
1595 08:06:15.712876
1596 08:06:15.713271 TX Vref Scan disable
1597 08:06:15.714698 == TX Byte 0 ==
1598 08:06:15.718312 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1599 08:06:15.724892 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1600 08:06:15.725486 == TX Byte 1 ==
1601 08:06:15.728222 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1602 08:06:15.734974 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1603 08:06:15.735533
1604 08:06:15.735889 [DATLAT]
1605 08:06:15.736259 Freq=800, CH1 RK0
1606 08:06:15.736595
1607 08:06:15.738593 DATLAT Default: 0xa
1608 08:06:15.739148 0, 0xFFFF, sum = 0
1609 08:06:15.741728 1, 0xFFFF, sum = 0
1610 08:06:15.742291 2, 0xFFFF, sum = 0
1611 08:06:15.745104 3, 0xFFFF, sum = 0
1612 08:06:15.745659 4, 0xFFFF, sum = 0
1613 08:06:15.748588 5, 0xFFFF, sum = 0
1614 08:06:15.751767 6, 0xFFFF, sum = 0
1615 08:06:15.752332 7, 0xFFFF, sum = 0
1616 08:06:15.754754 8, 0xFFFF, sum = 0
1617 08:06:15.755338 9, 0x0, sum = 1
1618 08:06:15.755840 10, 0x0, sum = 2
1619 08:06:15.758551 11, 0x0, sum = 3
1620 08:06:15.759140 12, 0x0, sum = 4
1621 08:06:15.762629 best_step = 10
1622 08:06:15.763197
1623 08:06:15.763567 ==
1624 08:06:15.765676 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 08:06:15.769211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 08:06:15.769924 ==
1627 08:06:15.770299 RX Vref Scan: 1
1628 08:06:15.770639
1629 08:06:15.772906 Set Vref Range= 32 -> 127
1630 08:06:15.773504
1631 08:06:15.775914 RX Vref 32 -> 127, step: 1
1632 08:06:15.776466
1633 08:06:15.779793 RX Delay -95 -> 252, step: 8
1634 08:06:15.780349
1635 08:06:15.782641 Set Vref, RX VrefLevel [Byte0]: 32
1636 08:06:15.785746 [Byte1]: 32
1637 08:06:15.786304
1638 08:06:15.789351 Set Vref, RX VrefLevel [Byte0]: 33
1639 08:06:15.792671 [Byte1]: 33
1640 08:06:15.793276
1641 08:06:15.796341 Set Vref, RX VrefLevel [Byte0]: 34
1642 08:06:15.799244 [Byte1]: 34
1643 08:06:15.802904
1644 08:06:15.803462 Set Vref, RX VrefLevel [Byte0]: 35
1645 08:06:15.806860 [Byte1]: 35
1646 08:06:15.810337
1647 08:06:15.810794 Set Vref, RX VrefLevel [Byte0]: 36
1648 08:06:15.813562 [Byte1]: 36
1649 08:06:15.818435
1650 08:06:15.818990 Set Vref, RX VrefLevel [Byte0]: 37
1651 08:06:15.821530 [Byte1]: 37
1652 08:06:15.825848
1653 08:06:15.826427 Set Vref, RX VrefLevel [Byte0]: 38
1654 08:06:15.829165 [Byte1]: 38
1655 08:06:15.833644
1656 08:06:15.834203 Set Vref, RX VrefLevel [Byte0]: 39
1657 08:06:15.836664 [Byte1]: 39
1658 08:06:15.840819
1659 08:06:15.841434 Set Vref, RX VrefLevel [Byte0]: 40
1660 08:06:15.844659 [Byte1]: 40
1661 08:06:15.848480
1662 08:06:15.849081 Set Vref, RX VrefLevel [Byte0]: 41
1663 08:06:15.851977 [Byte1]: 41
1664 08:06:15.856159
1665 08:06:15.856616 Set Vref, RX VrefLevel [Byte0]: 42
1666 08:06:15.859644 [Byte1]: 42
1667 08:06:15.864046
1668 08:06:15.864671 Set Vref, RX VrefLevel [Byte0]: 43
1669 08:06:15.866807 [Byte1]: 43
1670 08:06:15.871172
1671 08:06:15.871730 Set Vref, RX VrefLevel [Byte0]: 44
1672 08:06:15.874757 [Byte1]: 44
1673 08:06:15.879062
1674 08:06:15.879617 Set Vref, RX VrefLevel [Byte0]: 45
1675 08:06:15.882366 [Byte1]: 45
1676 08:06:15.886522
1677 08:06:15.887102 Set Vref, RX VrefLevel [Byte0]: 46
1678 08:06:15.890012 [Byte1]: 46
1679 08:06:15.894495
1680 08:06:15.895059 Set Vref, RX VrefLevel [Byte0]: 47
1681 08:06:15.898152 [Byte1]: 47
1682 08:06:15.901781
1683 08:06:15.902342 Set Vref, RX VrefLevel [Byte0]: 48
1684 08:06:15.904777 [Byte1]: 48
1685 08:06:15.909812
1686 08:06:15.910372 Set Vref, RX VrefLevel [Byte0]: 49
1687 08:06:15.912653 [Byte1]: 49
1688 08:06:15.916701
1689 08:06:15.917297 Set Vref, RX VrefLevel [Byte0]: 50
1690 08:06:15.920653 [Byte1]: 50
1691 08:06:15.924626
1692 08:06:15.925228 Set Vref, RX VrefLevel [Byte0]: 51
1693 08:06:15.927749 [Byte1]: 51
1694 08:06:15.932156
1695 08:06:15.932723 Set Vref, RX VrefLevel [Byte0]: 52
1696 08:06:15.935319 [Byte1]: 52
1697 08:06:15.939938
1698 08:06:15.940504 Set Vref, RX VrefLevel [Byte0]: 53
1699 08:06:15.943203 [Byte1]: 53
1700 08:06:15.947292
1701 08:06:15.947849 Set Vref, RX VrefLevel [Byte0]: 54
1702 08:06:15.950647 [Byte1]: 54
1703 08:06:15.954760
1704 08:06:15.955324 Set Vref, RX VrefLevel [Byte0]: 55
1705 08:06:15.958361 [Byte1]: 55
1706 08:06:15.962182
1707 08:06:15.962745 Set Vref, RX VrefLevel [Byte0]: 56
1708 08:06:15.965850 [Byte1]: 56
1709 08:06:15.969909
1710 08:06:15.970477 Set Vref, RX VrefLevel [Byte0]: 57
1711 08:06:15.973080 [Byte1]: 57
1712 08:06:15.977635
1713 08:06:15.978192 Set Vref, RX VrefLevel [Byte0]: 58
1714 08:06:15.980812 [Byte1]: 58
1715 08:06:15.985383
1716 08:06:15.985976 Set Vref, RX VrefLevel [Byte0]: 59
1717 08:06:15.988519 [Byte1]: 59
1718 08:06:15.992926
1719 08:06:15.993544 Set Vref, RX VrefLevel [Byte0]: 60
1720 08:06:15.996806 [Byte1]: 60
1721 08:06:16.000466
1722 08:06:16.001069 Set Vref, RX VrefLevel [Byte0]: 61
1723 08:06:16.004095 [Byte1]: 61
1724 08:06:16.008066
1725 08:06:16.008682 Set Vref, RX VrefLevel [Byte0]: 62
1726 08:06:16.011440 [Byte1]: 62
1727 08:06:16.015673
1728 08:06:16.016295 Set Vref, RX VrefLevel [Byte0]: 63
1729 08:06:16.019621 [Byte1]: 63
1730 08:06:16.023474
1731 08:06:16.024033 Set Vref, RX VrefLevel [Byte0]: 64
1732 08:06:16.026751 [Byte1]: 64
1733 08:06:16.031004
1734 08:06:16.031565 Set Vref, RX VrefLevel [Byte0]: 65
1735 08:06:16.034647 [Byte1]: 65
1736 08:06:16.038828
1737 08:06:16.039389 Set Vref, RX VrefLevel [Byte0]: 66
1738 08:06:16.041654 [Byte1]: 66
1739 08:06:16.045986
1740 08:06:16.046551 Set Vref, RX VrefLevel [Byte0]: 67
1741 08:06:16.049290 [Byte1]: 67
1742 08:06:16.053558
1743 08:06:16.054170 Set Vref, RX VrefLevel [Byte0]: 68
1744 08:06:16.056855 [Byte1]: 68
1745 08:06:16.061136
1746 08:06:16.061591 Set Vref, RX VrefLevel [Byte0]: 69
1747 08:06:16.064520 [Byte1]: 69
1748 08:06:16.068687
1749 08:06:16.069292 Set Vref, RX VrefLevel [Byte0]: 70
1750 08:06:16.071979 [Byte1]: 70
1751 08:06:16.076392
1752 08:06:16.076850 Set Vref, RX VrefLevel [Byte0]: 71
1753 08:06:16.079774 [Byte1]: 71
1754 08:06:16.084060
1755 08:06:16.084618 Set Vref, RX VrefLevel [Byte0]: 72
1756 08:06:16.087286 [Byte1]: 72
1757 08:06:16.091240
1758 08:06:16.091851 Set Vref, RX VrefLevel [Byte0]: 73
1759 08:06:16.094539 [Byte1]: 73
1760 08:06:16.099340
1761 08:06:16.099895 Set Vref, RX VrefLevel [Byte0]: 74
1762 08:06:16.102538 [Byte1]: 74
1763 08:06:16.107036
1764 08:06:16.107588 Set Vref, RX VrefLevel [Byte0]: 75
1765 08:06:16.110068 [Byte1]: 75
1766 08:06:16.114413
1767 08:06:16.114962 Set Vref, RX VrefLevel [Byte0]: 76
1768 08:06:16.117574 [Byte1]: 76
1769 08:06:16.121989
1770 08:06:16.122546 Set Vref, RX VrefLevel [Byte0]: 77
1771 08:06:16.124975 [Byte1]: 77
1772 08:06:16.129610
1773 08:06:16.130160 Final RX Vref Byte 0 = 49 to rank0
1774 08:06:16.133209 Final RX Vref Byte 1 = 64 to rank0
1775 08:06:16.136130 Final RX Vref Byte 0 = 49 to rank1
1776 08:06:16.139767 Final RX Vref Byte 1 = 64 to rank1==
1777 08:06:16.142801 Dram Type= 6, Freq= 0, CH_1, rank 0
1778 08:06:16.149695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 08:06:16.150255 ==
1780 08:06:16.150626 DQS Delay:
1781 08:06:16.150969 DQS0 = 0, DQS1 = 0
1782 08:06:16.152773 DQM Delay:
1783 08:06:16.153257 DQM0 = 92, DQM1 = 82
1784 08:06:16.156163 DQ Delay:
1785 08:06:16.159803 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1786 08:06:16.163213 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1787 08:06:16.166461 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1788 08:06:16.169916 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1789 08:06:16.170473
1790 08:06:16.170844
1791 08:06:16.176164 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1792 08:06:16.179509 CH1 RK0: MR19=606, MR18=2F4C
1793 08:06:16.186397 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1794 08:06:16.186949
1795 08:06:16.189526 ----->DramcWriteLeveling(PI) begin...
1796 08:06:16.190217 ==
1797 08:06:16.192812 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 08:06:16.196187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 08:06:16.196743 ==
1800 08:06:16.199810 Write leveling (Byte 0): 26 => 26
1801 08:06:16.203044 Write leveling (Byte 1): 31 => 31
1802 08:06:16.206417 DramcWriteLeveling(PI) end<-----
1803 08:06:16.206971
1804 08:06:16.207333 ==
1805 08:06:16.209502 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 08:06:16.213244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 08:06:16.213799 ==
1808 08:06:16.216734 [Gating] SW mode calibration
1809 08:06:16.222841 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1810 08:06:16.230159 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1811 08:06:16.233287 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1812 08:06:16.236635 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1813 08:06:16.243410 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1814 08:06:16.246627 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 08:06:16.249817 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 08:06:16.256542 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 08:06:16.259988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 08:06:16.263265 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 08:06:16.270180 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 08:06:16.273411 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 08:06:16.276555 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 08:06:16.279941 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 08:06:16.286695 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 08:06:16.289590 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 08:06:16.293053 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 08:06:16.299789 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 08:06:16.303352 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 08:06:16.306612 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1829 08:06:16.313535 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1830 08:06:16.317013 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 08:06:16.319998 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 08:06:16.326745 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 08:06:16.330067 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 08:06:16.333270 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 08:06:16.340184 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 08:06:16.343533 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 08:06:16.346930 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1838 08:06:16.353302 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 08:06:16.356650 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 08:06:16.360297 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 08:06:16.363437 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 08:06:16.370150 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 08:06:16.373805 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 08:06:16.376870 0 10 4 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
1845 08:06:16.383370 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1846 08:06:16.386797 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 08:06:16.389768 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 08:06:16.396628 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 08:06:16.399857 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 08:06:16.403567 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 08:06:16.410133 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 08:06:16.413485 0 11 4 | B1->B0 | 3636 2f2f | 0 0 | (0 0) (0 0)
1853 08:06:16.416859 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 08:06:16.423365 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 08:06:16.426390 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 08:06:16.430443 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 08:06:16.436605 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 08:06:16.439911 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 08:06:16.443452 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 08:06:16.449831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1861 08:06:16.453371 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 08:06:16.456983 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 08:06:16.460212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 08:06:16.466989 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 08:06:16.470135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 08:06:16.473599 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 08:06:16.480272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 08:06:16.483930 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 08:06:16.486889 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 08:06:16.493482 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 08:06:16.496852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 08:06:16.500255 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 08:06:16.506913 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 08:06:16.510288 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 08:06:16.513654 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 08:06:16.516810 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 08:06:16.523831 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 08:06:16.527662 Total UI for P1: 0, mck2ui 16
1879 08:06:16.530529 best dqsien dly found for B0: ( 0, 14, 6)
1880 08:06:16.533913 Total UI for P1: 0, mck2ui 16
1881 08:06:16.537430 best dqsien dly found for B1: ( 0, 14, 6)
1882 08:06:16.540638 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1883 08:06:16.544036 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1884 08:06:16.544600
1885 08:06:16.547198 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1886 08:06:16.550785 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1887 08:06:16.554103 [Gating] SW calibration Done
1888 08:06:16.554844 ==
1889 08:06:16.557157 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 08:06:16.560703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 08:06:16.561307 ==
1892 08:06:16.563935 RX Vref Scan: 0
1893 08:06:16.564504
1894 08:06:16.564873 RX Vref 0 -> 0, step: 1
1895 08:06:16.565245
1896 08:06:16.567089 RX Delay -130 -> 252, step: 16
1897 08:06:16.570531 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1898 08:06:16.577075 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1899 08:06:16.580389 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1900 08:06:16.583906 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1901 08:06:16.587172 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1902 08:06:16.590175 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1903 08:06:16.597327 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1904 08:06:16.600442 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1905 08:06:16.603969 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1906 08:06:16.606765 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1907 08:06:16.610419 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1908 08:06:16.617069 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1909 08:06:16.620414 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1910 08:06:16.623586 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1911 08:06:16.627190 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 08:06:16.630385 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1913 08:06:16.633575 ==
1914 08:06:16.637246 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 08:06:16.640408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 08:06:16.641027 ==
1917 08:06:16.641414 DQS Delay:
1918 08:06:16.644092 DQS0 = 0, DQS1 = 0
1919 08:06:16.644658 DQM Delay:
1920 08:06:16.647287 DQM0 = 87, DQM1 = 81
1921 08:06:16.647849 DQ Delay:
1922 08:06:16.650649 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1923 08:06:16.653874 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1924 08:06:16.656982 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
1925 08:06:16.660863 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1926 08:06:16.661468
1927 08:06:16.661833
1928 08:06:16.662171 ==
1929 08:06:16.664311 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 08:06:16.667289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 08:06:16.667858 ==
1932 08:06:16.668226
1933 08:06:16.668565
1934 08:06:16.670373 TX Vref Scan disable
1935 08:06:16.673844 == TX Byte 0 ==
1936 08:06:16.677561 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1937 08:06:16.680601 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1938 08:06:16.684029 == TX Byte 1 ==
1939 08:06:16.687744 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1940 08:06:16.690688 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1941 08:06:16.691156 ==
1942 08:06:16.694272 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 08:06:16.697137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 08:06:16.697602 ==
1945 08:06:16.712226 TX Vref=22, minBit 12, minWin=27, winSum=451
1946 08:06:16.715527 TX Vref=24, minBit 8, minWin=27, winSum=452
1947 08:06:16.718612 TX Vref=26, minBit 15, minWin=27, winSum=458
1948 08:06:16.721920 TX Vref=28, minBit 13, minWin=27, winSum=458
1949 08:06:16.725301 TX Vref=30, minBit 8, minWin=28, winSum=461
1950 08:06:16.729111 TX Vref=32, minBit 9, minWin=27, winSum=457
1951 08:06:16.735695 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1952 08:06:16.736263
1953 08:06:16.739268 Final TX Range 1 Vref 30
1954 08:06:16.739839
1955 08:06:16.740206 ==
1956 08:06:16.741910 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 08:06:16.745466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 08:06:16.746038 ==
1959 08:06:16.746411
1960 08:06:16.748839
1961 08:06:16.749443 TX Vref Scan disable
1962 08:06:16.752217 == TX Byte 0 ==
1963 08:06:16.755264 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1964 08:06:16.759184 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1965 08:06:16.762297 == TX Byte 1 ==
1966 08:06:16.765804 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1967 08:06:16.769051 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1968 08:06:16.772410
1969 08:06:16.772996 [DATLAT]
1970 08:06:16.773369 Freq=800, CH1 RK1
1971 08:06:16.773711
1972 08:06:16.775769 DATLAT Default: 0xa
1973 08:06:16.776338 0, 0xFFFF, sum = 0
1974 08:06:16.778899 1, 0xFFFF, sum = 0
1975 08:06:16.779471 2, 0xFFFF, sum = 0
1976 08:06:16.782261 3, 0xFFFF, sum = 0
1977 08:06:16.782831 4, 0xFFFF, sum = 0
1978 08:06:16.785672 5, 0xFFFF, sum = 0
1979 08:06:16.786252 6, 0xFFFF, sum = 0
1980 08:06:16.789004 7, 0xFFFF, sum = 0
1981 08:06:16.791964 8, 0xFFFF, sum = 0
1982 08:06:16.792431 9, 0x0, sum = 1
1983 08:06:16.792806 10, 0x0, sum = 2
1984 08:06:16.795604 11, 0x0, sum = 3
1985 08:06:16.796177 12, 0x0, sum = 4
1986 08:06:16.799115 best_step = 10
1987 08:06:16.799677
1988 08:06:16.800050 ==
1989 08:06:16.802180 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 08:06:16.805381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 08:06:16.805882 ==
1992 08:06:16.808908 RX Vref Scan: 0
1993 08:06:16.809499
1994 08:06:16.809869 RX Vref 0 -> 0, step: 1
1995 08:06:16.810209
1996 08:06:16.812246 RX Delay -95 -> 252, step: 8
1997 08:06:16.818745 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
1998 08:06:16.822172 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1999 08:06:16.825557 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2000 08:06:16.828674 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2001 08:06:16.832074 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2002 08:06:16.838782 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2003 08:06:16.842240 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2004 08:06:16.845497 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2005 08:06:16.848787 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2006 08:06:16.852294 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2007 08:06:16.859063 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2008 08:06:16.862193 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2009 08:06:16.865653 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2010 08:06:16.869235 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2011 08:06:16.872365 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2012 08:06:16.878947 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2013 08:06:16.879521 ==
2014 08:06:16.882346 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 08:06:16.885462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 08:06:16.886033 ==
2017 08:06:16.886401 DQS Delay:
2018 08:06:16.888850 DQS0 = 0, DQS1 = 0
2019 08:06:16.889462 DQM Delay:
2020 08:06:16.892065 DQM0 = 90, DQM1 = 83
2021 08:06:16.892527 DQ Delay:
2022 08:06:16.895351 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2023 08:06:16.899092 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2024 08:06:16.902128 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2025 08:06:16.905773 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2026 08:06:16.906394
2027 08:06:16.906766
2028 08:06:16.912486 [DQSOSCAuto] RK1, (LSB)MR18= 0x380e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2029 08:06:16.915970 CH1 RK1: MR19=606, MR18=380E
2030 08:06:16.922478 CH1_RK1: MR19=0x606, MR18=0x380E, DQSOSC=395, MR23=63, INC=94, DEC=63
2031 08:06:16.925683 [RxdqsGatingPostProcess] freq 800
2032 08:06:16.932173 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 08:06:16.932787 Pre-setting of DQS Precalculation
2034 08:06:16.939093 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 08:06:16.945432 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 08:06:16.952714 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 08:06:16.953309
2038 08:06:16.953676
2039 08:06:16.955651 [Calibration Summary] 1600 Mbps
2040 08:06:16.959287 CH 0, Rank 0
2041 08:06:16.959840 SW Impedance : PASS
2042 08:06:16.962750 DUTY Scan : NO K
2043 08:06:16.963316 ZQ Calibration : PASS
2044 08:06:16.965818 Jitter Meter : NO K
2045 08:06:16.969531 CBT Training : PASS
2046 08:06:16.970091 Write leveling : PASS
2047 08:06:16.972536 RX DQS gating : PASS
2048 08:06:16.975840 RX DQ/DQS(RDDQC) : PASS
2049 08:06:16.976400 TX DQ/DQS : PASS
2050 08:06:16.979223 RX DATLAT : PASS
2051 08:06:16.982523 RX DQ/DQS(Engine): PASS
2052 08:06:16.983080 TX OE : NO K
2053 08:06:16.986000 All Pass.
2054 08:06:16.986558
2055 08:06:16.986917 CH 0, Rank 1
2056 08:06:16.989307 SW Impedance : PASS
2057 08:06:16.989866 DUTY Scan : NO K
2058 08:06:16.992535 ZQ Calibration : PASS
2059 08:06:16.995826 Jitter Meter : NO K
2060 08:06:16.996290 CBT Training : PASS
2061 08:06:16.999364 Write leveling : PASS
2062 08:06:16.999927 RX DQS gating : PASS
2063 08:06:17.002914 RX DQ/DQS(RDDQC) : PASS
2064 08:06:17.005920 TX DQ/DQS : PASS
2065 08:06:17.006469 RX DATLAT : PASS
2066 08:06:17.009547 RX DQ/DQS(Engine): PASS
2067 08:06:17.012756 TX OE : NO K
2068 08:06:17.013378 All Pass.
2069 08:06:17.013747
2070 08:06:17.014083 CH 1, Rank 0
2071 08:06:17.016175 SW Impedance : PASS
2072 08:06:17.019363 DUTY Scan : NO K
2073 08:06:17.019825 ZQ Calibration : PASS
2074 08:06:17.023149 Jitter Meter : NO K
2075 08:06:17.026667 CBT Training : PASS
2076 08:06:17.027229 Write leveling : PASS
2077 08:06:17.029993 RX DQS gating : PASS
2078 08:06:17.030553 RX DQ/DQS(RDDQC) : PASS
2079 08:06:17.033303 TX DQ/DQS : PASS
2080 08:06:17.036169 RX DATLAT : PASS
2081 08:06:17.036729 RX DQ/DQS(Engine): PASS
2082 08:06:17.039921 TX OE : NO K
2083 08:06:17.040496 All Pass.
2084 08:06:17.040864
2085 08:06:17.042921 CH 1, Rank 1
2086 08:06:17.043431 SW Impedance : PASS
2087 08:06:17.046361 DUTY Scan : NO K
2088 08:06:17.049709 ZQ Calibration : PASS
2089 08:06:17.050451 Jitter Meter : NO K
2090 08:06:17.053221 CBT Training : PASS
2091 08:06:17.056394 Write leveling : PASS
2092 08:06:17.056881 RX DQS gating : PASS
2093 08:06:17.059394 RX DQ/DQS(RDDQC) : PASS
2094 08:06:17.063212 TX DQ/DQS : PASS
2095 08:06:17.063778 RX DATLAT : PASS
2096 08:06:17.066474 RX DQ/DQS(Engine): PASS
2097 08:06:17.067033 TX OE : NO K
2098 08:06:17.069842 All Pass.
2099 08:06:17.070299
2100 08:06:17.070661 DramC Write-DBI off
2101 08:06:17.072921 PER_BANK_REFRESH: Hybrid Mode
2102 08:06:17.076251 TX_TRACKING: ON
2103 08:06:17.079896 [GetDramInforAfterCalByMRR] Vendor 6.
2104 08:06:17.082779 [GetDramInforAfterCalByMRR] Revision 606.
2105 08:06:17.086650 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 08:06:17.087210 MR0 0x3b3b
2107 08:06:17.089662 MR8 0x5151
2108 08:06:17.093152 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 08:06:17.093827
2110 08:06:17.094200 MR0 0x3b3b
2111 08:06:17.094540 MR8 0x5151
2112 08:06:17.096342 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 08:06:17.096804
2114 08:06:17.106370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 08:06:17.109563 [FAST_K] Save calibration result to emmc
2116 08:06:17.112844 [FAST_K] Save calibration result to emmc
2117 08:06:17.116917 dram_init: config_dvfs: 1
2118 08:06:17.119564 dramc_set_vcore_voltage set vcore to 662500
2119 08:06:17.123100 Read voltage for 1200, 2
2120 08:06:17.123663 Vio18 = 0
2121 08:06:17.124025 Vcore = 662500
2122 08:06:17.126267 Vdram = 0
2123 08:06:17.126832 Vddq = 0
2124 08:06:17.127196 Vmddr = 0
2125 08:06:17.133098 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 08:06:17.136724 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 08:06:17.139805 MEM_TYPE=3, freq_sel=15
2128 08:06:17.142996 sv_algorithm_assistance_LP4_1600
2129 08:06:17.146503 ============ PULL DRAM RESETB DOWN ============
2130 08:06:17.149720 ========== PULL DRAM RESETB DOWN end =========
2131 08:06:17.156456 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 08:06:17.159946 ===================================
2133 08:06:17.163375 LPDDR4 DRAM CONFIGURATION
2134 08:06:17.166503 ===================================
2135 08:06:17.167091 EX_ROW_EN[0] = 0x0
2136 08:06:17.169781 EX_ROW_EN[1] = 0x0
2137 08:06:17.170238 LP4Y_EN = 0x0
2138 08:06:17.173604 WORK_FSP = 0x0
2139 08:06:17.174166 WL = 0x4
2140 08:06:17.177144 RL = 0x4
2141 08:06:17.177692 BL = 0x2
2142 08:06:17.179875 RPST = 0x0
2143 08:06:17.180442 RD_PRE = 0x0
2144 08:06:17.183269 WR_PRE = 0x1
2145 08:06:17.183829 WR_PST = 0x0
2146 08:06:17.186781 DBI_WR = 0x0
2147 08:06:17.187342 DBI_RD = 0x0
2148 08:06:17.189928 OTF = 0x1
2149 08:06:17.193370 ===================================
2150 08:06:17.196414 ===================================
2151 08:06:17.196873 ANA top config
2152 08:06:17.200214 ===================================
2153 08:06:17.203266 DLL_ASYNC_EN = 0
2154 08:06:17.206324 ALL_SLAVE_EN = 0
2155 08:06:17.209891 NEW_RANK_MODE = 1
2156 08:06:17.210358 DLL_IDLE_MODE = 1
2157 08:06:17.213359 LP45_APHY_COMB_EN = 1
2158 08:06:17.216706 TX_ODT_DIS = 1
2159 08:06:17.219660 NEW_8X_MODE = 1
2160 08:06:17.223381 ===================================
2161 08:06:17.226925 ===================================
2162 08:06:17.230480 data_rate = 2400
2163 08:06:17.231043 CKR = 1
2164 08:06:17.233610 DQ_P2S_RATIO = 8
2165 08:06:17.236917 ===================================
2166 08:06:17.239987 CA_P2S_RATIO = 8
2167 08:06:17.243656 DQ_CA_OPEN = 0
2168 08:06:17.246684 DQ_SEMI_OPEN = 0
2169 08:06:17.247248 CA_SEMI_OPEN = 0
2170 08:06:17.249942 CA_FULL_RATE = 0
2171 08:06:17.253321 DQ_CKDIV4_EN = 0
2172 08:06:17.256513 CA_CKDIV4_EN = 0
2173 08:06:17.260085 CA_PREDIV_EN = 0
2174 08:06:17.263699 PH8_DLY = 17
2175 08:06:17.264276 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 08:06:17.266730 DQ_AAMCK_DIV = 4
2177 08:06:17.269918 CA_AAMCK_DIV = 4
2178 08:06:17.273252 CA_ADMCK_DIV = 4
2179 08:06:17.277093 DQ_TRACK_CA_EN = 0
2180 08:06:17.280329 CA_PICK = 1200
2181 08:06:17.283895 CA_MCKIO = 1200
2182 08:06:17.284456 MCKIO_SEMI = 0
2183 08:06:17.286786 PLL_FREQ = 2366
2184 08:06:17.290257 DQ_UI_PI_RATIO = 32
2185 08:06:17.293774 CA_UI_PI_RATIO = 0
2186 08:06:17.296612 ===================================
2187 08:06:17.300409 ===================================
2188 08:06:17.303823 memory_type:LPDDR4
2189 08:06:17.304376 GP_NUM : 10
2190 08:06:17.306774 SRAM_EN : 1
2191 08:06:17.307261 MD32_EN : 0
2192 08:06:17.309972 ===================================
2193 08:06:17.313668 [ANA_INIT] >>>>>>>>>>>>>>
2194 08:06:17.317070 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 08:06:17.320305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 08:06:17.323892 ===================================
2197 08:06:17.327567 data_rate = 2400,PCW = 0X5b00
2198 08:06:17.330318 ===================================
2199 08:06:17.333864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 08:06:17.340498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 08:06:17.343661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 08:06:17.350344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 08:06:17.353526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 08:06:17.356604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 08:06:17.357115 [ANA_INIT] flow start
2206 08:06:17.360286 [ANA_INIT] PLL >>>>>>>>
2207 08:06:17.363439 [ANA_INIT] PLL <<<<<<<<
2208 08:06:17.364014 [ANA_INIT] MIDPI >>>>>>>>
2209 08:06:17.366959 [ANA_INIT] MIDPI <<<<<<<<
2210 08:06:17.370132 [ANA_INIT] DLL >>>>>>>>
2211 08:06:17.370589 [ANA_INIT] DLL <<<<<<<<
2212 08:06:17.373804 [ANA_INIT] flow end
2213 08:06:17.377126 ============ LP4 DIFF to SE enter ============
2214 08:06:17.380236 ============ LP4 DIFF to SE exit ============
2215 08:06:17.383789 [ANA_INIT] <<<<<<<<<<<<<
2216 08:06:17.387031 [Flow] Enable top DCM control >>>>>
2217 08:06:17.390285 [Flow] Enable top DCM control <<<<<
2218 08:06:17.393809 Enable DLL master slave shuffle
2219 08:06:17.400387 ==============================================================
2220 08:06:17.400996 Gating Mode config
2221 08:06:17.407145 ==============================================================
2222 08:06:17.407704 Config description:
2223 08:06:17.417186 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 08:06:17.423828 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 08:06:17.430397 SELPH_MODE 0: By rank 1: By Phase
2226 08:06:17.433743 ==============================================================
2227 08:06:17.437089 GAT_TRACK_EN = 1
2228 08:06:17.440577 RX_GATING_MODE = 2
2229 08:06:17.443805 RX_GATING_TRACK_MODE = 2
2230 08:06:17.447156 SELPH_MODE = 1
2231 08:06:17.450788 PICG_EARLY_EN = 1
2232 08:06:17.453835 VALID_LAT_VALUE = 1
2233 08:06:17.456915 ==============================================================
2234 08:06:17.460442 Enter into Gating configuration >>>>
2235 08:06:17.463703 Exit from Gating configuration <<<<
2236 08:06:17.466942 Enter into DVFS_PRE_config >>>>>
2237 08:06:17.480479 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 08:06:17.483861 Exit from DVFS_PRE_config <<<<<
2239 08:06:17.484432 Enter into PICG configuration >>>>
2240 08:06:17.486799 Exit from PICG configuration <<<<
2241 08:06:17.490239 [RX_INPUT] configuration >>>>>
2242 08:06:17.493881 [RX_INPUT] configuration <<<<<
2243 08:06:17.500531 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 08:06:17.503915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 08:06:17.510652 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 08:06:17.516995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 08:06:17.524175 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 08:06:17.530519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 08:06:17.534089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 08:06:17.537635 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 08:06:17.540525 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 08:06:17.547331 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 08:06:17.551235 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 08:06:17.554051 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 08:06:17.557024 ===================================
2256 08:06:17.560377 LPDDR4 DRAM CONFIGURATION
2257 08:06:17.564024 ===================================
2258 08:06:17.564589 EX_ROW_EN[0] = 0x0
2259 08:06:17.567440 EX_ROW_EN[1] = 0x0
2260 08:06:17.570678 LP4Y_EN = 0x0
2261 08:06:17.571138 WORK_FSP = 0x0
2262 08:06:17.573843 WL = 0x4
2263 08:06:17.574303 RL = 0x4
2264 08:06:17.577069 BL = 0x2
2265 08:06:17.577525 RPST = 0x0
2266 08:06:17.580680 RD_PRE = 0x0
2267 08:06:17.581298 WR_PRE = 0x1
2268 08:06:17.584083 WR_PST = 0x0
2269 08:06:17.584637 DBI_WR = 0x0
2270 08:06:17.587600 DBI_RD = 0x0
2271 08:06:17.588154 OTF = 0x1
2272 08:06:17.590355 ===================================
2273 08:06:17.593986 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 08:06:17.600535 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 08:06:17.604085 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 08:06:17.607353 ===================================
2277 08:06:17.610647 LPDDR4 DRAM CONFIGURATION
2278 08:06:17.614214 ===================================
2279 08:06:17.614799 EX_ROW_EN[0] = 0x10
2280 08:06:17.617493 EX_ROW_EN[1] = 0x0
2281 08:06:17.618070 LP4Y_EN = 0x0
2282 08:06:17.620572 WORK_FSP = 0x0
2283 08:06:17.621166 WL = 0x4
2284 08:06:17.624013 RL = 0x4
2285 08:06:17.624604 BL = 0x2
2286 08:06:17.627498 RPST = 0x0
2287 08:06:17.628076 RD_PRE = 0x0
2288 08:06:17.630870 WR_PRE = 0x1
2289 08:06:17.631448 WR_PST = 0x0
2290 08:06:17.633816 DBI_WR = 0x0
2291 08:06:17.634359 DBI_RD = 0x0
2292 08:06:17.637149 OTF = 0x1
2293 08:06:17.640702 ===================================
2294 08:06:17.647247 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 08:06:17.647808 ==
2296 08:06:17.650528 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 08:06:17.654191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 08:06:17.654747 ==
2299 08:06:17.657128 [Duty_Offset_Calibration]
2300 08:06:17.657571 B0:2 B1:0 CA:1
2301 08:06:17.657914
2302 08:06:17.660332 [DutyScan_Calibration_Flow] k_type=0
2303 08:06:17.670444
2304 08:06:17.670772 ==CLK 0==
2305 08:06:17.673720 Final CLK duty delay cell = -4
2306 08:06:17.677050 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2307 08:06:17.680775 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2308 08:06:17.683786 [-4] AVG Duty = 4953%(X100)
2309 08:06:17.684117
2310 08:06:17.687426 CH0 CLK Duty spec in!! Max-Min= 156%
2311 08:06:17.690667 [DutyScan_Calibration_Flow] ====Done====
2312 08:06:17.690993
2313 08:06:17.693835 [DutyScan_Calibration_Flow] k_type=1
2314 08:06:17.709494
2315 08:06:17.710036 ==DQS 0 ==
2316 08:06:17.712686 Final DQS duty delay cell = 0
2317 08:06:17.716248 [0] MAX Duty = 5187%(X100), DQS PI = 30
2318 08:06:17.719609 [0] MIN Duty = 4938%(X100), DQS PI = 2
2319 08:06:17.720171 [0] AVG Duty = 5062%(X100)
2320 08:06:17.723101
2321 08:06:17.723649 ==DQS 1 ==
2322 08:06:17.726090 Final DQS duty delay cell = -4
2323 08:06:17.729569 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2324 08:06:17.733220 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2325 08:06:17.736544 [-4] AVG Duty = 5031%(X100)
2326 08:06:17.737164
2327 08:06:17.740028 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2328 08:06:17.740569
2329 08:06:17.743360 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2330 08:06:17.746395 [DutyScan_Calibration_Flow] ====Done====
2331 08:06:17.746935
2332 08:06:17.749900 [DutyScan_Calibration_Flow] k_type=3
2333 08:06:17.765680
2334 08:06:17.766219 ==DQM 0 ==
2335 08:06:17.769044 Final DQM duty delay cell = 0
2336 08:06:17.772090 [0] MAX Duty = 5062%(X100), DQS PI = 24
2337 08:06:17.775785 [0] MIN Duty = 4844%(X100), DQS PI = 0
2338 08:06:17.776355 [0] AVG Duty = 4953%(X100)
2339 08:06:17.778798
2340 08:06:17.779338 ==DQM 1 ==
2341 08:06:17.782171 Final DQM duty delay cell = -4
2342 08:06:17.785555 [-4] MAX Duty = 5031%(X100), DQS PI = 48
2343 08:06:17.789024 [-4] MIN Duty = 4813%(X100), DQS PI = 22
2344 08:06:17.792443 [-4] AVG Duty = 4922%(X100)
2345 08:06:17.793046
2346 08:06:17.795641 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2347 08:06:17.796181
2348 08:06:17.798932 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2349 08:06:17.802117 [DutyScan_Calibration_Flow] ====Done====
2350 08:06:17.802571
2351 08:06:17.805444 [DutyScan_Calibration_Flow] k_type=2
2352 08:06:17.822285
2353 08:06:17.822842 ==DQ 0 ==
2354 08:06:17.825745 Final DQ duty delay cell = -4
2355 08:06:17.829166 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2356 08:06:17.832264 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2357 08:06:17.836076 [-4] AVG Duty = 4969%(X100)
2358 08:06:17.836620
2359 08:06:17.837030 ==DQ 1 ==
2360 08:06:17.839195 Final DQ duty delay cell = 4
2361 08:06:17.842249 [4] MAX Duty = 5093%(X100), DQS PI = 4
2362 08:06:17.845800 [4] MIN Duty = 5031%(X100), DQS PI = 16
2363 08:06:17.849573 [4] AVG Duty = 5062%(X100)
2364 08:06:17.850115
2365 08:06:17.852324 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2366 08:06:17.852871
2367 08:06:17.856151 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2368 08:06:17.859169 [DutyScan_Calibration_Flow] ====Done====
2369 08:06:17.859716 ==
2370 08:06:17.862486 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 08:06:17.865692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 08:06:17.866234 ==
2373 08:06:17.869100 [Duty_Offset_Calibration]
2374 08:06:17.869636 B0:0 B1:-1 CA:2
2375 08:06:17.869997
2376 08:06:17.872139 [DutyScan_Calibration_Flow] k_type=0
2377 08:06:17.882882
2378 08:06:17.883420 ==CLK 0==
2379 08:06:17.886142 Final CLK duty delay cell = 0
2380 08:06:17.889973 [0] MAX Duty = 5156%(X100), DQS PI = 18
2381 08:06:17.892497 [0] MIN Duty = 4938%(X100), DQS PI = 44
2382 08:06:17.893091 [0] AVG Duty = 5047%(X100)
2383 08:06:17.896323
2384 08:06:17.899418 CH1 CLK Duty spec in!! Max-Min= 218%
2385 08:06:17.902886 [DutyScan_Calibration_Flow] ====Done====
2386 08:06:17.903428
2387 08:06:17.905495 [DutyScan_Calibration_Flow] k_type=1
2388 08:06:17.921972
2389 08:06:17.922666 ==DQS 0 ==
2390 08:06:17.925365 Final DQS duty delay cell = 0
2391 08:06:17.928757 [0] MAX Duty = 5093%(X100), DQS PI = 24
2392 08:06:17.932146 [0] MIN Duty = 4969%(X100), DQS PI = 0
2393 08:06:17.932707 [0] AVG Duty = 5031%(X100)
2394 08:06:17.935538
2395 08:06:17.936089 ==DQS 1 ==
2396 08:06:17.938960 Final DQS duty delay cell = 0
2397 08:06:17.942241 [0] MAX Duty = 5156%(X100), DQS PI = 0
2398 08:06:17.945677 [0] MIN Duty = 4813%(X100), DQS PI = 36
2399 08:06:17.946240 [0] AVG Duty = 4984%(X100)
2400 08:06:17.946612
2401 08:06:17.952195 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2402 08:06:17.952752
2403 08:06:17.955443 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2404 08:06:17.958525 [DutyScan_Calibration_Flow] ====Done====
2405 08:06:17.958986
2406 08:06:17.961969 [DutyScan_Calibration_Flow] k_type=3
2407 08:06:17.979149
2408 08:06:17.979701 ==DQM 0 ==
2409 08:06:17.982567 Final DQM duty delay cell = 4
2410 08:06:17.985977 [4] MAX Duty = 5093%(X100), DQS PI = 6
2411 08:06:17.989307 [4] MIN Duty = 4969%(X100), DQS PI = 28
2412 08:06:17.989869 [4] AVG Duty = 5031%(X100)
2413 08:06:17.992407
2414 08:06:17.992863 ==DQM 1 ==
2415 08:06:17.995969 Final DQM duty delay cell = 0
2416 08:06:17.998929 [0] MAX Duty = 5249%(X100), DQS PI = 0
2417 08:06:18.002541 [0] MIN Duty = 4875%(X100), DQS PI = 36
2418 08:06:18.003099 [0] AVG Duty = 5062%(X100)
2419 08:06:18.005602
2420 08:06:18.009093 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2421 08:06:18.009553
2422 08:06:18.012591 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2423 08:06:18.016038 [DutyScan_Calibration_Flow] ====Done====
2424 08:06:18.016613
2425 08:06:18.019395 [DutyScan_Calibration_Flow] k_type=2
2426 08:06:18.035812
2427 08:06:18.036365 ==DQ 0 ==
2428 08:06:18.039550 Final DQ duty delay cell = 0
2429 08:06:18.042476 [0] MAX Duty = 5062%(X100), DQS PI = 20
2430 08:06:18.045673 [0] MIN Duty = 4938%(X100), DQS PI = 46
2431 08:06:18.046230 [0] AVG Duty = 5000%(X100)
2432 08:06:18.046598
2433 08:06:18.049356 ==DQ 1 ==
2434 08:06:18.052485 Final DQ duty delay cell = 0
2435 08:06:18.056406 [0] MAX Duty = 5062%(X100), DQS PI = 2
2436 08:06:18.059172 [0] MIN Duty = 4813%(X100), DQS PI = 36
2437 08:06:18.059731 [0] AVG Duty = 4937%(X100)
2438 08:06:18.060103
2439 08:06:18.062470 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2440 08:06:18.063027
2441 08:06:18.065810 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2442 08:06:18.072517 [DutyScan_Calibration_Flow] ====Done====
2443 08:06:18.075861 nWR fixed to 30
2444 08:06:18.076422 [ModeRegInit_LP4] CH0 RK0
2445 08:06:18.078957 [ModeRegInit_LP4] CH0 RK1
2446 08:06:18.082708 [ModeRegInit_LP4] CH1 RK0
2447 08:06:18.083261 [ModeRegInit_LP4] CH1 RK1
2448 08:06:18.085610 match AC timing 7
2449 08:06:18.088860 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 08:06:18.092619 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 08:06:18.098831 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 08:06:18.102514 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 08:06:18.108900 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 08:06:18.109513 ==
2455 08:06:18.112315 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 08:06:18.115601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 08:06:18.116068 ==
2458 08:06:18.122087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 08:06:18.125443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2460 08:06:18.135197 [CA 0] Center 38 (7~69) winsize 63
2461 08:06:18.139221 [CA 1] Center 38 (8~69) winsize 62
2462 08:06:18.142091 [CA 2] Center 35 (5~66) winsize 62
2463 08:06:18.145783 [CA 3] Center 35 (4~66) winsize 63
2464 08:06:18.149198 [CA 4] Center 34 (4~65) winsize 62
2465 08:06:18.152217 [CA 5] Center 33 (3~63) winsize 61
2466 08:06:18.152787
2467 08:06:18.155641 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2468 08:06:18.156212
2469 08:06:18.158679 [CATrainingPosCal] consider 1 rank data
2470 08:06:18.162422 u2DelayCellTimex100 = 270/100 ps
2471 08:06:18.165745 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2472 08:06:18.168988 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2473 08:06:18.172850 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 08:06:18.179167 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2475 08:06:18.182448 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2476 08:06:18.185856 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2477 08:06:18.186422
2478 08:06:18.189042 CA PerBit enable=1, Macro0, CA PI delay=33
2479 08:06:18.189609
2480 08:06:18.192089 [CBTSetCACLKResult] CA Dly = 33
2481 08:06:18.192551 CS Dly: 6 (0~37)
2482 08:06:18.192920 ==
2483 08:06:18.195787 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 08:06:18.202152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 08:06:18.202731 ==
2486 08:06:18.205787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 08:06:18.212502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2488 08:06:18.221191 [CA 0] Center 39 (8~70) winsize 63
2489 08:06:18.224516 [CA 1] Center 38 (8~69) winsize 62
2490 08:06:18.227779 [CA 2] Center 35 (5~66) winsize 62
2491 08:06:18.231341 [CA 3] Center 35 (5~66) winsize 62
2492 08:06:18.234816 [CA 4] Center 34 (4~65) winsize 62
2493 08:06:18.237609 [CA 5] Center 33 (3~64) winsize 62
2494 08:06:18.238076
2495 08:06:18.241442 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2496 08:06:18.241908
2497 08:06:18.245354 [CATrainingPosCal] consider 2 rank data
2498 08:06:18.247839 u2DelayCellTimex100 = 270/100 ps
2499 08:06:18.251329 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2500 08:06:18.254401 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2501 08:06:18.257932 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 08:06:18.264976 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 08:06:18.268452 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2504 08:06:18.271486 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2505 08:06:18.272056
2506 08:06:18.274743 CA PerBit enable=1, Macro0, CA PI delay=33
2507 08:06:18.275313
2508 08:06:18.278353 [CBTSetCACLKResult] CA Dly = 33
2509 08:06:18.278924 CS Dly: 7 (0~39)
2510 08:06:18.279300
2511 08:06:18.281500 ----->DramcWriteLeveling(PI) begin...
2512 08:06:18.282075 ==
2513 08:06:18.285188 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 08:06:18.291504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 08:06:18.292079 ==
2516 08:06:18.294492 Write leveling (Byte 0): 35 => 35
2517 08:06:18.297759 Write leveling (Byte 1): 31 => 31
2518 08:06:18.301145 DramcWriteLeveling(PI) end<-----
2519 08:06:18.301770
2520 08:06:18.302148 ==
2521 08:06:18.304813 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 08:06:18.308197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 08:06:18.308801 ==
2524 08:06:18.311268 [Gating] SW mode calibration
2525 08:06:18.318098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 08:06:18.321264 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 08:06:18.327908 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2528 08:06:18.331860 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2529 08:06:18.334776 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 08:06:18.341531 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 08:06:18.344637 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 08:06:18.347910 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 08:06:18.354949 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2534 08:06:18.358115 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2535 08:06:18.361028 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2536 08:06:18.367787 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2537 08:06:18.371493 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 08:06:18.374619 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 08:06:18.381117 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 08:06:18.384506 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 08:06:18.388096 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2542 08:06:18.395069 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2543 08:06:18.398236 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2544 08:06:18.401180 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 08:06:18.404795 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 08:06:18.411314 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 08:06:18.414956 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 08:06:18.418062 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 08:06:18.424559 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 08:06:18.427856 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 08:06:18.431555 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 08:06:18.438116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 08:06:18.441347 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 08:06:18.444720 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 08:06:18.452067 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 08:06:18.454627 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 08:06:18.458029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 08:06:18.464853 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 08:06:18.467973 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 08:06:18.471586 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 08:06:18.475067 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 08:06:18.481796 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 08:06:18.485289 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 08:06:18.488323 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 08:06:18.495243 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 08:06:18.498267 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 08:06:18.502006 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2568 08:06:18.505433 Total UI for P1: 0, mck2ui 16
2569 08:06:18.508830 best dqsien dly found for B0: ( 1, 3, 26)
2570 08:06:18.515137 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 08:06:18.515694 Total UI for P1: 0, mck2ui 16
2572 08:06:18.521836 best dqsien dly found for B1: ( 1, 4, 0)
2573 08:06:18.524991 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2574 08:06:18.528924 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2575 08:06:18.529512
2576 08:06:18.531821 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2577 08:06:18.535229 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2578 08:06:18.538381 [Gating] SW calibration Done
2579 08:06:18.538937 ==
2580 08:06:18.541825 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 08:06:18.544719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 08:06:18.545230 ==
2583 08:06:18.548483 RX Vref Scan: 0
2584 08:06:18.549083
2585 08:06:18.549449 RX Vref 0 -> 0, step: 1
2586 08:06:18.549793
2587 08:06:18.551813 RX Delay -40 -> 252, step: 8
2588 08:06:18.555262 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2589 08:06:18.561674 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2590 08:06:18.564898 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2591 08:06:18.568570 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2592 08:06:18.571916 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2593 08:06:18.575336 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2594 08:06:18.578568 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2595 08:06:18.585093 iDelay=208, Bit 7, Center 131 (56 ~ 207) 152
2596 08:06:18.588612 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2597 08:06:18.591916 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2598 08:06:18.595471 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2599 08:06:18.598796 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2600 08:06:18.605121 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2601 08:06:18.609352 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2602 08:06:18.612272 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2603 08:06:18.615687 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2604 08:06:18.616240 ==
2605 08:06:18.618510 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 08:06:18.621793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 08:06:18.625149 ==
2608 08:06:18.625614 DQS Delay:
2609 08:06:18.625981 DQS0 = 0, DQS1 = 0
2610 08:06:18.629078 DQM Delay:
2611 08:06:18.629627 DQM0 = 123, DQM1 = 110
2612 08:06:18.631555 DQ Delay:
2613 08:06:18.635324 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2614 08:06:18.638953 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =131
2615 08:06:18.641895 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2616 08:06:18.645037 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2617 08:06:18.645503
2618 08:06:18.645868
2619 08:06:18.646204 ==
2620 08:06:18.648394 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 08:06:18.651822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 08:06:18.652381 ==
2623 08:06:18.652751
2624 08:06:18.655155
2625 08:06:18.655710 TX Vref Scan disable
2626 08:06:18.658294 == TX Byte 0 ==
2627 08:06:18.661692 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2628 08:06:18.665214 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2629 08:06:18.668509 == TX Byte 1 ==
2630 08:06:18.671795 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2631 08:06:18.675251 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2632 08:06:18.675818 ==
2633 08:06:18.678873 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 08:06:18.685026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 08:06:18.685491 ==
2636 08:06:18.695661 TX Vref=22, minBit 7, minWin=23, winSum=404
2637 08:06:18.698975 TX Vref=24, minBit 5, minWin=23, winSum=410
2638 08:06:18.702253 TX Vref=26, minBit 0, minWin=24, winSum=417
2639 08:06:18.706091 TX Vref=28, minBit 4, minWin=25, winSum=421
2640 08:06:18.708999 TX Vref=30, minBit 7, minWin=24, winSum=420
2641 08:06:18.712272 TX Vref=32, minBit 1, minWin=25, winSum=416
2642 08:06:18.719173 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 28
2643 08:06:18.719737
2644 08:06:18.722247 Final TX Range 1 Vref 28
2645 08:06:18.722710
2646 08:06:18.723073 ==
2647 08:06:18.725687 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 08:06:18.729839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 08:06:18.730396 ==
2650 08:06:18.730766
2651 08:06:18.731102
2652 08:06:18.732448 TX Vref Scan disable
2653 08:06:18.735684 == TX Byte 0 ==
2654 08:06:18.739605 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2655 08:06:18.742446 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2656 08:06:18.745534 == TX Byte 1 ==
2657 08:06:18.748872 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2658 08:06:18.752795 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2659 08:06:18.753407
2660 08:06:18.755743 [DATLAT]
2661 08:06:18.756351 Freq=1200, CH0 RK0
2662 08:06:18.756748
2663 08:06:18.759204 DATLAT Default: 0xd
2664 08:06:18.759739 0, 0xFFFF, sum = 0
2665 08:06:18.762306 1, 0xFFFF, sum = 0
2666 08:06:18.762772 2, 0xFFFF, sum = 0
2667 08:06:18.766440 3, 0xFFFF, sum = 0
2668 08:06:18.767024 4, 0xFFFF, sum = 0
2669 08:06:18.769221 5, 0xFFFF, sum = 0
2670 08:06:18.769783 6, 0xFFFF, sum = 0
2671 08:06:18.772569 7, 0xFFFF, sum = 0
2672 08:06:18.773178 8, 0xFFFF, sum = 0
2673 08:06:18.775794 9, 0xFFFF, sum = 0
2674 08:06:18.776261 10, 0xFFFF, sum = 0
2675 08:06:18.779121 11, 0xFFFF, sum = 0
2676 08:06:18.779600 12, 0x0, sum = 1
2677 08:06:18.782791 13, 0x0, sum = 2
2678 08:06:18.783265 14, 0x0, sum = 3
2679 08:06:18.786161 15, 0x0, sum = 4
2680 08:06:18.786737 best_step = 13
2681 08:06:18.787103
2682 08:06:18.787442 ==
2683 08:06:18.789461 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 08:06:18.796005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 08:06:18.796575 ==
2686 08:06:18.796966 RX Vref Scan: 1
2687 08:06:18.797315
2688 08:06:18.799465 Set Vref Range= 32 -> 127
2689 08:06:18.800032
2690 08:06:18.802390 RX Vref 32 -> 127, step: 1
2691 08:06:18.802794
2692 08:06:18.806212 RX Delay -13 -> 252, step: 4
2693 08:06:18.806682
2694 08:06:18.809514 Set Vref, RX VrefLevel [Byte0]: 32
2695 08:06:18.810006 [Byte1]: 32
2696 08:06:18.814170
2697 08:06:18.814732 Set Vref, RX VrefLevel [Byte0]: 33
2698 08:06:18.817257 [Byte1]: 33
2699 08:06:18.821826
2700 08:06:18.822391 Set Vref, RX VrefLevel [Byte0]: 34
2701 08:06:18.825546 [Byte1]: 34
2702 08:06:18.829780
2703 08:06:18.830360 Set Vref, RX VrefLevel [Byte0]: 35
2704 08:06:18.833548 [Byte1]: 35
2705 08:06:18.837670
2706 08:06:18.838236 Set Vref, RX VrefLevel [Byte0]: 36
2707 08:06:18.840881 [Byte1]: 36
2708 08:06:18.845761
2709 08:06:18.846327 Set Vref, RX VrefLevel [Byte0]: 37
2710 08:06:18.848821 [Byte1]: 37
2711 08:06:18.853299
2712 08:06:18.853853 Set Vref, RX VrefLevel [Byte0]: 38
2713 08:06:18.856700 [Byte1]: 38
2714 08:06:18.861156
2715 08:06:18.861619 Set Vref, RX VrefLevel [Byte0]: 39
2716 08:06:18.864492 [Byte1]: 39
2717 08:06:18.869168
2718 08:06:18.869739 Set Vref, RX VrefLevel [Byte0]: 40
2719 08:06:18.872427 [Byte1]: 40
2720 08:06:18.877311
2721 08:06:18.877874 Set Vref, RX VrefLevel [Byte0]: 41
2722 08:06:18.880574 [Byte1]: 41
2723 08:06:18.885099
2724 08:06:18.885667 Set Vref, RX VrefLevel [Byte0]: 42
2725 08:06:18.888077 [Byte1]: 42
2726 08:06:18.892860
2727 08:06:18.893477 Set Vref, RX VrefLevel [Byte0]: 43
2728 08:06:18.896679 [Byte1]: 43
2729 08:06:18.900818
2730 08:06:18.901426 Set Vref, RX VrefLevel [Byte0]: 44
2731 08:06:18.903952 [Byte1]: 44
2732 08:06:18.909056
2733 08:06:18.909624 Set Vref, RX VrefLevel [Byte0]: 45
2734 08:06:18.912170 [Byte1]: 45
2735 08:06:18.916699
2736 08:06:18.917315 Set Vref, RX VrefLevel [Byte0]: 46
2737 08:06:18.919908 [Byte1]: 46
2738 08:06:18.924334
2739 08:06:18.924813 Set Vref, RX VrefLevel [Byte0]: 47
2740 08:06:18.928000 [Byte1]: 47
2741 08:06:18.932339
2742 08:06:18.932900 Set Vref, RX VrefLevel [Byte0]: 48
2743 08:06:18.935638 [Byte1]: 48
2744 08:06:18.940195
2745 08:06:18.940754 Set Vref, RX VrefLevel [Byte0]: 49
2746 08:06:18.943572 [Byte1]: 49
2747 08:06:18.948106
2748 08:06:18.948666 Set Vref, RX VrefLevel [Byte0]: 50
2749 08:06:18.951662 [Byte1]: 50
2750 08:06:18.955999
2751 08:06:18.956560 Set Vref, RX VrefLevel [Byte0]: 51
2752 08:06:18.959329 [Byte1]: 51
2753 08:06:18.963747
2754 08:06:18.964202 Set Vref, RX VrefLevel [Byte0]: 52
2755 08:06:18.966924 [Byte1]: 52
2756 08:06:18.971635
2757 08:06:18.972204 Set Vref, RX VrefLevel [Byte0]: 53
2758 08:06:18.974839 [Byte1]: 53
2759 08:06:18.979781
2760 08:06:18.980356 Set Vref, RX VrefLevel [Byte0]: 54
2761 08:06:18.983440 [Byte1]: 54
2762 08:06:18.987371
2763 08:06:18.987832 Set Vref, RX VrefLevel [Byte0]: 55
2764 08:06:18.990920 [Byte1]: 55
2765 08:06:18.995359
2766 08:06:18.995941 Set Vref, RX VrefLevel [Byte0]: 56
2767 08:06:18.998585 [Byte1]: 56
2768 08:06:19.003055
2769 08:06:19.003562 Set Vref, RX VrefLevel [Byte0]: 57
2770 08:06:19.006718 [Byte1]: 57
2771 08:06:19.011352
2772 08:06:19.011934 Set Vref, RX VrefLevel [Byte0]: 58
2773 08:06:19.014716 [Byte1]: 58
2774 08:06:19.019086
2775 08:06:19.019649 Set Vref, RX VrefLevel [Byte0]: 59
2776 08:06:19.022277 [Byte1]: 59
2777 08:06:19.026908
2778 08:06:19.027476 Set Vref, RX VrefLevel [Byte0]: 60
2779 08:06:19.030632 [Byte1]: 60
2780 08:06:19.034839
2781 08:06:19.035403 Set Vref, RX VrefLevel [Byte0]: 61
2782 08:06:19.038105 [Byte1]: 61
2783 08:06:19.042656
2784 08:06:19.043222 Set Vref, RX VrefLevel [Byte0]: 62
2785 08:06:19.045817 [Byte1]: 62
2786 08:06:19.050560
2787 08:06:19.051127 Set Vref, RX VrefLevel [Byte0]: 63
2788 08:06:19.054049 [Byte1]: 63
2789 08:06:19.058871
2790 08:06:19.059436 Set Vref, RX VrefLevel [Byte0]: 64
2791 08:06:19.061718 [Byte1]: 64
2792 08:06:19.066508
2793 08:06:19.067075 Set Vref, RX VrefLevel [Byte0]: 65
2794 08:06:19.069570 [Byte1]: 65
2795 08:06:19.074350
2796 08:06:19.074928 Set Vref, RX VrefLevel [Byte0]: 66
2797 08:06:19.077494 [Byte1]: 66
2798 08:06:19.082270
2799 08:06:19.082841 Set Vref, RX VrefLevel [Byte0]: 67
2800 08:06:19.085577 [Byte1]: 67
2801 08:06:19.090086
2802 08:06:19.090649 Set Vref, RX VrefLevel [Byte0]: 68
2803 08:06:19.093474 [Byte1]: 68
2804 08:06:19.097723
2805 08:06:19.098184 Set Vref, RX VrefLevel [Byte0]: 69
2806 08:06:19.101146 [Byte1]: 69
2807 08:06:19.105751
2808 08:06:19.106218 Final RX Vref Byte 0 = 56 to rank0
2809 08:06:19.109289 Final RX Vref Byte 1 = 49 to rank0
2810 08:06:19.113064 Final RX Vref Byte 0 = 56 to rank1
2811 08:06:19.116089 Final RX Vref Byte 1 = 49 to rank1==
2812 08:06:19.119428 Dram Type= 6, Freq= 0, CH_0, rank 0
2813 08:06:19.122816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2814 08:06:19.125904 ==
2815 08:06:19.126454 DQS Delay:
2816 08:06:19.126835 DQS0 = 0, DQS1 = 0
2817 08:06:19.129037 DQM Delay:
2818 08:06:19.129500 DQM0 = 122, DQM1 = 109
2819 08:06:19.132577 DQ Delay:
2820 08:06:19.135906 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2821 08:06:19.139562 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2822 08:06:19.142615 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2823 08:06:19.146059 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2824 08:06:19.146524
2825 08:06:19.146884
2826 08:06:19.152796 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2827 08:06:19.156188 CH0 RK0: MR19=404, MR18=906
2828 08:06:19.162584 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2829 08:06:19.163141
2830 08:06:19.166444 ----->DramcWriteLeveling(PI) begin...
2831 08:06:19.167017 ==
2832 08:06:19.169250 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 08:06:19.173216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 08:06:19.173790 ==
2835 08:06:19.175970 Write leveling (Byte 0): 34 => 34
2836 08:06:19.179442 Write leveling (Byte 1): 31 => 31
2837 08:06:19.183052 DramcWriteLeveling(PI) end<-----
2838 08:06:19.183614
2839 08:06:19.183981 ==
2840 08:06:19.186268 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 08:06:19.189389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 08:06:19.192708 ==
2843 08:06:19.193313 [Gating] SW mode calibration
2844 08:06:19.199494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2845 08:06:19.206213 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2846 08:06:19.209857 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2847 08:06:19.216085 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 08:06:19.220039 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 08:06:19.223226 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 08:06:19.226128 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 08:06:19.233513 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 08:06:19.236803 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 08:06:19.239844 0 15 28 | B1->B0 | 3131 2e2e | 1 1 | (0 1) (0 0)
2854 08:06:19.246457 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2855 08:06:19.250105 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 08:06:19.253474 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 08:06:19.260061 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 08:06:19.263671 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 08:06:19.266677 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 08:06:19.273128 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
2861 08:06:19.276407 1 0 28 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
2862 08:06:19.280470 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 08:06:19.286635 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 08:06:19.290072 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 08:06:19.293599 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 08:06:19.296883 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 08:06:19.303730 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 08:06:19.306782 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 08:06:19.309796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2870 08:06:19.316730 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2871 08:06:19.319986 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 08:06:19.323613 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 08:06:19.330541 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 08:06:19.333839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 08:06:19.336845 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 08:06:19.343939 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 08:06:19.347627 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 08:06:19.350410 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 08:06:19.357055 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 08:06:19.360267 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 08:06:19.363874 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 08:06:19.367357 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 08:06:19.373965 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 08:06:19.377200 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2885 08:06:19.380606 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2886 08:06:19.386987 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2887 08:06:19.390318 Total UI for P1: 0, mck2ui 16
2888 08:06:19.393491 best dqsien dly found for B0: ( 1, 3, 26)
2889 08:06:19.396921 Total UI for P1: 0, mck2ui 16
2890 08:06:19.400241 best dqsien dly found for B1: ( 1, 3, 28)
2891 08:06:19.403862 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2892 08:06:19.407132 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2893 08:06:19.407815
2894 08:06:19.410402 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2895 08:06:19.413671 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2896 08:06:19.416760 [Gating] SW calibration Done
2897 08:06:19.417387 ==
2898 08:06:19.420131 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 08:06:19.423338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 08:06:19.423806 ==
2901 08:06:19.427013 RX Vref Scan: 0
2902 08:06:19.427600
2903 08:06:19.428034 RX Vref 0 -> 0, step: 1
2904 08:06:19.428380
2905 08:06:19.430086 RX Delay -40 -> 252, step: 8
2906 08:06:19.433953 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2907 08:06:19.440503 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2908 08:06:19.443677 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2909 08:06:19.447573 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2910 08:06:19.450399 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2911 08:06:19.453842 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2912 08:06:19.460565 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2913 08:06:19.463938 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2914 08:06:19.467506 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2915 08:06:19.470463 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2916 08:06:19.473862 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2917 08:06:19.480678 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2918 08:06:19.483706 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2919 08:06:19.487157 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2920 08:06:19.490550 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2921 08:06:19.493598 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2922 08:06:19.497019 ==
2923 08:06:19.497585 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 08:06:19.503895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 08:06:19.504491 ==
2926 08:06:19.504868 DQS Delay:
2927 08:06:19.506802 DQS0 = 0, DQS1 = 0
2928 08:06:19.507263 DQM Delay:
2929 08:06:19.510603 DQM0 = 120, DQM1 = 108
2930 08:06:19.511220 DQ Delay:
2931 08:06:19.513757 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2932 08:06:19.516711 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2933 08:06:19.521028 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2934 08:06:19.523785 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2935 08:06:19.524249
2936 08:06:19.524607
2937 08:06:19.524974 ==
2938 08:06:19.527154 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 08:06:19.530323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 08:06:19.534323 ==
2941 08:06:19.534885
2942 08:06:19.535249
2943 08:06:19.535584 TX Vref Scan disable
2944 08:06:19.537215 == TX Byte 0 ==
2945 08:06:19.540435 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2946 08:06:19.543982 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2947 08:06:19.547440 == TX Byte 1 ==
2948 08:06:19.550381 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2949 08:06:19.553830 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2950 08:06:19.557034 ==
2951 08:06:19.560735 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 08:06:19.563667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 08:06:19.564288 ==
2954 08:06:19.575105 TX Vref=22, minBit 1, minWin=24, winSum=409
2955 08:06:19.578237 TX Vref=24, minBit 1, minWin=24, winSum=414
2956 08:06:19.581436 TX Vref=26, minBit 0, minWin=25, winSum=417
2957 08:06:19.585061 TX Vref=28, minBit 1, minWin=25, winSum=420
2958 08:06:19.588224 TX Vref=30, minBit 1, minWin=25, winSum=422
2959 08:06:19.591641 TX Vref=32, minBit 2, minWin=25, winSum=422
2960 08:06:19.598543 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 30
2961 08:06:19.599114
2962 08:06:19.601643 Final TX Range 1 Vref 30
2963 08:06:19.602211
2964 08:06:19.602568 ==
2965 08:06:19.605272 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 08:06:19.608593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 08:06:19.609117 ==
2968 08:06:19.609513
2969 08:06:19.609853
2970 08:06:19.611692 TX Vref Scan disable
2971 08:06:19.615097 == TX Byte 0 ==
2972 08:06:19.618567 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2973 08:06:19.621424 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2974 08:06:19.625085 == TX Byte 1 ==
2975 08:06:19.628253 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2976 08:06:19.631462 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2977 08:06:19.631921
2978 08:06:19.635151 [DATLAT]
2979 08:06:19.635727 Freq=1200, CH0 RK1
2980 08:06:19.636100
2981 08:06:19.638505 DATLAT Default: 0xd
2982 08:06:19.639059 0, 0xFFFF, sum = 0
2983 08:06:19.641532 1, 0xFFFF, sum = 0
2984 08:06:19.641996 2, 0xFFFF, sum = 0
2985 08:06:19.645074 3, 0xFFFF, sum = 0
2986 08:06:19.645641 4, 0xFFFF, sum = 0
2987 08:06:19.648618 5, 0xFFFF, sum = 0
2988 08:06:19.649229 6, 0xFFFF, sum = 0
2989 08:06:19.652085 7, 0xFFFF, sum = 0
2990 08:06:19.652645 8, 0xFFFF, sum = 0
2991 08:06:19.655055 9, 0xFFFF, sum = 0
2992 08:06:19.655550 10, 0xFFFF, sum = 0
2993 08:06:19.658406 11, 0xFFFF, sum = 0
2994 08:06:19.658967 12, 0x0, sum = 1
2995 08:06:19.661732 13, 0x0, sum = 2
2996 08:06:19.662205 14, 0x0, sum = 3
2997 08:06:19.664765 15, 0x0, sum = 4
2998 08:06:19.665322 best_step = 13
2999 08:06:19.665689
3000 08:06:19.666029 ==
3001 08:06:19.668702 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 08:06:19.675265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 08:06:19.675822 ==
3004 08:06:19.676195 RX Vref Scan: 0
3005 08:06:19.676539
3006 08:06:19.678403 RX Vref 0 -> 0, step: 1
3007 08:06:19.678951
3008 08:06:19.681851 RX Delay -21 -> 252, step: 4
3009 08:06:19.685289 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3010 08:06:19.688590 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3011 08:06:19.695327 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3012 08:06:19.698732 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3013 08:06:19.702267 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3014 08:06:19.705328 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3015 08:06:19.709085 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3016 08:06:19.711667 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3017 08:06:19.718949 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3018 08:06:19.721811 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3019 08:06:19.725368 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3020 08:06:19.728567 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3021 08:06:19.732319 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3022 08:06:19.738767 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3023 08:06:19.742756 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3024 08:06:19.745428 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3025 08:06:19.745890 ==
3026 08:06:19.749047 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 08:06:19.752118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 08:06:19.752675 ==
3029 08:06:19.755579 DQS Delay:
3030 08:06:19.756134 DQS0 = 0, DQS1 = 0
3031 08:06:19.759143 DQM Delay:
3032 08:06:19.759698 DQM0 = 119, DQM1 = 107
3033 08:06:19.760063 DQ Delay:
3034 08:06:19.766007 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3035 08:06:19.769307 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3036 08:06:19.772319 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3037 08:06:19.776019 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3038 08:06:19.776579
3039 08:06:19.776974
3040 08:06:19.782998 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3041 08:06:19.785680 CH0 RK1: MR19=403, MR18=EF5
3042 08:06:19.792493 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3043 08:06:19.795946 [RxdqsGatingPostProcess] freq 1200
3044 08:06:19.799281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3045 08:06:19.802308 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 08:06:19.806060 best DQS1 dly(2T, 0.5T) = (0, 12)
3047 08:06:19.809286 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 08:06:19.812448 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3049 08:06:19.815700 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 08:06:19.819348 best DQS1 dly(2T, 0.5T) = (0, 11)
3051 08:06:19.822597 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 08:06:19.825723 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3053 08:06:19.829075 Pre-setting of DQS Precalculation
3054 08:06:19.832478 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3055 08:06:19.833130 ==
3056 08:06:19.835768 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 08:06:19.839499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 08:06:19.842265 ==
3059 08:06:19.845579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3060 08:06:19.852426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3061 08:06:19.860901 [CA 0] Center 37 (7~68) winsize 62
3062 08:06:19.864356 [CA 1] Center 37 (7~68) winsize 62
3063 08:06:19.867783 [CA 2] Center 35 (5~65) winsize 61
3064 08:06:19.871040 [CA 3] Center 34 (4~65) winsize 62
3065 08:06:19.874235 [CA 4] Center 34 (3~65) winsize 63
3066 08:06:19.877710 [CA 5] Center 33 (3~64) winsize 62
3067 08:06:19.878267
3068 08:06:19.880972 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3069 08:06:19.881534
3070 08:06:19.884412 [CATrainingPosCal] consider 1 rank data
3071 08:06:19.887645 u2DelayCellTimex100 = 270/100 ps
3072 08:06:19.890850 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 08:06:19.894191 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 08:06:19.901094 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3075 08:06:19.904392 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3076 08:06:19.907596 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3077 08:06:19.910735 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3078 08:06:19.911219
3079 08:06:19.914005 CA PerBit enable=1, Macro0, CA PI delay=33
3080 08:06:19.914575
3081 08:06:19.917368 [CBTSetCACLKResult] CA Dly = 33
3082 08:06:19.917939 CS Dly: 5 (0~36)
3083 08:06:19.918316 ==
3084 08:06:19.920496 Dram Type= 6, Freq= 0, CH_1, rank 1
3085 08:06:19.927391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 08:06:19.928002 ==
3087 08:06:19.930942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 08:06:19.937375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3089 08:06:19.946600 [CA 0] Center 38 (8~68) winsize 61
3090 08:06:19.949748 [CA 1] Center 38 (7~69) winsize 63
3091 08:06:19.953267 [CA 2] Center 35 (5~66) winsize 62
3092 08:06:19.956265 [CA 3] Center 35 (5~65) winsize 61
3093 08:06:19.959768 [CA 4] Center 34 (5~64) winsize 60
3094 08:06:19.962890 [CA 5] Center 34 (4~64) winsize 61
3095 08:06:19.963352
3096 08:06:19.966541 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3097 08:06:19.967105
3098 08:06:19.969707 [CATrainingPosCal] consider 2 rank data
3099 08:06:19.973171 u2DelayCellTimex100 = 270/100 ps
3100 08:06:19.976555 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3101 08:06:19.979976 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3102 08:06:19.986631 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3103 08:06:19.989628 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3104 08:06:19.993185 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3105 08:06:19.996360 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3106 08:06:19.996919
3107 08:06:19.999891 CA PerBit enable=1, Macro0, CA PI delay=34
3108 08:06:20.000453
3109 08:06:20.003316 [CBTSetCACLKResult] CA Dly = 34
3110 08:06:20.003881 CS Dly: 6 (0~39)
3111 08:06:20.004255
3112 08:06:20.006426 ----->DramcWriteLeveling(PI) begin...
3113 08:06:20.006994 ==
3114 08:06:20.009908 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 08:06:20.016889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 08:06:20.017501 ==
3117 08:06:20.019924 Write leveling (Byte 0): 26 => 26
3118 08:06:20.023262 Write leveling (Byte 1): 28 => 28
3119 08:06:20.023842 DramcWriteLeveling(PI) end<-----
3120 08:06:20.026556
3121 08:06:20.027022 ==
3122 08:06:20.029426 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 08:06:20.033154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 08:06:20.033731 ==
3125 08:06:20.036231 [Gating] SW mode calibration
3126 08:06:20.043511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3127 08:06:20.046427 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3128 08:06:20.053112 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 08:06:20.056332 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 08:06:20.059785 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 08:06:20.066313 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 08:06:20.069883 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 08:06:20.073170 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3134 08:06:20.080021 0 15 24 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (1 0)
3135 08:06:20.083213 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 08:06:20.086890 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 08:06:20.093190 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 08:06:20.096544 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 08:06:20.099983 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 08:06:20.106664 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 08:06:20.110070 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3142 08:06:20.113099 1 0 24 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
3143 08:06:20.116779 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 08:06:20.123428 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 08:06:20.126755 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 08:06:20.130040 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 08:06:20.136962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 08:06:20.140246 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 08:06:20.143657 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3150 08:06:20.149955 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3151 08:06:20.153539 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3152 08:06:20.156867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 08:06:20.163573 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 08:06:20.166672 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 08:06:20.170344 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 08:06:20.173708 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 08:06:20.180691 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 08:06:20.184271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 08:06:20.187051 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 08:06:20.193816 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 08:06:20.197288 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 08:06:20.200556 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 08:06:20.207154 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 08:06:20.211001 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 08:06:20.213768 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 08:06:20.220604 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 08:06:20.223896 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3168 08:06:20.227258 Total UI for P1: 0, mck2ui 16
3169 08:06:20.230777 best dqsien dly found for B0: ( 1, 3, 24)
3170 08:06:20.234024 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 08:06:20.237676 Total UI for P1: 0, mck2ui 16
3172 08:06:20.240719 best dqsien dly found for B1: ( 1, 3, 26)
3173 08:06:20.243956 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3174 08:06:20.247431 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3175 08:06:20.248149
3176 08:06:20.250675 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3177 08:06:20.257361 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3178 08:06:20.257915 [Gating] SW calibration Done
3179 08:06:20.258289 ==
3180 08:06:20.260459 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 08:06:20.267808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 08:06:20.268367 ==
3183 08:06:20.268737 RX Vref Scan: 0
3184 08:06:20.269102
3185 08:06:20.270807 RX Vref 0 -> 0, step: 1
3186 08:06:20.271267
3187 08:06:20.274068 RX Delay -40 -> 252, step: 8
3188 08:06:20.277358 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3189 08:06:20.280467 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3190 08:06:20.284257 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3191 08:06:20.287370 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3192 08:06:20.293842 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3193 08:06:20.297238 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3194 08:06:20.300513 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3195 08:06:20.304007 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3196 08:06:20.307462 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3197 08:06:20.314255 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3198 08:06:20.317554 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3199 08:06:20.320864 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3200 08:06:20.324101 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3201 08:06:20.327577 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3202 08:06:20.334296 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3203 08:06:20.337675 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3204 08:06:20.338233 ==
3205 08:06:20.341092 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 08:06:20.344548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 08:06:20.345136 ==
3208 08:06:20.345511 DQS Delay:
3209 08:06:20.347705 DQS0 = 0, DQS1 = 0
3210 08:06:20.348263 DQM Delay:
3211 08:06:20.351044 DQM0 = 120, DQM1 = 112
3212 08:06:20.351596 DQ Delay:
3213 08:06:20.354285 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3214 08:06:20.357489 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3215 08:06:20.361037 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3216 08:06:20.364227 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3217 08:06:20.364695
3218 08:06:20.368118
3219 08:06:20.368841 ==
3220 08:06:20.371162 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 08:06:20.374664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 08:06:20.375226 ==
3223 08:06:20.375598
3224 08:06:20.375941
3225 08:06:20.377900 TX Vref Scan disable
3226 08:06:20.378402 == TX Byte 0 ==
3227 08:06:20.381178 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3228 08:06:20.387783 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3229 08:06:20.388353 == TX Byte 1 ==
3230 08:06:20.391386 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3231 08:06:20.398024 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3232 08:06:20.398574 ==
3233 08:06:20.401384 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 08:06:20.404695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 08:06:20.405298 ==
3236 08:06:20.416382 TX Vref=22, minBit 10, minWin=24, winSum=409
3237 08:06:20.419664 TX Vref=24, minBit 1, minWin=25, winSum=411
3238 08:06:20.423058 TX Vref=26, minBit 9, minWin=25, winSum=422
3239 08:06:20.426212 TX Vref=28, minBit 3, minWin=25, winSum=422
3240 08:06:20.429476 TX Vref=30, minBit 3, minWin=26, winSum=428
3241 08:06:20.436413 TX Vref=32, minBit 10, minWin=25, winSum=425
3242 08:06:20.439733 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 30
3243 08:06:20.440291
3244 08:06:20.443269 Final TX Range 1 Vref 30
3245 08:06:20.443824
3246 08:06:20.444194 ==
3247 08:06:20.446401 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 08:06:20.449637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 08:06:20.450198 ==
3250 08:06:20.450570
3251 08:06:20.453281
3252 08:06:20.453833 TX Vref Scan disable
3253 08:06:20.456350 == TX Byte 0 ==
3254 08:06:20.459517 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3255 08:06:20.462824 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3256 08:06:20.466297 == TX Byte 1 ==
3257 08:06:20.469641 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3258 08:06:20.473148 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3259 08:06:20.473704
3260 08:06:20.476192 [DATLAT]
3261 08:06:20.476775 Freq=1200, CH1 RK0
3262 08:06:20.477191
3263 08:06:20.479465 DATLAT Default: 0xd
3264 08:06:20.480017 0, 0xFFFF, sum = 0
3265 08:06:20.482482 1, 0xFFFF, sum = 0
3266 08:06:20.482954 2, 0xFFFF, sum = 0
3267 08:06:20.486377 3, 0xFFFF, sum = 0
3268 08:06:20.486945 4, 0xFFFF, sum = 0
3269 08:06:20.489761 5, 0xFFFF, sum = 0
3270 08:06:20.492798 6, 0xFFFF, sum = 0
3271 08:06:20.493402 7, 0xFFFF, sum = 0
3272 08:06:20.496254 8, 0xFFFF, sum = 0
3273 08:06:20.496810 9, 0xFFFF, sum = 0
3274 08:06:20.499506 10, 0xFFFF, sum = 0
3275 08:06:20.500216 11, 0xFFFF, sum = 0
3276 08:06:20.503212 12, 0x0, sum = 1
3277 08:06:20.503773 13, 0x0, sum = 2
3278 08:06:20.506432 14, 0x0, sum = 3
3279 08:06:20.506994 15, 0x0, sum = 4
3280 08:06:20.507369 best_step = 13
3281 08:06:20.507709
3282 08:06:20.509515 ==
3283 08:06:20.512523 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 08:06:20.516428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 08:06:20.517018 ==
3286 08:06:20.517394 RX Vref Scan: 1
3287 08:06:20.517741
3288 08:06:20.519523 Set Vref Range= 32 -> 127
3289 08:06:20.520079
3290 08:06:20.522840 RX Vref 32 -> 127, step: 1
3291 08:06:20.523397
3292 08:06:20.526064 RX Delay -13 -> 252, step: 4
3293 08:06:20.526520
3294 08:06:20.529513 Set Vref, RX VrefLevel [Byte0]: 32
3295 08:06:20.532650 [Byte1]: 32
3296 08:06:20.533128
3297 08:06:20.536374 Set Vref, RX VrefLevel [Byte0]: 33
3298 08:06:20.539291 [Byte1]: 33
3299 08:06:20.539744
3300 08:06:20.542807 Set Vref, RX VrefLevel [Byte0]: 34
3301 08:06:20.545843 [Byte1]: 34
3302 08:06:20.550747
3303 08:06:20.551287 Set Vref, RX VrefLevel [Byte0]: 35
3304 08:06:20.553776 [Byte1]: 35
3305 08:06:20.558294
3306 08:06:20.558837 Set Vref, RX VrefLevel [Byte0]: 36
3307 08:06:20.561496 [Byte1]: 36
3308 08:06:20.565993
3309 08:06:20.566533 Set Vref, RX VrefLevel [Byte0]: 37
3310 08:06:20.569462 [Byte1]: 37
3311 08:06:20.574162
3312 08:06:20.574823 Set Vref, RX VrefLevel [Byte0]: 38
3313 08:06:20.577309 [Byte1]: 38
3314 08:06:20.581958
3315 08:06:20.582647 Set Vref, RX VrefLevel [Byte0]: 39
3316 08:06:20.585207 [Byte1]: 39
3317 08:06:20.589970
3318 08:06:20.590648 Set Vref, RX VrefLevel [Byte0]: 40
3319 08:06:20.593226 [Byte1]: 40
3320 08:06:20.597532
3321 08:06:20.597982 Set Vref, RX VrefLevel [Byte0]: 41
3322 08:06:20.600861 [Byte1]: 41
3323 08:06:20.605421
3324 08:06:20.605956 Set Vref, RX VrefLevel [Byte0]: 42
3325 08:06:20.608771 [Byte1]: 42
3326 08:06:20.613157
3327 08:06:20.613658 Set Vref, RX VrefLevel [Byte0]: 43
3328 08:06:20.616834 [Byte1]: 43
3329 08:06:20.621065
3330 08:06:20.621520 Set Vref, RX VrefLevel [Byte0]: 44
3331 08:06:20.624811 [Byte1]: 44
3332 08:06:20.629273
3333 08:06:20.629897 Set Vref, RX VrefLevel [Byte0]: 45
3334 08:06:20.632504 [Byte1]: 45
3335 08:06:20.637298
3336 08:06:20.637836 Set Vref, RX VrefLevel [Byte0]: 46
3337 08:06:20.640525 [Byte1]: 46
3338 08:06:20.645060
3339 08:06:20.645597 Set Vref, RX VrefLevel [Byte0]: 47
3340 08:06:20.648398 [Byte1]: 47
3341 08:06:20.653068
3342 08:06:20.653600 Set Vref, RX VrefLevel [Byte0]: 48
3343 08:06:20.656425 [Byte1]: 48
3344 08:06:20.661077
3345 08:06:20.661613 Set Vref, RX VrefLevel [Byte0]: 49
3346 08:06:20.663756 [Byte1]: 49
3347 08:06:20.668850
3348 08:06:20.669428 Set Vref, RX VrefLevel [Byte0]: 50
3349 08:06:20.671913 [Byte1]: 50
3350 08:06:20.676500
3351 08:06:20.677082 Set Vref, RX VrefLevel [Byte0]: 51
3352 08:06:20.679875 [Byte1]: 51
3353 08:06:20.684560
3354 08:06:20.685178 Set Vref, RX VrefLevel [Byte0]: 52
3355 08:06:20.687924 [Byte1]: 52
3356 08:06:20.692362
3357 08:06:20.692901 Set Vref, RX VrefLevel [Byte0]: 53
3358 08:06:20.695704 [Byte1]: 53
3359 08:06:20.700175
3360 08:06:20.700635 Set Vref, RX VrefLevel [Byte0]: 54
3361 08:06:20.703553 [Byte1]: 54
3362 08:06:20.707990
3363 08:06:20.708547 Set Vref, RX VrefLevel [Byte0]: 55
3364 08:06:20.711726 [Byte1]: 55
3365 08:06:20.715940
3366 08:06:20.716405 Set Vref, RX VrefLevel [Byte0]: 56
3367 08:06:20.719435 [Byte1]: 56
3368 08:06:20.724109
3369 08:06:20.724664 Set Vref, RX VrefLevel [Byte0]: 57
3370 08:06:20.727278 [Byte1]: 57
3371 08:06:20.731923
3372 08:06:20.732475 Set Vref, RX VrefLevel [Byte0]: 58
3373 08:06:20.735729 [Byte1]: 58
3374 08:06:20.739605
3375 08:06:20.740157 Set Vref, RX VrefLevel [Byte0]: 59
3376 08:06:20.743165 [Byte1]: 59
3377 08:06:20.747858
3378 08:06:20.748417 Set Vref, RX VrefLevel [Byte0]: 60
3379 08:06:20.750963 [Byte1]: 60
3380 08:06:20.755839
3381 08:06:20.756394 Set Vref, RX VrefLevel [Byte0]: 61
3382 08:06:20.758772 [Byte1]: 61
3383 08:06:20.763164
3384 08:06:20.763623 Set Vref, RX VrefLevel [Byte0]: 62
3385 08:06:20.766932 [Byte1]: 62
3386 08:06:20.771461
3387 08:06:20.772005 Set Vref, RX VrefLevel [Byte0]: 63
3388 08:06:20.774530 [Byte1]: 63
3389 08:06:20.779392
3390 08:06:20.779940 Set Vref, RX VrefLevel [Byte0]: 64
3391 08:06:20.782316 [Byte1]: 64
3392 08:06:20.787318
3393 08:06:20.787868 Set Vref, RX VrefLevel [Byte0]: 65
3394 08:06:20.790755 [Byte1]: 65
3395 08:06:20.794795
3396 08:06:20.795484 Set Vref, RX VrefLevel [Byte0]: 66
3397 08:06:20.798184 [Byte1]: 66
3398 08:06:20.802796
3399 08:06:20.803385 Set Vref, RX VrefLevel [Byte0]: 67
3400 08:06:20.805874 [Byte1]: 67
3401 08:06:20.810441
3402 08:06:20.811094 Final RX Vref Byte 0 = 51 to rank0
3403 08:06:20.813862 Final RX Vref Byte 1 = 59 to rank0
3404 08:06:20.817099 Final RX Vref Byte 0 = 51 to rank1
3405 08:06:20.820461 Final RX Vref Byte 1 = 59 to rank1==
3406 08:06:20.823978 Dram Type= 6, Freq= 0, CH_1, rank 0
3407 08:06:20.830982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 08:06:20.831519 ==
3409 08:06:20.832007 DQS Delay:
3410 08:06:20.832430 DQS0 = 0, DQS1 = 0
3411 08:06:20.833815 DQM Delay:
3412 08:06:20.834057 DQM0 = 119, DQM1 = 113
3413 08:06:20.837151 DQ Delay:
3414 08:06:20.840279 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3415 08:06:20.843799 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3416 08:06:20.847041 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =106
3417 08:06:20.850471 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =122
3418 08:06:20.850790
3419 08:06:20.851061
3420 08:06:20.856989 [DQSOSCAuto] RK0, (LSB)MR18= 0x418, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3421 08:06:20.860280 CH1 RK0: MR19=404, MR18=418
3422 08:06:20.867237 CH1_RK0: MR19=0x404, MR18=0x418, DQSOSC=400, MR23=63, INC=40, DEC=27
3423 08:06:20.867624
3424 08:06:20.870524 ----->DramcWriteLeveling(PI) begin...
3425 08:06:20.871022 ==
3426 08:06:20.874221 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 08:06:20.877240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 08:06:20.878016 ==
3429 08:06:20.880974 Write leveling (Byte 0): 23 => 23
3430 08:06:20.883842 Write leveling (Byte 1): 30 => 30
3431 08:06:20.887247 DramcWriteLeveling(PI) end<-----
3432 08:06:20.887617
3433 08:06:20.887900 ==
3434 08:06:20.890463 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 08:06:20.893790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 08:06:20.897033 ==
3437 08:06:20.897279 [Gating] SW mode calibration
3438 08:06:20.903847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3439 08:06:20.910456 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3440 08:06:20.913897 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 08:06:20.920544 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 08:06:20.924353 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 08:06:20.927081 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 08:06:20.933976 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 08:06:20.937566 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 08:06:20.940328 0 15 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 0)
3447 08:06:20.947445 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (0 0)
3448 08:06:20.950412 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 08:06:20.953874 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 08:06:20.960342 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 08:06:20.963774 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 08:06:20.967234 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 08:06:20.970381 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3454 08:06:20.977243 1 0 24 | B1->B0 | 3737 2828 | 0 0 | (0 0) (0 0)
3455 08:06:20.980614 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3456 08:06:20.984052 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 08:06:20.990945 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 08:06:20.994206 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 08:06:20.997248 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 08:06:21.004656 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 08:06:21.007673 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 08:06:21.010923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3463 08:06:21.017957 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3464 08:06:21.021226 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 08:06:21.024511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 08:06:21.030916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 08:06:21.034491 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 08:06:21.037955 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 08:06:21.041840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 08:06:21.048094 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 08:06:21.051819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 08:06:21.054705 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 08:06:21.061390 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 08:06:21.064497 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 08:06:21.068419 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 08:06:21.074461 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 08:06:21.078080 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 08:06:21.081439 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3479 08:06:21.087792 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3480 08:06:21.088353 Total UI for P1: 0, mck2ui 16
3481 08:06:21.094632 best dqsien dly found for B1: ( 1, 3, 24)
3482 08:06:21.097829 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 08:06:21.101425 Total UI for P1: 0, mck2ui 16
3484 08:06:21.104446 best dqsien dly found for B0: ( 1, 3, 26)
3485 08:06:21.107727 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3486 08:06:21.111378 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3487 08:06:21.111979
3488 08:06:21.114056 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3489 08:06:21.117601 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3490 08:06:21.121014 [Gating] SW calibration Done
3491 08:06:21.121581 ==
3492 08:06:21.124481 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 08:06:21.127709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 08:06:21.131007 ==
3495 08:06:21.131470 RX Vref Scan: 0
3496 08:06:21.131928
3497 08:06:21.134330 RX Vref 0 -> 0, step: 1
3498 08:06:21.134935
3499 08:06:21.135309 RX Delay -40 -> 252, step: 8
3500 08:06:21.141358 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3501 08:06:21.144548 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3502 08:06:21.147905 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3503 08:06:21.151354 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3504 08:06:21.154570 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3505 08:06:21.161539 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3506 08:06:21.164484 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3507 08:06:21.168036 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3508 08:06:21.171299 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3509 08:06:21.174322 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3510 08:06:21.180858 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3511 08:06:21.184262 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3512 08:06:21.187655 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3513 08:06:21.190805 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3514 08:06:21.194768 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3515 08:06:21.201084 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3516 08:06:21.201633 ==
3517 08:06:21.204484 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 08:06:21.207827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 08:06:21.208399 ==
3520 08:06:21.208771 DQS Delay:
3521 08:06:21.211314 DQS0 = 0, DQS1 = 0
3522 08:06:21.211864 DQM Delay:
3523 08:06:21.214359 DQM0 = 120, DQM1 = 113
3524 08:06:21.214882 DQ Delay:
3525 08:06:21.217624 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3526 08:06:21.220840 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3527 08:06:21.224314 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3528 08:06:21.227549 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3529 08:06:21.228009
3530 08:06:21.230930
3531 08:06:21.231378 ==
3532 08:06:21.234349 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 08:06:21.237753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 08:06:21.238211 ==
3535 08:06:21.238615
3536 08:06:21.238954
3537 08:06:21.240647 TX Vref Scan disable
3538 08:06:21.241137 == TX Byte 0 ==
3539 08:06:21.247476 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3540 08:06:21.250953 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3541 08:06:21.251502 == TX Byte 1 ==
3542 08:06:21.257411 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3543 08:06:21.261062 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3544 08:06:21.261613 ==
3545 08:06:21.264043 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 08:06:21.267558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 08:06:21.268108 ==
3548 08:06:21.280159 TX Vref=22, minBit 1, minWin=25, winSum=418
3549 08:06:21.283896 TX Vref=24, minBit 1, minWin=26, winSum=423
3550 08:06:21.287037 TX Vref=26, minBit 1, minWin=26, winSum=425
3551 08:06:21.290218 TX Vref=28, minBit 8, minWin=25, winSum=426
3552 08:06:21.293445 TX Vref=30, minBit 1, minWin=26, winSum=431
3553 08:06:21.300515 TX Vref=32, minBit 7, minWin=26, winSum=431
3554 08:06:21.303551 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3555 08:06:21.304094
3556 08:06:21.306757 Final TX Range 1 Vref 30
3557 08:06:21.307309
3558 08:06:21.307673 ==
3559 08:06:21.310091 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 08:06:21.313326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 08:06:21.313880 ==
3562 08:06:21.316279
3563 08:06:21.316749
3564 08:06:21.317141 TX Vref Scan disable
3565 08:06:21.320118 == TX Byte 0 ==
3566 08:06:21.323043 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3567 08:06:21.329930 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3568 08:06:21.330596 == TX Byte 1 ==
3569 08:06:21.333037 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3570 08:06:21.336772 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3571 08:06:21.339826
3572 08:06:21.340383 [DATLAT]
3573 08:06:21.340750 Freq=1200, CH1 RK1
3574 08:06:21.341136
3575 08:06:21.343160 DATLAT Default: 0xd
3576 08:06:21.343627 0, 0xFFFF, sum = 0
3577 08:06:21.346462 1, 0xFFFF, sum = 0
3578 08:06:21.346932 2, 0xFFFF, sum = 0
3579 08:06:21.349855 3, 0xFFFF, sum = 0
3580 08:06:21.353310 4, 0xFFFF, sum = 0
3581 08:06:21.353888 5, 0xFFFF, sum = 0
3582 08:06:21.356664 6, 0xFFFF, sum = 0
3583 08:06:21.357238 7, 0xFFFF, sum = 0
3584 08:06:21.359880 8, 0xFFFF, sum = 0
3585 08:06:21.360437 9, 0xFFFF, sum = 0
3586 08:06:21.363423 10, 0xFFFF, sum = 0
3587 08:06:21.363891 11, 0xFFFF, sum = 0
3588 08:06:21.366250 12, 0x0, sum = 1
3589 08:06:21.366714 13, 0x0, sum = 2
3590 08:06:21.369726 14, 0x0, sum = 3
3591 08:06:21.370290 15, 0x0, sum = 4
3592 08:06:21.373233 best_step = 13
3593 08:06:21.373789
3594 08:06:21.374149 ==
3595 08:06:21.376647 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 08:06:21.379802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 08:06:21.380354 ==
3598 08:06:21.380727 RX Vref Scan: 0
3599 08:06:21.381120
3600 08:06:21.383021 RX Vref 0 -> 0, step: 1
3601 08:06:21.383580
3602 08:06:21.386348 RX Delay -13 -> 252, step: 4
3603 08:06:21.389896 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3604 08:06:21.396332 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3605 08:06:21.399450 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3606 08:06:21.403517 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3607 08:06:21.406290 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3608 08:06:21.409932 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3609 08:06:21.416101 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3610 08:06:21.419613 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3611 08:06:21.422846 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3612 08:06:21.426746 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3613 08:06:21.429582 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3614 08:06:21.436254 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3615 08:06:21.439618 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3616 08:06:21.442694 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3617 08:06:21.446145 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3618 08:06:21.449317 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3619 08:06:21.453025 ==
3620 08:06:21.455816 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 08:06:21.459491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 08:06:21.460048 ==
3623 08:06:21.460417 DQS Delay:
3624 08:06:21.462659 DQS0 = 0, DQS1 = 0
3625 08:06:21.463227 DQM Delay:
3626 08:06:21.466157 DQM0 = 119, DQM1 = 114
3627 08:06:21.466615 DQ Delay:
3628 08:06:21.469528 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3629 08:06:21.472530 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3630 08:06:21.476164 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3631 08:06:21.479545 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3632 08:06:21.480101
3633 08:06:21.480464
3634 08:06:21.489322 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3635 08:06:21.492856 CH1 RK1: MR19=403, MR18=CF1
3636 08:06:21.496092 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3637 08:06:21.499200 [RxdqsGatingPostProcess] freq 1200
3638 08:06:21.506123 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3639 08:06:21.509596 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 08:06:21.512495 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 08:06:21.515672 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 08:06:21.518900 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 08:06:21.522561 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 08:06:21.525706 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 08:06:21.529268 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 08:06:21.532298 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 08:06:21.532760 Pre-setting of DQS Precalculation
3648 08:06:21.539203 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3649 08:06:21.545751 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3650 08:06:21.552503 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3651 08:06:21.553114
3652 08:06:21.553483
3653 08:06:21.555889 [Calibration Summary] 2400 Mbps
3654 08:06:21.559285 CH 0, Rank 0
3655 08:06:21.559839 SW Impedance : PASS
3656 08:06:21.562330 DUTY Scan : NO K
3657 08:06:21.565662 ZQ Calibration : PASS
3658 08:06:21.566190 Jitter Meter : NO K
3659 08:06:21.569037 CBT Training : PASS
3660 08:06:21.572295 Write leveling : PASS
3661 08:06:21.572847 RX DQS gating : PASS
3662 08:06:21.575796 RX DQ/DQS(RDDQC) : PASS
3663 08:06:21.576357 TX DQ/DQS : PASS
3664 08:06:21.579264 RX DATLAT : PASS
3665 08:06:21.582491 RX DQ/DQS(Engine): PASS
3666 08:06:21.583090 TX OE : NO K
3667 08:06:21.585633 All Pass.
3668 08:06:21.586089
3669 08:06:21.586450 CH 0, Rank 1
3670 08:06:21.589222 SW Impedance : PASS
3671 08:06:21.589775 DUTY Scan : NO K
3672 08:06:21.592481 ZQ Calibration : PASS
3673 08:06:21.595959 Jitter Meter : NO K
3674 08:06:21.596511 CBT Training : PASS
3675 08:06:21.599002 Write leveling : PASS
3676 08:06:21.602558 RX DQS gating : PASS
3677 08:06:21.603110 RX DQ/DQS(RDDQC) : PASS
3678 08:06:21.605860 TX DQ/DQS : PASS
3679 08:06:21.609210 RX DATLAT : PASS
3680 08:06:21.609768 RX DQ/DQS(Engine): PASS
3681 08:06:21.612714 TX OE : NO K
3682 08:06:21.613297 All Pass.
3683 08:06:21.613669
3684 08:06:21.615821 CH 1, Rank 0
3685 08:06:21.616281 SW Impedance : PASS
3686 08:06:21.618978 DUTY Scan : NO K
3687 08:06:21.622668 ZQ Calibration : PASS
3688 08:06:21.623225 Jitter Meter : NO K
3689 08:06:21.625843 CBT Training : PASS
3690 08:06:21.626400 Write leveling : PASS
3691 08:06:21.628860 RX DQS gating : PASS
3692 08:06:21.632229 RX DQ/DQS(RDDQC) : PASS
3693 08:06:21.632691 TX DQ/DQS : PASS
3694 08:06:21.635923 RX DATLAT : PASS
3695 08:06:21.639589 RX DQ/DQS(Engine): PASS
3696 08:06:21.640147 TX OE : NO K
3697 08:06:21.642561 All Pass.
3698 08:06:21.643114
3699 08:06:21.643479 CH 1, Rank 1
3700 08:06:21.645653 SW Impedance : PASS
3701 08:06:21.646116 DUTY Scan : NO K
3702 08:06:21.648694 ZQ Calibration : PASS
3703 08:06:21.652471 Jitter Meter : NO K
3704 08:06:21.653067 CBT Training : PASS
3705 08:06:21.655551 Write leveling : PASS
3706 08:06:21.658775 RX DQS gating : PASS
3707 08:06:21.659340 RX DQ/DQS(RDDQC) : PASS
3708 08:06:21.662332 TX DQ/DQS : PASS
3709 08:06:21.665198 RX DATLAT : PASS
3710 08:06:21.665667 RX DQ/DQS(Engine): PASS
3711 08:06:21.668618 TX OE : NO K
3712 08:06:21.669120 All Pass.
3713 08:06:21.669486
3714 08:06:21.672120 DramC Write-DBI off
3715 08:06:21.675051 PER_BANK_REFRESH: Hybrid Mode
3716 08:06:21.675618 TX_TRACKING: ON
3717 08:06:21.685538 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3718 08:06:21.688814 [FAST_K] Save calibration result to emmc
3719 08:06:21.691848 dramc_set_vcore_voltage set vcore to 650000
3720 08:06:21.695446 Read voltage for 600, 5
3721 08:06:21.695999 Vio18 = 0
3722 08:06:21.696361 Vcore = 650000
3723 08:06:21.698793 Vdram = 0
3724 08:06:21.699246 Vddq = 0
3725 08:06:21.699603 Vmddr = 0
3726 08:06:21.705365 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3727 08:06:21.708764 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3728 08:06:21.712239 MEM_TYPE=3, freq_sel=19
3729 08:06:21.714987 sv_algorithm_assistance_LP4_1600
3730 08:06:21.718778 ============ PULL DRAM RESETB DOWN ============
3731 08:06:21.721577 ========== PULL DRAM RESETB DOWN end =========
3732 08:06:21.728651 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 08:06:21.731611 ===================================
3734 08:06:21.732089 LPDDR4 DRAM CONFIGURATION
3735 08:06:21.734817 ===================================
3736 08:06:21.738407 EX_ROW_EN[0] = 0x0
3737 08:06:21.741831 EX_ROW_EN[1] = 0x0
3738 08:06:21.742388 LP4Y_EN = 0x0
3739 08:06:21.745149 WORK_FSP = 0x0
3740 08:06:21.745701 WL = 0x2
3741 08:06:21.748172 RL = 0x2
3742 08:06:21.748728 BL = 0x2
3743 08:06:21.751589 RPST = 0x0
3744 08:06:21.752143 RD_PRE = 0x0
3745 08:06:21.755068 WR_PRE = 0x1
3746 08:06:21.755626 WR_PST = 0x0
3747 08:06:21.758035 DBI_WR = 0x0
3748 08:06:21.758491 DBI_RD = 0x0
3749 08:06:21.761537 OTF = 0x1
3750 08:06:21.764818 ===================================
3751 08:06:21.768164 ===================================
3752 08:06:21.768619 ANA top config
3753 08:06:21.771584 ===================================
3754 08:06:21.774529 DLL_ASYNC_EN = 0
3755 08:06:21.777805 ALL_SLAVE_EN = 1
3756 08:06:21.781465 NEW_RANK_MODE = 1
3757 08:06:21.782175 DLL_IDLE_MODE = 1
3758 08:06:21.784892 LP45_APHY_COMB_EN = 1
3759 08:06:21.788147 TX_ODT_DIS = 1
3760 08:06:21.791281 NEW_8X_MODE = 1
3761 08:06:21.794634 ===================================
3762 08:06:21.798151 ===================================
3763 08:06:21.801303 data_rate = 1200
3764 08:06:21.801861 CKR = 1
3765 08:06:21.804707 DQ_P2S_RATIO = 8
3766 08:06:21.808022 ===================================
3767 08:06:21.811514 CA_P2S_RATIO = 8
3768 08:06:21.814717 DQ_CA_OPEN = 0
3769 08:06:21.818290 DQ_SEMI_OPEN = 0
3770 08:06:21.818873 CA_SEMI_OPEN = 0
3771 08:06:21.821346 CA_FULL_RATE = 0
3772 08:06:21.824867 DQ_CKDIV4_EN = 1
3773 08:06:21.828201 CA_CKDIV4_EN = 1
3774 08:06:21.831097 CA_PREDIV_EN = 0
3775 08:06:21.835029 PH8_DLY = 0
3776 08:06:21.835598 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3777 08:06:21.838228 DQ_AAMCK_DIV = 4
3778 08:06:21.841522 CA_AAMCK_DIV = 4
3779 08:06:21.844899 CA_ADMCK_DIV = 4
3780 08:06:21.848126 DQ_TRACK_CA_EN = 0
3781 08:06:21.851631 CA_PICK = 600
3782 08:06:21.854649 CA_MCKIO = 600
3783 08:06:21.855221 MCKIO_SEMI = 0
3784 08:06:21.858076 PLL_FREQ = 2288
3785 08:06:21.861509 DQ_UI_PI_RATIO = 32
3786 08:06:21.864843 CA_UI_PI_RATIO = 0
3787 08:06:21.867915 ===================================
3788 08:06:21.871030 ===================================
3789 08:06:21.875189 memory_type:LPDDR4
3790 08:06:21.875762 GP_NUM : 10
3791 08:06:21.877662 SRAM_EN : 1
3792 08:06:21.881109 MD32_EN : 0
3793 08:06:21.881675 ===================================
3794 08:06:21.884509 [ANA_INIT] >>>>>>>>>>>>>>
3795 08:06:21.888073 <<<<<< [CONFIGURE PHASE]: ANA_TX
3796 08:06:21.891111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3797 08:06:21.894590 ===================================
3798 08:06:21.897856 data_rate = 1200,PCW = 0X5800
3799 08:06:21.901353 ===================================
3800 08:06:21.904589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3801 08:06:21.911590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 08:06:21.914555 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 08:06:21.921127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3804 08:06:21.924440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3805 08:06:21.927907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3806 08:06:21.928478 [ANA_INIT] flow start
3807 08:06:21.931186 [ANA_INIT] PLL >>>>>>>>
3808 08:06:21.934520 [ANA_INIT] PLL <<<<<<<<
3809 08:06:21.935092 [ANA_INIT] MIDPI >>>>>>>>
3810 08:06:21.937589 [ANA_INIT] MIDPI <<<<<<<<
3811 08:06:21.941276 [ANA_INIT] DLL >>>>>>>>
3812 08:06:21.941843 [ANA_INIT] flow end
3813 08:06:21.947841 ============ LP4 DIFF to SE enter ============
3814 08:06:21.951278 ============ LP4 DIFF to SE exit ============
3815 08:06:21.954578 [ANA_INIT] <<<<<<<<<<<<<
3816 08:06:21.958260 [Flow] Enable top DCM control >>>>>
3817 08:06:21.958831 [Flow] Enable top DCM control <<<<<
3818 08:06:21.961026 Enable DLL master slave shuffle
3819 08:06:21.967588 ==============================================================
3820 08:06:21.971251 Gating Mode config
3821 08:06:21.974755 ==============================================================
3822 08:06:21.977591 Config description:
3823 08:06:21.987486 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3824 08:06:21.994396 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3825 08:06:21.997682 SELPH_MODE 0: By rank 1: By Phase
3826 08:06:22.004416 ==============================================================
3827 08:06:22.007494 GAT_TRACK_EN = 1
3828 08:06:22.010796 RX_GATING_MODE = 2
3829 08:06:22.014077 RX_GATING_TRACK_MODE = 2
3830 08:06:22.014593 SELPH_MODE = 1
3831 08:06:22.017350 PICG_EARLY_EN = 1
3832 08:06:22.020499 VALID_LAT_VALUE = 1
3833 08:06:22.027756 ==============================================================
3834 08:06:22.031097 Enter into Gating configuration >>>>
3835 08:06:22.034124 Exit from Gating configuration <<<<
3836 08:06:22.037664 Enter into DVFS_PRE_config >>>>>
3837 08:06:22.047430 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3838 08:06:22.050977 Exit from DVFS_PRE_config <<<<<
3839 08:06:22.054422 Enter into PICG configuration >>>>
3840 08:06:22.057536 Exit from PICG configuration <<<<
3841 08:06:22.060789 [RX_INPUT] configuration >>>>>
3842 08:06:22.064297 [RX_INPUT] configuration <<<<<
3843 08:06:22.067110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3844 08:06:22.073903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3845 08:06:22.080836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 08:06:22.087110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 08:06:22.090541 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3848 08:06:22.097721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3849 08:06:22.100753 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3850 08:06:22.107391 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3851 08:06:22.110752 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3852 08:06:22.114064 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3853 08:06:22.117370 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3854 08:06:22.124404 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3855 08:06:22.127219 ===================================
3856 08:06:22.127686 LPDDR4 DRAM CONFIGURATION
3857 08:06:22.131345 ===================================
3858 08:06:22.134151 EX_ROW_EN[0] = 0x0
3859 08:06:22.137821 EX_ROW_EN[1] = 0x0
3860 08:06:22.138384 LP4Y_EN = 0x0
3861 08:06:22.141132 WORK_FSP = 0x0
3862 08:06:22.141694 WL = 0x2
3863 08:06:22.144474 RL = 0x2
3864 08:06:22.145082 BL = 0x2
3865 08:06:22.147898 RPST = 0x0
3866 08:06:22.148454 RD_PRE = 0x0
3867 08:06:22.151123 WR_PRE = 0x1
3868 08:06:22.151684 WR_PST = 0x0
3869 08:06:22.154327 DBI_WR = 0x0
3870 08:06:22.154885 DBI_RD = 0x0
3871 08:06:22.157398 OTF = 0x1
3872 08:06:22.161613 ===================================
3873 08:06:22.164525 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3874 08:06:22.167616 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3875 08:06:22.174217 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 08:06:22.177736 ===================================
3877 08:06:22.178296 LPDDR4 DRAM CONFIGURATION
3878 08:06:22.181067 ===================================
3879 08:06:22.184611 EX_ROW_EN[0] = 0x10
3880 08:06:22.185219 EX_ROW_EN[1] = 0x0
3881 08:06:22.187616 LP4Y_EN = 0x0
3882 08:06:22.188193 WORK_FSP = 0x0
3883 08:06:22.191529 WL = 0x2
3884 08:06:22.194206 RL = 0x2
3885 08:06:22.194776 BL = 0x2
3886 08:06:22.197449 RPST = 0x0
3887 08:06:22.197910 RD_PRE = 0x0
3888 08:06:22.200492 WR_PRE = 0x1
3889 08:06:22.200980 WR_PST = 0x0
3890 08:06:22.203888 DBI_WR = 0x0
3891 08:06:22.204408 DBI_RD = 0x0
3892 08:06:22.207419 OTF = 0x1
3893 08:06:22.210968 ===================================
3894 08:06:22.213953 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3895 08:06:22.219707 nWR fixed to 30
3896 08:06:22.222857 [ModeRegInit_LP4] CH0 RK0
3897 08:06:22.223333 [ModeRegInit_LP4] CH0 RK1
3898 08:06:22.226118 [ModeRegInit_LP4] CH1 RK0
3899 08:06:22.229548 [ModeRegInit_LP4] CH1 RK1
3900 08:06:22.230012 match AC timing 17
3901 08:06:22.236227 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3902 08:06:22.240068 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3903 08:06:22.243249 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3904 08:06:22.249897 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3905 08:06:22.253374 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3906 08:06:22.253940 ==
3907 08:06:22.256567 Dram Type= 6, Freq= 0, CH_0, rank 0
3908 08:06:22.260111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3909 08:06:22.260691 ==
3910 08:06:22.266625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3911 08:06:22.273074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3912 08:06:22.276545 [CA 0] Center 36 (6~67) winsize 62
3913 08:06:22.279831 [CA 1] Center 36 (6~67) winsize 62
3914 08:06:22.283236 [CA 2] Center 34 (4~65) winsize 62
3915 08:06:22.286438 [CA 3] Center 34 (4~65) winsize 62
3916 08:06:22.289826 [CA 4] Center 33 (3~64) winsize 62
3917 08:06:22.293234 [CA 5] Center 33 (2~64) winsize 63
3918 08:06:22.293793
3919 08:06:22.296518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3920 08:06:22.297108
3921 08:06:22.299747 [CATrainingPosCal] consider 1 rank data
3922 08:06:22.303356 u2DelayCellTimex100 = 270/100 ps
3923 08:06:22.306453 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3924 08:06:22.309665 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3925 08:06:22.313071 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3926 08:06:22.316926 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3927 08:06:22.319816 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3928 08:06:22.322968 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3929 08:06:22.323445
3930 08:06:22.329526 CA PerBit enable=1, Macro0, CA PI delay=33
3931 08:06:22.330075
3932 08:06:22.333397 [CBTSetCACLKResult] CA Dly = 33
3933 08:06:22.333879 CS Dly: 5 (0~36)
3934 08:06:22.334246 ==
3935 08:06:22.336192 Dram Type= 6, Freq= 0, CH_0, rank 1
3936 08:06:22.339694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3937 08:06:22.340268 ==
3938 08:06:22.346706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3939 08:06:22.353124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3940 08:06:22.356271 [CA 0] Center 36 (6~67) winsize 62
3941 08:06:22.359536 [CA 1] Center 36 (6~67) winsize 62
3942 08:06:22.362891 [CA 2] Center 34 (4~65) winsize 62
3943 08:06:22.365918 [CA 3] Center 34 (4~65) winsize 62
3944 08:06:22.369511 [CA 4] Center 34 (3~65) winsize 63
3945 08:06:22.372725 [CA 5] Center 33 (3~64) winsize 62
3946 08:06:22.373251
3947 08:06:22.375906 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3948 08:06:22.376460
3949 08:06:22.379556 [CATrainingPosCal] consider 2 rank data
3950 08:06:22.383224 u2DelayCellTimex100 = 270/100 ps
3951 08:06:22.386156 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3952 08:06:22.389327 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3953 08:06:22.392787 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 08:06:22.395998 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3955 08:06:22.399325 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 08:06:22.405854 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3957 08:06:22.406408
3958 08:06:22.409133 CA PerBit enable=1, Macro0, CA PI delay=33
3959 08:06:22.409599
3960 08:06:22.412606 [CBTSetCACLKResult] CA Dly = 33
3961 08:06:22.413189 CS Dly: 5 (0~37)
3962 08:06:22.413564
3963 08:06:22.415590 ----->DramcWriteLeveling(PI) begin...
3964 08:06:22.416056 ==
3965 08:06:22.419158 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 08:06:22.425607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 08:06:22.426151 ==
3968 08:06:22.428768 Write leveling (Byte 0): 34 => 34
3969 08:06:22.429263 Write leveling (Byte 1): 30 => 30
3970 08:06:22.432193 DramcWriteLeveling(PI) end<-----
3971 08:06:22.432699
3972 08:06:22.433107 ==
3973 08:06:22.435747 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 08:06:22.442056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 08:06:22.442594 ==
3976 08:06:22.445485 [Gating] SW mode calibration
3977 08:06:22.452615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3978 08:06:22.455962 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3979 08:06:22.462463 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 08:06:22.466144 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 08:06:22.468991 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 08:06:22.475987 0 9 12 | B1->B0 | 3333 2b2b | 1 1 | (1 1) (1 1)
3983 08:06:22.478950 0 9 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3984 08:06:22.482298 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 08:06:22.485755 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 08:06:22.492334 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 08:06:22.495946 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 08:06:22.499510 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 08:06:22.505582 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3990 08:06:22.509171 0 10 12 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
3991 08:06:22.512819 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3992 08:06:22.518882 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 08:06:22.522447 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 08:06:22.525562 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 08:06:22.532627 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 08:06:22.535190 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 08:06:22.538672 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3998 08:06:22.545312 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3999 08:06:22.548995 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4000 08:06:22.552196 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 08:06:22.558979 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 08:06:22.562080 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 08:06:22.565499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 08:06:22.571947 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 08:06:22.575537 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 08:06:22.578962 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 08:06:22.585422 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 08:06:22.588738 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 08:06:22.592077 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 08:06:22.598668 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 08:06:22.601831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 08:06:22.605539 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 08:06:22.612318 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 08:06:22.615408 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4015 08:06:22.618311 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4016 08:06:22.621999 Total UI for P1: 0, mck2ui 16
4017 08:06:22.624960 best dqsien dly found for B0: ( 0, 13, 12)
4018 08:06:22.628487 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 08:06:22.631690 Total UI for P1: 0, mck2ui 16
4020 08:06:22.635186 best dqsien dly found for B1: ( 0, 13, 16)
4021 08:06:22.638202 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4022 08:06:22.645217 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4023 08:06:22.645766
4024 08:06:22.648399 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4025 08:06:22.651727 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4026 08:06:22.655164 [Gating] SW calibration Done
4027 08:06:22.655722 ==
4028 08:06:22.658047 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 08:06:22.661715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 08:06:22.662280 ==
4031 08:06:22.665138 RX Vref Scan: 0
4032 08:06:22.665711
4033 08:06:22.666080 RX Vref 0 -> 0, step: 1
4034 08:06:22.666421
4035 08:06:22.668133 RX Delay -230 -> 252, step: 16
4036 08:06:22.671400 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4037 08:06:22.678198 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4038 08:06:22.681673 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4039 08:06:22.685216 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4040 08:06:22.688369 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4041 08:06:22.691401 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4042 08:06:22.698667 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4043 08:06:22.701813 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4044 08:06:22.705294 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4045 08:06:22.708321 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4046 08:06:22.714787 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4047 08:06:22.717996 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4048 08:06:22.721921 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4049 08:06:22.724987 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4050 08:06:22.731600 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4051 08:06:22.734906 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4052 08:06:22.735373 ==
4053 08:06:22.738311 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 08:06:22.741581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 08:06:22.742149 ==
4056 08:06:22.745230 DQS Delay:
4057 08:06:22.745799 DQS0 = 0, DQS1 = 0
4058 08:06:22.746176 DQM Delay:
4059 08:06:22.748213 DQM0 = 50, DQM1 = 37
4060 08:06:22.748785 DQ Delay:
4061 08:06:22.751445 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4062 08:06:22.754552 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4063 08:06:22.758036 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4064 08:06:22.761249 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4065 08:06:22.761812
4066 08:06:22.762179
4067 08:06:22.762519 ==
4068 08:06:22.764583 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 08:06:22.767778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 08:06:22.771469 ==
4071 08:06:22.772026
4072 08:06:22.772395
4073 08:06:22.772740 TX Vref Scan disable
4074 08:06:22.774661 == TX Byte 0 ==
4075 08:06:22.778085 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4076 08:06:22.781349 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4077 08:06:22.785209 == TX Byte 1 ==
4078 08:06:22.788089 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4079 08:06:22.794692 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4080 08:06:22.795265 ==
4081 08:06:22.798589 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 08:06:22.801558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 08:06:22.802136 ==
4084 08:06:22.802610
4085 08:06:22.803051
4086 08:06:22.804341 TX Vref Scan disable
4087 08:06:22.808112 == TX Byte 0 ==
4088 08:06:22.811646 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4089 08:06:22.814801 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4090 08:06:22.818125 == TX Byte 1 ==
4091 08:06:22.821502 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4092 08:06:22.824623 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4093 08:06:22.825217
4094 08:06:22.825693 [DATLAT]
4095 08:06:22.827633 Freq=600, CH0 RK0
4096 08:06:22.828108
4097 08:06:22.828576 DATLAT Default: 0x9
4098 08:06:22.831352 0, 0xFFFF, sum = 0
4099 08:06:22.834245 1, 0xFFFF, sum = 0
4100 08:06:22.834782 2, 0xFFFF, sum = 0
4101 08:06:22.837822 3, 0xFFFF, sum = 0
4102 08:06:22.838384 4, 0xFFFF, sum = 0
4103 08:06:22.840890 5, 0xFFFF, sum = 0
4104 08:06:22.841399 6, 0xFFFF, sum = 0
4105 08:06:22.844515 7, 0xFFFF, sum = 0
4106 08:06:22.845132 8, 0x0, sum = 1
4107 08:06:22.847851 9, 0x0, sum = 2
4108 08:06:22.848413 10, 0x0, sum = 3
4109 08:06:22.848786 11, 0x0, sum = 4
4110 08:06:22.851491 best_step = 9
4111 08:06:22.852044
4112 08:06:22.852403 ==
4113 08:06:22.854628 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 08:06:22.858082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 08:06:22.858643 ==
4116 08:06:22.861335 RX Vref Scan: 1
4117 08:06:22.861886
4118 08:06:22.862251 RX Vref 0 -> 0, step: 1
4119 08:06:22.862588
4120 08:06:22.864832 RX Delay -179 -> 252, step: 8
4121 08:06:22.865449
4122 08:06:22.867750 Set Vref, RX VrefLevel [Byte0]: 56
4123 08:06:22.871444 [Byte1]: 49
4124 08:06:22.875302
4125 08:06:22.875759 Final RX Vref Byte 0 = 56 to rank0
4126 08:06:22.878799 Final RX Vref Byte 1 = 49 to rank0
4127 08:06:22.882230 Final RX Vref Byte 0 = 56 to rank1
4128 08:06:22.885239 Final RX Vref Byte 1 = 49 to rank1==
4129 08:06:22.888699 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 08:06:22.895666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 08:06:22.896226 ==
4132 08:06:22.896590 DQS Delay:
4133 08:06:22.896959 DQS0 = 0, DQS1 = 0
4134 08:06:22.898395 DQM Delay:
4135 08:06:22.898893 DQM0 = 50, DQM1 = 37
4136 08:06:22.901857 DQ Delay:
4137 08:06:22.905284 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4138 08:06:22.908742 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =60
4139 08:06:22.909333 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4140 08:06:22.915144 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4141 08:06:22.915700
4142 08:06:22.916061
4143 08:06:22.921773 [DQSOSCAuto] RK0, (LSB)MR18= 0x615c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4144 08:06:22.925080 CH0 RK0: MR19=808, MR18=615C
4145 08:06:22.931860 CH0_RK0: MR19=0x808, MR18=0x615C, DQSOSC=391, MR23=63, INC=171, DEC=114
4146 08:06:22.932422
4147 08:06:22.935020 ----->DramcWriteLeveling(PI) begin...
4148 08:06:22.935687 ==
4149 08:06:22.938408 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 08:06:22.941834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 08:06:22.942361 ==
4152 08:06:22.945041 Write leveling (Byte 0): 36 => 36
4153 08:06:22.948385 Write leveling (Byte 1): 31 => 31
4154 08:06:22.951889 DramcWriteLeveling(PI) end<-----
4155 08:06:22.952443
4156 08:06:22.952811 ==
4157 08:06:22.955322 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 08:06:22.958514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 08:06:22.959073 ==
4160 08:06:22.961685 [Gating] SW mode calibration
4161 08:06:22.968289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4162 08:06:22.975092 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4163 08:06:22.978197 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 08:06:22.981919 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 08:06:22.988507 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 08:06:22.992181 0 9 12 | B1->B0 | 3232 3434 | 1 0 | (1 0) (0 1)
4167 08:06:22.994511 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
4168 08:06:23.001644 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 08:06:23.005147 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 08:06:23.008348 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 08:06:23.015088 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 08:06:23.018320 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 08:06:23.021626 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 08:06:23.027929 0 10 12 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
4175 08:06:23.031565 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4176 08:06:23.034414 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 08:06:23.041349 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 08:06:23.045055 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 08:06:23.048408 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 08:06:23.054646 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 08:06:23.058106 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 08:06:23.061472 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 08:06:23.068173 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4184 08:06:23.071194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 08:06:23.074766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 08:06:23.081513 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 08:06:23.084594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 08:06:23.087726 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 08:06:23.094375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 08:06:23.098023 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 08:06:23.101176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 08:06:23.104719 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 08:06:23.111395 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 08:06:23.115023 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 08:06:23.117937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 08:06:23.124505 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 08:06:23.127798 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 08:06:23.131242 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4199 08:06:23.138069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 08:06:23.140846 Total UI for P1: 0, mck2ui 16
4201 08:06:23.144717 best dqsien dly found for B0: ( 0, 13, 12)
4202 08:06:23.145321 Total UI for P1: 0, mck2ui 16
4203 08:06:23.151188 best dqsien dly found for B1: ( 0, 13, 12)
4204 08:06:23.154432 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4205 08:06:23.158008 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4206 08:06:23.158563
4207 08:06:23.161290 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4208 08:06:23.164453 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 08:06:23.167915 [Gating] SW calibration Done
4210 08:06:23.168381 ==
4211 08:06:23.171074 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 08:06:23.174392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 08:06:23.174954 ==
4214 08:06:23.177550 RX Vref Scan: 0
4215 08:06:23.178106
4216 08:06:23.178473 RX Vref 0 -> 0, step: 1
4217 08:06:23.181049
4218 08:06:23.181607 RX Delay -230 -> 252, step: 16
4219 08:06:23.187895 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4220 08:06:23.190980 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4221 08:06:23.194136 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4222 08:06:23.197575 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4223 08:06:23.204265 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4224 08:06:23.207429 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4225 08:06:23.210829 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4226 08:06:23.213926 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4227 08:06:23.217311 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4228 08:06:23.224281 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4229 08:06:23.227233 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4230 08:06:23.230634 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4231 08:06:23.233922 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4232 08:06:23.240775 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4233 08:06:23.244151 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4234 08:06:23.247786 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4235 08:06:23.248343 ==
4236 08:06:23.250851 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 08:06:23.253717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 08:06:23.254188 ==
4239 08:06:23.257678 DQS Delay:
4240 08:06:23.258232 DQS0 = 0, DQS1 = 0
4241 08:06:23.260524 DQM Delay:
4242 08:06:23.261013 DQM0 = 48, DQM1 = 42
4243 08:06:23.261387 DQ Delay:
4244 08:06:23.264146 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4245 08:06:23.267167 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4246 08:06:23.270637 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4247 08:06:23.273835 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4248 08:06:23.274393
4249 08:06:23.274760
4250 08:06:23.277565 ==
4251 08:06:23.280801 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 08:06:23.284006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 08:06:23.284576 ==
4254 08:06:23.284981
4255 08:06:23.285329
4256 08:06:23.287027 TX Vref Scan disable
4257 08:06:23.287488 == TX Byte 0 ==
4258 08:06:23.293859 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4259 08:06:23.297495 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4260 08:06:23.298053 == TX Byte 1 ==
4261 08:06:23.303876 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4262 08:06:23.307147 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4263 08:06:23.307699 ==
4264 08:06:23.310865 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 08:06:23.313762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 08:06:23.314226 ==
4267 08:06:23.314587
4268 08:06:23.314920
4269 08:06:23.317358 TX Vref Scan disable
4270 08:06:23.321091 == TX Byte 0 ==
4271 08:06:23.324266 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4272 08:06:23.327201 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4273 08:06:23.330894 == TX Byte 1 ==
4274 08:06:23.334163 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4275 08:06:23.337362 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4276 08:06:23.337819
4277 08:06:23.341140 [DATLAT]
4278 08:06:23.341597 Freq=600, CH0 RK1
4279 08:06:23.341961
4280 08:06:23.343681 DATLAT Default: 0x9
4281 08:06:23.344135 0, 0xFFFF, sum = 0
4282 08:06:23.347289 1, 0xFFFF, sum = 0
4283 08:06:23.347855 2, 0xFFFF, sum = 0
4284 08:06:23.350912 3, 0xFFFF, sum = 0
4285 08:06:23.351483 4, 0xFFFF, sum = 0
4286 08:06:23.353740 5, 0xFFFF, sum = 0
4287 08:06:23.354202 6, 0xFFFF, sum = 0
4288 08:06:23.357281 7, 0xFFFF, sum = 0
4289 08:06:23.357745 8, 0x0, sum = 1
4290 08:06:23.360336 9, 0x0, sum = 2
4291 08:06:23.360796 10, 0x0, sum = 3
4292 08:06:23.364072 11, 0x0, sum = 4
4293 08:06:23.364524 best_step = 9
4294 08:06:23.364872
4295 08:06:23.365240 ==
4296 08:06:23.366856 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 08:06:23.370103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 08:06:23.373725 ==
4299 08:06:23.374168 RX Vref Scan: 0
4300 08:06:23.374517
4301 08:06:23.376926 RX Vref 0 -> 0, step: 1
4302 08:06:23.377397
4303 08:06:23.380116 RX Delay -179 -> 252, step: 8
4304 08:06:23.383707 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4305 08:06:23.386929 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4306 08:06:23.393756 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4307 08:06:23.396628 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4308 08:06:23.400442 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4309 08:06:23.403669 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4310 08:06:23.407058 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4311 08:06:23.413517 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4312 08:06:23.416630 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4313 08:06:23.419967 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4314 08:06:23.423221 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4315 08:06:23.429926 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4316 08:06:23.433019 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4317 08:06:23.436800 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4318 08:06:23.440372 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4319 08:06:23.443517 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4320 08:06:23.446798 ==
4321 08:06:23.449835 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 08:06:23.453491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 08:06:23.454057 ==
4324 08:06:23.454415 DQS Delay:
4325 08:06:23.456682 DQS0 = 0, DQS1 = 0
4326 08:06:23.457286 DQM Delay:
4327 08:06:23.460053 DQM0 = 47, DQM1 = 42
4328 08:06:23.460609 DQ Delay:
4329 08:06:23.463292 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4330 08:06:23.466770 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4331 08:06:23.469686 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4332 08:06:23.473287 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4333 08:06:23.473858
4334 08:06:23.474216
4335 08:06:23.480077 [DQSOSCAuto] RK1, (LSB)MR18= 0x6836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4336 08:06:23.483239 CH0 RK1: MR19=808, MR18=6836
4337 08:06:23.489853 CH0_RK1: MR19=0x808, MR18=0x6836, DQSOSC=390, MR23=63, INC=172, DEC=114
4338 08:06:23.493184 [RxdqsGatingPostProcess] freq 600
4339 08:06:23.499807 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4340 08:06:23.500368 Pre-setting of DQS Precalculation
4341 08:06:23.506814 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4342 08:06:23.507369 ==
4343 08:06:23.509789 Dram Type= 6, Freq= 0, CH_1, rank 0
4344 08:06:23.513236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 08:06:23.513791 ==
4346 08:06:23.519533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4347 08:06:23.526094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4348 08:06:23.529622 [CA 0] Center 35 (5~66) winsize 62
4349 08:06:23.532888 [CA 1] Center 35 (5~66) winsize 62
4350 08:06:23.536344 [CA 2] Center 34 (4~65) winsize 62
4351 08:06:23.539753 [CA 3] Center 33 (3~64) winsize 62
4352 08:06:23.542642 [CA 4] Center 33 (3~64) winsize 62
4353 08:06:23.546358 [CA 5] Center 33 (3~64) winsize 62
4354 08:06:23.546811
4355 08:06:23.549761 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4356 08:06:23.550321
4357 08:06:23.552635 [CATrainingPosCal] consider 1 rank data
4358 08:06:23.556091 u2DelayCellTimex100 = 270/100 ps
4359 08:06:23.559882 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4360 08:06:23.562802 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4361 08:06:23.566070 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4362 08:06:23.569624 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4363 08:06:23.572722 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4364 08:06:23.575899 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4365 08:06:23.576477
4366 08:06:23.582819 CA PerBit enable=1, Macro0, CA PI delay=33
4367 08:06:23.583400
4368 08:06:23.583888 [CBTSetCACLKResult] CA Dly = 33
4369 08:06:23.586284 CS Dly: 4 (0~35)
4370 08:06:23.586862 ==
4371 08:06:23.589774 Dram Type= 6, Freq= 0, CH_1, rank 1
4372 08:06:23.592725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 08:06:23.593353 ==
4374 08:06:23.599482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 08:06:23.606388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4376 08:06:23.609278 [CA 0] Center 35 (5~66) winsize 62
4377 08:06:23.612907 [CA 1] Center 35 (5~66) winsize 62
4378 08:06:23.616078 [CA 2] Center 34 (4~65) winsize 62
4379 08:06:23.618994 [CA 3] Center 34 (4~65) winsize 62
4380 08:06:23.623004 [CA 4] Center 34 (4~64) winsize 61
4381 08:06:23.625940 [CA 5] Center 33 (3~64) winsize 62
4382 08:06:23.626519
4383 08:06:23.629117 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4384 08:06:23.629690
4385 08:06:23.632354 [CATrainingPosCal] consider 2 rank data
4386 08:06:23.635833 u2DelayCellTimex100 = 270/100 ps
4387 08:06:23.639313 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4388 08:06:23.642638 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 08:06:23.646110 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 08:06:23.649029 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4391 08:06:23.652500 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4392 08:06:23.659142 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4393 08:06:23.659702
4394 08:06:23.662652 CA PerBit enable=1, Macro0, CA PI delay=33
4395 08:06:23.663214
4396 08:06:23.666043 [CBTSetCACLKResult] CA Dly = 33
4397 08:06:23.666596 CS Dly: 4 (0~36)
4398 08:06:23.666960
4399 08:06:23.669093 ----->DramcWriteLeveling(PI) begin...
4400 08:06:23.669652 ==
4401 08:06:23.672498 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 08:06:23.676052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 08:06:23.679172 ==
4404 08:06:23.679729 Write leveling (Byte 0): 28 => 28
4405 08:06:23.682458 Write leveling (Byte 1): 32 => 32
4406 08:06:23.686102 DramcWriteLeveling(PI) end<-----
4407 08:06:23.686658
4408 08:06:23.687019 ==
4409 08:06:23.689426 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 08:06:23.695743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 08:06:23.696333 ==
4412 08:06:23.696701 [Gating] SW mode calibration
4413 08:06:23.705870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4414 08:06:23.709104 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4415 08:06:23.712687 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 08:06:23.719015 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 08:06:23.722533 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4418 08:06:23.725843 0 9 12 | B1->B0 | 2d2d 2c2c | 1 0 | (1 0) (1 0)
4419 08:06:23.732369 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 08:06:23.735708 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 08:06:23.739121 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 08:06:23.745459 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 08:06:23.748953 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 08:06:23.752132 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 08:06:23.759072 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4426 08:06:23.762437 0 10 12 | B1->B0 | 3838 4040 | 1 1 | (0 0) (0 0)
4427 08:06:23.765553 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 08:06:23.772479 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 08:06:23.776309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 08:06:23.779068 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 08:06:23.785605 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 08:06:23.789091 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 08:06:23.792418 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4434 08:06:23.799073 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4435 08:06:23.802084 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 08:06:23.805660 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 08:06:23.812070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 08:06:23.815335 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 08:06:23.818902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 08:06:23.822131 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 08:06:23.828712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 08:06:23.832148 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 08:06:23.835789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 08:06:23.842217 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 08:06:23.845131 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 08:06:23.848615 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 08:06:23.855429 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 08:06:23.858707 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 08:06:23.861898 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 08:06:23.868662 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 08:06:23.872311 Total UI for P1: 0, mck2ui 16
4452 08:06:23.875259 best dqsien dly found for B0: ( 0, 13, 10)
4453 08:06:23.875815 Total UI for P1: 0, mck2ui 16
4454 08:06:23.881824 best dqsien dly found for B1: ( 0, 13, 10)
4455 08:06:23.885506 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4456 08:06:23.888272 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4457 08:06:23.888733
4458 08:06:23.891765 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4459 08:06:23.895610 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4460 08:06:23.898632 [Gating] SW calibration Done
4461 08:06:23.899185 ==
4462 08:06:23.901761 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 08:06:23.904997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 08:06:23.905559 ==
4465 08:06:23.908749 RX Vref Scan: 0
4466 08:06:23.909338
4467 08:06:23.909708 RX Vref 0 -> 0, step: 1
4468 08:06:23.911948
4469 08:06:23.912515 RX Delay -230 -> 252, step: 16
4470 08:06:23.918643 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4471 08:06:23.922095 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4472 08:06:23.925358 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4473 08:06:23.928547 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4474 08:06:23.931672 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4475 08:06:23.938558 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4476 08:06:23.941806 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4477 08:06:23.945253 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4478 08:06:23.948734 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4479 08:06:23.955046 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4480 08:06:23.958400 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4481 08:06:23.962101 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4482 08:06:23.964894 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4483 08:06:23.968709 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4484 08:06:23.975038 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4485 08:06:23.978519 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4486 08:06:23.979073 ==
4487 08:06:23.981776 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 08:06:23.985200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 08:06:23.985754 ==
4490 08:06:23.988475 DQS Delay:
4491 08:06:23.989054 DQS0 = 0, DQS1 = 0
4492 08:06:23.991891 DQM Delay:
4493 08:06:23.992351 DQM0 = 51, DQM1 = 43
4494 08:06:23.992714 DQ Delay:
4495 08:06:23.995188 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4496 08:06:23.998405 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4497 08:06:24.002060 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4498 08:06:24.005357 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4499 08:06:24.005820
4500 08:06:24.006182
4501 08:06:24.006522 ==
4502 08:06:24.008548 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 08:06:24.015138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 08:06:24.015690 ==
4505 08:06:24.016059
4506 08:06:24.016395
4507 08:06:24.016714 TX Vref Scan disable
4508 08:06:24.018788 == TX Byte 0 ==
4509 08:06:24.022807 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4510 08:06:24.029092 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4511 08:06:24.029726 == TX Byte 1 ==
4512 08:06:24.032110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4513 08:06:24.038921 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4514 08:06:24.039461 ==
4515 08:06:24.042182 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 08:06:24.045271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 08:06:24.045733 ==
4518 08:06:24.046098
4519 08:06:24.046431
4520 08:06:24.048722 TX Vref Scan disable
4521 08:06:24.052035 == TX Byte 0 ==
4522 08:06:24.055422 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4523 08:06:24.058694 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4524 08:06:24.062287 == TX Byte 1 ==
4525 08:06:24.065422 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 08:06:24.068745 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 08:06:24.069365
4528 08:06:24.069735 [DATLAT]
4529 08:06:24.072391 Freq=600, CH1 RK0
4530 08:06:24.073049
4531 08:06:24.073447 DATLAT Default: 0x9
4532 08:06:24.075498 0, 0xFFFF, sum = 0
4533 08:06:24.076053 1, 0xFFFF, sum = 0
4534 08:06:24.078889 2, 0xFFFF, sum = 0
4535 08:06:24.081861 3, 0xFFFF, sum = 0
4536 08:06:24.082414 4, 0xFFFF, sum = 0
4537 08:06:24.085844 5, 0xFFFF, sum = 0
4538 08:06:24.086419 6, 0xFFFF, sum = 0
4539 08:06:24.088717 7, 0xFFFF, sum = 0
4540 08:06:24.089329 8, 0x0, sum = 1
4541 08:06:24.089724 9, 0x0, sum = 2
4542 08:06:24.092378 10, 0x0, sum = 3
4543 08:06:24.092974 11, 0x0, sum = 4
4544 08:06:24.095154 best_step = 9
4545 08:06:24.095605
4546 08:06:24.095966 ==
4547 08:06:24.099020 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 08:06:24.102050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 08:06:24.102608 ==
4550 08:06:24.105354 RX Vref Scan: 1
4551 08:06:24.105906
4552 08:06:24.106267 RX Vref 0 -> 0, step: 1
4553 08:06:24.106603
4554 08:06:24.108494 RX Delay -179 -> 252, step: 8
4555 08:06:24.108988
4556 08:06:24.112044 Set Vref, RX VrefLevel [Byte0]: 51
4557 08:06:24.115254 [Byte1]: 59
4558 08:06:24.119922
4559 08:06:24.120524 Final RX Vref Byte 0 = 51 to rank0
4560 08:06:24.122836 Final RX Vref Byte 1 = 59 to rank0
4561 08:06:24.126090 Final RX Vref Byte 0 = 51 to rank1
4562 08:06:24.129517 Final RX Vref Byte 1 = 59 to rank1==
4563 08:06:24.132702 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 08:06:24.139393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 08:06:24.139951 ==
4566 08:06:24.140317 DQS Delay:
4567 08:06:24.140649 DQS0 = 0, DQS1 = 0
4568 08:06:24.142847 DQM Delay:
4569 08:06:24.143301 DQM0 = 49, DQM1 = 41
4570 08:06:24.146187 DQ Delay:
4571 08:06:24.149350 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4572 08:06:24.149805 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4573 08:06:24.152867 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4574 08:06:24.159488 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4575 08:06:24.160043
4576 08:06:24.160409
4577 08:06:24.166293 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4578 08:06:24.169155 CH1 RK0: MR19=808, MR18=4B71
4579 08:06:24.176360 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4580 08:06:24.176921
4581 08:06:24.179567 ----->DramcWriteLeveling(PI) begin...
4582 08:06:24.180158 ==
4583 08:06:24.182880 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 08:06:24.186066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 08:06:24.186668 ==
4586 08:06:24.189260 Write leveling (Byte 0): 30 => 30
4587 08:06:24.192504 Write leveling (Byte 1): 30 => 30
4588 08:06:24.196255 DramcWriteLeveling(PI) end<-----
4589 08:06:24.196815
4590 08:06:24.197234 ==
4591 08:06:24.199354 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 08:06:24.202674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 08:06:24.203230 ==
4594 08:06:24.205741 [Gating] SW mode calibration
4595 08:06:24.212739 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4596 08:06:24.219411 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4597 08:06:24.222400 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 08:06:24.225597 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 08:06:24.232319 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4600 08:06:24.235836 0 9 12 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
4601 08:06:24.238999 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4602 08:06:24.245620 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 08:06:24.249360 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 08:06:24.253109 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 08:06:24.259653 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 08:06:24.263001 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 08:06:24.266232 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4608 08:06:24.272757 0 10 12 | B1->B0 | 3b3b 2d2d | 1 0 | (0 0) (0 0)
4609 08:06:24.275987 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4610 08:06:24.279026 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 08:06:24.285740 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 08:06:24.289056 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 08:06:24.292288 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 08:06:24.299031 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 08:06:24.302536 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4616 08:06:24.305833 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4617 08:06:24.312431 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 08:06:24.315695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 08:06:24.318977 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 08:06:24.322374 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 08:06:24.328918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 08:06:24.332247 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 08:06:24.335540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 08:06:24.342473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 08:06:24.345712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 08:06:24.348856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 08:06:24.355547 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 08:06:24.359229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 08:06:24.362397 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 08:06:24.368790 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 08:06:24.372651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4632 08:06:24.375544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4633 08:06:24.382194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 08:06:24.385486 Total UI for P1: 0, mck2ui 16
4635 08:06:24.388888 best dqsien dly found for B0: ( 0, 13, 10)
4636 08:06:24.389482 Total UI for P1: 0, mck2ui 16
4637 08:06:24.395568 best dqsien dly found for B1: ( 0, 13, 12)
4638 08:06:24.398754 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4639 08:06:24.401815 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4640 08:06:24.402373
4641 08:06:24.405188 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4642 08:06:24.408770 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4643 08:06:24.412082 [Gating] SW calibration Done
4644 08:06:24.412804 ==
4645 08:06:24.415542 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 08:06:24.418738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 08:06:24.419307 ==
4648 08:06:24.422113 RX Vref Scan: 0
4649 08:06:24.422683
4650 08:06:24.423057 RX Vref 0 -> 0, step: 1
4651 08:06:24.423397
4652 08:06:24.425252 RX Delay -230 -> 252, step: 16
4653 08:06:24.432425 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4654 08:06:24.435332 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4655 08:06:24.438745 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4656 08:06:24.441728 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4657 08:06:24.445564 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4658 08:06:24.452425 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4659 08:06:24.455445 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4660 08:06:24.458799 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4661 08:06:24.462129 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4662 08:06:24.465618 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4663 08:06:24.471774 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4664 08:06:24.475244 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4665 08:06:24.478536 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4666 08:06:24.482075 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4667 08:06:24.489039 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4668 08:06:24.492226 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4669 08:06:24.492784 ==
4670 08:06:24.495319 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 08:06:24.498792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 08:06:24.499351 ==
4673 08:06:24.502198 DQS Delay:
4674 08:06:24.502752 DQS0 = 0, DQS1 = 0
4675 08:06:24.503119 DQM Delay:
4676 08:06:24.505416 DQM0 = 51, DQM1 = 46
4677 08:06:24.505875 DQ Delay:
4678 08:06:24.508475 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4679 08:06:24.511832 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4680 08:06:24.515111 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4681 08:06:24.518353 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4682 08:06:24.518921
4683 08:06:24.519293
4684 08:06:24.519629 ==
4685 08:06:24.521578 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 08:06:24.528540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 08:06:24.529219 ==
4688 08:06:24.529600
4689 08:06:24.529937
4690 08:06:24.530259 TX Vref Scan disable
4691 08:06:24.532054 == TX Byte 0 ==
4692 08:06:24.535313 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4693 08:06:24.538836 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4694 08:06:24.542295 == TX Byte 1 ==
4695 08:06:24.545474 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 08:06:24.548850 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 08:06:24.552295 ==
4698 08:06:24.555744 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 08:06:24.559154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 08:06:24.559721 ==
4701 08:06:24.560087
4702 08:06:24.560420
4703 08:06:24.562083 TX Vref Scan disable
4704 08:06:24.562644 == TX Byte 0 ==
4705 08:06:24.568885 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 08:06:24.572020 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 08:06:24.572482 == TX Byte 1 ==
4708 08:06:24.579046 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 08:06:24.582198 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 08:06:24.582776
4711 08:06:24.583143 [DATLAT]
4712 08:06:24.585765 Freq=600, CH1 RK1
4713 08:06:24.586327
4714 08:06:24.586690 DATLAT Default: 0x9
4715 08:06:24.588841 0, 0xFFFF, sum = 0
4716 08:06:24.589448 1, 0xFFFF, sum = 0
4717 08:06:24.591863 2, 0xFFFF, sum = 0
4718 08:06:24.592328 3, 0xFFFF, sum = 0
4719 08:06:24.595615 4, 0xFFFF, sum = 0
4720 08:06:24.596182 5, 0xFFFF, sum = 0
4721 08:06:24.599084 6, 0xFFFF, sum = 0
4722 08:06:24.602033 7, 0xFFFF, sum = 0
4723 08:06:24.602603 8, 0x0, sum = 1
4724 08:06:24.602978 9, 0x0, sum = 2
4725 08:06:24.605288 10, 0x0, sum = 3
4726 08:06:24.605754 11, 0x0, sum = 4
4727 08:06:24.608616 best_step = 9
4728 08:06:24.609106
4729 08:06:24.609475 ==
4730 08:06:24.612105 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 08:06:24.615464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 08:06:24.616032 ==
4733 08:06:24.618704 RX Vref Scan: 0
4734 08:06:24.619266
4735 08:06:24.619628 RX Vref 0 -> 0, step: 1
4736 08:06:24.619966
4737 08:06:24.622020 RX Delay -179 -> 252, step: 8
4738 08:06:24.629046 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4739 08:06:24.632854 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4740 08:06:24.635669 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4741 08:06:24.639009 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4742 08:06:24.642345 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4743 08:06:24.649167 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4744 08:06:24.652357 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4745 08:06:24.655972 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4746 08:06:24.659408 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4747 08:06:24.662442 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4748 08:06:24.669082 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4749 08:06:24.672152 iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304
4750 08:06:24.675809 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4751 08:06:24.678720 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4752 08:06:24.685414 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4753 08:06:24.689131 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4754 08:06:24.689690 ==
4755 08:06:24.692555 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 08:06:24.695745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 08:06:24.696305 ==
4758 08:06:24.698792 DQS Delay:
4759 08:06:24.699352 DQS0 = 0, DQS1 = 0
4760 08:06:24.699721 DQM Delay:
4761 08:06:24.702323 DQM0 = 49, DQM1 = 43
4762 08:06:24.702878 DQ Delay:
4763 08:06:24.705462 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4764 08:06:24.708804 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4765 08:06:24.712145 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =36
4766 08:06:24.715342 DQ12 =56, DQ13 =48, DQ14 =48, DQ15 =52
4767 08:06:24.715899
4768 08:06:24.716264
4769 08:06:24.725568 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4770 08:06:24.726131 CH1 RK1: MR19=808, MR18=5E24
4771 08:06:24.732206 CH1_RK1: MR19=0x808, MR18=0x5E24, DQSOSC=392, MR23=63, INC=170, DEC=113
4772 08:06:24.735391 [RxdqsGatingPostProcess] freq 600
4773 08:06:24.741890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4774 08:06:24.745143 Pre-setting of DQS Precalculation
4775 08:06:24.748370 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4776 08:06:24.755470 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4777 08:06:24.765163 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4778 08:06:24.765706
4779 08:06:24.766063
4780 08:06:24.768589 [Calibration Summary] 1200 Mbps
4781 08:06:24.769068 CH 0, Rank 0
4782 08:06:24.772074 SW Impedance : PASS
4783 08:06:24.772532 DUTY Scan : NO K
4784 08:06:24.775435 ZQ Calibration : PASS
4785 08:06:24.778573 Jitter Meter : NO K
4786 08:06:24.779031 CBT Training : PASS
4787 08:06:24.782070 Write leveling : PASS
4788 08:06:24.782624 RX DQS gating : PASS
4789 08:06:24.785030 RX DQ/DQS(RDDQC) : PASS
4790 08:06:24.788544 TX DQ/DQS : PASS
4791 08:06:24.789129 RX DATLAT : PASS
4792 08:06:24.792029 RX DQ/DQS(Engine): PASS
4793 08:06:24.795398 TX OE : NO K
4794 08:06:24.795952 All Pass.
4795 08:06:24.796312
4796 08:06:24.796644 CH 0, Rank 1
4797 08:06:24.798759 SW Impedance : PASS
4798 08:06:24.801758 DUTY Scan : NO K
4799 08:06:24.802234 ZQ Calibration : PASS
4800 08:06:24.804853 Jitter Meter : NO K
4801 08:06:24.808575 CBT Training : PASS
4802 08:06:24.809160 Write leveling : PASS
4803 08:06:24.811695 RX DQS gating : PASS
4804 08:06:24.815054 RX DQ/DQS(RDDQC) : PASS
4805 08:06:24.815611 TX DQ/DQS : PASS
4806 08:06:24.818742 RX DATLAT : PASS
4807 08:06:24.821735 RX DQ/DQS(Engine): PASS
4808 08:06:24.822284 TX OE : NO K
4809 08:06:24.825127 All Pass.
4810 08:06:24.825678
4811 08:06:24.826038 CH 1, Rank 0
4812 08:06:24.828171 SW Impedance : PASS
4813 08:06:24.828727 DUTY Scan : NO K
4814 08:06:24.831580 ZQ Calibration : PASS
4815 08:06:24.834815 Jitter Meter : NO K
4816 08:06:24.835346 CBT Training : PASS
4817 08:06:24.837866 Write leveling : PASS
4818 08:06:24.841179 RX DQS gating : PASS
4819 08:06:24.841637 RX DQ/DQS(RDDQC) : PASS
4820 08:06:24.844686 TX DQ/DQS : PASS
4821 08:06:24.845292 RX DATLAT : PASS
4822 08:06:24.848214 RX DQ/DQS(Engine): PASS
4823 08:06:24.851342 TX OE : NO K
4824 08:06:24.851801 All Pass.
4825 08:06:24.852155
4826 08:06:24.852488 CH 1, Rank 1
4827 08:06:24.854647 SW Impedance : PASS
4828 08:06:24.858014 DUTY Scan : NO K
4829 08:06:24.858472 ZQ Calibration : PASS
4830 08:06:24.861269 Jitter Meter : NO K
4831 08:06:24.865071 CBT Training : PASS
4832 08:06:24.865649 Write leveling : PASS
4833 08:06:24.868002 RX DQS gating : PASS
4834 08:06:24.871226 RX DQ/DQS(RDDQC) : PASS
4835 08:06:24.871727 TX DQ/DQS : PASS
4836 08:06:24.874907 RX DATLAT : PASS
4837 08:06:24.878140 RX DQ/DQS(Engine): PASS
4838 08:06:24.878620 TX OE : NO K
4839 08:06:24.878986 All Pass.
4840 08:06:24.881492
4841 08:06:24.881945 DramC Write-DBI off
4842 08:06:24.885178 PER_BANK_REFRESH: Hybrid Mode
4843 08:06:24.885746 TX_TRACKING: ON
4844 08:06:24.895050 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4845 08:06:24.898427 [FAST_K] Save calibration result to emmc
4846 08:06:24.901352 dramc_set_vcore_voltage set vcore to 662500
4847 08:06:24.904762 Read voltage for 933, 3
4848 08:06:24.905350 Vio18 = 0
4849 08:06:24.908231 Vcore = 662500
4850 08:06:24.908795 Vdram = 0
4851 08:06:24.909193 Vddq = 0
4852 08:06:24.909532 Vmddr = 0
4853 08:06:24.914600 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4854 08:06:24.921424 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4855 08:06:24.921998 MEM_TYPE=3, freq_sel=17
4856 08:06:24.924789 sv_algorithm_assistance_LP4_1600
4857 08:06:24.927983 ============ PULL DRAM RESETB DOWN ============
4858 08:06:24.934701 ========== PULL DRAM RESETB DOWN end =========
4859 08:06:24.937496 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4860 08:06:24.940876 ===================================
4861 08:06:24.944497 LPDDR4 DRAM CONFIGURATION
4862 08:06:24.947622 ===================================
4863 08:06:24.948086 EX_ROW_EN[0] = 0x0
4864 08:06:24.951022 EX_ROW_EN[1] = 0x0
4865 08:06:24.951582 LP4Y_EN = 0x0
4866 08:06:24.954643 WORK_FSP = 0x0
4867 08:06:24.955100 WL = 0x3
4868 08:06:24.958086 RL = 0x3
4869 08:06:24.958547 BL = 0x2
4870 08:06:24.961059 RPST = 0x0
4871 08:06:24.961618 RD_PRE = 0x0
4872 08:06:24.964574 WR_PRE = 0x1
4873 08:06:24.967710 WR_PST = 0x0
4874 08:06:24.968288 DBI_WR = 0x0
4875 08:06:24.971190 DBI_RD = 0x0
4876 08:06:24.971706 OTF = 0x1
4877 08:06:24.974787 ===================================
4878 08:06:24.977770 ===================================
4879 08:06:24.978239 ANA top config
4880 08:06:24.980882 ===================================
4881 08:06:24.984523 DLL_ASYNC_EN = 0
4882 08:06:24.987882 ALL_SLAVE_EN = 1
4883 08:06:24.991608 NEW_RANK_MODE = 1
4884 08:06:24.994389 DLL_IDLE_MODE = 1
4885 08:06:24.994952 LP45_APHY_COMB_EN = 1
4886 08:06:24.997814 TX_ODT_DIS = 1
4887 08:06:25.001353 NEW_8X_MODE = 1
4888 08:06:25.004247 ===================================
4889 08:06:25.007781 ===================================
4890 08:06:25.010966 data_rate = 1866
4891 08:06:25.014299 CKR = 1
4892 08:06:25.014861 DQ_P2S_RATIO = 8
4893 08:06:25.017476 ===================================
4894 08:06:25.020958 CA_P2S_RATIO = 8
4895 08:06:25.024259 DQ_CA_OPEN = 0
4896 08:06:25.027596 DQ_SEMI_OPEN = 0
4897 08:06:25.030809 CA_SEMI_OPEN = 0
4898 08:06:25.034244 CA_FULL_RATE = 0
4899 08:06:25.034807 DQ_CKDIV4_EN = 1
4900 08:06:25.037564 CA_CKDIV4_EN = 1
4901 08:06:25.040923 CA_PREDIV_EN = 0
4902 08:06:25.044147 PH8_DLY = 0
4903 08:06:25.047602 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4904 08:06:25.051075 DQ_AAMCK_DIV = 4
4905 08:06:25.051534 CA_AAMCK_DIV = 4
4906 08:06:25.053896 CA_ADMCK_DIV = 4
4907 08:06:25.057355 DQ_TRACK_CA_EN = 0
4908 08:06:25.060655 CA_PICK = 933
4909 08:06:25.064183 CA_MCKIO = 933
4910 08:06:25.067634 MCKIO_SEMI = 0
4911 08:06:25.070609 PLL_FREQ = 3732
4912 08:06:25.071071 DQ_UI_PI_RATIO = 32
4913 08:06:25.074111 CA_UI_PI_RATIO = 0
4914 08:06:25.077316 ===================================
4915 08:06:25.080956 ===================================
4916 08:06:25.083850 memory_type:LPDDR4
4917 08:06:25.087529 GP_NUM : 10
4918 08:06:25.088094 SRAM_EN : 1
4919 08:06:25.090710 MD32_EN : 0
4920 08:06:25.094221 ===================================
4921 08:06:25.094682 [ANA_INIT] >>>>>>>>>>>>>>
4922 08:06:25.097580 <<<<<< [CONFIGURE PHASE]: ANA_TX
4923 08:06:25.100799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4924 08:06:25.103994 ===================================
4925 08:06:25.107413 data_rate = 1866,PCW = 0X8f00
4926 08:06:25.110813 ===================================
4927 08:06:25.113948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4928 08:06:25.120751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 08:06:25.127280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 08:06:25.130810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4931 08:06:25.134197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4932 08:06:25.137260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4933 08:06:25.140667 [ANA_INIT] flow start
4934 08:06:25.141270 [ANA_INIT] PLL >>>>>>>>
4935 08:06:25.143947 [ANA_INIT] PLL <<<<<<<<
4936 08:06:25.147336 [ANA_INIT] MIDPI >>>>>>>>
4937 08:06:25.147904 [ANA_INIT] MIDPI <<<<<<<<
4938 08:06:25.150947 [ANA_INIT] DLL >>>>>>>>
4939 08:06:25.153892 [ANA_INIT] flow end
4940 08:06:25.157531 ============ LP4 DIFF to SE enter ============
4941 08:06:25.160913 ============ LP4 DIFF to SE exit ============
4942 08:06:25.163956 [ANA_INIT] <<<<<<<<<<<<<
4943 08:06:25.167272 [Flow] Enable top DCM control >>>>>
4944 08:06:25.170492 [Flow] Enable top DCM control <<<<<
4945 08:06:25.173635 Enable DLL master slave shuffle
4946 08:06:25.177285 ==============================================================
4947 08:06:25.180277 Gating Mode config
4948 08:06:25.187342 ==============================================================
4949 08:06:25.187904 Config description:
4950 08:06:25.197018 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4951 08:06:25.203676 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4952 08:06:25.207572 SELPH_MODE 0: By rank 1: By Phase
4953 08:06:25.213910 ==============================================================
4954 08:06:25.217404 GAT_TRACK_EN = 1
4955 08:06:25.220087 RX_GATING_MODE = 2
4956 08:06:25.224078 RX_GATING_TRACK_MODE = 2
4957 08:06:25.227072 SELPH_MODE = 1
4958 08:06:25.230577 PICG_EARLY_EN = 1
4959 08:06:25.233805 VALID_LAT_VALUE = 1
4960 08:06:25.236822 ==============================================================
4961 08:06:25.240296 Enter into Gating configuration >>>>
4962 08:06:25.243310 Exit from Gating configuration <<<<
4963 08:06:25.246698 Enter into DVFS_PRE_config >>>>>
4964 08:06:25.260275 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4965 08:06:25.260852 Exit from DVFS_PRE_config <<<<<
4966 08:06:25.263790 Enter into PICG configuration >>>>
4967 08:06:25.267188 Exit from PICG configuration <<<<
4968 08:06:25.270461 [RX_INPUT] configuration >>>>>
4969 08:06:25.273352 [RX_INPUT] configuration <<<<<
4970 08:06:25.280004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4971 08:06:25.283391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4972 08:06:25.290222 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 08:06:25.296701 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 08:06:25.303496 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 08:06:25.310167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 08:06:25.313370 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4977 08:06:25.317068 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4978 08:06:25.319791 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4979 08:06:25.327127 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4980 08:06:25.330426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4981 08:06:25.333584 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4982 08:06:25.336692 ===================================
4983 08:06:25.339913 LPDDR4 DRAM CONFIGURATION
4984 08:06:25.343373 ===================================
4985 08:06:25.343952 EX_ROW_EN[0] = 0x0
4986 08:06:25.347046 EX_ROW_EN[1] = 0x0
4987 08:06:25.349811 LP4Y_EN = 0x0
4988 08:06:25.350290 WORK_FSP = 0x0
4989 08:06:25.353348 WL = 0x3
4990 08:06:25.353919 RL = 0x3
4991 08:06:25.356771 BL = 0x2
4992 08:06:25.357433 RPST = 0x0
4993 08:06:25.360114 RD_PRE = 0x0
4994 08:06:25.360678 WR_PRE = 0x1
4995 08:06:25.363263 WR_PST = 0x0
4996 08:06:25.363829 DBI_WR = 0x0
4997 08:06:25.366575 DBI_RD = 0x0
4998 08:06:25.367145 OTF = 0x1
4999 08:06:25.369849 ===================================
5000 08:06:25.373344 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5001 08:06:25.380185 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5002 08:06:25.383132 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 08:06:25.386410 ===================================
5004 08:06:25.389612 LPDDR4 DRAM CONFIGURATION
5005 08:06:25.393027 ===================================
5006 08:06:25.393601 EX_ROW_EN[0] = 0x10
5007 08:06:25.396496 EX_ROW_EN[1] = 0x0
5008 08:06:25.397088 LP4Y_EN = 0x0
5009 08:06:25.399339 WORK_FSP = 0x0
5010 08:06:25.402953 WL = 0x3
5011 08:06:25.403506 RL = 0x3
5012 08:06:25.406446 BL = 0x2
5013 08:06:25.407001 RPST = 0x0
5014 08:06:25.409429 RD_PRE = 0x0
5015 08:06:25.409891 WR_PRE = 0x1
5016 08:06:25.412845 WR_PST = 0x0
5017 08:06:25.413428 DBI_WR = 0x0
5018 08:06:25.416116 DBI_RD = 0x0
5019 08:06:25.416574 OTF = 0x1
5020 08:06:25.419550 ===================================
5021 08:06:25.426120 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5022 08:06:25.430056 nWR fixed to 30
5023 08:06:25.433589 [ModeRegInit_LP4] CH0 RK0
5024 08:06:25.434146 [ModeRegInit_LP4] CH0 RK1
5025 08:06:25.437028 [ModeRegInit_LP4] CH1 RK0
5026 08:06:25.439964 [ModeRegInit_LP4] CH1 RK1
5027 08:06:25.440423 match AC timing 9
5028 08:06:25.446517 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5029 08:06:25.450130 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5030 08:06:25.453633 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5031 08:06:25.460261 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5032 08:06:25.463533 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5033 08:06:25.464095 ==
5034 08:06:25.466817 Dram Type= 6, Freq= 0, CH_0, rank 0
5035 08:06:25.470101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5036 08:06:25.470665 ==
5037 08:06:25.476715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5038 08:06:25.483488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5039 08:06:25.486624 [CA 0] Center 38 (7~69) winsize 63
5040 08:06:25.490162 [CA 1] Center 38 (8~69) winsize 62
5041 08:06:25.493771 [CA 2] Center 35 (5~66) winsize 62
5042 08:06:25.496919 [CA 3] Center 34 (4~65) winsize 62
5043 08:06:25.500132 [CA 4] Center 34 (4~65) winsize 62
5044 08:06:25.503750 [CA 5] Center 33 (3~64) winsize 62
5045 08:06:25.504306
5046 08:06:25.506776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5047 08:06:25.507232
5048 08:06:25.510256 [CATrainingPosCal] consider 1 rank data
5049 08:06:25.513494 u2DelayCellTimex100 = 270/100 ps
5050 08:06:25.516842 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5051 08:06:25.520100 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5052 08:06:25.523339 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5053 08:06:25.526683 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5054 08:06:25.529862 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5055 08:06:25.533436 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5056 08:06:25.533994
5057 08:06:25.540121 CA PerBit enable=1, Macro0, CA PI delay=33
5058 08:06:25.540682
5059 08:06:25.543042 [CBTSetCACLKResult] CA Dly = 33
5060 08:06:25.543508 CS Dly: 6 (0~37)
5061 08:06:25.543873 ==
5062 08:06:25.546652 Dram Type= 6, Freq= 0, CH_0, rank 1
5063 08:06:25.549760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 08:06:25.550229 ==
5065 08:06:25.556805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 08:06:25.563091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5067 08:06:25.566864 [CA 0] Center 38 (8~69) winsize 62
5068 08:06:25.569849 [CA 1] Center 38 (8~69) winsize 62
5069 08:06:25.573212 [CA 2] Center 36 (6~66) winsize 61
5070 08:06:25.576808 [CA 3] Center 35 (5~66) winsize 62
5071 08:06:25.579973 [CA 4] Center 34 (4~65) winsize 62
5072 08:06:25.583353 [CA 5] Center 34 (4~64) winsize 61
5073 08:06:25.583921
5074 08:06:25.586658 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5075 08:06:25.587226
5076 08:06:25.589836 [CATrainingPosCal] consider 2 rank data
5077 08:06:25.592970 u2DelayCellTimex100 = 270/100 ps
5078 08:06:25.596471 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5079 08:06:25.599952 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 08:06:25.603382 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5081 08:06:25.606268 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5082 08:06:25.609566 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5083 08:06:25.616187 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5084 08:06:25.616752
5085 08:06:25.620071 CA PerBit enable=1, Macro0, CA PI delay=34
5086 08:06:25.620691
5087 08:06:25.622926 [CBTSetCACLKResult] CA Dly = 34
5088 08:06:25.623440 CS Dly: 7 (0~40)
5089 08:06:25.623812
5090 08:06:25.625907 ----->DramcWriteLeveling(PI) begin...
5091 08:06:25.626456 ==
5092 08:06:25.629506 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 08:06:25.633180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 08:06:25.636506 ==
5095 08:06:25.637097 Write leveling (Byte 0): 35 => 35
5096 08:06:25.639687 Write leveling (Byte 1): 30 => 30
5097 08:06:25.643030 DramcWriteLeveling(PI) end<-----
5098 08:06:25.643496
5099 08:06:25.643859 ==
5100 08:06:25.646368 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 08:06:25.653151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 08:06:25.653717 ==
5103 08:06:25.654092 [Gating] SW mode calibration
5104 08:06:25.663255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5105 08:06:25.666412 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5106 08:06:25.673121 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
5107 08:06:25.676277 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 08:06:25.679574 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 08:06:25.683145 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 08:06:25.689803 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 08:06:25.692875 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 08:06:25.696344 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5113 08:06:25.703041 0 14 28 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
5114 08:06:25.706178 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5115 08:06:25.709565 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 08:06:25.716215 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 08:06:25.719255 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 08:06:25.722711 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 08:06:25.729427 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 08:06:25.732912 0 15 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5121 08:06:25.735841 0 15 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
5122 08:06:25.742375 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5123 08:06:25.746390 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 08:06:25.749445 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 08:06:25.755961 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 08:06:25.759698 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 08:06:25.762516 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 08:06:25.769254 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5129 08:06:25.772788 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5130 08:06:25.776338 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 08:06:25.782910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 08:06:25.785815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 08:06:25.789634 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 08:06:25.796003 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 08:06:25.799760 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 08:06:25.802393 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 08:06:25.809069 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 08:06:25.812196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 08:06:25.815654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 08:06:25.822290 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 08:06:25.825707 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 08:06:25.828864 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 08:06:25.835275 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 08:06:25.838811 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5145 08:06:25.841805 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5146 08:06:25.845230 Total UI for P1: 0, mck2ui 16
5147 08:06:25.848883 best dqsien dly found for B0: ( 1, 2, 24)
5148 08:06:25.852281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 08:06:25.855563 Total UI for P1: 0, mck2ui 16
5150 08:06:25.859070 best dqsien dly found for B1: ( 1, 2, 28)
5151 08:06:25.862192 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5152 08:06:25.865244 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5153 08:06:25.868977
5154 08:06:25.872386 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5155 08:06:25.875692 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5156 08:06:25.878883 [Gating] SW calibration Done
5157 08:06:25.879437 ==
5158 08:06:25.882290 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 08:06:25.885721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 08:06:25.886282 ==
5161 08:06:25.886645 RX Vref Scan: 0
5162 08:06:25.886980
5163 08:06:25.888784 RX Vref 0 -> 0, step: 1
5164 08:06:25.889370
5165 08:06:25.892086 RX Delay -80 -> 252, step: 8
5166 08:06:25.895515 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5167 08:06:25.898768 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5168 08:06:25.905512 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5169 08:06:25.908501 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5170 08:06:25.911983 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5171 08:06:25.915676 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5172 08:06:25.918804 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5173 08:06:25.921646 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5174 08:06:25.928838 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5175 08:06:25.932210 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5176 08:06:25.935281 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5177 08:06:25.938599 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5178 08:06:25.942151 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5179 08:06:25.945123 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5180 08:06:25.952161 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5181 08:06:25.955245 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5182 08:06:25.955711 ==
5183 08:06:25.958503 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 08:06:25.961766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 08:06:25.962230 ==
5186 08:06:25.962591 DQS Delay:
5187 08:06:25.965025 DQS0 = 0, DQS1 = 0
5188 08:06:25.965483 DQM Delay:
5189 08:06:25.968800 DQM0 = 105, DQM1 = 90
5190 08:06:25.969405 DQ Delay:
5191 08:06:25.972296 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5192 08:06:25.975543 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5193 08:06:25.978487 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5194 08:06:25.981778 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5195 08:06:25.982337
5196 08:06:25.982698
5197 08:06:25.983027 ==
5198 08:06:25.984986 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 08:06:25.992120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 08:06:25.992678 ==
5201 08:06:25.993082
5202 08:06:25.993418
5203 08:06:25.993736 TX Vref Scan disable
5204 08:06:25.995499 == TX Byte 0 ==
5205 08:06:25.998699 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5206 08:06:26.002186 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5207 08:06:26.005367 == TX Byte 1 ==
5208 08:06:26.008832 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5209 08:06:26.015619 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5210 08:06:26.016175 ==
5211 08:06:26.018750 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 08:06:26.022371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 08:06:26.022834 ==
5214 08:06:26.023195
5215 08:06:26.023524
5216 08:06:26.025023 TX Vref Scan disable
5217 08:06:26.025477 == TX Byte 0 ==
5218 08:06:26.031965 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5219 08:06:26.035640 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5220 08:06:26.036200 == TX Byte 1 ==
5221 08:06:26.042130 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5222 08:06:26.045307 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5223 08:06:26.045763
5224 08:06:26.046121 [DATLAT]
5225 08:06:26.048409 Freq=933, CH0 RK0
5226 08:06:26.049022
5227 08:06:26.049508 DATLAT Default: 0xd
5228 08:06:26.051774 0, 0xFFFF, sum = 0
5229 08:06:26.052240 1, 0xFFFF, sum = 0
5230 08:06:26.055240 2, 0xFFFF, sum = 0
5231 08:06:26.055699 3, 0xFFFF, sum = 0
5232 08:06:26.058693 4, 0xFFFF, sum = 0
5233 08:06:26.059254 5, 0xFFFF, sum = 0
5234 08:06:26.061506 6, 0xFFFF, sum = 0
5235 08:06:26.064823 7, 0xFFFF, sum = 0
5236 08:06:26.065332 8, 0xFFFF, sum = 0
5237 08:06:26.068784 9, 0xFFFF, sum = 0
5238 08:06:26.069399 10, 0x0, sum = 1
5239 08:06:26.069771 11, 0x0, sum = 2
5240 08:06:26.071568 12, 0x0, sum = 3
5241 08:06:26.072027 13, 0x0, sum = 4
5242 08:06:26.075071 best_step = 11
5243 08:06:26.075526
5244 08:06:26.075884 ==
5245 08:06:26.078249 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 08:06:26.081899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 08:06:26.082456 ==
5248 08:06:26.085192 RX Vref Scan: 1
5249 08:06:26.085746
5250 08:06:26.086112 RX Vref 0 -> 0, step: 1
5251 08:06:26.086446
5252 08:06:26.088392 RX Delay -53 -> 252, step: 4
5253 08:06:26.088983
5254 08:06:26.091684 Set Vref, RX VrefLevel [Byte0]: 56
5255 08:06:26.095269 [Byte1]: 49
5256 08:06:26.099647
5257 08:06:26.100199 Final RX Vref Byte 0 = 56 to rank0
5258 08:06:26.102844 Final RX Vref Byte 1 = 49 to rank0
5259 08:06:26.105760 Final RX Vref Byte 0 = 56 to rank1
5260 08:06:26.109286 Final RX Vref Byte 1 = 49 to rank1==
5261 08:06:26.112692 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 08:06:26.119342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 08:06:26.119900 ==
5264 08:06:26.120263 DQS Delay:
5265 08:06:26.120596 DQS0 = 0, DQS1 = 0
5266 08:06:26.122338 DQM Delay:
5267 08:06:26.122795 DQM0 = 107, DQM1 = 91
5268 08:06:26.126216 DQ Delay:
5269 08:06:26.129619 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5270 08:06:26.132922 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5271 08:06:26.135983 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5272 08:06:26.139492 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =100
5273 08:06:26.140047
5274 08:06:26.140409
5275 08:06:26.145642 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5276 08:06:26.149180 CH0 RK0: MR19=505, MR18=2824
5277 08:06:26.155997 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5278 08:06:26.156562
5279 08:06:26.159167 ----->DramcWriteLeveling(PI) begin...
5280 08:06:26.159728 ==
5281 08:06:26.162609 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 08:06:26.165817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 08:06:26.166280 ==
5284 08:06:26.169307 Write leveling (Byte 0): 36 => 36
5285 08:06:26.172368 Write leveling (Byte 1): 30 => 30
5286 08:06:26.175729 DramcWriteLeveling(PI) end<-----
5287 08:06:26.176187
5288 08:06:26.176544 ==
5289 08:06:26.178889 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 08:06:26.182136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 08:06:26.185406 ==
5292 08:06:26.185818 [Gating] SW mode calibration
5293 08:06:26.195410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5294 08:06:26.199080 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5295 08:06:26.202254 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 08:06:26.209164 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 08:06:26.212679 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 08:06:26.215625 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 08:06:26.222383 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 08:06:26.225628 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 08:06:26.228814 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
5302 08:06:26.235761 0 14 28 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
5303 08:06:26.239005 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 08:06:26.242181 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 08:06:26.248645 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 08:06:26.251751 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 08:06:26.255224 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 08:06:26.261748 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 08:06:26.265204 0 15 24 | B1->B0 | 2727 2d2c | 0 1 | (0 0) (0 0)
5310 08:06:26.268457 0 15 28 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
5311 08:06:26.275609 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 08:06:26.278630 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 08:06:26.281616 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 08:06:26.288599 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 08:06:26.291600 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 08:06:26.295062 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 08:06:26.301726 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5318 08:06:26.305090 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5319 08:06:26.308705 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5320 08:06:26.315087 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 08:06:26.318398 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 08:06:26.321783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 08:06:26.325270 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 08:06:26.332305 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 08:06:26.335238 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 08:06:26.338566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 08:06:26.344874 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 08:06:26.348094 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 08:06:26.351862 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 08:06:26.358590 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 08:06:26.361838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 08:06:26.365386 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 08:06:26.371457 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5334 08:06:26.374759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5335 08:06:26.378465 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5336 08:06:26.381435 Total UI for P1: 0, mck2ui 16
5337 08:06:26.385112 best dqsien dly found for B1: ( 1, 2, 28)
5338 08:06:26.391390 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 08:06:26.391929 Total UI for P1: 0, mck2ui 16
5340 08:06:26.398467 best dqsien dly found for B0: ( 1, 2, 28)
5341 08:06:26.401679 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5342 08:06:26.405078 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5343 08:06:26.405631
5344 08:06:26.408491 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5345 08:06:26.411769 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 08:06:26.415074 [Gating] SW calibration Done
5347 08:06:26.415620 ==
5348 08:06:26.418638 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 08:06:26.421755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 08:06:26.422307 ==
5351 08:06:26.425066 RX Vref Scan: 0
5352 08:06:26.425630
5353 08:06:26.425992 RX Vref 0 -> 0, step: 1
5354 08:06:26.426326
5355 08:06:26.428497 RX Delay -80 -> 252, step: 8
5356 08:06:26.431715 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5357 08:06:26.438370 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5358 08:06:26.441796 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5359 08:06:26.444539 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5360 08:06:26.447977 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5361 08:06:26.451336 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5362 08:06:26.454658 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5363 08:06:26.461858 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5364 08:06:26.464771 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5365 08:06:26.468267 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5366 08:06:26.471521 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5367 08:06:26.474728 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5368 08:06:26.478142 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5369 08:06:26.484735 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5370 08:06:26.488139 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5371 08:06:26.491148 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5372 08:06:26.491603 ==
5373 08:06:26.494647 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 08:06:26.497908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 08:06:26.498363 ==
5376 08:06:26.501594 DQS Delay:
5377 08:06:26.502123 DQS0 = 0, DQS1 = 0
5378 08:06:26.502474 DQM Delay:
5379 08:06:26.504403 DQM0 = 102, DQM1 = 90
5380 08:06:26.504916 DQ Delay:
5381 08:06:26.508019 DQ0 =99, DQ1 =107, DQ2 =99, DQ3 =99
5382 08:06:26.511251 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =111
5383 08:06:26.514668 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5384 08:06:26.517868 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5385 08:06:26.518431
5386 08:06:26.518796
5387 08:06:26.521105 ==
5388 08:06:26.521665 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 08:06:26.528195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 08:06:26.528763 ==
5391 08:06:26.529172
5392 08:06:26.529509
5393 08:06:26.531229 TX Vref Scan disable
5394 08:06:26.531787 == TX Byte 0 ==
5395 08:06:26.534803 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5396 08:06:26.541421 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5397 08:06:26.541984 == TX Byte 1 ==
5398 08:06:26.544285 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5399 08:06:26.551182 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5400 08:06:26.551743 ==
5401 08:06:26.554335 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 08:06:26.557556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 08:06:26.558046 ==
5404 08:06:26.558408
5405 08:06:26.558741
5406 08:06:26.561416 TX Vref Scan disable
5407 08:06:26.564268 == TX Byte 0 ==
5408 08:06:26.567611 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5409 08:06:26.570841 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5410 08:06:26.574293 == TX Byte 1 ==
5411 08:06:26.577679 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5412 08:06:26.580905 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5413 08:06:26.581349
5414 08:06:26.581673 [DATLAT]
5415 08:06:26.584479 Freq=933, CH0 RK1
5416 08:06:26.585036
5417 08:06:26.587665 DATLAT Default: 0xb
5418 08:06:26.588190 0, 0xFFFF, sum = 0
5419 08:06:26.591064 1, 0xFFFF, sum = 0
5420 08:06:26.591593 2, 0xFFFF, sum = 0
5421 08:06:26.594205 3, 0xFFFF, sum = 0
5422 08:06:26.594625 4, 0xFFFF, sum = 0
5423 08:06:26.597428 5, 0xFFFF, sum = 0
5424 08:06:26.597853 6, 0xFFFF, sum = 0
5425 08:06:26.600917 7, 0xFFFF, sum = 0
5426 08:06:26.601383 8, 0xFFFF, sum = 0
5427 08:06:26.604295 9, 0xFFFF, sum = 0
5428 08:06:26.604821 10, 0x0, sum = 1
5429 08:06:26.607770 11, 0x0, sum = 2
5430 08:06:26.608313 12, 0x0, sum = 3
5431 08:06:26.610735 13, 0x0, sum = 4
5432 08:06:26.611157 best_step = 11
5433 08:06:26.611487
5434 08:06:26.611839 ==
5435 08:06:26.614325 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 08:06:26.617631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 08:06:26.618090 ==
5438 08:06:26.620836 RX Vref Scan: 0
5439 08:06:26.621399
5440 08:06:26.624107 RX Vref 0 -> 0, step: 1
5441 08:06:26.624633
5442 08:06:26.625214 RX Delay -53 -> 252, step: 4
5443 08:06:26.632512 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5444 08:06:26.635484 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5445 08:06:26.639070 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5446 08:06:26.642078 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5447 08:06:26.645566 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5448 08:06:26.652307 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5449 08:06:26.655692 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5450 08:06:26.658888 iDelay=199, Bit 7, Center 114 (31 ~ 198) 168
5451 08:06:26.662118 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5452 08:06:26.665370 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5453 08:06:26.672047 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5454 08:06:26.675511 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5455 08:06:26.678954 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5456 08:06:26.682150 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5457 08:06:26.685445 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5458 08:06:26.692363 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5459 08:06:26.692925 ==
5460 08:06:26.695293 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 08:06:26.698442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 08:06:26.698904 ==
5463 08:06:26.699263 DQS Delay:
5464 08:06:26.701795 DQS0 = 0, DQS1 = 0
5465 08:06:26.702396 DQM Delay:
5466 08:06:26.705170 DQM0 = 105, DQM1 = 91
5467 08:06:26.705723 DQ Delay:
5468 08:06:26.708649 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5469 08:06:26.711712 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =114
5470 08:06:26.715092 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =90
5471 08:06:26.718546 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5472 08:06:26.719104
5473 08:06:26.719462
5474 08:06:26.728634 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5475 08:06:26.729255 CH0 RK1: MR19=505, MR18=2708
5476 08:06:26.735239 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5477 08:06:26.738772 [RxdqsGatingPostProcess] freq 933
5478 08:06:26.745466 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5479 08:06:26.748598 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 08:06:26.752190 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 08:06:26.755545 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 08:06:26.758357 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 08:06:26.758929 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 08:06:26.761619 best DQS1 dly(2T, 0.5T) = (0, 10)
5485 08:06:26.765231 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 08:06:26.768279 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5487 08:06:26.771834 Pre-setting of DQS Precalculation
5488 08:06:26.778141 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5489 08:06:26.778610 ==
5490 08:06:26.781755 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 08:06:26.785164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 08:06:26.785739 ==
5493 08:06:26.791905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5494 08:06:26.798251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5495 08:06:26.801801 [CA 0] Center 37 (7~68) winsize 62
5496 08:06:26.804870 [CA 1] Center 37 (7~68) winsize 62
5497 08:06:26.808387 [CA 2] Center 36 (6~66) winsize 61
5498 08:06:26.811123 [CA 3] Center 35 (5~65) winsize 61
5499 08:06:26.814608 [CA 4] Center 35 (5~65) winsize 61
5500 08:06:26.818329 [CA 5] Center 34 (4~65) winsize 62
5501 08:06:26.818916
5502 08:06:26.821421 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5503 08:06:26.821994
5504 08:06:26.824577 [CATrainingPosCal] consider 1 rank data
5505 08:06:26.827875 u2DelayCellTimex100 = 270/100 ps
5506 08:06:26.831200 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5507 08:06:26.834607 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5508 08:06:26.837977 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5509 08:06:26.841469 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5510 08:06:26.845245 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5511 08:06:26.847919 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5512 08:06:26.848377
5513 08:06:26.851356 CA PerBit enable=1, Macro0, CA PI delay=34
5514 08:06:26.854790
5515 08:06:26.855343 [CBTSetCACLKResult] CA Dly = 34
5516 08:06:26.858009 CS Dly: 6 (0~37)
5517 08:06:26.858562 ==
5518 08:06:26.861372 Dram Type= 6, Freq= 0, CH_1, rank 1
5519 08:06:26.864653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 08:06:26.865307 ==
5521 08:06:26.871356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 08:06:26.877963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 08:06:26.881349 [CA 0] Center 38 (8~68) winsize 61
5524 08:06:26.884997 [CA 1] Center 38 (7~69) winsize 63
5525 08:06:26.888384 [CA 2] Center 36 (6~66) winsize 61
5526 08:06:26.891384 [CA 3] Center 35 (5~65) winsize 61
5527 08:06:26.894982 [CA 4] Center 35 (5~65) winsize 61
5528 08:06:26.897990 [CA 5] Center 34 (4~64) winsize 61
5529 08:06:26.898452
5530 08:06:26.901626 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 08:06:26.902185
5532 08:06:26.904722 [CATrainingPosCal] consider 2 rank data
5533 08:06:26.908250 u2DelayCellTimex100 = 270/100 ps
5534 08:06:26.911119 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5535 08:06:26.914765 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5536 08:06:26.917950 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5537 08:06:26.921265 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5538 08:06:26.924834 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5539 08:06:26.928042 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5540 08:06:26.928720
5541 08:06:26.931238 CA PerBit enable=1, Macro0, CA PI delay=34
5542 08:06:26.934807
5543 08:06:26.935360 [CBTSetCACLKResult] CA Dly = 34
5544 08:06:26.938670 CS Dly: 7 (0~39)
5545 08:06:26.939223
5546 08:06:26.941224 ----->DramcWriteLeveling(PI) begin...
5547 08:06:26.941716 ==
5548 08:06:26.944554 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 08:06:26.947843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 08:06:26.948320 ==
5551 08:06:26.951510 Write leveling (Byte 0): 27 => 27
5552 08:06:26.954799 Write leveling (Byte 1): 30 => 30
5553 08:06:26.957919 DramcWriteLeveling(PI) end<-----
5554 08:06:26.958472
5555 08:06:26.958835 ==
5556 08:06:26.961301 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 08:06:26.964522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 08:06:26.965021 ==
5559 08:06:26.967978 [Gating] SW mode calibration
5560 08:06:26.974690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5561 08:06:26.981349 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5562 08:06:26.984663 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 08:06:26.991567 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 08:06:26.994719 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 08:06:26.997809 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 08:06:27.005014 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 08:06:27.007991 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 08:06:27.011496 0 14 24 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 0)
5569 08:06:27.014874 0 14 28 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
5570 08:06:27.021428 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 08:06:27.024460 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 08:06:27.028208 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 08:06:27.034581 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 08:06:27.037774 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 08:06:27.041353 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 08:06:27.047582 0 15 24 | B1->B0 | 2626 2f2e | 0 1 | (0 0) (0 0)
5577 08:06:27.051223 0 15 28 | B1->B0 | 4141 3f3f | 0 0 | (0 0) (0 0)
5578 08:06:27.054987 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 08:06:27.061313 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 08:06:27.064923 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 08:06:27.067909 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 08:06:27.074667 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 08:06:27.078206 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 08:06:27.081088 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5585 08:06:27.088021 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5586 08:06:27.091341 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 08:06:27.094988 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 08:06:27.101286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 08:06:27.104678 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 08:06:27.108368 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 08:06:27.114663 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 08:06:27.117660 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 08:06:27.121068 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 08:06:27.127616 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 08:06:27.131178 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 08:06:27.134926 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 08:06:27.140908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 08:06:27.144427 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 08:06:27.147492 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 08:06:27.150783 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5601 08:06:27.157513 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 08:06:27.160625 Total UI for P1: 0, mck2ui 16
5603 08:06:27.164345 best dqsien dly found for B0: ( 1, 2, 24)
5604 08:06:27.167801 Total UI for P1: 0, mck2ui 16
5605 08:06:27.171205 best dqsien dly found for B1: ( 1, 2, 26)
5606 08:06:27.174299 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5607 08:06:27.177459 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5608 08:06:27.177916
5609 08:06:27.180802 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 08:06:27.184489 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5611 08:06:27.187773 [Gating] SW calibration Done
5612 08:06:27.188328 ==
5613 08:06:27.190959 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 08:06:27.193989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 08:06:27.194546 ==
5616 08:06:27.197633 RX Vref Scan: 0
5617 08:06:27.198191
5618 08:06:27.198557 RX Vref 0 -> 0, step: 1
5619 08:06:27.200885
5620 08:06:27.201479 RX Delay -80 -> 252, step: 8
5621 08:06:27.207546 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5622 08:06:27.211080 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5623 08:06:27.214158 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5624 08:06:27.217300 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5625 08:06:27.220759 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5626 08:06:27.224635 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5627 08:06:27.230791 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5628 08:06:27.234108 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5629 08:06:27.237577 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5630 08:06:27.240736 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5631 08:06:27.244013 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5632 08:06:27.247094 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5633 08:06:27.253868 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5634 08:06:27.256818 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5635 08:06:27.260270 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5636 08:06:27.263776 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5637 08:06:27.264369 ==
5638 08:06:27.266965 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 08:06:27.273627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 08:06:27.274233 ==
5641 08:06:27.274611 DQS Delay:
5642 08:06:27.277134 DQS0 = 0, DQS1 = 0
5643 08:06:27.277589 DQM Delay:
5644 08:06:27.277948 DQM0 = 104, DQM1 = 96
5645 08:06:27.280098 DQ Delay:
5646 08:06:27.283962 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5647 08:06:27.287262 DQ4 =103, DQ5 =111, DQ6 =119, DQ7 =103
5648 08:06:27.290086 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5649 08:06:27.293617 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5650 08:06:27.294263
5651 08:06:27.294636
5652 08:06:27.294972 ==
5653 08:06:27.297054 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 08:06:27.300268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 08:06:27.300828 ==
5656 08:06:27.301254
5657 08:06:27.301591
5658 08:06:27.303788 TX Vref Scan disable
5659 08:06:27.307137 == TX Byte 0 ==
5660 08:06:27.310473 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5661 08:06:27.313647 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5662 08:06:27.317004 == TX Byte 1 ==
5663 08:06:27.320720 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5664 08:06:27.323916 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5665 08:06:27.324473 ==
5666 08:06:27.327032 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 08:06:27.333561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 08:06:27.334149 ==
5669 08:06:27.334563
5670 08:06:27.334901
5671 08:06:27.335218 TX Vref Scan disable
5672 08:06:27.337514 == TX Byte 0 ==
5673 08:06:27.340883 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 08:06:27.344393 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 08:06:27.347411 == TX Byte 1 ==
5676 08:06:27.350688 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5677 08:06:27.357396 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5678 08:06:27.357936
5679 08:06:27.358293 [DATLAT]
5680 08:06:27.358684 Freq=933, CH1 RK0
5681 08:06:27.359016
5682 08:06:27.360680 DATLAT Default: 0xd
5683 08:06:27.361188 0, 0xFFFF, sum = 0
5684 08:06:27.363990 1, 0xFFFF, sum = 0
5685 08:06:27.364474 2, 0xFFFF, sum = 0
5686 08:06:27.367022 3, 0xFFFF, sum = 0
5687 08:06:27.370890 4, 0xFFFF, sum = 0
5688 08:06:27.371455 5, 0xFFFF, sum = 0
5689 08:06:27.373758 6, 0xFFFF, sum = 0
5690 08:06:27.374221 7, 0xFFFF, sum = 0
5691 08:06:27.377520 8, 0xFFFF, sum = 0
5692 08:06:27.377980 9, 0xFFFF, sum = 0
5693 08:06:27.380712 10, 0x0, sum = 1
5694 08:06:27.381332 11, 0x0, sum = 2
5695 08:06:27.381707 12, 0x0, sum = 3
5696 08:06:27.384224 13, 0x0, sum = 4
5697 08:06:27.384792 best_step = 11
5698 08:06:27.385322
5699 08:06:27.387159 ==
5700 08:06:27.387716 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 08:06:27.394044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 08:06:27.394607 ==
5703 08:06:27.394973 RX Vref Scan: 1
5704 08:06:27.395308
5705 08:06:27.397241 RX Vref 0 -> 0, step: 1
5706 08:06:27.397798
5707 08:06:27.400679 RX Delay -53 -> 252, step: 4
5708 08:06:27.401285
5709 08:06:27.404067 Set Vref, RX VrefLevel [Byte0]: 51
5710 08:06:27.407340 [Byte1]: 59
5711 08:06:27.407896
5712 08:06:27.410979 Final RX Vref Byte 0 = 51 to rank0
5713 08:06:27.413739 Final RX Vref Byte 1 = 59 to rank0
5714 08:06:27.417372 Final RX Vref Byte 0 = 51 to rank1
5715 08:06:27.420704 Final RX Vref Byte 1 = 59 to rank1==
5716 08:06:27.423982 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 08:06:27.426975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 08:06:27.427440 ==
5719 08:06:27.430500 DQS Delay:
5720 08:06:27.431061 DQS0 = 0, DQS1 = 0
5721 08:06:27.433809 DQM Delay:
5722 08:06:27.434358 DQM0 = 104, DQM1 = 97
5723 08:06:27.434725 DQ Delay:
5724 08:06:27.437423 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5725 08:06:27.444077 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5726 08:06:27.444659 DQ8 =90, DQ9 =84, DQ10 =98, DQ11 =92
5727 08:06:27.450158 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =102
5728 08:06:27.450680
5729 08:06:27.451054
5730 08:06:27.457087 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5731 08:06:27.461025 CH1 RK0: MR19=505, MR18=1A33
5732 08:06:27.467510 CH1_RK0: MR19=0x505, MR18=0x1A33, DQSOSC=405, MR23=63, INC=66, DEC=44
5733 08:06:27.468069
5734 08:06:27.470297 ----->DramcWriteLeveling(PI) begin...
5735 08:06:27.470861 ==
5736 08:06:27.473485 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 08:06:27.476972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 08:06:27.477542 ==
5739 08:06:27.480184 Write leveling (Byte 0): 26 => 26
5740 08:06:27.483561 Write leveling (Byte 1): 29 => 29
5741 08:06:27.487015 DramcWriteLeveling(PI) end<-----
5742 08:06:27.487591
5743 08:06:27.487960 ==
5744 08:06:27.490308 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 08:06:27.493802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 08:06:27.494364 ==
5747 08:06:27.497090 [Gating] SW mode calibration
5748 08:06:27.503545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5749 08:06:27.510349 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5750 08:06:27.513769 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 08:06:27.520338 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 08:06:27.523518 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 08:06:27.526827 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 08:06:27.533421 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 08:06:27.536901 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 08:06:27.540393 0 14 24 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
5757 08:06:27.546569 0 14 28 | B1->B0 | 2323 2525 | 0 1 | (1 0) (1 0)
5758 08:06:27.549906 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5759 08:06:27.553353 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 08:06:27.560049 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 08:06:27.563416 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 08:06:27.566739 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 08:06:27.569824 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 08:06:27.576640 0 15 24 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
5765 08:06:27.580002 0 15 28 | B1->B0 | 4444 3939 | 0 0 | (0 0) (1 1)
5766 08:06:27.582995 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5767 08:06:27.589738 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 08:06:27.593135 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 08:06:27.596433 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 08:06:27.603271 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 08:06:27.606778 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 08:06:27.609918 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5773 08:06:27.616519 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5774 08:06:27.620292 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 08:06:27.623525 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 08:06:27.630087 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 08:06:27.633335 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 08:06:27.636675 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 08:06:27.643721 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 08:06:27.646391 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 08:06:27.649626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 08:06:27.656594 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 08:06:27.659709 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 08:06:27.663105 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 08:06:27.669628 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 08:06:27.673365 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 08:06:27.676310 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 08:06:27.682874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5789 08:06:27.686200 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5790 08:06:27.689560 Total UI for P1: 0, mck2ui 16
5791 08:06:27.692856 best dqsien dly found for B1: ( 1, 2, 24)
5792 08:06:27.696316 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 08:06:27.699270 Total UI for P1: 0, mck2ui 16
5794 08:06:27.702971 best dqsien dly found for B0: ( 1, 2, 26)
5795 08:06:27.706433 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5796 08:06:27.709473 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5797 08:06:27.710028
5798 08:06:27.712707 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 08:06:27.719641 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5800 08:06:27.720202 [Gating] SW calibration Done
5801 08:06:27.720566 ==
5802 08:06:27.722733 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 08:06:27.729571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 08:06:27.730127 ==
5805 08:06:27.730493 RX Vref Scan: 0
5806 08:06:27.730835
5807 08:06:27.732873 RX Vref 0 -> 0, step: 1
5808 08:06:27.733460
5809 08:06:27.736308 RX Delay -80 -> 252, step: 8
5810 08:06:27.739589 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5811 08:06:27.742789 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5812 08:06:27.746608 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5813 08:06:27.749420 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5814 08:06:27.756371 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5815 08:06:27.759555 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5816 08:06:27.762996 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5817 08:06:27.766170 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5818 08:06:27.769365 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5819 08:06:27.773060 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5820 08:06:27.779563 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5821 08:06:27.783018 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5822 08:06:27.785968 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5823 08:06:27.789831 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5824 08:06:27.792803 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5825 08:06:27.799404 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5826 08:06:27.799952 ==
5827 08:06:27.802924 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 08:06:27.805804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 08:06:27.806269 ==
5830 08:06:27.806634 DQS Delay:
5831 08:06:27.809306 DQS0 = 0, DQS1 = 0
5832 08:06:27.809874 DQM Delay:
5833 08:06:27.812872 DQM0 = 103, DQM1 = 94
5834 08:06:27.813459 DQ Delay:
5835 08:06:27.816094 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5836 08:06:27.819253 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5837 08:06:27.822609 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5838 08:06:27.825999 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5839 08:06:27.826567
5840 08:06:27.826933
5841 08:06:27.827266 ==
5842 08:06:27.829126 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 08:06:27.836294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 08:06:27.836854 ==
5845 08:06:27.837245
5846 08:06:27.837585
5847 08:06:27.837909 TX Vref Scan disable
5848 08:06:27.839468 == TX Byte 0 ==
5849 08:06:27.842679 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 08:06:27.849340 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 08:06:27.849814 == TX Byte 1 ==
5852 08:06:27.852553 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5853 08:06:27.856045 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5854 08:06:27.859418 ==
5855 08:06:27.862839 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 08:06:27.866198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 08:06:27.866749 ==
5858 08:06:27.867117
5859 08:06:27.867457
5860 08:06:27.869104 TX Vref Scan disable
5861 08:06:27.869569 == TX Byte 0 ==
5862 08:06:27.876258 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 08:06:27.878923 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 08:06:27.879342 == TX Byte 1 ==
5865 08:06:27.886070 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5866 08:06:27.889449 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5867 08:06:27.889999
5868 08:06:27.890369 [DATLAT]
5869 08:06:27.892609 Freq=933, CH1 RK1
5870 08:06:27.893194
5871 08:06:27.893566 DATLAT Default: 0xb
5872 08:06:27.895808 0, 0xFFFF, sum = 0
5873 08:06:27.896369 1, 0xFFFF, sum = 0
5874 08:06:27.898861 2, 0xFFFF, sum = 0
5875 08:06:27.899325 3, 0xFFFF, sum = 0
5876 08:06:27.902693 4, 0xFFFF, sum = 0
5877 08:06:27.903252 5, 0xFFFF, sum = 0
5878 08:06:27.905471 6, 0xFFFF, sum = 0
5879 08:06:27.909062 7, 0xFFFF, sum = 0
5880 08:06:27.909619 8, 0xFFFF, sum = 0
5881 08:06:27.912469 9, 0xFFFF, sum = 0
5882 08:06:27.913222 10, 0x0, sum = 1
5883 08:06:27.913662 11, 0x0, sum = 2
5884 08:06:27.915777 12, 0x0, sum = 3
5885 08:06:27.916351 13, 0x0, sum = 4
5886 08:06:27.918935 best_step = 11
5887 08:06:27.919459
5888 08:06:27.919831 ==
5889 08:06:27.922373 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 08:06:27.925552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 08:06:27.926107 ==
5892 08:06:27.928908 RX Vref Scan: 0
5893 08:06:27.929404
5894 08:06:27.929764 RX Vref 0 -> 0, step: 1
5895 08:06:27.932305
5896 08:06:27.932765 RX Delay -53 -> 252, step: 4
5897 08:06:27.939873 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5898 08:06:27.942936 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5899 08:06:27.946435 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5900 08:06:27.949367 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5901 08:06:27.952737 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5902 08:06:27.959871 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5903 08:06:27.963087 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5904 08:06:27.966063 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5905 08:06:27.969991 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5906 08:06:27.973064 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5907 08:06:27.979551 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5908 08:06:27.982966 iDelay=199, Bit 11, Center 92 (3 ~ 182) 180
5909 08:06:27.986168 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5910 08:06:27.989455 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5911 08:06:27.993047 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5912 08:06:27.999926 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5913 08:06:28.000486 ==
5914 08:06:28.002989 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 08:06:28.005918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 08:06:28.006475 ==
5917 08:06:28.006841 DQS Delay:
5918 08:06:28.009604 DQS0 = 0, DQS1 = 0
5919 08:06:28.010157 DQM Delay:
5920 08:06:28.012775 DQM0 = 105, DQM1 = 97
5921 08:06:28.013366 DQ Delay:
5922 08:06:28.015991 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5923 08:06:28.019196 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =104
5924 08:06:28.023076 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =92
5925 08:06:28.026000 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5926 08:06:28.026480
5927 08:06:28.026845
5928 08:06:28.036124 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5929 08:06:28.036685 CH1 RK1: MR19=504, MR18=20FD
5930 08:06:28.042970 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5931 08:06:28.045932 [RxdqsGatingPostProcess] freq 933
5932 08:06:28.052880 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 08:06:28.056377 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 08:06:28.059531 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 08:06:28.062834 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 08:06:28.066170 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 08:06:28.069563 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 08:06:28.070129 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 08:06:28.072677 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 08:06:28.076169 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 08:06:28.079479 Pre-setting of DQS Precalculation
5942 08:06:28.086199 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 08:06:28.093017 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 08:06:28.099787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 08:06:28.100349
5946 08:06:28.100713
5947 08:06:28.102907 [Calibration Summary] 1866 Mbps
5948 08:06:28.103467 CH 0, Rank 0
5949 08:06:28.106407 SW Impedance : PASS
5950 08:06:28.109728 DUTY Scan : NO K
5951 08:06:28.110288 ZQ Calibration : PASS
5952 08:06:28.113028 Jitter Meter : NO K
5953 08:06:28.116428 CBT Training : PASS
5954 08:06:28.117017 Write leveling : PASS
5955 08:06:28.119561 RX DQS gating : PASS
5956 08:06:28.122839 RX DQ/DQS(RDDQC) : PASS
5957 08:06:28.123394 TX DQ/DQS : PASS
5958 08:06:28.125992 RX DATLAT : PASS
5959 08:06:28.129266 RX DQ/DQS(Engine): PASS
5960 08:06:28.129728 TX OE : NO K
5961 08:06:28.130092 All Pass.
5962 08:06:28.133089
5963 08:06:28.133640 CH 0, Rank 1
5964 08:06:28.135942 SW Impedance : PASS
5965 08:06:28.136413 DUTY Scan : NO K
5966 08:06:28.139496 ZQ Calibration : PASS
5967 08:06:28.140051 Jitter Meter : NO K
5968 08:06:28.143051 CBT Training : PASS
5969 08:06:28.146036 Write leveling : PASS
5970 08:06:28.146601 RX DQS gating : PASS
5971 08:06:28.149249 RX DQ/DQS(RDDQC) : PASS
5972 08:06:28.152965 TX DQ/DQS : PASS
5973 08:06:28.153660 RX DATLAT : PASS
5974 08:06:28.155839 RX DQ/DQS(Engine): PASS
5975 08:06:28.159390 TX OE : NO K
5976 08:06:28.159954 All Pass.
5977 08:06:28.160314
5978 08:06:28.160649 CH 1, Rank 0
5979 08:06:28.162519 SW Impedance : PASS
5980 08:06:28.166042 DUTY Scan : NO K
5981 08:06:28.166600 ZQ Calibration : PASS
5982 08:06:28.169629 Jitter Meter : NO K
5983 08:06:28.172739 CBT Training : PASS
5984 08:06:28.173346 Write leveling : PASS
5985 08:06:28.176048 RX DQS gating : PASS
5986 08:06:28.179412 RX DQ/DQS(RDDQC) : PASS
5987 08:06:28.179866 TX DQ/DQS : PASS
5988 08:06:28.182780 RX DATLAT : PASS
5989 08:06:28.185884 RX DQ/DQS(Engine): PASS
5990 08:06:28.186342 TX OE : NO K
5991 08:06:28.186703 All Pass.
5992 08:06:28.187041
5993 08:06:28.189493 CH 1, Rank 1
5994 08:06:28.192796 SW Impedance : PASS
5995 08:06:28.193394 DUTY Scan : NO K
5996 08:06:28.195901 ZQ Calibration : PASS
5997 08:06:28.196358 Jitter Meter : NO K
5998 08:06:28.199139 CBT Training : PASS
5999 08:06:28.202629 Write leveling : PASS
6000 08:06:28.203260 RX DQS gating : PASS
6001 08:06:28.205897 RX DQ/DQS(RDDQC) : PASS
6002 08:06:28.209422 TX DQ/DQS : PASS
6003 08:06:28.209984 RX DATLAT : PASS
6004 08:06:28.212326 RX DQ/DQS(Engine): PASS
6005 08:06:28.216451 TX OE : NO K
6006 08:06:28.217068 All Pass.
6007 08:06:28.217441
6008 08:06:28.217778 DramC Write-DBI off
6009 08:06:28.219074 PER_BANK_REFRESH: Hybrid Mode
6010 08:06:28.222722 TX_TRACKING: ON
6011 08:06:28.229028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 08:06:28.232319 [FAST_K] Save calibration result to emmc
6013 08:06:28.239128 dramc_set_vcore_voltage set vcore to 650000
6014 08:06:28.239680 Read voltage for 400, 6
6015 08:06:28.242294 Vio18 = 0
6016 08:06:28.242751 Vcore = 650000
6017 08:06:28.243166 Vdram = 0
6018 08:06:28.246018 Vddq = 0
6019 08:06:28.246474 Vmddr = 0
6020 08:06:28.249084 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 08:06:28.255687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 08:06:28.259104 MEM_TYPE=3, freq_sel=20
6023 08:06:28.262193 sv_algorithm_assistance_LP4_800
6024 08:06:28.265557 ============ PULL DRAM RESETB DOWN ============
6025 08:06:28.268925 ========== PULL DRAM RESETB DOWN end =========
6026 08:06:28.272565 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 08:06:28.275631 ===================================
6028 08:06:28.279603 LPDDR4 DRAM CONFIGURATION
6029 08:06:28.282136 ===================================
6030 08:06:28.285501 EX_ROW_EN[0] = 0x0
6031 08:06:28.285958 EX_ROW_EN[1] = 0x0
6032 08:06:28.288883 LP4Y_EN = 0x0
6033 08:06:28.289464 WORK_FSP = 0x0
6034 08:06:28.292482 WL = 0x2
6035 08:06:28.293084 RL = 0x2
6036 08:06:28.295810 BL = 0x2
6037 08:06:28.296282 RPST = 0x0
6038 08:06:28.298697 RD_PRE = 0x0
6039 08:06:28.299150 WR_PRE = 0x1
6040 08:06:28.302248 WR_PST = 0x0
6041 08:06:28.305483 DBI_WR = 0x0
6042 08:06:28.305940 DBI_RD = 0x0
6043 08:06:28.308541 OTF = 0x1
6044 08:06:28.312180 ===================================
6045 08:06:28.315898 ===================================
6046 08:06:28.316461 ANA top config
6047 08:06:28.318810 ===================================
6048 08:06:28.322213 DLL_ASYNC_EN = 0
6049 08:06:28.322772 ALL_SLAVE_EN = 1
6050 08:06:28.325379 NEW_RANK_MODE = 1
6051 08:06:28.328601 DLL_IDLE_MODE = 1
6052 08:06:28.332209 LP45_APHY_COMB_EN = 1
6053 08:06:28.335527 TX_ODT_DIS = 1
6054 08:06:28.336088 NEW_8X_MODE = 1
6055 08:06:28.338878 ===================================
6056 08:06:28.342265 ===================================
6057 08:06:28.345313 data_rate = 800
6058 08:06:28.348504 CKR = 1
6059 08:06:28.352060 DQ_P2S_RATIO = 4
6060 08:06:28.355235 ===================================
6061 08:06:28.358785 CA_P2S_RATIO = 4
6062 08:06:28.362068 DQ_CA_OPEN = 0
6063 08:06:28.362563 DQ_SEMI_OPEN = 1
6064 08:06:28.365343 CA_SEMI_OPEN = 1
6065 08:06:28.368539 CA_FULL_RATE = 0
6066 08:06:28.372107 DQ_CKDIV4_EN = 0
6067 08:06:28.375681 CA_CKDIV4_EN = 1
6068 08:06:28.376288 CA_PREDIV_EN = 0
6069 08:06:28.378367 PH8_DLY = 0
6070 08:06:28.382138 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 08:06:28.385505 DQ_AAMCK_DIV = 0
6072 08:06:28.388529 CA_AAMCK_DIV = 0
6073 08:06:28.392149 CA_ADMCK_DIV = 4
6074 08:06:28.392709 DQ_TRACK_CA_EN = 0
6075 08:06:28.395754 CA_PICK = 800
6076 08:06:28.399257 CA_MCKIO = 400
6077 08:06:28.402147 MCKIO_SEMI = 400
6078 08:06:28.405070 PLL_FREQ = 3016
6079 08:06:28.408771 DQ_UI_PI_RATIO = 32
6080 08:06:28.412156 CA_UI_PI_RATIO = 32
6081 08:06:28.415340 ===================================
6082 08:06:28.418773 ===================================
6083 08:06:28.419344 memory_type:LPDDR4
6084 08:06:28.422073 GP_NUM : 10
6085 08:06:28.425522 SRAM_EN : 1
6086 08:06:28.426089 MD32_EN : 0
6087 08:06:28.428676 ===================================
6088 08:06:28.432332 [ANA_INIT] >>>>>>>>>>>>>>
6089 08:06:28.435144 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 08:06:28.438549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 08:06:28.442234 ===================================
6092 08:06:28.445577 data_rate = 800,PCW = 0X7400
6093 08:06:28.449023 ===================================
6094 08:06:28.451790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 08:06:28.454953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 08:06:28.468539 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 08:06:28.472080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 08:06:28.475205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 08:06:28.478469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 08:06:28.482024 [ANA_INIT] flow start
6101 08:06:28.485243 [ANA_INIT] PLL >>>>>>>>
6102 08:06:28.485702 [ANA_INIT] PLL <<<<<<<<
6103 08:06:28.488305 [ANA_INIT] MIDPI >>>>>>>>
6104 08:06:28.491919 [ANA_INIT] MIDPI <<<<<<<<
6105 08:06:28.492479 [ANA_INIT] DLL >>>>>>>>
6106 08:06:28.495676 [ANA_INIT] flow end
6107 08:06:28.498525 ============ LP4 DIFF to SE enter ============
6108 08:06:28.501496 ============ LP4 DIFF to SE exit ============
6109 08:06:28.505317 [ANA_INIT] <<<<<<<<<<<<<
6110 08:06:28.508389 [Flow] Enable top DCM control >>>>>
6111 08:06:28.511997 [Flow] Enable top DCM control <<<<<
6112 08:06:28.514963 Enable DLL master slave shuffle
6113 08:06:28.521998 ==============================================================
6114 08:06:28.522565 Gating Mode config
6115 08:06:28.528977 ==============================================================
6116 08:06:28.529573 Config description:
6117 08:06:28.538550 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 08:06:28.545193 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 08:06:28.552007 SELPH_MODE 0: By rank 1: By Phase
6120 08:06:28.555146 ==============================================================
6121 08:06:28.558518 GAT_TRACK_EN = 0
6122 08:06:28.561476 RX_GATING_MODE = 2
6123 08:06:28.565443 RX_GATING_TRACK_MODE = 2
6124 08:06:28.568713 SELPH_MODE = 1
6125 08:06:28.571606 PICG_EARLY_EN = 1
6126 08:06:28.574919 VALID_LAT_VALUE = 1
6127 08:06:28.578185 ==============================================================
6128 08:06:28.581603 Enter into Gating configuration >>>>
6129 08:06:28.585182 Exit from Gating configuration <<<<
6130 08:06:28.588302 Enter into DVFS_PRE_config >>>>>
6131 08:06:28.601471 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 08:06:28.605015 Exit from DVFS_PRE_config <<<<<
6133 08:06:28.608278 Enter into PICG configuration >>>>
6134 08:06:28.611510 Exit from PICG configuration <<<<
6135 08:06:28.612066 [RX_INPUT] configuration >>>>>
6136 08:06:28.614529 [RX_INPUT] configuration <<<<<
6137 08:06:28.621452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 08:06:28.624588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 08:06:28.631333 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 08:06:28.637991 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 08:06:28.645092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 08:06:28.651246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 08:06:28.654582 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 08:06:28.657837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 08:06:28.661586 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 08:06:28.668460 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 08:06:28.670983 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 08:06:28.674452 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 08:06:28.677982 ===================================
6150 08:06:28.680985 LPDDR4 DRAM CONFIGURATION
6151 08:06:28.684362 ===================================
6152 08:06:28.687937 EX_ROW_EN[0] = 0x0
6153 08:06:28.688509 EX_ROW_EN[1] = 0x0
6154 08:06:28.691120 LP4Y_EN = 0x0
6155 08:06:28.691583 WORK_FSP = 0x0
6156 08:06:28.694788 WL = 0x2
6157 08:06:28.695343 RL = 0x2
6158 08:06:28.698091 BL = 0x2
6159 08:06:28.698698 RPST = 0x0
6160 08:06:28.701105 RD_PRE = 0x0
6161 08:06:28.701571 WR_PRE = 0x1
6162 08:06:28.704687 WR_PST = 0x0
6163 08:06:28.705293 DBI_WR = 0x0
6164 08:06:28.708360 DBI_RD = 0x0
6165 08:06:28.708922 OTF = 0x1
6166 08:06:28.711317 ===================================
6167 08:06:28.717832 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 08:06:28.721304 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 08:06:28.724556 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 08:06:28.727887 ===================================
6171 08:06:28.731416 LPDDR4 DRAM CONFIGURATION
6172 08:06:28.734780 ===================================
6173 08:06:28.737955 EX_ROW_EN[0] = 0x10
6174 08:06:28.738516 EX_ROW_EN[1] = 0x0
6175 08:06:28.741305 LP4Y_EN = 0x0
6176 08:06:28.741863 WORK_FSP = 0x0
6177 08:06:28.744646 WL = 0x2
6178 08:06:28.745237 RL = 0x2
6179 08:06:28.748110 BL = 0x2
6180 08:06:28.748665 RPST = 0x0
6181 08:06:28.751136 RD_PRE = 0x0
6182 08:06:28.751597 WR_PRE = 0x1
6183 08:06:28.754570 WR_PST = 0x0
6184 08:06:28.755126 DBI_WR = 0x0
6185 08:06:28.757957 DBI_RD = 0x0
6186 08:06:28.758446 OTF = 0x1
6187 08:06:28.761603 ===================================
6188 08:06:28.767681 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 08:06:28.771980 nWR fixed to 30
6190 08:06:28.775826 [ModeRegInit_LP4] CH0 RK0
6191 08:06:28.776399 [ModeRegInit_LP4] CH0 RK1
6192 08:06:28.778876 [ModeRegInit_LP4] CH1 RK0
6193 08:06:28.782310 [ModeRegInit_LP4] CH1 RK1
6194 08:06:28.782879 match AC timing 19
6195 08:06:28.789069 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 08:06:28.792144 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 08:06:28.795244 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 08:06:28.801817 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 08:06:28.805596 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 08:06:28.806159 ==
6201 08:06:28.808547 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 08:06:28.812240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 08:06:28.812852 ==
6204 08:06:28.818646 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 08:06:28.825563 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6206 08:06:28.828895 [CA 0] Center 36 (8~64) winsize 57
6207 08:06:28.832059 [CA 1] Center 36 (8~64) winsize 57
6208 08:06:28.835411 [CA 2] Center 36 (8~64) winsize 57
6209 08:06:28.835970 [CA 3] Center 36 (8~64) winsize 57
6210 08:06:28.839052 [CA 4] Center 36 (8~64) winsize 57
6211 08:06:28.842149 [CA 5] Center 36 (8~64) winsize 57
6212 08:06:28.842710
6213 08:06:28.845580 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6214 08:06:28.848723
6215 08:06:28.851964 [CATrainingPosCal] consider 1 rank data
6216 08:06:28.852427 u2DelayCellTimex100 = 270/100 ps
6217 08:06:28.858581 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 08:06:28.862046 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 08:06:28.865769 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 08:06:28.869205 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 08:06:28.872448 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 08:06:28.875866 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 08:06:28.876438
6224 08:06:28.878498 CA PerBit enable=1, Macro0, CA PI delay=36
6225 08:06:28.878965
6226 08:06:28.882435 [CBTSetCACLKResult] CA Dly = 36
6227 08:06:28.885524 CS Dly: 1 (0~32)
6228 08:06:28.886085 ==
6229 08:06:28.888711 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 08:06:28.892248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 08:06:28.892806 ==
6232 08:06:28.898727 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 08:06:28.902145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6234 08:06:28.905529 [CA 0] Center 36 (8~64) winsize 57
6235 08:06:28.908918 [CA 1] Center 36 (8~64) winsize 57
6236 08:06:28.912441 [CA 2] Center 36 (8~64) winsize 57
6237 08:06:28.915549 [CA 3] Center 36 (8~64) winsize 57
6238 08:06:28.918875 [CA 4] Center 36 (8~64) winsize 57
6239 08:06:28.922077 [CA 5] Center 36 (8~64) winsize 57
6240 08:06:28.922636
6241 08:06:28.926194 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6242 08:06:28.926758
6243 08:06:28.929487 [CATrainingPosCal] consider 2 rank data
6244 08:06:28.932380 u2DelayCellTimex100 = 270/100 ps
6245 08:06:28.935317 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 08:06:28.938700 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 08:06:28.942211 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 08:06:28.945525 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 08:06:28.952093 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 08:06:28.955210 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 08:06:28.955771
6252 08:06:28.958410 CA PerBit enable=1, Macro0, CA PI delay=36
6253 08:06:28.958871
6254 08:06:28.962188 [CBTSetCACLKResult] CA Dly = 36
6255 08:06:28.962749 CS Dly: 1 (0~32)
6256 08:06:28.963117
6257 08:06:28.965405 ----->DramcWriteLeveling(PI) begin...
6258 08:06:28.965972 ==
6259 08:06:28.968427 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 08:06:28.975244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 08:06:28.975800 ==
6262 08:06:28.978578 Write leveling (Byte 0): 40 => 8
6263 08:06:28.979139 Write leveling (Byte 1): 32 => 0
6264 08:06:28.982172 DramcWriteLeveling(PI) end<-----
6265 08:06:28.982731
6266 08:06:28.983093 ==
6267 08:06:28.985588 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 08:06:28.991896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 08:06:28.992456 ==
6270 08:06:28.995179 [Gating] SW mode calibration
6271 08:06:29.001889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 08:06:29.005007 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 08:06:29.011608 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 08:06:29.015021 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 08:06:29.018295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 08:06:29.025035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 08:06:29.028441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 08:06:29.031818 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 08:06:29.038489 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 08:06:29.041568 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 08:06:29.045211 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 08:06:29.048800 Total UI for P1: 0, mck2ui 16
6283 08:06:29.051892 best dqsien dly found for B0: ( 0, 14, 24)
6284 08:06:29.054897 Total UI for P1: 0, mck2ui 16
6285 08:06:29.058317 best dqsien dly found for B1: ( 0, 14, 24)
6286 08:06:29.061335 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 08:06:29.065161 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 08:06:29.065718
6289 08:06:29.068318 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 08:06:29.074947 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 08:06:29.075504 [Gating] SW calibration Done
6292 08:06:29.075874 ==
6293 08:06:29.077993 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 08:06:29.084566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 08:06:29.085054 ==
6296 08:06:29.085415 RX Vref Scan: 0
6297 08:06:29.085745
6298 08:06:29.087912 RX Vref 0 -> 0, step: 1
6299 08:06:29.088357
6300 08:06:29.091085 RX Delay -410 -> 252, step: 16
6301 08:06:29.094440 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6302 08:06:29.097729 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6303 08:06:29.104690 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6304 08:06:29.107963 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6305 08:06:29.111371 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6306 08:06:29.114519 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6307 08:06:29.121356 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6308 08:06:29.124442 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6309 08:06:29.127842 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6310 08:06:29.131146 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6311 08:06:29.137668 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6312 08:06:29.141506 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6313 08:06:29.144526 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6314 08:06:29.147737 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6315 08:06:29.154859 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6316 08:06:29.157759 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6317 08:06:29.158205 ==
6318 08:06:29.161007 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 08:06:29.164864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 08:06:29.165465 ==
6321 08:06:29.167579 DQS Delay:
6322 08:06:29.168022 DQS0 = 27, DQS1 = 43
6323 08:06:29.171496 DQM Delay:
6324 08:06:29.172038 DQM0 = 12, DQM1 = 13
6325 08:06:29.172392 DQ Delay:
6326 08:06:29.174959 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6327 08:06:29.177616 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6328 08:06:29.181256 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6329 08:06:29.185025 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6330 08:06:29.185571
6331 08:06:29.185919
6332 08:06:29.186246 ==
6333 08:06:29.187541 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 08:06:29.191591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 08:06:29.194860 ==
6336 08:06:29.195398
6337 08:06:29.195745
6338 08:06:29.196067 TX Vref Scan disable
6339 08:06:29.197804 == TX Byte 0 ==
6340 08:06:29.201289 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 08:06:29.204483 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 08:06:29.207950 == TX Byte 1 ==
6343 08:06:29.211311 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6344 08:06:29.214767 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6345 08:06:29.215310 ==
6346 08:06:29.218162 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 08:06:29.224365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 08:06:29.224903 ==
6349 08:06:29.225300
6350 08:06:29.225629
6351 08:06:29.226040 TX Vref Scan disable
6352 08:06:29.227757 == TX Byte 0 ==
6353 08:06:29.230807 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 08:06:29.234395 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 08:06:29.238083 == TX Byte 1 ==
6356 08:06:29.241064 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6357 08:06:29.244300 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6358 08:06:29.244760
6359 08:06:29.247730 [DATLAT]
6360 08:06:29.248286 Freq=400, CH0 RK0
6361 08:06:29.248657
6362 08:06:29.251034 DATLAT Default: 0xf
6363 08:06:29.251534 0, 0xFFFF, sum = 0
6364 08:06:29.254480 1, 0xFFFF, sum = 0
6365 08:06:29.255042 2, 0xFFFF, sum = 0
6366 08:06:29.257806 3, 0xFFFF, sum = 0
6367 08:06:29.258370 4, 0xFFFF, sum = 0
6368 08:06:29.260997 5, 0xFFFF, sum = 0
6369 08:06:29.261468 6, 0xFFFF, sum = 0
6370 08:06:29.264904 7, 0xFFFF, sum = 0
6371 08:06:29.265503 8, 0xFFFF, sum = 0
6372 08:06:29.267801 9, 0xFFFF, sum = 0
6373 08:06:29.268362 10, 0xFFFF, sum = 0
6374 08:06:29.271270 11, 0xFFFF, sum = 0
6375 08:06:29.274731 12, 0xFFFF, sum = 0
6376 08:06:29.275297 13, 0x0, sum = 1
6377 08:06:29.275664 14, 0x0, sum = 2
6378 08:06:29.278075 15, 0x0, sum = 3
6379 08:06:29.278660 16, 0x0, sum = 4
6380 08:06:29.281123 best_step = 14
6381 08:06:29.281581
6382 08:06:29.281938 ==
6383 08:06:29.284578 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 08:06:29.287874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 08:06:29.288432 ==
6386 08:06:29.291307 RX Vref Scan: 1
6387 08:06:29.291865
6388 08:06:29.292227 RX Vref 0 -> 0, step: 1
6389 08:06:29.292560
6390 08:06:29.294501 RX Delay -327 -> 252, step: 8
6391 08:06:29.295060
6392 08:06:29.297937 Set Vref, RX VrefLevel [Byte0]: 56
6393 08:06:29.301307 [Byte1]: 49
6394 08:06:29.305939
6395 08:06:29.306494 Final RX Vref Byte 0 = 56 to rank0
6396 08:06:29.309603 Final RX Vref Byte 1 = 49 to rank0
6397 08:06:29.313063 Final RX Vref Byte 0 = 56 to rank1
6398 08:06:29.316011 Final RX Vref Byte 1 = 49 to rank1==
6399 08:06:29.319392 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 08:06:29.322464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 08:06:29.325785 ==
6402 08:06:29.326312 DQS Delay:
6403 08:06:29.326683 DQS0 = 28, DQS1 = 48
6404 08:06:29.329248 DQM Delay:
6405 08:06:29.329703 DQM0 = 12, DQM1 = 14
6406 08:06:29.332482 DQ Delay:
6407 08:06:29.336076 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6408 08:06:29.336535 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6409 08:06:29.339269 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6410 08:06:29.342874 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6411 08:06:29.343441
6412 08:06:29.343802
6413 08:06:29.352521 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6414 08:06:29.356038 CH0 RK0: MR19=C0C, MR18=B3AB
6415 08:06:29.362518 CH0_RK0: MR19=0xC0C, MR18=0xB3AB, DQSOSC=387, MR23=63, INC=394, DEC=262
6416 08:06:29.362985 ==
6417 08:06:29.365976 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 08:06:29.369332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 08:06:29.369797 ==
6420 08:06:29.372841 [Gating] SW mode calibration
6421 08:06:29.379619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 08:06:29.382820 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 08:06:29.389848 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 08:06:29.392735 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 08:06:29.396145 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 08:06:29.402776 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 08:06:29.405909 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 08:06:29.409851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 08:06:29.416003 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 08:06:29.419129 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 08:06:29.422623 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 08:06:29.425783 Total UI for P1: 0, mck2ui 16
6433 08:06:29.429312 best dqsien dly found for B0: ( 0, 14, 24)
6434 08:06:29.432710 Total UI for P1: 0, mck2ui 16
6435 08:06:29.435755 best dqsien dly found for B1: ( 0, 14, 24)
6436 08:06:29.439212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 08:06:29.442779 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 08:06:29.443343
6439 08:06:29.449452 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 08:06:29.452521 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 08:06:29.455996 [Gating] SW calibration Done
6442 08:06:29.456564 ==
6443 08:06:29.459083 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 08:06:29.462230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 08:06:29.462769 ==
6446 08:06:29.463135 RX Vref Scan: 0
6447 08:06:29.463510
6448 08:06:29.465529 RX Vref 0 -> 0, step: 1
6449 08:06:29.465988
6450 08:06:29.468990 RX Delay -410 -> 252, step: 16
6451 08:06:29.472406 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6452 08:06:29.479442 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6453 08:06:29.482507 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6454 08:06:29.485863 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6455 08:06:29.489085 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6456 08:06:29.492393 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6457 08:06:29.499093 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6458 08:06:29.502289 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6459 08:06:29.505530 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6460 08:06:29.509089 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6461 08:06:29.515493 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6462 08:06:29.518767 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6463 08:06:29.522483 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6464 08:06:29.528788 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6465 08:06:29.531889 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6466 08:06:29.535725 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6467 08:06:29.536286 ==
6468 08:06:29.538873 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 08:06:29.542082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 08:06:29.545518 ==
6471 08:06:29.546075 DQS Delay:
6472 08:06:29.546440 DQS0 = 27, DQS1 = 43
6473 08:06:29.548786 DQM Delay:
6474 08:06:29.549365 DQM0 = 10, DQM1 = 15
6475 08:06:29.552164 DQ Delay:
6476 08:06:29.552878 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6477 08:06:29.555583 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6478 08:06:29.558978 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6479 08:06:29.561935 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6480 08:06:29.562606
6481 08:06:29.563157
6482 08:06:29.563511 ==
6483 08:06:29.565228 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 08:06:29.571884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 08:06:29.572499 ==
6486 08:06:29.572871
6487 08:06:29.573266
6488 08:06:29.573595 TX Vref Scan disable
6489 08:06:29.575702 == TX Byte 0 ==
6490 08:06:29.578904 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6491 08:06:29.582240 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6492 08:06:29.585426 == TX Byte 1 ==
6493 08:06:29.588637 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6494 08:06:29.591966 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6495 08:06:29.592527 ==
6496 08:06:29.595232 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 08:06:29.601839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 08:06:29.602401 ==
6499 08:06:29.602764
6500 08:06:29.603096
6501 08:06:29.603595 TX Vref Scan disable
6502 08:06:29.605520 == TX Byte 0 ==
6503 08:06:29.608668 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6504 08:06:29.612108 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6505 08:06:29.615530 == TX Byte 1 ==
6506 08:06:29.618766 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6507 08:06:29.621980 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6508 08:06:29.622542
6509 08:06:29.625187 [DATLAT]
6510 08:06:29.625735 Freq=400, CH0 RK1
6511 08:06:29.626101
6512 08:06:29.628682 DATLAT Default: 0xe
6513 08:06:29.629293 0, 0xFFFF, sum = 0
6514 08:06:29.632073 1, 0xFFFF, sum = 0
6515 08:06:29.632536 2, 0xFFFF, sum = 0
6516 08:06:29.635172 3, 0xFFFF, sum = 0
6517 08:06:29.635737 4, 0xFFFF, sum = 0
6518 08:06:29.638671 5, 0xFFFF, sum = 0
6519 08:06:29.639248 6, 0xFFFF, sum = 0
6520 08:06:29.641823 7, 0xFFFF, sum = 0
6521 08:06:29.642402 8, 0xFFFF, sum = 0
6522 08:06:29.645180 9, 0xFFFF, sum = 0
6523 08:06:29.648472 10, 0xFFFF, sum = 0
6524 08:06:29.649072 11, 0xFFFF, sum = 0
6525 08:06:29.652019 12, 0xFFFF, sum = 0
6526 08:06:29.652643 13, 0x0, sum = 1
6527 08:06:29.655097 14, 0x0, sum = 2
6528 08:06:29.655666 15, 0x0, sum = 3
6529 08:06:29.656035 16, 0x0, sum = 4
6530 08:06:29.658555 best_step = 14
6531 08:06:29.659147
6532 08:06:29.659515 ==
6533 08:06:29.661638 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 08:06:29.664765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 08:06:29.665313 ==
6536 08:06:29.668279 RX Vref Scan: 0
6537 08:06:29.668991
6538 08:06:29.671635 RX Vref 0 -> 0, step: 1
6539 08:06:29.672193
6540 08:06:29.672556 RX Delay -327 -> 252, step: 8
6541 08:06:29.680397 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6542 08:06:29.683616 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6543 08:06:29.686514 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6544 08:06:29.689914 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6545 08:06:29.696614 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6546 08:06:29.700111 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6547 08:06:29.703451 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6548 08:06:29.707018 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6549 08:06:29.713246 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6550 08:06:29.716868 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6551 08:06:29.719909 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6552 08:06:29.723076 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6553 08:06:29.729683 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6554 08:06:29.733157 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6555 08:06:29.736801 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6556 08:06:29.743463 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6557 08:06:29.744011 ==
6558 08:06:29.746702 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 08:06:29.750297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 08:06:29.750851 ==
6561 08:06:29.751224 DQS Delay:
6562 08:06:29.752889 DQS0 = 28, DQS1 = 44
6563 08:06:29.753428 DQM Delay:
6564 08:06:29.756447 DQM0 = 9, DQM1 = 14
6565 08:06:29.757053 DQ Delay:
6566 08:06:29.759640 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6567 08:06:29.762959 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6568 08:06:29.766301 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6569 08:06:29.769793 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6570 08:06:29.770346
6571 08:06:29.770713
6572 08:06:29.776291 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6573 08:06:29.779857 CH0 RK1: MR19=C0C, MR18=BD71
6574 08:06:29.786017 CH0_RK1: MR19=0xC0C, MR18=0xBD71, DQSOSC=386, MR23=63, INC=396, DEC=264
6575 08:06:29.789391 [RxdqsGatingPostProcess] freq 400
6576 08:06:29.796436 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 08:06:29.797034 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 08:06:29.799739 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 08:06:29.802944 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 08:06:29.806550 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 08:06:29.809606 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 08:06:29.813032 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 08:06:29.816161 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 08:06:29.819467 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 08:06:29.822777 Pre-setting of DQS Precalculation
6586 08:06:29.825965 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 08:06:29.829304 ==
6588 08:06:29.832668 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 08:06:29.836273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 08:06:29.836830 ==
6591 08:06:29.839547 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 08:06:29.846265 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6593 08:06:29.849533 [CA 0] Center 36 (8~64) winsize 57
6594 08:06:29.852730 [CA 1] Center 36 (8~64) winsize 57
6595 08:06:29.856285 [CA 2] Center 36 (8~64) winsize 57
6596 08:06:29.859624 [CA 3] Center 36 (8~64) winsize 57
6597 08:06:29.862986 [CA 4] Center 36 (8~64) winsize 57
6598 08:06:29.866126 [CA 5] Center 36 (8~64) winsize 57
6599 08:06:29.866689
6600 08:06:29.869227 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6601 08:06:29.869685
6602 08:06:29.873092 [CATrainingPosCal] consider 1 rank data
6603 08:06:29.876058 u2DelayCellTimex100 = 270/100 ps
6604 08:06:29.879612 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 08:06:29.882507 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 08:06:29.886159 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 08:06:29.889178 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 08:06:29.895805 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 08:06:29.899417 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 08:06:29.899973
6611 08:06:29.902766 CA PerBit enable=1, Macro0, CA PI delay=36
6612 08:06:29.903232
6613 08:06:29.905771 [CBTSetCACLKResult] CA Dly = 36
6614 08:06:29.906234 CS Dly: 1 (0~32)
6615 08:06:29.906599 ==
6616 08:06:29.909370 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 08:06:29.912551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 08:06:29.916181 ==
6619 08:06:29.919148 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 08:06:29.926047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6621 08:06:29.929369 [CA 0] Center 36 (8~64) winsize 57
6622 08:06:29.932324 [CA 1] Center 36 (8~64) winsize 57
6623 08:06:29.935952 [CA 2] Center 36 (8~64) winsize 57
6624 08:06:29.939128 [CA 3] Center 36 (8~64) winsize 57
6625 08:06:29.942594 [CA 4] Center 36 (8~64) winsize 57
6626 08:06:29.945743 [CA 5] Center 36 (8~64) winsize 57
6627 08:06:29.946301
6628 08:06:29.949216 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6629 08:06:29.949772
6630 08:06:29.952195 [CATrainingPosCal] consider 2 rank data
6631 08:06:29.955888 u2DelayCellTimex100 = 270/100 ps
6632 08:06:29.959176 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 08:06:29.962172 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 08:06:29.965492 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 08:06:29.969123 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 08:06:29.972055 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 08:06:29.975273 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 08:06:29.975830
6639 08:06:29.982030 CA PerBit enable=1, Macro0, CA PI delay=36
6640 08:06:29.982599
6641 08:06:29.985811 [CBTSetCACLKResult] CA Dly = 36
6642 08:06:29.986371 CS Dly: 1 (0~32)
6643 08:06:29.986740
6644 08:06:29.988911 ----->DramcWriteLeveling(PI) begin...
6645 08:06:29.989514 ==
6646 08:06:29.992771 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 08:06:29.995083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 08:06:29.995550 ==
6649 08:06:29.998751 Write leveling (Byte 0): 40 => 8
6650 08:06:30.002141 Write leveling (Byte 1): 32 => 0
6651 08:06:30.005176 DramcWriteLeveling(PI) end<-----
6652 08:06:30.005805
6653 08:06:30.006175 ==
6654 08:06:30.008498 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 08:06:30.011799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 08:06:30.015385 ==
6657 08:06:30.016003 [Gating] SW mode calibration
6658 08:06:30.025525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 08:06:30.028714 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 08:06:30.031938 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 08:06:30.038513 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 08:06:30.041950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 08:06:30.045222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 08:06:30.051905 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 08:06:30.055323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 08:06:30.058269 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 08:06:30.065062 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 08:06:30.068106 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 08:06:30.071748 Total UI for P1: 0, mck2ui 16
6670 08:06:30.074812 best dqsien dly found for B0: ( 0, 14, 24)
6671 08:06:30.078492 Total UI for P1: 0, mck2ui 16
6672 08:06:30.081569 best dqsien dly found for B1: ( 0, 14, 24)
6673 08:06:30.085030 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 08:06:30.088288 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 08:06:30.088845
6676 08:06:30.091493 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 08:06:30.094687 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 08:06:30.098068 [Gating] SW calibration Done
6679 08:06:30.098638 ==
6680 08:06:30.101581 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 08:06:30.104589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 08:06:30.108078 ==
6683 08:06:30.108706 RX Vref Scan: 0
6684 08:06:30.109113
6685 08:06:30.111321 RX Vref 0 -> 0, step: 1
6686 08:06:30.111777
6687 08:06:30.114731 RX Delay -410 -> 252, step: 16
6688 08:06:30.117744 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6689 08:06:30.121144 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6690 08:06:30.125018 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6691 08:06:30.131086 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6692 08:06:30.134540 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6693 08:06:30.138133 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6694 08:06:30.141553 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6695 08:06:30.147719 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6696 08:06:30.151357 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6697 08:06:30.154376 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6698 08:06:30.158042 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6699 08:06:30.164676 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6700 08:06:30.168202 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6701 08:06:30.171184 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6702 08:06:30.174762 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6703 08:06:30.181297 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6704 08:06:30.181859 ==
6705 08:06:30.184404 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 08:06:30.187962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 08:06:30.188528 ==
6708 08:06:30.188896 DQS Delay:
6709 08:06:30.191052 DQS0 = 27, DQS1 = 43
6710 08:06:30.191608 DQM Delay:
6711 08:06:30.194342 DQM0 = 5, DQM1 = 15
6712 08:06:30.194896 DQ Delay:
6713 08:06:30.197702 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6714 08:06:30.201296 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6715 08:06:30.204723 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6716 08:06:30.207966 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6717 08:06:30.208519
6718 08:06:30.208881
6719 08:06:30.209252 ==
6720 08:06:30.210973 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 08:06:30.214568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 08:06:30.215197 ==
6723 08:06:30.215568
6724 08:06:30.215899
6725 08:06:30.217785 TX Vref Scan disable
6726 08:06:30.221049 == TX Byte 0 ==
6727 08:06:30.224283 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 08:06:30.227586 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 08:06:30.230997 == TX Byte 1 ==
6730 08:06:30.234511 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6731 08:06:30.237437 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6732 08:06:30.237900 ==
6733 08:06:30.241433 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 08:06:30.244330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 08:06:30.244893 ==
6736 08:06:30.247684
6737 08:06:30.248248
6738 08:06:30.248617 TX Vref Scan disable
6739 08:06:30.251483 == TX Byte 0 ==
6740 08:06:30.254124 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 08:06:30.257827 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 08:06:30.261149 == TX Byte 1 ==
6743 08:06:30.264431 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6744 08:06:30.267368 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6745 08:06:30.267835
6746 08:06:30.270916 [DATLAT]
6747 08:06:30.271480 Freq=400, CH1 RK0
6748 08:06:30.271856
6749 08:06:30.274013 DATLAT Default: 0xf
6750 08:06:30.274583 0, 0xFFFF, sum = 0
6751 08:06:30.277299 1, 0xFFFF, sum = 0
6752 08:06:30.277768 2, 0xFFFF, sum = 0
6753 08:06:30.281006 3, 0xFFFF, sum = 0
6754 08:06:30.281576 4, 0xFFFF, sum = 0
6755 08:06:30.284152 5, 0xFFFF, sum = 0
6756 08:06:30.284625 6, 0xFFFF, sum = 0
6757 08:06:30.287668 7, 0xFFFF, sum = 0
6758 08:06:30.288255 8, 0xFFFF, sum = 0
6759 08:06:30.290441 9, 0xFFFF, sum = 0
6760 08:06:30.290916 10, 0xFFFF, sum = 0
6761 08:06:30.293733 11, 0xFFFF, sum = 0
6762 08:06:30.294213 12, 0xFFFF, sum = 0
6763 08:06:30.297655 13, 0x0, sum = 1
6764 08:06:30.298228 14, 0x0, sum = 2
6765 08:06:30.300672 15, 0x0, sum = 3
6766 08:06:30.301176 16, 0x0, sum = 4
6767 08:06:30.303980 best_step = 14
6768 08:06:30.304551
6769 08:06:30.304924 ==
6770 08:06:30.307830 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 08:06:30.310722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 08:06:30.311297 ==
6773 08:06:30.314360 RX Vref Scan: 1
6774 08:06:30.314930
6775 08:06:30.315301 RX Vref 0 -> 0, step: 1
6776 08:06:30.315645
6777 08:06:30.317140 RX Delay -327 -> 252, step: 8
6778 08:06:30.317608
6779 08:06:30.320673 Set Vref, RX VrefLevel [Byte0]: 51
6780 08:06:30.323643 [Byte1]: 59
6781 08:06:30.328393
6782 08:06:30.328857 Final RX Vref Byte 0 = 51 to rank0
6783 08:06:30.331553 Final RX Vref Byte 1 = 59 to rank0
6784 08:06:30.334929 Final RX Vref Byte 0 = 51 to rank1
6785 08:06:30.338398 Final RX Vref Byte 1 = 59 to rank1==
6786 08:06:30.341774 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 08:06:30.348508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 08:06:30.349127 ==
6789 08:06:30.349510 DQS Delay:
6790 08:06:30.351478 DQS0 = 32, DQS1 = 40
6791 08:06:30.351942 DQM Delay:
6792 08:06:30.352307 DQM0 = 11, DQM1 = 12
6793 08:06:30.355066 DQ Delay:
6794 08:06:30.358471 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6795 08:06:30.359042 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6796 08:06:30.361796 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6797 08:06:30.365373 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6798 08:06:30.365944
6799 08:06:30.368233
6800 08:06:30.375033 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6801 08:06:30.378356 CH1 RK0: MR19=C0C, MR18=99D3
6802 08:06:30.384690 CH1_RK0: MR19=0xC0C, MR18=0x99D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6803 08:06:30.385296 ==
6804 08:06:30.388261 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 08:06:30.391834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 08:06:30.392412 ==
6807 08:06:30.395147 [Gating] SW mode calibration
6808 08:06:30.401773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 08:06:30.408513 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 08:06:30.411840 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 08:06:30.415005 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 08:06:30.418156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 08:06:30.425082 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 08:06:30.428067 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 08:06:30.431639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 08:06:30.438157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 08:06:30.441483 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 08:06:30.444810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 08:06:30.447845 Total UI for P1: 0, mck2ui 16
6820 08:06:30.451449 best dqsien dly found for B0: ( 0, 14, 24)
6821 08:06:30.454458 Total UI for P1: 0, mck2ui 16
6822 08:06:30.458224 best dqsien dly found for B1: ( 0, 14, 24)
6823 08:06:30.461132 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 08:06:30.465025 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 08:06:30.467810
6826 08:06:30.471657 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 08:06:30.474693 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 08:06:30.478300 [Gating] SW calibration Done
6829 08:06:30.478857 ==
6830 08:06:30.481478 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 08:06:30.484991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 08:06:30.485557 ==
6833 08:06:30.485932 RX Vref Scan: 0
6834 08:06:30.486274
6835 08:06:30.488112 RX Vref 0 -> 0, step: 1
6836 08:06:30.488668
6837 08:06:30.491432 RX Delay -410 -> 252, step: 16
6838 08:06:30.495095 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6839 08:06:30.501646 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6840 08:06:30.504899 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6841 08:06:30.508061 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6842 08:06:30.511721 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6843 08:06:30.517852 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6844 08:06:30.521570 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6845 08:06:30.524956 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6846 08:06:30.528137 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6847 08:06:30.534307 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6848 08:06:30.537834 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6849 08:06:30.541288 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6850 08:06:30.544518 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6851 08:06:30.551071 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6852 08:06:30.554243 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6853 08:06:30.558104 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6854 08:06:30.558671 ==
6855 08:06:30.560908 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 08:06:30.564107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 08:06:30.567685 ==
6858 08:06:30.568366 DQS Delay:
6859 08:06:30.568764 DQS0 = 35, DQS1 = 43
6860 08:06:30.570992 DQM Delay:
6861 08:06:30.571549 DQM0 = 17, DQM1 = 18
6862 08:06:30.574349 DQ Delay:
6863 08:06:30.577573 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6864 08:06:30.578036 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6865 08:06:30.581177 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6866 08:06:30.584110 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6867 08:06:30.584571
6868 08:06:30.588016
6869 08:06:30.588577 ==
6870 08:06:30.591004 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 08:06:30.593992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 08:06:30.594455 ==
6873 08:06:30.594822
6874 08:06:30.595155
6875 08:06:30.597646 TX Vref Scan disable
6876 08:06:30.598106 == TX Byte 0 ==
6877 08:06:30.600550 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6878 08:06:30.607614 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6879 08:06:30.608184 == TX Byte 1 ==
6880 08:06:30.611068 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6881 08:06:30.617431 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6882 08:06:30.617994 ==
6883 08:06:30.620850 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 08:06:30.624425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 08:06:30.625038 ==
6886 08:06:30.625414
6887 08:06:30.625752
6888 08:06:30.627507 TX Vref Scan disable
6889 08:06:30.628069 == TX Byte 0 ==
6890 08:06:30.631024 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6891 08:06:30.637653 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6892 08:06:30.638217 == TX Byte 1 ==
6893 08:06:30.640491 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6894 08:06:30.647490 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6895 08:06:30.648077
6896 08:06:30.648444 [DATLAT]
6897 08:06:30.648782 Freq=400, CH1 RK1
6898 08:06:30.649155
6899 08:06:30.650927 DATLAT Default: 0xe
6900 08:06:30.653912 0, 0xFFFF, sum = 0
6901 08:06:30.654441 1, 0xFFFF, sum = 0
6902 08:06:30.657270 2, 0xFFFF, sum = 0
6903 08:06:30.657734 3, 0xFFFF, sum = 0
6904 08:06:30.660444 4, 0xFFFF, sum = 0
6905 08:06:30.660924 5, 0xFFFF, sum = 0
6906 08:06:30.663780 6, 0xFFFF, sum = 0
6907 08:06:30.664277 7, 0xFFFF, sum = 0
6908 08:06:30.667176 8, 0xFFFF, sum = 0
6909 08:06:30.667643 9, 0xFFFF, sum = 0
6910 08:06:30.670759 10, 0xFFFF, sum = 0
6911 08:06:30.671227 11, 0xFFFF, sum = 0
6912 08:06:30.673817 12, 0xFFFF, sum = 0
6913 08:06:30.674316 13, 0x0, sum = 1
6914 08:06:30.676999 14, 0x0, sum = 2
6915 08:06:30.677465 15, 0x0, sum = 3
6916 08:06:30.680265 16, 0x0, sum = 4
6917 08:06:30.680756 best_step = 14
6918 08:06:30.681177
6919 08:06:30.681523 ==
6920 08:06:30.683640 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 08:06:30.687466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 08:06:30.690464 ==
6923 08:06:30.690924 RX Vref Scan: 0
6924 08:06:30.691288
6925 08:06:30.693660 RX Vref 0 -> 0, step: 1
6926 08:06:30.694200
6927 08:06:30.696846 RX Delay -327 -> 252, step: 8
6928 08:06:30.704064 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6929 08:06:30.707457 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6930 08:06:30.710623 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6931 08:06:30.714100 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6932 08:06:30.717825 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6933 08:06:30.723932 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6934 08:06:30.727380 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6935 08:06:30.730568 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6936 08:06:30.733777 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6937 08:06:30.740619 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6938 08:06:30.744112 iDelay=217, Bit 10, Center -24 (-255 ~ 208) 464
6939 08:06:30.747470 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6940 08:06:30.750644 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6941 08:06:30.757334 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6942 08:06:30.760785 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6943 08:06:30.763819 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6944 08:06:30.764300 ==
6945 08:06:30.767303 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 08:06:30.773562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 08:06:30.774029 ==
6948 08:06:30.774394 DQS Delay:
6949 08:06:30.777585 DQS0 = 32, DQS1 = 40
6950 08:06:30.778050 DQM Delay:
6951 08:06:30.778416 DQM0 = 11, DQM1 = 14
6952 08:06:30.780493 DQ Delay:
6953 08:06:30.783786 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6954 08:06:30.787456 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
6955 08:06:30.788018 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6956 08:06:30.790561 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6957 08:06:30.791023
6958 08:06:30.793583
6959 08:06:30.800645 [DQSOSCAuto] RK1, (LSB)MR18= 0xab54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6960 08:06:30.804027 CH1 RK1: MR19=C0C, MR18=AB54
6961 08:06:30.810382 CH1_RK1: MR19=0xC0C, MR18=0xAB54, DQSOSC=388, MR23=63, INC=392, DEC=261
6962 08:06:30.813705 [RxdqsGatingPostProcess] freq 400
6963 08:06:30.817297 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 08:06:30.820787 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 08:06:30.823958 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 08:06:30.827977 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 08:06:30.830672 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 08:06:30.833624 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 08:06:30.837306 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 08:06:30.840775 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 08:06:30.844182 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 08:06:30.846981 Pre-setting of DQS Precalculation
6973 08:06:30.850604 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 08:06:30.857372 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 08:06:30.867506 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 08:06:30.868077
6977 08:06:30.868442
6978 08:06:30.868779 [Calibration Summary] 800 Mbps
6979 08:06:30.870202 CH 0, Rank 0
6980 08:06:30.870664 SW Impedance : PASS
6981 08:06:30.873753 DUTY Scan : NO K
6982 08:06:30.876900 ZQ Calibration : PASS
6983 08:06:30.877498 Jitter Meter : NO K
6984 08:06:30.880065 CBT Training : PASS
6985 08:06:30.883517 Write leveling : PASS
6986 08:06:30.883998 RX DQS gating : PASS
6987 08:06:30.886864 RX DQ/DQS(RDDQC) : PASS
6988 08:06:30.890273 TX DQ/DQS : PASS
6989 08:06:30.890782 RX DATLAT : PASS
6990 08:06:30.893514 RX DQ/DQS(Engine): PASS
6991 08:06:30.896730 TX OE : NO K
6992 08:06:30.897330 All Pass.
6993 08:06:30.897694
6994 08:06:30.898028 CH 0, Rank 1
6995 08:06:30.900688 SW Impedance : PASS
6996 08:06:30.903739 DUTY Scan : NO K
6997 08:06:30.904306 ZQ Calibration : PASS
6998 08:06:30.907011 Jitter Meter : NO K
6999 08:06:30.910298 CBT Training : PASS
7000 08:06:30.910861 Write leveling : NO K
7001 08:06:30.913863 RX DQS gating : PASS
7002 08:06:30.914429 RX DQ/DQS(RDDQC) : PASS
7003 08:06:30.917070 TX DQ/DQS : PASS
7004 08:06:30.919964 RX DATLAT : PASS
7005 08:06:30.920421 RX DQ/DQS(Engine): PASS
7006 08:06:30.923615 TX OE : NO K
7007 08:06:30.924171 All Pass.
7008 08:06:30.924542
7009 08:06:30.927075 CH 1, Rank 0
7010 08:06:30.927630 SW Impedance : PASS
7011 08:06:30.930093 DUTY Scan : NO K
7012 08:06:30.933818 ZQ Calibration : PASS
7013 08:06:30.934382 Jitter Meter : NO K
7014 08:06:30.937014 CBT Training : PASS
7015 08:06:30.940392 Write leveling : PASS
7016 08:06:30.940984 RX DQS gating : PASS
7017 08:06:30.943992 RX DQ/DQS(RDDQC) : PASS
7018 08:06:30.946761 TX DQ/DQS : PASS
7019 08:06:30.947224 RX DATLAT : PASS
7020 08:06:30.950214 RX DQ/DQS(Engine): PASS
7021 08:06:30.953564 TX OE : NO K
7022 08:06:30.954030 All Pass.
7023 08:06:30.954393
7024 08:06:30.954732 CH 1, Rank 1
7025 08:06:30.956583 SW Impedance : PASS
7026 08:06:30.960414 DUTY Scan : NO K
7027 08:06:30.961013 ZQ Calibration : PASS
7028 08:06:30.963576 Jitter Meter : NO K
7029 08:06:30.964142 CBT Training : PASS
7030 08:06:30.966796 Write leveling : NO K
7031 08:06:30.970162 RX DQS gating : PASS
7032 08:06:30.970743 RX DQ/DQS(RDDQC) : PASS
7033 08:06:30.973323 TX DQ/DQS : PASS
7034 08:06:30.976919 RX DATLAT : PASS
7035 08:06:30.977520 RX DQ/DQS(Engine): PASS
7036 08:06:30.980108 TX OE : NO K
7037 08:06:30.980676 All Pass.
7038 08:06:30.981093
7039 08:06:30.983333 DramC Write-DBI off
7040 08:06:30.986776 PER_BANK_REFRESH: Hybrid Mode
7041 08:06:30.987236 TX_TRACKING: ON
7042 08:06:30.996705 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 08:06:31.000047 [FAST_K] Save calibration result to emmc
7044 08:06:31.003353 dramc_set_vcore_voltage set vcore to 725000
7045 08:06:31.006770 Read voltage for 1600, 0
7046 08:06:31.007347 Vio18 = 0
7047 08:06:31.007715 Vcore = 725000
7048 08:06:31.010756 Vdram = 0
7049 08:06:31.011460 Vddq = 0
7050 08:06:31.011845 Vmddr = 0
7051 08:06:31.017048 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 08:06:31.019848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 08:06:31.023196 MEM_TYPE=3, freq_sel=13
7054 08:06:31.027176 sv_algorithm_assistance_LP4_3733
7055 08:06:31.030399 ============ PULL DRAM RESETB DOWN ============
7056 08:06:31.033693 ========== PULL DRAM RESETB DOWN end =========
7057 08:06:31.040127 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 08:06:31.043665 ===================================
7059 08:06:31.046770 LPDDR4 DRAM CONFIGURATION
7060 08:06:31.050729 ===================================
7061 08:06:31.051355 EX_ROW_EN[0] = 0x0
7062 08:06:31.053825 EX_ROW_EN[1] = 0x0
7063 08:06:31.054390 LP4Y_EN = 0x0
7064 08:06:31.056845 WORK_FSP = 0x1
7065 08:06:31.057323 WL = 0x5
7066 08:06:31.060439 RL = 0x5
7067 08:06:31.061035 BL = 0x2
7068 08:06:31.063534 RPST = 0x0
7069 08:06:31.064094 RD_PRE = 0x0
7070 08:06:31.066999 WR_PRE = 0x1
7071 08:06:31.067559 WR_PST = 0x1
7072 08:06:31.070210 DBI_WR = 0x0
7073 08:06:31.070826 DBI_RD = 0x0
7074 08:06:31.073187 OTF = 0x1
7075 08:06:31.076771 ===================================
7076 08:06:31.080448 ===================================
7077 08:06:31.081056 ANA top config
7078 08:06:31.083503 ===================================
7079 08:06:31.086742 DLL_ASYNC_EN = 0
7080 08:06:31.090070 ALL_SLAVE_EN = 0
7081 08:06:31.093265 NEW_RANK_MODE = 1
7082 08:06:31.093829 DLL_IDLE_MODE = 1
7083 08:06:31.096769 LP45_APHY_COMB_EN = 1
7084 08:06:31.100137 TX_ODT_DIS = 0
7085 08:06:31.102985 NEW_8X_MODE = 1
7086 08:06:31.106342 ===================================
7087 08:06:31.109581 ===================================
7088 08:06:31.113073 data_rate = 3200
7089 08:06:31.113586 CKR = 1
7090 08:06:31.116577 DQ_P2S_RATIO = 8
7091 08:06:31.119911 ===================================
7092 08:06:31.123174 CA_P2S_RATIO = 8
7093 08:06:31.126843 DQ_CA_OPEN = 0
7094 08:06:31.129632 DQ_SEMI_OPEN = 0
7095 08:06:31.133378 CA_SEMI_OPEN = 0
7096 08:06:31.133938 CA_FULL_RATE = 0
7097 08:06:31.136801 DQ_CKDIV4_EN = 0
7098 08:06:31.139688 CA_CKDIV4_EN = 0
7099 08:06:31.143084 CA_PREDIV_EN = 0
7100 08:06:31.146657 PH8_DLY = 12
7101 08:06:31.149713 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 08:06:31.150275 DQ_AAMCK_DIV = 4
7103 08:06:31.153586 CA_AAMCK_DIV = 4
7104 08:06:31.156708 CA_ADMCK_DIV = 4
7105 08:06:31.160552 DQ_TRACK_CA_EN = 0
7106 08:06:31.163308 CA_PICK = 1600
7107 08:06:31.166493 CA_MCKIO = 1600
7108 08:06:31.169766 MCKIO_SEMI = 0
7109 08:06:31.170330 PLL_FREQ = 3068
7110 08:06:31.173291 DQ_UI_PI_RATIO = 32
7111 08:06:31.176487 CA_UI_PI_RATIO = 0
7112 08:06:31.179852 ===================================
7113 08:06:31.183064 ===================================
7114 08:06:31.186618 memory_type:LPDDR4
7115 08:06:31.187179 GP_NUM : 10
7116 08:06:31.189672 SRAM_EN : 1
7117 08:06:31.193093 MD32_EN : 0
7118 08:06:31.196231 ===================================
7119 08:06:31.196799 [ANA_INIT] >>>>>>>>>>>>>>
7120 08:06:31.199631 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 08:06:31.203086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 08:06:31.206235 ===================================
7123 08:06:31.209516 data_rate = 3200,PCW = 0X7600
7124 08:06:31.212961 ===================================
7125 08:06:31.216281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 08:06:31.223006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 08:06:31.226196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 08:06:31.233061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 08:06:31.236276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 08:06:31.239737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 08:06:31.240305 [ANA_INIT] flow start
7132 08:06:31.242986 [ANA_INIT] PLL >>>>>>>>
7133 08:06:31.246093 [ANA_INIT] PLL <<<<<<<<
7134 08:06:31.249849 [ANA_INIT] MIDPI >>>>>>>>
7135 08:06:31.250413 [ANA_INIT] MIDPI <<<<<<<<
7136 08:06:31.252860 [ANA_INIT] DLL >>>>>>>>
7137 08:06:31.256225 [ANA_INIT] DLL <<<<<<<<
7138 08:06:31.256817 [ANA_INIT] flow end
7139 08:06:31.259706 ============ LP4 DIFF to SE enter ============
7140 08:06:31.265910 ============ LP4 DIFF to SE exit ============
7141 08:06:31.266480 [ANA_INIT] <<<<<<<<<<<<<
7142 08:06:31.269604 [Flow] Enable top DCM control >>>>>
7143 08:06:31.272388 [Flow] Enable top DCM control <<<<<
7144 08:06:31.276234 Enable DLL master slave shuffle
7145 08:06:31.282767 ==============================================================
7146 08:06:31.283340 Gating Mode config
7147 08:06:31.289488 ==============================================================
7148 08:06:31.292605 Config description:
7149 08:06:31.302560 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 08:06:31.309597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 08:06:31.312532 SELPH_MODE 0: By rank 1: By Phase
7152 08:06:31.318912 ==============================================================
7153 08:06:31.322273 GAT_TRACK_EN = 1
7154 08:06:31.325999 RX_GATING_MODE = 2
7155 08:06:31.326480 RX_GATING_TRACK_MODE = 2
7156 08:06:31.328982 SELPH_MODE = 1
7157 08:06:31.332302 PICG_EARLY_EN = 1
7158 08:06:31.335606 VALID_LAT_VALUE = 1
7159 08:06:31.342150 ==============================================================
7160 08:06:31.345306 Enter into Gating configuration >>>>
7161 08:06:31.348915 Exit from Gating configuration <<<<
7162 08:06:31.352496 Enter into DVFS_PRE_config >>>>>
7163 08:06:31.362338 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 08:06:31.365148 Exit from DVFS_PRE_config <<<<<
7165 08:06:31.368593 Enter into PICG configuration >>>>
7166 08:06:31.372190 Exit from PICG configuration <<<<
7167 08:06:31.375471 [RX_INPUT] configuration >>>>>
7168 08:06:31.378754 [RX_INPUT] configuration <<<<<
7169 08:06:31.382122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 08:06:31.388872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 08:06:31.395476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 08:06:31.402047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 08:06:31.405618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 08:06:31.412098 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 08:06:31.415676 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 08:06:31.421721 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 08:06:31.425308 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 08:06:31.428787 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 08:06:31.432068 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 08:06:31.439062 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 08:06:31.441993 ===================================
7182 08:06:31.442706 LPDDR4 DRAM CONFIGURATION
7183 08:06:31.445621 ===================================
7184 08:06:31.448878 EX_ROW_EN[0] = 0x0
7185 08:06:31.452574 EX_ROW_EN[1] = 0x0
7186 08:06:31.453185 LP4Y_EN = 0x0
7187 08:06:31.456045 WORK_FSP = 0x1
7188 08:06:31.456615 WL = 0x5
7189 08:06:31.458696 RL = 0x5
7190 08:06:31.459159 BL = 0x2
7191 08:06:31.461909 RPST = 0x0
7192 08:06:31.462370 RD_PRE = 0x0
7193 08:06:31.465339 WR_PRE = 0x1
7194 08:06:31.465802 WR_PST = 0x1
7195 08:06:31.469106 DBI_WR = 0x0
7196 08:06:31.469675 DBI_RD = 0x0
7197 08:06:31.472283 OTF = 0x1
7198 08:06:31.475193 ===================================
7199 08:06:31.478657 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 08:06:31.482211 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 08:06:31.488698 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 08:06:31.492205 ===================================
7203 08:06:31.492782 LPDDR4 DRAM CONFIGURATION
7204 08:06:31.495416 ===================================
7205 08:06:31.498861 EX_ROW_EN[0] = 0x10
7206 08:06:31.499430 EX_ROW_EN[1] = 0x0
7207 08:06:31.501965 LP4Y_EN = 0x0
7208 08:06:31.505365 WORK_FSP = 0x1
7209 08:06:31.505933 WL = 0x5
7210 08:06:31.509057 RL = 0x5
7211 08:06:31.509656 BL = 0x2
7212 08:06:31.512111 RPST = 0x0
7213 08:06:31.512678 RD_PRE = 0x0
7214 08:06:31.515452 WR_PRE = 0x1
7215 08:06:31.516019 WR_PST = 0x1
7216 08:06:31.518868 DBI_WR = 0x0
7217 08:06:31.519435 DBI_RD = 0x0
7218 08:06:31.521660 OTF = 0x1
7219 08:06:31.525539 ===================================
7220 08:06:31.531845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 08:06:31.532418 ==
7222 08:06:31.535235 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 08:06:31.538546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 08:06:31.539027 ==
7225 08:06:31.541920 [Duty_Offset_Calibration]
7226 08:06:31.542396 B0:2 B1:0 CA:1
7227 08:06:31.542872
7228 08:06:31.545266 [DutyScan_Calibration_Flow] k_type=0
7229 08:06:31.554642
7230 08:06:31.555211 ==CLK 0==
7231 08:06:31.557938 Final CLK duty delay cell = -4
7232 08:06:31.561186 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7233 08:06:31.565496 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7234 08:06:31.568389 [-4] AVG Duty = 4906%(X100)
7235 08:06:31.568980
7236 08:06:31.571205 CH0 CLK Duty spec in!! Max-Min= 187%
7237 08:06:31.574284 [DutyScan_Calibration_Flow] ====Done====
7238 08:06:31.574744
7239 08:06:31.577639 [DutyScan_Calibration_Flow] k_type=1
7240 08:06:31.593841
7241 08:06:31.594391 ==DQS 0 ==
7242 08:06:31.597510 Final DQS duty delay cell = 0
7243 08:06:31.600682 [0] MAX Duty = 5249%(X100), DQS PI = 32
7244 08:06:31.604163 [0] MIN Duty = 4969%(X100), DQS PI = 0
7245 08:06:31.607470 [0] AVG Duty = 5109%(X100)
7246 08:06:31.608028
7247 08:06:31.608388 ==DQS 1 ==
7248 08:06:31.610317 Final DQS duty delay cell = -4
7249 08:06:31.613889 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7250 08:06:31.617308 [-4] MIN Duty = 4875%(X100), DQS PI = 6
7251 08:06:31.620584 [-4] AVG Duty = 5000%(X100)
7252 08:06:31.621170
7253 08:06:31.624145 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7254 08:06:31.624721
7255 08:06:31.627520 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7256 08:06:31.630682 [DutyScan_Calibration_Flow] ====Done====
7257 08:06:31.631237
7258 08:06:31.633814 [DutyScan_Calibration_Flow] k_type=3
7259 08:06:31.651059
7260 08:06:31.651670 ==DQM 0 ==
7261 08:06:31.653679 Final DQM duty delay cell = 0
7262 08:06:31.657483 [0] MAX Duty = 5124%(X100), DQS PI = 26
7263 08:06:31.660884 [0] MIN Duty = 4813%(X100), DQS PI = 52
7264 08:06:31.663708 [0] AVG Duty = 4968%(X100)
7265 08:06:31.664162
7266 08:06:31.664521 ==DQM 1 ==
7267 08:06:31.667142 Final DQM duty delay cell = -4
7268 08:06:31.670461 [-4] MAX Duty = 5062%(X100), DQS PI = 46
7269 08:06:31.673849 [-4] MIN Duty = 4751%(X100), DQS PI = 20
7270 08:06:31.677046 [-4] AVG Duty = 4906%(X100)
7271 08:06:31.677503
7272 08:06:31.680108 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7273 08:06:31.680563
7274 08:06:31.683829 CH0 DQM 1 Duty spec in!! Max-Min= 311%
7275 08:06:31.687488 [DutyScan_Calibration_Flow] ====Done====
7276 08:06:31.688074
7277 08:06:31.690232 [DutyScan_Calibration_Flow] k_type=2
7278 08:06:31.708195
7279 08:06:31.708752 ==DQ 0 ==
7280 08:06:31.711563 Final DQ duty delay cell = 0
7281 08:06:31.714653 [0] MAX Duty = 5156%(X100), DQS PI = 36
7282 08:06:31.717815 [0] MIN Duty = 5000%(X100), DQS PI = 16
7283 08:06:31.718327 [0] AVG Duty = 5078%(X100)
7284 08:06:31.721178
7285 08:06:31.721629 ==DQ 1 ==
7286 08:06:31.724702 Final DQ duty delay cell = 0
7287 08:06:31.728255 [0] MAX Duty = 4969%(X100), DQS PI = 42
7288 08:06:31.731527 [0] MIN Duty = 4875%(X100), DQS PI = 10
7289 08:06:31.732086 [0] AVG Duty = 4922%(X100)
7290 08:06:31.732450
7291 08:06:31.734702 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7292 08:06:31.738101
7293 08:06:31.738547 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7294 08:06:31.744620 [DutyScan_Calibration_Flow] ====Done====
7295 08:06:31.745114 ==
7296 08:06:31.748119 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 08:06:31.751418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 08:06:31.751871 ==
7299 08:06:31.754696 [Duty_Offset_Calibration]
7300 08:06:31.755142 B0:0 B1:-1 CA:2
7301 08:06:31.755488
7302 08:06:31.758126 [DutyScan_Calibration_Flow] k_type=0
7303 08:06:31.768329
7304 08:06:31.768959 ==CLK 0==
7305 08:06:31.771523 Final CLK duty delay cell = 0
7306 08:06:31.774864 [0] MAX Duty = 5156%(X100), DQS PI = 10
7307 08:06:31.778445 [0] MIN Duty = 4906%(X100), DQS PI = 46
7308 08:06:31.779000 [0] AVG Duty = 5031%(X100)
7309 08:06:31.781484
7310 08:06:31.784687 CH1 CLK Duty spec in!! Max-Min= 250%
7311 08:06:31.788402 [DutyScan_Calibration_Flow] ====Done====
7312 08:06:31.788993
7313 08:06:31.791683 [DutyScan_Calibration_Flow] k_type=1
7314 08:06:31.808193
7315 08:06:31.808731 ==DQS 0 ==
7316 08:06:31.811251 Final DQS duty delay cell = 0
7317 08:06:31.814800 [0] MAX Duty = 5124%(X100), DQS PI = 24
7318 08:06:31.818299 [0] MIN Duty = 4969%(X100), DQS PI = 2
7319 08:06:31.818850 [0] AVG Duty = 5046%(X100)
7320 08:06:31.821313
7321 08:06:31.821849 ==DQS 1 ==
7322 08:06:31.824776 Final DQS duty delay cell = 0
7323 08:06:31.828195 [0] MAX Duty = 5187%(X100), DQS PI = 0
7324 08:06:31.831469 [0] MIN Duty = 4844%(X100), DQS PI = 32
7325 08:06:31.832012 [0] AVG Duty = 5015%(X100)
7326 08:06:31.835014
7327 08:06:31.838227 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7328 08:06:31.838772
7329 08:06:31.841348 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7330 08:06:31.845498 [DutyScan_Calibration_Flow] ====Done====
7331 08:06:31.846047
7332 08:06:31.848039 [DutyScan_Calibration_Flow] k_type=3
7333 08:06:31.865579
7334 08:06:31.866117 ==DQM 0 ==
7335 08:06:31.869028 Final DQM duty delay cell = 4
7336 08:06:31.872185 [4] MAX Duty = 5125%(X100), DQS PI = 24
7337 08:06:31.875490 [4] MIN Duty = 4969%(X100), DQS PI = 42
7338 08:06:31.878733 [4] AVG Duty = 5047%(X100)
7339 08:06:31.879328
7340 08:06:31.879688 ==DQM 1 ==
7341 08:06:31.882180 Final DQM duty delay cell = 0
7342 08:06:31.885481 [0] MAX Duty = 5281%(X100), DQS PI = 58
7343 08:06:31.888713 [0] MIN Duty = 4876%(X100), DQS PI = 34
7344 08:06:31.892134 [0] AVG Duty = 5078%(X100)
7345 08:06:31.892676
7346 08:06:31.895587 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7347 08:06:31.896150
7348 08:06:31.898946 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7349 08:06:31.902159 [DutyScan_Calibration_Flow] ====Done====
7350 08:06:31.902705
7351 08:06:31.905498 [DutyScan_Calibration_Flow] k_type=2
7352 08:06:31.922843
7353 08:06:31.923388 ==DQ 0 ==
7354 08:06:31.925856 Final DQ duty delay cell = 0
7355 08:06:31.929104 [0] MAX Duty = 5093%(X100), DQS PI = 22
7356 08:06:31.932451 [0] MIN Duty = 4969%(X100), DQS PI = 46
7357 08:06:31.933025 [0] AVG Duty = 5031%(X100)
7358 08:06:31.935999
7359 08:06:31.936538 ==DQ 1 ==
7360 08:06:31.939377 Final DQ duty delay cell = 0
7361 08:06:31.942252 [0] MAX Duty = 5062%(X100), DQS PI = 0
7362 08:06:31.945864 [0] MIN Duty = 4844%(X100), DQS PI = 32
7363 08:06:31.946411 [0] AVG Duty = 4953%(X100)
7364 08:06:31.949062
7365 08:06:31.952205 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7366 08:06:31.952663
7367 08:06:31.955784 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7368 08:06:31.959093 [DutyScan_Calibration_Flow] ====Done====
7369 08:06:31.962072 nWR fixed to 30
7370 08:06:31.962532 [ModeRegInit_LP4] CH0 RK0
7371 08:06:31.965654 [ModeRegInit_LP4] CH0 RK1
7372 08:06:31.969018 [ModeRegInit_LP4] CH1 RK0
7373 08:06:31.972332 [ModeRegInit_LP4] CH1 RK1
7374 08:06:31.972896 match AC timing 5
7375 08:06:31.978327 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 08:06:31.982042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 08:06:31.985229 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 08:06:31.991594 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 08:06:31.995262 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 08:06:31.995728 [MiockJmeterHQA]
7381 08:06:31.996093
7382 08:06:31.998845 [DramcMiockJmeter] u1RxGatingPI = 0
7383 08:06:32.001670 0 : 4252, 4027
7384 08:06:32.002142 4 : 4252, 4026
7385 08:06:32.005042 8 : 4253, 4026
7386 08:06:32.005515 12 : 4255, 4029
7387 08:06:32.005888 16 : 4253, 4026
7388 08:06:32.008735 20 : 4253, 4026
7389 08:06:32.009389 24 : 4255, 4029
7390 08:06:32.011760 28 : 4252, 4027
7391 08:06:32.012229 32 : 4258, 4029
7392 08:06:32.015339 36 : 4252, 4027
7393 08:06:32.015903 40 : 4252, 4027
7394 08:06:32.018776 44 : 4255, 4029
7395 08:06:32.019338 48 : 4255, 4030
7396 08:06:32.019714 52 : 4363, 4137
7397 08:06:32.021539 56 : 4363, 4138
7398 08:06:32.022012 60 : 4253, 4026
7399 08:06:32.025201 64 : 4252, 4027
7400 08:06:32.025758 68 : 4255, 4030
7401 08:06:32.028526 72 : 4250, 4027
7402 08:06:32.029128 76 : 4253, 4029
7403 08:06:32.031857 80 : 4252, 4029
7404 08:06:32.032422 84 : 4250, 4026
7405 08:06:32.032799 88 : 4250, 3672
7406 08:06:32.034987 92 : 4250, 0
7407 08:06:32.035454 96 : 4253, 0
7408 08:06:32.038480 100 : 4363, 0
7409 08:06:32.039042 104 : 4250, 0
7410 08:06:32.039420 108 : 4252, 0
7411 08:06:32.041858 112 : 4250, 0
7412 08:06:32.042422 116 : 4252, 0
7413 08:06:32.042799 120 : 4250, 0
7414 08:06:32.045011 124 : 4250, 0
7415 08:06:32.045567 128 : 4255, 0
7416 08:06:32.048738 132 : 4361, 0
7417 08:06:32.049342 136 : 4250, 0
7418 08:06:32.049728 140 : 4361, 0
7419 08:06:32.051777 144 : 4250, 0
7420 08:06:32.052338 148 : 4250, 0
7421 08:06:32.055259 152 : 4250, 0
7422 08:06:32.055822 156 : 4250, 0
7423 08:06:32.056201 160 : 4255, 0
7424 08:06:32.058245 164 : 4250, 0
7425 08:06:32.058717 168 : 4252, 0
7426 08:06:32.061584 172 : 4250, 0
7427 08:06:32.062053 176 : 4250, 0
7428 08:06:32.062427 180 : 4255, 0
7429 08:06:32.065368 184 : 4361, 0
7430 08:06:32.065929 188 : 4250, 0
7431 08:06:32.066303 192 : 4361, 0
7432 08:06:32.068374 196 : 4250, 0
7433 08:06:32.068983 200 : 4250, 4
7434 08:06:32.072013 204 : 4250, 2438
7435 08:06:32.072571 208 : 4360, 4137
7436 08:06:32.075207 212 : 4366, 4140
7437 08:06:32.075996 216 : 4250, 4027
7438 08:06:32.078530 220 : 4250, 4027
7439 08:06:32.079098 224 : 4250, 4027
7440 08:06:32.079477 228 : 4250, 4027
7441 08:06:32.081489 232 : 4250, 4027
7442 08:06:32.081961 236 : 4363, 4140
7443 08:06:32.085294 240 : 4250, 4027
7444 08:06:32.085863 244 : 4250, 4027
7445 08:06:32.088316 248 : 4363, 4140
7446 08:06:32.088790 252 : 4250, 4027
7447 08:06:32.091591 256 : 4252, 4030
7448 08:06:32.092155 260 : 4360, 4137
7449 08:06:32.094735 264 : 4360, 4137
7450 08:06:32.095208 268 : 4250, 4027
7451 08:06:32.098374 272 : 4250, 4027
7452 08:06:32.098843 276 : 4252, 4030
7453 08:06:32.101501 280 : 4252, 4030
7454 08:06:32.101974 284 : 4250, 4027
7455 08:06:32.102342 288 : 4361, 4137
7456 08:06:32.105078 292 : 4250, 4027
7457 08:06:32.105542 296 : 4250, 4027
7458 08:06:32.108118 300 : 4363, 4140
7459 08:06:32.108576 304 : 4250, 4027
7460 08:06:32.111693 308 : 4250, 4027
7461 08:06:32.112156 312 : 4363, 4047
7462 08:06:32.115015 316 : 4360, 2145
7463 08:06:32.115575
7464 08:06:32.115935 MIOCK jitter meter ch=0
7465 08:06:32.116270
7466 08:06:32.118775 1T = (316-92) = 224 dly cells
7467 08:06:32.125273 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7468 08:06:32.125832 ==
7469 08:06:32.128422 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 08:06:32.131955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7471 08:06:32.132515 ==
7472 08:06:32.138074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7473 08:06:32.141667 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7474 08:06:32.148370 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7475 08:06:32.151492 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7476 08:06:32.161856 [CA 0] Center 43 (13~73) winsize 61
7477 08:06:32.164842 [CA 1] Center 43 (13~73) winsize 61
7478 08:06:32.168211 [CA 2] Center 38 (8~68) winsize 61
7479 08:06:32.171860 [CA 3] Center 37 (8~67) winsize 60
7480 08:06:32.174520 [CA 4] Center 36 (6~66) winsize 61
7481 08:06:32.177948 [CA 5] Center 35 (5~65) winsize 61
7482 08:06:32.178403
7483 08:06:32.181092 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7484 08:06:32.181584
7485 08:06:32.184478 [CATrainingPosCal] consider 1 rank data
7486 08:06:32.188052 u2DelayCellTimex100 = 290/100 ps
7487 08:06:32.191492 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7488 08:06:32.197587 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7489 08:06:32.200866 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7490 08:06:32.204295 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7491 08:06:32.208064 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7492 08:06:32.211179 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7493 08:06:32.211944
7494 08:06:32.214582 CA PerBit enable=1, Macro0, CA PI delay=35
7495 08:06:32.215039
7496 08:06:32.217657 [CBTSetCACLKResult] CA Dly = 35
7497 08:06:32.221151 CS Dly: 9 (0~40)
7498 08:06:32.224856 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7499 08:06:32.227886 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7500 08:06:32.228445 ==
7501 08:06:32.231510 Dram Type= 6, Freq= 0, CH_0, rank 1
7502 08:06:32.234428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 08:06:32.234987 ==
7504 08:06:32.241506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 08:06:32.244658 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 08:06:32.251221 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 08:06:32.254341 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 08:06:32.265089 [CA 0] Center 43 (13~73) winsize 61
7509 08:06:32.268277 [CA 1] Center 43 (13~73) winsize 61
7510 08:06:32.271555 [CA 2] Center 37 (8~67) winsize 60
7511 08:06:32.274664 [CA 3] Center 38 (8~68) winsize 61
7512 08:06:32.278131 [CA 4] Center 36 (6~66) winsize 61
7513 08:06:32.281398 [CA 5] Center 36 (6~66) winsize 61
7514 08:06:32.281952
7515 08:06:32.284356 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 08:06:32.284810
7517 08:06:32.288029 [CATrainingPosCal] consider 2 rank data
7518 08:06:32.291644 u2DelayCellTimex100 = 290/100 ps
7519 08:06:32.294432 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7520 08:06:32.301184 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7521 08:06:32.304694 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7522 08:06:32.308140 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7523 08:06:32.311278 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7524 08:06:32.314594 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7525 08:06:32.315051
7526 08:06:32.318112 CA PerBit enable=1, Macro0, CA PI delay=35
7527 08:06:32.318661
7528 08:06:32.321045 [CBTSetCACLKResult] CA Dly = 35
7529 08:06:32.321503 CS Dly: 10 (0~43)
7530 08:06:32.328307 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 08:06:32.331304 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 08:06:32.331847
7533 08:06:32.335096 ----->DramcWriteLeveling(PI) begin...
7534 08:06:32.335653 ==
7535 08:06:32.338070 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 08:06:32.341573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 08:06:32.342126 ==
7538 08:06:32.344824 Write leveling (Byte 0): 38 => 38
7539 08:06:32.348031 Write leveling (Byte 1): 33 => 33
7540 08:06:32.351485 DramcWriteLeveling(PI) end<-----
7541 08:06:32.352029
7542 08:06:32.352389 ==
7543 08:06:32.354983 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 08:06:32.358421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 08:06:32.361334 ==
7546 08:06:32.361789 [Gating] SW mode calibration
7547 08:06:32.371596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7548 08:06:32.374739 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7549 08:06:32.377720 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 08:06:32.384628 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 08:06:32.387577 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7552 08:06:32.391389 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7553 08:06:32.398037 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
7554 08:06:32.401251 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 08:06:32.404545 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 08:06:32.410935 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 08:06:32.414536 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 08:06:32.417642 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 08:06:32.424447 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7560 08:06:32.427749 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7561 08:06:32.431177 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7562 08:06:32.437985 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7563 08:06:32.440899 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 08:06:32.444594 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 08:06:32.451157 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 08:06:32.454415 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 08:06:32.457762 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7568 08:06:32.464310 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7569 08:06:32.467808 1 6 16 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
7570 08:06:32.470740 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7571 08:06:32.477567 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 08:06:32.480707 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 08:06:32.484241 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 08:06:32.490764 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 08:06:32.494215 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 08:06:32.497884 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 08:06:32.504233 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 08:06:32.507501 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 08:06:32.510782 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 08:06:32.517366 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 08:06:32.520296 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 08:06:32.523824 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 08:06:32.527103 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 08:06:32.533899 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 08:06:32.537024 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 08:06:32.543631 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 08:06:32.546930 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 08:06:32.549931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 08:06:32.553908 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 08:06:32.560217 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 08:06:32.563911 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 08:06:32.567014 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7593 08:06:32.570151 Total UI for P1: 0, mck2ui 16
7594 08:06:32.573741 best dqsien dly found for B0: ( 1, 9, 8)
7595 08:06:32.579904 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 08:06:32.583576 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 08:06:32.586419 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 08:06:32.589968 Total UI for P1: 0, mck2ui 16
7599 08:06:32.593595 best dqsien dly found for B1: ( 1, 9, 18)
7600 08:06:32.596488 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7601 08:06:32.599920 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7602 08:06:32.603108
7603 08:06:32.606813 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7604 08:06:32.609828 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7605 08:06:32.613269 [Gating] SW calibration Done
7606 08:06:32.613831 ==
7607 08:06:32.616772 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 08:06:32.619936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 08:06:32.620507 ==
7610 08:06:32.620876 RX Vref Scan: 0
7611 08:06:32.623446
7612 08:06:32.624006 RX Vref 0 -> 0, step: 1
7613 08:06:32.624379
7614 08:06:32.626532 RX Delay 0 -> 252, step: 8
7615 08:06:32.629479 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7616 08:06:32.632926 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7617 08:06:32.639604 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7618 08:06:32.642900 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7619 08:06:32.646305 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 08:06:32.649282 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7621 08:06:32.652907 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7622 08:06:32.659484 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7623 08:06:32.662523 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7624 08:06:32.666125 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7625 08:06:32.669722 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7626 08:06:32.673044 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7627 08:06:32.679591 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7628 08:06:32.682963 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7629 08:06:32.686224 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7630 08:06:32.689471 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7631 08:06:32.689928 ==
7632 08:06:32.693195 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 08:06:32.696233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 08:06:32.699560 ==
7635 08:06:32.700116 DQS Delay:
7636 08:06:32.700478 DQS0 = 0, DQS1 = 0
7637 08:06:32.702858 DQM Delay:
7638 08:06:32.703314 DQM0 = 138, DQM1 = 127
7639 08:06:32.706359 DQ Delay:
7640 08:06:32.709652 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7641 08:06:32.713002 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7642 08:06:32.716149 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7643 08:06:32.719465 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7644 08:06:32.720029
7645 08:06:32.720389
7646 08:06:32.720720 ==
7647 08:06:32.722801 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 08:06:32.725899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 08:06:32.726461 ==
7650 08:06:32.726822
7651 08:06:32.729557
7652 08:06:32.730107 TX Vref Scan disable
7653 08:06:32.733017 == TX Byte 0 ==
7654 08:06:32.736154 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7655 08:06:32.739054 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7656 08:06:32.742588 == TX Byte 1 ==
7657 08:06:32.745997 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7658 08:06:32.749418 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7659 08:06:32.749877 ==
7660 08:06:32.752377 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 08:06:32.759399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 08:06:32.759963 ==
7663 08:06:32.771271
7664 08:06:32.774459 TX Vref early break, caculate TX vref
7665 08:06:32.777852 TX Vref=16, minBit 0, minWin=23, winSum=374
7666 08:06:32.781774 TX Vref=18, minBit 0, minWin=23, winSum=387
7667 08:06:32.784331 TX Vref=20, minBit 0, minWin=24, winSum=394
7668 08:06:32.787310 TX Vref=22, minBit 2, minWin=24, winSum=403
7669 08:06:32.791016 TX Vref=24, minBit 7, minWin=24, winSum=415
7670 08:06:32.797398 TX Vref=26, minBit 0, minWin=26, winSum=427
7671 08:06:32.801211 TX Vref=28, minBit 4, minWin=25, winSum=429
7672 08:06:32.804369 TX Vref=30, minBit 0, minWin=26, winSum=426
7673 08:06:32.807531 TX Vref=32, minBit 6, minWin=25, winSum=416
7674 08:06:32.810924 TX Vref=34, minBit 7, minWin=24, winSum=404
7675 08:06:32.817871 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
7676 08:06:32.818436
7677 08:06:32.820729 Final TX Range 0 Vref 26
7678 08:06:32.821344
7679 08:06:32.821748 ==
7680 08:06:32.824105 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 08:06:32.827619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 08:06:32.828190 ==
7683 08:06:32.828555
7684 08:06:32.828885
7685 08:06:32.830961 TX Vref Scan disable
7686 08:06:32.837480 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 08:06:32.838068 == TX Byte 0 ==
7688 08:06:32.841099 u2DelayCellOfst[0]=13 cells (4 PI)
7689 08:06:32.844035 u2DelayCellOfst[1]=16 cells (5 PI)
7690 08:06:32.847940 u2DelayCellOfst[2]=13 cells (4 PI)
7691 08:06:32.850463 u2DelayCellOfst[3]=13 cells (4 PI)
7692 08:06:32.854070 u2DelayCellOfst[4]=6 cells (2 PI)
7693 08:06:32.857281 u2DelayCellOfst[5]=0 cells (0 PI)
7694 08:06:32.860432 u2DelayCellOfst[6]=16 cells (5 PI)
7695 08:06:32.860885 u2DelayCellOfst[7]=16 cells (5 PI)
7696 08:06:32.866912 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7697 08:06:32.870104 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7698 08:06:32.873589 == TX Byte 1 ==
7699 08:06:32.874155 u2DelayCellOfst[8]=0 cells (0 PI)
7700 08:06:32.877158 u2DelayCellOfst[9]=0 cells (0 PI)
7701 08:06:32.880671 u2DelayCellOfst[10]=6 cells (2 PI)
7702 08:06:32.884320 u2DelayCellOfst[11]=3 cells (1 PI)
7703 08:06:32.886876 u2DelayCellOfst[12]=13 cells (4 PI)
7704 08:06:32.890759 u2DelayCellOfst[13]=10 cells (3 PI)
7705 08:06:32.893475 u2DelayCellOfst[14]=16 cells (5 PI)
7706 08:06:32.896904 u2DelayCellOfst[15]=13 cells (4 PI)
7707 08:06:32.900636 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7708 08:06:32.906972 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7709 08:06:32.907542 DramC Write-DBI on
7710 08:06:32.907910 ==
7711 08:06:32.910496 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 08:06:32.913342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 08:06:32.916850 ==
7714 08:06:32.917459
7715 08:06:32.917825
7716 08:06:32.918159 TX Vref Scan disable
7717 08:06:32.920492 == TX Byte 0 ==
7718 08:06:32.923484 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7719 08:06:32.927072 == TX Byte 1 ==
7720 08:06:32.931090 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7721 08:06:32.934061 DramC Write-DBI off
7722 08:06:32.934619
7723 08:06:32.934984 [DATLAT]
7724 08:06:32.935321 Freq=1600, CH0 RK0
7725 08:06:32.935645
7726 08:06:32.936784 DATLAT Default: 0xf
7727 08:06:32.937268 0, 0xFFFF, sum = 0
7728 08:06:32.940614 1, 0xFFFF, sum = 0
7729 08:06:32.941221 2, 0xFFFF, sum = 0
7730 08:06:32.943757 3, 0xFFFF, sum = 0
7731 08:06:32.946950 4, 0xFFFF, sum = 0
7732 08:06:32.947522 5, 0xFFFF, sum = 0
7733 08:06:32.950614 6, 0xFFFF, sum = 0
7734 08:06:32.951269 7, 0xFFFF, sum = 0
7735 08:06:32.953674 8, 0xFFFF, sum = 0
7736 08:06:32.954238 9, 0xFFFF, sum = 0
7737 08:06:32.956773 10, 0xFFFF, sum = 0
7738 08:06:32.957279 11, 0xFFFF, sum = 0
7739 08:06:32.960002 12, 0xFFFF, sum = 0
7740 08:06:32.960564 13, 0xFFFF, sum = 0
7741 08:06:32.963372 14, 0x0, sum = 1
7742 08:06:32.963841 15, 0x0, sum = 2
7743 08:06:32.966853 16, 0x0, sum = 3
7744 08:06:32.967417 17, 0x0, sum = 4
7745 08:06:32.970079 best_step = 15
7746 08:06:32.970637
7747 08:06:32.971130 ==
7748 08:06:32.973638 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 08:06:32.976808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 08:06:32.977415 ==
7751 08:06:32.977790 RX Vref Scan: 1
7752 08:06:32.980071
7753 08:06:32.980654 Set Vref Range= 24 -> 127
7754 08:06:32.981204
7755 08:06:32.983097 RX Vref 24 -> 127, step: 1
7756 08:06:32.983676
7757 08:06:32.986646 RX Delay 19 -> 252, step: 4
7758 08:06:32.987106
7759 08:06:32.990139 Set Vref, RX VrefLevel [Byte0]: 24
7760 08:06:32.993677 [Byte1]: 24
7761 08:06:32.994244
7762 08:06:32.996856 Set Vref, RX VrefLevel [Byte0]: 25
7763 08:06:33.000282 [Byte1]: 25
7764 08:06:33.000851
7765 08:06:33.003710 Set Vref, RX VrefLevel [Byte0]: 26
7766 08:06:33.006730 [Byte1]: 26
7767 08:06:33.010874
7768 08:06:33.011441 Set Vref, RX VrefLevel [Byte0]: 27
7769 08:06:33.013735 [Byte1]: 27
7770 08:06:33.018007
7771 08:06:33.018569 Set Vref, RX VrefLevel [Byte0]: 28
7772 08:06:33.021618 [Byte1]: 28
7773 08:06:33.025832
7774 08:06:33.026394 Set Vref, RX VrefLevel [Byte0]: 29
7775 08:06:33.029135 [Byte1]: 29
7776 08:06:33.033570
7777 08:06:33.034136 Set Vref, RX VrefLevel [Byte0]: 30
7778 08:06:33.036669 [Byte1]: 30
7779 08:06:33.041148
7780 08:06:33.041713 Set Vref, RX VrefLevel [Byte0]: 31
7781 08:06:33.044257 [Byte1]: 31
7782 08:06:33.048472
7783 08:06:33.049066 Set Vref, RX VrefLevel [Byte0]: 32
7784 08:06:33.051755 [Byte1]: 32
7785 08:06:33.055906
7786 08:06:33.056468 Set Vref, RX VrefLevel [Byte0]: 33
7787 08:06:33.059769 [Byte1]: 33
7788 08:06:33.063449
7789 08:06:33.063912 Set Vref, RX VrefLevel [Byte0]: 34
7790 08:06:33.067211 [Byte1]: 34
7791 08:06:33.070984
7792 08:06:33.071544 Set Vref, RX VrefLevel [Byte0]: 35
7793 08:06:33.074773 [Byte1]: 35
7794 08:06:33.078654
7795 08:06:33.079202 Set Vref, RX VrefLevel [Byte0]: 36
7796 08:06:33.081909 [Byte1]: 36
7797 08:06:33.086537
7798 08:06:33.087008 Set Vref, RX VrefLevel [Byte0]: 37
7799 08:06:33.089475 [Byte1]: 37
7800 08:06:33.093725
7801 08:06:33.094316 Set Vref, RX VrefLevel [Byte0]: 38
7802 08:06:33.097189 [Byte1]: 38
7803 08:06:33.101488
7804 08:06:33.102056 Set Vref, RX VrefLevel [Byte0]: 39
7805 08:06:33.105055 [Byte1]: 39
7806 08:06:33.109194
7807 08:06:33.109761 Set Vref, RX VrefLevel [Byte0]: 40
7808 08:06:33.112266 [Byte1]: 40
7809 08:06:33.117132
7810 08:06:33.117700 Set Vref, RX VrefLevel [Byte0]: 41
7811 08:06:33.120764 [Byte1]: 41
7812 08:06:33.124241
7813 08:06:33.124805 Set Vref, RX VrefLevel [Byte0]: 42
7814 08:06:33.127651 [Byte1]: 42
7815 08:06:33.131941
7816 08:06:33.132502 Set Vref, RX VrefLevel [Byte0]: 43
7817 08:06:33.135686 [Byte1]: 43
7818 08:06:33.139235
7819 08:06:33.139691 Set Vref, RX VrefLevel [Byte0]: 44
7820 08:06:33.142938 [Byte1]: 44
7821 08:06:33.146882
7822 08:06:33.147433 Set Vref, RX VrefLevel [Byte0]: 45
7823 08:06:33.150314 [Byte1]: 45
7824 08:06:33.154782
7825 08:06:33.155333 Set Vref, RX VrefLevel [Byte0]: 46
7826 08:06:33.157780 [Byte1]: 46
7827 08:06:33.162034
7828 08:06:33.162741 Set Vref, RX VrefLevel [Byte0]: 47
7829 08:06:33.165054 [Byte1]: 47
7830 08:06:33.169638
7831 08:06:33.170192 Set Vref, RX VrefLevel [Byte0]: 48
7832 08:06:33.173057 [Byte1]: 48
7833 08:06:33.177364
7834 08:06:33.177916 Set Vref, RX VrefLevel [Byte0]: 49
7835 08:06:33.180276 [Byte1]: 49
7836 08:06:33.185066
7837 08:06:33.185611 Set Vref, RX VrefLevel [Byte0]: 50
7838 08:06:33.188076 [Byte1]: 50
7839 08:06:33.192701
7840 08:06:33.193302 Set Vref, RX VrefLevel [Byte0]: 51
7841 08:06:33.195744 [Byte1]: 51
7842 08:06:33.199926
7843 08:06:33.200503 Set Vref, RX VrefLevel [Byte0]: 52
7844 08:06:33.203232 [Byte1]: 52
7845 08:06:33.207758
7846 08:06:33.208307 Set Vref, RX VrefLevel [Byte0]: 53
7847 08:06:33.210857 [Byte1]: 53
7848 08:06:33.215293
7849 08:06:33.215844 Set Vref, RX VrefLevel [Byte0]: 54
7850 08:06:33.218596 [Byte1]: 54
7851 08:06:33.222745
7852 08:06:33.223293 Set Vref, RX VrefLevel [Byte0]: 55
7853 08:06:33.226145 [Byte1]: 55
7854 08:06:33.230418
7855 08:06:33.231075 Set Vref, RX VrefLevel [Byte0]: 56
7856 08:06:33.233528 [Byte1]: 56
7857 08:06:33.237718
7858 08:06:33.238275 Set Vref, RX VrefLevel [Byte0]: 57
7859 08:06:33.241195 [Byte1]: 57
7860 08:06:33.245342
7861 08:06:33.245899 Set Vref, RX VrefLevel [Byte0]: 58
7862 08:06:33.248660 [Byte1]: 58
7863 08:06:33.253177
7864 08:06:33.253739 Set Vref, RX VrefLevel [Byte0]: 59
7865 08:06:33.256614 [Byte1]: 59
7866 08:06:33.260514
7867 08:06:33.261098 Set Vref, RX VrefLevel [Byte0]: 60
7868 08:06:33.263693 [Byte1]: 60
7869 08:06:33.268107
7870 08:06:33.268659 Set Vref, RX VrefLevel [Byte0]: 61
7871 08:06:33.271654 [Byte1]: 61
7872 08:06:33.275778
7873 08:06:33.276331 Set Vref, RX VrefLevel [Byte0]: 62
7874 08:06:33.279003 [Byte1]: 62
7875 08:06:33.282913
7876 08:06:33.283425 Set Vref, RX VrefLevel [Byte0]: 63
7877 08:06:33.286256 [Byte1]: 63
7878 08:06:33.291489
7879 08:06:33.292048 Set Vref, RX VrefLevel [Byte0]: 64
7880 08:06:33.293869 [Byte1]: 64
7881 08:06:33.298218
7882 08:06:33.298672 Set Vref, RX VrefLevel [Byte0]: 65
7883 08:06:33.301471 [Byte1]: 65
7884 08:06:33.306066
7885 08:06:33.306651 Set Vref, RX VrefLevel [Byte0]: 66
7886 08:06:33.309094 [Byte1]: 66
7887 08:06:33.313845
7888 08:06:33.314412 Set Vref, RX VrefLevel [Byte0]: 67
7889 08:06:33.316803 [Byte1]: 67
7890 08:06:33.321565
7891 08:06:33.322131 Set Vref, RX VrefLevel [Byte0]: 68
7892 08:06:33.324455 [Byte1]: 68
7893 08:06:33.329078
7894 08:06:33.329639 Set Vref, RX VrefLevel [Byte0]: 69
7895 08:06:33.332010 [Byte1]: 69
7896 08:06:33.336234
7897 08:06:33.336799 Set Vref, RX VrefLevel [Byte0]: 70
7898 08:06:33.339383 [Byte1]: 70
7899 08:06:33.343861
7900 08:06:33.344425 Set Vref, RX VrefLevel [Byte0]: 71
7901 08:06:33.347360 [Byte1]: 71
7902 08:06:33.351365
7903 08:06:33.351933 Set Vref, RX VrefLevel [Byte0]: 72
7904 08:06:33.354729 [Byte1]: 72
7905 08:06:33.358916
7906 08:06:33.359478 Set Vref, RX VrefLevel [Byte0]: 73
7907 08:06:33.362161 [Byte1]: 73
7908 08:06:33.366920
7909 08:06:33.367494 Set Vref, RX VrefLevel [Byte0]: 74
7910 08:06:33.369712 [Byte1]: 74
7911 08:06:33.374330
7912 08:06:33.374896 Set Vref, RX VrefLevel [Byte0]: 75
7913 08:06:33.377352 [Byte1]: 75
7914 08:06:33.381634
7915 08:06:33.382201 Set Vref, RX VrefLevel [Byte0]: 76
7916 08:06:33.385093 [Byte1]: 76
7917 08:06:33.389027
7918 08:06:33.389490 Set Vref, RX VrefLevel [Byte0]: 77
7919 08:06:33.392355 [Byte1]: 77
7920 08:06:33.396455
7921 08:06:33.396914 Set Vref, RX VrefLevel [Byte0]: 78
7922 08:06:33.399678 [Byte1]: 78
7923 08:06:33.404371
7924 08:06:33.404823 Set Vref, RX VrefLevel [Byte0]: 79
7925 08:06:33.407620 [Byte1]: 79
7926 08:06:33.411943
7927 08:06:33.412508 Set Vref, RX VrefLevel [Byte0]: 80
7928 08:06:33.414925 [Byte1]: 80
7929 08:06:33.419507
7930 08:06:33.420072 Final RX Vref Byte 0 = 61 to rank0
7931 08:06:33.422863 Final RX Vref Byte 1 = 61 to rank0
7932 08:06:33.426353 Final RX Vref Byte 0 = 61 to rank1
7933 08:06:33.429393 Final RX Vref Byte 1 = 61 to rank1==
7934 08:06:33.432782 Dram Type= 6, Freq= 0, CH_0, rank 0
7935 08:06:33.439535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7936 08:06:33.440094 ==
7937 08:06:33.440460 DQS Delay:
7938 08:06:33.440794 DQS0 = 0, DQS1 = 0
7939 08:06:33.442666 DQM Delay:
7940 08:06:33.443124 DQM0 = 137, DQM1 = 124
7941 08:06:33.446393 DQ Delay:
7942 08:06:33.449824 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7943 08:06:33.452895 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7944 08:06:33.456162 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
7945 08:06:33.459461 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7946 08:06:33.460020
7947 08:06:33.460381
7948 08:06:33.460714
7949 08:06:33.462584 [DramC_TX_OE_Calibration] TA2
7950 08:06:33.466212 Original DQ_B0 (3 6) =30, OEN = 27
7951 08:06:33.469280 Original DQ_B1 (3 6) =30, OEN = 27
7952 08:06:33.472585 24, 0x0, End_B0=24 End_B1=24
7953 08:06:33.473173 25, 0x0, End_B0=25 End_B1=25
7954 08:06:33.476490 26, 0x0, End_B0=26 End_B1=26
7955 08:06:33.479698 27, 0x0, End_B0=27 End_B1=27
7956 08:06:33.482552 28, 0x0, End_B0=28 End_B1=28
7957 08:06:33.483017 29, 0x0, End_B0=29 End_B1=29
7958 08:06:33.486128 30, 0x0, End_B0=30 End_B1=30
7959 08:06:33.489179 31, 0x4141, End_B0=30 End_B1=30
7960 08:06:33.492997 Byte0 end_step=30 best_step=27
7961 08:06:33.496111 Byte1 end_step=30 best_step=27
7962 08:06:33.499506 Byte0 TX OE(2T, 0.5T) = (3, 3)
7963 08:06:33.500070 Byte1 TX OE(2T, 0.5T) = (3, 3)
7964 08:06:33.500433
7965 08:06:33.502568
7966 08:06:33.509301 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7967 08:06:33.512880 CH0 RK0: MR19=303, MR18=1E1C
7968 08:06:33.519086 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7969 08:06:33.519554
7970 08:06:33.522664 ----->DramcWriteLeveling(PI) begin...
7971 08:06:33.523238 ==
7972 08:06:33.525828 Dram Type= 6, Freq= 0, CH_0, rank 1
7973 08:06:33.529336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7974 08:06:33.529803 ==
7975 08:06:33.532819 Write leveling (Byte 0): 36 => 36
7976 08:06:33.536287 Write leveling (Byte 1): 27 => 27
7977 08:06:33.539709 DramcWriteLeveling(PI) end<-----
7978 08:06:33.540283
7979 08:06:33.540651 ==
7980 08:06:33.543002 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 08:06:33.546035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 08:06:33.546603 ==
7983 08:06:33.549183 [Gating] SW mode calibration
7984 08:06:33.556314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7985 08:06:33.562688 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7986 08:06:33.565767 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 08:06:33.569522 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 08:06:33.575958 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 08:06:33.579253 1 4 12 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
7990 08:06:33.582769 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 08:06:33.589498 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 08:06:33.592774 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 08:06:33.595873 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 08:06:33.602645 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 08:06:33.606250 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 08:06:33.609268 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7997 08:06:33.615937 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7998 08:06:33.619372 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7999 08:06:33.622411 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 08:06:33.629314 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 08:06:33.632594 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 08:06:33.635919 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 08:06:33.638961 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 08:06:33.645858 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8005 08:06:33.649797 1 6 12 | B1->B0 | 2d2d 4343 | 1 0 | (0 0) (0 0)
8006 08:06:33.652482 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 08:06:33.659298 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 08:06:33.662525 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 08:06:33.665901 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 08:06:33.672607 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 08:06:33.675733 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 08:06:33.679129 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 08:06:33.685703 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8014 08:06:33.689205 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8015 08:06:33.692334 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 08:06:33.698724 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 08:06:33.702246 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 08:06:33.705669 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 08:06:33.712255 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 08:06:33.715683 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 08:06:33.719004 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 08:06:33.725868 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 08:06:33.728847 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 08:06:33.731982 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 08:06:33.738657 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 08:06:33.742152 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 08:06:33.745400 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 08:06:33.752466 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8029 08:06:33.755578 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8030 08:06:33.758725 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8031 08:06:33.762361 Total UI for P1: 0, mck2ui 16
8032 08:06:33.765372 best dqsien dly found for B0: ( 1, 9, 10)
8033 08:06:33.769122 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 08:06:33.772449 Total UI for P1: 0, mck2ui 16
8035 08:06:33.775676 best dqsien dly found for B1: ( 1, 9, 16)
8036 08:06:33.778892 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8037 08:06:33.785558 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8038 08:06:33.786273
8039 08:06:33.788855 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8040 08:06:33.792184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8041 08:06:33.795614 [Gating] SW calibration Done
8042 08:06:33.796175 ==
8043 08:06:33.798685 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 08:06:33.802118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 08:06:33.802686 ==
8046 08:06:33.803058 RX Vref Scan: 0
8047 08:06:33.805338
8048 08:06:33.805890 RX Vref 0 -> 0, step: 1
8049 08:06:33.806259
8050 08:06:33.808634 RX Delay 0 -> 252, step: 8
8051 08:06:33.812155 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8052 08:06:33.815575 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8053 08:06:33.821958 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8054 08:06:33.825582 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8055 08:06:33.829213 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8056 08:06:33.832067 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8057 08:06:33.835123 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8058 08:06:33.841760 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8059 08:06:33.845430 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8060 08:06:33.848503 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8061 08:06:33.851822 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8062 08:06:33.854983 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8063 08:06:33.862004 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8064 08:06:33.864916 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8065 08:06:33.868562 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8066 08:06:33.871968 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8067 08:06:33.872523 ==
8068 08:06:33.875550 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 08:06:33.881854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 08:06:33.882418 ==
8071 08:06:33.882789 DQS Delay:
8072 08:06:33.883130 DQS0 = 0, DQS1 = 0
8073 08:06:33.885866 DQM Delay:
8074 08:06:33.886628 DQM0 = 136, DQM1 = 125
8075 08:06:33.888504 DQ Delay:
8076 08:06:33.892044 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8077 08:06:33.895493 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8078 08:06:33.898177 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8079 08:06:33.901861 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8080 08:06:33.902418
8081 08:06:33.902783
8082 08:06:33.903122 ==
8083 08:06:33.905070 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 08:06:33.908588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 08:06:33.911845 ==
8086 08:06:33.912393
8087 08:06:33.912758
8088 08:06:33.913161 TX Vref Scan disable
8089 08:06:33.915633 == TX Byte 0 ==
8090 08:06:33.918143 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8091 08:06:33.921407 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8092 08:06:33.924553 == TX Byte 1 ==
8093 08:06:33.928700 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8094 08:06:33.931573 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8095 08:06:33.934868 ==
8096 08:06:33.935426 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 08:06:33.941498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 08:06:33.942044 ==
8099 08:06:33.955806
8100 08:06:33.959442 TX Vref early break, caculate TX vref
8101 08:06:33.962473 TX Vref=16, minBit 0, minWin=23, winSum=388
8102 08:06:33.965616 TX Vref=18, minBit 0, minWin=24, winSum=394
8103 08:06:33.969069 TX Vref=20, minBit 0, minWin=24, winSum=403
8104 08:06:33.972795 TX Vref=22, minBit 0, minWin=24, winSum=410
8105 08:06:33.975637 TX Vref=24, minBit 8, minWin=25, winSum=419
8106 08:06:33.982800 TX Vref=26, minBit 0, minWin=26, winSum=424
8107 08:06:33.985589 TX Vref=28, minBit 0, minWin=25, winSum=427
8108 08:06:33.989174 TX Vref=30, minBit 0, minWin=25, winSum=424
8109 08:06:33.992413 TX Vref=32, minBit 1, minWin=25, winSum=415
8110 08:06:33.995737 TX Vref=34, minBit 2, minWin=24, winSum=405
8111 08:06:33.998634 TX Vref=36, minBit 0, minWin=24, winSum=398
8112 08:06:34.005628 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 26
8113 08:06:34.006186
8114 08:06:34.009137 Final TX Range 0 Vref 26
8115 08:06:34.009687
8116 08:06:34.010053 ==
8117 08:06:34.012537 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 08:06:34.015418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 08:06:34.015976 ==
8120 08:06:34.016343
8121 08:06:34.016680
8122 08:06:34.019217 TX Vref Scan disable
8123 08:06:34.025416 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8124 08:06:34.025973 == TX Byte 0 ==
8125 08:06:34.029216 u2DelayCellOfst[0]=10 cells (3 PI)
8126 08:06:34.032346 u2DelayCellOfst[1]=16 cells (5 PI)
8127 08:06:34.035860 u2DelayCellOfst[2]=10 cells (3 PI)
8128 08:06:34.039284 u2DelayCellOfst[3]=10 cells (3 PI)
8129 08:06:34.042442 u2DelayCellOfst[4]=6 cells (2 PI)
8130 08:06:34.045601 u2DelayCellOfst[5]=0 cells (0 PI)
8131 08:06:34.048640 u2DelayCellOfst[6]=16 cells (5 PI)
8132 08:06:34.052076 u2DelayCellOfst[7]=16 cells (5 PI)
8133 08:06:34.055578 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8134 08:06:34.058776 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8135 08:06:34.062325 == TX Byte 1 ==
8136 08:06:34.065178 u2DelayCellOfst[8]=0 cells (0 PI)
8137 08:06:34.069104 u2DelayCellOfst[9]=0 cells (0 PI)
8138 08:06:34.069663 u2DelayCellOfst[10]=6 cells (2 PI)
8139 08:06:34.072040 u2DelayCellOfst[11]=3 cells (1 PI)
8140 08:06:34.075116 u2DelayCellOfst[12]=10 cells (3 PI)
8141 08:06:34.078643 u2DelayCellOfst[13]=10 cells (3 PI)
8142 08:06:34.082072 u2DelayCellOfst[14]=13 cells (4 PI)
8143 08:06:34.085320 u2DelayCellOfst[15]=10 cells (3 PI)
8144 08:06:34.092152 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8145 08:06:34.095372 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8146 08:06:34.095932 DramC Write-DBI on
8147 08:06:34.096299 ==
8148 08:06:34.098552 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 08:06:34.105753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 08:06:34.106311 ==
8151 08:06:34.106678
8152 08:06:34.107016
8153 08:06:34.107343 TX Vref Scan disable
8154 08:06:34.109046 == TX Byte 0 ==
8155 08:06:34.112704 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8156 08:06:34.115994 == TX Byte 1 ==
8157 08:06:34.119326 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8158 08:06:34.122825 DramC Write-DBI off
8159 08:06:34.123382
8160 08:06:34.123750 [DATLAT]
8161 08:06:34.124096 Freq=1600, CH0 RK1
8162 08:06:34.124430
8163 08:06:34.126167 DATLAT Default: 0xf
8164 08:06:34.126628 0, 0xFFFF, sum = 0
8165 08:06:34.129540 1, 0xFFFF, sum = 0
8166 08:06:34.130105 2, 0xFFFF, sum = 0
8167 08:06:34.132655 3, 0xFFFF, sum = 0
8168 08:06:34.133147 4, 0xFFFF, sum = 0
8169 08:06:34.136357 5, 0xFFFF, sum = 0
8170 08:06:34.136921 6, 0xFFFF, sum = 0
8171 08:06:34.139713 7, 0xFFFF, sum = 0
8172 08:06:34.142550 8, 0xFFFF, sum = 0
8173 08:06:34.143036 9, 0xFFFF, sum = 0
8174 08:06:34.146472 10, 0xFFFF, sum = 0
8175 08:06:34.147037 11, 0xFFFF, sum = 0
8176 08:06:34.149565 12, 0xFFFF, sum = 0
8177 08:06:34.150129 13, 0xFFFF, sum = 0
8178 08:06:34.152959 14, 0x0, sum = 1
8179 08:06:34.153433 15, 0x0, sum = 2
8180 08:06:34.156018 16, 0x0, sum = 3
8181 08:06:34.156577 17, 0x0, sum = 4
8182 08:06:34.159256 best_step = 15
8183 08:06:34.159811
8184 08:06:34.160176 ==
8185 08:06:34.162384 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 08:06:34.165954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 08:06:34.166421 ==
8188 08:06:34.166788 RX Vref Scan: 0
8189 08:06:34.167164
8190 08:06:34.169494 RX Vref 0 -> 0, step: 1
8191 08:06:34.170049
8192 08:06:34.172605 RX Delay 11 -> 252, step: 4
8193 08:06:34.175821 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8194 08:06:34.182727 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8195 08:06:34.185830 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8196 08:06:34.189100 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8197 08:06:34.193086 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8198 08:06:34.196164 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8199 08:06:34.199371 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8200 08:06:34.205955 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8201 08:06:34.209531 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8202 08:06:34.212599 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8203 08:06:34.216094 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8204 08:06:34.219245 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8205 08:06:34.225799 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8206 08:06:34.229089 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8207 08:06:34.232584 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8208 08:06:34.235928 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8209 08:06:34.236487 ==
8210 08:06:34.239076 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 08:06:34.245787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 08:06:34.246345 ==
8213 08:06:34.246718 DQS Delay:
8214 08:06:34.249060 DQS0 = 0, DQS1 = 0
8215 08:06:34.249614 DQM Delay:
8216 08:06:34.252598 DQM0 = 133, DQM1 = 123
8217 08:06:34.253185 DQ Delay:
8218 08:06:34.255696 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8219 08:06:34.258991 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8220 08:06:34.262197 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8221 08:06:34.265674 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8222 08:06:34.266237
8223 08:06:34.266604
8224 08:06:34.266941
8225 08:06:34.268887 [DramC_TX_OE_Calibration] TA2
8226 08:06:34.272154 Original DQ_B0 (3 6) =30, OEN = 27
8227 08:06:34.275470 Original DQ_B1 (3 6) =30, OEN = 27
8228 08:06:34.278873 24, 0x0, End_B0=24 End_B1=24
8229 08:06:34.282046 25, 0x0, End_B0=25 End_B1=25
8230 08:06:34.282518 26, 0x0, End_B0=26 End_B1=26
8231 08:06:34.285641 27, 0x0, End_B0=27 End_B1=27
8232 08:06:34.288432 28, 0x0, End_B0=28 End_B1=28
8233 08:06:34.291962 29, 0x0, End_B0=29 End_B1=29
8234 08:06:34.292442 30, 0x0, End_B0=30 End_B1=30
8235 08:06:34.295326 31, 0x4141, End_B0=30 End_B1=30
8236 08:06:34.298674 Byte0 end_step=30 best_step=27
8237 08:06:34.302249 Byte1 end_step=30 best_step=27
8238 08:06:34.305255 Byte0 TX OE(2T, 0.5T) = (3, 3)
8239 08:06:34.308510 Byte1 TX OE(2T, 0.5T) = (3, 3)
8240 08:06:34.309010
8241 08:06:34.309377
8242 08:06:34.315442 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8243 08:06:34.318768 CH0 RK1: MR19=303, MR18=210E
8244 08:06:34.325299 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8245 08:06:34.328864 [RxdqsGatingPostProcess] freq 1600
8246 08:06:34.332156 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8247 08:06:34.335834 best DQS0 dly(2T, 0.5T) = (1, 1)
8248 08:06:34.338889 best DQS1 dly(2T, 0.5T) = (1, 1)
8249 08:06:34.341923 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8250 08:06:34.345749 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8251 08:06:34.348867 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 08:06:34.352320 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 08:06:34.355723 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 08:06:34.358817 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 08:06:34.362269 Pre-setting of DQS Precalculation
8256 08:06:34.365582 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8257 08:06:34.366289 ==
8258 08:06:34.369222 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 08:06:34.372347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 08:06:34.372905 ==
8261 08:06:34.378802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 08:06:34.382169 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 08:06:34.388792 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 08:06:34.392156 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 08:06:34.402190 [CA 0] Center 40 (11~70) winsize 60
8266 08:06:34.405250 [CA 1] Center 41 (11~71) winsize 61
8267 08:06:34.409159 [CA 2] Center 37 (8~67) winsize 60
8268 08:06:34.412112 [CA 3] Center 36 (7~66) winsize 60
8269 08:06:34.415379 [CA 4] Center 36 (7~66) winsize 60
8270 08:06:34.418644 [CA 5] Center 35 (5~66) winsize 62
8271 08:06:34.419305
8272 08:06:34.421933 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8273 08:06:34.422394
8274 08:06:34.425220 [CATrainingPosCal] consider 1 rank data
8275 08:06:34.428439 u2DelayCellTimex100 = 290/100 ps
8276 08:06:34.431900 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8277 08:06:34.438781 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8278 08:06:34.441869 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
8279 08:06:34.445358 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8280 08:06:34.449018 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8281 08:06:34.452075 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8282 08:06:34.452631
8283 08:06:34.455343 CA PerBit enable=1, Macro0, CA PI delay=35
8284 08:06:34.455898
8285 08:06:34.458816 [CBTSetCACLKResult] CA Dly = 35
8286 08:06:34.462373 CS Dly: 8 (0~39)
8287 08:06:34.465139 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 08:06:34.468517 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 08:06:34.469028 ==
8290 08:06:34.472257 Dram Type= 6, Freq= 0, CH_1, rank 1
8291 08:06:34.475495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 08:06:34.476055 ==
8293 08:06:34.481824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 08:06:34.485109 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 08:06:34.491941 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 08:06:34.494820 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 08:06:34.504965 [CA 0] Center 42 (13~72) winsize 60
8298 08:06:34.508533 [CA 1] Center 41 (11~71) winsize 61
8299 08:06:34.511873 [CA 2] Center 37 (8~67) winsize 60
8300 08:06:34.515280 [CA 3] Center 37 (8~67) winsize 60
8301 08:06:34.518577 [CA 4] Center 37 (8~67) winsize 60
8302 08:06:34.521858 [CA 5] Center 37 (7~67) winsize 61
8303 08:06:34.522321
8304 08:06:34.525531 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 08:06:34.525975
8306 08:06:34.528979 [CATrainingPosCal] consider 2 rank data
8307 08:06:34.532115 u2DelayCellTimex100 = 290/100 ps
8308 08:06:34.535482 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8309 08:06:34.541964 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8310 08:06:34.545768 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8311 08:06:34.548667 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 08:06:34.552269 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8313 08:06:34.555352 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 08:06:34.555899
8315 08:06:34.558673 CA PerBit enable=1, Macro0, CA PI delay=36
8316 08:06:34.559215
8317 08:06:34.562228 [CBTSetCACLKResult] CA Dly = 36
8318 08:06:34.562777 CS Dly: 9 (0~42)
8319 08:06:34.568793 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 08:06:34.572016 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 08:06:34.572560
8322 08:06:34.575475 ----->DramcWriteLeveling(PI) begin...
8323 08:06:34.576029 ==
8324 08:06:34.578740 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 08:06:34.581815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 08:06:34.582359 ==
8327 08:06:34.585172 Write leveling (Byte 0): 23 => 23
8328 08:06:34.588474 Write leveling (Byte 1): 29 => 29
8329 08:06:34.591583 DramcWriteLeveling(PI) end<-----
8330 08:06:34.592028
8331 08:06:34.592373 ==
8332 08:06:34.595261 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 08:06:34.601613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 08:06:34.602178 ==
8335 08:06:34.602591 [Gating] SW mode calibration
8336 08:06:34.612064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8337 08:06:34.615065 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8338 08:06:34.618376 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 08:06:34.625016 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 08:06:34.628488 1 4 8 | B1->B0 | 2c2c 2c2c | 0 1 | (0 0) (1 1)
8341 08:06:34.631721 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 08:06:34.638528 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 08:06:34.641775 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 08:06:34.644908 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 08:06:34.651874 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 08:06:34.655273 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 08:06:34.658475 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8348 08:06:34.665181 1 5 8 | B1->B0 | 3030 2a2a | 1 1 | (1 1) (1 0)
8349 08:06:34.668517 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8350 08:06:34.672007 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 08:06:34.678336 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 08:06:34.681750 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 08:06:34.685092 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 08:06:34.691400 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 08:06:34.695014 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8356 08:06:34.698269 1 6 8 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
8357 08:06:34.705091 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 08:06:34.708326 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 08:06:34.711558 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 08:06:34.718154 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 08:06:34.721435 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 08:06:34.724853 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 08:06:34.728511 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8364 08:06:34.735212 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8365 08:06:34.737983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 08:06:34.741233 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 08:06:34.748126 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 08:06:34.751780 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 08:06:34.754858 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 08:06:34.761823 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 08:06:34.764843 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 08:06:34.768253 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 08:06:34.774778 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 08:06:34.777987 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 08:06:34.781301 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 08:06:34.788110 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 08:06:34.791225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 08:06:34.794802 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 08:06:34.801487 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8380 08:06:34.804840 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 08:06:34.807924 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8382 08:06:34.811330 Total UI for P1: 0, mck2ui 16
8383 08:06:34.814624 best dqsien dly found for B0: ( 1, 9, 6)
8384 08:06:34.821026 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 08:06:34.821588 Total UI for P1: 0, mck2ui 16
8386 08:06:34.827998 best dqsien dly found for B1: ( 1, 9, 10)
8387 08:06:34.831100 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8388 08:06:34.834902 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8389 08:06:34.835474
8390 08:06:34.837549 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8391 08:06:34.840839 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8392 08:06:34.844648 [Gating] SW calibration Done
8393 08:06:34.845243 ==
8394 08:06:34.848109 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 08:06:34.851196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 08:06:34.851661 ==
8397 08:06:34.854893 RX Vref Scan: 0
8398 08:06:34.855454
8399 08:06:34.855817 RX Vref 0 -> 0, step: 1
8400 08:06:34.856155
8401 08:06:34.858071 RX Delay 0 -> 252, step: 8
8402 08:06:34.861434 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8403 08:06:34.864697 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8404 08:06:34.871186 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8405 08:06:34.874610 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8406 08:06:34.878150 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8407 08:06:34.881314 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8408 08:06:34.884410 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8409 08:06:34.891608 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8410 08:06:34.894588 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8411 08:06:34.897577 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8412 08:06:34.901355 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8413 08:06:34.904538 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8414 08:06:34.907972 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8415 08:06:34.914534 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8416 08:06:34.917857 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8417 08:06:34.921143 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8418 08:06:34.921699 ==
8419 08:06:34.924448 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 08:06:34.927959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 08:06:34.930854 ==
8422 08:06:34.931312 DQS Delay:
8423 08:06:34.931676 DQS0 = 0, DQS1 = 0
8424 08:06:34.934423 DQM Delay:
8425 08:06:34.935027 DQM0 = 138, DQM1 = 130
8426 08:06:34.937415 DQ Delay:
8427 08:06:34.940855 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8428 08:06:34.944404 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8429 08:06:34.947869 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8430 08:06:34.950879 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8431 08:06:34.951337
8432 08:06:34.951697
8433 08:06:34.952032 ==
8434 08:06:34.954322 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 08:06:34.957573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 08:06:34.958036 ==
8437 08:06:34.958394
8438 08:06:34.961220
8439 08:06:34.961784 TX Vref Scan disable
8440 08:06:34.964495 == TX Byte 0 ==
8441 08:06:34.967973 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8442 08:06:34.971277 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8443 08:06:34.974201 == TX Byte 1 ==
8444 08:06:34.977871 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8445 08:06:34.981109 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8446 08:06:34.981667 ==
8447 08:06:34.984106 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 08:06:34.990755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 08:06:34.991297 ==
8450 08:06:35.002405
8451 08:06:35.005864 TX Vref early break, caculate TX vref
8452 08:06:35.009612 TX Vref=16, minBit 8, minWin=21, winSum=364
8453 08:06:35.012645 TX Vref=18, minBit 8, minWin=22, winSum=373
8454 08:06:35.016181 TX Vref=20, minBit 9, minWin=22, winSum=377
8455 08:06:35.019317 TX Vref=22, minBit 10, minWin=22, winSum=392
8456 08:06:35.022409 TX Vref=24, minBit 8, minWin=24, winSum=402
8457 08:06:35.029374 TX Vref=26, minBit 10, minWin=24, winSum=412
8458 08:06:35.032323 TX Vref=28, minBit 9, minWin=24, winSum=414
8459 08:06:35.035586 TX Vref=30, minBit 8, minWin=24, winSum=409
8460 08:06:35.039029 TX Vref=32, minBit 9, minWin=23, winSum=400
8461 08:06:35.042312 TX Vref=34, minBit 11, minWin=22, winSum=389
8462 08:06:35.049398 [TxChooseVref] Worse bit 9, Min win 24, Win sum 414, Final Vref 28
8463 08:06:35.049968
8464 08:06:35.052547 Final TX Range 0 Vref 28
8465 08:06:35.053132
8466 08:06:35.053490 ==
8467 08:06:35.055863 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 08:06:35.059170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 08:06:35.059732 ==
8470 08:06:35.060099
8471 08:06:35.060430
8472 08:06:35.062373 TX Vref Scan disable
8473 08:06:35.069049 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8474 08:06:35.069586 == TX Byte 0 ==
8475 08:06:35.072577 u2DelayCellOfst[0]=13 cells (4 PI)
8476 08:06:35.075855 u2DelayCellOfst[1]=10 cells (3 PI)
8477 08:06:35.079391 u2DelayCellOfst[2]=0 cells (0 PI)
8478 08:06:35.082512 u2DelayCellOfst[3]=3 cells (1 PI)
8479 08:06:35.085848 u2DelayCellOfst[4]=6 cells (2 PI)
8480 08:06:35.089064 u2DelayCellOfst[5]=16 cells (5 PI)
8481 08:06:35.092221 u2DelayCellOfst[6]=16 cells (5 PI)
8482 08:06:35.092681 u2DelayCellOfst[7]=3 cells (1 PI)
8483 08:06:35.099376 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8484 08:06:35.102284 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8485 08:06:35.102744 == TX Byte 1 ==
8486 08:06:35.105799 u2DelayCellOfst[8]=0 cells (0 PI)
8487 08:06:35.109267 u2DelayCellOfst[9]=3 cells (1 PI)
8488 08:06:35.112815 u2DelayCellOfst[10]=10 cells (3 PI)
8489 08:06:35.115710 u2DelayCellOfst[11]=3 cells (1 PI)
8490 08:06:35.119311 u2DelayCellOfst[12]=13 cells (4 PI)
8491 08:06:35.122373 u2DelayCellOfst[13]=16 cells (5 PI)
8492 08:06:35.125588 u2DelayCellOfst[14]=16 cells (5 PI)
8493 08:06:35.129145 u2DelayCellOfst[15]=16 cells (5 PI)
8494 08:06:35.132294 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8495 08:06:35.139083 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8496 08:06:35.139640 DramC Write-DBI on
8497 08:06:35.140007 ==
8498 08:06:35.142074 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 08:06:35.145657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 08:06:35.146258 ==
8501 08:06:35.149042
8502 08:06:35.149492
8503 08:06:35.149846 TX Vref Scan disable
8504 08:06:35.152414 == TX Byte 0 ==
8505 08:06:35.155349 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8506 08:06:35.158693 == TX Byte 1 ==
8507 08:06:35.162301 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8508 08:06:35.162868 DramC Write-DBI off
8509 08:06:35.165439
8510 08:06:35.165993 [DATLAT]
8511 08:06:35.166358 Freq=1600, CH1 RK0
8512 08:06:35.166695
8513 08:06:35.168568 DATLAT Default: 0xf
8514 08:06:35.169050 0, 0xFFFF, sum = 0
8515 08:06:35.171981 1, 0xFFFF, sum = 0
8516 08:06:35.172445 2, 0xFFFF, sum = 0
8517 08:06:35.175460 3, 0xFFFF, sum = 0
8518 08:06:35.176023 4, 0xFFFF, sum = 0
8519 08:06:35.178937 5, 0xFFFF, sum = 0
8520 08:06:35.182618 6, 0xFFFF, sum = 0
8521 08:06:35.183178 7, 0xFFFF, sum = 0
8522 08:06:35.185502 8, 0xFFFF, sum = 0
8523 08:06:35.186068 9, 0xFFFF, sum = 0
8524 08:06:35.189029 10, 0xFFFF, sum = 0
8525 08:06:35.189584 11, 0xFFFF, sum = 0
8526 08:06:35.192005 12, 0xFFFF, sum = 0
8527 08:06:35.192473 13, 0xFFFF, sum = 0
8528 08:06:35.195642 14, 0x0, sum = 1
8529 08:06:35.196205 15, 0x0, sum = 2
8530 08:06:35.198695 16, 0x0, sum = 3
8531 08:06:35.199159 17, 0x0, sum = 4
8532 08:06:35.201963 best_step = 15
8533 08:06:35.202418
8534 08:06:35.202772 ==
8535 08:06:35.205791 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 08:06:35.208754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 08:06:35.209346 ==
8538 08:06:35.209715 RX Vref Scan: 1
8539 08:06:35.212347
8540 08:06:35.212902 Set Vref Range= 24 -> 127
8541 08:06:35.213324
8542 08:06:35.215667 RX Vref 24 -> 127, step: 1
8543 08:06:35.216224
8544 08:06:35.218775 RX Delay 19 -> 252, step: 4
8545 08:06:35.219329
8546 08:06:35.222265 Set Vref, RX VrefLevel [Byte0]: 24
8547 08:06:35.225176 [Byte1]: 24
8548 08:06:35.225731
8549 08:06:35.228400 Set Vref, RX VrefLevel [Byte0]: 25
8550 08:06:35.232080 [Byte1]: 25
8551 08:06:35.232641
8552 08:06:35.235312 Set Vref, RX VrefLevel [Byte0]: 26
8553 08:06:35.238523 [Byte1]: 26
8554 08:06:35.242370
8555 08:06:35.242987 Set Vref, RX VrefLevel [Byte0]: 27
8556 08:06:35.245537 [Byte1]: 27
8557 08:06:35.249888
8558 08:06:35.250442 Set Vref, RX VrefLevel [Byte0]: 28
8559 08:06:35.253370 [Byte1]: 28
8560 08:06:35.257635
8561 08:06:35.258187 Set Vref, RX VrefLevel [Byte0]: 29
8562 08:06:35.260899 [Byte1]: 29
8563 08:06:35.264809
8564 08:06:35.265311 Set Vref, RX VrefLevel [Byte0]: 30
8565 08:06:35.268730 [Byte1]: 30
8566 08:06:35.272593
8567 08:06:35.273185 Set Vref, RX VrefLevel [Byte0]: 31
8568 08:06:35.275877 [Byte1]: 31
8569 08:06:35.280155
8570 08:06:35.280705 Set Vref, RX VrefLevel [Byte0]: 32
8571 08:06:35.283613 [Byte1]: 32
8572 08:06:35.287653
8573 08:06:35.288213 Set Vref, RX VrefLevel [Byte0]: 33
8574 08:06:35.290911 [Byte1]: 33
8575 08:06:35.295272
8576 08:06:35.295740 Set Vref, RX VrefLevel [Byte0]: 34
8577 08:06:35.298894 [Byte1]: 34
8578 08:06:35.302805
8579 08:06:35.303260 Set Vref, RX VrefLevel [Byte0]: 35
8580 08:06:35.306216 [Byte1]: 35
8581 08:06:35.310496
8582 08:06:35.311050 Set Vref, RX VrefLevel [Byte0]: 36
8583 08:06:35.313802 [Byte1]: 36
8584 08:06:35.318301
8585 08:06:35.318852 Set Vref, RX VrefLevel [Byte0]: 37
8586 08:06:35.321166 [Byte1]: 37
8587 08:06:35.325742
8588 08:06:35.326297 Set Vref, RX VrefLevel [Byte0]: 38
8589 08:06:35.328832 [Byte1]: 38
8590 08:06:35.333333
8591 08:06:35.333887 Set Vref, RX VrefLevel [Byte0]: 39
8592 08:06:35.336709 [Byte1]: 39
8593 08:06:35.341161
8594 08:06:35.341714 Set Vref, RX VrefLevel [Byte0]: 40
8595 08:06:35.343778 [Byte1]: 40
8596 08:06:35.348284
8597 08:06:35.348837 Set Vref, RX VrefLevel [Byte0]: 41
8598 08:06:35.351766 [Byte1]: 41
8599 08:06:35.356207
8600 08:06:35.356760 Set Vref, RX VrefLevel [Byte0]: 42
8601 08:06:35.359151 [Byte1]: 42
8602 08:06:35.363628
8603 08:06:35.364253 Set Vref, RX VrefLevel [Byte0]: 43
8604 08:06:35.366402 [Byte1]: 43
8605 08:06:35.370736
8606 08:06:35.371292 Set Vref, RX VrefLevel [Byte0]: 44
8607 08:06:35.374512 [Byte1]: 44
8608 08:06:35.378620
8609 08:06:35.381705 Set Vref, RX VrefLevel [Byte0]: 45
8610 08:06:35.385090 [Byte1]: 45
8611 08:06:35.385548
8612 08:06:35.388235 Set Vref, RX VrefLevel [Byte0]: 46
8613 08:06:35.391690 [Byte1]: 46
8614 08:06:35.392410
8615 08:06:35.394812 Set Vref, RX VrefLevel [Byte0]: 47
8616 08:06:35.398466 [Byte1]: 47
8617 08:06:35.399027
8618 08:06:35.401499 Set Vref, RX VrefLevel [Byte0]: 48
8619 08:06:35.405287 [Byte1]: 48
8620 08:06:35.408761
8621 08:06:35.409445 Set Vref, RX VrefLevel [Byte0]: 49
8622 08:06:35.412207 [Byte1]: 49
8623 08:06:35.416851
8624 08:06:35.417449 Set Vref, RX VrefLevel [Byte0]: 50
8625 08:06:35.419798 [Byte1]: 50
8626 08:06:35.424503
8627 08:06:35.425104 Set Vref, RX VrefLevel [Byte0]: 51
8628 08:06:35.427533 [Byte1]: 51
8629 08:06:35.431659
8630 08:06:35.432245 Set Vref, RX VrefLevel [Byte0]: 52
8631 08:06:35.435336 [Byte1]: 52
8632 08:06:35.439130
8633 08:06:35.439607 Set Vref, RX VrefLevel [Byte0]: 53
8634 08:06:35.442202 [Byte1]: 53
8635 08:06:35.447007
8636 08:06:35.447560 Set Vref, RX VrefLevel [Byte0]: 54
8637 08:06:35.450291 [Byte1]: 54
8638 08:06:35.454378
8639 08:06:35.454933 Set Vref, RX VrefLevel [Byte0]: 55
8640 08:06:35.457837 [Byte1]: 55
8641 08:06:35.461829
8642 08:06:35.462393 Set Vref, RX VrefLevel [Byte0]: 56
8643 08:06:35.465632 [Byte1]: 56
8644 08:06:35.469344
8645 08:06:35.469799 Set Vref, RX VrefLevel [Byte0]: 57
8646 08:06:35.472874 [Byte1]: 57
8647 08:06:35.477141
8648 08:06:35.477697 Set Vref, RX VrefLevel [Byte0]: 58
8649 08:06:35.480432 [Byte1]: 58
8650 08:06:35.484625
8651 08:06:35.485223 Set Vref, RX VrefLevel [Byte0]: 59
8652 08:06:35.488094 [Byte1]: 59
8653 08:06:35.492470
8654 08:06:35.493159 Set Vref, RX VrefLevel [Byte0]: 60
8655 08:06:35.495309 [Byte1]: 60
8656 08:06:35.499456
8657 08:06:35.499908 Set Vref, RX VrefLevel [Byte0]: 61
8658 08:06:35.503042 [Byte1]: 61
8659 08:06:35.507350
8660 08:06:35.507905 Set Vref, RX VrefLevel [Byte0]: 62
8661 08:06:35.514079 [Byte1]: 62
8662 08:06:35.514679
8663 08:06:35.516916 Set Vref, RX VrefLevel [Byte0]: 63
8664 08:06:35.520456 [Byte1]: 63
8665 08:06:35.521061
8666 08:06:35.523885 Set Vref, RX VrefLevel [Byte0]: 64
8667 08:06:35.527467 [Byte1]: 64
8668 08:06:35.528027
8669 08:06:35.530728 Set Vref, RX VrefLevel [Byte0]: 65
8670 08:06:35.533649 [Byte1]: 65
8671 08:06:35.537865
8672 08:06:35.538417 Set Vref, RX VrefLevel [Byte0]: 66
8673 08:06:35.541167 [Byte1]: 66
8674 08:06:35.545245
8675 08:06:35.545697 Set Vref, RX VrefLevel [Byte0]: 67
8676 08:06:35.548927 [Byte1]: 67
8677 08:06:35.552812
8678 08:06:35.553400 Set Vref, RX VrefLevel [Byte0]: 68
8679 08:06:35.556422 [Byte1]: 68
8680 08:06:35.560620
8681 08:06:35.561226 Set Vref, RX VrefLevel [Byte0]: 69
8682 08:06:35.563970 [Byte1]: 69
8683 08:06:35.568293
8684 08:06:35.568847 Set Vref, RX VrefLevel [Byte0]: 70
8685 08:06:35.571785 [Byte1]: 70
8686 08:06:35.575793
8687 08:06:35.576346 Set Vref, RX VrefLevel [Byte0]: 71
8688 08:06:35.578739 [Byte1]: 71
8689 08:06:35.583278
8690 08:06:35.583915 Set Vref, RX VrefLevel [Byte0]: 72
8691 08:06:35.586848 [Byte1]: 72
8692 08:06:35.590563
8693 08:06:35.591114 Set Vref, RX VrefLevel [Byte0]: 73
8694 08:06:35.593730 [Byte1]: 73
8695 08:06:35.598181
8696 08:06:35.598742 Set Vref, RX VrefLevel [Byte0]: 74
8697 08:06:35.601313 [Byte1]: 74
8698 08:06:35.605568
8699 08:06:35.606042 Final RX Vref Byte 0 = 59 to rank0
8700 08:06:35.608905 Final RX Vref Byte 1 = 61 to rank0
8701 08:06:35.612193 Final RX Vref Byte 0 = 59 to rank1
8702 08:06:35.616043 Final RX Vref Byte 1 = 61 to rank1==
8703 08:06:35.619339 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 08:06:35.625878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 08:06:35.626441 ==
8706 08:06:35.626805 DQS Delay:
8707 08:06:35.627137 DQS0 = 0, DQS1 = 0
8708 08:06:35.629180 DQM Delay:
8709 08:06:35.629730 DQM0 = 134, DQM1 = 129
8710 08:06:35.632433 DQ Delay:
8711 08:06:35.635925 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8712 08:06:35.639185 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8713 08:06:35.642612 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8714 08:06:35.645871 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8715 08:06:35.646425
8716 08:06:35.646782
8717 08:06:35.647112
8718 08:06:35.649147 [DramC_TX_OE_Calibration] TA2
8719 08:06:35.652621 Original DQ_B0 (3 6) =30, OEN = 27
8720 08:06:35.655953 Original DQ_B1 (3 6) =30, OEN = 27
8721 08:06:35.659437 24, 0x0, End_B0=24 End_B1=24
8722 08:06:35.659998 25, 0x0, End_B0=25 End_B1=25
8723 08:06:35.662546 26, 0x0, End_B0=26 End_B1=26
8724 08:06:35.665854 27, 0x0, End_B0=27 End_B1=27
8725 08:06:35.669300 28, 0x0, End_B0=28 End_B1=28
8726 08:06:35.670006 29, 0x0, End_B0=29 End_B1=29
8727 08:06:35.672614 30, 0x0, End_B0=30 End_B1=30
8728 08:06:35.675658 31, 0x4545, End_B0=30 End_B1=30
8729 08:06:35.679037 Byte0 end_step=30 best_step=27
8730 08:06:35.682353 Byte1 end_step=30 best_step=27
8731 08:06:35.685667 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 08:06:35.686225 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 08:06:35.689117
8734 08:06:35.689663
8735 08:06:35.695965 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8736 08:06:35.698699 CH1 RK0: MR19=303, MR18=1825
8737 08:06:35.705301 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8738 08:06:35.705763
8739 08:06:35.708751 ----->DramcWriteLeveling(PI) begin...
8740 08:06:35.709256 ==
8741 08:06:35.711884 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 08:06:35.715460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 08:06:35.716024 ==
8744 08:06:35.718525 Write leveling (Byte 0): 25 => 25
8745 08:06:35.721936 Write leveling (Byte 1): 29 => 29
8746 08:06:35.725638 DramcWriteLeveling(PI) end<-----
8747 08:06:35.726195
8748 08:06:35.726587 ==
8749 08:06:35.728986 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 08:06:35.732240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 08:06:35.732701 ==
8752 08:06:35.735664 [Gating] SW mode calibration
8753 08:06:35.742274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 08:06:35.749082 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 08:06:35.752508 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 08:06:35.755614 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 08:06:35.762496 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8758 08:06:35.765380 1 4 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
8759 08:06:35.768484 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 08:06:35.775891 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 08:06:35.778676 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 08:06:35.782273 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 08:06:35.788686 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 08:06:35.792194 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 08:06:35.795204 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8766 08:06:35.801530 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8767 08:06:35.804846 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 08:06:35.808407 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 08:06:35.815188 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 08:06:35.818386 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 08:06:35.821374 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 08:06:35.828470 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8773 08:06:35.831721 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8774 08:06:35.835331 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
8775 08:06:35.841826 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 08:06:35.845192 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 08:06:35.848327 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 08:06:35.855153 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 08:06:35.858280 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 08:06:35.861433 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 08:06:35.865087 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 08:06:35.871476 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 08:06:35.875029 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 08:06:35.878346 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 08:06:35.884833 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 08:06:35.888431 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 08:06:35.891380 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 08:06:35.898136 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 08:06:35.901247 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 08:06:35.904791 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 08:06:35.911315 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 08:06:35.914803 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 08:06:35.918090 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 08:06:35.925218 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 08:06:35.928054 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 08:06:35.931612 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 08:06:35.938160 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8798 08:06:35.941769 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8799 08:06:35.944613 Total UI for P1: 0, mck2ui 16
8800 08:06:35.948263 best dqsien dly found for B1: ( 1, 9, 8)
8801 08:06:35.951793 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 08:06:35.954821 Total UI for P1: 0, mck2ui 16
8803 08:06:35.957915 best dqsien dly found for B0: ( 1, 9, 10)
8804 08:06:35.961472 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8805 08:06:35.964698 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8806 08:06:35.965291
8807 08:06:35.967973 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8808 08:06:35.974617 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8809 08:06:35.975187 [Gating] SW calibration Done
8810 08:06:35.978006 ==
8811 08:06:35.978566 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 08:06:35.984839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 08:06:35.985437 ==
8814 08:06:35.985807 RX Vref Scan: 0
8815 08:06:35.986150
8816 08:06:35.987675 RX Vref 0 -> 0, step: 1
8817 08:06:35.988253
8818 08:06:35.991272 RX Delay 0 -> 252, step: 8
8819 08:06:35.994384 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8820 08:06:35.997537 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8821 08:06:36.001534 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8822 08:06:36.007707 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8823 08:06:36.011270 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8824 08:06:36.014721 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8825 08:06:36.017493 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8826 08:06:36.021070 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8827 08:06:36.024696 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8828 08:06:36.030882 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8829 08:06:36.034531 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8830 08:06:36.037416 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8831 08:06:36.040647 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8832 08:06:36.047372 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8833 08:06:36.050766 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8834 08:06:36.054540 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8835 08:06:36.055251 ==
8836 08:06:36.057394 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 08:06:36.060909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 08:06:36.061504 ==
8839 08:06:36.064540 DQS Delay:
8840 08:06:36.065150 DQS0 = 0, DQS1 = 0
8841 08:06:36.067472 DQM Delay:
8842 08:06:36.068040 DQM0 = 137, DQM1 = 132
8843 08:06:36.068413 DQ Delay:
8844 08:06:36.074036 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8845 08:06:36.077539 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8846 08:06:36.080707 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8847 08:06:36.084299 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8848 08:06:36.084854
8849 08:06:36.085256
8850 08:06:36.085593 ==
8851 08:06:36.087543 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 08:06:36.091280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 08:06:36.091842 ==
8854 08:06:36.092204
8855 08:06:36.092534
8856 08:06:36.093696 TX Vref Scan disable
8857 08:06:36.097145 == TX Byte 0 ==
8858 08:06:36.100306 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8859 08:06:36.104093 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8860 08:06:36.107544 == TX Byte 1 ==
8861 08:06:36.110266 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8862 08:06:36.114020 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8863 08:06:36.114578 ==
8864 08:06:36.116901 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 08:06:36.123644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 08:06:36.124201 ==
8867 08:06:36.136344
8868 08:06:36.139806 TX Vref early break, caculate TX vref
8869 08:06:36.142709 TX Vref=16, minBit 9, minWin=21, winSum=374
8870 08:06:36.145725 TX Vref=18, minBit 9, minWin=22, winSum=386
8871 08:06:36.149503 TX Vref=20, minBit 8, minWin=23, winSum=398
8872 08:06:36.152612 TX Vref=22, minBit 9, minWin=23, winSum=408
8873 08:06:36.156080 TX Vref=24, minBit 9, minWin=24, winSum=408
8874 08:06:36.162746 TX Vref=26, minBit 11, minWin=24, winSum=417
8875 08:06:36.165914 TX Vref=28, minBit 8, minWin=24, winSum=416
8876 08:06:36.169228 TX Vref=30, minBit 10, minWin=24, winSum=411
8877 08:06:36.172659 TX Vref=32, minBit 8, minWin=24, winSum=403
8878 08:06:36.175795 TX Vref=34, minBit 9, minWin=23, winSum=397
8879 08:06:36.179768 TX Vref=36, minBit 8, minWin=23, winSum=388
8880 08:06:36.185819 [TxChooseVref] Worse bit 11, Min win 24, Win sum 417, Final Vref 26
8881 08:06:36.186385
8882 08:06:36.189359 Final TX Range 0 Vref 26
8883 08:06:36.189926
8884 08:06:36.190291 ==
8885 08:06:36.192658 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 08:06:36.195942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 08:06:36.196525 ==
8888 08:06:36.198913
8889 08:06:36.199376
8890 08:06:36.200016 TX Vref Scan disable
8891 08:06:36.205719 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8892 08:06:36.206280 == TX Byte 0 ==
8893 08:06:36.209529 u2DelayCellOfst[0]=16 cells (5 PI)
8894 08:06:36.212489 u2DelayCellOfst[1]=10 cells (3 PI)
8895 08:06:36.215611 u2DelayCellOfst[2]=0 cells (0 PI)
8896 08:06:36.219353 u2DelayCellOfst[3]=6 cells (2 PI)
8897 08:06:36.222694 u2DelayCellOfst[4]=10 cells (3 PI)
8898 08:06:36.226153 u2DelayCellOfst[5]=16 cells (5 PI)
8899 08:06:36.229577 u2DelayCellOfst[6]=16 cells (5 PI)
8900 08:06:36.232533 u2DelayCellOfst[7]=6 cells (2 PI)
8901 08:06:36.235909 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8902 08:06:36.239335 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8903 08:06:36.242582 == TX Byte 1 ==
8904 08:06:36.246668 u2DelayCellOfst[8]=0 cells (0 PI)
8905 08:06:36.249105 u2DelayCellOfst[9]=3 cells (1 PI)
8906 08:06:36.249671 u2DelayCellOfst[10]=10 cells (3 PI)
8907 08:06:36.252301 u2DelayCellOfst[11]=3 cells (1 PI)
8908 08:06:36.256287 u2DelayCellOfst[12]=13 cells (4 PI)
8909 08:06:36.259182 u2DelayCellOfst[13]=16 cells (5 PI)
8910 08:06:36.262581 u2DelayCellOfst[14]=16 cells (5 PI)
8911 08:06:36.265483 u2DelayCellOfst[15]=16 cells (5 PI)
8912 08:06:36.272402 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8913 08:06:36.275812 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8914 08:06:36.276378 DramC Write-DBI on
8915 08:06:36.276746 ==
8916 08:06:36.279138 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 08:06:36.285843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 08:06:36.286410 ==
8919 08:06:36.286783
8920 08:06:36.287123
8921 08:06:36.287449 TX Vref Scan disable
8922 08:06:36.289582 == TX Byte 0 ==
8923 08:06:36.293458 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8924 08:06:36.296568 == TX Byte 1 ==
8925 08:06:36.299471 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8926 08:06:36.303052 DramC Write-DBI off
8927 08:06:36.303619
8928 08:06:36.303989 [DATLAT]
8929 08:06:36.304330 Freq=1600, CH1 RK1
8930 08:06:36.304664
8931 08:06:36.306092 DATLAT Default: 0xf
8932 08:06:36.306552 0, 0xFFFF, sum = 0
8933 08:06:36.309627 1, 0xFFFF, sum = 0
8934 08:06:36.312902 2, 0xFFFF, sum = 0
8935 08:06:36.313507 3, 0xFFFF, sum = 0
8936 08:06:36.316437 4, 0xFFFF, sum = 0
8937 08:06:36.317056 5, 0xFFFF, sum = 0
8938 08:06:36.319694 6, 0xFFFF, sum = 0
8939 08:06:36.320264 7, 0xFFFF, sum = 0
8940 08:06:36.322884 8, 0xFFFF, sum = 0
8941 08:06:36.323462 9, 0xFFFF, sum = 0
8942 08:06:36.326384 10, 0xFFFF, sum = 0
8943 08:06:36.326962 11, 0xFFFF, sum = 0
8944 08:06:36.329601 12, 0xFFFF, sum = 0
8945 08:06:36.330177 13, 0xFFFF, sum = 0
8946 08:06:36.332852 14, 0x0, sum = 1
8947 08:06:36.333476 15, 0x0, sum = 2
8948 08:06:36.336331 16, 0x0, sum = 3
8949 08:06:36.336915 17, 0x0, sum = 4
8950 08:06:36.339297 best_step = 15
8951 08:06:36.339757
8952 08:06:36.340117 ==
8953 08:06:36.342678 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 08:06:36.346134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 08:06:36.346705 ==
8956 08:06:36.349438 RX Vref Scan: 0
8957 08:06:36.350000
8958 08:06:36.350370 RX Vref 0 -> 0, step: 1
8959 08:06:36.350713
8960 08:06:36.352734 RX Delay 19 -> 252, step: 4
8961 08:06:36.355964 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8962 08:06:36.362646 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8963 08:06:36.365820 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8964 08:06:36.369135 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8965 08:06:36.372921 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8966 08:06:36.375795 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8967 08:06:36.379589 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8968 08:06:36.386163 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8969 08:06:36.389492 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8970 08:06:36.392690 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8971 08:06:36.396094 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8972 08:06:36.399754 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8973 08:06:36.405969 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8974 08:06:36.409221 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8975 08:06:36.412744 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8976 08:06:36.416382 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8977 08:06:36.416848 ==
8978 08:06:36.419179 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 08:06:36.425709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 08:06:36.426180 ==
8981 08:06:36.426547 DQS Delay:
8982 08:06:36.429263 DQS0 = 0, DQS1 = 0
8983 08:06:36.429730 DQM Delay:
8984 08:06:36.430093 DQM0 = 133, DQM1 = 130
8985 08:06:36.432598 DQ Delay:
8986 08:06:36.435917 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8987 08:06:36.439218 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8988 08:06:36.442377 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
8989 08:06:36.445719 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8990 08:06:36.446183
8991 08:06:36.446544
8992 08:06:36.446880
8993 08:06:36.448986 [DramC_TX_OE_Calibration] TA2
8994 08:06:36.452474 Original DQ_B0 (3 6) =30, OEN = 27
8995 08:06:36.455842 Original DQ_B1 (3 6) =30, OEN = 27
8996 08:06:36.458923 24, 0x0, End_B0=24 End_B1=24
8997 08:06:36.459391 25, 0x0, End_B0=25 End_B1=25
8998 08:06:36.462323 26, 0x0, End_B0=26 End_B1=26
8999 08:06:36.465779 27, 0x0, End_B0=27 End_B1=27
9000 08:06:36.468772 28, 0x0, End_B0=28 End_B1=28
9001 08:06:36.471927 29, 0x0, End_B0=29 End_B1=29
9002 08:06:36.472394 30, 0x0, End_B0=30 End_B1=30
9003 08:06:36.475546 31, 0x4141, End_B0=30 End_B1=30
9004 08:06:36.478904 Byte0 end_step=30 best_step=27
9005 08:06:36.482094 Byte1 end_step=30 best_step=27
9006 08:06:36.485344 Byte0 TX OE(2T, 0.5T) = (3, 3)
9007 08:06:36.488828 Byte1 TX OE(2T, 0.5T) = (3, 3)
9008 08:06:36.489435
9009 08:06:36.489806
9010 08:06:36.495472 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9011 08:06:36.499051 CH1 RK1: MR19=303, MR18=1E09
9012 08:06:36.505428 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9013 08:06:36.508571 [RxdqsGatingPostProcess] freq 1600
9014 08:06:36.512276 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9015 08:06:36.515577 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 08:06:36.518687 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 08:06:36.522006 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 08:06:36.525453 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 08:06:36.528683 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 08:06:36.531928 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 08:06:36.535379 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 08:06:36.538915 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 08:06:36.542096 Pre-setting of DQS Precalculation
9024 08:06:36.545230 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9025 08:06:36.552081 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9026 08:06:36.562271 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9027 08:06:36.562829
9028 08:06:36.563196
9029 08:06:36.563533 [Calibration Summary] 3200 Mbps
9030 08:06:36.565191 CH 0, Rank 0
9031 08:06:36.565649 SW Impedance : PASS
9032 08:06:36.568805 DUTY Scan : NO K
9033 08:06:36.572011 ZQ Calibration : PASS
9034 08:06:36.572470 Jitter Meter : NO K
9035 08:06:36.575140 CBT Training : PASS
9036 08:06:36.578829 Write leveling : PASS
9037 08:06:36.579381 RX DQS gating : PASS
9038 08:06:36.581757 RX DQ/DQS(RDDQC) : PASS
9039 08:06:36.585131 TX DQ/DQS : PASS
9040 08:06:36.585689 RX DATLAT : PASS
9041 08:06:36.588592 RX DQ/DQS(Engine): PASS
9042 08:06:36.591996 TX OE : PASS
9043 08:06:36.592568 All Pass.
9044 08:06:36.592965
9045 08:06:36.593306 CH 0, Rank 1
9046 08:06:36.595448 SW Impedance : PASS
9047 08:06:36.598784 DUTY Scan : NO K
9048 08:06:36.599340 ZQ Calibration : PASS
9049 08:06:36.602108 Jitter Meter : NO K
9050 08:06:36.605278 CBT Training : PASS
9051 08:06:36.605741 Write leveling : PASS
9052 08:06:36.608403 RX DQS gating : PASS
9053 08:06:36.608857 RX DQ/DQS(RDDQC) : PASS
9054 08:06:36.611678 TX DQ/DQS : PASS
9055 08:06:36.615466 RX DATLAT : PASS
9056 08:06:36.616020 RX DQ/DQS(Engine): PASS
9057 08:06:36.618671 TX OE : PASS
9058 08:06:36.619228 All Pass.
9059 08:06:36.619593
9060 08:06:36.621637 CH 1, Rank 0
9061 08:06:36.622093 SW Impedance : PASS
9062 08:06:36.625123 DUTY Scan : NO K
9063 08:06:36.628491 ZQ Calibration : PASS
9064 08:06:36.628997 Jitter Meter : NO K
9065 08:06:36.632064 CBT Training : PASS
9066 08:06:36.635398 Write leveling : PASS
9067 08:06:36.635953 RX DQS gating : PASS
9068 08:06:36.639064 RX DQ/DQS(RDDQC) : PASS
9069 08:06:36.641991 TX DQ/DQS : PASS
9070 08:06:36.642553 RX DATLAT : PASS
9071 08:06:36.645054 RX DQ/DQS(Engine): PASS
9072 08:06:36.648371 TX OE : PASS
9073 08:06:36.648847 All Pass.
9074 08:06:36.649247
9075 08:06:36.649580 CH 1, Rank 1
9076 08:06:36.651709 SW Impedance : PASS
9077 08:06:36.652162 DUTY Scan : NO K
9078 08:06:36.655341 ZQ Calibration : PASS
9079 08:06:36.658762 Jitter Meter : NO K
9080 08:06:36.659319 CBT Training : PASS
9081 08:06:36.662313 Write leveling : PASS
9082 08:06:36.665375 RX DQS gating : PASS
9083 08:06:36.665937 RX DQ/DQS(RDDQC) : PASS
9084 08:06:36.668601 TX DQ/DQS : PASS
9085 08:06:36.671659 RX DATLAT : PASS
9086 08:06:36.672246 RX DQ/DQS(Engine): PASS
9087 08:06:36.675465 TX OE : PASS
9088 08:06:36.676028 All Pass.
9089 08:06:36.676388
9090 08:06:36.678294 DramC Write-DBI on
9091 08:06:36.682198 PER_BANK_REFRESH: Hybrid Mode
9092 08:06:36.682807 TX_TRACKING: ON
9093 08:06:36.691838 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9094 08:06:36.698421 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9095 08:06:36.705122 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 08:06:36.708816 [FAST_K] Save calibration result to emmc
9097 08:06:36.711834 sync common calibartion params.
9098 08:06:36.715688 sync cbt_mode0:1, 1:1
9099 08:06:36.718677 dram_init: ddr_geometry: 2
9100 08:06:36.719233 dram_init: ddr_geometry: 2
9101 08:06:36.722289 dram_init: ddr_geometry: 2
9102 08:06:36.725175 0:dram_rank_size:100000000
9103 08:06:36.725641 1:dram_rank_size:100000000
9104 08:06:36.732195 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9105 08:06:36.735429 DFS_SHUFFLE_HW_MODE: ON
9106 08:06:36.739066 dramc_set_vcore_voltage set vcore to 725000
9107 08:06:36.741960 Read voltage for 1600, 0
9108 08:06:36.742518 Vio18 = 0
9109 08:06:36.742881 Vcore = 725000
9110 08:06:36.745280 Vdram = 0
9111 08:06:36.745753 Vddq = 0
9112 08:06:36.746169 Vmddr = 0
9113 08:06:36.748802 switch to 3200 Mbps bootup
9114 08:06:36.749389 [DramcRunTimeConfig]
9115 08:06:36.751736 PHYPLL
9116 08:06:36.752192 DPM_CONTROL_AFTERK: ON
9117 08:06:36.755582 PER_BANK_REFRESH: ON
9118 08:06:36.758365 REFRESH_OVERHEAD_REDUCTION: ON
9119 08:06:36.758823 CMD_PICG_NEW_MODE: OFF
9120 08:06:36.762222 XRTWTW_NEW_MODE: ON
9121 08:06:36.762779 XRTRTR_NEW_MODE: ON
9122 08:06:36.765133 TX_TRACKING: ON
9123 08:06:36.765595 RDSEL_TRACKING: OFF
9124 08:06:36.768871 DQS Precalculation for DVFS: ON
9125 08:06:36.771753 RX_TRACKING: OFF
9126 08:06:36.772216 HW_GATING DBG: ON
9127 08:06:36.775632 ZQCS_ENABLE_LP4: ON
9128 08:06:36.776197 RX_PICG_NEW_MODE: ON
9129 08:06:36.778657 TX_PICG_NEW_MODE: ON
9130 08:06:36.779215 ENABLE_RX_DCM_DPHY: ON
9131 08:06:36.781827 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9132 08:06:36.785378 DUMMY_READ_FOR_TRACKING: OFF
9133 08:06:36.788397 !!! SPM_CONTROL_AFTERK: OFF
9134 08:06:36.792070 !!! SPM could not control APHY
9135 08:06:36.792630 IMPEDANCE_TRACKING: ON
9136 08:06:36.794976 TEMP_SENSOR: ON
9137 08:06:36.795522 HW_SAVE_FOR_SR: OFF
9138 08:06:36.798502 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9139 08:06:36.801788 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9140 08:06:36.804865 Read ODT Tracking: ON
9141 08:06:36.808320 Refresh Rate DeBounce: ON
9142 08:06:36.808779 DFS_NO_QUEUE_FLUSH: ON
9143 08:06:36.811931 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9144 08:06:36.815278 ENABLE_DFS_RUNTIME_MRW: OFF
9145 08:06:36.818801 DDR_RESERVE_NEW_MODE: ON
9146 08:06:36.819365 MR_CBT_SWITCH_FREQ: ON
9147 08:06:36.821421 =========================
9148 08:06:36.841065 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9149 08:06:36.844136 dram_init: ddr_geometry: 2
9150 08:06:36.862250 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9151 08:06:36.865845 dram_init: dram init end (result: 0)
9152 08:06:36.872134 DRAM-K: Full calibration passed in 24510 msecs
9153 08:06:36.875933 MRC: failed to locate region type 0.
9154 08:06:36.876497 DRAM rank0 size:0x100000000,
9155 08:06:36.879048 DRAM rank1 size=0x100000000
9156 08:06:36.888807 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9157 08:06:36.895339 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9158 08:06:36.902291 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9159 08:06:36.908673 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9160 08:06:36.911937 DRAM rank0 size:0x100000000,
9161 08:06:36.915075 DRAM rank1 size=0x100000000
9162 08:06:36.915538 CBMEM:
9163 08:06:36.919073 IMD: root @ 0xfffff000 254 entries.
9164 08:06:36.921662 IMD: root @ 0xffffec00 62 entries.
9165 08:06:36.925252 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9166 08:06:36.928601 WARNING: RO_VPD is uninitialized or empty.
9167 08:06:36.935251 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9168 08:06:36.942107 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9169 08:06:36.955038 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9170 08:06:36.966660 BS: romstage times (exec / console): total (unknown) / 24007 ms
9171 08:06:36.967238
9172 08:06:36.967608
9173 08:06:36.976421 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9174 08:06:36.979893 ARM64: Exception handlers installed.
9175 08:06:36.983330 ARM64: Testing exception
9176 08:06:36.986396 ARM64: Done test exception
9177 08:06:36.986957 Enumerating buses...
9178 08:06:36.989846 Show all devs... Before device enumeration.
9179 08:06:36.993242 Root Device: enabled 1
9180 08:06:36.995990 CPU_CLUSTER: 0: enabled 1
9181 08:06:36.996459 CPU: 00: enabled 1
9182 08:06:36.999348 Compare with tree...
9183 08:06:36.999811 Root Device: enabled 1
9184 08:06:37.002876 CPU_CLUSTER: 0: enabled 1
9185 08:06:37.005961 CPU: 00: enabled 1
9186 08:06:37.006426 Root Device scanning...
9187 08:06:37.009716 scan_static_bus for Root Device
9188 08:06:37.012839 CPU_CLUSTER: 0 enabled
9189 08:06:37.016272 scan_static_bus for Root Device done
9190 08:06:37.020021 scan_bus: bus Root Device finished in 8 msecs
9191 08:06:37.020590 done
9192 08:06:37.026346 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9193 08:06:37.029438 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9194 08:06:37.036301 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9195 08:06:37.039917 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9196 08:06:37.043068 Allocating resources...
9197 08:06:37.043623 Reading resources...
9198 08:06:37.049550 Root Device read_resources bus 0 link: 0
9199 08:06:37.050108 DRAM rank0 size:0x100000000,
9200 08:06:37.053153 DRAM rank1 size=0x100000000
9201 08:06:37.056313 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9202 08:06:37.059795 CPU: 00 missing read_resources
9203 08:06:37.063150 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9204 08:06:37.069713 Root Device read_resources bus 0 link: 0 done
9205 08:06:37.070272 Done reading resources.
9206 08:06:37.076431 Show resources in subtree (Root Device)...After reading.
9207 08:06:37.079709 Root Device child on link 0 CPU_CLUSTER: 0
9208 08:06:37.083081 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 08:06:37.092921 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 08:06:37.093515 CPU: 00
9211 08:06:37.096024 Root Device assign_resources, bus 0 link: 0
9212 08:06:37.099935 CPU_CLUSTER: 0 missing set_resources
9213 08:06:37.102825 Root Device assign_resources, bus 0 link: 0 done
9214 08:06:37.106202 Done setting resources.
9215 08:06:37.112664 Show resources in subtree (Root Device)...After assigning values.
9216 08:06:37.116252 Root Device child on link 0 CPU_CLUSTER: 0
9217 08:06:37.119609 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 08:06:37.129381 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 08:06:37.129929 CPU: 00
9220 08:06:37.133144 Done allocating resources.
9221 08:06:37.136026 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9222 08:06:37.139496 Enabling resources...
9223 08:06:37.140058 done.
9224 08:06:37.142898 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9225 08:06:37.145802 Initializing devices...
9226 08:06:37.149098 Root Device init
9227 08:06:37.149556 init hardware done!
9228 08:06:37.152858 0x00000018: ctrlr->caps
9229 08:06:37.156165 52.000 MHz: ctrlr->f_max
9230 08:06:37.156729 0.400 MHz: ctrlr->f_min
9231 08:06:37.159019 0x40ff8080: ctrlr->voltages
9232 08:06:37.159488 sclk: 390625
9233 08:06:37.162723 Bus Width = 1
9234 08:06:37.163304 sclk: 390625
9235 08:06:37.163670 Bus Width = 1
9236 08:06:37.166467 Early init status = 3
9237 08:06:37.172452 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9238 08:06:37.176014 in-header: 03 fc 00 00 01 00 00 00
9239 08:06:37.176586 in-data: 00
9240 08:06:37.182815 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9241 08:06:37.185807 in-header: 03 fd 00 00 00 00 00 00
9242 08:06:37.189267 in-data:
9243 08:06:37.192556 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9244 08:06:37.195807 in-header: 03 fc 00 00 01 00 00 00
9245 08:06:37.199343 in-data: 00
9246 08:06:37.202731 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9247 08:06:37.208122 in-header: 03 fd 00 00 00 00 00 00
9248 08:06:37.211405 in-data:
9249 08:06:37.214585 [SSUSB] Setting up USB HOST controller...
9250 08:06:37.218325 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9251 08:06:37.221207 [SSUSB] phy power-on done.
9252 08:06:37.224781 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9253 08:06:37.231739 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9254 08:06:37.234531 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9255 08:06:37.241553 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9256 08:06:37.248087 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9257 08:06:37.254529 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9258 08:06:37.261260 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9259 08:06:37.267956 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9260 08:06:37.271129 SPM: binary array size = 0x9dc
9261 08:06:37.274366 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9262 08:06:37.281173 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9263 08:06:37.287841 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9264 08:06:37.291108 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9265 08:06:37.297218 configure_display: Starting display init
9266 08:06:37.331686 anx7625_power_on_init: Init interface.
9267 08:06:37.334684 anx7625_disable_pd_protocol: Disabled PD feature.
9268 08:06:37.338572 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9269 08:06:37.366031 anx7625_start_dp_work: Secure OCM version=00
9270 08:06:37.369141 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9271 08:06:37.383912 sp_tx_get_edid_block: EDID Block = 1
9272 08:06:37.486252 Extracted contents:
9273 08:06:37.489703 header: 00 ff ff ff ff ff ff 00
9274 08:06:37.492715 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9275 08:06:37.496317 version: 01 04
9276 08:06:37.499768 basic params: 95 1f 11 78 0a
9277 08:06:37.503126 chroma info: 76 90 94 55 54 90 27 21 50 54
9278 08:06:37.506267 established: 00 00 00
9279 08:06:37.512780 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9280 08:06:37.516640 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9281 08:06:37.522738 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9282 08:06:37.529325 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9283 08:06:37.536380 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9284 08:06:37.539505 extensions: 00
9285 08:06:37.540063 checksum: fb
9286 08:06:37.540432
9287 08:06:37.542699 Manufacturer: IVO Model 57d Serial Number 0
9288 08:06:37.546220 Made week 0 of 2020
9289 08:06:37.546783 EDID version: 1.4
9290 08:06:37.549375 Digital display
9291 08:06:37.552591 6 bits per primary color channel
9292 08:06:37.553197 DisplayPort interface
9293 08:06:37.555761 Maximum image size: 31 cm x 17 cm
9294 08:06:37.559082 Gamma: 220%
9295 08:06:37.559532 Check DPMS levels
9296 08:06:37.562249 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9297 08:06:37.569073 First detailed timing is preferred timing
9298 08:06:37.569535 Established timings supported:
9299 08:06:37.572096 Standard timings supported:
9300 08:06:37.575575 Detailed timings
9301 08:06:37.579016 Hex of detail: 383680a07038204018303c0035ae10000019
9302 08:06:37.582351 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9303 08:06:37.589105 0780 0798 07c8 0820 hborder 0
9304 08:06:37.592301 0438 043b 0447 0458 vborder 0
9305 08:06:37.595756 -hsync -vsync
9306 08:06:37.596300 Did detailed timing
9307 08:06:37.602256 Hex of detail: 000000000000000000000000000000000000
9308 08:06:37.605533 Manufacturer-specified data, tag 0
9309 08:06:37.608725 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9310 08:06:37.611817 ASCII string: InfoVision
9311 08:06:37.615498 Hex of detail: 000000fe00523134304e574635205248200a
9312 08:06:37.618742 ASCII string: R140NWF5 RH
9313 08:06:37.619286 Checksum
9314 08:06:37.621809 Checksum: 0xfb (valid)
9315 08:06:37.625577 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9316 08:06:37.628627 DSI data_rate: 832800000 bps
9317 08:06:37.635137 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9318 08:06:37.638480 anx7625_parse_edid: pixelclock(138800).
9319 08:06:37.641775 hactive(1920), hsync(48), hfp(24), hbp(88)
9320 08:06:37.645320 vactive(1080), vsync(12), vfp(3), vbp(17)
9321 08:06:37.648466 anx7625_dsi_config: config dsi.
9322 08:06:37.655146 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9323 08:06:37.668397 anx7625_dsi_config: success to config DSI
9324 08:06:37.671623 anx7625_dp_start: MIPI phy setup OK.
9325 08:06:37.675242 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9326 08:06:37.678140 mtk_ddp_mode_set invalid vrefresh 60
9327 08:06:37.682234 main_disp_path_setup
9328 08:06:37.682680 ovl_layer_smi_id_en
9329 08:06:37.685191 ovl_layer_smi_id_en
9330 08:06:37.685728 ccorr_config
9331 08:06:37.686091 aal_config
9332 08:06:37.688532 gamma_config
9333 08:06:37.689121 postmask_config
9334 08:06:37.691736 dither_config
9335 08:06:37.695274 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9336 08:06:37.701505 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9337 08:06:37.705682 Root Device init finished in 553 msecs
9338 08:06:37.708195 CPU_CLUSTER: 0 init
9339 08:06:37.715408 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9340 08:06:37.718337 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9341 08:06:37.721652 APU_MBOX 0x190000b0 = 0x10001
9342 08:06:37.725131 APU_MBOX 0x190001b0 = 0x10001
9343 08:06:37.728410 APU_MBOX 0x190005b0 = 0x10001
9344 08:06:37.731607 APU_MBOX 0x190006b0 = 0x10001
9345 08:06:37.734795 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9346 08:06:37.747504 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9347 08:06:37.760154 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9348 08:06:37.766501 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9349 08:06:37.778117 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9350 08:06:37.787338 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9351 08:06:37.790779 CPU_CLUSTER: 0 init finished in 81 msecs
9352 08:06:37.793774 Devices initialized
9353 08:06:37.797054 Show all devs... After init.
9354 08:06:37.797570 Root Device: enabled 1
9355 08:06:37.801089 CPU_CLUSTER: 0: enabled 1
9356 08:06:37.803882 CPU: 00: enabled 1
9357 08:06:37.806795 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9358 08:06:37.810811 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9359 08:06:37.813530 ELOG: NV offset 0x57f000 size 0x1000
9360 08:06:37.820589 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9361 08:06:37.827098 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9362 08:06:37.830391 ELOG: Event(17) added with size 13 at 2023-09-21 08:06:15 UTC
9363 08:06:37.836902 out: cmd=0x121: 03 db 21 01 00 00 00 00
9364 08:06:37.840081 in-header: 03 2e 00 00 2c 00 00 00
9365 08:06:37.849813 in-data: 31 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9366 08:06:37.856949 ELOG: Event(A1) added with size 10 at 2023-09-21 08:06:15 UTC
9367 08:06:37.863316 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9368 08:06:37.869762 ELOG: Event(A0) added with size 9 at 2023-09-21 08:06:15 UTC
9369 08:06:37.873597 elog_add_boot_reason: Logged dev mode boot
9370 08:06:37.879753 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9371 08:06:37.880315 Finalize devices...
9372 08:06:37.883168 Devices finalized
9373 08:06:37.886579 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9374 08:06:37.889762 Writing coreboot table at 0xffe64000
9375 08:06:37.893101 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 08:06:37.896293 1. 0000000040000000-00000000400fffff: RAM
9377 08:06:37.903224 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 08:06:37.906825 3. 000000004032b000-00000000545fffff: RAM
9379 08:06:37.909715 4. 0000000054600000-000000005465ffff: BL31
9380 08:06:37.912688 5. 0000000054660000-00000000ffe63fff: RAM
9381 08:06:37.919766 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 08:06:37.923169 7. 0000000100000000-000000023fffffff: RAM
9383 08:06:37.926373 Passing 5 GPIOs to payload:
9384 08:06:37.929723 NAME | PORT | POLARITY | VALUE
9385 08:06:37.933283 EC in RW | 0x000000aa | low | undefined
9386 08:06:37.939797 EC interrupt | 0x00000005 | low | undefined
9387 08:06:37.942981 TPM interrupt | 0x000000ab | high | undefined
9388 08:06:37.949652 SD card detect | 0x00000011 | high | undefined
9389 08:06:37.952852 speaker enable | 0x00000093 | high | undefined
9390 08:06:37.956213 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 08:06:37.959825 in-header: 03 f9 00 00 02 00 00 00
9392 08:06:37.962738 in-data: 02 00
9393 08:06:37.963303 ADC[4]: Raw value=900663 ID=7
9394 08:06:37.966013 ADC[3]: Raw value=212810 ID=1
9395 08:06:37.969246 RAM Code: 0x71
9396 08:06:37.969812 ADC[6]: Raw value=74870 ID=0
9397 08:06:37.972744 ADC[5]: Raw value=212072 ID=1
9398 08:06:37.975706 SKU Code: 0x1
9399 08:06:37.979145 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5bd8
9400 08:06:37.982720 coreboot table: 964 bytes.
9401 08:06:37.986085 IMD ROOT 0. 0xfffff000 0x00001000
9402 08:06:37.988909 IMD SMALL 1. 0xffffe000 0x00001000
9403 08:06:37.992209 RO MCACHE 2. 0xffffc000 0x00001104
9404 08:06:37.995486 CONSOLE 3. 0xfff7c000 0x00080000
9405 08:06:37.998968 FMAP 4. 0xfff7b000 0x00000452
9406 08:06:38.002557 TIME STAMP 5. 0xfff7a000 0x00000910
9407 08:06:38.005511 VBOOT WORK 6. 0xfff66000 0x00014000
9408 08:06:38.008865 RAMOOPS 7. 0xffe66000 0x00100000
9409 08:06:38.012127 COREBOOT 8. 0xffe64000 0x00002000
9410 08:06:38.015338 IMD small region:
9411 08:06:38.018732 IMD ROOT 0. 0xffffec00 0x00000400
9412 08:06:38.022371 VPD 1. 0xffffeb80 0x0000006c
9413 08:06:38.025356 MMC STATUS 2. 0xffffeb60 0x00000004
9414 08:06:38.028836 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 08:06:38.032337 Probing TPM: done!
9416 08:06:38.035763 Connected to device vid:did:rid of 1ae0:0028:00
9417 08:06:38.045771 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9418 08:06:38.049301 Initialized TPM device CR50 revision 0
9419 08:06:38.052585 Checking cr50 for pending updates
9420 08:06:38.057053 Reading cr50 TPM mode
9421 08:06:38.065378 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9422 08:06:38.072235 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9423 08:06:38.112000 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9424 08:06:38.115709 Checking segment from ROM address 0x40100000
9425 08:06:38.118783 Checking segment from ROM address 0x4010001c
9426 08:06:38.125557 Loading segment from ROM address 0x40100000
9427 08:06:38.126128 code (compression=0)
9428 08:06:38.132340 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9429 08:06:38.142387 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9430 08:06:38.142960 it's not compressed!
9431 08:06:38.149055 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9432 08:06:38.152397 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9433 08:06:38.172820 Loading segment from ROM address 0x4010001c
9434 08:06:38.173424 Entry Point 0x80000000
9435 08:06:38.176005 Loaded segments
9436 08:06:38.179132 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9437 08:06:38.185817 Jumping to boot code at 0x80000000(0xffe64000)
9438 08:06:38.192774 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9439 08:06:38.198939 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9440 08:06:38.207025 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9441 08:06:38.210149 Checking segment from ROM address 0x40100000
9442 08:06:38.213330 Checking segment from ROM address 0x4010001c
9443 08:06:38.220443 Loading segment from ROM address 0x40100000
9444 08:06:38.221070 code (compression=1)
9445 08:06:38.227203 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9446 08:06:38.237032 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9447 08:06:38.237599 using LZMA
9448 08:06:38.245670 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9449 08:06:38.252009 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9450 08:06:38.255308 Loading segment from ROM address 0x4010001c
9451 08:06:38.255875 Entry Point 0x54601000
9452 08:06:38.258179 Loaded segments
9453 08:06:38.261793 NOTICE: MT8192 bl31_setup
9454 08:06:38.268901 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9455 08:06:38.272530 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9456 08:06:38.275791 WARNING: region 0:
9457 08:06:38.279454 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 08:06:38.280023 WARNING: region 1:
9459 08:06:38.285772 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9460 08:06:38.288905 WARNING: region 2:
9461 08:06:38.292814 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9462 08:06:38.295791 WARNING: region 3:
9463 08:06:38.298825 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 08:06:38.302521 WARNING: region 4:
9465 08:06:38.305877 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 08:06:38.308979 WARNING: region 5:
9467 08:06:38.316853 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 08:06:38.317005 WARNING: region 6:
9469 08:06:38.318458 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 08:06:38.318541 WARNING: region 7:
9471 08:06:38.325293 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 08:06:38.332098 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9473 08:06:38.335282 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9474 08:06:38.339099 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9475 08:06:38.345712 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9476 08:06:38.348761 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9477 08:06:38.352324 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9478 08:06:38.358855 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9479 08:06:38.362559 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9480 08:06:38.365490 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9481 08:06:38.372165 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9482 08:06:38.375499 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9483 08:06:38.382481 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9484 08:06:38.385769 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9485 08:06:38.389296 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9486 08:06:38.395722 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9487 08:06:38.399252 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9488 08:06:38.402673 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9489 08:06:38.409475 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9490 08:06:38.412565 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9491 08:06:38.415860 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9492 08:06:38.422607 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9493 08:06:38.425735 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9494 08:06:38.432878 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9495 08:06:38.436140 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9496 08:06:38.439281 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9497 08:06:38.445993 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9498 08:06:38.449050 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9499 08:06:38.455716 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9500 08:06:38.459628 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9501 08:06:38.462464 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9502 08:06:38.469260 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9503 08:06:38.473144 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9504 08:06:38.476347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9505 08:06:38.482766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9506 08:06:38.486372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9507 08:06:38.489286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9508 08:06:38.493116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9509 08:06:38.499501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9510 08:06:38.503349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9511 08:06:38.506438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9512 08:06:38.509809 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9513 08:06:38.512768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9514 08:06:38.519850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9515 08:06:38.523122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9516 08:06:38.526157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9517 08:06:38.533143 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9518 08:06:38.536254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9519 08:06:38.539624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9520 08:06:38.546084 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9521 08:06:38.549660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9522 08:06:38.553094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9523 08:06:38.559731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9524 08:06:38.563335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9525 08:06:38.569738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9526 08:06:38.573473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9527 08:06:38.576897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9528 08:06:38.583240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9529 08:06:38.586676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9530 08:06:38.593631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9531 08:06:38.597147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9532 08:06:38.603019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9533 08:06:38.606308 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9534 08:06:38.613379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9535 08:06:38.616427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9536 08:06:38.619714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9537 08:06:38.626418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9538 08:06:38.629832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9539 08:06:38.636369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9540 08:06:38.640080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9541 08:06:38.643154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9542 08:06:38.650071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9543 08:06:38.653040 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9544 08:06:38.659886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9545 08:06:38.662912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9546 08:06:38.669925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9547 08:06:38.673659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9548 08:06:38.679828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9549 08:06:38.683297 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9550 08:06:38.686369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9551 08:06:38.693425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9552 08:06:38.696654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9553 08:06:38.703562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9554 08:06:38.706451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9555 08:06:38.713192 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9556 08:06:38.716446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9557 08:06:38.719791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9558 08:06:38.726544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9559 08:06:38.729847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9560 08:06:38.736414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9561 08:06:38.740101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9562 08:06:38.746691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9563 08:06:38.749604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9564 08:06:38.753289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9565 08:06:38.759646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9566 08:06:38.763658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9567 08:06:38.770244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9568 08:06:38.773195 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9569 08:06:38.776993 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9570 08:06:38.779902 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9571 08:06:38.786697 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9572 08:06:38.790092 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9573 08:06:38.793736 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9574 08:06:38.800114 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9575 08:06:38.803566 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9576 08:06:38.810171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9577 08:06:38.813476 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9578 08:06:38.817064 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9579 08:06:38.823531 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9580 08:06:38.826695 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9581 08:06:38.833383 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9582 08:06:38.836811 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9583 08:06:38.839984 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9584 08:06:38.846561 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9585 08:06:38.849872 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9586 08:06:38.856737 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9587 08:06:38.860218 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9588 08:06:38.863345 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9589 08:06:38.866857 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9590 08:06:38.873205 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9591 08:06:38.876617 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9592 08:06:38.880474 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9593 08:06:38.884179 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9594 08:06:38.890118 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9595 08:06:38.893149 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9596 08:06:38.896496 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9597 08:06:38.903592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9598 08:06:38.906801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9599 08:06:38.910013 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9600 08:06:38.916841 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9601 08:06:38.920151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9602 08:06:38.926972 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9603 08:06:38.930005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9604 08:06:38.933489 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9605 08:06:38.940473 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9606 08:06:38.943680 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9607 08:06:38.950114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9608 08:06:38.953402 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9609 08:06:38.956956 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9610 08:06:38.963930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9611 08:06:38.966776 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9612 08:06:38.970176 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9613 08:06:38.977042 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9614 08:06:38.980169 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9615 08:06:38.986936 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9616 08:06:38.990403 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9617 08:06:38.993633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9618 08:06:38.999949 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9619 08:06:39.003534 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9620 08:06:39.010513 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9621 08:06:39.013847 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9622 08:06:39.016822 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9623 08:06:39.024010 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9624 08:06:39.026914 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9625 08:06:39.030244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9626 08:06:39.037039 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9627 08:06:39.040489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9628 08:06:39.046799 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9629 08:06:39.050213 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9630 08:06:39.053661 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9631 08:06:39.060388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9632 08:06:39.063848 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9633 08:06:39.069996 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9634 08:06:39.073570 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9635 08:06:39.076599 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9636 08:06:39.083422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9637 08:06:39.086837 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9638 08:06:39.089712 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9639 08:06:39.096836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9640 08:06:39.099854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9641 08:06:39.106389 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9642 08:06:39.110098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9643 08:06:39.112912 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9644 08:06:39.119820 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9645 08:06:39.123501 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9646 08:06:39.130010 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9647 08:06:39.133015 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9648 08:06:39.136841 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9649 08:06:39.143339 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9650 08:06:39.146679 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9651 08:06:39.149859 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9652 08:06:39.156996 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9653 08:06:39.160340 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9654 08:06:39.167021 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9655 08:06:39.170079 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9656 08:06:39.173554 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9657 08:06:39.179949 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9658 08:06:39.183582 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9659 08:06:39.190201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9660 08:06:39.193358 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9661 08:06:39.196659 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9662 08:06:39.203285 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9663 08:06:39.207047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9664 08:06:39.213212 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9665 08:06:39.216477 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9666 08:06:39.223233 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9667 08:06:39.226222 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9668 08:06:39.229599 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9669 08:06:39.236321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9670 08:06:39.239645 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9671 08:06:39.246358 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9672 08:06:39.249828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9673 08:06:39.253452 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9674 08:06:39.259769 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9675 08:06:39.262940 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9676 08:06:39.269574 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9677 08:06:39.272855 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9678 08:06:39.279305 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9679 08:06:39.282885 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9680 08:06:39.286325 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9681 08:06:39.292961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9682 08:06:39.296252 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9683 08:06:39.302658 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9684 08:06:39.306250 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9685 08:06:39.312499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9686 08:06:39.315872 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9687 08:06:39.318930 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9688 08:06:39.326267 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9689 08:06:39.329104 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9690 08:06:39.335857 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9691 08:06:39.339177 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9692 08:06:39.342428 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9693 08:06:39.349257 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9694 08:06:39.352512 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9695 08:06:39.359155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9696 08:06:39.362624 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9697 08:06:39.368786 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9698 08:06:39.372517 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9699 08:06:39.375722 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9700 08:06:39.382298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9701 08:06:39.385510 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9702 08:06:39.389115 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9703 08:06:39.392342 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9704 08:06:39.398889 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9705 08:06:39.401924 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9706 08:06:39.405777 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9707 08:06:39.412468 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9708 08:06:39.415875 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9709 08:06:39.418661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9710 08:06:39.425685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9711 08:06:39.428846 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9712 08:06:39.432191 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9713 08:06:39.438674 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9714 08:06:39.442058 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9715 08:06:39.445454 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9716 08:06:39.451996 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9717 08:06:39.455821 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9718 08:06:39.462377 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9719 08:06:39.465540 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9720 08:06:39.468993 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9721 08:06:39.475618 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9722 08:06:39.478635 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9723 08:06:39.482370 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9724 08:06:39.489099 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9725 08:06:39.492017 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9726 08:06:39.498565 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9727 08:06:39.501583 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9728 08:06:39.505353 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9729 08:06:39.511741 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9730 08:06:39.515193 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9731 08:06:39.518389 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9732 08:06:39.525217 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9733 08:06:39.528479 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9734 08:06:39.535217 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9735 08:06:39.538662 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9736 08:06:39.541900 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9737 08:06:39.548792 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9738 08:06:39.551751 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9739 08:06:39.555374 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9740 08:06:39.562171 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9741 08:06:39.564862 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9742 08:06:39.568676 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9743 08:06:39.572113 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9744 08:06:39.574916 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9745 08:06:39.581578 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9746 08:06:39.585232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9747 08:06:39.588721 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9748 08:06:39.592006 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9749 08:06:39.598244 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9750 08:06:39.601830 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9751 08:06:39.605121 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9752 08:06:39.611930 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9753 08:06:39.615234 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9754 08:06:39.618319 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9755 08:06:39.625145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9756 08:06:39.628540 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9757 08:06:39.631504 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9758 08:06:39.638085 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9759 08:06:39.641405 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9760 08:06:39.648361 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9761 08:06:39.651424 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9762 08:06:39.654881 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9763 08:06:39.661550 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9764 08:06:39.664869 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9765 08:06:39.671342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9766 08:06:39.674574 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9767 08:06:39.681227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9768 08:06:39.684825 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9769 08:06:39.688375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9770 08:06:39.694911 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9771 08:06:39.698137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9772 08:06:39.704670 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9773 08:06:39.707889 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9774 08:06:39.711588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9775 08:06:39.717927 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9776 08:06:39.721141 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9777 08:06:39.728238 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9778 08:06:39.731236 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9779 08:06:39.734906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9780 08:06:39.741181 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9781 08:06:39.744619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9782 08:06:39.751148 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9783 08:06:39.754645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9784 08:06:39.761235 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9785 08:06:39.764484 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9786 08:06:39.767928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9787 08:06:39.774608 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9788 08:06:39.777862 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9789 08:06:39.781160 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9790 08:06:39.788181 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9791 08:06:39.791456 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9792 08:06:39.797833 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9793 08:06:39.801357 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9794 08:06:39.804653 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9795 08:06:39.811264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9796 08:06:39.814808 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9797 08:06:39.821390 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9798 08:06:39.824608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9799 08:06:39.830928 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9800 08:06:39.834632 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9801 08:06:39.837496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9802 08:06:39.844693 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9803 08:06:39.847584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9804 08:06:39.854327 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9805 08:06:39.857520 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9806 08:06:39.860854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9807 08:06:39.867294 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9808 08:06:39.870793 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9809 08:06:39.877584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9810 08:06:39.880752 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9811 08:06:39.883982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9812 08:06:39.890731 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9813 08:06:39.894512 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9814 08:06:39.901293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9815 08:06:39.904189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9816 08:06:39.910533 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9817 08:06:39.914206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9818 08:06:39.917609 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9819 08:06:39.923791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9820 08:06:39.927554 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9821 08:06:39.933876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9822 08:06:39.937341 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9823 08:06:39.940465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9824 08:06:39.947263 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9825 08:06:39.950695 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9826 08:06:39.957320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9827 08:06:39.960468 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9828 08:06:39.964084 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9829 08:06:39.970147 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9830 08:06:39.973550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9831 08:06:39.979929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9832 08:06:39.983774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9833 08:06:39.990271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9834 08:06:39.993625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9835 08:06:39.997044 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9836 08:06:40.004251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9837 08:06:40.006944 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9838 08:06:40.013885 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9839 08:06:40.017376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9840 08:06:40.023886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9841 08:06:40.026745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9842 08:06:40.030737 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9843 08:06:40.037099 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9844 08:06:40.040513 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9845 08:06:40.046865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9846 08:06:40.050174 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9847 08:06:40.056820 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9848 08:06:40.060126 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9849 08:06:40.063812 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9850 08:06:40.070199 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9851 08:06:40.073574 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9852 08:06:40.080253 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9853 08:06:40.083635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9854 08:06:40.090060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9855 08:06:40.093389 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9856 08:06:40.100248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9857 08:06:40.103352 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9858 08:06:40.106847 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9859 08:06:40.113505 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9860 08:06:40.116791 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9861 08:06:40.123246 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9862 08:06:40.126710 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9863 08:06:40.133362 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9864 08:06:40.137194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9865 08:06:40.139836 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9866 08:06:40.146598 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9867 08:06:40.149748 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9868 08:06:40.156682 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9869 08:06:40.159905 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9870 08:06:40.166561 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9871 08:06:40.170451 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9872 08:06:40.173442 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9873 08:06:40.180027 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9874 08:06:40.183465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9875 08:06:40.189972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9876 08:06:40.193278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9877 08:06:40.197072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9878 08:06:40.202935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9879 08:06:40.206793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9880 08:06:40.213105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9881 08:06:40.216673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9882 08:06:40.222993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9883 08:06:40.226484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9884 08:06:40.233304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9885 08:06:40.236576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9886 08:06:40.243267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9887 08:06:40.246944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9888 08:06:40.253032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9889 08:06:40.256696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9890 08:06:40.263464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9891 08:06:40.266506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9892 08:06:40.273162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9893 08:06:40.276533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9894 08:06:40.283092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9895 08:06:40.286284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9896 08:06:40.293001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9897 08:06:40.296801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9898 08:06:40.302889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9899 08:06:40.306237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9900 08:06:40.313091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9901 08:06:40.316306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9902 08:06:40.322922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9903 08:06:40.325893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9904 08:06:40.333077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9905 08:06:40.336549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9906 08:06:40.339541 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9907 08:06:40.343297 INFO: [APUAPC] vio 0
9908 08:06:40.349852 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9909 08:06:40.352975 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9910 08:06:40.356670 INFO: [APUAPC] D0_APC_0: 0x400510
9911 08:06:40.359491 INFO: [APUAPC] D0_APC_1: 0x0
9912 08:06:40.362832 INFO: [APUAPC] D0_APC_2: 0x1540
9913 08:06:40.366154 INFO: [APUAPC] D0_APC_3: 0x0
9914 08:06:40.369483 INFO: [APUAPC] D1_APC_0: 0xffffffff
9915 08:06:40.373136 INFO: [APUAPC] D1_APC_1: 0xffffffff
9916 08:06:40.376202 INFO: [APUAPC] D1_APC_2: 0x3fffff
9917 08:06:40.376761 INFO: [APUAPC] D1_APC_3: 0x0
9918 08:06:40.382942 INFO: [APUAPC] D2_APC_0: 0xffffffff
9919 08:06:40.386264 INFO: [APUAPC] D2_APC_1: 0xffffffff
9920 08:06:40.389110 INFO: [APUAPC] D2_APC_2: 0x3fffff
9921 08:06:40.389577 INFO: [APUAPC] D2_APC_3: 0x0
9922 08:06:40.392416 INFO: [APUAPC] D3_APC_0: 0xffffffff
9923 08:06:40.396312 INFO: [APUAPC] D3_APC_1: 0xffffffff
9924 08:06:40.399489 INFO: [APUAPC] D3_APC_2: 0x3fffff
9925 08:06:40.402627 INFO: [APUAPC] D3_APC_3: 0x0
9926 08:06:40.405953 INFO: [APUAPC] D4_APC_0: 0xffffffff
9927 08:06:40.409331 INFO: [APUAPC] D4_APC_1: 0xffffffff
9928 08:06:40.412519 INFO: [APUAPC] D4_APC_2: 0x3fffff
9929 08:06:40.415643 INFO: [APUAPC] D4_APC_3: 0x0
9930 08:06:40.419244 INFO: [APUAPC] D5_APC_0: 0xffffffff
9931 08:06:40.422231 INFO: [APUAPC] D5_APC_1: 0xffffffff
9932 08:06:40.425715 INFO: [APUAPC] D5_APC_2: 0x3fffff
9933 08:06:40.428923 INFO: [APUAPC] D5_APC_3: 0x0
9934 08:06:40.432426 INFO: [APUAPC] D6_APC_0: 0xffffffff
9935 08:06:40.435848 INFO: [APUAPC] D6_APC_1: 0xffffffff
9936 08:06:40.438927 INFO: [APUAPC] D6_APC_2: 0x3fffff
9937 08:06:40.442364 INFO: [APUAPC] D6_APC_3: 0x0
9938 08:06:40.445818 INFO: [APUAPC] D7_APC_0: 0xffffffff
9939 08:06:40.449402 INFO: [APUAPC] D7_APC_1: 0xffffffff
9940 08:06:40.452541 INFO: [APUAPC] D7_APC_2: 0x3fffff
9941 08:06:40.455452 INFO: [APUAPC] D7_APC_3: 0x0
9942 08:06:40.458795 INFO: [APUAPC] D8_APC_0: 0xffffffff
9943 08:06:40.462270 INFO: [APUAPC] D8_APC_1: 0xffffffff
9944 08:06:40.465546 INFO: [APUAPC] D8_APC_2: 0x3fffff
9945 08:06:40.469026 INFO: [APUAPC] D8_APC_3: 0x0
9946 08:06:40.472424 INFO: [APUAPC] D9_APC_0: 0xffffffff
9947 08:06:40.475107 INFO: [APUAPC] D9_APC_1: 0xffffffff
9948 08:06:40.478881 INFO: [APUAPC] D9_APC_2: 0x3fffff
9949 08:06:40.482218 INFO: [APUAPC] D9_APC_3: 0x0
9950 08:06:40.485831 INFO: [APUAPC] D10_APC_0: 0xffffffff
9951 08:06:40.488903 INFO: [APUAPC] D10_APC_1: 0xffffffff
9952 08:06:40.492106 INFO: [APUAPC] D10_APC_2: 0x3fffff
9953 08:06:40.495091 INFO: [APUAPC] D10_APC_3: 0x0
9954 08:06:40.498432 INFO: [APUAPC] D11_APC_0: 0xffffffff
9955 08:06:40.501810 INFO: [APUAPC] D11_APC_1: 0xffffffff
9956 08:06:40.504849 INFO: [APUAPC] D11_APC_2: 0x3fffff
9957 08:06:40.508563 INFO: [APUAPC] D11_APC_3: 0x0
9958 08:06:40.511921 INFO: [APUAPC] D12_APC_0: 0xffffffff
9959 08:06:40.515393 INFO: [APUAPC] D12_APC_1: 0xffffffff
9960 08:06:40.518299 INFO: [APUAPC] D12_APC_2: 0x3fffff
9961 08:06:40.521677 INFO: [APUAPC] D12_APC_3: 0x0
9962 08:06:40.525025 INFO: [APUAPC] D13_APC_0: 0xffffffff
9963 08:06:40.528349 INFO: [APUAPC] D13_APC_1: 0xffffffff
9964 08:06:40.531848 INFO: [APUAPC] D13_APC_2: 0x3fffff
9965 08:06:40.535065 INFO: [APUAPC] D13_APC_3: 0x0
9966 08:06:40.538431 INFO: [APUAPC] D14_APC_0: 0xffffffff
9967 08:06:40.541663 INFO: [APUAPC] D14_APC_1: 0xffffffff
9968 08:06:40.545147 INFO: [APUAPC] D14_APC_2: 0x3fffff
9969 08:06:40.548460 INFO: [APUAPC] D14_APC_3: 0x0
9970 08:06:40.551635 INFO: [APUAPC] D15_APC_0: 0xffffffff
9971 08:06:40.555173 INFO: [APUAPC] D15_APC_1: 0xffffffff
9972 08:06:40.558409 INFO: [APUAPC] D15_APC_2: 0x3fffff
9973 08:06:40.561575 INFO: [APUAPC] D15_APC_3: 0x0
9974 08:06:40.565199 INFO: [APUAPC] APC_CON: 0x4
9975 08:06:40.568883 INFO: [NOCDAPC] D0_APC_0: 0x0
9976 08:06:40.572074 INFO: [NOCDAPC] D0_APC_1: 0x0
9977 08:06:40.572629 INFO: [NOCDAPC] D1_APC_0: 0x0
9978 08:06:40.575217 INFO: [NOCDAPC] D1_APC_1: 0xfff
9979 08:06:40.578446 INFO: [NOCDAPC] D2_APC_0: 0x0
9980 08:06:40.581855 INFO: [NOCDAPC] D2_APC_1: 0xfff
9981 08:06:40.584975 INFO: [NOCDAPC] D3_APC_0: 0x0
9982 08:06:40.588285 INFO: [NOCDAPC] D3_APC_1: 0xfff
9983 08:06:40.591981 INFO: [NOCDAPC] D4_APC_0: 0x0
9984 08:06:40.595316 INFO: [NOCDAPC] D4_APC_1: 0xfff
9985 08:06:40.598657 INFO: [NOCDAPC] D5_APC_0: 0x0
9986 08:06:40.601934 INFO: [NOCDAPC] D5_APC_1: 0xfff
9987 08:06:40.605005 INFO: [NOCDAPC] D6_APC_0: 0x0
9988 08:06:40.605558 INFO: [NOCDAPC] D6_APC_1: 0xfff
9989 08:06:40.608666 INFO: [NOCDAPC] D7_APC_0: 0x0
9990 08:06:40.612082 INFO: [NOCDAPC] D7_APC_1: 0xfff
9991 08:06:40.615352 INFO: [NOCDAPC] D8_APC_0: 0x0
9992 08:06:40.619065 INFO: [NOCDAPC] D8_APC_1: 0xfff
9993 08:06:40.622007 INFO: [NOCDAPC] D9_APC_0: 0x0
9994 08:06:40.624972 INFO: [NOCDAPC] D9_APC_1: 0xfff
9995 08:06:40.628395 INFO: [NOCDAPC] D10_APC_0: 0x0
9996 08:06:40.632073 INFO: [NOCDAPC] D10_APC_1: 0xfff
9997 08:06:40.635159 INFO: [NOCDAPC] D11_APC_0: 0x0
9998 08:06:40.638427 INFO: [NOCDAPC] D11_APC_1: 0xfff
9999 08:06:40.641796 INFO: [NOCDAPC] D12_APC_0: 0x0
10000 08:06:40.642263 INFO: [NOCDAPC] D12_APC_1: 0xfff
10001 08:06:40.645142 INFO: [NOCDAPC] D13_APC_0: 0x0
10002 08:06:40.648419 INFO: [NOCDAPC] D13_APC_1: 0xfff
10003 08:06:40.651867 INFO: [NOCDAPC] D14_APC_0: 0x0
10004 08:06:40.655607 INFO: [NOCDAPC] D14_APC_1: 0xfff
10005 08:06:40.658774 INFO: [NOCDAPC] D15_APC_0: 0x0
10006 08:06:40.661478 INFO: [NOCDAPC] D15_APC_1: 0xfff
10007 08:06:40.664922 INFO: [NOCDAPC] APC_CON: 0x4
10008 08:06:40.668294 INFO: [APUAPC] set_apusys_apc done
10009 08:06:40.671571 INFO: [DEVAPC] devapc_init done
10010 08:06:40.675066 INFO: GICv3 without legacy support detected.
10011 08:06:40.678405 INFO: ARM GICv3 driver initialized in EL3
10012 08:06:40.681574 INFO: Maximum SPI INTID supported: 639
10013 08:06:40.688322 INFO: BL31: Initializing runtime services
10014 08:06:40.691650 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10015 08:06:40.695363 INFO: SPM: enable CPC mode
10016 08:06:40.701832 INFO: mcdi ready for mcusys-off-idle and system suspend
10017 08:06:40.704876 INFO: BL31: Preparing for EL3 exit to normal world
10018 08:06:40.708403 INFO: Entry point address = 0x80000000
10019 08:06:40.711755 INFO: SPSR = 0x8
10020 08:06:40.717007
10021 08:06:40.717568
10022 08:06:40.717933
10023 08:06:40.720352 Starting depthcharge on Spherion...
10024 08:06:40.720922
10025 08:06:40.721329 Wipe memory regions:
10026 08:06:40.721670
10027 08:06:40.724074 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10028 08:06:40.724616 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10029 08:06:40.725097 Setting prompt string to ['asurada:']
10030 08:06:40.725550 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10031 08:06:40.726273 [0x00000040000000, 0x00000054600000)
10032 08:06:40.845948
10033 08:06:40.846505 [0x00000054660000, 0x00000080000000)
10034 08:06:41.106672
10035 08:06:41.107230 [0x000000821a7280, 0x000000ffe64000)
10036 08:06:41.851569
10037 08:06:41.852124 [0x00000100000000, 0x00000240000000)
10038 08:06:43.741918
10039 08:06:43.744986 Initializing XHCI USB controller at 0x11200000.
10040 08:06:44.783152
10041 08:06:44.786678 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10042 08:06:44.787247
10043 08:06:44.787810
10044 08:06:44.788216
10045 08:06:44.789076 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 08:06:44.890712 asurada: tftpboot 192.168.201.1 11585993/tftp-deploy-gliuz5fj/kernel/image.itb 11585993/tftp-deploy-gliuz5fj/kernel/cmdline
10048 08:06:44.891559 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 08:06:44.892062 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 08:06:44.896432 tftpboot 192.168.201.1 11585993/tftp-deploy-gliuz5fj/kernel/image.itb tp-deploy-gliuz5fj/kernel/cmdline
10051 08:06:44.896962
10052 08:06:44.897334 Waiting for link
10053 08:06:45.056990
10054 08:06:45.057570 R8152: Initializing
10055 08:06:45.057947
10056 08:06:45.060530 Version 9 (ocp_data = 6010)
10057 08:06:45.061130
10058 08:06:45.063577 R8152: Done initializing
10059 08:06:45.064140
10060 08:06:45.064650 Adding net device
10061 08:06:46.930822
10062 08:06:46.931390 done.
10063 08:06:46.931764
10064 08:06:46.932166 MAC: 00:e0:4c:72:2d:d6
10065 08:06:46.932704
10066 08:06:46.934221 Sending DHCP discover... done.
10067 08:06:46.934683
10068 08:06:46.937482 Waiting for reply... done.
10069 08:06:46.938063
10070 08:06:46.940987 Sending DHCP request... done.
10071 08:06:46.941451
10072 08:06:46.941819 Waiting for reply... done.
10073 08:06:46.942166
10074 08:06:46.944069 My ip is 192.168.201.21
10075 08:06:46.944533
10076 08:06:46.947514 The DHCP server ip is 192.168.201.1
10077 08:06:46.947981
10078 08:06:46.950825 TFTP server IP predefined by user: 192.168.201.1
10079 08:06:46.951400
10080 08:06:46.957263 Bootfile predefined by user: 11585993/tftp-deploy-gliuz5fj/kernel/image.itb
10081 08:06:46.957730
10082 08:06:46.960959 Sending tftp read request... done.
10083 08:06:46.961542
10084 08:06:46.967893 Waiting for the transfer...
10085 08:06:46.968359
10086 08:06:47.280021 00000000 ################################################################
10087 08:06:47.280156
10088 08:06:47.573698 00080000 ################################################################
10089 08:06:47.573831
10090 08:06:47.860086 00100000 ################################################################
10091 08:06:47.860236
10092 08:06:48.242500 00180000 ################################################################
10093 08:06:48.243053
10094 08:06:48.629351 00200000 ################################################################
10095 08:06:48.629843
10096 08:06:49.015090 00280000 ################################################################
10097 08:06:49.015677
10098 08:06:49.405400 00300000 ################################################################
10099 08:06:49.406049
10100 08:06:49.790249 00380000 ################################################################
10101 08:06:49.790745
10102 08:06:50.181044 00400000 ################################################################
10103 08:06:50.181592
10104 08:06:50.588492 00480000 ################################################################
10105 08:06:50.589249
10106 08:06:50.993792 00500000 ################################################################
10107 08:06:50.994300
10108 08:06:51.397064 00580000 ################################################################
10109 08:06:51.397560
10110 08:06:51.778618 00600000 ################################################################
10111 08:06:51.779160
10112 08:06:52.153787 00680000 ################################################################
10113 08:06:52.154281
10114 08:06:52.504859 00700000 ################################################################
10115 08:06:52.505036
10116 08:06:52.877713 00780000 ################################################################
10117 08:06:52.877850
10118 08:06:53.172184 00800000 ################################################################
10119 08:06:53.172317
10120 08:06:53.442613 00880000 ################################################################
10121 08:06:53.442737
10122 08:06:53.739435 00900000 ################################################################
10123 08:06:53.739568
10124 08:06:54.035976 00980000 ################################################################
10125 08:06:54.036110
10126 08:06:54.337952 00a00000 ################################################################
10127 08:06:54.338085
10128 08:06:54.632446 00a80000 ################################################################
10129 08:06:54.632578
10130 08:06:54.922749 00b00000 ################################################################
10131 08:06:54.922894
10132 08:06:55.218227 00b80000 ################################################################
10133 08:06:55.218360
10134 08:06:55.491463 00c00000 ################################################################
10135 08:06:55.491589
10136 08:06:55.789638 00c80000 ################################################################
10137 08:06:55.789771
10138 08:06:56.087587 00d00000 ################################################################
10139 08:06:56.087733
10140 08:06:56.390244 00d80000 ################################################################
10141 08:06:56.390372
10142 08:06:56.693451 00e00000 ################################################################
10143 08:06:56.693582
10144 08:06:56.990329 00e80000 ################################################################
10145 08:06:56.990476
10146 08:06:57.275108 00f00000 ################################################################
10147 08:06:57.275244
10148 08:06:57.572270 00f80000 ################################################################
10149 08:06:57.572400
10150 08:06:57.867345 01000000 ################################################################
10151 08:06:57.867479
10152 08:06:58.157406 01080000 ################################################################
10153 08:06:58.157550
10154 08:06:58.452316 01100000 ################################################################
10155 08:06:58.452446
10156 08:06:58.729098 01180000 ################################################################
10157 08:06:58.729227
10158 08:06:59.005605 01200000 ################################################################
10159 08:06:59.005738
10160 08:06:59.291082 01280000 ################################################################
10161 08:06:59.291205
10162 08:06:59.582067 01300000 ################################################################
10163 08:06:59.582197
10164 08:06:59.865332 01380000 ################################################################
10165 08:06:59.865460
10166 08:07:00.161028 01400000 ################################################################
10167 08:07:00.161167
10168 08:07:00.458896 01480000 ################################################################
10169 08:07:00.459025
10170 08:07:00.760523 01500000 ################################################################
10171 08:07:00.760653
10172 08:07:01.059647 01580000 ################################################################
10173 08:07:01.059786
10174 08:07:01.357715 01600000 ################################################################
10175 08:07:01.357845
10176 08:07:01.653854 01680000 ################################################################
10177 08:07:01.653984
10178 08:07:01.951175 01700000 ################################################################
10179 08:07:01.951306
10180 08:07:02.233331 01780000 ################################################################
10181 08:07:02.233480
10182 08:07:02.554774 01800000 ################################################################
10183 08:07:02.555323
10184 08:07:02.931440 01880000 ################################################################
10185 08:07:02.931939
10186 08:07:03.324749 01900000 ################################################################
10187 08:07:03.325331
10188 08:07:03.707027 01980000 ################################################################
10189 08:07:03.707719
10190 08:07:04.076533 01a00000 ################################################################
10191 08:07:04.076718
10192 08:07:04.448339 01a80000 ################################################################
10193 08:07:04.448888
10194 08:07:04.844284 01b00000 ################################################################
10195 08:07:04.844841
10196 08:07:05.230724 01b80000 ################################################################
10197 08:07:05.230887
10198 08:07:05.525820 01c00000 ################################################################
10199 08:07:05.525960
10200 08:07:05.776241 01c80000 ################################################################
10201 08:07:05.776370
10202 08:07:06.026348 01d00000 ################################################################
10203 08:07:06.026477
10204 08:07:06.321140 01d80000 ################################################################
10205 08:07:06.321276
10206 08:07:06.614865 01e00000 ################################################################
10207 08:07:06.615023
10208 08:07:06.910251 01e80000 ################################################################
10209 08:07:06.910383
10210 08:07:07.205111 01f00000 ################################################################
10211 08:07:07.205245
10212 08:07:07.500516 01f80000 ################################################################
10213 08:07:07.500646
10214 08:07:07.761193 02000000 ################################################################
10215 08:07:07.761321
10216 08:07:08.025562 02080000 ################################################################
10217 08:07:08.025690
10218 08:07:08.316083 02100000 ################################################################
10219 08:07:08.316213
10220 08:07:08.613280 02180000 ################################################################
10221 08:07:08.613407
10222 08:07:08.868881 02200000 ################################################################
10223 08:07:08.869104
10224 08:07:09.130072 02280000 ################################################################
10225 08:07:09.130212
10226 08:07:09.410084 02300000 ################################################################
10227 08:07:09.410213
10228 08:07:09.675585 02380000 ################################################################
10229 08:07:09.675709
10230 08:07:09.944606 02400000 ################################################################
10231 08:07:09.944743
10232 08:07:10.239785 02480000 ################################################################
10233 08:07:10.239926
10234 08:07:10.517143 02500000 ################################################################
10235 08:07:10.517276
10236 08:07:10.779773 02580000 ################################################################
10237 08:07:10.780005
10238 08:07:11.074862 02600000 ################################################################
10239 08:07:11.074992
10240 08:07:11.447847 02680000 ################################################################
10241 08:07:11.448527
10242 08:07:11.830735 02700000 ################################################################
10243 08:07:11.831252
10244 08:07:12.207652 02780000 ################################################################
10245 08:07:12.208191
10246 08:07:12.585831 02800000 ################################################################
10247 08:07:12.586449
10248 08:07:12.998175 02880000 ################################################################
10249 08:07:12.998695
10250 08:07:13.419106 02900000 ################################################################
10251 08:07:13.419614
10252 08:07:13.796449 02980000 ################################################################
10253 08:07:13.797027
10254 08:07:14.170841 02a00000 ################################################################
10255 08:07:14.171339
10256 08:07:14.520955 02a80000 ################################################################
10257 08:07:14.521094
10258 08:07:14.822809 02b00000 ################################################################
10259 08:07:14.822959
10260 08:07:15.124893 02b80000 ################################################################
10261 08:07:15.125035
10262 08:07:15.423698 02c00000 ################################################################
10263 08:07:15.423835
10264 08:07:15.709706 02c80000 ################################################################
10265 08:07:15.709833
10266 08:07:16.006548 02d00000 ################################################################
10267 08:07:16.006680
10268 08:07:16.341707 02d80000 ################################################################
10269 08:07:16.341840
10270 08:07:16.593355 02e00000 ################################################################
10271 08:07:16.593479
10272 08:07:16.877455 02e80000 ################################################################
10273 08:07:16.877583
10274 08:07:17.178080 02f00000 ################################################################
10275 08:07:17.178212
10276 08:07:17.439225 02f80000 ################################################################
10277 08:07:17.439351
10278 08:07:17.498135 03000000 ############### done.
10279 08:07:17.498233
10280 08:07:17.501332 The bootfile was 50453134 bytes long.
10281 08:07:17.501419
10282 08:07:17.504774 Sending tftp read request... done.
10283 08:07:17.504886
10284 08:07:17.504977 Waiting for the transfer...
10285 08:07:17.505042
10286 08:07:17.507977 00000000 # done.
10287 08:07:17.508070
10288 08:07:17.514693 Command line loaded dynamically from TFTP file: 11585993/tftp-deploy-gliuz5fj/kernel/cmdline
10289 08:07:17.514870
10290 08:07:17.528196 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10291 08:07:17.528408
10292 08:07:17.531565 Loading FIT.
10293 08:07:17.531777
10294 08:07:17.534972 Image ramdisk-1 has 39358556 bytes.
10295 08:07:17.535201
10296 08:07:17.535329 Image fdt-1 has 47278 bytes.
10297 08:07:17.535444
10298 08:07:17.538308 Image kernel-1 has 11045265 bytes.
10299 08:07:17.538561
10300 08:07:17.548179 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10301 08:07:17.548495
10302 08:07:17.564725 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10303 08:07:17.565334
10304 08:07:17.571622 Choosing best match conf-1 for compat google,spherion-rev2.
10305 08:07:17.576124
10306 08:07:17.580790 Connected to device vid:did:rid of 1ae0:0028:00
10307 08:07:17.588509
10308 08:07:17.591534 tpm_get_response: command 0x17b, return code 0x0
10309 08:07:17.592073
10310 08:07:17.595250 ec_init: CrosEC protocol v3 supported (256, 248)
10311 08:07:17.599338
10312 08:07:17.602734 tpm_cleanup: add release locality here.
10313 08:07:17.603295
10314 08:07:17.603661 Shutting down all USB controllers.
10315 08:07:17.605539
10316 08:07:17.605994 Removing current net device
10317 08:07:17.606363
10318 08:07:17.612190 Exiting depthcharge with code 4 at timestamp: 66200181
10319 08:07:17.612660
10320 08:07:17.615622 LZMA decompressing kernel-1 to 0x821a6718
10321 08:07:17.616187
10322 08:07:17.619175 LZMA decompressing kernel-1 to 0x40000000
10323 08:07:19.006861
10324 08:07:19.007432 jumping to kernel
10325 08:07:19.009020 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10326 08:07:19.009592 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10327 08:07:19.010010 Setting prompt string to ['Linux version [0-9]']
10328 08:07:19.010396 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10329 08:07:19.010788 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10330 08:07:19.088624
10331 08:07:19.092280 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10332 08:07:19.095853 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10333 08:07:19.096440 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10334 08:07:19.096839 Setting prompt string to []
10335 08:07:19.097321 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10336 08:07:19.097731 Using line separator: #'\n'#
10337 08:07:19.098080 No login prompt set.
10338 08:07:19.098421 Parsing kernel messages
10339 08:07:19.098734 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10340 08:07:19.099280 [login-action] Waiting for messages, (timeout 00:03:47)
10341 08:07:19.114781 [ 0.000000] Linux version 6.1.54-cip6 (KernelCI@build-j53272-arm64-gcc-10-defconfig-arm64-chromebook-xzlx8) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023
10342 08:07:19.118563 [ 0.000000] random: crng init done
10343 08:07:19.125046 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 08:07:19.125247 [ 0.000000] efi: UEFI not found.
10345 08:07:19.134992 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 08:07:19.141565 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 08:07:19.151274 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 08:07:19.161500 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 08:07:19.168185 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 08:07:19.174869 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 08:07:19.181408 [ 0.000000] NUMA: No NUMA configuration found
10352 08:07:19.188199 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 08:07:19.191305 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10354 08:07:19.194736 [ 0.000000] Zone ranges:
10355 08:07:19.201548 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 08:07:19.204764 [ 0.000000] DMA32 empty
10357 08:07:19.211290 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 08:07:19.214101 [ 0.000000] Movable zone start for each node
10359 08:07:19.217700 [ 0.000000] Early memory node ranges
10360 08:07:19.224319 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 08:07:19.231285 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 08:07:19.237839 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 08:07:19.244658 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 08:07:19.247963 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 08:07:19.254212 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 08:07:19.313324 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 08:07:19.320152 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 08:07:19.326706 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 08:07:19.329955 [ 0.000000] psci: probing for conduit method from DT.
10370 08:07:19.336392 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 08:07:19.340164 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 08:07:19.346455 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 08:07:19.349605 [ 0.000000] psci: SMC Calling Convention v1.2
10374 08:07:19.356461 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10375 08:07:19.359852 [ 0.000000] Detected VIPT I-cache on CPU0
10376 08:07:19.366510 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 08:07:19.372988 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 08:07:19.379681 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 08:07:19.386257 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 08:07:19.392881 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 08:07:19.399694 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 08:07:19.406065 [ 0.000000] alternatives: applying boot alternatives
10383 08:07:19.409520 [ 0.000000] Fallback order for Node 0: 0
10384 08:07:19.419180 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 08:07:19.419648 [ 0.000000] Policy zone: Normal
10386 08:07:19.436052 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10387 08:07:19.445928 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 08:07:19.457705 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 08:07:19.467695 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 08:07:19.474540 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10391 08:07:19.477474 <6>[ 0.000000] software IO TLB: area num 8.
10392 08:07:19.534182 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 08:07:19.683212 <6>[ 0.000000] Memory: 7930992K/8385536K available (17984K kernel code, 4116K rwdata, 17472K rodata, 8448K init, 615K bss, 421776K reserved, 32768K cma-reserved)
10394 08:07:19.689806 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10395 08:07:19.696415 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10396 08:07:19.699541 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10397 08:07:19.706452 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10398 08:07:19.713055 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10399 08:07:19.716409 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10400 08:07:19.726235 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10401 08:07:19.732875 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10402 08:07:19.736192 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10403 08:07:19.744069 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10404 08:07:19.747367 <6>[ 0.000000] GICv3: 608 SPIs implemented
10405 08:07:19.753997 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10406 08:07:19.756914 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10407 08:07:19.760414 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10408 08:07:19.770217 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10409 08:07:19.780238 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10410 08:07:19.793816 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10411 08:07:19.800658 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10412 08:07:19.809467 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10413 08:07:19.822668 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10414 08:07:19.829436 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10415 08:07:19.836638 <6>[ 0.009240] Console: colour dummy device 80x25
10416 08:07:19.845898 <6>[ 0.013968] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10417 08:07:19.852403 <6>[ 0.024475] pid_max: default: 32768 minimum: 301
10418 08:07:19.855787 <6>[ 0.029347] LSM: Security Framework initializing
10419 08:07:19.862587 <6>[ 0.034247] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 08:07:19.872576 <6>[ 0.042061] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 08:07:19.879125 <6>[ 0.051451] cblist_init_generic: Setting adjustable number of callback queues.
10422 08:07:19.885734 <6>[ 0.058897] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 08:07:19.895946 <6>[ 0.065234] cblist_init_generic: Setting adjustable number of callback queues.
10424 08:07:19.899281 <6>[ 0.072662] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 08:07:19.905993 <6>[ 0.079062] rcu: Hierarchical SRCU implementation.
10426 08:07:19.912773 <6>[ 0.084078] rcu: Max phase no-delay instances is 1000.
10427 08:07:19.919225 <6>[ 0.091113] EFI services will not be available.
10428 08:07:19.922403 <6>[ 0.096099] smp: Bringing up secondary CPUs ...
10429 08:07:19.930676 <6>[ 0.101139] Detected VIPT I-cache on CPU1
10430 08:07:19.937041 <6>[ 0.101197] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10431 08:07:19.943841 <6>[ 0.101221] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10432 08:07:19.947110 <6>[ 0.101536] Detected VIPT I-cache on CPU2
10433 08:07:19.953506 <6>[ 0.101582] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10434 08:07:19.959990 <6>[ 0.101599] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10435 08:07:19.966945 <6>[ 0.101860] Detected VIPT I-cache on CPU3
10436 08:07:19.973399 <6>[ 0.101907] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10437 08:07:19.980172 <6>[ 0.101921] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10438 08:07:19.983764 <6>[ 0.102224] CPU features: detected: Spectre-v4
10439 08:07:19.990248 <6>[ 0.102230] CPU features: detected: Spectre-BHB
10440 08:07:19.993301 <6>[ 0.102236] Detected PIPT I-cache on CPU4
10441 08:07:20.000376 <6>[ 0.102294] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10442 08:07:20.007064 <6>[ 0.102311] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10443 08:07:20.013614 <6>[ 0.102603] Detected PIPT I-cache on CPU5
10444 08:07:20.020486 <6>[ 0.102668] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10445 08:07:20.027299 <6>[ 0.102684] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10446 08:07:20.030689 <6>[ 0.102962] Detected PIPT I-cache on CPU6
10447 08:07:20.037265 <6>[ 0.103028] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10448 08:07:20.043749 <6>[ 0.103044] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10449 08:07:20.046894 <6>[ 0.103342] Detected PIPT I-cache on CPU7
10450 08:07:20.057193 <6>[ 0.103409] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10451 08:07:20.063500 <6>[ 0.103425] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10452 08:07:20.066822 <6>[ 0.103473] smp: Brought up 1 node, 8 CPUs
10453 08:07:20.069955 <6>[ 0.244847] SMP: Total of 8 processors activated.
10454 08:07:20.076617 <6>[ 0.249798] CPU features: detected: 32-bit EL0 Support
10455 08:07:20.086681 <6>[ 0.255193] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10456 08:07:20.093292 <6>[ 0.263994] CPU features: detected: Common not Private translations
10457 08:07:20.096839 <6>[ 0.270510] CPU features: detected: CRC32 instructions
10458 08:07:20.103646 <6>[ 0.275894] CPU features: detected: RCpc load-acquire (LDAPR)
10459 08:07:20.109565 <6>[ 0.281890] CPU features: detected: LSE atomic instructions
10460 08:07:20.116628 <6>[ 0.287672] CPU features: detected: Privileged Access Never
10461 08:07:20.120129 <6>[ 0.293452] CPU features: detected: RAS Extension Support
10462 08:07:20.126480 <6>[ 0.299095] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10463 08:07:20.133527 <6>[ 0.306314] CPU: All CPU(s) started at EL2
10464 08:07:20.139806 <6>[ 0.310631] alternatives: applying system-wide alternatives
10465 08:07:20.148366 <6>[ 0.321320] devtmpfs: initialized
10466 08:07:20.160787 <6>[ 0.330418] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10467 08:07:20.170472 <6>[ 0.340383] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10468 08:07:20.176916 <6>[ 0.348616] pinctrl core: initialized pinctrl subsystem
10469 08:07:20.180161 <6>[ 0.355407] DMI not present or invalid.
10470 08:07:20.187351 <6>[ 0.359819] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10471 08:07:20.197348 <6>[ 0.366698] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10472 08:07:20.203598 <6>[ 0.374283] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10473 08:07:20.213845 <6>[ 0.382509] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10474 08:07:20.216893 <6>[ 0.390751] audit: initializing netlink subsys (disabled)
10475 08:07:20.226870 <5>[ 0.396447] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10476 08:07:20.233709 <6>[ 0.397212] thermal_sys: Registered thermal governor 'step_wise'
10477 08:07:20.240217 <6>[ 0.404413] thermal_sys: Registered thermal governor 'power_allocator'
10478 08:07:20.243624 <6>[ 0.410669] cpuidle: using governor menu
10479 08:07:20.250788 <6>[ 0.421632] NET: Registered PF_QIPCRTR protocol family
10480 08:07:20.256575 <6>[ 0.427108] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10481 08:07:20.259843 <6>[ 0.434212] ASID allocator initialised with 32768 entries
10482 08:07:20.268045 <6>[ 0.440847] Serial: AMBA PL011 UART driver
10483 08:07:20.277012 <4>[ 0.449958] Trying to register duplicate clock ID: 134
10484 08:07:20.333652 <6>[ 0.510170] KASLR enabled
10485 08:07:20.348226 <6>[ 0.517917] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10486 08:07:20.354928 <6>[ 0.524931] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10487 08:07:20.361545 <6>[ 0.531419] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10488 08:07:20.368175 <6>[ 0.538425] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10489 08:07:20.374687 <6>[ 0.544914] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10490 08:07:20.381502 <6>[ 0.551916] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10491 08:07:20.388108 <6>[ 0.558404] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10492 08:07:20.394892 <6>[ 0.565408] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10493 08:07:20.397757 <6>[ 0.572886] ACPI: Interpreter disabled.
10494 08:07:20.406251 <6>[ 0.579396] iommu: Default domain type: Translated
10495 08:07:20.412852 <6>[ 0.584511] iommu: DMA domain TLB invalidation policy: strict mode
10496 08:07:20.416226 <5>[ 0.591179] SCSI subsystem initialized
10497 08:07:20.422777 <6>[ 0.595425] usbcore: registered new interface driver usbfs
10498 08:07:20.429661 <6>[ 0.601155] usbcore: registered new interface driver hub
10499 08:07:20.432551 <6>[ 0.606706] usbcore: registered new device driver usb
10500 08:07:20.440035 <6>[ 0.612868] pps_core: LinuxPPS API ver. 1 registered
10501 08:07:20.449615 <6>[ 0.618064] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10502 08:07:20.453282 <6>[ 0.627409] PTP clock support registered
10503 08:07:20.456373 <6>[ 0.631652] EDAC MC: Ver: 3.0.0
10504 08:07:20.463873 <6>[ 0.636901] FPGA manager framework
10505 08:07:20.470264 <6>[ 0.640576] Advanced Linux Sound Architecture Driver Initialized.
10506 08:07:20.473594 <6>[ 0.647351] vgaarb: loaded
10507 08:07:20.480535 <6>[ 0.650522] clocksource: Switched to clocksource arch_sys_counter
10508 08:07:20.483569 <5>[ 0.656971] VFS: Disk quotas dquot_6.6.0
10509 08:07:20.489881 <6>[ 0.661158] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10510 08:07:20.493473 <6>[ 0.668352] pnp: PnP ACPI: disabled
10511 08:07:20.501773 <6>[ 0.675057] NET: Registered PF_INET protocol family
10512 08:07:20.511620 <6>[ 0.680653] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10513 08:07:20.523061 <6>[ 0.692979] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10514 08:07:20.533301 <6>[ 0.701795] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10515 08:07:20.539862 <6>[ 0.709765] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10516 08:07:20.546534 <6>[ 0.718466] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10517 08:07:20.558249 <6>[ 0.728225] TCP: Hash tables configured (established 65536 bind 65536)
10518 08:07:20.565209 <6>[ 0.735092] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 08:07:20.571725 <6>[ 0.742294] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 08:07:20.578364 <6>[ 0.749995] NET: Registered PF_UNIX/PF_LOCAL protocol family
10521 08:07:20.585244 <6>[ 0.756144] RPC: Registered named UNIX socket transport module.
10522 08:07:20.588473 <6>[ 0.762298] RPC: Registered udp transport module.
10523 08:07:20.595080 <6>[ 0.767231] RPC: Registered tcp transport module.
10524 08:07:20.601664 <6>[ 0.772163] RPC: Registered tcp NFSv4.1 backchannel transport module.
10525 08:07:20.604815 <6>[ 0.778827] PCI: CLS 0 bytes, default 64
10526 08:07:20.608405 <6>[ 0.783170] Unpacking initramfs...
10527 08:07:20.632727 <6>[ 0.802627] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10528 08:07:20.642853 <6>[ 0.811283] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10529 08:07:20.646341 <6>[ 0.820138] kvm [1]: IPA Size Limit: 40 bits
10530 08:07:20.652867 <6>[ 0.824664] kvm [1]: GICv3: no GICV resource entry
10531 08:07:20.656184 <6>[ 0.829687] kvm [1]: disabling GICv2 emulation
10532 08:07:20.662520 <6>[ 0.834370] kvm [1]: GIC system register CPU interface enabled
10533 08:07:20.665933 <6>[ 0.840526] kvm [1]: vgic interrupt IRQ18
10534 08:07:20.673040 <6>[ 0.844888] kvm [1]: VHE mode initialized successfully
10535 08:07:20.679515 <5>[ 0.851362] Initialise system trusted keyrings
10536 08:07:20.686186 <6>[ 0.856213] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10537 08:07:20.693671 <6>[ 0.866202] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10538 08:07:20.699786 <5>[ 0.872554] NFS: Registering the id_resolver key type
10539 08:07:20.702686 <5>[ 0.877856] Key type id_resolver registered
10540 08:07:20.709629 <5>[ 0.882271] Key type id_legacy registered
10541 08:07:20.716421 <6>[ 0.886546] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10542 08:07:20.723191 <6>[ 0.893470] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10543 08:07:20.729549 <6>[ 0.901197] 9p: Installing v9fs 9p2000 file system support
10544 08:07:20.765782 <5>[ 0.939225] Key type asymmetric registered
10545 08:07:20.769306 <5>[ 0.943555] Asymmetric key parser 'x509' registered
10546 08:07:20.779551 <6>[ 0.948720] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10547 08:07:20.782781 <6>[ 0.956335] io scheduler mq-deadline registered
10548 08:07:20.785792 <6>[ 0.961120] io scheduler kyber registered
10549 08:07:20.805481 <6>[ 0.978628] EINJ: ACPI disabled.
10550 08:07:20.838436 <4>[ 1.004927] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 08:07:20.848188 <4>[ 1.015555] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 08:07:20.862915 <6>[ 1.036549] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10553 08:07:20.871423 <6>[ 1.044502] printk: console [ttyS0] disabled
10554 08:07:20.899482 <6>[ 1.069155] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10555 08:07:20.906623 <6>[ 1.078644] printk: console [ttyS0] enabled
10556 08:07:20.909242 <6>[ 1.078644] printk: console [ttyS0] enabled
10557 08:07:20.915790 <6>[ 1.087541] printk: bootconsole [mtk8250] disabled
10558 08:07:20.919114 <6>[ 1.087541] printk: bootconsole [mtk8250] disabled
10559 08:07:20.925798 <6>[ 1.098864] SuperH (H)SCI(F) driver initialized
10560 08:07:20.929092 <6>[ 1.104161] msm_serial: driver initialized
10561 08:07:20.943100 <6>[ 1.113250] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10562 08:07:20.953365 <6>[ 1.121803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10563 08:07:20.959935 <6>[ 1.130346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10564 08:07:20.969581 <6>[ 1.138976] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10565 08:07:20.976463 <6>[ 1.147683] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10566 08:07:20.986405 <6>[ 1.156407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10567 08:07:20.996496 <6>[ 1.164949] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10568 08:07:21.003111 <6>[ 1.173745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10569 08:07:21.013226 <6>[ 1.182289] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10570 08:07:21.024792 <6>[ 1.198246] loop: module loaded
10571 08:07:21.031522 <6>[ 1.204332] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10572 08:07:21.054289 <4>[ 1.227711] mtk-pmic-keys: Failed to locate of_node [id: -1]
10573 08:07:21.060883 <6>[ 1.234604] megasas: 07.719.03.00-rc1
10574 08:07:21.070968 <6>[ 1.244273] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10575 08:07:21.080574 <6>[ 1.253894] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10576 08:07:21.097653 <6>[ 1.270647] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10577 08:07:21.153796 <6>[ 1.320749] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10578 08:07:22.211161 <6>[ 2.384146] Freeing initrd memory: 38432K
10579 08:07:22.221052 <6>[ 2.394397] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10580 08:07:22.232156 <6>[ 2.405604] tun: Universal TUN/TAP device driver, 1.6
10581 08:07:22.235707 <6>[ 2.411719] thunder_xcv, ver 1.0
10582 08:07:22.238778 <6>[ 2.415227] thunder_bgx, ver 1.0
10583 08:07:22.241846 <6>[ 2.418721] nicpf, ver 1.0
10584 08:07:22.252555 <6>[ 2.422782] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10585 08:07:22.256238 <6>[ 2.430257] hns3: Copyright (c) 2017 Huawei Corporation.
10586 08:07:22.262385 <6>[ 2.435845] hclge is initializing
10587 08:07:22.265736 <6>[ 2.439426] e1000: Intel(R) PRO/1000 Network Driver
10588 08:07:22.272314 <6>[ 2.444555] e1000: Copyright (c) 1999-2006 Intel Corporation.
10589 08:07:22.275594 <6>[ 2.450569] e1000e: Intel(R) PRO/1000 Network Driver
10590 08:07:22.282332 <6>[ 2.455785] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10591 08:07:22.288914 <6>[ 2.461974] igb: Intel(R) Gigabit Ethernet Network Driver
10592 08:07:22.295946 <6>[ 2.467625] igb: Copyright (c) 2007-2014 Intel Corporation.
10593 08:07:22.302626 <6>[ 2.473461] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10594 08:07:22.308959 <6>[ 2.479979] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10595 08:07:22.312382 <6>[ 2.486450] sky2: driver version 1.30
10596 08:07:22.319077 <6>[ 2.491497] VFIO - User Level meta-driver version: 0.3
10597 08:07:22.326650 <6>[ 2.499870] usbcore: registered new interface driver usb-storage
10598 08:07:22.333512 <6>[ 2.506315] usbcore: registered new device driver onboard-usb-hub
10599 08:07:22.341874 <6>[ 2.515476] mt6397-rtc mt6359-rtc: registered as rtc0
10600 08:07:22.351887 <6>[ 2.520943] mt6397-rtc mt6359-rtc: setting system clock to 2023-09-21T08:06:59 UTC (1695283619)
10601 08:07:22.355118 <6>[ 2.530539] i2c_dev: i2c /dev entries driver
10602 08:07:22.372386 <6>[ 2.542502] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10603 08:07:22.392070 <6>[ 2.565501] cpu cpu0: EM: created perf domain
10604 08:07:22.395400 <6>[ 2.570441] cpu cpu4: EM: created perf domain
10605 08:07:22.402673 <6>[ 2.576083] sdhci: Secure Digital Host Controller Interface driver
10606 08:07:22.409264 <6>[ 2.582516] sdhci: Copyright(c) Pierre Ossman
10607 08:07:22.416131 <6>[ 2.587478] Synopsys Designware Multimedia Card Interface Driver
10608 08:07:22.423048 <6>[ 2.594116] sdhci-pltfm: SDHCI platform and OF driver helper
10609 08:07:22.425721 <6>[ 2.594154] mmc0: CQHCI version 5.10
10610 08:07:22.432582 <6>[ 2.604465] ledtrig-cpu: registered to indicate activity on CPUs
10611 08:07:22.439216 <6>[ 2.611614] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10612 08:07:22.445777 <6>[ 2.618685] usbcore: registered new interface driver usbhid
10613 08:07:22.449234 <6>[ 2.624507] usbhid: USB HID core driver
10614 08:07:22.458868 <6>[ 2.628702] spi_master spi0: will run message pump with realtime priority
10615 08:07:22.499855 <6>[ 2.666863] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10616 08:07:22.519487 <6>[ 2.682757] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10617 08:07:22.523163 <6>[ 2.697560] mmc0: Command Queue Engine enabled
10618 08:07:22.529528 <6>[ 2.702320] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 08:07:22.536589 <6>[ 2.709040] cros-ec-spi spi0.0: Chrome EC device registered
10620 08:07:22.539802 <6>[ 2.709606] mmcblk0: mmc0:0001 DA4128 116 GiB
10621 08:07:22.552421 <6>[ 2.725705] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10622 08:07:22.559718 <6>[ 2.733025] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10623 08:07:22.566193 <6>[ 2.738967] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10624 08:07:22.572727 <6>[ 2.745068] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10625 08:07:22.587751 <6>[ 2.758111] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10626 08:07:22.595165 <6>[ 2.768762] NET: Registered PF_PACKET protocol family
10627 08:07:22.598381 <6>[ 2.774158] 9pnet: Installing 9P2000 support
10628 08:07:22.605227 <5>[ 2.778720] Key type dns_resolver registered
10629 08:07:22.609104 <6>[ 2.783716] registered taskstats version 1
10630 08:07:22.615619 <5>[ 2.788105] Loading compiled-in X.509 certificates
10631 08:07:22.645406 <4>[ 2.812158] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 08:07:22.655450 <4>[ 2.822925] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 08:07:22.661599 <3>[ 2.833467] debugfs: File 'uA_load' in directory '/' already present!
10634 08:07:22.668615 <3>[ 2.840167] debugfs: File 'min_uV' in directory '/' already present!
10635 08:07:22.675196 <3>[ 2.846775] debugfs: File 'max_uV' in directory '/' already present!
10636 08:07:22.681806 <3>[ 2.853381] debugfs: File 'constraint_flags' in directory '/' already present!
10637 08:07:22.693099 <3>[ 2.863220] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10638 08:07:22.702026 <6>[ 2.875637] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10639 08:07:22.708761 <6>[ 2.882330] xhci-mtk 11200000.usb: xHCI Host Controller
10640 08:07:22.715369 <6>[ 2.887820] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10641 08:07:22.725739 <6>[ 2.895662] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10642 08:07:22.732192 <6>[ 2.905089] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10643 08:07:22.739012 <6>[ 2.911149] xhci-mtk 11200000.usb: xHCI Host Controller
10644 08:07:22.745602 <6>[ 2.916623] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10645 08:07:22.752133 <6>[ 2.924267] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10646 08:07:22.758778 <6>[ 2.931923] hub 1-0:1.0: USB hub found
10647 08:07:22.762031 <6>[ 2.935935] hub 1-0:1.0: 1 port detected
10648 08:07:22.768678 <6>[ 2.940191] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10649 08:07:22.775622 <6>[ 2.948765] hub 2-0:1.0: USB hub found
10650 08:07:22.778243 <6>[ 2.952769] hub 2-0:1.0: 1 port detected
10651 08:07:22.787090 <6>[ 2.960598] mtk-msdc 11f70000.mmc: Got CD GPIO
10652 08:07:22.797713 <6>[ 2.967821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10653 08:07:22.804155 <6>[ 2.975840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10654 08:07:22.813990 <4>[ 2.983728] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10655 08:07:22.824327 <6>[ 2.993253] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10656 08:07:22.830835 <6>[ 3.001331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10657 08:07:22.837385 <6>[ 3.009463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10658 08:07:22.847601 <6>[ 3.017386] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10659 08:07:22.853770 <6>[ 3.025208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10660 08:07:22.863772 <6>[ 3.033025] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10661 08:07:22.873784 <6>[ 3.043567] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10662 08:07:22.880724 <6>[ 3.051954] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10663 08:07:22.890682 <6>[ 3.060292] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10664 08:07:22.897098 <6>[ 3.068631] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10665 08:07:22.907031 <6>[ 3.076969] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10666 08:07:22.913478 <6>[ 3.085312] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10667 08:07:22.923318 <6>[ 3.093650] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10668 08:07:22.930031 <6>[ 3.101988] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10669 08:07:22.940359 <6>[ 3.110326] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10670 08:07:22.949891 <6>[ 3.118664] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10671 08:07:22.956720 <6>[ 3.127002] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10672 08:07:22.966202 <6>[ 3.135342] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10673 08:07:22.973248 <6>[ 3.143682] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10674 08:07:22.982967 <6>[ 3.152034] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10675 08:07:22.989590 <6>[ 3.160373] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10676 08:07:22.996282 <6>[ 3.169105] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10677 08:07:23.003175 <6>[ 3.176227] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10678 08:07:23.009406 <6>[ 3.183008] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10679 08:07:23.016281 <6>[ 3.189792] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10680 08:07:23.026270 <6>[ 3.196751] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10681 08:07:23.033131 <6>[ 3.203600] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10682 08:07:23.043090 <6>[ 3.212731] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10683 08:07:23.053432 <6>[ 3.221850] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10684 08:07:23.062969 <6>[ 3.231146] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10685 08:07:23.073121 <6>[ 3.240613] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10686 08:07:23.079862 <6>[ 3.250102] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10687 08:07:23.089342 <6>[ 3.259223] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10688 08:07:23.099397 <6>[ 3.268691] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10689 08:07:23.109371 <6>[ 3.277811] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10690 08:07:23.119021 <6>[ 3.287106] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10691 08:07:23.128880 <6>[ 3.297266] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10692 08:07:23.138911 <6>[ 3.309252] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10693 08:07:23.168614 <6>[ 3.339068] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10694 08:07:23.197093 <6>[ 3.370775] hub 2-1:1.0: USB hub found
10695 08:07:23.200623 <6>[ 3.375264] hub 2-1:1.0: 3 ports detected
10696 08:07:23.320582 <6>[ 3.490823] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10697 08:07:23.475570 <6>[ 3.649341] hub 1-1:1.0: USB hub found
10698 08:07:23.478948 <6>[ 3.653752] hub 1-1:1.0: 4 ports detected
10699 08:07:23.553001 <6>[ 3.723067] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10700 08:07:23.800240 <6>[ 3.970931] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10701 08:07:23.932534 <6>[ 4.105914] hub 1-1.4:1.0: USB hub found
10702 08:07:23.935887 <6>[ 4.110459] hub 1-1.4:1.0: 2 ports detected
10703 08:07:24.232438 <6>[ 4.402784] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 08:07:24.424648 <6>[ 4.594823] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 08:07:35.421546 <6>[ 15.599833] ALSA device list:
10706 08:07:35.427834 <6>[ 15.603123] No soundcards found.
10707 08:07:35.436128 <6>[ 15.611214] Freeing unused kernel memory: 8448K
10708 08:07:35.439520 <6>[ 15.616195] Run /init as init process
10709 08:07:35.489575 <6>[ 15.664592] NET: Registered PF_INET6 protocol family
10710 08:07:35.496541 <6>[ 15.671132] Segment Routing with IPv6
10711 08:07:35.499658 <6>[ 15.675087] In-situ OAM (IOAM) with IPv6
10712 08:07:35.535987 <30>[ 15.691292] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10713 08:07:35.539332 <30>[ 15.715142] systemd[1]: Detected architecture arm64.
10714 08:07:35.542542
10715 08:07:35.546050 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10716 08:07:35.546642
10717 08:07:35.563878 <30>[ 15.738776] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10718 08:07:35.717045 <30>[ 15.888685] systemd[1]: Queued start job for default target Graphical Interface.
10719 08:07:35.760867 <30>[ 15.935750] systemd[1]: Created slice system-getty.slice.
10720 08:07:35.767525 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10721 08:07:35.785231 <30>[ 15.960000] systemd[1]: Created slice system-modprobe.slice.
10722 08:07:35.791968 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10723 08:07:35.809405 <30>[ 15.984150] systemd[1]: Created slice system-serial\x2dgetty.slice.
10724 08:07:35.819641 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10725 08:07:35.832397 <30>[ 16.007279] systemd[1]: Created slice User and Session Slice.
10726 08:07:35.839167 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10727 08:07:35.860274 <30>[ 16.031515] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10728 08:07:35.866904 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10729 08:07:35.888063 <30>[ 16.059519] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10730 08:07:35.894538 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10731 08:07:35.919087 <30>[ 16.087357] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10732 08:07:35.925755 <30>[ 16.099636] systemd[1]: Reached target Local Encrypted Volumes.
10733 08:07:35.932184 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10734 08:07:35.948211 <30>[ 16.123366] systemd[1]: Reached target Paths.
10735 08:07:35.951351 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10736 08:07:35.967878 <30>[ 16.142847] systemd[1]: Reached target Remote File Systems.
10737 08:07:35.974435 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10738 08:07:35.992554 <30>[ 16.167202] systemd[1]: Reached target Slices.
10739 08:07:35.999116 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10740 08:07:36.011997 <30>[ 16.186868] systemd[1]: Reached target Swap.
10741 08:07:36.015333 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10742 08:07:36.035928 <30>[ 16.207361] systemd[1]: Listening on initctl Compatibility Named Pipe.
10743 08:07:36.042188 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10744 08:07:36.056893 <30>[ 16.231769] systemd[1]: Listening on Journal Audit Socket.
10745 08:07:36.063264 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10746 08:07:36.081248 <30>[ 16.256053] systemd[1]: Listening on Journal Socket (/dev/log).
10747 08:07:36.087938 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10748 08:07:36.104459 <30>[ 16.279449] systemd[1]: Listening on Journal Socket.
10749 08:07:36.110848 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10750 08:07:36.128020 <30>[ 16.299612] systemd[1]: Listening on Network Service Netlink Socket.
10751 08:07:36.134561 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10752 08:07:36.149279 <30>[ 16.324094] systemd[1]: Listening on udev Control Socket.
10753 08:07:36.155659 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10754 08:07:36.173312 <30>[ 16.347992] systemd[1]: Listening on udev Kernel Socket.
10755 08:07:36.179642 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10756 08:07:36.232019 <30>[ 16.407042] systemd[1]: Mounting Huge Pages File System...
10757 08:07:36.238627 Mounting [0;1;39mHuge Pages File System[0m...
10758 08:07:36.256348 <30>[ 16.431205] systemd[1]: Mounting POSIX Message Queue File System...
10759 08:07:36.263308 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10760 08:07:36.291994 <30>[ 16.466874] systemd[1]: Mounting Kernel Debug File System...
10761 08:07:36.298743 Mounting [0;1;39mKernel Debug File System[0m...
10762 08:07:36.315277 <30>[ 16.487275] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10763 08:07:36.328974 <30>[ 16.500763] systemd[1]: Starting Create list of static device nodes for the current kernel...
10764 08:07:36.335852 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10765 08:07:36.355865 <30>[ 16.530805] systemd[1]: Starting Load Kernel Module configfs...
10766 08:07:36.362552 Starting [0;1;39mLoad Kernel Module configfs[0m...
10767 08:07:36.379980 <30>[ 16.554978] systemd[1]: Starting Load Kernel Module drm...
10768 08:07:36.386512 Starting [0;1;39mLoad Kernel Module drm[0m...
10769 08:07:36.402771 <30>[ 16.574892] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10770 08:07:36.413514 <30>[ 16.588563] systemd[1]: Starting Journal Service...
10771 08:07:36.416679 Starting [0;1;39mJournal Service[0m...
10772 08:07:36.434726 <30>[ 16.609633] systemd[1]: Starting Load Kernel Modules...
10773 08:07:36.441578 Starting [0;1;39mLoad Kernel Modules[0m...
10774 08:07:36.462214 <30>[ 16.634057] systemd[1]: Starting Remount Root and Kernel File Systems...
10775 08:07:36.469077 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10776 08:07:36.487338 <30>[ 16.662307] systemd[1]: Starting Coldplug All udev Devices...
10777 08:07:36.493973 Starting [0;1;39mColdplug All udev Devices[0m...
10778 08:07:36.512915 <30>[ 16.687646] systemd[1]: Started Journal Service.
10779 08:07:36.519127 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10780 08:07:36.534220 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10781 08:07:36.553273 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10782 08:07:36.569167 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10783 08:07:36.588681 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10784 08:07:36.605767 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10785 08:07:36.622795 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10786 08:07:36.640953 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10787 08:07:36.661382 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10788 08:07:36.676112 See 'systemctl status systemd-remount-fs.service' for details.
10789 08:07:36.728755 Mounting [0;1;39mKernel Configuration File System[0m...
10790 08:07:36.749682 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10791 08:07:36.763085 <46>[ 16.935067] systemd-journald[175]: Received client request to flush runtime journal.
10792 08:07:36.774629 Starting [0;1;39mLoad/Save Random Seed[0m...
10793 08:07:36.792324 Starting [0;1;39mApply Kernel Variables[0m...
10794 08:07:36.810951 Starting [0;1;39mCreate System Users[0m...
10795 08:07:36.834051 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10796 08:07:36.853137 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10797 08:07:36.873223 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10798 08:07:36.889818 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10799 08:07:36.898148 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10800 08:07:36.918174 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10801 08:07:36.964282 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10802 08:07:36.988521 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10803 08:07:37.000178 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10804 08:07:37.019814 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10805 08:07:37.056166 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10806 08:07:37.084217 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10807 08:07:37.106605 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10808 08:07:37.128120 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10809 08:07:37.182654 Starting [0;1;39mNetwork Service[0m...
10810 08:07:37.213149 Starting [0;1;39mNetwork Time Synchronization[0m...
10811 08:07:37.233245 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10812 08:07:37.250954 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10813 08:07:37.276629 <6>[ 17.448257] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10814 08:07:37.282863 <6>[ 17.456052] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10815 08:07:37.292664 <6>[ 17.464825] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10816 08:07:37.299522 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10817 08:07:37.318328 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10818 08:07:37.333909 <6>[ 17.505591] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10819 08:07:37.344171 <3>[ 17.515533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 08:07:37.353624 [[0;32m OK [0m] Finished [0<3>[ 17.525782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 08:07:37.363610 ;1;39mUpdate UTM<4>[ 17.529529] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10822 08:07:37.370568 <6>[ 17.534182] remoteproc remoteproc0: scp is available
10823 08:07:37.377299 P about System B<6>[ 17.534243] remoteproc remoteproc0: powering up scp
10824 08:07:37.383925 <6>[ 17.534249] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10825 08:07:37.390072 <6>[ 17.534266] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10826 08:07:37.399846 oot/Shutdown[0m<3>[ 17.535249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 08:07:37.400541 .
10828 08:07:37.406637 <3>[ 17.579324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 08:07:37.413366 <4>[ 17.583189] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10830 08:07:37.423155 <3>[ 17.587912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 08:07:37.429985 <6>[ 17.604226] usbcore: registered new interface driver r8152
10832 08:07:37.436861 <3>[ 17.606633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 08:07:37.443034 <6>[ 17.615656] mc: Linux media interface: v0.10
10834 08:07:37.449831 <6>[ 17.617061] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10835 08:07:37.456440 <6>[ 17.617070] pci_bus 0000:00: root bus resource [bus 00-ff]
10836 08:07:37.463235 <6>[ 17.617083] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10837 08:07:37.473253 <6>[ 17.617089] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10838 08:07:37.479782 <6>[ 17.617124] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10839 08:07:37.486507 <6>[ 17.617144] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10840 08:07:37.493083 <6>[ 17.617221] pci 0000:00:00.0: supports D1 D2
10841 08:07:37.499565 <6>[ 17.617225] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10842 08:07:37.505964 <3>[ 17.618203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 08:07:37.512824 <6>[ 17.631357] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10844 08:07:37.523392 <6>[ 17.634158] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10845 08:07:37.529474 <3>[ 17.635234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 08:07:37.539238 <3>[ 17.635583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10847 08:07:37.545894 <6>[ 17.636942] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10848 08:07:37.552787 <6>[ 17.636971] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10849 08:07:37.559072 <6>[ 17.636989] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10850 08:07:37.565869 <6>[ 17.637003] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10851 08:07:37.572641 <6>[ 17.637100] videodev: Linux video capture interface: v2.00
10852 08:07:37.578968 <6>[ 17.637116] pci 0000:01:00.0: supports D1 D2
10853 08:07:37.586240 <6>[ 17.637118] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10854 08:07:37.592809 <6>[ 17.650914] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10855 08:07:37.599126 <3>[ 17.653328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 08:07:37.605726 <6>[ 17.660381] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10857 08:07:37.616127 <6>[ 17.660861] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10858 08:07:37.622784 <6>[ 17.660880] remoteproc remoteproc0: remote processor scp is now up
10859 08:07:37.629558 <6>[ 17.661298] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10860 08:07:37.636379 <6>[ 17.661305] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10861 08:07:37.645851 <6>[ 17.661315] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10862 08:07:37.652772 <6>[ 17.661328] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10863 08:07:37.662675 <6>[ 17.661341] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10864 08:07:37.666360 <6>[ 17.661353] pci 0000:00:00.0: PCI bridge to [bus 01]
10865 08:07:37.675995 <6>[ 17.661358] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10866 08:07:37.682409 <6>[ 17.661519] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10867 08:07:37.685614 <6>[ 17.662200] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10868 08:07:37.692645 <6>[ 17.662433] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10869 08:07:37.702805 <3>[ 17.666391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 08:07:37.709195 <3>[ 17.666407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 08:07:37.715576 <3>[ 17.666565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 08:07:37.725635 <3>[ 17.666580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 08:07:37.732424 <3>[ 17.666582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 08:07:37.742864 <3>[ 17.666603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 08:07:37.750047 <3>[ 17.666609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 08:07:37.757276 <3>[ 17.666649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 08:07:37.763482 <6>[ 17.732429] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10878 08:07:37.773799 <6>[ 17.743011] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10879 08:07:37.783492 <4>[ 17.748394] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10880 08:07:37.786916 <4>[ 17.748394] Fallback method does not support PEC.
10881 08:07:37.797227 <6>[ 17.748873] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10882 08:07:37.807252 <6>[ 17.749142] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10883 08:07:37.817867 <4>[ 17.774125] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10884 08:07:37.820763 <6>[ 17.796018] usbcore: registered new interface driver cdc_ether
10885 08:07:37.831366 <4>[ 17.801643] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10886 08:07:37.834600 <6>[ 17.811277] Bluetooth: Core ver 2.22
10887 08:07:37.841150 <6>[ 17.812481] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10888 08:07:37.851164 <5>[ 17.812573] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10889 08:07:37.857748 <6>[ 17.817041] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10890 08:07:37.867703 <3>[ 17.817576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 08:07:37.871331 <6>[ 17.818352] usbcore: registered new interface driver r8153_ecm
10892 08:07:37.885229 <6>[ 17.820039] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10893 08:07:37.891802 <6>[ 17.821007] usbcore: registered new interface driver uvcvideo
10894 08:07:37.899184 <6>[ 17.821587] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10895 08:07:37.905347 <6>[ 17.826599] NET: Registered PF_BLUETOOTH protocol family
10896 08:07:37.911814 <5>[ 17.828939] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10897 08:07:37.918893 <4>[ 17.829066] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10898 08:07:37.925231 <6>[ 17.829077] cfg80211: failed to load regulatory.db
10899 08:07:37.931961 <6>[ 17.848360] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10900 08:07:37.938737 <6>[ 17.855066] Bluetooth: HCI device and connection manager initialized
10901 08:07:37.941942 <6>[ 17.878902] r8152 2-1.3:1.0 eth0: v1.12.13
10902 08:07:37.948520 <6>[ 17.881542] Bluetooth: HCI socket layer initialized
10903 08:07:37.956041 <6>[ 17.898323] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10904 08:07:37.959490 <6>[ 17.905795] Bluetooth: L2CAP socket layer initialized
10905 08:07:37.969379 <3>[ 17.927986] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 08:07:37.976046 <3>[ 17.928747] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10907 08:07:37.982856 <6>[ 17.930222] Bluetooth: SCO socket layer initialized
10908 08:07:37.989671 <6>[ 17.933576] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10909 08:07:37.996270 <6>[ 17.933686] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10910 08:07:38.002873 <3>[ 17.936248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 08:07:38.009172 <6>[ 17.950781] mt7921e 0000:01:00.0: ASIC revision: 79610010
10912 08:07:38.019302 <3>[ 18.016078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 08:07:38.025800 <6>[ 18.023308] usbcore: registered new interface driver btusb
10914 08:07:38.035557 <4>[ 18.031274] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10915 08:07:38.042297 <3>[ 18.037836] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10916 08:07:38.048814 <3>[ 18.046642] Bluetooth: hci0: Failed to load firmware file (-2)
10917 08:07:38.058885 <3>[ 18.058668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 08:07:38.062113 <3>[ 18.065414] Bluetooth: hci0: Failed to set up firmware (-2)
10919 08:07:38.072073 <3>[ 18.093201] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 08:07:38.081871 <4>[ 18.100789] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10921 08:07:38.095144 <4>[ 18.118369] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10922 08:07:38.102057 <3>[ 18.136616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 08:07:38.112151 <4>[ 18.262997] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10924 08:07:38.126341 [[0;32m OK [<3>[ 18.295792] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 08:07:38.129575 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10926 08:07:38.148096 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10927 08:07:38.167711 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10928 08:07:38.232574 Starting [0;1;39mLoad/Save Screen …o<4>[ 18.401514] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10929 08:07:38.235886 f leds:white:kbd_backlight[0m...
10930 08:07:38.262618 Starting [0;1;39mNetwork Name Resolution[0m...
10931 08:07:38.286175 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10932 08:07:38.320367 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10933 08:07:38.353098 <4>[ 18.521186] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 08:07:38.471575 <4>[ 18.640416] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10935 08:07:38.478863 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10936 08:07:38.495975 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10937 08:07:38.515275 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10938 08:07:38.531721 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10939 08:07:38.551584 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10940 08:07:38.567035 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10941 08:07:38.589652 [[0;32m OK [0m] Reached targ<4>[ 18.756880] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 08:07:38.590220 et [0;1;39mTimers[0m.
10943 08:07:38.612297 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10944 08:07:38.623711 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10945 08:07:38.639804 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10946 08:07:38.660145 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10947 08:07:38.708120 <4>[ 18.876999] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10948 08:07:38.728731 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10949 08:07:38.758493 Starting [0;1;39mUser Login Management[0m...
10950 08:07:38.776385 Starting [0;1;39mPermit User Sessions[0m...
10951 08:07:38.796145 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10952 08:07:38.834183 <4>[ 19.002499] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10953 08:07:38.864986 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10954 08:07:38.885196 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10955 08:07:38.899946 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10956 08:07:38.919165 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10957 08:07:38.953915 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch St<4>[ 19.121297] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 08:07:38.954505 atus[0m.
10959 08:07:38.970835 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10960 08:07:38.979460 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10961 08:07:38.996679 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10962 08:07:39.057440 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10963 08:07:39.073450 <4>[ 19.242290] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10964 08:07:39.100682 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10965 08:07:39.145873
10966 08:07:39.146425
10967 08:07:39.149197 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10968 08:07:39.149754
10969 08:07:39.152439 debian-bullseye-arm64 login: root (automatic login)
10970 08:07:39.153028
10971 08:07:39.153398
10972 08:07:39.184793 Linux debian-bullseye-arm64 6.1.<3>[ 19.359816] mt7921e 0000:01:00.0: hardware init failed
10973 08:07:39.191695 54-cip6 #1 SMP PREEMPT Thu Sep 21 07:49:54 UTC 2023 aarch64
10974 08:07:39.192267
10975 08:07:39.198207 The programs included with the Debian GNU/Linux system are free software;
10976 08:07:39.201508 the exact distribution terms for each program are described in the
10977 08:07:39.207893 individual files in /usr/share/doc/*/copyright.
10978 08:07:39.208448
10979 08:07:39.214322 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10980 08:07:39.214870 permitted by applicable law.
10981 08:07:39.215964 Matched prompt #10: / #
10983 08:07:39.217065 Setting prompt string to ['/ #']
10984 08:07:39.217531 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10986 08:07:39.218576 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10987 08:07:39.219040 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
10988 08:07:39.219419 Setting prompt string to ['/ #']
10989 08:07:39.219748 Forcing a shell prompt, looking for ['/ #']
10991 08:07:39.270640 / #
10992 08:07:39.271288 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10993 08:07:39.271740 Waiting using forced prompt support (timeout 00:02:30)
10994 08:07:39.276763
10995 08:07:39.277723 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10996 08:07:39.278558 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
10997 08:07:39.279095 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10998 08:07:39.279572 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
10999 08:07:39.280039 end: 2 depthcharge-action (duration 00:01:33) [common]
11000 08:07:39.280501 start: 3 lava-test-retry (timeout 00:08:04) [common]
11001 08:07:39.280999 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
11002 08:07:39.281424 Using namespace: common
11004 08:07:39.382748 / # #
11005 08:07:39.383392 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11006 08:07:39.429503 #<6>[ 19.562268] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11007 08:07:39.430069
11008 08:07:39.430437 <6>[ 19.570741] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11009 08:07:39.431093 Using /lava-11585993
11011 08:07:39.532422 / # export SHELL=/bin/sh
11012 08:07:39.538950 export SHELL=/bin/sh
11014 08:07:39.640703 / # . /lava-11585993/environment
11015 08:07:39.647364 . /lava-11585993/environment
11017 08:07:39.749085 / # /lava-11585993/bin/lava-test-runner /lava-11585993/0
11018 08:07:39.749716 Test shell timeout: 10s (minimum of the action and connection timeout)
11019 08:07:39.755440 /lava-11585993/bin/lava-test-runner /lava-11585993/0
11020 08:07:39.777298 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11021 08:07:39.784067 + cd /lava-11585993/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11022 08:07:39.784632 + cat uuid
11023 08:07:39.787153 + UUID=11585993_1.5.2.3.1
11024 08:07:39.787614 + set +x
11025 08:07:39.794540 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 11585993_1.5.2.3.1>
11026 08:07:39.795396 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 11585993_1.5.2.3.1
11027 08:07:39.795813 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (11585993_1.5.2.3.1)
11028 08:07:39.796317 Skipping test definition patterns.
11029 08:07:39.797234 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11030 08:07:39.800912 Received signal: <TESTCASE> TEST_CASE_ID=device-presence<4
11031 08:07:39.801600 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'device-presence<4', 'result': 'unknown'}
11032 08:07:39.810575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence<4>[ 19.980964] use of bytesused == 0 is deprecated and will be removed in the future,
11033 08:07:39.811199 RESULT=pass>
11034 08:07:39.813698 d<4>[ 19.990018] use the actual size instead.
11035 08:07:39.817365 evice: /dev/video2
11036 08:07:39.820266 <4>[ 19.997488] ------------[ cut here ]------------
11037 08:07:39.827096 <4>[ 20.002383] get_vaddr_frames() cannot follow VM_IO mapping
11038 08:07:39.840581 <4>[ 20.002535] WARNING: CPU: 6 PID: 309 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11039 08:07:39.890514 <4>[ 20.020624] Modules linked in: btusb btintel btmtk btrtl btbcm mt7921e mt7921_common mt76_connac_lib mt76 mtk_vcodec_enc mac80211 mtk_vcodec_common libarc4 mtk_vpu r8153_ecm uvcvideo v4l2_mem2mem bluetooth videobuf2_vmalloc videobuf2_dma_contig cdc_ether cfg80211 usbnet videobuf2_memops cros_ec_rpmsg ecdh_generic videobuf2_v4l2 videobuf2_common ecc videodev rfkill crct10dif_ce mc sbs_battery r8152 cros_ec_chardev elants_i2c elan_i2c hid_google_hammer cros_ec_typec hid_vivaldi_common mtk_scp mtk_rpmsg pcie_mediatek_gen3 mtk_scp_ipi ip_tables x_tables ipv6
11040 08:07:39.897021 <4>[ 20.069967] CPU: 6 PID: 309 Comm: v4l2-compliance Not tainted 6.1.54-cip6 #1
11041 08:07:39.903521 <4>[ 20.077262] Hardware name: Google Spherion (rev0 - 3) (DT)
11042 08:07:39.909841 <4>[ 20.082995] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11043 08:07:39.917143 <4>[ 20.090204] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11044 08:07:39.923731 <4>[ 20.096290] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11045 08:07:39.926619 <4>[ 20.102375] sp : ffff8000090e3850
11046 08:07:39.933595 <4>[ 20.105937] x29: ffff8000090e3850 x28: ffffb777115f3000 x27: ffffb777115ef238
11047 08:07:39.939958 <4>[ 20.113319] x26: 0000000000000000 x25: ffffb7773922dd80 x24: ffff5d940e569298
11048 08:07:39.946447 <4>[ 20.120701] x23: ffff5d940bdda800 x22: ffff5d9400d48010 x21: 0000000000000000
11049 08:07:39.956685 <4>[ 20.128084] x20: 00000000fffffff2 x19: ffff5d940de4cb80 x18: fffffffffffe9760
11050 08:07:39.962719 <4>[ 20.135466] x17: 0000000000000000 x16: ffffb7773708bb90 x15: 0000000000000038
11051 08:07:39.969265 <4>[ 20.142848] x14: ffffb77739b234a8 x13: 000000000000064e x12: 000000000000021a
11052 08:07:39.976099 <4>[ 20.150230] x11: fffffffffffe9760 x10: fffffffffffe9728 x9 : 00000000fffff21a
11053 08:07:39.985881 <4>[ 20.157612] x8 : ffffb77739b234a8 x7 : ffffb77739b7b4a8 x6 : 0000000000001938
11054 08:07:39.992613 <4>[ 20.164994] x5 : ffff5d953ef93a18 x4 : 00000000fffff21a x3 : ffffa61e05b30000
11055 08:07:39.999352 <4>[ 20.172376] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff5d940a3349c0
11056 08:07:40.002661 <4>[ 20.179759] Call trace:
11057 08:07:40.009144 <4>[ 20.182453] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11058 08:07:40.012672 <4>[ 20.188192] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11059 08:07:40.019682 <4>[ 20.194191] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11060 08:07:40.026045 <4>[ 20.200537] __prepare_userptr+0x280/0x410 [videobuf2_common]
11061 08:07:40.032463 <4>[ 20.206536] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11062 08:07:40.039442 <4>[ 20.212187] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11063 08:07:40.042359 <4>[ 20.218359] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11064 08:07:40.049572 <4>[ 20.223846] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11065 08:07:40.055870 <4>[ 20.229596] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11066 08:07:40.059196 <4>[ 20.235856] v4l_prepare_buf+0x48/0x60 [videodev]
11067 08:07:40.065923 <4>[ 20.240869] __video_do_ioctl+0x184/0x3d0 [videodev]
11068 08:07:40.069506 <4>[ 20.246097] video_usercopy+0x358/0x680 [videodev]
11069 08:07:40.075607 <4>[ 20.251149] video_ioctl2+0x18/0x30 [videodev]
11070 08:07:40.079115 <4>[ 20.255855] v4l2_ioctl+0x40/0x60 [videodev]
11071 08:07:40.085499 <4>[ 20.260387] __arm64_sys_ioctl+0xa8/0xf0
11072 08:07:40.089032 <4>[ 20.264565] invoke_syscall+0x48/0x114
11073 08:07:40.092024 <4>[ 20.268567] el0_svc_common.constprop.0+0x44/0xec
11074 08:07:40.095664 <4>[ 20.273521] do_el0_svc+0x2c/0xd0
11075 08:07:40.098700 <4>[ 20.277085] el0_svc+0x2c/0x84
11076 08:07:40.105980 <4>[ 20.280390] el0t_64_sync_handler+0xb8/0xc0
11077 08:07:40.109091 <4>[ 20.284820] el0t_64_sync+0x18c/0x190
11078 08:07:40.112004 <4>[ 20.288731] ---[ end trace 0000000000000000 ]---
11079 08:07:40.125107 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11080 08:07:40.134328 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11081 08:07:40.142094
11082 08:07:40.155326 Compliance test for mtk-vcodec-enc device /dev/video2:
11083 08:07:40.161522
11084 08:07:40.171313 Driver Info:
11085 08:07:40.185918 Driver name : mtk-vcodec-enc
11086 08:07:40.199754 Card type : MT8192 video encoder
11087 08:07:40.209903 Bus info : platform:17020000.vcodec
11088 08:07:40.217746 Driver version : 6.1.54
11089 08:07:40.233821 Capabilities : 0x84204000
11090 08:07:40.246397 Video Memory-to-Memory Multiplanar
11091 08:07:40.257985 Streaming
11092 08:07:40.271017 Extended Pix Format
11093 08:07:40.281714 Device Capabilities
11094 08:07:40.294305 Device Caps : 0x04204000
11095 08:07:40.310473 Video Memory-to-Memory Multiplanar
11096 08:07:40.321073 Streaming
11097 08:07:40.336874 Extended Pix Format
11098 08:07:40.347684 Detected Stateful Encoder
11099 08:07:40.361392
11100 08:07:40.371253 Required ioctls:
11101 08:07:40.390891 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11102 08:07:40.391464 test VIDIOC_QUERYCAP: OK
11103 08:07:40.392158 Received signal: <TESTSET> START Required-ioctls
11104 08:07:40.392565 Starting test_set Required-ioctls
11105 08:07:40.414105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11106 08:07:40.414938 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11108 08:07:40.417437 test invalid ioctls: OK
11109 08:07:40.440126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11110 08:07:40.440694
11111 08:07:40.441359 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11113 08:07:40.450833 Allow for multiple opens:
11114 08:07:40.457474 <LAVA_SIGNAL_TESTSET STOP>
11115 08:07:40.457826 Received signal: <TESTSET> STOP
11116 08:07:40.457923 Closing test_set Required-ioctls
11117 08:07:40.467058 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11118 08:07:40.467432 Received signal: <TESTSET> START Allow-for-multiple-opens
11119 08:07:40.467536 Starting test_set Allow-for-multiple-opens
11120 08:07:40.470170 test second /dev/video2 open: OK
11121 08:07:40.492116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11122 08:07:40.492595 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11124 08:07:40.495150 test VIDIOC_QUERYCAP: OK
11125 08:07:40.521611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11126 08:07:40.522446 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11128 08:07:40.524896 test VIDIOC_G/S_PRIORITY: OK
11129 08:07:40.548450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11130 08:07:40.549308 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11132 08:07:40.552002 test for unlimited opens: OK
11133 08:07:40.573167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11134 08:07:40.573728
11135 08:07:40.574364 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11137 08:07:40.588920 Debug ioctls:
11138 08:07:40.597111 <LAVA_SIGNAL_TESTSET STOP>
11139 08:07:40.597938 Received signal: <TESTSET> STOP
11140 08:07:40.598319 Closing test_set Allow-for-multiple-opens
11141 08:07:40.606604 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11142 08:07:40.607436 Received signal: <TESTSET> START Debug-ioctls
11143 08:07:40.607824 Starting test_set Debug-ioctls
11144 08:07:40.609910 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11145 08:07:40.635885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11146 08:07:40.636716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11148 08:07:40.642153 test VIDIOC_LOG_STATUS: OK (Not Supported)
11149 08:07:40.658400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11150 08:07:40.658946
11151 08:07:40.659577 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11153 08:07:40.673907 Input ioctls:
11154 08:07:40.680723 <LAVA_SIGNAL_TESTSET STOP>
11155 08:07:40.681574 Received signal: <TESTSET> STOP
11156 08:07:40.681959 Closing test_set Debug-ioctls
11157 08:07:40.689829 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11158 08:07:40.690658 Received signal: <TESTSET> START Input-ioctls
11159 08:07:40.691048 Starting test_set Input-ioctls
11160 08:07:40.693063 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11161 08:07:40.717963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11162 08:07:40.718796 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11164 08:07:40.720967 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11165 08:07:40.738828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11166 08:07:40.739718 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11168 08:07:40.745508 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11169 08:07:40.763814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11170 08:07:40.764717 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11172 08:07:40.770294 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11173 08:07:40.788433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11174 08:07:40.789269 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11176 08:07:40.792277 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11177 08:07:40.814059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11178 08:07:40.814903 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11180 08:07:40.817387 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11181 08:07:40.840239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11182 08:07:40.841062 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11184 08:07:40.843447 Inputs: 0 Audio Inputs: 0 Tuners: 0
11185 08:07:40.851204
11186 08:07:40.872399 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11187 08:07:40.898339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11188 08:07:40.899172 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11190 08:07:40.904686 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11191 08:07:40.918696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11192 08:07:40.919540 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11194 08:07:40.925207 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11195 08:07:40.940005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11196 08:07:40.940923 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11198 08:07:40.946540 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11199 08:07:40.961178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11200 08:07:40.962006 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11202 08:07:40.967859 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11203 08:07:40.981541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11204 08:07:40.982108
11205 08:07:40.982741 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11207 08:07:41.000699 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11208 08:07:41.022627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11209 08:07:41.023495 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11211 08:07:41.029038 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11212 08:07:41.051831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11213 08:07:41.052666 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11215 08:07:41.054985 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11216 08:07:41.073553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11217 08:07:41.074534 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11219 08:07:41.076815 test VIDIOC_G/S_EDID: OK (Not Supported)
11220 08:07:41.114643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11221 08:07:41.115206
11222 08:07:41.115838 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11224 08:07:41.123281 Control ioctls:
11225 08:07:41.129176 <LAVA_SIGNAL_TESTSET STOP>
11226 08:07:41.130000 Received signal: <TESTSET> STOP
11227 08:07:41.130379 Closing test_set Input-ioctls
11228 08:07:41.142247 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11229 08:07:41.143091 Received signal: <TESTSET> START Control-ioctls
11230 08:07:41.143473 Starting test_set Control-ioctls
11231 08:07:41.145440 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11232 08:07:41.172331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11233 08:07:41.172900 test VIDIOC_QUERYCTRL: OK
11234 08:07:41.173584 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11236 08:07:41.200569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11237 08:07:41.201427 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11239 08:07:41.203964 test VIDIOC_G/S_CTRL: OK
11240 08:07:41.223349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11241 08:07:41.224298 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11243 08:07:41.227104 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11244 08:07:41.249205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11245 08:07:41.250048 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11247 08:07:41.259076 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11248 08:07:41.262340 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11249 08:07:41.287053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11250 08:07:41.287885 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11252 08:07:41.289527 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11253 08:07:41.313954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11254 08:07:41.314852 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11256 08:07:41.317267 Standard Controls: 16 Private Controls: 0
11257 08:07:41.324680
11258 08:07:41.335406 Format ioctls:
11259 08:07:41.341852 <LAVA_SIGNAL_TESTSET STOP>
11260 08:07:41.342676 Received signal: <TESTSET> STOP
11261 08:07:41.343053 Closing test_set Control-ioctls
11262 08:07:41.351555 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11263 08:07:41.352383 Received signal: <TESTSET> START Format-ioctls
11264 08:07:41.352768 Starting test_set Format-ioctls
11265 08:07:41.354782 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11266 08:07:41.380381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11267 08:07:41.381270 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11269 08:07:41.382956 test VIDIOC_G/S_PARM: OK
11270 08:07:41.402037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11271 08:07:41.402862 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11273 08:07:41.405513 test VIDIOC_G_FBUF: OK (Not Supported)
11274 08:07:41.427747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11275 08:07:41.428580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11277 08:07:41.430586 test VIDIOC_G_FMT: OK
11278 08:07:41.451856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11279 08:07:41.452691 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11281 08:07:41.454993 test VIDIOC_TRY_FMT: OK
11282 08:07:41.478689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11283 08:07:41.479489 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11285 08:07:41.488641 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11286 08:07:41.489241 test VIDIOC_S_FMT: FAIL
11287 08:07:41.515549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11288 08:07:41.516417 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11290 08:07:41.518473 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11291 08:07:41.540313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11292 08:07:41.541140 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11294 08:07:41.543508 test Cropping: OK
11295 08:07:41.563559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11296 08:07:41.564392 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11298 08:07:41.566954 test Composing: OK (Not Supported)
11299 08:07:41.588265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11300 08:07:41.589099 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11302 08:07:41.591580 test Scaling: OK (Not Supported)
11303 08:07:41.616783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11304 08:07:41.617377
11305 08:07:41.618055 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11307 08:07:41.627573 Codec ioctls:
11308 08:07:41.637850 <LAVA_SIGNAL_TESTSET STOP>
11309 08:07:41.638675 Received signal: <TESTSET> STOP
11310 08:07:41.639055 Closing test_set Format-ioctls
11311 08:07:41.647662 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11312 08:07:41.648490 Received signal: <TESTSET> START Codec-ioctls
11313 08:07:41.648877 Starting test_set Codec-ioctls
11314 08:07:41.651076 test VIDIOC_(TRY_)ENCODER_CMD: OK
11315 08:07:41.672481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11316 08:07:41.673801 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11318 08:07:41.679144 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11319 08:07:41.703806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11320 08:07:41.704609 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11322 08:07:41.710301 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11323 08:07:41.728485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11324 08:07:41.729078
11325 08:07:41.729711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11327 08:07:41.738065 Buffer ioctls:
11328 08:07:41.745078 <LAVA_SIGNAL_TESTSET STOP>
11329 08:07:41.745902 Received signal: <TESTSET> STOP
11330 08:07:41.746284 Closing test_set Codec-ioctls
11331 08:07:41.754742 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11332 08:07:41.755564 Received signal: <TESTSET> START Buffer-ioctls
11333 08:07:41.755950 Starting test_set Buffer-ioctls
11334 08:07:41.758215 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11335 08:07:41.783214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11336 08:07:41.783781 test VIDIOC_EXPBUF: OK
11337 08:07:41.784422 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11339 08:07:41.806497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11340 08:07:41.807319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11342 08:07:41.809804 test Requests: OK (Not Supported)
11343 08:07:41.833760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11344 08:07:41.834323
11345 08:07:41.834949 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11347 08:07:41.843678 Test input 0:
11348 08:07:41.853375
11349 08:07:41.865837 Streaming ioctls:
11350 08:07:41.872500 <LAVA_SIGNAL_TESTSET STOP>
11351 08:07:41.873345 Received signal: <TESTSET> STOP
11352 08:07:41.873731 Closing test_set Buffer-ioctls
11353 08:07:41.885435 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11354 08:07:41.886387 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11355 08:07:41.886781 Starting test_set Streaming-ioctls_Test-input-0
11356 08:07:41.888175 test read/write: OK (Not Supported)
11357 08:07:41.910527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11358 08:07:41.911360 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11360 08:07:41.917004 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11361 08:07:41.929031 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11362 08:07:41.933824 test blocking wait: FAIL
11363 08:07:41.964431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11364 08:07:41.965290 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11366 08:07:41.974139 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11367 08:07:41.977361 test MMAP (select): FAIL
11368 08:07:41.998363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11369 08:07:41.999242 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11371 08:07:42.004983 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11372 08:07:42.009040 test MMAP (epoll): FAIL
11373 08:07:42.033996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11374 08:07:42.034834 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11376 08:07:42.043662 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11377 08:07:42.050327 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11378 08:07:42.054524 test USERPTR (select): FAIL
11379 08:07:42.080464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11380 08:07:42.081339 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11382 08:07:42.087015 test DMABUF: Cannot test, specify --expbuf-device
11383 08:07:42.090981
11384 08:07:42.109040 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11385 08:07:42.112519 <LAVA_TEST_RUNNER EXIT>
11386 08:07:42.113407 ok: lava_test_shell seems to have completed
11387 08:07:42.113812 Marking unfinished test run as failed
11389 08:07:42.119042 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11390 08:07:42.119696 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11391 08:07:42.120189 end: 3 lava-test-retry (duration 00:00:03) [common]
11392 08:07:42.120664 start: 4 finalize (timeout 00:08:01) [common]
11393 08:07:42.121193 start: 4.1 power-off (timeout 00:00:30) [common]
11394 08:07:42.122010 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11395 08:07:42.213693 >> Command sent successfully.
11396 08:07:42.225282 Returned 0 in 0 seconds
11397 08:07:42.326652 end: 4.1 power-off (duration 00:00:00) [common]
11399 08:07:42.328199 start: 4.2 read-feedback (timeout 00:08:01) [common]
11400 08:07:42.329659 Listened to connection for namespace 'common' for up to 1s
11401 08:07:43.330319 Finalising connection for namespace 'common'
11402 08:07:43.331001 Disconnecting from shell: Finalise
11403 08:07:43.331419 / #
11404 08:07:43.432543 end: 4.2 read-feedback (duration 00:00:01) [common]
11405 08:07:43.433283 end: 4 finalize (duration 00:00:01) [common]
11406 08:07:43.433883 Cleaning after the job
11407 08:07:43.434401 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/ramdisk
11408 08:07:43.441378 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/kernel
11409 08:07:43.447549 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/dtb
11410 08:07:43.447692 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11585993/tftp-deploy-gliuz5fj/modules
11411 08:07:43.453066 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11585993
11412 08:07:43.506032 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11585993
11413 08:07:43.506217 Job finished correctly